Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
1f25f5d3 CD |
211 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
212 | if they have not been initialized. Changed by `.set <asename>', by | |
213 | command line options, and based on the default architecture. */ | |
214 | int ase_mips3d; | |
deec1734 | 215 | int ase_mdmx; |
e16bfa71 | 216 | int ase_smartmips; |
74cd071d | 217 | int ase_dsp; |
8b082fb1 | 218 | int ase_dspr2; |
ef2e4d86 | 219 | int ase_mt; |
dec0624d | 220 | int ase_mcu; |
252b5132 RH |
221 | /* Whether we are assembling for the mips16 processor. 0 if we are |
222 | not, 1 if we are, and -1 if the value has not been initialized. | |
223 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
224 | -nomips16 command line options, and the default CPU. */ | |
225 | int mips16; | |
df58fc94 RS |
226 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
227 | 1 if we are, and -1 if the value has not been initialized. Changed | |
228 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
229 | and -mno-micromips command line options, and the default CPU. */ | |
230 | int micromips; | |
252b5132 RH |
231 | /* Non-zero if we should not reorder instructions. Changed by `.set |
232 | reorder' and `.set noreorder'. */ | |
233 | int noreorder; | |
741fe287 MR |
234 | /* Non-zero if we should not permit the register designated "assembler |
235 | temporary" to be used in instructions. The value is the register | |
236 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
237 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
238 | unsigned int at; | |
252b5132 RH |
239 | /* Non-zero if we should warn when a macro instruction expands into |
240 | more than one machine instruction. Changed by `.set nomacro' and | |
241 | `.set macro'. */ | |
242 | int warn_about_macros; | |
243 | /* Non-zero if we should not move instructions. Changed by `.set | |
244 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
245 | int nomove; | |
246 | /* Non-zero if we should not optimize branches by moving the target | |
247 | of the branch into the delay slot. Actually, we don't perform | |
248 | this optimization anyhow. Changed by `.set bopt' and `.set | |
249 | nobopt'. */ | |
250 | int nobopt; | |
251 | /* Non-zero if we should not autoextend mips16 instructions. | |
252 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
253 | int noautoextend; | |
a325df1d TS |
254 | /* Restrict general purpose registers and floating point registers |
255 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
256 | is passed but can changed if the assembler code uses .set mipsN. */ | |
257 | int gp32; | |
258 | int fp32; | |
fef14a42 TS |
259 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
260 | command line option, and the default CPU. */ | |
261 | int arch; | |
aed1a261 RS |
262 | /* True if ".set sym32" is in effect. */ |
263 | bfd_boolean sym32; | |
037b32b9 AN |
264 | /* True if floating-point operations are not allowed. Changed by .set |
265 | softfloat or .set hardfloat, by command line options -msoft-float or | |
266 | -mhard-float. The default is false. */ | |
267 | bfd_boolean soft_float; | |
268 | ||
269 | /* True if only single-precision floating-point operations are allowed. | |
270 | Changed by .set singlefloat or .set doublefloat, command-line options | |
271 | -msingle-float or -mdouble-float. The default is false. */ | |
272 | bfd_boolean single_float; | |
252b5132 RH |
273 | }; |
274 | ||
037b32b9 AN |
275 | /* This is the struct we use to hold the current set of options. Note |
276 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
277 | -1 to indicate that they have not been initialized. */ | |
278 | ||
a325df1d | 279 | /* True if -mgp32 was passed. */ |
a8e8e863 | 280 | static int file_mips_gp32 = -1; |
a325df1d TS |
281 | |
282 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 283 | static int file_mips_fp32 = -1; |
a325df1d | 284 | |
037b32b9 AN |
285 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
286 | static int file_mips_soft_float = 0; | |
287 | ||
288 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
289 | static int file_mips_single_float = 0; | |
252b5132 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
037b32b9 AN |
293 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
294 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
295 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
296 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
297 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
298 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 299 | }; |
252b5132 RH |
300 | |
301 | /* These variables are filled in with the masks of registers used. | |
302 | The object format code reads them and puts them in the appropriate | |
303 | place. */ | |
304 | unsigned long mips_gprmask; | |
305 | unsigned long mips_cprmask[4]; | |
306 | ||
307 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 308 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 309 | |
738f4d98 | 310 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
311 | static int file_ase_mips16; |
312 | ||
3994f87e TS |
313 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
314 | || mips_opts.isa == ISA_MIPS32R2 \ | |
315 | || mips_opts.isa == ISA_MIPS64 \ | |
316 | || mips_opts.isa == ISA_MIPS64R2) | |
317 | ||
df58fc94 RS |
318 | /* True if any microMIPS code was produced. */ |
319 | static int file_ase_micromips; | |
320 | ||
b12dd2e4 CF |
321 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
322 | #ifdef TE_IRIX | |
1180b5a4 | 323 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 324 | #else |
1180b5a4 RS |
325 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
326 | because there's no place for any addend, the only acceptable | |
327 | expression is a bare symbol. */ | |
328 | #define MIPS_JALR_HINT_P(EXPR) \ | |
329 | (!HAVE_IN_PLACE_ADDENDS \ | |
330 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
331 | #endif |
332 | ||
1f25f5d3 CD |
333 | /* True if -mips3d was passed or implied by arguments passed on the |
334 | command line (e.g., by -march). */ | |
335 | static int file_ase_mips3d; | |
336 | ||
deec1734 CD |
337 | /* True if -mdmx was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mdmx; | |
340 | ||
e16bfa71 TS |
341 | /* True if -msmartmips was passed or implied by arguments passed on the |
342 | command line (e.g., by -march). */ | |
343 | static int file_ase_smartmips; | |
344 | ||
ad3fea08 TS |
345 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
346 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 347 | |
74cd071d CF |
348 | /* True if -mdsp was passed or implied by arguments passed on the |
349 | command line (e.g., by -march). */ | |
350 | static int file_ase_dsp; | |
351 | ||
ad3fea08 | 352 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
353 | || mips_opts.isa == ISA_MIPS64R2 \ |
354 | || mips_opts.micromips) | |
ad3fea08 | 355 | |
65263ce3 TS |
356 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
357 | ||
8b082fb1 TS |
358 | /* True if -mdspr2 was passed or implied by arguments passed on the |
359 | command line (e.g., by -march). */ | |
360 | static int file_ase_dspr2; | |
361 | ||
362 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
363 | || mips_opts.isa == ISA_MIPS64R2 \ |
364 | || mips_opts.micromips) | |
8b082fb1 | 365 | |
ef2e4d86 CF |
366 | /* True if -mmt was passed or implied by arguments passed on the |
367 | command line (e.g., by -march). */ | |
368 | static int file_ase_mt; | |
369 | ||
ad3fea08 TS |
370 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
371 | || mips_opts.isa == ISA_MIPS64R2) | |
372 | ||
dec0624d | 373 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
374 | || mips_opts.isa == ISA_MIPS64R2 \ |
375 | || mips_opts.micromips) | |
dec0624d | 376 | |
ec68c924 | 377 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 378 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 379 | static const char *mips_arch_string; |
ec68c924 EC |
380 | |
381 | /* The argument of the -mtune= flag. The architecture for which we | |
382 | are optimizing. */ | |
383 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 384 | static const char *mips_tune_string; |
ec68c924 | 385 | |
316f5878 | 386 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
387 | static int mips_32bitmode = 0; |
388 | ||
316f5878 RS |
389 | /* True if the given ABI requires 32-bit registers. */ |
390 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
391 | ||
392 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
393 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
394 | ((ABI) == N32_ABI \ | |
395 | || (ABI) == N64_ABI \ | |
316f5878 RS |
396 | || (ABI) == O64_ABI) |
397 | ||
ad3fea08 | 398 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
399 | #define ISA_HAS_64BIT_REGS(ISA) \ |
400 | ((ISA) == ISA_MIPS3 \ | |
401 | || (ISA) == ISA_MIPS4 \ | |
402 | || (ISA) == ISA_MIPS5 \ | |
403 | || (ISA) == ISA_MIPS64 \ | |
404 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 405 | |
ad3fea08 TS |
406 | /* Return true if ISA supports 64 bit wide float registers. */ |
407 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
408 | ((ISA) == ISA_MIPS3 \ | |
409 | || (ISA) == ISA_MIPS4 \ | |
410 | || (ISA) == ISA_MIPS5 \ | |
411 | || (ISA) == ISA_MIPS32R2 \ | |
412 | || (ISA) == ISA_MIPS64 \ | |
413 | || (ISA) == ISA_MIPS64R2) | |
414 | ||
af7ee8bf CD |
415 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
416 | instructions. */ | |
707bfff6 | 417 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
418 | ((ISA) == ISA_MIPS64R2 \ |
419 | || (mips_opts.micromips \ | |
420 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
421 | ) | |
af7ee8bf CD |
422 | |
423 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
424 | instructions. */ | |
707bfff6 TS |
425 | #define ISA_HAS_ROR(ISA) \ |
426 | ((ISA) == ISA_MIPS32R2 \ | |
427 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
428 | || mips_opts.ase_smartmips \ |
429 | || mips_opts.micromips \ | |
430 | ) | |
707bfff6 | 431 | |
7455baf8 TS |
432 | /* Return true if ISA supports single-precision floats in odd registers. */ |
433 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
434 | ((ISA) == ISA_MIPS32 \ | |
435 | || (ISA) == ISA_MIPS32R2 \ | |
436 | || (ISA) == ISA_MIPS64 \ | |
437 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 438 | |
ad3fea08 TS |
439 | /* Return true if ISA supports move to/from high part of a 64-bit |
440 | floating-point register. */ | |
441 | #define ISA_HAS_MXHC1(ISA) \ | |
442 | ((ISA) == ISA_MIPS32R2 \ | |
443 | || (ISA) == ISA_MIPS64R2) | |
444 | ||
e013f690 | 445 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 446 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 447 | |
e013f690 | 448 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 449 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 450 | |
ad3fea08 TS |
451 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
452 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 453 | |
316f5878 | 454 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 455 | |
316f5878 | 456 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 457 | |
3b91255e RS |
458 | /* True if relocations are stored in-place. */ |
459 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
460 | ||
aed1a261 RS |
461 | /* The ABI-derived address size. */ |
462 | #define HAVE_64BIT_ADDRESSES \ | |
463 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
464 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 465 | |
aed1a261 RS |
466 | /* The size of symbolic constants (i.e., expressions of the form |
467 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
468 | #define HAVE_32BIT_SYMBOLS \ | |
469 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
470 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 471 | |
b7c7d6c1 TS |
472 | /* Addresses are loaded in different ways, depending on the address size |
473 | in use. The n32 ABI Documentation also mandates the use of additions | |
474 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 475 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 476 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
477 | |
478 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 479 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
480 | |
481 | #define ADDRESS_LOAD_INSN \ | |
482 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
483 | ||
484 | #define ADDRESS_STORE_INSN \ | |
485 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
486 | ||
a4672219 | 487 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
488 | #define CPU_HAS_MIPS16(cpu) \ |
489 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
490 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 491 | |
2309ddf2 | 492 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
493 | #define CPU_HAS_MICROMIPS(cpu) 0 |
494 | ||
60b63b72 RS |
495 | /* True if CPU has a dror instruction. */ |
496 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
497 | ||
498 | /* True if CPU has a ror instruction. */ | |
499 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
500 | ||
dd6a37e7 | 501 | /* True if CPU is in the Octeon family */ |
432233b3 | 502 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 503 | |
dd3cbb7e | 504 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 505 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 506 | |
c8978940 CD |
507 | /* True if mflo and mfhi can be immediately followed by instructions |
508 | which write to the HI and LO registers. | |
509 | ||
510 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
511 | (at least) two instructions between the reads of HI/LO and | |
512 | instructions which write them, and later ISAs do not. Contradicting | |
513 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
514 | the UM for the NEC Vr5000) document needing the instructions between | |
515 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
516 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
517 | earlier-ISA CPUs for which CPU documentation declares that the | |
518 | instructions are really interlocked. */ | |
519 | #define hilo_interlocks \ | |
520 | (mips_opts.isa == ISA_MIPS32 \ | |
521 | || mips_opts.isa == ISA_MIPS32R2 \ | |
522 | || mips_opts.isa == ISA_MIPS64 \ | |
523 | || mips_opts.isa == ISA_MIPS64R2 \ | |
524 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 525 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
526 | || mips_opts.arch == CPU_R10000 \ |
527 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
528 | || mips_opts.arch == CPU_R14000 \ |
529 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 530 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 531 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 532 | || mips_opts.micromips \ |
c8978940 | 533 | ) |
252b5132 RH |
534 | |
535 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
536 | from the GPRs after they are loaded from memory, and thus does not |
537 | require nops to be inserted. This applies to instructions marked | |
538 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
539 | level I and microMIPS mode instructions are always interlocked. */ |
540 | #define gpr_interlocks \ | |
541 | (mips_opts.isa != ISA_MIPS1 \ | |
542 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 543 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
544 | || mips_opts.micromips \ |
545 | ) | |
252b5132 | 546 | |
81912461 ILT |
547 | /* Whether the processor uses hardware interlocks to avoid delays |
548 | required by coprocessor instructions, and thus does not require | |
549 | nops to be inserted. This applies to instructions marked | |
550 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
551 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
552 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
553 | levels I, II, and III and microMIPS mode instructions are always |
554 | interlocked. */ | |
bdaaa2e1 | 555 | /* Itbl support may require additional care here. */ |
81912461 ILT |
556 | #define cop_interlocks \ |
557 | ((mips_opts.isa != ISA_MIPS1 \ | |
558 | && mips_opts.isa != ISA_MIPS2 \ | |
559 | && mips_opts.isa != ISA_MIPS3) \ | |
560 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 561 | || mips_opts.micromips \ |
81912461 ILT |
562 | ) |
563 | ||
564 | /* Whether the processor uses hardware interlocks to protect reads | |
565 | from coprocessor registers after they are loaded from memory, and | |
566 | thus does not require nops to be inserted. This applies to | |
567 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
568 | requires at MIPS ISA level I and microMIPS mode instructions are |
569 | always interlocked. */ | |
570 | #define cop_mem_interlocks \ | |
571 | (mips_opts.isa != ISA_MIPS1 \ | |
572 | || mips_opts.micromips \ | |
573 | ) | |
252b5132 | 574 | |
6b76fefe CM |
575 | /* Is this a mfhi or mflo instruction? */ |
576 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
577 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
578 | ||
df58fc94 RS |
579 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
580 | has been selected. This implies, in particular, that addresses of text | |
581 | labels have their LSB set. */ | |
582 | #define HAVE_CODE_COMPRESSION \ | |
583 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
584 | ||
252b5132 RH |
585 | /* MIPS PIC level. */ |
586 | ||
a161fe53 | 587 | enum mips_pic_level mips_pic; |
252b5132 | 588 | |
c9914766 | 589 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 590 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 591 | static int mips_big_got = 0; |
252b5132 RH |
592 | |
593 | /* 1 if trap instructions should used for overflow rather than break | |
594 | instructions. */ | |
c9914766 | 595 | static int mips_trap = 0; |
252b5132 | 596 | |
119d663a | 597 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 598 | by assembling two single width halves into two single width floating |
119d663a NC |
599 | point registers which just happen to alias the double width destination |
600 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 601 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
602 | automatically at assemble time. */ |
603 | static int mips_disable_float_construction; | |
604 | ||
252b5132 RH |
605 | /* Non-zero if any .set noreorder directives were used. */ |
606 | ||
607 | static int mips_any_noreorder; | |
608 | ||
6b76fefe CM |
609 | /* Non-zero if nops should be inserted when the register referenced in |
610 | an mfhi/mflo instruction is read in the next two instructions. */ | |
611 | static int mips_7000_hilo_fix; | |
612 | ||
02ffd3e4 | 613 | /* The size of objects in the small data section. */ |
156c2f8b | 614 | static unsigned int g_switch_value = 8; |
252b5132 RH |
615 | /* Whether the -G option was used. */ |
616 | static int g_switch_seen = 0; | |
617 | ||
618 | #define N_RMASK 0xc4 | |
619 | #define N_VFP 0xd4 | |
620 | ||
621 | /* If we can determine in advance that GP optimization won't be | |
622 | possible, we can skip the relaxation stuff that tries to produce | |
623 | GP-relative references. This makes delay slot optimization work | |
624 | better. | |
625 | ||
626 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
627 | gcc output. It needs to guess right for gcc, otherwise gcc |
628 | will put what it thinks is a GP-relative instruction in a branch | |
629 | delay slot. | |
252b5132 RH |
630 | |
631 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
632 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 633 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
634 | |
635 | /* handle of the OPCODE hash table */ | |
636 | static struct hash_control *op_hash = NULL; | |
637 | ||
638 | /* The opcode hash table we use for the mips16. */ | |
639 | static struct hash_control *mips16_op_hash = NULL; | |
640 | ||
df58fc94 RS |
641 | /* The opcode hash table we use for the microMIPS ASE. */ |
642 | static struct hash_control *micromips_op_hash = NULL; | |
643 | ||
252b5132 RH |
644 | /* This array holds the chars that always start a comment. If the |
645 | pre-processor is disabled, these aren't very useful */ | |
646 | const char comment_chars[] = "#"; | |
647 | ||
648 | /* This array holds the chars that only start a comment at the beginning of | |
649 | a line. If the line seems to have the form '# 123 filename' | |
650 | .line and .file directives will appear in the pre-processed output */ | |
651 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
652 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 653 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
654 | /* Also note that C style comments are always supported. */ |
655 | const char line_comment_chars[] = "#"; | |
656 | ||
bdaaa2e1 | 657 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 658 | const char line_separator_chars[] = ";"; |
252b5132 RH |
659 | |
660 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
661 | const char EXP_CHARS[] = "eE"; | |
662 | ||
663 | /* Chars that mean this number is a floating point constant */ | |
664 | /* As in 0f12.456 */ | |
665 | /* or 0d1.2345e12 */ | |
666 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
667 | ||
668 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
669 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
670 | but nothing is ideal around here. | |
671 | */ | |
672 | ||
673 | static char *insn_error; | |
674 | ||
675 | static int auto_align = 1; | |
676 | ||
677 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
678 | offset in the stack frame from which to restore the $gp register. | |
679 | This is set by the .cprestore pseudo-op, and saved in this | |
680 | variable. */ | |
681 | static offsetT mips_cprestore_offset = -1; | |
682 | ||
67c1ffbe | 683 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 684 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 685 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
686 | static offsetT mips_cpreturn_offset = -1; |
687 | static int mips_cpreturn_register = -1; | |
688 | static int mips_gp_register = GP; | |
def2e0dd | 689 | static int mips_gprel_offset = 0; |
6478892d | 690 | |
7a621144 DJ |
691 | /* Whether mips_cprestore_offset has been set in the current function |
692 | (or whether it has already been warned about, if not). */ | |
693 | static int mips_cprestore_valid = 0; | |
694 | ||
252b5132 RH |
695 | /* This is the register which holds the stack frame, as set by the |
696 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
697 | static int mips_frame_reg = SP; | |
698 | ||
7a621144 DJ |
699 | /* Whether mips_frame_reg has been set in the current function |
700 | (or whether it has already been warned about, if not). */ | |
701 | static int mips_frame_reg_valid = 0; | |
702 | ||
252b5132 RH |
703 | /* To output NOP instructions correctly, we need to keep information |
704 | about the previous two instructions. */ | |
705 | ||
706 | /* Whether we are optimizing. The default value of 2 means to remove | |
707 | unneeded NOPs and swap branch instructions when possible. A value | |
708 | of 1 means to not swap branches. A value of 0 means to always | |
709 | insert NOPs. */ | |
710 | static int mips_optimize = 2; | |
711 | ||
712 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
713 | equivalent to seeing no -g option at all. */ | |
714 | static int mips_debug = 0; | |
715 | ||
7d8e00cf RS |
716 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
717 | #define MAX_VR4130_NOPS 4 | |
718 | ||
719 | /* The maximum number of NOPs needed to fill delay slots. */ | |
720 | #define MAX_DELAY_NOPS 2 | |
721 | ||
722 | /* The maximum number of NOPs needed for any purpose. */ | |
723 | #define MAX_NOPS 4 | |
71400594 RS |
724 | |
725 | /* A list of previous instructions, with index 0 being the most recent. | |
726 | We need to look back MAX_NOPS instructions when filling delay slots | |
727 | or working around processor errata. We need to look back one | |
728 | instruction further if we're thinking about using history[0] to | |
729 | fill a branch delay slot. */ | |
730 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 731 | |
1e915849 | 732 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
733 | static struct mips_cl_insn nop_insn; |
734 | static struct mips_cl_insn mips16_nop_insn; | |
735 | static struct mips_cl_insn micromips_nop16_insn; | |
736 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
737 | |
738 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
739 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
740 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
741 | ||
742 | /* The size of NOP_INSN in bytes. */ | |
743 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 744 | |
252b5132 RH |
745 | /* If this is set, it points to a frag holding nop instructions which |
746 | were inserted before the start of a noreorder section. If those | |
747 | nops turn out to be unnecessary, the size of the frag can be | |
748 | decreased. */ | |
749 | static fragS *prev_nop_frag; | |
750 | ||
751 | /* The number of nop instructions we created in prev_nop_frag. */ | |
752 | static int prev_nop_frag_holds; | |
753 | ||
754 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 755 | prev_nop_frag. */ |
252b5132 RH |
756 | static int prev_nop_frag_required; |
757 | ||
758 | /* The number of instructions we've seen since prev_nop_frag. */ | |
759 | static int prev_nop_frag_since; | |
760 | ||
761 | /* For ECOFF and ELF, relocations against symbols are done in two | |
762 | parts, with a HI relocation and a LO relocation. Each relocation | |
763 | has only 16 bits of space to store an addend. This means that in | |
764 | order for the linker to handle carries correctly, it must be able | |
765 | to locate both the HI and the LO relocation. This means that the | |
766 | relocations must appear in order in the relocation table. | |
767 | ||
768 | In order to implement this, we keep track of each unmatched HI | |
769 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 770 | corresponding LO relocation. */ |
252b5132 | 771 | |
e972090a NC |
772 | struct mips_hi_fixup |
773 | { | |
252b5132 RH |
774 | /* Next HI fixup. */ |
775 | struct mips_hi_fixup *next; | |
776 | /* This fixup. */ | |
777 | fixS *fixp; | |
778 | /* The section this fixup is in. */ | |
779 | segT seg; | |
780 | }; | |
781 | ||
782 | /* The list of unmatched HI relocs. */ | |
783 | ||
784 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
785 | ||
64bdfcaf RS |
786 | /* The frag containing the last explicit relocation operator. |
787 | Null if explicit relocations have not been used. */ | |
788 | ||
789 | static fragS *prev_reloc_op_frag; | |
790 | ||
252b5132 RH |
791 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
792 | ||
793 | #define X ILLEGAL_REG | |
e972090a NC |
794 | static const int mips32_to_16_reg_map[] = |
795 | { | |
252b5132 RH |
796 | X, X, 2, 3, 4, 5, 6, 7, |
797 | X, X, X, X, X, X, X, X, | |
798 | 0, 1, X, X, X, X, X, X, | |
799 | X, X, X, X, X, X, X, X | |
800 | }; | |
801 | #undef X | |
802 | ||
803 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
804 | ||
e972090a NC |
805 | static const unsigned int mips16_to_32_reg_map[] = |
806 | { | |
252b5132 RH |
807 | 16, 17, 2, 3, 4, 5, 6, 7 |
808 | }; | |
60b63b72 | 809 | |
df58fc94 RS |
810 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
811 | ||
812 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
813 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
814 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
815 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
816 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
817 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
818 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
819 | ||
820 | #define X ILLEGAL_REG | |
821 | /* reg type h: 4, 5, 6. */ | |
822 | static const int mips32_to_micromips_reg_h_map[] = | |
823 | { | |
824 | X, X, X, X, 4, 5, 6, X, | |
825 | X, X, X, X, X, X, X, X, | |
826 | X, X, X, X, X, X, X, X, | |
827 | X, X, X, X, X, X, X, X | |
828 | }; | |
829 | ||
830 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
831 | static const int mips32_to_micromips_reg_m_map[] = | |
832 | { | |
833 | 0, X, 2, 3, X, X, X, X, | |
834 | X, X, X, X, X, X, X, X, | |
835 | 4, 1, 5, 6, 7, X, X, X, | |
836 | X, X, X, X, X, X, X, X | |
837 | }; | |
838 | ||
839 | /* reg type q: 0, 2-7. 17. */ | |
840 | static const int mips32_to_micromips_reg_q_map[] = | |
841 | { | |
842 | 0, X, 2, 3, 4, 5, 6, 7, | |
843 | X, X, X, X, X, X, X, X, | |
844 | X, 1, X, X, X, X, X, X, | |
845 | X, X, X, X, X, X, X, X | |
846 | }; | |
847 | ||
848 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
849 | #undef X | |
850 | ||
851 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
852 | ||
853 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
854 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
855 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
856 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
857 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
858 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
859 | ||
860 | /* The microMIPS registers with type h. */ | |
861 | static const unsigned int micromips_to_32_reg_h_map[] = | |
862 | { | |
863 | 5, 5, 6, 4, 4, 4, 4, 4 | |
864 | }; | |
865 | ||
866 | /* The microMIPS registers with type i. */ | |
867 | static const unsigned int micromips_to_32_reg_i_map[] = | |
868 | { | |
869 | 6, 7, 7, 21, 22, 5, 6, 7 | |
870 | }; | |
871 | ||
872 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
873 | ||
874 | /* The microMIPS registers with type m. */ | |
875 | static const unsigned int micromips_to_32_reg_m_map[] = | |
876 | { | |
877 | 0, 17, 2, 3, 16, 18, 19, 20 | |
878 | }; | |
879 | ||
880 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
881 | ||
882 | /* The microMIPS registers with type q. */ | |
883 | static const unsigned int micromips_to_32_reg_q_map[] = | |
884 | { | |
885 | 0, 17, 2, 3, 4, 5, 6, 7 | |
886 | }; | |
887 | ||
888 | /* microMIPS imm type B. */ | |
889 | static const int micromips_imm_b_map[] = | |
890 | { | |
891 | 1, 4, 8, 12, 16, 20, 24, -1 | |
892 | }; | |
893 | ||
894 | /* microMIPS imm type C. */ | |
895 | static const int micromips_imm_c_map[] = | |
896 | { | |
897 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
898 | }; | |
899 | ||
71400594 RS |
900 | /* Classifies the kind of instructions we're interested in when |
901 | implementing -mfix-vr4120. */ | |
c67a084a NC |
902 | enum fix_vr4120_class |
903 | { | |
71400594 RS |
904 | FIX_VR4120_MACC, |
905 | FIX_VR4120_DMACC, | |
906 | FIX_VR4120_MULT, | |
907 | FIX_VR4120_DMULT, | |
908 | FIX_VR4120_DIV, | |
909 | FIX_VR4120_MTHILO, | |
910 | NUM_FIX_VR4120_CLASSES | |
911 | }; | |
912 | ||
c67a084a NC |
913 | /* ...likewise -mfix-loongson2f-jump. */ |
914 | static bfd_boolean mips_fix_loongson2f_jump; | |
915 | ||
916 | /* ...likewise -mfix-loongson2f-nop. */ | |
917 | static bfd_boolean mips_fix_loongson2f_nop; | |
918 | ||
919 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
920 | static bfd_boolean mips_fix_loongson2f; | |
921 | ||
71400594 RS |
922 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
923 | there must be at least one other instruction between an instruction | |
924 | of type X and an instruction of type Y. */ | |
925 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
926 | ||
927 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 928 | static int mips_fix_vr4120; |
4a6a3df4 | 929 | |
7d8e00cf RS |
930 | /* ...likewise -mfix-vr4130. */ |
931 | static int mips_fix_vr4130; | |
932 | ||
6a32d874 CM |
933 | /* ...likewise -mfix-24k. */ |
934 | static int mips_fix_24k; | |
935 | ||
d954098f DD |
936 | /* ...likewise -mfix-cn63xxp1 */ |
937 | static bfd_boolean mips_fix_cn63xxp1; | |
938 | ||
4a6a3df4 AO |
939 | /* We don't relax branches by default, since this causes us to expand |
940 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
941 | fail to compute the offset before expanding the macro to the most | |
942 | efficient expansion. */ | |
943 | ||
944 | static int mips_relax_branch; | |
252b5132 | 945 | \f |
4d7206a2 RS |
946 | /* The expansion of many macros depends on the type of symbol that |
947 | they refer to. For example, when generating position-dependent code, | |
948 | a macro that refers to a symbol may have two different expansions, | |
949 | one which uses GP-relative addresses and one which uses absolute | |
950 | addresses. When generating SVR4-style PIC, a macro may have | |
951 | different expansions for local and global symbols. | |
952 | ||
953 | We handle these situations by generating both sequences and putting | |
954 | them in variant frags. In position-dependent code, the first sequence | |
955 | will be the GP-relative one and the second sequence will be the | |
956 | absolute one. In SVR4 PIC, the first sequence will be for global | |
957 | symbols and the second will be for local symbols. | |
958 | ||
584892a6 RS |
959 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
960 | SECOND are the lengths of the two sequences in bytes. These fields | |
961 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
962 | the subtype has the following flags: | |
4d7206a2 | 963 | |
584892a6 RS |
964 | RELAX_USE_SECOND |
965 | Set if it has been decided that we should use the second | |
966 | sequence instead of the first. | |
967 | ||
968 | RELAX_SECOND_LONGER | |
969 | Set in the first variant frag if the macro's second implementation | |
970 | is longer than its first. This refers to the macro as a whole, | |
971 | not an individual relaxation. | |
972 | ||
973 | RELAX_NOMACRO | |
974 | Set in the first variant frag if the macro appeared in a .set nomacro | |
975 | block and if one alternative requires a warning but the other does not. | |
976 | ||
977 | RELAX_DELAY_SLOT | |
978 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
979 | delay slot. | |
4d7206a2 | 980 | |
df58fc94 RS |
981 | RELAX_DELAY_SLOT_16BIT |
982 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
983 | 16-bit instruction. | |
984 | ||
985 | RELAX_DELAY_SLOT_SIZE_FIRST | |
986 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
987 | the macro is of the wrong size for the branch delay slot. | |
988 | ||
989 | RELAX_DELAY_SLOT_SIZE_SECOND | |
990 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
991 | the macro is of the wrong size for the branch delay slot. | |
992 | ||
4d7206a2 RS |
993 | The frag's "opcode" points to the first fixup for relaxable code. |
994 | ||
995 | Relaxable macros are generated using a sequence such as: | |
996 | ||
997 | relax_start (SYMBOL); | |
998 | ... generate first expansion ... | |
999 | relax_switch (); | |
1000 | ... generate second expansion ... | |
1001 | relax_end (); | |
1002 | ||
1003 | The code and fixups for the unwanted alternative are discarded | |
1004 | by md_convert_frag. */ | |
584892a6 | 1005 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1006 | |
584892a6 RS |
1007 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1008 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1009 | #define RELAX_USE_SECOND 0x10000 | |
1010 | #define RELAX_SECOND_LONGER 0x20000 | |
1011 | #define RELAX_NOMACRO 0x40000 | |
1012 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1013 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1014 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1015 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1016 | |
4a6a3df4 AO |
1017 | /* Branch without likely bit. If label is out of range, we turn: |
1018 | ||
1019 | beq reg1, reg2, label | |
1020 | delay slot | |
1021 | ||
1022 | into | |
1023 | ||
1024 | bne reg1, reg2, 0f | |
1025 | nop | |
1026 | j label | |
1027 | 0: delay slot | |
1028 | ||
1029 | with the following opcode replacements: | |
1030 | ||
1031 | beq <-> bne | |
1032 | blez <-> bgtz | |
1033 | bltz <-> bgez | |
1034 | bc1f <-> bc1t | |
1035 | ||
1036 | bltzal <-> bgezal (with jal label instead of j label) | |
1037 | ||
1038 | Even though keeping the delay slot instruction in the delay slot of | |
1039 | the branch would be more efficient, it would be very tricky to do | |
1040 | correctly, because we'd have to introduce a variable frag *after* | |
1041 | the delay slot instruction, and expand that instead. Let's do it | |
1042 | the easy way for now, even if the branch-not-taken case now costs | |
1043 | one additional instruction. Out-of-range branches are not supposed | |
1044 | to be common, anyway. | |
1045 | ||
1046 | Branch likely. If label is out of range, we turn: | |
1047 | ||
1048 | beql reg1, reg2, label | |
1049 | delay slot (annulled if branch not taken) | |
1050 | ||
1051 | into | |
1052 | ||
1053 | beql reg1, reg2, 1f | |
1054 | nop | |
1055 | beql $0, $0, 2f | |
1056 | nop | |
1057 | 1: j[al] label | |
1058 | delay slot (executed only if branch taken) | |
1059 | 2: | |
1060 | ||
1061 | It would be possible to generate a shorter sequence by losing the | |
1062 | likely bit, generating something like: | |
b34976b6 | 1063 | |
4a6a3df4 AO |
1064 | bne reg1, reg2, 0f |
1065 | nop | |
1066 | j[al] label | |
1067 | delay slot (executed only if branch taken) | |
1068 | 0: | |
1069 | ||
1070 | beql -> bne | |
1071 | bnel -> beq | |
1072 | blezl -> bgtz | |
1073 | bgtzl -> blez | |
1074 | bltzl -> bgez | |
1075 | bgezl -> bltz | |
1076 | bc1fl -> bc1t | |
1077 | bc1tl -> bc1f | |
1078 | ||
1079 | bltzall -> bgezal (with jal label instead of j label) | |
1080 | bgezall -> bltzal (ditto) | |
1081 | ||
1082 | ||
1083 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1084 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1085 | ((relax_substateT) \ | |
1086 | (0xc0000000 \ | |
1087 | | ((at) & 0x1f) \ | |
1088 | | ((toofar) ? 0x20 : 0) \ | |
1089 | | ((link) ? 0x40 : 0) \ | |
1090 | | ((likely) ? 0x80 : 0) \ | |
1091 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1092 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1093 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1094 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1095 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1096 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1097 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1098 | |
252b5132 RH |
1099 | /* For mips16 code, we use an entirely different form of relaxation. |
1100 | mips16 supports two versions of most instructions which take | |
1101 | immediate values: a small one which takes some small value, and a | |
1102 | larger one which takes a 16 bit value. Since branches also follow | |
1103 | this pattern, relaxing these values is required. | |
1104 | ||
1105 | We can assemble both mips16 and normal MIPS code in a single | |
1106 | object. Therefore, we need to support this type of relaxation at | |
1107 | the same time that we support the relaxation described above. We | |
1108 | use the high bit of the subtype field to distinguish these cases. | |
1109 | ||
1110 | The information we store for this type of relaxation is the | |
1111 | argument code found in the opcode file for this relocation, whether | |
1112 | the user explicitly requested a small or extended form, and whether | |
1113 | the relocation is in a jump or jal delay slot. That tells us the | |
1114 | size of the value, and how it should be stored. We also store | |
1115 | whether the fragment is considered to be extended or not. We also | |
1116 | store whether this is known to be a branch to a different section, | |
1117 | whether we have tried to relax this frag yet, and whether we have | |
1118 | ever extended a PC relative fragment because of a shift count. */ | |
1119 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1120 | (0x80000000 \ | |
1121 | | ((type) & 0xff) \ | |
1122 | | ((small) ? 0x100 : 0) \ | |
1123 | | ((ext) ? 0x200 : 0) \ | |
1124 | | ((dslot) ? 0x400 : 0) \ | |
1125 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1126 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1127 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1128 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1129 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1130 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1131 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1132 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1133 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1134 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1135 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1136 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1137 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1138 | |
df58fc94 RS |
1139 | /* For microMIPS code, we use relaxation similar to one we use for |
1140 | MIPS16 code. Some instructions that take immediate values support | |
1141 | two encodings: a small one which takes some small value, and a | |
1142 | larger one which takes a 16 bit value. As some branches also follow | |
1143 | this pattern, relaxing these values is required. | |
1144 | ||
1145 | We can assemble both microMIPS and normal MIPS code in a single | |
1146 | object. Therefore, we need to support this type of relaxation at | |
1147 | the same time that we support the relaxation described above. We | |
1148 | use one of the high bits of the subtype field to distinguish these | |
1149 | cases. | |
1150 | ||
1151 | The information we store for this type of relaxation is the argument | |
1152 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1153 | selected as the assembler temporary, whether the branch is |
1154 | unconditional, whether it is compact, whether it stores the link | |
1155 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1156 | branches to a sequence of instructions is enabled, and whether the | |
1157 | displacement of a branch is too large to fit as an immediate argument | |
1158 | of a 16-bit and a 32-bit branch, respectively. */ | |
1159 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1160 | relax32, toofar16, toofar32) \ | |
1161 | (0x40000000 \ | |
1162 | | ((type) & 0xff) \ | |
1163 | | (((at) & 0x1f) << 8) \ | |
1164 | | ((uncond) ? 0x2000 : 0) \ | |
1165 | | ((compact) ? 0x4000 : 0) \ | |
1166 | | ((link) ? 0x8000 : 0) \ | |
1167 | | ((relax32) ? 0x10000 : 0) \ | |
1168 | | ((toofar16) ? 0x20000 : 0) \ | |
1169 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1170 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1171 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1172 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1173 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1174 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1175 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1176 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1177 | ||
1178 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1179 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1180 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1181 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1182 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1183 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1184 | |
43c0598f RS |
1185 | /* Sign-extend 16-bit value X. */ |
1186 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1187 | ||
885add95 CD |
1188 | /* Is the given value a sign-extended 32-bit value? */ |
1189 | #define IS_SEXT_32BIT_NUM(x) \ | |
1190 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1191 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1192 | ||
1193 | /* Is the given value a sign-extended 16-bit value? */ | |
1194 | #define IS_SEXT_16BIT_NUM(x) \ | |
1195 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1196 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1197 | ||
df58fc94 RS |
1198 | /* Is the given value a sign-extended 12-bit value? */ |
1199 | #define IS_SEXT_12BIT_NUM(x) \ | |
1200 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1201 | ||
2051e8c4 MR |
1202 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1203 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1204 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1205 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1206 | ||
bf12938e RS |
1207 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1208 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1209 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1210 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1211 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1212 | ||
1213 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1214 | SHIFT places. */ | |
1215 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1216 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1217 | ||
1218 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1219 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1220 | ||
1221 | include/opcode/mips.h specifies operand fields using the macros | |
1222 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1223 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1224 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1225 | do \ | |
1226 | if (!(MICROMIPS)) \ | |
1227 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1228 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1229 | else \ | |
1230 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1231 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1232 | while (0) | |
bf12938e RS |
1233 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1234 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1235 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1236 | ||
1237 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1238 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1239 | (!(MICROMIPS) \ | |
1240 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1241 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1242 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1243 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1244 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1245 | MIPS16OP_MASK_##FIELD, \ | |
1246 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1247 | |
1248 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1249 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1250 | \f |
df58fc94 RS |
1251 | /* Whether or not we are emitting a branch-likely macro. */ |
1252 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1253 | ||
4d7206a2 RS |
1254 | /* Global variables used when generating relaxable macros. See the |
1255 | comment above RELAX_ENCODE for more details about how relaxation | |
1256 | is used. */ | |
1257 | static struct { | |
1258 | /* 0 if we're not emitting a relaxable macro. | |
1259 | 1 if we're emitting the first of the two relaxation alternatives. | |
1260 | 2 if we're emitting the second alternative. */ | |
1261 | int sequence; | |
1262 | ||
1263 | /* The first relaxable fixup in the current frag. (In other words, | |
1264 | the first fixup that refers to relaxable code.) */ | |
1265 | fixS *first_fixup; | |
1266 | ||
1267 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1268 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1269 | unsigned int sizes[2]; | |
1270 | ||
1271 | /* The symbol on which the choice of sequence depends. */ | |
1272 | symbolS *symbol; | |
1273 | } mips_relax; | |
252b5132 | 1274 | \f |
584892a6 RS |
1275 | /* Global variables used to decide whether a macro needs a warning. */ |
1276 | static struct { | |
1277 | /* True if the macro is in a branch delay slot. */ | |
1278 | bfd_boolean delay_slot_p; | |
1279 | ||
df58fc94 RS |
1280 | /* Set to the length in bytes required if the macro is in a delay slot |
1281 | that requires a specific length of instruction, otherwise zero. */ | |
1282 | unsigned int delay_slot_length; | |
1283 | ||
584892a6 RS |
1284 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1285 | in bytes and sizes[1] is the length of the second alternative. | |
1286 | For non-relaxable macros, both elements give the length of the | |
1287 | macro in bytes. */ | |
1288 | unsigned int sizes[2]; | |
1289 | ||
df58fc94 RS |
1290 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1291 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1292 | is the length of the first instruction of the second alternative. | |
1293 | For non-relaxable macros, both elements give the length of the first | |
1294 | instruction in bytes. | |
1295 | ||
1296 | Set to zero if we haven't yet seen the first instruction. */ | |
1297 | unsigned int first_insn_sizes[2]; | |
1298 | ||
1299 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1300 | first alternative and insns[1] is the number of instructions for the | |
1301 | second alternative. | |
1302 | ||
1303 | For non-relaxable macros, both elements give the number of | |
1304 | instructions for the macro. */ | |
1305 | unsigned int insns[2]; | |
1306 | ||
584892a6 RS |
1307 | /* The first variant frag for this macro. */ |
1308 | fragS *first_frag; | |
1309 | } mips_macro_warning; | |
1310 | \f | |
252b5132 RH |
1311 | /* Prototypes for static functions. */ |
1312 | ||
17a2f251 | 1313 | #define internalError() \ |
252b5132 | 1314 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1315 | |
1316 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1317 | ||
b34976b6 | 1318 | static void append_insn |
df58fc94 RS |
1319 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1320 | bfd_boolean expansionp); | |
7d10b47d | 1321 | static void mips_no_prev_insn (void); |
c67a084a | 1322 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1323 | static void mips16_macro_build |
03ea81db | 1324 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1325 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1326 | static void macro_start (void); |
1327 | static void macro_end (void); | |
17a2f251 TS |
1328 | static void macro (struct mips_cl_insn * ip); |
1329 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1330 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1331 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1332 | static void mips16_immed |
43c0598f RS |
1333 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1334 | unsigned int, unsigned long *); | |
5e0116d5 | 1335 | static size_t my_getSmallExpression |
17a2f251 TS |
1336 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1337 | static void my_getExpression (expressionS *, char *); | |
1338 | static void s_align (int); | |
1339 | static void s_change_sec (int); | |
1340 | static void s_change_section (int); | |
1341 | static void s_cons (int); | |
1342 | static void s_float_cons (int); | |
1343 | static void s_mips_globl (int); | |
1344 | static void s_option (int); | |
1345 | static void s_mipsset (int); | |
1346 | static void s_abicalls (int); | |
1347 | static void s_cpload (int); | |
1348 | static void s_cpsetup (int); | |
1349 | static void s_cplocal (int); | |
1350 | static void s_cprestore (int); | |
1351 | static void s_cpreturn (int); | |
741d6ea8 JM |
1352 | static void s_dtprelword (int); |
1353 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1354 | static void s_tprelword (int); |
1355 | static void s_tpreldword (int); | |
17a2f251 TS |
1356 | static void s_gpvalue (int); |
1357 | static void s_gpword (int); | |
1358 | static void s_gpdword (int); | |
1359 | static void s_cpadd (int); | |
1360 | static void s_insn (int); | |
1361 | static void md_obj_begin (void); | |
1362 | static void md_obj_end (void); | |
1363 | static void s_mips_ent (int); | |
1364 | static void s_mips_end (int); | |
1365 | static void s_mips_frame (int); | |
1366 | static void s_mips_mask (int reg_type); | |
1367 | static void s_mips_stab (int); | |
1368 | static void s_mips_weakext (int); | |
1369 | static void s_mips_file (int); | |
1370 | static void s_mips_loc (int); | |
1371 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1372 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1373 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1374 | static int validate_micromips_insn (const struct mips_opcode *); |
1375 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1376 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1377 | |
1378 | /* Table and functions used to map between CPU/ISA names, and | |
1379 | ISA levels, and CPU numbers. */ | |
1380 | ||
e972090a NC |
1381 | struct mips_cpu_info |
1382 | { | |
e7af610e | 1383 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1384 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1385 | int isa; /* ISA level. */ |
1386 | int cpu; /* CPU number (default CPU if ISA). */ | |
1387 | }; | |
1388 | ||
ad3fea08 TS |
1389 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1390 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1391 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1392 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1393 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1394 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1395 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1396 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1397 | |
17a2f251 TS |
1398 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1399 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1400 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1401 | \f |
1402 | /* Pseudo-op table. | |
1403 | ||
1404 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1405 | should be defined here, but are currently unsupported: .alias, | |
1406 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1407 | ||
1408 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1409 | specific to the type of debugging information being generated, and | |
1410 | should be defined by the object format: .aent, .begin, .bend, | |
1411 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1412 | .vreg. | |
1413 | ||
1414 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1415 | not MIPS CPU specific, but are also not specific to the object file | |
1416 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1417 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1418 | |
e972090a NC |
1419 | static const pseudo_typeS mips_pseudo_table[] = |
1420 | { | |
beae10d5 | 1421 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1422 | {"option", s_option, 0}, |
1423 | {"set", s_mipsset, 0}, | |
1424 | {"rdata", s_change_sec, 'r'}, | |
1425 | {"sdata", s_change_sec, 's'}, | |
1426 | {"livereg", s_ignore, 0}, | |
1427 | {"abicalls", s_abicalls, 0}, | |
1428 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1429 | {"cpsetup", s_cpsetup, 0}, |
1430 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1431 | {"cprestore", s_cprestore, 0}, |
6478892d | 1432 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1433 | {"dtprelword", s_dtprelword, 0}, |
1434 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1435 | {"tprelword", s_tprelword, 0}, |
1436 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1437 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1438 | {"gpword", s_gpword, 0}, |
10181a0d | 1439 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1440 | {"cpadd", s_cpadd, 0}, |
1441 | {"insn", s_insn, 0}, | |
1442 | ||
beae10d5 | 1443 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1444 | chips. */ |
38a57ae7 | 1445 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1446 | {"bss", s_change_sec, 'b'}, |
1447 | {"err", s_err, 0}, | |
1448 | {"half", s_cons, 1}, | |
1449 | {"dword", s_cons, 3}, | |
1450 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1451 | {"origin", s_org, 0}, |
1452 | {"repeat", s_rept, 0}, | |
252b5132 | 1453 | |
998b3c36 MR |
1454 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1455 | {"sbss", s_change_sec, 'B'}, | |
1456 | ||
beae10d5 | 1457 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1458 | here for one reason or another. */ |
1459 | {"align", s_align, 0}, | |
1460 | {"byte", s_cons, 0}, | |
1461 | {"data", s_change_sec, 'd'}, | |
1462 | {"double", s_float_cons, 'd'}, | |
1463 | {"float", s_float_cons, 'f'}, | |
1464 | {"globl", s_mips_globl, 0}, | |
1465 | {"global", s_mips_globl, 0}, | |
1466 | {"hword", s_cons, 1}, | |
1467 | {"int", s_cons, 2}, | |
1468 | {"long", s_cons, 2}, | |
1469 | {"octa", s_cons, 4}, | |
1470 | {"quad", s_cons, 3}, | |
cca86cc8 | 1471 | {"section", s_change_section, 0}, |
252b5132 RH |
1472 | {"short", s_cons, 1}, |
1473 | {"single", s_float_cons, 'f'}, | |
1474 | {"stabn", s_mips_stab, 'n'}, | |
1475 | {"text", s_change_sec, 't'}, | |
1476 | {"word", s_cons, 2}, | |
add56521 | 1477 | |
add56521 | 1478 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1479 | |
43841e91 | 1480 | { NULL, NULL, 0 }, |
252b5132 RH |
1481 | }; |
1482 | ||
e972090a NC |
1483 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1484 | { | |
beae10d5 KH |
1485 | /* These pseudo-ops should be defined by the object file format. |
1486 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1487 | {"aent", s_mips_ent, 1}, |
1488 | {"bgnb", s_ignore, 0}, | |
1489 | {"end", s_mips_end, 0}, | |
1490 | {"endb", s_ignore, 0}, | |
1491 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1492 | {"file", s_mips_file, 0}, |
252b5132 RH |
1493 | {"fmask", s_mips_mask, 'F'}, |
1494 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1495 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1496 | {"mask", s_mips_mask, 'R'}, |
1497 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1498 | { NULL, NULL, 0 }, |
252b5132 RH |
1499 | }; |
1500 | ||
3ae8dd8d MR |
1501 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1502 | purpose of the `.dc.a' internal pseudo-op. */ | |
1503 | ||
1504 | int | |
1505 | mips_address_bytes (void) | |
1506 | { | |
1507 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1508 | } | |
1509 | ||
17a2f251 | 1510 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1511 | |
1512 | void | |
17a2f251 | 1513 | mips_pop_insert (void) |
252b5132 RH |
1514 | { |
1515 | pop_insert (mips_pseudo_table); | |
1516 | if (! ECOFF_DEBUGGING) | |
1517 | pop_insert (mips_nonecoff_pseudo_table); | |
1518 | } | |
1519 | \f | |
1520 | /* Symbols labelling the current insn. */ | |
1521 | ||
e972090a NC |
1522 | struct insn_label_list |
1523 | { | |
252b5132 RH |
1524 | struct insn_label_list *next; |
1525 | symbolS *label; | |
1526 | }; | |
1527 | ||
252b5132 | 1528 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1529 | #define label_list tc_segment_info_data.labels |
252b5132 | 1530 | |
17a2f251 | 1531 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1532 | static void mips_mark_labels (void); |
1533 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1534 | |
1535 | static inline void | |
17a2f251 | 1536 | mips_clear_insn_labels (void) |
252b5132 RH |
1537 | { |
1538 | register struct insn_label_list **pl; | |
a8dbcb85 | 1539 | segment_info_type *si; |
252b5132 | 1540 | |
a8dbcb85 TS |
1541 | if (now_seg) |
1542 | { | |
1543 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1544 | ; | |
1545 | ||
1546 | si = seg_info (now_seg); | |
1547 | *pl = si->label_list; | |
1548 | si->label_list = NULL; | |
1549 | } | |
252b5132 | 1550 | } |
a8dbcb85 | 1551 | |
df58fc94 RS |
1552 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1553 | ||
1554 | static inline void | |
1555 | mips_mark_labels (void) | |
1556 | { | |
1557 | if (HAVE_CODE_COMPRESSION) | |
1558 | mips_compressed_mark_labels (); | |
1559 | } | |
252b5132 RH |
1560 | \f |
1561 | static char *expr_end; | |
1562 | ||
1563 | /* Expressions which appear in instructions. These are set by | |
1564 | mips_ip. */ | |
1565 | ||
1566 | static expressionS imm_expr; | |
5f74bc13 | 1567 | static expressionS imm2_expr; |
252b5132 RH |
1568 | static expressionS offset_expr; |
1569 | ||
1570 | /* Relocs associated with imm_expr and offset_expr. */ | |
1571 | ||
f6688943 TS |
1572 | static bfd_reloc_code_real_type imm_reloc[3] |
1573 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1574 | static bfd_reloc_code_real_type offset_reloc[3] | |
1575 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1576 | |
df58fc94 RS |
1577 | /* This is set to the resulting size of the instruction to be produced |
1578 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1579 | explicit size is supplied. */ | |
252b5132 | 1580 | |
df58fc94 | 1581 | static unsigned int forced_insn_length; |
252b5132 | 1582 | |
e1b47bd5 RS |
1583 | /* True if we are assembling an instruction. All dot symbols defined during |
1584 | this time should be treated as code labels. */ | |
1585 | ||
1586 | static bfd_boolean mips_assembling_insn; | |
1587 | ||
7ed4a06a | 1588 | #ifdef OBJ_ELF |
ecb4347a DJ |
1589 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1590 | ECOFF debugging. */ | |
252b5132 RH |
1591 | |
1592 | static segT pdr_seg; | |
7ed4a06a | 1593 | #endif |
252b5132 | 1594 | |
e013f690 TS |
1595 | /* The default target format to use. */ |
1596 | ||
aeffff67 RS |
1597 | #if defined (TE_FreeBSD) |
1598 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1599 | #elif defined (TE_TMIPS) | |
1600 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1601 | #else | |
1602 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1603 | #endif | |
1604 | ||
e013f690 | 1605 | const char * |
17a2f251 | 1606 | mips_target_format (void) |
e013f690 TS |
1607 | { |
1608 | switch (OUTPUT_FLAVOR) | |
1609 | { | |
e013f690 TS |
1610 | case bfd_target_ecoff_flavour: |
1611 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1612 | case bfd_target_coff_flavour: | |
1613 | return "pe-mips"; | |
1614 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1615 | #ifdef TE_VXWORKS |
1616 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1617 | return (target_big_endian | |
1618 | ? "elf32-bigmips-vxworks" | |
1619 | : "elf32-littlemips-vxworks"); | |
1620 | #endif | |
e013f690 | 1621 | return (target_big_endian |
cfe86eaa | 1622 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1623 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1624 | : (HAVE_NEWABI |
aeffff67 RS |
1625 | ? ELF_TARGET ("elf32-n", "big") |
1626 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1627 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1628 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1629 | : (HAVE_NEWABI |
aeffff67 RS |
1630 | ? ELF_TARGET ("elf32-n", "little") |
1631 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1632 | default: |
1633 | abort (); | |
1634 | return NULL; | |
1635 | } | |
1636 | } | |
1637 | ||
df58fc94 RS |
1638 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1639 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1640 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1641 | major opcode) will require further modifications to the opcode | |
1642 | table. */ | |
1643 | ||
1644 | static inline unsigned int | |
1645 | micromips_insn_length (const struct mips_opcode *mo) | |
1646 | { | |
1647 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1648 | } | |
1649 | ||
5c04167a RS |
1650 | /* Return the length of MIPS16 instruction OPCODE. */ |
1651 | ||
1652 | static inline unsigned int | |
1653 | mips16_opcode_length (unsigned long opcode) | |
1654 | { | |
1655 | return (opcode >> 16) == 0 ? 2 : 4; | |
1656 | } | |
1657 | ||
1e915849 RS |
1658 | /* Return the length of instruction INSN. */ |
1659 | ||
1660 | static inline unsigned int | |
1661 | insn_length (const struct mips_cl_insn *insn) | |
1662 | { | |
df58fc94 RS |
1663 | if (mips_opts.micromips) |
1664 | return micromips_insn_length (insn->insn_mo); | |
1665 | else if (mips_opts.mips16) | |
5c04167a | 1666 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1667 | else |
1e915849 | 1668 | return 4; |
1e915849 RS |
1669 | } |
1670 | ||
1671 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1672 | ||
1673 | static void | |
1674 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1675 | { | |
1676 | size_t i; | |
1677 | ||
1678 | insn->insn_mo = mo; | |
1e915849 RS |
1679 | insn->insn_opcode = mo->match; |
1680 | insn->frag = NULL; | |
1681 | insn->where = 0; | |
1682 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1683 | insn->fixp[i] = NULL; | |
1684 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1685 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1686 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1687 | insn->complete_p = 0; |
e407c74b | 1688 | insn->cleared_p = 0; |
1e915849 RS |
1689 | } |
1690 | ||
df58fc94 | 1691 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1692 | |
1693 | static void | |
df58fc94 | 1694 | mips_record_compressed_mode (void) |
742a56fe RS |
1695 | { |
1696 | segment_info_type *si; | |
1697 | ||
1698 | si = seg_info (now_seg); | |
1699 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1700 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1701 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1702 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1703 | } |
1704 | ||
4d68580a RS |
1705 | /* Read a standard MIPS instruction from BUF. */ |
1706 | ||
1707 | static unsigned long | |
1708 | read_insn (char *buf) | |
1709 | { | |
1710 | if (target_big_endian) | |
1711 | return bfd_getb32 ((bfd_byte *) buf); | |
1712 | else | |
1713 | return bfd_getl32 ((bfd_byte *) buf); | |
1714 | } | |
1715 | ||
1716 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1717 | the next byte. */ | |
1718 | ||
1719 | static char * | |
1720 | write_insn (char *buf, unsigned int insn) | |
1721 | { | |
1722 | md_number_to_chars (buf, insn, 4); | |
1723 | return buf + 4; | |
1724 | } | |
1725 | ||
1726 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1727 | has length LENGTH. */ | |
1728 | ||
1729 | static unsigned long | |
1730 | read_compressed_insn (char *buf, unsigned int length) | |
1731 | { | |
1732 | unsigned long insn; | |
1733 | unsigned int i; | |
1734 | ||
1735 | insn = 0; | |
1736 | for (i = 0; i < length; i += 2) | |
1737 | { | |
1738 | insn <<= 16; | |
1739 | if (target_big_endian) | |
1740 | insn |= bfd_getb16 ((char *) buf); | |
1741 | else | |
1742 | insn |= bfd_getl16 ((char *) buf); | |
1743 | buf += 2; | |
1744 | } | |
1745 | return insn; | |
1746 | } | |
1747 | ||
5c04167a RS |
1748 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1749 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1750 | ||
1751 | static char * | |
1752 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1753 | { | |
1754 | unsigned int i; | |
1755 | ||
1756 | for (i = 0; i < length; i += 2) | |
1757 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1758 | return buf + length; | |
1759 | } | |
1760 | ||
1e915849 RS |
1761 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1762 | ||
1763 | static void | |
1764 | install_insn (const struct mips_cl_insn *insn) | |
1765 | { | |
1766 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1767 | if (HAVE_CODE_COMPRESSION) |
1768 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1769 | else |
4d68580a | 1770 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1771 | mips_record_compressed_mode (); |
1e915849 RS |
1772 | } |
1773 | ||
1774 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1775 | and install the opcode in the new location. */ | |
1776 | ||
1777 | static void | |
1778 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1779 | { | |
1780 | size_t i; | |
1781 | ||
1782 | insn->frag = frag; | |
1783 | insn->where = where; | |
1784 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1785 | if (insn->fixp[i] != NULL) | |
1786 | { | |
1787 | insn->fixp[i]->fx_frag = frag; | |
1788 | insn->fixp[i]->fx_where = where; | |
1789 | } | |
1790 | install_insn (insn); | |
1791 | } | |
1792 | ||
1793 | /* Add INSN to the end of the output. */ | |
1794 | ||
1795 | static void | |
1796 | add_fixed_insn (struct mips_cl_insn *insn) | |
1797 | { | |
1798 | char *f = frag_more (insn_length (insn)); | |
1799 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1800 | } | |
1801 | ||
1802 | /* Start a variant frag and move INSN to the start of the variant part, | |
1803 | marking it as fixed. The other arguments are as for frag_var. */ | |
1804 | ||
1805 | static void | |
1806 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1807 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1808 | { | |
1809 | frag_grow (max_chars); | |
1810 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1811 | insn->fixed_p = 1; | |
1812 | frag_var (rs_machine_dependent, max_chars, var, | |
1813 | subtype, symbol, offset, NULL); | |
1814 | } | |
1815 | ||
1816 | /* Insert N copies of INSN into the history buffer, starting at | |
1817 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1818 | ||
1819 | static void | |
1820 | insert_into_history (unsigned int first, unsigned int n, | |
1821 | const struct mips_cl_insn *insn) | |
1822 | { | |
1823 | if (mips_relax.sequence != 2) | |
1824 | { | |
1825 | unsigned int i; | |
1826 | ||
1827 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1828 | if (i >= first + n) | |
1829 | history[i] = history[i - n]; | |
1830 | else | |
1831 | history[i] = *insn; | |
1832 | } | |
1833 | } | |
1834 | ||
71400594 RS |
1835 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1836 | the idea is to make it obvious at a glance that each errata is | |
1837 | included. */ | |
1838 | ||
1839 | static void | |
1840 | init_vr4120_conflicts (void) | |
1841 | { | |
1842 | #define CONFLICT(FIRST, SECOND) \ | |
1843 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1844 | ||
1845 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1846 | CONFLICT (MACC, DIV); | |
1847 | CONFLICT (DMACC, DIV); | |
1848 | ||
1849 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1850 | CONFLICT (DMULT, DMULT); | |
1851 | CONFLICT (DMULT, DMACC); | |
1852 | CONFLICT (DMACC, DMULT); | |
1853 | CONFLICT (DMACC, DMACC); | |
1854 | ||
1855 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1856 | CONFLICT (MACC, MTHILO); | |
1857 | CONFLICT (DMACC, MTHILO); | |
1858 | ||
1859 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1860 | instruction is executed immediately after a MACC or DMACC | |
1861 | instruction, the result of [either instruction] is incorrect." */ | |
1862 | CONFLICT (MACC, MULT); | |
1863 | CONFLICT (MACC, DMULT); | |
1864 | CONFLICT (DMACC, MULT); | |
1865 | CONFLICT (DMACC, DMULT); | |
1866 | ||
1867 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1868 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1869 | DDIV or DDIVU instruction, the result of the MACC or | |
1870 | DMACC instruction is incorrect.". */ | |
1871 | CONFLICT (DMULT, MACC); | |
1872 | CONFLICT (DMULT, DMACC); | |
1873 | CONFLICT (DIV, MACC); | |
1874 | CONFLICT (DIV, DMACC); | |
1875 | ||
1876 | #undef CONFLICT | |
1877 | } | |
1878 | ||
707bfff6 TS |
1879 | struct regname { |
1880 | const char *name; | |
1881 | unsigned int num; | |
1882 | }; | |
1883 | ||
1884 | #define RTYPE_MASK 0x1ff00 | |
1885 | #define RTYPE_NUM 0x00100 | |
1886 | #define RTYPE_FPU 0x00200 | |
1887 | #define RTYPE_FCC 0x00400 | |
1888 | #define RTYPE_VEC 0x00800 | |
1889 | #define RTYPE_GP 0x01000 | |
1890 | #define RTYPE_CP0 0x02000 | |
1891 | #define RTYPE_PC 0x04000 | |
1892 | #define RTYPE_ACC 0x08000 | |
1893 | #define RTYPE_CCC 0x10000 | |
1894 | #define RNUM_MASK 0x000ff | |
1895 | #define RWARN 0x80000 | |
1896 | ||
1897 | #define GENERIC_REGISTER_NUMBERS \ | |
1898 | {"$0", RTYPE_NUM | 0}, \ | |
1899 | {"$1", RTYPE_NUM | 1}, \ | |
1900 | {"$2", RTYPE_NUM | 2}, \ | |
1901 | {"$3", RTYPE_NUM | 3}, \ | |
1902 | {"$4", RTYPE_NUM | 4}, \ | |
1903 | {"$5", RTYPE_NUM | 5}, \ | |
1904 | {"$6", RTYPE_NUM | 6}, \ | |
1905 | {"$7", RTYPE_NUM | 7}, \ | |
1906 | {"$8", RTYPE_NUM | 8}, \ | |
1907 | {"$9", RTYPE_NUM | 9}, \ | |
1908 | {"$10", RTYPE_NUM | 10}, \ | |
1909 | {"$11", RTYPE_NUM | 11}, \ | |
1910 | {"$12", RTYPE_NUM | 12}, \ | |
1911 | {"$13", RTYPE_NUM | 13}, \ | |
1912 | {"$14", RTYPE_NUM | 14}, \ | |
1913 | {"$15", RTYPE_NUM | 15}, \ | |
1914 | {"$16", RTYPE_NUM | 16}, \ | |
1915 | {"$17", RTYPE_NUM | 17}, \ | |
1916 | {"$18", RTYPE_NUM | 18}, \ | |
1917 | {"$19", RTYPE_NUM | 19}, \ | |
1918 | {"$20", RTYPE_NUM | 20}, \ | |
1919 | {"$21", RTYPE_NUM | 21}, \ | |
1920 | {"$22", RTYPE_NUM | 22}, \ | |
1921 | {"$23", RTYPE_NUM | 23}, \ | |
1922 | {"$24", RTYPE_NUM | 24}, \ | |
1923 | {"$25", RTYPE_NUM | 25}, \ | |
1924 | {"$26", RTYPE_NUM | 26}, \ | |
1925 | {"$27", RTYPE_NUM | 27}, \ | |
1926 | {"$28", RTYPE_NUM | 28}, \ | |
1927 | {"$29", RTYPE_NUM | 29}, \ | |
1928 | {"$30", RTYPE_NUM | 30}, \ | |
1929 | {"$31", RTYPE_NUM | 31} | |
1930 | ||
1931 | #define FPU_REGISTER_NAMES \ | |
1932 | {"$f0", RTYPE_FPU | 0}, \ | |
1933 | {"$f1", RTYPE_FPU | 1}, \ | |
1934 | {"$f2", RTYPE_FPU | 2}, \ | |
1935 | {"$f3", RTYPE_FPU | 3}, \ | |
1936 | {"$f4", RTYPE_FPU | 4}, \ | |
1937 | {"$f5", RTYPE_FPU | 5}, \ | |
1938 | {"$f6", RTYPE_FPU | 6}, \ | |
1939 | {"$f7", RTYPE_FPU | 7}, \ | |
1940 | {"$f8", RTYPE_FPU | 8}, \ | |
1941 | {"$f9", RTYPE_FPU | 9}, \ | |
1942 | {"$f10", RTYPE_FPU | 10}, \ | |
1943 | {"$f11", RTYPE_FPU | 11}, \ | |
1944 | {"$f12", RTYPE_FPU | 12}, \ | |
1945 | {"$f13", RTYPE_FPU | 13}, \ | |
1946 | {"$f14", RTYPE_FPU | 14}, \ | |
1947 | {"$f15", RTYPE_FPU | 15}, \ | |
1948 | {"$f16", RTYPE_FPU | 16}, \ | |
1949 | {"$f17", RTYPE_FPU | 17}, \ | |
1950 | {"$f18", RTYPE_FPU | 18}, \ | |
1951 | {"$f19", RTYPE_FPU | 19}, \ | |
1952 | {"$f20", RTYPE_FPU | 20}, \ | |
1953 | {"$f21", RTYPE_FPU | 21}, \ | |
1954 | {"$f22", RTYPE_FPU | 22}, \ | |
1955 | {"$f23", RTYPE_FPU | 23}, \ | |
1956 | {"$f24", RTYPE_FPU | 24}, \ | |
1957 | {"$f25", RTYPE_FPU | 25}, \ | |
1958 | {"$f26", RTYPE_FPU | 26}, \ | |
1959 | {"$f27", RTYPE_FPU | 27}, \ | |
1960 | {"$f28", RTYPE_FPU | 28}, \ | |
1961 | {"$f29", RTYPE_FPU | 29}, \ | |
1962 | {"$f30", RTYPE_FPU | 30}, \ | |
1963 | {"$f31", RTYPE_FPU | 31} | |
1964 | ||
1965 | #define FPU_CONDITION_CODE_NAMES \ | |
1966 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1967 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1968 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1969 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1970 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1971 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1972 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1973 | {"$fcc7", RTYPE_FCC | 7} | |
1974 | ||
1975 | #define COPROC_CONDITION_CODE_NAMES \ | |
1976 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1977 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1978 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1979 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1980 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1981 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1982 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1983 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1984 | ||
1985 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1986 | {"$a4", RTYPE_GP | 8}, \ | |
1987 | {"$a5", RTYPE_GP | 9}, \ | |
1988 | {"$a6", RTYPE_GP | 10}, \ | |
1989 | {"$a7", RTYPE_GP | 11}, \ | |
1990 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1991 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1992 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1993 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1994 | {"$t0", RTYPE_GP | 12}, \ | |
1995 | {"$t1", RTYPE_GP | 13}, \ | |
1996 | {"$t2", RTYPE_GP | 14}, \ | |
1997 | {"$t3", RTYPE_GP | 15} | |
1998 | ||
1999 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2000 | {"$t0", RTYPE_GP | 8}, \ | |
2001 | {"$t1", RTYPE_GP | 9}, \ | |
2002 | {"$t2", RTYPE_GP | 10}, \ | |
2003 | {"$t3", RTYPE_GP | 11}, \ | |
2004 | {"$t4", RTYPE_GP | 12}, \ | |
2005 | {"$t5", RTYPE_GP | 13}, \ | |
2006 | {"$t6", RTYPE_GP | 14}, \ | |
2007 | {"$t7", RTYPE_GP | 15}, \ | |
2008 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2009 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2010 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2011 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2012 | ||
2013 | /* Remaining symbolic register names */ | |
2014 | #define SYMBOLIC_REGISTER_NAMES \ | |
2015 | {"$zero", RTYPE_GP | 0}, \ | |
2016 | {"$at", RTYPE_GP | 1}, \ | |
2017 | {"$AT", RTYPE_GP | 1}, \ | |
2018 | {"$v0", RTYPE_GP | 2}, \ | |
2019 | {"$v1", RTYPE_GP | 3}, \ | |
2020 | {"$a0", RTYPE_GP | 4}, \ | |
2021 | {"$a1", RTYPE_GP | 5}, \ | |
2022 | {"$a2", RTYPE_GP | 6}, \ | |
2023 | {"$a3", RTYPE_GP | 7}, \ | |
2024 | {"$s0", RTYPE_GP | 16}, \ | |
2025 | {"$s1", RTYPE_GP | 17}, \ | |
2026 | {"$s2", RTYPE_GP | 18}, \ | |
2027 | {"$s3", RTYPE_GP | 19}, \ | |
2028 | {"$s4", RTYPE_GP | 20}, \ | |
2029 | {"$s5", RTYPE_GP | 21}, \ | |
2030 | {"$s6", RTYPE_GP | 22}, \ | |
2031 | {"$s7", RTYPE_GP | 23}, \ | |
2032 | {"$t8", RTYPE_GP | 24}, \ | |
2033 | {"$t9", RTYPE_GP | 25}, \ | |
2034 | {"$k0", RTYPE_GP | 26}, \ | |
2035 | {"$kt0", RTYPE_GP | 26}, \ | |
2036 | {"$k1", RTYPE_GP | 27}, \ | |
2037 | {"$kt1", RTYPE_GP | 27}, \ | |
2038 | {"$gp", RTYPE_GP | 28}, \ | |
2039 | {"$sp", RTYPE_GP | 29}, \ | |
2040 | {"$s8", RTYPE_GP | 30}, \ | |
2041 | {"$fp", RTYPE_GP | 30}, \ | |
2042 | {"$ra", RTYPE_GP | 31} | |
2043 | ||
2044 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2045 | {"$pc", RTYPE_PC | 0} | |
2046 | ||
2047 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2048 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2049 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2050 | {"$v2", RTYPE_VEC | 2}, \ | |
2051 | {"$v3", RTYPE_VEC | 3}, \ | |
2052 | {"$v4", RTYPE_VEC | 4}, \ | |
2053 | {"$v5", RTYPE_VEC | 5}, \ | |
2054 | {"$v6", RTYPE_VEC | 6}, \ | |
2055 | {"$v7", RTYPE_VEC | 7}, \ | |
2056 | {"$v8", RTYPE_VEC | 8}, \ | |
2057 | {"$v9", RTYPE_VEC | 9}, \ | |
2058 | {"$v10", RTYPE_VEC | 10}, \ | |
2059 | {"$v11", RTYPE_VEC | 11}, \ | |
2060 | {"$v12", RTYPE_VEC | 12}, \ | |
2061 | {"$v13", RTYPE_VEC | 13}, \ | |
2062 | {"$v14", RTYPE_VEC | 14}, \ | |
2063 | {"$v15", RTYPE_VEC | 15}, \ | |
2064 | {"$v16", RTYPE_VEC | 16}, \ | |
2065 | {"$v17", RTYPE_VEC | 17}, \ | |
2066 | {"$v18", RTYPE_VEC | 18}, \ | |
2067 | {"$v19", RTYPE_VEC | 19}, \ | |
2068 | {"$v20", RTYPE_VEC | 20}, \ | |
2069 | {"$v21", RTYPE_VEC | 21}, \ | |
2070 | {"$v22", RTYPE_VEC | 22}, \ | |
2071 | {"$v23", RTYPE_VEC | 23}, \ | |
2072 | {"$v24", RTYPE_VEC | 24}, \ | |
2073 | {"$v25", RTYPE_VEC | 25}, \ | |
2074 | {"$v26", RTYPE_VEC | 26}, \ | |
2075 | {"$v27", RTYPE_VEC | 27}, \ | |
2076 | {"$v28", RTYPE_VEC | 28}, \ | |
2077 | {"$v29", RTYPE_VEC | 29}, \ | |
2078 | {"$v30", RTYPE_VEC | 30}, \ | |
2079 | {"$v31", RTYPE_VEC | 31} | |
2080 | ||
2081 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2082 | {"$ac0", RTYPE_ACC | 0}, \ | |
2083 | {"$ac1", RTYPE_ACC | 1}, \ | |
2084 | {"$ac2", RTYPE_ACC | 2}, \ | |
2085 | {"$ac3", RTYPE_ACC | 3} | |
2086 | ||
2087 | static const struct regname reg_names[] = { | |
2088 | GENERIC_REGISTER_NUMBERS, | |
2089 | FPU_REGISTER_NAMES, | |
2090 | FPU_CONDITION_CODE_NAMES, | |
2091 | COPROC_CONDITION_CODE_NAMES, | |
2092 | ||
2093 | /* The $txx registers depends on the abi, | |
2094 | these will be added later into the symbol table from | |
2095 | one of the tables below once mips_abi is set after | |
2096 | parsing of arguments from the command line. */ | |
2097 | SYMBOLIC_REGISTER_NAMES, | |
2098 | ||
2099 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2100 | MDMX_VECTOR_REGISTER_NAMES, | |
2101 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2102 | {0, 0} | |
2103 | }; | |
2104 | ||
2105 | static const struct regname reg_names_o32[] = { | |
2106 | O32_SYMBOLIC_REGISTER_NAMES, | |
2107 | {0, 0} | |
2108 | }; | |
2109 | ||
2110 | static const struct regname reg_names_n32n64[] = { | |
2111 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2112 | {0, 0} | |
2113 | }; | |
2114 | ||
df58fc94 RS |
2115 | /* Check if S points at a valid register specifier according to TYPES. |
2116 | If so, then return 1, advance S to consume the specifier and store | |
2117 | the register's number in REGNOP, otherwise return 0. */ | |
2118 | ||
707bfff6 TS |
2119 | static int |
2120 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2121 | { | |
2122 | symbolS *symbolP; | |
2123 | char *e; | |
2124 | char save_c; | |
2125 | int reg = -1; | |
2126 | ||
2127 | /* Find end of name. */ | |
2128 | e = *s; | |
2129 | if (is_name_beginner (*e)) | |
2130 | ++e; | |
2131 | while (is_part_of_name (*e)) | |
2132 | ++e; | |
2133 | ||
2134 | /* Terminate name. */ | |
2135 | save_c = *e; | |
2136 | *e = '\0'; | |
2137 | ||
2138 | /* Look for a register symbol. */ | |
2139 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2140 | { | |
2141 | int r = S_GET_VALUE (symbolP); | |
2142 | if (r & types) | |
2143 | reg = r & RNUM_MASK; | |
2144 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2145 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2146 | reg = (r & RNUM_MASK) - 2; | |
2147 | } | |
2148 | /* Else see if this is a register defined in an itbl entry. */ | |
2149 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2150 | { | |
2151 | char *n = *s; | |
2152 | unsigned long r; | |
2153 | ||
2154 | if (*n == '$') | |
2155 | ++n; | |
2156 | if (itbl_get_reg_val (n, &r)) | |
2157 | reg = r & RNUM_MASK; | |
2158 | } | |
2159 | ||
2160 | /* Advance to next token if a register was recognised. */ | |
2161 | if (reg >= 0) | |
2162 | *s = e; | |
2163 | else if (types & RWARN) | |
20203fb9 | 2164 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2165 | |
2166 | *e = save_c; | |
2167 | if (regnop) | |
2168 | *regnop = reg; | |
2169 | return reg >= 0; | |
2170 | } | |
2171 | ||
df58fc94 RS |
2172 | /* Check if S points at a valid register list according to TYPES. |
2173 | If so, then return 1, advance S to consume the list and store | |
2174 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2175 | otherwise return 0. A valid list comprises a comma-separated | |
2176 | enumeration of valid single registers and/or dash-separated | |
2177 | contiguous register ranges as determined by their numbers. | |
2178 | ||
2179 | As a special exception if one of s0-s7 registers is specified as | |
2180 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2181 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2182 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2183 | |
2184 | static int | |
2185 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2186 | { | |
2187 | unsigned int reglist = 0; | |
2188 | unsigned int lastregno; | |
2189 | bfd_boolean ok = TRUE; | |
2190 | unsigned int regmask; | |
2309ddf2 | 2191 | char *s_endlist = *s; |
df58fc94 | 2192 | char *s_reset = *s; |
2309ddf2 | 2193 | unsigned int regno; |
df58fc94 RS |
2194 | |
2195 | while (reg_lookup (s, types, ®no)) | |
2196 | { | |
2197 | lastregno = regno; | |
2198 | if (**s == '-') | |
2199 | { | |
2200 | (*s)++; | |
2201 | ok = reg_lookup (s, types, &lastregno); | |
2202 | if (ok && lastregno < regno) | |
2203 | ok = FALSE; | |
2204 | if (!ok) | |
2205 | break; | |
2206 | } | |
2207 | ||
2208 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2209 | { | |
2210 | lastregno = S7; | |
2211 | reglist |= 1 << FP; | |
2212 | } | |
2213 | regmask = 1 << lastregno; | |
2214 | regmask = (regmask << 1) - 1; | |
2215 | regmask ^= (1 << regno) - 1; | |
2216 | reglist |= regmask; | |
2217 | ||
2309ddf2 | 2218 | s_endlist = *s; |
df58fc94 RS |
2219 | if (**s != ',') |
2220 | break; | |
2221 | (*s)++; | |
2222 | } | |
2223 | ||
2224 | if (ok) | |
2309ddf2 | 2225 | *s = s_endlist; |
df58fc94 RS |
2226 | else |
2227 | *s = s_reset; | |
2228 | if (reglistp) | |
2229 | *reglistp = reglist; | |
2230 | return ok && reglist != 0; | |
2231 | } | |
2232 | ||
037b32b9 | 2233 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2234 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2235 | |
2236 | static bfd_boolean | |
f79e2745 | 2237 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2238 | { |
2239 | int isa = mips_opts.isa; | |
2240 | int fp_s, fp_d; | |
2241 | ||
2242 | if (mips_opts.ase_mdmx) | |
2243 | isa |= INSN_MDMX; | |
2244 | if (mips_opts.ase_dsp) | |
2245 | isa |= INSN_DSP; | |
2246 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2247 | isa |= INSN_DSP64; | |
2248 | if (mips_opts.ase_dspr2) | |
2249 | isa |= INSN_DSPR2; | |
2250 | if (mips_opts.ase_mt) | |
2251 | isa |= INSN_MT; | |
2252 | if (mips_opts.ase_mips3d) | |
2253 | isa |= INSN_MIPS3D; | |
2254 | if (mips_opts.ase_smartmips) | |
2255 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2256 | if (mips_opts.ase_mcu) |
2257 | isa |= INSN_MCU; | |
037b32b9 | 2258 | |
35d0a169 | 2259 | if (!opcode_is_member (mo, isa, mips_opts.arch)) |
037b32b9 AN |
2260 | return FALSE; |
2261 | ||
2262 | /* Check whether the instruction or macro requires single-precision or | |
2263 | double-precision floating-point support. Note that this information is | |
2264 | stored differently in the opcode table for insns and macros. */ | |
2265 | if (mo->pinfo == INSN_MACRO) | |
2266 | { | |
2267 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2268 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2269 | } | |
2270 | else | |
2271 | { | |
2272 | fp_s = mo->pinfo & FP_S; | |
2273 | fp_d = mo->pinfo & FP_D; | |
2274 | } | |
2275 | ||
2276 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2277 | return FALSE; | |
2278 | ||
2279 | if (fp_s && mips_opts.soft_float) | |
2280 | return FALSE; | |
2281 | ||
2282 | return TRUE; | |
2283 | } | |
2284 | ||
2285 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2286 | selected ISA and architecture. */ | |
2287 | ||
2288 | static bfd_boolean | |
2289 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2290 | { | |
35d0a169 | 2291 | return opcode_is_member (mo, mips_opts.isa, mips_opts.arch); |
037b32b9 AN |
2292 | } |
2293 | ||
df58fc94 RS |
2294 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2295 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2296 | ||
2297 | static bfd_boolean | |
2298 | is_size_valid (const struct mips_opcode *mo) | |
2299 | { | |
2300 | if (!mips_opts.micromips) | |
2301 | return TRUE; | |
2302 | ||
2303 | if (!forced_insn_length) | |
2304 | return TRUE; | |
2305 | if (mo->pinfo == INSN_MACRO) | |
2306 | return FALSE; | |
2307 | return forced_insn_length == micromips_insn_length (mo); | |
2308 | } | |
2309 | ||
2310 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2311 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2312 | ||
2313 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2314 | a macro expansion fails because it relies on a preceding 32-bit real | |
2315 | instruction to have matched and does not handle the operands correctly. | |
2316 | The only macros that may expand to 16-bit instructions are JAL that | |
2317 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2318 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2319 | a NOP. In all these cases the macros precede any corresponding real | |
2320 | instruction definitions in the opcode table, so they will match in the | |
2321 | second pass where the size of the delay slot is ignored and therefore | |
2322 | produce correct code. */ | |
df58fc94 RS |
2323 | |
2324 | static bfd_boolean | |
2325 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2326 | { | |
2327 | if (!mips_opts.micromips) | |
2328 | return TRUE; | |
2329 | ||
2330 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2331 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2332 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2333 | && micromips_insn_length (mo) != 4) | |
2334 | return FALSE; | |
2335 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2336 | && micromips_insn_length (mo) != 2) | |
2337 | return FALSE; | |
2338 | ||
2339 | return TRUE; | |
2340 | } | |
2341 | ||
707bfff6 TS |
2342 | /* This function is called once, at assembler startup time. It should set up |
2343 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2344 | |
252b5132 | 2345 | void |
17a2f251 | 2346 | md_begin (void) |
252b5132 | 2347 | { |
3994f87e | 2348 | const char *retval = NULL; |
156c2f8b | 2349 | int i = 0; |
252b5132 | 2350 | int broken = 0; |
1f25f5d3 | 2351 | |
0a44bf69 RS |
2352 | if (mips_pic != NO_PIC) |
2353 | { | |
2354 | if (g_switch_seen && g_switch_value != 0) | |
2355 | as_bad (_("-G may not be used in position-independent code")); | |
2356 | g_switch_value = 0; | |
2357 | } | |
2358 | ||
fef14a42 | 2359 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2360 | as_warn (_("Could not set architecture and machine")); |
2361 | ||
252b5132 RH |
2362 | op_hash = hash_new (); |
2363 | ||
2364 | for (i = 0; i < NUMOPCODES;) | |
2365 | { | |
2366 | const char *name = mips_opcodes[i].name; | |
2367 | ||
17a2f251 | 2368 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2369 | if (retval != NULL) |
2370 | { | |
2371 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2372 | mips_opcodes[i].name, retval); | |
2373 | /* Probably a memory allocation problem? Give up now. */ | |
2374 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2375 | } | |
2376 | do | |
2377 | { | |
2378 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2379 | { | |
2380 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2381 | broken = 1; | |
1e915849 RS |
2382 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2383 | { | |
2384 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2385 | if (mips_fix_loongson2f_nop) |
2386 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2387 | nop_insn.fixed_p = 1; |
2388 | } | |
252b5132 RH |
2389 | } |
2390 | ++i; | |
2391 | } | |
2392 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2393 | } | |
2394 | ||
2395 | mips16_op_hash = hash_new (); | |
2396 | ||
2397 | i = 0; | |
2398 | while (i < bfd_mips16_num_opcodes) | |
2399 | { | |
2400 | const char *name = mips16_opcodes[i].name; | |
2401 | ||
17a2f251 | 2402 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2403 | if (retval != NULL) |
2404 | as_fatal (_("internal: can't hash `%s': %s"), | |
2405 | mips16_opcodes[i].name, retval); | |
2406 | do | |
2407 | { | |
2408 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2409 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2410 | != mips16_opcodes[i].match)) | |
2411 | { | |
2412 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2413 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2414 | broken = 1; | |
2415 | } | |
1e915849 RS |
2416 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2417 | { | |
2418 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2419 | mips16_nop_insn.fixed_p = 1; | |
2420 | } | |
252b5132 RH |
2421 | ++i; |
2422 | } | |
2423 | while (i < bfd_mips16_num_opcodes | |
2424 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2425 | } | |
2426 | ||
df58fc94 RS |
2427 | micromips_op_hash = hash_new (); |
2428 | ||
2429 | i = 0; | |
2430 | while (i < bfd_micromips_num_opcodes) | |
2431 | { | |
2432 | const char *name = micromips_opcodes[i].name; | |
2433 | ||
2434 | retval = hash_insert (micromips_op_hash, name, | |
2435 | (void *) µmips_opcodes[i]); | |
2436 | if (retval != NULL) | |
2437 | as_fatal (_("internal: can't hash `%s': %s"), | |
2438 | micromips_opcodes[i].name, retval); | |
2439 | do | |
2440 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2441 | { | |
2442 | struct mips_cl_insn *micromips_nop_insn; | |
2443 | ||
2444 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2445 | broken = 1; | |
2446 | ||
2447 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2448 | micromips_nop_insn = µmips_nop16_insn; | |
2449 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2450 | micromips_nop_insn = µmips_nop32_insn; | |
2451 | else | |
2452 | continue; | |
2453 | ||
2454 | if (micromips_nop_insn->insn_mo == NULL | |
2455 | && strcmp (name, "nop") == 0) | |
2456 | { | |
2457 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2458 | micromips_nop_insn->fixed_p = 1; | |
2459 | } | |
2460 | } | |
2461 | while (++i < bfd_micromips_num_opcodes | |
2462 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2463 | } | |
2464 | ||
252b5132 RH |
2465 | if (broken) |
2466 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2467 | ||
2468 | /* We add all the general register names to the symbol table. This | |
2469 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2470 | for (i = 0; reg_names[i].name; i++) |
2471 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2472 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2473 | &zero_address_frag)); |
2474 | if (HAVE_NEWABI) | |
2475 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2476 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2477 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2478 | &zero_address_frag)); |
707bfff6 TS |
2479 | else |
2480 | for (i = 0; reg_names_o32[i].name; i++) | |
2481 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2482 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2483 | &zero_address_frag)); |
6047c971 | 2484 | |
7d10b47d | 2485 | mips_no_prev_insn (); |
252b5132 RH |
2486 | |
2487 | mips_gprmask = 0; | |
2488 | mips_cprmask[0] = 0; | |
2489 | mips_cprmask[1] = 0; | |
2490 | mips_cprmask[2] = 0; | |
2491 | mips_cprmask[3] = 0; | |
2492 | ||
2493 | /* set the default alignment for the text section (2**2) */ | |
2494 | record_alignment (text_section, 2); | |
2495 | ||
4d0d148d | 2496 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2497 | |
707bfff6 | 2498 | #ifdef OBJ_ELF |
f43abd2b | 2499 | if (IS_ELF) |
252b5132 | 2500 | { |
0a44bf69 RS |
2501 | /* On a native system other than VxWorks, sections must be aligned |
2502 | to 16 byte boundaries. When configured for an embedded ELF | |
2503 | target, we don't bother. */ | |
c41e87e3 CF |
2504 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2505 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2506 | { |
2507 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2508 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2509 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2510 | } | |
2511 | ||
2512 | /* Create a .reginfo section for register masks and a .mdebug | |
2513 | section for debugging information. */ | |
2514 | { | |
2515 | segT seg; | |
2516 | subsegT subseg; | |
2517 | flagword flags; | |
2518 | segT sec; | |
2519 | ||
2520 | seg = now_seg; | |
2521 | subseg = now_subseg; | |
2522 | ||
2523 | /* The ABI says this section should be loaded so that the | |
2524 | running program can access it. However, we don't load it | |
2525 | if we are configured for an embedded target */ | |
2526 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2527 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2528 | flags |= SEC_ALLOC | SEC_LOAD; |
2529 | ||
316f5878 | 2530 | if (mips_abi != N64_ABI) |
252b5132 RH |
2531 | { |
2532 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2533 | ||
195325d2 TS |
2534 | bfd_set_section_flags (stdoutput, sec, flags); |
2535 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2536 | |
252b5132 | 2537 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2538 | } |
2539 | else | |
2540 | { | |
2541 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2542 | .reginfo section. */ | |
2543 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2544 | bfd_set_section_flags (stdoutput, sec, flags); |
2545 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2546 | |
252b5132 RH |
2547 | /* Set up the option header. */ |
2548 | { | |
2549 | Elf_Internal_Options opthdr; | |
2550 | char *f; | |
2551 | ||
2552 | opthdr.kind = ODK_REGINFO; | |
2553 | opthdr.size = (sizeof (Elf_External_Options) | |
2554 | + sizeof (Elf64_External_RegInfo)); | |
2555 | opthdr.section = 0; | |
2556 | opthdr.info = 0; | |
2557 | f = frag_more (sizeof (Elf_External_Options)); | |
2558 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2559 | (Elf_External_Options *) f); | |
2560 | ||
2561 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2562 | } | |
252b5132 RH |
2563 | } |
2564 | ||
2565 | if (ECOFF_DEBUGGING) | |
2566 | { | |
2567 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2568 | (void) bfd_set_section_flags (stdoutput, sec, | |
2569 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2570 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2571 | } | |
f43abd2b | 2572 | else if (mips_flag_pdr) |
ecb4347a DJ |
2573 | { |
2574 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2575 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2576 | SEC_READONLY | SEC_RELOC | |
2577 | | SEC_DEBUGGING); | |
2578 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2579 | } | |
252b5132 RH |
2580 | |
2581 | subseg_set (seg, subseg); | |
2582 | } | |
2583 | } | |
707bfff6 | 2584 | #endif /* OBJ_ELF */ |
252b5132 RH |
2585 | |
2586 | if (! ECOFF_DEBUGGING) | |
2587 | md_obj_begin (); | |
71400594 RS |
2588 | |
2589 | if (mips_fix_vr4120) | |
2590 | init_vr4120_conflicts (); | |
252b5132 RH |
2591 | } |
2592 | ||
2593 | void | |
17a2f251 | 2594 | md_mips_end (void) |
252b5132 | 2595 | { |
02b1ab82 | 2596 | mips_emit_delays (); |
252b5132 RH |
2597 | if (! ECOFF_DEBUGGING) |
2598 | md_obj_end (); | |
2599 | } | |
2600 | ||
2601 | void | |
17a2f251 | 2602 | md_assemble (char *str) |
252b5132 RH |
2603 | { |
2604 | struct mips_cl_insn insn; | |
f6688943 TS |
2605 | bfd_reloc_code_real_type unused_reloc[3] |
2606 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2607 | |
2608 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2609 | imm2_expr.X_op = O_absent; |
252b5132 | 2610 | offset_expr.X_op = O_absent; |
f6688943 TS |
2611 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2612 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2613 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2614 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2615 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2616 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2617 | |
e1b47bd5 RS |
2618 | mips_mark_labels (); |
2619 | mips_assembling_insn = TRUE; | |
2620 | ||
252b5132 RH |
2621 | if (mips_opts.mips16) |
2622 | mips16_ip (str, &insn); | |
2623 | else | |
2624 | { | |
2625 | mips_ip (str, &insn); | |
beae10d5 KH |
2626 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2627 | str, insn.insn_opcode)); | |
252b5132 RH |
2628 | } |
2629 | ||
2630 | if (insn_error) | |
e1b47bd5 RS |
2631 | as_bad ("%s `%s'", insn_error, str); |
2632 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2633 | { |
584892a6 | 2634 | macro_start (); |
252b5132 RH |
2635 | if (mips_opts.mips16) |
2636 | mips16_macro (&insn); | |
2637 | else | |
2638 | macro (&insn); | |
584892a6 | 2639 | macro_end (); |
252b5132 RH |
2640 | } |
2641 | else | |
2642 | { | |
2643 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2644 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2645 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2646 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2647 | else |
df58fc94 | 2648 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2649 | } |
e1b47bd5 RS |
2650 | |
2651 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2652 | } |
2653 | ||
738e5348 RS |
2654 | /* Convenience functions for abstracting away the differences between |
2655 | MIPS16 and non-MIPS16 relocations. */ | |
2656 | ||
2657 | static inline bfd_boolean | |
2658 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2659 | { | |
2660 | switch (reloc) | |
2661 | { | |
2662 | case BFD_RELOC_MIPS16_JMP: | |
2663 | case BFD_RELOC_MIPS16_GPREL: | |
2664 | case BFD_RELOC_MIPS16_GOT16: | |
2665 | case BFD_RELOC_MIPS16_CALL16: | |
2666 | case BFD_RELOC_MIPS16_HI16_S: | |
2667 | case BFD_RELOC_MIPS16_HI16: | |
2668 | case BFD_RELOC_MIPS16_LO16: | |
2669 | return TRUE; | |
2670 | ||
2671 | default: | |
2672 | return FALSE; | |
2673 | } | |
2674 | } | |
2675 | ||
df58fc94 RS |
2676 | static inline bfd_boolean |
2677 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2678 | { | |
2679 | switch (reloc) | |
2680 | { | |
2681 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2682 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2683 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2684 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2685 | case BFD_RELOC_MICROMIPS_JMP: | |
2686 | case BFD_RELOC_MICROMIPS_HI16: | |
2687 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2688 | case BFD_RELOC_MICROMIPS_LO16: | |
2689 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2690 | case BFD_RELOC_MICROMIPS_GOT16: | |
2691 | case BFD_RELOC_MICROMIPS_CALL16: | |
2692 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2693 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2694 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2695 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2696 | case BFD_RELOC_MICROMIPS_SUB: | |
2697 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2698 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2699 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2700 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2701 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2702 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2703 | case BFD_RELOC_MICROMIPS_JALR: | |
2704 | return TRUE; | |
2705 | ||
2706 | default: | |
2707 | return FALSE; | |
2708 | } | |
2709 | } | |
2710 | ||
2309ddf2 MR |
2711 | static inline bfd_boolean |
2712 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2713 | { | |
2714 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2715 | } | |
2716 | ||
738e5348 RS |
2717 | static inline bfd_boolean |
2718 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2719 | { | |
2309ddf2 | 2720 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2721 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2722 | } |
2723 | ||
2724 | static inline bfd_boolean | |
2725 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2726 | { | |
2309ddf2 | 2727 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2728 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2729 | } |
2730 | ||
2731 | static inline bfd_boolean | |
2732 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2733 | { | |
2309ddf2 | 2734 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2735 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2736 | } | |
2737 | ||
df58fc94 RS |
2738 | static inline bfd_boolean |
2739 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2740 | { | |
2309ddf2 | 2741 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2742 | } |
2743 | ||
5919d012 | 2744 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2745 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2746 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2747 | |
2748 | static inline bfd_boolean | |
17a2f251 | 2749 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2750 | { |
3b91255e | 2751 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2752 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2753 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2754 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2755 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2756 | } | |
2757 | ||
2758 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2759 | reloc_needs_lo_p. */ | |
2760 | ||
2761 | static inline bfd_reloc_code_real_type | |
2762 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2763 | { | |
df58fc94 RS |
2764 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2765 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2766 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2767 | } |
2768 | ||
2769 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2770 | relocation. */ | |
2771 | ||
2772 | static inline bfd_boolean | |
17a2f251 | 2773 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2774 | { |
2775 | return (fixp->fx_next != NULL | |
738e5348 | 2776 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2777 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2778 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2779 | } | |
2780 | ||
252b5132 RH |
2781 | /* This function returns true if modifying a register requires a |
2782 | delay. */ | |
2783 | ||
2784 | static int | |
17a2f251 | 2785 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2786 | { |
2787 | unsigned long prev_pinfo; | |
2788 | ||
47e39b9d | 2789 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2790 | if (! mips_opts.noreorder |
81912461 ILT |
2791 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2792 | && ! gpr_interlocks) | |
2793 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2794 | && ! cop_interlocks))) | |
252b5132 | 2795 | { |
81912461 ILT |
2796 | /* A load from a coprocessor or from memory. All load delays |
2797 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2798 | /* Itbl support may require additional care here. */ |
252b5132 | 2799 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2800 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2801 | return 1; |
2802 | } | |
2803 | ||
2804 | return 0; | |
2805 | } | |
2806 | ||
462427c4 RS |
2807 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2808 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2809 | |
2810 | static void | |
462427c4 | 2811 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2812 | { |
2813 | struct insn_label_list *l; | |
2814 | valueT val; | |
2815 | ||
462427c4 | 2816 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2817 | { |
9c2799c2 | 2818 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2819 | symbol_set_frag (l->label, frag_now); |
2820 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2821 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2822 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2823 | ++val; |
2824 | S_SET_VALUE (l->label, val); | |
2825 | } | |
2826 | } | |
2827 | ||
462427c4 RS |
2828 | /* Move all labels in insn_labels to the current insertion point |
2829 | and treat them as text labels. */ | |
2830 | ||
2831 | static void | |
2832 | mips_move_text_labels (void) | |
2833 | { | |
2834 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2835 | } | |
2836 | ||
5f0fe04b TS |
2837 | static bfd_boolean |
2838 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2839 | { | |
2840 | bfd_boolean linkonce = FALSE; | |
2841 | segT symseg = S_GET_SEGMENT (sym); | |
2842 | ||
2843 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2844 | { | |
2845 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2846 | linkonce = TRUE; | |
2847 | #ifdef OBJ_ELF | |
2848 | /* The GNU toolchain uses an extension for ELF: a section | |
2849 | beginning with the magic string .gnu.linkonce is a | |
2850 | linkonce section. */ | |
2851 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2852 | sizeof ".gnu.linkonce" - 1) == 0) | |
2853 | linkonce = TRUE; | |
2854 | #endif | |
2855 | } | |
2856 | return linkonce; | |
2857 | } | |
2858 | ||
e1b47bd5 | 2859 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2860 | linker to handle them specially, such as generating jalx instructions |
2861 | when needed. We also make them odd for the duration of the assembly, | |
2862 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2863 | in the adjust_symtab routine, while leaving them marked. This is |
2864 | convenient for the debugger and the disassembler. The linker knows | |
2865 | to make them odd again. */ | |
2866 | ||
2867 | static void | |
e1b47bd5 | 2868 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2869 | { |
df58fc94 | 2870 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2871 | |
a8dbcb85 | 2872 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2873 | if (IS_ELF) |
2874 | { | |
2875 | if (mips_opts.mips16) | |
2876 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2877 | else | |
2878 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2879 | } |
e1b47bd5 RS |
2880 | #endif |
2881 | if ((S_GET_VALUE (label) & 1) == 0 | |
2882 | /* Don't adjust the address if the label is global or weak, or | |
2883 | in a link-once section, since we'll be emitting symbol reloc | |
2884 | references to it which will be patched up by the linker, and | |
2885 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2886 | && !S_IS_WEAK (label) | |
2887 | && !S_IS_EXTERNAL (label) | |
2888 | && !s_is_linkonce (label, now_seg)) | |
2889 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2890 | } | |
2891 | ||
2892 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2893 | ||
2894 | static void | |
2895 | mips_compressed_mark_labels (void) | |
2896 | { | |
2897 | struct insn_label_list *l; | |
2898 | ||
2899 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2900 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2901 | } |
2902 | ||
4d7206a2 RS |
2903 | /* End the current frag. Make it a variant frag and record the |
2904 | relaxation info. */ | |
2905 | ||
2906 | static void | |
2907 | relax_close_frag (void) | |
2908 | { | |
584892a6 | 2909 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2910 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2911 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2912 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2913 | ||
2914 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2915 | mips_relax.first_fixup = 0; | |
2916 | } | |
2917 | ||
2918 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2919 | See the comment above RELAX_ENCODE for more details. */ | |
2920 | ||
2921 | static void | |
2922 | relax_start (symbolS *symbol) | |
2923 | { | |
9c2799c2 | 2924 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2925 | mips_relax.sequence = 1; |
2926 | mips_relax.symbol = symbol; | |
2927 | } | |
2928 | ||
2929 | /* Start generating the second version of a relaxable sequence. | |
2930 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2931 | |
2932 | static void | |
4d7206a2 RS |
2933 | relax_switch (void) |
2934 | { | |
9c2799c2 | 2935 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2936 | mips_relax.sequence = 2; |
2937 | } | |
2938 | ||
2939 | /* End the current relaxable sequence. */ | |
2940 | ||
2941 | static void | |
2942 | relax_end (void) | |
2943 | { | |
9c2799c2 | 2944 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2945 | relax_close_frag (); |
2946 | mips_relax.sequence = 0; | |
2947 | } | |
2948 | ||
11625dd8 RS |
2949 | /* Return true if IP is a delayed branch or jump. */ |
2950 | ||
2951 | static inline bfd_boolean | |
2952 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2953 | { | |
2954 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2955 | | INSN_COND_BRANCH_DELAY | |
2956 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2957 | } | |
2958 | ||
2959 | /* Return true if IP is a compact branch or jump. */ | |
2960 | ||
2961 | static inline bfd_boolean | |
2962 | compact_branch_p (const struct mips_cl_insn *ip) | |
2963 | { | |
2964 | if (mips_opts.mips16) | |
2965 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2966 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2967 | else | |
2968 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2969 | | INSN2_COND_BRANCH)) != 0; | |
2970 | } | |
2971 | ||
2972 | /* Return true if IP is an unconditional branch or jump. */ | |
2973 | ||
2974 | static inline bfd_boolean | |
2975 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2976 | { | |
2977 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2978 | || (mips_opts.mips16 | |
2979 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2980 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2981 | } | |
2982 | ||
2983 | /* Return true if IP is a branch-likely instruction. */ | |
2984 | ||
2985 | static inline bfd_boolean | |
2986 | branch_likely_p (const struct mips_cl_insn *ip) | |
2987 | { | |
2988 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2989 | } | |
2990 | ||
14fe068b RS |
2991 | /* Return the type of nop that should be used to fill the delay slot |
2992 | of delayed branch IP. */ | |
2993 | ||
2994 | static struct mips_cl_insn * | |
2995 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2996 | { | |
2997 | if (mips_opts.micromips | |
2998 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2999 | return µmips_nop32_insn; | |
3000 | return NOP_INSN; | |
3001 | } | |
3002 | ||
2309ddf2 | 3003 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3004 | |
3005 | static unsigned int | |
3006 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3007 | { | |
2309ddf2 | 3008 | unsigned long pinfo2; |
df58fc94 RS |
3009 | unsigned int mask; |
3010 | ||
3011 | mask = 0; | |
df58fc94 RS |
3012 | pinfo2 = ip->insn_mo->pinfo2; |
3013 | if (mips_opts.micromips) | |
3014 | { | |
df58fc94 RS |
3015 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3016 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3017 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3018 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3019 | if (pinfo2 & INSN2_MOD_SP) |
3020 | mask |= 1 << SP; | |
3021 | } | |
3022 | return mask; | |
3023 | } | |
3024 | ||
4c260379 RS |
3025 | /* Return the mask of core registers that IP reads. */ |
3026 | ||
3027 | static unsigned int | |
3028 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3029 | { | |
3030 | unsigned long pinfo, pinfo2; | |
3031 | unsigned int mask; | |
3032 | ||
df58fc94 | 3033 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3034 | pinfo = ip->insn_mo->pinfo; |
3035 | pinfo2 = ip->insn_mo->pinfo2; | |
3036 | if (mips_opts.mips16) | |
3037 | { | |
3038 | if (pinfo & MIPS16_INSN_READ_X) | |
3039 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3040 | if (pinfo & MIPS16_INSN_READ_Y) | |
3041 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3042 | if (pinfo & MIPS16_INSN_READ_T) | |
3043 | mask |= 1 << TREG; | |
3044 | if (pinfo & MIPS16_INSN_READ_SP) | |
3045 | mask |= 1 << SP; | |
3046 | if (pinfo & MIPS16_INSN_READ_31) | |
3047 | mask |= 1 << RA; | |
3048 | if (pinfo & MIPS16_INSN_READ_Z) | |
3049 | mask |= 1 << (mips16_to_32_reg_map | |
3050 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3051 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3052 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3057 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3058 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3059 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3060 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3061 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3062 | if (pinfo2 & INSN2_READ_GP) | |
3063 | mask |= 1 << GP; | |
3064 | if (pinfo2 & INSN2_READ_GPR_31) | |
3065 | mask |= 1 << RA; | |
4c260379 | 3066 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3067 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3068 | } |
2b0c8b40 MR |
3069 | if (mips_opts.micromips) |
3070 | { | |
3071 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3072 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3073 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3074 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3075 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3076 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3077 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3078 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3079 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3080 | { | |
3081 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3082 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3083 | } | |
3084 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3085 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3086 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3087 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3088 | } | |
fe35f09f RS |
3089 | /* Don't include register 0. */ |
3090 | return mask & ~1; | |
4c260379 RS |
3091 | } |
3092 | ||
3093 | /* Return the mask of core registers that IP writes. */ | |
3094 | ||
3095 | static unsigned int | |
3096 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3097 | { | |
3098 | unsigned long pinfo, pinfo2; | |
3099 | unsigned int mask; | |
3100 | ||
df58fc94 | 3101 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3102 | pinfo = ip->insn_mo->pinfo; |
3103 | pinfo2 = ip->insn_mo->pinfo2; | |
3104 | if (mips_opts.mips16) | |
3105 | { | |
3106 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3107 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3108 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3109 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3110 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3111 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3112 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3113 | mask |= 1 << TREG; | |
3114 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3115 | mask |= 1 << SP; | |
3116 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3117 | mask |= 1 << RA; | |
3118 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3119 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3120 | } | |
3121 | else | |
3122 | { | |
3123 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3124 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3125 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3126 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3127 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3128 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3129 | if (pinfo & INSN_WRITE_GPR_31) |
3130 | mask |= 1 << RA; | |
3131 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3132 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3133 | } |
2b0c8b40 MR |
3134 | if (mips_opts.micromips) |
3135 | { | |
3136 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3137 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3138 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3139 | { | |
3140 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3141 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3142 | } | |
3143 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3144 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3145 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3146 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3147 | } | |
fe35f09f RS |
3148 | /* Don't include register 0. */ |
3149 | return mask & ~1; | |
4c260379 RS |
3150 | } |
3151 | ||
3152 | /* Return the mask of floating-point registers that IP reads. */ | |
3153 | ||
3154 | static unsigned int | |
3155 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3156 | { | |
3157 | unsigned long pinfo, pinfo2; | |
3158 | unsigned int mask; | |
3159 | ||
3160 | mask = 0; | |
3161 | pinfo = ip->insn_mo->pinfo; | |
3162 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3163 | if (!mips_opts.mips16) |
df58fc94 RS |
3164 | { |
3165 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3166 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3167 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3168 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3169 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3170 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3171 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3172 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3173 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3174 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3175 | } |
3176 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3177 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3178 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3179 | mask |= mask << 1; | |
3180 | return mask; | |
3181 | } | |
3182 | ||
3183 | /* Return the mask of floating-point registers that IP writes. */ | |
3184 | ||
3185 | static unsigned int | |
3186 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3187 | { | |
3188 | unsigned long pinfo, pinfo2; | |
3189 | unsigned int mask; | |
3190 | ||
3191 | mask = 0; | |
3192 | pinfo = ip->insn_mo->pinfo; | |
3193 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3194 | if (!mips_opts.mips16) |
4c260379 RS |
3195 | { |
3196 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3197 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3198 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3199 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3200 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3201 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3202 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3203 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3204 | } |
3205 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3206 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3207 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3208 | mask |= mask << 1; | |
3209 | return mask; | |
3210 | } | |
3211 | ||
71400594 RS |
3212 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3213 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3214 | by VR4120 errata. */ | |
4d7206a2 | 3215 | |
71400594 RS |
3216 | static unsigned int |
3217 | classify_vr4120_insn (const char *name) | |
252b5132 | 3218 | { |
71400594 RS |
3219 | if (strncmp (name, "macc", 4) == 0) |
3220 | return FIX_VR4120_MACC; | |
3221 | if (strncmp (name, "dmacc", 5) == 0) | |
3222 | return FIX_VR4120_DMACC; | |
3223 | if (strncmp (name, "mult", 4) == 0) | |
3224 | return FIX_VR4120_MULT; | |
3225 | if (strncmp (name, "dmult", 5) == 0) | |
3226 | return FIX_VR4120_DMULT; | |
3227 | if (strstr (name, "div")) | |
3228 | return FIX_VR4120_DIV; | |
3229 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3230 | return FIX_VR4120_MTHILO; | |
3231 | return NUM_FIX_VR4120_CLASSES; | |
3232 | } | |
252b5132 | 3233 | |
ff239038 CM |
3234 | #define INSN_ERET 0x42000018 |
3235 | #define INSN_DERET 0x4200001f | |
3236 | ||
71400594 RS |
3237 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3238 | where INSN1 is the earlier instruction. Return the worst-case value | |
3239 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3240 | |
71400594 RS |
3241 | static unsigned int |
3242 | insns_between (const struct mips_cl_insn *insn1, | |
3243 | const struct mips_cl_insn *insn2) | |
3244 | { | |
3245 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3246 | unsigned int mask; |
71400594 RS |
3247 | |
3248 | /* This function needs to know which pinfo flags are set for INSN2 | |
3249 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3250 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3251 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3252 | pinfo1 = insn1->insn_mo->pinfo; |
3253 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3254 | |
4c260379 RS |
3255 | #define INSN2_USES_GPR(REG) \ |
3256 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3257 | |
3258 | /* For most targets, write-after-read dependencies on the HI and LO | |
3259 | registers must be separated by at least two instructions. */ | |
3260 | if (!hilo_interlocks) | |
252b5132 | 3261 | { |
71400594 RS |
3262 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3263 | return 2; | |
3264 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3265 | return 2; | |
3266 | } | |
3267 | ||
3268 | /* If we're working around r7000 errata, there must be two instructions | |
3269 | between an mfhi or mflo and any instruction that uses the result. */ | |
3270 | if (mips_7000_hilo_fix | |
df58fc94 | 3271 | && !mips_opts.micromips |
71400594 | 3272 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3273 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3274 | return 2; |
3275 | ||
ff239038 CM |
3276 | /* If we're working around 24K errata, one instruction is required |
3277 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3278 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3279 | { |
3280 | if (insn1->insn_opcode == INSN_ERET | |
3281 | || insn1->insn_opcode == INSN_DERET) | |
3282 | { | |
3283 | if (insn2 == NULL | |
3284 | || insn2->insn_opcode == INSN_ERET | |
3285 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3286 | || delayed_branch_p (insn2)) |
ff239038 CM |
3287 | return 1; |
3288 | } | |
3289 | } | |
3290 | ||
71400594 RS |
3291 | /* If working around VR4120 errata, check for combinations that need |
3292 | a single intervening instruction. */ | |
df58fc94 | 3293 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3294 | { |
3295 | unsigned int class1, class2; | |
252b5132 | 3296 | |
71400594 RS |
3297 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3298 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3299 | { |
71400594 RS |
3300 | if (insn2 == NULL) |
3301 | return 1; | |
3302 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3303 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3304 | return 1; | |
252b5132 | 3305 | } |
71400594 RS |
3306 | } |
3307 | ||
df58fc94 | 3308 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3309 | { |
3310 | /* Check for GPR or coprocessor load delays. All such delays | |
3311 | are on the RT register. */ | |
3312 | /* Itbl support may require additional care here. */ | |
3313 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3314 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3315 | { |
71400594 | 3316 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3317 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3318 | return 1; |
3319 | } | |
3320 | ||
3321 | /* Check for generic coprocessor hazards. | |
3322 | ||
3323 | This case is not handled very well. There is no special | |
3324 | knowledge of CP0 handling, and the coprocessors other than | |
3325 | the floating point unit are not distinguished at all. */ | |
3326 | /* Itbl support may require additional care here. FIXME! | |
3327 | Need to modify this to include knowledge about | |
3328 | user specified delays! */ | |
3329 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3330 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3331 | { | |
3332 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3333 | register. There must be a one instruction delay before INSN2 | |
3334 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3335 | mask = fpr_write_mask (insn1); |
3336 | if (mask != 0) | |
252b5132 | 3337 | { |
4c260379 | 3338 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3339 | return 1; |
252b5132 RH |
3340 | } |
3341 | else | |
3342 | { | |
71400594 RS |
3343 | /* Read-after-write dependencies on the control registers |
3344 | require a two-instruction gap. */ | |
3345 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3346 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3347 | return 2; | |
3348 | ||
3349 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3350 | also a coprocessor instruction, assume there must be | |
3351 | a one instruction gap. */ | |
3352 | if (pinfo2 & INSN_COP) | |
3353 | return 1; | |
252b5132 RH |
3354 | } |
3355 | } | |
6b76fefe | 3356 | |
71400594 RS |
3357 | /* Check for read-after-write dependencies on the coprocessor |
3358 | control registers in cases where INSN1 does not need a general | |
3359 | coprocessor delay. This means that INSN1 is a floating point | |
3360 | comparison instruction. */ | |
3361 | /* Itbl support may require additional care here. */ | |
3362 | else if (!cop_interlocks | |
3363 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3364 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3365 | return 1; | |
3366 | } | |
6b76fefe | 3367 | |
4c260379 | 3368 | #undef INSN2_USES_GPR |
6b76fefe | 3369 | |
71400594 RS |
3370 | return 0; |
3371 | } | |
6b76fefe | 3372 | |
7d8e00cf RS |
3373 | /* Return the number of nops that would be needed to work around the |
3374 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3375 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3376 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3377 | |
3378 | static int | |
932d1a1b | 3379 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3380 | const struct mips_cl_insn *insn) |
3381 | { | |
4c260379 RS |
3382 | int i, j; |
3383 | unsigned int mask; | |
7d8e00cf RS |
3384 | |
3385 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3386 | are not affected by the errata. */ | |
3387 | if (insn != 0 | |
3388 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3389 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3390 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3391 | return 0; | |
3392 | ||
3393 | /* Search for the first MFLO or MFHI. */ | |
3394 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3395 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3396 | { |
3397 | /* Extract the destination register. */ | |
4c260379 | 3398 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3399 | |
3400 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3401 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3402 | return 0; |
3403 | ||
3404 | /* ...or if any of the intervening instructions do. */ | |
3405 | for (j = 0; j < i; j++) | |
4c260379 | 3406 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3407 | return 0; |
3408 | ||
932d1a1b RS |
3409 | if (i >= ignore) |
3410 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3411 | } |
3412 | return 0; | |
3413 | } | |
3414 | ||
15be625d CM |
3415 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3416 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3417 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3418 | ||
3419 | /* Return the minimum alignment for this store instruction. */ | |
3420 | ||
3421 | static int | |
3422 | fix_24k_align_to (const struct mips_opcode *mo) | |
3423 | { | |
3424 | if (strcmp (mo->name, "sh") == 0) | |
3425 | return 2; | |
3426 | ||
3427 | if (strcmp (mo->name, "swc1") == 0 | |
3428 | || strcmp (mo->name, "swc2") == 0 | |
3429 | || strcmp (mo->name, "sw") == 0 | |
3430 | || strcmp (mo->name, "sc") == 0 | |
3431 | || strcmp (mo->name, "s.s") == 0) | |
3432 | return 4; | |
3433 | ||
3434 | if (strcmp (mo->name, "sdc1") == 0 | |
3435 | || strcmp (mo->name, "sdc2") == 0 | |
3436 | || strcmp (mo->name, "s.d") == 0) | |
3437 | return 8; | |
3438 | ||
3439 | /* sb, swl, swr */ | |
3440 | return 1; | |
3441 | } | |
3442 | ||
3443 | struct fix_24k_store_info | |
3444 | { | |
3445 | /* Immediate offset, if any, for this store instruction. */ | |
3446 | short off; | |
3447 | /* Alignment required by this store instruction. */ | |
3448 | int align_to; | |
3449 | /* True for register offsets. */ | |
3450 | int register_offset; | |
3451 | }; | |
3452 | ||
3453 | /* Comparison function used by qsort. */ | |
3454 | ||
3455 | static int | |
3456 | fix_24k_sort (const void *a, const void *b) | |
3457 | { | |
3458 | const struct fix_24k_store_info *pos1 = a; | |
3459 | const struct fix_24k_store_info *pos2 = b; | |
3460 | ||
3461 | return (pos1->off - pos2->off); | |
3462 | } | |
3463 | ||
3464 | /* INSN is a store instruction. Try to record the store information | |
3465 | in STINFO. Return false if the information isn't known. */ | |
3466 | ||
3467 | static bfd_boolean | |
3468 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3469 | const struct mips_cl_insn *insn) |
15be625d CM |
3470 | { |
3471 | /* The instruction must have a known offset. */ | |
3472 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3473 | return FALSE; | |
3474 | ||
3475 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3476 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3477 | return TRUE; | |
3478 | } | |
3479 | ||
932d1a1b RS |
3480 | /* Return the number of nops that would be needed to work around the 24k |
3481 | "lost data on stores during refill" errata if instruction INSN | |
3482 | immediately followed the 2 instructions described by HIST. | |
3483 | Ignore hazards that are contained within the first IGNORE | |
3484 | instructions of HIST. | |
3485 | ||
3486 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3487 | for the data cache refills and store data. The following describes | |
3488 | the scenario where the store data could be lost. | |
3489 | ||
3490 | * A data cache miss, due to either a load or a store, causing fill | |
3491 | data to be supplied by the memory subsystem | |
3492 | * The first three doublewords of fill data are returned and written | |
3493 | into the cache | |
3494 | * A sequence of four stores occurs in consecutive cycles around the | |
3495 | final doubleword of the fill: | |
3496 | * Store A | |
3497 | * Store B | |
3498 | * Store C | |
3499 | * Zero, One or more instructions | |
3500 | * Store D | |
3501 | ||
3502 | The four stores A-D must be to different doublewords of the line that | |
3503 | is being filled. The fourth instruction in the sequence above permits | |
3504 | the fill of the final doubleword to be transferred from the FSB into | |
3505 | the cache. In the sequence above, the stores may be either integer | |
3506 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3507 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3508 | different doublewords on the line. If the floating point unit is | |
3509 | running in 1:2 mode, it is not possible to create the sequence above | |
3510 | using only floating point store instructions. | |
15be625d CM |
3511 | |
3512 | In this case, the cache line being filled is incorrectly marked | |
3513 | invalid, thereby losing the data from any store to the line that | |
3514 | occurs between the original miss and the completion of the five | |
3515 | cycle sequence shown above. | |
3516 | ||
932d1a1b | 3517 | The workarounds are: |
15be625d | 3518 | |
932d1a1b RS |
3519 | * Run the data cache in write-through mode. |
3520 | * Insert a non-store instruction between | |
3521 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3522 | |
3523 | static int | |
932d1a1b | 3524 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3525 | const struct mips_cl_insn *insn) |
3526 | { | |
3527 | struct fix_24k_store_info pos[3]; | |
3528 | int align, i, base_offset; | |
3529 | ||
932d1a1b RS |
3530 | if (ignore >= 2) |
3531 | return 0; | |
3532 | ||
ab9794cf RS |
3533 | /* If the previous instruction wasn't a store, there's nothing to |
3534 | worry about. */ | |
15be625d CM |
3535 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3536 | return 0; | |
3537 | ||
ab9794cf RS |
3538 | /* If the instructions after the previous one are unknown, we have |
3539 | to assume the worst. */ | |
3540 | if (!insn) | |
15be625d CM |
3541 | return 1; |
3542 | ||
ab9794cf RS |
3543 | /* Check whether we are dealing with three consecutive stores. */ |
3544 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3545 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3546 | return 0; |
3547 | ||
3548 | /* If we don't know the relationship between the store addresses, | |
3549 | assume the worst. */ | |
ab9794cf | 3550 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3551 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3552 | return 1; | |
3553 | ||
3554 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3555 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3556 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3557 | return 1; | |
3558 | ||
3559 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3560 | ||
3561 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3562 | X bytes and such that the base register + X is known to be aligned | |
3563 | to align bytes. */ | |
3564 | ||
3565 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3566 | align = 8; | |
3567 | else | |
3568 | { | |
3569 | align = pos[0].align_to; | |
3570 | base_offset = pos[0].off; | |
3571 | for (i = 1; i < 3; i++) | |
3572 | if (align < pos[i].align_to) | |
3573 | { | |
3574 | align = pos[i].align_to; | |
3575 | base_offset = pos[i].off; | |
3576 | } | |
3577 | for (i = 0; i < 3; i++) | |
3578 | pos[i].off -= base_offset; | |
3579 | } | |
3580 | ||
3581 | pos[0].off &= ~align + 1; | |
3582 | pos[1].off &= ~align + 1; | |
3583 | pos[2].off &= ~align + 1; | |
3584 | ||
3585 | /* If any two stores write to the same chunk, they also write to the | |
3586 | same doubleword. The offsets are still sorted at this point. */ | |
3587 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3588 | return 0; | |
3589 | ||
3590 | /* A range of at least 9 bytes is needed for the stores to be in | |
3591 | non-overlapping doublewords. */ | |
3592 | if (pos[2].off - pos[0].off <= 8) | |
3593 | return 0; | |
3594 | ||
3595 | if (pos[2].off - pos[1].off >= 24 | |
3596 | || pos[1].off - pos[0].off >= 24 | |
3597 | || pos[2].off - pos[0].off >= 32) | |
3598 | return 0; | |
3599 | ||
3600 | return 1; | |
3601 | } | |
3602 | ||
71400594 | 3603 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3604 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3605 | where HIST[0] is the most recent instruction. Ignore hazards |
3606 | between INSN and the first IGNORE instructions in HIST. | |
3607 | ||
3608 | If INSN is null, return the worse-case number of nops for any | |
3609 | instruction. */ | |
bdaaa2e1 | 3610 | |
71400594 | 3611 | static int |
932d1a1b | 3612 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3613 | const struct mips_cl_insn *insn) |
3614 | { | |
3615 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3616 | |
71400594 | 3617 | nops = 0; |
932d1a1b | 3618 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3619 | { |
91d6fa6a | 3620 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3621 | if (tmp_nops > nops) |
3622 | nops = tmp_nops; | |
3623 | } | |
7d8e00cf | 3624 | |
df58fc94 | 3625 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3626 | { |
932d1a1b | 3627 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3628 | if (tmp_nops > nops) |
3629 | nops = tmp_nops; | |
3630 | } | |
3631 | ||
df58fc94 | 3632 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3633 | { |
932d1a1b | 3634 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3635 | if (tmp_nops > nops) |
3636 | nops = tmp_nops; | |
3637 | } | |
3638 | ||
71400594 RS |
3639 | return nops; |
3640 | } | |
252b5132 | 3641 | |
71400594 | 3642 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3643 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3644 | would be needed after the extended sequence, ignoring hazards |
3645 | in the first IGNORE instructions. */ | |
252b5132 | 3646 | |
71400594 | 3647 | static int |
932d1a1b RS |
3648 | nops_for_sequence (int num_insns, int ignore, |
3649 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3650 | { |
3651 | va_list args; | |
3652 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3653 | struct mips_cl_insn *cursor; | |
3654 | int nops; | |
3655 | ||
91d6fa6a | 3656 | va_start (args, hist); |
71400594 | 3657 | cursor = buffer + num_insns; |
91d6fa6a | 3658 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3659 | while (cursor > buffer) |
3660 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3661 | ||
932d1a1b | 3662 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3663 | va_end (args); |
3664 | return nops; | |
3665 | } | |
252b5132 | 3666 | |
71400594 RS |
3667 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3668 | worst-case delay for the branch target. */ | |
252b5132 | 3669 | |
71400594 | 3670 | static int |
932d1a1b | 3671 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3672 | const struct mips_cl_insn *insn) |
3673 | { | |
3674 | int nops, tmp_nops; | |
60b63b72 | 3675 | |
932d1a1b | 3676 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3677 | if (delayed_branch_p (insn)) |
71400594 | 3678 | { |
932d1a1b | 3679 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3680 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3681 | if (tmp_nops > nops) |
3682 | nops = tmp_nops; | |
3683 | } | |
11625dd8 | 3684 | else if (compact_branch_p (insn)) |
71400594 | 3685 | { |
932d1a1b | 3686 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3687 | if (tmp_nops > nops) |
3688 | nops = tmp_nops; | |
3689 | } | |
3690 | return nops; | |
3691 | } | |
3692 | ||
c67a084a NC |
3693 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3694 | ||
3695 | static void | |
3696 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3697 | { | |
df58fc94 | 3698 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3699 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3700 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3701 | } | |
3702 | ||
3703 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3704 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3705 | ||
3706 | static void | |
3707 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3708 | { | |
df58fc94 | 3709 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3710 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3711 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3712 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3713 | { | |
3714 | int sreg; | |
3715 | expressionS ep; | |
3716 | ||
3717 | if (! mips_opts.at) | |
3718 | return; | |
3719 | ||
df58fc94 | 3720 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3721 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3722 | return; | |
3723 | ||
3724 | ep.X_op = O_constant; | |
3725 | ep.X_add_number = 0xcfff0000; | |
3726 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3727 | ep.X_add_number = 0xffff; | |
3728 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3729 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3730 | } | |
3731 | } | |
3732 | ||
3733 | static void | |
3734 | fix_loongson2f (struct mips_cl_insn * ip) | |
3735 | { | |
3736 | if (mips_fix_loongson2f_nop) | |
3737 | fix_loongson2f_nop (ip); | |
3738 | ||
3739 | if (mips_fix_loongson2f_jump) | |
3740 | fix_loongson2f_jump (ip); | |
3741 | } | |
3742 | ||
a4e06468 RS |
3743 | /* IP is a branch that has a delay slot, and we need to fill it |
3744 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3745 | with the previous instruction. |
3746 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3747 | RELOC_TYPE. */ | |
a4e06468 RS |
3748 | |
3749 | static bfd_boolean | |
e407c74b NC |
3750 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3751 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3752 | { |
2b0c8b40 | 3753 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3754 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3755 | ||
3756 | /* -O2 and above is required for this optimization. */ | |
3757 | if (mips_optimize < 2) | |
3758 | return FALSE; | |
3759 | ||
3760 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3761 | if (mips_opts.nomove) | |
3762 | return FALSE; | |
3763 | ||
3764 | /* We can't swap if the previous instruction's position is fixed. */ | |
3765 | if (history[0].fixed_p) | |
3766 | return FALSE; | |
3767 | ||
3768 | /* If the previous previous insn was in a .set noreorder, we can't | |
3769 | swap. Actually, the MIPS assembler will swap in this situation. | |
3770 | However, gcc configured -with-gnu-as will generate code like | |
3771 | ||
3772 | .set noreorder | |
3773 | lw $4,XXX | |
3774 | .set reorder | |
3775 | INSN | |
3776 | bne $4,$0,foo | |
3777 | ||
3778 | in which we can not swap the bne and INSN. If gcc is not configured | |
3779 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3780 | if (history[1].noreorder_p) | |
3781 | return FALSE; | |
3782 | ||
87333bb7 MR |
3783 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3784 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3785 | if (mips_opts.mips16 && history[0].fixp[0]) |
3786 | return FALSE; | |
3787 | ||
3788 | /* If the branch is itself the target of a branch, we can not swap. | |
3789 | We cheat on this; all we check for is whether there is a label on | |
3790 | this instruction. If there are any branches to anything other than | |
3791 | a label, users must use .set noreorder. */ | |
3792 | if (seg_info (now_seg)->label_list) | |
3793 | return FALSE; | |
3794 | ||
3795 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3796 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3797 | MIPS16 code, which uses variant frags for different purposes. */ |
3798 | if (!mips_opts.mips16 | |
a4e06468 RS |
3799 | && history[0].frag |
3800 | && history[0].frag->fr_type == rs_machine_dependent) | |
3801 | return FALSE; | |
3802 | ||
bcd530a7 RS |
3803 | /* We do not swap with instructions that cannot architecturally |
3804 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3805 | also refrain from swapping with a trap instruction, since it | |
3806 | complicates trap handlers to have the trap instruction be in | |
3807 | a delay slot. */ | |
a4e06468 | 3808 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3809 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3810 | return FALSE; |
3811 | ||
3812 | /* Check for conflicts between the branch and the instructions | |
3813 | before the candidate delay slot. */ | |
3814 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3815 | return FALSE; | |
3816 | ||
3817 | /* Check for conflicts between the swapped sequence and the | |
3818 | target of the branch. */ | |
3819 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3820 | return FALSE; | |
3821 | ||
3822 | /* If the branch reads a register that the previous | |
3823 | instruction sets, we can not swap. */ | |
3824 | gpr_read = gpr_read_mask (ip); | |
3825 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3826 | if (gpr_read & prev_gpr_write) | |
3827 | return FALSE; | |
3828 | ||
3829 | /* If the branch writes a register that the previous | |
3830 | instruction sets, we can not swap. */ | |
3831 | gpr_write = gpr_write_mask (ip); | |
3832 | if (gpr_write & prev_gpr_write) | |
3833 | return FALSE; | |
3834 | ||
3835 | /* If the branch writes a register that the previous | |
3836 | instruction reads, we can not swap. */ | |
3837 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3838 | if (gpr_write & prev_gpr_read) | |
3839 | return FALSE; | |
3840 | ||
3841 | /* If one instruction sets a condition code and the | |
3842 | other one uses a condition code, we can not swap. */ | |
3843 | pinfo = ip->insn_mo->pinfo; | |
3844 | if ((pinfo & INSN_READ_COND_CODE) | |
3845 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3846 | return FALSE; | |
3847 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3848 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3849 | return FALSE; | |
3850 | ||
3851 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3852 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3853 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3854 | return FALSE; | |
2b0c8b40 MR |
3855 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3856 | return FALSE; | |
a4e06468 | 3857 | |
df58fc94 RS |
3858 | /* If the previous instruction has an incorrect size for a fixed |
3859 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3860 | pinfo2 = ip->insn_mo->pinfo2; |
3861 | if (mips_opts.micromips | |
3862 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3863 | && insn_length (history) != 2) | |
3864 | return FALSE; | |
3865 | if (mips_opts.micromips | |
3866 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3867 | && insn_length (history) != 4) | |
3868 | return FALSE; | |
3869 | ||
e407c74b NC |
3870 | /* On R5900 short loops need to be fixed by inserting a nop in |
3871 | the branch delay slots. | |
3872 | A short loop can be terminated too early. */ | |
3873 | if (mips_opts.arch == CPU_R5900 | |
3874 | /* Check if instruction has a parameter, ignore "j $31". */ | |
3875 | && (address_expr != NULL) | |
3876 | /* Parameter must be 16 bit. */ | |
3877 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
3878 | /* Branch to same segment. */ | |
3879 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
3880 | /* Branch to same code fragment. */ | |
3881 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
3882 | /* Can only calculate branch offset if value is known. */ | |
3883 | && symbol_constant_p(address_expr->X_add_symbol) | |
3884 | /* Check if branch is really conditional. */ | |
3885 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
3886 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
3887 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
3888 | { | |
3889 | int distance; | |
3890 | /* Check if loop is shorter than 6 instructions including | |
3891 | branch and delay slot. */ | |
3892 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
3893 | if (distance <= 20) | |
3894 | { | |
3895 | int i; | |
3896 | int rv; | |
3897 | ||
3898 | rv = FALSE; | |
3899 | /* When the loop includes branches or jumps, | |
3900 | it is not a short loop. */ | |
3901 | for (i = 0; i < (distance / 4); i++) | |
3902 | { | |
3903 | if ((history[i].cleared_p) | |
3904 | || delayed_branch_p(&history[i])) | |
3905 | { | |
3906 | rv = TRUE; | |
3907 | break; | |
3908 | } | |
3909 | } | |
3910 | if (rv == FALSE) | |
3911 | { | |
3912 | /* Insert nop after branch to fix short loop. */ | |
3913 | return FALSE; | |
3914 | } | |
3915 | } | |
3916 | } | |
3917 | ||
a4e06468 RS |
3918 | return TRUE; |
3919 | } | |
3920 | ||
e407c74b NC |
3921 | /* Decide how we should add IP to the instruction stream. |
3922 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3923 | RELOC_TYPE. */ | |
a4e06468 RS |
3924 | |
3925 | static enum append_method | |
e407c74b NC |
3926 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
3927 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
3928 | { |
3929 | unsigned long pinfo; | |
3930 | ||
3931 | /* The relaxed version of a macro sequence must be inherently | |
3932 | hazard-free. */ | |
3933 | if (mips_relax.sequence == 2) | |
3934 | return APPEND_ADD; | |
3935 | ||
3936 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3937 | if (mips_opts.noreorder) | |
3938 | return APPEND_ADD; | |
3939 | ||
3940 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3941 | if (delayed_branch_p (ip)) |
a4e06468 | 3942 | { |
e407c74b NC |
3943 | if (!branch_likely_p (ip) |
3944 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
3945 | return APPEND_SWAP; |
3946 | ||
11625dd8 | 3947 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3948 | if (mips_opts.mips16 |
3949 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3950 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3951 | return APPEND_ADD_COMPACT; | |
3952 | ||
3953 | return APPEND_ADD_WITH_NOP; | |
3954 | } | |
3955 | ||
a4e06468 RS |
3956 | return APPEND_ADD; |
3957 | } | |
3958 | ||
ceb94aa5 RS |
3959 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3960 | Point IP->insn_mo to the new opcode's definition. */ | |
3961 | ||
3962 | static void | |
3963 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3964 | { | |
3965 | const struct mips_opcode *mo, *end; | |
3966 | ||
3967 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3968 | for (mo = ip->insn_mo; mo < end; mo++) | |
3969 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3970 | { | |
3971 | ip->insn_mo = mo; | |
3972 | return; | |
3973 | } | |
3974 | abort (); | |
3975 | } | |
3976 | ||
df58fc94 RS |
3977 | /* For microMIPS macros, we need to generate a local number label |
3978 | as the target of branches. */ | |
3979 | #define MICROMIPS_LABEL_CHAR '\037' | |
3980 | static unsigned long micromips_target_label; | |
3981 | static char micromips_target_name[32]; | |
3982 | ||
3983 | static char * | |
3984 | micromips_label_name (void) | |
3985 | { | |
3986 | char *p = micromips_target_name; | |
3987 | char symbol_name_temporary[24]; | |
3988 | unsigned long l; | |
3989 | int i; | |
3990 | ||
3991 | if (*p) | |
3992 | return p; | |
3993 | ||
3994 | i = 0; | |
3995 | l = micromips_target_label; | |
3996 | #ifdef LOCAL_LABEL_PREFIX | |
3997 | *p++ = LOCAL_LABEL_PREFIX; | |
3998 | #endif | |
3999 | *p++ = 'L'; | |
4000 | *p++ = MICROMIPS_LABEL_CHAR; | |
4001 | do | |
4002 | { | |
4003 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4004 | l /= 10; | |
4005 | } | |
4006 | while (l != 0); | |
4007 | while (i > 0) | |
4008 | *p++ = symbol_name_temporary[--i]; | |
4009 | *p = '\0'; | |
4010 | ||
4011 | return micromips_target_name; | |
4012 | } | |
4013 | ||
4014 | static void | |
4015 | micromips_label_expr (expressionS *label_expr) | |
4016 | { | |
4017 | label_expr->X_op = O_symbol; | |
4018 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4019 | label_expr->X_add_number = 0; | |
4020 | } | |
4021 | ||
4022 | static void | |
4023 | micromips_label_inc (void) | |
4024 | { | |
4025 | micromips_target_label++; | |
4026 | *micromips_target_name = '\0'; | |
4027 | } | |
4028 | ||
4029 | static void | |
4030 | micromips_add_label (void) | |
4031 | { | |
4032 | symbolS *s; | |
4033 | ||
4034 | s = colon (micromips_label_name ()); | |
4035 | micromips_label_inc (); | |
4036 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4037 | if (IS_ELF) | |
4038 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4039 | #else |
4040 | (void) s; | |
df58fc94 RS |
4041 | #endif |
4042 | } | |
4043 | ||
4044 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4045 | corresponding to the requested one if any. Otherwise return | |
4046 | the reloc unchanged. */ | |
4047 | ||
4048 | static bfd_reloc_code_real_type | |
4049 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4050 | { | |
4051 | static const bfd_reloc_code_real_type relocs[][2] = | |
4052 | { | |
4053 | /* Keep sorted incrementally by the left-hand key. */ | |
4054 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4055 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4056 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4057 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4058 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4059 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4060 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4061 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4062 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4063 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4064 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4065 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4066 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4067 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4068 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4069 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4070 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4071 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4072 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4073 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4074 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4075 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4076 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4077 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4078 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4079 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4080 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4081 | }; | |
4082 | bfd_reloc_code_real_type r; | |
4083 | size_t i; | |
4084 | ||
4085 | if (!mips_opts.micromips) | |
4086 | return reloc; | |
4087 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4088 | { | |
4089 | r = relocs[i][0]; | |
4090 | if (r > reloc) | |
4091 | return reloc; | |
4092 | if (r == reloc) | |
4093 | return relocs[i][1]; | |
4094 | } | |
4095 | return reloc; | |
4096 | } | |
4097 | ||
b886a2ab RS |
4098 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4099 | Return true on success, storing the resolved value in RESULT. */ | |
4100 | ||
4101 | static bfd_boolean | |
4102 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4103 | offsetT *result) | |
4104 | { | |
4105 | switch (reloc) | |
4106 | { | |
4107 | case BFD_RELOC_MIPS_HIGHEST: | |
4108 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4109 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4110 | return TRUE; | |
4111 | ||
4112 | case BFD_RELOC_MIPS_HIGHER: | |
4113 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4114 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4115 | return TRUE; | |
4116 | ||
4117 | case BFD_RELOC_HI16_S: | |
4118 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4119 | case BFD_RELOC_MIPS16_HI16_S: | |
4120 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4121 | return TRUE; | |
4122 | ||
4123 | case BFD_RELOC_HI16: | |
4124 | case BFD_RELOC_MICROMIPS_HI16: | |
4125 | case BFD_RELOC_MIPS16_HI16: | |
4126 | *result = (operand >> 16) & 0xffff; | |
4127 | return TRUE; | |
4128 | ||
4129 | case BFD_RELOC_LO16: | |
4130 | case BFD_RELOC_MICROMIPS_LO16: | |
4131 | case BFD_RELOC_MIPS16_LO16: | |
4132 | *result = operand & 0xffff; | |
4133 | return TRUE; | |
4134 | ||
4135 | case BFD_RELOC_UNUSED: | |
4136 | *result = operand; | |
4137 | return TRUE; | |
4138 | ||
4139 | default: | |
4140 | return FALSE; | |
4141 | } | |
4142 | } | |
4143 | ||
71400594 RS |
4144 | /* Output an instruction. IP is the instruction information. |
4145 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4146 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4147 | a macro expansion. */ | |
71400594 RS |
4148 | |
4149 | static void | |
4150 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4151 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4152 | { |
14fe068b | 4153 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4154 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4155 | enum append_method method; |
2309ddf2 | 4156 | bfd_boolean relax32; |
2b0c8b40 | 4157 | int branch_disp; |
71400594 | 4158 | |
2309ddf2 | 4159 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4160 | fix_loongson2f (ip); |
4161 | ||
738f4d98 | 4162 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4163 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4164 | |
df58fc94 | 4165 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4166 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4167 | |
4168 | if (mips_opts.micromips | |
4169 | && !expansionp | |
4170 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4171 | && micromips_insn_length (ip->insn_mo) != 2) | |
4172 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4173 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4174 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4175 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4176 | |
15be625d CM |
4177 | if (address_expr == NULL) |
4178 | ip->complete_p = 1; | |
b886a2ab RS |
4179 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4180 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4181 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4182 | && address_expr->X_op == O_constant) |
4183 | { | |
15be625d CM |
4184 | switch (*reloc_type) |
4185 | { | |
15be625d | 4186 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4187 | { |
4188 | int shift; | |
4189 | ||
4190 | shift = mips_opts.micromips ? 1 : 2; | |
4191 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4192 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4193 | (unsigned long) address_expr->X_add_number); | |
4194 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4195 | & 0x3ffffff); | |
335574df | 4196 | ip->complete_p = 1; |
df58fc94 | 4197 | } |
15be625d CM |
4198 | break; |
4199 | ||
4200 | case BFD_RELOC_MIPS16_JMP: | |
4201 | if ((address_expr->X_add_number & 3) != 0) | |
4202 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4203 | (unsigned long) address_expr->X_add_number); | |
4204 | ip->insn_opcode |= | |
4205 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4206 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4207 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4208 | ip->complete_p = 1; |
15be625d CM |
4209 | break; |
4210 | ||
4211 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4212 | { |
4213 | int shift; | |
4214 | ||
4215 | shift = mips_opts.micromips ? 1 : 2; | |
4216 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4217 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4218 | (unsigned long) address_expr->X_add_number); | |
4219 | if (!mips_relax_branch) | |
4220 | { | |
4221 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4222 | & ~((1 << (shift + 16)) - 1)) | |
4223 | as_bad (_("branch address range overflow (0x%lx)"), | |
4224 | (unsigned long) address_expr->X_add_number); | |
4225 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4226 | & 0xffff); | |
4227 | } | |
df58fc94 | 4228 | } |
15be625d CM |
4229 | break; |
4230 | ||
4231 | default: | |
b886a2ab RS |
4232 | { |
4233 | offsetT value; | |
4234 | ||
4235 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4236 | &value)) | |
4237 | { | |
4238 | ip->insn_opcode |= value & 0xffff; | |
4239 | ip->complete_p = 1; | |
4240 | } | |
4241 | } | |
4242 | break; | |
4243 | } | |
15be625d CM |
4244 | } |
4245 | ||
71400594 RS |
4246 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4247 | { | |
4248 | /* There are a lot of optimizations we could do that we don't. | |
4249 | In particular, we do not, in general, reorder instructions. | |
4250 | If you use gcc with optimization, it will reorder | |
4251 | instructions and generally do much more optimization then we | |
4252 | do here; repeating all that work in the assembler would only | |
4253 | benefit hand written assembly code, and does not seem worth | |
4254 | it. */ | |
4255 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4256 | ? nops_for_insn (0, history, NULL) |
4257 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4258 | if (nops > 0) |
252b5132 RH |
4259 | { |
4260 | fragS *old_frag; | |
4261 | unsigned long old_frag_offset; | |
4262 | int i; | |
252b5132 RH |
4263 | |
4264 | old_frag = frag_now; | |
4265 | old_frag_offset = frag_now_fix (); | |
4266 | ||
4267 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4268 | add_fixed_insn (NOP_INSN); |
4269 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4270 | |
4271 | if (listing) | |
4272 | { | |
4273 | listing_prev_line (); | |
4274 | /* We may be at the start of a variant frag. In case we | |
4275 | are, make sure there is enough space for the frag | |
4276 | after the frags created by listing_prev_line. The | |
4277 | argument to frag_grow here must be at least as large | |
4278 | as the argument to all other calls to frag_grow in | |
4279 | this file. We don't have to worry about being in the | |
4280 | middle of a variant frag, because the variants insert | |
4281 | all needed nop instructions themselves. */ | |
4282 | frag_grow (40); | |
4283 | } | |
4284 | ||
462427c4 | 4285 | mips_move_text_labels (); |
252b5132 RH |
4286 | |
4287 | #ifndef NO_ECOFF_DEBUGGING | |
4288 | if (ECOFF_DEBUGGING) | |
4289 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4290 | #endif | |
4291 | } | |
71400594 RS |
4292 | } |
4293 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4294 | { | |
932d1a1b RS |
4295 | int nops; |
4296 | ||
4297 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4298 | ignoring hazards generated by the first prev_nop_frag_since | |
4299 | instructions. */ | |
4300 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4301 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4302 | |
71400594 RS |
4303 | /* Enforce NOPS as a minimum. */ |
4304 | if (nops > prev_nop_frag_required) | |
4305 | prev_nop_frag_required = nops; | |
252b5132 | 4306 | |
71400594 RS |
4307 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4308 | { | |
4309 | /* Settle for the current number of nops. Update the history | |
4310 | accordingly (for the benefit of any future .set reorder code). */ | |
4311 | prev_nop_frag = NULL; | |
4312 | insert_into_history (prev_nop_frag_since, | |
4313 | prev_nop_frag_holds, NOP_INSN); | |
4314 | } | |
4315 | else | |
4316 | { | |
4317 | /* Allow this instruction to replace one of the nops that was | |
4318 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4319 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4320 | prev_nop_frag_holds--; |
4321 | prev_nop_frag_since++; | |
252b5132 RH |
4322 | } |
4323 | } | |
4324 | ||
e407c74b | 4325 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4326 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4327 | |
58e2ea4d MR |
4328 | #ifdef OBJ_ELF |
4329 | /* The value passed to dwarf2_emit_insn is the distance between | |
4330 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4331 | should be recorded in the debug tables. This is normally the |
4332 | current address. | |
4333 | ||
df58fc94 RS |
4334 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4335 | addresses, so we use -1 for an address higher by one than the | |
4336 | current one. | |
e3a82c8e MR |
4337 | |
4338 | If the instruction produced is a branch that we will swap with | |
4339 | the preceding instruction, then we add the displacement by which | |
4340 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4341 | and for MIPS16/microMIPS code also prevents a debugger from |
4342 | placing a breakpoint in the middle of the branch (and corrupting | |
4343 | code if software breakpoints are used). */ | |
2b0c8b40 | 4344 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4345 | #endif |
4346 | ||
df58fc94 RS |
4347 | relax32 = (mips_relax_branch |
4348 | /* Don't try branch relaxation within .set nomacro, or within | |
4349 | .set noat if we use $at for PIC computations. If it turns | |
4350 | out that the branch was out-of-range, we'll get an error. */ | |
4351 | && !mips_opts.warn_about_macros | |
4352 | && (mips_opts.at || mips_pic == NO_PIC) | |
4353 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4354 | branches. */ | |
40209cad | 4355 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4356 | |
4357 | if (!HAVE_CODE_COMPRESSION | |
4358 | && address_expr | |
4359 | && relax32 | |
0b25d3e6 | 4360 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4361 | && delayed_branch_p (ip)) |
4a6a3df4 | 4362 | { |
895921c9 | 4363 | relaxed_branch = TRUE; |
1e915849 RS |
4364 | add_relaxed_insn (ip, (relaxed_branch_length |
4365 | (NULL, NULL, | |
11625dd8 RS |
4366 | uncond_branch_p (ip) ? -1 |
4367 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4368 | : 0)), 4, |
4369 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4370 | (AT, |
11625dd8 RS |
4371 | uncond_branch_p (ip), |
4372 | branch_likely_p (ip), | |
1e915849 RS |
4373 | pinfo & INSN_WRITE_GPR_31, |
4374 | 0), | |
4375 | address_expr->X_add_symbol, | |
4376 | address_expr->X_add_number); | |
4a6a3df4 AO |
4377 | *reloc_type = BFD_RELOC_UNUSED; |
4378 | } | |
df58fc94 RS |
4379 | else if (mips_opts.micromips |
4380 | && address_expr | |
4381 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4382 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4383 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4384 | /* Don't try branch relaxation when users specify | |
4385 | 16-bit/32-bit instructions. */ | |
4386 | && !forced_insn_length) | |
df58fc94 RS |
4387 | { |
4388 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4389 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4390 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4391 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4392 | int al = pinfo & INSN_WRITE_GPR_31; |
4393 | int length32; | |
4394 | ||
4395 | gas_assert (address_expr != NULL); | |
4396 | gas_assert (!mips_relax.sequence); | |
4397 | ||
2b0c8b40 | 4398 | relaxed_branch = TRUE; |
df58fc94 RS |
4399 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4400 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4401 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4402 | relax32, 0, 0), | |
df58fc94 RS |
4403 | address_expr->X_add_symbol, |
4404 | address_expr->X_add_number); | |
4405 | *reloc_type = BFD_RELOC_UNUSED; | |
4406 | } | |
4407 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4408 | { |
4409 | /* We need to set up a variant frag. */ | |
df58fc94 | 4410 | gas_assert (address_expr != NULL); |
1e915849 RS |
4411 | add_relaxed_insn (ip, 4, 0, |
4412 | RELAX_MIPS16_ENCODE | |
4413 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4414 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4415 | delayed_branch_p (&history[0]), |
1e915849 RS |
4416 | history[0].mips16_absolute_jump_p), |
4417 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4418 | } |
5c04167a | 4419 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4420 | { |
11625dd8 | 4421 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4422 | /* Make sure there is enough room to swap this instruction with |
4423 | a following jump instruction. */ | |
4424 | frag_grow (6); | |
1e915849 | 4425 | add_fixed_insn (ip); |
252b5132 RH |
4426 | } |
4427 | else | |
4428 | { | |
4429 | if (mips_opts.mips16 | |
4430 | && mips_opts.noreorder | |
11625dd8 | 4431 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4432 | as_warn (_("extended instruction in delay slot")); |
4433 | ||
4d7206a2 RS |
4434 | if (mips_relax.sequence) |
4435 | { | |
4436 | /* If we've reached the end of this frag, turn it into a variant | |
4437 | frag and record the information for the instructions we've | |
4438 | written so far. */ | |
4439 | if (frag_room () < 4) | |
4440 | relax_close_frag (); | |
df58fc94 | 4441 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4442 | } |
4443 | ||
584892a6 | 4444 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4445 | { |
4446 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4447 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4448 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4449 | mips_macro_warning.insns[0]++; | |
4450 | } | |
584892a6 | 4451 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4452 | { |
4453 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4454 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4455 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4456 | mips_macro_warning.insns[1]++; | |
4457 | } | |
584892a6 | 4458 | |
1e915849 RS |
4459 | if (mips_opts.mips16) |
4460 | { | |
4461 | ip->fixed_p = 1; | |
4462 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4463 | } | |
4464 | add_fixed_insn (ip); | |
252b5132 RH |
4465 | } |
4466 | ||
9fe77896 | 4467 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4468 | { |
df58fc94 | 4469 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4470 | reloc_howto_type *howto0; |
9fe77896 RS |
4471 | reloc_howto_type *howto; |
4472 | int i; | |
34ce925e | 4473 | |
df58fc94 RS |
4474 | /* Perform any necessary conversion to microMIPS relocations |
4475 | and find out how many relocations there actually are. */ | |
4476 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4477 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4478 | ||
9fe77896 RS |
4479 | /* In a compound relocation, it is the final (outermost) |
4480 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4481 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4482 | ||
9fe77896 RS |
4483 | if (howto == NULL) |
4484 | { | |
4485 | /* To reproduce this failure try assembling gas/testsuites/ | |
4486 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4487 | assembler. */ | |
df58fc94 RS |
4488 | as_bad (_("Unsupported MIPS relocation number %d"), |
4489 | final_type[i - 1]); | |
9fe77896 RS |
4490 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4491 | } | |
2309ddf2 MR |
4492 | |
4493 | if (i > 1) | |
4494 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4495 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4496 | bfd_get_reloc_size (howto), | |
4497 | address_expr, | |
2309ddf2 MR |
4498 | howto0 && howto0->pc_relative, |
4499 | final_type[0]); | |
9fe77896 RS |
4500 | |
4501 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4502 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4503 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4504 | ||
4505 | /* These relocations can have an addend that won't fit in | |
4506 | 4 octets for 64bit assembly. */ | |
4507 | if (HAVE_64BIT_GPRS | |
4508 | && ! howto->partial_inplace | |
4509 | && (reloc_type[0] == BFD_RELOC_16 | |
4510 | || reloc_type[0] == BFD_RELOC_32 | |
4511 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4512 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4513 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4514 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4515 | || reloc_type[0] == BFD_RELOC_64 | |
4516 | || reloc_type[0] == BFD_RELOC_CTOR | |
4517 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4518 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4519 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4520 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4521 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4522 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4523 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4524 | || hi16_reloc_p (reloc_type[0]) | |
4525 | || lo16_reloc_p (reloc_type[0]))) | |
4526 | ip->fixp[0]->fx_no_overflow = 1; | |
4527 | ||
ddaf2c41 MR |
4528 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4529 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4530 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4531 | ip->fixp[0]->fx_no_overflow = 1; | |
4532 | ||
9fe77896 RS |
4533 | if (mips_relax.sequence) |
4534 | { | |
4535 | if (mips_relax.first_fixup == 0) | |
4536 | mips_relax.first_fixup = ip->fixp[0]; | |
4537 | } | |
4538 | else if (reloc_needs_lo_p (*reloc_type)) | |
4539 | { | |
4540 | struct mips_hi_fixup *hi_fixup; | |
4541 | ||
4542 | /* Reuse the last entry if it already has a matching %lo. */ | |
4543 | hi_fixup = mips_hi_fixup_list; | |
4544 | if (hi_fixup == 0 | |
4545 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4546 | { |
9fe77896 RS |
4547 | hi_fixup = ((struct mips_hi_fixup *) |
4548 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4549 | hi_fixup->next = mips_hi_fixup_list; | |
4550 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4551 | } |
9fe77896 RS |
4552 | hi_fixup->fixp = ip->fixp[0]; |
4553 | hi_fixup->seg = now_seg; | |
4554 | } | |
252b5132 | 4555 | |
9fe77896 RS |
4556 | /* Add fixups for the second and third relocations, if given. |
4557 | Note that the ABI allows the second relocation to be | |
4558 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4559 | moment we only use RSS_UNDEF, but we could add support | |
4560 | for the others if it ever becomes necessary. */ | |
4561 | for (i = 1; i < 3; i++) | |
4562 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4563 | { | |
4564 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4565 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4566 | FALSE, final_type[i]); |
f6688943 | 4567 | |
9fe77896 RS |
4568 | /* Use fx_tcbit to mark compound relocs. */ |
4569 | ip->fixp[0]->fx_tcbit = 1; | |
4570 | ip->fixp[i]->fx_tcbit = 1; | |
4571 | } | |
252b5132 | 4572 | } |
1e915849 | 4573 | install_insn (ip); |
252b5132 RH |
4574 | |
4575 | /* Update the register mask information. */ | |
4c260379 RS |
4576 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4577 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4578 | |
a4e06468 | 4579 | switch (method) |
252b5132 | 4580 | { |
a4e06468 RS |
4581 | case APPEND_ADD: |
4582 | insert_into_history (0, 1, ip); | |
4583 | break; | |
4584 | ||
4585 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4586 | { |
4587 | struct mips_cl_insn *nop; | |
4588 | ||
4589 | insert_into_history (0, 1, ip); | |
4590 | nop = get_delay_slot_nop (ip); | |
4591 | add_fixed_insn (nop); | |
4592 | insert_into_history (0, 1, nop); | |
4593 | if (mips_relax.sequence) | |
4594 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4595 | } | |
a4e06468 RS |
4596 | break; |
4597 | ||
4598 | case APPEND_ADD_COMPACT: | |
4599 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4600 | gas_assert (mips_opts.mips16); | |
4601 | ip->insn_opcode |= 0x0080; | |
4602 | find_altered_mips16_opcode (ip); | |
4603 | install_insn (ip); | |
4604 | insert_into_history (0, 1, ip); | |
4605 | break; | |
4606 | ||
4607 | case APPEND_SWAP: | |
4608 | { | |
4609 | struct mips_cl_insn delay = history[0]; | |
4610 | if (mips_opts.mips16) | |
4611 | { | |
4612 | know (delay.frag == ip->frag); | |
4613 | move_insn (ip, delay.frag, delay.where); | |
4614 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4615 | } | |
464ab0e5 | 4616 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4617 | { |
4618 | /* Add the delay slot instruction to the end of the | |
4619 | current frag and shrink the fixed part of the | |
4620 | original frag. If the branch occupies the tail of | |
4621 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4622 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4623 | if (delay.frag == ip->frag) |
2b0c8b40 | 4624 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4625 | add_fixed_insn (&delay); |
4626 | } | |
4627 | else | |
4628 | { | |
2b0c8b40 MR |
4629 | move_insn (&delay, ip->frag, |
4630 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4631 | move_insn (ip, history[0].frag, history[0].where); |
4632 | } | |
4633 | history[0] = *ip; | |
4634 | delay.fixed_p = 1; | |
4635 | insert_into_history (0, 1, &delay); | |
4636 | } | |
4637 | break; | |
252b5132 RH |
4638 | } |
4639 | ||
13408f1e | 4640 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4641 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4642 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4643 | { |
4644 | unsigned int i; | |
4645 | ||
13408f1e RS |
4646 | mips_no_prev_insn (); |
4647 | ||
e407c74b NC |
4648 | for (i = 0; i < ARRAY_SIZE (history); i++) |
4649 | { | |
4650 | history[i].cleared_p = 1; | |
4651 | } | |
4652 | } | |
4653 | ||
df58fc94 RS |
4654 | /* We need to emit a label at the end of branch-likely macros. */ |
4655 | if (emit_branch_likely_macro) | |
4656 | { | |
4657 | emit_branch_likely_macro = FALSE; | |
4658 | micromips_add_label (); | |
4659 | } | |
4660 | ||
252b5132 RH |
4661 | /* We just output an insn, so the next one doesn't have a label. */ |
4662 | mips_clear_insn_labels (); | |
252b5132 RH |
4663 | } |
4664 | ||
e407c74b NC |
4665 | /* Forget that there was any previous instruction or label. |
4666 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4667 | |
4668 | static void | |
7d10b47d | 4669 | mips_no_prev_insn (void) |
252b5132 | 4670 | { |
7d10b47d RS |
4671 | prev_nop_frag = NULL; |
4672 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4673 | mips_clear_insn_labels (); |
4674 | } | |
4675 | ||
7d10b47d RS |
4676 | /* This function must be called before we emit something other than |
4677 | instructions. It is like mips_no_prev_insn except that it inserts | |
4678 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4679 | |
7d10b47d RS |
4680 | void |
4681 | mips_emit_delays (void) | |
252b5132 RH |
4682 | { |
4683 | if (! mips_opts.noreorder) | |
4684 | { | |
932d1a1b | 4685 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4686 | if (nops > 0) |
4687 | { | |
7d10b47d RS |
4688 | while (nops-- > 0) |
4689 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4690 | mips_move_text_labels (); |
7d10b47d RS |
4691 | } |
4692 | } | |
4693 | mips_no_prev_insn (); | |
4694 | } | |
4695 | ||
4696 | /* Start a (possibly nested) noreorder block. */ | |
4697 | ||
4698 | static void | |
4699 | start_noreorder (void) | |
4700 | { | |
4701 | if (mips_opts.noreorder == 0) | |
4702 | { | |
4703 | unsigned int i; | |
4704 | int nops; | |
4705 | ||
4706 | /* None of the instructions before the .set noreorder can be moved. */ | |
4707 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4708 | history[i].fixed_p = 1; | |
4709 | ||
4710 | /* Insert any nops that might be needed between the .set noreorder | |
4711 | block and the previous instructions. We will later remove any | |
4712 | nops that turn out not to be needed. */ | |
932d1a1b | 4713 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4714 | if (nops > 0) |
4715 | { | |
4716 | if (mips_optimize != 0) | |
252b5132 RH |
4717 | { |
4718 | /* Record the frag which holds the nop instructions, so | |
4719 | that we can remove them if we don't need them. */ | |
df58fc94 | 4720 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4721 | prev_nop_frag = frag_now; |
4722 | prev_nop_frag_holds = nops; | |
4723 | prev_nop_frag_required = 0; | |
4724 | prev_nop_frag_since = 0; | |
4725 | } | |
4726 | ||
4727 | for (; nops > 0; --nops) | |
1e915849 | 4728 | add_fixed_insn (NOP_INSN); |
252b5132 | 4729 | |
7d10b47d RS |
4730 | /* Move on to a new frag, so that it is safe to simply |
4731 | decrease the size of prev_nop_frag. */ | |
4732 | frag_wane (frag_now); | |
4733 | frag_new (0); | |
462427c4 | 4734 | mips_move_text_labels (); |
252b5132 | 4735 | } |
df58fc94 | 4736 | mips_mark_labels (); |
7d10b47d | 4737 | mips_clear_insn_labels (); |
252b5132 | 4738 | } |
7d10b47d RS |
4739 | mips_opts.noreorder++; |
4740 | mips_any_noreorder = 1; | |
4741 | } | |
252b5132 | 4742 | |
7d10b47d | 4743 | /* End a nested noreorder block. */ |
252b5132 | 4744 | |
7d10b47d RS |
4745 | static void |
4746 | end_noreorder (void) | |
4747 | { | |
4748 | mips_opts.noreorder--; | |
4749 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4750 | { | |
4751 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4752 | handling nop insertion the .set reorder way. */ | |
4753 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4754 | * NOP_INSN_SIZE); |
7d10b47d RS |
4755 | insert_into_history (prev_nop_frag_since, |
4756 | prev_nop_frag_required, NOP_INSN); | |
4757 | prev_nop_frag = NULL; | |
4758 | } | |
252b5132 RH |
4759 | } |
4760 | ||
584892a6 RS |
4761 | /* Set up global variables for the start of a new macro. */ |
4762 | ||
4763 | static void | |
4764 | macro_start (void) | |
4765 | { | |
4766 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4767 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4768 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4769 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4770 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4771 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4772 | switch (history[0].insn_mo->pinfo2 |
4773 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4774 | { | |
4775 | case INSN2_BRANCH_DELAY_32BIT: | |
4776 | mips_macro_warning.delay_slot_length = 4; | |
4777 | break; | |
4778 | case INSN2_BRANCH_DELAY_16BIT: | |
4779 | mips_macro_warning.delay_slot_length = 2; | |
4780 | break; | |
4781 | default: | |
4782 | mips_macro_warning.delay_slot_length = 0; | |
4783 | break; | |
4784 | } | |
4785 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4786 | } |
4787 | ||
df58fc94 RS |
4788 | /* Given that a macro is longer than one instruction or of the wrong size, |
4789 | return the appropriate warning for it. Return null if no warning is | |
4790 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4791 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4792 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4793 | |
4794 | static const char * | |
4795 | macro_warning (relax_substateT subtype) | |
4796 | { | |
4797 | if (subtype & RELAX_DELAY_SLOT) | |
4798 | return _("Macro instruction expanded into multiple instructions" | |
4799 | " in a branch delay slot"); | |
4800 | else if (subtype & RELAX_NOMACRO) | |
4801 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4802 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4803 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4804 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4805 | ? _("Macro instruction expanded into a wrong size instruction" | |
4806 | " in a 16-bit branch delay slot") | |
4807 | : _("Macro instruction expanded into a wrong size instruction" | |
4808 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4809 | else |
4810 | return 0; | |
4811 | } | |
4812 | ||
4813 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4814 | ||
4815 | static void | |
4816 | macro_end (void) | |
4817 | { | |
df58fc94 RS |
4818 | /* Relaxation warning flags. */ |
4819 | relax_substateT subtype = 0; | |
4820 | ||
4821 | /* Check delay slot size requirements. */ | |
4822 | if (mips_macro_warning.delay_slot_length == 2) | |
4823 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4824 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4825 | { |
df58fc94 RS |
4826 | if (mips_macro_warning.delay_slot_length |
4827 | != mips_macro_warning.first_insn_sizes[0]) | |
4828 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4829 | if (mips_macro_warning.delay_slot_length | |
4830 | != mips_macro_warning.first_insn_sizes[1]) | |
4831 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4832 | } | |
584892a6 | 4833 | |
df58fc94 RS |
4834 | /* Check instruction count requirements. */ |
4835 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4836 | { | |
4837 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4838 | subtype |= RELAX_SECOND_LONGER; |
4839 | if (mips_opts.warn_about_macros) | |
4840 | subtype |= RELAX_NOMACRO; | |
4841 | if (mips_macro_warning.delay_slot_p) | |
4842 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4843 | } |
584892a6 | 4844 | |
df58fc94 RS |
4845 | /* If both alternatives fail to fill a delay slot correctly, |
4846 | emit the warning now. */ | |
4847 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4848 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4849 | { | |
4850 | relax_substateT s; | |
4851 | const char *msg; | |
4852 | ||
4853 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4854 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4855 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4856 | msg = macro_warning (s); | |
4857 | if (msg != NULL) | |
4858 | as_warn ("%s", msg); | |
4859 | subtype &= ~s; | |
4860 | } | |
4861 | ||
4862 | /* If both implementations are longer than 1 instruction, then emit the | |
4863 | warning now. */ | |
4864 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4865 | { | |
4866 | relax_substateT s; | |
4867 | const char *msg; | |
4868 | ||
4869 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4870 | msg = macro_warning (s); | |
4871 | if (msg != NULL) | |
4872 | as_warn ("%s", msg); | |
4873 | subtype &= ~s; | |
584892a6 | 4874 | } |
df58fc94 RS |
4875 | |
4876 | /* If any flags still set, then one implementation might need a warning | |
4877 | and the other either will need one of a different kind or none at all. | |
4878 | Pass any remaining flags over to relaxation. */ | |
4879 | if (mips_macro_warning.first_frag != NULL) | |
4880 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4881 | } |
4882 | ||
df58fc94 RS |
4883 | /* Instruction operand formats used in macros that vary between |
4884 | standard MIPS and microMIPS code. */ | |
4885 | ||
4886 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4887 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4888 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4889 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4890 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4891 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4892 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4893 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4894 | ||
4895 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4896 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4897 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4898 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4899 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4900 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4901 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4902 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4903 | ||
6e1304d8 RS |
4904 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4905 | The first argument in *ARGS will be either the code for a single | |
4906 | relocation or -1 followed by the three codes that make up a | |
4907 | composite relocation. */ | |
4908 | ||
4909 | static void | |
4910 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4911 | { | |
4912 | int i, next; | |
4913 | ||
4914 | next = va_arg (*args, int); | |
4915 | if (next >= 0) | |
4916 | r[0] = (bfd_reloc_code_real_type) next; | |
4917 | else | |
4918 | for (i = 0; i < 3; i++) | |
4919 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4920 | } | |
4921 | ||
252b5132 RH |
4922 | /* Build an instruction created by a macro expansion. This is passed |
4923 | a pointer to the count of instructions created so far, an | |
4924 | expression, the name of the instruction to build, an operand format | |
4925 | string, and corresponding arguments. */ | |
4926 | ||
252b5132 | 4927 | static void |
67c0d1eb | 4928 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4929 | { |
df58fc94 | 4930 | const struct mips_opcode *mo = NULL; |
f6688943 | 4931 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4932 | const struct mips_opcode *amo; |
4933 | struct hash_control *hash; | |
4934 | struct mips_cl_insn insn; | |
252b5132 | 4935 | va_list args; |
252b5132 | 4936 | |
252b5132 | 4937 | va_start (args, fmt); |
252b5132 | 4938 | |
252b5132 RH |
4939 | if (mips_opts.mips16) |
4940 | { | |
03ea81db | 4941 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4942 | va_end (args); |
4943 | return; | |
4944 | } | |
4945 | ||
f6688943 TS |
4946 | r[0] = BFD_RELOC_UNUSED; |
4947 | r[1] = BFD_RELOC_UNUSED; | |
4948 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4949 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4950 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4951 | gas_assert (amo); | |
4952 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4953 | |
df58fc94 | 4954 | do |
8b082fb1 TS |
4955 | { |
4956 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4957 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4958 | We try to match an instruction that fulfils the branch delay | |
4959 | slot instruction length requirement (if any) of the previous | |
4960 | instruction. While doing this we record the first instruction | |
4961 | seen that matches all the other conditions and use it anyway | |
4962 | if the requirement cannot be met; we will issue an appropriate | |
4963 | warning later on. */ | |
4964 | if (strcmp (fmt, amo->args) == 0 | |
4965 | && amo->pinfo != INSN_MACRO | |
4966 | && is_opcode_valid (amo) | |
4967 | && is_size_valid (amo)) | |
4968 | { | |
4969 | if (is_delay_slot_valid (amo)) | |
4970 | { | |
4971 | mo = amo; | |
4972 | break; | |
4973 | } | |
4974 | else if (!mo) | |
4975 | mo = amo; | |
4976 | } | |
8b082fb1 | 4977 | |
df58fc94 RS |
4978 | ++amo; |
4979 | gas_assert (amo->name); | |
252b5132 | 4980 | } |
df58fc94 | 4981 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4982 | |
df58fc94 | 4983 | gas_assert (mo); |
1e915849 | 4984 | create_insn (&insn, mo); |
252b5132 RH |
4985 | for (;;) |
4986 | { | |
4987 | switch (*fmt++) | |
4988 | { | |
4989 | case '\0': | |
4990 | break; | |
4991 | ||
4992 | case ',': | |
4993 | case '(': | |
4994 | case ')': | |
4995 | continue; | |
4996 | ||
5f74bc13 CD |
4997 | case '+': |
4998 | switch (*fmt++) | |
4999 | { | |
5000 | case 'A': | |
5001 | case 'E': | |
df58fc94 RS |
5002 | INSERT_OPERAND (mips_opts.micromips, |
5003 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5004 | continue; |
5005 | ||
5006 | case 'B': | |
5007 | case 'F': | |
5008 | /* Note that in the macro case, these arguments are already | |
5009 | in MSB form. (When handling the instruction in the | |
5010 | non-macro case, these arguments are sizes from which | |
5011 | MSB values must be calculated.) */ | |
df58fc94 RS |
5012 | INSERT_OPERAND (mips_opts.micromips, |
5013 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5014 | continue; |
5015 | ||
5016 | case 'C': | |
5017 | case 'G': | |
5018 | case 'H': | |
5019 | /* Note that in the macro case, these arguments are already | |
5020 | in MSBD form. (When handling the instruction in the | |
5021 | non-macro case, these arguments are sizes from which | |
5022 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5023 | INSERT_OPERAND (mips_opts.micromips, |
5024 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5025 | continue; |
5026 | ||
dd3cbb7e | 5027 | case 'Q': |
df58fc94 RS |
5028 | gas_assert (!mips_opts.micromips); |
5029 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5030 | continue; |
5031 | ||
5f74bc13 CD |
5032 | default: |
5033 | internalError (); | |
5034 | } | |
5035 | continue; | |
5036 | ||
8b082fb1 | 5037 | case '2': |
03f66e8a | 5038 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5039 | continue; |
5040 | ||
df58fc94 RS |
5041 | case 'n': |
5042 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5043 | case 't': |
5044 | case 'w': | |
5045 | case 'E': | |
df58fc94 | 5046 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5047 | continue; |
5048 | ||
5049 | case 'c': | |
df58fc94 RS |
5050 | gas_assert (!mips_opts.micromips); |
5051 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5052 | continue; |
5053 | ||
252b5132 | 5054 | case 'W': |
df58fc94 RS |
5055 | gas_assert (!mips_opts.micromips); |
5056 | case 'T': | |
5057 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5058 | continue; |
5059 | ||
252b5132 | 5060 | case 'G': |
df58fc94 RS |
5061 | if (mips_opts.micromips) |
5062 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5063 | else | |
5064 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5065 | continue; | |
5066 | ||
af7ee8bf | 5067 | case 'K': |
df58fc94 RS |
5068 | gas_assert (!mips_opts.micromips); |
5069 | case 'd': | |
5070 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5071 | continue; |
5072 | ||
4372b673 | 5073 | case 'U': |
df58fc94 | 5074 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5075 | { |
5076 | int tmp = va_arg (args, int); | |
5077 | ||
df58fc94 RS |
5078 | INSERT_OPERAND (0, RT, insn, tmp); |
5079 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5080 | } |
df58fc94 | 5081 | continue; |
4372b673 | 5082 | |
252b5132 RH |
5083 | case 'V': |
5084 | case 'S': | |
df58fc94 RS |
5085 | gas_assert (!mips_opts.micromips); |
5086 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5087 | continue; |
5088 | ||
5089 | case 'z': | |
5090 | continue; | |
5091 | ||
5092 | case '<': | |
df58fc94 RS |
5093 | INSERT_OPERAND (mips_opts.micromips, |
5094 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5095 | continue; |
5096 | ||
5097 | case 'D': | |
df58fc94 RS |
5098 | gas_assert (!mips_opts.micromips); |
5099 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5100 | continue; |
5101 | ||
5102 | case 'B': | |
df58fc94 RS |
5103 | gas_assert (!mips_opts.micromips); |
5104 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5105 | continue; |
5106 | ||
4372b673 | 5107 | case 'J': |
df58fc94 RS |
5108 | gas_assert (!mips_opts.micromips); |
5109 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5110 | continue; |
5111 | ||
252b5132 | 5112 | case 'q': |
df58fc94 RS |
5113 | gas_assert (!mips_opts.micromips); |
5114 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5115 | continue; |
5116 | ||
5117 | case 'b': | |
5118 | case 's': | |
5119 | case 'r': | |
5120 | case 'v': | |
df58fc94 | 5121 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5122 | continue; |
5123 | ||
5124 | case 'i': | |
5125 | case 'j': | |
6e1304d8 | 5126 | macro_read_relocs (&args, r); |
9c2799c2 | 5127 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5128 | || *r == BFD_RELOC_MIPS_HIGHER |
5129 | || *r == BFD_RELOC_HI16_S | |
5130 | || *r == BFD_RELOC_LO16 | |
5131 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5132 | continue; | |
5133 | ||
5134 | case 'o': | |
5135 | macro_read_relocs (&args, r); | |
252b5132 RH |
5136 | continue; |
5137 | ||
5138 | case 'u': | |
6e1304d8 | 5139 | macro_read_relocs (&args, r); |
9c2799c2 | 5140 | gas_assert (ep != NULL |
90ecf173 MR |
5141 | && (ep->X_op == O_constant |
5142 | || (ep->X_op == O_symbol | |
5143 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5144 | || *r == BFD_RELOC_HI16_S | |
5145 | || *r == BFD_RELOC_HI16 | |
5146 | || *r == BFD_RELOC_GPREL16 | |
5147 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5148 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5149 | continue; |
5150 | ||
5151 | case 'p': | |
9c2799c2 | 5152 | gas_assert (ep != NULL); |
bad36eac | 5153 | |
252b5132 RH |
5154 | /* |
5155 | * This allows macro() to pass an immediate expression for | |
5156 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5157 | * |
5158 | * We don't allow branch relaxation for these branches, as | |
5159 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5160 | */ |
5161 | if (ep->X_op == O_constant) | |
5162 | { | |
df58fc94 RS |
5163 | /* For microMIPS we always use relocations for branches. |
5164 | So we should not resolve immediate values. */ | |
5165 | gas_assert (!mips_opts.micromips); | |
5166 | ||
bad36eac DJ |
5167 | if ((ep->X_add_number & 3) != 0) |
5168 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5169 | (unsigned long) ep->X_add_number); | |
5170 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5171 | as_bad (_("branch address range overflow (0x%lx)"), | |
5172 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5173 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5174 | ep = NULL; | |
5175 | } | |
5176 | else | |
0b25d3e6 | 5177 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5178 | continue; |
5179 | ||
5180 | case 'a': | |
9c2799c2 | 5181 | gas_assert (ep != NULL); |
f6688943 | 5182 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5183 | continue; |
5184 | ||
5185 | case 'C': | |
df58fc94 RS |
5186 | gas_assert (!mips_opts.micromips); |
5187 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5188 | continue; |
5189 | ||
d43b4baf | 5190 | case 'k': |
df58fc94 RS |
5191 | INSERT_OPERAND (mips_opts.micromips, |
5192 | CACHE, insn, va_arg (args, unsigned long)); | |
5193 | continue; | |
5194 | ||
5195 | case '|': | |
5196 | gas_assert (mips_opts.micromips); | |
5197 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5198 | continue; | |
5199 | ||
5200 | case '.': | |
5201 | gas_assert (mips_opts.micromips); | |
5202 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5203 | continue; | |
5204 | ||
dec0624d MR |
5205 | case '\\': |
5206 | INSERT_OPERAND (mips_opts.micromips, | |
5207 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5208 | continue; | |
5209 | ||
df58fc94 | 5210 | case '~': |
dec0624d MR |
5211 | INSERT_OPERAND (mips_opts.micromips, |
5212 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5213 | continue; |
5214 | ||
5215 | case 'N': | |
5216 | gas_assert (mips_opts.micromips); | |
5217 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5218 | continue; | |
5219 | ||
5220 | case 'm': /* Opcode extension character. */ | |
5221 | gas_assert (mips_opts.micromips); | |
5222 | switch (*fmt++) | |
5223 | { | |
5224 | case 'j': | |
5225 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5226 | break; | |
5227 | ||
5228 | case 'p': | |
5229 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5230 | break; | |
5231 | ||
5232 | case 'F': | |
5233 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5234 | break; | |
5235 | ||
5236 | default: | |
5237 | internalError (); | |
5238 | } | |
d43b4baf TS |
5239 | continue; |
5240 | ||
252b5132 RH |
5241 | default: |
5242 | internalError (); | |
5243 | } | |
5244 | break; | |
5245 | } | |
5246 | va_end (args); | |
9c2799c2 | 5247 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5248 | |
df58fc94 | 5249 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5250 | } |
5251 | ||
5252 | static void | |
67c0d1eb | 5253 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5254 | va_list *args) |
252b5132 | 5255 | { |
1e915849 | 5256 | struct mips_opcode *mo; |
252b5132 | 5257 | struct mips_cl_insn insn; |
f6688943 TS |
5258 | bfd_reloc_code_real_type r[3] |
5259 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5260 | |
1e915849 | 5261 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5262 | gas_assert (mo); |
5263 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5264 | |
1e915849 | 5265 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5266 | { |
1e915849 | 5267 | ++mo; |
9c2799c2 NC |
5268 | gas_assert (mo->name); |
5269 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5270 | } |
5271 | ||
1e915849 | 5272 | create_insn (&insn, mo); |
252b5132 RH |
5273 | for (;;) |
5274 | { | |
5275 | int c; | |
5276 | ||
5277 | c = *fmt++; | |
5278 | switch (c) | |
5279 | { | |
5280 | case '\0': | |
5281 | break; | |
5282 | ||
5283 | case ',': | |
5284 | case '(': | |
5285 | case ')': | |
5286 | continue; | |
5287 | ||
5288 | case 'y': | |
5289 | case 'w': | |
03ea81db | 5290 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5291 | continue; |
5292 | ||
5293 | case 'x': | |
5294 | case 'v': | |
03ea81db | 5295 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5296 | continue; |
5297 | ||
5298 | case 'z': | |
03ea81db | 5299 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5300 | continue; |
5301 | ||
5302 | case 'Z': | |
03ea81db | 5303 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5304 | continue; |
5305 | ||
5306 | case '0': | |
5307 | case 'S': | |
5308 | case 'P': | |
5309 | case 'R': | |
5310 | continue; | |
5311 | ||
5312 | case 'X': | |
03ea81db | 5313 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5314 | continue; |
5315 | ||
5316 | case 'Y': | |
5317 | { | |
5318 | int regno; | |
5319 | ||
03ea81db | 5320 | regno = va_arg (*args, int); |
252b5132 | 5321 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5322 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5323 | } |
5324 | continue; | |
5325 | ||
5326 | case '<': | |
5327 | case '>': | |
5328 | case '4': | |
5329 | case '5': | |
5330 | case 'H': | |
5331 | case 'W': | |
5332 | case 'D': | |
5333 | case 'j': | |
5334 | case '8': | |
5335 | case 'V': | |
5336 | case 'C': | |
5337 | case 'U': | |
5338 | case 'k': | |
5339 | case 'K': | |
5340 | case 'p': | |
5341 | case 'q': | |
5342 | { | |
b886a2ab RS |
5343 | offsetT value; |
5344 | ||
9c2799c2 | 5345 | gas_assert (ep != NULL); |
252b5132 RH |
5346 | |
5347 | if (ep->X_op != O_constant) | |
874e8986 | 5348 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5349 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5350 | { |
b886a2ab | 5351 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5352 | ep = NULL; |
f6688943 | 5353 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5354 | } |
5355 | } | |
5356 | continue; | |
5357 | ||
5358 | case '6': | |
03ea81db | 5359 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5360 | continue; |
5361 | } | |
5362 | ||
5363 | break; | |
5364 | } | |
5365 | ||
9c2799c2 | 5366 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5367 | |
df58fc94 | 5368 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5369 | } |
5370 | ||
2051e8c4 MR |
5371 | /* |
5372 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5373 | * higher bits unset. | |
5374 | */ | |
9f872bbe | 5375 | static void |
2051e8c4 MR |
5376 | normalize_constant_expr (expressionS *ex) |
5377 | { | |
9ee2a2d4 | 5378 | if (ex->X_op == O_constant |
2051e8c4 MR |
5379 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5380 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5381 | - 0x80000000); | |
5382 | } | |
5383 | ||
5384 | /* | |
5385 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5386 | * all higher bits unset. | |
5387 | */ | |
5388 | static void | |
5389 | normalize_address_expr (expressionS *ex) | |
5390 | { | |
5391 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5392 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5393 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5394 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5395 | - 0x80000000); | |
5396 | } | |
5397 | ||
438c16b8 TS |
5398 | /* |
5399 | * Generate a "jalr" instruction with a relocation hint to the called | |
5400 | * function. This occurs in NewABI PIC code. | |
5401 | */ | |
5402 | static void | |
df58fc94 | 5403 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5404 | { |
df58fc94 RS |
5405 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5406 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5407 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5408 | const char *jalr; | |
685736be | 5409 | char *f = NULL; |
b34976b6 | 5410 | |
1180b5a4 | 5411 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5412 | { |
cc3d92a5 | 5413 | frag_grow (8); |
f21f8242 AO |
5414 | f = frag_more (0); |
5415 | } | |
2906b037 | 5416 | if (mips_opts.micromips) |
df58fc94 RS |
5417 | { |
5418 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5419 | if (MIPS_JALR_HINT_P (ep) |
5420 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5421 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5422 | else | |
5423 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5424 | } | |
2906b037 MR |
5425 | else |
5426 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5427 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5428 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5429 | } |
5430 | ||
252b5132 RH |
5431 | /* |
5432 | * Generate a "lui" instruction. | |
5433 | */ | |
5434 | static void | |
67c0d1eb | 5435 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5436 | { |
9c2799c2 | 5437 | gas_assert (! mips_opts.mips16); |
252b5132 | 5438 | |
df58fc94 | 5439 | if (ep->X_op != O_constant) |
252b5132 | 5440 | { |
9c2799c2 | 5441 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5442 | /* _gp_disp is a special case, used from s_cpload. |
5443 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5444 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5445 | || (! HAVE_NEWABI |
aa6975fb ILT |
5446 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5447 | || (! mips_in_shared | |
bbe506e8 TS |
5448 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5449 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5450 | } |
5451 | ||
df58fc94 | 5452 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5453 | } |
5454 | ||
885add95 CD |
5455 | /* Generate a sequence of instructions to do a load or store from a constant |
5456 | offset off of a base register (breg) into/from a target register (treg), | |
5457 | using AT if necessary. */ | |
5458 | static void | |
67c0d1eb RS |
5459 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5460 | int treg, int breg, int dbl) | |
885add95 | 5461 | { |
9c2799c2 | 5462 | gas_assert (ep->X_op == O_constant); |
885add95 | 5463 | |
256ab948 | 5464 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5465 | if (!dbl) |
5466 | normalize_constant_expr (ep); | |
256ab948 | 5467 | |
67c1ffbe | 5468 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5469 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5470 | as_warn (_("operand overflow")); |
5471 | ||
5472 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5473 | { | |
5474 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5475 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5476 | } |
5477 | else | |
5478 | { | |
5479 | /* 32-bit offset, need multiple instructions and AT, like: | |
5480 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5481 | addu $tempreg,$tempreg,$breg | |
5482 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5483 | to handle the complete offset. */ | |
67c0d1eb RS |
5484 | macro_build_lui (ep, AT); |
5485 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5486 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5487 | |
741fe287 | 5488 | if (!mips_opts.at) |
8fc2e39e | 5489 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5490 | } |
5491 | } | |
5492 | ||
252b5132 RH |
5493 | /* set_at() |
5494 | * Generates code to set the $at register to true (one) | |
5495 | * if reg is less than the immediate expression. | |
5496 | */ | |
5497 | static void | |
67c0d1eb | 5498 | set_at (int reg, int unsignedp) |
252b5132 RH |
5499 | { |
5500 | if (imm_expr.X_op == O_constant | |
5501 | && imm_expr.X_add_number >= -0x8000 | |
5502 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5503 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5504 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5505 | else |
5506 | { | |
67c0d1eb RS |
5507 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5508 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5509 | } |
5510 | } | |
5511 | ||
5512 | /* Warn if an expression is not a constant. */ | |
5513 | ||
5514 | static void | |
17a2f251 | 5515 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5516 | { |
5517 | if (ex->X_op == O_big) | |
5518 | as_bad (_("unsupported large constant")); | |
5519 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5520 | as_bad (_("Instruction %s requires absolute expression"), |
5521 | ip->insn_mo->name); | |
13757d0c | 5522 | |
9ee2a2d4 MR |
5523 | if (HAVE_32BIT_GPRS) |
5524 | normalize_constant_expr (ex); | |
252b5132 RH |
5525 | } |
5526 | ||
5527 | /* Count the leading zeroes by performing a binary chop. This is a | |
5528 | bulky bit of source, but performance is a LOT better for the | |
5529 | majority of values than a simple loop to count the bits: | |
5530 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5531 | if ((v) & (1 << (31 - lcnt))) | |
5532 | break; | |
5533 | However it is not code size friendly, and the gain will drop a bit | |
5534 | on certain cached systems. | |
5535 | */ | |
5536 | #define COUNT_TOP_ZEROES(v) \ | |
5537 | (((v) & ~0xffff) == 0 \ | |
5538 | ? ((v) & ~0xff) == 0 \ | |
5539 | ? ((v) & ~0xf) == 0 \ | |
5540 | ? ((v) & ~0x3) == 0 \ | |
5541 | ? ((v) & ~0x1) == 0 \ | |
5542 | ? !(v) \ | |
5543 | ? 32 \ | |
5544 | : 31 \ | |
5545 | : 30 \ | |
5546 | : ((v) & ~0x7) == 0 \ | |
5547 | ? 29 \ | |
5548 | : 28 \ | |
5549 | : ((v) & ~0x3f) == 0 \ | |
5550 | ? ((v) & ~0x1f) == 0 \ | |
5551 | ? 27 \ | |
5552 | : 26 \ | |
5553 | : ((v) & ~0x7f) == 0 \ | |
5554 | ? 25 \ | |
5555 | : 24 \ | |
5556 | : ((v) & ~0xfff) == 0 \ | |
5557 | ? ((v) & ~0x3ff) == 0 \ | |
5558 | ? ((v) & ~0x1ff) == 0 \ | |
5559 | ? 23 \ | |
5560 | : 22 \ | |
5561 | : ((v) & ~0x7ff) == 0 \ | |
5562 | ? 21 \ | |
5563 | : 20 \ | |
5564 | : ((v) & ~0x3fff) == 0 \ | |
5565 | ? ((v) & ~0x1fff) == 0 \ | |
5566 | ? 19 \ | |
5567 | : 18 \ | |
5568 | : ((v) & ~0x7fff) == 0 \ | |
5569 | ? 17 \ | |
5570 | : 16 \ | |
5571 | : ((v) & ~0xffffff) == 0 \ | |
5572 | ? ((v) & ~0xfffff) == 0 \ | |
5573 | ? ((v) & ~0x3ffff) == 0 \ | |
5574 | ? ((v) & ~0x1ffff) == 0 \ | |
5575 | ? 15 \ | |
5576 | : 14 \ | |
5577 | : ((v) & ~0x7ffff) == 0 \ | |
5578 | ? 13 \ | |
5579 | : 12 \ | |
5580 | : ((v) & ~0x3fffff) == 0 \ | |
5581 | ? ((v) & ~0x1fffff) == 0 \ | |
5582 | ? 11 \ | |
5583 | : 10 \ | |
5584 | : ((v) & ~0x7fffff) == 0 \ | |
5585 | ? 9 \ | |
5586 | : 8 \ | |
5587 | : ((v) & ~0xfffffff) == 0 \ | |
5588 | ? ((v) & ~0x3ffffff) == 0 \ | |
5589 | ? ((v) & ~0x1ffffff) == 0 \ | |
5590 | ? 7 \ | |
5591 | : 6 \ | |
5592 | : ((v) & ~0x7ffffff) == 0 \ | |
5593 | ? 5 \ | |
5594 | : 4 \ | |
5595 | : ((v) & ~0x3fffffff) == 0 \ | |
5596 | ? ((v) & ~0x1fffffff) == 0 \ | |
5597 | ? 3 \ | |
5598 | : 2 \ | |
5599 | : ((v) & ~0x7fffffff) == 0 \ | |
5600 | ? 1 \ | |
5601 | : 0) | |
5602 | ||
5603 | /* load_register() | |
67c1ffbe | 5604 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5605 | * an absolute expression value into a register. |
5606 | */ | |
5607 | static void | |
67c0d1eb | 5608 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5609 | { |
5610 | int freg; | |
5611 | expressionS hi32, lo32; | |
5612 | ||
5613 | if (ep->X_op != O_big) | |
5614 | { | |
9c2799c2 | 5615 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5616 | |
5617 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5618 | if (!dbl) |
5619 | normalize_constant_expr (ep); | |
256ab948 TS |
5620 | |
5621 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5622 | { |
5623 | /* We can handle 16 bit signed values with an addiu to | |
5624 | $zero. No need to ever use daddiu here, since $zero and | |
5625 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5626 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5627 | return; |
5628 | } | |
5629 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5630 | { | |
5631 | /* We can handle 16 bit unsigned values with an ori to | |
5632 | $zero. */ | |
67c0d1eb | 5633 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5634 | return; |
5635 | } | |
256ab948 | 5636 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5637 | { |
5638 | /* 32 bit values require an lui. */ | |
df58fc94 | 5639 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5640 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5641 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5642 | return; |
5643 | } | |
5644 | } | |
5645 | ||
5646 | /* The value is larger than 32 bits. */ | |
5647 | ||
2051e8c4 | 5648 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5649 | { |
55e08f71 NC |
5650 | char value[32]; |
5651 | ||
5652 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5653 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5654 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5655 | return; |
5656 | } | |
5657 | ||
5658 | if (ep->X_op != O_big) | |
5659 | { | |
5660 | hi32 = *ep; | |
5661 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5662 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5663 | hi32.X_add_number &= 0xffffffff; | |
5664 | lo32 = *ep; | |
5665 | lo32.X_add_number &= 0xffffffff; | |
5666 | } | |
5667 | else | |
5668 | { | |
9c2799c2 | 5669 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5670 | if (ep->X_add_number == 3) |
5671 | generic_bignum[3] = 0; | |
5672 | else if (ep->X_add_number > 4) | |
5673 | as_bad (_("Number larger than 64 bits")); | |
5674 | lo32.X_op = O_constant; | |
5675 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5676 | hi32.X_op = O_constant; | |
5677 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5678 | } | |
5679 | ||
5680 | if (hi32.X_add_number == 0) | |
5681 | freg = 0; | |
5682 | else | |
5683 | { | |
5684 | int shift, bit; | |
5685 | unsigned long hi, lo; | |
5686 | ||
956cd1d6 | 5687 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5688 | { |
5689 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5690 | { | |
67c0d1eb | 5691 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5692 | return; |
5693 | } | |
5694 | if (lo32.X_add_number & 0x80000000) | |
5695 | { | |
df58fc94 | 5696 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5697 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5698 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5699 | return; |
5700 | } | |
5701 | } | |
252b5132 RH |
5702 | |
5703 | /* Check for 16bit shifted constant. We know that hi32 is | |
5704 | non-zero, so start the mask on the first bit of the hi32 | |
5705 | value. */ | |
5706 | shift = 17; | |
5707 | do | |
beae10d5 KH |
5708 | { |
5709 | unsigned long himask, lomask; | |
5710 | ||
5711 | if (shift < 32) | |
5712 | { | |
5713 | himask = 0xffff >> (32 - shift); | |
5714 | lomask = (0xffff << shift) & 0xffffffff; | |
5715 | } | |
5716 | else | |
5717 | { | |
5718 | himask = 0xffff << (shift - 32); | |
5719 | lomask = 0; | |
5720 | } | |
5721 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5722 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5723 | { | |
5724 | expressionS tmp; | |
5725 | ||
5726 | tmp.X_op = O_constant; | |
5727 | if (shift < 32) | |
5728 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5729 | | (lo32.X_add_number >> shift)); | |
5730 | else | |
5731 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5732 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5733 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5734 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5735 | return; |
5736 | } | |
f9419b05 | 5737 | ++shift; |
beae10d5 KH |
5738 | } |
5739 | while (shift <= (64 - 16)); | |
252b5132 RH |
5740 | |
5741 | /* Find the bit number of the lowest one bit, and store the | |
5742 | shifted value in hi/lo. */ | |
5743 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5744 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5745 | if (lo != 0) | |
5746 | { | |
5747 | bit = 0; | |
5748 | while ((lo & 1) == 0) | |
5749 | { | |
5750 | lo >>= 1; | |
5751 | ++bit; | |
5752 | } | |
5753 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5754 | hi >>= bit; | |
5755 | } | |
5756 | else | |
5757 | { | |
5758 | bit = 32; | |
5759 | while ((hi & 1) == 0) | |
5760 | { | |
5761 | hi >>= 1; | |
5762 | ++bit; | |
5763 | } | |
5764 | lo = hi; | |
5765 | hi = 0; | |
5766 | } | |
5767 | ||
5768 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5769 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5770 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5771 | { |
5772 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5773 | if (shift != 0) |
beae10d5 | 5774 | { |
252b5132 RH |
5775 | expressionS tmp; |
5776 | ||
5777 | /* This instruction will set the register to be all | |
5778 | ones. */ | |
beae10d5 KH |
5779 | tmp.X_op = O_constant; |
5780 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5781 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5782 | if (bit != 0) |
5783 | { | |
5784 | bit += shift; | |
df58fc94 | 5785 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5786 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5787 | } |
df58fc94 | 5788 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5789 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5790 | return; |
5791 | } | |
5792 | } | |
252b5132 RH |
5793 | |
5794 | /* Sign extend hi32 before calling load_register, because we can | |
5795 | generally get better code when we load a sign extended value. */ | |
5796 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5797 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5798 | load_register (reg, &hi32, 0); |
252b5132 RH |
5799 | freg = reg; |
5800 | } | |
5801 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5802 | { | |
5803 | if (freg != 0) | |
5804 | { | |
df58fc94 | 5805 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5806 | freg = reg; |
5807 | } | |
5808 | } | |
5809 | else | |
5810 | { | |
5811 | expressionS mid16; | |
5812 | ||
956cd1d6 | 5813 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5814 | { |
df58fc94 RS |
5815 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5816 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5817 | return; |
5818 | } | |
252b5132 RH |
5819 | |
5820 | if (freg != 0) | |
5821 | { | |
df58fc94 | 5822 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5823 | freg = reg; |
5824 | } | |
5825 | mid16 = lo32; | |
5826 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5827 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5828 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5829 | freg = reg; |
5830 | } | |
5831 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5832 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5833 | } |
5834 | ||
269137b2 TS |
5835 | static inline void |
5836 | load_delay_nop (void) | |
5837 | { | |
5838 | if (!gpr_interlocks) | |
5839 | macro_build (NULL, "nop", ""); | |
5840 | } | |
5841 | ||
252b5132 RH |
5842 | /* Load an address into a register. */ |
5843 | ||
5844 | static void | |
67c0d1eb | 5845 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5846 | { |
252b5132 RH |
5847 | if (ep->X_op != O_constant |
5848 | && ep->X_op != O_symbol) | |
5849 | { | |
5850 | as_bad (_("expression too complex")); | |
5851 | ep->X_op = O_constant; | |
5852 | } | |
5853 | ||
5854 | if (ep->X_op == O_constant) | |
5855 | { | |
67c0d1eb | 5856 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5857 | return; |
5858 | } | |
5859 | ||
5860 | if (mips_pic == NO_PIC) | |
5861 | { | |
5862 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5863 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5864 | Otherwise we want |
5865 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5866 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5867 | If we have an addend, we always use the latter form. |
76b3015f | 5868 | |
d6bc6245 TS |
5869 | With 64bit address space and a usable $at we want |
5870 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5871 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5872 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5873 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5874 | dsll32 $reg,0 | |
3a482fd5 | 5875 | daddu $reg,$reg,$at |
76b3015f | 5876 | |
c03099e6 | 5877 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5878 | on superscalar processors. |
5879 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5880 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5881 | dsll $reg,16 | |
5882 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5883 | dsll $reg,16 | |
5884 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5885 | |
5886 | For GP relative symbols in 64bit address space we can use | |
5887 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5888 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5889 | { |
6caf9ef4 TS |
5890 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5891 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5892 | { | |
5893 | relax_start (ep->X_add_symbol); | |
5894 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5895 | mips_gp_register, BFD_RELOC_GPREL16); | |
5896 | relax_switch (); | |
5897 | } | |
d6bc6245 | 5898 | |
741fe287 | 5899 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5900 | { |
df58fc94 RS |
5901 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5902 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5903 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5904 | BFD_RELOC_MIPS_HIGHER); | |
5905 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5906 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5907 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5908 | *used_at = 1; |
5909 | } | |
5910 | else | |
5911 | { | |
df58fc94 | 5912 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5913 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5914 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5915 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5916 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5917 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5918 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5919 | } |
6caf9ef4 TS |
5920 | |
5921 | if (mips_relax.sequence) | |
5922 | relax_end (); | |
d6bc6245 | 5923 | } |
252b5132 RH |
5924 | else |
5925 | { | |
d6bc6245 | 5926 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5927 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5928 | { |
4d7206a2 | 5929 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5930 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5931 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5932 | relax_switch (); |
d6bc6245 | 5933 | } |
67c0d1eb RS |
5934 | macro_build_lui (ep, reg); |
5935 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5936 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5937 | if (mips_relax.sequence) |
5938 | relax_end (); | |
d6bc6245 | 5939 | } |
252b5132 | 5940 | } |
0a44bf69 | 5941 | else if (!mips_big_got) |
252b5132 RH |
5942 | { |
5943 | expressionS ex; | |
5944 | ||
5945 | /* If this is a reference to an external symbol, we want | |
5946 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5947 | Otherwise we want | |
5948 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5949 | nop | |
5950 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5951 | If there is a constant, it must be added in after. |
5952 | ||
ed6fb7bd | 5953 | If we have NewABI, we want |
f5040a92 AO |
5954 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5955 | unless we're referencing a global symbol with a non-zero | |
5956 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5957 | if (HAVE_NEWABI) |
5958 | { | |
f5040a92 AO |
5959 | if (ep->X_add_number) |
5960 | { | |
4d7206a2 | 5961 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5962 | ep->X_add_number = 0; |
4d7206a2 | 5963 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5964 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5965 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5966 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5967 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5968 | ex.X_op = O_constant; | |
67c0d1eb | 5969 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5970 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5971 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5972 | relax_switch (); |
f5040a92 | 5973 | } |
67c0d1eb | 5974 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5975 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5976 | if (mips_relax.sequence) |
5977 | relax_end (); | |
ed6fb7bd SC |
5978 | } |
5979 | else | |
5980 | { | |
f5040a92 AO |
5981 | ex.X_add_number = ep->X_add_number; |
5982 | ep->X_add_number = 0; | |
67c0d1eb RS |
5983 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5984 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5985 | load_delay_nop (); |
4d7206a2 RS |
5986 | relax_start (ep->X_add_symbol); |
5987 | relax_switch (); | |
67c0d1eb | 5988 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5989 | BFD_RELOC_LO16); |
4d7206a2 | 5990 | relax_end (); |
ed6fb7bd | 5991 | |
f5040a92 AO |
5992 | if (ex.X_add_number != 0) |
5993 | { | |
5994 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5995 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5996 | ex.X_op = O_constant; | |
67c0d1eb | 5997 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5998 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5999 | } |
252b5132 RH |
6000 | } |
6001 | } | |
0a44bf69 | 6002 | else if (mips_big_got) |
252b5132 RH |
6003 | { |
6004 | expressionS ex; | |
252b5132 RH |
6005 | |
6006 | /* This is the large GOT case. If this is a reference to an | |
6007 | external symbol, we want | |
6008 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6009 | addu $reg,$reg,$gp | |
6010 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6011 | |
6012 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6013 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6014 | nop | |
6015 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6016 | If there is a constant, it must be added in after. |
f5040a92 AO |
6017 | |
6018 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6019 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6020 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6021 | */ |
438c16b8 TS |
6022 | if (HAVE_NEWABI) |
6023 | { | |
4d7206a2 | 6024 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6025 | ep->X_add_number = 0; |
4d7206a2 | 6026 | relax_start (ep->X_add_symbol); |
df58fc94 | 6027 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6028 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6029 | reg, reg, mips_gp_register); | |
6030 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6031 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6032 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6033 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6034 | else if (ex.X_add_number) | |
6035 | { | |
6036 | ex.X_op = O_constant; | |
67c0d1eb RS |
6037 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6038 | BFD_RELOC_LO16); | |
f5040a92 AO |
6039 | } |
6040 | ||
6041 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6042 | relax_switch (); |
67c0d1eb | 6043 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6044 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6045 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6046 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6047 | relax_end (); |
438c16b8 | 6048 | } |
252b5132 | 6049 | else |
438c16b8 | 6050 | { |
f5040a92 AO |
6051 | ex.X_add_number = ep->X_add_number; |
6052 | ep->X_add_number = 0; | |
4d7206a2 | 6053 | relax_start (ep->X_add_symbol); |
df58fc94 | 6054 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6056 | reg, reg, mips_gp_register); | |
6057 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6058 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6059 | relax_switch (); |
6060 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6061 | { |
6062 | /* We need a nop before loading from $gp. This special | |
6063 | check is required because the lui which starts the main | |
6064 | instruction stream does not refer to $gp, and so will not | |
6065 | insert the nop which may be required. */ | |
67c0d1eb | 6066 | macro_build (NULL, "nop", ""); |
438c16b8 | 6067 | } |
67c0d1eb | 6068 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6069 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6070 | load_delay_nop (); |
67c0d1eb | 6071 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6072 | BFD_RELOC_LO16); |
4d7206a2 | 6073 | relax_end (); |
438c16b8 | 6074 | |
f5040a92 AO |
6075 | if (ex.X_add_number != 0) |
6076 | { | |
6077 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6078 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6079 | ex.X_op = O_constant; | |
67c0d1eb RS |
6080 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6081 | BFD_RELOC_LO16); | |
f5040a92 | 6082 | } |
252b5132 RH |
6083 | } |
6084 | } | |
252b5132 RH |
6085 | else |
6086 | abort (); | |
8fc2e39e | 6087 | |
741fe287 | 6088 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6089 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6090 | } |
6091 | ||
ea1fb5dc RS |
6092 | /* Move the contents of register SOURCE into register DEST. */ |
6093 | ||
6094 | static void | |
67c0d1eb | 6095 | move_register (int dest, int source) |
ea1fb5dc | 6096 | { |
df58fc94 RS |
6097 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6098 | instruction specifically requires a 32-bit one. */ | |
6099 | if (mips_opts.micromips | |
6100 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6101 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6102 | else |
6103 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6104 | dest, source, 0); | |
ea1fb5dc RS |
6105 | } |
6106 | ||
4d7206a2 | 6107 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6108 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6109 | The two alternatives are: | |
4d7206a2 RS |
6110 | |
6111 | Global symbol Local sybmol | |
6112 | ------------- ------------ | |
6113 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6114 | ... ... | |
6115 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6116 | ||
6117 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6118 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6119 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6120 | |
6121 | static void | |
67c0d1eb | 6122 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6123 | { |
6124 | expressionS global; | |
6125 | ||
6126 | global = *local; | |
6127 | global.X_add_number = 0; | |
6128 | ||
6129 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6130 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6131 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6132 | relax_switch (); |
67c0d1eb RS |
6133 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6134 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6135 | relax_end (); |
6136 | } | |
6137 | ||
6138 | static void | |
67c0d1eb | 6139 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6140 | { |
6141 | expressionS global; | |
6142 | ||
6143 | global.X_op = O_constant; | |
6144 | global.X_op_symbol = NULL; | |
6145 | global.X_add_symbol = NULL; | |
6146 | global.X_add_number = local->X_add_number; | |
6147 | ||
6148 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6149 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6150 | dest, dest, BFD_RELOC_LO16); |
6151 | relax_switch (); | |
67c0d1eb | 6152 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6153 | relax_end (); |
6154 | } | |
6155 | ||
f6a22291 MR |
6156 | static void |
6157 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6158 | { | |
6159 | expressionS global; | |
6160 | int hold_mips_optimize; | |
6161 | ||
6162 | global.X_op = O_constant; | |
6163 | global.X_op_symbol = NULL; | |
6164 | global.X_add_symbol = NULL; | |
6165 | global.X_add_number = local->X_add_number; | |
6166 | ||
6167 | relax_start (local->X_add_symbol); | |
6168 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6169 | relax_switch (); | |
6170 | /* Set mips_optimize around the lui instruction to avoid | |
6171 | inserting an unnecessary nop after the lw. */ | |
6172 | hold_mips_optimize = mips_optimize; | |
6173 | mips_optimize = 2; | |
6174 | macro_build_lui (&global, tmp); | |
6175 | mips_optimize = hold_mips_optimize; | |
6176 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6177 | relax_end (); | |
6178 | ||
6179 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6180 | } | |
6181 | ||
df58fc94 RS |
6182 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6183 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6184 | is its complementing branch with the original condition negated. | |
6185 | CALL is set if the original branch specified the link operation. | |
6186 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6187 | ||
6188 | Code like this is produced in the noreorder mode: | |
6189 | ||
6190 | BRNEG <args>, 1f | |
6191 | nop | |
6192 | b <sym> | |
6193 | delay slot (executed only if branch taken) | |
6194 | 1: | |
6195 | ||
6196 | or, if CALL is set: | |
6197 | ||
6198 | BRNEG <args>, 1f | |
6199 | nop | |
6200 | bal <sym> | |
6201 | delay slot (executed only if branch taken) | |
6202 | 1: | |
6203 | ||
6204 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6205 | so code produced is simply: | |
6206 | ||
6207 | BR <args>, <sym> | |
6208 | nop | |
6209 | ||
6210 | This function is used when producing code for the microMIPS ASE that | |
6211 | does not implement branch likely instructions in hardware. */ | |
6212 | ||
6213 | static void | |
6214 | macro_build_branch_likely (const char *br, const char *brneg, | |
6215 | int call, expressionS *ep, const char *fmt, | |
6216 | unsigned int sreg, unsigned int treg) | |
6217 | { | |
6218 | int noreorder = mips_opts.noreorder; | |
6219 | expressionS expr1; | |
6220 | ||
6221 | gas_assert (mips_opts.micromips); | |
6222 | start_noreorder (); | |
6223 | if (noreorder) | |
6224 | { | |
6225 | micromips_label_expr (&expr1); | |
6226 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6227 | macro_build (NULL, "nop", ""); | |
6228 | macro_build (ep, call ? "bal" : "b", "p"); | |
6229 | ||
6230 | /* Set to true so that append_insn adds a label. */ | |
6231 | emit_branch_likely_macro = TRUE; | |
6232 | } | |
6233 | else | |
6234 | { | |
6235 | macro_build (ep, br, fmt, sreg, treg); | |
6236 | macro_build (NULL, "nop", ""); | |
6237 | } | |
6238 | end_noreorder (); | |
6239 | } | |
6240 | ||
6241 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6242 | the condition code tested. EP specifies the branch target. */ | |
6243 | ||
6244 | static void | |
6245 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6246 | { | |
6247 | const int call = 0; | |
6248 | const char *brneg; | |
6249 | const char *br; | |
6250 | ||
6251 | switch (type) | |
6252 | { | |
6253 | case M_BC1FL: | |
6254 | br = "bc1f"; | |
6255 | brneg = "bc1t"; | |
6256 | break; | |
6257 | case M_BC1TL: | |
6258 | br = "bc1t"; | |
6259 | brneg = "bc1f"; | |
6260 | break; | |
6261 | case M_BC2FL: | |
6262 | br = "bc2f"; | |
6263 | brneg = "bc2t"; | |
6264 | break; | |
6265 | case M_BC2TL: | |
6266 | br = "bc2t"; | |
6267 | brneg = "bc2f"; | |
6268 | break; | |
6269 | default: | |
6270 | abort (); | |
6271 | } | |
6272 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6273 | } | |
6274 | ||
6275 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6276 | the register tested. EP specifies the branch target. */ | |
6277 | ||
6278 | static void | |
6279 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6280 | { | |
6281 | const char *brneg = NULL; | |
6282 | const char *br; | |
6283 | int call = 0; | |
6284 | ||
6285 | switch (type) | |
6286 | { | |
6287 | case M_BGEZ: | |
6288 | br = "bgez"; | |
6289 | break; | |
6290 | case M_BGEZL: | |
6291 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6292 | brneg = "bltz"; | |
6293 | break; | |
6294 | case M_BGEZALL: | |
6295 | gas_assert (mips_opts.micromips); | |
6296 | br = "bgezals"; | |
6297 | brneg = "bltz"; | |
6298 | call = 1; | |
6299 | break; | |
6300 | case M_BGTZ: | |
6301 | br = "bgtz"; | |
6302 | break; | |
6303 | case M_BGTZL: | |
6304 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6305 | brneg = "blez"; | |
6306 | break; | |
6307 | case M_BLEZ: | |
6308 | br = "blez"; | |
6309 | break; | |
6310 | case M_BLEZL: | |
6311 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6312 | brneg = "bgtz"; | |
6313 | break; | |
6314 | case M_BLTZ: | |
6315 | br = "bltz"; | |
6316 | break; | |
6317 | case M_BLTZL: | |
6318 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6319 | brneg = "bgez"; | |
6320 | break; | |
6321 | case M_BLTZALL: | |
6322 | gas_assert (mips_opts.micromips); | |
6323 | br = "bltzals"; | |
6324 | brneg = "bgez"; | |
6325 | call = 1; | |
6326 | break; | |
6327 | default: | |
6328 | abort (); | |
6329 | } | |
6330 | if (mips_opts.micromips && brneg) | |
6331 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6332 | else | |
6333 | macro_build (ep, br, "s,p", sreg); | |
6334 | } | |
6335 | ||
6336 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6337 | TREG as the registers tested. EP specifies the branch target. */ | |
6338 | ||
6339 | static void | |
6340 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6341 | unsigned int sreg, unsigned int treg) | |
6342 | { | |
6343 | const char *brneg = NULL; | |
6344 | const int call = 0; | |
6345 | const char *br; | |
6346 | ||
6347 | switch (type) | |
6348 | { | |
6349 | case M_BEQ: | |
6350 | case M_BEQ_I: | |
6351 | br = "beq"; | |
6352 | break; | |
6353 | case M_BEQL: | |
6354 | case M_BEQL_I: | |
6355 | br = mips_opts.micromips ? "beq" : "beql"; | |
6356 | brneg = "bne"; | |
6357 | break; | |
6358 | case M_BNE: | |
6359 | case M_BNE_I: | |
6360 | br = "bne"; | |
6361 | break; | |
6362 | case M_BNEL: | |
6363 | case M_BNEL_I: | |
6364 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6365 | brneg = "beq"; | |
6366 | break; | |
6367 | default: | |
6368 | abort (); | |
6369 | } | |
6370 | if (mips_opts.micromips && brneg) | |
6371 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6372 | else | |
6373 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6374 | } | |
6375 | ||
252b5132 RH |
6376 | /* |
6377 | * Build macros | |
6378 | * This routine implements the seemingly endless macro or synthesized | |
6379 | * instructions and addressing modes in the mips assembly language. Many | |
6380 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6381 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6382 | * this verbose method. Others are not simple macros but are more like |
6383 | * optimizing code generation. | |
6384 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6385 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6386 | * The ensuing load upper instructions are ommited. This implies some kind |
6387 | * of global optimization. We currently only optimize within a single macro. | |
6388 | * For many of the load and store macros if the address is specified as a | |
6389 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6390 | * first load register 'at' with zero and use it as the base register. The | |
6391 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6392 | * we're missing. | |
6393 | */ | |
6394 | static void | |
17a2f251 | 6395 | macro (struct mips_cl_insn *ip) |
252b5132 | 6396 | { |
741fe287 MR |
6397 | unsigned int treg, sreg, dreg, breg; |
6398 | unsigned int tempreg; | |
252b5132 | 6399 | int mask; |
43841e91 | 6400 | int used_at = 0; |
df58fc94 | 6401 | expressionS label_expr; |
252b5132 | 6402 | expressionS expr1; |
df58fc94 | 6403 | expressionS *ep; |
252b5132 RH |
6404 | const char *s; |
6405 | const char *s2; | |
6406 | const char *fmt; | |
6407 | int likely = 0; | |
252b5132 | 6408 | int coproc = 0; |
df58fc94 | 6409 | int off12 = 0; |
1abe91b1 | 6410 | int call = 0; |
df58fc94 RS |
6411 | int jals = 0; |
6412 | int dbl = 0; | |
6413 | int imm = 0; | |
6414 | int ust = 0; | |
6415 | int lp = 0; | |
6416 | int ab = 0; | |
dd6a37e7 | 6417 | int off0 = 0; |
252b5132 | 6418 | int off; |
67c0d1eb | 6419 | offsetT maxnum; |
252b5132 | 6420 | bfd_reloc_code_real_type r; |
252b5132 RH |
6421 | int hold_mips_optimize; |
6422 | ||
9c2799c2 | 6423 | gas_assert (! mips_opts.mips16); |
252b5132 | 6424 | |
df58fc94 RS |
6425 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6426 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6427 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6428 | mask = ip->insn_mo->mask; |
6429 | ||
df58fc94 RS |
6430 | label_expr.X_op = O_constant; |
6431 | label_expr.X_op_symbol = NULL; | |
6432 | label_expr.X_add_symbol = NULL; | |
6433 | label_expr.X_add_number = 0; | |
6434 | ||
252b5132 RH |
6435 | expr1.X_op = O_constant; |
6436 | expr1.X_op_symbol = NULL; | |
6437 | expr1.X_add_symbol = NULL; | |
6438 | expr1.X_add_number = 1; | |
6439 | ||
6440 | switch (mask) | |
6441 | { | |
6442 | case M_DABS: | |
6443 | dbl = 1; | |
6444 | case M_ABS: | |
df58fc94 RS |
6445 | /* bgez $a0,1f |
6446 | move v0,$a0 | |
6447 | sub v0,$zero,$a0 | |
6448 | 1: | |
6449 | */ | |
252b5132 | 6450 | |
7d10b47d | 6451 | start_noreorder (); |
252b5132 | 6452 | |
df58fc94 RS |
6453 | if (mips_opts.micromips) |
6454 | micromips_label_expr (&label_expr); | |
6455 | else | |
6456 | label_expr.X_add_number = 8; | |
6457 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6458 | if (dreg == sreg) |
a605d2b3 | 6459 | macro_build (NULL, "nop", ""); |
252b5132 | 6460 | else |
67c0d1eb RS |
6461 | move_register (dreg, sreg); |
6462 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6463 | if (mips_opts.micromips) |
6464 | micromips_add_label (); | |
252b5132 | 6465 | |
7d10b47d | 6466 | end_noreorder (); |
8fc2e39e | 6467 | break; |
252b5132 RH |
6468 | |
6469 | case M_ADD_I: | |
6470 | s = "addi"; | |
6471 | s2 = "add"; | |
6472 | goto do_addi; | |
6473 | case M_ADDU_I: | |
6474 | s = "addiu"; | |
6475 | s2 = "addu"; | |
6476 | goto do_addi; | |
6477 | case M_DADD_I: | |
6478 | dbl = 1; | |
6479 | s = "daddi"; | |
6480 | s2 = "dadd"; | |
df58fc94 RS |
6481 | if (!mips_opts.micromips) |
6482 | goto do_addi; | |
6483 | if (imm_expr.X_op == O_constant | |
6484 | && imm_expr.X_add_number >= -0x200 | |
6485 | && imm_expr.X_add_number < 0x200) | |
6486 | { | |
6487 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6488 | break; | |
6489 | } | |
6490 | goto do_addi_i; | |
252b5132 RH |
6491 | case M_DADDU_I: |
6492 | dbl = 1; | |
6493 | s = "daddiu"; | |
6494 | s2 = "daddu"; | |
6495 | do_addi: | |
6496 | if (imm_expr.X_op == O_constant | |
6497 | && imm_expr.X_add_number >= -0x8000 | |
6498 | && imm_expr.X_add_number < 0x8000) | |
6499 | { | |
67c0d1eb | 6500 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6501 | break; |
252b5132 | 6502 | } |
df58fc94 | 6503 | do_addi_i: |
8fc2e39e | 6504 | used_at = 1; |
67c0d1eb RS |
6505 | load_register (AT, &imm_expr, dbl); |
6506 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6507 | break; |
6508 | ||
6509 | case M_AND_I: | |
6510 | s = "andi"; | |
6511 | s2 = "and"; | |
6512 | goto do_bit; | |
6513 | case M_OR_I: | |
6514 | s = "ori"; | |
6515 | s2 = "or"; | |
6516 | goto do_bit; | |
6517 | case M_NOR_I: | |
6518 | s = ""; | |
6519 | s2 = "nor"; | |
6520 | goto do_bit; | |
6521 | case M_XOR_I: | |
6522 | s = "xori"; | |
6523 | s2 = "xor"; | |
6524 | do_bit: | |
6525 | if (imm_expr.X_op == O_constant | |
6526 | && imm_expr.X_add_number >= 0 | |
6527 | && imm_expr.X_add_number < 0x10000) | |
6528 | { | |
6529 | if (mask != M_NOR_I) | |
67c0d1eb | 6530 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6531 | else |
6532 | { | |
67c0d1eb RS |
6533 | macro_build (&imm_expr, "ori", "t,r,i", |
6534 | treg, sreg, BFD_RELOC_LO16); | |
6535 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6536 | } |
8fc2e39e | 6537 | break; |
252b5132 RH |
6538 | } |
6539 | ||
8fc2e39e | 6540 | used_at = 1; |
67c0d1eb RS |
6541 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6542 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6543 | break; |
6544 | ||
8b082fb1 TS |
6545 | case M_BALIGN: |
6546 | switch (imm_expr.X_add_number) | |
6547 | { | |
6548 | case 0: | |
6549 | macro_build (NULL, "nop", ""); | |
6550 | break; | |
6551 | case 2: | |
6552 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6553 | break; | |
03f66e8a MR |
6554 | case 1: |
6555 | case 3: | |
8b082fb1 | 6556 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6557 | (int) imm_expr.X_add_number); |
8b082fb1 | 6558 | break; |
03f66e8a MR |
6559 | default: |
6560 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6561 | (unsigned long) imm_expr.X_add_number); | |
6562 | break; | |
8b082fb1 TS |
6563 | } |
6564 | break; | |
6565 | ||
df58fc94 RS |
6566 | case M_BC1FL: |
6567 | case M_BC1TL: | |
6568 | case M_BC2FL: | |
6569 | case M_BC2TL: | |
6570 | gas_assert (mips_opts.micromips); | |
6571 | macro_build_branch_ccl (mask, &offset_expr, | |
6572 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6573 | break; | |
6574 | ||
252b5132 | 6575 | case M_BEQ_I: |
252b5132 | 6576 | case M_BEQL_I: |
252b5132 | 6577 | case M_BNE_I: |
252b5132 | 6578 | case M_BNEL_I: |
252b5132 | 6579 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6580 | treg = 0; |
6581 | else | |
252b5132 | 6582 | { |
df58fc94 RS |
6583 | treg = AT; |
6584 | used_at = 1; | |
6585 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6586 | } |
df58fc94 RS |
6587 | /* Fall through. */ |
6588 | case M_BEQL: | |
6589 | case M_BNEL: | |
6590 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6591 | break; |
6592 | ||
6593 | case M_BGEL: | |
6594 | likely = 1; | |
6595 | case M_BGE: | |
6596 | if (treg == 0) | |
df58fc94 RS |
6597 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6598 | else if (sreg == 0) | |
6599 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6600 | else | |
252b5132 | 6601 | { |
df58fc94 RS |
6602 | used_at = 1; |
6603 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6604 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6605 | &offset_expr, AT, ZERO); | |
252b5132 | 6606 | } |
df58fc94 RS |
6607 | break; |
6608 | ||
6609 | case M_BGEZL: | |
6610 | case M_BGEZALL: | |
6611 | case M_BGTZL: | |
6612 | case M_BLEZL: | |
6613 | case M_BLTZL: | |
6614 | case M_BLTZALL: | |
6615 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6616 | break; |
6617 | ||
6618 | case M_BGTL_I: | |
6619 | likely = 1; | |
6620 | case M_BGT_I: | |
90ecf173 | 6621 | /* Check for > max integer. */ |
252b5132 | 6622 | maxnum = 0x7fffffff; |
ca4e0257 | 6623 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6624 | { |
6625 | maxnum <<= 16; | |
6626 | maxnum |= 0xffff; | |
6627 | maxnum <<= 16; | |
6628 | maxnum |= 0xffff; | |
6629 | } | |
6630 | if (imm_expr.X_op == O_constant | |
6631 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6632 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6633 | { |
6634 | do_false: | |
90ecf173 | 6635 | /* Result is always false. */ |
252b5132 | 6636 | if (! likely) |
a605d2b3 | 6637 | macro_build (NULL, "nop", ""); |
252b5132 | 6638 | else |
df58fc94 | 6639 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6640 | break; |
252b5132 RH |
6641 | } |
6642 | if (imm_expr.X_op != O_constant) | |
6643 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6644 | ++imm_expr.X_add_number; |
252b5132 RH |
6645 | /* FALLTHROUGH */ |
6646 | case M_BGE_I: | |
6647 | case M_BGEL_I: | |
6648 | if (mask == M_BGEL_I) | |
6649 | likely = 1; | |
6650 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6651 | { | |
df58fc94 RS |
6652 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6653 | &offset_expr, sreg); | |
8fc2e39e | 6654 | break; |
252b5132 RH |
6655 | } |
6656 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6657 | { | |
df58fc94 RS |
6658 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6659 | &offset_expr, sreg); | |
8fc2e39e | 6660 | break; |
252b5132 RH |
6661 | } |
6662 | maxnum = 0x7fffffff; | |
ca4e0257 | 6663 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6664 | { |
6665 | maxnum <<= 16; | |
6666 | maxnum |= 0xffff; | |
6667 | maxnum <<= 16; | |
6668 | maxnum |= 0xffff; | |
6669 | } | |
6670 | maxnum = - maxnum - 1; | |
6671 | if (imm_expr.X_op == O_constant | |
6672 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6673 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6674 | { |
6675 | do_true: | |
6676 | /* result is always true */ | |
6677 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6678 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6679 | break; |
252b5132 | 6680 | } |
8fc2e39e | 6681 | used_at = 1; |
67c0d1eb | 6682 | set_at (sreg, 0); |
df58fc94 RS |
6683 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6684 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6685 | break; |
6686 | ||
6687 | case M_BGEUL: | |
6688 | likely = 1; | |
6689 | case M_BGEU: | |
6690 | if (treg == 0) | |
6691 | goto do_true; | |
df58fc94 RS |
6692 | else if (sreg == 0) |
6693 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6694 | &offset_expr, ZERO, treg); | |
6695 | else | |
252b5132 | 6696 | { |
df58fc94 RS |
6697 | used_at = 1; |
6698 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6699 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6700 | &offset_expr, AT, ZERO); | |
252b5132 | 6701 | } |
252b5132 RH |
6702 | break; |
6703 | ||
6704 | case M_BGTUL_I: | |
6705 | likely = 1; | |
6706 | case M_BGTU_I: | |
6707 | if (sreg == 0 | |
ca4e0257 | 6708 | || (HAVE_32BIT_GPRS |
252b5132 | 6709 | && imm_expr.X_op == O_constant |
f01dc953 | 6710 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6711 | goto do_false; |
6712 | if (imm_expr.X_op != O_constant) | |
6713 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6714 | ++imm_expr.X_add_number; |
252b5132 RH |
6715 | /* FALLTHROUGH */ |
6716 | case M_BGEU_I: | |
6717 | case M_BGEUL_I: | |
6718 | if (mask == M_BGEUL_I) | |
6719 | likely = 1; | |
6720 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6721 | goto do_true; | |
df58fc94 RS |
6722 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6723 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6724 | &offset_expr, sreg, ZERO); | |
6725 | else | |
252b5132 | 6726 | { |
df58fc94 RS |
6727 | used_at = 1; |
6728 | set_at (sreg, 1); | |
6729 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6730 | &offset_expr, AT, ZERO); | |
252b5132 | 6731 | } |
252b5132 RH |
6732 | break; |
6733 | ||
6734 | case M_BGTL: | |
6735 | likely = 1; | |
6736 | case M_BGT: | |
6737 | if (treg == 0) | |
df58fc94 RS |
6738 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6739 | else if (sreg == 0) | |
6740 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6741 | else | |
252b5132 | 6742 | { |
df58fc94 RS |
6743 | used_at = 1; |
6744 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6745 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6746 | &offset_expr, AT, ZERO); | |
252b5132 | 6747 | } |
252b5132 RH |
6748 | break; |
6749 | ||
6750 | case M_BGTUL: | |
6751 | likely = 1; | |
6752 | case M_BGTU: | |
6753 | if (treg == 0) | |
df58fc94 RS |
6754 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6755 | &offset_expr, sreg, ZERO); | |
6756 | else if (sreg == 0) | |
6757 | goto do_false; | |
6758 | else | |
252b5132 | 6759 | { |
df58fc94 RS |
6760 | used_at = 1; |
6761 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6762 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6763 | &offset_expr, AT, ZERO); | |
252b5132 | 6764 | } |
252b5132 RH |
6765 | break; |
6766 | ||
6767 | case M_BLEL: | |
6768 | likely = 1; | |
6769 | case M_BLE: | |
6770 | if (treg == 0) | |
df58fc94 RS |
6771 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6772 | else if (sreg == 0) | |
6773 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6774 | else | |
252b5132 | 6775 | { |
df58fc94 RS |
6776 | used_at = 1; |
6777 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6778 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6779 | &offset_expr, AT, ZERO); | |
252b5132 | 6780 | } |
252b5132 RH |
6781 | break; |
6782 | ||
6783 | case M_BLEL_I: | |
6784 | likely = 1; | |
6785 | case M_BLE_I: | |
6786 | maxnum = 0x7fffffff; | |
ca4e0257 | 6787 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6788 | { |
6789 | maxnum <<= 16; | |
6790 | maxnum |= 0xffff; | |
6791 | maxnum <<= 16; | |
6792 | maxnum |= 0xffff; | |
6793 | } | |
6794 | if (imm_expr.X_op == O_constant | |
6795 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6796 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6797 | goto do_true; |
6798 | if (imm_expr.X_op != O_constant) | |
6799 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6800 | ++imm_expr.X_add_number; |
252b5132 RH |
6801 | /* FALLTHROUGH */ |
6802 | case M_BLT_I: | |
6803 | case M_BLTL_I: | |
6804 | if (mask == M_BLTL_I) | |
6805 | likely = 1; | |
6806 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6807 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6808 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6809 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6810 | else | |
252b5132 | 6811 | { |
df58fc94 RS |
6812 | used_at = 1; |
6813 | set_at (sreg, 0); | |
6814 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6815 | &offset_expr, AT, ZERO); | |
252b5132 | 6816 | } |
252b5132 RH |
6817 | break; |
6818 | ||
6819 | case M_BLEUL: | |
6820 | likely = 1; | |
6821 | case M_BLEU: | |
6822 | if (treg == 0) | |
df58fc94 RS |
6823 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6824 | &offset_expr, sreg, ZERO); | |
6825 | else if (sreg == 0) | |
6826 | goto do_true; | |
6827 | else | |
252b5132 | 6828 | { |
df58fc94 RS |
6829 | used_at = 1; |
6830 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6831 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6832 | &offset_expr, AT, ZERO); | |
252b5132 | 6833 | } |
252b5132 RH |
6834 | break; |
6835 | ||
6836 | case M_BLEUL_I: | |
6837 | likely = 1; | |
6838 | case M_BLEU_I: | |
6839 | if (sreg == 0 | |
ca4e0257 | 6840 | || (HAVE_32BIT_GPRS |
252b5132 | 6841 | && imm_expr.X_op == O_constant |
f01dc953 | 6842 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6843 | goto do_true; |
6844 | if (imm_expr.X_op != O_constant) | |
6845 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6846 | ++imm_expr.X_add_number; |
252b5132 RH |
6847 | /* FALLTHROUGH */ |
6848 | case M_BLTU_I: | |
6849 | case M_BLTUL_I: | |
6850 | if (mask == M_BLTUL_I) | |
6851 | likely = 1; | |
6852 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6853 | goto do_false; | |
df58fc94 RS |
6854 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6855 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6856 | &offset_expr, sreg, ZERO); | |
6857 | else | |
252b5132 | 6858 | { |
df58fc94 RS |
6859 | used_at = 1; |
6860 | set_at (sreg, 1); | |
6861 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6862 | &offset_expr, AT, ZERO); | |
252b5132 | 6863 | } |
252b5132 RH |
6864 | break; |
6865 | ||
6866 | case M_BLTL: | |
6867 | likely = 1; | |
6868 | case M_BLT: | |
6869 | if (treg == 0) | |
df58fc94 RS |
6870 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6871 | else if (sreg == 0) | |
6872 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6873 | else | |
252b5132 | 6874 | { |
df58fc94 RS |
6875 | used_at = 1; |
6876 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6877 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6878 | &offset_expr, AT, ZERO); | |
252b5132 | 6879 | } |
252b5132 RH |
6880 | break; |
6881 | ||
6882 | case M_BLTUL: | |
6883 | likely = 1; | |
6884 | case M_BLTU: | |
6885 | if (treg == 0) | |
6886 | goto do_false; | |
df58fc94 RS |
6887 | else if (sreg == 0) |
6888 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6889 | &offset_expr, ZERO, treg); | |
6890 | else | |
252b5132 | 6891 | { |
df58fc94 RS |
6892 | used_at = 1; |
6893 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6894 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6895 | &offset_expr, AT, ZERO); | |
252b5132 | 6896 | } |
252b5132 RH |
6897 | break; |
6898 | ||
5f74bc13 CD |
6899 | case M_DEXT: |
6900 | { | |
d5818fca MR |
6901 | /* Use unsigned arithmetic. */ |
6902 | addressT pos; | |
6903 | addressT size; | |
5f74bc13 | 6904 | |
90ecf173 | 6905 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6906 | { |
6907 | as_bad (_("Unsupported large constant")); | |
6908 | pos = size = 1; | |
6909 | } | |
6910 | else | |
6911 | { | |
d5818fca MR |
6912 | pos = imm_expr.X_add_number; |
6913 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6914 | } |
6915 | ||
6916 | if (pos > 63) | |
6917 | { | |
d5818fca | 6918 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6919 | pos = 1; |
6920 | } | |
90ecf173 | 6921 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6922 | { |
6923 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6924 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6925 | size = 1; |
6926 | } | |
6927 | ||
6928 | if (size <= 32 && pos < 32) | |
6929 | { | |
6930 | s = "dext"; | |
6931 | fmt = "t,r,+A,+C"; | |
6932 | } | |
6933 | else if (size <= 32) | |
6934 | { | |
6935 | s = "dextu"; | |
6936 | fmt = "t,r,+E,+H"; | |
6937 | } | |
6938 | else | |
6939 | { | |
6940 | s = "dextm"; | |
6941 | fmt = "t,r,+A,+G"; | |
6942 | } | |
d5818fca MR |
6943 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6944 | (int) (size - 1)); | |
5f74bc13 | 6945 | } |
8fc2e39e | 6946 | break; |
5f74bc13 CD |
6947 | |
6948 | case M_DINS: | |
6949 | { | |
d5818fca MR |
6950 | /* Use unsigned arithmetic. */ |
6951 | addressT pos; | |
6952 | addressT size; | |
5f74bc13 | 6953 | |
90ecf173 | 6954 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6955 | { |
6956 | as_bad (_("Unsupported large constant")); | |
6957 | pos = size = 1; | |
6958 | } | |
6959 | else | |
6960 | { | |
d5818fca MR |
6961 | pos = imm_expr.X_add_number; |
6962 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6963 | } |
6964 | ||
6965 | if (pos > 63) | |
6966 | { | |
d5818fca | 6967 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6968 | pos = 1; |
6969 | } | |
90ecf173 | 6970 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6971 | { |
6972 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6973 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6974 | size = 1; |
6975 | } | |
6976 | ||
6977 | if (pos < 32 && (pos + size - 1) < 32) | |
6978 | { | |
6979 | s = "dins"; | |
6980 | fmt = "t,r,+A,+B"; | |
6981 | } | |
6982 | else if (pos >= 32) | |
6983 | { | |
6984 | s = "dinsu"; | |
6985 | fmt = "t,r,+E,+F"; | |
6986 | } | |
6987 | else | |
6988 | { | |
6989 | s = "dinsm"; | |
6990 | fmt = "t,r,+A,+F"; | |
6991 | } | |
750bdd57 AS |
6992 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6993 | (int) (pos + size - 1)); | |
5f74bc13 | 6994 | } |
8fc2e39e | 6995 | break; |
5f74bc13 | 6996 | |
252b5132 RH |
6997 | case M_DDIV_3: |
6998 | dbl = 1; | |
6999 | case M_DIV_3: | |
7000 | s = "mflo"; | |
7001 | goto do_div3; | |
7002 | case M_DREM_3: | |
7003 | dbl = 1; | |
7004 | case M_REM_3: | |
7005 | s = "mfhi"; | |
7006 | do_div3: | |
7007 | if (treg == 0) | |
7008 | { | |
7009 | as_warn (_("Divide by zero.")); | |
7010 | if (mips_trap) | |
df58fc94 | 7011 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7012 | else |
df58fc94 | 7013 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7014 | break; |
252b5132 RH |
7015 | } |
7016 | ||
7d10b47d | 7017 | start_noreorder (); |
252b5132 RH |
7018 | if (mips_trap) |
7019 | { | |
df58fc94 | 7020 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7021 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7022 | } |
7023 | else | |
7024 | { | |
df58fc94 RS |
7025 | if (mips_opts.micromips) |
7026 | micromips_label_expr (&label_expr); | |
7027 | else | |
7028 | label_expr.X_add_number = 8; | |
7029 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7030 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7031 | macro_build (NULL, "break", BRK_FMT, 7); |
7032 | if (mips_opts.micromips) | |
7033 | micromips_add_label (); | |
252b5132 RH |
7034 | } |
7035 | expr1.X_add_number = -1; | |
8fc2e39e | 7036 | used_at = 1; |
f6a22291 | 7037 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7038 | if (mips_opts.micromips) |
7039 | micromips_label_expr (&label_expr); | |
7040 | else | |
7041 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7042 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7043 | if (dbl) |
7044 | { | |
7045 | expr1.X_add_number = 1; | |
f6a22291 | 7046 | load_register (AT, &expr1, dbl); |
df58fc94 | 7047 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7048 | } |
7049 | else | |
7050 | { | |
7051 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7052 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7053 | } |
7054 | if (mips_trap) | |
7055 | { | |
df58fc94 | 7056 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7057 | /* We want to close the noreorder block as soon as possible, so |
7058 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7059 | end_noreorder (); |
252b5132 RH |
7060 | } |
7061 | else | |
7062 | { | |
df58fc94 RS |
7063 | if (mips_opts.micromips) |
7064 | micromips_label_expr (&label_expr); | |
7065 | else | |
7066 | label_expr.X_add_number = 8; | |
7067 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7068 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7069 | |
7070 | /* We want to close the noreorder block as soon as possible, so | |
7071 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7072 | end_noreorder (); |
252b5132 | 7073 | |
df58fc94 | 7074 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7075 | } |
df58fc94 RS |
7076 | if (mips_opts.micromips) |
7077 | micromips_add_label (); | |
7078 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7079 | break; |
7080 | ||
7081 | case M_DIV_3I: | |
7082 | s = "div"; | |
7083 | s2 = "mflo"; | |
7084 | goto do_divi; | |
7085 | case M_DIVU_3I: | |
7086 | s = "divu"; | |
7087 | s2 = "mflo"; | |
7088 | goto do_divi; | |
7089 | case M_REM_3I: | |
7090 | s = "div"; | |
7091 | s2 = "mfhi"; | |
7092 | goto do_divi; | |
7093 | case M_REMU_3I: | |
7094 | s = "divu"; | |
7095 | s2 = "mfhi"; | |
7096 | goto do_divi; | |
7097 | case M_DDIV_3I: | |
7098 | dbl = 1; | |
7099 | s = "ddiv"; | |
7100 | s2 = "mflo"; | |
7101 | goto do_divi; | |
7102 | case M_DDIVU_3I: | |
7103 | dbl = 1; | |
7104 | s = "ddivu"; | |
7105 | s2 = "mflo"; | |
7106 | goto do_divi; | |
7107 | case M_DREM_3I: | |
7108 | dbl = 1; | |
7109 | s = "ddiv"; | |
7110 | s2 = "mfhi"; | |
7111 | goto do_divi; | |
7112 | case M_DREMU_3I: | |
7113 | dbl = 1; | |
7114 | s = "ddivu"; | |
7115 | s2 = "mfhi"; | |
7116 | do_divi: | |
7117 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7118 | { | |
7119 | as_warn (_("Divide by zero.")); | |
7120 | if (mips_trap) | |
df58fc94 | 7121 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7122 | else |
df58fc94 | 7123 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7124 | break; |
252b5132 RH |
7125 | } |
7126 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7127 | { | |
7128 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7129 | move_register (dreg, sreg); |
252b5132 | 7130 | else |
c80c840e | 7131 | move_register (dreg, ZERO); |
8fc2e39e | 7132 | break; |
252b5132 RH |
7133 | } |
7134 | if (imm_expr.X_op == O_constant | |
7135 | && imm_expr.X_add_number == -1 | |
7136 | && s[strlen (s) - 1] != 'u') | |
7137 | { | |
7138 | if (strcmp (s2, "mflo") == 0) | |
7139 | { | |
67c0d1eb | 7140 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7141 | } |
7142 | else | |
c80c840e | 7143 | move_register (dreg, ZERO); |
8fc2e39e | 7144 | break; |
252b5132 RH |
7145 | } |
7146 | ||
8fc2e39e | 7147 | used_at = 1; |
67c0d1eb RS |
7148 | load_register (AT, &imm_expr, dbl); |
7149 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7150 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7151 | break; |
7152 | ||
7153 | case M_DIVU_3: | |
7154 | s = "divu"; | |
7155 | s2 = "mflo"; | |
7156 | goto do_divu3; | |
7157 | case M_REMU_3: | |
7158 | s = "divu"; | |
7159 | s2 = "mfhi"; | |
7160 | goto do_divu3; | |
7161 | case M_DDIVU_3: | |
7162 | s = "ddivu"; | |
7163 | s2 = "mflo"; | |
7164 | goto do_divu3; | |
7165 | case M_DREMU_3: | |
7166 | s = "ddivu"; | |
7167 | s2 = "mfhi"; | |
7168 | do_divu3: | |
7d10b47d | 7169 | start_noreorder (); |
252b5132 RH |
7170 | if (mips_trap) |
7171 | { | |
df58fc94 | 7172 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7173 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7174 | /* We want to close the noreorder block as soon as possible, so |
7175 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7176 | end_noreorder (); |
252b5132 RH |
7177 | } |
7178 | else | |
7179 | { | |
df58fc94 RS |
7180 | if (mips_opts.micromips) |
7181 | micromips_label_expr (&label_expr); | |
7182 | else | |
7183 | label_expr.X_add_number = 8; | |
7184 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7185 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7186 | |
7187 | /* We want to close the noreorder block as soon as possible, so | |
7188 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7189 | end_noreorder (); |
df58fc94 RS |
7190 | macro_build (NULL, "break", BRK_FMT, 7); |
7191 | if (mips_opts.micromips) | |
7192 | micromips_add_label (); | |
252b5132 | 7193 | } |
df58fc94 | 7194 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7195 | break; |
252b5132 | 7196 | |
1abe91b1 MR |
7197 | case M_DLCA_AB: |
7198 | dbl = 1; | |
7199 | case M_LCA_AB: | |
7200 | call = 1; | |
7201 | goto do_la; | |
252b5132 RH |
7202 | case M_DLA_AB: |
7203 | dbl = 1; | |
7204 | case M_LA_AB: | |
1abe91b1 | 7205 | do_la: |
252b5132 RH |
7206 | /* Load the address of a symbol into a register. If breg is not |
7207 | zero, we then add a base register to it. */ | |
7208 | ||
3bec30a8 TS |
7209 | if (dbl && HAVE_32BIT_GPRS) |
7210 | as_warn (_("dla used to load 32-bit register")); | |
7211 | ||
90ecf173 | 7212 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7213 | as_warn (_("la used to load 64-bit address")); |
7214 | ||
0c11417f MR |
7215 | if (offset_expr.X_op == O_constant |
7216 | && offset_expr.X_add_number >= -0x8000 | |
7217 | && offset_expr.X_add_number < 0x8000) | |
7218 | { | |
aed1a261 | 7219 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7220 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7221 | break; |
0c11417f MR |
7222 | } |
7223 | ||
741fe287 | 7224 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7225 | { |
7226 | tempreg = AT; | |
7227 | used_at = 1; | |
7228 | } | |
7229 | else | |
7230 | { | |
7231 | tempreg = treg; | |
afdbd6d0 CD |
7232 | } |
7233 | ||
252b5132 RH |
7234 | if (offset_expr.X_op != O_symbol |
7235 | && offset_expr.X_op != O_constant) | |
7236 | { | |
f71d0d44 | 7237 | as_bad (_("Expression too complex")); |
252b5132 RH |
7238 | offset_expr.X_op = O_constant; |
7239 | } | |
7240 | ||
252b5132 | 7241 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7242 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7243 | else if (mips_pic == NO_PIC) |
7244 | { | |
d6bc6245 | 7245 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7246 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7247 | Otherwise we want |
7248 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7249 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7250 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7251 | so we may as well always use the latter form. |
76b3015f | 7252 | |
6caf9ef4 TS |
7253 | With 64bit address space and a usable $at we want |
7254 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7255 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7256 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7257 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7258 | dsll32 $tempreg,0 | |
7259 | daddu $tempreg,$tempreg,$at | |
7260 | ||
7261 | If $at is already in use, we use a path which is suboptimal | |
7262 | on superscalar processors. | |
7263 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7264 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7265 | dsll $tempreg,16 | |
7266 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7267 | dsll $tempreg,16 | |
7268 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7269 | ||
7270 | For GP relative symbols in 64bit address space we can use | |
7271 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7272 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7273 | { |
6caf9ef4 TS |
7274 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7275 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7276 | { | |
7277 | relax_start (offset_expr.X_add_symbol); | |
7278 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7279 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7280 | relax_switch (); | |
7281 | } | |
d6bc6245 | 7282 | |
741fe287 | 7283 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7284 | { |
df58fc94 | 7285 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7286 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7287 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7288 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7289 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7290 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7291 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7292 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7293 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7294 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7295 | used_at = 1; |
7296 | } | |
7297 | else | |
7298 | { | |
df58fc94 | 7299 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7300 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7301 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7302 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7303 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7304 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7305 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7306 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7307 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7308 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7309 | } |
6caf9ef4 TS |
7310 | |
7311 | if (mips_relax.sequence) | |
7312 | relax_end (); | |
98d3f06f KH |
7313 | } |
7314 | else | |
7315 | { | |
7316 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7317 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7318 | { |
4d7206a2 | 7319 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7320 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7321 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7322 | relax_switch (); |
98d3f06f | 7323 | } |
6943caf0 | 7324 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7325 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7326 | macro_build_lui (&offset_expr, tempreg); |
7327 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7328 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7329 | if (mips_relax.sequence) |
7330 | relax_end (); | |
98d3f06f | 7331 | } |
252b5132 | 7332 | } |
0a44bf69 | 7333 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7334 | { |
9117d219 NC |
7335 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7336 | ||
252b5132 RH |
7337 | /* If this is a reference to an external symbol, and there |
7338 | is no constant, we want | |
7339 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7340 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7341 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7342 | For a local symbol, we want |
7343 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7344 | nop | |
7345 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7346 | ||
7347 | If we have a small constant, and this is a reference to | |
7348 | an external symbol, we want | |
7349 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7350 | nop | |
7351 | addiu $tempreg,$tempreg,<constant> | |
7352 | For a local symbol, we want the same instruction | |
7353 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7354 | addiu instruction. | |
7355 | ||
7356 | If we have a large constant, and this is a reference to | |
7357 | an external symbol, we want | |
7358 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7359 | lui $at,<hiconstant> | |
7360 | addiu $at,$at,<loconstant> | |
7361 | addu $tempreg,$tempreg,$at | |
7362 | For a local symbol, we want the same instruction | |
7363 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7364 | addiu instruction. |
ed6fb7bd SC |
7365 | */ |
7366 | ||
4d7206a2 | 7367 | if (offset_expr.X_add_number == 0) |
252b5132 | 7368 | { |
0a44bf69 RS |
7369 | if (mips_pic == SVR4_PIC |
7370 | && breg == 0 | |
7371 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7372 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7373 | ||
7374 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7375 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7376 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7377 | if (breg != 0) |
252b5132 RH |
7378 | { |
7379 | /* We're going to put in an addu instruction using | |
7380 | tempreg, so we may as well insert the nop right | |
7381 | now. */ | |
269137b2 | 7382 | load_delay_nop (); |
252b5132 | 7383 | } |
4d7206a2 | 7384 | relax_switch (); |
67c0d1eb RS |
7385 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7386 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7387 | load_delay_nop (); |
67c0d1eb RS |
7388 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7389 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7390 | relax_end (); |
252b5132 RH |
7391 | /* FIXME: If breg == 0, and the next instruction uses |
7392 | $tempreg, then if this variant case is used an extra | |
7393 | nop will be generated. */ | |
7394 | } | |
4d7206a2 RS |
7395 | else if (offset_expr.X_add_number >= -0x8000 |
7396 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7397 | { |
67c0d1eb | 7398 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7399 | load_delay_nop (); |
67c0d1eb | 7400 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7401 | } |
7402 | else | |
7403 | { | |
4d7206a2 RS |
7404 | expr1.X_add_number = offset_expr.X_add_number; |
7405 | offset_expr.X_add_number = | |
43c0598f | 7406 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7407 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7408 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7409 | /* If we are going to add in a base register, and the |
7410 | target register and the base register are the same, | |
7411 | then we are using AT as a temporary register. Since | |
7412 | we want to load the constant into AT, we add our | |
7413 | current AT (from the global offset table) and the | |
7414 | register into the register now, and pretend we were | |
7415 | not using a base register. */ | |
67c0d1eb | 7416 | if (breg == treg) |
252b5132 | 7417 | { |
269137b2 | 7418 | load_delay_nop (); |
67c0d1eb | 7419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7420 | treg, AT, breg); |
252b5132 RH |
7421 | breg = 0; |
7422 | tempreg = treg; | |
252b5132 | 7423 | } |
f6a22291 | 7424 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7425 | used_at = 1; |
7426 | } | |
7427 | } | |
0a44bf69 | 7428 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7429 | { |
67c0d1eb | 7430 | int add_breg_early = 0; |
f5040a92 AO |
7431 | |
7432 | /* If this is a reference to an external, and there is no | |
7433 | constant, or local symbol (*), with or without a | |
7434 | constant, we want | |
7435 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7436 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7437 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7438 | ||
7439 | If we have a small constant, and this is a reference to | |
7440 | an external symbol, we want | |
7441 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7442 | addiu $tempreg,$tempreg,<constant> | |
7443 | ||
7444 | If we have a large constant, and this is a reference to | |
7445 | an external symbol, we want | |
7446 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7447 | lui $at,<hiconstant> | |
7448 | addiu $at,$at,<loconstant> | |
7449 | addu $tempreg,$tempreg,$at | |
7450 | ||
7451 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7452 | local symbols, even though it introduces an additional | |
7453 | instruction. */ | |
7454 | ||
f5040a92 AO |
7455 | if (offset_expr.X_add_number) |
7456 | { | |
4d7206a2 | 7457 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7458 | offset_expr.X_add_number = 0; |
7459 | ||
4d7206a2 | 7460 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7461 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7462 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7463 | |
7464 | if (expr1.X_add_number >= -0x8000 | |
7465 | && expr1.X_add_number < 0x8000) | |
7466 | { | |
67c0d1eb RS |
7467 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7468 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7469 | } |
ecd13cd3 | 7470 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7471 | { |
f5040a92 AO |
7472 | /* If we are going to add in a base register, and the |
7473 | target register and the base register are the same, | |
7474 | then we are using AT as a temporary register. Since | |
7475 | we want to load the constant into AT, we add our | |
7476 | current AT (from the global offset table) and the | |
7477 | register into the register now, and pretend we were | |
7478 | not using a base register. */ | |
7479 | if (breg != treg) | |
7480 | dreg = tempreg; | |
7481 | else | |
7482 | { | |
9c2799c2 | 7483 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7484 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7485 | treg, AT, breg); | |
f5040a92 | 7486 | dreg = treg; |
67c0d1eb | 7487 | add_breg_early = 1; |
f5040a92 AO |
7488 | } |
7489 | ||
f6a22291 | 7490 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7491 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7492 | dreg, dreg, AT); |
f5040a92 | 7493 | |
f5040a92 AO |
7494 | used_at = 1; |
7495 | } | |
7496 | else | |
7497 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7498 | ||
4d7206a2 | 7499 | relax_switch (); |
f5040a92 AO |
7500 | offset_expr.X_add_number = expr1.X_add_number; |
7501 | ||
67c0d1eb RS |
7502 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7503 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7504 | if (add_breg_early) | |
f5040a92 | 7505 | { |
67c0d1eb | 7506 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7507 | treg, tempreg, breg); |
f5040a92 AO |
7508 | breg = 0; |
7509 | tempreg = treg; | |
7510 | } | |
4d7206a2 | 7511 | relax_end (); |
f5040a92 | 7512 | } |
4d7206a2 | 7513 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7514 | { |
4d7206a2 | 7515 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7516 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7517 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7518 | relax_switch (); |
67c0d1eb RS |
7519 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7520 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7521 | relax_end (); |
f5040a92 | 7522 | } |
4d7206a2 | 7523 | else |
f5040a92 | 7524 | { |
67c0d1eb RS |
7525 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7526 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7527 | } |
7528 | } | |
0a44bf69 | 7529 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7530 | { |
67c0d1eb | 7531 | int gpdelay; |
9117d219 NC |
7532 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7533 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7534 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7535 | |
7536 | /* This is the large GOT case. If this is a reference to an | |
7537 | external symbol, and there is no constant, we want | |
7538 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7539 | addu $tempreg,$tempreg,$gp | |
7540 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7541 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7542 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7543 | addu $tempreg,$tempreg,$gp | |
7544 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7545 | For a local symbol, we want |
7546 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7547 | nop | |
7548 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7549 | ||
7550 | If we have a small constant, and this is a reference to | |
7551 | an external symbol, we want | |
7552 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7553 | addu $tempreg,$tempreg,$gp | |
7554 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7555 | nop | |
7556 | addiu $tempreg,$tempreg,<constant> | |
7557 | For a local symbol, we want | |
7558 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7559 | nop | |
7560 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7561 | ||
7562 | If we have a large constant, and this is a reference to | |
7563 | an external symbol, we want | |
7564 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7565 | addu $tempreg,$tempreg,$gp | |
7566 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7567 | lui $at,<hiconstant> | |
7568 | addiu $at,$at,<loconstant> | |
7569 | addu $tempreg,$tempreg,$at | |
7570 | For a local symbol, we want | |
7571 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7572 | lui $at,<hiconstant> | |
7573 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7574 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7575 | */ |
438c16b8 | 7576 | |
252b5132 RH |
7577 | expr1.X_add_number = offset_expr.X_add_number; |
7578 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7579 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7580 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7581 | if (expr1.X_add_number == 0 && breg == 0 |
7582 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7583 | { |
7584 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7585 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7586 | } | |
df58fc94 | 7587 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7588 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7589 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7590 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7591 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7592 | if (expr1.X_add_number == 0) |
7593 | { | |
67c0d1eb | 7594 | if (breg != 0) |
252b5132 RH |
7595 | { |
7596 | /* We're going to put in an addu instruction using | |
7597 | tempreg, so we may as well insert the nop right | |
7598 | now. */ | |
269137b2 | 7599 | load_delay_nop (); |
252b5132 | 7600 | } |
252b5132 RH |
7601 | } |
7602 | else if (expr1.X_add_number >= -0x8000 | |
7603 | && expr1.X_add_number < 0x8000) | |
7604 | { | |
269137b2 | 7605 | load_delay_nop (); |
67c0d1eb | 7606 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7607 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7608 | } |
7609 | else | |
7610 | { | |
252b5132 RH |
7611 | /* If we are going to add in a base register, and the |
7612 | target register and the base register are the same, | |
7613 | then we are using AT as a temporary register. Since | |
7614 | we want to load the constant into AT, we add our | |
7615 | current AT (from the global offset table) and the | |
7616 | register into the register now, and pretend we were | |
7617 | not using a base register. */ | |
7618 | if (breg != treg) | |
67c0d1eb | 7619 | dreg = tempreg; |
252b5132 RH |
7620 | else |
7621 | { | |
9c2799c2 | 7622 | gas_assert (tempreg == AT); |
269137b2 | 7623 | load_delay_nop (); |
67c0d1eb | 7624 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7625 | treg, AT, breg); |
252b5132 | 7626 | dreg = treg; |
252b5132 RH |
7627 | } |
7628 | ||
f6a22291 | 7629 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7630 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7631 | |
252b5132 RH |
7632 | used_at = 1; |
7633 | } | |
43c0598f | 7634 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7635 | relax_switch (); |
252b5132 | 7636 | |
67c0d1eb | 7637 | if (gpdelay) |
252b5132 RH |
7638 | { |
7639 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7640 | the first instruction on the main stream does not. */ |
67c0d1eb | 7641 | macro_build (NULL, "nop", ""); |
252b5132 | 7642 | } |
ed6fb7bd | 7643 | |
67c0d1eb RS |
7644 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7645 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7646 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7647 | && expr1.X_add_number < 0x8000) |
7648 | { | |
269137b2 | 7649 | load_delay_nop (); |
67c0d1eb RS |
7650 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7651 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7652 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7653 | register, the external symbol case ended with a load, |
7654 | so if the symbol turns out to not be external, and | |
7655 | the next instruction uses tempreg, an unnecessary nop | |
7656 | will be inserted. */ | |
252b5132 RH |
7657 | } |
7658 | else | |
7659 | { | |
7660 | if (breg == treg) | |
7661 | { | |
7662 | /* We must add in the base register now, as in the | |
f5040a92 | 7663 | external symbol case. */ |
9c2799c2 | 7664 | gas_assert (tempreg == AT); |
269137b2 | 7665 | load_delay_nop (); |
67c0d1eb | 7666 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7667 | treg, AT, breg); |
252b5132 RH |
7668 | tempreg = treg; |
7669 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7670 | it in in both cases. */ |
252b5132 RH |
7671 | breg = 0; |
7672 | } | |
7673 | ||
67c0d1eb RS |
7674 | macro_build_lui (&expr1, AT); |
7675 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7676 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7677 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7678 | tempreg, tempreg, AT); |
8fc2e39e | 7679 | used_at = 1; |
252b5132 | 7680 | } |
4d7206a2 | 7681 | relax_end (); |
252b5132 | 7682 | } |
0a44bf69 | 7683 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7684 | { |
f5040a92 AO |
7685 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7686 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7687 | int add_breg_early = 0; |
f5040a92 AO |
7688 | |
7689 | /* This is the large GOT case. If this is a reference to an | |
7690 | external symbol, and there is no constant, we want | |
7691 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7692 | add $tempreg,$tempreg,$gp | |
7693 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7694 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7695 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7696 | add $tempreg,$tempreg,$gp | |
7697 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7698 | ||
7699 | If we have a small constant, and this is a reference to | |
7700 | an external symbol, we want | |
7701 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7702 | add $tempreg,$tempreg,$gp | |
7703 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7704 | addi $tempreg,$tempreg,<constant> | |
7705 | ||
7706 | If we have a large constant, and this is a reference to | |
7707 | an external symbol, we want | |
7708 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7709 | addu $tempreg,$tempreg,$gp | |
7710 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7711 | lui $at,<hiconstant> | |
7712 | addi $at,$at,<loconstant> | |
7713 | add $tempreg,$tempreg,$at | |
7714 | ||
7715 | If we have NewABI, and we know it's a local symbol, we want | |
7716 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7717 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7718 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7719 | ||
4d7206a2 | 7720 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7721 | |
4d7206a2 | 7722 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7723 | offset_expr.X_add_number = 0; |
7724 | ||
1abe91b1 MR |
7725 | if (expr1.X_add_number == 0 && breg == 0 |
7726 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7727 | { |
7728 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7729 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7730 | } | |
df58fc94 | 7731 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7732 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7733 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7734 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7735 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7736 | |
7737 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7738 | ; |
f5040a92 AO |
7739 | else if (expr1.X_add_number >= -0x8000 |
7740 | && expr1.X_add_number < 0x8000) | |
7741 | { | |
67c0d1eb | 7742 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7743 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7744 | } |
ecd13cd3 | 7745 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7746 | { |
f5040a92 AO |
7747 | /* If we are going to add in a base register, and the |
7748 | target register and the base register are the same, | |
7749 | then we are using AT as a temporary register. Since | |
7750 | we want to load the constant into AT, we add our | |
7751 | current AT (from the global offset table) and the | |
7752 | register into the register now, and pretend we were | |
7753 | not using a base register. */ | |
7754 | if (breg != treg) | |
7755 | dreg = tempreg; | |
7756 | else | |
7757 | { | |
9c2799c2 | 7758 | gas_assert (tempreg == AT); |
67c0d1eb | 7759 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7760 | treg, AT, breg); |
f5040a92 | 7761 | dreg = treg; |
67c0d1eb | 7762 | add_breg_early = 1; |
f5040a92 AO |
7763 | } |
7764 | ||
f6a22291 | 7765 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7766 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7767 | |
f5040a92 AO |
7768 | used_at = 1; |
7769 | } | |
7770 | else | |
7771 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7772 | ||
4d7206a2 | 7773 | relax_switch (); |
f5040a92 | 7774 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7775 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7776 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7777 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7778 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7779 | if (add_breg_early) | |
f5040a92 | 7780 | { |
67c0d1eb | 7781 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7782 | treg, tempreg, breg); |
f5040a92 AO |
7783 | breg = 0; |
7784 | tempreg = treg; | |
7785 | } | |
4d7206a2 | 7786 | relax_end (); |
f5040a92 | 7787 | } |
252b5132 RH |
7788 | else |
7789 | abort (); | |
7790 | ||
7791 | if (breg != 0) | |
aed1a261 | 7792 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7793 | break; |
7794 | ||
52b6b6b9 | 7795 | case M_MSGSND: |
df58fc94 | 7796 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7797 | { |
7798 | unsigned long temp = (treg << 16) | (0x01); | |
7799 | macro_build (NULL, "c2", "C", temp); | |
7800 | } | |
c7af4273 | 7801 | break; |
52b6b6b9 JM |
7802 | |
7803 | case M_MSGLD: | |
df58fc94 | 7804 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7805 | { |
7806 | unsigned long temp = (0x02); | |
7807 | macro_build (NULL, "c2", "C", temp); | |
7808 | } | |
c7af4273 | 7809 | break; |
52b6b6b9 JM |
7810 | |
7811 | case M_MSGLD_T: | |
df58fc94 | 7812 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7813 | { |
7814 | unsigned long temp = (treg << 16) | (0x02); | |
7815 | macro_build (NULL, "c2", "C", temp); | |
7816 | } | |
c7af4273 | 7817 | break; |
52b6b6b9 JM |
7818 | |
7819 | case M_MSGWAIT: | |
df58fc94 | 7820 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7821 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7822 | break; |
52b6b6b9 JM |
7823 | |
7824 | case M_MSGWAIT_T: | |
df58fc94 | 7825 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7826 | { |
7827 | unsigned long temp = (treg << 16) | 0x03; | |
7828 | macro_build (NULL, "c2", "C", temp); | |
7829 | } | |
c7af4273 | 7830 | break; |
52b6b6b9 | 7831 | |
252b5132 RH |
7832 | case M_J_A: |
7833 | /* The j instruction may not be used in PIC code, since it | |
7834 | requires an absolute address. We convert it to a b | |
7835 | instruction. */ | |
7836 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7837 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7838 | else |
67c0d1eb | 7839 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7840 | break; |
252b5132 RH |
7841 | |
7842 | /* The jal instructions must be handled as macros because when | |
7843 | generating PIC code they expand to multi-instruction | |
7844 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7845 | case M_JALS_1: |
7846 | dreg = RA; | |
7847 | /* Fall through. */ | |
7848 | case M_JALS_2: | |
7849 | gas_assert (mips_opts.micromips); | |
7850 | jals = 1; | |
7851 | goto jal; | |
252b5132 RH |
7852 | case M_JAL_1: |
7853 | dreg = RA; | |
7854 | /* Fall through. */ | |
7855 | case M_JAL_2: | |
df58fc94 | 7856 | jal: |
3e722fb5 | 7857 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7858 | { |
7859 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7860 | if (mips_opts.micromips |
7861 | && dreg == RA | |
7862 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7863 | macro_build (NULL, s, "mj", sreg); |
7864 | else | |
7865 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7866 | } | |
0a44bf69 | 7867 | else |
252b5132 | 7868 | { |
df58fc94 RS |
7869 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7870 | && mips_cprestore_offset >= 0); | |
7871 | ||
252b5132 RH |
7872 | if (sreg != PIC_CALL_REG) |
7873 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7874 | |
df58fc94 RS |
7875 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7876 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7877 | if (mips_opts.micromips |
7878 | && dreg == RA | |
7879 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7880 | macro_build (NULL, s, "mj", sreg); |
7881 | else | |
7882 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7883 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7884 | { |
6478892d TS |
7885 | if (mips_cprestore_offset < 0) |
7886 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7887 | else | |
7888 | { | |
90ecf173 | 7889 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7890 | { |
7891 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7892 | /* Quiet this warning. */ | |
7893 | mips_frame_reg_valid = 1; | |
7894 | } | |
90ecf173 | 7895 | if (!mips_cprestore_valid) |
7a621144 DJ |
7896 | { |
7897 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7898 | /* Quiet this warning. */ | |
7899 | mips_cprestore_valid = 1; | |
7900 | } | |
d3fca0b5 MR |
7901 | if (mips_opts.noreorder) |
7902 | macro_build (NULL, "nop", ""); | |
6478892d | 7903 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7904 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7905 | mips_gp_register, |
256ab948 TS |
7906 | mips_frame_reg, |
7907 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7908 | } |
252b5132 RH |
7909 | } |
7910 | } | |
252b5132 | 7911 | |
8fc2e39e | 7912 | break; |
252b5132 | 7913 | |
df58fc94 RS |
7914 | case M_JALS_A: |
7915 | gas_assert (mips_opts.micromips); | |
7916 | jals = 1; | |
7917 | /* Fall through. */ | |
252b5132 RH |
7918 | case M_JAL_A: |
7919 | if (mips_pic == NO_PIC) | |
df58fc94 | 7920 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7921 | else if (mips_pic == SVR4_PIC) |
7922 | { | |
7923 | /* If this is a reference to an external symbol, and we are | |
7924 | using a small GOT, we want | |
7925 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7926 | nop | |
f9419b05 | 7927 | jalr $ra,$25 |
252b5132 RH |
7928 | nop |
7929 | lw $gp,cprestore($sp) | |
7930 | The cprestore value is set using the .cprestore | |
7931 | pseudo-op. If we are using a big GOT, we want | |
7932 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7933 | addu $25,$25,$gp | |
7934 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7935 | nop | |
f9419b05 | 7936 | jalr $ra,$25 |
252b5132 RH |
7937 | nop |
7938 | lw $gp,cprestore($sp) | |
7939 | If the symbol is not external, we want | |
7940 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7941 | nop | |
7942 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7943 | jalr $ra,$25 |
252b5132 | 7944 | nop |
438c16b8 | 7945 | lw $gp,cprestore($sp) |
f5040a92 AO |
7946 | |
7947 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7948 | sequences above, minus nops, unless the symbol is local, | |
7949 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7950 | GOT_DISP. */ | |
438c16b8 | 7951 | if (HAVE_NEWABI) |
252b5132 | 7952 | { |
90ecf173 | 7953 | if (!mips_big_got) |
f5040a92 | 7954 | { |
4d7206a2 | 7955 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7956 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7957 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7958 | mips_gp_register); |
4d7206a2 | 7959 | relax_switch (); |
67c0d1eb RS |
7960 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7961 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7962 | mips_gp_register); |
7963 | relax_end (); | |
f5040a92 AO |
7964 | } |
7965 | else | |
7966 | { | |
4d7206a2 | 7967 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7968 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7969 | BFD_RELOC_MIPS_CALL_HI16); |
7970 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7971 | PIC_CALL_REG, mips_gp_register); | |
7972 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7973 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7974 | PIC_CALL_REG); | |
4d7206a2 | 7975 | relax_switch (); |
67c0d1eb RS |
7976 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7977 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7978 | mips_gp_register); | |
7979 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7980 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7981 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7982 | relax_end (); |
f5040a92 | 7983 | } |
684022ea | 7984 | |
df58fc94 | 7985 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7986 | } |
7987 | else | |
7988 | { | |
4d7206a2 | 7989 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7990 | if (!mips_big_got) |
438c16b8 | 7991 | { |
67c0d1eb RS |
7992 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7993 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7994 | mips_gp_register); |
269137b2 | 7995 | load_delay_nop (); |
4d7206a2 | 7996 | relax_switch (); |
438c16b8 | 7997 | } |
252b5132 | 7998 | else |
252b5132 | 7999 | { |
67c0d1eb RS |
8000 | int gpdelay; |
8001 | ||
8002 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8003 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8004 | BFD_RELOC_MIPS_CALL_HI16); |
8005 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8006 | PIC_CALL_REG, mips_gp_register); | |
8007 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8008 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8009 | PIC_CALL_REG); | |
269137b2 | 8010 | load_delay_nop (); |
4d7206a2 | 8011 | relax_switch (); |
67c0d1eb RS |
8012 | if (gpdelay) |
8013 | macro_build (NULL, "nop", ""); | |
252b5132 | 8014 | } |
67c0d1eb RS |
8015 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8016 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8017 | mips_gp_register); |
269137b2 | 8018 | load_delay_nop (); |
67c0d1eb RS |
8019 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8020 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8021 | relax_end (); |
df58fc94 | 8022 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8023 | |
6478892d TS |
8024 | if (mips_cprestore_offset < 0) |
8025 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8026 | else | |
8027 | { | |
90ecf173 | 8028 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8029 | { |
8030 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8031 | /* Quiet this warning. */ | |
8032 | mips_frame_reg_valid = 1; | |
8033 | } | |
90ecf173 | 8034 | if (!mips_cprestore_valid) |
7a621144 DJ |
8035 | { |
8036 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8037 | /* Quiet this warning. */ | |
8038 | mips_cprestore_valid = 1; | |
8039 | } | |
6478892d | 8040 | if (mips_opts.noreorder) |
67c0d1eb | 8041 | macro_build (NULL, "nop", ""); |
6478892d | 8042 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8043 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8044 | mips_gp_register, |
256ab948 TS |
8045 | mips_frame_reg, |
8046 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8047 | } |
252b5132 RH |
8048 | } |
8049 | } | |
0a44bf69 RS |
8050 | else if (mips_pic == VXWORKS_PIC) |
8051 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8052 | else |
8053 | abort (); | |
8054 | ||
8fc2e39e | 8055 | break; |
252b5132 | 8056 | |
dec0624d MR |
8057 | case M_ACLR_AB: |
8058 | ab = 1; | |
8059 | case M_ACLR_OB: | |
8060 | s = "aclr"; | |
8061 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8062 | fmt = "\\,~(b)"; | |
8063 | off12 = 1; | |
8064 | goto ld_st; | |
8065 | case M_ASET_AB: | |
8066 | ab = 1; | |
8067 | case M_ASET_OB: | |
8068 | s = "aset"; | |
8069 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8070 | fmt = "\\,~(b)"; | |
8071 | off12 = 1; | |
8072 | goto ld_st; | |
252b5132 | 8073 | case M_LB_AB: |
df58fc94 | 8074 | ab = 1; |
252b5132 | 8075 | s = "lb"; |
df58fc94 | 8076 | fmt = "t,o(b)"; |
252b5132 RH |
8077 | goto ld; |
8078 | case M_LBU_AB: | |
df58fc94 | 8079 | ab = 1; |
252b5132 | 8080 | s = "lbu"; |
df58fc94 | 8081 | fmt = "t,o(b)"; |
252b5132 RH |
8082 | goto ld; |
8083 | case M_LH_AB: | |
df58fc94 | 8084 | ab = 1; |
252b5132 | 8085 | s = "lh"; |
df58fc94 | 8086 | fmt = "t,o(b)"; |
252b5132 RH |
8087 | goto ld; |
8088 | case M_LHU_AB: | |
df58fc94 | 8089 | ab = 1; |
252b5132 | 8090 | s = "lhu"; |
df58fc94 | 8091 | fmt = "t,o(b)"; |
252b5132 RH |
8092 | goto ld; |
8093 | case M_LW_AB: | |
df58fc94 | 8094 | ab = 1; |
252b5132 | 8095 | s = "lw"; |
df58fc94 | 8096 | fmt = "t,o(b)"; |
252b5132 RH |
8097 | goto ld; |
8098 | case M_LWC0_AB: | |
df58fc94 RS |
8099 | ab = 1; |
8100 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8101 | s = "lwc0"; |
df58fc94 | 8102 | fmt = "E,o(b)"; |
bdaaa2e1 | 8103 | /* Itbl support may require additional care here. */ |
252b5132 | 8104 | coproc = 1; |
df58fc94 | 8105 | goto ld_st; |
252b5132 | 8106 | case M_LWC1_AB: |
df58fc94 | 8107 | ab = 1; |
252b5132 | 8108 | s = "lwc1"; |
df58fc94 | 8109 | fmt = "T,o(b)"; |
bdaaa2e1 | 8110 | /* Itbl support may require additional care here. */ |
252b5132 | 8111 | coproc = 1; |
df58fc94 | 8112 | goto ld_st; |
252b5132 | 8113 | case M_LWC2_AB: |
df58fc94 RS |
8114 | ab = 1; |
8115 | case M_LWC2_OB: | |
252b5132 | 8116 | s = "lwc2"; |
df58fc94 RS |
8117 | fmt = COP12_FMT; |
8118 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8119 | /* Itbl support may require additional care here. */ |
252b5132 | 8120 | coproc = 1; |
df58fc94 | 8121 | goto ld_st; |
252b5132 | 8122 | case M_LWC3_AB: |
df58fc94 RS |
8123 | ab = 1; |
8124 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8125 | s = "lwc3"; |
df58fc94 | 8126 | fmt = "E,o(b)"; |
bdaaa2e1 | 8127 | /* Itbl support may require additional care here. */ |
252b5132 | 8128 | coproc = 1; |
df58fc94 | 8129 | goto ld_st; |
252b5132 | 8130 | case M_LWL_AB: |
df58fc94 RS |
8131 | ab = 1; |
8132 | case M_LWL_OB: | |
252b5132 | 8133 | s = "lwl"; |
df58fc94 RS |
8134 | fmt = MEM12_FMT; |
8135 | off12 = mips_opts.micromips; | |
8136 | goto ld_st; | |
252b5132 | 8137 | case M_LWR_AB: |
df58fc94 RS |
8138 | ab = 1; |
8139 | case M_LWR_OB: | |
252b5132 | 8140 | s = "lwr"; |
df58fc94 RS |
8141 | fmt = MEM12_FMT; |
8142 | off12 = mips_opts.micromips; | |
8143 | goto ld_st; | |
252b5132 | 8144 | case M_LDC1_AB: |
df58fc94 | 8145 | ab = 1; |
252b5132 | 8146 | s = "ldc1"; |
df58fc94 | 8147 | fmt = "T,o(b)"; |
bdaaa2e1 | 8148 | /* Itbl support may require additional care here. */ |
252b5132 | 8149 | coproc = 1; |
df58fc94 | 8150 | goto ld_st; |
252b5132 | 8151 | case M_LDC2_AB: |
df58fc94 RS |
8152 | ab = 1; |
8153 | case M_LDC2_OB: | |
252b5132 | 8154 | s = "ldc2"; |
df58fc94 RS |
8155 | fmt = COP12_FMT; |
8156 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8157 | /* Itbl support may require additional care here. */ |
252b5132 | 8158 | coproc = 1; |
df58fc94 | 8159 | goto ld_st; |
252b5132 | 8160 | case M_LDC3_AB: |
df58fc94 | 8161 | ab = 1; |
252b5132 | 8162 | s = "ldc3"; |
df58fc94 | 8163 | fmt = "E,o(b)"; |
bdaaa2e1 | 8164 | /* Itbl support may require additional care here. */ |
252b5132 | 8165 | coproc = 1; |
df58fc94 | 8166 | goto ld_st; |
252b5132 | 8167 | case M_LDL_AB: |
df58fc94 RS |
8168 | ab = 1; |
8169 | case M_LDL_OB: | |
252b5132 | 8170 | s = "ldl"; |
df58fc94 RS |
8171 | fmt = MEM12_FMT; |
8172 | off12 = mips_opts.micromips; | |
8173 | goto ld_st; | |
252b5132 | 8174 | case M_LDR_AB: |
df58fc94 RS |
8175 | ab = 1; |
8176 | case M_LDR_OB: | |
252b5132 | 8177 | s = "ldr"; |
df58fc94 RS |
8178 | fmt = MEM12_FMT; |
8179 | off12 = mips_opts.micromips; | |
8180 | goto ld_st; | |
252b5132 | 8181 | case M_LL_AB: |
df58fc94 RS |
8182 | ab = 1; |
8183 | case M_LL_OB: | |
252b5132 | 8184 | s = "ll"; |
df58fc94 RS |
8185 | fmt = MEM12_FMT; |
8186 | off12 = mips_opts.micromips; | |
252b5132 RH |
8187 | goto ld; |
8188 | case M_LLD_AB: | |
df58fc94 RS |
8189 | ab = 1; |
8190 | case M_LLD_OB: | |
252b5132 | 8191 | s = "lld"; |
df58fc94 RS |
8192 | fmt = MEM12_FMT; |
8193 | off12 = mips_opts.micromips; | |
252b5132 RH |
8194 | goto ld; |
8195 | case M_LWU_AB: | |
df58fc94 RS |
8196 | ab = 1; |
8197 | case M_LWU_OB: | |
252b5132 | 8198 | s = "lwu"; |
df58fc94 RS |
8199 | fmt = MEM12_FMT; |
8200 | off12 = mips_opts.micromips; | |
8201 | goto ld; | |
8202 | case M_LWP_AB: | |
8203 | ab = 1; | |
8204 | case M_LWP_OB: | |
8205 | gas_assert (mips_opts.micromips); | |
8206 | s = "lwp"; | |
8207 | fmt = "t,~(b)"; | |
8208 | off12 = 1; | |
8209 | lp = 1; | |
8210 | goto ld; | |
8211 | case M_LDP_AB: | |
8212 | ab = 1; | |
8213 | case M_LDP_OB: | |
8214 | gas_assert (mips_opts.micromips); | |
8215 | s = "ldp"; | |
8216 | fmt = "t,~(b)"; | |
8217 | off12 = 1; | |
8218 | lp = 1; | |
8219 | goto ld; | |
8220 | case M_LWM_AB: | |
8221 | ab = 1; | |
8222 | case M_LWM_OB: | |
8223 | gas_assert (mips_opts.micromips); | |
8224 | s = "lwm"; | |
8225 | fmt = "n,~(b)"; | |
8226 | off12 = 1; | |
8227 | goto ld_st; | |
8228 | case M_LDM_AB: | |
8229 | ab = 1; | |
8230 | case M_LDM_OB: | |
8231 | gas_assert (mips_opts.micromips); | |
8232 | s = "ldm"; | |
8233 | fmt = "n,~(b)"; | |
8234 | off12 = 1; | |
8235 | goto ld_st; | |
8236 | ||
252b5132 | 8237 | ld: |
df58fc94 RS |
8238 | if (breg == treg + lp) |
8239 | goto ld_st; | |
252b5132 | 8240 | else |
df58fc94 RS |
8241 | tempreg = treg + lp; |
8242 | goto ld_noat; | |
8243 | ||
252b5132 | 8244 | case M_SB_AB: |
df58fc94 | 8245 | ab = 1; |
252b5132 | 8246 | s = "sb"; |
df58fc94 RS |
8247 | fmt = "t,o(b)"; |
8248 | goto ld_st; | |
252b5132 | 8249 | case M_SH_AB: |
df58fc94 | 8250 | ab = 1; |
252b5132 | 8251 | s = "sh"; |
df58fc94 RS |
8252 | fmt = "t,o(b)"; |
8253 | goto ld_st; | |
252b5132 | 8254 | case M_SW_AB: |
df58fc94 | 8255 | ab = 1; |
252b5132 | 8256 | s = "sw"; |
df58fc94 RS |
8257 | fmt = "t,o(b)"; |
8258 | goto ld_st; | |
252b5132 | 8259 | case M_SWC0_AB: |
df58fc94 RS |
8260 | ab = 1; |
8261 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8262 | s = "swc0"; |
df58fc94 | 8263 | fmt = "E,o(b)"; |
bdaaa2e1 | 8264 | /* Itbl support may require additional care here. */ |
252b5132 | 8265 | coproc = 1; |
df58fc94 | 8266 | goto ld_st; |
252b5132 | 8267 | case M_SWC1_AB: |
df58fc94 | 8268 | ab = 1; |
252b5132 | 8269 | s = "swc1"; |
df58fc94 | 8270 | fmt = "T,o(b)"; |
bdaaa2e1 | 8271 | /* Itbl support may require additional care here. */ |
252b5132 | 8272 | coproc = 1; |
df58fc94 | 8273 | goto ld_st; |
252b5132 | 8274 | case M_SWC2_AB: |
df58fc94 RS |
8275 | ab = 1; |
8276 | case M_SWC2_OB: | |
252b5132 | 8277 | s = "swc2"; |
df58fc94 RS |
8278 | fmt = COP12_FMT; |
8279 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8280 | /* Itbl support may require additional care here. */ |
252b5132 | 8281 | coproc = 1; |
df58fc94 | 8282 | goto ld_st; |
252b5132 | 8283 | case M_SWC3_AB: |
df58fc94 RS |
8284 | ab = 1; |
8285 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8286 | s = "swc3"; |
df58fc94 | 8287 | fmt = "E,o(b)"; |
bdaaa2e1 | 8288 | /* Itbl support may require additional care here. */ |
252b5132 | 8289 | coproc = 1; |
df58fc94 | 8290 | goto ld_st; |
252b5132 | 8291 | case M_SWL_AB: |
df58fc94 RS |
8292 | ab = 1; |
8293 | case M_SWL_OB: | |
252b5132 | 8294 | s = "swl"; |
df58fc94 RS |
8295 | fmt = MEM12_FMT; |
8296 | off12 = mips_opts.micromips; | |
8297 | goto ld_st; | |
252b5132 | 8298 | case M_SWR_AB: |
df58fc94 RS |
8299 | ab = 1; |
8300 | case M_SWR_OB: | |
252b5132 | 8301 | s = "swr"; |
df58fc94 RS |
8302 | fmt = MEM12_FMT; |
8303 | off12 = mips_opts.micromips; | |
8304 | goto ld_st; | |
252b5132 | 8305 | case M_SC_AB: |
df58fc94 RS |
8306 | ab = 1; |
8307 | case M_SC_OB: | |
252b5132 | 8308 | s = "sc"; |
df58fc94 RS |
8309 | fmt = MEM12_FMT; |
8310 | off12 = mips_opts.micromips; | |
8311 | goto ld_st; | |
252b5132 | 8312 | case M_SCD_AB: |
df58fc94 RS |
8313 | ab = 1; |
8314 | case M_SCD_OB: | |
252b5132 | 8315 | s = "scd"; |
df58fc94 RS |
8316 | fmt = MEM12_FMT; |
8317 | off12 = mips_opts.micromips; | |
8318 | goto ld_st; | |
d43b4baf | 8319 | case M_CACHE_AB: |
df58fc94 RS |
8320 | ab = 1; |
8321 | case M_CACHE_OB: | |
d43b4baf | 8322 | s = "cache"; |
df58fc94 RS |
8323 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8324 | off12 = mips_opts.micromips; | |
8325 | goto ld_st; | |
3eebd5eb | 8326 | case M_PREF_AB: |
df58fc94 RS |
8327 | ab = 1; |
8328 | case M_PREF_OB: | |
3eebd5eb | 8329 | s = "pref"; |
df58fc94 RS |
8330 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8331 | off12 = mips_opts.micromips; | |
8332 | goto ld_st; | |
252b5132 | 8333 | case M_SDC1_AB: |
df58fc94 | 8334 | ab = 1; |
252b5132 | 8335 | s = "sdc1"; |
df58fc94 | 8336 | fmt = "T,o(b)"; |
252b5132 | 8337 | coproc = 1; |
bdaaa2e1 | 8338 | /* Itbl support may require additional care here. */ |
df58fc94 | 8339 | goto ld_st; |
252b5132 | 8340 | case M_SDC2_AB: |
df58fc94 RS |
8341 | ab = 1; |
8342 | case M_SDC2_OB: | |
252b5132 | 8343 | s = "sdc2"; |
df58fc94 RS |
8344 | fmt = COP12_FMT; |
8345 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8346 | /* Itbl support may require additional care here. */ |
252b5132 | 8347 | coproc = 1; |
df58fc94 | 8348 | goto ld_st; |
252b5132 | 8349 | case M_SDC3_AB: |
df58fc94 RS |
8350 | ab = 1; |
8351 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8352 | s = "sdc3"; |
df58fc94 | 8353 | fmt = "E,o(b)"; |
bdaaa2e1 | 8354 | /* Itbl support may require additional care here. */ |
252b5132 | 8355 | coproc = 1; |
df58fc94 | 8356 | goto ld_st; |
252b5132 | 8357 | case M_SDL_AB: |
df58fc94 RS |
8358 | ab = 1; |
8359 | case M_SDL_OB: | |
252b5132 | 8360 | s = "sdl"; |
df58fc94 RS |
8361 | fmt = MEM12_FMT; |
8362 | off12 = mips_opts.micromips; | |
8363 | goto ld_st; | |
252b5132 | 8364 | case M_SDR_AB: |
df58fc94 RS |
8365 | ab = 1; |
8366 | case M_SDR_OB: | |
252b5132 | 8367 | s = "sdr"; |
df58fc94 RS |
8368 | fmt = MEM12_FMT; |
8369 | off12 = mips_opts.micromips; | |
8370 | goto ld_st; | |
8371 | case M_SWP_AB: | |
8372 | ab = 1; | |
8373 | case M_SWP_OB: | |
8374 | gas_assert (mips_opts.micromips); | |
8375 | s = "swp"; | |
8376 | fmt = "t,~(b)"; | |
8377 | off12 = 1; | |
8378 | goto ld_st; | |
8379 | case M_SDP_AB: | |
8380 | ab = 1; | |
8381 | case M_SDP_OB: | |
8382 | gas_assert (mips_opts.micromips); | |
8383 | s = "sdp"; | |
8384 | fmt = "t,~(b)"; | |
8385 | off12 = 1; | |
8386 | goto ld_st; | |
8387 | case M_SWM_AB: | |
8388 | ab = 1; | |
8389 | case M_SWM_OB: | |
8390 | gas_assert (mips_opts.micromips); | |
8391 | s = "swm"; | |
8392 | fmt = "n,~(b)"; | |
8393 | off12 = 1; | |
8394 | goto ld_st; | |
8395 | case M_SDM_AB: | |
8396 | ab = 1; | |
8397 | case M_SDM_OB: | |
8398 | gas_assert (mips_opts.micromips); | |
8399 | s = "sdm"; | |
8400 | fmt = "n,~(b)"; | |
8401 | off12 = 1; | |
8402 | ||
8403 | ld_st: | |
8fc2e39e TS |
8404 | tempreg = AT; |
8405 | used_at = 1; | |
df58fc94 | 8406 | ld_noat: |
252b5132 RH |
8407 | if (offset_expr.X_op != O_constant |
8408 | && offset_expr.X_op != O_symbol) | |
8409 | { | |
f71d0d44 | 8410 | as_bad (_("Expression too complex")); |
252b5132 RH |
8411 | offset_expr.X_op = O_constant; |
8412 | } | |
8413 | ||
2051e8c4 MR |
8414 | if (HAVE_32BIT_ADDRESSES |
8415 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8416 | { |
8417 | char value [32]; | |
8418 | ||
8419 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8420 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8421 | } |
2051e8c4 | 8422 | |
252b5132 RH |
8423 | /* A constant expression in PIC code can be handled just as it |
8424 | is in non PIC code. */ | |
aed1a261 RS |
8425 | if (offset_expr.X_op == O_constant) |
8426 | { | |
df58fc94 RS |
8427 | int hipart = 0; |
8428 | ||
842f8b2a | 8429 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8430 | normalize_address_expr (&expr1); |
df58fc94 | 8431 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8432 | { |
8433 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8434 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8435 | hipart = 1; |
8436 | } | |
8437 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8438 | { | |
8439 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8440 | & ~(bfd_vma) 0xfff); | |
8441 | hipart = 1; | |
8442 | } | |
8443 | if (hipart) | |
8444 | { | |
842f8b2a MR |
8445 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8446 | if (breg != 0) | |
8447 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8448 | tempreg, tempreg, breg); | |
8449 | breg = tempreg; | |
8450 | } | |
dd6a37e7 AP |
8451 | if (off0) |
8452 | { | |
8453 | if (offset_expr.X_add_number == 0) | |
8454 | tempreg = breg; | |
8455 | else | |
8456 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8457 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8458 | macro_build (NULL, s, fmt, treg, tempreg); | |
8459 | } | |
8460 | else if (!off12) | |
df58fc94 RS |
8461 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8462 | else | |
8463 | macro_build (NULL, s, fmt, | |
8464 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8465 | } | |
dd6a37e7 | 8466 | else if (off12 || off0) |
df58fc94 | 8467 | { |
dd6a37e7 AP |
8468 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8469 | for a low-part relocation, so load the whole address into | |
8470 | the auxillary register. In the case of "A(b)" addresses, | |
8471 | we first load absolute address "A" into the register and | |
8472 | then add base register "b". In the case of "o(b)" addresses, | |
8473 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8474 | offset_reloc already contains the relocations associated |
8475 | with "o". */ | |
8476 | if (ab) | |
8477 | { | |
8478 | load_address (tempreg, &offset_expr, &used_at); | |
8479 | if (breg != 0) | |
8480 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8481 | tempreg, tempreg, breg); | |
8482 | } | |
8483 | else | |
8484 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8485 | tempreg, breg, -1, | |
8486 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8487 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8488 | if (off0) |
8489 | macro_build (NULL, s, fmt, treg, tempreg); | |
8490 | else | |
8491 | macro_build (NULL, s, fmt, | |
8492 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8493 | } |
8494 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8495 | { |
8496 | /* If this is a reference to a GP relative symbol, and there | |
8497 | is no base register, we want | |
cdf6fd85 | 8498 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8499 | Otherwise, if there is no base register, we want |
8500 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8501 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8502 | If we have a constant, we need two instructions anyhow, | |
8503 | so we always use the latter form. | |
8504 | ||
8505 | If we have a base register, and this is a reference to a | |
8506 | GP relative symbol, we want | |
8507 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8508 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8509 | Otherwise we want |
8510 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8511 | addu $tempreg,$tempreg,$breg | |
8512 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8513 | With a constant we always use the latter case. |
76b3015f | 8514 | |
d6bc6245 TS |
8515 | With 64bit address space and no base register and $at usable, |
8516 | we want | |
8517 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8518 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8519 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8520 | dsll32 $tempreg,0 | |
8521 | daddu $tempreg,$at | |
8522 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8523 | If we have a base register, we want | |
8524 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8525 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8526 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8527 | daddu $at,$breg | |
8528 | dsll32 $tempreg,0 | |
8529 | daddu $tempreg,$at | |
8530 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8531 | ||
8532 | Without $at we can't generate the optimal path for superscalar | |
8533 | processors here since this would require two temporary registers. | |
8534 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8535 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8536 | dsll $tempreg,16 | |
8537 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8538 | dsll $tempreg,16 | |
8539 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8540 | If we have a base register, we want | |
8541 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8542 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8543 | dsll $tempreg,16 | |
8544 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8545 | dsll $tempreg,16 | |
8546 | daddu $tempreg,$tempreg,$breg | |
8547 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8548 | |
6caf9ef4 | 8549 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8550 | the same sequence as in 32bit address space. */ |
8551 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8552 | { |
aed1a261 | 8553 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8554 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8555 | { | |
8556 | relax_start (offset_expr.X_add_symbol); | |
8557 | if (breg == 0) | |
8558 | { | |
8559 | macro_build (&offset_expr, s, fmt, treg, | |
8560 | BFD_RELOC_GPREL16, mips_gp_register); | |
8561 | } | |
8562 | else | |
8563 | { | |
8564 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8565 | tempreg, breg, mips_gp_register); | |
8566 | macro_build (&offset_expr, s, fmt, treg, | |
8567 | BFD_RELOC_GPREL16, tempreg); | |
8568 | } | |
8569 | relax_switch (); | |
8570 | } | |
d6bc6245 | 8571 | |
741fe287 | 8572 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8573 | { |
df58fc94 | 8574 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8575 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8576 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8577 | BFD_RELOC_HI16_S); |
8578 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8579 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8580 | if (breg != 0) |
67c0d1eb | 8581 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8582 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8583 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8584 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8585 | tempreg); | |
d6bc6245 TS |
8586 | used_at = 1; |
8587 | } | |
8588 | else | |
8589 | { | |
df58fc94 | 8590 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8591 | BFD_RELOC_MIPS_HIGHEST); |
8592 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8593 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8594 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8595 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8596 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8597 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8598 | if (breg != 0) |
67c0d1eb | 8599 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8600 | tempreg, tempreg, breg); |
67c0d1eb | 8601 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8602 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8603 | } |
6caf9ef4 TS |
8604 | |
8605 | if (mips_relax.sequence) | |
8606 | relax_end (); | |
8fc2e39e | 8607 | break; |
d6bc6245 | 8608 | } |
256ab948 | 8609 | |
252b5132 RH |
8610 | if (breg == 0) |
8611 | { | |
67c0d1eb | 8612 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8613 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8614 | { |
4d7206a2 | 8615 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8616 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8617 | mips_gp_register); | |
4d7206a2 | 8618 | relax_switch (); |
252b5132 | 8619 | } |
67c0d1eb RS |
8620 | macro_build_lui (&offset_expr, tempreg); |
8621 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8622 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8623 | if (mips_relax.sequence) |
8624 | relax_end (); | |
252b5132 RH |
8625 | } |
8626 | else | |
8627 | { | |
67c0d1eb | 8628 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8629 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8630 | { |
4d7206a2 | 8631 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8632 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8633 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8634 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8635 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8636 | relax_switch (); |
252b5132 | 8637 | } |
67c0d1eb RS |
8638 | macro_build_lui (&offset_expr, tempreg); |
8639 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8640 | tempreg, tempreg, breg); |
67c0d1eb | 8641 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8642 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8643 | if (mips_relax.sequence) |
8644 | relax_end (); | |
252b5132 RH |
8645 | } |
8646 | } | |
0a44bf69 | 8647 | else if (!mips_big_got) |
252b5132 | 8648 | { |
ed6fb7bd | 8649 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8650 | |
252b5132 RH |
8651 | /* If this is a reference to an external symbol, we want |
8652 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8653 | nop | |
8654 | <op> $treg,0($tempreg) | |
8655 | Otherwise we want | |
8656 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8657 | nop | |
8658 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8659 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8660 | |
8661 | For NewABI, we want | |
8662 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8663 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8664 | ||
252b5132 RH |
8665 | If there is a base register, we add it to $tempreg before |
8666 | the <op>. If there is a constant, we stick it in the | |
8667 | <op> instruction. We don't handle constants larger than | |
8668 | 16 bits, because we have no way to load the upper 16 bits | |
8669 | (actually, we could handle them for the subset of cases | |
8670 | in which we are not using $at). */ | |
9c2799c2 | 8671 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8672 | if (HAVE_NEWABI) |
8673 | { | |
67c0d1eb RS |
8674 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8675 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8676 | if (breg != 0) |
67c0d1eb | 8677 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8678 | tempreg, tempreg, breg); |
67c0d1eb | 8679 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8680 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8681 | break; |
8682 | } | |
252b5132 RH |
8683 | expr1.X_add_number = offset_expr.X_add_number; |
8684 | offset_expr.X_add_number = 0; | |
8685 | if (expr1.X_add_number < -0x8000 | |
8686 | || expr1.X_add_number >= 0x8000) | |
8687 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8688 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8689 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8690 | load_delay_nop (); |
4d7206a2 RS |
8691 | relax_start (offset_expr.X_add_symbol); |
8692 | relax_switch (); | |
67c0d1eb RS |
8693 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8694 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8695 | relax_end (); |
252b5132 | 8696 | if (breg != 0) |
67c0d1eb | 8697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8698 | tempreg, tempreg, breg); |
67c0d1eb | 8699 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8700 | } |
0a44bf69 | 8701 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8702 | { |
67c0d1eb | 8703 | int gpdelay; |
252b5132 RH |
8704 | |
8705 | /* If this is a reference to an external symbol, we want | |
8706 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8707 | addu $tempreg,$tempreg,$gp | |
8708 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8709 | <op> $treg,0($tempreg) | |
8710 | Otherwise we want | |
8711 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8712 | nop | |
8713 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8714 | <op> $treg,0($tempreg) | |
8715 | If there is a base register, we add it to $tempreg before | |
8716 | the <op>. If there is a constant, we stick it in the | |
8717 | <op> instruction. We don't handle constants larger than | |
8718 | 16 bits, because we have no way to load the upper 16 bits | |
8719 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8720 | in which we are not using $at). */ |
9c2799c2 | 8721 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8722 | expr1.X_add_number = offset_expr.X_add_number; |
8723 | offset_expr.X_add_number = 0; | |
8724 | if (expr1.X_add_number < -0x8000 | |
8725 | || expr1.X_add_number >= 0x8000) | |
8726 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8727 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8728 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8729 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8730 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8731 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8732 | mips_gp_register); | |
8733 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8734 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8735 | relax_switch (); |
67c0d1eb RS |
8736 | if (gpdelay) |
8737 | macro_build (NULL, "nop", ""); | |
8738 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8739 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8740 | load_delay_nop (); |
67c0d1eb RS |
8741 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8742 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8743 | relax_end (); |
8744 | ||
252b5132 | 8745 | if (breg != 0) |
67c0d1eb | 8746 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8747 | tempreg, tempreg, breg); |
67c0d1eb | 8748 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8749 | } |
0a44bf69 | 8750 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8751 | { |
f5040a92 AO |
8752 | /* If this is a reference to an external symbol, we want |
8753 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8754 | add $tempreg,$tempreg,$gp | |
8755 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8756 | <op> $treg,<ofst>($tempreg) | |
8757 | Otherwise, for local symbols, we want: | |
8758 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8759 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8760 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8761 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8762 | offset_expr.X_add_number = 0; |
8763 | if (expr1.X_add_number < -0x8000 | |
8764 | || expr1.X_add_number >= 0x8000) | |
8765 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8766 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8767 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8768 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8769 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8770 | mips_gp_register); | |
8771 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8772 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8773 | if (breg != 0) |
67c0d1eb | 8774 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8775 | tempreg, tempreg, breg); |
67c0d1eb | 8776 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8777 | |
4d7206a2 | 8778 | relax_switch (); |
f5040a92 | 8779 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8780 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8781 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8782 | if (breg != 0) |
67c0d1eb | 8783 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8784 | tempreg, tempreg, breg); |
67c0d1eb | 8785 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8786 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8787 | relax_end (); |
f5040a92 | 8788 | } |
252b5132 RH |
8789 | else |
8790 | abort (); | |
8791 | ||
252b5132 RH |
8792 | break; |
8793 | ||
8794 | case M_LI: | |
8795 | case M_LI_S: | |
67c0d1eb | 8796 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8797 | break; |
252b5132 RH |
8798 | |
8799 | case M_DLI: | |
67c0d1eb | 8800 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8801 | break; |
252b5132 RH |
8802 | |
8803 | case M_LI_SS: | |
8804 | if (imm_expr.X_op == O_constant) | |
8805 | { | |
8fc2e39e | 8806 | used_at = 1; |
67c0d1eb RS |
8807 | load_register (AT, &imm_expr, 0); |
8808 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8809 | break; |
8810 | } | |
8811 | else | |
8812 | { | |
9c2799c2 | 8813 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8814 | && strcmp (segment_name (S_GET_SEGMENT |
8815 | (offset_expr.X_add_symbol)), | |
8816 | ".lit4") == 0 | |
8817 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8818 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8819 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8820 | break; |
252b5132 RH |
8821 | } |
8822 | ||
8823 | case M_LI_D: | |
ca4e0257 RS |
8824 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8825 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8826 | order 32 bits of the value and the low order 32 bits are either | |
8827 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8828 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8829 | { | |
ca4e0257 | 8830 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8831 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8832 | else |
8833 | { | |
8834 | int hreg, lreg; | |
8835 | ||
8836 | if (target_big_endian) | |
8837 | { | |
8838 | hreg = treg; | |
8839 | lreg = treg + 1; | |
8840 | } | |
8841 | else | |
8842 | { | |
8843 | hreg = treg + 1; | |
8844 | lreg = treg; | |
8845 | } | |
8846 | ||
8847 | if (hreg <= 31) | |
67c0d1eb | 8848 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8849 | if (lreg <= 31) |
8850 | { | |
8851 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8852 | move_register (lreg, 0); |
252b5132 RH |
8853 | else |
8854 | { | |
9c2799c2 | 8855 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8856 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8857 | } |
8858 | } | |
8859 | } | |
8fc2e39e | 8860 | break; |
252b5132 RH |
8861 | } |
8862 | ||
8863 | /* We know that sym is in the .rdata section. First we get the | |
8864 | upper 16 bits of the address. */ | |
8865 | if (mips_pic == NO_PIC) | |
8866 | { | |
67c0d1eb | 8867 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8868 | used_at = 1; |
252b5132 | 8869 | } |
0a44bf69 | 8870 | else |
252b5132 | 8871 | { |
67c0d1eb RS |
8872 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8873 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8874 | used_at = 1; |
252b5132 | 8875 | } |
bdaaa2e1 | 8876 | |
252b5132 | 8877 | /* Now we load the register(s). */ |
ca4e0257 | 8878 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8879 | { |
8880 | used_at = 1; | |
8881 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8882 | } | |
252b5132 RH |
8883 | else |
8884 | { | |
8fc2e39e | 8885 | used_at = 1; |
67c0d1eb | 8886 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8887 | if (treg != RA) |
252b5132 RH |
8888 | { |
8889 | /* FIXME: How in the world do we deal with the possible | |
8890 | overflow here? */ | |
8891 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8892 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8893 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8894 | } |
8895 | } | |
252b5132 RH |
8896 | break; |
8897 | ||
8898 | case M_LI_DD: | |
ca4e0257 RS |
8899 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8900 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8901 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8902 | the value and the low order 32 bits are either zero or in | |
8903 | OFFSET_EXPR. */ | |
252b5132 RH |
8904 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8905 | { | |
8fc2e39e | 8906 | used_at = 1; |
67c0d1eb | 8907 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8908 | if (HAVE_64BIT_FPRS) |
8909 | { | |
9c2799c2 | 8910 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8911 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8912 | } |
252b5132 RH |
8913 | else |
8914 | { | |
67c0d1eb | 8915 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8916 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8917 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8918 | else |
8919 | { | |
9c2799c2 | 8920 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8921 | load_register (AT, &offset_expr, 0); |
8922 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8923 | } |
8924 | } | |
8925 | break; | |
8926 | } | |
8927 | ||
9c2799c2 | 8928 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8929 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8930 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8931 | if (strcmp (s, ".lit8") == 0) | |
8932 | { | |
e407c74b NC |
8933 | if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
8934 | && (mips_opts.arch != CPU_R5900)) | |
252b5132 | 8935 | { |
67c0d1eb | 8936 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8937 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8938 | break; |
252b5132 | 8939 | } |
c9914766 | 8940 | breg = mips_gp_register; |
252b5132 RH |
8941 | r = BFD_RELOC_MIPS_LITERAL; |
8942 | goto dob; | |
8943 | } | |
8944 | else | |
8945 | { | |
9c2799c2 | 8946 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8947 | used_at = 1; |
0a44bf69 | 8948 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8949 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8950 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8951 | else |
8952 | { | |
8953 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8954 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8955 | } |
bdaaa2e1 | 8956 | |
e407c74b NC |
8957 | if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
8958 | && (mips_opts.arch != CPU_R5900)) | |
252b5132 | 8959 | { |
67c0d1eb RS |
8960 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8961 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8962 | break; |
8963 | } | |
8964 | breg = AT; | |
8965 | r = BFD_RELOC_LO16; | |
8966 | goto dob; | |
8967 | } | |
8968 | ||
8969 | case M_L_DOB: | |
252b5132 RH |
8970 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8971 | to adjust when loading from memory. */ | |
8972 | r = BFD_RELOC_LO16; | |
8973 | dob: | |
df58fc94 | 8974 | gas_assert (!mips_opts.micromips); |
e407c74b NC |
8975 | gas_assert ((mips_opts.isa == ISA_MIPS1) |
8976 | || (mips_opts.arch == CPU_R5900)); | |
67c0d1eb | 8977 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8978 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8979 | /* FIXME: A possible overflow which I don't know how to deal |
8980 | with. */ | |
8981 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8982 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8983 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8984 | break; |
8985 | ||
c4a68bea | 8986 | case M_S_DOB: |
df58fc94 | 8987 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8988 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8989 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8990 | to adjust when storing to memory. */ | |
8991 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8992 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8993 | offset_expr.X_add_number += 4; | |
8994 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8995 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8996 | break; | |
8997 | ||
252b5132 | 8998 | case M_L_DAB: |
df58fc94 | 8999 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9000 | /* |
9001 | * The MIPS assembler seems to check for X_add_number not | |
9002 | * being double aligned and generating: | |
9003 | * lui at,%hi(foo+1) | |
9004 | * addu at,at,v1 | |
9005 | * addiu at,at,%lo(foo+1) | |
9006 | * lwc1 f2,0(at) | |
9007 | * lwc1 f3,4(at) | |
9008 | * But, the resulting address is the same after relocation so why | |
9009 | * generate the extra instruction? | |
9010 | */ | |
bdaaa2e1 | 9011 | /* Itbl support may require additional care here. */ |
252b5132 | 9012 | coproc = 1; |
df58fc94 | 9013 | fmt = "T,o(b)"; |
e407c74b | 9014 | if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900)) |
252b5132 RH |
9015 | { |
9016 | s = "ldc1"; | |
df58fc94 | 9017 | goto ld_st; |
252b5132 | 9018 | } |
252b5132 | 9019 | s = "lwc1"; |
252b5132 RH |
9020 | goto ldd_std; |
9021 | ||
9022 | case M_S_DAB: | |
df58fc94 RS |
9023 | gas_assert (!mips_opts.micromips); |
9024 | /* Itbl support may require additional care here. */ | |
9025 | coproc = 1; | |
9026 | fmt = "T,o(b)"; | |
e407c74b | 9027 | if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900)) |
252b5132 RH |
9028 | { |
9029 | s = "sdc1"; | |
df58fc94 | 9030 | goto ld_st; |
252b5132 | 9031 | } |
252b5132 | 9032 | s = "swc1"; |
252b5132 RH |
9033 | goto ldd_std; |
9034 | ||
e407c74b NC |
9035 | case M_LQ_AB: |
9036 | fmt = "t,o(b)"; | |
9037 | s = "lq"; | |
9038 | goto ld; | |
9039 | ||
9040 | case M_SQ_AB: | |
9041 | fmt = "t,o(b)"; | |
9042 | s = "sq"; | |
9043 | goto ld_st; | |
9044 | ||
252b5132 | 9045 | case M_LD_AB: |
df58fc94 | 9046 | fmt = "t,o(b)"; |
ca4e0257 | 9047 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9048 | { |
9049 | s = "ld"; | |
9050 | goto ld; | |
9051 | } | |
252b5132 | 9052 | s = "lw"; |
252b5132 RH |
9053 | goto ldd_std; |
9054 | ||
9055 | case M_SD_AB: | |
df58fc94 | 9056 | fmt = "t,o(b)"; |
ca4e0257 | 9057 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9058 | { |
9059 | s = "sd"; | |
df58fc94 | 9060 | goto ld_st; |
252b5132 | 9061 | } |
252b5132 | 9062 | s = "sw"; |
252b5132 RH |
9063 | |
9064 | ldd_std: | |
9065 | if (offset_expr.X_op != O_symbol | |
9066 | && offset_expr.X_op != O_constant) | |
9067 | { | |
f71d0d44 | 9068 | as_bad (_("Expression too complex")); |
252b5132 RH |
9069 | offset_expr.X_op = O_constant; |
9070 | } | |
9071 | ||
2051e8c4 MR |
9072 | if (HAVE_32BIT_ADDRESSES |
9073 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9074 | { |
9075 | char value [32]; | |
9076 | ||
9077 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9078 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9079 | } |
2051e8c4 | 9080 | |
252b5132 RH |
9081 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9082 | to adjust when loading from memory. We set coproc if we must | |
9083 | load $fn+1 first. */ | |
bdaaa2e1 | 9084 | /* Itbl support may require additional care here. */ |
90ecf173 | 9085 | if (!target_big_endian) |
252b5132 RH |
9086 | coproc = 0; |
9087 | ||
90ecf173 | 9088 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9089 | { |
9090 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9091 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9092 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9093 | If we have a base register, we use this |
9094 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9095 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9096 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9097 | If this is not a GP relative symbol, we want |
9098 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9099 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9100 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9101 | If there is a base register, we add it to $at after the | |
9102 | lui instruction. If there is a constant, we always use | |
9103 | the last case. */ | |
39a59cf8 MR |
9104 | if (offset_expr.X_op == O_symbol |
9105 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9106 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9107 | { |
4d7206a2 | 9108 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9109 | if (breg == 0) |
9110 | { | |
c9914766 | 9111 | tempreg = mips_gp_register; |
252b5132 RH |
9112 | } |
9113 | else | |
9114 | { | |
67c0d1eb | 9115 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9116 | AT, breg, mips_gp_register); |
252b5132 | 9117 | tempreg = AT; |
252b5132 RH |
9118 | used_at = 1; |
9119 | } | |
9120 | ||
beae10d5 | 9121 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9122 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9123 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9124 | offset_expr.X_add_number += 4; |
9125 | ||
9126 | /* Set mips_optimize to 2 to avoid inserting an | |
9127 | undesired nop. */ | |
9128 | hold_mips_optimize = mips_optimize; | |
9129 | mips_optimize = 2; | |
beae10d5 | 9130 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9131 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9132 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9133 | mips_optimize = hold_mips_optimize; |
9134 | ||
4d7206a2 | 9135 | relax_switch (); |
252b5132 | 9136 | |
0970e49e | 9137 | offset_expr.X_add_number -= 4; |
252b5132 | 9138 | } |
8fc2e39e | 9139 | used_at = 1; |
67c0d1eb | 9140 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9141 | if (breg != 0) |
67c0d1eb | 9142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9143 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9144 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9145 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9146 | /* FIXME: How do we handle overflow here? */ |
9147 | offset_expr.X_add_number += 4; | |
beae10d5 | 9148 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9149 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9150 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9151 | if (mips_relax.sequence) |
9152 | relax_end (); | |
bdaaa2e1 | 9153 | } |
0a44bf69 | 9154 | else if (!mips_big_got) |
252b5132 | 9155 | { |
252b5132 RH |
9156 | /* If this is a reference to an external symbol, we want |
9157 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9158 | nop | |
9159 | <op> $treg,0($at) | |
9160 | <op> $treg+1,4($at) | |
9161 | Otherwise we want | |
9162 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9163 | nop | |
9164 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9165 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9166 | If there is a base register we add it to $at before the | |
9167 | lwc1 instructions. If there is a constant we include it | |
9168 | in the lwc1 instructions. */ | |
9169 | used_at = 1; | |
9170 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9171 | if (expr1.X_add_number < -0x8000 |
9172 | || expr1.X_add_number >= 0x8000 - 4) | |
9173 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9174 | load_got_offset (AT, &offset_expr); |
269137b2 | 9175 | load_delay_nop (); |
252b5132 | 9176 | if (breg != 0) |
67c0d1eb | 9177 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9178 | |
9179 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9180 | nop. */ | |
9181 | hold_mips_optimize = mips_optimize; | |
9182 | mips_optimize = 2; | |
4d7206a2 | 9183 | |
beae10d5 | 9184 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9185 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9186 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9187 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9188 | expr1.X_add_number += 4; |
67c0d1eb RS |
9189 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9190 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9191 | relax_switch (); |
67c0d1eb RS |
9192 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9193 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9194 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9195 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9196 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9197 | relax_end (); |
252b5132 | 9198 | |
4d7206a2 | 9199 | mips_optimize = hold_mips_optimize; |
252b5132 | 9200 | } |
0a44bf69 | 9201 | else if (mips_big_got) |
252b5132 | 9202 | { |
67c0d1eb | 9203 | int gpdelay; |
252b5132 RH |
9204 | |
9205 | /* If this is a reference to an external symbol, we want | |
9206 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9207 | addu $at,$at,$gp | |
9208 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9209 | nop | |
9210 | <op> $treg,0($at) | |
9211 | <op> $treg+1,4($at) | |
9212 | Otherwise we want | |
9213 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9214 | nop | |
9215 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9216 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9217 | If there is a base register we add it to $at before the | |
9218 | lwc1 instructions. If there is a constant we include it | |
9219 | in the lwc1 instructions. */ | |
9220 | used_at = 1; | |
9221 | expr1.X_add_number = offset_expr.X_add_number; | |
9222 | offset_expr.X_add_number = 0; | |
9223 | if (expr1.X_add_number < -0x8000 | |
9224 | || expr1.X_add_number >= 0x8000 - 4) | |
9225 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9226 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9227 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9228 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9229 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9230 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9231 | AT, AT, mips_gp_register); |
67c0d1eb | 9232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9233 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9234 | load_delay_nop (); |
252b5132 | 9235 | if (breg != 0) |
67c0d1eb | 9236 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9237 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9238 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9239 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9240 | expr1.X_add_number += 4; |
9241 | ||
9242 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9243 | nop. */ | |
9244 | hold_mips_optimize = mips_optimize; | |
9245 | mips_optimize = 2; | |
beae10d5 | 9246 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9247 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9248 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9249 | mips_optimize = hold_mips_optimize; |
9250 | expr1.X_add_number -= 4; | |
9251 | ||
4d7206a2 RS |
9252 | relax_switch (); |
9253 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9254 | if (gpdelay) |
9255 | macro_build (NULL, "nop", ""); | |
9256 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9257 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9258 | load_delay_nop (); |
252b5132 | 9259 | if (breg != 0) |
67c0d1eb | 9260 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9261 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9262 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9263 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9264 | offset_expr.X_add_number += 4; |
252b5132 RH |
9265 | |
9266 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9267 | nop. */ | |
9268 | hold_mips_optimize = mips_optimize; | |
9269 | mips_optimize = 2; | |
beae10d5 | 9270 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9271 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9272 | BFD_RELOC_LO16, AT); | |
252b5132 | 9273 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9274 | relax_end (); |
252b5132 | 9275 | } |
252b5132 RH |
9276 | else |
9277 | abort (); | |
9278 | ||
252b5132 RH |
9279 | break; |
9280 | ||
9281 | case M_LD_OB: | |
704897fb | 9282 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9283 | goto sd_ob; |
9284 | case M_SD_OB: | |
704897fb | 9285 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9286 | sd_ob: |
4614d845 MR |
9287 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9288 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9289 | breg); | |
704897fb MR |
9290 | if (!HAVE_64BIT_GPRS) |
9291 | { | |
9292 | offset_expr.X_add_number += 4; | |
9293 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9294 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9295 | breg); | |
704897fb | 9296 | } |
8fc2e39e | 9297 | break; |
252b5132 | 9298 | |
dd6a37e7 AP |
9299 | |
9300 | case M_SAA_AB: | |
9301 | ab = 1; | |
9302 | case M_SAA_OB: | |
9303 | s = "saa"; | |
9304 | off0 = 1; | |
9305 | fmt = "t,(b)"; | |
9306 | goto ld_st; | |
9307 | case M_SAAD_AB: | |
9308 | ab = 1; | |
9309 | case M_SAAD_OB: | |
9310 | s = "saad"; | |
9311 | off0 = 1; | |
9312 | fmt = "t,(b)"; | |
9313 | goto ld_st; | |
9314 | ||
252b5132 RH |
9315 | /* New code added to support COPZ instructions. |
9316 | This code builds table entries out of the macros in mip_opcodes. | |
9317 | R4000 uses interlocks to handle coproc delays. | |
9318 | Other chips (like the R3000) require nops to be inserted for delays. | |
9319 | ||
f72c8c98 | 9320 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9321 | In order to fill delay slots for non-interlocked chips, |
9322 | we must have a way to specify delays based on the coprocessor. | |
9323 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9324 | What are the side-effects of the cop instruction? | |
9325 | What cache support might we have and what are its effects? | |
9326 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9327 | What registers are read/set/modified? |
252b5132 RH |
9328 | |
9329 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9330 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9331 | |
9332 | case M_COP0: | |
9333 | s = "c0"; | |
9334 | goto copz; | |
9335 | case M_COP1: | |
9336 | s = "c1"; | |
9337 | goto copz; | |
9338 | case M_COP2: | |
9339 | s = "c2"; | |
9340 | goto copz; | |
9341 | case M_COP3: | |
9342 | s = "c3"; | |
9343 | copz: | |
df58fc94 | 9344 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9345 | /* For now we just do C (same as Cz). The parameter will be |
9346 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9347 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9348 | break; |
252b5132 | 9349 | |
ea1fb5dc | 9350 | case M_MOVE: |
67c0d1eb | 9351 | move_register (dreg, sreg); |
8fc2e39e | 9352 | break; |
ea1fb5dc | 9353 | |
252b5132 RH |
9354 | case M_DMUL: |
9355 | dbl = 1; | |
9356 | case M_MUL: | |
e407c74b NC |
9357 | if (mips_opts.arch == CPU_R5900) |
9358 | { | |
9359 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9360 | } | |
9361 | else | |
9362 | { | |
67c0d1eb | 9363 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9364 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9365 | } |
8fc2e39e | 9366 | break; |
252b5132 RH |
9367 | |
9368 | case M_DMUL_I: | |
9369 | dbl = 1; | |
9370 | case M_MUL_I: | |
9371 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9372 | not trying to be that fancy. GCC should do this for us | |
9373 | anyway. */ | |
8fc2e39e | 9374 | used_at = 1; |
67c0d1eb RS |
9375 | load_register (AT, &imm_expr, dbl); |
9376 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9377 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9378 | break; |
9379 | ||
9380 | case M_DMULO_I: | |
9381 | dbl = 1; | |
9382 | case M_MULO_I: | |
9383 | imm = 1; | |
9384 | goto do_mulo; | |
9385 | ||
9386 | case M_DMULO: | |
9387 | dbl = 1; | |
9388 | case M_MULO: | |
9389 | do_mulo: | |
7d10b47d | 9390 | start_noreorder (); |
8fc2e39e | 9391 | used_at = 1; |
252b5132 | 9392 | if (imm) |
67c0d1eb RS |
9393 | load_register (AT, &imm_expr, dbl); |
9394 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9395 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9396 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9397 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9398 | if (mips_trap) |
df58fc94 | 9399 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9400 | else |
9401 | { | |
df58fc94 RS |
9402 | if (mips_opts.micromips) |
9403 | micromips_label_expr (&label_expr); | |
9404 | else | |
9405 | label_expr.X_add_number = 8; | |
9406 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9407 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9408 | macro_build (NULL, "break", BRK_FMT, 6); |
9409 | if (mips_opts.micromips) | |
9410 | micromips_add_label (); | |
252b5132 | 9411 | } |
7d10b47d | 9412 | end_noreorder (); |
df58fc94 | 9413 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9414 | break; |
9415 | ||
9416 | case M_DMULOU_I: | |
9417 | dbl = 1; | |
9418 | case M_MULOU_I: | |
9419 | imm = 1; | |
9420 | goto do_mulou; | |
9421 | ||
9422 | case M_DMULOU: | |
9423 | dbl = 1; | |
9424 | case M_MULOU: | |
9425 | do_mulou: | |
7d10b47d | 9426 | start_noreorder (); |
8fc2e39e | 9427 | used_at = 1; |
252b5132 | 9428 | if (imm) |
67c0d1eb RS |
9429 | load_register (AT, &imm_expr, dbl); |
9430 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9431 | sreg, imm ? AT : treg); |
df58fc94 RS |
9432 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9433 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9434 | if (mips_trap) |
df58fc94 | 9435 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9436 | else |
9437 | { | |
df58fc94 RS |
9438 | if (mips_opts.micromips) |
9439 | micromips_label_expr (&label_expr); | |
9440 | else | |
9441 | label_expr.X_add_number = 8; | |
9442 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9443 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9444 | macro_build (NULL, "break", BRK_FMT, 6); |
9445 | if (mips_opts.micromips) | |
9446 | micromips_add_label (); | |
252b5132 | 9447 | } |
7d10b47d | 9448 | end_noreorder (); |
252b5132 RH |
9449 | break; |
9450 | ||
771c7ce4 | 9451 | case M_DROL: |
fef14a42 | 9452 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9453 | { |
9454 | if (dreg == sreg) | |
9455 | { | |
9456 | tempreg = AT; | |
9457 | used_at = 1; | |
9458 | } | |
9459 | else | |
9460 | { | |
9461 | tempreg = dreg; | |
82dd0097 | 9462 | } |
67c0d1eb RS |
9463 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9464 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9465 | break; |
82dd0097 | 9466 | } |
8fc2e39e | 9467 | used_at = 1; |
c80c840e | 9468 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9469 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9470 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9471 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9472 | break; |
9473 | ||
252b5132 | 9474 | case M_ROL: |
fef14a42 | 9475 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9476 | { |
9477 | if (dreg == sreg) | |
9478 | { | |
9479 | tempreg = AT; | |
9480 | used_at = 1; | |
9481 | } | |
9482 | else | |
9483 | { | |
9484 | tempreg = dreg; | |
82dd0097 | 9485 | } |
67c0d1eb RS |
9486 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9487 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9488 | break; |
82dd0097 | 9489 | } |
8fc2e39e | 9490 | used_at = 1; |
c80c840e | 9491 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9492 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9493 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9494 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9495 | break; |
9496 | ||
771c7ce4 TS |
9497 | case M_DROL_I: |
9498 | { | |
9499 | unsigned int rot; | |
91d6fa6a NC |
9500 | char *l; |
9501 | char *rr; | |
771c7ce4 TS |
9502 | |
9503 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9504 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9505 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9506 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9507 | { |
9508 | rot = (64 - rot) & 0x3f; | |
9509 | if (rot >= 32) | |
df58fc94 | 9510 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9511 | else |
df58fc94 | 9512 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9513 | break; |
60b63b72 | 9514 | } |
483fc7cd | 9515 | if (rot == 0) |
483fc7cd | 9516 | { |
df58fc94 | 9517 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9518 | break; |
483fc7cd | 9519 | } |
82dd0097 | 9520 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9521 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9522 | rot &= 0x1f; |
8fc2e39e | 9523 | used_at = 1; |
df58fc94 RS |
9524 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9525 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9526 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9527 | } |
9528 | break; | |
9529 | ||
252b5132 | 9530 | case M_ROL_I: |
771c7ce4 TS |
9531 | { |
9532 | unsigned int rot; | |
9533 | ||
9534 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9535 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9536 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9537 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9538 | { |
df58fc94 | 9539 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9540 | break; |
60b63b72 | 9541 | } |
483fc7cd | 9542 | if (rot == 0) |
483fc7cd | 9543 | { |
df58fc94 | 9544 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9545 | break; |
483fc7cd | 9546 | } |
8fc2e39e | 9547 | used_at = 1; |
df58fc94 RS |
9548 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9549 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9550 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9551 | } |
9552 | break; | |
9553 | ||
9554 | case M_DROR: | |
fef14a42 | 9555 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9556 | { |
67c0d1eb | 9557 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9558 | break; |
82dd0097 | 9559 | } |
8fc2e39e | 9560 | used_at = 1; |
c80c840e | 9561 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9562 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9563 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9564 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9565 | break; |
9566 | ||
9567 | case M_ROR: | |
fef14a42 | 9568 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9569 | { |
67c0d1eb | 9570 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9571 | break; |
82dd0097 | 9572 | } |
8fc2e39e | 9573 | used_at = 1; |
c80c840e | 9574 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9575 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9576 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9577 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9578 | break; |
9579 | ||
771c7ce4 TS |
9580 | case M_DROR_I: |
9581 | { | |
9582 | unsigned int rot; | |
91d6fa6a NC |
9583 | char *l; |
9584 | char *rr; | |
771c7ce4 TS |
9585 | |
9586 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9587 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9588 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9589 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9590 | { |
9591 | if (rot >= 32) | |
df58fc94 | 9592 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9593 | else |
df58fc94 | 9594 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9595 | break; |
82dd0097 | 9596 | } |
483fc7cd | 9597 | if (rot == 0) |
483fc7cd | 9598 | { |
df58fc94 | 9599 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9600 | break; |
483fc7cd | 9601 | } |
91d6fa6a | 9602 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9603 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9604 | rot &= 0x1f; | |
8fc2e39e | 9605 | used_at = 1; |
df58fc94 RS |
9606 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9607 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9608 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9609 | } |
9610 | break; | |
9611 | ||
252b5132 | 9612 | case M_ROR_I: |
771c7ce4 TS |
9613 | { |
9614 | unsigned int rot; | |
9615 | ||
9616 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9617 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9618 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9619 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9620 | { |
df58fc94 | 9621 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9622 | break; |
82dd0097 | 9623 | } |
483fc7cd | 9624 | if (rot == 0) |
483fc7cd | 9625 | { |
df58fc94 | 9626 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9627 | break; |
483fc7cd | 9628 | } |
8fc2e39e | 9629 | used_at = 1; |
df58fc94 RS |
9630 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9631 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9632 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9633 | } |
252b5132 RH |
9634 | break; |
9635 | ||
252b5132 RH |
9636 | case M_SEQ: |
9637 | if (sreg == 0) | |
67c0d1eb | 9638 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9639 | else if (treg == 0) |
67c0d1eb | 9640 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9641 | else |
9642 | { | |
67c0d1eb RS |
9643 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9644 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9645 | } |
8fc2e39e | 9646 | break; |
252b5132 RH |
9647 | |
9648 | case M_SEQ_I: | |
9649 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9650 | { | |
67c0d1eb | 9651 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9652 | break; |
252b5132 RH |
9653 | } |
9654 | if (sreg == 0) | |
9655 | { | |
9656 | as_warn (_("Instruction %s: result is always false"), | |
9657 | ip->insn_mo->name); | |
67c0d1eb | 9658 | move_register (dreg, 0); |
8fc2e39e | 9659 | break; |
252b5132 | 9660 | } |
dd3cbb7e NC |
9661 | if (CPU_HAS_SEQ (mips_opts.arch) |
9662 | && -512 <= imm_expr.X_add_number | |
9663 | && imm_expr.X_add_number < 512) | |
9664 | { | |
9665 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9666 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9667 | break; |
9668 | } | |
252b5132 RH |
9669 | if (imm_expr.X_op == O_constant |
9670 | && imm_expr.X_add_number >= 0 | |
9671 | && imm_expr.X_add_number < 0x10000) | |
9672 | { | |
67c0d1eb | 9673 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9674 | } |
9675 | else if (imm_expr.X_op == O_constant | |
9676 | && imm_expr.X_add_number > -0x8000 | |
9677 | && imm_expr.X_add_number < 0) | |
9678 | { | |
9679 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9680 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9681 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9682 | } |
dd3cbb7e NC |
9683 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9684 | { | |
9685 | used_at = 1; | |
9686 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9687 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9688 | break; | |
9689 | } | |
252b5132 RH |
9690 | else |
9691 | { | |
67c0d1eb RS |
9692 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9693 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9694 | used_at = 1; |
9695 | } | |
67c0d1eb | 9696 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9697 | break; |
252b5132 RH |
9698 | |
9699 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9700 | s = "slt"; | |
9701 | goto sge; | |
9702 | case M_SGEU: | |
9703 | s = "sltu"; | |
9704 | sge: | |
67c0d1eb RS |
9705 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9706 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9707 | break; |
252b5132 RH |
9708 | |
9709 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9710 | case M_SGEU_I: | |
9711 | if (imm_expr.X_op == O_constant | |
9712 | && imm_expr.X_add_number >= -0x8000 | |
9713 | && imm_expr.X_add_number < 0x8000) | |
9714 | { | |
67c0d1eb RS |
9715 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9716 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9717 | } |
9718 | else | |
9719 | { | |
67c0d1eb RS |
9720 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9721 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9722 | dreg, sreg, AT); | |
252b5132 RH |
9723 | used_at = 1; |
9724 | } | |
67c0d1eb | 9725 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9726 | break; |
252b5132 RH |
9727 | |
9728 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9729 | s = "slt"; | |
9730 | goto sgt; | |
9731 | case M_SGTU: | |
9732 | s = "sltu"; | |
9733 | sgt: | |
67c0d1eb | 9734 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9735 | break; |
252b5132 RH |
9736 | |
9737 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9738 | s = "slt"; | |
9739 | goto sgti; | |
9740 | case M_SGTU_I: | |
9741 | s = "sltu"; | |
9742 | sgti: | |
8fc2e39e | 9743 | used_at = 1; |
67c0d1eb RS |
9744 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9745 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9746 | break; |
9747 | ||
2396cfb9 | 9748 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9749 | s = "slt"; |
9750 | goto sle; | |
9751 | case M_SLEU: | |
9752 | s = "sltu"; | |
9753 | sle: | |
67c0d1eb RS |
9754 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9755 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9756 | break; |
252b5132 | 9757 | |
2396cfb9 | 9758 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9759 | s = "slt"; |
9760 | goto slei; | |
9761 | case M_SLEU_I: | |
9762 | s = "sltu"; | |
9763 | slei: | |
8fc2e39e | 9764 | used_at = 1; |
67c0d1eb RS |
9765 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9766 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9767 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9768 | break; |
9769 | ||
9770 | case M_SLT_I: | |
9771 | if (imm_expr.X_op == O_constant | |
9772 | && imm_expr.X_add_number >= -0x8000 | |
9773 | && imm_expr.X_add_number < 0x8000) | |
9774 | { | |
67c0d1eb | 9775 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9776 | break; |
252b5132 | 9777 | } |
8fc2e39e | 9778 | used_at = 1; |
67c0d1eb RS |
9779 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9780 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9781 | break; |
9782 | ||
9783 | case M_SLTU_I: | |
9784 | if (imm_expr.X_op == O_constant | |
9785 | && imm_expr.X_add_number >= -0x8000 | |
9786 | && imm_expr.X_add_number < 0x8000) | |
9787 | { | |
67c0d1eb | 9788 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9789 | BFD_RELOC_LO16); |
8fc2e39e | 9790 | break; |
252b5132 | 9791 | } |
8fc2e39e | 9792 | used_at = 1; |
67c0d1eb RS |
9793 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9794 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9795 | break; |
9796 | ||
9797 | case M_SNE: | |
9798 | if (sreg == 0) | |
67c0d1eb | 9799 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9800 | else if (treg == 0) |
67c0d1eb | 9801 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9802 | else |
9803 | { | |
67c0d1eb RS |
9804 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9805 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9806 | } |
8fc2e39e | 9807 | break; |
252b5132 RH |
9808 | |
9809 | case M_SNE_I: | |
9810 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9811 | { | |
67c0d1eb | 9812 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9813 | break; |
252b5132 RH |
9814 | } |
9815 | if (sreg == 0) | |
9816 | { | |
9817 | as_warn (_("Instruction %s: result is always true"), | |
9818 | ip->insn_mo->name); | |
67c0d1eb RS |
9819 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9820 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9821 | break; |
252b5132 | 9822 | } |
dd3cbb7e NC |
9823 | if (CPU_HAS_SEQ (mips_opts.arch) |
9824 | && -512 <= imm_expr.X_add_number | |
9825 | && imm_expr.X_add_number < 512) | |
9826 | { | |
9827 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9828 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9829 | break; |
9830 | } | |
252b5132 RH |
9831 | if (imm_expr.X_op == O_constant |
9832 | && imm_expr.X_add_number >= 0 | |
9833 | && imm_expr.X_add_number < 0x10000) | |
9834 | { | |
67c0d1eb | 9835 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9836 | } |
9837 | else if (imm_expr.X_op == O_constant | |
9838 | && imm_expr.X_add_number > -0x8000 | |
9839 | && imm_expr.X_add_number < 0) | |
9840 | { | |
9841 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9842 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9843 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9844 | } |
dd3cbb7e NC |
9845 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9846 | { | |
9847 | used_at = 1; | |
9848 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9849 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9850 | break; | |
9851 | } | |
252b5132 RH |
9852 | else |
9853 | { | |
67c0d1eb RS |
9854 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9855 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9856 | used_at = 1; |
9857 | } | |
67c0d1eb | 9858 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9859 | break; |
252b5132 | 9860 | |
df58fc94 RS |
9861 | case M_SUB_I: |
9862 | s = "addi"; | |
9863 | s2 = "sub"; | |
9864 | goto do_subi; | |
9865 | case M_SUBU_I: | |
9866 | s = "addiu"; | |
9867 | s2 = "subu"; | |
9868 | goto do_subi; | |
252b5132 RH |
9869 | case M_DSUB_I: |
9870 | dbl = 1; | |
df58fc94 RS |
9871 | s = "daddi"; |
9872 | s2 = "dsub"; | |
9873 | if (!mips_opts.micromips) | |
9874 | goto do_subi; | |
252b5132 | 9875 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9876 | && imm_expr.X_add_number > -0x200 |
9877 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9878 | { |
df58fc94 | 9879 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9880 | break; |
252b5132 | 9881 | } |
df58fc94 | 9882 | goto do_subi_i; |
252b5132 RH |
9883 | case M_DSUBU_I: |
9884 | dbl = 1; | |
df58fc94 RS |
9885 | s = "daddiu"; |
9886 | s2 = "dsubu"; | |
9887 | do_subi: | |
252b5132 RH |
9888 | if (imm_expr.X_op == O_constant |
9889 | && imm_expr.X_add_number > -0x8000 | |
9890 | && imm_expr.X_add_number <= 0x8000) | |
9891 | { | |
9892 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9893 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9894 | break; |
252b5132 | 9895 | } |
df58fc94 | 9896 | do_subi_i: |
8fc2e39e | 9897 | used_at = 1; |
67c0d1eb | 9898 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9899 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9900 | break; |
9901 | ||
9902 | case M_TEQ_I: | |
9903 | s = "teq"; | |
9904 | goto trap; | |
9905 | case M_TGE_I: | |
9906 | s = "tge"; | |
9907 | goto trap; | |
9908 | case M_TGEU_I: | |
9909 | s = "tgeu"; | |
9910 | goto trap; | |
9911 | case M_TLT_I: | |
9912 | s = "tlt"; | |
9913 | goto trap; | |
9914 | case M_TLTU_I: | |
9915 | s = "tltu"; | |
9916 | goto trap; | |
9917 | case M_TNE_I: | |
9918 | s = "tne"; | |
9919 | trap: | |
8fc2e39e | 9920 | used_at = 1; |
67c0d1eb RS |
9921 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9922 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9923 | break; |
9924 | ||
252b5132 | 9925 | case M_TRUNCWS: |
43841e91 | 9926 | case M_TRUNCWD: |
df58fc94 | 9927 | gas_assert (!mips_opts.micromips); |
e407c74b | 9928 | gas_assert ((mips_opts.isa == ISA_MIPS1) || (mips_opts.arch == CPU_R5900)); |
8fc2e39e | 9929 | used_at = 1; |
252b5132 RH |
9930 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9931 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9932 | ||
9933 | /* | |
9934 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9935 | * or is there a reason for it? | |
9936 | */ | |
7d10b47d | 9937 | start_noreorder (); |
67c0d1eb RS |
9938 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9939 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9940 | macro_build (NULL, "nop", ""); | |
252b5132 | 9941 | expr1.X_add_number = 3; |
67c0d1eb | 9942 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9943 | expr1.X_add_number = 2; |
67c0d1eb RS |
9944 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9945 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9946 | macro_build (NULL, "nop", ""); | |
9947 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9948 | dreg, sreg); | |
9949 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9950 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9951 | end_noreorder (); |
252b5132 RH |
9952 | break; |
9953 | ||
df58fc94 RS |
9954 | case M_ULH_A: |
9955 | ab = 1; | |
252b5132 RH |
9956 | case M_ULH: |
9957 | s = "lb"; | |
df58fc94 RS |
9958 | s2 = "lbu"; |
9959 | off = 1; | |
9960 | goto uld_st; | |
9961 | case M_ULHU_A: | |
9962 | ab = 1; | |
252b5132 RH |
9963 | case M_ULHU: |
9964 | s = "lbu"; | |
df58fc94 RS |
9965 | s2 = "lbu"; |
9966 | off = 1; | |
9967 | goto uld_st; | |
9968 | case M_ULW_A: | |
9969 | ab = 1; | |
9970 | case M_ULW: | |
9971 | s = "lwl"; | |
9972 | s2 = "lwr"; | |
9973 | off12 = mips_opts.micromips; | |
9974 | off = 3; | |
9975 | goto uld_st; | |
9976 | case M_ULD_A: | |
9977 | ab = 1; | |
252b5132 RH |
9978 | case M_ULD: |
9979 | s = "ldl"; | |
9980 | s2 = "ldr"; | |
df58fc94 | 9981 | off12 = mips_opts.micromips; |
252b5132 | 9982 | off = 7; |
df58fc94 RS |
9983 | goto uld_st; |
9984 | case M_USH_A: | |
9985 | ab = 1; | |
9986 | case M_USH: | |
9987 | s = "sb"; | |
9988 | s2 = "sb"; | |
9989 | off = 1; | |
9990 | ust = 1; | |
9991 | goto uld_st; | |
9992 | case M_USW_A: | |
9993 | ab = 1; | |
9994 | case M_USW: | |
9995 | s = "swl"; | |
9996 | s2 = "swr"; | |
9997 | off12 = mips_opts.micromips; | |
252b5132 | 9998 | off = 3; |
df58fc94 RS |
9999 | ust = 1; |
10000 | goto uld_st; | |
10001 | case M_USD_A: | |
10002 | ab = 1; | |
10003 | case M_USD: | |
10004 | s = "sdl"; | |
10005 | s2 = "sdr"; | |
10006 | off12 = mips_opts.micromips; | |
10007 | off = 7; | |
10008 | ust = 1; | |
10009 | ||
10010 | uld_st: | |
10011 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10012 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10013 | |
10014 | ep = &offset_expr; | |
10015 | expr1.X_add_number = 0; | |
10016 | if (ab) | |
10017 | { | |
10018 | used_at = 1; | |
10019 | tempreg = AT; | |
10020 | load_address (tempreg, ep, &used_at); | |
10021 | if (breg != 0) | |
10022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10023 | tempreg, tempreg, breg); | |
10024 | breg = tempreg; | |
10025 | tempreg = treg; | |
10026 | ep = &expr1; | |
10027 | } | |
10028 | else if (off12 | |
10029 | && (offset_expr.X_op != O_constant | |
10030 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10031 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10032 | { | |
10033 | used_at = 1; | |
10034 | tempreg = AT; | |
10035 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10036 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10037 | breg = tempreg; | |
10038 | tempreg = treg; | |
10039 | ep = &expr1; | |
10040 | } | |
10041 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10042 | { |
10043 | used_at = 1; | |
10044 | tempreg = AT; | |
10045 | } | |
252b5132 | 10046 | else |
df58fc94 | 10047 | tempreg = treg; |
af22f5b2 | 10048 | |
df58fc94 RS |
10049 | if (off == 1) |
10050 | goto ulh_sh; | |
252b5132 | 10051 | |
90ecf173 | 10052 | if (!target_big_endian) |
df58fc94 RS |
10053 | ep->X_add_number += off; |
10054 | if (!off12) | |
10055 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10056 | else |
df58fc94 RS |
10057 | macro_build (NULL, s, "t,~(b)", |
10058 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10059 | ||
90ecf173 | 10060 | if (!target_big_endian) |
df58fc94 | 10061 | ep->X_add_number -= off; |
252b5132 | 10062 | else |
df58fc94 RS |
10063 | ep->X_add_number += off; |
10064 | if (!off12) | |
10065 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10066 | else | |
10067 | macro_build (NULL, s2, "t,~(b)", | |
10068 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10069 | |
df58fc94 RS |
10070 | /* If necessary, move the result in tempreg to the final destination. */ |
10071 | if (!ust && treg != tempreg) | |
10072 | { | |
10073 | /* Protect second load's delay slot. */ | |
10074 | load_delay_nop (); | |
10075 | move_register (treg, tempreg); | |
10076 | } | |
8fc2e39e | 10077 | break; |
252b5132 | 10078 | |
df58fc94 | 10079 | ulh_sh: |
d6bc6245 | 10080 | used_at = 1; |
df58fc94 RS |
10081 | if (target_big_endian == ust) |
10082 | ep->X_add_number += off; | |
10083 | tempreg = ust || ab ? treg : AT; | |
10084 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10085 | ||
10086 | /* For halfword transfers we need a temporary register to shuffle | |
10087 | bytes. Unfortunately for M_USH_A we have none available before | |
10088 | the next store as AT holds the base address. We deal with this | |
10089 | case by clobbering TREG and then restoring it as with ULH. */ | |
10090 | tempreg = ust == ab ? treg : AT; | |
10091 | if (ust) | |
10092 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10093 | ||
10094 | if (target_big_endian == ust) | |
10095 | ep->X_add_number -= off; | |
252b5132 | 10096 | else |
df58fc94 RS |
10097 | ep->X_add_number += off; |
10098 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10099 | |
df58fc94 RS |
10100 | /* For M_USH_A re-retrieve the LSB. */ |
10101 | if (ust && ab) | |
10102 | { | |
10103 | if (target_big_endian) | |
10104 | ep->X_add_number += off; | |
10105 | else | |
10106 | ep->X_add_number -= off; | |
10107 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10108 | } | |
10109 | /* For ULH and M_USH_A OR the LSB in. */ | |
10110 | if (!ust || ab) | |
10111 | { | |
10112 | tempreg = !ab ? AT : treg; | |
10113 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10114 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10115 | } | |
252b5132 RH |
10116 | break; |
10117 | ||
10118 | default: | |
10119 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10120 | are added dynamically. */ |
252b5132 RH |
10121 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10122 | break; | |
10123 | } | |
741fe287 | 10124 | if (!mips_opts.at && used_at) |
8fc2e39e | 10125 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10126 | } |
10127 | ||
10128 | /* Implement macros in mips16 mode. */ | |
10129 | ||
10130 | static void | |
17a2f251 | 10131 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10132 | { |
10133 | int mask; | |
10134 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10135 | expressionS expr1; |
10136 | int dbl; | |
10137 | const char *s, *s2, *s3; | |
10138 | ||
10139 | mask = ip->insn_mo->mask; | |
10140 | ||
bf12938e RS |
10141 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10142 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10143 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10144 | |
252b5132 RH |
10145 | expr1.X_op = O_constant; |
10146 | expr1.X_op_symbol = NULL; | |
10147 | expr1.X_add_symbol = NULL; | |
10148 | expr1.X_add_number = 1; | |
10149 | ||
10150 | dbl = 0; | |
10151 | ||
10152 | switch (mask) | |
10153 | { | |
10154 | default: | |
10155 | internalError (); | |
10156 | ||
10157 | case M_DDIV_3: | |
10158 | dbl = 1; | |
10159 | case M_DIV_3: | |
10160 | s = "mflo"; | |
10161 | goto do_div3; | |
10162 | case M_DREM_3: | |
10163 | dbl = 1; | |
10164 | case M_REM_3: | |
10165 | s = "mfhi"; | |
10166 | do_div3: | |
7d10b47d | 10167 | start_noreorder (); |
67c0d1eb | 10168 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10169 | expr1.X_add_number = 2; |
67c0d1eb RS |
10170 | macro_build (&expr1, "bnez", "x,p", yreg); |
10171 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10172 | |
252b5132 RH |
10173 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10174 | since that causes an overflow. We should do that as well, | |
10175 | but I don't see how to do the comparisons without a temporary | |
10176 | register. */ | |
7d10b47d | 10177 | end_noreorder (); |
67c0d1eb | 10178 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10179 | break; |
10180 | ||
10181 | case M_DIVU_3: | |
10182 | s = "divu"; | |
10183 | s2 = "mflo"; | |
10184 | goto do_divu3; | |
10185 | case M_REMU_3: | |
10186 | s = "divu"; | |
10187 | s2 = "mfhi"; | |
10188 | goto do_divu3; | |
10189 | case M_DDIVU_3: | |
10190 | s = "ddivu"; | |
10191 | s2 = "mflo"; | |
10192 | goto do_divu3; | |
10193 | case M_DREMU_3: | |
10194 | s = "ddivu"; | |
10195 | s2 = "mfhi"; | |
10196 | do_divu3: | |
7d10b47d | 10197 | start_noreorder (); |
67c0d1eb | 10198 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10199 | expr1.X_add_number = 2; |
67c0d1eb RS |
10200 | macro_build (&expr1, "bnez", "x,p", yreg); |
10201 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10202 | end_noreorder (); |
67c0d1eb | 10203 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10204 | break; |
10205 | ||
10206 | case M_DMUL: | |
10207 | dbl = 1; | |
10208 | case M_MUL: | |
67c0d1eb RS |
10209 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10210 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10211 | break; |
252b5132 RH |
10212 | |
10213 | case M_DSUBU_I: | |
10214 | dbl = 1; | |
10215 | goto do_subu; | |
10216 | case M_SUBU_I: | |
10217 | do_subu: | |
10218 | if (imm_expr.X_op != O_constant) | |
10219 | as_bad (_("Unsupported large constant")); | |
10220 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10221 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10222 | break; |
10223 | ||
10224 | case M_SUBU_I_2: | |
10225 | if (imm_expr.X_op != O_constant) | |
10226 | as_bad (_("Unsupported large constant")); | |
10227 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10228 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10229 | break; |
10230 | ||
10231 | case M_DSUBU_I_2: | |
10232 | if (imm_expr.X_op != O_constant) | |
10233 | as_bad (_("Unsupported large constant")); | |
10234 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10235 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10236 | break; |
10237 | ||
10238 | case M_BEQ: | |
10239 | s = "cmp"; | |
10240 | s2 = "bteqz"; | |
10241 | goto do_branch; | |
10242 | case M_BNE: | |
10243 | s = "cmp"; | |
10244 | s2 = "btnez"; | |
10245 | goto do_branch; | |
10246 | case M_BLT: | |
10247 | s = "slt"; | |
10248 | s2 = "btnez"; | |
10249 | goto do_branch; | |
10250 | case M_BLTU: | |
10251 | s = "sltu"; | |
10252 | s2 = "btnez"; | |
10253 | goto do_branch; | |
10254 | case M_BLE: | |
10255 | s = "slt"; | |
10256 | s2 = "bteqz"; | |
10257 | goto do_reverse_branch; | |
10258 | case M_BLEU: | |
10259 | s = "sltu"; | |
10260 | s2 = "bteqz"; | |
10261 | goto do_reverse_branch; | |
10262 | case M_BGE: | |
10263 | s = "slt"; | |
10264 | s2 = "bteqz"; | |
10265 | goto do_branch; | |
10266 | case M_BGEU: | |
10267 | s = "sltu"; | |
10268 | s2 = "bteqz"; | |
10269 | goto do_branch; | |
10270 | case M_BGT: | |
10271 | s = "slt"; | |
10272 | s2 = "btnez"; | |
10273 | goto do_reverse_branch; | |
10274 | case M_BGTU: | |
10275 | s = "sltu"; | |
10276 | s2 = "btnez"; | |
10277 | ||
10278 | do_reverse_branch: | |
10279 | tmp = xreg; | |
10280 | xreg = yreg; | |
10281 | yreg = tmp; | |
10282 | ||
10283 | do_branch: | |
67c0d1eb RS |
10284 | macro_build (NULL, s, "x,y", xreg, yreg); |
10285 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10286 | break; |
10287 | ||
10288 | case M_BEQ_I: | |
10289 | s = "cmpi"; | |
10290 | s2 = "bteqz"; | |
10291 | s3 = "x,U"; | |
10292 | goto do_branch_i; | |
10293 | case M_BNE_I: | |
10294 | s = "cmpi"; | |
10295 | s2 = "btnez"; | |
10296 | s3 = "x,U"; | |
10297 | goto do_branch_i; | |
10298 | case M_BLT_I: | |
10299 | s = "slti"; | |
10300 | s2 = "btnez"; | |
10301 | s3 = "x,8"; | |
10302 | goto do_branch_i; | |
10303 | case M_BLTU_I: | |
10304 | s = "sltiu"; | |
10305 | s2 = "btnez"; | |
10306 | s3 = "x,8"; | |
10307 | goto do_branch_i; | |
10308 | case M_BLE_I: | |
10309 | s = "slti"; | |
10310 | s2 = "btnez"; | |
10311 | s3 = "x,8"; | |
10312 | goto do_addone_branch_i; | |
10313 | case M_BLEU_I: | |
10314 | s = "sltiu"; | |
10315 | s2 = "btnez"; | |
10316 | s3 = "x,8"; | |
10317 | goto do_addone_branch_i; | |
10318 | case M_BGE_I: | |
10319 | s = "slti"; | |
10320 | s2 = "bteqz"; | |
10321 | s3 = "x,8"; | |
10322 | goto do_branch_i; | |
10323 | case M_BGEU_I: | |
10324 | s = "sltiu"; | |
10325 | s2 = "bteqz"; | |
10326 | s3 = "x,8"; | |
10327 | goto do_branch_i; | |
10328 | case M_BGT_I: | |
10329 | s = "slti"; | |
10330 | s2 = "bteqz"; | |
10331 | s3 = "x,8"; | |
10332 | goto do_addone_branch_i; | |
10333 | case M_BGTU_I: | |
10334 | s = "sltiu"; | |
10335 | s2 = "bteqz"; | |
10336 | s3 = "x,8"; | |
10337 | ||
10338 | do_addone_branch_i: | |
10339 | if (imm_expr.X_op != O_constant) | |
10340 | as_bad (_("Unsupported large constant")); | |
10341 | ++imm_expr.X_add_number; | |
10342 | ||
10343 | do_branch_i: | |
67c0d1eb RS |
10344 | macro_build (&imm_expr, s, s3, xreg); |
10345 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10346 | break; |
10347 | ||
10348 | case M_ABS: | |
10349 | expr1.X_add_number = 0; | |
67c0d1eb | 10350 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10351 | if (xreg != yreg) |
67c0d1eb | 10352 | move_register (xreg, yreg); |
252b5132 | 10353 | expr1.X_add_number = 2; |
67c0d1eb RS |
10354 | macro_build (&expr1, "bteqz", "p"); |
10355 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10356 | } |
10357 | } | |
10358 | ||
10359 | /* For consistency checking, verify that all bits are specified either | |
10360 | by the match/mask part of the instruction definition, or by the | |
10361 | operand list. */ | |
10362 | static int | |
17a2f251 | 10363 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10364 | { |
10365 | const char *p = opc->args; | |
10366 | char c; | |
10367 | unsigned long used_bits = opc->mask; | |
10368 | ||
10369 | if ((used_bits & opc->match) != opc->match) | |
10370 | { | |
10371 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10372 | opc->name, opc->args); | |
10373 | return 0; | |
10374 | } | |
10375 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10376 | while (*p) | |
10377 | switch (c = *p++) | |
10378 | { | |
10379 | case ',': break; | |
10380 | case '(': break; | |
10381 | case ')': break; | |
af7ee8bf CD |
10382 | case '+': |
10383 | switch (c = *p++) | |
10384 | { | |
9bcd4f99 TS |
10385 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10386 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10387 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10388 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10389 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10390 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10391 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10392 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10393 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10394 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10395 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10396 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10397 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10398 | case 'I': break; | |
ef2e4d86 CF |
10399 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10400 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10401 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10402 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10403 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10404 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10405 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10406 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10407 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10408 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10409 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10410 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10411 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10412 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10413 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10414 | |
af7ee8bf CD |
10415 | default: |
10416 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10417 | c, opc->name, opc->args); | |
10418 | return 0; | |
10419 | } | |
10420 | break; | |
252b5132 RH |
10421 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10422 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10423 | case 'A': break; | |
4372b673 | 10424 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10425 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10426 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10427 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10428 | case 'F': break; | |
10429 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10430 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10431 | case 'I': break; |
e972090a | 10432 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10433 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10434 | case 'L': break; |
10435 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10436 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10437 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10438 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10439 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10440 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10441 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10442 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10443 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10444 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10445 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10446 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10447 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10448 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10449 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10450 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10451 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10452 | case 'f': break; | |
10453 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10454 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10455 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10456 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10457 | case 'l': break; | |
10458 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10459 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10460 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10461 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10462 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10463 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10464 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10465 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10466 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10467 | case 'x': break; | |
10468 | case 'z': break; | |
10469 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10470 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10471 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10472 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10473 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10474 | case '[': break; | |
10475 | case ']': break; | |
620edafd | 10476 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10477 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10478 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10479 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10480 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10481 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10482 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10483 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10484 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10485 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10486 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10487 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10488 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10489 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10490 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10491 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10492 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10493 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10494 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10495 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10496 | default: |
10497 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10498 | c, opc->name, opc->args); | |
10499 | return 0; | |
10500 | } | |
10501 | #undef USE_BITS | |
10502 | if (used_bits != 0xffffffff) | |
10503 | { | |
10504 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10505 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10506 | return 0; | |
10507 | } | |
10508 | return 1; | |
10509 | } | |
10510 | ||
df58fc94 RS |
10511 | /* For consistency checking, verify that the length implied matches the |
10512 | major opcode and that all bits are specified either by the match/mask | |
10513 | part of the instruction definition, or by the operand list. */ | |
10514 | ||
10515 | static int | |
10516 | validate_micromips_insn (const struct mips_opcode *opc) | |
10517 | { | |
10518 | unsigned long match = opc->match; | |
10519 | unsigned long mask = opc->mask; | |
10520 | const char *p = opc->args; | |
10521 | unsigned long insn_bits; | |
10522 | unsigned long used_bits; | |
10523 | unsigned long major; | |
10524 | unsigned int length; | |
10525 | char e; | |
10526 | char c; | |
10527 | ||
10528 | if ((mask & match) != match) | |
10529 | { | |
10530 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10531 | opc->name, opc->args); | |
10532 | return 0; | |
10533 | } | |
10534 | length = micromips_insn_length (opc); | |
10535 | if (length != 2 && length != 4) | |
10536 | { | |
10537 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10538 | "%s %s"), length, opc->name, opc->args); | |
10539 | return 0; | |
10540 | } | |
10541 | major = match >> (10 + 8 * (length - 2)); | |
10542 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10543 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10544 | { | |
10545 | as_bad (_("Internal error: bad microMIPS opcode " | |
10546 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10547 | return 0; | |
10548 | } | |
10549 | ||
10550 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10551 | insn_bits = 1 << 4 * length; | |
10552 | insn_bits <<= 4 * length; | |
10553 | insn_bits -= 1; | |
10554 | used_bits = mask; | |
10555 | #define USE_BITS(field) \ | |
10556 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10557 | while (*p) | |
10558 | switch (c = *p++) | |
10559 | { | |
10560 | case ',': break; | |
10561 | case '(': break; | |
10562 | case ')': break; | |
10563 | case '+': | |
10564 | e = c; | |
10565 | switch (c = *p++) | |
10566 | { | |
10567 | case 'A': USE_BITS (EXTLSB); break; | |
10568 | case 'B': USE_BITS (INSMSB); break; | |
10569 | case 'C': USE_BITS (EXTMSBD); break; | |
10570 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10571 | case 'E': USE_BITS (EXTLSB); break; | |
10572 | case 'F': USE_BITS (INSMSB); break; | |
10573 | case 'G': USE_BITS (EXTMSBD); break; | |
10574 | case 'H': USE_BITS (EXTMSBD); break; | |
10575 | default: | |
10576 | as_bad (_("Internal error: bad mips opcode " | |
10577 | "(unknown extension operand type `%c%c'): %s %s"), | |
10578 | e, c, opc->name, opc->args); | |
10579 | return 0; | |
10580 | } | |
10581 | break; | |
10582 | case 'm': | |
10583 | e = c; | |
10584 | switch (c = *p++) | |
10585 | { | |
10586 | case 'A': USE_BITS (IMMA); break; | |
10587 | case 'B': USE_BITS (IMMB); break; | |
10588 | case 'C': USE_BITS (IMMC); break; | |
10589 | case 'D': USE_BITS (IMMD); break; | |
10590 | case 'E': USE_BITS (IMME); break; | |
10591 | case 'F': USE_BITS (IMMF); break; | |
10592 | case 'G': USE_BITS (IMMG); break; | |
10593 | case 'H': USE_BITS (IMMH); break; | |
10594 | case 'I': USE_BITS (IMMI); break; | |
10595 | case 'J': USE_BITS (IMMJ); break; | |
10596 | case 'L': USE_BITS (IMML); break; | |
10597 | case 'M': USE_BITS (IMMM); break; | |
10598 | case 'N': USE_BITS (IMMN); break; | |
10599 | case 'O': USE_BITS (IMMO); break; | |
10600 | case 'P': USE_BITS (IMMP); break; | |
10601 | case 'Q': USE_BITS (IMMQ); break; | |
10602 | case 'U': USE_BITS (IMMU); break; | |
10603 | case 'W': USE_BITS (IMMW); break; | |
10604 | case 'X': USE_BITS (IMMX); break; | |
10605 | case 'Y': USE_BITS (IMMY); break; | |
10606 | case 'Z': break; | |
10607 | case 'a': break; | |
10608 | case 'b': USE_BITS (MB); break; | |
10609 | case 'c': USE_BITS (MC); break; | |
10610 | case 'd': USE_BITS (MD); break; | |
10611 | case 'e': USE_BITS (ME); break; | |
10612 | case 'f': USE_BITS (MF); break; | |
10613 | case 'g': USE_BITS (MG); break; | |
10614 | case 'h': USE_BITS (MH); break; | |
10615 | case 'i': USE_BITS (MI); break; | |
10616 | case 'j': USE_BITS (MJ); break; | |
10617 | case 'l': USE_BITS (ML); break; | |
10618 | case 'm': USE_BITS (MM); break; | |
10619 | case 'n': USE_BITS (MN); break; | |
10620 | case 'p': USE_BITS (MP); break; | |
10621 | case 'q': USE_BITS (MQ); break; | |
10622 | case 'r': break; | |
10623 | case 's': break; | |
10624 | case 't': break; | |
10625 | case 'x': break; | |
10626 | case 'y': break; | |
10627 | case 'z': break; | |
10628 | default: | |
10629 | as_bad (_("Internal error: bad mips opcode " | |
10630 | "(unknown extension operand type `%c%c'): %s %s"), | |
10631 | e, c, opc->name, opc->args); | |
10632 | return 0; | |
10633 | } | |
10634 | break; | |
10635 | case '.': USE_BITS (OFFSET10); break; | |
10636 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10637 | case '2': USE_BITS (BP); break; |
10638 | case '3': USE_BITS (SA3); break; | |
10639 | case '4': USE_BITS (SA4); break; | |
10640 | case '5': USE_BITS (IMM8); break; | |
10641 | case '6': USE_BITS (RS); break; | |
10642 | case '7': USE_BITS (DSPACC); break; | |
10643 | case '8': USE_BITS (WRDSP); break; | |
10644 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10645 | case '<': USE_BITS (SHAMT); break; |
10646 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10647 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10648 | case 'B': USE_BITS (CODE10); break; |
10649 | case 'C': USE_BITS (COPZ); break; | |
10650 | case 'D': USE_BITS (FD); break; | |
10651 | case 'E': USE_BITS (RT); break; | |
10652 | case 'G': USE_BITS (RS); break; | |
444d75be | 10653 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10654 | case 'K': USE_BITS (RS); break; |
10655 | case 'M': USE_BITS (CCC); break; | |
10656 | case 'N': USE_BITS (BCC); break; | |
10657 | case 'R': USE_BITS (FR); break; | |
10658 | case 'S': USE_BITS (FS); break; | |
10659 | case 'T': USE_BITS (FT); break; | |
10660 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10661 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10662 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10663 | case 'a': USE_BITS (TARGET); break; |
10664 | case 'b': USE_BITS (RS); break; | |
10665 | case 'c': USE_BITS (CODE); break; | |
10666 | case 'd': USE_BITS (RD); break; | |
10667 | case 'h': USE_BITS (PREFX); break; | |
10668 | case 'i': USE_BITS (IMMEDIATE); break; | |
10669 | case 'j': USE_BITS (DELTA); break; | |
10670 | case 'k': USE_BITS (CACHE); break; | |
10671 | case 'n': USE_BITS (RT); break; | |
10672 | case 'o': USE_BITS (DELTA); break; | |
10673 | case 'p': USE_BITS (DELTA); break; | |
10674 | case 'q': USE_BITS (CODE2); break; | |
10675 | case 'r': USE_BITS (RS); break; | |
10676 | case 's': USE_BITS (RS); break; | |
10677 | case 't': USE_BITS (RT); break; | |
10678 | case 'u': USE_BITS (IMMEDIATE); break; | |
10679 | case 'v': USE_BITS (RS); break; | |
10680 | case 'w': USE_BITS (RT); break; | |
10681 | case 'y': USE_BITS (RS3); break; | |
10682 | case 'z': break; | |
10683 | case '|': USE_BITS (TRAP); break; | |
10684 | case '~': USE_BITS (OFFSET12); break; | |
10685 | default: | |
10686 | as_bad (_("Internal error: bad microMIPS opcode " | |
10687 | "(unknown operand type `%c'): %s %s"), | |
10688 | c, opc->name, opc->args); | |
10689 | return 0; | |
10690 | } | |
10691 | #undef USE_BITS | |
10692 | if (used_bits != insn_bits) | |
10693 | { | |
10694 | if (~used_bits & insn_bits) | |
10695 | as_bad (_("Internal error: bad microMIPS opcode " | |
10696 | "(bits 0x%lx undefined): %s %s"), | |
10697 | ~used_bits & insn_bits, opc->name, opc->args); | |
10698 | if (used_bits & ~insn_bits) | |
10699 | as_bad (_("Internal error: bad microMIPS opcode " | |
10700 | "(bits 0x%lx defined): %s %s"), | |
10701 | used_bits & ~insn_bits, opc->name, opc->args); | |
10702 | return 0; | |
10703 | } | |
10704 | return 1; | |
10705 | } | |
10706 | ||
9bcd4f99 TS |
10707 | /* UDI immediates. */ |
10708 | struct mips_immed { | |
10709 | char type; | |
10710 | unsigned int shift; | |
10711 | unsigned long mask; | |
10712 | const char * desc; | |
10713 | }; | |
10714 | ||
10715 | static const struct mips_immed mips_immed[] = { | |
10716 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10717 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10718 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10719 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10720 | { 0,0,0,0 } | |
10721 | }; | |
10722 | ||
7455baf8 TS |
10723 | /* Check whether an odd floating-point register is allowed. */ |
10724 | static int | |
10725 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10726 | { | |
10727 | const char *s = insn->name; | |
10728 | ||
10729 | if (insn->pinfo == INSN_MACRO) | |
10730 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10731 | return 1; | |
10732 | ||
e407c74b | 10733 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
10734 | { |
10735 | /* Allow odd registers for single-precision ops. */ | |
10736 | switch (insn->pinfo & (FP_S | FP_D)) | |
10737 | { | |
10738 | case FP_S: | |
10739 | case 0: | |
10740 | return 1; /* both single precision - ok */ | |
10741 | case FP_D: | |
10742 | return 0; /* both double precision - fail */ | |
10743 | default: | |
10744 | break; | |
10745 | } | |
10746 | ||
10747 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10748 | s = strchr (insn->name, '.'); | |
10749 | if (argnum == 2) | |
10750 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10751 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10752 | } | |
10753 | ||
10754 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10755 | if ((insn->pinfo & FP_S) | |
10756 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10757 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10758 | return 1; | |
10759 | ||
10760 | return 0; | |
10761 | } | |
10762 | ||
df58fc94 RS |
10763 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10764 | taking bits from BIT up. */ | |
10765 | static int | |
10766 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10767 | { | |
10768 | return (ep->X_op == O_constant | |
10769 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10770 | && ep->X_add_number >= min << bit | |
10771 | && ep->X_add_number < max << bit); | |
10772 | } | |
10773 | ||
252b5132 RH |
10774 | /* This routine assembles an instruction into its binary format. As a |
10775 | side effect, it sets one of the global variables imm_reloc or | |
10776 | offset_reloc to the type of relocation to do if one of the operands | |
10777 | is an address expression. */ | |
10778 | ||
10779 | static void | |
17a2f251 | 10780 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10781 | { |
df58fc94 RS |
10782 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10783 | bfd_boolean need_delay_slot_ok = TRUE; | |
10784 | struct mips_opcode *firstinsn = NULL; | |
10785 | const struct mips_opcode *past; | |
10786 | struct hash_control *hash; | |
252b5132 RH |
10787 | char *s; |
10788 | const char *args; | |
43841e91 | 10789 | char c = 0; |
252b5132 RH |
10790 | struct mips_opcode *insn; |
10791 | char *argsStart; | |
10792 | unsigned int regno; | |
34224acf | 10793 | unsigned int lastregno; |
df58fc94 | 10794 | unsigned int destregno = 0; |
af7ee8bf | 10795 | unsigned int lastpos = 0; |
071742cf | 10796 | unsigned int limlo, limhi; |
252b5132 | 10797 | char *s_reset; |
74cd071d | 10798 | offsetT min_range, max_range; |
df58fc94 | 10799 | long opend; |
a40bc9dd | 10800 | char *name; |
707bfff6 TS |
10801 | int argnum; |
10802 | unsigned int rtype; | |
df58fc94 | 10803 | char *dot; |
a40bc9dd | 10804 | long end; |
252b5132 RH |
10805 | |
10806 | insn_error = NULL; | |
10807 | ||
df58fc94 RS |
10808 | if (mips_opts.micromips) |
10809 | { | |
10810 | hash = micromips_op_hash; | |
10811 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10812 | } | |
10813 | else | |
10814 | { | |
10815 | hash = op_hash; | |
10816 | past = &mips_opcodes[NUMOPCODES]; | |
10817 | } | |
10818 | forced_insn_length = 0; | |
252b5132 | 10819 | insn = NULL; |
252b5132 | 10820 | |
df58fc94 | 10821 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10822 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10823 | continue; | |
bdaaa2e1 | 10824 | |
a40bc9dd RS |
10825 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10826 | name = alloca (end + 1); | |
10827 | memcpy (name, str, end); | |
10828 | name[end] = '\0'; | |
252b5132 | 10829 | |
df58fc94 RS |
10830 | for (;;) |
10831 | { | |
10832 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10833 | ||
10834 | if (insn != NULL || !mips_opts.micromips) | |
10835 | break; | |
10836 | if (forced_insn_length) | |
10837 | break; | |
10838 | ||
10839 | /* See if there's an instruction size override suffix, | |
10840 | either `16' or `32', at the end of the mnemonic proper, | |
10841 | that defines the operation, i.e. before the first `.' | |
10842 | character if any. Strip it and retry. */ | |
10843 | dot = strchr (name, '.'); | |
10844 | opend = dot != NULL ? dot - name : end; | |
10845 | if (opend < 3) | |
10846 | break; | |
10847 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10848 | forced_insn_length = 2; | |
10849 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10850 | forced_insn_length = 4; | |
10851 | else | |
10852 | break; | |
10853 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10854 | } | |
252b5132 RH |
10855 | if (insn == NULL) |
10856 | { | |
a40bc9dd RS |
10857 | insn_error = _("Unrecognized opcode"); |
10858 | return; | |
252b5132 RH |
10859 | } |
10860 | ||
df58fc94 RS |
10861 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10862 | we make up to two passes over the relevant fragment of the opcode | |
10863 | table. First we try instructions that meet the delay slot's length | |
10864 | requirement. If none matched, then we retry with the remaining ones | |
10865 | and if one matches, then we use it and then issue an appropriate | |
10866 | warning later on. */ | |
a40bc9dd | 10867 | argsStart = s = str + end; |
252b5132 RH |
10868 | for (;;) |
10869 | { | |
df58fc94 RS |
10870 | bfd_boolean delay_slot_ok; |
10871 | bfd_boolean size_ok; | |
b34976b6 | 10872 | bfd_boolean ok; |
252b5132 | 10873 | |
a40bc9dd | 10874 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10875 | |
f79e2745 | 10876 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10877 | size_ok = is_size_valid (insn); |
10878 | delay_slot_ok = is_delay_slot_valid (insn); | |
10879 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10880 | { |
df58fc94 RS |
10881 | firstinsn = insn; |
10882 | wrong_delay_slot_insns = TRUE; | |
10883 | } | |
10884 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10885 | { | |
10886 | static char buf[256]; | |
10887 | ||
10888 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10889 | { |
10890 | ++insn; | |
10891 | continue; | |
10892 | } | |
df58fc94 | 10893 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10894 | { |
df58fc94 RS |
10895 | gas_assert (firstinsn); |
10896 | need_delay_slot_ok = FALSE; | |
10897 | past = insn + 1; | |
10898 | insn = firstinsn; | |
10899 | continue; | |
252b5132 | 10900 | } |
df58fc94 RS |
10901 | |
10902 | if (insn_error) | |
10903 | return; | |
10904 | ||
10905 | if (!ok) | |
7bd942df | 10906 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10907 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10908 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10909 | else | |
10910 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10911 | 8 * forced_insn_length); | |
10912 | insn_error = buf; | |
10913 | ||
10914 | return; | |
252b5132 RH |
10915 | } |
10916 | ||
1e915849 | 10917 | create_insn (ip, insn); |
268f6bed | 10918 | insn_error = NULL; |
707bfff6 | 10919 | argnum = 1; |
24864476 | 10920 | lastregno = 0xffffffff; |
252b5132 RH |
10921 | for (args = insn->args;; ++args) |
10922 | { | |
deec1734 CD |
10923 | int is_mdmx; |
10924 | ||
ad8d3bb3 | 10925 | s += strspn (s, " \t"); |
deec1734 | 10926 | is_mdmx = 0; |
252b5132 RH |
10927 | switch (*args) |
10928 | { | |
10929 | case '\0': /* end of args */ | |
10930 | if (*s == '\0') | |
10931 | return; | |
10932 | break; | |
10933 | ||
03f66e8a MR |
10934 | case '2': |
10935 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
10936 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
10937 | my_getExpression (&imm_expr, s); |
10938 | check_absolute_expr (ip, &imm_expr); | |
10939 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10940 | && (unsigned long) imm_expr.X_add_number != 3) | |
10941 | { | |
10942 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10943 | (unsigned long) imm_expr.X_add_number); | |
10944 | } | |
03f66e8a MR |
10945 | INSERT_OPERAND (mips_opts.micromips, |
10946 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
10947 | imm_expr.X_op = O_absent; |
10948 | s = expr_end; | |
10949 | continue; | |
10950 | ||
03f66e8a MR |
10951 | case '3': |
10952 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
10953 | code) or 21 (for microMIPS code). */ | |
10954 | { | |
10955 | unsigned long mask = (mips_opts.micromips | |
10956 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
10957 | ||
10958 | my_getExpression (&imm_expr, s); | |
10959 | check_absolute_expr (ip, &imm_expr); | |
10960 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10961 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10962 | mask, (unsigned long) imm_expr.X_add_number); | |
10963 | INSERT_OPERAND (mips_opts.micromips, | |
10964 | SA3, *ip, imm_expr.X_add_number); | |
10965 | imm_expr.X_op = O_absent; | |
10966 | s = expr_end; | |
10967 | } | |
74cd071d CF |
10968 | continue; |
10969 | ||
03f66e8a MR |
10970 | case '4': |
10971 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
10972 | code) or 21 (for microMIPS code). */ | |
10973 | { | |
10974 | unsigned long mask = (mips_opts.micromips | |
10975 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
10976 | ||
10977 | my_getExpression (&imm_expr, s); | |
10978 | check_absolute_expr (ip, &imm_expr); | |
10979 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10980 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10981 | mask, (unsigned long) imm_expr.X_add_number); | |
10982 | INSERT_OPERAND (mips_opts.micromips, | |
10983 | SA4, *ip, imm_expr.X_add_number); | |
10984 | imm_expr.X_op = O_absent; | |
10985 | s = expr_end; | |
10986 | } | |
74cd071d CF |
10987 | continue; |
10988 | ||
03f66e8a MR |
10989 | case '5': |
10990 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
10991 | code) or 16 (for microMIPS code). */ | |
10992 | { | |
10993 | unsigned long mask = (mips_opts.micromips | |
10994 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
10995 | ||
10996 | my_getExpression (&imm_expr, s); | |
10997 | check_absolute_expr (ip, &imm_expr); | |
10998 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10999 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11000 | mask, (unsigned long) imm_expr.X_add_number); | |
11001 | INSERT_OPERAND (mips_opts.micromips, | |
11002 | IMM8, *ip, imm_expr.X_add_number); | |
11003 | imm_expr.X_op = O_absent; | |
11004 | s = expr_end; | |
11005 | } | |
74cd071d CF |
11006 | continue; |
11007 | ||
03f66e8a MR |
11008 | case '6': |
11009 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11010 | code) or 21 (for microMIPS code). */ | |
11011 | { | |
11012 | unsigned long mask = (mips_opts.micromips | |
11013 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11014 | ||
11015 | my_getExpression (&imm_expr, s); | |
11016 | check_absolute_expr (ip, &imm_expr); | |
11017 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11018 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11019 | mask, (unsigned long) imm_expr.X_add_number); | |
11020 | INSERT_OPERAND (mips_opts.micromips, | |
11021 | RS, *ip, imm_expr.X_add_number); | |
11022 | imm_expr.X_op = O_absent; | |
11023 | s = expr_end; | |
11024 | } | |
74cd071d CF |
11025 | continue; |
11026 | ||
90ecf173 | 11027 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11028 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11029 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11030 | { |
11031 | regno = s[3] - '0'; | |
11032 | s += 4; | |
03f66e8a | 11033 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11034 | continue; |
11035 | } | |
11036 | else | |
11037 | as_bad (_("Invalid dsp acc register")); | |
11038 | break; | |
11039 | ||
03f66e8a MR |
11040 | case '8': |
11041 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11042 | code) or 14 (for microMIPS code). */ | |
11043 | { | |
11044 | unsigned long mask = (mips_opts.micromips | |
11045 | ? MICROMIPSOP_MASK_WRDSP | |
11046 | : OP_MASK_WRDSP); | |
11047 | ||
11048 | my_getExpression (&imm_expr, s); | |
11049 | check_absolute_expr (ip, &imm_expr); | |
11050 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11051 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11052 | mask, (unsigned long) imm_expr.X_add_number); | |
11053 | INSERT_OPERAND (mips_opts.micromips, | |
11054 | WRDSP, *ip, imm_expr.X_add_number); | |
11055 | imm_expr.X_op = O_absent; | |
11056 | s = expr_end; | |
11057 | } | |
74cd071d CF |
11058 | continue; |
11059 | ||
90ecf173 | 11060 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11061 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11062 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11063 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11064 | { |
11065 | regno = s[3] - '0'; | |
11066 | s += 4; | |
df58fc94 | 11067 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11068 | continue; |
11069 | } | |
11070 | else | |
11071 | as_bad (_("Invalid dsp acc register")); | |
11072 | break; | |
11073 | ||
03f66e8a MR |
11074 | case '0': |
11075 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11076 | code) or 20 (for microMIPS code). */ | |
11077 | { | |
11078 | long mask = (mips_opts.micromips | |
11079 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11080 | ||
11081 | my_getExpression (&imm_expr, s); | |
11082 | check_absolute_expr (ip, &imm_expr); | |
11083 | min_range = -((mask + 1) >> 1); | |
11084 | max_range = ((mask + 1) >> 1) - 1; | |
11085 | if (imm_expr.X_add_number < min_range | |
11086 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11087 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11088 | (long) min_range, (long) max_range, | |
11089 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11090 | INSERT_OPERAND (mips_opts.micromips, |
11091 | DSPSFT, *ip, imm_expr.X_add_number); | |
11092 | imm_expr.X_op = O_absent; | |
11093 | s = expr_end; | |
11094 | } | |
74cd071d CF |
11095 | continue; |
11096 | ||
90ecf173 | 11097 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11098 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11099 | my_getExpression (&imm_expr, s); |
11100 | check_absolute_expr (ip, &imm_expr); | |
11101 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11102 | { | |
a9e24354 TS |
11103 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11104 | OP_MASK_RDDSP, | |
11105 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11106 | } |
df58fc94 | 11107 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11108 | imm_expr.X_op = O_absent; |
11109 | s = expr_end; | |
11110 | continue; | |
11111 | ||
90ecf173 | 11112 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11113 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11114 | my_getExpression (&imm_expr, s); |
11115 | check_absolute_expr (ip, &imm_expr); | |
11116 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11117 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11118 | if (imm_expr.X_add_number < min_range || | |
11119 | imm_expr.X_add_number > max_range) | |
11120 | { | |
a9e24354 TS |
11121 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11122 | (long) min_range, (long) max_range, | |
11123 | (long) imm_expr.X_add_number); | |
74cd071d | 11124 | } |
df58fc94 | 11125 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11126 | imm_expr.X_op = O_absent; |
11127 | s = expr_end; | |
11128 | continue; | |
11129 | ||
90ecf173 | 11130 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11131 | { |
11132 | long mask = (mips_opts.micromips | |
11133 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11134 | ||
11135 | my_getExpression (&imm_expr, s); | |
11136 | check_absolute_expr (ip, &imm_expr); | |
11137 | min_range = -((mask + 1) >> 1); | |
11138 | max_range = ((mask + 1) >> 1) - 1; | |
11139 | if (imm_expr.X_add_number < min_range | |
11140 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11141 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11142 | (long) min_range, (long) max_range, | |
11143 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11144 | INSERT_OPERAND (mips_opts.micromips, |
11145 | IMM10, *ip, imm_expr.X_add_number); | |
11146 | imm_expr.X_op = O_absent; | |
11147 | s = expr_end; | |
11148 | } | |
11149 | continue; | |
11150 | ||
11151 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11152 | gas_assert (mips_opts.micromips); | |
11153 | my_getExpression (&imm_expr, s); | |
11154 | check_absolute_expr (ip, &imm_expr); | |
11155 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11156 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11157 | MICROMIPSOP_MASK_RD, | |
11158 | (unsigned long) imm_expr.X_add_number); | |
11159 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11160 | imm_expr.X_op = O_absent; |
11161 | s = expr_end; | |
11162 | continue; | |
11163 | ||
a9e24354 | 11164 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11165 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11166 | my_getExpression (&imm_expr, s); |
11167 | check_absolute_expr (ip, &imm_expr); | |
11168 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11169 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11170 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11171 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11172 | imm_expr.X_op = O_absent; |
11173 | s = expr_end; | |
11174 | continue; | |
11175 | ||
a9e24354 | 11176 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11177 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11178 | my_getExpression (&imm_expr, s); |
11179 | check_absolute_expr (ip, &imm_expr); | |
11180 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11181 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11182 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11183 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11184 | imm_expr.X_op = O_absent; |
11185 | s = expr_end; | |
11186 | continue; | |
11187 | ||
90ecf173 | 11188 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11189 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11190 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11191 | s[3] >= '0' && s[3] <= '3') | |
11192 | { | |
11193 | regno = s[3] - '0'; | |
11194 | s += 4; | |
df58fc94 | 11195 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11196 | continue; |
11197 | } | |
11198 | else | |
11199 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11200 | break; | |
11201 | ||
90ecf173 | 11202 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11203 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11204 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11205 | s[3] >= '0' && s[3] <= '3') | |
11206 | { | |
11207 | regno = s[3] - '0'; | |
11208 | s += 4; | |
df58fc94 | 11209 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11210 | continue; |
11211 | } | |
11212 | else | |
11213 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11214 | break; | |
11215 | ||
dec0624d MR |
11216 | case '\\': /* 3-bit bit position. */ |
11217 | { | |
2906b037 MR |
11218 | unsigned long mask = (mips_opts.micromips |
11219 | ? MICROMIPSOP_MASK_3BITPOS | |
11220 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11221 | |
11222 | my_getExpression (&imm_expr, s); | |
11223 | check_absolute_expr (ip, &imm_expr); | |
11224 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11225 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11226 | ip->insn_mo->name, | |
11227 | mask, (unsigned long) imm_expr.X_add_number); | |
11228 | INSERT_OPERAND (mips_opts.micromips, | |
11229 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11230 | imm_expr.X_op = O_absent; | |
11231 | s = expr_end; | |
11232 | } | |
11233 | continue; | |
11234 | ||
252b5132 | 11235 | case ',': |
a339155f | 11236 | ++argnum; |
252b5132 RH |
11237 | if (*s++ == *args) |
11238 | continue; | |
11239 | s--; | |
11240 | switch (*++args) | |
11241 | { | |
11242 | case 'r': | |
11243 | case 'v': | |
df58fc94 | 11244 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11245 | continue; |
11246 | ||
11247 | case 'w': | |
df58fc94 | 11248 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11249 | continue; |
11250 | ||
252b5132 | 11251 | case 'W': |
df58fc94 RS |
11252 | gas_assert (!mips_opts.micromips); |
11253 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11254 | continue; |
11255 | ||
11256 | case 'V': | |
df58fc94 | 11257 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11258 | continue; |
11259 | } | |
11260 | break; | |
11261 | ||
11262 | case '(': | |
11263 | /* Handle optional base register. | |
11264 | Either the base register is omitted or | |
bdaaa2e1 | 11265 | we must have a left paren. */ |
252b5132 RH |
11266 | /* This is dependent on the next operand specifier |
11267 | is a base register specification. */ | |
df58fc94 RS |
11268 | gas_assert (args[1] == 'b' |
11269 | || (mips_opts.micromips | |
11270 | && args[1] == 'm' | |
11271 | && (args[2] == 'l' || args[2] == 'n' | |
11272 | || args[2] == 's' || args[2] == 'a'))); | |
11273 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11274 | return; |
df58fc94 | 11275 | /* Fall through. */ |
252b5132 | 11276 | |
90ecf173 | 11277 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11278 | if (*s++ == *args) |
11279 | continue; | |
11280 | break; | |
11281 | ||
11282 | case '[': /* These must match exactly. */ | |
60b63b72 | 11283 | case ']': |
df58fc94 | 11284 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11285 | if (*s++ == *args) |
11286 | continue; | |
11287 | break; | |
11288 | ||
af7ee8bf CD |
11289 | case '+': /* Opcode extension character. */ |
11290 | switch (*++args) | |
11291 | { | |
9bcd4f99 TS |
11292 | case '1': /* UDI immediates. */ |
11293 | case '2': | |
11294 | case '3': | |
11295 | case '4': | |
df58fc94 | 11296 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11297 | { |
11298 | const struct mips_immed *imm = mips_immed; | |
11299 | ||
11300 | while (imm->type && imm->type != *args) | |
11301 | ++imm; | |
11302 | if (! imm->type) | |
11303 | internalError (); | |
11304 | my_getExpression (&imm_expr, s); | |
11305 | check_absolute_expr (ip, &imm_expr); | |
11306 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11307 | { | |
11308 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11309 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11310 | (unsigned long) imm_expr.X_add_number, | |
11311 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11312 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11313 | } |
11314 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11315 | << imm->shift); | |
11316 | imm_expr.X_op = O_absent; | |
11317 | s = expr_end; | |
11318 | } | |
11319 | continue; | |
90ecf173 | 11320 | |
071742cf CD |
11321 | case 'A': /* ins/ext position, becomes LSB. */ |
11322 | limlo = 0; | |
11323 | limhi = 31; | |
5f74bc13 CD |
11324 | goto do_lsb; |
11325 | case 'E': | |
11326 | limlo = 32; | |
11327 | limhi = 63; | |
11328 | goto do_lsb; | |
90ecf173 | 11329 | do_lsb: |
071742cf CD |
11330 | my_getExpression (&imm_expr, s); |
11331 | check_absolute_expr (ip, &imm_expr); | |
11332 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11333 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11334 | { | |
11335 | as_bad (_("Improper position (%lu)"), | |
11336 | (unsigned long) imm_expr.X_add_number); | |
11337 | imm_expr.X_add_number = limlo; | |
11338 | } | |
11339 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11340 | INSERT_OPERAND (mips_opts.micromips, |
11341 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11342 | imm_expr.X_op = O_absent; |
11343 | s = expr_end; | |
11344 | continue; | |
11345 | ||
11346 | case 'B': /* ins size, becomes MSB. */ | |
11347 | limlo = 1; | |
11348 | limhi = 32; | |
5f74bc13 CD |
11349 | goto do_msb; |
11350 | case 'F': | |
11351 | limlo = 33; | |
11352 | limhi = 64; | |
11353 | goto do_msb; | |
90ecf173 | 11354 | do_msb: |
071742cf CD |
11355 | my_getExpression (&imm_expr, s); |
11356 | check_absolute_expr (ip, &imm_expr); | |
11357 | /* Check for negative input so that small negative numbers | |
11358 | will not succeed incorrectly. The checks against | |
11359 | (pos+size) transitively check "size" itself, | |
11360 | assuming that "pos" is reasonable. */ | |
11361 | if ((long) imm_expr.X_add_number < 0 | |
11362 | || ((unsigned long) imm_expr.X_add_number | |
11363 | + lastpos) < limlo | |
11364 | || ((unsigned long) imm_expr.X_add_number | |
11365 | + lastpos) > limhi) | |
11366 | { | |
11367 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11368 | (unsigned long) imm_expr.X_add_number, | |
11369 | (unsigned long) lastpos); | |
11370 | imm_expr.X_add_number = limlo - lastpos; | |
11371 | } | |
df58fc94 RS |
11372 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11373 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11374 | imm_expr.X_op = O_absent; |
11375 | s = expr_end; | |
11376 | continue; | |
11377 | ||
11378 | case 'C': /* ext size, becomes MSBD. */ | |
11379 | limlo = 1; | |
11380 | limhi = 32; | |
5f74bc13 CD |
11381 | goto do_msbd; |
11382 | case 'G': | |
11383 | limlo = 33; | |
11384 | limhi = 64; | |
11385 | goto do_msbd; | |
11386 | case 'H': | |
11387 | limlo = 33; | |
11388 | limhi = 64; | |
11389 | goto do_msbd; | |
90ecf173 | 11390 | do_msbd: |
071742cf CD |
11391 | my_getExpression (&imm_expr, s); |
11392 | check_absolute_expr (ip, &imm_expr); | |
11393 | /* Check for negative input so that small negative numbers | |
11394 | will not succeed incorrectly. The checks against | |
11395 | (pos+size) transitively check "size" itself, | |
11396 | assuming that "pos" is reasonable. */ | |
11397 | if ((long) imm_expr.X_add_number < 0 | |
11398 | || ((unsigned long) imm_expr.X_add_number | |
11399 | + lastpos) < limlo | |
11400 | || ((unsigned long) imm_expr.X_add_number | |
11401 | + lastpos) > limhi) | |
11402 | { | |
11403 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11404 | (unsigned long) imm_expr.X_add_number, | |
11405 | (unsigned long) lastpos); | |
11406 | imm_expr.X_add_number = limlo - lastpos; | |
11407 | } | |
df58fc94 RS |
11408 | INSERT_OPERAND (mips_opts.micromips, |
11409 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11410 | imm_expr.X_op = O_absent; |
11411 | s = expr_end; | |
11412 | continue; | |
af7ee8bf | 11413 | |
bbcc0807 CD |
11414 | case 'D': |
11415 | /* +D is for disassembly only; never match. */ | |
11416 | break; | |
11417 | ||
5f74bc13 CD |
11418 | case 'I': |
11419 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11420 | my_getExpression (&imm2_expr, s); | |
11421 | if (imm2_expr.X_op != O_big | |
11422 | && imm2_expr.X_op != O_constant) | |
11423 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11424 | if (HAVE_32BIT_GPRS) |
11425 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11426 | s = expr_end; |
11427 | continue; | |
11428 | ||
707bfff6 | 11429 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11430 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11431 | /* +T is for disassembly only; never match. */ |
11432 | break; | |
11433 | ||
707bfff6 | 11434 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11435 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11436 | if (s[0] == '$' && ISDIGIT (s[1])) |
11437 | { | |
11438 | ++s; | |
11439 | regno = 0; | |
11440 | do | |
11441 | { | |
11442 | regno *= 10; | |
11443 | regno += *s - '0'; | |
11444 | ++s; | |
11445 | } | |
11446 | while (ISDIGIT (*s)); | |
11447 | if (regno > 31) | |
11448 | as_bad (_("Invalid register number (%d)"), regno); | |
11449 | else | |
11450 | { | |
df58fc94 | 11451 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11452 | continue; |
11453 | } | |
11454 | } | |
11455 | else | |
11456 | as_bad (_("Invalid coprocessor 0 register number")); | |
11457 | break; | |
11458 | ||
bb35fb24 NC |
11459 | case 'x': |
11460 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11461 | is not in the valid range. */ | |
df58fc94 | 11462 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11463 | my_getExpression (&imm_expr, s); |
11464 | check_absolute_expr (ip, &imm_expr); | |
11465 | if ((unsigned) imm_expr.X_add_number > 31) | |
11466 | { | |
11467 | as_bad (_("Improper bit index (%lu)"), | |
11468 | (unsigned long) imm_expr.X_add_number); | |
11469 | imm_expr.X_add_number = 0; | |
11470 | } | |
df58fc94 | 11471 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11472 | imm_expr.X_op = O_absent; |
11473 | s = expr_end; | |
11474 | continue; | |
11475 | ||
11476 | case 'X': | |
11477 | /* bbit[01] bit index when bbit is used but we generate | |
11478 | bbit[01]32 because the index is over 32. Move to the | |
11479 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11480 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11481 | my_getExpression (&imm_expr, s); |
11482 | check_absolute_expr (ip, &imm_expr); | |
11483 | if ((unsigned) imm_expr.X_add_number < 32 | |
11484 | || (unsigned) imm_expr.X_add_number > 63) | |
11485 | break; | |
df58fc94 | 11486 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11487 | imm_expr.X_op = O_absent; |
11488 | s = expr_end; | |
11489 | continue; | |
11490 | ||
11491 | case 'p': | |
11492 | /* cins, cins32, exts and exts32 position field. Give error | |
11493 | if it's not in the valid range. */ | |
df58fc94 | 11494 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11495 | my_getExpression (&imm_expr, s); |
11496 | check_absolute_expr (ip, &imm_expr); | |
11497 | if ((unsigned) imm_expr.X_add_number > 31) | |
11498 | { | |
11499 | as_bad (_("Improper position (%lu)"), | |
11500 | (unsigned long) imm_expr.X_add_number); | |
11501 | imm_expr.X_add_number = 0; | |
11502 | } | |
11503 | /* Make the pos explicit to simplify +S. */ | |
11504 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11505 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11506 | imm_expr.X_op = O_absent; |
11507 | s = expr_end; | |
11508 | continue; | |
11509 | ||
11510 | case 'P': | |
11511 | /* cins, cins32, exts and exts32 position field. Move to | |
11512 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11513 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11514 | my_getExpression (&imm_expr, s); |
11515 | check_absolute_expr (ip, &imm_expr); | |
11516 | if ((unsigned) imm_expr.X_add_number < 32 | |
11517 | || (unsigned) imm_expr.X_add_number > 63) | |
11518 | break; | |
11519 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11520 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11521 | imm_expr.X_op = O_absent; |
11522 | s = expr_end; | |
11523 | continue; | |
11524 | ||
11525 | case 's': | |
11526 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11527 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11528 | my_getExpression (&imm_expr, s); |
11529 | check_absolute_expr (ip, &imm_expr); | |
11530 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11531 | { | |
11532 | as_bad (_("Improper size (%lu)"), | |
11533 | (unsigned long) imm_expr.X_add_number); | |
11534 | imm_expr.X_add_number = 0; | |
11535 | } | |
df58fc94 | 11536 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11537 | imm_expr.X_op = O_absent; |
11538 | s = expr_end; | |
11539 | continue; | |
11540 | ||
11541 | case 'S': | |
11542 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11543 | length-minus-one field. */ | |
df58fc94 | 11544 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11545 | my_getExpression (&imm_expr, s); |
11546 | check_absolute_expr (ip, &imm_expr); | |
11547 | if ((long) imm_expr.X_add_number < 0 | |
11548 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11549 | { | |
11550 | as_bad (_("Improper size (%lu)"), | |
11551 | (unsigned long) imm_expr.X_add_number); | |
11552 | imm_expr.X_add_number = 0; | |
11553 | } | |
df58fc94 | 11554 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11555 | imm_expr.X_op = O_absent; |
11556 | s = expr_end; | |
11557 | continue; | |
11558 | ||
dd3cbb7e NC |
11559 | case 'Q': |
11560 | /* seqi/snei immediate field. */ | |
df58fc94 | 11561 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11562 | my_getExpression (&imm_expr, s); |
11563 | check_absolute_expr (ip, &imm_expr); | |
11564 | if ((long) imm_expr.X_add_number < -512 | |
11565 | || (long) imm_expr.X_add_number >= 512) | |
11566 | { | |
11567 | as_bad (_("Improper immediate (%ld)"), | |
11568 | (long) imm_expr.X_add_number); | |
11569 | imm_expr.X_add_number = 0; | |
11570 | } | |
df58fc94 | 11571 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11572 | imm_expr.X_op = O_absent; |
11573 | s = expr_end; | |
11574 | continue; | |
11575 | ||
98675402 | 11576 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11577 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11578 | my_getExpression (&imm_expr, s); |
11579 | check_absolute_expr (ip, &imm_expr); | |
11580 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11581 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11582 | if (imm_expr.X_add_number < min_range | |
11583 | || imm_expr.X_add_number > max_range) | |
11584 | { | |
c95354ed | 11585 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11586 | (long) min_range, (long) max_range, |
11587 | (long) imm_expr.X_add_number); | |
11588 | } | |
df58fc94 | 11589 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11590 | imm_expr.X_op = O_absent; |
11591 | s = expr_end; | |
11592 | continue; | |
11593 | ||
11594 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11595 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11596 | my_getExpression (&imm_expr, s); |
11597 | check_absolute_expr (ip, &imm_expr); | |
11598 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11599 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11600 | if (imm_expr.X_add_number < min_range | |
11601 | || imm_expr.X_add_number > max_range) | |
11602 | { | |
c95354ed | 11603 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11604 | (long) min_range, (long) max_range, |
11605 | (long) imm_expr.X_add_number); | |
11606 | } | |
df58fc94 | 11607 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11608 | imm_expr.X_op = O_absent; |
11609 | s = expr_end; | |
11610 | continue; | |
11611 | ||
11612 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11613 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11614 | my_getExpression (&imm_expr, s); |
11615 | check_absolute_expr (ip, &imm_expr); | |
11616 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11617 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11618 | /* We check the offset range before adjusted. */ |
11619 | min_range <<= 4; | |
11620 | max_range <<= 4; | |
98675402 RS |
11621 | if (imm_expr.X_add_number < min_range |
11622 | || imm_expr.X_add_number > max_range) | |
11623 | { | |
c95354ed | 11624 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11625 | (long) min_range, (long) max_range, |
11626 | (long) imm_expr.X_add_number); | |
11627 | } | |
c95354ed MX |
11628 | if (imm_expr.X_add_number & 0xf) |
11629 | { | |
11630 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11631 | (long) imm_expr.X_add_number); | |
11632 | } | |
11633 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11634 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11635 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11636 | imm_expr.X_op = O_absent; |
11637 | s = expr_end; | |
11638 | continue; | |
11639 | ||
11640 | case 'z': | |
df58fc94 | 11641 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11642 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11643 | break; | |
11644 | if (regno == AT && mips_opts.at) | |
11645 | { | |
11646 | if (mips_opts.at == ATREG) | |
11647 | as_warn (_("used $at without \".set noat\"")); | |
11648 | else | |
11649 | as_warn (_("used $%u with \".set at=$%u\""), | |
11650 | regno, mips_opts.at); | |
11651 | } | |
df58fc94 | 11652 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11653 | continue; |
11654 | ||
11655 | case 'Z': | |
df58fc94 | 11656 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11657 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11658 | break; | |
df58fc94 | 11659 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11660 | continue; |
11661 | ||
af7ee8bf | 11662 | default: |
df58fc94 | 11663 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11664 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11665 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11666 | *args, insn->name, insn->args); |
af7ee8bf CD |
11667 | /* Further processing is fruitless. */ |
11668 | return; | |
11669 | } | |
11670 | break; | |
11671 | ||
df58fc94 | 11672 | case '.': /* 10-bit offset. */ |
df58fc94 | 11673 | gas_assert (mips_opts.micromips); |
dec0624d | 11674 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11675 | { |
11676 | int shift = *args == '.' ? 9 : 11; | |
11677 | size_t i; | |
11678 | ||
11679 | /* Check whether there is only a single bracketed expression | |
11680 | left. If so, it must be the base register and the | |
11681 | constant must be zero. */ | |
11682 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11683 | continue; | |
11684 | ||
11685 | /* If this value won't fit into the offset, then go find | |
11686 | a macro that will generate a 16- or 32-bit offset code | |
11687 | pattern. */ | |
11688 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11689 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11690 | || imm_expr.X_add_number >= 1 << shift | |
11691 | || imm_expr.X_add_number < -1 << shift)) | |
11692 | || i > 0) | |
11693 | { | |
11694 | imm_expr.X_op = O_absent; | |
11695 | break; | |
11696 | } | |
11697 | if (shift == 9) | |
11698 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11699 | else | |
dec0624d MR |
11700 | INSERT_OPERAND (mips_opts.micromips, |
11701 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11702 | imm_expr.X_op = O_absent; |
11703 | s = expr_end; | |
11704 | } | |
11705 | continue; | |
11706 | ||
252b5132 RH |
11707 | case '<': /* must be at least one digit */ |
11708 | /* | |
11709 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11710 | * than 31 or less than 0, then the shift amount should be |
11711 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11712 | * We issue a warning and mask out all but the low 5 bits. |
11713 | */ | |
11714 | my_getExpression (&imm_expr, s); | |
11715 | check_absolute_expr (ip, &imm_expr); | |
11716 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11717 | as_warn (_("Improper shift amount (%lu)"), |
11718 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11719 | INSERT_OPERAND (mips_opts.micromips, |
11720 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11721 | imm_expr.X_op = O_absent; |
11722 | s = expr_end; | |
11723 | continue; | |
11724 | ||
11725 | case '>': /* shift amount minus 32 */ | |
11726 | my_getExpression (&imm_expr, s); | |
11727 | check_absolute_expr (ip, &imm_expr); | |
11728 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11729 | || (unsigned long) imm_expr.X_add_number > 63) | |
11730 | break; | |
df58fc94 RS |
11731 | INSERT_OPERAND (mips_opts.micromips, |
11732 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11733 | imm_expr.X_op = O_absent; |
11734 | s = expr_end; | |
11735 | continue; | |
11736 | ||
90ecf173 MR |
11737 | case 'k': /* CACHE code. */ |
11738 | case 'h': /* PREFX code. */ | |
11739 | case '1': /* SYNC type. */ | |
252b5132 RH |
11740 | my_getExpression (&imm_expr, s); |
11741 | check_absolute_expr (ip, &imm_expr); | |
11742 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11743 | as_warn (_("Invalid value for `%s' (%lu)"), |
11744 | ip->insn_mo->name, | |
11745 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11746 | switch (*args) |
d954098f | 11747 | { |
df58fc94 RS |
11748 | case 'k': |
11749 | if (mips_fix_cn63xxp1 | |
11750 | && !mips_opts.micromips | |
11751 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11752 | switch (imm_expr.X_add_number) |
11753 | { | |
11754 | case 5: | |
11755 | case 25: | |
11756 | case 26: | |
11757 | case 27: | |
11758 | case 28: | |
11759 | case 29: | |
11760 | case 30: | |
11761 | case 31: /* These are ok. */ | |
11762 | break; | |
11763 | ||
11764 | default: /* The rest must be changed to 28. */ | |
11765 | imm_expr.X_add_number = 28; | |
11766 | break; | |
11767 | } | |
df58fc94 RS |
11768 | INSERT_OPERAND (mips_opts.micromips, |
11769 | CACHE, *ip, imm_expr.X_add_number); | |
11770 | break; | |
11771 | case 'h': | |
11772 | INSERT_OPERAND (mips_opts.micromips, | |
11773 | PREFX, *ip, imm_expr.X_add_number); | |
11774 | break; | |
11775 | case '1': | |
11776 | INSERT_OPERAND (mips_opts.micromips, | |
11777 | STYPE, *ip, imm_expr.X_add_number); | |
11778 | break; | |
d954098f | 11779 | } |
252b5132 RH |
11780 | imm_expr.X_op = O_absent; |
11781 | s = expr_end; | |
11782 | continue; | |
11783 | ||
90ecf173 | 11784 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11785 | { |
11786 | unsigned long mask = (mips_opts.micromips | |
11787 | ? MICROMIPSOP_MASK_CODE | |
11788 | : OP_MASK_CODE); | |
11789 | ||
11790 | my_getExpression (&imm_expr, s); | |
11791 | check_absolute_expr (ip, &imm_expr); | |
11792 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11793 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11794 | ip->insn_mo->name, | |
11795 | mask, (unsigned long) imm_expr.X_add_number); | |
11796 | INSERT_OPERAND (mips_opts.micromips, | |
11797 | CODE, *ip, imm_expr.X_add_number); | |
11798 | imm_expr.X_op = O_absent; | |
11799 | s = expr_end; | |
11800 | } | |
252b5132 RH |
11801 | continue; |
11802 | ||
90ecf173 | 11803 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11804 | { |
11805 | unsigned long mask = (mips_opts.micromips | |
11806 | ? MICROMIPSOP_MASK_CODE2 | |
11807 | : OP_MASK_CODE2); | |
11808 | ||
11809 | my_getExpression (&imm_expr, s); | |
11810 | check_absolute_expr (ip, &imm_expr); | |
11811 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11812 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11813 | ip->insn_mo->name, | |
11814 | mask, (unsigned long) imm_expr.X_add_number); | |
11815 | INSERT_OPERAND (mips_opts.micromips, | |
11816 | CODE2, *ip, imm_expr.X_add_number); | |
11817 | imm_expr.X_op = O_absent; | |
11818 | s = expr_end; | |
11819 | } | |
252b5132 RH |
11820 | continue; |
11821 | ||
df58fc94 RS |
11822 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11823 | { | |
11824 | unsigned long mask = (mips_opts.micromips | |
11825 | ? MICROMIPSOP_MASK_CODE10 | |
11826 | : OP_MASK_CODE20); | |
11827 | ||
11828 | my_getExpression (&imm_expr, s); | |
11829 | check_absolute_expr (ip, &imm_expr); | |
11830 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11831 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11832 | ip->insn_mo->name, | |
11833 | mask, (unsigned long) imm_expr.X_add_number); | |
11834 | if (mips_opts.micromips) | |
11835 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11836 | else | |
11837 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11838 | imm_expr.X_op = O_absent; | |
11839 | s = expr_end; | |
11840 | } | |
252b5132 RH |
11841 | continue; |
11842 | ||
df58fc94 RS |
11843 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11844 | { | |
11845 | unsigned long mask = (mips_opts.micromips | |
11846 | ? MICROMIPSOP_MASK_COPZ | |
11847 | : OP_MASK_COPZ); | |
11848 | ||
11849 | my_getExpression (&imm_expr, s); | |
11850 | check_absolute_expr (ip, &imm_expr); | |
11851 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11852 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11853 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11854 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11855 | INSERT_OPERAND (mips_opts.micromips, |
11856 | COPZ, *ip, imm_expr.X_add_number); | |
11857 | imm_expr.X_op = O_absent; | |
11858 | s = expr_end; | |
11859 | } | |
beae10d5 | 11860 | continue; |
252b5132 | 11861 | |
df58fc94 RS |
11862 | case 'J': /* 19-bit WAIT code. */ |
11863 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11864 | my_getExpression (&imm_expr, s); |
11865 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11866 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11867 | { |
11868 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11869 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11870 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11871 | } | |
11872 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11873 | imm_expr.X_op = O_absent; |
11874 | s = expr_end; | |
11875 | continue; | |
11876 | ||
707bfff6 | 11877 | case 'P': /* Performance register. */ |
df58fc94 | 11878 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11879 | my_getExpression (&imm_expr, s); |
252b5132 | 11880 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11881 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11882 | as_warn (_("Invalid performance register (%lu)"), |
11883 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
11884 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
11885 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
11886 | as_warn (_("Invalid performance register (%lu)"), | |
11887 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11888 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11889 | imm_expr.X_op = O_absent; |
11890 | s = expr_end; | |
11891 | continue; | |
252b5132 | 11892 | |
707bfff6 | 11893 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11894 | { |
11895 | unsigned long opcode = ip->insn_opcode; | |
11896 | unsigned long mask; | |
11897 | unsigned int types; | |
11898 | int cop0; | |
11899 | ||
11900 | if (mips_opts.micromips) | |
11901 | { | |
11902 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11903 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11904 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11905 | opcode &= mask; | |
11906 | switch (opcode) | |
11907 | { | |
11908 | case 0x000000fc: /* mfc0 */ | |
11909 | case 0x000002fc: /* mtc0 */ | |
11910 | case 0x580000fc: /* dmfc0 */ | |
11911 | case 0x580002fc: /* dmtc0 */ | |
11912 | cop0 = 1; | |
11913 | break; | |
11914 | default: | |
11915 | cop0 = 0; | |
11916 | break; | |
11917 | } | |
11918 | } | |
11919 | else | |
11920 | { | |
11921 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11922 | cop0 = opcode == OP_OP_COP0; | |
11923 | } | |
11924 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11925 | ok = reg_lookup (&s, types, ®no); | |
11926 | if (mips_opts.micromips) | |
11927 | INSERT_OPERAND (1, RS, *ip, regno); | |
11928 | else | |
11929 | INSERT_OPERAND (0, RD, *ip, regno); | |
11930 | if (ok) | |
11931 | { | |
11932 | lastregno = regno; | |
11933 | continue; | |
11934 | } | |
11935 | } | |
11936 | break; | |
707bfff6 | 11937 | |
df58fc94 RS |
11938 | case 'y': /* ALNV.PS source register. */ |
11939 | gas_assert (mips_opts.micromips); | |
11940 | goto do_reg; | |
11941 | case 'x': /* Ignore register name. */ | |
11942 | case 'U': /* Destination register (CLO/CLZ). */ | |
11943 | case 'g': /* Coprocessor destination register. */ | |
11944 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11945 | case 'b': /* Base register. */ |
11946 | case 'd': /* Destination register. */ | |
11947 | case 's': /* Source register. */ | |
11948 | case 't': /* Target register. */ | |
11949 | case 'r': /* Both target and source. */ | |
11950 | case 'v': /* Both dest and source. */ | |
11951 | case 'w': /* Both dest and target. */ | |
11952 | case 'E': /* Coprocessor target register. */ | |
11953 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11954 | case 'z': /* Must be zero register. */ |
df58fc94 | 11955 | do_reg: |
90ecf173 | 11956 | s_reset = s; |
707bfff6 TS |
11957 | if (*args == 'E' || *args == 'K') |
11958 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11959 | else | |
11960 | { | |
11961 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11962 | if (regno == AT && mips_opts.at) |
11963 | { | |
11964 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11965 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11966 | else |
f71d0d44 | 11967 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11968 | regno, mips_opts.at); |
11969 | } | |
707bfff6 TS |
11970 | } |
11971 | if (ok) | |
252b5132 | 11972 | { |
252b5132 RH |
11973 | c = *args; |
11974 | if (*s == ' ') | |
f9419b05 | 11975 | ++s; |
252b5132 RH |
11976 | if (args[1] != *s) |
11977 | { | |
11978 | if (c == 'r' || c == 'v' || c == 'w') | |
11979 | { | |
11980 | regno = lastregno; | |
11981 | s = s_reset; | |
f9419b05 | 11982 | ++args; |
252b5132 RH |
11983 | } |
11984 | } | |
11985 | /* 'z' only matches $0. */ | |
11986 | if (c == 'z' && regno != 0) | |
11987 | break; | |
11988 | ||
24864476 | 11989 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11990 | { |
11991 | if (regno == lastregno) | |
90ecf173 MR |
11992 | { |
11993 | insn_error | |
f71d0d44 | 11994 | = _("Source and destination must be different"); |
e7c604dd | 11995 | continue; |
90ecf173 | 11996 | } |
24864476 | 11997 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11998 | { |
11999 | insn_error | |
f71d0d44 | 12000 | = _("A destination register must be supplied"); |
e7c604dd | 12001 | continue; |
90ecf173 | 12002 | } |
e7c604dd | 12003 | } |
90ecf173 MR |
12004 | /* Now that we have assembled one operand, we use the args |
12005 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12006 | switch (c) |
12007 | { | |
12008 | case 'r': | |
12009 | case 's': | |
12010 | case 'v': | |
12011 | case 'b': | |
df58fc94 | 12012 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12013 | break; |
df58fc94 | 12014 | |
af7ee8bf | 12015 | case 'K': |
df58fc94 RS |
12016 | if (mips_opts.micromips) |
12017 | INSERT_OPERAND (1, RS, *ip, regno); | |
12018 | else | |
12019 | INSERT_OPERAND (0, RD, *ip, regno); | |
12020 | break; | |
12021 | ||
12022 | case 'd': | |
ef2e4d86 | 12023 | case 'g': |
df58fc94 | 12024 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12025 | break; |
df58fc94 | 12026 | |
4372b673 | 12027 | case 'U': |
df58fc94 RS |
12028 | gas_assert (!mips_opts.micromips); |
12029 | INSERT_OPERAND (0, RD, *ip, regno); | |
12030 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12031 | break; |
df58fc94 | 12032 | |
252b5132 RH |
12033 | case 'w': |
12034 | case 't': | |
12035 | case 'E': | |
df58fc94 RS |
12036 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12037 | break; | |
12038 | ||
12039 | case 'y': | |
12040 | gas_assert (mips_opts.micromips); | |
12041 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12042 | break; |
df58fc94 | 12043 | |
252b5132 RH |
12044 | case 'x': |
12045 | /* This case exists because on the r3000 trunc | |
12046 | expands into a macro which requires a gp | |
12047 | register. On the r6000 or r4000 it is | |
12048 | assembled into a single instruction which | |
12049 | ignores the register. Thus the insn version | |
12050 | is MIPS_ISA2 and uses 'x', and the macro | |
12051 | version is MIPS_ISA1 and uses 't'. */ | |
12052 | break; | |
df58fc94 | 12053 | |
252b5132 RH |
12054 | case 'z': |
12055 | /* This case is for the div instruction, which | |
12056 | acts differently if the destination argument | |
12057 | is $0. This only matches $0, and is checked | |
12058 | outside the switch. */ | |
12059 | break; | |
252b5132 RH |
12060 | } |
12061 | lastregno = regno; | |
12062 | continue; | |
12063 | } | |
252b5132 RH |
12064 | switch (*args++) |
12065 | { | |
12066 | case 'r': | |
12067 | case 'v': | |
df58fc94 | 12068 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12069 | continue; |
df58fc94 | 12070 | |
252b5132 | 12071 | case 'w': |
df58fc94 | 12072 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12073 | continue; |
12074 | } | |
12075 | break; | |
12076 | ||
deec1734 | 12077 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12078 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12079 | my_getExpression (&imm_expr, s); |
12080 | check_absolute_expr (ip, &imm_expr); | |
12081 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12082 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12083 | (long) imm_expr.X_add_number); |
df58fc94 | 12084 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12085 | imm_expr.X_op = O_absent; |
12086 | s = expr_end; | |
12087 | continue; | |
12088 | ||
12089 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12090 | if (s[0] != '$') | |
12091 | { | |
12092 | /* MDMX Immediate. */ | |
df58fc94 | 12093 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12094 | my_getExpression (&imm_expr, s); |
12095 | check_absolute_expr (ip, &imm_expr); | |
12096 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12097 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12098 | (long) imm_expr.X_add_number); | |
df58fc94 | 12099 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12100 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12101 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12102 | else | |
12103 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12104 | imm_expr.X_op = O_absent; |
12105 | s = expr_end; | |
12106 | continue; | |
12107 | } | |
12108 | /* Not MDMX Immediate. Fall through. */ | |
12109 | case 'X': /* MDMX destination register. */ | |
12110 | case 'Y': /* MDMX source register. */ | |
12111 | case 'Z': /* MDMX target register. */ | |
12112 | is_mdmx = 1; | |
df58fc94 RS |
12113 | case 'W': |
12114 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12115 | case 'D': /* Floating point destination register. */ |
12116 | case 'S': /* Floating point source register. */ | |
12117 | case 'T': /* Floating point target register. */ | |
12118 | case 'R': /* Floating point source register. */ | |
252b5132 | 12119 | case 'V': |
707bfff6 TS |
12120 | rtype = RTYPE_FPU; |
12121 | if (is_mdmx | |
12122 | || (mips_opts.ase_mdmx | |
12123 | && (ip->insn_mo->pinfo & FP_D) | |
12124 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12125 | | INSN_COPROC_MEMORY_DELAY | |
12126 | | INSN_LOAD_COPROC_DELAY | |
12127 | | INSN_LOAD_MEMORY_DELAY | |
12128 | | INSN_STORE_MEMORY)))) | |
12129 | rtype |= RTYPE_VEC; | |
252b5132 | 12130 | s_reset = s; |
707bfff6 | 12131 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12132 | { |
252b5132 | 12133 | if ((regno & 1) != 0 |
ca4e0257 | 12134 | && HAVE_32BIT_FPRS |
90ecf173 | 12135 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12136 | as_warn (_("Float register should be even, was %d"), |
12137 | regno); | |
12138 | ||
12139 | c = *args; | |
12140 | if (*s == ' ') | |
f9419b05 | 12141 | ++s; |
252b5132 RH |
12142 | if (args[1] != *s) |
12143 | { | |
12144 | if (c == 'V' || c == 'W') | |
12145 | { | |
12146 | regno = lastregno; | |
12147 | s = s_reset; | |
f9419b05 | 12148 | ++args; |
252b5132 RH |
12149 | } |
12150 | } | |
12151 | switch (c) | |
12152 | { | |
12153 | case 'D': | |
deec1734 | 12154 | case 'X': |
df58fc94 | 12155 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12156 | break; |
df58fc94 | 12157 | |
252b5132 RH |
12158 | case 'V': |
12159 | case 'S': | |
deec1734 | 12160 | case 'Y': |
df58fc94 | 12161 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12162 | break; |
df58fc94 | 12163 | |
deec1734 CD |
12164 | case 'Q': |
12165 | /* This is like 'Z', but also needs to fix the MDMX | |
12166 | vector/scalar select bits. Note that the | |
12167 | scalar immediate case is handled above. */ | |
12168 | if (*s == '[') | |
12169 | { | |
12170 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12171 | int max_el = (is_qh ? 3 : 7); | |
12172 | s++; | |
12173 | my_getExpression(&imm_expr, s); | |
12174 | check_absolute_expr (ip, &imm_expr); | |
12175 | s = expr_end; | |
12176 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12177 | as_bad (_("Bad element selector %ld"), |
12178 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12179 | imm_expr.X_add_number &= max_el; |
12180 | ip->insn_opcode |= (imm_expr.X_add_number | |
12181 | << (OP_SH_VSEL + | |
12182 | (is_qh ? 2 : 1))); | |
01a3f561 | 12183 | imm_expr.X_op = O_absent; |
deec1734 | 12184 | if (*s != ']') |
20203fb9 | 12185 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12186 | else |
12187 | s++; | |
12188 | } | |
12189 | else | |
12190 | { | |
12191 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12192 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12193 | << OP_SH_VSEL); | |
12194 | else | |
12195 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12196 | OP_SH_VSEL); | |
12197 | } | |
90ecf173 | 12198 | /* Fall through. */ |
252b5132 RH |
12199 | case 'W': |
12200 | case 'T': | |
deec1734 | 12201 | case 'Z': |
df58fc94 | 12202 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12203 | break; |
df58fc94 | 12204 | |
252b5132 | 12205 | case 'R': |
df58fc94 | 12206 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12207 | break; |
12208 | } | |
12209 | lastregno = regno; | |
12210 | continue; | |
12211 | } | |
12212 | ||
252b5132 RH |
12213 | switch (*args++) |
12214 | { | |
12215 | case 'V': | |
df58fc94 | 12216 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12217 | continue; |
df58fc94 | 12218 | |
252b5132 | 12219 | case 'W': |
df58fc94 | 12220 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12221 | continue; |
12222 | } | |
12223 | break; | |
12224 | ||
12225 | case 'I': | |
12226 | my_getExpression (&imm_expr, s); | |
12227 | if (imm_expr.X_op != O_big | |
12228 | && imm_expr.X_op != O_constant) | |
12229 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12230 | if (HAVE_32BIT_GPRS) |
12231 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12232 | s = expr_end; |
12233 | continue; | |
12234 | ||
12235 | case 'A': | |
12236 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12237 | normalize_address_expr (&offset_expr); |
f6688943 | 12238 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12239 | s = expr_end; |
12240 | continue; | |
12241 | ||
12242 | case 'F': | |
12243 | case 'L': | |
12244 | case 'f': | |
12245 | case 'l': | |
12246 | { | |
12247 | int f64; | |
ca4e0257 | 12248 | int using_gprs; |
252b5132 RH |
12249 | char *save_in; |
12250 | char *err; | |
12251 | unsigned char temp[8]; | |
12252 | int len; | |
12253 | unsigned int length; | |
12254 | segT seg; | |
12255 | subsegT subseg; | |
12256 | char *p; | |
12257 | ||
12258 | /* These only appear as the last operand in an | |
12259 | instruction, and every instruction that accepts | |
12260 | them in any variant accepts them in all variants. | |
12261 | This means we don't have to worry about backing out | |
12262 | any changes if the instruction does not match. | |
12263 | ||
12264 | The difference between them is the size of the | |
12265 | floating point constant and where it goes. For 'F' | |
12266 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12267 | is 32 bits. Where the constant is placed is based | |
12268 | on how the MIPS assembler does things: | |
12269 | F -- .rdata | |
12270 | L -- .lit8 | |
12271 | f -- immediate value | |
12272 | l -- .lit4 | |
12273 | ||
12274 | The .lit4 and .lit8 sections are only used if | |
12275 | permitted by the -G argument. | |
12276 | ||
ca4e0257 RS |
12277 | The code below needs to know whether the target register |
12278 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12279 | 'F' are used with GPR-based instructions and 'l' and | |
12280 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12281 | |
12282 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12283 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12284 | |
12285 | save_in = input_line_pointer; | |
12286 | input_line_pointer = s; | |
12287 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12288 | length = len; | |
12289 | s = input_line_pointer; | |
12290 | input_line_pointer = save_in; | |
12291 | if (err != NULL && *err != '\0') | |
12292 | { | |
12293 | as_bad (_("Bad floating point constant: %s"), err); | |
12294 | memset (temp, '\0', sizeof temp); | |
12295 | length = f64 ? 8 : 4; | |
12296 | } | |
12297 | ||
9c2799c2 | 12298 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12299 | |
12300 | if (*args == 'f' | |
12301 | || (*args == 'l' | |
3e722fb5 | 12302 | && (g_switch_value < 4 |
252b5132 RH |
12303 | || (temp[0] == 0 && temp[1] == 0) |
12304 | || (temp[2] == 0 && temp[3] == 0)))) | |
12305 | { | |
12306 | imm_expr.X_op = O_constant; | |
90ecf173 | 12307 | if (!target_big_endian) |
252b5132 RH |
12308 | imm_expr.X_add_number = bfd_getl32 (temp); |
12309 | else | |
12310 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12311 | } | |
12312 | else if (length > 4 | |
90ecf173 | 12313 | && !mips_disable_float_construction |
ca4e0257 RS |
12314 | /* Constants can only be constructed in GPRs and |
12315 | copied to FPRs if the GPRs are at least as wide | |
12316 | as the FPRs. Force the constant into memory if | |
12317 | we are using 64-bit FPRs but the GPRs are only | |
12318 | 32 bits wide. */ | |
12319 | && (using_gprs | |
90ecf173 | 12320 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12321 | && ((temp[0] == 0 && temp[1] == 0) |
12322 | || (temp[2] == 0 && temp[3] == 0)) | |
12323 | && ((temp[4] == 0 && temp[5] == 0) | |
12324 | || (temp[6] == 0 && temp[7] == 0))) | |
12325 | { | |
ca4e0257 | 12326 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12327 | instructions. If using 32-bit registers, set |
12328 | imm_expr to the high order 32 bits and offset_expr to | |
12329 | the low order 32 bits. Otherwise, set imm_expr to | |
12330 | the entire 64 bit constant. */ | |
ca4e0257 | 12331 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12332 | { |
12333 | imm_expr.X_op = O_constant; | |
12334 | offset_expr.X_op = O_constant; | |
90ecf173 | 12335 | if (!target_big_endian) |
252b5132 RH |
12336 | { |
12337 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12338 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12339 | } | |
12340 | else | |
12341 | { | |
12342 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12343 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12344 | } | |
12345 | if (offset_expr.X_add_number == 0) | |
12346 | offset_expr.X_op = O_absent; | |
12347 | } | |
12348 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12349 | { | |
12350 | imm_expr.X_op = O_constant; | |
90ecf173 | 12351 | if (!target_big_endian) |
252b5132 RH |
12352 | imm_expr.X_add_number = bfd_getl64 (temp); |
12353 | else | |
12354 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12355 | } | |
12356 | else | |
12357 | { | |
12358 | imm_expr.X_op = O_big; | |
12359 | imm_expr.X_add_number = 4; | |
90ecf173 | 12360 | if (!target_big_endian) |
252b5132 RH |
12361 | { |
12362 | generic_bignum[0] = bfd_getl16 (temp); | |
12363 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12364 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12365 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12366 | } | |
12367 | else | |
12368 | { | |
12369 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12370 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12371 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12372 | generic_bignum[3] = bfd_getb16 (temp); | |
12373 | } | |
12374 | } | |
12375 | } | |
12376 | else | |
12377 | { | |
12378 | const char *newname; | |
12379 | segT new_seg; | |
12380 | ||
12381 | /* Switch to the right section. */ | |
12382 | seg = now_seg; | |
12383 | subseg = now_subseg; | |
12384 | switch (*args) | |
12385 | { | |
12386 | default: /* unused default case avoids warnings. */ | |
12387 | case 'L': | |
12388 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12389 | if (g_switch_value >= 8) |
252b5132 RH |
12390 | newname = ".lit8"; |
12391 | break; | |
12392 | case 'F': | |
3e722fb5 | 12393 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12394 | break; |
12395 | case 'l': | |
9c2799c2 | 12396 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12397 | newname = ".lit4"; |
12398 | break; | |
12399 | } | |
12400 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12401 | if (IS_ELF) |
252b5132 RH |
12402 | bfd_set_section_flags (stdoutput, new_seg, |
12403 | (SEC_ALLOC | |
12404 | | SEC_LOAD | |
12405 | | SEC_READONLY | |
12406 | | SEC_DATA)); | |
12407 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12408 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12409 | record_alignment (new_seg, 4); |
12410 | else | |
12411 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12412 | if (seg == now_seg) | |
12413 | as_bad (_("Can't use floating point insn in this section")); | |
12414 | ||
df58fc94 RS |
12415 | /* Set the argument to the current address in the |
12416 | section. */ | |
12417 | offset_expr.X_op = O_symbol; | |
12418 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12419 | offset_expr.X_add_number = 0; | |
12420 | ||
12421 | /* Put the floating point number into the section. */ | |
12422 | p = frag_more ((int) length); | |
12423 | memcpy (p, temp, length); | |
12424 | ||
12425 | /* Switch back to the original section. */ | |
12426 | subseg_set (seg, subseg); | |
12427 | } | |
12428 | } | |
12429 | continue; | |
12430 | ||
12431 | case 'i': /* 16-bit unsigned immediate. */ | |
12432 | case 'j': /* 16-bit signed immediate. */ | |
12433 | *imm_reloc = BFD_RELOC_LO16; | |
12434 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12435 | { | |
12436 | int more; | |
12437 | offsetT minval, maxval; | |
12438 | ||
12439 | more = (insn + 1 < past | |
12440 | && strcmp (insn->name, insn[1].name) == 0); | |
12441 | ||
12442 | /* If the expression was written as an unsigned number, | |
12443 | only treat it as signed if there are no more | |
12444 | alternatives. */ | |
12445 | if (more | |
12446 | && *args == 'j' | |
12447 | && sizeof (imm_expr.X_add_number) <= 4 | |
12448 | && imm_expr.X_op == O_constant | |
12449 | && imm_expr.X_add_number < 0 | |
12450 | && imm_expr.X_unsigned | |
12451 | && HAVE_64BIT_GPRS) | |
12452 | break; | |
12453 | ||
12454 | /* For compatibility with older assemblers, we accept | |
12455 | 0x8000-0xffff as signed 16-bit numbers when only | |
12456 | signed numbers are allowed. */ | |
12457 | if (*args == 'i') | |
12458 | minval = 0, maxval = 0xffff; | |
12459 | else if (more) | |
12460 | minval = -0x8000, maxval = 0x7fff; | |
12461 | else | |
12462 | minval = -0x8000, maxval = 0xffff; | |
12463 | ||
12464 | if (imm_expr.X_op != O_constant | |
12465 | || imm_expr.X_add_number < minval | |
12466 | || imm_expr.X_add_number > maxval) | |
12467 | { | |
12468 | if (more) | |
12469 | break; | |
12470 | if (imm_expr.X_op == O_constant | |
12471 | || imm_expr.X_op == O_big) | |
12472 | as_bad (_("Expression out of range")); | |
12473 | } | |
12474 | } | |
12475 | s = expr_end; | |
12476 | continue; | |
12477 | ||
12478 | case 'o': /* 16-bit offset. */ | |
12479 | offset_reloc[0] = BFD_RELOC_LO16; | |
12480 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12481 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12482 | ||
12483 | /* Check whether there is only a single bracketed expression | |
12484 | left. If so, it must be the base register and the | |
12485 | constant must be zero. */ | |
12486 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12487 | { | |
12488 | offset_expr.X_op = O_constant; | |
12489 | offset_expr.X_add_number = 0; | |
12490 | continue; | |
12491 | } | |
12492 | ||
12493 | /* If this value won't fit into a 16 bit offset, then go | |
12494 | find a macro that will generate the 32 bit offset | |
12495 | code pattern. */ | |
12496 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12497 | && (offset_expr.X_op != O_constant | |
12498 | || offset_expr.X_add_number >= 0x8000 | |
12499 | || offset_expr.X_add_number < -0x8000)) | |
12500 | break; | |
12501 | ||
12502 | s = expr_end; | |
12503 | continue; | |
12504 | ||
12505 | case 'p': /* PC-relative offset. */ | |
12506 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12507 | my_getExpression (&offset_expr, s); | |
12508 | s = expr_end; | |
12509 | continue; | |
12510 | ||
12511 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12512 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12513 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12514 | && imm_expr.X_op == O_constant | |
12515 | && (imm_expr.X_add_number < 0 | |
12516 | || imm_expr.X_add_number >= 0x10000)) | |
12517 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12518 | (unsigned long) imm_expr.X_add_number); | |
12519 | s = expr_end; | |
12520 | continue; | |
12521 | ||
12522 | case 'a': /* 26-bit address. */ | |
12523 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12524 | my_getExpression (&offset_expr, s); | |
12525 | s = expr_end; | |
12526 | continue; | |
12527 | ||
12528 | case 'N': /* 3-bit branch condition code. */ | |
12529 | case 'M': /* 3-bit compare condition code. */ | |
12530 | rtype = RTYPE_CCC; | |
12531 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12532 | rtype |= RTYPE_FCC; | |
12533 | if (!reg_lookup (&s, rtype, ®no)) | |
12534 | break; | |
12535 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12536 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12537 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12538 | && (regno & 1) != 0) | |
12539 | as_warn (_("Condition code register should be even for %s, " | |
12540 | "was %d"), | |
12541 | str, regno); | |
12542 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12543 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12544 | && (regno & 3) != 0) | |
12545 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12546 | "was %d"), | |
12547 | str, regno); | |
12548 | if (*args == 'N') | |
12549 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12550 | else | |
12551 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12552 | continue; | |
12553 | ||
12554 | case 'H': | |
12555 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12556 | s += 2; | |
12557 | if (ISDIGIT (*s)) | |
12558 | { | |
12559 | c = 0; | |
12560 | do | |
12561 | { | |
12562 | c *= 10; | |
12563 | c += *s - '0'; | |
12564 | ++s; | |
12565 | } | |
12566 | while (ISDIGIT (*s)); | |
12567 | } | |
12568 | else | |
12569 | c = 8; /* Invalid sel value. */ | |
12570 | ||
12571 | if (c > 7) | |
12572 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12573 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12574 | continue; | |
12575 | ||
12576 | case 'e': | |
12577 | gas_assert (!mips_opts.micromips); | |
12578 | /* Must be at least one digit. */ | |
12579 | my_getExpression (&imm_expr, s); | |
12580 | check_absolute_expr (ip, &imm_expr); | |
12581 | ||
12582 | if ((unsigned long) imm_expr.X_add_number | |
12583 | > (unsigned long) OP_MASK_VECBYTE) | |
12584 | { | |
12585 | as_bad (_("bad byte vector index (%ld)"), | |
12586 | (long) imm_expr.X_add_number); | |
12587 | imm_expr.X_add_number = 0; | |
12588 | } | |
12589 | ||
12590 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12591 | imm_expr.X_op = O_absent; | |
12592 | s = expr_end; | |
12593 | continue; | |
12594 | ||
12595 | case '%': | |
12596 | gas_assert (!mips_opts.micromips); | |
12597 | my_getExpression (&imm_expr, s); | |
12598 | check_absolute_expr (ip, &imm_expr); | |
12599 | ||
12600 | if ((unsigned long) imm_expr.X_add_number | |
12601 | > (unsigned long) OP_MASK_VECALIGN) | |
12602 | { | |
12603 | as_bad (_("bad byte vector index (%ld)"), | |
12604 | (long) imm_expr.X_add_number); | |
12605 | imm_expr.X_add_number = 0; | |
12606 | } | |
12607 | ||
12608 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12609 | imm_expr.X_op = O_absent; | |
12610 | s = expr_end; | |
12611 | continue; | |
12612 | ||
12613 | case 'm': /* Opcode extension character. */ | |
12614 | gas_assert (mips_opts.micromips); | |
12615 | c = *++args; | |
12616 | switch (c) | |
12617 | { | |
12618 | case 'r': | |
12619 | if (strncmp (s, "$pc", 3) == 0) | |
12620 | { | |
12621 | s += 3; | |
12622 | continue; | |
12623 | } | |
12624 | break; | |
12625 | ||
12626 | case 'a': | |
12627 | case 'b': | |
12628 | case 'c': | |
12629 | case 'd': | |
12630 | case 'e': | |
12631 | case 'f': | |
12632 | case 'g': | |
12633 | case 'h': | |
12634 | case 'i': | |
12635 | case 'j': | |
12636 | case 'l': | |
12637 | case 'm': | |
12638 | case 'n': | |
12639 | case 'p': | |
12640 | case 'q': | |
12641 | case 's': | |
12642 | case 't': | |
12643 | case 'x': | |
12644 | case 'y': | |
12645 | case 'z': | |
12646 | s_reset = s; | |
12647 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12648 | if (regno == AT && mips_opts.at) | |
12649 | { | |
12650 | if (mips_opts.at == ATREG) | |
12651 | as_warn (_("Used $at without \".set noat\"")); | |
12652 | else | |
12653 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12654 | regno, mips_opts.at); | |
12655 | } | |
12656 | if (!ok) | |
12657 | { | |
12658 | if (c == 'c') | |
12659 | { | |
12660 | gas_assert (args[1] == ','); | |
12661 | regno = lastregno; | |
12662 | ++args; | |
12663 | } | |
12664 | else if (c == 't') | |
12665 | { | |
12666 | gas_assert (args[1] == ','); | |
12667 | ++args; | |
12668 | continue; /* Nothing to do. */ | |
12669 | } | |
12670 | else | |
12671 | break; | |
12672 | } | |
12673 | ||
12674 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12675 | { | |
12676 | if (regno == lastregno) | |
12677 | { | |
12678 | insn_error | |
12679 | = _("Source and destination must be different"); | |
12680 | continue; | |
12681 | } | |
12682 | if (regno == 31 && lastregno == 0xffffffff) | |
12683 | { | |
12684 | insn_error | |
12685 | = _("A destination register must be supplied"); | |
12686 | continue; | |
12687 | } | |
12688 | } | |
12689 | ||
12690 | if (*s == ' ') | |
12691 | ++s; | |
12692 | if (args[1] != *s) | |
12693 | { | |
12694 | if (c == 'e') | |
12695 | { | |
12696 | gas_assert (args[1] == ','); | |
12697 | regno = lastregno; | |
12698 | s = s_reset; | |
12699 | ++args; | |
12700 | } | |
12701 | else if (c == 't') | |
12702 | { | |
12703 | gas_assert (args[1] == ','); | |
12704 | s = s_reset; | |
12705 | ++args; | |
12706 | continue; /* Nothing to do. */ | |
12707 | } | |
12708 | } | |
12709 | ||
12710 | /* Make sure regno is the same as lastregno. */ | |
12711 | if (c == 't' && regno != lastregno) | |
12712 | break; | |
12713 | ||
12714 | /* Make sure regno is the same as destregno. */ | |
12715 | if (c == 'x' && regno != destregno) | |
12716 | break; | |
12717 | ||
12718 | /* We need to save regno, before regno maps to the | |
12719 | microMIPS register encoding. */ | |
12720 | lastregno = regno; | |
12721 | ||
12722 | if (c == 'f') | |
12723 | destregno = regno; | |
12724 | ||
12725 | switch (c) | |
12726 | { | |
12727 | case 'a': | |
12728 | if (regno != GP) | |
12729 | regno = ILLEGAL_REG; | |
12730 | break; | |
12731 | ||
12732 | case 'b': | |
12733 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12734 | break; | |
12735 | ||
12736 | case 'c': | |
12737 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12738 | break; | |
12739 | ||
12740 | case 'd': | |
12741 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12742 | break; | |
12743 | ||
12744 | case 'e': | |
12745 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12746 | break; | |
12747 | ||
12748 | case 'f': | |
12749 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12750 | break; | |
12751 | ||
12752 | case 'g': | |
12753 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12754 | break; | |
12755 | ||
12756 | case 'h': | |
12757 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12758 | break; | |
12759 | ||
12760 | case 'i': | |
12761 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12762 | { | |
12763 | case 4: | |
12764 | if (regno == 21) | |
12765 | regno = 3; | |
12766 | else if (regno == 22) | |
12767 | regno = 4; | |
12768 | else if (regno == 5) | |
12769 | regno = 5; | |
12770 | else if (regno == 6) | |
12771 | regno = 6; | |
12772 | else if (regno == 7) | |
12773 | regno = 7; | |
12774 | else | |
12775 | regno = ILLEGAL_REG; | |
12776 | break; | |
12777 | ||
12778 | case 5: | |
12779 | if (regno == 6) | |
12780 | regno = 0; | |
12781 | else if (regno == 7) | |
12782 | regno = 1; | |
12783 | else | |
12784 | regno = ILLEGAL_REG; | |
12785 | break; | |
12786 | ||
12787 | case 6: | |
12788 | if (regno == 7) | |
12789 | regno = 2; | |
12790 | else | |
12791 | regno = ILLEGAL_REG; | |
12792 | break; | |
12793 | ||
12794 | default: | |
12795 | regno = ILLEGAL_REG; | |
12796 | break; | |
12797 | } | |
12798 | break; | |
12799 | ||
12800 | case 'l': | |
12801 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12802 | break; | |
12803 | ||
12804 | case 'm': | |
12805 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12806 | break; | |
12807 | ||
12808 | case 'n': | |
12809 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12810 | break; | |
12811 | ||
12812 | case 'q': | |
12813 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12814 | break; | |
12815 | ||
12816 | case 's': | |
12817 | if (regno != SP) | |
12818 | regno = ILLEGAL_REG; | |
12819 | break; | |
12820 | ||
12821 | case 'y': | |
12822 | if (regno != 31) | |
12823 | regno = ILLEGAL_REG; | |
12824 | break; | |
12825 | ||
12826 | case 'z': | |
12827 | if (regno != ZERO) | |
12828 | regno = ILLEGAL_REG; | |
12829 | break; | |
12830 | ||
12831 | case 'j': /* Do nothing. */ | |
12832 | case 'p': | |
12833 | case 't': | |
12834 | case 'x': | |
12835 | break; | |
12836 | ||
12837 | default: | |
12838 | internalError (); | |
12839 | } | |
12840 | ||
12841 | if (regno == ILLEGAL_REG) | |
12842 | break; | |
12843 | ||
12844 | switch (c) | |
12845 | { | |
12846 | case 'b': | |
12847 | INSERT_OPERAND (1, MB, *ip, regno); | |
12848 | break; | |
12849 | ||
12850 | case 'c': | |
12851 | INSERT_OPERAND (1, MC, *ip, regno); | |
12852 | break; | |
12853 | ||
12854 | case 'd': | |
12855 | INSERT_OPERAND (1, MD, *ip, regno); | |
12856 | break; | |
12857 | ||
12858 | case 'e': | |
12859 | INSERT_OPERAND (1, ME, *ip, regno); | |
12860 | break; | |
12861 | ||
12862 | case 'f': | |
12863 | INSERT_OPERAND (1, MF, *ip, regno); | |
12864 | break; | |
12865 | ||
12866 | case 'g': | |
12867 | INSERT_OPERAND (1, MG, *ip, regno); | |
12868 | break; | |
12869 | ||
12870 | case 'h': | |
12871 | INSERT_OPERAND (1, MH, *ip, regno); | |
12872 | break; | |
12873 | ||
12874 | case 'i': | |
12875 | INSERT_OPERAND (1, MI, *ip, regno); | |
12876 | break; | |
12877 | ||
12878 | case 'j': | |
12879 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12880 | break; | |
12881 | ||
12882 | case 'l': | |
12883 | INSERT_OPERAND (1, ML, *ip, regno); | |
12884 | break; | |
12885 | ||
12886 | case 'm': | |
12887 | INSERT_OPERAND (1, MM, *ip, regno); | |
12888 | break; | |
12889 | ||
12890 | case 'n': | |
12891 | INSERT_OPERAND (1, MN, *ip, regno); | |
12892 | break; | |
12893 | ||
12894 | case 'p': | |
12895 | INSERT_OPERAND (1, MP, *ip, regno); | |
12896 | break; | |
12897 | ||
12898 | case 'q': | |
12899 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12900 | break; | |
12901 | ||
12902 | case 'a': /* Do nothing. */ | |
12903 | case 's': /* Do nothing. */ | |
12904 | case 't': /* Do nothing. */ | |
12905 | case 'x': /* Do nothing. */ | |
12906 | case 'y': /* Do nothing. */ | |
12907 | case 'z': /* Do nothing. */ | |
12908 | break; | |
12909 | ||
12910 | default: | |
12911 | internalError (); | |
12912 | } | |
12913 | continue; | |
12914 | ||
12915 | case 'A': | |
12916 | { | |
12917 | bfd_reloc_code_real_type r[3]; | |
12918 | expressionS ep; | |
12919 | int imm; | |
12920 | ||
12921 | /* Check whether there is only a single bracketed | |
12922 | expression left. If so, it must be the base register | |
12923 | and the constant must be zero. */ | |
12924 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12925 | { | |
12926 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12927 | continue; | |
12928 | } | |
12929 | ||
12930 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12931 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12932 | break; | |
12933 | ||
12934 | imm = ep.X_add_number >> 2; | |
12935 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12936 | } | |
12937 | s = expr_end; | |
12938 | continue; | |
12939 | ||
12940 | case 'B': | |
12941 | { | |
12942 | bfd_reloc_code_real_type r[3]; | |
12943 | expressionS ep; | |
12944 | int imm; | |
12945 | ||
12946 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12947 | || ep.X_op != O_constant) | |
12948 | break; | |
12949 | ||
12950 | for (imm = 0; imm < 8; imm++) | |
12951 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12952 | break; | |
12953 | if (imm >= 8) | |
12954 | break; | |
12955 | ||
12956 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12957 | } | |
12958 | s = expr_end; | |
12959 | continue; | |
12960 | ||
12961 | case 'C': | |
12962 | { | |
12963 | bfd_reloc_code_real_type r[3]; | |
12964 | expressionS ep; | |
12965 | int imm; | |
12966 | ||
12967 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12968 | || ep.X_op != O_constant) | |
12969 | break; | |
12970 | ||
12971 | for (imm = 0; imm < 16; imm++) | |
12972 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12973 | break; | |
12974 | if (imm >= 16) | |
12975 | break; | |
12976 | ||
12977 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12978 | } | |
12979 | s = expr_end; | |
12980 | continue; | |
12981 | ||
12982 | case 'D': /* pc relative offset */ | |
12983 | case 'E': /* pc relative offset */ | |
12984 | my_getExpression (&offset_expr, s); | |
12985 | if (offset_expr.X_op == O_register) | |
12986 | break; | |
12987 | ||
40209cad MR |
12988 | if (!forced_insn_length) |
12989 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12990 | else if (c == 'D') | |
12991 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12992 | else | |
12993 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12994 | s = expr_end; |
12995 | continue; | |
12996 | ||
12997 | case 'F': | |
12998 | { | |
12999 | bfd_reloc_code_real_type r[3]; | |
13000 | expressionS ep; | |
13001 | int imm; | |
13002 | ||
13003 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13004 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13005 | break; | |
13006 | ||
13007 | imm = ep.X_add_number; | |
13008 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13009 | } | |
13010 | s = expr_end; | |
13011 | continue; | |
13012 | ||
13013 | case 'G': | |
13014 | { | |
13015 | bfd_reloc_code_real_type r[3]; | |
13016 | expressionS ep; | |
13017 | int imm; | |
13018 | ||
13019 | /* Check whether there is only a single bracketed | |
13020 | expression left. If so, it must be the base register | |
13021 | and the constant must be zero. */ | |
13022 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13023 | { | |
13024 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13025 | continue; | |
13026 | } | |
13027 | ||
13028 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13029 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13030 | break; | |
13031 | ||
13032 | imm = ep.X_add_number & 15; | |
13033 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13034 | } | |
13035 | s = expr_end; | |
13036 | continue; | |
13037 | ||
13038 | case 'H': | |
13039 | { | |
13040 | bfd_reloc_code_real_type r[3]; | |
13041 | expressionS ep; | |
13042 | int imm; | |
13043 | ||
13044 | /* Check whether there is only a single bracketed | |
13045 | expression left. If so, it must be the base register | |
13046 | and the constant must be zero. */ | |
13047 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13048 | { | |
13049 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13050 | continue; | |
13051 | } | |
13052 | ||
13053 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13054 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13055 | break; | |
13056 | ||
13057 | imm = ep.X_add_number >> 1; | |
13058 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13059 | } | |
13060 | s = expr_end; | |
13061 | continue; | |
13062 | ||
13063 | case 'I': | |
13064 | { | |
13065 | bfd_reloc_code_real_type r[3]; | |
13066 | expressionS ep; | |
13067 | int imm; | |
13068 | ||
13069 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13070 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13071 | break; | |
13072 | ||
13073 | imm = ep.X_add_number & 127; | |
13074 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13075 | } | |
13076 | s = expr_end; | |
13077 | continue; | |
13078 | ||
13079 | case 'J': | |
13080 | { | |
13081 | bfd_reloc_code_real_type r[3]; | |
13082 | expressionS ep; | |
13083 | int imm; | |
13084 | ||
13085 | /* Check whether there is only a single bracketed | |
13086 | expression left. If so, it must be the base register | |
13087 | and the constant must be zero. */ | |
13088 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13089 | { | |
13090 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13091 | continue; | |
13092 | } | |
13093 | ||
13094 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13095 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13096 | break; | |
13097 | ||
13098 | imm = ep.X_add_number >> 2; | |
13099 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13100 | } | |
13101 | s = expr_end; | |
13102 | continue; | |
13103 | ||
13104 | case 'L': | |
13105 | { | |
13106 | bfd_reloc_code_real_type r[3]; | |
13107 | expressionS ep; | |
13108 | int imm; | |
13109 | ||
13110 | /* Check whether there is only a single bracketed | |
13111 | expression left. If so, it must be the base register | |
13112 | and the constant must be zero. */ | |
13113 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13114 | { | |
13115 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13116 | continue; | |
13117 | } | |
13118 | ||
13119 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13120 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13121 | break; | |
13122 | ||
13123 | imm = ep.X_add_number; | |
13124 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13125 | } | |
13126 | s = expr_end; | |
13127 | continue; | |
13128 | ||
13129 | case 'M': | |
13130 | { | |
13131 | bfd_reloc_code_real_type r[3]; | |
13132 | expressionS ep; | |
13133 | int imm; | |
13134 | ||
13135 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13136 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13137 | break; | |
13138 | ||
13139 | imm = ep.X_add_number & 7; | |
13140 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13141 | } | |
13142 | s = expr_end; | |
13143 | continue; | |
13144 | ||
13145 | case 'N': /* Register list for lwm and swm. */ | |
13146 | { | |
13147 | /* A comma-separated list of registers and/or | |
13148 | dash-separated contiguous ranges including | |
13149 | both ra and a set of one or more registers | |
13150 | starting at s0 up to s3 which have to be | |
13151 | consecutive, e.g.: | |
13152 | ||
13153 | s0, ra | |
13154 | s0, s1, ra, s2, s3 | |
13155 | s0-s2, ra | |
13156 | ||
13157 | and any permutations of these. */ | |
13158 | unsigned int reglist; | |
13159 | int imm; | |
13160 | ||
13161 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13162 | break; | |
13163 | ||
13164 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13165 | break; | |
13166 | ||
13167 | reglist = (reglist >> 17) & 7; | |
13168 | reglist += 1; | |
13169 | if ((reglist & -reglist) != reglist) | |
13170 | break; | |
252b5132 | 13171 | |
df58fc94 RS |
13172 | imm = ffs (reglist) - 1; |
13173 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13174 | } | |
13175 | continue; | |
252b5132 | 13176 | |
df58fc94 RS |
13177 | case 'O': /* sdbbp 4-bit code. */ |
13178 | { | |
13179 | bfd_reloc_code_real_type r[3]; | |
13180 | expressionS ep; | |
13181 | int imm; | |
13182 | ||
13183 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13184 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13185 | break; | |
13186 | ||
13187 | imm = ep.X_add_number; | |
13188 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13189 | } |
df58fc94 RS |
13190 | s = expr_end; |
13191 | continue; | |
252b5132 | 13192 | |
df58fc94 RS |
13193 | case 'P': |
13194 | { | |
13195 | bfd_reloc_code_real_type r[3]; | |
13196 | expressionS ep; | |
13197 | int imm; | |
5e0116d5 | 13198 | |
df58fc94 RS |
13199 | if (my_getSmallExpression (&ep, r, s) > 0 |
13200 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13201 | break; | |
5e0116d5 | 13202 | |
df58fc94 RS |
13203 | imm = ep.X_add_number >> 2; |
13204 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13205 | } | |
13206 | s = expr_end; | |
13207 | continue; | |
5e0116d5 | 13208 | |
df58fc94 RS |
13209 | case 'Q': |
13210 | { | |
13211 | bfd_reloc_code_real_type r[3]; | |
13212 | expressionS ep; | |
13213 | int imm; | |
5e0116d5 | 13214 | |
df58fc94 RS |
13215 | if (my_getSmallExpression (&ep, r, s) > 0 |
13216 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13217 | break; | |
252b5132 | 13218 | |
df58fc94 RS |
13219 | imm = ep.X_add_number >> 2; |
13220 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13221 | } | |
13222 | s = expr_end; | |
13223 | continue; | |
4614d845 | 13224 | |
df58fc94 RS |
13225 | case 'U': |
13226 | { | |
13227 | bfd_reloc_code_real_type r[3]; | |
13228 | expressionS ep; | |
13229 | int imm; | |
13230 | ||
13231 | /* Check whether there is only a single bracketed | |
13232 | expression left. If so, it must be the base register | |
13233 | and the constant must be zero. */ | |
13234 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13235 | { | |
13236 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13237 | continue; | |
13238 | } | |
13239 | ||
13240 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13241 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13242 | break; | |
13243 | ||
13244 | imm = ep.X_add_number >> 2; | |
13245 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13246 | } | |
13247 | s = expr_end; | |
5e0116d5 | 13248 | continue; |
252b5132 | 13249 | |
df58fc94 RS |
13250 | case 'W': |
13251 | { | |
13252 | bfd_reloc_code_real_type r[3]; | |
13253 | expressionS ep; | |
13254 | int imm; | |
252b5132 | 13255 | |
df58fc94 RS |
13256 | if (my_getSmallExpression (&ep, r, s) > 0 |
13257 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13258 | break; | |
252b5132 | 13259 | |
df58fc94 RS |
13260 | imm = ep.X_add_number >> 2; |
13261 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13262 | } | |
13263 | s = expr_end; | |
13264 | continue; | |
252b5132 | 13265 | |
df58fc94 RS |
13266 | case 'X': |
13267 | { | |
13268 | bfd_reloc_code_real_type r[3]; | |
13269 | expressionS ep; | |
13270 | int imm; | |
252b5132 | 13271 | |
df58fc94 RS |
13272 | if (my_getSmallExpression (&ep, r, s) > 0 |
13273 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13274 | break; | |
252b5132 | 13275 | |
df58fc94 RS |
13276 | imm = ep.X_add_number; |
13277 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13278 | } | |
13279 | s = expr_end; | |
13280 | continue; | |
252b5132 | 13281 | |
df58fc94 RS |
13282 | case 'Y': |
13283 | { | |
13284 | bfd_reloc_code_real_type r[3]; | |
13285 | expressionS ep; | |
13286 | int imm; | |
156c2f8b | 13287 | |
df58fc94 RS |
13288 | if (my_getSmallExpression (&ep, r, s) > 0 |
13289 | || expr_const_in_range (&ep, -2, 2, 2) | |
13290 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13291 | break; | |
156c2f8b | 13292 | |
df58fc94 RS |
13293 | imm = ep.X_add_number >> 2; |
13294 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13295 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13296 | } | |
13297 | s = expr_end; | |
13298 | continue; | |
60b63b72 | 13299 | |
df58fc94 RS |
13300 | case 'Z': |
13301 | { | |
13302 | bfd_reloc_code_real_type r[3]; | |
13303 | expressionS ep; | |
13304 | ||
13305 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13306 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13307 | break; | |
13308 | } | |
13309 | s = expr_end; | |
13310 | continue; | |
13311 | ||
13312 | default: | |
13313 | as_bad (_("Internal error: bad microMIPS opcode " | |
13314 | "(unknown extension operand type `m%c'): %s %s"), | |
13315 | *args, insn->name, insn->args); | |
13316 | /* Further processing is fruitless. */ | |
13317 | return; | |
60b63b72 | 13318 | } |
df58fc94 | 13319 | break; |
60b63b72 | 13320 | |
df58fc94 RS |
13321 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13322 | gas_assert (mips_opts.micromips); | |
13323 | { | |
13324 | /* A comma-separated list of registers and/or | |
13325 | dash-separated contiguous ranges including | |
13326 | at least one of ra and a set of one or more | |
13327 | registers starting at s0 up to s7 and then | |
13328 | s8 which have to be consecutive, e.g.: | |
13329 | ||
13330 | ra | |
13331 | s0 | |
13332 | ra, s0, s1, s2 | |
13333 | s0-s8 | |
13334 | s0-s5, ra | |
13335 | ||
13336 | and any permutations of these. */ | |
13337 | unsigned int reglist; | |
13338 | int imm; | |
13339 | int ra; | |
13340 | ||
13341 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13342 | break; | |
13343 | ||
13344 | if ((reglist & 0x3f00ffff) != 0) | |
13345 | break; | |
13346 | ||
13347 | ra = (reglist >> 27) & 0x10; | |
13348 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13349 | reglist += 1; | |
13350 | if ((reglist & -reglist) != reglist) | |
13351 | break; | |
13352 | ||
13353 | imm = (ffs (reglist) - 1) | ra; | |
13354 | INSERT_OPERAND (1, RT, *ip, imm); | |
13355 | imm_expr.X_op = O_absent; | |
13356 | } | |
60b63b72 RS |
13357 | continue; |
13358 | ||
df58fc94 RS |
13359 | case '|': /* 4-bit trap code. */ |
13360 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13361 | my_getExpression (&imm_expr, s); |
13362 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13363 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13364 | > MICROMIPSOP_MASK_TRAP) |
13365 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13366 | (unsigned long) imm_expr.X_add_number, | |
13367 | ip->insn_mo->name); | |
13368 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13369 | imm_expr.X_op = O_absent; |
13370 | s = expr_end; | |
13371 | continue; | |
13372 | ||
252b5132 | 13373 | default: |
f71d0d44 | 13374 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13375 | internalError (); |
13376 | } | |
13377 | break; | |
13378 | } | |
13379 | /* Args don't match. */ | |
df58fc94 RS |
13380 | s = argsStart; |
13381 | insn_error = _("Illegal operands"); | |
13382 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13383 | { |
13384 | ++insn; | |
252b5132 RH |
13385 | continue; |
13386 | } | |
df58fc94 RS |
13387 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13388 | { | |
13389 | gas_assert (firstinsn); | |
13390 | need_delay_slot_ok = FALSE; | |
13391 | past = insn + 1; | |
13392 | insn = firstinsn; | |
13393 | continue; | |
13394 | } | |
252b5132 RH |
13395 | return; |
13396 | } | |
13397 | } | |
13398 | ||
0499d65b TS |
13399 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13400 | ||
252b5132 RH |
13401 | /* This routine assembles an instruction into its binary format when |
13402 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13403 | global variables imm_reloc or offset_reloc to the type of relocation |
13404 | to do if one of the operands is an address expression. It also sets | |
13405 | forced_insn_length to the resulting instruction size in bytes if the | |
13406 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13407 | |
13408 | static void | |
17a2f251 | 13409 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13410 | { |
13411 | char *s; | |
13412 | const char *args; | |
13413 | struct mips_opcode *insn; | |
13414 | char *argsstart; | |
13415 | unsigned int regno; | |
13416 | unsigned int lastregno = 0; | |
13417 | char *s_reset; | |
d6f16593 | 13418 | size_t i; |
252b5132 RH |
13419 | |
13420 | insn_error = NULL; | |
13421 | ||
df58fc94 | 13422 | forced_insn_length = 0; |
252b5132 | 13423 | |
3882b010 | 13424 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13425 | ; |
13426 | switch (*s) | |
13427 | { | |
13428 | case '\0': | |
13429 | break; | |
13430 | ||
13431 | case ' ': | |
13432 | *s++ = '\0'; | |
13433 | break; | |
13434 | ||
13435 | case '.': | |
13436 | if (s[1] == 't' && s[2] == ' ') | |
13437 | { | |
13438 | *s = '\0'; | |
df58fc94 | 13439 | forced_insn_length = 2; |
252b5132 RH |
13440 | s += 3; |
13441 | break; | |
13442 | } | |
13443 | else if (s[1] == 'e' && s[2] == ' ') | |
13444 | { | |
13445 | *s = '\0'; | |
df58fc94 | 13446 | forced_insn_length = 4; |
252b5132 RH |
13447 | s += 3; |
13448 | break; | |
13449 | } | |
13450 | /* Fall through. */ | |
13451 | default: | |
13452 | insn_error = _("unknown opcode"); | |
13453 | return; | |
13454 | } | |
13455 | ||
df58fc94 RS |
13456 | if (mips_opts.noautoextend && !forced_insn_length) |
13457 | forced_insn_length = 2; | |
252b5132 RH |
13458 | |
13459 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13460 | { | |
13461 | insn_error = _("unrecognized opcode"); | |
13462 | return; | |
13463 | } | |
13464 | ||
13465 | argsstart = s; | |
13466 | for (;;) | |
13467 | { | |
9b3f89ee TS |
13468 | bfd_boolean ok; |
13469 | ||
9c2799c2 | 13470 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13471 | |
037b32b9 | 13472 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13473 | if (! ok) |
13474 | { | |
13475 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13476 | && strcmp (insn->name, insn[1].name) == 0) | |
13477 | { | |
13478 | ++insn; | |
13479 | continue; | |
13480 | } | |
13481 | else | |
13482 | { | |
13483 | if (!insn_error) | |
13484 | { | |
13485 | static char buf[100]; | |
13486 | sprintf (buf, | |
7bd942df | 13487 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13488 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13489 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13490 | insn_error = buf; | |
13491 | } | |
13492 | return; | |
13493 | } | |
13494 | } | |
13495 | ||
1e915849 | 13496 | create_insn (ip, insn); |
252b5132 | 13497 | imm_expr.X_op = O_absent; |
f6688943 TS |
13498 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13499 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13500 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13501 | imm2_expr.X_op = O_absent; |
252b5132 | 13502 | offset_expr.X_op = O_absent; |
f6688943 TS |
13503 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13504 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13505 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13506 | for (args = insn->args; 1; ++args) |
13507 | { | |
13508 | int c; | |
13509 | ||
13510 | if (*s == ' ') | |
13511 | ++s; | |
13512 | ||
13513 | /* In this switch statement we call break if we did not find | |
13514 | a match, continue if we did find a match, or return if we | |
13515 | are done. */ | |
13516 | ||
13517 | c = *args; | |
13518 | switch (c) | |
13519 | { | |
13520 | case '\0': | |
13521 | if (*s == '\0') | |
13522 | { | |
b886a2ab RS |
13523 | offsetT value; |
13524 | ||
252b5132 RH |
13525 | /* Stuff the immediate value in now, if we can. */ |
13526 | if (imm_expr.X_op == O_constant | |
f6688943 | 13527 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13528 | && insn->pinfo != INSN_MACRO |
13529 | && calculate_reloc (*offset_reloc, | |
13530 | imm_expr.X_add_number, &value)) | |
252b5132 | 13531 | { |
c4e7957c | 13532 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13533 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13534 | &ip->insn_opcode); |
252b5132 | 13535 | imm_expr.X_op = O_absent; |
f6688943 | 13536 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13537 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13538 | } |
13539 | ||
13540 | return; | |
13541 | } | |
13542 | break; | |
13543 | ||
13544 | case ',': | |
13545 | if (*s++ == c) | |
13546 | continue; | |
13547 | s--; | |
13548 | switch (*++args) | |
13549 | { | |
13550 | case 'v': | |
bf12938e | 13551 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13552 | continue; |
13553 | case 'w': | |
bf12938e | 13554 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13555 | continue; |
13556 | } | |
13557 | break; | |
13558 | ||
13559 | case '(': | |
13560 | case ')': | |
13561 | if (*s++ == c) | |
13562 | continue; | |
13563 | break; | |
13564 | ||
13565 | case 'v': | |
13566 | case 'w': | |
13567 | if (s[0] != '$') | |
13568 | { | |
13569 | if (c == 'v') | |
bf12938e | 13570 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13571 | else |
bf12938e | 13572 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13573 | ++args; |
13574 | continue; | |
13575 | } | |
13576 | /* Fall through. */ | |
13577 | case 'x': | |
13578 | case 'y': | |
13579 | case 'z': | |
13580 | case 'Z': | |
13581 | case '0': | |
13582 | case 'S': | |
13583 | case 'R': | |
13584 | case 'X': | |
13585 | case 'Y': | |
707bfff6 TS |
13586 | s_reset = s; |
13587 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13588 | { |
707bfff6 | 13589 | if (c == 'v' || c == 'w') |
85b51719 | 13590 | { |
707bfff6 | 13591 | if (c == 'v') |
a9e24354 | 13592 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13593 | else |
a9e24354 | 13594 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13595 | ++args; |
13596 | continue; | |
85b51719 | 13597 | } |
707bfff6 | 13598 | break; |
252b5132 RH |
13599 | } |
13600 | ||
13601 | if (*s == ' ') | |
13602 | ++s; | |
13603 | if (args[1] != *s) | |
13604 | { | |
13605 | if (c == 'v' || c == 'w') | |
13606 | { | |
13607 | regno = mips16_to_32_reg_map[lastregno]; | |
13608 | s = s_reset; | |
f9419b05 | 13609 | ++args; |
252b5132 RH |
13610 | } |
13611 | } | |
13612 | ||
13613 | switch (c) | |
13614 | { | |
13615 | case 'x': | |
13616 | case 'y': | |
13617 | case 'z': | |
13618 | case 'v': | |
13619 | case 'w': | |
13620 | case 'Z': | |
13621 | regno = mips32_to_16_reg_map[regno]; | |
13622 | break; | |
13623 | ||
13624 | case '0': | |
13625 | if (regno != 0) | |
13626 | regno = ILLEGAL_REG; | |
13627 | break; | |
13628 | ||
13629 | case 'S': | |
13630 | if (regno != SP) | |
13631 | regno = ILLEGAL_REG; | |
13632 | break; | |
13633 | ||
13634 | case 'R': | |
13635 | if (regno != RA) | |
13636 | regno = ILLEGAL_REG; | |
13637 | break; | |
13638 | ||
13639 | case 'X': | |
13640 | case 'Y': | |
741fe287 MR |
13641 | if (regno == AT && mips_opts.at) |
13642 | { | |
13643 | if (mips_opts.at == ATREG) | |
13644 | as_warn (_("used $at without \".set noat\"")); | |
13645 | else | |
13646 | as_warn (_("used $%u with \".set at=$%u\""), | |
13647 | regno, mips_opts.at); | |
13648 | } | |
252b5132 RH |
13649 | break; |
13650 | ||
13651 | default: | |
13652 | internalError (); | |
13653 | } | |
13654 | ||
13655 | if (regno == ILLEGAL_REG) | |
13656 | break; | |
13657 | ||
13658 | switch (c) | |
13659 | { | |
13660 | case 'x': | |
13661 | case 'v': | |
bf12938e | 13662 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13663 | break; |
13664 | case 'y': | |
13665 | case 'w': | |
bf12938e | 13666 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13667 | break; |
13668 | case 'z': | |
bf12938e | 13669 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13670 | break; |
13671 | case 'Z': | |
bf12938e | 13672 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13673 | case '0': |
13674 | case 'S': | |
13675 | case 'R': | |
13676 | break; | |
13677 | case 'X': | |
bf12938e | 13678 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13679 | break; |
13680 | case 'Y': | |
13681 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13682 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13683 | break; |
13684 | default: | |
13685 | internalError (); | |
13686 | } | |
13687 | ||
13688 | lastregno = regno; | |
13689 | continue; | |
13690 | ||
13691 | case 'P': | |
13692 | if (strncmp (s, "$pc", 3) == 0) | |
13693 | { | |
13694 | s += 3; | |
13695 | continue; | |
13696 | } | |
13697 | break; | |
13698 | ||
252b5132 RH |
13699 | case '5': |
13700 | case 'H': | |
13701 | case 'W': | |
13702 | case 'D': | |
13703 | case 'j': | |
252b5132 RH |
13704 | case 'V': |
13705 | case 'C': | |
13706 | case 'U': | |
13707 | case 'k': | |
13708 | case 'K': | |
d6f16593 MR |
13709 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13710 | if (i > 0) | |
252b5132 | 13711 | { |
d6f16593 | 13712 | if (imm_expr.X_op != O_constant) |
252b5132 | 13713 | { |
df58fc94 | 13714 | forced_insn_length = 4; |
5c04167a | 13715 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13716 | } |
d6f16593 MR |
13717 | else |
13718 | { | |
13719 | /* We need to relax this instruction. */ | |
13720 | *offset_reloc = *imm_reloc; | |
13721 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13722 | } | |
13723 | s = expr_end; | |
13724 | continue; | |
252b5132 | 13725 | } |
d6f16593 MR |
13726 | *imm_reloc = BFD_RELOC_UNUSED; |
13727 | /* Fall through. */ | |
13728 | case '<': | |
13729 | case '>': | |
13730 | case '[': | |
13731 | case ']': | |
13732 | case '4': | |
13733 | case '8': | |
13734 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13735 | if (imm_expr.X_op == O_register) |
13736 | { | |
13737 | /* What we thought was an expression turned out to | |
13738 | be a register. */ | |
13739 | ||
13740 | if (s[0] == '(' && args[1] == '(') | |
13741 | { | |
13742 | /* It looks like the expression was omitted | |
13743 | before a register indirection, which means | |
13744 | that the expression is implicitly zero. We | |
13745 | still set up imm_expr, so that we handle | |
13746 | explicit extensions correctly. */ | |
13747 | imm_expr.X_op = O_constant; | |
13748 | imm_expr.X_add_number = 0; | |
f6688943 | 13749 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13750 | continue; |
13751 | } | |
13752 | ||
13753 | break; | |
13754 | } | |
13755 | ||
13756 | /* We need to relax this instruction. */ | |
f6688943 | 13757 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13758 | s = expr_end; |
13759 | continue; | |
13760 | ||
13761 | case 'p': | |
13762 | case 'q': | |
13763 | case 'A': | |
13764 | case 'B': | |
13765 | case 'E': | |
13766 | /* We use offset_reloc rather than imm_reloc for the PC | |
13767 | relative operands. This lets macros with both | |
13768 | immediate and address operands work correctly. */ | |
13769 | my_getExpression (&offset_expr, s); | |
13770 | ||
13771 | if (offset_expr.X_op == O_register) | |
13772 | break; | |
13773 | ||
13774 | /* We need to relax this instruction. */ | |
f6688943 | 13775 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13776 | s = expr_end; |
13777 | continue; | |
13778 | ||
13779 | case '6': /* break code */ | |
13780 | my_getExpression (&imm_expr, s); | |
13781 | check_absolute_expr (ip, &imm_expr); | |
13782 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13783 | as_warn (_("Invalid value for `%s' (%lu)"), |
13784 | ip->insn_mo->name, | |
13785 | (unsigned long) imm_expr.X_add_number); | |
13786 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13787 | imm_expr.X_op = O_absent; |
13788 | s = expr_end; | |
13789 | continue; | |
13790 | ||
13791 | case 'a': /* 26 bit address */ | |
13792 | my_getExpression (&offset_expr, s); | |
13793 | s = expr_end; | |
f6688943 | 13794 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13795 | ip->insn_opcode <<= 16; |
13796 | continue; | |
13797 | ||
13798 | case 'l': /* register list for entry macro */ | |
13799 | case 'L': /* register list for exit macro */ | |
13800 | { | |
13801 | int mask; | |
13802 | ||
13803 | if (c == 'l') | |
13804 | mask = 0; | |
13805 | else | |
13806 | mask = 7 << 3; | |
13807 | while (*s != '\0') | |
13808 | { | |
707bfff6 | 13809 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13810 | |
13811 | while (*s == ' ' || *s == ',') | |
13812 | ++s; | |
707bfff6 | 13813 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13814 | freg = 0; |
707bfff6 TS |
13815 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13816 | freg = 1; | |
252b5132 RH |
13817 | else |
13818 | { | |
707bfff6 TS |
13819 | as_bad (_("can't parse register list")); |
13820 | break; | |
252b5132 RH |
13821 | } |
13822 | if (*s == ' ') | |
13823 | ++s; | |
13824 | if (*s != '-') | |
13825 | reg2 = reg1; | |
13826 | else | |
13827 | { | |
13828 | ++s; | |
707bfff6 TS |
13829 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13830 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13831 | { |
707bfff6 TS |
13832 | as_bad (_("invalid register list")); |
13833 | break; | |
252b5132 RH |
13834 | } |
13835 | } | |
13836 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13837 | { | |
13838 | mask &= ~ (7 << 3); | |
13839 | mask |= 5 << 3; | |
13840 | } | |
13841 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13842 | { | |
13843 | mask &= ~ (7 << 3); | |
13844 | mask |= 6 << 3; | |
13845 | } | |
13846 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13847 | mask |= (reg2 - 3) << 3; | |
13848 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13849 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13850 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13851 | mask |= 1; |
13852 | else | |
13853 | { | |
13854 | as_bad (_("invalid register list")); | |
13855 | break; | |
13856 | } | |
13857 | } | |
13858 | /* The mask is filled in in the opcode table for the | |
13859 | benefit of the disassembler. We remove it before | |
13860 | applying the actual mask. */ | |
13861 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13862 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13863 | } | |
13864 | continue; | |
13865 | ||
0499d65b TS |
13866 | case 'm': /* Register list for save insn. */ |
13867 | case 'M': /* Register list for restore insn. */ | |
13868 | { | |
5c04167a | 13869 | int opcode = ip->insn_opcode; |
0499d65b | 13870 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13871 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13872 | |
13873 | while (*s != '\0') | |
13874 | { | |
13875 | unsigned int reg1, reg2; | |
13876 | ||
13877 | SKIP_SPACE_TABS (s); | |
13878 | while (*s == ',') | |
13879 | ++s; | |
13880 | SKIP_SPACE_TABS (s); | |
13881 | ||
13882 | my_getExpression (&imm_expr, s); | |
13883 | if (imm_expr.X_op == O_constant) | |
13884 | { | |
13885 | /* Handle the frame size. */ | |
13886 | if (seen_framesz) | |
13887 | { | |
13888 | as_bad (_("more than one frame size in list")); | |
13889 | break; | |
13890 | } | |
13891 | seen_framesz = 1; | |
13892 | framesz = imm_expr.X_add_number; | |
13893 | imm_expr.X_op = O_absent; | |
13894 | s = expr_end; | |
13895 | continue; | |
13896 | } | |
13897 | ||
707bfff6 | 13898 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13899 | { |
13900 | as_bad (_("can't parse register list")); | |
13901 | break; | |
13902 | } | |
0499d65b | 13903 | |
707bfff6 TS |
13904 | while (*s == ' ') |
13905 | ++s; | |
13906 | ||
0499d65b TS |
13907 | if (*s != '-') |
13908 | reg2 = reg1; | |
13909 | else | |
13910 | { | |
13911 | ++s; | |
707bfff6 TS |
13912 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13913 | || reg2 < reg1) | |
0499d65b TS |
13914 | { |
13915 | as_bad (_("can't parse register list")); | |
13916 | break; | |
13917 | } | |
0499d65b TS |
13918 | } |
13919 | ||
13920 | while (reg1 <= reg2) | |
13921 | { | |
13922 | if (reg1 >= 4 && reg1 <= 7) | |
13923 | { | |
3a93f742 | 13924 | if (!seen_framesz) |
0499d65b | 13925 | /* args $a0-$a3 */ |
91d6fa6a | 13926 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13927 | else |
13928 | /* statics $a0-$a3 */ | |
13929 | statics |= 1 << (reg1 - 4); | |
13930 | } | |
13931 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13932 | { | |
13933 | /* $s0-$s8 */ | |
13934 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13935 | } | |
13936 | else if (reg1 == 31) | |
13937 | { | |
13938 | /* Add $ra to insn. */ | |
13939 | opcode |= 0x40; | |
13940 | } | |
13941 | else | |
13942 | { | |
13943 | as_bad (_("unexpected register in list")); | |
13944 | break; | |
13945 | } | |
13946 | if (++reg1 == 24) | |
13947 | reg1 = 30; | |
13948 | } | |
13949 | } | |
13950 | ||
13951 | /* Encode args/statics combination. */ | |
91d6fa6a | 13952 | if (nargs & statics) |
0499d65b | 13953 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13954 | else if (nargs == 0xf) |
0499d65b TS |
13955 | /* All $a0-$a3 are args. */ |
13956 | opcode |= MIPS16_ALL_ARGS << 16; | |
13957 | else if (statics == 0xf) | |
13958 | /* All $a0-$a3 are statics. */ | |
13959 | opcode |= MIPS16_ALL_STATICS << 16; | |
13960 | else | |
13961 | { | |
13962 | int narg = 0, nstat = 0; | |
13963 | ||
13964 | /* Count arg registers. */ | |
91d6fa6a | 13965 | while (nargs & 0x1) |
0499d65b | 13966 | { |
91d6fa6a | 13967 | nargs >>= 1; |
0499d65b TS |
13968 | narg++; |
13969 | } | |
91d6fa6a | 13970 | if (nargs != 0) |
0499d65b TS |
13971 | as_bad (_("invalid arg register list")); |
13972 | ||
13973 | /* Count static registers. */ | |
13974 | while (statics & 0x8) | |
13975 | { | |
13976 | statics = (statics << 1) & 0xf; | |
13977 | nstat++; | |
13978 | } | |
13979 | if (statics != 0) | |
13980 | as_bad (_("invalid static register list")); | |
13981 | ||
13982 | /* Encode args/statics. */ | |
13983 | opcode |= ((narg << 2) | nstat) << 16; | |
13984 | } | |
13985 | ||
13986 | /* Encode $s0/$s1. */ | |
13987 | if (sregs & (1 << 0)) /* $s0 */ | |
13988 | opcode |= 0x20; | |
13989 | if (sregs & (1 << 1)) /* $s1 */ | |
13990 | opcode |= 0x10; | |
13991 | sregs >>= 2; | |
13992 | ||
13993 | if (sregs != 0) | |
13994 | { | |
13995 | /* Count regs $s2-$s8. */ | |
13996 | int nsreg = 0; | |
13997 | while (sregs & 1) | |
13998 | { | |
13999 | sregs >>= 1; | |
14000 | nsreg++; | |
14001 | } | |
14002 | if (sregs != 0) | |
14003 | as_bad (_("invalid static register list")); | |
14004 | /* Encode $s2-$s8. */ | |
14005 | opcode |= nsreg << 24; | |
14006 | } | |
14007 | ||
14008 | /* Encode frame size. */ | |
14009 | if (!seen_framesz) | |
14010 | as_bad (_("missing frame size")); | |
14011 | else if ((framesz & 7) != 0 || framesz < 0 | |
14012 | || framesz > 0xff * 8) | |
14013 | as_bad (_("invalid frame size")); | |
14014 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14015 | { | |
14016 | framesz /= 8; | |
14017 | opcode |= (((framesz & 0xf0) << 16) | |
14018 | | (framesz & 0x0f)); | |
14019 | } | |
14020 | ||
14021 | /* Finally build the instruction. */ | |
14022 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14023 | opcode |= MIPS16_EXTEND; |
14024 | ip->insn_opcode = opcode; | |
0499d65b TS |
14025 | } |
14026 | continue; | |
14027 | ||
252b5132 RH |
14028 | case 'e': /* extend code */ |
14029 | my_getExpression (&imm_expr, s); | |
14030 | check_absolute_expr (ip, &imm_expr); | |
14031 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14032 | { | |
14033 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14034 | ip->insn_mo->name, | |
14035 | (unsigned long) imm_expr.X_add_number); | |
14036 | imm_expr.X_add_number &= 0x7ff; | |
14037 | } | |
14038 | ip->insn_opcode |= imm_expr.X_add_number; | |
14039 | imm_expr.X_op = O_absent; | |
14040 | s = expr_end; | |
14041 | continue; | |
14042 | ||
14043 | default: | |
14044 | internalError (); | |
14045 | } | |
14046 | break; | |
14047 | } | |
14048 | ||
14049 | /* Args don't match. */ | |
14050 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14051 | strcmp (insn->name, insn[1].name) == 0) | |
14052 | { | |
14053 | ++insn; | |
14054 | s = argsstart; | |
14055 | continue; | |
14056 | } | |
14057 | ||
14058 | insn_error = _("illegal operands"); | |
14059 | ||
14060 | return; | |
14061 | } | |
14062 | } | |
14063 | ||
14064 | /* This structure holds information we know about a mips16 immediate | |
14065 | argument type. */ | |
14066 | ||
e972090a NC |
14067 | struct mips16_immed_operand |
14068 | { | |
252b5132 RH |
14069 | /* The type code used in the argument string in the opcode table. */ |
14070 | int type; | |
14071 | /* The number of bits in the short form of the opcode. */ | |
14072 | int nbits; | |
14073 | /* The number of bits in the extended form of the opcode. */ | |
14074 | int extbits; | |
14075 | /* The amount by which the short form is shifted when it is used; | |
14076 | for example, the sw instruction has a shift count of 2. */ | |
14077 | int shift; | |
14078 | /* The amount by which the short form is shifted when it is stored | |
14079 | into the instruction code. */ | |
14080 | int op_shift; | |
14081 | /* Non-zero if the short form is unsigned. */ | |
14082 | int unsp; | |
14083 | /* Non-zero if the extended form is unsigned. */ | |
14084 | int extu; | |
14085 | /* Non-zero if the value is PC relative. */ | |
14086 | int pcrel; | |
14087 | }; | |
14088 | ||
14089 | /* The mips16 immediate operand types. */ | |
14090 | ||
14091 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14092 | { | |
14093 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14094 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14095 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14096 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14097 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14098 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14099 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14100 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14101 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14102 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14103 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14104 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14105 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14106 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14107 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14108 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14109 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14110 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14111 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14112 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14113 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14114 | }; | |
14115 | ||
14116 | #define MIPS16_NUM_IMMED \ | |
14117 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14118 | ||
b886a2ab RS |
14119 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14120 | NBITS is the number of significant bits in VAL. */ | |
14121 | ||
14122 | static unsigned long | |
14123 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14124 | { | |
14125 | int extval; | |
14126 | if (nbits == 16) | |
14127 | { | |
14128 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14129 | val &= 0x1f; | |
14130 | } | |
14131 | else if (nbits == 15) | |
14132 | { | |
14133 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14134 | val &= 0xf; | |
14135 | } | |
14136 | else | |
14137 | { | |
14138 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14139 | val = 0; | |
14140 | } | |
14141 | return (extval << 16) | val; | |
14142 | } | |
14143 | ||
5c04167a RS |
14144 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14145 | extending it if necessary. The instruction in *INSN may | |
14146 | already be extended. | |
14147 | ||
43c0598f RS |
14148 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14149 | if none. In the former case, VAL is a 16-bit number with no | |
14150 | defined signedness. | |
14151 | ||
14152 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14153 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14154 | |
14155 | static void | |
43c0598f RS |
14156 | mips16_immed (char *file, unsigned int line, int type, |
14157 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14158 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14159 | { |
3994f87e | 14160 | const struct mips16_immed_operand *op; |
252b5132 | 14161 | int mintiny, maxtiny; |
252b5132 RH |
14162 | |
14163 | op = mips16_immed_operands; | |
14164 | while (op->type != type) | |
14165 | { | |
14166 | ++op; | |
9c2799c2 | 14167 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14168 | } |
14169 | ||
14170 | if (op->unsp) | |
14171 | { | |
14172 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14173 | { | |
14174 | mintiny = 1; | |
14175 | maxtiny = 1 << op->nbits; | |
14176 | } | |
14177 | else | |
14178 | { | |
14179 | mintiny = 0; | |
14180 | maxtiny = (1 << op->nbits) - 1; | |
14181 | } | |
43c0598f RS |
14182 | if (reloc != BFD_RELOC_UNUSED) |
14183 | val &= 0xffff; | |
252b5132 RH |
14184 | } |
14185 | else | |
14186 | { | |
14187 | mintiny = - (1 << (op->nbits - 1)); | |
14188 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14189 | if (reloc != BFD_RELOC_UNUSED) |
14190 | val = SEXT_16BIT (val); | |
252b5132 RH |
14191 | } |
14192 | ||
14193 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14194 | if (type == 'p' || type == 'q') | |
14195 | val /= 2; | |
14196 | ||
14197 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14198 | || val < (mintiny << op->shift) | |
14199 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14200 | { |
14201 | /* We need an extended instruction. */ | |
14202 | if (user_insn_length == 2) | |
14203 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14204 | else | |
14205 | *insn |= MIPS16_EXTEND; | |
14206 | } | |
14207 | else if (user_insn_length == 4) | |
14208 | { | |
14209 | /* The operand doesn't force an unextended instruction to be extended. | |
14210 | Warn if the user wanted an extended instruction anyway. */ | |
14211 | *insn |= MIPS16_EXTEND; | |
14212 | as_warn_where (file, line, | |
14213 | _("extended operand requested but not required")); | |
14214 | } | |
252b5132 | 14215 | |
5c04167a | 14216 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14217 | { |
14218 | int insnval; | |
14219 | ||
252b5132 RH |
14220 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14221 | insnval <<= op->op_shift; | |
14222 | *insn |= insnval; | |
14223 | } | |
14224 | else | |
14225 | { | |
14226 | long minext, maxext; | |
252b5132 | 14227 | |
43c0598f | 14228 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14229 | { |
43c0598f RS |
14230 | if (op->extu) |
14231 | { | |
14232 | minext = 0; | |
14233 | maxext = (1 << op->extbits) - 1; | |
14234 | } | |
14235 | else | |
14236 | { | |
14237 | minext = - (1 << (op->extbits - 1)); | |
14238 | maxext = (1 << (op->extbits - 1)) - 1; | |
14239 | } | |
14240 | if (val < minext || val > maxext) | |
14241 | as_bad_where (file, line, | |
14242 | _("operand value out of range for instruction")); | |
252b5132 | 14243 | } |
252b5132 | 14244 | |
b886a2ab | 14245 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14246 | } |
14247 | } | |
14248 | \f | |
d6f16593 | 14249 | struct percent_op_match |
ad8d3bb3 | 14250 | { |
5e0116d5 RS |
14251 | const char *str; |
14252 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14253 | }; |
14254 | ||
14255 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14256 | { |
5e0116d5 | 14257 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14258 | #ifdef OBJ_ELF |
5e0116d5 RS |
14259 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14260 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14261 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14262 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14263 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14264 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14265 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14266 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14267 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14268 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14269 | {"%half", BFD_RELOC_16}, | |
14270 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14271 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14272 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14273 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14274 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14275 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14276 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14277 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14278 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14279 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14280 | #endif |
5e0116d5 | 14281 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14282 | }; |
14283 | ||
d6f16593 MR |
14284 | static const struct percent_op_match mips16_percent_op[] = |
14285 | { | |
14286 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14287 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14288 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14289 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14290 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14291 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14292 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14293 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14294 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14295 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14296 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14297 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14298 | }; |
14299 | ||
252b5132 | 14300 | |
5e0116d5 RS |
14301 | /* Return true if *STR points to a relocation operator. When returning true, |
14302 | move *STR over the operator and store its relocation code in *RELOC. | |
14303 | Leave both *STR and *RELOC alone when returning false. */ | |
14304 | ||
14305 | static bfd_boolean | |
17a2f251 | 14306 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14307 | { |
d6f16593 MR |
14308 | const struct percent_op_match *percent_op; |
14309 | size_t limit, i; | |
14310 | ||
14311 | if (mips_opts.mips16) | |
14312 | { | |
14313 | percent_op = mips16_percent_op; | |
14314 | limit = ARRAY_SIZE (mips16_percent_op); | |
14315 | } | |
14316 | else | |
14317 | { | |
14318 | percent_op = mips_percent_op; | |
14319 | limit = ARRAY_SIZE (mips_percent_op); | |
14320 | } | |
76b3015f | 14321 | |
d6f16593 | 14322 | for (i = 0; i < limit; i++) |
5e0116d5 | 14323 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14324 | { |
3f98094e DJ |
14325 | int len = strlen (percent_op[i].str); |
14326 | ||
14327 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14328 | continue; | |
14329 | ||
5e0116d5 RS |
14330 | *str += strlen (percent_op[i].str); |
14331 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14332 | |
5e0116d5 RS |
14333 | /* Check whether the output BFD supports this relocation. |
14334 | If not, issue an error and fall back on something safe. */ | |
14335 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14336 | { |
20203fb9 | 14337 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14338 | percent_op[i].str); |
01a3f561 | 14339 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14340 | } |
5e0116d5 | 14341 | return TRUE; |
394f9b3a | 14342 | } |
5e0116d5 | 14343 | return FALSE; |
394f9b3a | 14344 | } |
ad8d3bb3 | 14345 | |
ad8d3bb3 | 14346 | |
5e0116d5 RS |
14347 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14348 | expression in *EP and the relocations in the array starting | |
14349 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14350 | |
01a3f561 | 14351 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14352 | |
5e0116d5 | 14353 | static size_t |
17a2f251 TS |
14354 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14355 | char *str) | |
ad8d3bb3 | 14356 | { |
5e0116d5 RS |
14357 | bfd_reloc_code_real_type reversed_reloc[3]; |
14358 | size_t reloc_index, i; | |
09b8f35a RS |
14359 | int crux_depth, str_depth; |
14360 | char *crux; | |
5e0116d5 RS |
14361 | |
14362 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14363 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14364 | of the main expression and with CRUX_DEPTH containing the number | |
14365 | of open brackets at that point. */ | |
14366 | reloc_index = -1; | |
14367 | str_depth = 0; | |
14368 | do | |
fb1b3232 | 14369 | { |
09b8f35a RS |
14370 | reloc_index++; |
14371 | crux = str; | |
14372 | crux_depth = str_depth; | |
14373 | ||
14374 | /* Skip over whitespace and brackets, keeping count of the number | |
14375 | of brackets. */ | |
14376 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14377 | if (*str++ == '(') | |
14378 | str_depth++; | |
5e0116d5 | 14379 | } |
09b8f35a RS |
14380 | while (*str == '%' |
14381 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14382 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14383 | |
09b8f35a | 14384 | my_getExpression (ep, crux); |
5e0116d5 | 14385 | str = expr_end; |
394f9b3a | 14386 | |
5e0116d5 | 14387 | /* Match every open bracket. */ |
09b8f35a | 14388 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14389 | if (*str++ == ')') |
09b8f35a | 14390 | crux_depth--; |
394f9b3a | 14391 | |
09b8f35a | 14392 | if (crux_depth > 0) |
20203fb9 | 14393 | as_bad (_("unclosed '('")); |
394f9b3a | 14394 | |
5e0116d5 | 14395 | expr_end = str; |
252b5132 | 14396 | |
01a3f561 | 14397 | if (reloc_index != 0) |
64bdfcaf RS |
14398 | { |
14399 | prev_reloc_op_frag = frag_now; | |
14400 | for (i = 0; i < reloc_index; i++) | |
14401 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14402 | } | |
fb1b3232 | 14403 | |
5e0116d5 | 14404 | return reloc_index; |
252b5132 RH |
14405 | } |
14406 | ||
14407 | static void | |
17a2f251 | 14408 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14409 | { |
14410 | char *save_in; | |
14411 | ||
14412 | save_in = input_line_pointer; | |
14413 | input_line_pointer = str; | |
14414 | expression (ep); | |
14415 | expr_end = input_line_pointer; | |
14416 | input_line_pointer = save_in; | |
252b5132 RH |
14417 | } |
14418 | ||
252b5132 | 14419 | char * |
17a2f251 | 14420 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14421 | { |
499ac353 | 14422 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14423 | } |
14424 | ||
14425 | void | |
17a2f251 | 14426 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14427 | { |
14428 | if (target_big_endian) | |
14429 | number_to_chars_bigendian (buf, val, n); | |
14430 | else | |
14431 | number_to_chars_littleendian (buf, val, n); | |
14432 | } | |
14433 | \f | |
ae948b86 | 14434 | #ifdef OBJ_ELF |
e013f690 TS |
14435 | static int support_64bit_objects(void) |
14436 | { | |
14437 | const char **list, **l; | |
aa3d8fdf | 14438 | int yes; |
e013f690 TS |
14439 | |
14440 | list = bfd_target_list (); | |
14441 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14442 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14443 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14444 | break; |
aa3d8fdf | 14445 | yes = (*l != NULL); |
e013f690 | 14446 | free (list); |
aa3d8fdf | 14447 | return yes; |
e013f690 | 14448 | } |
ae948b86 | 14449 | #endif /* OBJ_ELF */ |
e013f690 | 14450 | |
78849248 | 14451 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14452 | |
23fce1e3 NC |
14453 | enum options |
14454 | { | |
14455 | OPTION_MARCH = OPTION_MD_BASE, | |
14456 | OPTION_MTUNE, | |
14457 | OPTION_MIPS1, | |
14458 | OPTION_MIPS2, | |
14459 | OPTION_MIPS3, | |
14460 | OPTION_MIPS4, | |
14461 | OPTION_MIPS5, | |
14462 | OPTION_MIPS32, | |
14463 | OPTION_MIPS64, | |
14464 | OPTION_MIPS32R2, | |
14465 | OPTION_MIPS64R2, | |
14466 | OPTION_MIPS16, | |
14467 | OPTION_NO_MIPS16, | |
14468 | OPTION_MIPS3D, | |
14469 | OPTION_NO_MIPS3D, | |
14470 | OPTION_MDMX, | |
14471 | OPTION_NO_MDMX, | |
14472 | OPTION_DSP, | |
14473 | OPTION_NO_DSP, | |
14474 | OPTION_MT, | |
14475 | OPTION_NO_MT, | |
14476 | OPTION_SMARTMIPS, | |
14477 | OPTION_NO_SMARTMIPS, | |
14478 | OPTION_DSPR2, | |
14479 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14480 | OPTION_MICROMIPS, |
14481 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14482 | OPTION_MCU, |
14483 | OPTION_NO_MCU, | |
23fce1e3 NC |
14484 | OPTION_COMPAT_ARCH_BASE, |
14485 | OPTION_M4650, | |
14486 | OPTION_NO_M4650, | |
14487 | OPTION_M4010, | |
14488 | OPTION_NO_M4010, | |
14489 | OPTION_M4100, | |
14490 | OPTION_NO_M4100, | |
14491 | OPTION_M3900, | |
14492 | OPTION_NO_M3900, | |
14493 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14494 | OPTION_MNO_7000_HILO_FIX, |
14495 | OPTION_FIX_24K, | |
14496 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14497 | OPTION_FIX_LOONGSON2F_JUMP, |
14498 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14499 | OPTION_FIX_LOONGSON2F_NOP, | |
14500 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14501 | OPTION_FIX_VR4120, |
14502 | OPTION_NO_FIX_VR4120, | |
14503 | OPTION_FIX_VR4130, | |
14504 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14505 | OPTION_FIX_CN63XXP1, |
14506 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14507 | OPTION_TRAP, |
14508 | OPTION_BREAK, | |
14509 | OPTION_EB, | |
14510 | OPTION_EL, | |
14511 | OPTION_FP32, | |
14512 | OPTION_GP32, | |
14513 | OPTION_CONSTRUCT_FLOATS, | |
14514 | OPTION_NO_CONSTRUCT_FLOATS, | |
14515 | OPTION_FP64, | |
14516 | OPTION_GP64, | |
14517 | OPTION_RELAX_BRANCH, | |
14518 | OPTION_NO_RELAX_BRANCH, | |
14519 | OPTION_MSHARED, | |
14520 | OPTION_MNO_SHARED, | |
14521 | OPTION_MSYM32, | |
14522 | OPTION_MNO_SYM32, | |
14523 | OPTION_SOFT_FLOAT, | |
14524 | OPTION_HARD_FLOAT, | |
14525 | OPTION_SINGLE_FLOAT, | |
14526 | OPTION_DOUBLE_FLOAT, | |
14527 | OPTION_32, | |
14528 | #ifdef OBJ_ELF | |
14529 | OPTION_CALL_SHARED, | |
14530 | OPTION_CALL_NONPIC, | |
14531 | OPTION_NON_SHARED, | |
14532 | OPTION_XGOT, | |
14533 | OPTION_MABI, | |
14534 | OPTION_N32, | |
14535 | OPTION_64, | |
14536 | OPTION_MDEBUG, | |
14537 | OPTION_NO_MDEBUG, | |
14538 | OPTION_PDR, | |
14539 | OPTION_NO_PDR, | |
14540 | OPTION_MVXWORKS_PIC, | |
14541 | #endif /* OBJ_ELF */ | |
14542 | OPTION_END_OF_ENUM | |
14543 | }; | |
14544 | ||
e972090a NC |
14545 | struct option md_longopts[] = |
14546 | { | |
f9b4148d | 14547 | /* Options which specify architecture. */ |
f9b4148d | 14548 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14549 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14550 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14551 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14552 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14553 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14554 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14555 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14556 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14557 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14558 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14559 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14560 | |
14561 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14562 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14563 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14564 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14565 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14566 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14567 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14568 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14569 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14570 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14571 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14572 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14573 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14574 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14575 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14576 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14577 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14578 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14579 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14580 | |
14581 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14582 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14583 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14584 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14585 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14586 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14587 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14588 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14589 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14590 | ||
14591 | /* Options which enable bug fixes. */ | |
f9b4148d | 14592 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14593 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14594 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14595 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14596 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14597 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14598 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14599 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14600 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14601 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14602 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14603 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14604 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14605 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14606 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14607 | |
14608 | /* Miscellaneous options. */ | |
252b5132 RH |
14609 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14610 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14611 | {"break", no_argument, NULL, OPTION_BREAK}, |
14612 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14613 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14614 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14615 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14616 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14617 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14618 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14619 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14620 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14621 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14622 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14623 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14624 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14625 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14626 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14627 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14628 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14629 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14630 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14631 | |
14632 | /* Strictly speaking this next option is ELF specific, | |
14633 | but we allow it for other ports as well in order to | |
14634 | make testing easier. */ | |
14635 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14636 | |
f9b4148d | 14637 | /* ELF-specific options. */ |
156c2f8b | 14638 | #ifdef OBJ_ELF |
156c2f8b NC |
14639 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14640 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14641 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14642 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14643 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14644 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14645 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14646 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14647 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14648 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14649 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14650 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14651 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14652 | #endif /* OBJ_ELF */ |
f9b4148d | 14653 | |
252b5132 RH |
14654 | {NULL, no_argument, NULL, 0} |
14655 | }; | |
156c2f8b | 14656 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14657 | |
316f5878 RS |
14658 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14659 | NEW_VALUE. Warn if another value was already specified. Note: | |
14660 | we have to defer parsing the -march and -mtune arguments in order | |
14661 | to handle 'from-abi' correctly, since the ABI might be specified | |
14662 | in a later argument. */ | |
14663 | ||
14664 | static void | |
17a2f251 | 14665 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14666 | { |
14667 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14668 | as_warn (_("A different %s was already specified, is now %s"), | |
14669 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14670 | new_value); | |
14671 | ||
14672 | *string_ptr = new_value; | |
14673 | } | |
14674 | ||
252b5132 | 14675 | int |
17a2f251 | 14676 | md_parse_option (int c, char *arg) |
252b5132 RH |
14677 | { |
14678 | switch (c) | |
14679 | { | |
119d663a NC |
14680 | case OPTION_CONSTRUCT_FLOATS: |
14681 | mips_disable_float_construction = 0; | |
14682 | break; | |
bdaaa2e1 | 14683 | |
119d663a NC |
14684 | case OPTION_NO_CONSTRUCT_FLOATS: |
14685 | mips_disable_float_construction = 1; | |
14686 | break; | |
bdaaa2e1 | 14687 | |
252b5132 RH |
14688 | case OPTION_TRAP: |
14689 | mips_trap = 1; | |
14690 | break; | |
14691 | ||
14692 | case OPTION_BREAK: | |
14693 | mips_trap = 0; | |
14694 | break; | |
14695 | ||
14696 | case OPTION_EB: | |
14697 | target_big_endian = 1; | |
14698 | break; | |
14699 | ||
14700 | case OPTION_EL: | |
14701 | target_big_endian = 0; | |
14702 | break; | |
14703 | ||
14704 | case 'O': | |
4ffff32f TS |
14705 | if (arg == NULL) |
14706 | mips_optimize = 1; | |
14707 | else if (arg[0] == '0') | |
14708 | mips_optimize = 0; | |
14709 | else if (arg[0] == '1') | |
252b5132 RH |
14710 | mips_optimize = 1; |
14711 | else | |
14712 | mips_optimize = 2; | |
14713 | break; | |
14714 | ||
14715 | case 'g': | |
14716 | if (arg == NULL) | |
14717 | mips_debug = 2; | |
14718 | else | |
14719 | mips_debug = atoi (arg); | |
252b5132 RH |
14720 | break; |
14721 | ||
14722 | case OPTION_MIPS1: | |
316f5878 | 14723 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14724 | break; |
14725 | ||
14726 | case OPTION_MIPS2: | |
316f5878 | 14727 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14728 | break; |
14729 | ||
14730 | case OPTION_MIPS3: | |
316f5878 | 14731 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14732 | break; |
14733 | ||
14734 | case OPTION_MIPS4: | |
316f5878 | 14735 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14736 | break; |
14737 | ||
84ea6cf2 | 14738 | case OPTION_MIPS5: |
316f5878 | 14739 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14740 | break; |
14741 | ||
e7af610e | 14742 | case OPTION_MIPS32: |
316f5878 | 14743 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14744 | break; |
14745 | ||
af7ee8bf CD |
14746 | case OPTION_MIPS32R2: |
14747 | file_mips_isa = ISA_MIPS32R2; | |
14748 | break; | |
14749 | ||
5f74bc13 CD |
14750 | case OPTION_MIPS64R2: |
14751 | file_mips_isa = ISA_MIPS64R2; | |
14752 | break; | |
14753 | ||
84ea6cf2 | 14754 | case OPTION_MIPS64: |
316f5878 | 14755 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14756 | break; |
14757 | ||
ec68c924 | 14758 | case OPTION_MTUNE: |
316f5878 RS |
14759 | mips_set_option_string (&mips_tune_string, arg); |
14760 | break; | |
ec68c924 | 14761 | |
316f5878 RS |
14762 | case OPTION_MARCH: |
14763 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14764 | break; |
14765 | ||
14766 | case OPTION_M4650: | |
316f5878 RS |
14767 | mips_set_option_string (&mips_arch_string, "4650"); |
14768 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14769 | break; |
14770 | ||
14771 | case OPTION_NO_M4650: | |
14772 | break; | |
14773 | ||
14774 | case OPTION_M4010: | |
316f5878 RS |
14775 | mips_set_option_string (&mips_arch_string, "4010"); |
14776 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14777 | break; |
14778 | ||
14779 | case OPTION_NO_M4010: | |
14780 | break; | |
14781 | ||
14782 | case OPTION_M4100: | |
316f5878 RS |
14783 | mips_set_option_string (&mips_arch_string, "4100"); |
14784 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14785 | break; |
14786 | ||
14787 | case OPTION_NO_M4100: | |
14788 | break; | |
14789 | ||
252b5132 | 14790 | case OPTION_M3900: |
316f5878 RS |
14791 | mips_set_option_string (&mips_arch_string, "3900"); |
14792 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14793 | break; |
bdaaa2e1 | 14794 | |
252b5132 RH |
14795 | case OPTION_NO_M3900: |
14796 | break; | |
14797 | ||
deec1734 CD |
14798 | case OPTION_MDMX: |
14799 | mips_opts.ase_mdmx = 1; | |
14800 | break; | |
14801 | ||
14802 | case OPTION_NO_MDMX: | |
14803 | mips_opts.ase_mdmx = 0; | |
14804 | break; | |
14805 | ||
74cd071d CF |
14806 | case OPTION_DSP: |
14807 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14808 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14809 | break; |
14810 | ||
14811 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14812 | mips_opts.ase_dsp = 0; |
14813 | mips_opts.ase_dspr2 = 0; | |
14814 | break; | |
14815 | ||
14816 | case OPTION_DSPR2: | |
14817 | mips_opts.ase_dspr2 = 1; | |
14818 | mips_opts.ase_dsp = 1; | |
14819 | break; | |
14820 | ||
14821 | case OPTION_NO_DSPR2: | |
14822 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14823 | mips_opts.ase_dsp = 0; |
14824 | break; | |
14825 | ||
ef2e4d86 CF |
14826 | case OPTION_MT: |
14827 | mips_opts.ase_mt = 1; | |
14828 | break; | |
14829 | ||
14830 | case OPTION_NO_MT: | |
14831 | mips_opts.ase_mt = 0; | |
14832 | break; | |
14833 | ||
dec0624d MR |
14834 | case OPTION_MCU: |
14835 | mips_opts.ase_mcu = 1; | |
14836 | break; | |
14837 | ||
14838 | case OPTION_NO_MCU: | |
14839 | mips_opts.ase_mcu = 0; | |
14840 | break; | |
14841 | ||
df58fc94 RS |
14842 | case OPTION_MICROMIPS: |
14843 | if (mips_opts.mips16 == 1) | |
14844 | { | |
14845 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14846 | return 0; | |
14847 | } | |
14848 | mips_opts.micromips = 1; | |
14849 | mips_no_prev_insn (); | |
14850 | break; | |
14851 | ||
14852 | case OPTION_NO_MICROMIPS: | |
14853 | mips_opts.micromips = 0; | |
14854 | mips_no_prev_insn (); | |
14855 | break; | |
14856 | ||
252b5132 | 14857 | case OPTION_MIPS16: |
df58fc94 RS |
14858 | if (mips_opts.micromips == 1) |
14859 | { | |
14860 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14861 | return 0; | |
14862 | } | |
252b5132 | 14863 | mips_opts.mips16 = 1; |
7d10b47d | 14864 | mips_no_prev_insn (); |
252b5132 RH |
14865 | break; |
14866 | ||
14867 | case OPTION_NO_MIPS16: | |
14868 | mips_opts.mips16 = 0; | |
7d10b47d | 14869 | mips_no_prev_insn (); |
252b5132 RH |
14870 | break; |
14871 | ||
1f25f5d3 CD |
14872 | case OPTION_MIPS3D: |
14873 | mips_opts.ase_mips3d = 1; | |
14874 | break; | |
14875 | ||
14876 | case OPTION_NO_MIPS3D: | |
14877 | mips_opts.ase_mips3d = 0; | |
14878 | break; | |
14879 | ||
e16bfa71 TS |
14880 | case OPTION_SMARTMIPS: |
14881 | mips_opts.ase_smartmips = 1; | |
14882 | break; | |
14883 | ||
14884 | case OPTION_NO_SMARTMIPS: | |
14885 | mips_opts.ase_smartmips = 0; | |
14886 | break; | |
14887 | ||
6a32d874 CM |
14888 | case OPTION_FIX_24K: |
14889 | mips_fix_24k = 1; | |
14890 | break; | |
14891 | ||
14892 | case OPTION_NO_FIX_24K: | |
14893 | mips_fix_24k = 0; | |
14894 | break; | |
14895 | ||
c67a084a NC |
14896 | case OPTION_FIX_LOONGSON2F_JUMP: |
14897 | mips_fix_loongson2f_jump = TRUE; | |
14898 | break; | |
14899 | ||
14900 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14901 | mips_fix_loongson2f_jump = FALSE; | |
14902 | break; | |
14903 | ||
14904 | case OPTION_FIX_LOONGSON2F_NOP: | |
14905 | mips_fix_loongson2f_nop = TRUE; | |
14906 | break; | |
14907 | ||
14908 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14909 | mips_fix_loongson2f_nop = FALSE; | |
14910 | break; | |
14911 | ||
d766e8ec RS |
14912 | case OPTION_FIX_VR4120: |
14913 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14914 | break; |
14915 | ||
d766e8ec RS |
14916 | case OPTION_NO_FIX_VR4120: |
14917 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14918 | break; |
14919 | ||
7d8e00cf RS |
14920 | case OPTION_FIX_VR4130: |
14921 | mips_fix_vr4130 = 1; | |
14922 | break; | |
14923 | ||
14924 | case OPTION_NO_FIX_VR4130: | |
14925 | mips_fix_vr4130 = 0; | |
14926 | break; | |
14927 | ||
d954098f DD |
14928 | case OPTION_FIX_CN63XXP1: |
14929 | mips_fix_cn63xxp1 = TRUE; | |
14930 | break; | |
14931 | ||
14932 | case OPTION_NO_FIX_CN63XXP1: | |
14933 | mips_fix_cn63xxp1 = FALSE; | |
14934 | break; | |
14935 | ||
4a6a3df4 AO |
14936 | case OPTION_RELAX_BRANCH: |
14937 | mips_relax_branch = 1; | |
14938 | break; | |
14939 | ||
14940 | case OPTION_NO_RELAX_BRANCH: | |
14941 | mips_relax_branch = 0; | |
14942 | break; | |
14943 | ||
aa6975fb ILT |
14944 | case OPTION_MSHARED: |
14945 | mips_in_shared = TRUE; | |
14946 | break; | |
14947 | ||
14948 | case OPTION_MNO_SHARED: | |
14949 | mips_in_shared = FALSE; | |
14950 | break; | |
14951 | ||
aed1a261 RS |
14952 | case OPTION_MSYM32: |
14953 | mips_opts.sym32 = TRUE; | |
14954 | break; | |
14955 | ||
14956 | case OPTION_MNO_SYM32: | |
14957 | mips_opts.sym32 = FALSE; | |
14958 | break; | |
14959 | ||
0f074f60 | 14960 | #ifdef OBJ_ELF |
252b5132 RH |
14961 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14962 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14963 | intended to be compatible with Irix 5. */ | |
14964 | case OPTION_CALL_SHARED: | |
f43abd2b | 14965 | if (!IS_ELF) |
252b5132 RH |
14966 | { |
14967 | as_bad (_("-call_shared is supported only for ELF format")); | |
14968 | return 0; | |
14969 | } | |
14970 | mips_pic = SVR4_PIC; | |
143d77c5 | 14971 | mips_abicalls = TRUE; |
252b5132 RH |
14972 | break; |
14973 | ||
861fb55a DJ |
14974 | case OPTION_CALL_NONPIC: |
14975 | if (!IS_ELF) | |
14976 | { | |
14977 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14978 | return 0; | |
14979 | } | |
14980 | mips_pic = NO_PIC; | |
14981 | mips_abicalls = TRUE; | |
14982 | break; | |
14983 | ||
252b5132 | 14984 | case OPTION_NON_SHARED: |
f43abd2b | 14985 | if (!IS_ELF) |
252b5132 RH |
14986 | { |
14987 | as_bad (_("-non_shared is supported only for ELF format")); | |
14988 | return 0; | |
14989 | } | |
14990 | mips_pic = NO_PIC; | |
143d77c5 | 14991 | mips_abicalls = FALSE; |
252b5132 RH |
14992 | break; |
14993 | ||
44075ae2 TS |
14994 | /* The -xgot option tells the assembler to use 32 bit offsets |
14995 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14996 | compatibility. */ |
14997 | case OPTION_XGOT: | |
14998 | mips_big_got = 1; | |
14999 | break; | |
0f074f60 | 15000 | #endif /* OBJ_ELF */ |
252b5132 RH |
15001 | |
15002 | case 'G': | |
6caf9ef4 TS |
15003 | g_switch_value = atoi (arg); |
15004 | g_switch_seen = 1; | |
252b5132 RH |
15005 | break; |
15006 | ||
34ba82a8 TS |
15007 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15008 | and -mabi=64. */ | |
252b5132 | 15009 | case OPTION_32: |
23fce1e3 NC |
15010 | if (IS_ELF) |
15011 | mips_abi = O32_ABI; | |
15012 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15013 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15014 | break; |
15015 | ||
23fce1e3 | 15016 | #ifdef OBJ_ELF |
e013f690 | 15017 | case OPTION_N32: |
f43abd2b | 15018 | if (!IS_ELF) |
34ba82a8 TS |
15019 | { |
15020 | as_bad (_("-n32 is supported for ELF format only")); | |
15021 | return 0; | |
15022 | } | |
316f5878 | 15023 | mips_abi = N32_ABI; |
e013f690 | 15024 | break; |
252b5132 | 15025 | |
e013f690 | 15026 | case OPTION_64: |
f43abd2b | 15027 | if (!IS_ELF) |
34ba82a8 TS |
15028 | { |
15029 | as_bad (_("-64 is supported for ELF format only")); | |
15030 | return 0; | |
15031 | } | |
316f5878 | 15032 | mips_abi = N64_ABI; |
f43abd2b | 15033 | if (!support_64bit_objects()) |
e013f690 | 15034 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15035 | break; |
ae948b86 | 15036 | #endif /* OBJ_ELF */ |
252b5132 | 15037 | |
c97ef257 | 15038 | case OPTION_GP32: |
a325df1d | 15039 | file_mips_gp32 = 1; |
c97ef257 AH |
15040 | break; |
15041 | ||
15042 | case OPTION_GP64: | |
a325df1d | 15043 | file_mips_gp32 = 0; |
c97ef257 | 15044 | break; |
252b5132 | 15045 | |
ca4e0257 | 15046 | case OPTION_FP32: |
a325df1d | 15047 | file_mips_fp32 = 1; |
316f5878 RS |
15048 | break; |
15049 | ||
15050 | case OPTION_FP64: | |
15051 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15052 | break; |
15053 | ||
037b32b9 AN |
15054 | case OPTION_SINGLE_FLOAT: |
15055 | file_mips_single_float = 1; | |
15056 | break; | |
15057 | ||
15058 | case OPTION_DOUBLE_FLOAT: | |
15059 | file_mips_single_float = 0; | |
15060 | break; | |
15061 | ||
15062 | case OPTION_SOFT_FLOAT: | |
15063 | file_mips_soft_float = 1; | |
15064 | break; | |
15065 | ||
15066 | case OPTION_HARD_FLOAT: | |
15067 | file_mips_soft_float = 0; | |
15068 | break; | |
15069 | ||
ae948b86 | 15070 | #ifdef OBJ_ELF |
252b5132 | 15071 | case OPTION_MABI: |
f43abd2b | 15072 | if (!IS_ELF) |
34ba82a8 TS |
15073 | { |
15074 | as_bad (_("-mabi is supported for ELF format only")); | |
15075 | return 0; | |
15076 | } | |
e013f690 | 15077 | if (strcmp (arg, "32") == 0) |
316f5878 | 15078 | mips_abi = O32_ABI; |
e013f690 | 15079 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15080 | mips_abi = O64_ABI; |
e013f690 | 15081 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15082 | mips_abi = N32_ABI; |
e013f690 TS |
15083 | else if (strcmp (arg, "64") == 0) |
15084 | { | |
316f5878 | 15085 | mips_abi = N64_ABI; |
e013f690 TS |
15086 | if (! support_64bit_objects()) |
15087 | as_fatal (_("No compiled in support for 64 bit object file " | |
15088 | "format")); | |
15089 | } | |
15090 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15091 | mips_abi = EABI_ABI; |
e013f690 | 15092 | else |
da0e507f TS |
15093 | { |
15094 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15095 | return 0; | |
15096 | } | |
252b5132 | 15097 | break; |
e013f690 | 15098 | #endif /* OBJ_ELF */ |
252b5132 | 15099 | |
6b76fefe | 15100 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15101 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15102 | break; |
15103 | ||
9ee72ff1 | 15104 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15105 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15106 | break; |
15107 | ||
ecb4347a DJ |
15108 | #ifdef OBJ_ELF |
15109 | case OPTION_MDEBUG: | |
b34976b6 | 15110 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15111 | break; |
15112 | ||
15113 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15114 | mips_flag_mdebug = FALSE; |
ecb4347a | 15115 | break; |
dcd410fe RO |
15116 | |
15117 | case OPTION_PDR: | |
15118 | mips_flag_pdr = TRUE; | |
15119 | break; | |
15120 | ||
15121 | case OPTION_NO_PDR: | |
15122 | mips_flag_pdr = FALSE; | |
15123 | break; | |
0a44bf69 RS |
15124 | |
15125 | case OPTION_MVXWORKS_PIC: | |
15126 | mips_pic = VXWORKS_PIC; | |
15127 | break; | |
ecb4347a DJ |
15128 | #endif /* OBJ_ELF */ |
15129 | ||
252b5132 RH |
15130 | default: |
15131 | return 0; | |
15132 | } | |
15133 | ||
c67a084a NC |
15134 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15135 | ||
252b5132 RH |
15136 | return 1; |
15137 | } | |
316f5878 RS |
15138 | \f |
15139 | /* Set up globals to generate code for the ISA or processor | |
15140 | described by INFO. */ | |
252b5132 | 15141 | |
252b5132 | 15142 | static void |
17a2f251 | 15143 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15144 | { |
316f5878 | 15145 | if (info != 0) |
252b5132 | 15146 | { |
fef14a42 TS |
15147 | file_mips_arch = info->cpu; |
15148 | mips_opts.arch = info->cpu; | |
316f5878 | 15149 | mips_opts.isa = info->isa; |
252b5132 | 15150 | } |
252b5132 RH |
15151 | } |
15152 | ||
252b5132 | 15153 | |
316f5878 | 15154 | /* Likewise for tuning. */ |
252b5132 | 15155 | |
316f5878 | 15156 | static void |
17a2f251 | 15157 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15158 | { |
15159 | if (info != 0) | |
fef14a42 | 15160 | mips_tune = info->cpu; |
316f5878 | 15161 | } |
80cc45a5 | 15162 | |
34ba82a8 | 15163 | |
252b5132 | 15164 | void |
17a2f251 | 15165 | mips_after_parse_args (void) |
e9670677 | 15166 | { |
fef14a42 TS |
15167 | const struct mips_cpu_info *arch_info = 0; |
15168 | const struct mips_cpu_info *tune_info = 0; | |
15169 | ||
e9670677 | 15170 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15171 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15172 | { |
6caf9ef4 | 15173 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15174 | as_bad (_("-G not supported in this configuration.")); |
15175 | g_switch_value = 0; | |
15176 | } | |
15177 | ||
cac012d6 AO |
15178 | if (mips_abi == NO_ABI) |
15179 | mips_abi = MIPS_DEFAULT_ABI; | |
15180 | ||
22923709 RS |
15181 | /* The following code determines the architecture and register size. |
15182 | Similar code was added to GCC 3.3 (see override_options() in | |
15183 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15184 | as much as possible. */ | |
e9670677 | 15185 | |
316f5878 | 15186 | if (mips_arch_string != 0) |
fef14a42 | 15187 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15188 | |
316f5878 | 15189 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15190 | { |
316f5878 | 15191 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15192 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15193 | the -march selection (if any). */ |
fef14a42 | 15194 | if (arch_info != 0) |
e9670677 | 15195 | { |
316f5878 RS |
15196 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15197 | There's no harm in specifying both as long as the ISA levels | |
15198 | are the same. */ | |
fef14a42 | 15199 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15200 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15201 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15202 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15203 | } |
316f5878 | 15204 | else |
fef14a42 | 15205 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15206 | } |
15207 | ||
fef14a42 | 15208 | if (arch_info == 0) |
95bfe26e MF |
15209 | { |
15210 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15211 | gas_assert (arch_info); | |
15212 | } | |
e9670677 | 15213 | |
fef14a42 | 15214 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15215 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15216 | arch_info->name); |
15217 | ||
15218 | mips_set_architecture (arch_info); | |
15219 | ||
15220 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15221 | if (mips_tune_string != 0) | |
15222 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15223 | |
fef14a42 TS |
15224 | if (tune_info == 0) |
15225 | mips_set_tune (arch_info); | |
15226 | else | |
15227 | mips_set_tune (tune_info); | |
e9670677 | 15228 | |
316f5878 | 15229 | if (file_mips_gp32 >= 0) |
e9670677 | 15230 | { |
316f5878 RS |
15231 | /* The user specified the size of the integer registers. Make sure |
15232 | it agrees with the ABI and ISA. */ | |
15233 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15234 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15235 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15236 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15237 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15238 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15239 | } |
15240 | else | |
15241 | { | |
316f5878 RS |
15242 | /* Infer the integer register size from the ABI and processor. |
15243 | Restrict ourselves to 32-bit registers if that's all the | |
15244 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15245 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15246 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15247 | } |
15248 | ||
ad3fea08 TS |
15249 | switch (file_mips_fp32) |
15250 | { | |
15251 | default: | |
15252 | case -1: | |
15253 | /* No user specified float register size. | |
15254 | ??? GAS treats single-float processors as though they had 64-bit | |
15255 | float registers (although it complains when double-precision | |
15256 | instructions are used). As things stand, saying they have 32-bit | |
15257 | registers would lead to spurious "register must be even" messages. | |
15258 | So here we assume float registers are never smaller than the | |
15259 | integer ones. */ | |
15260 | if (file_mips_gp32 == 0) | |
15261 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15262 | file_mips_fp32 = 0; | |
15263 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15264 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15265 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15266 | file_mips_fp32 = 0; | |
15267 | else | |
15268 | /* 32-bit float registers. */ | |
15269 | file_mips_fp32 = 1; | |
15270 | break; | |
15271 | ||
15272 | /* The user specified the size of the float registers. Check if it | |
15273 | agrees with the ABI and ISA. */ | |
15274 | case 0: | |
15275 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15276 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15277 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15278 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15279 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15280 | break; | |
15281 | case 1: | |
15282 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15283 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15284 | break; | |
15285 | } | |
e9670677 | 15286 | |
316f5878 | 15287 | /* End of GCC-shared inference code. */ |
e9670677 | 15288 | |
17a2f251 TS |
15289 | /* This flag is set when we have a 64-bit capable CPU but use only |
15290 | 32-bit wide registers. Note that EABI does not use it. */ | |
15291 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15292 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15293 | || mips_abi == O32_ABI)) | |
316f5878 | 15294 | mips_32bitmode = 1; |
e9670677 MR |
15295 | |
15296 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15297 | as_bad (_("trap exception not supported at ISA 1")); | |
15298 | ||
e9670677 MR |
15299 | /* If the selected architecture includes support for ASEs, enable |
15300 | generation of code for them. */ | |
a4672219 | 15301 | if (mips_opts.mips16 == -1) |
fef14a42 | 15302 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15303 | if (mips_opts.micromips == -1) |
15304 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15305 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15306 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15307 | && file_mips_fp32 == 0) ? 1 : 0; |
15308 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15309 | as_bad (_("-mfp32 used with -mips3d")); | |
15310 | ||
ffdefa66 | 15311 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15312 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15313 | && file_mips_fp32 == 0) ? 1 : 0; |
15314 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15315 | as_bad (_("-mfp32 used with -mdmx")); | |
15316 | ||
15317 | if (mips_opts.ase_smartmips == -1) | |
15318 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15319 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15320 | as_warn (_("%s ISA does not support SmartMIPS"), |
15321 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15322 | |
74cd071d | 15323 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15324 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15325 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15326 | as_warn (_("%s ISA does not support DSP ASE"), |
15327 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15328 | |
8b082fb1 TS |
15329 | if (mips_opts.ase_dspr2 == -1) |
15330 | { | |
15331 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15332 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15333 | } | |
15334 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15335 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15336 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15337 | |
ef2e4d86 | 15338 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15339 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15340 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15341 | as_warn (_("%s ISA does not support MT ASE"), |
15342 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15343 | |
dec0624d MR |
15344 | if (mips_opts.ase_mcu == -1) |
15345 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15346 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15347 | as_warn (_("%s ISA does not support MCU ASE"), | |
15348 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15349 | ||
e9670677 | 15350 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15351 | file_ase_mips3d = mips_opts.ase_mips3d; |
15352 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15353 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15354 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15355 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15356 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15357 | mips_opts.gp32 = file_mips_gp32; |
15358 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15359 | mips_opts.soft_float = file_mips_soft_float; |
15360 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15361 | |
ecb4347a DJ |
15362 | if (mips_flag_mdebug < 0) |
15363 | { | |
15364 | #ifdef OBJ_MAYBE_ECOFF | |
15365 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15366 | mips_flag_mdebug = 1; | |
15367 | else | |
15368 | #endif /* OBJ_MAYBE_ECOFF */ | |
15369 | mips_flag_mdebug = 0; | |
15370 | } | |
e9670677 MR |
15371 | } |
15372 | \f | |
15373 | void | |
17a2f251 | 15374 | mips_init_after_args (void) |
252b5132 RH |
15375 | { |
15376 | /* initialize opcodes */ | |
15377 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15378 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15379 | } |
15380 | ||
15381 | long | |
17a2f251 | 15382 | md_pcrel_from (fixS *fixP) |
252b5132 | 15383 | { |
a7ebbfdf TS |
15384 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15385 | switch (fixP->fx_r_type) | |
15386 | { | |
df58fc94 RS |
15387 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15388 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15389 | /* Return the address of the delay slot. */ | |
15390 | return addr + 2; | |
15391 | ||
15392 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15393 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15394 | case BFD_RELOC_16_PCREL_S2: |
15395 | case BFD_RELOC_MIPS_JMP: | |
15396 | /* Return the address of the delay slot. */ | |
15397 | return addr + 4; | |
df58fc94 | 15398 | |
a7ebbfdf | 15399 | default: |
58ea3d6a | 15400 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15401 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15402 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15403 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15404 | return addr; |
15405 | } | |
252b5132 RH |
15406 | } |
15407 | ||
252b5132 RH |
15408 | /* This is called before the symbol table is processed. In order to |
15409 | work with gcc when using mips-tfile, we must keep all local labels. | |
15410 | However, in other cases, we want to discard them. If we were | |
15411 | called with -g, but we didn't see any debugging information, it may | |
15412 | mean that gcc is smuggling debugging information through to | |
15413 | mips-tfile, in which case we must generate all local labels. */ | |
15414 | ||
15415 | void | |
17a2f251 | 15416 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15417 | { |
15418 | #ifndef NO_ECOFF_DEBUGGING | |
15419 | if (ECOFF_DEBUGGING | |
15420 | && mips_debug != 0 | |
15421 | && ! ecoff_debugging_seen) | |
15422 | flag_keep_locals = 1; | |
15423 | #endif | |
15424 | } | |
15425 | ||
3b91255e | 15426 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15427 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15428 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15429 | relocation operators. | |
15430 | ||
15431 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15432 | expression if: | |
15433 | ||
15434 | (a) it refers to the same symbol; and | |
15435 | (b) the offset applied in the %lo() expression is no lower than | |
15436 | the offset applied in the %got() or %hi(). | |
15437 | ||
15438 | (b) allows us to cope with code like: | |
15439 | ||
15440 | lui $4,%hi(foo) | |
15441 | lh $4,%lo(foo+2)($4) | |
15442 | ||
15443 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15444 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15445 | the high 16 bits. | |
15446 | ||
15447 | When several %lo()s match a particular %got() or %hi(), we use the | |
15448 | following rules to distinguish them: | |
15449 | ||
15450 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15451 | higher offsets. | |
15452 | ||
15453 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15454 | that already have a matching %got() or %hi(). | |
15455 | ||
15456 | (3) later %lo()s are better than earlier %lo()s. | |
15457 | ||
15458 | These rules are applied in order. | |
15459 | ||
15460 | (1) means, among other things, that %lo()s with identical offsets are | |
15461 | chosen if they exist. | |
15462 | ||
15463 | (2) means that we won't associate several high-part relocations with | |
15464 | the same low-part relocation unless there's no alternative. Having | |
15465 | several high parts for the same low part is a GNU extension; this rule | |
15466 | allows careful users to avoid it. | |
15467 | ||
15468 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15469 | with the last high-part relocation being at the front of the list. | |
15470 | It therefore makes sense to choose the last matching low-part | |
15471 | relocation, all other things being equal. It's also easier | |
15472 | to code that way. */ | |
252b5132 RH |
15473 | |
15474 | void | |
17a2f251 | 15475 | mips_frob_file (void) |
252b5132 RH |
15476 | { |
15477 | struct mips_hi_fixup *l; | |
35903be0 | 15478 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15479 | |
15480 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15481 | { | |
15482 | segment_info_type *seginfo; | |
3b91255e RS |
15483 | bfd_boolean matched_lo_p; |
15484 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15485 | |
9c2799c2 | 15486 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15487 | |
5919d012 | 15488 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15489 | there isn't supposed to be a matching LO. Ignore %gots against |
15490 | constants; we'll report an error for those later. */ | |
738e5348 | 15491 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15492 | && !(l->fixp->fx_addsy |
15493 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15494 | continue; |
15495 | ||
15496 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15497 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15498 | continue; |
15499 | ||
252b5132 | 15500 | seginfo = seg_info (l->seg); |
252b5132 | 15501 | |
3b91255e RS |
15502 | /* Set HI_POS to the position of this relocation in the chain. |
15503 | Set LO_POS to the position of the chosen low-part relocation. | |
15504 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15505 | relocation that matches an immediately-preceding high-part | |
15506 | relocation. */ | |
15507 | hi_pos = NULL; | |
15508 | lo_pos = NULL; | |
15509 | matched_lo_p = FALSE; | |
738e5348 | 15510 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15511 | |
3b91255e RS |
15512 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15513 | { | |
15514 | if (*pos == l->fixp) | |
15515 | hi_pos = pos; | |
15516 | ||
35903be0 | 15517 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15518 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15519 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15520 | && (lo_pos == NULL | |
15521 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15522 | || (!matched_lo_p | |
15523 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15524 | lo_pos = pos; | |
15525 | ||
15526 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15527 | && fixup_has_matching_lo_p (*pos)); | |
15528 | } | |
15529 | ||
15530 | /* If we found a match, remove the high-part relocation from its | |
15531 | current position and insert it before the low-part relocation. | |
15532 | Make the offsets match so that fixup_has_matching_lo_p() | |
15533 | will return true. | |
15534 | ||
15535 | We don't warn about unmatched high-part relocations since some | |
15536 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15537 | instructions. */ | |
15538 | if (lo_pos != NULL) | |
15539 | { | |
15540 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15541 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15542 | { |
3b91255e RS |
15543 | *hi_pos = l->fixp->fx_next; |
15544 | l->fixp->fx_next = *lo_pos; | |
15545 | *lo_pos = l->fixp; | |
252b5132 | 15546 | } |
252b5132 RH |
15547 | } |
15548 | } | |
15549 | } | |
15550 | ||
252b5132 | 15551 | int |
17a2f251 | 15552 | mips_force_relocation (fixS *fixp) |
252b5132 | 15553 | { |
ae6063d4 | 15554 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15555 | return 1; |
15556 | ||
df58fc94 RS |
15557 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15558 | so that the linker relaxation can update targets. */ | |
15559 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15560 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15561 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15562 | return 1; | |
15563 | ||
3e722fb5 | 15564 | return 0; |
252b5132 RH |
15565 | } |
15566 | ||
b886a2ab RS |
15567 | /* Read the instruction associated with RELOC from BUF. */ |
15568 | ||
15569 | static unsigned int | |
15570 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15571 | { | |
15572 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15573 | return read_compressed_insn (buf, 4); | |
15574 | else | |
15575 | return read_insn (buf); | |
15576 | } | |
15577 | ||
15578 | /* Write instruction INSN to BUF, given that it has been relocated | |
15579 | by RELOC. */ | |
15580 | ||
15581 | static void | |
15582 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15583 | unsigned long insn) | |
15584 | { | |
15585 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15586 | write_compressed_insn (buf, insn, 4); | |
15587 | else | |
15588 | write_insn (buf, insn); | |
15589 | } | |
15590 | ||
252b5132 RH |
15591 | /* Apply a fixup to the object file. */ |
15592 | ||
94f592af | 15593 | void |
55cf6793 | 15594 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15595 | { |
4d68580a | 15596 | char *buf; |
b886a2ab | 15597 | unsigned long insn; |
a7ebbfdf | 15598 | reloc_howto_type *howto; |
252b5132 | 15599 | |
a7ebbfdf TS |
15600 | /* We ignore generic BFD relocations we don't know about. */ |
15601 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15602 | if (! howto) | |
15603 | return; | |
65551fa4 | 15604 | |
df58fc94 RS |
15605 | gas_assert (fixP->fx_size == 2 |
15606 | || fixP->fx_size == 4 | |
90ecf173 MR |
15607 | || fixP->fx_r_type == BFD_RELOC_16 |
15608 | || fixP->fx_r_type == BFD_RELOC_64 | |
15609 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15610 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15611 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15612 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15613 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15614 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15615 | |
4d68580a | 15616 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15617 | |
df58fc94 RS |
15618 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15619 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15620 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15621 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15622 | |
15623 | /* Don't treat parts of a composite relocation as done. There are two | |
15624 | reasons for this: | |
15625 | ||
15626 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15627 | should nevertheless be emitted if the first part is. | |
15628 | ||
15629 | (2) In normal usage, composite relocations are never assembly-time | |
15630 | constants. The easiest way of dealing with the pathological | |
15631 | exceptions is to generate a relocation against STN_UNDEF and | |
15632 | leave everything up to the linker. */ | |
3994f87e | 15633 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15634 | fixP->fx_done = 1; |
15635 | ||
15636 | switch (fixP->fx_r_type) | |
15637 | { | |
3f98094e DJ |
15638 | case BFD_RELOC_MIPS_TLS_GD: |
15639 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15640 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15641 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15642 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15643 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15644 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15645 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15646 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15647 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15648 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15649 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15650 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15651 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15652 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15653 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15654 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15655 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15656 | case BFD_RELOC_MIPS16_TLS_GD: |
15657 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15658 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15659 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15660 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15661 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15662 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15663 | if (!fixP->fx_addsy) |
15664 | { | |
15665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15666 | _("TLS relocation against a constant")); | |
15667 | break; | |
15668 | } | |
3f98094e DJ |
15669 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15670 | /* fall through */ | |
15671 | ||
252b5132 | 15672 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15673 | case BFD_RELOC_MIPS_SHIFT5: |
15674 | case BFD_RELOC_MIPS_SHIFT6: | |
15675 | case BFD_RELOC_MIPS_GOT_DISP: | |
15676 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15677 | case BFD_RELOC_MIPS_GOT_OFST: | |
15678 | case BFD_RELOC_MIPS_SUB: | |
15679 | case BFD_RELOC_MIPS_INSERT_A: | |
15680 | case BFD_RELOC_MIPS_INSERT_B: | |
15681 | case BFD_RELOC_MIPS_DELETE: | |
15682 | case BFD_RELOC_MIPS_HIGHEST: | |
15683 | case BFD_RELOC_MIPS_HIGHER: | |
15684 | case BFD_RELOC_MIPS_SCN_DISP: | |
15685 | case BFD_RELOC_MIPS_REL16: | |
15686 | case BFD_RELOC_MIPS_RELGOT: | |
15687 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15688 | case BFD_RELOC_HI16: |
15689 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15690 | case BFD_RELOC_LO16: |
cdf6fd85 | 15691 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15692 | case BFD_RELOC_MIPS_LITERAL: |
15693 | case BFD_RELOC_MIPS_CALL16: | |
15694 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15695 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15696 | case BFD_RELOC_MIPS_GOT_HI16: |
15697 | case BFD_RELOC_MIPS_GOT_LO16: | |
15698 | case BFD_RELOC_MIPS_CALL_HI16: | |
15699 | case BFD_RELOC_MIPS_CALL_LO16: | |
15700 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15701 | case BFD_RELOC_MIPS16_GOT16: |
15702 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15703 | case BFD_RELOC_MIPS16_HI16: |
15704 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15705 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15706 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15707 | case BFD_RELOC_MICROMIPS_JMP: |
15708 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15709 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15710 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15711 | case BFD_RELOC_MICROMIPS_SUB: | |
15712 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15713 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15714 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15715 | case BFD_RELOC_MICROMIPS_JALR: | |
15716 | case BFD_RELOC_MICROMIPS_HI16: | |
15717 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15718 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15719 | case BFD_RELOC_MICROMIPS_GPREL16: |
15720 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15721 | case BFD_RELOC_MICROMIPS_CALL16: | |
15722 | case BFD_RELOC_MICROMIPS_GOT16: | |
15723 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15724 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15725 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15726 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
b886a2ab RS |
15727 | if (fixP->fx_done) |
15728 | { | |
15729 | offsetT value; | |
15730 | ||
15731 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15732 | { | |
15733 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15734 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15735 | insn |= mips16_immed_extend (value, 16); | |
15736 | else | |
15737 | insn |= (value & 0xffff); | |
15738 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15739 | } | |
15740 | else | |
15741 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15742 | _("Unsupported constant in relocation")); | |
15743 | } | |
252b5132 RH |
15744 | break; |
15745 | ||
252b5132 RH |
15746 | case BFD_RELOC_64: |
15747 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15748 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15749 | if (fixP->fx_done) |
252b5132 RH |
15750 | { |
15751 | if (8 <= sizeof (valueT)) | |
4d68580a | 15752 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15753 | else |
15754 | { | |
a7ebbfdf | 15755 | valueT hiv; |
252b5132 | 15756 | |
a7ebbfdf | 15757 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15758 | hiv = 0xffffffff; |
15759 | else | |
15760 | hiv = 0; | |
4d68580a RS |
15761 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15762 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15763 | } |
15764 | } | |
15765 | break; | |
15766 | ||
056350c6 | 15767 | case BFD_RELOC_RVA: |
252b5132 | 15768 | case BFD_RELOC_32: |
252b5132 RH |
15769 | case BFD_RELOC_16: |
15770 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15771 | value now. This can happen if we have a .word which is not |
15772 | resolved when it appears but is later defined. */ | |
252b5132 | 15773 | if (fixP->fx_done) |
4d68580a | 15774 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15775 | break; |
15776 | ||
252b5132 | 15777 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15778 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15779 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15780 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15781 | |
54f4ddb3 TS |
15782 | /* We need to save the bits in the instruction since fixup_segment() |
15783 | might be deleting the relocation entry (i.e., a branch within | |
15784 | the current segment). */ | |
a7ebbfdf | 15785 | if (! fixP->fx_done) |
bb2d6cd7 | 15786 | break; |
252b5132 | 15787 | |
54f4ddb3 | 15788 | /* Update old instruction data. */ |
4d68580a | 15789 | insn = read_insn (buf); |
252b5132 | 15790 | |
a7ebbfdf TS |
15791 | if (*valP + 0x20000 <= 0x3ffff) |
15792 | { | |
15793 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15794 | write_insn (buf, insn); |
a7ebbfdf TS |
15795 | } |
15796 | else if (mips_pic == NO_PIC | |
15797 | && fixP->fx_done | |
15798 | && fixP->fx_frag->fr_address >= text_section->vma | |
15799 | && (fixP->fx_frag->fr_address | |
587aac4e | 15800 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15801 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15802 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15803 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15804 | { |
15805 | /* The branch offset is too large. If this is an | |
15806 | unconditional branch, and we are not generating PIC code, | |
15807 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15808 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15809 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15810 | else |
a7ebbfdf TS |
15811 | insn = 0x08000000; /* j */ |
15812 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15813 | fixP->fx_done = 0; | |
15814 | fixP->fx_addsy = section_symbol (text_section); | |
15815 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15816 | write_insn (buf, insn); |
a7ebbfdf TS |
15817 | } |
15818 | else | |
15819 | { | |
15820 | /* If we got here, we have branch-relaxation disabled, | |
15821 | and there's nothing we can do to fix this instruction | |
15822 | without turning it into a longer sequence. */ | |
15823 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15824 | _("Branch out of range")); | |
252b5132 | 15825 | } |
252b5132 RH |
15826 | break; |
15827 | ||
df58fc94 RS |
15828 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15829 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15830 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15831 | /* We adjust the offset back to even. */ | |
15832 | if ((*valP & 0x1) != 0) | |
15833 | --(*valP); | |
15834 | ||
15835 | if (! fixP->fx_done) | |
15836 | break; | |
15837 | ||
15838 | /* Should never visit here, because we keep the relocation. */ | |
15839 | abort (); | |
15840 | break; | |
15841 | ||
252b5132 RH |
15842 | case BFD_RELOC_VTABLE_INHERIT: |
15843 | fixP->fx_done = 0; | |
15844 | if (fixP->fx_addsy | |
15845 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15846 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15847 | S_SET_WEAK (fixP->fx_addsy); | |
15848 | break; | |
15849 | ||
15850 | case BFD_RELOC_VTABLE_ENTRY: | |
15851 | fixP->fx_done = 0; | |
15852 | break; | |
15853 | ||
15854 | default: | |
15855 | internalError (); | |
15856 | } | |
a7ebbfdf TS |
15857 | |
15858 | /* Remember value for tc_gen_reloc. */ | |
15859 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15860 | } |
15861 | ||
252b5132 | 15862 | static symbolS * |
17a2f251 | 15863 | get_symbol (void) |
252b5132 RH |
15864 | { |
15865 | int c; | |
15866 | char *name; | |
15867 | symbolS *p; | |
15868 | ||
15869 | name = input_line_pointer; | |
15870 | c = get_symbol_end (); | |
15871 | p = (symbolS *) symbol_find_or_make (name); | |
15872 | *input_line_pointer = c; | |
15873 | return p; | |
15874 | } | |
15875 | ||
742a56fe RS |
15876 | /* Align the current frag to a given power of two. If a particular |
15877 | fill byte should be used, FILL points to an integer that contains | |
15878 | that byte, otherwise FILL is null. | |
15879 | ||
462427c4 RS |
15880 | This function used to have the comment: |
15881 | ||
15882 | The MIPS assembler also automatically adjusts any preceding label. | |
15883 | ||
15884 | The implementation therefore applied the adjustment to a maximum of | |
15885 | one label. However, other label adjustments are applied to batches | |
15886 | of labels, and adjusting just one caused problems when new labels | |
15887 | were added for the sake of debugging or unwind information. | |
15888 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15889 | |
15890 | static void | |
462427c4 | 15891 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15892 | { |
7d10b47d | 15893 | mips_emit_delays (); |
df58fc94 | 15894 | mips_record_compressed_mode (); |
742a56fe RS |
15895 | if (fill == NULL && subseg_text_p (now_seg)) |
15896 | frag_align_code (to, 0); | |
15897 | else | |
15898 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15899 | record_alignment (now_seg, to); |
462427c4 | 15900 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15901 | } |
15902 | ||
15903 | /* Align to a given power of two. .align 0 turns off the automatic | |
15904 | alignment used by the data creating pseudo-ops. */ | |
15905 | ||
15906 | static void | |
17a2f251 | 15907 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15908 | { |
742a56fe | 15909 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15910 | long max_alignment = 28; |
252b5132 | 15911 | |
54f4ddb3 | 15912 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15913 | to the aligned address. |
54f4ddb3 | 15914 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15915 | a .align pseudo instruction. |
54f4ddb3 | 15916 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15917 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15918 | We don't. */ |
252b5132 RH |
15919 | |
15920 | temp = get_absolute_expression (); | |
15921 | if (temp > max_alignment) | |
15922 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15923 | else if (temp < 0) | |
15924 | { | |
15925 | as_warn (_("Alignment negative: 0 assumed.")); | |
15926 | temp = 0; | |
15927 | } | |
15928 | if (*input_line_pointer == ',') | |
15929 | { | |
f9419b05 | 15930 | ++input_line_pointer; |
742a56fe RS |
15931 | fill_value = get_absolute_expression (); |
15932 | fill_ptr = &fill_value; | |
252b5132 RH |
15933 | } |
15934 | else | |
742a56fe | 15935 | fill_ptr = 0; |
252b5132 RH |
15936 | if (temp) |
15937 | { | |
a8dbcb85 TS |
15938 | segment_info_type *si = seg_info (now_seg); |
15939 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15940 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15941 | auto_align = 1; |
462427c4 | 15942 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15943 | } |
15944 | else | |
15945 | { | |
15946 | auto_align = 0; | |
15947 | } | |
15948 | ||
15949 | demand_empty_rest_of_line (); | |
15950 | } | |
15951 | ||
252b5132 | 15952 | static void |
17a2f251 | 15953 | s_change_sec (int sec) |
252b5132 RH |
15954 | { |
15955 | segT seg; | |
15956 | ||
252b5132 RH |
15957 | #ifdef OBJ_ELF |
15958 | /* The ELF backend needs to know that we are changing sections, so | |
15959 | that .previous works correctly. We could do something like check | |
b6ff326e | 15960 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15961 | as it would not be appropriate to use it in the section changing |
15962 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15963 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15964 | if (IS_ELF) |
15965 | obj_elf_section_change_hook (); | |
252b5132 RH |
15966 | #endif |
15967 | ||
7d10b47d | 15968 | mips_emit_delays (); |
6a32d874 | 15969 | |
252b5132 RH |
15970 | switch (sec) |
15971 | { | |
15972 | case 't': | |
15973 | s_text (0); | |
15974 | break; | |
15975 | case 'd': | |
15976 | s_data (0); | |
15977 | break; | |
15978 | case 'b': | |
15979 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15980 | demand_empty_rest_of_line (); | |
15981 | break; | |
15982 | ||
15983 | case 'r': | |
4d0d148d TS |
15984 | seg = subseg_new (RDATA_SECTION_NAME, |
15985 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15986 | if (IS_ELF) |
252b5132 | 15987 | { |
4d0d148d TS |
15988 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15989 | | SEC_READONLY | SEC_RELOC | |
15990 | | SEC_DATA)); | |
c41e87e3 | 15991 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15992 | record_alignment (seg, 4); |
252b5132 | 15993 | } |
4d0d148d | 15994 | demand_empty_rest_of_line (); |
252b5132 RH |
15995 | break; |
15996 | ||
15997 | case 's': | |
4d0d148d | 15998 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15999 | if (IS_ELF) |
252b5132 | 16000 | { |
4d0d148d TS |
16001 | bfd_set_section_flags (stdoutput, seg, |
16002 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16003 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16004 | record_alignment (seg, 4); |
252b5132 | 16005 | } |
4d0d148d TS |
16006 | demand_empty_rest_of_line (); |
16007 | break; | |
998b3c36 MR |
16008 | |
16009 | case 'B': | |
16010 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16011 | if (IS_ELF) | |
16012 | { | |
16013 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16014 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16015 | record_alignment (seg, 4); | |
16016 | } | |
16017 | demand_empty_rest_of_line (); | |
16018 | break; | |
252b5132 RH |
16019 | } |
16020 | ||
16021 | auto_align = 1; | |
16022 | } | |
b34976b6 | 16023 | |
cca86cc8 | 16024 | void |
17a2f251 | 16025 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16026 | { |
7ed4a06a | 16027 | #ifdef OBJ_ELF |
cca86cc8 SC |
16028 | char *section_name; |
16029 | char c; | |
684022ea | 16030 | char next_c = 0; |
cca86cc8 SC |
16031 | int section_type; |
16032 | int section_flag; | |
16033 | int section_entry_size; | |
16034 | int section_alignment; | |
b34976b6 | 16035 | |
f43abd2b | 16036 | if (!IS_ELF) |
7ed4a06a TS |
16037 | return; |
16038 | ||
cca86cc8 SC |
16039 | section_name = input_line_pointer; |
16040 | c = get_symbol_end (); | |
a816d1ed AO |
16041 | if (c) |
16042 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16043 | |
4cf0dd0d TS |
16044 | /* Do we have .section Name<,"flags">? */ |
16045 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16046 | { |
4cf0dd0d TS |
16047 | /* just after name is now '\0'. */ |
16048 | *input_line_pointer = c; | |
cca86cc8 SC |
16049 | input_line_pointer = section_name; |
16050 | obj_elf_section (ignore); | |
16051 | return; | |
16052 | } | |
16053 | input_line_pointer++; | |
16054 | ||
16055 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16056 | if (c == ',') | |
16057 | section_type = get_absolute_expression (); | |
16058 | else | |
16059 | section_type = 0; | |
16060 | if (*input_line_pointer++ == ',') | |
16061 | section_flag = get_absolute_expression (); | |
16062 | else | |
16063 | section_flag = 0; | |
16064 | if (*input_line_pointer++ == ',') | |
16065 | section_entry_size = get_absolute_expression (); | |
16066 | else | |
16067 | section_entry_size = 0; | |
16068 | if (*input_line_pointer++ == ',') | |
16069 | section_alignment = get_absolute_expression (); | |
16070 | else | |
16071 | section_alignment = 0; | |
87975d2a AM |
16072 | /* FIXME: really ignore? */ |
16073 | (void) section_alignment; | |
cca86cc8 | 16074 | |
a816d1ed AO |
16075 | section_name = xstrdup (section_name); |
16076 | ||
8ab8a5c8 RS |
16077 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16078 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16079 | traditionally had to fall back on the more common @progbits instead. | |
16080 | ||
16081 | There's nothing really harmful in this, since bfd will correct | |
16082 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16083 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16084 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16085 | ||
16086 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16087 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16088 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16089 | generic type-checking code. */ | |
16090 | if (section_type == SHT_MIPS_DWARF) | |
16091 | section_type = SHT_PROGBITS; | |
16092 | ||
cca86cc8 SC |
16093 | obj_elf_change_section (section_name, section_type, section_flag, |
16094 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16095 | |
16096 | if (now_seg->name != section_name) | |
16097 | free (section_name); | |
7ed4a06a | 16098 | #endif /* OBJ_ELF */ |
cca86cc8 | 16099 | } |
252b5132 RH |
16100 | |
16101 | void | |
17a2f251 | 16102 | mips_enable_auto_align (void) |
252b5132 RH |
16103 | { |
16104 | auto_align = 1; | |
16105 | } | |
16106 | ||
16107 | static void | |
17a2f251 | 16108 | s_cons (int log_size) |
252b5132 | 16109 | { |
a8dbcb85 TS |
16110 | segment_info_type *si = seg_info (now_seg); |
16111 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16112 | |
7d10b47d | 16113 | mips_emit_delays (); |
252b5132 | 16114 | if (log_size > 0 && auto_align) |
462427c4 | 16115 | mips_align (log_size, 0, l); |
252b5132 | 16116 | cons (1 << log_size); |
a1facbec | 16117 | mips_clear_insn_labels (); |
252b5132 RH |
16118 | } |
16119 | ||
16120 | static void | |
17a2f251 | 16121 | s_float_cons (int type) |
252b5132 | 16122 | { |
a8dbcb85 TS |
16123 | segment_info_type *si = seg_info (now_seg); |
16124 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16125 | |
7d10b47d | 16126 | mips_emit_delays (); |
252b5132 RH |
16127 | |
16128 | if (auto_align) | |
49309057 ILT |
16129 | { |
16130 | if (type == 'd') | |
462427c4 | 16131 | mips_align (3, 0, l); |
49309057 | 16132 | else |
462427c4 | 16133 | mips_align (2, 0, l); |
49309057 | 16134 | } |
252b5132 | 16135 | |
252b5132 | 16136 | float_cons (type); |
a1facbec | 16137 | mips_clear_insn_labels (); |
252b5132 RH |
16138 | } |
16139 | ||
16140 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16141 | permitted to say | |
16142 | .globl foo .text | |
16143 | where foo is an undefined symbol, to mean that foo should be | |
16144 | considered to be the address of a function. */ | |
16145 | ||
16146 | static void | |
17a2f251 | 16147 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16148 | { |
16149 | char *name; | |
16150 | int c; | |
16151 | symbolS *symbolP; | |
16152 | flagword flag; | |
16153 | ||
8a06b769 | 16154 | do |
252b5132 | 16155 | { |
8a06b769 | 16156 | name = input_line_pointer; |
252b5132 | 16157 | c = get_symbol_end (); |
8a06b769 TS |
16158 | symbolP = symbol_find_or_make (name); |
16159 | S_SET_EXTERNAL (symbolP); | |
16160 | ||
252b5132 | 16161 | *input_line_pointer = c; |
8a06b769 | 16162 | SKIP_WHITESPACE (); |
252b5132 | 16163 | |
8a06b769 TS |
16164 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16165 | being a function is apparently labelled as being an object. */ | |
16166 | flag = BSF_OBJECT; | |
252b5132 | 16167 | |
8a06b769 TS |
16168 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16169 | && (*input_line_pointer != ',')) | |
16170 | { | |
16171 | char *secname; | |
16172 | asection *sec; | |
16173 | ||
16174 | secname = input_line_pointer; | |
16175 | c = get_symbol_end (); | |
16176 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16177 | if (sec == NULL) | |
16178 | as_bad (_("%s: no such section"), secname); | |
16179 | *input_line_pointer = c; | |
16180 | ||
16181 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16182 | flag = BSF_FUNCTION; | |
16183 | } | |
16184 | ||
16185 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16186 | ||
16187 | c = *input_line_pointer; | |
16188 | if (c == ',') | |
16189 | { | |
16190 | input_line_pointer++; | |
16191 | SKIP_WHITESPACE (); | |
16192 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16193 | c = '\n'; | |
16194 | } | |
16195 | } | |
16196 | while (c == ','); | |
252b5132 | 16197 | |
252b5132 RH |
16198 | demand_empty_rest_of_line (); |
16199 | } | |
16200 | ||
16201 | static void | |
17a2f251 | 16202 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16203 | { |
16204 | char *opt; | |
16205 | char c; | |
16206 | ||
16207 | opt = input_line_pointer; | |
16208 | c = get_symbol_end (); | |
16209 | ||
16210 | if (*opt == 'O') | |
16211 | { | |
16212 | /* FIXME: What does this mean? */ | |
16213 | } | |
16214 | else if (strncmp (opt, "pic", 3) == 0) | |
16215 | { | |
16216 | int i; | |
16217 | ||
16218 | i = atoi (opt + 3); | |
16219 | if (i == 0) | |
16220 | mips_pic = NO_PIC; | |
16221 | else if (i == 2) | |
143d77c5 | 16222 | { |
8b828383 | 16223 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16224 | mips_abicalls = TRUE; |
16225 | } | |
252b5132 RH |
16226 | else |
16227 | as_bad (_(".option pic%d not supported"), i); | |
16228 | ||
4d0d148d | 16229 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16230 | { |
16231 | if (g_switch_seen && g_switch_value != 0) | |
16232 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16233 | g_switch_value = 0; | |
16234 | bfd_set_gp_size (stdoutput, 0); | |
16235 | } | |
16236 | } | |
16237 | else | |
16238 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16239 | ||
16240 | *input_line_pointer = c; | |
16241 | demand_empty_rest_of_line (); | |
16242 | } | |
16243 | ||
16244 | /* This structure is used to hold a stack of .set values. */ | |
16245 | ||
e972090a NC |
16246 | struct mips_option_stack |
16247 | { | |
252b5132 RH |
16248 | struct mips_option_stack *next; |
16249 | struct mips_set_options options; | |
16250 | }; | |
16251 | ||
16252 | static struct mips_option_stack *mips_opts_stack; | |
16253 | ||
16254 | /* Handle the .set pseudo-op. */ | |
16255 | ||
16256 | static void | |
17a2f251 | 16257 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16258 | { |
16259 | char *name = input_line_pointer, ch; | |
16260 | ||
16261 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16262 | ++input_line_pointer; |
252b5132 RH |
16263 | ch = *input_line_pointer; |
16264 | *input_line_pointer = '\0'; | |
16265 | ||
16266 | if (strcmp (name, "reorder") == 0) | |
16267 | { | |
7d10b47d RS |
16268 | if (mips_opts.noreorder) |
16269 | end_noreorder (); | |
252b5132 RH |
16270 | } |
16271 | else if (strcmp (name, "noreorder") == 0) | |
16272 | { | |
7d10b47d RS |
16273 | if (!mips_opts.noreorder) |
16274 | start_noreorder (); | |
252b5132 | 16275 | } |
741fe287 MR |
16276 | else if (strncmp (name, "at=", 3) == 0) |
16277 | { | |
16278 | char *s = name + 3; | |
16279 | ||
16280 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16281 | as_bad (_("Unrecognized register name `%s'"), s); | |
16282 | } | |
252b5132 RH |
16283 | else if (strcmp (name, "at") == 0) |
16284 | { | |
741fe287 | 16285 | mips_opts.at = ATREG; |
252b5132 RH |
16286 | } |
16287 | else if (strcmp (name, "noat") == 0) | |
16288 | { | |
741fe287 | 16289 | mips_opts.at = ZERO; |
252b5132 RH |
16290 | } |
16291 | else if (strcmp (name, "macro") == 0) | |
16292 | { | |
16293 | mips_opts.warn_about_macros = 0; | |
16294 | } | |
16295 | else if (strcmp (name, "nomacro") == 0) | |
16296 | { | |
16297 | if (mips_opts.noreorder == 0) | |
16298 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16299 | mips_opts.warn_about_macros = 1; | |
16300 | } | |
16301 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16302 | { | |
16303 | mips_opts.nomove = 0; | |
16304 | } | |
16305 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16306 | { | |
16307 | mips_opts.nomove = 1; | |
16308 | } | |
16309 | else if (strcmp (name, "bopt") == 0) | |
16310 | { | |
16311 | mips_opts.nobopt = 0; | |
16312 | } | |
16313 | else if (strcmp (name, "nobopt") == 0) | |
16314 | { | |
16315 | mips_opts.nobopt = 1; | |
16316 | } | |
ad3fea08 TS |
16317 | else if (strcmp (name, "gp=default") == 0) |
16318 | mips_opts.gp32 = file_mips_gp32; | |
16319 | else if (strcmp (name, "gp=32") == 0) | |
16320 | mips_opts.gp32 = 1; | |
16321 | else if (strcmp (name, "gp=64") == 0) | |
16322 | { | |
16323 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16324 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16325 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16326 | mips_opts.gp32 = 0; | |
16327 | } | |
16328 | else if (strcmp (name, "fp=default") == 0) | |
16329 | mips_opts.fp32 = file_mips_fp32; | |
16330 | else if (strcmp (name, "fp=32") == 0) | |
16331 | mips_opts.fp32 = 1; | |
16332 | else if (strcmp (name, "fp=64") == 0) | |
16333 | { | |
16334 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16335 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16336 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16337 | mips_opts.fp32 = 0; | |
16338 | } | |
037b32b9 AN |
16339 | else if (strcmp (name, "softfloat") == 0) |
16340 | mips_opts.soft_float = 1; | |
16341 | else if (strcmp (name, "hardfloat") == 0) | |
16342 | mips_opts.soft_float = 0; | |
16343 | else if (strcmp (name, "singlefloat") == 0) | |
16344 | mips_opts.single_float = 1; | |
16345 | else if (strcmp (name, "doublefloat") == 0) | |
16346 | mips_opts.single_float = 0; | |
252b5132 RH |
16347 | else if (strcmp (name, "mips16") == 0 |
16348 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16349 | { |
16350 | if (mips_opts.micromips == 1) | |
16351 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16352 | mips_opts.mips16 = 1; | |
16353 | } | |
252b5132 RH |
16354 | else if (strcmp (name, "nomips16") == 0 |
16355 | || strcmp (name, "noMIPS-16") == 0) | |
16356 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16357 | else if (strcmp (name, "micromips") == 0) |
16358 | { | |
16359 | if (mips_opts.mips16 == 1) | |
16360 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16361 | mips_opts.micromips = 1; | |
16362 | } | |
16363 | else if (strcmp (name, "nomicromips") == 0) | |
16364 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16365 | else if (strcmp (name, "smartmips") == 0) |
16366 | { | |
ad3fea08 | 16367 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16368 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16369 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16370 | mips_opts.ase_smartmips = 1; | |
16371 | } | |
16372 | else if (strcmp (name, "nosmartmips") == 0) | |
16373 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16374 | else if (strcmp (name, "mips3d") == 0) |
16375 | mips_opts.ase_mips3d = 1; | |
16376 | else if (strcmp (name, "nomips3d") == 0) | |
16377 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16378 | else if (strcmp (name, "mdmx") == 0) |
16379 | mips_opts.ase_mdmx = 1; | |
16380 | else if (strcmp (name, "nomdmx") == 0) | |
16381 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16382 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16383 | { |
16384 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16385 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16386 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16387 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16388 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16389 | } |
74cd071d | 16390 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16391 | { |
16392 | mips_opts.ase_dsp = 0; | |
16393 | mips_opts.ase_dspr2 = 0; | |
16394 | } | |
16395 | else if (strcmp (name, "dspr2") == 0) | |
16396 | { | |
16397 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16398 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16399 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16400 | mips_opts.ase_dspr2 = 1; | |
16401 | mips_opts.ase_dsp = 1; | |
16402 | } | |
16403 | else if (strcmp (name, "nodspr2") == 0) | |
16404 | { | |
16405 | mips_opts.ase_dspr2 = 0; | |
16406 | mips_opts.ase_dsp = 0; | |
16407 | } | |
ef2e4d86 | 16408 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16409 | { |
16410 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16411 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16412 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16413 | mips_opts.ase_mt = 1; | |
16414 | } | |
ef2e4d86 CF |
16415 | else if (strcmp (name, "nomt") == 0) |
16416 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16417 | else if (strcmp (name, "mcu") == 0) |
16418 | mips_opts.ase_mcu = 1; | |
16419 | else if (strcmp (name, "nomcu") == 0) | |
16420 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16421 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16422 | { |
af7ee8bf | 16423 | int reset = 0; |
252b5132 | 16424 | |
1a2c1fad CD |
16425 | /* Permit the user to change the ISA and architecture on the fly. |
16426 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16427 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16428 | { |
16429 | reset = 1; | |
16430 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16431 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16432 | } |
16433 | else if (strncmp (name, "arch=", 5) == 0) | |
16434 | { | |
16435 | const struct mips_cpu_info *p; | |
16436 | ||
16437 | p = mips_parse_cpu("internal use", name + 5); | |
16438 | if (!p) | |
16439 | as_bad (_("unknown architecture %s"), name + 5); | |
16440 | else | |
16441 | { | |
16442 | mips_opts.arch = p->cpu; | |
16443 | mips_opts.isa = p->isa; | |
16444 | } | |
16445 | } | |
81a21e38 TS |
16446 | else if (strncmp (name, "mips", 4) == 0) |
16447 | { | |
16448 | const struct mips_cpu_info *p; | |
16449 | ||
16450 | p = mips_parse_cpu("internal use", name); | |
16451 | if (!p) | |
16452 | as_bad (_("unknown ISA level %s"), name + 4); | |
16453 | else | |
16454 | { | |
16455 | mips_opts.arch = p->cpu; | |
16456 | mips_opts.isa = p->isa; | |
16457 | } | |
16458 | } | |
af7ee8bf | 16459 | else |
81a21e38 | 16460 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16461 | |
16462 | switch (mips_opts.isa) | |
98d3f06f KH |
16463 | { |
16464 | case 0: | |
98d3f06f | 16465 | break; |
af7ee8bf CD |
16466 | case ISA_MIPS1: |
16467 | case ISA_MIPS2: | |
16468 | case ISA_MIPS32: | |
16469 | case ISA_MIPS32R2: | |
98d3f06f KH |
16470 | mips_opts.gp32 = 1; |
16471 | mips_opts.fp32 = 1; | |
16472 | break; | |
af7ee8bf CD |
16473 | case ISA_MIPS3: |
16474 | case ISA_MIPS4: | |
16475 | case ISA_MIPS5: | |
16476 | case ISA_MIPS64: | |
5f74bc13 | 16477 | case ISA_MIPS64R2: |
98d3f06f | 16478 | mips_opts.gp32 = 0; |
e407c74b NC |
16479 | if (mips_opts.arch == CPU_R5900) |
16480 | { | |
16481 | mips_opts.fp32 = 1; | |
16482 | } | |
16483 | else | |
16484 | { | |
98d3f06f | 16485 | mips_opts.fp32 = 0; |
e407c74b | 16486 | } |
98d3f06f KH |
16487 | break; |
16488 | default: | |
16489 | as_bad (_("unknown ISA level %s"), name + 4); | |
16490 | break; | |
16491 | } | |
af7ee8bf | 16492 | if (reset) |
98d3f06f | 16493 | { |
af7ee8bf CD |
16494 | mips_opts.gp32 = file_mips_gp32; |
16495 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16496 | } |
252b5132 RH |
16497 | } |
16498 | else if (strcmp (name, "autoextend") == 0) | |
16499 | mips_opts.noautoextend = 0; | |
16500 | else if (strcmp (name, "noautoextend") == 0) | |
16501 | mips_opts.noautoextend = 1; | |
16502 | else if (strcmp (name, "push") == 0) | |
16503 | { | |
16504 | struct mips_option_stack *s; | |
16505 | ||
16506 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16507 | s->next = mips_opts_stack; | |
16508 | s->options = mips_opts; | |
16509 | mips_opts_stack = s; | |
16510 | } | |
16511 | else if (strcmp (name, "pop") == 0) | |
16512 | { | |
16513 | struct mips_option_stack *s; | |
16514 | ||
16515 | s = mips_opts_stack; | |
16516 | if (s == NULL) | |
16517 | as_bad (_(".set pop with no .set push")); | |
16518 | else | |
16519 | { | |
16520 | /* If we're changing the reorder mode we need to handle | |
16521 | delay slots correctly. */ | |
16522 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16523 | start_noreorder (); |
252b5132 | 16524 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16525 | end_noreorder (); |
252b5132 RH |
16526 | |
16527 | mips_opts = s->options; | |
16528 | mips_opts_stack = s->next; | |
16529 | free (s); | |
16530 | } | |
16531 | } | |
aed1a261 RS |
16532 | else if (strcmp (name, "sym32") == 0) |
16533 | mips_opts.sym32 = TRUE; | |
16534 | else if (strcmp (name, "nosym32") == 0) | |
16535 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16536 | else if (strchr (name, ',')) |
16537 | { | |
16538 | /* Generic ".set" directive; use the generic handler. */ | |
16539 | *input_line_pointer = ch; | |
16540 | input_line_pointer = name; | |
16541 | s_set (0); | |
16542 | return; | |
16543 | } | |
252b5132 RH |
16544 | else |
16545 | { | |
16546 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16547 | } | |
16548 | *input_line_pointer = ch; | |
16549 | demand_empty_rest_of_line (); | |
16550 | } | |
16551 | ||
16552 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16553 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16554 | ||
16555 | static void | |
17a2f251 | 16556 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16557 | { |
16558 | mips_pic = SVR4_PIC; | |
143d77c5 | 16559 | mips_abicalls = TRUE; |
4d0d148d TS |
16560 | |
16561 | if (g_switch_seen && g_switch_value != 0) | |
16562 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16563 | g_switch_value = 0; | |
16564 | ||
252b5132 RH |
16565 | bfd_set_gp_size (stdoutput, 0); |
16566 | demand_empty_rest_of_line (); | |
16567 | } | |
16568 | ||
16569 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16570 | PIC code. It sets the $gp register for the function based on the | |
16571 | function address, which is in the register named in the argument. | |
16572 | This uses a relocation against _gp_disp, which is handled specially | |
16573 | by the linker. The result is: | |
16574 | lui $gp,%hi(_gp_disp) | |
16575 | addiu $gp,$gp,%lo(_gp_disp) | |
16576 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16577 | The .cpload argument is normally $25 == $t9. |
16578 | ||
16579 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16580 | lui $gp,%hi(__gnu_local_gp) |
16581 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16582 | and the argument is ignored. This saves an instruction, but the |
16583 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16584 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16585 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16586 | |
16587 | static void | |
17a2f251 | 16588 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16589 | { |
16590 | expressionS ex; | |
aa6975fb ILT |
16591 | int reg; |
16592 | int in_shared; | |
252b5132 | 16593 | |
6478892d TS |
16594 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16595 | .cpload is ignored. */ | |
16596 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16597 | { |
16598 | s_ignore (0); | |
16599 | return; | |
16600 | } | |
16601 | ||
a276b80c MR |
16602 | if (mips_opts.mips16) |
16603 | { | |
16604 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16605 | ignore_rest_of_line (); | |
16606 | return; | |
16607 | } | |
16608 | ||
d3ecfc59 | 16609 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16610 | if (mips_opts.noreorder == 0) |
16611 | as_warn (_(".cpload not in noreorder section")); | |
16612 | ||
aa6975fb ILT |
16613 | reg = tc_get_register (0); |
16614 | ||
16615 | /* If we need to produce a 64-bit address, we are better off using | |
16616 | the default instruction sequence. */ | |
aed1a261 | 16617 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16618 | |
252b5132 | 16619 | ex.X_op = O_symbol; |
bbe506e8 TS |
16620 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16621 | "__gnu_local_gp"); | |
252b5132 RH |
16622 | ex.X_op_symbol = NULL; |
16623 | ex.X_add_number = 0; | |
16624 | ||
16625 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16626 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16627 | |
584892a6 | 16628 | macro_start (); |
67c0d1eb RS |
16629 | macro_build_lui (&ex, mips_gp_register); |
16630 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16631 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16632 | if (in_shared) |
16633 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16634 | mips_gp_register, reg); | |
584892a6 | 16635 | macro_end (); |
252b5132 RH |
16636 | |
16637 | demand_empty_rest_of_line (); | |
16638 | } | |
16639 | ||
6478892d TS |
16640 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16641 | .cpsetup $reg1, offset|$reg2, label | |
16642 | ||
16643 | If offset is given, this results in: | |
16644 | sd $gp, offset($sp) | |
956cd1d6 | 16645 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16646 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16647 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16648 | |
16649 | If $reg2 is given, this results in: | |
16650 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16651 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16652 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16653 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16654 | $reg1 is normally $25 == $t9. |
16655 | ||
16656 | The -mno-shared option replaces the last three instructions with | |
16657 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16658 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16659 | |
6478892d | 16660 | static void |
17a2f251 | 16661 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16662 | { |
16663 | expressionS ex_off; | |
16664 | expressionS ex_sym; | |
16665 | int reg1; | |
6478892d | 16666 | |
8586fc66 | 16667 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16668 | We also need NewABI support. */ |
16669 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16670 | { | |
16671 | s_ignore (0); | |
16672 | return; | |
16673 | } | |
16674 | ||
a276b80c MR |
16675 | if (mips_opts.mips16) |
16676 | { | |
16677 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16678 | ignore_rest_of_line (); | |
16679 | return; | |
16680 | } | |
16681 | ||
6478892d TS |
16682 | reg1 = tc_get_register (0); |
16683 | SKIP_WHITESPACE (); | |
16684 | if (*input_line_pointer != ',') | |
16685 | { | |
16686 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16687 | return; | |
16688 | } | |
16689 | else | |
80245285 | 16690 | ++input_line_pointer; |
6478892d TS |
16691 | SKIP_WHITESPACE (); |
16692 | if (*input_line_pointer == '$') | |
80245285 TS |
16693 | { |
16694 | mips_cpreturn_register = tc_get_register (0); | |
16695 | mips_cpreturn_offset = -1; | |
16696 | } | |
6478892d | 16697 | else |
80245285 TS |
16698 | { |
16699 | mips_cpreturn_offset = get_absolute_expression (); | |
16700 | mips_cpreturn_register = -1; | |
16701 | } | |
6478892d TS |
16702 | SKIP_WHITESPACE (); |
16703 | if (*input_line_pointer != ',') | |
16704 | { | |
16705 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16706 | return; | |
16707 | } | |
16708 | else | |
f9419b05 | 16709 | ++input_line_pointer; |
6478892d | 16710 | SKIP_WHITESPACE (); |
f21f8242 | 16711 | expression (&ex_sym); |
6478892d | 16712 | |
584892a6 | 16713 | macro_start (); |
6478892d TS |
16714 | if (mips_cpreturn_register == -1) |
16715 | { | |
16716 | ex_off.X_op = O_constant; | |
16717 | ex_off.X_add_symbol = NULL; | |
16718 | ex_off.X_op_symbol = NULL; | |
16719 | ex_off.X_add_number = mips_cpreturn_offset; | |
16720 | ||
67c0d1eb | 16721 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16722 | BFD_RELOC_LO16, SP); |
6478892d TS |
16723 | } |
16724 | else | |
67c0d1eb | 16725 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16726 | mips_gp_register, 0); |
6478892d | 16727 | |
aed1a261 | 16728 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16729 | { |
df58fc94 | 16730 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16731 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16732 | BFD_RELOC_HI16_S); | |
16733 | ||
16734 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16735 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16736 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16737 | ||
16738 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16739 | mips_gp_register, reg1); | |
16740 | } | |
16741 | else | |
16742 | { | |
16743 | expressionS ex; | |
16744 | ||
16745 | ex.X_op = O_symbol; | |
4184909a | 16746 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16747 | ex.X_op_symbol = NULL; |
16748 | ex.X_add_number = 0; | |
6e1304d8 | 16749 | |
aa6975fb ILT |
16750 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16751 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16752 | ||
16753 | macro_build_lui (&ex, mips_gp_register); | |
16754 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16755 | mips_gp_register, BFD_RELOC_LO16); | |
16756 | } | |
f21f8242 | 16757 | |
584892a6 | 16758 | macro_end (); |
6478892d TS |
16759 | |
16760 | demand_empty_rest_of_line (); | |
16761 | } | |
16762 | ||
16763 | static void | |
17a2f251 | 16764 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16765 | { |
16766 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16767 | .cplocal is ignored. */ |
6478892d TS |
16768 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16769 | { | |
16770 | s_ignore (0); | |
16771 | return; | |
16772 | } | |
16773 | ||
a276b80c MR |
16774 | if (mips_opts.mips16) |
16775 | { | |
16776 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16777 | ignore_rest_of_line (); | |
16778 | return; | |
16779 | } | |
16780 | ||
6478892d | 16781 | mips_gp_register = tc_get_register (0); |
85b51719 | 16782 | demand_empty_rest_of_line (); |
6478892d TS |
16783 | } |
16784 | ||
252b5132 RH |
16785 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16786 | offset from $sp. The offset is remembered, and after making a PIC | |
16787 | call $gp is restored from that location. */ | |
16788 | ||
16789 | static void | |
17a2f251 | 16790 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16791 | { |
16792 | expressionS ex; | |
252b5132 | 16793 | |
6478892d | 16794 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16795 | .cprestore is ignored. */ |
6478892d | 16796 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16797 | { |
16798 | s_ignore (0); | |
16799 | return; | |
16800 | } | |
16801 | ||
a276b80c MR |
16802 | if (mips_opts.mips16) |
16803 | { | |
16804 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16805 | ignore_rest_of_line (); | |
16806 | return; | |
16807 | } | |
16808 | ||
252b5132 | 16809 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16810 | mips_cprestore_valid = 1; |
252b5132 RH |
16811 | |
16812 | ex.X_op = O_constant; | |
16813 | ex.X_add_symbol = NULL; | |
16814 | ex.X_op_symbol = NULL; | |
16815 | ex.X_add_number = mips_cprestore_offset; | |
16816 | ||
584892a6 | 16817 | macro_start (); |
67c0d1eb RS |
16818 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16819 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16820 | macro_end (); |
252b5132 RH |
16821 | |
16822 | demand_empty_rest_of_line (); | |
16823 | } | |
16824 | ||
6478892d | 16825 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16826 | was given in the preceding .cpsetup, it results in: |
6478892d | 16827 | ld $gp, offset($sp) |
76b3015f | 16828 | |
6478892d | 16829 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16830 | daddu $gp, $reg2, $0 */ |
16831 | ||
6478892d | 16832 | static void |
17a2f251 | 16833 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16834 | { |
16835 | expressionS ex; | |
6478892d TS |
16836 | |
16837 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16838 | We also need NewABI support. */ | |
16839 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16840 | { | |
16841 | s_ignore (0); | |
16842 | return; | |
16843 | } | |
16844 | ||
a276b80c MR |
16845 | if (mips_opts.mips16) |
16846 | { | |
16847 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16848 | ignore_rest_of_line (); | |
16849 | return; | |
16850 | } | |
16851 | ||
584892a6 | 16852 | macro_start (); |
6478892d TS |
16853 | if (mips_cpreturn_register == -1) |
16854 | { | |
16855 | ex.X_op = O_constant; | |
16856 | ex.X_add_symbol = NULL; | |
16857 | ex.X_op_symbol = NULL; | |
16858 | ex.X_add_number = mips_cpreturn_offset; | |
16859 | ||
67c0d1eb | 16860 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16861 | } |
16862 | else | |
67c0d1eb | 16863 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16864 | mips_cpreturn_register, 0); |
584892a6 | 16865 | macro_end (); |
6478892d TS |
16866 | |
16867 | demand_empty_rest_of_line (); | |
16868 | } | |
16869 | ||
d0f13682 CLT |
16870 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16871 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16872 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16873 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16874 | |
16875 | static void | |
d0f13682 CLT |
16876 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16877 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16878 | { |
16879 | expressionS ex; | |
16880 | char *p; | |
16881 | ||
16882 | expression (&ex); | |
16883 | ||
16884 | if (ex.X_op != O_symbol) | |
16885 | { | |
d0f13682 | 16886 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16887 | ignore_rest_of_line (); |
16888 | } | |
16889 | ||
16890 | p = frag_more (bytes); | |
16891 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16892 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16893 | demand_empty_rest_of_line (); |
de64cffd | 16894 | mips_clear_insn_labels (); |
741d6ea8 JM |
16895 | } |
16896 | ||
16897 | /* Handle .dtprelword. */ | |
16898 | ||
16899 | static void | |
16900 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16901 | { | |
d0f13682 | 16902 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16903 | } |
16904 | ||
16905 | /* Handle .dtpreldword. */ | |
16906 | ||
16907 | static void | |
16908 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16909 | { | |
d0f13682 CLT |
16910 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16911 | } | |
16912 | ||
16913 | /* Handle .tprelword. */ | |
16914 | ||
16915 | static void | |
16916 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16917 | { | |
16918 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16919 | } | |
16920 | ||
16921 | /* Handle .tpreldword. */ | |
16922 | ||
16923 | static void | |
16924 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16925 | { | |
16926 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16927 | } |
16928 | ||
6478892d TS |
16929 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16930 | code. It sets the offset to use in gp_rel relocations. */ | |
16931 | ||
16932 | static void | |
17a2f251 | 16933 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16934 | { |
16935 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16936 | We also need NewABI support. */ | |
16937 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16938 | { | |
16939 | s_ignore (0); | |
16940 | return; | |
16941 | } | |
16942 | ||
def2e0dd | 16943 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16944 | |
16945 | demand_empty_rest_of_line (); | |
16946 | } | |
16947 | ||
252b5132 RH |
16948 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16949 | code. It generates a 32 bit GP relative reloc. */ | |
16950 | ||
16951 | static void | |
17a2f251 | 16952 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16953 | { |
a8dbcb85 TS |
16954 | segment_info_type *si; |
16955 | struct insn_label_list *l; | |
252b5132 RH |
16956 | expressionS ex; |
16957 | char *p; | |
16958 | ||
16959 | /* When not generating PIC code, this is treated as .word. */ | |
16960 | if (mips_pic != SVR4_PIC) | |
16961 | { | |
16962 | s_cons (2); | |
16963 | return; | |
16964 | } | |
16965 | ||
a8dbcb85 TS |
16966 | si = seg_info (now_seg); |
16967 | l = si->label_list; | |
7d10b47d | 16968 | mips_emit_delays (); |
252b5132 | 16969 | if (auto_align) |
462427c4 | 16970 | mips_align (2, 0, l); |
252b5132 RH |
16971 | |
16972 | expression (&ex); | |
a1facbec | 16973 | mips_clear_insn_labels (); |
252b5132 RH |
16974 | |
16975 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16976 | { | |
16977 | as_bad (_("Unsupported use of .gpword")); | |
16978 | ignore_rest_of_line (); | |
16979 | } | |
16980 | ||
16981 | p = frag_more (4); | |
17a2f251 | 16982 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16983 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16984 | BFD_RELOC_GPREL32); |
252b5132 RH |
16985 | |
16986 | demand_empty_rest_of_line (); | |
16987 | } | |
16988 | ||
10181a0d | 16989 | static void |
17a2f251 | 16990 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16991 | { |
a8dbcb85 TS |
16992 | segment_info_type *si; |
16993 | struct insn_label_list *l; | |
10181a0d AO |
16994 | expressionS ex; |
16995 | char *p; | |
16996 | ||
16997 | /* When not generating PIC code, this is treated as .dword. */ | |
16998 | if (mips_pic != SVR4_PIC) | |
16999 | { | |
17000 | s_cons (3); | |
17001 | return; | |
17002 | } | |
17003 | ||
a8dbcb85 TS |
17004 | si = seg_info (now_seg); |
17005 | l = si->label_list; | |
7d10b47d | 17006 | mips_emit_delays (); |
10181a0d | 17007 | if (auto_align) |
462427c4 | 17008 | mips_align (3, 0, l); |
10181a0d AO |
17009 | |
17010 | expression (&ex); | |
a1facbec | 17011 | mips_clear_insn_labels (); |
10181a0d AO |
17012 | |
17013 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17014 | { | |
17015 | as_bad (_("Unsupported use of .gpdword")); | |
17016 | ignore_rest_of_line (); | |
17017 | } | |
17018 | ||
17019 | p = frag_more (8); | |
17a2f251 | 17020 | md_number_to_chars (p, 0, 8); |
a105a300 | 17021 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17022 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17023 | |
17024 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17025 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17026 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17027 | |
17028 | demand_empty_rest_of_line (); | |
17029 | } | |
17030 | ||
252b5132 RH |
17031 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17032 | tables in SVR4 PIC code. */ | |
17033 | ||
17034 | static void | |
17a2f251 | 17035 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17036 | { |
252b5132 RH |
17037 | int reg; |
17038 | ||
10181a0d AO |
17039 | /* This is ignored when not generating SVR4 PIC code. */ |
17040 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17041 | { |
17042 | s_ignore (0); | |
17043 | return; | |
17044 | } | |
17045 | ||
17046 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 17047 | macro_start (); |
252b5132 | 17048 | reg = tc_get_register (0); |
67c0d1eb | 17049 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17050 | macro_end (); |
252b5132 | 17051 | |
bdaaa2e1 | 17052 | demand_empty_rest_of_line (); |
252b5132 RH |
17053 | } |
17054 | ||
17055 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17056 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17057 | such as generating jalx instructions when needed. We also make |
17058 | them odd for the duration of the assembly, in order to generate the | |
17059 | right sort of code. We will make them even in the adjust_symtab | |
17060 | routine, while leaving them marked. This is convenient for the | |
17061 | debugger and the disassembler. The linker knows to make them odd | |
17062 | again. */ | |
17063 | ||
17064 | static void | |
17a2f251 | 17065 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17066 | { |
df58fc94 | 17067 | mips_mark_labels (); |
252b5132 RH |
17068 | |
17069 | demand_empty_rest_of_line (); | |
17070 | } | |
17071 | ||
17072 | /* Handle a .stabn directive. We need these in order to mark a label | |
17073 | as being a mips16 text label correctly. Sometimes the compiler | |
17074 | will emit a label, followed by a .stabn, and then switch sections. | |
17075 | If the label and .stabn are in mips16 mode, then the label is | |
17076 | really a mips16 text label. */ | |
17077 | ||
17078 | static void | |
17a2f251 | 17079 | s_mips_stab (int type) |
252b5132 | 17080 | { |
f9419b05 | 17081 | if (type == 'n') |
df58fc94 | 17082 | mips_mark_labels (); |
252b5132 RH |
17083 | |
17084 | s_stab (type); | |
17085 | } | |
17086 | ||
54f4ddb3 | 17087 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17088 | |
17089 | static void | |
17a2f251 | 17090 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17091 | { |
17092 | char *name; | |
17093 | int c; | |
17094 | symbolS *symbolP; | |
17095 | expressionS exp; | |
17096 | ||
17097 | name = input_line_pointer; | |
17098 | c = get_symbol_end (); | |
17099 | symbolP = symbol_find_or_make (name); | |
17100 | S_SET_WEAK (symbolP); | |
17101 | *input_line_pointer = c; | |
17102 | ||
17103 | SKIP_WHITESPACE (); | |
17104 | ||
17105 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17106 | { | |
17107 | if (S_IS_DEFINED (symbolP)) | |
17108 | { | |
20203fb9 | 17109 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17110 | S_GET_NAME (symbolP)); |
17111 | ignore_rest_of_line (); | |
17112 | return; | |
17113 | } | |
bdaaa2e1 | 17114 | |
252b5132 RH |
17115 | if (*input_line_pointer == ',') |
17116 | { | |
17117 | ++input_line_pointer; | |
17118 | SKIP_WHITESPACE (); | |
17119 | } | |
bdaaa2e1 | 17120 | |
252b5132 RH |
17121 | expression (&exp); |
17122 | if (exp.X_op != O_symbol) | |
17123 | { | |
20203fb9 | 17124 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17125 | ignore_rest_of_line (); |
252b5132 RH |
17126 | return; |
17127 | } | |
49309057 | 17128 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17129 | } |
17130 | ||
17131 | demand_empty_rest_of_line (); | |
17132 | } | |
17133 | ||
17134 | /* Parse a register string into a number. Called from the ECOFF code | |
17135 | to parse .frame. The argument is non-zero if this is the frame | |
17136 | register, so that we can record it in mips_frame_reg. */ | |
17137 | ||
17138 | int | |
17a2f251 | 17139 | tc_get_register (int frame) |
252b5132 | 17140 | { |
707bfff6 | 17141 | unsigned int reg; |
252b5132 RH |
17142 | |
17143 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17144 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17145 | reg = 0; | |
252b5132 | 17146 | if (frame) |
7a621144 DJ |
17147 | { |
17148 | mips_frame_reg = reg != 0 ? reg : SP; | |
17149 | mips_frame_reg_valid = 1; | |
17150 | mips_cprestore_valid = 0; | |
17151 | } | |
252b5132 RH |
17152 | return reg; |
17153 | } | |
17154 | ||
17155 | valueT | |
17a2f251 | 17156 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17157 | { |
17158 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17159 | ||
b4c71f56 TS |
17160 | if (IS_ELF) |
17161 | { | |
17162 | /* We don't need to align ELF sections to the full alignment. | |
17163 | However, Irix 5 may prefer that we align them at least to a 16 | |
17164 | byte boundary. We don't bother to align the sections if we | |
17165 | are targeted for an embedded system. */ | |
c41e87e3 | 17166 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17167 | return addr; |
17168 | if (align > 4) | |
17169 | align = 4; | |
17170 | } | |
252b5132 RH |
17171 | |
17172 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17173 | } | |
17174 | ||
17175 | /* Utility routine, called from above as well. If called while the | |
17176 | input file is still being read, it's only an approximation. (For | |
17177 | example, a symbol may later become defined which appeared to be | |
17178 | undefined earlier.) */ | |
17179 | ||
17180 | static int | |
17a2f251 | 17181 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17182 | { |
17183 | if (sym == 0) | |
17184 | return 0; | |
17185 | ||
4d0d148d | 17186 | if (g_switch_value > 0) |
252b5132 RH |
17187 | { |
17188 | const char *symname; | |
17189 | int change; | |
17190 | ||
c9914766 | 17191 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17192 | register. It can be if it is smaller than the -G size or if |
17193 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17194 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17195 | they can. */ |
17196 | symname = S_GET_NAME (sym); | |
17197 | if (symname != (const char *) NULL | |
17198 | && (strcmp (symname, "eprol") == 0 | |
17199 | || strcmp (symname, "etext") == 0 | |
17200 | || strcmp (symname, "_gp") == 0 | |
17201 | || strcmp (symname, "edata") == 0 | |
17202 | || strcmp (symname, "_fbss") == 0 | |
17203 | || strcmp (symname, "_fdata") == 0 | |
17204 | || strcmp (symname, "_ftext") == 0 | |
17205 | || strcmp (symname, "end") == 0 | |
17206 | || strcmp (symname, "_gp_disp") == 0)) | |
17207 | change = 1; | |
17208 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17209 | && (0 | |
17210 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17211 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17212 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17213 | <= g_switch_value)) | |
252b5132 RH |
17214 | #endif |
17215 | /* We must defer this decision until after the whole | |
17216 | file has been read, since there might be a .extern | |
17217 | after the first use of this symbol. */ | |
17218 | || (before_relaxing | |
17219 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17220 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17221 | #endif |
17222 | && S_GET_VALUE (sym) == 0) | |
17223 | || (S_GET_VALUE (sym) != 0 | |
17224 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17225 | change = 0; | |
17226 | else | |
17227 | { | |
17228 | const char *segname; | |
17229 | ||
17230 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17231 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17232 | && strcmp (segname, ".lit4") != 0); |
17233 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17234 | && strcmp (segname, ".sbss") != 0 |
17235 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17236 | && strncmp (segname, ".sbss.", 6) != 0 |
17237 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17238 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17239 | } |
17240 | return change; | |
17241 | } | |
17242 | else | |
c9914766 | 17243 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17244 | return 1; |
17245 | } | |
17246 | ||
5919d012 RS |
17247 | |
17248 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17249 | ||
17250 | static bfd_boolean | |
17a2f251 | 17251 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17252 | { |
17253 | asection *symsec; | |
5919d012 RS |
17254 | |
17255 | /* Handle the case of a symbol equated to another symbol. */ | |
17256 | while (symbol_equated_reloc_p (sym)) | |
17257 | { | |
17258 | symbolS *n; | |
17259 | ||
5f0fe04b | 17260 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17261 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17262 | if (n == sym) | |
17263 | break; | |
17264 | sym = n; | |
17265 | } | |
17266 | ||
df1f3cda DD |
17267 | if (symbol_section_p (sym)) |
17268 | return TRUE; | |
17269 | ||
5919d012 RS |
17270 | symsec = S_GET_SEGMENT (sym); |
17271 | ||
5919d012 | 17272 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17273 | return (!bfd_is_und_section (symsec) |
17274 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17275 | && !bfd_is_com_section (symsec) |
17276 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17277 | #ifdef OBJ_ELF |
17278 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17279 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17280 | #endif |
17281 | ); | |
17282 | } | |
17283 | ||
17284 | ||
252b5132 RH |
17285 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17286 | extended opcode. SEC is the section the frag is in. */ | |
17287 | ||
17288 | static int | |
17a2f251 | 17289 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17290 | { |
17291 | int type; | |
3994f87e | 17292 | const struct mips16_immed_operand *op; |
252b5132 RH |
17293 | offsetT val; |
17294 | int mintiny, maxtiny; | |
17295 | segT symsec; | |
98aa84af | 17296 | fragS *sym_frag; |
252b5132 RH |
17297 | |
17298 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17299 | return 0; | |
17300 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17301 | return 1; | |
17302 | ||
17303 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17304 | op = mips16_immed_operands; | |
17305 | while (op->type != type) | |
17306 | { | |
17307 | ++op; | |
9c2799c2 | 17308 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17309 | } |
17310 | ||
17311 | if (op->unsp) | |
17312 | { | |
17313 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17314 | { | |
17315 | mintiny = 1; | |
17316 | maxtiny = 1 << op->nbits; | |
17317 | } | |
17318 | else | |
17319 | { | |
17320 | mintiny = 0; | |
17321 | maxtiny = (1 << op->nbits) - 1; | |
17322 | } | |
17323 | } | |
17324 | else | |
17325 | { | |
17326 | mintiny = - (1 << (op->nbits - 1)); | |
17327 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17328 | } | |
17329 | ||
98aa84af | 17330 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17331 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17332 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17333 | |
17334 | if (op->pcrel) | |
17335 | { | |
17336 | addressT addr; | |
17337 | ||
17338 | /* We won't have the section when we are called from | |
17339 | mips_relax_frag. However, we will always have been called | |
17340 | from md_estimate_size_before_relax first. If this is a | |
17341 | branch to a different section, we mark it as such. If SEC is | |
17342 | NULL, and the frag is not marked, then it must be a branch to | |
17343 | the same section. */ | |
17344 | if (sec == NULL) | |
17345 | { | |
17346 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17347 | return 1; | |
17348 | } | |
17349 | else | |
17350 | { | |
98aa84af | 17351 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17352 | if (symsec != sec) |
17353 | { | |
17354 | fragp->fr_subtype = | |
17355 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17356 | ||
17357 | /* FIXME: We should support this, and let the linker | |
17358 | catch branches and loads that are out of range. */ | |
17359 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17360 | _("unsupported PC relative reference to different section")); | |
17361 | ||
17362 | return 1; | |
17363 | } | |
98aa84af AM |
17364 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17365 | /* Assume non-extended on the first relaxation pass. | |
17366 | The address we have calculated will be bogus if this is | |
17367 | a forward branch to another frag, as the forward frag | |
17368 | will have fr_address == 0. */ | |
17369 | return 0; | |
252b5132 RH |
17370 | } |
17371 | ||
17372 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17373 | the same section. If the relax_marker of the symbol fragment |
17374 | differs from the relax_marker of this fragment, we have not | |
17375 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17376 | in STRETCH in order to get a better estimate of the address. |
17377 | This particularly matters because of the shift bits. */ | |
17378 | if (stretch != 0 | |
98aa84af | 17379 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17380 | { |
17381 | fragS *f; | |
17382 | ||
17383 | /* Adjust stretch for any alignment frag. Note that if have | |
17384 | been expanding the earlier code, the symbol may be | |
17385 | defined in what appears to be an earlier frag. FIXME: | |
17386 | This doesn't handle the fr_subtype field, which specifies | |
17387 | a maximum number of bytes to skip when doing an | |
17388 | alignment. */ | |
98aa84af | 17389 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17390 | { |
17391 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17392 | { | |
17393 | if (stretch < 0) | |
17394 | stretch = - ((- stretch) | |
17395 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17396 | else | |
17397 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17398 | if (stretch == 0) | |
17399 | break; | |
17400 | } | |
17401 | } | |
17402 | if (f != NULL) | |
17403 | val += stretch; | |
17404 | } | |
17405 | ||
17406 | addr = fragp->fr_address + fragp->fr_fix; | |
17407 | ||
17408 | /* The base address rules are complicated. The base address of | |
17409 | a branch is the following instruction. The base address of a | |
17410 | PC relative load or add is the instruction itself, but if it | |
17411 | is in a delay slot (in which case it can not be extended) use | |
17412 | the address of the instruction whose delay slot it is in. */ | |
17413 | if (type == 'p' || type == 'q') | |
17414 | { | |
17415 | addr += 2; | |
17416 | ||
17417 | /* If we are currently assuming that this frag should be | |
17418 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17419 | higher. */ |
252b5132 RH |
17420 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17421 | addr += 2; | |
17422 | ||
17423 | /* Ignore the low bit in the target, since it will be set | |
17424 | for a text label. */ | |
17425 | if ((val & 1) != 0) | |
17426 | --val; | |
17427 | } | |
17428 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17429 | addr -= 4; | |
17430 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17431 | addr -= 2; | |
17432 | ||
17433 | val -= addr & ~ ((1 << op->shift) - 1); | |
17434 | ||
17435 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17436 | if (type == 'p' || type == 'q') | |
17437 | val /= 2; | |
17438 | ||
17439 | /* If any of the shifted bits are set, we must use an extended | |
17440 | opcode. If the address depends on the size of this | |
17441 | instruction, this can lead to a loop, so we arrange to always | |
17442 | use an extended opcode. We only check this when we are in | |
17443 | the main relaxation loop, when SEC is NULL. */ | |
17444 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17445 | { | |
17446 | fragp->fr_subtype = | |
17447 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17448 | return 1; | |
17449 | } | |
17450 | ||
17451 | /* If we are about to mark a frag as extended because the value | |
17452 | is precisely maxtiny + 1, then there is a chance of an | |
17453 | infinite loop as in the following code: | |
17454 | la $4,foo | |
17455 | .skip 1020 | |
17456 | .align 2 | |
17457 | foo: | |
17458 | In this case when the la is extended, foo is 0x3fc bytes | |
17459 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17460 | the la must be extended. To avoid this loop, we mark the | |
17461 | frag as extended if it was small, and is about to become | |
17462 | extended with a value of maxtiny + 1. */ | |
17463 | if (val == ((maxtiny + 1) << op->shift) | |
17464 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17465 | && sec == NULL) | |
17466 | { | |
17467 | fragp->fr_subtype = | |
17468 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17469 | return 1; | |
17470 | } | |
17471 | } | |
17472 | else if (symsec != absolute_section && sec != NULL) | |
17473 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17474 | ||
17475 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17476 | || val < (mintiny << op->shift) | |
17477 | || val > (maxtiny << op->shift)) | |
17478 | return 1; | |
17479 | else | |
17480 | return 0; | |
17481 | } | |
17482 | ||
4a6a3df4 AO |
17483 | /* Compute the length of a branch sequence, and adjust the |
17484 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17485 | worst-case length is computed, with UPDATE being used to indicate | |
17486 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17487 | branch is to be computed. */ | |
17488 | static int | |
17a2f251 | 17489 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17490 | { |
b34976b6 | 17491 | bfd_boolean toofar; |
4a6a3df4 AO |
17492 | int length; |
17493 | ||
17494 | if (fragp | |
17495 | && S_IS_DEFINED (fragp->fr_symbol) | |
17496 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17497 | { | |
17498 | addressT addr; | |
17499 | offsetT val; | |
17500 | ||
17501 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17502 | ||
17503 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17504 | ||
17505 | val -= addr; | |
17506 | ||
17507 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17508 | } | |
17509 | else if (fragp) | |
17510 | /* If the symbol is not defined or it's in a different segment, | |
17511 | assume the user knows what's going on and emit a short | |
17512 | branch. */ | |
b34976b6 | 17513 | toofar = FALSE; |
4a6a3df4 | 17514 | else |
b34976b6 | 17515 | toofar = TRUE; |
4a6a3df4 AO |
17516 | |
17517 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17518 | fragp->fr_subtype | |
66b3e8da MR |
17519 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17520 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17521 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17522 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17523 | toofar); | |
17524 | ||
17525 | length = 4; | |
17526 | if (toofar) | |
17527 | { | |
17528 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17529 | length += 8; | |
17530 | ||
17531 | if (mips_pic != NO_PIC) | |
17532 | { | |
17533 | /* Additional space for PIC loading of target address. */ | |
17534 | length += 8; | |
17535 | if (mips_opts.isa == ISA_MIPS1) | |
17536 | /* Additional space for $at-stabilizing nop. */ | |
17537 | length += 4; | |
17538 | } | |
17539 | ||
17540 | /* If branch is conditional. */ | |
17541 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17542 | length += 8; | |
17543 | } | |
b34976b6 | 17544 | |
4a6a3df4 AO |
17545 | return length; |
17546 | } | |
17547 | ||
df58fc94 RS |
17548 | /* Compute the length of a branch sequence, and adjust the |
17549 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17550 | worst-case length is computed, with UPDATE being used to indicate | |
17551 | whether an unconditional (-1), or regular (0) branch is to be | |
17552 | computed. */ | |
17553 | ||
17554 | static int | |
17555 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17556 | { | |
17557 | bfd_boolean toofar; | |
17558 | int length; | |
17559 | ||
17560 | if (fragp | |
17561 | && S_IS_DEFINED (fragp->fr_symbol) | |
17562 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17563 | { | |
17564 | addressT addr; | |
17565 | offsetT val; | |
17566 | ||
17567 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17568 | /* Ignore the low bit in the target, since it will be set | |
17569 | for a text label. */ | |
17570 | if ((val & 1) != 0) | |
17571 | --val; | |
17572 | ||
17573 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17574 | ||
17575 | val -= addr; | |
17576 | ||
17577 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17578 | } | |
17579 | else if (fragp) | |
17580 | /* If the symbol is not defined or it's in a different segment, | |
17581 | assume the user knows what's going on and emit a short | |
17582 | branch. */ | |
17583 | toofar = FALSE; | |
17584 | else | |
17585 | toofar = TRUE; | |
17586 | ||
17587 | if (fragp && update | |
17588 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17589 | fragp->fr_subtype = (toofar | |
17590 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17591 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17592 | ||
17593 | length = 4; | |
17594 | if (toofar) | |
17595 | { | |
17596 | bfd_boolean compact_known = fragp != NULL; | |
17597 | bfd_boolean compact = FALSE; | |
17598 | bfd_boolean uncond; | |
17599 | ||
17600 | if (compact_known) | |
17601 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17602 | if (fragp) | |
17603 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17604 | else | |
17605 | uncond = update < 0; | |
17606 | ||
17607 | /* If label is out of range, we turn branch <br>: | |
17608 | ||
17609 | <br> label # 4 bytes | |
17610 | 0: | |
17611 | ||
17612 | into: | |
17613 | ||
17614 | j label # 4 bytes | |
17615 | nop # 2 bytes if compact && !PIC | |
17616 | 0: | |
17617 | */ | |
17618 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17619 | length += 2; | |
17620 | ||
17621 | /* If assembling PIC code, we further turn: | |
17622 | ||
17623 | j label # 4 bytes | |
17624 | ||
17625 | into: | |
17626 | ||
17627 | lw/ld at, %got(label)(gp) # 4 bytes | |
17628 | d/addiu at, %lo(label) # 4 bytes | |
17629 | jr/c at # 2 bytes | |
17630 | */ | |
17631 | if (mips_pic != NO_PIC) | |
17632 | length += 6; | |
17633 | ||
17634 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17635 | ||
17636 | <brneg> 0f # 4 bytes | |
17637 | nop # 2 bytes if !compact | |
17638 | */ | |
17639 | if (!uncond) | |
17640 | length += (compact_known && compact) ? 4 : 6; | |
17641 | } | |
17642 | ||
17643 | return length; | |
17644 | } | |
17645 | ||
17646 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17647 | bit accordingly. */ | |
17648 | ||
17649 | static int | |
17650 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17651 | { | |
17652 | bfd_boolean toofar; | |
17653 | ||
df58fc94 RS |
17654 | if (fragp |
17655 | && S_IS_DEFINED (fragp->fr_symbol) | |
17656 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17657 | { | |
17658 | addressT addr; | |
17659 | offsetT val; | |
17660 | int type; | |
17661 | ||
17662 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17663 | /* Ignore the low bit in the target, since it will be set | |
17664 | for a text label. */ | |
17665 | if ((val & 1) != 0) | |
17666 | --val; | |
17667 | ||
17668 | /* Assume this is a 2-byte branch. */ | |
17669 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17670 | ||
17671 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17672 | long branches. */ | |
17673 | ||
17674 | val -= addr; | |
17675 | ||
17676 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17677 | if (type == 'D') | |
17678 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17679 | else if (type == 'E') | |
17680 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17681 | else | |
17682 | abort (); | |
17683 | } | |
17684 | else | |
17685 | /* If the symbol is not defined or it's in a different segment, | |
17686 | we emit a normal 32-bit branch. */ | |
17687 | toofar = TRUE; | |
17688 | ||
17689 | if (fragp && update | |
17690 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17691 | fragp->fr_subtype | |
17692 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17693 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17694 | ||
17695 | if (toofar) | |
17696 | return 4; | |
17697 | ||
17698 | return 2; | |
17699 | } | |
17700 | ||
252b5132 RH |
17701 | /* Estimate the size of a frag before relaxing. Unless this is the |
17702 | mips16, we are not really relaxing here, and the final size is | |
17703 | encoded in the subtype information. For the mips16, we have to | |
17704 | decide whether we are using an extended opcode or not. */ | |
17705 | ||
252b5132 | 17706 | int |
17a2f251 | 17707 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17708 | { |
5919d012 | 17709 | int change; |
252b5132 | 17710 | |
4a6a3df4 AO |
17711 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17712 | { | |
17713 | ||
b34976b6 AM |
17714 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17715 | ||
4a6a3df4 AO |
17716 | return fragp->fr_var; |
17717 | } | |
17718 | ||
252b5132 | 17719 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17720 | /* We don't want to modify the EXTENDED bit here; it might get us |
17721 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17722 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17723 | |
df58fc94 RS |
17724 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17725 | { | |
17726 | int length = 4; | |
17727 | ||
17728 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17729 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17730 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17731 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17732 | fragp->fr_var = length; | |
17733 | ||
17734 | return length; | |
17735 | } | |
17736 | ||
252b5132 | 17737 | if (mips_pic == NO_PIC) |
5919d012 | 17738 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17739 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17740 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17741 | else if (mips_pic == VXWORKS_PIC) |
17742 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17743 | change = 0; | |
252b5132 RH |
17744 | else |
17745 | abort (); | |
17746 | ||
17747 | if (change) | |
17748 | { | |
4d7206a2 | 17749 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17750 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17751 | } |
4d7206a2 RS |
17752 | else |
17753 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17754 | } |
17755 | ||
17756 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17757 | should be converted into a reloc against a section. */ |
252b5132 RH |
17758 | |
17759 | int | |
17a2f251 | 17760 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17761 | { |
252b5132 RH |
17762 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17763 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17764 | return 0; | |
a161fe53 | 17765 | |
252b5132 RH |
17766 | if (fixp->fx_addsy == NULL) |
17767 | return 1; | |
a161fe53 | 17768 | |
de7e6852 RS |
17769 | /* If symbol SYM is in a mergeable section, relocations of the form |
17770 | SYM + 0 can usually be made section-relative. The mergeable data | |
17771 | is then identified by the section offset rather than by the symbol. | |
17772 | ||
17773 | However, if we're generating REL LO16 relocations, the offset is split | |
17774 | between the LO16 and parterning high part relocation. The linker will | |
17775 | need to recalculate the complete offset in order to correctly identify | |
17776 | the merge data. | |
17777 | ||
17778 | The linker has traditionally not looked for the parterning high part | |
17779 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17780 | placed anywhere. Rather than break backwards compatibility by changing | |
17781 | this, it seems better not to force the issue, and instead keep the | |
17782 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17783 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17784 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17785 | && HAVE_IN_PLACE_ADDENDS |
17786 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17787 | return 0; | |
17788 | ||
ce70d90a MR |
17789 | /* There is no place to store an in-place offset for JALR relocations. |
17790 | Likewise an in-range offset of PC-relative relocations may overflow | |
17791 | the in-place relocatable field if recalculated against the start | |
17792 | address of the symbol's containing section. */ | |
17793 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17794 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17795 | return 0; |
17796 | ||
252b5132 | 17797 | #ifdef OBJ_ELF |
b314ec0e RS |
17798 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17799 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17800 | relocations against MIPS16 functions; in this case, the stub becomes | |
17801 | the function's canonical address. | |
17802 | ||
17803 | Floating-point stubs are stored in unique .mips16.call.* or | |
17804 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17805 | the first relocation in section S must be against F; this is how the | |
17806 | linker determines the target function. All relocations that might | |
17807 | resolve to T must also be against F. We therefore have the following | |
17808 | restrictions, which are given in an intentionally-redundant way: | |
17809 | ||
17810 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17811 | symbols. | |
17812 | ||
17813 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17814 | if that stub might be used. | |
17815 | ||
17816 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17817 | symbols. | |
17818 | ||
17819 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17820 | that stub might be used. | |
17821 | ||
17822 | There is a further restriction: | |
17823 | ||
df58fc94 RS |
17824 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17825 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17826 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17827 | encode the low bit. |
17828 | ||
df58fc94 RS |
17829 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17830 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17831 | such relocations on REL targets. | |
b314ec0e RS |
17832 | |
17833 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17834 | relocation against some symbol R, no relocation against R may be | |
17835 | reduced. (Note that this deals with (2) as well as (1) because | |
17836 | relocations against global symbols will never be reduced on ELF | |
17837 | targets.) This approach is a little simpler than trying to detect | |
17838 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17839 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17840 | if (IS_ELF |
b314ec0e | 17841 | && fixp->fx_subsy == NULL |
30c09090 | 17842 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17843 | || *symbol_get_tc (fixp->fx_addsy) |
17844 | || (HAVE_IN_PLACE_ADDENDS | |
17845 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17846 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17847 | return 0; |
17848 | #endif | |
a161fe53 | 17849 | |
252b5132 RH |
17850 | return 1; |
17851 | } | |
17852 | ||
17853 | /* Translate internal representation of relocation info to BFD target | |
17854 | format. */ | |
17855 | ||
17856 | arelent ** | |
17a2f251 | 17857 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17858 | { |
17859 | static arelent *retval[4]; | |
17860 | arelent *reloc; | |
17861 | bfd_reloc_code_real_type code; | |
17862 | ||
4b0cff4e TS |
17863 | memset (retval, 0, sizeof(retval)); |
17864 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17865 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17866 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17867 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17868 | ||
bad36eac DJ |
17869 | if (fixp->fx_pcrel) |
17870 | { | |
df58fc94 RS |
17871 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17872 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17873 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17874 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17875 | |
17876 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17877 | Relocations want only the symbol offset. */ | |
17878 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17879 | if (!IS_ELF) |
bad36eac DJ |
17880 | { |
17881 | /* A gruesome hack which is a result of the gruesome gas | |
17882 | reloc handling. What's worse, for COFF (as opposed to | |
17883 | ECOFF), we might need yet another copy of reloc->address. | |
17884 | See bfd_install_relocation. */ | |
17885 | reloc->addend += reloc->address; | |
17886 | } | |
17887 | } | |
17888 | else | |
17889 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17890 | |
438c16b8 TS |
17891 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17892 | entry to be used in the relocation's section offset. */ | |
17893 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17894 | { |
17895 | reloc->address = reloc->addend; | |
17896 | reloc->addend = 0; | |
17897 | } | |
17898 | ||
252b5132 | 17899 | code = fixp->fx_r_type; |
252b5132 | 17900 | |
bad36eac | 17901 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17902 | if (reloc->howto == NULL) |
17903 | { | |
17904 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17905 | _("Can not represent %s relocation in this object file format"), | |
17906 | bfd_get_reloc_code_name (code)); | |
17907 | retval[0] = NULL; | |
17908 | } | |
17909 | ||
17910 | return retval; | |
17911 | } | |
17912 | ||
17913 | /* Relax a machine dependent frag. This returns the amount by which | |
17914 | the current size of the frag should change. */ | |
17915 | ||
17916 | int | |
17a2f251 | 17917 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17918 | { |
4a6a3df4 AO |
17919 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17920 | { | |
17921 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17922 | |
17923 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17924 | |
17925 | return fragp->fr_var - old_var; | |
17926 | } | |
17927 | ||
df58fc94 RS |
17928 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17929 | { | |
17930 | offsetT old_var = fragp->fr_var; | |
17931 | offsetT new_var = 4; | |
17932 | ||
17933 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17934 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17935 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17936 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17937 | fragp->fr_var = new_var; | |
17938 | ||
17939 | return new_var - old_var; | |
17940 | } | |
17941 | ||
252b5132 RH |
17942 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17943 | return 0; | |
17944 | ||
c4e7957c | 17945 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17946 | { |
17947 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17948 | return 0; | |
17949 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17950 | return 2; | |
17951 | } | |
17952 | else | |
17953 | { | |
17954 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17955 | return 0; | |
17956 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17957 | return -2; | |
17958 | } | |
17959 | ||
17960 | return 0; | |
17961 | } | |
17962 | ||
17963 | /* Convert a machine dependent frag. */ | |
17964 | ||
17965 | void | |
17a2f251 | 17966 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17967 | { |
4a6a3df4 AO |
17968 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17969 | { | |
4d68580a | 17970 | char *buf; |
4a6a3df4 AO |
17971 | unsigned long insn; |
17972 | expressionS exp; | |
17973 | fixS *fixp; | |
b34976b6 | 17974 | |
4d68580a RS |
17975 | buf = fragp->fr_literal + fragp->fr_fix; |
17976 | insn = read_insn (buf); | |
b34976b6 | 17977 | |
4a6a3df4 AO |
17978 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17979 | { | |
17980 | /* We generate a fixup instead of applying it right now | |
17981 | because, if there are linker relaxations, we're going to | |
17982 | need the relocations. */ | |
17983 | exp.X_op = O_symbol; | |
17984 | exp.X_add_symbol = fragp->fr_symbol; | |
17985 | exp.X_add_number = fragp->fr_offset; | |
17986 | ||
4d68580a RS |
17987 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
17988 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
17989 | fixp->fx_file = fragp->fr_file; |
17990 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17991 | |
4d68580a | 17992 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17993 | } |
17994 | else | |
17995 | { | |
17996 | int i; | |
17997 | ||
17998 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17999 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18000 | |
18001 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18002 | goto uncond; | |
18003 | ||
18004 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18005 | { | |
18006 | /* Reverse the branch. */ | |
18007 | switch ((insn >> 28) & 0xf) | |
18008 | { | |
18009 | case 4: | |
18010 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
18011 | have the condition reversed by tweaking a single | |
18012 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 18013 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
18014 | insn ^= 0x00010000; |
18015 | break; | |
18016 | ||
18017 | case 0: | |
18018 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18019 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18020 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18021 | insn ^= 0x00010000; |
18022 | break; | |
b34976b6 | 18023 | |
4a6a3df4 AO |
18024 | case 1: |
18025 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18026 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18027 | insn ^= 0x04000000; |
18028 | break; | |
18029 | ||
18030 | default: | |
18031 | abort (); | |
18032 | } | |
18033 | } | |
18034 | ||
18035 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18036 | { | |
18037 | /* Clear the and-link bit. */ | |
9c2799c2 | 18038 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18039 | |
54f4ddb3 TS |
18040 | /* bltzal 0x04100000 bgezal 0x04110000 |
18041 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18042 | insn &= ~0x00100000; |
18043 | } | |
18044 | ||
18045 | /* Branch over the branch (if the branch was likely) or the | |
18046 | full jump (not likely case). Compute the offset from the | |
18047 | current instruction to branch to. */ | |
18048 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18049 | i = 16; | |
18050 | else | |
18051 | { | |
18052 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18053 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18054 | /* How many bytes in instructions from here to the end? */ |
18055 | i = fragp->fr_var - i; | |
18056 | } | |
18057 | /* Convert to instruction count. */ | |
18058 | i >>= 2; | |
18059 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18060 | i--; |
4a6a3df4 AO |
18061 | insn |= i; |
18062 | /* Branch over the jump. */ | |
4d68580a | 18063 | buf = write_insn (buf, insn); |
4a6a3df4 | 18064 | |
54f4ddb3 | 18065 | /* nop */ |
4d68580a | 18066 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18067 | |
18068 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18069 | { | |
18070 | /* beql $0, $0, 2f */ | |
18071 | insn = 0x50000000; | |
18072 | /* Compute the PC offset from the current instruction to | |
18073 | the end of the variable frag. */ | |
18074 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18075 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18076 | /* How many bytes in instructions from here to the end? */ |
18077 | i = fragp->fr_var - i; | |
18078 | /* Convert to instruction count. */ | |
18079 | i >>= 2; | |
18080 | /* Don't decrement i, because we want to branch over the | |
18081 | delay slot. */ | |
4a6a3df4 | 18082 | insn |= i; |
4a6a3df4 | 18083 | |
4d68580a RS |
18084 | buf = write_insn (buf, insn); |
18085 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18086 | } |
18087 | ||
18088 | uncond: | |
18089 | if (mips_pic == NO_PIC) | |
18090 | { | |
18091 | /* j or jal. */ | |
18092 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18093 | ? 0x0c000000 : 0x08000000); | |
18094 | exp.X_op = O_symbol; | |
18095 | exp.X_add_symbol = fragp->fr_symbol; | |
18096 | exp.X_add_number = fragp->fr_offset; | |
18097 | ||
4d68580a RS |
18098 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18099 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18100 | fixp->fx_file = fragp->fr_file; |
18101 | fixp->fx_line = fragp->fr_line; | |
18102 | ||
4d68580a | 18103 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18104 | } |
18105 | else | |
18106 | { | |
66b3e8da MR |
18107 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18108 | ||
4a6a3df4 | 18109 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18110 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18111 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18112 | exp.X_op = O_symbol; |
18113 | exp.X_add_symbol = fragp->fr_symbol; | |
18114 | exp.X_add_number = fragp->fr_offset; | |
18115 | ||
18116 | if (fragp->fr_offset) | |
18117 | { | |
18118 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18119 | exp.X_add_number = 0; | |
18120 | } | |
18121 | ||
4d68580a RS |
18122 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18123 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18124 | fixp->fx_file = fragp->fr_file; |
18125 | fixp->fx_line = fragp->fr_line; | |
18126 | ||
4d68580a | 18127 | buf = write_insn (buf, insn); |
b34976b6 | 18128 | |
4a6a3df4 | 18129 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18130 | /* nop */ |
18131 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18132 | |
18133 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18134 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18135 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18136 | |
4d68580a RS |
18137 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18138 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18139 | fixp->fx_file = fragp->fr_file; |
18140 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18141 | |
4d68580a | 18142 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18143 | |
18144 | /* j(al)r $at. */ | |
18145 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18146 | insn = 0x0000f809; |
4a6a3df4 | 18147 | else |
66b3e8da MR |
18148 | insn = 0x00000008; |
18149 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18150 | |
4d68580a | 18151 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18152 | } |
18153 | } | |
18154 | ||
4a6a3df4 | 18155 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18156 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18157 | return; |
18158 | } | |
18159 | ||
df58fc94 RS |
18160 | /* Relax microMIPS branches. */ |
18161 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18162 | { | |
4d68580a | 18163 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18164 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18165 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18166 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18167 | bfd_boolean short_ds; |
df58fc94 RS |
18168 | unsigned long insn; |
18169 | expressionS exp; | |
18170 | fixS *fixp; | |
18171 | ||
18172 | exp.X_op = O_symbol; | |
18173 | exp.X_add_symbol = fragp->fr_symbol; | |
18174 | exp.X_add_number = fragp->fr_offset; | |
18175 | ||
18176 | fragp->fr_fix += fragp->fr_var; | |
18177 | ||
18178 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18179 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18180 | { | |
18181 | /* We generate a fixup instead of applying it right now, | |
18182 | because if there is linker relaxation, we're going to | |
18183 | need the relocations. */ | |
18184 | if (type == 'D') | |
4d68580a | 18185 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18186 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18187 | else if (type == 'E') | |
4d68580a | 18188 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18189 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18190 | else | |
18191 | abort (); | |
18192 | ||
18193 | fixp->fx_file = fragp->fr_file; | |
18194 | fixp->fx_line = fragp->fr_line; | |
18195 | ||
18196 | /* These relocations can have an addend that won't fit in | |
18197 | 2 octets. */ | |
18198 | fixp->fx_no_overflow = 1; | |
18199 | ||
18200 | return; | |
18201 | } | |
18202 | ||
2309ddf2 | 18203 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18204 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18205 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18206 | { | |
18207 | /* We generate a fixup instead of applying it right now, | |
18208 | because if there is linker relaxation, we're going to | |
18209 | need the relocations. */ | |
4d68580a RS |
18210 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18211 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18212 | fixp->fx_file = fragp->fr_file; |
18213 | fixp->fx_line = fragp->fr_line; | |
18214 | ||
18215 | if (type == 0) | |
18216 | return; | |
18217 | } | |
18218 | ||
18219 | /* Relax 16-bit branches to 32-bit branches. */ | |
18220 | if (type != 0) | |
18221 | { | |
4d68580a | 18222 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18223 | |
18224 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18225 | insn = 0x94000000; /* beq */ | |
18226 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18227 | { | |
18228 | unsigned long regno; | |
18229 | ||
18230 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18231 | regno = micromips_to_32_reg_d_map [regno]; | |
18232 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18233 | insn |= regno << MICROMIPSOP_SH_RS; | |
18234 | } | |
18235 | else | |
18236 | abort (); | |
18237 | ||
18238 | /* Nothing else to do, just write it out. */ | |
18239 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18240 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18241 | { | |
4d68580a RS |
18242 | buf = write_compressed_insn (buf, insn, 4); |
18243 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18244 | return; |
18245 | } | |
18246 | } | |
18247 | else | |
4d68580a | 18248 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18249 | |
18250 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18251 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18252 | _("Relaxed out-of-range branch into a jump")); | |
18253 | ||
2309ddf2 MR |
18254 | /* Set the short-delay-slot bit. */ |
18255 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18256 | |
18257 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18258 | { | |
18259 | symbolS *l; | |
18260 | ||
18261 | /* Reverse the branch. */ | |
18262 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18263 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18264 | insn ^= 0x20000000; | |
18265 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18266 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18267 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18268 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18269 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18270 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18271 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18272 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18273 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18274 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18275 | insn ^= 0x00400000; | |
18276 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18277 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18278 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18279 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18280 | insn ^= 0x00200000; | |
18281 | else | |
18282 | abort (); | |
18283 | ||
18284 | if (al) | |
18285 | { | |
18286 | /* Clear the and-link and short-delay-slot bits. */ | |
18287 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18288 | ||
18289 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18290 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18291 | insn &= ~0x02200000; | |
18292 | } | |
18293 | ||
18294 | /* Make a label at the end for use with the branch. */ | |
18295 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18296 | micromips_label_inc (); | |
18297 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18298 | if (IS_ELF) | |
18299 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18300 | #endif | |
18301 | ||
18302 | /* Refer to it. */ | |
4d68580a RS |
18303 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18304 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18305 | fixp->fx_file = fragp->fr_file; |
18306 | fixp->fx_line = fragp->fr_line; | |
18307 | ||
18308 | /* Branch over the jump. */ | |
4d68580a | 18309 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18310 | if (!compact) |
4d68580a RS |
18311 | /* nop */ |
18312 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18313 | } |
18314 | ||
18315 | if (mips_pic == NO_PIC) | |
18316 | { | |
2309ddf2 MR |
18317 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18318 | ||
df58fc94 RS |
18319 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18320 | insn = al ? jal : 0xd4000000; | |
18321 | ||
4d68580a RS |
18322 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18323 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18324 | fixp->fx_file = fragp->fr_file; |
18325 | fixp->fx_line = fragp->fr_line; | |
18326 | ||
4d68580a | 18327 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18328 | if (compact) |
4d68580a RS |
18329 | /* nop */ |
18330 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18331 | } |
18332 | else | |
18333 | { | |
18334 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18335 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18336 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18337 | |
18338 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18339 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18340 | insn |= at << MICROMIPSOP_SH_RT; | |
18341 | ||
18342 | if (exp.X_add_number) | |
18343 | { | |
18344 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18345 | exp.X_add_number = 0; | |
18346 | } | |
18347 | ||
4d68580a RS |
18348 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18349 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18350 | fixp->fx_file = fragp->fr_file; |
18351 | fixp->fx_line = fragp->fr_line; | |
18352 | ||
4d68580a | 18353 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18354 | |
18355 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18356 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18357 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18358 | ||
4d68580a RS |
18359 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18360 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18361 | fixp->fx_file = fragp->fr_file; |
18362 | fixp->fx_line = fragp->fr_line; | |
18363 | ||
4d68580a | 18364 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18365 | |
18366 | /* jr/jrc/jalr/jalrs $at */ | |
18367 | insn = al ? jalr : jr; | |
18368 | insn |= at << MICROMIPSOP_SH_MJ; | |
18369 | ||
4d68580a | 18370 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18371 | } |
18372 | ||
4d68580a | 18373 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18374 | return; |
18375 | } | |
18376 | ||
252b5132 RH |
18377 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18378 | { | |
18379 | int type; | |
3994f87e | 18380 | const struct mips16_immed_operand *op; |
252b5132 | 18381 | offsetT val; |
5c04167a RS |
18382 | char *buf; |
18383 | unsigned int user_length, length; | |
252b5132 | 18384 | unsigned long insn; |
5c04167a | 18385 | bfd_boolean ext; |
252b5132 RH |
18386 | |
18387 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18388 | op = mips16_immed_operands; | |
18389 | while (op->type != type) | |
18390 | ++op; | |
18391 | ||
5c04167a | 18392 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18393 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18394 | if (op->pcrel) |
18395 | { | |
18396 | addressT addr; | |
18397 | ||
18398 | addr = fragp->fr_address + fragp->fr_fix; | |
18399 | ||
18400 | /* The rules for the base address of a PC relative reloc are | |
18401 | complicated; see mips16_extended_frag. */ | |
18402 | if (type == 'p' || type == 'q') | |
18403 | { | |
18404 | addr += 2; | |
18405 | if (ext) | |
18406 | addr += 2; | |
18407 | /* Ignore the low bit in the target, since it will be | |
18408 | set for a text label. */ | |
18409 | if ((val & 1) != 0) | |
18410 | --val; | |
18411 | } | |
18412 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18413 | addr -= 4; | |
18414 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18415 | addr -= 2; | |
18416 | ||
18417 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18418 | val -= addr; | |
18419 | ||
18420 | /* Make sure the section winds up with the alignment we have | |
18421 | assumed. */ | |
18422 | if (op->shift > 0) | |
18423 | record_alignment (asec, op->shift); | |
18424 | } | |
18425 | ||
18426 | if (ext | |
18427 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18428 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18429 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18430 | _("extended instruction in delay slot")); | |
18431 | ||
5c04167a | 18432 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18433 | |
4d68580a | 18434 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18435 | if (ext) |
18436 | insn |= MIPS16_EXTEND; | |
252b5132 | 18437 | |
5c04167a RS |
18438 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18439 | user_length = 4; | |
18440 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18441 | user_length = 2; | |
18442 | else | |
18443 | user_length = 0; | |
18444 | ||
43c0598f | 18445 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18446 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18447 | |
5c04167a RS |
18448 | length = (ext ? 4 : 2); |
18449 | gas_assert (mips16_opcode_length (insn) == length); | |
18450 | write_compressed_insn (buf, insn, length); | |
18451 | fragp->fr_fix += length; | |
252b5132 RH |
18452 | } |
18453 | else | |
18454 | { | |
df58fc94 RS |
18455 | relax_substateT subtype = fragp->fr_subtype; |
18456 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18457 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18458 | int first, second; |
18459 | fixS *fixp; | |
252b5132 | 18460 | |
df58fc94 RS |
18461 | first = RELAX_FIRST (subtype); |
18462 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18463 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18464 | |
df58fc94 RS |
18465 | /* If the delay slot chosen does not match the size of the instruction, |
18466 | then emit a warning. */ | |
18467 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18468 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18469 | { | |
18470 | relax_substateT s; | |
18471 | const char *msg; | |
18472 | ||
18473 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18474 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18475 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18476 | msg = macro_warning (s); | |
18477 | if (msg != NULL) | |
db9b2be4 | 18478 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18479 | subtype &= ~s; |
18480 | } | |
18481 | ||
584892a6 | 18482 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18483 | if (use_second == second_longer) |
584892a6 | 18484 | { |
df58fc94 RS |
18485 | relax_substateT s; |
18486 | const char *msg; | |
18487 | ||
18488 | s = (subtype | |
18489 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18490 | msg = macro_warning (s); | |
18491 | if (msg != NULL) | |
db9b2be4 | 18492 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18493 | subtype &= ~s; |
584892a6 RS |
18494 | } |
18495 | ||
4d7206a2 RS |
18496 | /* Go through all the fixups for the first sequence. Disable them |
18497 | (by marking them as done) if we're going to use the second | |
18498 | sequence instead. */ | |
18499 | while (fixp | |
18500 | && fixp->fx_frag == fragp | |
18501 | && fixp->fx_where < fragp->fr_fix - second) | |
18502 | { | |
df58fc94 | 18503 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18504 | fixp->fx_done = 1; |
18505 | fixp = fixp->fx_next; | |
18506 | } | |
252b5132 | 18507 | |
4d7206a2 RS |
18508 | /* Go through the fixups for the second sequence. Disable them if |
18509 | we're going to use the first sequence, otherwise adjust their | |
18510 | addresses to account for the relaxation. */ | |
18511 | while (fixp && fixp->fx_frag == fragp) | |
18512 | { | |
df58fc94 | 18513 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18514 | fixp->fx_where -= first; |
18515 | else | |
18516 | fixp->fx_done = 1; | |
18517 | fixp = fixp->fx_next; | |
18518 | } | |
18519 | ||
18520 | /* Now modify the frag contents. */ | |
df58fc94 | 18521 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18522 | { |
18523 | char *start; | |
18524 | ||
18525 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18526 | memmove (start, start + first, second); | |
18527 | fragp->fr_fix -= first; | |
18528 | } | |
18529 | else | |
18530 | fragp->fr_fix -= second; | |
252b5132 RH |
18531 | } |
18532 | } | |
18533 | ||
18534 | #ifdef OBJ_ELF | |
18535 | ||
18536 | /* This function is called after the relocs have been generated. | |
18537 | We've been storing mips16 text labels as odd. Here we convert them | |
18538 | back to even for the convenience of the debugger. */ | |
18539 | ||
18540 | void | |
17a2f251 | 18541 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18542 | { |
18543 | asymbol **syms; | |
18544 | unsigned int count, i; | |
18545 | ||
f43abd2b | 18546 | if (!IS_ELF) |
252b5132 RH |
18547 | return; |
18548 | ||
18549 | syms = bfd_get_outsymbols (stdoutput); | |
18550 | count = bfd_get_symcount (stdoutput); | |
18551 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18552 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18553 | && ((*syms)->value & 1) != 0) | |
18554 | { | |
18555 | (*syms)->value &= ~1; | |
18556 | /* If the symbol has an odd size, it was probably computed | |
18557 | incorrectly, so adjust that as well. */ | |
18558 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18559 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18560 | } | |
252b5132 RH |
18561 | } |
18562 | ||
18563 | #endif | |
18564 | ||
a1facbec MR |
18565 | /* This function is called whenever a label is defined, including fake |
18566 | labels instantiated off the dot special symbol. It is used when | |
18567 | handling branch delays; if a branch has a label, we assume we cannot | |
18568 | move it. This also bumps the value of the symbol by 1 in compressed | |
18569 | code. */ | |
252b5132 | 18570 | |
e1b47bd5 | 18571 | static void |
a1facbec | 18572 | mips_record_label (symbolS *sym) |
252b5132 | 18573 | { |
a8dbcb85 | 18574 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18575 | struct insn_label_list *l; |
18576 | ||
18577 | if (free_insn_labels == NULL) | |
18578 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18579 | else | |
18580 | { | |
18581 | l = free_insn_labels; | |
18582 | free_insn_labels = l->next; | |
18583 | } | |
18584 | ||
18585 | l->label = sym; | |
a8dbcb85 TS |
18586 | l->next = si->label_list; |
18587 | si->label_list = l; | |
a1facbec | 18588 | } |
07a53e5c | 18589 | |
a1facbec MR |
18590 | /* This function is called as tc_frob_label() whenever a label is defined |
18591 | and adds a DWARF-2 record we only want for true labels. */ | |
18592 | ||
18593 | void | |
18594 | mips_define_label (symbolS *sym) | |
18595 | { | |
18596 | mips_record_label (sym); | |
07a53e5c RH |
18597 | #ifdef OBJ_ELF |
18598 | dwarf2_emit_label (sym); | |
18599 | #endif | |
252b5132 | 18600 | } |
e1b47bd5 RS |
18601 | |
18602 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18603 | is defined. */ | |
18604 | ||
18605 | void | |
18606 | mips_add_dot_label (symbolS *sym) | |
18607 | { | |
18608 | mips_record_label (sym); | |
18609 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18610 | mips_compressed_mark_label (sym); | |
18611 | } | |
252b5132 RH |
18612 | \f |
18613 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18614 | ||
18615 | /* Some special processing for a MIPS ELF file. */ | |
18616 | ||
18617 | void | |
17a2f251 | 18618 | mips_elf_final_processing (void) |
252b5132 RH |
18619 | { |
18620 | /* Write out the register information. */ | |
316f5878 | 18621 | if (mips_abi != N64_ABI) |
252b5132 RH |
18622 | { |
18623 | Elf32_RegInfo s; | |
18624 | ||
18625 | s.ri_gprmask = mips_gprmask; | |
18626 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18627 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18628 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18629 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18630 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18631 | ||
18632 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18633 | ((Elf32_External_RegInfo *) | |
18634 | mips_regmask_frag)); | |
18635 | } | |
18636 | else | |
18637 | { | |
18638 | Elf64_Internal_RegInfo s; | |
18639 | ||
18640 | s.ri_gprmask = mips_gprmask; | |
18641 | s.ri_pad = 0; | |
18642 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18643 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18644 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18645 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18646 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18647 | ||
18648 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18649 | ((Elf64_External_RegInfo *) | |
18650 | mips_regmask_frag)); | |
18651 | } | |
18652 | ||
18653 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18654 | sort of BFD interface for this. */ | |
18655 | if (mips_any_noreorder) | |
18656 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18657 | if (mips_pic != NO_PIC) | |
143d77c5 | 18658 | { |
8b828383 | 18659 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18660 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18661 | } | |
18662 | if (mips_abicalls) | |
18663 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18664 | |
98d3f06f | 18665 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18666 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18667 | file_ase_dsp is true. */ | |
8b082fb1 | 18668 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18669 | /* We may need to define a new flag for MT ASE, and set this flag when |
18670 | file_ase_mt is true. */ | |
a4672219 TS |
18671 | if (file_ase_mips16) |
18672 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18673 | if (file_ase_micromips) |
18674 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18675 | #if 0 /* XXX FIXME */ |
18676 | if (file_ase_mips3d) | |
18677 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18678 | #endif | |
deec1734 CD |
18679 | if (file_ase_mdmx) |
18680 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18681 | |
bdaaa2e1 | 18682 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18683 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18684 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18685 | else if (mips_abi == O64_ABI) |
252b5132 | 18686 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18687 | else if (mips_abi == EABI_ABI) |
252b5132 | 18688 | { |
316f5878 | 18689 | if (!file_mips_gp32) |
252b5132 RH |
18690 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18691 | else | |
18692 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18693 | } | |
316f5878 | 18694 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18695 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18696 | ||
c9914766 | 18697 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18698 | |
18699 | if (mips_32bitmode) | |
18700 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18701 | |
18702 | #if 0 /* XXX FIXME */ | |
18703 | /* 32 bit code with 64 bit FP registers. */ | |
18704 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18705 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18706 | #endif | |
252b5132 RH |
18707 | } |
18708 | ||
18709 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18710 | \f | |
beae10d5 | 18711 | typedef struct proc { |
9b2f1d35 EC |
18712 | symbolS *func_sym; |
18713 | symbolS *func_end_sym; | |
beae10d5 KH |
18714 | unsigned long reg_mask; |
18715 | unsigned long reg_offset; | |
18716 | unsigned long fpreg_mask; | |
18717 | unsigned long fpreg_offset; | |
18718 | unsigned long frame_offset; | |
18719 | unsigned long frame_reg; | |
18720 | unsigned long pc_reg; | |
18721 | } procS; | |
252b5132 RH |
18722 | |
18723 | static procS cur_proc; | |
18724 | static procS *cur_proc_ptr; | |
18725 | static int numprocs; | |
18726 | ||
df58fc94 RS |
18727 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18728 | as "2", and a normal nop as "0". */ | |
18729 | ||
18730 | #define NOP_OPCODE_MIPS 0 | |
18731 | #define NOP_OPCODE_MIPS16 1 | |
18732 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18733 | |
18734 | char | |
18735 | mips_nop_opcode (void) | |
18736 | { | |
df58fc94 RS |
18737 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18738 | return NOP_OPCODE_MICROMIPS; | |
18739 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18740 | return NOP_OPCODE_MIPS16; | |
18741 | else | |
18742 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18743 | } |
18744 | ||
df58fc94 RS |
18745 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18746 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18747 | |
0a9ef439 | 18748 | void |
17a2f251 | 18749 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18750 | { |
df58fc94 | 18751 | char nop_opcode; |
742a56fe | 18752 | char *p; |
c67a084a NC |
18753 | int bytes, size, excess; |
18754 | valueT opcode; | |
742a56fe | 18755 | |
0a9ef439 RH |
18756 | if (fragp->fr_type != rs_align_code) |
18757 | return; | |
18758 | ||
742a56fe | 18759 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18760 | nop_opcode = *p; |
18761 | switch (nop_opcode) | |
a19d8eb0 | 18762 | { |
df58fc94 RS |
18763 | case NOP_OPCODE_MICROMIPS: |
18764 | opcode = micromips_nop32_insn.insn_opcode; | |
18765 | size = 4; | |
18766 | break; | |
18767 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18768 | opcode = mips16_nop_insn.insn_opcode; |
18769 | size = 2; | |
df58fc94 RS |
18770 | break; |
18771 | case NOP_OPCODE_MIPS: | |
18772 | default: | |
c67a084a NC |
18773 | opcode = nop_insn.insn_opcode; |
18774 | size = 4; | |
df58fc94 | 18775 | break; |
c67a084a | 18776 | } |
a19d8eb0 | 18777 | |
c67a084a NC |
18778 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18779 | excess = bytes % size; | |
df58fc94 RS |
18780 | |
18781 | /* Handle the leading part if we're not inserting a whole number of | |
18782 | instructions, and make it the end of the fixed part of the frag. | |
18783 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18784 | and use zeroes otherwise. */ | |
18785 | gas_assert (excess < 4); | |
18786 | fragp->fr_fix += excess; | |
18787 | switch (excess) | |
c67a084a | 18788 | { |
df58fc94 RS |
18789 | case 3: |
18790 | *p++ = '\0'; | |
18791 | /* Fall through. */ | |
18792 | case 2: | |
18793 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18794 | { | |
4d68580a | 18795 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18796 | break; |
18797 | } | |
18798 | *p++ = '\0'; | |
18799 | /* Fall through. */ | |
18800 | case 1: | |
18801 | *p++ = '\0'; | |
18802 | /* Fall through. */ | |
18803 | case 0: | |
18804 | break; | |
a19d8eb0 | 18805 | } |
c67a084a NC |
18806 | |
18807 | md_number_to_chars (p, opcode, size); | |
18808 | fragp->fr_var = size; | |
a19d8eb0 CP |
18809 | } |
18810 | ||
252b5132 | 18811 | static void |
17a2f251 | 18812 | md_obj_begin (void) |
252b5132 RH |
18813 | { |
18814 | } | |
18815 | ||
18816 | static void | |
17a2f251 | 18817 | md_obj_end (void) |
252b5132 | 18818 | { |
54f4ddb3 | 18819 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18820 | if (cur_proc_ptr) |
9a41af64 | 18821 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18822 | } |
18823 | ||
18824 | static long | |
17a2f251 | 18825 | get_number (void) |
252b5132 RH |
18826 | { |
18827 | int negative = 0; | |
18828 | long val = 0; | |
18829 | ||
18830 | if (*input_line_pointer == '-') | |
18831 | { | |
18832 | ++input_line_pointer; | |
18833 | negative = 1; | |
18834 | } | |
3882b010 | 18835 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18836 | as_bad (_("expected simple number")); |
252b5132 RH |
18837 | if (input_line_pointer[0] == '0') |
18838 | { | |
18839 | if (input_line_pointer[1] == 'x') | |
18840 | { | |
18841 | input_line_pointer += 2; | |
3882b010 | 18842 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18843 | { |
18844 | val <<= 4; | |
18845 | val |= hex_value (*input_line_pointer++); | |
18846 | } | |
18847 | return negative ? -val : val; | |
18848 | } | |
18849 | else | |
18850 | { | |
18851 | ++input_line_pointer; | |
3882b010 | 18852 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18853 | { |
18854 | val <<= 3; | |
18855 | val |= *input_line_pointer++ - '0'; | |
18856 | } | |
18857 | return negative ? -val : val; | |
18858 | } | |
18859 | } | |
3882b010 | 18860 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18861 | { |
18862 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18863 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18864 | as_warn (_("invalid number")); |
252b5132 RH |
18865 | return -1; |
18866 | } | |
3882b010 | 18867 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18868 | { |
18869 | val *= 10; | |
18870 | val += *input_line_pointer++ - '0'; | |
18871 | } | |
18872 | return negative ? -val : val; | |
18873 | } | |
18874 | ||
18875 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18876 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18877 | case .file implies DWARF-2. */ | |
18878 | ||
18879 | static void | |
17a2f251 | 18880 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18881 | { |
ecb4347a DJ |
18882 | static int first_file_directive = 0; |
18883 | ||
c5dd6aab DJ |
18884 | if (ECOFF_DEBUGGING) |
18885 | { | |
18886 | get_number (); | |
18887 | s_app_file (0); | |
18888 | } | |
18889 | else | |
ecb4347a DJ |
18890 | { |
18891 | char *filename; | |
18892 | ||
18893 | filename = dwarf2_directive_file (0); | |
18894 | ||
18895 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18896 | directive even for stabs output. Make sure that this | |
18897 | ".file" is handled. Note that you need a version of GCC | |
18898 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18899 | if (filename != NULL && ! first_file_directive) | |
18900 | { | |
18901 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18902 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18903 | } |
18904 | first_file_directive = 1; | |
18905 | } | |
c5dd6aab DJ |
18906 | } |
18907 | ||
18908 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18909 | |
18910 | static void | |
17a2f251 | 18911 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18912 | { |
c5dd6aab DJ |
18913 | if (!ECOFF_DEBUGGING) |
18914 | dwarf2_directive_loc (0); | |
252b5132 RH |
18915 | } |
18916 | ||
252b5132 RH |
18917 | /* The .end directive. */ |
18918 | ||
18919 | static void | |
17a2f251 | 18920 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18921 | { |
18922 | symbolS *p; | |
252b5132 | 18923 | |
7a621144 DJ |
18924 | /* Following functions need their own .frame and .cprestore directives. */ |
18925 | mips_frame_reg_valid = 0; | |
18926 | mips_cprestore_valid = 0; | |
18927 | ||
252b5132 RH |
18928 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18929 | { | |
18930 | p = get_symbol (); | |
18931 | demand_empty_rest_of_line (); | |
18932 | } | |
18933 | else | |
18934 | p = NULL; | |
18935 | ||
14949570 | 18936 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18937 | as_warn (_(".end not in text section")); |
18938 | ||
18939 | if (!cur_proc_ptr) | |
18940 | { | |
18941 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18942 | demand_empty_rest_of_line (); | |
18943 | return; | |
18944 | } | |
18945 | ||
18946 | if (p != NULL) | |
18947 | { | |
9c2799c2 | 18948 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18949 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18950 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18951 | |
18952 | if (debug_type == DEBUG_STABS) | |
18953 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18954 | S_GET_NAME (p)); | |
252b5132 RH |
18955 | } |
18956 | else | |
18957 | as_warn (_(".end directive missing or unknown symbol")); | |
18958 | ||
2132e3a3 | 18959 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18960 | /* Create an expression to calculate the size of the function. */ |
18961 | if (p && cur_proc_ptr) | |
18962 | { | |
18963 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18964 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18965 | ||
18966 | obj->size = exp; | |
18967 | exp->X_op = O_subtract; | |
18968 | exp->X_add_symbol = symbol_temp_new_now (); | |
18969 | exp->X_op_symbol = p; | |
18970 | exp->X_add_number = 0; | |
18971 | ||
18972 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18973 | } | |
18974 | ||
ecb4347a | 18975 | /* Generate a .pdr section. */ |
f43abd2b | 18976 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18977 | { |
18978 | segT saved_seg = now_seg; | |
18979 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18980 | expressionS exp; |
18981 | char *fragp; | |
252b5132 | 18982 | |
252b5132 | 18983 | #ifdef md_flush_pending_output |
ecb4347a | 18984 | md_flush_pending_output (); |
252b5132 RH |
18985 | #endif |
18986 | ||
9c2799c2 | 18987 | gas_assert (pdr_seg); |
ecb4347a | 18988 | subseg_set (pdr_seg, 0); |
252b5132 | 18989 | |
ecb4347a DJ |
18990 | /* Write the symbol. */ |
18991 | exp.X_op = O_symbol; | |
18992 | exp.X_add_symbol = p; | |
18993 | exp.X_add_number = 0; | |
18994 | emit_expr (&exp, 4); | |
252b5132 | 18995 | |
ecb4347a | 18996 | fragp = frag_more (7 * 4); |
252b5132 | 18997 | |
17a2f251 TS |
18998 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18999 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19000 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19001 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19002 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19003 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19004 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19005 | |
ecb4347a DJ |
19006 | subseg_set (saved_seg, saved_subseg); |
19007 | } | |
19008 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19009 | |
19010 | cur_proc_ptr = NULL; | |
19011 | } | |
19012 | ||
19013 | /* The .aent and .ent directives. */ | |
19014 | ||
19015 | static void | |
17a2f251 | 19016 | s_mips_ent (int aent) |
252b5132 | 19017 | { |
252b5132 | 19018 | symbolS *symbolP; |
252b5132 RH |
19019 | |
19020 | symbolP = get_symbol (); | |
19021 | if (*input_line_pointer == ',') | |
f9419b05 | 19022 | ++input_line_pointer; |
252b5132 | 19023 | SKIP_WHITESPACE (); |
3882b010 | 19024 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19025 | || *input_line_pointer == '-') |
874e8986 | 19026 | get_number (); |
252b5132 | 19027 | |
14949570 | 19028 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19029 | as_warn (_(".ent or .aent not in text section.")); |
19030 | ||
19031 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19032 | as_warn (_("missing .end")); |
252b5132 RH |
19033 | |
19034 | if (!aent) | |
19035 | { | |
7a621144 DJ |
19036 | /* This function needs its own .frame and .cprestore directives. */ |
19037 | mips_frame_reg_valid = 0; | |
19038 | mips_cprestore_valid = 0; | |
19039 | ||
252b5132 RH |
19040 | cur_proc_ptr = &cur_proc; |
19041 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19042 | ||
9b2f1d35 | 19043 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19044 | |
f9419b05 | 19045 | ++numprocs; |
ecb4347a DJ |
19046 | |
19047 | if (debug_type == DEBUG_STABS) | |
19048 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19049 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19050 | } |
19051 | ||
7c0fc524 MR |
19052 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19053 | ||
252b5132 RH |
19054 | demand_empty_rest_of_line (); |
19055 | } | |
19056 | ||
19057 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19058 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19059 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19060 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19061 | symbol table (in the mdebug section). */ |
19062 | ||
19063 | static void | |
17a2f251 | 19064 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19065 | { |
ecb4347a | 19066 | #ifdef OBJ_ELF |
f43abd2b | 19067 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19068 | { |
19069 | long val; | |
252b5132 | 19070 | |
ecb4347a DJ |
19071 | if (cur_proc_ptr == (procS *) NULL) |
19072 | { | |
19073 | as_warn (_(".frame outside of .ent")); | |
19074 | demand_empty_rest_of_line (); | |
19075 | return; | |
19076 | } | |
252b5132 | 19077 | |
ecb4347a DJ |
19078 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19079 | ||
19080 | SKIP_WHITESPACE (); | |
19081 | if (*input_line_pointer++ != ',' | |
19082 | || get_absolute_expression_and_terminator (&val) != ',') | |
19083 | { | |
19084 | as_warn (_("Bad .frame directive")); | |
19085 | --input_line_pointer; | |
19086 | demand_empty_rest_of_line (); | |
19087 | return; | |
19088 | } | |
252b5132 | 19089 | |
ecb4347a DJ |
19090 | cur_proc_ptr->frame_offset = val; |
19091 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19092 | |
252b5132 | 19093 | demand_empty_rest_of_line (); |
252b5132 | 19094 | } |
ecb4347a DJ |
19095 | else |
19096 | #endif /* OBJ_ELF */ | |
19097 | s_ignore (ignore); | |
252b5132 RH |
19098 | } |
19099 | ||
bdaaa2e1 KH |
19100 | /* The .fmask and .mask directives. If the mdebug section is present |
19101 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19102 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19103 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19104 | make reference to the ecoff symbol table (in the mdebug section). */ |
19105 | ||
19106 | static void | |
17a2f251 | 19107 | s_mips_mask (int reg_type) |
252b5132 | 19108 | { |
ecb4347a | 19109 | #ifdef OBJ_ELF |
f43abd2b | 19110 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19111 | { |
ecb4347a | 19112 | long mask, off; |
252b5132 | 19113 | |
ecb4347a DJ |
19114 | if (cur_proc_ptr == (procS *) NULL) |
19115 | { | |
19116 | as_warn (_(".mask/.fmask outside of .ent")); | |
19117 | demand_empty_rest_of_line (); | |
19118 | return; | |
19119 | } | |
252b5132 | 19120 | |
ecb4347a DJ |
19121 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19122 | { | |
19123 | as_warn (_("Bad .mask/.fmask directive")); | |
19124 | --input_line_pointer; | |
19125 | demand_empty_rest_of_line (); | |
19126 | return; | |
19127 | } | |
252b5132 | 19128 | |
ecb4347a DJ |
19129 | off = get_absolute_expression (); |
19130 | ||
19131 | if (reg_type == 'F') | |
19132 | { | |
19133 | cur_proc_ptr->fpreg_mask = mask; | |
19134 | cur_proc_ptr->fpreg_offset = off; | |
19135 | } | |
19136 | else | |
19137 | { | |
19138 | cur_proc_ptr->reg_mask = mask; | |
19139 | cur_proc_ptr->reg_offset = off; | |
19140 | } | |
19141 | ||
19142 | demand_empty_rest_of_line (); | |
252b5132 RH |
19143 | } |
19144 | else | |
ecb4347a DJ |
19145 | #endif /* OBJ_ELF */ |
19146 | s_ignore (reg_type); | |
252b5132 RH |
19147 | } |
19148 | ||
316f5878 RS |
19149 | /* A table describing all the processors gas knows about. Names are |
19150 | matched in the order listed. | |
e7af610e | 19151 | |
316f5878 RS |
19152 | To ease comparison, please keep this table in the same order as |
19153 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19154 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19155 | { | |
316f5878 | 19156 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19157 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19158 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19159 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19160 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19161 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19162 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19163 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19164 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19165 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19166 | |
19167 | /* MIPS I */ | |
ad3fea08 TS |
19168 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19169 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19170 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19171 | |
19172 | /* MIPS II */ | |
ad3fea08 | 19173 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19174 | |
19175 | /* MIPS III */ | |
ad3fea08 TS |
19176 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19177 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19178 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19179 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19180 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19181 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19182 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19183 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19184 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19185 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19186 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19187 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
e407c74b | 19188 | { "r5900", 0, ISA_MIPS3, CPU_R5900 }, |
b15591bb AN |
19189 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19190 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19191 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19192 | |
19193 | /* MIPS IV */ | |
ad3fea08 TS |
19194 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19195 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19196 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19197 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19198 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19199 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19200 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19201 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19202 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19203 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19204 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19205 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19206 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19207 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19208 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19209 | |
19210 | /* MIPS 32 */ | |
ad3fea08 TS |
19211 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19212 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19213 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19214 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19215 | ||
19216 | /* MIPS 32 Release 2 */ | |
19217 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19218 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19219 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19220 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19221 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19222 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19223 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19224 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19225 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19226 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19227 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19228 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19229 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19230 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19231 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19232 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19233 | /* Deprecated forms of the above. */ | |
19234 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19235 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19236 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19237 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19238 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19239 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19240 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19241 | /* Deprecated forms of the above. */ | |
19242 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19243 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19244 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19245 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19246 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19247 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19248 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19249 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19250 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19251 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19252 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19253 | /* Deprecated forms of the above. */ | |
19254 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19255 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19256 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19257 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19258 | /* 34Kn is a 34kc without DSP. */ |
19259 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19260 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19261 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19262 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19263 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19264 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19265 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19266 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19267 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19268 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19269 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19270 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19271 | /* Deprecated forms of the above. */ | |
19272 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19273 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19274 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19275 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19276 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19277 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19278 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19279 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19280 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19281 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19282 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19283 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19284 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19285 | |
316f5878 | 19286 | /* MIPS 64 */ |
ad3fea08 TS |
19287 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19288 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19289 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19290 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19291 | |
c7a23324 | 19292 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19293 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19294 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19295 | /* Broadcom SB-1A CPU core */ |
19296 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19297 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19298 | |
19299 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19300 | |
ed163775 MR |
19301 | /* MIPS 64 Release 2 */ |
19302 | ||
967344c6 AN |
19303 | /* Cavium Networks Octeon CPU core */ |
19304 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19305 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19306 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19307 | |
52b6b6b9 JM |
19308 | /* RMI Xlr */ |
19309 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19310 | ||
55a36193 MK |
19311 | /* Broadcom XLP. |
19312 | XLP is mostly like XLR, with the prominent exception that it is | |
19313 | MIPS64R2 rather than MIPS64. */ | |
19314 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19315 | ||
316f5878 RS |
19316 | /* End marker */ |
19317 | { NULL, 0, 0, 0 } | |
19318 | }; | |
e7af610e | 19319 | |
84ea6cf2 | 19320 | |
316f5878 RS |
19321 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19322 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19323 | |
316f5878 | 19324 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19325 | |
b34976b6 | 19326 | static bfd_boolean |
17a2f251 | 19327 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19328 | { |
19329 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19330 | given++, canonical++; | |
19331 | ||
19332 | return ((*given == 0 && *canonical == 0) | |
19333 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19334 | } | |
19335 | ||
19336 | ||
19337 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19338 | CPU name. We've traditionally allowed a lot of variation here. | |
19339 | ||
19340 | Note: this function is shared between GCC and GAS. */ | |
19341 | ||
b34976b6 | 19342 | static bfd_boolean |
17a2f251 | 19343 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19344 | { |
19345 | /* First see if the name matches exactly, or with a final "000" | |
19346 | turned into "k". */ | |
19347 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19348 | return TRUE; |
316f5878 RS |
19349 | |
19350 | /* If not, try comparing based on numerical designation alone. | |
19351 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19352 | if (TOLOWER (*given) == 'r') | |
19353 | given++; | |
19354 | if (!ISDIGIT (*given)) | |
b34976b6 | 19355 | return FALSE; |
316f5878 RS |
19356 | |
19357 | /* Skip over some well-known prefixes in the canonical name, | |
19358 | hoping to find a number there too. */ | |
19359 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19360 | canonical += 2; | |
19361 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19362 | canonical += 2; | |
19363 | else if (TOLOWER (canonical[0]) == 'r') | |
19364 | canonical += 1; | |
19365 | ||
19366 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19367 | } | |
19368 | ||
19369 | ||
19370 | /* Parse an option that takes the name of a processor as its argument. | |
19371 | OPTION is the name of the option and CPU_STRING is the argument. | |
19372 | Return the corresponding processor enumeration if the CPU_STRING is | |
19373 | recognized, otherwise report an error and return null. | |
19374 | ||
19375 | A similar function exists in GCC. */ | |
e7af610e NC |
19376 | |
19377 | static const struct mips_cpu_info * | |
17a2f251 | 19378 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19379 | { |
316f5878 | 19380 | const struct mips_cpu_info *p; |
e7af610e | 19381 | |
316f5878 RS |
19382 | /* 'from-abi' selects the most compatible architecture for the given |
19383 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19384 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19385 | version. Look first at the -mgp options, if given, otherwise base | |
19386 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19387 | |
316f5878 RS |
19388 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19389 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19390 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19391 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19392 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19393 | { | |
19394 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19395 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19396 | ||
19397 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19398 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19399 | ||
19400 | if (file_mips_gp32 >= 0) | |
19401 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19402 | ||
19403 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19404 | ? ISA_MIPS3 | |
19405 | : ISA_MIPS1); | |
19406 | } | |
19407 | ||
19408 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19409 | if (strcasecmp (cpu_string, "default") == 0) | |
19410 | return 0; | |
19411 | ||
19412 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19413 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19414 | return p; | |
19415 | ||
20203fb9 | 19416 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19417 | return 0; |
e7af610e NC |
19418 | } |
19419 | ||
316f5878 RS |
19420 | /* Return the canonical processor information for ISA (a member of the |
19421 | ISA_MIPS* enumeration). */ | |
19422 | ||
e7af610e | 19423 | static const struct mips_cpu_info * |
17a2f251 | 19424 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19425 | { |
19426 | int i; | |
19427 | ||
19428 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19429 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19430 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19431 | return (&mips_cpu_info_table[i]); |
19432 | ||
e972090a | 19433 | return NULL; |
e7af610e | 19434 | } |
fef14a42 TS |
19435 | |
19436 | static const struct mips_cpu_info * | |
17a2f251 | 19437 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19438 | { |
19439 | int i; | |
19440 | ||
19441 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19442 | if (arch == mips_cpu_info_table[i].cpu) | |
19443 | return (&mips_cpu_info_table[i]); | |
19444 | ||
19445 | return NULL; | |
19446 | } | |
316f5878 RS |
19447 | \f |
19448 | static void | |
17a2f251 | 19449 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19450 | { |
19451 | if (*first_p) | |
19452 | { | |
19453 | fprintf (stream, "%24s", ""); | |
19454 | *col_p = 24; | |
19455 | } | |
19456 | else | |
19457 | { | |
19458 | fprintf (stream, ", "); | |
19459 | *col_p += 2; | |
19460 | } | |
e7af610e | 19461 | |
316f5878 RS |
19462 | if (*col_p + strlen (string) > 72) |
19463 | { | |
19464 | fprintf (stream, "\n%24s", ""); | |
19465 | *col_p = 24; | |
19466 | } | |
19467 | ||
19468 | fprintf (stream, "%s", string); | |
19469 | *col_p += strlen (string); | |
19470 | ||
19471 | *first_p = 0; | |
19472 | } | |
19473 | ||
19474 | void | |
17a2f251 | 19475 | md_show_usage (FILE *stream) |
e7af610e | 19476 | { |
316f5878 RS |
19477 | int column, first; |
19478 | size_t i; | |
19479 | ||
19480 | fprintf (stream, _("\ | |
19481 | MIPS options:\n\ | |
316f5878 RS |
19482 | -EB generate big endian output\n\ |
19483 | -EL generate little endian output\n\ | |
19484 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19485 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19486 | implicitly with the gp register [default 8]\n")); | |
19487 | fprintf (stream, _("\ | |
19488 | -mips1 generate MIPS ISA I instructions\n\ | |
19489 | -mips2 generate MIPS ISA II instructions\n\ | |
19490 | -mips3 generate MIPS ISA III instructions\n\ | |
19491 | -mips4 generate MIPS ISA IV instructions\n\ | |
19492 | -mips5 generate MIPS ISA V instructions\n\ | |
19493 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19494 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19495 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19496 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19497 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19498 | ||
19499 | first = 1; | |
e7af610e NC |
19500 | |
19501 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19502 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19503 | show (stream, "from-abi", &column, &first); | |
19504 | fputc ('\n', stream); | |
e7af610e | 19505 | |
316f5878 RS |
19506 | fprintf (stream, _("\ |
19507 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19508 | -no-mCPU don't generate code specific to CPU.\n\ | |
19509 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19510 | ||
19511 | first = 1; | |
19512 | ||
19513 | show (stream, "3900", &column, &first); | |
19514 | show (stream, "4010", &column, &first); | |
19515 | show (stream, "4100", &column, &first); | |
19516 | show (stream, "4650", &column, &first); | |
19517 | fputc ('\n', stream); | |
19518 | ||
19519 | fprintf (stream, _("\ | |
19520 | -mips16 generate mips16 instructions\n\ | |
19521 | -no-mips16 do not generate mips16 instructions\n")); | |
19522 | fprintf (stream, _("\ | |
df58fc94 RS |
19523 | -mmicromips generate microMIPS instructions\n\ |
19524 | -mno-micromips do not generate microMIPS instructions\n")); | |
19525 | fprintf (stream, _("\ | |
e16bfa71 TS |
19526 | -msmartmips generate smartmips instructions\n\ |
19527 | -mno-smartmips do not generate smartmips instructions\n")); | |
19528 | fprintf (stream, _("\ | |
74cd071d CF |
19529 | -mdsp generate DSP instructions\n\ |
19530 | -mno-dsp do not generate DSP instructions\n")); | |
19531 | fprintf (stream, _("\ | |
8b082fb1 TS |
19532 | -mdspr2 generate DSP R2 instructions\n\ |
19533 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19534 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19535 | -mmt generate MT instructions\n\ |
19536 | -mno-mt do not generate MT instructions\n")); | |
19537 | fprintf (stream, _("\ | |
dec0624d MR |
19538 | -mmcu generate MCU instructions\n\ |
19539 | -mno-mcu do not generate MCU instructions\n")); | |
19540 | fprintf (stream, _("\ | |
c67a084a NC |
19541 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19542 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19543 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19544 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19545 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19546 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19547 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19548 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19549 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19550 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19551 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19552 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19553 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19554 | fprintf (stream, _("\ |
19555 | -mhard-float allow floating-point instructions\n\ | |
19556 | -msoft-float do not allow floating-point instructions\n\ | |
19557 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19558 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19559 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19560 | )); | |
316f5878 RS |
19561 | #ifdef OBJ_ELF |
19562 | fprintf (stream, _("\ | |
19563 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19564 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19565 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19566 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19567 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19568 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19569 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19570 | position dependent (non shared) code\n\ |
316f5878 RS |
19571 | -mabi=ABI create ABI conformant object file for:\n")); |
19572 | ||
19573 | first = 1; | |
19574 | ||
19575 | show (stream, "32", &column, &first); | |
19576 | show (stream, "o64", &column, &first); | |
19577 | show (stream, "n32", &column, &first); | |
19578 | show (stream, "64", &column, &first); | |
19579 | show (stream, "eabi", &column, &first); | |
19580 | ||
19581 | fputc ('\n', stream); | |
19582 | ||
19583 | fprintf (stream, _("\ | |
19584 | -32 create o32 ABI object file (default)\n\ | |
19585 | -n32 create n32 ABI object file\n\ | |
19586 | -64 create 64 ABI object file\n")); | |
19587 | #endif | |
e7af610e | 19588 | } |
14e777e0 | 19589 | |
1575952e | 19590 | #ifdef TE_IRIX |
14e777e0 | 19591 | enum dwarf2_format |
413a266c | 19592 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19593 | { |
369943fe | 19594 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19595 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19596 | else |
19597 | return dwarf2_format_32bit; | |
19598 | } | |
1575952e | 19599 | #endif |
73369e65 EC |
19600 | |
19601 | int | |
19602 | mips_dwarf2_addr_size (void) | |
19603 | { | |
6b6b3450 | 19604 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19605 | return 8; |
73369e65 EC |
19606 | else |
19607 | return 4; | |
19608 | } | |
5862107c EC |
19609 | |
19610 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19611 | void | |
19612 | mips_cfi_frame_initial_instructions (void) | |
19613 | { | |
19614 | cfi_add_CFA_def_cfa_register (SP); | |
19615 | } | |
19616 | ||
707bfff6 TS |
19617 | int |
19618 | tc_mips_regname_to_dw2regnum (char *regname) | |
19619 | { | |
19620 | unsigned int regnum = -1; | |
19621 | unsigned int reg; | |
19622 | ||
19623 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19624 | regnum = reg; | |
19625 | ||
19626 | return regnum; | |
19627 | } |