Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 RH |
113 | /* The name of the readonly data section. */ |
114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
115 | ? ".data" \ | |
116 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
117 | ? ".rdata" \ | |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
a325df1d TS |
124 | /* The ABI to use. */ |
125 | enum mips_abi_level | |
126 | { | |
127 | NO_ABI = 0, | |
128 | O32_ABI, | |
129 | O64_ABI, | |
130 | N32_ABI, | |
131 | N64_ABI, | |
132 | EABI_ABI | |
133 | }; | |
134 | ||
135 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 136 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 137 | |
143d77c5 EC |
138 | /* Whether or not we have code that can call pic code. */ |
139 | int mips_abicalls = FALSE; | |
140 | ||
252b5132 RH |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
e972090a NC |
145 | struct mips_set_options |
146 | { | |
252b5132 RH |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
1f25f5d3 CD |
151 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
152 | if they have not been initialized. Changed by `.set <asename>', by | |
153 | command line options, and based on the default architecture. */ | |
154 | int ase_mips3d; | |
deec1734 | 155 | int ase_mdmx; |
252b5132 RH |
156 | /* Whether we are assembling for the mips16 processor. 0 if we are |
157 | not, 1 if we are, and -1 if the value has not been initialized. | |
158 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
159 | -nomips16 command line options, and the default CPU. */ | |
160 | int mips16; | |
161 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
162 | reorder' and `.set noreorder'. */ | |
163 | int noreorder; | |
164 | /* Non-zero if we should not permit the $at ($1) register to be used | |
165 | in instructions. Changed by `.set at' and `.set noat'. */ | |
166 | int noat; | |
167 | /* Non-zero if we should warn when a macro instruction expands into | |
168 | more than one machine instruction. Changed by `.set nomacro' and | |
169 | `.set macro'. */ | |
170 | int warn_about_macros; | |
171 | /* Non-zero if we should not move instructions. Changed by `.set | |
172 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
173 | int nomove; | |
174 | /* Non-zero if we should not optimize branches by moving the target | |
175 | of the branch into the delay slot. Actually, we don't perform | |
176 | this optimization anyhow. Changed by `.set bopt' and `.set | |
177 | nobopt'. */ | |
178 | int nobopt; | |
179 | /* Non-zero if we should not autoextend mips16 instructions. | |
180 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
181 | int noautoextend; | |
a325df1d TS |
182 | /* Restrict general purpose registers and floating point registers |
183 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
184 | is passed but can changed if the assembler code uses .set mipsN. */ | |
185 | int gp32; | |
186 | int fp32; | |
fef14a42 TS |
187 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
188 | command line option, and the default CPU. */ | |
189 | int arch; | |
252b5132 RH |
190 | }; |
191 | ||
a325df1d | 192 | /* True if -mgp32 was passed. */ |
a8e8e863 | 193 | static int file_mips_gp32 = -1; |
a325df1d TS |
194 | |
195 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 196 | static int file_mips_fp32 = -1; |
a325df1d | 197 | |
252b5132 | 198 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 199 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 200 | -1 to indicate that they have not been initialized. */ |
252b5132 | 201 | |
e972090a NC |
202 | static struct mips_set_options mips_opts = |
203 | { | |
fef14a42 | 204 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 205 | }; |
252b5132 RH |
206 | |
207 | /* These variables are filled in with the masks of registers used. | |
208 | The object format code reads them and puts them in the appropriate | |
209 | place. */ | |
210 | unsigned long mips_gprmask; | |
211 | unsigned long mips_cprmask[4]; | |
212 | ||
213 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 214 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 215 | |
a4672219 TS |
216 | /* True if -mips16 was passed or implied by arguments passed on the |
217 | command line (e.g., by -march). */ | |
218 | static int file_ase_mips16; | |
219 | ||
1f25f5d3 CD |
220 | /* True if -mips3d was passed or implied by arguments passed on the |
221 | command line (e.g., by -march). */ | |
222 | static int file_ase_mips3d; | |
223 | ||
deec1734 CD |
224 | /* True if -mdmx was passed or implied by arguments passed on the |
225 | command line (e.g., by -march). */ | |
226 | static int file_ase_mdmx; | |
227 | ||
ec68c924 | 228 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 229 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 230 | static const char *mips_arch_string; |
ec68c924 EC |
231 | |
232 | /* The argument of the -mtune= flag. The architecture for which we | |
233 | are optimizing. */ | |
234 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 235 | static const char *mips_tune_string; |
ec68c924 | 236 | |
316f5878 | 237 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
238 | static int mips_32bitmode = 0; |
239 | ||
316f5878 RS |
240 | /* True if the given ABI requires 32-bit registers. */ |
241 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
242 | ||
243 | /* Likewise 64-bit registers. */ | |
244 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
245 | ((ABI) == N32_ABI \ | |
246 | || (ABI) == N64_ABI \ | |
247 | || (ABI) == O64_ABI) | |
248 | ||
bdaaa2e1 | 249 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 250 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
251 | (ISA) == ISA_MIPS3 \ |
252 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 253 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 254 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 255 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
256 | ) |
257 | ||
af7ee8bf CD |
258 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
259 | instructions. */ | |
260 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 261 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
262 | ) |
263 | ||
264 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
265 | instructions. */ | |
266 | #define ISA_HAS_ROR(ISA) ( \ | |
267 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 268 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
269 | ) |
270 | ||
e013f690 | 271 | #define HAVE_32BIT_GPRS \ |
316f5878 | 272 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 273 | |
e013f690 | 274 | #define HAVE_32BIT_FPRS \ |
316f5878 | 275 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
276 | |
277 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
278 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
279 | ||
316f5878 | 280 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 281 | |
316f5878 | 282 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
283 | |
284 | /* We can only have 64bit addresses if the object file format | |
285 | supports it. */ | |
afdbd6d0 CD |
286 | #define HAVE_32BIT_ADDRESSES \ |
287 | (HAVE_32BIT_GPRS \ | |
288 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
289 | || ! HAVE_64BIT_OBJECTS) \ | |
290 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
291 | |
292 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 293 | |
b7c7d6c1 TS |
294 | /* Addresses are loaded in different ways, depending on the address size |
295 | in use. The n32 ABI Documentation also mandates the use of additions | |
296 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 297 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 298 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
299 | |
300 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 301 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
302 | |
303 | #define ADDRESS_LOAD_INSN \ | |
304 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
305 | ||
306 | #define ADDRESS_STORE_INSN \ | |
307 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
308 | ||
a4672219 | 309 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
310 | #define CPU_HAS_MIPS16(cpu) \ |
311 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
312 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 313 | |
1f25f5d3 CD |
314 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
315 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
316 | ) | |
317 | ||
deec1734 | 318 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 319 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
320 | ) |
321 | ||
60b63b72 RS |
322 | /* True if CPU has a dror instruction. */ |
323 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
324 | ||
325 | /* True if CPU has a ror instruction. */ | |
326 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
327 | ||
bdaaa2e1 | 328 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 329 | reads from the HI and LO registers, and thus does not |
ec68c924 | 330 | require nops to be inserted. */ |
252b5132 | 331 | |
fef14a42 TS |
332 | #define hilo_interlocks (mips_opts.arch == CPU_R4010 \ |
333 | || mips_opts.arch == CPU_VR5500 \ | |
5a7ea749 | 334 | || mips_opts.arch == CPU_RM7000 \ |
fef14a42 | 335 | || mips_opts.arch == CPU_SB1 \ |
252b5132 RH |
336 | ) |
337 | ||
338 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
339 | from the GPRs after they are loaded from memory, and thus does not |
340 | require nops to be inserted. This applies to instructions marked | |
341 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
342 | level I. */ | |
252b5132 | 343 | #define gpr_interlocks \ |
e7af610e | 344 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 TS |
345 | || mips_opts.arch == CPU_VR5400 \ |
346 | || mips_opts.arch == CPU_VR5500 \ | |
347 | || mips_opts.arch == CPU_R3900) | |
252b5132 | 348 | |
81912461 ILT |
349 | /* Whether the processor uses hardware interlocks to avoid delays |
350 | required by coprocessor instructions, and thus does not require | |
351 | nops to be inserted. This applies to instructions marked | |
352 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
353 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
354 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
355 | levels I, II, and III. */ | |
bdaaa2e1 | 356 | /* Itbl support may require additional care here. */ |
81912461 ILT |
357 | #define cop_interlocks \ |
358 | ((mips_opts.isa != ISA_MIPS1 \ | |
359 | && mips_opts.isa != ISA_MIPS2 \ | |
360 | && mips_opts.isa != ISA_MIPS3) \ | |
361 | || mips_opts.arch == CPU_R4300 \ | |
362 | || mips_opts.arch == CPU_VR5400 \ | |
363 | || mips_opts.arch == CPU_VR5500 \ | |
364 | || mips_opts.arch == CPU_SB1 \ | |
365 | ) | |
366 | ||
367 | /* Whether the processor uses hardware interlocks to protect reads | |
368 | from coprocessor registers after they are loaded from memory, and | |
369 | thus does not require nops to be inserted. This applies to | |
370 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
371 | requires at MIPS ISA level I. */ | |
372 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 373 | |
6b76fefe CM |
374 | /* Is this a mfhi or mflo instruction? */ |
375 | #define MF_HILO_INSN(PINFO) \ | |
376 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
377 | ||
252b5132 RH |
378 | /* MIPS PIC level. */ |
379 | ||
a161fe53 | 380 | enum mips_pic_level mips_pic; |
252b5132 | 381 | |
c9914766 | 382 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 383 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 384 | static int mips_big_got = 0; |
252b5132 RH |
385 | |
386 | /* 1 if trap instructions should used for overflow rather than break | |
387 | instructions. */ | |
c9914766 | 388 | static int mips_trap = 0; |
252b5132 | 389 | |
119d663a | 390 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 391 | by assembling two single width halves into two single width floating |
119d663a NC |
392 | point registers which just happen to alias the double width destination |
393 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 394 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
395 | automatically at assemble time. */ |
396 | static int mips_disable_float_construction; | |
397 | ||
252b5132 RH |
398 | /* Non-zero if any .set noreorder directives were used. */ |
399 | ||
400 | static int mips_any_noreorder; | |
401 | ||
6b76fefe CM |
402 | /* Non-zero if nops should be inserted when the register referenced in |
403 | an mfhi/mflo instruction is read in the next two instructions. */ | |
404 | static int mips_7000_hilo_fix; | |
405 | ||
252b5132 | 406 | /* The size of the small data section. */ |
156c2f8b | 407 | static unsigned int g_switch_value = 8; |
252b5132 RH |
408 | /* Whether the -G option was used. */ |
409 | static int g_switch_seen = 0; | |
410 | ||
411 | #define N_RMASK 0xc4 | |
412 | #define N_VFP 0xd4 | |
413 | ||
414 | /* If we can determine in advance that GP optimization won't be | |
415 | possible, we can skip the relaxation stuff that tries to produce | |
416 | GP-relative references. This makes delay slot optimization work | |
417 | better. | |
418 | ||
419 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
420 | gcc output. It needs to guess right for gcc, otherwise gcc |
421 | will put what it thinks is a GP-relative instruction in a branch | |
422 | delay slot. | |
252b5132 RH |
423 | |
424 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
425 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 426 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
427 | |
428 | /* handle of the OPCODE hash table */ | |
429 | static struct hash_control *op_hash = NULL; | |
430 | ||
431 | /* The opcode hash table we use for the mips16. */ | |
432 | static struct hash_control *mips16_op_hash = NULL; | |
433 | ||
434 | /* This array holds the chars that always start a comment. If the | |
435 | pre-processor is disabled, these aren't very useful */ | |
436 | const char comment_chars[] = "#"; | |
437 | ||
438 | /* This array holds the chars that only start a comment at the beginning of | |
439 | a line. If the line seems to have the form '# 123 filename' | |
440 | .line and .file directives will appear in the pre-processed output */ | |
441 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
442 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 443 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
444 | /* Also note that C style comments are always supported. */ |
445 | const char line_comment_chars[] = "#"; | |
446 | ||
bdaaa2e1 | 447 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 448 | const char line_separator_chars[] = ";"; |
252b5132 RH |
449 | |
450 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
451 | const char EXP_CHARS[] = "eE"; | |
452 | ||
453 | /* Chars that mean this number is a floating point constant */ | |
454 | /* As in 0f12.456 */ | |
455 | /* or 0d1.2345e12 */ | |
456 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
457 | ||
458 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
459 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
460 | but nothing is ideal around here. | |
461 | */ | |
462 | ||
463 | static char *insn_error; | |
464 | ||
465 | static int auto_align = 1; | |
466 | ||
467 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
468 | offset in the stack frame from which to restore the $gp register. | |
469 | This is set by the .cprestore pseudo-op, and saved in this | |
470 | variable. */ | |
471 | static offsetT mips_cprestore_offset = -1; | |
472 | ||
67c1ffbe | 473 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 474 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 475 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
476 | static offsetT mips_cpreturn_offset = -1; |
477 | static int mips_cpreturn_register = -1; | |
478 | static int mips_gp_register = GP; | |
def2e0dd | 479 | static int mips_gprel_offset = 0; |
6478892d | 480 | |
7a621144 DJ |
481 | /* Whether mips_cprestore_offset has been set in the current function |
482 | (or whether it has already been warned about, if not). */ | |
483 | static int mips_cprestore_valid = 0; | |
484 | ||
252b5132 RH |
485 | /* This is the register which holds the stack frame, as set by the |
486 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
487 | static int mips_frame_reg = SP; | |
488 | ||
7a621144 DJ |
489 | /* Whether mips_frame_reg has been set in the current function |
490 | (or whether it has already been warned about, if not). */ | |
491 | static int mips_frame_reg_valid = 0; | |
492 | ||
252b5132 RH |
493 | /* To output NOP instructions correctly, we need to keep information |
494 | about the previous two instructions. */ | |
495 | ||
496 | /* Whether we are optimizing. The default value of 2 means to remove | |
497 | unneeded NOPs and swap branch instructions when possible. A value | |
498 | of 1 means to not swap branches. A value of 0 means to always | |
499 | insert NOPs. */ | |
500 | static int mips_optimize = 2; | |
501 | ||
502 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
503 | equivalent to seeing no -g option at all. */ | |
504 | static int mips_debug = 0; | |
505 | ||
506 | /* The previous instruction. */ | |
507 | static struct mips_cl_insn prev_insn; | |
508 | ||
509 | /* The instruction before prev_insn. */ | |
510 | static struct mips_cl_insn prev_prev_insn; | |
511 | ||
512 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
513 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 514 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
515 | |
516 | /* Non-zero if prev_insn is valid. */ | |
517 | static int prev_insn_valid; | |
518 | ||
519 | /* The frag for the previous instruction. */ | |
520 | static struct frag *prev_insn_frag; | |
521 | ||
522 | /* The offset into prev_insn_frag for the previous instruction. */ | |
523 | static long prev_insn_where; | |
524 | ||
525 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 526 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
527 | |
528 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 529 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
530 | |
531 | /* Non-zero if the previous instruction was in a delay slot. */ | |
532 | static int prev_insn_is_delay_slot; | |
533 | ||
534 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
535 | static int prev_insn_unreordered; | |
536 | ||
537 | /* Non-zero if the previous instruction uses an extend opcode (if | |
538 | mips16). */ | |
539 | static int prev_insn_extended; | |
540 | ||
541 | /* Non-zero if the previous previous instruction was in a .set | |
542 | noreorder. */ | |
543 | static int prev_prev_insn_unreordered; | |
544 | ||
545 | /* If this is set, it points to a frag holding nop instructions which | |
546 | were inserted before the start of a noreorder section. If those | |
547 | nops turn out to be unnecessary, the size of the frag can be | |
548 | decreased. */ | |
549 | static fragS *prev_nop_frag; | |
550 | ||
551 | /* The number of nop instructions we created in prev_nop_frag. */ | |
552 | static int prev_nop_frag_holds; | |
553 | ||
554 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 555 | prev_nop_frag. */ |
252b5132 RH |
556 | static int prev_nop_frag_required; |
557 | ||
558 | /* The number of instructions we've seen since prev_nop_frag. */ | |
559 | static int prev_nop_frag_since; | |
560 | ||
561 | /* For ECOFF and ELF, relocations against symbols are done in two | |
562 | parts, with a HI relocation and a LO relocation. Each relocation | |
563 | has only 16 bits of space to store an addend. This means that in | |
564 | order for the linker to handle carries correctly, it must be able | |
565 | to locate both the HI and the LO relocation. This means that the | |
566 | relocations must appear in order in the relocation table. | |
567 | ||
568 | In order to implement this, we keep track of each unmatched HI | |
569 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 570 | corresponding LO relocation. */ |
252b5132 | 571 | |
e972090a NC |
572 | struct mips_hi_fixup |
573 | { | |
252b5132 RH |
574 | /* Next HI fixup. */ |
575 | struct mips_hi_fixup *next; | |
576 | /* This fixup. */ | |
577 | fixS *fixp; | |
578 | /* The section this fixup is in. */ | |
579 | segT seg; | |
580 | }; | |
581 | ||
582 | /* The list of unmatched HI relocs. */ | |
583 | ||
584 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
585 | ||
64bdfcaf RS |
586 | /* The frag containing the last explicit relocation operator. |
587 | Null if explicit relocations have not been used. */ | |
588 | ||
589 | static fragS *prev_reloc_op_frag; | |
590 | ||
252b5132 RH |
591 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
592 | ||
593 | #define X ILLEGAL_REG | |
e972090a NC |
594 | static const int mips32_to_16_reg_map[] = |
595 | { | |
252b5132 RH |
596 | X, X, 2, 3, 4, 5, 6, 7, |
597 | X, X, X, X, X, X, X, X, | |
598 | 0, 1, X, X, X, X, X, X, | |
599 | X, X, X, X, X, X, X, X | |
600 | }; | |
601 | #undef X | |
602 | ||
603 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
604 | ||
e972090a NC |
605 | static const unsigned int mips16_to_32_reg_map[] = |
606 | { | |
252b5132 RH |
607 | 16, 17, 2, 3, 4, 5, 6, 7 |
608 | }; | |
60b63b72 RS |
609 | |
610 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
611 | |
612 | /* We don't relax branches by default, since this causes us to expand | |
613 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
614 | fail to compute the offset before expanding the macro to the most | |
615 | efficient expansion. */ | |
616 | ||
617 | static int mips_relax_branch; | |
252b5132 | 618 | \f |
4d7206a2 RS |
619 | /* The expansion of many macros depends on the type of symbol that |
620 | they refer to. For example, when generating position-dependent code, | |
621 | a macro that refers to a symbol may have two different expansions, | |
622 | one which uses GP-relative addresses and one which uses absolute | |
623 | addresses. When generating SVR4-style PIC, a macro may have | |
624 | different expansions for local and global symbols. | |
625 | ||
626 | We handle these situations by generating both sequences and putting | |
627 | them in variant frags. In position-dependent code, the first sequence | |
628 | will be the GP-relative one and the second sequence will be the | |
629 | absolute one. In SVR4 PIC, the first sequence will be for global | |
630 | symbols and the second will be for local symbols. | |
631 | ||
584892a6 RS |
632 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
633 | SECOND are the lengths of the two sequences in bytes. These fields | |
634 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
635 | the subtype has the following flags: | |
4d7206a2 | 636 | |
584892a6 RS |
637 | RELAX_USE_SECOND |
638 | Set if it has been decided that we should use the second | |
639 | sequence instead of the first. | |
640 | ||
641 | RELAX_SECOND_LONGER | |
642 | Set in the first variant frag if the macro's second implementation | |
643 | is longer than its first. This refers to the macro as a whole, | |
644 | not an individual relaxation. | |
645 | ||
646 | RELAX_NOMACRO | |
647 | Set in the first variant frag if the macro appeared in a .set nomacro | |
648 | block and if one alternative requires a warning but the other does not. | |
649 | ||
650 | RELAX_DELAY_SLOT | |
651 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
652 | delay slot. | |
4d7206a2 RS |
653 | |
654 | The frag's "opcode" points to the first fixup for relaxable code. | |
655 | ||
656 | Relaxable macros are generated using a sequence such as: | |
657 | ||
658 | relax_start (SYMBOL); | |
659 | ... generate first expansion ... | |
660 | relax_switch (); | |
661 | ... generate second expansion ... | |
662 | relax_end (); | |
663 | ||
664 | The code and fixups for the unwanted alternative are discarded | |
665 | by md_convert_frag. */ | |
584892a6 | 666 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 667 | |
584892a6 RS |
668 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
669 | #define RELAX_SECOND(X) ((X) & 0xff) | |
670 | #define RELAX_USE_SECOND 0x10000 | |
671 | #define RELAX_SECOND_LONGER 0x20000 | |
672 | #define RELAX_NOMACRO 0x40000 | |
673 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 674 | |
4a6a3df4 AO |
675 | /* Branch without likely bit. If label is out of range, we turn: |
676 | ||
677 | beq reg1, reg2, label | |
678 | delay slot | |
679 | ||
680 | into | |
681 | ||
682 | bne reg1, reg2, 0f | |
683 | nop | |
684 | j label | |
685 | 0: delay slot | |
686 | ||
687 | with the following opcode replacements: | |
688 | ||
689 | beq <-> bne | |
690 | blez <-> bgtz | |
691 | bltz <-> bgez | |
692 | bc1f <-> bc1t | |
693 | ||
694 | bltzal <-> bgezal (with jal label instead of j label) | |
695 | ||
696 | Even though keeping the delay slot instruction in the delay slot of | |
697 | the branch would be more efficient, it would be very tricky to do | |
698 | correctly, because we'd have to introduce a variable frag *after* | |
699 | the delay slot instruction, and expand that instead. Let's do it | |
700 | the easy way for now, even if the branch-not-taken case now costs | |
701 | one additional instruction. Out-of-range branches are not supposed | |
702 | to be common, anyway. | |
703 | ||
704 | Branch likely. If label is out of range, we turn: | |
705 | ||
706 | beql reg1, reg2, label | |
707 | delay slot (annulled if branch not taken) | |
708 | ||
709 | into | |
710 | ||
711 | beql reg1, reg2, 1f | |
712 | nop | |
713 | beql $0, $0, 2f | |
714 | nop | |
715 | 1: j[al] label | |
716 | delay slot (executed only if branch taken) | |
717 | 2: | |
718 | ||
719 | It would be possible to generate a shorter sequence by losing the | |
720 | likely bit, generating something like: | |
b34976b6 | 721 | |
4a6a3df4 AO |
722 | bne reg1, reg2, 0f |
723 | nop | |
724 | j[al] label | |
725 | delay slot (executed only if branch taken) | |
726 | 0: | |
727 | ||
728 | beql -> bne | |
729 | bnel -> beq | |
730 | blezl -> bgtz | |
731 | bgtzl -> blez | |
732 | bltzl -> bgez | |
733 | bgezl -> bltz | |
734 | bc1fl -> bc1t | |
735 | bc1tl -> bc1f | |
736 | ||
737 | bltzall -> bgezal (with jal label instead of j label) | |
738 | bgezall -> bltzal (ditto) | |
739 | ||
740 | ||
741 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 742 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
743 | ((relax_substateT) \ |
744 | (0xc0000000 \ | |
745 | | ((toofar) ? 1 : 0) \ | |
746 | | ((link) ? 2 : 0) \ | |
747 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 748 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 749 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
750 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
751 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
752 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 753 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 754 | |
252b5132 RH |
755 | /* For mips16 code, we use an entirely different form of relaxation. |
756 | mips16 supports two versions of most instructions which take | |
757 | immediate values: a small one which takes some small value, and a | |
758 | larger one which takes a 16 bit value. Since branches also follow | |
759 | this pattern, relaxing these values is required. | |
760 | ||
761 | We can assemble both mips16 and normal MIPS code in a single | |
762 | object. Therefore, we need to support this type of relaxation at | |
763 | the same time that we support the relaxation described above. We | |
764 | use the high bit of the subtype field to distinguish these cases. | |
765 | ||
766 | The information we store for this type of relaxation is the | |
767 | argument code found in the opcode file for this relocation, whether | |
768 | the user explicitly requested a small or extended form, and whether | |
769 | the relocation is in a jump or jal delay slot. That tells us the | |
770 | size of the value, and how it should be stored. We also store | |
771 | whether the fragment is considered to be extended or not. We also | |
772 | store whether this is known to be a branch to a different section, | |
773 | whether we have tried to relax this frag yet, and whether we have | |
774 | ever extended a PC relative fragment because of a shift count. */ | |
775 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
776 | (0x80000000 \ | |
777 | | ((type) & 0xff) \ | |
778 | | ((small) ? 0x100 : 0) \ | |
779 | | ((ext) ? 0x200 : 0) \ | |
780 | | ((dslot) ? 0x400 : 0) \ | |
781 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 782 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
783 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
784 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
785 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
786 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
787 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
788 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
789 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
790 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
791 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
792 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
793 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
794 | |
795 | /* Is the given value a sign-extended 32-bit value? */ | |
796 | #define IS_SEXT_32BIT_NUM(x) \ | |
797 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
798 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
799 | ||
800 | /* Is the given value a sign-extended 16-bit value? */ | |
801 | #define IS_SEXT_16BIT_NUM(x) \ | |
802 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
803 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
804 | ||
4d7206a2 RS |
805 | \f |
806 | /* Global variables used when generating relaxable macros. See the | |
807 | comment above RELAX_ENCODE for more details about how relaxation | |
808 | is used. */ | |
809 | static struct { | |
810 | /* 0 if we're not emitting a relaxable macro. | |
811 | 1 if we're emitting the first of the two relaxation alternatives. | |
812 | 2 if we're emitting the second alternative. */ | |
813 | int sequence; | |
814 | ||
815 | /* The first relaxable fixup in the current frag. (In other words, | |
816 | the first fixup that refers to relaxable code.) */ | |
817 | fixS *first_fixup; | |
818 | ||
819 | /* sizes[0] says how many bytes of the first alternative are stored in | |
820 | the current frag. Likewise sizes[1] for the second alternative. */ | |
821 | unsigned int sizes[2]; | |
822 | ||
823 | /* The symbol on which the choice of sequence depends. */ | |
824 | symbolS *symbol; | |
825 | } mips_relax; | |
252b5132 | 826 | \f |
584892a6 RS |
827 | /* Global variables used to decide whether a macro needs a warning. */ |
828 | static struct { | |
829 | /* True if the macro is in a branch delay slot. */ | |
830 | bfd_boolean delay_slot_p; | |
831 | ||
832 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
833 | in bytes and sizes[1] is the length of the second alternative. | |
834 | For non-relaxable macros, both elements give the length of the | |
835 | macro in bytes. */ | |
836 | unsigned int sizes[2]; | |
837 | ||
838 | /* The first variant frag for this macro. */ | |
839 | fragS *first_frag; | |
840 | } mips_macro_warning; | |
841 | \f | |
252b5132 RH |
842 | /* Prototypes for static functions. */ |
843 | ||
17a2f251 | 844 | #define internalError() \ |
252b5132 | 845 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
846 | |
847 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
848 | ||
b34976b6 | 849 | static void append_insn |
4d7206a2 | 850 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 851 | static void mips_no_prev_insn (int); |
b34976b6 | 852 | static void mips16_macro_build |
67c0d1eb RS |
853 | (expressionS *, const char *, const char *, va_list); |
854 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
855 | static void macro_start (void); |
856 | static void macro_end (void); | |
17a2f251 TS |
857 | static void macro (struct mips_cl_insn * ip); |
858 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 859 | #ifdef LOSING_COMPILER |
17a2f251 | 860 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 861 | #endif |
17a2f251 TS |
862 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
863 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 864 | static void mips16_immed |
17a2f251 TS |
865 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
866 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 867 | static size_t my_getSmallExpression |
17a2f251 TS |
868 | (expressionS *, bfd_reloc_code_real_type *, char *); |
869 | static void my_getExpression (expressionS *, char *); | |
870 | static void s_align (int); | |
871 | static void s_change_sec (int); | |
872 | static void s_change_section (int); | |
873 | static void s_cons (int); | |
874 | static void s_float_cons (int); | |
875 | static void s_mips_globl (int); | |
876 | static void s_option (int); | |
877 | static void s_mipsset (int); | |
878 | static void s_abicalls (int); | |
879 | static void s_cpload (int); | |
880 | static void s_cpsetup (int); | |
881 | static void s_cplocal (int); | |
882 | static void s_cprestore (int); | |
883 | static void s_cpreturn (int); | |
884 | static void s_gpvalue (int); | |
885 | static void s_gpword (int); | |
886 | static void s_gpdword (int); | |
887 | static void s_cpadd (int); | |
888 | static void s_insn (int); | |
889 | static void md_obj_begin (void); | |
890 | static void md_obj_end (void); | |
891 | static void s_mips_ent (int); | |
892 | static void s_mips_end (int); | |
893 | static void s_mips_frame (int); | |
894 | static void s_mips_mask (int reg_type); | |
895 | static void s_mips_stab (int); | |
896 | static void s_mips_weakext (int); | |
897 | static void s_mips_file (int); | |
898 | static void s_mips_loc (int); | |
899 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 900 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 901 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
902 | |
903 | /* Table and functions used to map between CPU/ISA names, and | |
904 | ISA levels, and CPU numbers. */ | |
905 | ||
e972090a NC |
906 | struct mips_cpu_info |
907 | { | |
e7af610e NC |
908 | const char *name; /* CPU or ISA name. */ |
909 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
910 | int isa; /* ISA level. */ | |
911 | int cpu; /* CPU number (default CPU if ISA). */ | |
912 | }; | |
913 | ||
17a2f251 TS |
914 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
915 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
916 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
917 | \f |
918 | /* Pseudo-op table. | |
919 | ||
920 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
921 | should be defined here, but are currently unsupported: .alias, | |
922 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
923 | ||
924 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
925 | specific to the type of debugging information being generated, and | |
926 | should be defined by the object format: .aent, .begin, .bend, | |
927 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
928 | .vreg. | |
929 | ||
930 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
931 | not MIPS CPU specific, but are also not specific to the object file | |
932 | format. This file is probably the best place to define them, but | |
933 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
934 | .struct. */ | |
935 | ||
e972090a NC |
936 | static const pseudo_typeS mips_pseudo_table[] = |
937 | { | |
beae10d5 | 938 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
939 | {"option", s_option, 0}, |
940 | {"set", s_mipsset, 0}, | |
941 | {"rdata", s_change_sec, 'r'}, | |
942 | {"sdata", s_change_sec, 's'}, | |
943 | {"livereg", s_ignore, 0}, | |
944 | {"abicalls", s_abicalls, 0}, | |
945 | {"cpload", s_cpload, 0}, | |
6478892d TS |
946 | {"cpsetup", s_cpsetup, 0}, |
947 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 948 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
949 | {"cpreturn", s_cpreturn, 0}, |
950 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 951 | {"gpword", s_gpword, 0}, |
10181a0d | 952 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
953 | {"cpadd", s_cpadd, 0}, |
954 | {"insn", s_insn, 0}, | |
955 | ||
beae10d5 | 956 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
957 | chips. */ |
958 | {"asciiz", stringer, 1}, | |
959 | {"bss", s_change_sec, 'b'}, | |
960 | {"err", s_err, 0}, | |
961 | {"half", s_cons, 1}, | |
962 | {"dword", s_cons, 3}, | |
963 | {"weakext", s_mips_weakext, 0}, | |
964 | ||
beae10d5 | 965 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
966 | here for one reason or another. */ |
967 | {"align", s_align, 0}, | |
968 | {"byte", s_cons, 0}, | |
969 | {"data", s_change_sec, 'd'}, | |
970 | {"double", s_float_cons, 'd'}, | |
971 | {"float", s_float_cons, 'f'}, | |
972 | {"globl", s_mips_globl, 0}, | |
973 | {"global", s_mips_globl, 0}, | |
974 | {"hword", s_cons, 1}, | |
975 | {"int", s_cons, 2}, | |
976 | {"long", s_cons, 2}, | |
977 | {"octa", s_cons, 4}, | |
978 | {"quad", s_cons, 3}, | |
cca86cc8 | 979 | {"section", s_change_section, 0}, |
252b5132 RH |
980 | {"short", s_cons, 1}, |
981 | {"single", s_float_cons, 'f'}, | |
982 | {"stabn", s_mips_stab, 'n'}, | |
983 | {"text", s_change_sec, 't'}, | |
984 | {"word", s_cons, 2}, | |
add56521 | 985 | |
add56521 | 986 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 987 | |
43841e91 | 988 | { NULL, NULL, 0 }, |
252b5132 RH |
989 | }; |
990 | ||
e972090a NC |
991 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
992 | { | |
beae10d5 KH |
993 | /* These pseudo-ops should be defined by the object file format. |
994 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
995 | {"aent", s_mips_ent, 1}, |
996 | {"bgnb", s_ignore, 0}, | |
997 | {"end", s_mips_end, 0}, | |
998 | {"endb", s_ignore, 0}, | |
999 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1000 | {"file", s_mips_file, 0}, |
252b5132 RH |
1001 | {"fmask", s_mips_mask, 'F'}, |
1002 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1003 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1004 | {"mask", s_mips_mask, 'R'}, |
1005 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1006 | { NULL, NULL, 0 }, |
252b5132 RH |
1007 | }; |
1008 | ||
17a2f251 | 1009 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1010 | |
1011 | void | |
17a2f251 | 1012 | mips_pop_insert (void) |
252b5132 RH |
1013 | { |
1014 | pop_insert (mips_pseudo_table); | |
1015 | if (! ECOFF_DEBUGGING) | |
1016 | pop_insert (mips_nonecoff_pseudo_table); | |
1017 | } | |
1018 | \f | |
1019 | /* Symbols labelling the current insn. */ | |
1020 | ||
e972090a NC |
1021 | struct insn_label_list |
1022 | { | |
252b5132 RH |
1023 | struct insn_label_list *next; |
1024 | symbolS *label; | |
1025 | }; | |
1026 | ||
1027 | static struct insn_label_list *insn_labels; | |
1028 | static struct insn_label_list *free_insn_labels; | |
1029 | ||
17a2f251 | 1030 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1031 | |
1032 | static inline void | |
17a2f251 | 1033 | mips_clear_insn_labels (void) |
252b5132 RH |
1034 | { |
1035 | register struct insn_label_list **pl; | |
1036 | ||
1037 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1038 | ; | |
1039 | *pl = insn_labels; | |
1040 | insn_labels = NULL; | |
1041 | } | |
1042 | \f | |
1043 | static char *expr_end; | |
1044 | ||
1045 | /* Expressions which appear in instructions. These are set by | |
1046 | mips_ip. */ | |
1047 | ||
1048 | static expressionS imm_expr; | |
5f74bc13 | 1049 | static expressionS imm2_expr; |
252b5132 RH |
1050 | static expressionS offset_expr; |
1051 | ||
1052 | /* Relocs associated with imm_expr and offset_expr. */ | |
1053 | ||
f6688943 TS |
1054 | static bfd_reloc_code_real_type imm_reloc[3] |
1055 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1056 | static bfd_reloc_code_real_type offset_reloc[3] | |
1057 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1058 | |
252b5132 RH |
1059 | /* These are set by mips16_ip if an explicit extension is used. */ |
1060 | ||
b34976b6 | 1061 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1062 | |
7ed4a06a | 1063 | #ifdef OBJ_ELF |
ecb4347a DJ |
1064 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1065 | ECOFF debugging. */ | |
252b5132 RH |
1066 | |
1067 | static segT pdr_seg; | |
7ed4a06a | 1068 | #endif |
252b5132 | 1069 | |
e013f690 TS |
1070 | /* The default target format to use. */ |
1071 | ||
1072 | const char * | |
17a2f251 | 1073 | mips_target_format (void) |
e013f690 TS |
1074 | { |
1075 | switch (OUTPUT_FLAVOR) | |
1076 | { | |
1077 | case bfd_target_aout_flavour: | |
1078 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1079 | case bfd_target_ecoff_flavour: | |
1080 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1081 | case bfd_target_coff_flavour: | |
1082 | return "pe-mips"; | |
1083 | case bfd_target_elf_flavour: | |
1084 | #ifdef TE_TMIPS | |
cfe86eaa | 1085 | /* This is traditional mips. */ |
e013f690 | 1086 | return (target_big_endian |
cfe86eaa TS |
1087 | ? (HAVE_64BIT_OBJECTS |
1088 | ? "elf64-tradbigmips" | |
1089 | : (HAVE_NEWABI | |
1090 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1091 | : (HAVE_64BIT_OBJECTS | |
1092 | ? "elf64-tradlittlemips" | |
1093 | : (HAVE_NEWABI | |
1094 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1095 | #else |
1096 | return (target_big_endian | |
cfe86eaa TS |
1097 | ? (HAVE_64BIT_OBJECTS |
1098 | ? "elf64-bigmips" | |
1099 | : (HAVE_NEWABI | |
1100 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1101 | : (HAVE_64BIT_OBJECTS | |
1102 | ? "elf64-littlemips" | |
1103 | : (HAVE_NEWABI | |
1104 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1105 | #endif |
1106 | default: | |
1107 | abort (); | |
1108 | return NULL; | |
1109 | } | |
1110 | } | |
1111 | ||
156c2f8b NC |
1112 | /* This function is called once, at assembler startup time. It should |
1113 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1114 | ||
252b5132 | 1115 | void |
17a2f251 | 1116 | md_begin (void) |
252b5132 | 1117 | { |
252b5132 | 1118 | register const char *retval = NULL; |
156c2f8b | 1119 | int i = 0; |
252b5132 | 1120 | int broken = 0; |
1f25f5d3 | 1121 | |
fef14a42 | 1122 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1123 | as_warn (_("Could not set architecture and machine")); |
1124 | ||
252b5132 RH |
1125 | op_hash = hash_new (); |
1126 | ||
1127 | for (i = 0; i < NUMOPCODES;) | |
1128 | { | |
1129 | const char *name = mips_opcodes[i].name; | |
1130 | ||
17a2f251 | 1131 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1132 | if (retval != NULL) |
1133 | { | |
1134 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1135 | mips_opcodes[i].name, retval); | |
1136 | /* Probably a memory allocation problem? Give up now. */ | |
1137 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1138 | } | |
1139 | do | |
1140 | { | |
1141 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1142 | { | |
1143 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1144 | broken = 1; | |
1145 | } | |
1146 | ++i; | |
1147 | } | |
1148 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1149 | } | |
1150 | ||
1151 | mips16_op_hash = hash_new (); | |
1152 | ||
1153 | i = 0; | |
1154 | while (i < bfd_mips16_num_opcodes) | |
1155 | { | |
1156 | const char *name = mips16_opcodes[i].name; | |
1157 | ||
17a2f251 | 1158 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1159 | if (retval != NULL) |
1160 | as_fatal (_("internal: can't hash `%s': %s"), | |
1161 | mips16_opcodes[i].name, retval); | |
1162 | do | |
1163 | { | |
1164 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1165 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1166 | != mips16_opcodes[i].match)) | |
1167 | { | |
1168 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1169 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1170 | broken = 1; | |
1171 | } | |
1172 | ++i; | |
1173 | } | |
1174 | while (i < bfd_mips16_num_opcodes | |
1175 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1176 | } | |
1177 | ||
1178 | if (broken) | |
1179 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1180 | ||
1181 | /* We add all the general register names to the symbol table. This | |
1182 | helps us detect invalid uses of them. */ | |
1183 | for (i = 0; i < 32; i++) | |
1184 | { | |
1185 | char buf[5]; | |
1186 | ||
1187 | sprintf (buf, "$%d", i); | |
1188 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1189 | &zero_address_frag)); | |
1190 | } | |
76db943d TS |
1191 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1192 | &zero_address_frag)); | |
252b5132 RH |
1193 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1194 | &zero_address_frag)); | |
1195 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1196 | &zero_address_frag)); | |
1197 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1198 | &zero_address_frag)); | |
1199 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1200 | &zero_address_frag)); | |
1201 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1202 | &zero_address_frag)); | |
1203 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1204 | &zero_address_frag)); | |
85b51719 TS |
1205 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1206 | &zero_address_frag)); | |
252b5132 RH |
1207 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1208 | &zero_address_frag)); | |
1209 | ||
6047c971 AO |
1210 | /* If we don't add these register names to the symbol table, they |
1211 | may end up being added as regular symbols by operand(), and then | |
1212 | make it to the object file as undefined in case they're not | |
1213 | regarded as local symbols. They're local in o32, since `$' is a | |
1214 | local symbol prefix, but not in n32 or n64. */ | |
1215 | for (i = 0; i < 8; i++) | |
1216 | { | |
1217 | char buf[6]; | |
1218 | ||
1219 | sprintf (buf, "$fcc%i", i); | |
1220 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1221 | &zero_address_frag)); | |
1222 | } | |
1223 | ||
b34976b6 | 1224 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1225 | |
1226 | mips_gprmask = 0; | |
1227 | mips_cprmask[0] = 0; | |
1228 | mips_cprmask[1] = 0; | |
1229 | mips_cprmask[2] = 0; | |
1230 | mips_cprmask[3] = 0; | |
1231 | ||
1232 | /* set the default alignment for the text section (2**2) */ | |
1233 | record_alignment (text_section, 2); | |
1234 | ||
1235 | if (USE_GLOBAL_POINTER_OPT) | |
1236 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1237 | ||
1238 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1239 | { | |
1240 | /* On a native system, sections must be aligned to 16 byte | |
1241 | boundaries. When configured for an embedded ELF target, we | |
1242 | don't bother. */ | |
1243 | if (strcmp (TARGET_OS, "elf") != 0) | |
1244 | { | |
1245 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1246 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1247 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1248 | } | |
1249 | ||
1250 | /* Create a .reginfo section for register masks and a .mdebug | |
1251 | section for debugging information. */ | |
1252 | { | |
1253 | segT seg; | |
1254 | subsegT subseg; | |
1255 | flagword flags; | |
1256 | segT sec; | |
1257 | ||
1258 | seg = now_seg; | |
1259 | subseg = now_subseg; | |
1260 | ||
1261 | /* The ABI says this section should be loaded so that the | |
1262 | running program can access it. However, we don't load it | |
1263 | if we are configured for an embedded target */ | |
1264 | flags = SEC_READONLY | SEC_DATA; | |
1265 | if (strcmp (TARGET_OS, "elf") != 0) | |
1266 | flags |= SEC_ALLOC | SEC_LOAD; | |
1267 | ||
316f5878 | 1268 | if (mips_abi != N64_ABI) |
252b5132 RH |
1269 | { |
1270 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1271 | ||
195325d2 TS |
1272 | bfd_set_section_flags (stdoutput, sec, flags); |
1273 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1274 | |
252b5132 RH |
1275 | #ifdef OBJ_ELF |
1276 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1277 | #endif | |
1278 | } | |
1279 | else | |
1280 | { | |
1281 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1282 | .reginfo section. */ | |
1283 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1284 | bfd_set_section_flags (stdoutput, sec, flags); |
1285 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1286 | |
1287 | #ifdef OBJ_ELF | |
1288 | /* Set up the option header. */ | |
1289 | { | |
1290 | Elf_Internal_Options opthdr; | |
1291 | char *f; | |
1292 | ||
1293 | opthdr.kind = ODK_REGINFO; | |
1294 | opthdr.size = (sizeof (Elf_External_Options) | |
1295 | + sizeof (Elf64_External_RegInfo)); | |
1296 | opthdr.section = 0; | |
1297 | opthdr.info = 0; | |
1298 | f = frag_more (sizeof (Elf_External_Options)); | |
1299 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1300 | (Elf_External_Options *) f); | |
1301 | ||
1302 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1303 | } | |
1304 | #endif | |
1305 | } | |
1306 | ||
1307 | if (ECOFF_DEBUGGING) | |
1308 | { | |
1309 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1310 | (void) bfd_set_section_flags (stdoutput, sec, | |
1311 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1312 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1313 | } | |
ecb4347a | 1314 | #ifdef OBJ_ELF |
dcd410fe | 1315 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1316 | { |
1317 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1318 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1319 | SEC_READONLY | SEC_RELOC | |
1320 | | SEC_DEBUGGING); | |
1321 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1322 | } | |
252b5132 RH |
1323 | #endif |
1324 | ||
1325 | subseg_set (seg, subseg); | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | if (! ECOFF_DEBUGGING) | |
1330 | md_obj_begin (); | |
1331 | } | |
1332 | ||
1333 | void | |
17a2f251 | 1334 | md_mips_end (void) |
252b5132 RH |
1335 | { |
1336 | if (! ECOFF_DEBUGGING) | |
1337 | md_obj_end (); | |
1338 | } | |
1339 | ||
1340 | void | |
17a2f251 | 1341 | md_assemble (char *str) |
252b5132 RH |
1342 | { |
1343 | struct mips_cl_insn insn; | |
f6688943 TS |
1344 | bfd_reloc_code_real_type unused_reloc[3] |
1345 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1346 | |
1347 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1348 | imm2_expr.X_op = O_absent; |
252b5132 | 1349 | offset_expr.X_op = O_absent; |
f6688943 TS |
1350 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1351 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1352 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1353 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1354 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1355 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1356 | |
1357 | if (mips_opts.mips16) | |
1358 | mips16_ip (str, &insn); | |
1359 | else | |
1360 | { | |
1361 | mips_ip (str, &insn); | |
beae10d5 KH |
1362 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1363 | str, insn.insn_opcode)); | |
252b5132 RH |
1364 | } |
1365 | ||
1366 | if (insn_error) | |
1367 | { | |
1368 | as_bad ("%s `%s'", insn_error, str); | |
1369 | return; | |
1370 | } | |
1371 | ||
1372 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1373 | { | |
584892a6 | 1374 | macro_start (); |
252b5132 RH |
1375 | if (mips_opts.mips16) |
1376 | mips16_macro (&insn); | |
1377 | else | |
1378 | macro (&insn); | |
584892a6 | 1379 | macro_end (); |
252b5132 RH |
1380 | } |
1381 | else | |
1382 | { | |
1383 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1384 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1385 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1386 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1387 | else |
4d7206a2 | 1388 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1389 | } |
1390 | } | |
1391 | ||
5919d012 RS |
1392 | /* Return true if the given relocation might need a matching %lo(). |
1393 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1394 | applied to local symbols. */ | |
1395 | ||
1396 | static inline bfd_boolean | |
17a2f251 | 1397 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 RS |
1398 | { |
1399 | return (reloc == BFD_RELOC_HI16_S | |
1400 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1401 | } | |
1402 | ||
1403 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1404 | relocation. */ | |
1405 | ||
1406 | static inline bfd_boolean | |
17a2f251 | 1407 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1408 | { |
1409 | return (fixp->fx_next != NULL | |
1410 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1411 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1412 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1413 | } | |
1414 | ||
252b5132 RH |
1415 | /* See whether instruction IP reads register REG. CLASS is the type |
1416 | of register. */ | |
1417 | ||
1418 | static int | |
17a2f251 TS |
1419 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1420 | enum mips_regclass class) | |
252b5132 RH |
1421 | { |
1422 | if (class == MIPS16_REG) | |
1423 | { | |
1424 | assert (mips_opts.mips16); | |
1425 | reg = mips16_to_32_reg_map[reg]; | |
1426 | class = MIPS_GR_REG; | |
1427 | } | |
1428 | ||
85b51719 TS |
1429 | /* Don't report on general register ZERO, since it never changes. */ |
1430 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1431 | return 0; |
1432 | ||
1433 | if (class == MIPS_FP_REG) | |
1434 | { | |
1435 | assert (! mips_opts.mips16); | |
1436 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1437 | This is not optimal, because it will introduce an unnecessary | |
1438 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1439 | need to distinguish reading both $f0 and $f1 or just one of | |
1440 | them. Note that we don't have to check the other way, | |
1441 | because there is no instruction that sets both $f0 and $f1 | |
1442 | and requires a delay. */ | |
1443 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1444 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1445 | == (reg &~ (unsigned) 1))) | |
1446 | return 1; | |
1447 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1448 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1449 | == (reg &~ (unsigned) 1))) | |
1450 | return 1; | |
1451 | } | |
1452 | else if (! mips_opts.mips16) | |
1453 | { | |
1454 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1455 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1456 | return 1; | |
1457 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1458 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1459 | return 1; | |
1460 | } | |
1461 | else | |
1462 | { | |
1463 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1464 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1465 | & MIPS16OP_MASK_RX)] | |
1466 | == reg)) | |
1467 | return 1; | |
1468 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1469 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1470 | & MIPS16OP_MASK_RY)] | |
1471 | == reg)) | |
1472 | return 1; | |
1473 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1474 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1475 | & MIPS16OP_MASK_MOVE32Z)] | |
1476 | == reg)) | |
1477 | return 1; | |
1478 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1479 | return 1; | |
1480 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1481 | return 1; | |
1482 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1483 | return 1; | |
1484 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1485 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1486 | & MIPS16OP_MASK_REGR32) == reg) | |
1487 | return 1; | |
1488 | } | |
1489 | ||
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | /* This function returns true if modifying a register requires a | |
1494 | delay. */ | |
1495 | ||
1496 | static int | |
17a2f251 | 1497 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1498 | { |
1499 | unsigned long prev_pinfo; | |
1500 | ||
1501 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1502 | if (! mips_opts.noreorder | |
81912461 ILT |
1503 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1504 | && ! gpr_interlocks) | |
1505 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1506 | && ! cop_interlocks))) | |
252b5132 | 1507 | { |
81912461 ILT |
1508 | /* A load from a coprocessor or from memory. All load delays |
1509 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1510 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1511 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1512 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1513 | return 1; | |
1514 | } | |
1515 | ||
1516 | return 0; | |
1517 | } | |
1518 | ||
1519 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1520 | handle them specially, such as generating jalx instructions when | |
1521 | needed. We also make them odd for the duration of the assembly, in | |
1522 | order to generate the right sort of code. We will make them even | |
1523 | in the adjust_symtab routine, while leaving them marked. This is | |
1524 | convenient for the debugger and the disassembler. The linker knows | |
1525 | to make them odd again. */ | |
1526 | ||
1527 | static void | |
17a2f251 | 1528 | mips16_mark_labels (void) |
252b5132 RH |
1529 | { |
1530 | if (mips_opts.mips16) | |
1531 | { | |
1532 | struct insn_label_list *l; | |
98aa84af | 1533 | valueT val; |
252b5132 RH |
1534 | |
1535 | for (l = insn_labels; l != NULL; l = l->next) | |
1536 | { | |
1537 | #ifdef OBJ_ELF | |
1538 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1539 | S_SET_OTHER (l->label, STO_MIPS16); | |
1540 | #endif | |
98aa84af AM |
1541 | val = S_GET_VALUE (l->label); |
1542 | if ((val & 1) == 0) | |
1543 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1544 | } |
1545 | } | |
1546 | } | |
1547 | ||
4d7206a2 RS |
1548 | /* End the current frag. Make it a variant frag and record the |
1549 | relaxation info. */ | |
1550 | ||
1551 | static void | |
1552 | relax_close_frag (void) | |
1553 | { | |
584892a6 | 1554 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1555 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1556 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1557 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1558 | ||
1559 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1560 | mips_relax.first_fixup = 0; | |
1561 | } | |
1562 | ||
1563 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1564 | See the comment above RELAX_ENCODE for more details. */ | |
1565 | ||
1566 | static void | |
1567 | relax_start (symbolS *symbol) | |
1568 | { | |
1569 | assert (mips_relax.sequence == 0); | |
1570 | mips_relax.sequence = 1; | |
1571 | mips_relax.symbol = symbol; | |
1572 | } | |
1573 | ||
1574 | /* Start generating the second version of a relaxable sequence. | |
1575 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1576 | |
1577 | static void | |
4d7206a2 RS |
1578 | relax_switch (void) |
1579 | { | |
1580 | assert (mips_relax.sequence == 1); | |
1581 | mips_relax.sequence = 2; | |
1582 | } | |
1583 | ||
1584 | /* End the current relaxable sequence. */ | |
1585 | ||
1586 | static void | |
1587 | relax_end (void) | |
1588 | { | |
1589 | assert (mips_relax.sequence == 2); | |
1590 | relax_close_frag (); | |
1591 | mips_relax.sequence = 0; | |
1592 | } | |
1593 | ||
1594 | /* Output an instruction. IP is the instruction information. | |
1595 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1596 | RELOC_TYPE. */ | |
1597 | ||
1598 | static void | |
1599 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1600 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1601 | { |
1602 | register unsigned long prev_pinfo, pinfo; | |
1603 | char *f; | |
f6688943 | 1604 | fixS *fixp[3]; |
252b5132 | 1605 | int nops = 0; |
895921c9 MR |
1606 | relax_stateT prev_insn_frag_type = 0; |
1607 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1608 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1609 | |
1610 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1611 | mips16_mark_labels (); |
252b5132 RH |
1612 | |
1613 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1614 | pinfo = ip->insn_mo->pinfo; | |
1615 | ||
4d7206a2 RS |
1616 | if (mips_relax.sequence != 2 |
1617 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1618 | { |
1619 | int prev_prev_nop; | |
1620 | ||
1621 | /* If the previous insn required any delay slots, see if we need | |
1622 | to insert a NOP or two. There are eight kinds of possible | |
1623 | hazards, of which an instruction can have at most one type. | |
1624 | (1) a load from memory delay | |
1625 | (2) a load from a coprocessor delay | |
1626 | (3) an unconditional branch delay | |
1627 | (4) a conditional branch delay | |
1628 | (5) a move to coprocessor register delay | |
1629 | (6) a load coprocessor register from memory delay | |
1630 | (7) a coprocessor condition code delay | |
1631 | (8) a HI/LO special register delay | |
1632 | ||
1633 | There are a lot of optimizations we could do that we don't. | |
1634 | In particular, we do not, in general, reorder instructions. | |
1635 | If you use gcc with optimization, it will reorder | |
1636 | instructions and generally do much more optimization then we | |
1637 | do here; repeating all that work in the assembler would only | |
1638 | benefit hand written assembly code, and does not seem worth | |
1639 | it. */ | |
1640 | ||
1641 | /* This is how a NOP is emitted. */ | |
1642 | #define emit_nop() \ | |
1643 | (mips_opts.mips16 \ | |
1644 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1645 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1646 | ||
1647 | /* The previous insn might require a delay slot, depending upon | |
1648 | the contents of the current insn. */ | |
1649 | if (! mips_opts.mips16 | |
81912461 ILT |
1650 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1651 | && ! gpr_interlocks) | |
1652 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1653 | && ! cop_interlocks))) | |
252b5132 RH |
1654 | { |
1655 | /* A load from a coprocessor or from memory. All load | |
1656 | delays delay the use of general register rt for one | |
81912461 | 1657 | instruction. */ |
beae10d5 | 1658 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1659 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1660 | if (mips_optimize == 0 | |
1661 | || insn_uses_reg (ip, | |
1662 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1663 | & OP_MASK_RT), | |
1664 | MIPS_GR_REG)) | |
1665 | ++nops; | |
1666 | } | |
1667 | else if (! mips_opts.mips16 | |
252b5132 | 1668 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1669 | && ! cop_interlocks) |
81912461 ILT |
1670 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1671 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1672 | { |
1673 | /* A generic coprocessor delay. The previous instruction | |
1674 | modified a coprocessor general or control register. If | |
1675 | it modified a control register, we need to avoid any | |
1676 | coprocessor instruction (this is probably not always | |
1677 | required, but it sometimes is). If it modified a general | |
1678 | register, we avoid using that register. | |
1679 | ||
252b5132 RH |
1680 | This case is not handled very well. There is no special |
1681 | knowledge of CP0 handling, and the coprocessors other | |
1682 | than the floating point unit are not distinguished at | |
1683 | all. */ | |
1684 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1685 | Need to modify this to include knowledge about |
252b5132 RH |
1686 | user specified delays! */ |
1687 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1688 | { | |
1689 | if (mips_optimize == 0 | |
1690 | || insn_uses_reg (ip, | |
1691 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1692 | & OP_MASK_FT), | |
1693 | MIPS_FP_REG)) | |
1694 | ++nops; | |
1695 | } | |
1696 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1697 | { | |
1698 | if (mips_optimize == 0 | |
1699 | || insn_uses_reg (ip, | |
1700 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1701 | & OP_MASK_FS), | |
1702 | MIPS_FP_REG)) | |
1703 | ++nops; | |
1704 | } | |
1705 | else | |
1706 | { | |
1707 | /* We don't know exactly what the previous instruction | |
1708 | does. If the current instruction uses a coprocessor | |
1709 | register, we must insert a NOP. If previous | |
1710 | instruction may set the condition codes, and the | |
1711 | current instruction uses them, we must insert two | |
1712 | NOPS. */ | |
bdaaa2e1 | 1713 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1714 | if (mips_optimize == 0 |
1715 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1716 | && (pinfo & INSN_READ_COND_CODE))) | |
1717 | nops += 2; | |
1718 | else if (pinfo & INSN_COP) | |
1719 | ++nops; | |
1720 | } | |
1721 | } | |
1722 | else if (! mips_opts.mips16 | |
252b5132 RH |
1723 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1724 | && ! cop_interlocks) | |
1725 | { | |
1726 | /* The previous instruction sets the coprocessor condition | |
1727 | codes, but does not require a general coprocessor delay | |
1728 | (this means it is a floating point comparison | |
1729 | instruction). If this instruction uses the condition | |
1730 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1731 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1732 | if (mips_optimize == 0 |
1733 | || (pinfo & INSN_READ_COND_CODE)) | |
1734 | ++nops; | |
1735 | } | |
6b76fefe CM |
1736 | |
1737 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1738 | previous insn was an mfhi/mflo and the current insn | |
1739 | reads the register that the mfhi/mflo wrote to, then | |
1740 | insert two nops. */ | |
1741 | ||
1742 | else if (mips_7000_hilo_fix | |
1743 | && MF_HILO_INSN (prev_pinfo) | |
1744 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1745 | & OP_MASK_RD), |
1746 | MIPS_GR_REG)) | |
6b76fefe CM |
1747 | { |
1748 | nops += 2; | |
1749 | } | |
1750 | ||
1751 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1752 | 2nd previous insn was an mfhi/mflo and the current insn | |
1753 | reads the register that the mfhi/mflo wrote to, then | |
1754 | insert one nop. */ | |
1755 | ||
1756 | else if (mips_7000_hilo_fix | |
1757 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1758 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1759 | & OP_MASK_RD), | |
1760 | MIPS_GR_REG)) | |
bdaaa2e1 | 1761 | |
6b76fefe | 1762 | { |
f9419b05 | 1763 | ++nops; |
6b76fefe | 1764 | } |
bdaaa2e1 | 1765 | |
252b5132 RH |
1766 | else if (prev_pinfo & INSN_READ_LO) |
1767 | { | |
1768 | /* The previous instruction reads the LO register; if the | |
1769 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1770 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1771 | Also the tx39's multiply instructions can be executed |
1772 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1773 | though the tx39's divide insns still do require the |
1774 | delay. */ | |
252b5132 | 1775 | if (! (hilo_interlocks |
048cdf86 | 1776 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1777 | && (mips_optimize == 0 |
1778 | || (pinfo & INSN_WRITE_LO))) | |
1779 | nops += 2; | |
1780 | /* Most mips16 branch insns don't have a delay slot. | |
1781 | If a read from LO is immediately followed by a branch | |
1782 | to a write to LO we have a read followed by a write | |
1783 | less than 2 insns away. We assume the target of | |
1784 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1785 | between a read and an immediately following branch. */ |
252b5132 RH |
1786 | else if (mips_opts.mips16 |
1787 | && (mips_optimize == 0 | |
1788 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1789 | ++nops; |
252b5132 RH |
1790 | } |
1791 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1792 | { | |
1793 | /* The previous instruction reads the HI register; if the | |
1794 | current instruction writes to the HI register, we must | |
1795 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1796 | Also the note tx39's multiply above. */ |
252b5132 | 1797 | if (! (hilo_interlocks |
048cdf86 | 1798 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1799 | && (mips_optimize == 0 |
1800 | || (pinfo & INSN_WRITE_HI))) | |
1801 | nops += 2; | |
1802 | /* Most mips16 branch insns don't have a delay slot. | |
1803 | If a read from HI is immediately followed by a branch | |
1804 | to a write to HI we have a read followed by a write | |
1805 | less than 2 insns away. We assume the target of | |
1806 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1807 | between a read and an immediately following branch. */ |
252b5132 RH |
1808 | else if (mips_opts.mips16 |
1809 | && (mips_optimize == 0 | |
1810 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1811 | ++nops; |
252b5132 RH |
1812 | } |
1813 | ||
1814 | /* If the previous instruction was in a noreorder section, then | |
1815 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1816 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1817 | if (prev_insn_unreordered) |
1818 | nops = 0; | |
1819 | ||
1820 | /* There are two cases which require two intervening | |
1821 | instructions: 1) setting the condition codes using a move to | |
1822 | coprocessor instruction which requires a general coprocessor | |
1823 | delay and then reading the condition codes 2) reading the HI | |
1824 | or LO register and then writing to it (except on processors | |
1825 | which have interlocks). If we are not already emitting a NOP | |
1826 | instruction, we must check for these cases compared to the | |
1827 | instruction previous to the previous instruction. */ | |
1828 | if ((! mips_opts.mips16 | |
252b5132 RH |
1829 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1830 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1831 | && (pinfo & INSN_READ_COND_CODE) | |
1832 | && ! cop_interlocks) | |
1833 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1834 | && (pinfo & INSN_WRITE_LO) | |
1835 | && ! (hilo_interlocks | |
048cdf86 | 1836 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1837 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1838 | && (pinfo & INSN_WRITE_HI) | |
1839 | && ! (hilo_interlocks | |
048cdf86 | 1840 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1841 | prev_prev_nop = 1; |
1842 | else | |
1843 | prev_prev_nop = 0; | |
1844 | ||
1845 | if (prev_prev_insn_unreordered) | |
1846 | prev_prev_nop = 0; | |
1847 | ||
1848 | if (prev_prev_nop && nops == 0) | |
1849 | ++nops; | |
1850 | ||
60b63b72 RS |
1851 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1852 | { | |
1853 | /* We're out of bits in pinfo, so we must resort to string | |
1854 | ops here. Shortcuts are selected based on opcodes being | |
1855 | limited to the VR4122 instruction set. */ | |
1856 | int min_nops = 0; | |
1857 | const char *pn = prev_insn.insn_mo->name; | |
1858 | const char *tn = ip->insn_mo->name; | |
1859 | if (strncmp(pn, "macc", 4) == 0 | |
1860 | || strncmp(pn, "dmacc", 5) == 0) | |
1861 | { | |
1862 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1863 | if (strstr (tn, "div")) | |
1864 | { | |
1865 | min_nops = 1; | |
1866 | } | |
1867 | ||
1868 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1869 | if (pn[0] == 'd' /* dmacc */ | |
1870 | && (strncmp(tn, "dmult", 5) == 0 | |
1871 | || strncmp(tn, "dmacc", 5) == 0)) | |
1872 | { | |
1873 | min_nops = 1; | |
1874 | } | |
1875 | ||
1876 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1877 | if (strcmp (tn, "mtlo") == 0 | |
1878 | || strcmp (tn, "mthi") == 0) | |
1879 | { | |
1880 | min_nops = 1; | |
1881 | } | |
1882 | ||
1883 | } | |
1884 | else if (strncmp(pn, "dmult", 5) == 0 | |
1885 | && (strncmp(tn, "dmult", 5) == 0 | |
1886 | || strncmp(tn, "dmacc", 5) == 0)) | |
1887 | { | |
1888 | /* Here is the rest of errata 23. */ | |
1889 | min_nops = 1; | |
1890 | } | |
1891 | if (nops < min_nops) | |
1892 | nops = min_nops; | |
1893 | } | |
1894 | ||
252b5132 RH |
1895 | /* If we are being given a nop instruction, don't bother with |
1896 | one of the nops we would otherwise output. This will only | |
1897 | happen when a nop instruction is used with mips_optimize set | |
1898 | to 0. */ | |
1899 | if (nops > 0 | |
1900 | && ! mips_opts.noreorder | |
156c2f8b | 1901 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1902 | --nops; |
1903 | ||
1904 | /* Now emit the right number of NOP instructions. */ | |
1905 | if (nops > 0 && ! mips_opts.noreorder) | |
1906 | { | |
1907 | fragS *old_frag; | |
1908 | unsigned long old_frag_offset; | |
1909 | int i; | |
1910 | struct insn_label_list *l; | |
1911 | ||
1912 | old_frag = frag_now; | |
1913 | old_frag_offset = frag_now_fix (); | |
1914 | ||
1915 | for (i = 0; i < nops; i++) | |
1916 | emit_nop (); | |
1917 | ||
1918 | if (listing) | |
1919 | { | |
1920 | listing_prev_line (); | |
1921 | /* We may be at the start of a variant frag. In case we | |
1922 | are, make sure there is enough space for the frag | |
1923 | after the frags created by listing_prev_line. The | |
1924 | argument to frag_grow here must be at least as large | |
1925 | as the argument to all other calls to frag_grow in | |
1926 | this file. We don't have to worry about being in the | |
1927 | middle of a variant frag, because the variants insert | |
1928 | all needed nop instructions themselves. */ | |
1929 | frag_grow (40); | |
1930 | } | |
1931 | ||
1932 | for (l = insn_labels; l != NULL; l = l->next) | |
1933 | { | |
98aa84af AM |
1934 | valueT val; |
1935 | ||
252b5132 | 1936 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1937 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1938 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1939 | /* mips16 text labels are stored as odd. */ |
1940 | if (mips_opts.mips16) | |
f9419b05 | 1941 | ++val; |
98aa84af | 1942 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1943 | } |
1944 | ||
1945 | #ifndef NO_ECOFF_DEBUGGING | |
1946 | if (ECOFF_DEBUGGING) | |
1947 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1948 | #endif | |
1949 | } | |
1950 | else if (prev_nop_frag != NULL) | |
1951 | { | |
1952 | /* We have a frag holding nops we may be able to remove. If | |
1953 | we don't need any nops, we can decrease the size of | |
1954 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1955 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1956 | if (prev_nop_frag_since == 0) |
1957 | { | |
1958 | if (nops == 0) | |
1959 | { | |
1960 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1961 | --prev_nop_frag_holds; | |
1962 | } | |
1963 | else | |
1964 | prev_nop_frag_required += nops; | |
1965 | } | |
1966 | else | |
1967 | { | |
1968 | if (prev_prev_nop == 0) | |
1969 | { | |
1970 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1971 | --prev_nop_frag_holds; | |
1972 | } | |
1973 | else | |
1974 | ++prev_nop_frag_required; | |
1975 | } | |
1976 | ||
1977 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1978 | prev_nop_frag = NULL; | |
1979 | ||
1980 | ++prev_nop_frag_since; | |
1981 | ||
1982 | /* Sanity check: by the time we reach the second instruction | |
1983 | after prev_nop_frag, we should have used up all the nops | |
1984 | one way or another. */ | |
1985 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1986 | } | |
1987 | } | |
1988 | ||
895921c9 MR |
1989 | /* Record the frag type before frag_var. */ |
1990 | if (prev_insn_frag) | |
1991 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
1992 | ||
4d7206a2 | 1993 | if (address_expr |
0b25d3e6 | 1994 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
1995 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
1996 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
1997 | && mips_relax_branch | |
1998 | /* Don't try branch relaxation within .set nomacro, or within | |
1999 | .set noat if we use $at for PIC computations. If it turns | |
2000 | out that the branch was out-of-range, we'll get an error. */ | |
2001 | && !mips_opts.warn_about_macros | |
2002 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2003 | && !mips_opts.mips16) | |
2004 | { | |
895921c9 | 2005 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2006 | f = frag_var (rs_machine_dependent, |
2007 | relaxed_branch_length | |
2008 | (NULL, NULL, | |
2009 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2010 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2011 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2012 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2013 | pinfo & INSN_COND_BRANCH_LIKELY, |
2014 | pinfo & INSN_WRITE_GPR_31, | |
2015 | 0), | |
2016 | address_expr->X_add_symbol, | |
2017 | address_expr->X_add_number, | |
2018 | 0); | |
2019 | *reloc_type = BFD_RELOC_UNUSED; | |
2020 | } | |
2021 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2022 | { |
2023 | /* We need to set up a variant frag. */ | |
2024 | assert (mips_opts.mips16 && address_expr != NULL); | |
2025 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2026 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2027 | mips16_small, mips16_ext, |
2028 | (prev_pinfo | |
2029 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2030 | (*prev_insn_reloc_type |
252b5132 | 2031 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2032 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2033 | } |
252b5132 RH |
2034 | else if (mips_opts.mips16 |
2035 | && ! ip->use_extend | |
f6688943 | 2036 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2037 | { |
2038 | /* Make sure there is enough room to swap this instruction with | |
2039 | a following jump instruction. */ | |
2040 | frag_grow (6); | |
2041 | f = frag_more (2); | |
2042 | } | |
2043 | else | |
2044 | { | |
2045 | if (mips_opts.mips16 | |
2046 | && mips_opts.noreorder | |
2047 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2048 | as_warn (_("extended instruction in delay slot")); | |
2049 | ||
4d7206a2 RS |
2050 | if (mips_relax.sequence) |
2051 | { | |
2052 | /* If we've reached the end of this frag, turn it into a variant | |
2053 | frag and record the information for the instructions we've | |
2054 | written so far. */ | |
2055 | if (frag_room () < 4) | |
2056 | relax_close_frag (); | |
2057 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2058 | } | |
2059 | ||
584892a6 RS |
2060 | if (mips_relax.sequence != 2) |
2061 | mips_macro_warning.sizes[0] += 4; | |
2062 | if (mips_relax.sequence != 1) | |
2063 | mips_macro_warning.sizes[1] += 4; | |
2064 | ||
252b5132 RH |
2065 | f = frag_more (4); |
2066 | } | |
2067 | ||
f6688943 TS |
2068 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2069 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2070 | { |
2071 | if (address_expr->X_op == O_constant) | |
2072 | { | |
4db1a35d | 2073 | valueT tmp; |
f6688943 TS |
2074 | |
2075 | switch (*reloc_type) | |
252b5132 RH |
2076 | { |
2077 | case BFD_RELOC_32: | |
2078 | ip->insn_opcode |= address_expr->X_add_number; | |
2079 | break; | |
2080 | ||
f6688943 | 2081 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2082 | tmp = (address_expr->X_add_number |
2083 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2084 | tmp >>= 16; |
2085 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2086 | break; | |
2087 | ||
2088 | case BFD_RELOC_MIPS_HIGHER: | |
2089 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2090 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2091 | break; | |
2092 | ||
2093 | case BFD_RELOC_HI16_S: | |
2094 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2095 | >> 16) & 0xffff; | |
2096 | break; | |
2097 | ||
2098 | case BFD_RELOC_HI16: | |
2099 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2100 | break; | |
2101 | ||
252b5132 | 2102 | case BFD_RELOC_LO16: |
ed6fb7bd | 2103 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2104 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2105 | break; | |
2106 | ||
2107 | case BFD_RELOC_MIPS_JMP: | |
2108 | if ((address_expr->X_add_number & 3) != 0) | |
2109 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2110 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2111 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2112 | as_bad (_("jump address range overflow (0x%lx)"), |
2113 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2114 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2115 | break; | |
2116 | ||
2117 | case BFD_RELOC_MIPS16_JMP: | |
2118 | if ((address_expr->X_add_number & 3) != 0) | |
2119 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2120 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2121 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2122 | as_bad (_("jump address range overflow (0x%lx)"), |
2123 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2124 | ip->insn_opcode |= |
2125 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2126 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2127 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2128 | break; | |
2129 | ||
252b5132 RH |
2130 | case BFD_RELOC_16_PCREL_S2: |
2131 | goto need_reloc; | |
2132 | ||
2133 | default: | |
2134 | internalError (); | |
2135 | } | |
2136 | } | |
2137 | else | |
252b5132 | 2138 | need_reloc: |
4d7206a2 RS |
2139 | { |
2140 | reloc_howto_type *howto; | |
2141 | int i; | |
34ce925e | 2142 | |
4d7206a2 RS |
2143 | /* In a compound relocation, it is the final (outermost) |
2144 | operator that determines the relocated field. */ | |
2145 | for (i = 1; i < 3; i++) | |
2146 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2147 | break; | |
34ce925e | 2148 | |
4d7206a2 RS |
2149 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2150 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2151 | bfd_get_reloc_size(howto), | |
2152 | address_expr, | |
2153 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2154 | reloc_type[0]); | |
2155 | ||
2156 | /* These relocations can have an addend that won't fit in | |
2157 | 4 octets for 64bit assembly. */ | |
2158 | if (HAVE_64BIT_GPRS | |
2159 | && ! howto->partial_inplace | |
2160 | && (reloc_type[0] == BFD_RELOC_16 | |
2161 | || reloc_type[0] == BFD_RELOC_32 | |
2162 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2163 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2164 | || reloc_type[0] == BFD_RELOC_LO16 | |
2165 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2166 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2167 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2168 | || reloc_type[0] == BFD_RELOC_64 | |
2169 | || reloc_type[0] == BFD_RELOC_CTOR | |
2170 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2171 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2172 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2173 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2174 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2175 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
2176 | fixp[0]->fx_no_overflow = 1; | |
2177 | ||
2178 | if (mips_relax.sequence) | |
2179 | { | |
2180 | if (mips_relax.first_fixup == 0) | |
2181 | mips_relax.first_fixup = fixp[0]; | |
2182 | } | |
2183 | else if (reloc_needs_lo_p (*reloc_type)) | |
2184 | { | |
2185 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2186 | |
4d7206a2 RS |
2187 | /* Reuse the last entry if it already has a matching %lo. */ |
2188 | hi_fixup = mips_hi_fixup_list; | |
2189 | if (hi_fixup == 0 | |
2190 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2191 | { | |
2192 | hi_fixup = ((struct mips_hi_fixup *) | |
2193 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2194 | hi_fixup->next = mips_hi_fixup_list; | |
2195 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2196 | } |
4d7206a2 RS |
2197 | hi_fixup->fixp = fixp[0]; |
2198 | hi_fixup->seg = now_seg; | |
2199 | } | |
f6688943 | 2200 | |
4d7206a2 RS |
2201 | /* Add fixups for the second and third relocations, if given. |
2202 | Note that the ABI allows the second relocation to be | |
2203 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2204 | moment we only use RSS_UNDEF, but we could add support | |
2205 | for the others if it ever becomes necessary. */ | |
2206 | for (i = 1; i < 3; i++) | |
2207 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2208 | { | |
2209 | address_expr->X_op = O_absent; | |
2210 | address_expr->X_add_symbol = 0; | |
2211 | address_expr->X_add_number = 0; | |
34ce925e | 2212 | |
4d7206a2 RS |
2213 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, |
2214 | fixp[0]->fx_size, address_expr, | |
2215 | FALSE, reloc_type[i]); | |
2216 | } | |
252b5132 RH |
2217 | } |
2218 | } | |
2219 | ||
2220 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2221 | { |
2222 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2223 | #ifdef OBJ_ELF | |
2224 | dwarf2_emit_insn (4); | |
2225 | #endif | |
2226 | } | |
f6688943 | 2227 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2228 | { |
2229 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2230 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2231 | #ifdef OBJ_ELF |
2232 | dwarf2_emit_insn (4); | |
2233 | #endif | |
252b5132 RH |
2234 | } |
2235 | else | |
2236 | { | |
2237 | if (ip->use_extend) | |
2238 | { | |
2239 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2240 | f += 2; | |
2241 | } | |
2242 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2243 | #ifdef OBJ_ELF |
2244 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2245 | #endif | |
252b5132 RH |
2246 | } |
2247 | ||
2248 | /* Update the register mask information. */ | |
2249 | if (! mips_opts.mips16) | |
2250 | { | |
2251 | if (pinfo & INSN_WRITE_GPR_D) | |
2252 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2253 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2254 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2255 | if (pinfo & INSN_READ_GPR_S) | |
2256 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2257 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2258 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2259 | if (pinfo & INSN_WRITE_FPR_D) |
2260 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2261 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2262 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2263 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2264 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2265 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2266 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2267 | if (pinfo & INSN_COP) | |
2268 | { | |
bdaaa2e1 KH |
2269 | /* We don't keep enough information to sort these cases out. |
2270 | The itbl support does keep this information however, although | |
2271 | we currently don't support itbl fprmats as part of the cop | |
2272 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2273 | } |
2274 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2275 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2276 | } |
2277 | else | |
2278 | { | |
2279 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2280 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2281 | & MIPS16OP_MASK_RX); | |
2282 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2283 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2284 | & MIPS16OP_MASK_RY); | |
2285 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2286 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2287 | & MIPS16OP_MASK_RZ); | |
2288 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2289 | mips_gprmask |= 1 << TREG; | |
2290 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2291 | mips_gprmask |= 1 << SP; | |
2292 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2293 | mips_gprmask |= 1 << RA; | |
2294 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2295 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2296 | if (pinfo & MIPS16_INSN_READ_Z) | |
2297 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2298 | & MIPS16OP_MASK_MOVE32Z); | |
2299 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2300 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2301 | & MIPS16OP_MASK_REGR32); | |
2302 | } | |
2303 | ||
4d7206a2 | 2304 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2305 | { |
2306 | /* Filling the branch delay slot is more complex. We try to | |
2307 | switch the branch with the previous instruction, which we can | |
2308 | do if the previous instruction does not set up a condition | |
2309 | that the branch tests and if the branch is not itself the | |
2310 | target of any branch. */ | |
2311 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2312 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2313 | { | |
2314 | if (mips_optimize < 2 | |
2315 | /* If we have seen .set volatile or .set nomove, don't | |
2316 | optimize. */ | |
2317 | || mips_opts.nomove != 0 | |
2318 | /* If we had to emit any NOP instructions, then we | |
2319 | already know we can not swap. */ | |
2320 | || nops != 0 | |
2321 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2322 | swap. */ |
252b5132 RH |
2323 | || ! prev_insn_valid |
2324 | /* If the previous insn is already in a branch delay | |
2325 | slot, then we can not swap. */ | |
2326 | || prev_insn_is_delay_slot | |
2327 | /* If the previous previous insn was in a .set | |
2328 | noreorder, we can't swap. Actually, the MIPS | |
2329 | assembler will swap in this situation. However, gcc | |
2330 | configured -with-gnu-as will generate code like | |
2331 | .set noreorder | |
2332 | lw $4,XXX | |
2333 | .set reorder | |
2334 | INSN | |
2335 | bne $4,$0,foo | |
2336 | in which we can not swap the bne and INSN. If gcc is | |
2337 | not configured -with-gnu-as, it does not output the | |
2338 | .set pseudo-ops. We don't have to check | |
2339 | prev_insn_unreordered, because prev_insn_valid will | |
2340 | be 0 in that case. We don't want to use | |
2341 | prev_prev_insn_valid, because we do want to be able | |
2342 | to swap at the start of a function. */ | |
2343 | || prev_prev_insn_unreordered | |
2344 | /* If the branch is itself the target of a branch, we | |
2345 | can not swap. We cheat on this; all we check for is | |
2346 | whether there is a label on this instruction. If | |
2347 | there are any branches to anything other than a | |
2348 | label, users must use .set noreorder. */ | |
2349 | || insn_labels != NULL | |
895921c9 MR |
2350 | /* If the previous instruction is in a variant frag |
2351 | other than this branch's one, we cannot do the swap. | |
2352 | This does not apply to the mips16, which uses variant | |
2353 | frags for different purposes. */ | |
252b5132 | 2354 | || (! mips_opts.mips16 |
895921c9 | 2355 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2356 | /* If the branch reads the condition codes, we don't |
2357 | even try to swap, because in the sequence | |
2358 | ctc1 $X,$31 | |
2359 | INSN | |
2360 | INSN | |
2361 | bc1t LABEL | |
2362 | we can not swap, and I don't feel like handling that | |
2363 | case. */ | |
2364 | || (! mips_opts.mips16 | |
81912461 ILT |
2365 | && (pinfo & INSN_READ_COND_CODE) |
2366 | && ! cop_interlocks) | |
252b5132 | 2367 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2368 | delay slot, because the target of the branch might |
252b5132 RH |
2369 | interfere with that instruction. */ |
2370 | || (! mips_opts.mips16 | |
252b5132 | 2371 | && (prev_pinfo |
bdaaa2e1 | 2372 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2373 | & (INSN_LOAD_COPROC_DELAY |
2374 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2375 | | INSN_WRITE_COND_CODE)) |
2376 | && ! cop_interlocks) | |
252b5132 | 2377 | || (! (hilo_interlocks |
048cdf86 | 2378 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2379 | && (prev_pinfo |
2380 | & (INSN_READ_LO | |
2381 | | INSN_READ_HI))) | |
2382 | || (! mips_opts.mips16 | |
81912461 ILT |
2383 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2384 | && ! gpr_interlocks) | |
252b5132 | 2385 | || (! mips_opts.mips16 |
bdaaa2e1 | 2386 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2387 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2388 | && ! cop_mem_interlocks) | |
252b5132 RH |
2389 | /* We can not swap with a branch instruction. */ |
2390 | || (prev_pinfo | |
2391 | & (INSN_UNCOND_BRANCH_DELAY | |
2392 | | INSN_COND_BRANCH_DELAY | |
2393 | | INSN_COND_BRANCH_LIKELY)) | |
2394 | /* We do not swap with a trap instruction, since it | |
2395 | complicates trap handlers to have the trap | |
2396 | instruction be in a delay slot. */ | |
2397 | || (prev_pinfo & INSN_TRAP) | |
2398 | /* If the branch reads a register that the previous | |
2399 | instruction sets, we can not swap. */ | |
2400 | || (! mips_opts.mips16 | |
2401 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2402 | && insn_uses_reg (ip, | |
2403 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2404 | & OP_MASK_RT), | |
2405 | MIPS_GR_REG)) | |
2406 | || (! mips_opts.mips16 | |
2407 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2408 | && insn_uses_reg (ip, | |
2409 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2410 | & OP_MASK_RD), | |
2411 | MIPS_GR_REG)) | |
2412 | || (mips_opts.mips16 | |
2413 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2414 | && insn_uses_reg (ip, | |
2415 | ((prev_insn.insn_opcode | |
2416 | >> MIPS16OP_SH_RX) | |
2417 | & MIPS16OP_MASK_RX), | |
2418 | MIPS16_REG)) | |
2419 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2420 | && insn_uses_reg (ip, | |
2421 | ((prev_insn.insn_opcode | |
2422 | >> MIPS16OP_SH_RY) | |
2423 | & MIPS16OP_MASK_RY), | |
2424 | MIPS16_REG)) | |
2425 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2426 | && insn_uses_reg (ip, | |
2427 | ((prev_insn.insn_opcode | |
2428 | >> MIPS16OP_SH_RZ) | |
2429 | & MIPS16OP_MASK_RZ), | |
2430 | MIPS16_REG)) | |
2431 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2432 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2433 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2434 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2435 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2436 | && insn_uses_reg (ip, | |
2437 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2438 | insn_opcode), | |
2439 | MIPS_GR_REG)))) | |
2440 | /* If the branch writes a register that the previous | |
2441 | instruction sets, we can not swap (we know that | |
2442 | branches write only to RD or to $31). */ | |
2443 | || (! mips_opts.mips16 | |
2444 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2445 | && (((pinfo & INSN_WRITE_GPR_D) | |
2446 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2447 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2448 | || ((pinfo & INSN_WRITE_GPR_31) | |
2449 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2450 | & OP_MASK_RT) | |
f9419b05 | 2451 | == RA)))) |
252b5132 RH |
2452 | || (! mips_opts.mips16 |
2453 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2454 | && (((pinfo & INSN_WRITE_GPR_D) | |
2455 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2456 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2457 | || ((pinfo & INSN_WRITE_GPR_31) | |
2458 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2459 | & OP_MASK_RD) | |
f9419b05 | 2460 | == RA)))) |
252b5132 RH |
2461 | || (mips_opts.mips16 |
2462 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2463 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2464 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2465 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2466 | == RA)))) | |
2467 | /* If the branch writes a register that the previous | |
2468 | instruction reads, we can not swap (we know that | |
2469 | branches only write to RD or to $31). */ | |
2470 | || (! mips_opts.mips16 | |
2471 | && (pinfo & INSN_WRITE_GPR_D) | |
2472 | && insn_uses_reg (&prev_insn, | |
2473 | ((ip->insn_opcode >> OP_SH_RD) | |
2474 | & OP_MASK_RD), | |
2475 | MIPS_GR_REG)) | |
2476 | || (! mips_opts.mips16 | |
2477 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2478 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2479 | || (mips_opts.mips16 |
2480 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2481 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2482 | /* If we are generating embedded PIC code, the branch | |
2483 | might be expanded into a sequence which uses $at, so | |
2484 | we can't swap with an instruction which reads it. */ | |
2485 | || (mips_pic == EMBEDDED_PIC | |
2486 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2487 | /* If the previous previous instruction has a load | |
2488 | delay, and sets a register that the branch reads, we | |
2489 | can not swap. */ | |
2490 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2491 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2492 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2493 | && ! cop_interlocks) | |
2494 | || ((prev_prev_insn.insn_mo->pinfo | |
2495 | & INSN_LOAD_MEMORY_DELAY) | |
2496 | && ! gpr_interlocks)) | |
252b5132 RH |
2497 | && insn_uses_reg (ip, |
2498 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2499 | & OP_MASK_RT), | |
2500 | MIPS_GR_REG)) | |
2501 | /* If one instruction sets a condition code and the | |
2502 | other one uses a condition code, we can not swap. */ | |
2503 | || ((pinfo & INSN_READ_COND_CODE) | |
2504 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2505 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2506 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2507 | /* If the previous instruction uses the PC, we can not | |
2508 | swap. */ | |
2509 | || (mips_opts.mips16 | |
2510 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2511 | /* If the previous instruction was extended, we can not | |
2512 | swap. */ | |
2513 | || (mips_opts.mips16 && prev_insn_extended) | |
2514 | /* If the previous instruction had a fixup in mips16 | |
2515 | mode, we can not swap. This normally means that the | |
2516 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2517 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2518 | /* If the previous instruction is a sync, sync.l, or |
2519 | sync.p, we can not swap. */ | |
f173e82e | 2520 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2521 | { |
2522 | /* We could do even better for unconditional branches to | |
2523 | portions of this object file; we could pick up the | |
2524 | instruction at the destination, put it in the delay | |
2525 | slot, and bump the destination address. */ | |
2526 | emit_nop (); | |
2527 | /* Update the previous insn information. */ | |
2528 | prev_prev_insn = *ip; | |
2529 | prev_insn.insn_mo = &dummy_opcode; | |
2530 | } | |
2531 | else | |
2532 | { | |
2533 | /* It looks like we can actually do the swap. */ | |
2534 | if (! mips_opts.mips16) | |
2535 | { | |
2536 | char *prev_f; | |
2537 | char temp[4]; | |
2538 | ||
2539 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2540 | if (!relaxed_branch) |
2541 | { | |
2542 | /* If this is not a relaxed branch, then just | |
2543 | swap the instructions. */ | |
2544 | memcpy (temp, prev_f, 4); | |
2545 | memcpy (prev_f, f, 4); | |
2546 | memcpy (f, temp, 4); | |
2547 | } | |
2548 | else | |
2549 | { | |
2550 | /* If this is a relaxed branch, then we move the | |
2551 | instruction to be placed in the delay slot to | |
2552 | the current frag, shrinking the fixed part of | |
2553 | the originating frag. If the branch occupies | |
2554 | the tail of the latter, we move it backwards, | |
2555 | into the space freed by the moved instruction. */ | |
2556 | f = frag_more (4); | |
2557 | memcpy (f, prev_f, 4); | |
2558 | prev_insn_frag->fr_fix -= 4; | |
2559 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2560 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2561 | } | |
2562 | ||
f6688943 TS |
2563 | if (prev_insn_fixp[0]) |
2564 | { | |
2565 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2566 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2567 | } | |
2568 | if (prev_insn_fixp[1]) | |
2569 | { | |
2570 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2571 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2572 | } | |
2573 | if (prev_insn_fixp[2]) | |
252b5132 | 2574 | { |
f6688943 TS |
2575 | prev_insn_fixp[2]->fx_frag = frag_now; |
2576 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2577 | } |
f5040a92 AO |
2578 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2579 | && prev_insn_frag != frag_now | |
2580 | && (prev_insn_fixp[0]->fx_r_type | |
2581 | == BFD_RELOC_MIPS_GOT_DISP | |
2582 | || (prev_insn_fixp[0]->fx_r_type | |
2583 | == BFD_RELOC_MIPS_CALL16))) | |
2584 | { | |
2585 | /* To avoid confusion in tc_gen_reloc, we must | |
2586 | ensure that this does not become a variant | |
2587 | frag. */ | |
2588 | force_new_frag = TRUE; | |
2589 | } | |
895921c9 MR |
2590 | |
2591 | if (!relaxed_branch) | |
f6688943 | 2592 | { |
895921c9 MR |
2593 | if (fixp[0]) |
2594 | { | |
2595 | fixp[0]->fx_frag = prev_insn_frag; | |
2596 | fixp[0]->fx_where = prev_insn_where; | |
2597 | } | |
2598 | if (fixp[1]) | |
2599 | { | |
2600 | fixp[1]->fx_frag = prev_insn_frag; | |
2601 | fixp[1]->fx_where = prev_insn_where; | |
2602 | } | |
2603 | if (fixp[2]) | |
2604 | { | |
2605 | fixp[2]->fx_frag = prev_insn_frag; | |
2606 | fixp[2]->fx_where = prev_insn_where; | |
2607 | } | |
f6688943 | 2608 | } |
895921c9 | 2609 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2610 | { |
895921c9 MR |
2611 | if (fixp[0]) |
2612 | fixp[0]->fx_where -= 4; | |
2613 | if (fixp[1]) | |
2614 | fixp[1]->fx_where -= 4; | |
2615 | if (fixp[2]) | |
2616 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2617 | } |
2618 | } | |
2619 | else | |
2620 | { | |
2621 | char *prev_f; | |
2622 | char temp[2]; | |
2623 | ||
f6688943 TS |
2624 | assert (prev_insn_fixp[0] == NULL); |
2625 | assert (prev_insn_fixp[1] == NULL); | |
2626 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2627 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2628 | memcpy (temp, prev_f, 2); | |
2629 | memcpy (prev_f, f, 2); | |
f6688943 | 2630 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2631 | { |
f6688943 | 2632 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2633 | memcpy (f, temp, 2); |
2634 | } | |
2635 | else | |
2636 | { | |
2637 | memcpy (f, f + 2, 2); | |
2638 | memcpy (f + 2, temp, 2); | |
2639 | } | |
f6688943 TS |
2640 | if (fixp[0]) |
2641 | { | |
2642 | fixp[0]->fx_frag = prev_insn_frag; | |
2643 | fixp[0]->fx_where = prev_insn_where; | |
2644 | } | |
2645 | if (fixp[1]) | |
2646 | { | |
2647 | fixp[1]->fx_frag = prev_insn_frag; | |
2648 | fixp[1]->fx_where = prev_insn_where; | |
2649 | } | |
2650 | if (fixp[2]) | |
252b5132 | 2651 | { |
f6688943 TS |
2652 | fixp[2]->fx_frag = prev_insn_frag; |
2653 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2654 | } |
2655 | } | |
2656 | ||
2657 | /* Update the previous insn information; leave prev_insn | |
2658 | unchanged. */ | |
2659 | prev_prev_insn = *ip; | |
2660 | } | |
2661 | prev_insn_is_delay_slot = 1; | |
2662 | ||
2663 | /* If that was an unconditional branch, forget the previous | |
2664 | insn information. */ | |
2665 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2666 | { | |
2667 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2668 | prev_insn.insn_mo = &dummy_opcode; | |
2669 | } | |
2670 | ||
f6688943 TS |
2671 | prev_insn_fixp[0] = NULL; |
2672 | prev_insn_fixp[1] = NULL; | |
2673 | prev_insn_fixp[2] = NULL; | |
2674 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2675 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2676 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2677 | prev_insn_extended = 0; |
2678 | } | |
2679 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2680 | { | |
2681 | /* We don't yet optimize a branch likely. What we should do | |
2682 | is look at the target, copy the instruction found there | |
2683 | into the delay slot, and increment the branch to jump to | |
2684 | the next instruction. */ | |
2685 | emit_nop (); | |
2686 | /* Update the previous insn information. */ | |
2687 | prev_prev_insn = *ip; | |
2688 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2689 | prev_insn_fixp[0] = NULL; |
2690 | prev_insn_fixp[1] = NULL; | |
2691 | prev_insn_fixp[2] = NULL; | |
2692 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2693 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2694 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2695 | prev_insn_extended = 0; |
2696 | } | |
2697 | else | |
2698 | { | |
2699 | /* Update the previous insn information. */ | |
2700 | if (nops > 0) | |
2701 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2702 | else | |
2703 | prev_prev_insn = prev_insn; | |
2704 | prev_insn = *ip; | |
2705 | ||
2706 | /* Any time we see a branch, we always fill the delay slot | |
2707 | immediately; since this insn is not a branch, we know it | |
2708 | is not in a delay slot. */ | |
2709 | prev_insn_is_delay_slot = 0; | |
2710 | ||
f6688943 TS |
2711 | prev_insn_fixp[0] = fixp[0]; |
2712 | prev_insn_fixp[1] = fixp[1]; | |
2713 | prev_insn_fixp[2] = fixp[2]; | |
2714 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2715 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2716 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2717 | if (mips_opts.mips16) |
2718 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2719 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2720 | } |
2721 | ||
2722 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2723 | prev_insn_unreordered = 0; | |
2724 | prev_insn_frag = frag_now; | |
2725 | prev_insn_where = f - frag_now->fr_literal; | |
2726 | prev_insn_valid = 1; | |
2727 | } | |
4d7206a2 | 2728 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2729 | { |
2730 | /* We need to record a bit of information even when we are not | |
2731 | reordering, in order to determine the base address for mips16 | |
2732 | PC relative relocs. */ | |
2733 | prev_prev_insn = prev_insn; | |
2734 | prev_insn = *ip; | |
f6688943 TS |
2735 | prev_insn_reloc_type[0] = reloc_type[0]; |
2736 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2737 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2738 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2739 | prev_insn_unreordered = 1; | |
2740 | } | |
2741 | ||
2742 | /* We just output an insn, so the next one doesn't have a label. */ | |
2743 | mips_clear_insn_labels (); | |
252b5132 RH |
2744 | } |
2745 | ||
2746 | /* This function forgets that there was any previous instruction or | |
2747 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2748 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2749 | |
2750 | static void | |
17a2f251 | 2751 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2752 | { |
2753 | if (! preserve) | |
2754 | { | |
2755 | prev_insn.insn_mo = &dummy_opcode; | |
2756 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2757 | prev_nop_frag = NULL; | |
2758 | prev_nop_frag_holds = 0; | |
2759 | prev_nop_frag_required = 0; | |
2760 | prev_nop_frag_since = 0; | |
2761 | } | |
2762 | prev_insn_valid = 0; | |
2763 | prev_insn_is_delay_slot = 0; | |
2764 | prev_insn_unreordered = 0; | |
2765 | prev_insn_extended = 0; | |
f6688943 TS |
2766 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2767 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2768 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2769 | prev_prev_insn_unreordered = 0; |
2770 | mips_clear_insn_labels (); | |
2771 | } | |
2772 | ||
2773 | /* This function must be called whenever we turn on noreorder or emit | |
2774 | something other than instructions. It inserts any NOPS which might | |
2775 | be needed by the previous instruction, and clears the information | |
2776 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2777 | instructions are to follow. */ |
252b5132 RH |
2778 | |
2779 | static void | |
17a2f251 | 2780 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2781 | { |
2782 | if (! mips_opts.noreorder) | |
2783 | { | |
2784 | int nops; | |
2785 | ||
2786 | nops = 0; | |
2787 | if ((! mips_opts.mips16 | |
81912461 ILT |
2788 | && ((prev_insn.insn_mo->pinfo |
2789 | & (INSN_LOAD_COPROC_DELAY | |
2790 | | INSN_COPROC_MOVE_DELAY | |
2791 | | INSN_WRITE_COND_CODE)) | |
2792 | && ! cop_interlocks)) | |
252b5132 RH |
2793 | || (! hilo_interlocks |
2794 | && (prev_insn.insn_mo->pinfo | |
2795 | & (INSN_READ_LO | |
2796 | | INSN_READ_HI))) | |
2797 | || (! mips_opts.mips16 | |
81912461 ILT |
2798 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2799 | && ! gpr_interlocks) | |
252b5132 | 2800 | || (! mips_opts.mips16 |
81912461 ILT |
2801 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2802 | && ! cop_mem_interlocks)) | |
252b5132 | 2803 | { |
beae10d5 | 2804 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2805 | ++nops; |
2806 | if ((! mips_opts.mips16 | |
81912461 ILT |
2807 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2808 | && ! cop_interlocks)) | |
252b5132 RH |
2809 | || (! hilo_interlocks |
2810 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2811 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2812 | ++nops; | |
2813 | ||
2814 | if (prev_insn_unreordered) | |
2815 | nops = 0; | |
2816 | } | |
2817 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2818 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2819 | && ! cop_interlocks)) | |
252b5132 RH |
2820 | || (! hilo_interlocks |
2821 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2822 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2823 | { | |
beae10d5 | 2824 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2825 | if (! prev_prev_insn_unreordered) |
2826 | ++nops; | |
2827 | } | |
2828 | ||
60b63b72 RS |
2829 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2830 | { | |
2831 | int min_nops = 0; | |
2832 | const char *pn = prev_insn.insn_mo->name; | |
2833 | if (strncmp(pn, "macc", 4) == 0 | |
2834 | || strncmp(pn, "dmacc", 5) == 0 | |
2835 | || strncmp(pn, "dmult", 5) == 0) | |
2836 | { | |
2837 | min_nops = 1; | |
2838 | } | |
2839 | if (nops < min_nops) | |
2840 | nops = min_nops; | |
2841 | } | |
2842 | ||
252b5132 RH |
2843 | if (nops > 0) |
2844 | { | |
2845 | struct insn_label_list *l; | |
2846 | ||
2847 | if (insns) | |
2848 | { | |
2849 | /* Record the frag which holds the nop instructions, so | |
2850 | that we can remove them if we don't need them. */ | |
2851 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2852 | prev_nop_frag = frag_now; | |
2853 | prev_nop_frag_holds = nops; | |
2854 | prev_nop_frag_required = 0; | |
2855 | prev_nop_frag_since = 0; | |
2856 | } | |
2857 | ||
2858 | for (; nops > 0; --nops) | |
2859 | emit_nop (); | |
2860 | ||
2861 | if (insns) | |
2862 | { | |
2863 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2864 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2865 | frag_wane (frag_now); |
2866 | frag_new (0); | |
2867 | } | |
2868 | ||
2869 | for (l = insn_labels; l != NULL; l = l->next) | |
2870 | { | |
98aa84af AM |
2871 | valueT val; |
2872 | ||
252b5132 | 2873 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2874 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2875 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2876 | /* mips16 text labels are stored as odd. */ |
2877 | if (mips_opts.mips16) | |
f9419b05 | 2878 | ++val; |
98aa84af | 2879 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2880 | } |
2881 | } | |
2882 | } | |
2883 | ||
2884 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2885 | if (insns) |
252b5132 RH |
2886 | mips16_mark_labels (); |
2887 | ||
2888 | mips_no_prev_insn (insns); | |
2889 | } | |
2890 | ||
584892a6 RS |
2891 | /* Set up global variables for the start of a new macro. */ |
2892 | ||
2893 | static void | |
2894 | macro_start (void) | |
2895 | { | |
2896 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2897 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2898 | && (prev_insn.insn_mo->pinfo | |
2899 | & (INSN_UNCOND_BRANCH_DELAY | |
2900 | | INSN_COND_BRANCH_DELAY | |
2901 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2902 | } | |
2903 | ||
2904 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2905 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2906 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2907 | ||
2908 | static const char * | |
2909 | macro_warning (relax_substateT subtype) | |
2910 | { | |
2911 | if (subtype & RELAX_DELAY_SLOT) | |
2912 | return _("Macro instruction expanded into multiple instructions" | |
2913 | " in a branch delay slot"); | |
2914 | else if (subtype & RELAX_NOMACRO) | |
2915 | return _("Macro instruction expanded into multiple instructions"); | |
2916 | else | |
2917 | return 0; | |
2918 | } | |
2919 | ||
2920 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2921 | ||
2922 | static void | |
2923 | macro_end (void) | |
2924 | { | |
2925 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2926 | { | |
2927 | relax_substateT subtype; | |
2928 | ||
2929 | /* Set up the relaxation warning flags. */ | |
2930 | subtype = 0; | |
2931 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2932 | subtype |= RELAX_SECOND_LONGER; | |
2933 | if (mips_opts.warn_about_macros) | |
2934 | subtype |= RELAX_NOMACRO; | |
2935 | if (mips_macro_warning.delay_slot_p) | |
2936 | subtype |= RELAX_DELAY_SLOT; | |
2937 | ||
2938 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2939 | { | |
2940 | /* Either the macro has a single implementation or both | |
2941 | implementations are longer than 4 bytes. Emit the | |
2942 | warning now. */ | |
2943 | const char *msg = macro_warning (subtype); | |
2944 | if (msg != 0) | |
2945 | as_warn (msg); | |
2946 | } | |
2947 | else | |
2948 | { | |
2949 | /* One implementation might need a warning but the other | |
2950 | definitely doesn't. */ | |
2951 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2952 | } | |
2953 | } | |
2954 | } | |
2955 | ||
252b5132 RH |
2956 | /* Build an instruction created by a macro expansion. This is passed |
2957 | a pointer to the count of instructions created so far, an | |
2958 | expression, the name of the instruction to build, an operand format | |
2959 | string, and corresponding arguments. */ | |
2960 | ||
252b5132 | 2961 | static void |
67c0d1eb | 2962 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
2963 | { |
2964 | struct mips_cl_insn insn; | |
f6688943 | 2965 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2966 | va_list args; |
252b5132 | 2967 | |
252b5132 | 2968 | va_start (args, fmt); |
252b5132 | 2969 | |
252b5132 RH |
2970 | if (mips_opts.mips16) |
2971 | { | |
67c0d1eb | 2972 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2973 | va_end (args); |
2974 | return; | |
2975 | } | |
2976 | ||
f6688943 TS |
2977 | r[0] = BFD_RELOC_UNUSED; |
2978 | r[1] = BFD_RELOC_UNUSED; | |
2979 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2980 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2981 | assert (insn.insn_mo); | |
2982 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2983 | ||
2984 | /* Search until we get a match for NAME. */ | |
2985 | while (1) | |
2986 | { | |
b34976b6 | 2987 | /* It is assumed here that macros will never generate |
deec1734 | 2988 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2989 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2990 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2991 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2992 | (mips_opts.isa | |
3396de36 | 2993 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
2994 | mips_opts.arch) |
2995 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
2996 | break; |
2997 | ||
2998 | ++insn.insn_mo; | |
2999 | assert (insn.insn_mo->name); | |
3000 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3001 | } | |
3002 | ||
3003 | insn.insn_opcode = insn.insn_mo->match; | |
3004 | for (;;) | |
3005 | { | |
3006 | switch (*fmt++) | |
3007 | { | |
3008 | case '\0': | |
3009 | break; | |
3010 | ||
3011 | case ',': | |
3012 | case '(': | |
3013 | case ')': | |
3014 | continue; | |
3015 | ||
5f74bc13 CD |
3016 | case '+': |
3017 | switch (*fmt++) | |
3018 | { | |
3019 | case 'A': | |
3020 | case 'E': | |
3021 | insn.insn_opcode |= (va_arg (args, int) | |
3022 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3023 | continue; | |
3024 | ||
3025 | case 'B': | |
3026 | case 'F': | |
3027 | /* Note that in the macro case, these arguments are already | |
3028 | in MSB form. (When handling the instruction in the | |
3029 | non-macro case, these arguments are sizes from which | |
3030 | MSB values must be calculated.) */ | |
3031 | insn.insn_opcode |= (va_arg (args, int) | |
3032 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3033 | continue; | |
3034 | ||
3035 | case 'C': | |
3036 | case 'G': | |
3037 | case 'H': | |
3038 | /* Note that in the macro case, these arguments are already | |
3039 | in MSBD form. (When handling the instruction in the | |
3040 | non-macro case, these arguments are sizes from which | |
3041 | MSBD values must be calculated.) */ | |
3042 | insn.insn_opcode |= (va_arg (args, int) | |
3043 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3044 | continue; | |
3045 | ||
3046 | default: | |
3047 | internalError (); | |
3048 | } | |
3049 | continue; | |
3050 | ||
252b5132 RH |
3051 | case 't': |
3052 | case 'w': | |
3053 | case 'E': | |
38487616 | 3054 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3055 | continue; |
3056 | ||
3057 | case 'c': | |
38487616 TS |
3058 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3059 | continue; | |
3060 | ||
252b5132 RH |
3061 | case 'T': |
3062 | case 'W': | |
38487616 | 3063 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3064 | continue; |
3065 | ||
3066 | case 'd': | |
3067 | case 'G': | |
af7ee8bf | 3068 | case 'K': |
38487616 | 3069 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3070 | continue; |
3071 | ||
4372b673 NC |
3072 | case 'U': |
3073 | { | |
3074 | int tmp = va_arg (args, int); | |
3075 | ||
38487616 TS |
3076 | insn.insn_opcode |= tmp << OP_SH_RT; |
3077 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3078 | continue; |
4372b673 NC |
3079 | } |
3080 | ||
252b5132 RH |
3081 | case 'V': |
3082 | case 'S': | |
38487616 | 3083 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3084 | continue; |
3085 | ||
3086 | case 'z': | |
3087 | continue; | |
3088 | ||
3089 | case '<': | |
38487616 | 3090 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3091 | continue; |
3092 | ||
3093 | case 'D': | |
38487616 | 3094 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3095 | continue; |
3096 | ||
3097 | case 'B': | |
38487616 | 3098 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3099 | continue; |
3100 | ||
4372b673 | 3101 | case 'J': |
38487616 | 3102 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3103 | continue; |
3104 | ||
252b5132 | 3105 | case 'q': |
38487616 | 3106 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3107 | continue; |
3108 | ||
3109 | case 'b': | |
3110 | case 's': | |
3111 | case 'r': | |
3112 | case 'v': | |
38487616 | 3113 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3114 | continue; |
3115 | ||
3116 | case 'i': | |
3117 | case 'j': | |
3118 | case 'o': | |
f6688943 | 3119 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3120 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3121 | || *r == BFD_RELOC_MIPS_LITERAL |
3122 | || *r == BFD_RELOC_MIPS_HIGHER | |
3123 | || *r == BFD_RELOC_HI16_S | |
3124 | || *r == BFD_RELOC_LO16 | |
3125 | || *r == BFD_RELOC_MIPS_GOT16 | |
3126 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3127 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3128 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3129 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3130 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3131 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3132 | || (ep->X_op == O_subtract |
f6688943 | 3133 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3134 | continue; |
3135 | ||
3136 | case 'u': | |
f6688943 | 3137 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3138 | assert (ep != NULL |
3139 | && (ep->X_op == O_constant | |
3140 | || (ep->X_op == O_symbol | |
f6688943 TS |
3141 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3142 | || *r == BFD_RELOC_HI16_S | |
3143 | || *r == BFD_RELOC_HI16 | |
3144 | || *r == BFD_RELOC_GPREL16 | |
3145 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3146 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3147 | || (ep->X_op == O_subtract |
f6688943 | 3148 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3149 | continue; |
3150 | ||
3151 | case 'p': | |
3152 | assert (ep != NULL); | |
3153 | /* | |
3154 | * This allows macro() to pass an immediate expression for | |
3155 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3156 | * Note that the expression still might come from the assembly |
3157 | * input, in which case the value is not checked for range nor | |
3158 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3159 | */ |
3160 | if (ep->X_op == O_constant) | |
3161 | { | |
3162 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3163 | ep = NULL; | |
3164 | } | |
3165 | else | |
0b25d3e6 | 3166 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3167 | continue; |
3168 | ||
3169 | case 'a': | |
3170 | assert (ep != NULL); | |
f6688943 | 3171 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3172 | continue; |
3173 | ||
3174 | case 'C': | |
3175 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3176 | continue; | |
3177 | ||
3178 | default: | |
3179 | internalError (); | |
3180 | } | |
3181 | break; | |
3182 | } | |
3183 | va_end (args); | |
f6688943 | 3184 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3185 | |
4d7206a2 | 3186 | append_insn (&insn, ep, r); |
252b5132 RH |
3187 | } |
3188 | ||
3189 | static void | |
67c0d1eb | 3190 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3191 | va_list args) |
252b5132 RH |
3192 | { |
3193 | struct mips_cl_insn insn; | |
f6688943 TS |
3194 | bfd_reloc_code_real_type r[3] |
3195 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3196 | |
252b5132 RH |
3197 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3198 | assert (insn.insn_mo); | |
3199 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3200 | ||
3201 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3202 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3203 | { | |
3204 | ++insn.insn_mo; | |
3205 | assert (insn.insn_mo->name); | |
3206 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3207 | } | |
3208 | ||
3209 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3210 | insn.use_extend = FALSE; |
252b5132 RH |
3211 | |
3212 | for (;;) | |
3213 | { | |
3214 | int c; | |
3215 | ||
3216 | c = *fmt++; | |
3217 | switch (c) | |
3218 | { | |
3219 | case '\0': | |
3220 | break; | |
3221 | ||
3222 | case ',': | |
3223 | case '(': | |
3224 | case ')': | |
3225 | continue; | |
3226 | ||
3227 | case 'y': | |
3228 | case 'w': | |
3229 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3230 | continue; | |
3231 | ||
3232 | case 'x': | |
3233 | case 'v': | |
3234 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3235 | continue; | |
3236 | ||
3237 | case 'z': | |
3238 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3239 | continue; | |
3240 | ||
3241 | case 'Z': | |
3242 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3243 | continue; | |
3244 | ||
3245 | case '0': | |
3246 | case 'S': | |
3247 | case 'P': | |
3248 | case 'R': | |
3249 | continue; | |
3250 | ||
3251 | case 'X': | |
3252 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3253 | continue; | |
3254 | ||
3255 | case 'Y': | |
3256 | { | |
3257 | int regno; | |
3258 | ||
3259 | regno = va_arg (args, int); | |
3260 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3261 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3262 | } | |
3263 | continue; | |
3264 | ||
3265 | case '<': | |
3266 | case '>': | |
3267 | case '4': | |
3268 | case '5': | |
3269 | case 'H': | |
3270 | case 'W': | |
3271 | case 'D': | |
3272 | case 'j': | |
3273 | case '8': | |
3274 | case 'V': | |
3275 | case 'C': | |
3276 | case 'U': | |
3277 | case 'k': | |
3278 | case 'K': | |
3279 | case 'p': | |
3280 | case 'q': | |
3281 | { | |
3282 | assert (ep != NULL); | |
3283 | ||
3284 | if (ep->X_op != O_constant) | |
874e8986 | 3285 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3286 | else |
3287 | { | |
b34976b6 AM |
3288 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3289 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3290 | &insn.extend); |
252b5132 | 3291 | ep = NULL; |
f6688943 | 3292 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3293 | } |
3294 | } | |
3295 | continue; | |
3296 | ||
3297 | case '6': | |
3298 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3299 | continue; | |
3300 | } | |
3301 | ||
3302 | break; | |
3303 | } | |
3304 | ||
f6688943 | 3305 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3306 | |
4d7206a2 | 3307 | append_insn (&insn, ep, r); |
252b5132 RH |
3308 | } |
3309 | ||
438c16b8 TS |
3310 | /* |
3311 | * Generate a "jalr" instruction with a relocation hint to the called | |
3312 | * function. This occurs in NewABI PIC code. | |
3313 | */ | |
3314 | static void | |
67c0d1eb | 3315 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3316 | { |
685736be | 3317 | char *f = NULL; |
b34976b6 | 3318 | |
438c16b8 | 3319 | if (HAVE_NEWABI) |
f21f8242 | 3320 | { |
cc3d92a5 | 3321 | frag_grow (8); |
f21f8242 AO |
3322 | f = frag_more (0); |
3323 | } | |
67c0d1eb | 3324 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3325 | if (HAVE_NEWABI) |
f21f8242 | 3326 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3327 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3328 | } |
3329 | ||
252b5132 RH |
3330 | /* |
3331 | * Generate a "lui" instruction. | |
3332 | */ | |
3333 | static void | |
67c0d1eb | 3334 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3335 | { |
3336 | expressionS high_expr; | |
3337 | struct mips_cl_insn insn; | |
f6688943 TS |
3338 | bfd_reloc_code_real_type r[3] |
3339 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3340 | const char *name = "lui"; |
3341 | const char *fmt = "t,u"; | |
252b5132 RH |
3342 | |
3343 | assert (! mips_opts.mips16); | |
3344 | ||
4d7206a2 | 3345 | high_expr = *ep; |
252b5132 RH |
3346 | |
3347 | if (high_expr.X_op == O_constant) | |
3348 | { | |
3349 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3350 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3351 | >> 16) & 0xffff; | |
f6688943 | 3352 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3353 | } |
78e1bb40 | 3354 | else |
252b5132 RH |
3355 | { |
3356 | assert (ep->X_op == O_symbol); | |
3357 | /* _gp_disp is a special case, used from s_cpload. */ | |
3358 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3359 | || (! HAVE_NEWABI |
3360 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3361 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3362 | } |
3363 | ||
252b5132 RH |
3364 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3365 | assert (insn.insn_mo); | |
3366 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3367 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3368 | ||
3369 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3370 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3371 | { |
3372 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3373 | append_insn (&insn, NULL, r); |
252b5132 RH |
3374 | } |
3375 | else | |
4d7206a2 | 3376 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3377 | } |
3378 | ||
885add95 CD |
3379 | /* Generate a sequence of instructions to do a load or store from a constant |
3380 | offset off of a base register (breg) into/from a target register (treg), | |
3381 | using AT if necessary. */ | |
3382 | static void | |
67c0d1eb RS |
3383 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3384 | int treg, int breg, int dbl) | |
885add95 CD |
3385 | { |
3386 | assert (ep->X_op == O_constant); | |
3387 | ||
256ab948 | 3388 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3389 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3390 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3391 | { |
d17e7bce | 3392 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3393 | as_bad (_("constant too large")); |
ae826530 | 3394 | |
1b8e29e5 TS |
3395 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3396 | - 0x80000000); | |
ae826530 | 3397 | } |
256ab948 | 3398 | |
67c1ffbe | 3399 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3400 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3401 | as_warn (_("operand overflow")); |
3402 | ||
3403 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3404 | { | |
3405 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3406 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3407 | } |
3408 | else | |
3409 | { | |
3410 | /* 32-bit offset, need multiple instructions and AT, like: | |
3411 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3412 | addu $tempreg,$tempreg,$breg | |
3413 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3414 | to handle the complete offset. */ | |
67c0d1eb RS |
3415 | macro_build_lui (ep, AT); |
3416 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3417 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3418 | |
3419 | if (mips_opts.noat) | |
3420 | as_warn (_("Macro used $at after \".set noat\"")); | |
3421 | } | |
3422 | } | |
3423 | ||
252b5132 RH |
3424 | /* set_at() |
3425 | * Generates code to set the $at register to true (one) | |
3426 | * if reg is less than the immediate expression. | |
3427 | */ | |
3428 | static void | |
67c0d1eb | 3429 | set_at (int reg, int unsignedp) |
252b5132 RH |
3430 | { |
3431 | if (imm_expr.X_op == O_constant | |
3432 | && imm_expr.X_add_number >= -0x8000 | |
3433 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3434 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3435 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3436 | else |
3437 | { | |
67c0d1eb RS |
3438 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3439 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3440 | } |
3441 | } | |
3442 | ||
13757d0c TS |
3443 | static void |
3444 | normalize_constant_expr (expressionS *ex) | |
3445 | { | |
3446 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3447 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3448 | - 0x80000000); | |
3449 | } | |
3450 | ||
252b5132 RH |
3451 | /* Warn if an expression is not a constant. */ |
3452 | ||
3453 | static void | |
17a2f251 | 3454 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3455 | { |
3456 | if (ex->X_op == O_big) | |
3457 | as_bad (_("unsupported large constant")); | |
3458 | else if (ex->X_op != O_constant) | |
3459 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3460 | |
3461 | normalize_constant_expr (ex); | |
252b5132 RH |
3462 | } |
3463 | ||
3464 | /* Count the leading zeroes by performing a binary chop. This is a | |
3465 | bulky bit of source, but performance is a LOT better for the | |
3466 | majority of values than a simple loop to count the bits: | |
3467 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3468 | if ((v) & (1 << (31 - lcnt))) | |
3469 | break; | |
3470 | However it is not code size friendly, and the gain will drop a bit | |
3471 | on certain cached systems. | |
3472 | */ | |
3473 | #define COUNT_TOP_ZEROES(v) \ | |
3474 | (((v) & ~0xffff) == 0 \ | |
3475 | ? ((v) & ~0xff) == 0 \ | |
3476 | ? ((v) & ~0xf) == 0 \ | |
3477 | ? ((v) & ~0x3) == 0 \ | |
3478 | ? ((v) & ~0x1) == 0 \ | |
3479 | ? !(v) \ | |
3480 | ? 32 \ | |
3481 | : 31 \ | |
3482 | : 30 \ | |
3483 | : ((v) & ~0x7) == 0 \ | |
3484 | ? 29 \ | |
3485 | : 28 \ | |
3486 | : ((v) & ~0x3f) == 0 \ | |
3487 | ? ((v) & ~0x1f) == 0 \ | |
3488 | ? 27 \ | |
3489 | : 26 \ | |
3490 | : ((v) & ~0x7f) == 0 \ | |
3491 | ? 25 \ | |
3492 | : 24 \ | |
3493 | : ((v) & ~0xfff) == 0 \ | |
3494 | ? ((v) & ~0x3ff) == 0 \ | |
3495 | ? ((v) & ~0x1ff) == 0 \ | |
3496 | ? 23 \ | |
3497 | : 22 \ | |
3498 | : ((v) & ~0x7ff) == 0 \ | |
3499 | ? 21 \ | |
3500 | : 20 \ | |
3501 | : ((v) & ~0x3fff) == 0 \ | |
3502 | ? ((v) & ~0x1fff) == 0 \ | |
3503 | ? 19 \ | |
3504 | : 18 \ | |
3505 | : ((v) & ~0x7fff) == 0 \ | |
3506 | ? 17 \ | |
3507 | : 16 \ | |
3508 | : ((v) & ~0xffffff) == 0 \ | |
3509 | ? ((v) & ~0xfffff) == 0 \ | |
3510 | ? ((v) & ~0x3ffff) == 0 \ | |
3511 | ? ((v) & ~0x1ffff) == 0 \ | |
3512 | ? 15 \ | |
3513 | : 14 \ | |
3514 | : ((v) & ~0x7ffff) == 0 \ | |
3515 | ? 13 \ | |
3516 | : 12 \ | |
3517 | : ((v) & ~0x3fffff) == 0 \ | |
3518 | ? ((v) & ~0x1fffff) == 0 \ | |
3519 | ? 11 \ | |
3520 | : 10 \ | |
3521 | : ((v) & ~0x7fffff) == 0 \ | |
3522 | ? 9 \ | |
3523 | : 8 \ | |
3524 | : ((v) & ~0xfffffff) == 0 \ | |
3525 | ? ((v) & ~0x3ffffff) == 0 \ | |
3526 | ? ((v) & ~0x1ffffff) == 0 \ | |
3527 | ? 7 \ | |
3528 | : 6 \ | |
3529 | : ((v) & ~0x7ffffff) == 0 \ | |
3530 | ? 5 \ | |
3531 | : 4 \ | |
3532 | : ((v) & ~0x3fffffff) == 0 \ | |
3533 | ? ((v) & ~0x1fffffff) == 0 \ | |
3534 | ? 3 \ | |
3535 | : 2 \ | |
3536 | : ((v) & ~0x7fffffff) == 0 \ | |
3537 | ? 1 \ | |
3538 | : 0) | |
3539 | ||
3540 | /* load_register() | |
67c1ffbe | 3541 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3542 | * an absolute expression value into a register. |
3543 | */ | |
3544 | static void | |
67c0d1eb | 3545 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3546 | { |
3547 | int freg; | |
3548 | expressionS hi32, lo32; | |
3549 | ||
3550 | if (ep->X_op != O_big) | |
3551 | { | |
3552 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3553 | |
3554 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3555 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3556 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3557 | { |
d17e7bce | 3558 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3559 | as_bad (_("constant too large")); |
ae826530 | 3560 | |
1b8e29e5 TS |
3561 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3562 | - 0x80000000); | |
ae826530 | 3563 | } |
256ab948 TS |
3564 | |
3565 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3566 | { |
3567 | /* We can handle 16 bit signed values with an addiu to | |
3568 | $zero. No need to ever use daddiu here, since $zero and | |
3569 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3570 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3571 | return; |
3572 | } | |
3573 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3574 | { | |
3575 | /* We can handle 16 bit unsigned values with an ori to | |
3576 | $zero. */ | |
67c0d1eb | 3577 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3578 | return; |
3579 | } | |
256ab948 | 3580 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3581 | { |
3582 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3583 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3584 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3585 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3586 | return; |
3587 | } | |
3588 | } | |
3589 | ||
3590 | /* The value is larger than 32 bits. */ | |
3591 | ||
ca4e0257 | 3592 | if (HAVE_32BIT_GPRS) |
252b5132 | 3593 | { |
956cd1d6 TS |
3594 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3595 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3596 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3597 | return; |
3598 | } | |
3599 | ||
3600 | if (ep->X_op != O_big) | |
3601 | { | |
3602 | hi32 = *ep; | |
3603 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3604 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3605 | hi32.X_add_number &= 0xffffffff; | |
3606 | lo32 = *ep; | |
3607 | lo32.X_add_number &= 0xffffffff; | |
3608 | } | |
3609 | else | |
3610 | { | |
3611 | assert (ep->X_add_number > 2); | |
3612 | if (ep->X_add_number == 3) | |
3613 | generic_bignum[3] = 0; | |
3614 | else if (ep->X_add_number > 4) | |
3615 | as_bad (_("Number larger than 64 bits")); | |
3616 | lo32.X_op = O_constant; | |
3617 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3618 | hi32.X_op = O_constant; | |
3619 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3620 | } | |
3621 | ||
3622 | if (hi32.X_add_number == 0) | |
3623 | freg = 0; | |
3624 | else | |
3625 | { | |
3626 | int shift, bit; | |
3627 | unsigned long hi, lo; | |
3628 | ||
956cd1d6 | 3629 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3630 | { |
3631 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3632 | { | |
67c0d1eb | 3633 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3634 | return; |
3635 | } | |
3636 | if (lo32.X_add_number & 0x80000000) | |
3637 | { | |
67c0d1eb | 3638 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3639 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3640 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3641 | return; |
3642 | } | |
3643 | } | |
252b5132 RH |
3644 | |
3645 | /* Check for 16bit shifted constant. We know that hi32 is | |
3646 | non-zero, so start the mask on the first bit of the hi32 | |
3647 | value. */ | |
3648 | shift = 17; | |
3649 | do | |
beae10d5 KH |
3650 | { |
3651 | unsigned long himask, lomask; | |
3652 | ||
3653 | if (shift < 32) | |
3654 | { | |
3655 | himask = 0xffff >> (32 - shift); | |
3656 | lomask = (0xffff << shift) & 0xffffffff; | |
3657 | } | |
3658 | else | |
3659 | { | |
3660 | himask = 0xffff << (shift - 32); | |
3661 | lomask = 0; | |
3662 | } | |
3663 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3664 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3665 | { | |
3666 | expressionS tmp; | |
3667 | ||
3668 | tmp.X_op = O_constant; | |
3669 | if (shift < 32) | |
3670 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3671 | | (lo32.X_add_number >> shift)); | |
3672 | else | |
3673 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3674 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3675 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3676 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3677 | return; |
3678 | } | |
f9419b05 | 3679 | ++shift; |
beae10d5 KH |
3680 | } |
3681 | while (shift <= (64 - 16)); | |
252b5132 RH |
3682 | |
3683 | /* Find the bit number of the lowest one bit, and store the | |
3684 | shifted value in hi/lo. */ | |
3685 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3686 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3687 | if (lo != 0) | |
3688 | { | |
3689 | bit = 0; | |
3690 | while ((lo & 1) == 0) | |
3691 | { | |
3692 | lo >>= 1; | |
3693 | ++bit; | |
3694 | } | |
3695 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3696 | hi >>= bit; | |
3697 | } | |
3698 | else | |
3699 | { | |
3700 | bit = 32; | |
3701 | while ((hi & 1) == 0) | |
3702 | { | |
3703 | hi >>= 1; | |
3704 | ++bit; | |
3705 | } | |
3706 | lo = hi; | |
3707 | hi = 0; | |
3708 | } | |
3709 | ||
3710 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3711 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3712 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3713 | { |
3714 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3715 | if (shift != 0) |
beae10d5 | 3716 | { |
252b5132 RH |
3717 | expressionS tmp; |
3718 | ||
3719 | /* This instruction will set the register to be all | |
3720 | ones. */ | |
beae10d5 KH |
3721 | tmp.X_op = O_constant; |
3722 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3723 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3724 | if (bit != 0) |
3725 | { | |
3726 | bit += shift; | |
67c0d1eb RS |
3727 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3728 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3729 | } |
67c0d1eb RS |
3730 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3731 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3732 | return; |
3733 | } | |
3734 | } | |
252b5132 RH |
3735 | |
3736 | /* Sign extend hi32 before calling load_register, because we can | |
3737 | generally get better code when we load a sign extended value. */ | |
3738 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3739 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3740 | load_register (reg, &hi32, 0); |
252b5132 RH |
3741 | freg = reg; |
3742 | } | |
3743 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3744 | { | |
3745 | if (freg != 0) | |
3746 | { | |
67c0d1eb | 3747 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3748 | freg = reg; |
3749 | } | |
3750 | } | |
3751 | else | |
3752 | { | |
3753 | expressionS mid16; | |
3754 | ||
956cd1d6 | 3755 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3756 | { |
67c0d1eb RS |
3757 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3758 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3759 | return; |
3760 | } | |
252b5132 RH |
3761 | |
3762 | if (freg != 0) | |
3763 | { | |
67c0d1eb | 3764 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3765 | freg = reg; |
3766 | } | |
3767 | mid16 = lo32; | |
3768 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3769 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3770 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3771 | freg = reg; |
3772 | } | |
3773 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3774 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3775 | } |
3776 | ||
3777 | /* Load an address into a register. */ | |
3778 | ||
3779 | static void | |
67c0d1eb | 3780 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3781 | { |
252b5132 RH |
3782 | if (ep->X_op != O_constant |
3783 | && ep->X_op != O_symbol) | |
3784 | { | |
3785 | as_bad (_("expression too complex")); | |
3786 | ep->X_op = O_constant; | |
3787 | } | |
3788 | ||
3789 | if (ep->X_op == O_constant) | |
3790 | { | |
67c0d1eb | 3791 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3792 | return; |
3793 | } | |
3794 | ||
3795 | if (mips_pic == NO_PIC) | |
3796 | { | |
3797 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3798 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3799 | Otherwise we want |
3800 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3801 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3802 | If we have an addend, we always use the latter form. |
76b3015f | 3803 | |
d6bc6245 TS |
3804 | With 64bit address space and a usable $at we want |
3805 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3806 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3807 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3808 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3809 | dsll32 $reg,0 | |
3a482fd5 | 3810 | daddu $reg,$reg,$at |
76b3015f | 3811 | |
c03099e6 | 3812 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3813 | on superscalar processors. |
3814 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3815 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3816 | dsll $reg,16 | |
3817 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3818 | dsll $reg,16 | |
3819 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3820 | */ | |
c9914766 | 3821 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3822 | { |
e864ceca RS |
3823 | /* ??? We don't provide a GP-relative alternative for these macros. |
3824 | It used not to be possible with the original relaxation code, | |
3825 | but it could be done now. */ | |
d6bc6245 | 3826 | |
460597ba | 3827 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 3828 | { |
67c0d1eb RS |
3829 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3830 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3831 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3832 | BFD_RELOC_MIPS_HIGHER); | |
3833 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3834 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3835 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3836 | *used_at = 1; |
3837 | } | |
3838 | else | |
3839 | { | |
67c0d1eb RS |
3840 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3841 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3842 | BFD_RELOC_MIPS_HIGHER); | |
3843 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3844 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3845 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3846 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3847 | } |
3848 | } | |
252b5132 RH |
3849 | else |
3850 | { | |
d6bc6245 TS |
3851 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3852 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3853 | { | |
4d7206a2 | 3854 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3855 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3856 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3857 | relax_switch (); |
d6bc6245 | 3858 | } |
67c0d1eb RS |
3859 | macro_build_lui (ep, reg); |
3860 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3861 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3862 | if (mips_relax.sequence) |
3863 | relax_end (); | |
d6bc6245 | 3864 | } |
252b5132 RH |
3865 | } |
3866 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3867 | { | |
3868 | expressionS ex; | |
3869 | ||
3870 | /* If this is a reference to an external symbol, we want | |
3871 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3872 | Otherwise we want | |
3873 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3874 | nop | |
3875 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3876 | If there is a constant, it must be added in after. |
3877 | ||
ed6fb7bd | 3878 | If we have NewABI, we want |
f5040a92 AO |
3879 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3880 | unless we're referencing a global symbol with a non-zero | |
3881 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3882 | if (HAVE_NEWABI) |
3883 | { | |
f5040a92 AO |
3884 | if (ep->X_add_number) |
3885 | { | |
4d7206a2 | 3886 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3887 | ep->X_add_number = 0; |
4d7206a2 | 3888 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3889 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3890 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3891 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3892 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3893 | ex.X_op = O_constant; | |
67c0d1eb | 3894 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3895 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3896 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3897 | relax_switch (); |
f5040a92 | 3898 | } |
67c0d1eb | 3899 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3900 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3901 | if (mips_relax.sequence) |
3902 | relax_end (); | |
ed6fb7bd SC |
3903 | } |
3904 | else | |
3905 | { | |
f5040a92 AO |
3906 | ex.X_add_number = ep->X_add_number; |
3907 | ep->X_add_number = 0; | |
67c0d1eb RS |
3908 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3909 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3910 | macro_build (NULL, "nop", ""); | |
4d7206a2 RS |
3911 | relax_start (ep->X_add_symbol); |
3912 | relax_switch (); | |
67c0d1eb | 3913 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3914 | BFD_RELOC_LO16); |
4d7206a2 | 3915 | relax_end (); |
ed6fb7bd | 3916 | |
f5040a92 AO |
3917 | if (ex.X_add_number != 0) |
3918 | { | |
3919 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3920 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3921 | ex.X_op = O_constant; | |
67c0d1eb | 3922 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3923 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3924 | } |
252b5132 RH |
3925 | } |
3926 | } | |
3927 | else if (mips_pic == SVR4_PIC) | |
3928 | { | |
3929 | expressionS ex; | |
252b5132 RH |
3930 | |
3931 | /* This is the large GOT case. If this is a reference to an | |
3932 | external symbol, we want | |
3933 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3934 | addu $reg,$reg,$gp | |
3935 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3936 | |
3937 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3938 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3939 | nop | |
3940 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3941 | If there is a constant, it must be added in after. |
f5040a92 AO |
3942 | |
3943 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3944 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3945 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3946 | */ |
438c16b8 TS |
3947 | if (HAVE_NEWABI) |
3948 | { | |
4d7206a2 | 3949 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3950 | ep->X_add_number = 0; |
4d7206a2 | 3951 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3952 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3953 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3954 | reg, reg, mips_gp_register); | |
3955 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3956 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3957 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3958 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3959 | else if (ex.X_add_number) | |
3960 | { | |
3961 | ex.X_op = O_constant; | |
67c0d1eb RS |
3962 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3963 | BFD_RELOC_LO16); | |
f5040a92 AO |
3964 | } |
3965 | ||
3966 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3967 | relax_switch (); |
67c0d1eb | 3968 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3969 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3970 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3971 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3972 | relax_end (); |
438c16b8 | 3973 | } |
252b5132 | 3974 | else |
438c16b8 | 3975 | { |
f5040a92 AO |
3976 | ex.X_add_number = ep->X_add_number; |
3977 | ep->X_add_number = 0; | |
4d7206a2 | 3978 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3979 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3980 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3981 | reg, reg, mips_gp_register); | |
3982 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3983 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3984 | relax_switch (); |
3985 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3986 | { |
3987 | /* We need a nop before loading from $gp. This special | |
3988 | check is required because the lui which starts the main | |
3989 | instruction stream does not refer to $gp, and so will not | |
3990 | insert the nop which may be required. */ | |
67c0d1eb | 3991 | macro_build (NULL, "nop", ""); |
438c16b8 | 3992 | } |
67c0d1eb | 3993 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3994 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
67c0d1eb RS |
3995 | macro_build (NULL, "nop", ""); |
3996 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, | |
17a2f251 | 3997 | BFD_RELOC_LO16); |
4d7206a2 | 3998 | relax_end (); |
438c16b8 | 3999 | |
f5040a92 AO |
4000 | if (ex.X_add_number != 0) |
4001 | { | |
4002 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4003 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4004 | ex.X_op = O_constant; | |
67c0d1eb RS |
4005 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4006 | BFD_RELOC_LO16); | |
f5040a92 | 4007 | } |
252b5132 RH |
4008 | } |
4009 | } | |
4010 | else if (mips_pic == EMBEDDED_PIC) | |
4011 | { | |
4012 | /* We always do | |
cdf6fd85 | 4013 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 4014 | */ |
67c0d1eb RS |
4015 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", |
4016 | reg, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
4017 | } |
4018 | else | |
4019 | abort (); | |
4020 | } | |
4021 | ||
ea1fb5dc RS |
4022 | /* Move the contents of register SOURCE into register DEST. */ |
4023 | ||
4024 | static void | |
67c0d1eb | 4025 | move_register (int dest, int source) |
ea1fb5dc | 4026 | { |
67c0d1eb RS |
4027 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4028 | dest, source, 0); | |
ea1fb5dc RS |
4029 | } |
4030 | ||
4d7206a2 RS |
4031 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
4032 | LOCAL is the sum of a symbol and a 16-bit displacement. The two | |
4033 | alternatives are: | |
4034 | ||
4035 | Global symbol Local sybmol | |
4036 | ------------- ------------ | |
4037 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4038 | ... ... | |
4039 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4040 | ||
4041 | load_got_offset emits the first instruction and add_got_offset | |
4042 | emits the second. */ | |
4043 | ||
4044 | static void | |
67c0d1eb | 4045 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4046 | { |
4047 | expressionS global; | |
4048 | ||
4049 | global = *local; | |
4050 | global.X_add_number = 0; | |
4051 | ||
4052 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4053 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4054 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4055 | relax_switch (); |
67c0d1eb RS |
4056 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4057 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4058 | relax_end (); |
4059 | } | |
4060 | ||
4061 | static void | |
67c0d1eb | 4062 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4063 | { |
4064 | expressionS global; | |
4065 | ||
4066 | global.X_op = O_constant; | |
4067 | global.X_op_symbol = NULL; | |
4068 | global.X_add_symbol = NULL; | |
4069 | global.X_add_number = local->X_add_number; | |
4070 | ||
4071 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4072 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4073 | dest, dest, BFD_RELOC_LO16); |
4074 | relax_switch (); | |
67c0d1eb | 4075 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4076 | relax_end (); |
4077 | } | |
4078 | ||
252b5132 RH |
4079 | /* |
4080 | * Build macros | |
4081 | * This routine implements the seemingly endless macro or synthesized | |
4082 | * instructions and addressing modes in the mips assembly language. Many | |
4083 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4084 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4085 | * this verbose method. Others are not simple macros but are more like |
4086 | * optimizing code generation. | |
4087 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4088 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4089 | * The ensuing load upper instructions are ommited. This implies some kind |
4090 | * of global optimization. We currently only optimize within a single macro. | |
4091 | * For many of the load and store macros if the address is specified as a | |
4092 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4093 | * first load register 'at' with zero and use it as the base register. The | |
4094 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4095 | * we're missing. | |
4096 | */ | |
4097 | static void | |
17a2f251 | 4098 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4099 | { |
4100 | register int treg, sreg, dreg, breg; | |
4101 | int tempreg; | |
4102 | int mask; | |
43841e91 | 4103 | int used_at = 0; |
252b5132 RH |
4104 | expressionS expr1; |
4105 | const char *s; | |
4106 | const char *s2; | |
4107 | const char *fmt; | |
4108 | int likely = 0; | |
4109 | int dbl = 0; | |
4110 | int coproc = 0; | |
4111 | int lr = 0; | |
4112 | int imm = 0; | |
1abe91b1 | 4113 | int call = 0; |
252b5132 | 4114 | int off; |
67c0d1eb | 4115 | offsetT maxnum; |
252b5132 | 4116 | bfd_reloc_code_real_type r; |
252b5132 RH |
4117 | int hold_mips_optimize; |
4118 | ||
4119 | assert (! mips_opts.mips16); | |
4120 | ||
4121 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4122 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4123 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4124 | mask = ip->insn_mo->mask; | |
4125 | ||
4126 | expr1.X_op = O_constant; | |
4127 | expr1.X_op_symbol = NULL; | |
4128 | expr1.X_add_symbol = NULL; | |
4129 | expr1.X_add_number = 1; | |
4130 | ||
4131 | switch (mask) | |
4132 | { | |
4133 | case M_DABS: | |
4134 | dbl = 1; | |
4135 | case M_ABS: | |
4136 | /* bgez $a0,.+12 | |
4137 | move v0,$a0 | |
4138 | sub v0,$zero,$a0 | |
4139 | */ | |
4140 | ||
b34976b6 | 4141 | mips_emit_delays (TRUE); |
252b5132 RH |
4142 | ++mips_opts.noreorder; |
4143 | mips_any_noreorder = 1; | |
4144 | ||
4145 | expr1.X_add_number = 8; | |
67c0d1eb | 4146 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4147 | if (dreg == sreg) |
67c0d1eb | 4148 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4149 | else |
67c0d1eb RS |
4150 | move_register (dreg, sreg); |
4151 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4152 | |
4153 | --mips_opts.noreorder; | |
4154 | return; | |
4155 | ||
4156 | case M_ADD_I: | |
4157 | s = "addi"; | |
4158 | s2 = "add"; | |
4159 | goto do_addi; | |
4160 | case M_ADDU_I: | |
4161 | s = "addiu"; | |
4162 | s2 = "addu"; | |
4163 | goto do_addi; | |
4164 | case M_DADD_I: | |
4165 | dbl = 1; | |
4166 | s = "daddi"; | |
4167 | s2 = "dadd"; | |
4168 | goto do_addi; | |
4169 | case M_DADDU_I: | |
4170 | dbl = 1; | |
4171 | s = "daddiu"; | |
4172 | s2 = "daddu"; | |
4173 | do_addi: | |
4174 | if (imm_expr.X_op == O_constant | |
4175 | && imm_expr.X_add_number >= -0x8000 | |
4176 | && imm_expr.X_add_number < 0x8000) | |
4177 | { | |
67c0d1eb | 4178 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4179 | return; |
4180 | } | |
67c0d1eb RS |
4181 | load_register (AT, &imm_expr, dbl); |
4182 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4183 | break; |
4184 | ||
4185 | case M_AND_I: | |
4186 | s = "andi"; | |
4187 | s2 = "and"; | |
4188 | goto do_bit; | |
4189 | case M_OR_I: | |
4190 | s = "ori"; | |
4191 | s2 = "or"; | |
4192 | goto do_bit; | |
4193 | case M_NOR_I: | |
4194 | s = ""; | |
4195 | s2 = "nor"; | |
4196 | goto do_bit; | |
4197 | case M_XOR_I: | |
4198 | s = "xori"; | |
4199 | s2 = "xor"; | |
4200 | do_bit: | |
4201 | if (imm_expr.X_op == O_constant | |
4202 | && imm_expr.X_add_number >= 0 | |
4203 | && imm_expr.X_add_number < 0x10000) | |
4204 | { | |
4205 | if (mask != M_NOR_I) | |
67c0d1eb | 4206 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4207 | else |
4208 | { | |
67c0d1eb RS |
4209 | macro_build (&imm_expr, "ori", "t,r,i", |
4210 | treg, sreg, BFD_RELOC_LO16); | |
4211 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4212 | } |
4213 | return; | |
4214 | } | |
4215 | ||
67c0d1eb RS |
4216 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4217 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4218 | break; |
4219 | ||
4220 | case M_BEQ_I: | |
4221 | s = "beq"; | |
4222 | goto beq_i; | |
4223 | case M_BEQL_I: | |
4224 | s = "beql"; | |
4225 | likely = 1; | |
4226 | goto beq_i; | |
4227 | case M_BNE_I: | |
4228 | s = "bne"; | |
4229 | goto beq_i; | |
4230 | case M_BNEL_I: | |
4231 | s = "bnel"; | |
4232 | likely = 1; | |
4233 | beq_i: | |
4234 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4235 | { | |
67c0d1eb | 4236 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4237 | return; |
4238 | } | |
67c0d1eb RS |
4239 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4240 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4241 | break; |
4242 | ||
4243 | case M_BGEL: | |
4244 | likely = 1; | |
4245 | case M_BGE: | |
4246 | if (treg == 0) | |
4247 | { | |
67c0d1eb | 4248 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4249 | return; |
4250 | } | |
4251 | if (sreg == 0) | |
4252 | { | |
67c0d1eb | 4253 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4254 | return; |
4255 | } | |
67c0d1eb RS |
4256 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4257 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4258 | break; |
4259 | ||
4260 | case M_BGTL_I: | |
4261 | likely = 1; | |
4262 | case M_BGT_I: | |
4263 | /* check for > max integer */ | |
4264 | maxnum = 0x7fffffff; | |
ca4e0257 | 4265 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4266 | { |
4267 | maxnum <<= 16; | |
4268 | maxnum |= 0xffff; | |
4269 | maxnum <<= 16; | |
4270 | maxnum |= 0xffff; | |
4271 | } | |
4272 | if (imm_expr.X_op == O_constant | |
4273 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4274 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4275 | { |
4276 | do_false: | |
4277 | /* result is always false */ | |
4278 | if (! likely) | |
67c0d1eb | 4279 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4280 | else |
67c0d1eb | 4281 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4282 | return; |
4283 | } | |
4284 | if (imm_expr.X_op != O_constant) | |
4285 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4286 | ++imm_expr.X_add_number; |
252b5132 RH |
4287 | /* FALLTHROUGH */ |
4288 | case M_BGE_I: | |
4289 | case M_BGEL_I: | |
4290 | if (mask == M_BGEL_I) | |
4291 | likely = 1; | |
4292 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4293 | { | |
67c0d1eb | 4294 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4295 | return; |
4296 | } | |
4297 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4298 | { | |
67c0d1eb | 4299 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4300 | return; |
4301 | } | |
4302 | maxnum = 0x7fffffff; | |
ca4e0257 | 4303 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4304 | { |
4305 | maxnum <<= 16; | |
4306 | maxnum |= 0xffff; | |
4307 | maxnum <<= 16; | |
4308 | maxnum |= 0xffff; | |
4309 | } | |
4310 | maxnum = - maxnum - 1; | |
4311 | if (imm_expr.X_op == O_constant | |
4312 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4313 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4314 | { |
4315 | do_true: | |
4316 | /* result is always true */ | |
4317 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4318 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4319 | return; |
4320 | } | |
67c0d1eb RS |
4321 | set_at (sreg, 0); |
4322 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4323 | break; |
4324 | ||
4325 | case M_BGEUL: | |
4326 | likely = 1; | |
4327 | case M_BGEU: | |
4328 | if (treg == 0) | |
4329 | goto do_true; | |
4330 | if (sreg == 0) | |
4331 | { | |
67c0d1eb | 4332 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4333 | "s,t,p", 0, treg); |
252b5132 RH |
4334 | return; |
4335 | } | |
67c0d1eb RS |
4336 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4337 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4338 | break; |
4339 | ||
4340 | case M_BGTUL_I: | |
4341 | likely = 1; | |
4342 | case M_BGTU_I: | |
4343 | if (sreg == 0 | |
ca4e0257 | 4344 | || (HAVE_32BIT_GPRS |
252b5132 | 4345 | && imm_expr.X_op == O_constant |
956cd1d6 | 4346 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4347 | goto do_false; |
4348 | if (imm_expr.X_op != O_constant) | |
4349 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4350 | ++imm_expr.X_add_number; |
252b5132 RH |
4351 | /* FALLTHROUGH */ |
4352 | case M_BGEU_I: | |
4353 | case M_BGEUL_I: | |
4354 | if (mask == M_BGEUL_I) | |
4355 | likely = 1; | |
4356 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4357 | goto do_true; | |
4358 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4359 | { | |
67c0d1eb | 4360 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4361 | "s,t,p", sreg, 0); |
252b5132 RH |
4362 | return; |
4363 | } | |
67c0d1eb RS |
4364 | set_at (sreg, 1); |
4365 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4366 | break; |
4367 | ||
4368 | case M_BGTL: | |
4369 | likely = 1; | |
4370 | case M_BGT: | |
4371 | if (treg == 0) | |
4372 | { | |
67c0d1eb | 4373 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4374 | return; |
4375 | } | |
4376 | if (sreg == 0) | |
4377 | { | |
67c0d1eb | 4378 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4379 | return; |
4380 | } | |
67c0d1eb RS |
4381 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4382 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4383 | break; |
4384 | ||
4385 | case M_BGTUL: | |
4386 | likely = 1; | |
4387 | case M_BGTU: | |
4388 | if (treg == 0) | |
4389 | { | |
67c0d1eb | 4390 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4391 | "s,t,p", sreg, 0); |
252b5132 RH |
4392 | return; |
4393 | } | |
4394 | if (sreg == 0) | |
4395 | goto do_false; | |
67c0d1eb RS |
4396 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4397 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4398 | break; |
4399 | ||
4400 | case M_BLEL: | |
4401 | likely = 1; | |
4402 | case M_BLE: | |
4403 | if (treg == 0) | |
4404 | { | |
67c0d1eb | 4405 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4406 | return; |
4407 | } | |
4408 | if (sreg == 0) | |
4409 | { | |
67c0d1eb | 4410 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4411 | return; |
4412 | } | |
67c0d1eb RS |
4413 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4414 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4415 | break; |
4416 | ||
4417 | case M_BLEL_I: | |
4418 | likely = 1; | |
4419 | case M_BLE_I: | |
4420 | maxnum = 0x7fffffff; | |
ca4e0257 | 4421 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4422 | { |
4423 | maxnum <<= 16; | |
4424 | maxnum |= 0xffff; | |
4425 | maxnum <<= 16; | |
4426 | maxnum |= 0xffff; | |
4427 | } | |
4428 | if (imm_expr.X_op == O_constant | |
4429 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4430 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4431 | goto do_true; |
4432 | if (imm_expr.X_op != O_constant) | |
4433 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4434 | ++imm_expr.X_add_number; |
252b5132 RH |
4435 | /* FALLTHROUGH */ |
4436 | case M_BLT_I: | |
4437 | case M_BLTL_I: | |
4438 | if (mask == M_BLTL_I) | |
4439 | likely = 1; | |
4440 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4441 | { | |
67c0d1eb | 4442 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4443 | return; |
4444 | } | |
4445 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4446 | { | |
67c0d1eb | 4447 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4448 | return; |
4449 | } | |
67c0d1eb RS |
4450 | set_at (sreg, 0); |
4451 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4452 | break; |
4453 | ||
4454 | case M_BLEUL: | |
4455 | likely = 1; | |
4456 | case M_BLEU: | |
4457 | if (treg == 0) | |
4458 | { | |
67c0d1eb | 4459 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4460 | "s,t,p", sreg, 0); |
252b5132 RH |
4461 | return; |
4462 | } | |
4463 | if (sreg == 0) | |
4464 | goto do_true; | |
67c0d1eb RS |
4465 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4466 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4467 | break; |
4468 | ||
4469 | case M_BLEUL_I: | |
4470 | likely = 1; | |
4471 | case M_BLEU_I: | |
4472 | if (sreg == 0 | |
ca4e0257 | 4473 | || (HAVE_32BIT_GPRS |
252b5132 | 4474 | && imm_expr.X_op == O_constant |
956cd1d6 | 4475 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4476 | goto do_true; |
4477 | if (imm_expr.X_op != O_constant) | |
4478 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4479 | ++imm_expr.X_add_number; |
252b5132 RH |
4480 | /* FALLTHROUGH */ |
4481 | case M_BLTU_I: | |
4482 | case M_BLTUL_I: | |
4483 | if (mask == M_BLTUL_I) | |
4484 | likely = 1; | |
4485 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4486 | goto do_false; | |
4487 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4488 | { | |
67c0d1eb | 4489 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4490 | "s,t,p", sreg, 0); |
4491 | return; | |
4492 | } | |
67c0d1eb RS |
4493 | set_at (sreg, 1); |
4494 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4495 | break; |
4496 | ||
4497 | case M_BLTL: | |
4498 | likely = 1; | |
4499 | case M_BLT: | |
4500 | if (treg == 0) | |
4501 | { | |
67c0d1eb | 4502 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4503 | return; |
4504 | } | |
4505 | if (sreg == 0) | |
4506 | { | |
67c0d1eb | 4507 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4508 | return; |
4509 | } | |
67c0d1eb RS |
4510 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4511 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4512 | break; |
4513 | ||
4514 | case M_BLTUL: | |
4515 | likely = 1; | |
4516 | case M_BLTU: | |
4517 | if (treg == 0) | |
4518 | goto do_false; | |
4519 | if (sreg == 0) | |
4520 | { | |
67c0d1eb | 4521 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4522 | "s,t,p", 0, treg); |
252b5132 RH |
4523 | return; |
4524 | } | |
67c0d1eb RS |
4525 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4526 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4527 | break; |
4528 | ||
5f74bc13 CD |
4529 | case M_DEXT: |
4530 | { | |
4531 | unsigned long pos; | |
4532 | unsigned long size; | |
4533 | ||
4534 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4535 | { | |
4536 | as_bad (_("Unsupported large constant")); | |
4537 | pos = size = 1; | |
4538 | } | |
4539 | else | |
4540 | { | |
4541 | pos = (unsigned long) imm_expr.X_add_number; | |
4542 | size = (unsigned long) imm2_expr.X_add_number; | |
4543 | } | |
4544 | ||
4545 | if (pos > 63) | |
4546 | { | |
4547 | as_bad (_("Improper position (%lu)"), pos); | |
4548 | pos = 1; | |
4549 | } | |
4550 | if (size == 0 || size > 64 | |
4551 | || (pos + size - 1) > 63) | |
4552 | { | |
4553 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4554 | size, pos); | |
4555 | size = 1; | |
4556 | } | |
4557 | ||
4558 | if (size <= 32 && pos < 32) | |
4559 | { | |
4560 | s = "dext"; | |
4561 | fmt = "t,r,+A,+C"; | |
4562 | } | |
4563 | else if (size <= 32) | |
4564 | { | |
4565 | s = "dextu"; | |
4566 | fmt = "t,r,+E,+H"; | |
4567 | } | |
4568 | else | |
4569 | { | |
4570 | s = "dextm"; | |
4571 | fmt = "t,r,+A,+G"; | |
4572 | } | |
67c0d1eb | 4573 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4574 | } |
4575 | return; | |
4576 | ||
4577 | case M_DINS: | |
4578 | { | |
4579 | unsigned long pos; | |
4580 | unsigned long size; | |
4581 | ||
4582 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4583 | { | |
4584 | as_bad (_("Unsupported large constant")); | |
4585 | pos = size = 1; | |
4586 | } | |
4587 | else | |
4588 | { | |
4589 | pos = (unsigned long) imm_expr.X_add_number; | |
4590 | size = (unsigned long) imm2_expr.X_add_number; | |
4591 | } | |
4592 | ||
4593 | if (pos > 63) | |
4594 | { | |
4595 | as_bad (_("Improper position (%lu)"), pos); | |
4596 | pos = 1; | |
4597 | } | |
4598 | if (size == 0 || size > 64 | |
4599 | || (pos + size - 1) > 63) | |
4600 | { | |
4601 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4602 | size, pos); | |
4603 | size = 1; | |
4604 | } | |
4605 | ||
4606 | if (pos < 32 && (pos + size - 1) < 32) | |
4607 | { | |
4608 | s = "dins"; | |
4609 | fmt = "t,r,+A,+B"; | |
4610 | } | |
4611 | else if (pos >= 32) | |
4612 | { | |
4613 | s = "dinsu"; | |
4614 | fmt = "t,r,+E,+F"; | |
4615 | } | |
4616 | else | |
4617 | { | |
4618 | s = "dinsm"; | |
4619 | fmt = "t,r,+A,+F"; | |
4620 | } | |
67c0d1eb RS |
4621 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4622 | pos + size - 1); | |
5f74bc13 CD |
4623 | } |
4624 | return; | |
4625 | ||
252b5132 RH |
4626 | case M_DDIV_3: |
4627 | dbl = 1; | |
4628 | case M_DIV_3: | |
4629 | s = "mflo"; | |
4630 | goto do_div3; | |
4631 | case M_DREM_3: | |
4632 | dbl = 1; | |
4633 | case M_REM_3: | |
4634 | s = "mfhi"; | |
4635 | do_div3: | |
4636 | if (treg == 0) | |
4637 | { | |
4638 | as_warn (_("Divide by zero.")); | |
4639 | if (mips_trap) | |
67c0d1eb | 4640 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4641 | else |
67c0d1eb | 4642 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4643 | return; |
4644 | } | |
4645 | ||
b34976b6 | 4646 | mips_emit_delays (TRUE); |
252b5132 RH |
4647 | ++mips_opts.noreorder; |
4648 | mips_any_noreorder = 1; | |
4649 | if (mips_trap) | |
4650 | { | |
67c0d1eb RS |
4651 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4652 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4653 | } |
4654 | else | |
4655 | { | |
4656 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4657 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4658 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4659 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4660 | } |
4661 | expr1.X_add_number = -1; | |
67c0d1eb RS |
4662 | macro_build (&expr1, dbl ? "daddiu" : "addiu", "t,r,j", AT, 0, |
4663 | BFD_RELOC_LO16); | |
252b5132 | 4664 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4665 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4666 | if (dbl) |
4667 | { | |
4668 | expr1.X_add_number = 1; | |
67c0d1eb RS |
4669 | macro_build (&expr1, "daddiu", "t,r,j", AT, 0, BFD_RELOC_LO16); |
4670 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); | |
252b5132 RH |
4671 | } |
4672 | else | |
4673 | { | |
4674 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4675 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4676 | } |
4677 | if (mips_trap) | |
4678 | { | |
67c0d1eb | 4679 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4680 | /* We want to close the noreorder block as soon as possible, so |
4681 | that later insns are available for delay slot filling. */ | |
4682 | --mips_opts.noreorder; | |
4683 | } | |
4684 | else | |
4685 | { | |
4686 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4687 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4688 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4689 | |
4690 | /* We want to close the noreorder block as soon as possible, so | |
4691 | that later insns are available for delay slot filling. */ | |
4692 | --mips_opts.noreorder; | |
4693 | ||
67c0d1eb | 4694 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4695 | } |
67c0d1eb | 4696 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4697 | break; |
4698 | ||
4699 | case M_DIV_3I: | |
4700 | s = "div"; | |
4701 | s2 = "mflo"; | |
4702 | goto do_divi; | |
4703 | case M_DIVU_3I: | |
4704 | s = "divu"; | |
4705 | s2 = "mflo"; | |
4706 | goto do_divi; | |
4707 | case M_REM_3I: | |
4708 | s = "div"; | |
4709 | s2 = "mfhi"; | |
4710 | goto do_divi; | |
4711 | case M_REMU_3I: | |
4712 | s = "divu"; | |
4713 | s2 = "mfhi"; | |
4714 | goto do_divi; | |
4715 | case M_DDIV_3I: | |
4716 | dbl = 1; | |
4717 | s = "ddiv"; | |
4718 | s2 = "mflo"; | |
4719 | goto do_divi; | |
4720 | case M_DDIVU_3I: | |
4721 | dbl = 1; | |
4722 | s = "ddivu"; | |
4723 | s2 = "mflo"; | |
4724 | goto do_divi; | |
4725 | case M_DREM_3I: | |
4726 | dbl = 1; | |
4727 | s = "ddiv"; | |
4728 | s2 = "mfhi"; | |
4729 | goto do_divi; | |
4730 | case M_DREMU_3I: | |
4731 | dbl = 1; | |
4732 | s = "ddivu"; | |
4733 | s2 = "mfhi"; | |
4734 | do_divi: | |
4735 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4736 | { | |
4737 | as_warn (_("Divide by zero.")); | |
4738 | if (mips_trap) | |
67c0d1eb | 4739 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4740 | else |
67c0d1eb | 4741 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4742 | return; |
4743 | } | |
4744 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4745 | { | |
4746 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4747 | move_register (dreg, sreg); |
252b5132 | 4748 | else |
67c0d1eb | 4749 | move_register (dreg, 0); |
252b5132 RH |
4750 | return; |
4751 | } | |
4752 | if (imm_expr.X_op == O_constant | |
4753 | && imm_expr.X_add_number == -1 | |
4754 | && s[strlen (s) - 1] != 'u') | |
4755 | { | |
4756 | if (strcmp (s2, "mflo") == 0) | |
4757 | { | |
67c0d1eb | 4758 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4759 | } |
4760 | else | |
67c0d1eb | 4761 | move_register (dreg, 0); |
252b5132 RH |
4762 | return; |
4763 | } | |
4764 | ||
67c0d1eb RS |
4765 | load_register (AT, &imm_expr, dbl); |
4766 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4767 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4768 | break; |
4769 | ||
4770 | case M_DIVU_3: | |
4771 | s = "divu"; | |
4772 | s2 = "mflo"; | |
4773 | goto do_divu3; | |
4774 | case M_REMU_3: | |
4775 | s = "divu"; | |
4776 | s2 = "mfhi"; | |
4777 | goto do_divu3; | |
4778 | case M_DDIVU_3: | |
4779 | s = "ddivu"; | |
4780 | s2 = "mflo"; | |
4781 | goto do_divu3; | |
4782 | case M_DREMU_3: | |
4783 | s = "ddivu"; | |
4784 | s2 = "mfhi"; | |
4785 | do_divu3: | |
b34976b6 | 4786 | mips_emit_delays (TRUE); |
252b5132 RH |
4787 | ++mips_opts.noreorder; |
4788 | mips_any_noreorder = 1; | |
4789 | if (mips_trap) | |
4790 | { | |
67c0d1eb RS |
4791 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4792 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4793 | /* We want to close the noreorder block as soon as possible, so |
4794 | that later insns are available for delay slot filling. */ | |
4795 | --mips_opts.noreorder; | |
4796 | } | |
4797 | else | |
4798 | { | |
4799 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4800 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4801 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4802 | |
4803 | /* We want to close the noreorder block as soon as possible, so | |
4804 | that later insns are available for delay slot filling. */ | |
4805 | --mips_opts.noreorder; | |
67c0d1eb | 4806 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4807 | } |
67c0d1eb | 4808 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4809 | return; |
4810 | ||
1abe91b1 MR |
4811 | case M_DLCA_AB: |
4812 | dbl = 1; | |
4813 | case M_LCA_AB: | |
4814 | call = 1; | |
4815 | goto do_la; | |
252b5132 RH |
4816 | case M_DLA_AB: |
4817 | dbl = 1; | |
4818 | case M_LA_AB: | |
1abe91b1 | 4819 | do_la: |
252b5132 RH |
4820 | /* Load the address of a symbol into a register. If breg is not |
4821 | zero, we then add a base register to it. */ | |
4822 | ||
3bec30a8 TS |
4823 | if (dbl && HAVE_32BIT_GPRS) |
4824 | as_warn (_("dla used to load 32-bit register")); | |
4825 | ||
c90bbe5b | 4826 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4827 | as_warn (_("la used to load 64-bit address")); |
4828 | ||
0c11417f MR |
4829 | if (offset_expr.X_op == O_constant |
4830 | && offset_expr.X_add_number >= -0x8000 | |
4831 | && offset_expr.X_add_number < 0x8000) | |
4832 | { | |
67c0d1eb | 4833 | macro_build (&offset_expr, |
b7c7d6c1 | 4834 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4835 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4836 | return; |
4837 | } | |
4838 | ||
afdbd6d0 CD |
4839 | if (treg == breg) |
4840 | { | |
4841 | tempreg = AT; | |
4842 | used_at = 1; | |
4843 | } | |
4844 | else | |
4845 | { | |
4846 | tempreg = treg; | |
4847 | used_at = 0; | |
4848 | } | |
4849 | ||
252b5132 RH |
4850 | /* When generating embedded PIC code, we permit expressions of |
4851 | the form | |
afdbd6d0 CD |
4852 | la $treg,foo-bar |
4853 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4854 | where bar is an address in the current section. These are used |
252b5132 RH |
4855 | when getting the addresses of functions. We don't permit |
4856 | X_add_number to be non-zero, because if the symbol is | |
4857 | external the relaxing code needs to know that any addend is | |
4858 | purely the offset to X_op_symbol. */ | |
4859 | if (mips_pic == EMBEDDED_PIC | |
4860 | && offset_expr.X_op == O_subtract | |
49309057 | 4861 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4862 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4863 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4864 | && (S_GET_SEGMENT | |
4865 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4866 | ->X_add_symbol) | |
bb2d6cd7 | 4867 | == now_seg))) |
bb2d6cd7 GK |
4868 | && (offset_expr.X_add_number == 0 |
4869 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4870 | { |
afdbd6d0 CD |
4871 | if (breg == 0) |
4872 | { | |
4873 | tempreg = treg; | |
4874 | used_at = 0; | |
67c0d1eb RS |
4875 | macro_build (&offset_expr, "lui", "t,u", |
4876 | tempreg, BFD_RELOC_PCREL_HI16_S); | |
afdbd6d0 CD |
4877 | } |
4878 | else | |
4879 | { | |
67c0d1eb RS |
4880 | macro_build (&offset_expr, "lui", "t,u", |
4881 | tempreg, BFD_RELOC_PCREL_HI16_S); | |
4882 | macro_build (NULL, | |
4d34fb5f | 4883 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4884 | "d,v,t", tempreg, tempreg, breg); |
4885 | } | |
67c0d1eb | 4886 | macro_build (&offset_expr, |
4d34fb5f | 4887 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4888 | "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); |
afdbd6d0 CD |
4889 | if (! used_at) |
4890 | return; | |
4891 | break; | |
252b5132 RH |
4892 | } |
4893 | ||
4894 | if (offset_expr.X_op != O_symbol | |
4895 | && offset_expr.X_op != O_constant) | |
4896 | { | |
4897 | as_bad (_("expression too complex")); | |
4898 | offset_expr.X_op = O_constant; | |
4899 | } | |
4900 | ||
252b5132 | 4901 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4902 | load_register (tempreg, &offset_expr, |
4d34fb5f TS |
4903 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) |
4904 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4905 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4906 | else if (mips_pic == NO_PIC) |
4907 | { | |
d6bc6245 | 4908 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4909 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4910 | Otherwise we want |
4911 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4912 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4913 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4914 | so we may as well always use the latter form. |
76b3015f | 4915 | |
d6bc6245 TS |
4916 | With 64bit address space and a usable $at we want |
4917 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4918 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4919 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4920 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4921 | dsll32 $tempreg,0 | |
3a482fd5 | 4922 | daddu $tempreg,$tempreg,$at |
76b3015f | 4923 | |
c03099e6 | 4924 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4925 | on superscalar processors. |
4926 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4927 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4928 | dsll $tempreg,16 | |
4929 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4930 | dsll $tempreg,16 | |
4931 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4932 | */ | |
d6bc6245 | 4933 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4934 | { |
e864ceca RS |
4935 | /* ??? We don't provide a GP-relative alternative for |
4936 | these macros. It used not to be possible with the | |
4937 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4938 | |
460597ba | 4939 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f | 4940 | { |
67c0d1eb | 4941 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4942 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4943 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4944 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4945 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4946 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4947 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4948 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4949 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4950 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4951 | used_at = 1; |
4952 | } | |
4953 | else | |
4954 | { | |
67c0d1eb | 4955 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4956 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4957 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4958 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4959 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4960 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4961 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4962 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4963 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4964 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4965 | } |
4966 | } | |
4967 | else | |
4968 | { | |
4969 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4970 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4971 | { | |
4d7206a2 | 4972 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4973 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4974 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4975 | relax_switch (); |
98d3f06f | 4976 | } |
67c0d1eb RS |
4977 | macro_build_lui (&offset_expr, tempreg); |
4978 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4979 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4980 | if (mips_relax.sequence) |
4981 | relax_end (); | |
98d3f06f | 4982 | } |
252b5132 | 4983 | } |
f5040a92 | 4984 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4985 | { |
9117d219 NC |
4986 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4987 | ||
252b5132 RH |
4988 | /* If this is a reference to an external symbol, and there |
4989 | is no constant, we want | |
4990 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4991 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4992 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4993 | For a local symbol, we want |
4994 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4995 | nop | |
4996 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4997 | ||
4998 | If we have a small constant, and this is a reference to | |
4999 | an external symbol, we want | |
5000 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5001 | nop | |
5002 | addiu $tempreg,$tempreg,<constant> | |
5003 | For a local symbol, we want the same instruction | |
5004 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5005 | addiu instruction. | |
5006 | ||
5007 | If we have a large constant, and this is a reference to | |
5008 | an external symbol, we want | |
5009 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5010 | lui $at,<hiconstant> | |
5011 | addiu $at,$at,<loconstant> | |
5012 | addu $tempreg,$tempreg,$at | |
5013 | For a local symbol, we want the same instruction | |
5014 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5015 | addiu instruction. |
ed6fb7bd SC |
5016 | */ |
5017 | ||
4d7206a2 | 5018 | if (offset_expr.X_add_number == 0) |
252b5132 | 5019 | { |
4d7206a2 RS |
5020 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5021 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5022 | ||
5023 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5024 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5025 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5026 | if (breg != 0) |
252b5132 RH |
5027 | { |
5028 | /* We're going to put in an addu instruction using | |
5029 | tempreg, so we may as well insert the nop right | |
5030 | now. */ | |
67c0d1eb | 5031 | macro_build (NULL, "nop", ""); |
252b5132 | 5032 | } |
4d7206a2 | 5033 | relax_switch (); |
67c0d1eb RS |
5034 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5035 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5036 | macro_build (NULL, "nop", ""); | |
5037 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5038 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5039 | relax_end (); |
252b5132 RH |
5040 | /* FIXME: If breg == 0, and the next instruction uses |
5041 | $tempreg, then if this variant case is used an extra | |
5042 | nop will be generated. */ | |
5043 | } | |
4d7206a2 RS |
5044 | else if (offset_expr.X_add_number >= -0x8000 |
5045 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5046 | { |
67c0d1eb RS |
5047 | load_got_offset (tempreg, &offset_expr); |
5048 | macro_build (NULL, "nop", ""); | |
5049 | add_got_offset (tempreg, &offset_expr); | |
252b5132 RH |
5050 | } |
5051 | else | |
5052 | { | |
4d7206a2 RS |
5053 | expr1.X_add_number = offset_expr.X_add_number; |
5054 | offset_expr.X_add_number = | |
5055 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5056 | load_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5057 | /* If we are going to add in a base register, and the |
5058 | target register and the base register are the same, | |
5059 | then we are using AT as a temporary register. Since | |
5060 | we want to load the constant into AT, we add our | |
5061 | current AT (from the global offset table) and the | |
5062 | register into the register now, and pretend we were | |
5063 | not using a base register. */ | |
67c0d1eb | 5064 | if (breg == treg) |
252b5132 | 5065 | { |
67c0d1eb RS |
5066 | macro_build (NULL, "nop", ""); |
5067 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5068 | treg, AT, breg); |
252b5132 RH |
5069 | breg = 0; |
5070 | tempreg = treg; | |
252b5132 RH |
5071 | } |
5072 | ||
5073 | /* Set mips_optimize around the lui instruction to avoid | |
5074 | inserting an unnecessary nop after the lw. */ | |
5075 | hold_mips_optimize = mips_optimize; | |
5076 | mips_optimize = 2; | |
67c0d1eb | 5077 | macro_build_lui (&expr1, AT); |
252b5132 RH |
5078 | mips_optimize = hold_mips_optimize; |
5079 | ||
67c0d1eb RS |
5080 | add_got_offset (AT, &offset_expr); |
5081 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5082 | tempreg, tempreg, AT); |
252b5132 RH |
5083 | used_at = 1; |
5084 | } | |
5085 | } | |
f5040a92 AO |
5086 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5087 | { | |
67c0d1eb | 5088 | int add_breg_early = 0; |
f5040a92 AO |
5089 | |
5090 | /* If this is a reference to an external, and there is no | |
5091 | constant, or local symbol (*), with or without a | |
5092 | constant, we want | |
5093 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5094 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5095 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5096 | ||
5097 | If we have a small constant, and this is a reference to | |
5098 | an external symbol, we want | |
5099 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5100 | addiu $tempreg,$tempreg,<constant> | |
5101 | ||
5102 | If we have a large constant, and this is a reference to | |
5103 | an external symbol, we want | |
5104 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5105 | lui $at,<hiconstant> | |
5106 | addiu $at,$at,<loconstant> | |
5107 | addu $tempreg,$tempreg,$at | |
5108 | ||
5109 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5110 | local symbols, even though it introduces an additional | |
5111 | instruction. */ | |
5112 | ||
f5040a92 AO |
5113 | if (offset_expr.X_add_number) |
5114 | { | |
4d7206a2 | 5115 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5116 | offset_expr.X_add_number = 0; |
5117 | ||
4d7206a2 | 5118 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5119 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5120 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5121 | |
5122 | if (expr1.X_add_number >= -0x8000 | |
5123 | && expr1.X_add_number < 0x8000) | |
5124 | { | |
67c0d1eb RS |
5125 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5126 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5127 | } |
ecd13cd3 | 5128 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5129 | { |
5130 | int dreg; | |
5131 | ||
5132 | /* If we are going to add in a base register, and the | |
5133 | target register and the base register are the same, | |
5134 | then we are using AT as a temporary register. Since | |
5135 | we want to load the constant into AT, we add our | |
5136 | current AT (from the global offset table) and the | |
5137 | register into the register now, and pretend we were | |
5138 | not using a base register. */ | |
5139 | if (breg != treg) | |
5140 | dreg = tempreg; | |
5141 | else | |
5142 | { | |
5143 | assert (tempreg == AT); | |
67c0d1eb RS |
5144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5145 | treg, AT, breg); | |
f5040a92 | 5146 | dreg = treg; |
67c0d1eb | 5147 | add_breg_early = 1; |
f5040a92 AO |
5148 | } |
5149 | ||
67c0d1eb RS |
5150 | macro_build_lui (&expr1, AT); |
5151 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", | |
5152 | AT, AT, BFD_RELOC_LO16); | |
5153 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5154 | dreg, dreg, AT); |
f5040a92 | 5155 | |
f5040a92 AO |
5156 | used_at = 1; |
5157 | } | |
5158 | else | |
5159 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5160 | ||
4d7206a2 | 5161 | relax_switch (); |
f5040a92 AO |
5162 | offset_expr.X_add_number = expr1.X_add_number; |
5163 | ||
67c0d1eb RS |
5164 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5165 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5166 | if (add_breg_early) | |
f5040a92 | 5167 | { |
67c0d1eb | 5168 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5169 | treg, tempreg, breg); |
f5040a92 AO |
5170 | breg = 0; |
5171 | tempreg = treg; | |
5172 | } | |
4d7206a2 | 5173 | relax_end (); |
f5040a92 | 5174 | } |
4d7206a2 | 5175 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5176 | { |
4d7206a2 | 5177 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5178 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5179 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5180 | relax_switch (); |
67c0d1eb RS |
5181 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5182 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5183 | relax_end (); |
f5040a92 | 5184 | } |
4d7206a2 | 5185 | else |
f5040a92 | 5186 | { |
67c0d1eb RS |
5187 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5188 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5189 | } |
5190 | } | |
5191 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5192 | { |
67c0d1eb | 5193 | int gpdelay; |
9117d219 NC |
5194 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5195 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5196 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5197 | |
5198 | /* This is the large GOT case. If this is a reference to an | |
5199 | external symbol, and there is no constant, we want | |
5200 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5201 | addu $tempreg,$tempreg,$gp | |
5202 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5203 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5204 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5205 | addu $tempreg,$tempreg,$gp | |
5206 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5207 | For a local symbol, we want |
5208 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5209 | nop | |
5210 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5211 | ||
5212 | If we have a small constant, and this is a reference to | |
5213 | an external symbol, we want | |
5214 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5215 | addu $tempreg,$tempreg,$gp | |
5216 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5217 | nop | |
5218 | addiu $tempreg,$tempreg,<constant> | |
5219 | For a local symbol, we want | |
5220 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5221 | nop | |
5222 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5223 | ||
5224 | If we have a large constant, and this is a reference to | |
5225 | an external symbol, we want | |
5226 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5227 | addu $tempreg,$tempreg,$gp | |
5228 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5229 | lui $at,<hiconstant> | |
5230 | addiu $at,$at,<loconstant> | |
5231 | addu $tempreg,$tempreg,$at | |
5232 | For a local symbol, we want | |
5233 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5234 | lui $at,<hiconstant> | |
5235 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5236 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5237 | */ |
438c16b8 | 5238 | |
252b5132 RH |
5239 | expr1.X_add_number = offset_expr.X_add_number; |
5240 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5241 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5242 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5243 | if (expr1.X_add_number == 0 && breg == 0 |
5244 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5245 | { |
5246 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5247 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5248 | } | |
67c0d1eb RS |
5249 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5251 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5252 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5253 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5254 | if (expr1.X_add_number == 0) |
5255 | { | |
67c0d1eb | 5256 | if (breg != 0) |
252b5132 RH |
5257 | { |
5258 | /* We're going to put in an addu instruction using | |
5259 | tempreg, so we may as well insert the nop right | |
5260 | now. */ | |
67c0d1eb | 5261 | macro_build (NULL, "nop", ""); |
252b5132 | 5262 | } |
252b5132 RH |
5263 | } |
5264 | else if (expr1.X_add_number >= -0x8000 | |
5265 | && expr1.X_add_number < 0x8000) | |
5266 | { | |
67c0d1eb RS |
5267 | macro_build (NULL, "nop", ""); |
5268 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5269 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5270 | } |
5271 | else | |
5272 | { | |
67c0d1eb | 5273 | int dreg; |
252b5132 RH |
5274 | |
5275 | /* If we are going to add in a base register, and the | |
5276 | target register and the base register are the same, | |
5277 | then we are using AT as a temporary register. Since | |
5278 | we want to load the constant into AT, we add our | |
5279 | current AT (from the global offset table) and the | |
5280 | register into the register now, and pretend we were | |
5281 | not using a base register. */ | |
5282 | if (breg != treg) | |
67c0d1eb | 5283 | dreg = tempreg; |
252b5132 RH |
5284 | else |
5285 | { | |
5286 | assert (tempreg == AT); | |
67c0d1eb RS |
5287 | macro_build (NULL, "nop", ""); |
5288 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5289 | treg, AT, breg); |
252b5132 | 5290 | dreg = treg; |
252b5132 RH |
5291 | } |
5292 | ||
5293 | /* Set mips_optimize around the lui instruction to avoid | |
5294 | inserting an unnecessary nop after the lw. */ | |
5295 | hold_mips_optimize = mips_optimize; | |
5296 | mips_optimize = 2; | |
67c0d1eb | 5297 | macro_build_lui (&expr1, AT); |
252b5132 RH |
5298 | mips_optimize = hold_mips_optimize; |
5299 | ||
67c0d1eb | 5300 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5301 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5302 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5303 | |
252b5132 RH |
5304 | used_at = 1; |
5305 | } | |
4d7206a2 RS |
5306 | offset_expr.X_add_number = |
5307 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5308 | relax_switch (); | |
252b5132 | 5309 | |
67c0d1eb | 5310 | if (gpdelay) |
252b5132 RH |
5311 | { |
5312 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5313 | the first instruction on the main stream does not. */ |
67c0d1eb | 5314 | macro_build (NULL, "nop", ""); |
252b5132 | 5315 | } |
ed6fb7bd | 5316 | |
67c0d1eb RS |
5317 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5318 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5319 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5320 | && expr1.X_add_number < 0x8000) |
5321 | { | |
67c0d1eb RS |
5322 | macro_build (NULL, "nop", ""); |
5323 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5324 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5325 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5326 | register, the external symbol case ended with a load, |
5327 | so if the symbol turns out to not be external, and | |
5328 | the next instruction uses tempreg, an unnecessary nop | |
5329 | will be inserted. */ | |
252b5132 RH |
5330 | } |
5331 | else | |
5332 | { | |
5333 | if (breg == treg) | |
5334 | { | |
5335 | /* We must add in the base register now, as in the | |
f5040a92 | 5336 | external symbol case. */ |
252b5132 | 5337 | assert (tempreg == AT); |
67c0d1eb RS |
5338 | macro_build (NULL, "nop", ""); |
5339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5340 | treg, AT, breg); |
252b5132 RH |
5341 | tempreg = treg; |
5342 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5343 | it in in both cases. */ |
252b5132 RH |
5344 | breg = 0; |
5345 | } | |
5346 | ||
67c0d1eb RS |
5347 | macro_build_lui (&expr1, AT); |
5348 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5349 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5350 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5351 | tempreg, tempreg, AT); |
252b5132 | 5352 | } |
4d7206a2 | 5353 | relax_end (); |
252b5132 | 5354 | } |
f5040a92 AO |
5355 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5356 | { | |
f5040a92 AO |
5357 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5358 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5359 | int add_breg_early = 0; |
f5040a92 AO |
5360 | |
5361 | /* This is the large GOT case. If this is a reference to an | |
5362 | external symbol, and there is no constant, we want | |
5363 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5364 | add $tempreg,$tempreg,$gp | |
5365 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5366 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5367 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5368 | add $tempreg,$tempreg,$gp | |
5369 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5370 | ||
5371 | If we have a small constant, and this is a reference to | |
5372 | an external symbol, we want | |
5373 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5374 | add $tempreg,$tempreg,$gp | |
5375 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5376 | addi $tempreg,$tempreg,<constant> | |
5377 | ||
5378 | If we have a large constant, and this is a reference to | |
5379 | an external symbol, we want | |
5380 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5381 | addu $tempreg,$tempreg,$gp | |
5382 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5383 | lui $at,<hiconstant> | |
5384 | addi $at,$at,<loconstant> | |
5385 | add $tempreg,$tempreg,$at | |
5386 | ||
5387 | If we have NewABI, and we know it's a local symbol, we want | |
5388 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5389 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5390 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5391 | ||
4d7206a2 | 5392 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5393 | |
4d7206a2 | 5394 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5395 | offset_expr.X_add_number = 0; |
5396 | ||
1abe91b1 MR |
5397 | if (expr1.X_add_number == 0 && breg == 0 |
5398 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5399 | { |
5400 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5401 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5402 | } | |
67c0d1eb RS |
5403 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5404 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5405 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5406 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5407 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5408 | |
5409 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5410 | ; |
f5040a92 AO |
5411 | else if (expr1.X_add_number >= -0x8000 |
5412 | && expr1.X_add_number < 0x8000) | |
5413 | { | |
67c0d1eb | 5414 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5415 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5416 | } |
ecd13cd3 | 5417 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5418 | { |
5419 | int dreg; | |
5420 | ||
5421 | /* If we are going to add in a base register, and the | |
5422 | target register and the base register are the same, | |
5423 | then we are using AT as a temporary register. Since | |
5424 | we want to load the constant into AT, we add our | |
5425 | current AT (from the global offset table) and the | |
5426 | register into the register now, and pretend we were | |
5427 | not using a base register. */ | |
5428 | if (breg != treg) | |
5429 | dreg = tempreg; | |
5430 | else | |
5431 | { | |
5432 | assert (tempreg == AT); | |
67c0d1eb | 5433 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5434 | treg, AT, breg); |
f5040a92 | 5435 | dreg = treg; |
67c0d1eb | 5436 | add_breg_early = 1; |
f5040a92 AO |
5437 | } |
5438 | ||
5439 | /* Set mips_optimize around the lui instruction to avoid | |
5440 | inserting an unnecessary nop after the lw. */ | |
67c0d1eb RS |
5441 | macro_build_lui (&expr1, AT); |
5442 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", | |
5443 | AT, AT, BFD_RELOC_LO16); | |
5444 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); | |
f5040a92 | 5445 | |
f5040a92 AO |
5446 | used_at = 1; |
5447 | } | |
5448 | else | |
5449 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5450 | ||
4d7206a2 | 5451 | relax_switch (); |
f5040a92 | 5452 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5453 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5454 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5455 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5456 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5457 | if (add_breg_early) | |
f5040a92 | 5458 | { |
67c0d1eb | 5459 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5460 | treg, tempreg, breg); |
f5040a92 AO |
5461 | breg = 0; |
5462 | tempreg = treg; | |
5463 | } | |
4d7206a2 | 5464 | relax_end (); |
f5040a92 | 5465 | } |
252b5132 RH |
5466 | else if (mips_pic == EMBEDDED_PIC) |
5467 | { | |
5468 | /* We use | |
cdf6fd85 | 5469 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5470 | */ |
67c0d1eb RS |
5471 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
5472 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
5473 | } |
5474 | else | |
5475 | abort (); | |
5476 | ||
5477 | if (breg != 0) | |
4d34fb5f TS |
5478 | { |
5479 | char *s; | |
5480 | ||
5481 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
b7c7d6c1 | 5482 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5483 | else |
f899b4b8 | 5484 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5485 | |
67c0d1eb | 5486 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5487 | } |
252b5132 RH |
5488 | |
5489 | if (! used_at) | |
5490 | return; | |
5491 | ||
5492 | break; | |
5493 | ||
5494 | case M_J_A: | |
5495 | /* The j instruction may not be used in PIC code, since it | |
5496 | requires an absolute address. We convert it to a b | |
5497 | instruction. */ | |
5498 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5499 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5500 | else |
67c0d1eb | 5501 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5502 | return; |
5503 | ||
5504 | /* The jal instructions must be handled as macros because when | |
5505 | generating PIC code they expand to multi-instruction | |
5506 | sequences. Normally they are simple instructions. */ | |
5507 | case M_JAL_1: | |
5508 | dreg = RA; | |
5509 | /* Fall through. */ | |
5510 | case M_JAL_2: | |
5511 | if (mips_pic == NO_PIC | |
5512 | || mips_pic == EMBEDDED_PIC) | |
67c0d1eb | 5513 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5514 | else if (mips_pic == SVR4_PIC) |
5515 | { | |
5516 | if (sreg != PIC_CALL_REG) | |
5517 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5518 | |
67c0d1eb | 5519 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5520 | if (! HAVE_NEWABI) |
252b5132 | 5521 | { |
6478892d TS |
5522 | if (mips_cprestore_offset < 0) |
5523 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5524 | else | |
5525 | { | |
7a621144 DJ |
5526 | if (! mips_frame_reg_valid) |
5527 | { | |
5528 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5529 | /* Quiet this warning. */ | |
5530 | mips_frame_reg_valid = 1; | |
5531 | } | |
5532 | if (! mips_cprestore_valid) | |
5533 | { | |
5534 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5535 | /* Quiet this warning. */ | |
5536 | mips_cprestore_valid = 1; | |
5537 | } | |
6478892d | 5538 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5539 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5540 | mips_gp_register, |
256ab948 TS |
5541 | mips_frame_reg, |
5542 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5543 | } |
252b5132 RH |
5544 | } |
5545 | } | |
5546 | else | |
5547 | abort (); | |
5548 | ||
5549 | return; | |
5550 | ||
5551 | case M_JAL_A: | |
5552 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5553 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5554 | else if (mips_pic == SVR4_PIC) |
5555 | { | |
5556 | /* If this is a reference to an external symbol, and we are | |
5557 | using a small GOT, we want | |
5558 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5559 | nop | |
f9419b05 | 5560 | jalr $ra,$25 |
252b5132 RH |
5561 | nop |
5562 | lw $gp,cprestore($sp) | |
5563 | The cprestore value is set using the .cprestore | |
5564 | pseudo-op. If we are using a big GOT, we want | |
5565 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5566 | addu $25,$25,$gp | |
5567 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5568 | nop | |
f9419b05 | 5569 | jalr $ra,$25 |
252b5132 RH |
5570 | nop |
5571 | lw $gp,cprestore($sp) | |
5572 | If the symbol is not external, we want | |
5573 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5574 | nop | |
5575 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5576 | jalr $ra,$25 |
252b5132 | 5577 | nop |
438c16b8 | 5578 | lw $gp,cprestore($sp) |
f5040a92 AO |
5579 | |
5580 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5581 | sequences above, minus nops, unless the symbol is local, | |
5582 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5583 | GOT_DISP. */ | |
438c16b8 | 5584 | if (HAVE_NEWABI) |
252b5132 | 5585 | { |
f5040a92 AO |
5586 | if (! mips_big_got) |
5587 | { | |
4d7206a2 | 5588 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5589 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5590 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5591 | mips_gp_register); |
4d7206a2 | 5592 | relax_switch (); |
67c0d1eb RS |
5593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5594 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5595 | mips_gp_register); |
5596 | relax_end (); | |
f5040a92 AO |
5597 | } |
5598 | else | |
5599 | { | |
4d7206a2 | 5600 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5601 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5602 | BFD_RELOC_MIPS_CALL_HI16); | |
5603 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5604 | PIC_CALL_REG, mips_gp_register); | |
5605 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5606 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5607 | PIC_CALL_REG); | |
4d7206a2 | 5608 | relax_switch (); |
67c0d1eb RS |
5609 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5610 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5611 | mips_gp_register); | |
5612 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5613 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5614 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5615 | relax_end (); |
f5040a92 | 5616 | } |
684022ea | 5617 | |
67c0d1eb | 5618 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5619 | } |
5620 | else | |
5621 | { | |
4d7206a2 | 5622 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5623 | if (! mips_big_got) |
5624 | { | |
67c0d1eb RS |
5625 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5626 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5627 | mips_gp_register); |
67c0d1eb | 5628 | macro_build (NULL, "nop", ""); |
4d7206a2 | 5629 | relax_switch (); |
438c16b8 | 5630 | } |
252b5132 | 5631 | else |
252b5132 | 5632 | { |
67c0d1eb RS |
5633 | int gpdelay; |
5634 | ||
5635 | gpdelay = reg_needs_delay (mips_gp_register); | |
5636 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5637 | BFD_RELOC_MIPS_CALL_HI16); | |
5638 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5639 | PIC_CALL_REG, mips_gp_register); | |
5640 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5641 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5642 | PIC_CALL_REG); | |
5643 | macro_build (NULL, "nop", ""); | |
4d7206a2 | 5644 | relax_switch (); |
67c0d1eb RS |
5645 | if (gpdelay) |
5646 | macro_build (NULL, "nop", ""); | |
252b5132 | 5647 | } |
67c0d1eb RS |
5648 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5649 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5650 | mips_gp_register); |
67c0d1eb RS |
5651 | macro_build (NULL, "nop", ""); |
5652 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5653 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5654 | relax_end (); |
67c0d1eb | 5655 | macro_build_jalr (&offset_expr); |
438c16b8 | 5656 | |
6478892d TS |
5657 | if (mips_cprestore_offset < 0) |
5658 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5659 | else | |
5660 | { | |
7a621144 DJ |
5661 | if (! mips_frame_reg_valid) |
5662 | { | |
5663 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5664 | /* Quiet this warning. */ | |
5665 | mips_frame_reg_valid = 1; | |
5666 | } | |
5667 | if (! mips_cprestore_valid) | |
5668 | { | |
5669 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5670 | /* Quiet this warning. */ | |
5671 | mips_cprestore_valid = 1; | |
5672 | } | |
6478892d | 5673 | if (mips_opts.noreorder) |
67c0d1eb | 5674 | macro_build (NULL, "nop", ""); |
6478892d | 5675 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5676 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5677 | mips_gp_register, |
256ab948 TS |
5678 | mips_frame_reg, |
5679 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5680 | } |
252b5132 RH |
5681 | } |
5682 | } | |
5683 | else if (mips_pic == EMBEDDED_PIC) | |
5684 | { | |
67c0d1eb | 5685 | macro_build (&offset_expr, "bal", "p"); |
252b5132 RH |
5686 | /* The linker may expand the call to a longer sequence which |
5687 | uses $at, so we must break rather than return. */ | |
5688 | break; | |
5689 | } | |
5690 | else | |
5691 | abort (); | |
5692 | ||
5693 | return; | |
5694 | ||
5695 | case M_LB_AB: | |
5696 | s = "lb"; | |
5697 | goto ld; | |
5698 | case M_LBU_AB: | |
5699 | s = "lbu"; | |
5700 | goto ld; | |
5701 | case M_LH_AB: | |
5702 | s = "lh"; | |
5703 | goto ld; | |
5704 | case M_LHU_AB: | |
5705 | s = "lhu"; | |
5706 | goto ld; | |
5707 | case M_LW_AB: | |
5708 | s = "lw"; | |
5709 | goto ld; | |
5710 | case M_LWC0_AB: | |
5711 | s = "lwc0"; | |
bdaaa2e1 | 5712 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5713 | coproc = 1; |
5714 | goto ld; | |
5715 | case M_LWC1_AB: | |
5716 | s = "lwc1"; | |
bdaaa2e1 | 5717 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5718 | coproc = 1; |
5719 | goto ld; | |
5720 | case M_LWC2_AB: | |
5721 | s = "lwc2"; | |
bdaaa2e1 | 5722 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5723 | coproc = 1; |
5724 | goto ld; | |
5725 | case M_LWC3_AB: | |
5726 | s = "lwc3"; | |
bdaaa2e1 | 5727 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5728 | coproc = 1; |
5729 | goto ld; | |
5730 | case M_LWL_AB: | |
5731 | s = "lwl"; | |
5732 | lr = 1; | |
5733 | goto ld; | |
5734 | case M_LWR_AB: | |
5735 | s = "lwr"; | |
5736 | lr = 1; | |
5737 | goto ld; | |
5738 | case M_LDC1_AB: | |
fef14a42 | 5739 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5740 | { |
5741 | as_bad (_("opcode not supported on this processor")); | |
5742 | return; | |
5743 | } | |
5744 | s = "ldc1"; | |
bdaaa2e1 | 5745 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5746 | coproc = 1; |
5747 | goto ld; | |
5748 | case M_LDC2_AB: | |
5749 | s = "ldc2"; | |
bdaaa2e1 | 5750 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5751 | coproc = 1; |
5752 | goto ld; | |
5753 | case M_LDC3_AB: | |
5754 | s = "ldc3"; | |
bdaaa2e1 | 5755 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5756 | coproc = 1; |
5757 | goto ld; | |
5758 | case M_LDL_AB: | |
5759 | s = "ldl"; | |
5760 | lr = 1; | |
5761 | goto ld; | |
5762 | case M_LDR_AB: | |
5763 | s = "ldr"; | |
5764 | lr = 1; | |
5765 | goto ld; | |
5766 | case M_LL_AB: | |
5767 | s = "ll"; | |
5768 | goto ld; | |
5769 | case M_LLD_AB: | |
5770 | s = "lld"; | |
5771 | goto ld; | |
5772 | case M_LWU_AB: | |
5773 | s = "lwu"; | |
5774 | ld: | |
5775 | if (breg == treg || coproc || lr) | |
5776 | { | |
5777 | tempreg = AT; | |
5778 | used_at = 1; | |
5779 | } | |
5780 | else | |
5781 | { | |
5782 | tempreg = treg; | |
5783 | used_at = 0; | |
5784 | } | |
5785 | goto ld_st; | |
5786 | case M_SB_AB: | |
5787 | s = "sb"; | |
5788 | goto st; | |
5789 | case M_SH_AB: | |
5790 | s = "sh"; | |
5791 | goto st; | |
5792 | case M_SW_AB: | |
5793 | s = "sw"; | |
5794 | goto st; | |
5795 | case M_SWC0_AB: | |
5796 | s = "swc0"; | |
bdaaa2e1 | 5797 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5798 | coproc = 1; |
5799 | goto st; | |
5800 | case M_SWC1_AB: | |
5801 | s = "swc1"; | |
bdaaa2e1 | 5802 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5803 | coproc = 1; |
5804 | goto st; | |
5805 | case M_SWC2_AB: | |
5806 | s = "swc2"; | |
bdaaa2e1 | 5807 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5808 | coproc = 1; |
5809 | goto st; | |
5810 | case M_SWC3_AB: | |
5811 | s = "swc3"; | |
bdaaa2e1 | 5812 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5813 | coproc = 1; |
5814 | goto st; | |
5815 | case M_SWL_AB: | |
5816 | s = "swl"; | |
5817 | goto st; | |
5818 | case M_SWR_AB: | |
5819 | s = "swr"; | |
5820 | goto st; | |
5821 | case M_SC_AB: | |
5822 | s = "sc"; | |
5823 | goto st; | |
5824 | case M_SCD_AB: | |
5825 | s = "scd"; | |
5826 | goto st; | |
5827 | case M_SDC1_AB: | |
fef14a42 | 5828 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5829 | { |
5830 | as_bad (_("opcode not supported on this processor")); | |
5831 | return; | |
5832 | } | |
5833 | s = "sdc1"; | |
5834 | coproc = 1; | |
bdaaa2e1 | 5835 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5836 | goto st; |
5837 | case M_SDC2_AB: | |
5838 | s = "sdc2"; | |
bdaaa2e1 | 5839 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5840 | coproc = 1; |
5841 | goto st; | |
5842 | case M_SDC3_AB: | |
5843 | s = "sdc3"; | |
bdaaa2e1 | 5844 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5845 | coproc = 1; |
5846 | goto st; | |
5847 | case M_SDL_AB: | |
5848 | s = "sdl"; | |
5849 | goto st; | |
5850 | case M_SDR_AB: | |
5851 | s = "sdr"; | |
5852 | st: | |
5853 | tempreg = AT; | |
5854 | used_at = 1; | |
5855 | ld_st: | |
bdaaa2e1 | 5856 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5857 | if (mask == M_LWC1_AB |
5858 | || mask == M_SWC1_AB | |
5859 | || mask == M_LDC1_AB | |
5860 | || mask == M_SDC1_AB | |
5861 | || mask == M_L_DAB | |
5862 | || mask == M_S_DAB) | |
5863 | fmt = "T,o(b)"; | |
5864 | else if (coproc) | |
5865 | fmt = "E,o(b)"; | |
5866 | else | |
5867 | fmt = "t,o(b)"; | |
5868 | ||
256ab948 TS |
5869 | /* Sign-extending 32-bit constants makes their handling easier. |
5870 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5871 | described below. */ | |
5872 | if ((! HAVE_64BIT_ADDRESSES | |
5873 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5874 | && (offset_expr.X_op == O_constant) |
5875 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5876 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5877 | { |
d17e7bce | 5878 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5879 | as_bad (_("constant too large")); |
ae826530 | 5880 | |
1b8e29e5 TS |
5881 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5882 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5883 | } |
256ab948 | 5884 | |
afdbd6d0 CD |
5885 | /* For embedded PIC, we allow loads where the offset is calculated |
5886 | by subtracting a symbol in the current segment from an unknown | |
5887 | symbol, relative to a base register, e.g.: | |
5888 | <op> $treg, <sym>-<localsym>($breg) | |
5889 | This is used by the compiler for switch statements. */ | |
76b3015f | 5890 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5891 | && offset_expr.X_op == O_subtract |
5892 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5893 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5894 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5895 | && (S_GET_SEGMENT | |
5896 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5897 | ->X_add_symbol) | |
5898 | == now_seg))) | |
5899 | && breg != 0 | |
5900 | && (offset_expr.X_add_number == 0 | |
5901 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5902 | { | |
5903 | /* For this case, we output the instructions: | |
5904 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5905 | addiu $tempreg,$tempreg,$breg | |
5906 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5907 | If the relocation would fit entirely in 16 bits, it would be | |
5908 | nice to emit: | |
5909 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5910 | instead, but that seems quite difficult. */ | |
67c0d1eb | 5911 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 5912 | BFD_RELOC_PCREL_HI16_S); |
67c0d1eb RS |
5913 | macro_build (NULL, |
5914 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5915 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5916 | ? "addu" : "daddu"), | |
5917 | "d,v,t", tempreg, tempreg, breg); | |
5918 | macro_build (&offset_expr, s, fmt, treg, | |
5919 | BFD_RELOC_PCREL_LO16, tempreg); | |
afdbd6d0 CD |
5920 | if (! used_at) |
5921 | return; | |
5922 | break; | |
5923 | } | |
5924 | ||
252b5132 RH |
5925 | if (offset_expr.X_op != O_constant |
5926 | && offset_expr.X_op != O_symbol) | |
5927 | { | |
5928 | as_bad (_("expression too complex")); | |
5929 | offset_expr.X_op = O_constant; | |
5930 | } | |
5931 | ||
5932 | /* A constant expression in PIC code can be handled just as it | |
5933 | is in non PIC code. */ | |
5934 | if (mips_pic == NO_PIC | |
5935 | || offset_expr.X_op == O_constant) | |
5936 | { | |
5937 | /* If this is a reference to a GP relative symbol, and there | |
5938 | is no base register, we want | |
cdf6fd85 | 5939 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5940 | Otherwise, if there is no base register, we want |
5941 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5942 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5943 | If we have a constant, we need two instructions anyhow, | |
5944 | so we always use the latter form. | |
5945 | ||
5946 | If we have a base register, and this is a reference to a | |
5947 | GP relative symbol, we want | |
5948 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5949 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5950 | Otherwise we want |
5951 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5952 | addu $tempreg,$tempreg,$breg | |
5953 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5954 | With a constant we always use the latter case. |
76b3015f | 5955 | |
d6bc6245 TS |
5956 | With 64bit address space and no base register and $at usable, |
5957 | we want | |
5958 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5959 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5960 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5961 | dsll32 $tempreg,0 | |
5962 | daddu $tempreg,$at | |
5963 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5964 | If we have a base register, we want | |
5965 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5966 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5967 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5968 | daddu $at,$breg | |
5969 | dsll32 $tempreg,0 | |
5970 | daddu $tempreg,$at | |
5971 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5972 | ||
5973 | Without $at we can't generate the optimal path for superscalar | |
5974 | processors here since this would require two temporary registers. | |
5975 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5976 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5977 | dsll $tempreg,16 | |
5978 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5979 | dsll $tempreg,16 | |
5980 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5981 | If we have a base register, we want | |
5982 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5983 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5984 | dsll $tempreg,16 | |
5985 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5986 | dsll $tempreg,16 | |
5987 | daddu $tempreg,$tempreg,$breg | |
5988 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5989 | |
5990 | If we have 64-bit addresses, as an optimization, for | |
5991 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5992 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5993 | mechanism since it is more efficient. Note that due to |
5994 | the signed offset used by memory operations, the 32-bit | |
5995 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5996 | probably attempt to generate 64-bit constants more |
5997 | efficiently in general. | |
9214dd3b AO |
5998 | |
5999 | As an extension for architectures with 64-bit registers, | |
6000 | we don't truncate 64-bit addresses given as literal | |
6001 | constants down to 32 bits, to support existing practice | |
6002 | in the mips64 Linux (the kernel), that compiles source | |
6003 | files with -mabi=64, assembling them as o32 or n32 (with | |
6004 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
6005 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 6006 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
6007 | wasteful to compute the upper 32 bits of every |
6008 | non-literal address, that takes more space and time. | |
6009 | Some day this should probably be implemented as an | |
6010 | assembler option, such that the kernel doesn't have to | |
6011 | use such ugly hacks, even though it will still have to | |
6012 | end up converting the binary to ELF32 for a number of | |
6013 | platforms whose boot loaders don't support ELF64 | |
6014 | binaries. */ | |
256ab948 TS |
6015 | if ((HAVE_64BIT_ADDRESSES |
6016 | && ! (offset_expr.X_op == O_constant | |
6017 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
6018 | || (HAVE_64BIT_GPRS | |
6019 | && offset_expr.X_op == O_constant | |
6020 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 6021 | { |
e864ceca RS |
6022 | /* ??? We don't provide a GP-relative alternative for |
6023 | these macros. It used not to be possible with the | |
6024 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 6025 | |
460597ba | 6026 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 6027 | { |
67c0d1eb RS |
6028 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6029 | BFD_RELOC_MIPS_HIGHEST); | |
6030 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6031 | BFD_RELOC_HI16_S); | |
6032 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6033 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6034 | if (breg != 0) |
67c0d1eb RS |
6035 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6036 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6037 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6038 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6039 | tempreg); | |
d6bc6245 TS |
6040 | used_at = 1; |
6041 | } | |
6042 | else | |
6043 | { | |
67c0d1eb RS |
6044 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6045 | BFD_RELOC_MIPS_HIGHEST); | |
6046 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6047 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6048 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6049 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6050 | tempreg, BFD_RELOC_HI16_S); | |
6051 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6052 | if (breg != 0) |
67c0d1eb | 6053 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6054 | tempreg, tempreg, breg); |
67c0d1eb | 6055 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6056 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
6057 | } |
6058 | ||
6059 | return; | |
6060 | } | |
256ab948 TS |
6061 | |
6062 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 6063 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6064 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6065 | |
252b5132 RH |
6066 | if (breg == 0) |
6067 | { | |
67c0d1eb RS |
6068 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6069 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6070 | { |
4d7206a2 | 6071 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6072 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6073 | mips_gp_register); | |
4d7206a2 | 6074 | relax_switch (); |
252b5132 RH |
6075 | used_at = 0; |
6076 | } | |
67c0d1eb RS |
6077 | macro_build_lui (&offset_expr, tempreg); |
6078 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6079 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6080 | if (mips_relax.sequence) |
6081 | relax_end (); | |
252b5132 RH |
6082 | } |
6083 | else | |
6084 | { | |
67c0d1eb RS |
6085 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6086 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6087 | { |
4d7206a2 | 6088 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6089 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6090 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6091 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6092 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6093 | relax_switch (); |
252b5132 | 6094 | } |
67c0d1eb RS |
6095 | macro_build_lui (&offset_expr, tempreg); |
6096 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6097 | tempreg, tempreg, breg); |
67c0d1eb | 6098 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6099 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6100 | if (mips_relax.sequence) |
6101 | relax_end (); | |
252b5132 RH |
6102 | } |
6103 | } | |
6104 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6105 | { | |
ed6fb7bd | 6106 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6107 | |
252b5132 RH |
6108 | /* If this is a reference to an external symbol, we want |
6109 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6110 | nop | |
6111 | <op> $treg,0($tempreg) | |
6112 | Otherwise we want | |
6113 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6114 | nop | |
6115 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6116 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6117 | |
6118 | For NewABI, we want | |
6119 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6120 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6121 | ||
252b5132 RH |
6122 | If there is a base register, we add it to $tempreg before |
6123 | the <op>. If there is a constant, we stick it in the | |
6124 | <op> instruction. We don't handle constants larger than | |
6125 | 16 bits, because we have no way to load the upper 16 bits | |
6126 | (actually, we could handle them for the subset of cases | |
6127 | in which we are not using $at). */ | |
6128 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6129 | if (HAVE_NEWABI) |
6130 | { | |
67c0d1eb RS |
6131 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6132 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6133 | if (breg != 0) |
67c0d1eb | 6134 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6135 | tempreg, tempreg, breg); |
67c0d1eb | 6136 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6137 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6138 | |
6139 | if (! used_at) | |
6140 | return; | |
6141 | ||
6142 | break; | |
6143 | } | |
252b5132 RH |
6144 | expr1.X_add_number = offset_expr.X_add_number; |
6145 | offset_expr.X_add_number = 0; | |
6146 | if (expr1.X_add_number < -0x8000 | |
6147 | || expr1.X_add_number >= 0x8000) | |
6148 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6149 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6150 | lw_reloc_type, mips_gp_register); | |
6151 | macro_build (NULL, "nop", ""); | |
4d7206a2 RS |
6152 | relax_start (offset_expr.X_add_symbol); |
6153 | relax_switch (); | |
67c0d1eb RS |
6154 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6155 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6156 | relax_end (); |
252b5132 | 6157 | if (breg != 0) |
67c0d1eb | 6158 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6159 | tempreg, tempreg, breg); |
67c0d1eb | 6160 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6161 | } |
f5040a92 | 6162 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6163 | { |
67c0d1eb | 6164 | int gpdelay; |
252b5132 RH |
6165 | |
6166 | /* If this is a reference to an external symbol, we want | |
6167 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6168 | addu $tempreg,$tempreg,$gp | |
6169 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6170 | <op> $treg,0($tempreg) | |
6171 | Otherwise we want | |
6172 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6173 | nop | |
6174 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6175 | <op> $treg,0($tempreg) | |
6176 | If there is a base register, we add it to $tempreg before | |
6177 | the <op>. If there is a constant, we stick it in the | |
6178 | <op> instruction. We don't handle constants larger than | |
6179 | 16 bits, because we have no way to load the upper 16 bits | |
6180 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6181 | in which we are not using $at). */ |
252b5132 RH |
6182 | assert (offset_expr.X_op == O_symbol); |
6183 | expr1.X_add_number = offset_expr.X_add_number; | |
6184 | offset_expr.X_add_number = 0; | |
6185 | if (expr1.X_add_number < -0x8000 | |
6186 | || expr1.X_add_number >= 0x8000) | |
6187 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6188 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6189 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6190 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6191 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6192 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6193 | mips_gp_register); | |
6194 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6195 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6196 | relax_switch (); |
67c0d1eb RS |
6197 | if (gpdelay) |
6198 | macro_build (NULL, "nop", ""); | |
6199 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6200 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
6201 | macro_build (NULL, "nop", ""); | |
6202 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6203 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6204 | relax_end (); |
6205 | ||
252b5132 | 6206 | if (breg != 0) |
67c0d1eb | 6207 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6208 | tempreg, tempreg, breg); |
67c0d1eb | 6209 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6210 | } |
f5040a92 AO |
6211 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6212 | { | |
f5040a92 AO |
6213 | /* If this is a reference to an external symbol, we want |
6214 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6215 | add $tempreg,$tempreg,$gp | |
6216 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6217 | <op> $treg,<ofst>($tempreg) | |
6218 | Otherwise, for local symbols, we want: | |
6219 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6220 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6221 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6222 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6223 | offset_expr.X_add_number = 0; |
6224 | if (expr1.X_add_number < -0x8000 | |
6225 | || expr1.X_add_number >= 0x8000) | |
6226 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6227 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6228 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6229 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6230 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6231 | mips_gp_register); | |
6232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6233 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6234 | if (breg != 0) |
67c0d1eb | 6235 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6236 | tempreg, tempreg, breg); |
67c0d1eb | 6237 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6238 | |
4d7206a2 | 6239 | relax_switch (); |
f5040a92 | 6240 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6241 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6242 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6243 | if (breg != 0) |
67c0d1eb | 6244 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6245 | tempreg, tempreg, breg); |
67c0d1eb | 6246 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6247 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6248 | relax_end (); |
f5040a92 | 6249 | } |
252b5132 RH |
6250 | else if (mips_pic == EMBEDDED_PIC) |
6251 | { | |
6252 | /* If there is no base register, we want | |
cdf6fd85 | 6253 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6254 | If there is a base register, we want |
6255 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6256 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6257 | */ |
6258 | assert (offset_expr.X_op == O_symbol); | |
6259 | if (breg == 0) | |
6260 | { | |
67c0d1eb RS |
6261 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6262 | mips_gp_register); | |
252b5132 RH |
6263 | used_at = 0; |
6264 | } | |
6265 | else | |
6266 | { | |
67c0d1eb | 6267 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6268 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6269 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6270 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6271 | } |
6272 | } | |
6273 | else | |
6274 | abort (); | |
6275 | ||
6276 | if (! used_at) | |
6277 | return; | |
6278 | ||
6279 | break; | |
6280 | ||
6281 | case M_LI: | |
6282 | case M_LI_S: | |
67c0d1eb | 6283 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6284 | return; |
6285 | ||
6286 | case M_DLI: | |
67c0d1eb | 6287 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6288 | return; |
6289 | ||
6290 | case M_LI_SS: | |
6291 | if (imm_expr.X_op == O_constant) | |
6292 | { | |
67c0d1eb RS |
6293 | load_register (AT, &imm_expr, 0); |
6294 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6295 | break; |
6296 | } | |
6297 | else | |
6298 | { | |
6299 | assert (offset_expr.X_op == O_symbol | |
6300 | && strcmp (segment_name (S_GET_SEGMENT | |
6301 | (offset_expr.X_add_symbol)), | |
6302 | ".lit4") == 0 | |
6303 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6304 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6305 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6306 | return; |
6307 | } | |
6308 | ||
6309 | case M_LI_D: | |
ca4e0257 RS |
6310 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6311 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6312 | order 32 bits of the value and the low order 32 bits are either | |
6313 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6314 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6315 | { | |
ca4e0257 | 6316 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6317 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6318 | else |
6319 | { | |
6320 | int hreg, lreg; | |
6321 | ||
6322 | if (target_big_endian) | |
6323 | { | |
6324 | hreg = treg; | |
6325 | lreg = treg + 1; | |
6326 | } | |
6327 | else | |
6328 | { | |
6329 | hreg = treg + 1; | |
6330 | lreg = treg; | |
6331 | } | |
6332 | ||
6333 | if (hreg <= 31) | |
67c0d1eb | 6334 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6335 | if (lreg <= 31) |
6336 | { | |
6337 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6338 | move_register (lreg, 0); |
252b5132 RH |
6339 | else |
6340 | { | |
6341 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6342 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6343 | } |
6344 | } | |
6345 | } | |
6346 | return; | |
6347 | } | |
6348 | ||
6349 | /* We know that sym is in the .rdata section. First we get the | |
6350 | upper 16 bits of the address. */ | |
6351 | if (mips_pic == NO_PIC) | |
6352 | { | |
67c0d1eb | 6353 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6354 | } |
6355 | else if (mips_pic == SVR4_PIC) | |
6356 | { | |
67c0d1eb RS |
6357 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6358 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6359 | } |
6360 | else if (mips_pic == EMBEDDED_PIC) | |
6361 | { | |
6362 | /* For embedded PIC we pick up the entire address off $gp in | |
6363 | a single instruction. */ | |
67c0d1eb RS |
6364 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, |
6365 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
6366 | offset_expr.X_op = O_constant; |
6367 | offset_expr.X_add_number = 0; | |
6368 | } | |
6369 | else | |
6370 | abort (); | |
bdaaa2e1 | 6371 | |
252b5132 | 6372 | /* Now we load the register(s). */ |
ca4e0257 | 6373 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6374 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6375 | else |
6376 | { | |
67c0d1eb | 6377 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6378 | if (treg != RA) |
252b5132 RH |
6379 | { |
6380 | /* FIXME: How in the world do we deal with the possible | |
6381 | overflow here? */ | |
6382 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6383 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6384 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6385 | } |
6386 | } | |
252b5132 RH |
6387 | break; |
6388 | ||
6389 | case M_LI_DD: | |
ca4e0257 RS |
6390 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6391 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6392 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6393 | the value and the low order 32 bits are either zero or in | |
6394 | OFFSET_EXPR. */ | |
252b5132 RH |
6395 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6396 | { | |
67c0d1eb | 6397 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6398 | if (HAVE_64BIT_FPRS) |
6399 | { | |
6400 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6401 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6402 | } |
252b5132 RH |
6403 | else |
6404 | { | |
67c0d1eb | 6405 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6406 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6407 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6408 | else |
6409 | { | |
6410 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6411 | load_register (AT, &offset_expr, 0); |
6412 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6413 | } |
6414 | } | |
6415 | break; | |
6416 | } | |
6417 | ||
6418 | assert (offset_expr.X_op == O_symbol | |
6419 | && offset_expr.X_add_number == 0); | |
6420 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6421 | if (strcmp (s, ".lit8") == 0) | |
6422 | { | |
e7af610e | 6423 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6424 | { |
67c0d1eb | 6425 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6426 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6427 | return; |
6428 | } | |
c9914766 | 6429 | breg = mips_gp_register; |
252b5132 RH |
6430 | r = BFD_RELOC_MIPS_LITERAL; |
6431 | goto dob; | |
6432 | } | |
6433 | else | |
6434 | { | |
6435 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6436 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6437 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6438 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6439 | else |
6440 | { | |
6441 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6442 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6443 | } |
bdaaa2e1 | 6444 | |
e7af610e | 6445 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6446 | { |
67c0d1eb RS |
6447 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6448 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6449 | break; |
6450 | } | |
6451 | breg = AT; | |
6452 | r = BFD_RELOC_LO16; | |
6453 | goto dob; | |
6454 | } | |
6455 | ||
6456 | case M_L_DOB: | |
fef14a42 | 6457 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6458 | { |
6459 | as_bad (_("opcode not supported on this processor")); | |
6460 | return; | |
6461 | } | |
6462 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6463 | to adjust when loading from memory. */ | |
6464 | r = BFD_RELOC_LO16; | |
6465 | dob: | |
e7af610e | 6466 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6467 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6468 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6469 | /* FIXME: A possible overflow which I don't know how to deal |
6470 | with. */ | |
6471 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6472 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6473 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6474 | |
252b5132 RH |
6475 | if (breg != AT) |
6476 | return; | |
6477 | break; | |
6478 | ||
6479 | case M_L_DAB: | |
6480 | /* | |
6481 | * The MIPS assembler seems to check for X_add_number not | |
6482 | * being double aligned and generating: | |
6483 | * lui at,%hi(foo+1) | |
6484 | * addu at,at,v1 | |
6485 | * addiu at,at,%lo(foo+1) | |
6486 | * lwc1 f2,0(at) | |
6487 | * lwc1 f3,4(at) | |
6488 | * But, the resulting address is the same after relocation so why | |
6489 | * generate the extra instruction? | |
6490 | */ | |
fef14a42 | 6491 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6492 | { |
6493 | as_bad (_("opcode not supported on this processor")); | |
6494 | return; | |
6495 | } | |
bdaaa2e1 | 6496 | /* Itbl support may require additional care here. */ |
252b5132 | 6497 | coproc = 1; |
e7af610e | 6498 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6499 | { |
6500 | s = "ldc1"; | |
6501 | goto ld; | |
6502 | } | |
6503 | ||
6504 | s = "lwc1"; | |
6505 | fmt = "T,o(b)"; | |
6506 | goto ldd_std; | |
6507 | ||
6508 | case M_S_DAB: | |
fef14a42 | 6509 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6510 | { |
6511 | as_bad (_("opcode not supported on this processor")); | |
6512 | return; | |
6513 | } | |
6514 | ||
e7af610e | 6515 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6516 | { |
6517 | s = "sdc1"; | |
6518 | goto st; | |
6519 | } | |
6520 | ||
6521 | s = "swc1"; | |
6522 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6523 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6524 | coproc = 1; |
6525 | goto ldd_std; | |
6526 | ||
6527 | case M_LD_AB: | |
ca4e0257 | 6528 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6529 | { |
6530 | s = "ld"; | |
6531 | goto ld; | |
6532 | } | |
6533 | ||
6534 | s = "lw"; | |
6535 | fmt = "t,o(b)"; | |
6536 | goto ldd_std; | |
6537 | ||
6538 | case M_SD_AB: | |
ca4e0257 | 6539 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6540 | { |
6541 | s = "sd"; | |
6542 | goto st; | |
6543 | } | |
6544 | ||
6545 | s = "sw"; | |
6546 | fmt = "t,o(b)"; | |
6547 | ||
6548 | ldd_std: | |
afdbd6d0 CD |
6549 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6550 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6551 | This is not currently done by the compiler, and assembly coders | |
6552 | writing embedded-pic code can cope. */ | |
6553 | ||
252b5132 RH |
6554 | if (offset_expr.X_op != O_symbol |
6555 | && offset_expr.X_op != O_constant) | |
6556 | { | |
6557 | as_bad (_("expression too complex")); | |
6558 | offset_expr.X_op = O_constant; | |
6559 | } | |
6560 | ||
6561 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6562 | to adjust when loading from memory. We set coproc if we must | |
6563 | load $fn+1 first. */ | |
bdaaa2e1 | 6564 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6565 | if (! target_big_endian) |
6566 | coproc = 0; | |
6567 | ||
6568 | if (mips_pic == NO_PIC | |
6569 | || offset_expr.X_op == O_constant) | |
6570 | { | |
6571 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6572 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6573 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6574 | If we have a base register, we use this |
6575 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6576 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6577 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6578 | If this is not a GP relative symbol, we want |
6579 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6580 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6581 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6582 | If there is a base register, we add it to $at after the | |
6583 | lui instruction. If there is a constant, we always use | |
6584 | the last case. */ | |
e7d556df | 6585 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6586 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6587 | used_at = 1; |
252b5132 RH |
6588 | else |
6589 | { | |
4d7206a2 | 6590 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6591 | if (breg == 0) |
6592 | { | |
c9914766 | 6593 | tempreg = mips_gp_register; |
252b5132 RH |
6594 | used_at = 0; |
6595 | } | |
6596 | else | |
6597 | { | |
67c0d1eb | 6598 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6599 | AT, breg, mips_gp_register); |
252b5132 | 6600 | tempreg = AT; |
252b5132 RH |
6601 | used_at = 1; |
6602 | } | |
6603 | ||
beae10d5 | 6604 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6605 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6606 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6607 | offset_expr.X_add_number += 4; |
6608 | ||
6609 | /* Set mips_optimize to 2 to avoid inserting an | |
6610 | undesired nop. */ | |
6611 | hold_mips_optimize = mips_optimize; | |
6612 | mips_optimize = 2; | |
beae10d5 | 6613 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6614 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6615 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6616 | mips_optimize = hold_mips_optimize; |
6617 | ||
4d7206a2 | 6618 | relax_switch (); |
252b5132 RH |
6619 | |
6620 | /* We just generated two relocs. When tc_gen_reloc | |
6621 | handles this case, it will skip the first reloc and | |
6622 | handle the second. The second reloc already has an | |
6623 | extra addend of 4, which we added above. We must | |
6624 | subtract it out, and then subtract another 4 to make | |
6625 | the first reloc come out right. The second reloc | |
6626 | will come out right because we are going to add 4 to | |
6627 | offset_expr when we build its instruction below. | |
6628 | ||
6629 | If we have a symbol, then we don't want to include | |
6630 | the offset, because it will wind up being included | |
6631 | when we generate the reloc. */ | |
6632 | ||
6633 | if (offset_expr.X_op == O_constant) | |
6634 | offset_expr.X_add_number -= 8; | |
6635 | else | |
6636 | { | |
6637 | offset_expr.X_add_number = -4; | |
6638 | offset_expr.X_op = O_constant; | |
6639 | } | |
6640 | } | |
67c0d1eb | 6641 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6642 | if (breg != 0) |
67c0d1eb | 6643 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6644 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6645 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6646 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6647 | /* FIXME: How do we handle overflow here? */ |
6648 | offset_expr.X_add_number += 4; | |
beae10d5 | 6649 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6650 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6651 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6652 | if (mips_relax.sequence) |
6653 | relax_end (); | |
bdaaa2e1 | 6654 | } |
252b5132 RH |
6655 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6656 | { | |
252b5132 RH |
6657 | /* If this is a reference to an external symbol, we want |
6658 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6659 | nop | |
6660 | <op> $treg,0($at) | |
6661 | <op> $treg+1,4($at) | |
6662 | Otherwise we want | |
6663 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6664 | nop | |
6665 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6666 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6667 | If there is a base register we add it to $at before the | |
6668 | lwc1 instructions. If there is a constant we include it | |
6669 | in the lwc1 instructions. */ | |
6670 | used_at = 1; | |
6671 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6672 | if (expr1.X_add_number < -0x8000 |
6673 | || expr1.X_add_number >= 0x8000 - 4) | |
6674 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6675 | load_got_offset (AT, &offset_expr); |
6676 | macro_build (NULL, "nop", ""); | |
252b5132 | 6677 | if (breg != 0) |
67c0d1eb | 6678 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6679 | |
6680 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6681 | nop. */ | |
6682 | hold_mips_optimize = mips_optimize; | |
6683 | mips_optimize = 2; | |
4d7206a2 | 6684 | |
beae10d5 | 6685 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6686 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6687 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6688 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6689 | expr1.X_add_number += 4; |
67c0d1eb RS |
6690 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6691 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6692 | relax_switch (); |
67c0d1eb RS |
6693 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6694 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6695 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6696 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6697 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6698 | relax_end (); |
252b5132 | 6699 | |
4d7206a2 | 6700 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6701 | } |
6702 | else if (mips_pic == SVR4_PIC) | |
6703 | { | |
67c0d1eb | 6704 | int gpdelay; |
252b5132 RH |
6705 | |
6706 | /* If this is a reference to an external symbol, we want | |
6707 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6708 | addu $at,$at,$gp | |
6709 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6710 | nop | |
6711 | <op> $treg,0($at) | |
6712 | <op> $treg+1,4($at) | |
6713 | Otherwise we want | |
6714 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6715 | nop | |
6716 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6717 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6718 | If there is a base register we add it to $at before the | |
6719 | lwc1 instructions. If there is a constant we include it | |
6720 | in the lwc1 instructions. */ | |
6721 | used_at = 1; | |
6722 | expr1.X_add_number = offset_expr.X_add_number; | |
6723 | offset_expr.X_add_number = 0; | |
6724 | if (expr1.X_add_number < -0x8000 | |
6725 | || expr1.X_add_number >= 0x8000 - 4) | |
6726 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6727 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6728 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6729 | macro_build (&offset_expr, "lui", "t,u", |
6730 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6731 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6732 | AT, AT, mips_gp_register); |
67c0d1eb | 6733 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6734 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
67c0d1eb | 6735 | macro_build (NULL, "nop", ""); |
252b5132 | 6736 | if (breg != 0) |
67c0d1eb | 6737 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6738 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6739 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6740 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6741 | expr1.X_add_number += 4; |
6742 | ||
6743 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6744 | nop. */ | |
6745 | hold_mips_optimize = mips_optimize; | |
6746 | mips_optimize = 2; | |
beae10d5 | 6747 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6748 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6749 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6750 | mips_optimize = hold_mips_optimize; |
6751 | expr1.X_add_number -= 4; | |
6752 | ||
4d7206a2 RS |
6753 | relax_switch (); |
6754 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6755 | if (gpdelay) |
6756 | macro_build (NULL, "nop", ""); | |
6757 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6758 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
6759 | macro_build (NULL, "nop", ""); | |
252b5132 | 6760 | if (breg != 0) |
67c0d1eb | 6761 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6762 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6763 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6764 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6765 | offset_expr.X_add_number += 4; |
252b5132 RH |
6766 | |
6767 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6768 | nop. */ | |
6769 | hold_mips_optimize = mips_optimize; | |
6770 | mips_optimize = 2; | |
beae10d5 | 6771 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6772 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6773 | BFD_RELOC_LO16, AT); | |
252b5132 | 6774 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6775 | relax_end (); |
252b5132 RH |
6776 | } |
6777 | else if (mips_pic == EMBEDDED_PIC) | |
6778 | { | |
6779 | /* If there is no base register, we use | |
cdf6fd85 TS |
6780 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6781 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6782 | If we have a base register, we use |
6783 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6784 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6785 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6786 | */ |
6787 | if (breg == 0) | |
6788 | { | |
c9914766 | 6789 | tempreg = mips_gp_register; |
252b5132 RH |
6790 | used_at = 0; |
6791 | } | |
6792 | else | |
6793 | { | |
67c0d1eb | 6794 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6795 | AT, breg, mips_gp_register); |
252b5132 RH |
6796 | tempreg = AT; |
6797 | used_at = 1; | |
6798 | } | |
6799 | ||
beae10d5 | 6800 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6801 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6802 | BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6803 | offset_expr.X_add_number += 4; |
beae10d5 | 6804 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6805 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6806 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6807 | } |
6808 | else | |
6809 | abort (); | |
6810 | ||
6811 | if (! used_at) | |
6812 | return; | |
6813 | ||
6814 | break; | |
6815 | ||
6816 | case M_LD_OB: | |
6817 | s = "lw"; | |
6818 | goto sd_ob; | |
6819 | case M_SD_OB: | |
6820 | s = "sw"; | |
6821 | sd_ob: | |
ca4e0257 | 6822 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6823 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6824 | offset_expr.X_add_number += 4; |
67c0d1eb | 6825 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6826 | return; |
6827 | ||
6828 | /* New code added to support COPZ instructions. | |
6829 | This code builds table entries out of the macros in mip_opcodes. | |
6830 | R4000 uses interlocks to handle coproc delays. | |
6831 | Other chips (like the R3000) require nops to be inserted for delays. | |
6832 | ||
f72c8c98 | 6833 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6834 | In order to fill delay slots for non-interlocked chips, |
6835 | we must have a way to specify delays based on the coprocessor. | |
6836 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6837 | What are the side-effects of the cop instruction? | |
6838 | What cache support might we have and what are its effects? | |
6839 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6840 | What registers are read/set/modified? |
252b5132 RH |
6841 | |
6842 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6843 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6844 | |
6845 | case M_COP0: | |
6846 | s = "c0"; | |
6847 | goto copz; | |
6848 | case M_COP1: | |
6849 | s = "c1"; | |
6850 | goto copz; | |
6851 | case M_COP2: | |
6852 | s = "c2"; | |
6853 | goto copz; | |
6854 | case M_COP3: | |
6855 | s = "c3"; | |
6856 | copz: | |
6857 | /* For now we just do C (same as Cz). The parameter will be | |
6858 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6859 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6860 | return; |
6861 | ||
ea1fb5dc | 6862 | case M_MOVE: |
67c0d1eb | 6863 | move_register (dreg, sreg); |
ea1fb5dc RS |
6864 | return; |
6865 | ||
252b5132 RH |
6866 | #ifdef LOSING_COMPILER |
6867 | default: | |
6868 | /* Try and see if this is a new itbl instruction. | |
6869 | This code builds table entries out of the macros in mip_opcodes. | |
6870 | FIXME: For now we just assemble the expression and pass it's | |
6871 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6872 | We may want to have the assembler assemble this value, |
252b5132 RH |
6873 | so that we gain the assembler's knowledge of delay slots, |
6874 | symbols, etc. | |
6875 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6876 | if (itbl_have_entries |
252b5132 | 6877 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6878 | { |
252b5132 RH |
6879 | s = ip->insn_mo->name; |
6880 | s2 = "cop3"; | |
6881 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6882 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6883 | return; |
beae10d5 | 6884 | } |
252b5132 RH |
6885 | macro2 (ip); |
6886 | return; | |
6887 | } | |
6888 | if (mips_opts.noat) | |
6889 | as_warn (_("Macro used $at after \".set noat\"")); | |
6890 | } | |
bdaaa2e1 | 6891 | |
252b5132 | 6892 | static void |
17a2f251 | 6893 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6894 | { |
6895 | register int treg, sreg, dreg, breg; | |
6896 | int tempreg; | |
6897 | int mask; | |
252b5132 RH |
6898 | int used_at; |
6899 | expressionS expr1; | |
6900 | const char *s; | |
6901 | const char *s2; | |
6902 | const char *fmt; | |
6903 | int likely = 0; | |
6904 | int dbl = 0; | |
6905 | int coproc = 0; | |
6906 | int lr = 0; | |
6907 | int imm = 0; | |
6908 | int off; | |
6909 | offsetT maxnum; | |
6910 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6911 | |
252b5132 RH |
6912 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6913 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6914 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6915 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6916 | |
252b5132 RH |
6917 | expr1.X_op = O_constant; |
6918 | expr1.X_op_symbol = NULL; | |
6919 | expr1.X_add_symbol = NULL; | |
6920 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6921 | |
252b5132 RH |
6922 | switch (mask) |
6923 | { | |
6924 | #endif /* LOSING_COMPILER */ | |
6925 | ||
6926 | case M_DMUL: | |
6927 | dbl = 1; | |
6928 | case M_MUL: | |
67c0d1eb RS |
6929 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6930 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6931 | return; |
6932 | ||
6933 | case M_DMUL_I: | |
6934 | dbl = 1; | |
6935 | case M_MUL_I: | |
6936 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6937 | not trying to be that fancy. GCC should do this for us | |
6938 | anyway. */ | |
67c0d1eb RS |
6939 | load_register (AT, &imm_expr, dbl); |
6940 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6941 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6942 | break; |
6943 | ||
6944 | case M_DMULO_I: | |
6945 | dbl = 1; | |
6946 | case M_MULO_I: | |
6947 | imm = 1; | |
6948 | goto do_mulo; | |
6949 | ||
6950 | case M_DMULO: | |
6951 | dbl = 1; | |
6952 | case M_MULO: | |
6953 | do_mulo: | |
b34976b6 | 6954 | mips_emit_delays (TRUE); |
252b5132 RH |
6955 | ++mips_opts.noreorder; |
6956 | mips_any_noreorder = 1; | |
6957 | if (imm) | |
67c0d1eb RS |
6958 | load_register (AT, &imm_expr, dbl); |
6959 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6960 | macro_build (NULL, "mflo", "d", dreg); | |
6961 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6962 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6963 | if (mips_trap) |
67c0d1eb | 6964 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6965 | else |
6966 | { | |
6967 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6968 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6969 | macro_build (NULL, "nop", "", 0); | |
6970 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6971 | } |
6972 | --mips_opts.noreorder; | |
67c0d1eb | 6973 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6974 | break; |
6975 | ||
6976 | case M_DMULOU_I: | |
6977 | dbl = 1; | |
6978 | case M_MULOU_I: | |
6979 | imm = 1; | |
6980 | goto do_mulou; | |
6981 | ||
6982 | case M_DMULOU: | |
6983 | dbl = 1; | |
6984 | case M_MULOU: | |
6985 | do_mulou: | |
b34976b6 | 6986 | mips_emit_delays (TRUE); |
252b5132 RH |
6987 | ++mips_opts.noreorder; |
6988 | mips_any_noreorder = 1; | |
6989 | if (imm) | |
67c0d1eb RS |
6990 | load_register (AT, &imm_expr, dbl); |
6991 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6992 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6993 | macro_build (NULL, "mfhi", "d", AT); |
6994 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6995 | if (mips_trap) |
67c0d1eb | 6996 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6997 | else |
6998 | { | |
6999 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7000 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7001 | macro_build (NULL, "nop", "", 0); | |
7002 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
7003 | } |
7004 | --mips_opts.noreorder; | |
7005 | break; | |
7006 | ||
771c7ce4 | 7007 | case M_DROL: |
fef14a42 | 7008 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7009 | { |
7010 | if (dreg == sreg) | |
7011 | { | |
7012 | tempreg = AT; | |
7013 | used_at = 1; | |
7014 | } | |
7015 | else | |
7016 | { | |
7017 | tempreg = dreg; | |
7018 | used_at = 0; | |
7019 | } | |
67c0d1eb RS |
7020 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7021 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
7022 | if (used_at) |
7023 | break; | |
7024 | return; | |
7025 | } | |
67c0d1eb RS |
7026 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7027 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7028 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7029 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7030 | break; |
7031 | ||
252b5132 | 7032 | case M_ROL: |
fef14a42 | 7033 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7034 | { |
7035 | if (dreg == sreg) | |
7036 | { | |
7037 | tempreg = AT; | |
7038 | used_at = 1; | |
7039 | } | |
7040 | else | |
7041 | { | |
7042 | tempreg = dreg; | |
7043 | used_at = 0; | |
7044 | } | |
67c0d1eb RS |
7045 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7046 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
7047 | if (used_at) |
7048 | break; | |
7049 | return; | |
7050 | } | |
67c0d1eb RS |
7051 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7052 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7053 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7054 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7055 | break; |
7056 | ||
771c7ce4 TS |
7057 | case M_DROL_I: |
7058 | { | |
7059 | unsigned int rot; | |
82dd0097 | 7060 | char *l, *r; |
771c7ce4 TS |
7061 | |
7062 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7063 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7064 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7065 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7066 | { |
7067 | rot = (64 - rot) & 0x3f; | |
7068 | if (rot >= 32) | |
67c0d1eb | 7069 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7070 | else |
67c0d1eb | 7071 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 7072 | return; |
60b63b72 | 7073 | } |
483fc7cd | 7074 | if (rot == 0) |
483fc7cd | 7075 | { |
67c0d1eb | 7076 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7077 | return; |
483fc7cd | 7078 | } |
82dd0097 CD |
7079 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7080 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7081 | rot &= 0x1f; | |
67c0d1eb RS |
7082 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7083 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7084 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7085 | } |
7086 | break; | |
7087 | ||
252b5132 | 7088 | case M_ROL_I: |
771c7ce4 TS |
7089 | { |
7090 | unsigned int rot; | |
7091 | ||
7092 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7093 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7094 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7095 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7096 | { |
67c0d1eb | 7097 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 7098 | return; |
60b63b72 | 7099 | } |
483fc7cd | 7100 | if (rot == 0) |
483fc7cd | 7101 | { |
67c0d1eb | 7102 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7103 | return; |
483fc7cd | 7104 | } |
67c0d1eb RS |
7105 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7106 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7107 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7108 | } |
7109 | break; | |
7110 | ||
7111 | case M_DROR: | |
fef14a42 | 7112 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7113 | { |
67c0d1eb | 7114 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7115 | return; |
7116 | } | |
67c0d1eb RS |
7117 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7118 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7119 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7120 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7121 | break; |
7122 | ||
7123 | case M_ROR: | |
fef14a42 | 7124 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7125 | { |
67c0d1eb | 7126 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7127 | return; |
7128 | } | |
67c0d1eb RS |
7129 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7130 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7131 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7132 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7133 | break; |
7134 | ||
771c7ce4 TS |
7135 | case M_DROR_I: |
7136 | { | |
7137 | unsigned int rot; | |
82dd0097 | 7138 | char *l, *r; |
771c7ce4 TS |
7139 | |
7140 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7141 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7142 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7143 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7144 | { |
7145 | if (rot >= 32) | |
67c0d1eb | 7146 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7147 | else |
67c0d1eb | 7148 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7149 | return; |
7150 | } | |
483fc7cd | 7151 | if (rot == 0) |
483fc7cd | 7152 | { |
67c0d1eb | 7153 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7154 | return; |
483fc7cd | 7155 | } |
82dd0097 CD |
7156 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7157 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7158 | rot &= 0x1f; | |
67c0d1eb RS |
7159 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7160 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7161 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7162 | } |
7163 | break; | |
7164 | ||
252b5132 | 7165 | case M_ROR_I: |
771c7ce4 TS |
7166 | { |
7167 | unsigned int rot; | |
7168 | ||
7169 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7170 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7171 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7172 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7173 | { |
67c0d1eb | 7174 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7175 | return; |
7176 | } | |
483fc7cd | 7177 | if (rot == 0) |
483fc7cd | 7178 | { |
67c0d1eb | 7179 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7180 | return; |
483fc7cd | 7181 | } |
67c0d1eb RS |
7182 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7183 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7184 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7185 | } |
252b5132 RH |
7186 | break; |
7187 | ||
7188 | case M_S_DOB: | |
fef14a42 | 7189 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7190 | { |
7191 | as_bad (_("opcode not supported on this processor")); | |
7192 | return; | |
7193 | } | |
e7af610e | 7194 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7195 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7196 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7197 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7198 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7199 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7200 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7201 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7202 | return; |
7203 | ||
7204 | case M_SEQ: | |
7205 | if (sreg == 0) | |
67c0d1eb | 7206 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7207 | else if (treg == 0) |
67c0d1eb | 7208 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7209 | else |
7210 | { | |
67c0d1eb RS |
7211 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7212 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7213 | } |
7214 | return; | |
7215 | ||
7216 | case M_SEQ_I: | |
7217 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7218 | { | |
67c0d1eb | 7219 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7220 | return; |
7221 | } | |
7222 | if (sreg == 0) | |
7223 | { | |
7224 | as_warn (_("Instruction %s: result is always false"), | |
7225 | ip->insn_mo->name); | |
67c0d1eb | 7226 | move_register (dreg, 0); |
252b5132 RH |
7227 | return; |
7228 | } | |
7229 | if (imm_expr.X_op == O_constant | |
7230 | && imm_expr.X_add_number >= 0 | |
7231 | && imm_expr.X_add_number < 0x10000) | |
7232 | { | |
67c0d1eb | 7233 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7234 | used_at = 0; |
7235 | } | |
7236 | else if (imm_expr.X_op == O_constant | |
7237 | && imm_expr.X_add_number > -0x8000 | |
7238 | && imm_expr.X_add_number < 0) | |
7239 | { | |
7240 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7241 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7242 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7243 | used_at = 0; |
7244 | } | |
7245 | else | |
7246 | { | |
67c0d1eb RS |
7247 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7248 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7249 | used_at = 1; |
7250 | } | |
67c0d1eb | 7251 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7252 | if (used_at) |
7253 | break; | |
7254 | return; | |
7255 | ||
7256 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7257 | s = "slt"; | |
7258 | goto sge; | |
7259 | case M_SGEU: | |
7260 | s = "sltu"; | |
7261 | sge: | |
67c0d1eb RS |
7262 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7263 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7264 | return; |
7265 | ||
7266 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7267 | case M_SGEU_I: | |
7268 | if (imm_expr.X_op == O_constant | |
7269 | && imm_expr.X_add_number >= -0x8000 | |
7270 | && imm_expr.X_add_number < 0x8000) | |
7271 | { | |
67c0d1eb RS |
7272 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7273 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7274 | used_at = 0; |
7275 | } | |
7276 | else | |
7277 | { | |
67c0d1eb RS |
7278 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7279 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7280 | dreg, sreg, AT); | |
252b5132 RH |
7281 | used_at = 1; |
7282 | } | |
67c0d1eb | 7283 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7284 | if (used_at) |
7285 | break; | |
7286 | return; | |
7287 | ||
7288 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7289 | s = "slt"; | |
7290 | goto sgt; | |
7291 | case M_SGTU: | |
7292 | s = "sltu"; | |
7293 | sgt: | |
67c0d1eb | 7294 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7295 | return; |
7296 | ||
7297 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7298 | s = "slt"; | |
7299 | goto sgti; | |
7300 | case M_SGTU_I: | |
7301 | s = "sltu"; | |
7302 | sgti: | |
67c0d1eb RS |
7303 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7304 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7305 | break; |
7306 | ||
2396cfb9 | 7307 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7308 | s = "slt"; |
7309 | goto sle; | |
7310 | case M_SLEU: | |
7311 | s = "sltu"; | |
7312 | sle: | |
67c0d1eb RS |
7313 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7314 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7315 | return; |
7316 | ||
2396cfb9 | 7317 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7318 | s = "slt"; |
7319 | goto slei; | |
7320 | case M_SLEU_I: | |
7321 | s = "sltu"; | |
7322 | slei: | |
67c0d1eb RS |
7323 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7324 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7325 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7326 | break; |
7327 | ||
7328 | case M_SLT_I: | |
7329 | if (imm_expr.X_op == O_constant | |
7330 | && imm_expr.X_add_number >= -0x8000 | |
7331 | && imm_expr.X_add_number < 0x8000) | |
7332 | { | |
67c0d1eb | 7333 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7334 | return; |
7335 | } | |
67c0d1eb RS |
7336 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7337 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7338 | break; |
7339 | ||
7340 | case M_SLTU_I: | |
7341 | if (imm_expr.X_op == O_constant | |
7342 | && imm_expr.X_add_number >= -0x8000 | |
7343 | && imm_expr.X_add_number < 0x8000) | |
7344 | { | |
67c0d1eb | 7345 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7346 | BFD_RELOC_LO16); |
252b5132 RH |
7347 | return; |
7348 | } | |
67c0d1eb RS |
7349 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7350 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7351 | break; |
7352 | ||
7353 | case M_SNE: | |
7354 | if (sreg == 0) | |
67c0d1eb | 7355 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7356 | else if (treg == 0) |
67c0d1eb | 7357 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7358 | else |
7359 | { | |
67c0d1eb RS |
7360 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7361 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7362 | } |
7363 | return; | |
7364 | ||
7365 | case M_SNE_I: | |
7366 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7367 | { | |
67c0d1eb | 7368 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7369 | return; |
7370 | } | |
7371 | if (sreg == 0) | |
7372 | { | |
7373 | as_warn (_("Instruction %s: result is always true"), | |
7374 | ip->insn_mo->name); | |
67c0d1eb RS |
7375 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7376 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7377 | return; |
7378 | } | |
7379 | if (imm_expr.X_op == O_constant | |
7380 | && imm_expr.X_add_number >= 0 | |
7381 | && imm_expr.X_add_number < 0x10000) | |
7382 | { | |
67c0d1eb | 7383 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7384 | used_at = 0; |
7385 | } | |
7386 | else if (imm_expr.X_op == O_constant | |
7387 | && imm_expr.X_add_number > -0x8000 | |
7388 | && imm_expr.X_add_number < 0) | |
7389 | { | |
7390 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7391 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7392 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7393 | used_at = 0; |
7394 | } | |
7395 | else | |
7396 | { | |
67c0d1eb RS |
7397 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7398 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7399 | used_at = 1; |
7400 | } | |
67c0d1eb | 7401 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7402 | if (used_at) |
7403 | break; | |
7404 | return; | |
7405 | ||
7406 | case M_DSUB_I: | |
7407 | dbl = 1; | |
7408 | case M_SUB_I: | |
7409 | if (imm_expr.X_op == O_constant | |
7410 | && imm_expr.X_add_number > -0x8000 | |
7411 | && imm_expr.X_add_number <= 0x8000) | |
7412 | { | |
7413 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7414 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7415 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7416 | return; |
7417 | } | |
67c0d1eb RS |
7418 | load_register (AT, &imm_expr, dbl); |
7419 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7420 | break; |
7421 | ||
7422 | case M_DSUBU_I: | |
7423 | dbl = 1; | |
7424 | case M_SUBU_I: | |
7425 | if (imm_expr.X_op == O_constant | |
7426 | && imm_expr.X_add_number > -0x8000 | |
7427 | && imm_expr.X_add_number <= 0x8000) | |
7428 | { | |
7429 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7430 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7431 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7432 | return; |
7433 | } | |
67c0d1eb RS |
7434 | load_register (AT, &imm_expr, dbl); |
7435 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7436 | break; |
7437 | ||
7438 | case M_TEQ_I: | |
7439 | s = "teq"; | |
7440 | goto trap; | |
7441 | case M_TGE_I: | |
7442 | s = "tge"; | |
7443 | goto trap; | |
7444 | case M_TGEU_I: | |
7445 | s = "tgeu"; | |
7446 | goto trap; | |
7447 | case M_TLT_I: | |
7448 | s = "tlt"; | |
7449 | goto trap; | |
7450 | case M_TLTU_I: | |
7451 | s = "tltu"; | |
7452 | goto trap; | |
7453 | case M_TNE_I: | |
7454 | s = "tne"; | |
7455 | trap: | |
67c0d1eb RS |
7456 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7457 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7458 | break; |
7459 | ||
252b5132 | 7460 | case M_TRUNCWS: |
43841e91 | 7461 | case M_TRUNCWD: |
e7af610e | 7462 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7463 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7464 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7465 | ||
7466 | /* | |
7467 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7468 | * or is there a reason for it? | |
7469 | */ | |
b34976b6 | 7470 | mips_emit_delays (TRUE); |
252b5132 RH |
7471 | ++mips_opts.noreorder; |
7472 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7473 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7474 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7475 | macro_build (NULL, "nop", ""); | |
252b5132 | 7476 | expr1.X_add_number = 3; |
67c0d1eb | 7477 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7478 | expr1.X_add_number = 2; |
67c0d1eb RS |
7479 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7480 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7481 | macro_build (NULL, "nop", ""); | |
7482 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7483 | dreg, sreg); | |
7484 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7485 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7486 | --mips_opts.noreorder; |
7487 | break; | |
7488 | ||
7489 | case M_ULH: | |
7490 | s = "lb"; | |
7491 | goto ulh; | |
7492 | case M_ULHU: | |
7493 | s = "lbu"; | |
7494 | ulh: | |
7495 | if (offset_expr.X_add_number >= 0x7fff) | |
7496 | as_bad (_("operand overflow")); | |
252b5132 | 7497 | if (! target_big_endian) |
f9419b05 | 7498 | ++offset_expr.X_add_number; |
67c0d1eb | 7499 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7500 | if (! target_big_endian) |
f9419b05 | 7501 | --offset_expr.X_add_number; |
252b5132 | 7502 | else |
f9419b05 | 7503 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7504 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7505 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7506 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7507 | break; |
7508 | ||
7509 | case M_ULD: | |
7510 | s = "ldl"; | |
7511 | s2 = "ldr"; | |
7512 | off = 7; | |
7513 | goto ulw; | |
7514 | case M_ULW: | |
7515 | s = "lwl"; | |
7516 | s2 = "lwr"; | |
7517 | off = 3; | |
7518 | ulw: | |
7519 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7520 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7521 | if (treg != breg) |
7522 | tempreg = treg; | |
7523 | else | |
7524 | tempreg = AT; | |
252b5132 RH |
7525 | if (! target_big_endian) |
7526 | offset_expr.X_add_number += off; | |
67c0d1eb | 7527 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7528 | if (! target_big_endian) |
7529 | offset_expr.X_add_number -= off; | |
7530 | else | |
7531 | offset_expr.X_add_number += off; | |
67c0d1eb | 7532 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7533 | |
7534 | /* If necessary, move the result in tempreg the final destination. */ | |
7535 | if (treg == tempreg) | |
7536 | return; | |
7537 | /* Protect second load's delay slot. */ | |
7538 | if (!gpr_interlocks) | |
67c0d1eb RS |
7539 | macro_build (NULL, "nop", ""); |
7540 | move_register (treg, tempreg); | |
af22f5b2 | 7541 | break; |
252b5132 RH |
7542 | |
7543 | case M_ULD_A: | |
7544 | s = "ldl"; | |
7545 | s2 = "ldr"; | |
7546 | off = 7; | |
7547 | goto ulwa; | |
7548 | case M_ULW_A: | |
7549 | s = "lwl"; | |
7550 | s2 = "lwr"; | |
7551 | off = 3; | |
7552 | ulwa: | |
d6bc6245 | 7553 | used_at = 1; |
67c0d1eb | 7554 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7555 | if (breg != 0) |
67c0d1eb | 7556 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7557 | if (! target_big_endian) |
7558 | expr1.X_add_number = off; | |
7559 | else | |
7560 | expr1.X_add_number = 0; | |
67c0d1eb | 7561 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7562 | if (! target_big_endian) |
7563 | expr1.X_add_number = 0; | |
7564 | else | |
7565 | expr1.X_add_number = off; | |
67c0d1eb | 7566 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7567 | break; |
7568 | ||
7569 | case M_ULH_A: | |
7570 | case M_ULHU_A: | |
d6bc6245 | 7571 | used_at = 1; |
67c0d1eb | 7572 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7573 | if (breg != 0) |
67c0d1eb | 7574 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7575 | if (target_big_endian) |
7576 | expr1.X_add_number = 0; | |
67c0d1eb | 7577 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7578 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7579 | if (target_big_endian) |
7580 | expr1.X_add_number = 1; | |
7581 | else | |
7582 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7583 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7584 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7585 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7586 | break; |
7587 | ||
7588 | case M_USH: | |
7589 | if (offset_expr.X_add_number >= 0x7fff) | |
7590 | as_bad (_("operand overflow")); | |
7591 | if (target_big_endian) | |
f9419b05 | 7592 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7593 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7594 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7595 | if (target_big_endian) |
f9419b05 | 7596 | --offset_expr.X_add_number; |
252b5132 | 7597 | else |
f9419b05 | 7598 | ++offset_expr.X_add_number; |
67c0d1eb | 7599 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7600 | break; |
7601 | ||
7602 | case M_USD: | |
7603 | s = "sdl"; | |
7604 | s2 = "sdr"; | |
7605 | off = 7; | |
7606 | goto usw; | |
7607 | case M_USW: | |
7608 | s = "swl"; | |
7609 | s2 = "swr"; | |
7610 | off = 3; | |
7611 | usw: | |
7612 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7613 | as_bad (_("operand overflow")); | |
7614 | if (! target_big_endian) | |
7615 | offset_expr.X_add_number += off; | |
67c0d1eb | 7616 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7617 | if (! target_big_endian) |
7618 | offset_expr.X_add_number -= off; | |
7619 | else | |
7620 | offset_expr.X_add_number += off; | |
67c0d1eb | 7621 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7622 | return; |
7623 | ||
7624 | case M_USD_A: | |
7625 | s = "sdl"; | |
7626 | s2 = "sdr"; | |
7627 | off = 7; | |
7628 | goto uswa; | |
7629 | case M_USW_A: | |
7630 | s = "swl"; | |
7631 | s2 = "swr"; | |
7632 | off = 3; | |
7633 | uswa: | |
d6bc6245 | 7634 | used_at = 1; |
67c0d1eb | 7635 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7636 | if (breg != 0) |
67c0d1eb | 7637 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7638 | if (! target_big_endian) |
7639 | expr1.X_add_number = off; | |
7640 | else | |
7641 | expr1.X_add_number = 0; | |
67c0d1eb | 7642 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7643 | if (! target_big_endian) |
7644 | expr1.X_add_number = 0; | |
7645 | else | |
7646 | expr1.X_add_number = off; | |
67c0d1eb | 7647 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7648 | break; |
7649 | ||
7650 | case M_USH_A: | |
d6bc6245 | 7651 | used_at = 1; |
67c0d1eb | 7652 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7653 | if (breg != 0) |
67c0d1eb | 7654 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7655 | if (! target_big_endian) |
7656 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7657 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7658 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7659 | if (! target_big_endian) |
7660 | expr1.X_add_number = 1; | |
7661 | else | |
7662 | expr1.X_add_number = 0; | |
67c0d1eb | 7663 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7664 | if (! target_big_endian) |
7665 | expr1.X_add_number = 0; | |
7666 | else | |
7667 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7668 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7669 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7670 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7671 | break; |
7672 | ||
7673 | default: | |
7674 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7675 | are added dynamically. */ |
252b5132 RH |
7676 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7677 | break; | |
7678 | } | |
7679 | if (mips_opts.noat) | |
7680 | as_warn (_("Macro used $at after \".set noat\"")); | |
7681 | } | |
7682 | ||
7683 | /* Implement macros in mips16 mode. */ | |
7684 | ||
7685 | static void | |
17a2f251 | 7686 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7687 | { |
7688 | int mask; | |
7689 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7690 | expressionS expr1; |
7691 | int dbl; | |
7692 | const char *s, *s2, *s3; | |
7693 | ||
7694 | mask = ip->insn_mo->mask; | |
7695 | ||
7696 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7697 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7698 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7699 | ||
252b5132 RH |
7700 | expr1.X_op = O_constant; |
7701 | expr1.X_op_symbol = NULL; | |
7702 | expr1.X_add_symbol = NULL; | |
7703 | expr1.X_add_number = 1; | |
7704 | ||
7705 | dbl = 0; | |
7706 | ||
7707 | switch (mask) | |
7708 | { | |
7709 | default: | |
7710 | internalError (); | |
7711 | ||
7712 | case M_DDIV_3: | |
7713 | dbl = 1; | |
7714 | case M_DIV_3: | |
7715 | s = "mflo"; | |
7716 | goto do_div3; | |
7717 | case M_DREM_3: | |
7718 | dbl = 1; | |
7719 | case M_REM_3: | |
7720 | s = "mfhi"; | |
7721 | do_div3: | |
b34976b6 | 7722 | mips_emit_delays (TRUE); |
252b5132 RH |
7723 | ++mips_opts.noreorder; |
7724 | mips_any_noreorder = 1; | |
67c0d1eb | 7725 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7726 | expr1.X_add_number = 2; |
67c0d1eb RS |
7727 | macro_build (&expr1, "bnez", "x,p", yreg); |
7728 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7729 | |
252b5132 RH |
7730 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7731 | since that causes an overflow. We should do that as well, | |
7732 | but I don't see how to do the comparisons without a temporary | |
7733 | register. */ | |
7734 | --mips_opts.noreorder; | |
67c0d1eb | 7735 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7736 | break; |
7737 | ||
7738 | case M_DIVU_3: | |
7739 | s = "divu"; | |
7740 | s2 = "mflo"; | |
7741 | goto do_divu3; | |
7742 | case M_REMU_3: | |
7743 | s = "divu"; | |
7744 | s2 = "mfhi"; | |
7745 | goto do_divu3; | |
7746 | case M_DDIVU_3: | |
7747 | s = "ddivu"; | |
7748 | s2 = "mflo"; | |
7749 | goto do_divu3; | |
7750 | case M_DREMU_3: | |
7751 | s = "ddivu"; | |
7752 | s2 = "mfhi"; | |
7753 | do_divu3: | |
b34976b6 | 7754 | mips_emit_delays (TRUE); |
252b5132 RH |
7755 | ++mips_opts.noreorder; |
7756 | mips_any_noreorder = 1; | |
67c0d1eb | 7757 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7758 | expr1.X_add_number = 2; |
67c0d1eb RS |
7759 | macro_build (&expr1, "bnez", "x,p", yreg); |
7760 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7761 | --mips_opts.noreorder; |
67c0d1eb | 7762 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7763 | break; |
7764 | ||
7765 | case M_DMUL: | |
7766 | dbl = 1; | |
7767 | case M_MUL: | |
67c0d1eb RS |
7768 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7769 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7770 | return; |
7771 | ||
7772 | case M_DSUBU_I: | |
7773 | dbl = 1; | |
7774 | goto do_subu; | |
7775 | case M_SUBU_I: | |
7776 | do_subu: | |
7777 | if (imm_expr.X_op != O_constant) | |
7778 | as_bad (_("Unsupported large constant")); | |
7779 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7780 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7781 | break; |
7782 | ||
7783 | case M_SUBU_I_2: | |
7784 | if (imm_expr.X_op != O_constant) | |
7785 | as_bad (_("Unsupported large constant")); | |
7786 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7787 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7788 | break; |
7789 | ||
7790 | case M_DSUBU_I_2: | |
7791 | if (imm_expr.X_op != O_constant) | |
7792 | as_bad (_("Unsupported large constant")); | |
7793 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7794 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7795 | break; |
7796 | ||
7797 | case M_BEQ: | |
7798 | s = "cmp"; | |
7799 | s2 = "bteqz"; | |
7800 | goto do_branch; | |
7801 | case M_BNE: | |
7802 | s = "cmp"; | |
7803 | s2 = "btnez"; | |
7804 | goto do_branch; | |
7805 | case M_BLT: | |
7806 | s = "slt"; | |
7807 | s2 = "btnez"; | |
7808 | goto do_branch; | |
7809 | case M_BLTU: | |
7810 | s = "sltu"; | |
7811 | s2 = "btnez"; | |
7812 | goto do_branch; | |
7813 | case M_BLE: | |
7814 | s = "slt"; | |
7815 | s2 = "bteqz"; | |
7816 | goto do_reverse_branch; | |
7817 | case M_BLEU: | |
7818 | s = "sltu"; | |
7819 | s2 = "bteqz"; | |
7820 | goto do_reverse_branch; | |
7821 | case M_BGE: | |
7822 | s = "slt"; | |
7823 | s2 = "bteqz"; | |
7824 | goto do_branch; | |
7825 | case M_BGEU: | |
7826 | s = "sltu"; | |
7827 | s2 = "bteqz"; | |
7828 | goto do_branch; | |
7829 | case M_BGT: | |
7830 | s = "slt"; | |
7831 | s2 = "btnez"; | |
7832 | goto do_reverse_branch; | |
7833 | case M_BGTU: | |
7834 | s = "sltu"; | |
7835 | s2 = "btnez"; | |
7836 | ||
7837 | do_reverse_branch: | |
7838 | tmp = xreg; | |
7839 | xreg = yreg; | |
7840 | yreg = tmp; | |
7841 | ||
7842 | do_branch: | |
67c0d1eb RS |
7843 | macro_build (NULL, s, "x,y", xreg, yreg); |
7844 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7845 | break; |
7846 | ||
7847 | case M_BEQ_I: | |
7848 | s = "cmpi"; | |
7849 | s2 = "bteqz"; | |
7850 | s3 = "x,U"; | |
7851 | goto do_branch_i; | |
7852 | case M_BNE_I: | |
7853 | s = "cmpi"; | |
7854 | s2 = "btnez"; | |
7855 | s3 = "x,U"; | |
7856 | goto do_branch_i; | |
7857 | case M_BLT_I: | |
7858 | s = "slti"; | |
7859 | s2 = "btnez"; | |
7860 | s3 = "x,8"; | |
7861 | goto do_branch_i; | |
7862 | case M_BLTU_I: | |
7863 | s = "sltiu"; | |
7864 | s2 = "btnez"; | |
7865 | s3 = "x,8"; | |
7866 | goto do_branch_i; | |
7867 | case M_BLE_I: | |
7868 | s = "slti"; | |
7869 | s2 = "btnez"; | |
7870 | s3 = "x,8"; | |
7871 | goto do_addone_branch_i; | |
7872 | case M_BLEU_I: | |
7873 | s = "sltiu"; | |
7874 | s2 = "btnez"; | |
7875 | s3 = "x,8"; | |
7876 | goto do_addone_branch_i; | |
7877 | case M_BGE_I: | |
7878 | s = "slti"; | |
7879 | s2 = "bteqz"; | |
7880 | s3 = "x,8"; | |
7881 | goto do_branch_i; | |
7882 | case M_BGEU_I: | |
7883 | s = "sltiu"; | |
7884 | s2 = "bteqz"; | |
7885 | s3 = "x,8"; | |
7886 | goto do_branch_i; | |
7887 | case M_BGT_I: | |
7888 | s = "slti"; | |
7889 | s2 = "bteqz"; | |
7890 | s3 = "x,8"; | |
7891 | goto do_addone_branch_i; | |
7892 | case M_BGTU_I: | |
7893 | s = "sltiu"; | |
7894 | s2 = "bteqz"; | |
7895 | s3 = "x,8"; | |
7896 | ||
7897 | do_addone_branch_i: | |
7898 | if (imm_expr.X_op != O_constant) | |
7899 | as_bad (_("Unsupported large constant")); | |
7900 | ++imm_expr.X_add_number; | |
7901 | ||
7902 | do_branch_i: | |
67c0d1eb RS |
7903 | macro_build (&imm_expr, s, s3, xreg); |
7904 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7905 | break; |
7906 | ||
7907 | case M_ABS: | |
7908 | expr1.X_add_number = 0; | |
67c0d1eb | 7909 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7910 | if (xreg != yreg) |
67c0d1eb | 7911 | move_register (xreg, yreg); |
252b5132 | 7912 | expr1.X_add_number = 2; |
67c0d1eb RS |
7913 | macro_build (&expr1, "bteqz", "p"); |
7914 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7915 | } |
7916 | } | |
7917 | ||
7918 | /* For consistency checking, verify that all bits are specified either | |
7919 | by the match/mask part of the instruction definition, or by the | |
7920 | operand list. */ | |
7921 | static int | |
17a2f251 | 7922 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7923 | { |
7924 | const char *p = opc->args; | |
7925 | char c; | |
7926 | unsigned long used_bits = opc->mask; | |
7927 | ||
7928 | if ((used_bits & opc->match) != opc->match) | |
7929 | { | |
7930 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7931 | opc->name, opc->args); | |
7932 | return 0; | |
7933 | } | |
7934 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7935 | while (*p) | |
7936 | switch (c = *p++) | |
7937 | { | |
7938 | case ',': break; | |
7939 | case '(': break; | |
7940 | case ')': break; | |
af7ee8bf CD |
7941 | case '+': |
7942 | switch (c = *p++) | |
7943 | { | |
7944 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7945 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7946 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7947 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7948 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7949 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7950 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7951 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7952 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7953 | case 'I': break; | |
af7ee8bf CD |
7954 | default: |
7955 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7956 | c, opc->name, opc->args); | |
7957 | return 0; | |
7958 | } | |
7959 | break; | |
252b5132 RH |
7960 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7961 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7962 | case 'A': break; | |
4372b673 | 7963 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7964 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7965 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7966 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7967 | case 'F': break; | |
7968 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7969 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7970 | case 'I': break; |
e972090a | 7971 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7972 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7973 | case 'L': break; |
7974 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7975 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7976 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7977 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7978 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7979 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7980 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7981 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7982 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7983 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7984 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7985 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7986 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7987 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7988 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7989 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7990 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7991 | case 'f': break; | |
7992 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7993 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7994 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7995 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7996 | case 'l': break; | |
7997 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7998 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7999 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8000 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8001 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8002 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8003 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8004 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8005 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8006 | case 'x': break; | |
8007 | case 'z': break; | |
8008 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8009 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8010 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8011 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8012 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8013 | case '[': break; | |
8014 | case ']': break; | |
252b5132 RH |
8015 | default: |
8016 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8017 | c, opc->name, opc->args); | |
8018 | return 0; | |
8019 | } | |
8020 | #undef USE_BITS | |
8021 | if (used_bits != 0xffffffff) | |
8022 | { | |
8023 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8024 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8025 | return 0; | |
8026 | } | |
8027 | return 1; | |
8028 | } | |
8029 | ||
8030 | /* This routine assembles an instruction into its binary format. As a | |
8031 | side effect, it sets one of the global variables imm_reloc or | |
8032 | offset_reloc to the type of relocation to do if one of the operands | |
8033 | is an address expression. */ | |
8034 | ||
8035 | static void | |
17a2f251 | 8036 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8037 | { |
8038 | char *s; | |
8039 | const char *args; | |
43841e91 | 8040 | char c = 0; |
252b5132 RH |
8041 | struct mips_opcode *insn; |
8042 | char *argsStart; | |
8043 | unsigned int regno; | |
8044 | unsigned int lastregno = 0; | |
af7ee8bf | 8045 | unsigned int lastpos = 0; |
071742cf | 8046 | unsigned int limlo, limhi; |
252b5132 RH |
8047 | char *s_reset; |
8048 | char save_c = 0; | |
252b5132 RH |
8049 | |
8050 | insn_error = NULL; | |
8051 | ||
8052 | /* If the instruction contains a '.', we first try to match an instruction | |
8053 | including the '.'. Then we try again without the '.'. */ | |
8054 | insn = NULL; | |
3882b010 | 8055 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8056 | continue; |
8057 | ||
8058 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8059 | the call to hash_find. Save the character we replaced just in case we | |
8060 | have to re-parse the instruction. */ | |
3882b010 | 8061 | if (ISSPACE (*s)) |
252b5132 RH |
8062 | { |
8063 | save_c = *s; | |
8064 | *s++ = '\0'; | |
8065 | } | |
bdaaa2e1 | 8066 | |
252b5132 RH |
8067 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8068 | ||
8069 | /* If we didn't find the instruction in the opcode table, try again, but | |
8070 | this time with just the instruction up to, but not including the | |
8071 | first '.'. */ | |
8072 | if (insn == NULL) | |
8073 | { | |
bdaaa2e1 | 8074 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8075 | if (save_c) |
8076 | *(--s) = save_c; | |
8077 | ||
8078 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8079 | for (s = str; |
8080 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8081 | ++s) | |
252b5132 RH |
8082 | continue; |
8083 | ||
8084 | /* If we did not find a '.', then we can quit now. */ | |
8085 | if (*s != '.') | |
8086 | { | |
8087 | insn_error = "unrecognized opcode"; | |
8088 | return; | |
8089 | } | |
8090 | ||
8091 | /* Lookup the instruction in the hash table. */ | |
8092 | *s++ = '\0'; | |
8093 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8094 | { | |
8095 | insn_error = "unrecognized opcode"; | |
8096 | return; | |
8097 | } | |
252b5132 RH |
8098 | } |
8099 | ||
8100 | argsStart = s; | |
8101 | for (;;) | |
8102 | { | |
b34976b6 | 8103 | bfd_boolean ok; |
252b5132 RH |
8104 | |
8105 | assert (strcmp (insn->name, str) == 0); | |
8106 | ||
1f25f5d3 CD |
8107 | if (OPCODE_IS_MEMBER (insn, |
8108 | (mips_opts.isa | |
3396de36 | 8109 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8110 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8111 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8112 | mips_opts.arch)) |
b34976b6 | 8113 | ok = TRUE; |
bdaaa2e1 | 8114 | else |
b34976b6 | 8115 | ok = FALSE; |
bdaaa2e1 | 8116 | |
252b5132 RH |
8117 | if (insn->pinfo != INSN_MACRO) |
8118 | { | |
fef14a42 | 8119 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8120 | ok = FALSE; |
252b5132 RH |
8121 | } |
8122 | ||
8123 | if (! ok) | |
8124 | { | |
8125 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8126 | && strcmp (insn->name, insn[1].name) == 0) | |
8127 | { | |
8128 | ++insn; | |
8129 | continue; | |
8130 | } | |
252b5132 | 8131 | else |
beae10d5 | 8132 | { |
268f6bed L |
8133 | if (!insn_error) |
8134 | { | |
8135 | static char buf[100]; | |
fef14a42 TS |
8136 | sprintf (buf, |
8137 | _("opcode not supported on this processor: %s (%s)"), | |
8138 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8139 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8140 | insn_error = buf; |
8141 | } | |
8142 | if (save_c) | |
8143 | *(--s) = save_c; | |
2bd7f1f3 | 8144 | return; |
252b5132 | 8145 | } |
252b5132 RH |
8146 | } |
8147 | ||
8148 | ip->insn_mo = insn; | |
8149 | ip->insn_opcode = insn->match; | |
268f6bed | 8150 | insn_error = NULL; |
252b5132 RH |
8151 | for (args = insn->args;; ++args) |
8152 | { | |
deec1734 CD |
8153 | int is_mdmx; |
8154 | ||
ad8d3bb3 | 8155 | s += strspn (s, " \t"); |
deec1734 | 8156 | is_mdmx = 0; |
252b5132 RH |
8157 | switch (*args) |
8158 | { | |
8159 | case '\0': /* end of args */ | |
8160 | if (*s == '\0') | |
8161 | return; | |
8162 | break; | |
8163 | ||
8164 | case ',': | |
8165 | if (*s++ == *args) | |
8166 | continue; | |
8167 | s--; | |
8168 | switch (*++args) | |
8169 | { | |
8170 | case 'r': | |
8171 | case 'v': | |
38487616 | 8172 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8173 | continue; |
8174 | ||
8175 | case 'w': | |
38487616 TS |
8176 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8177 | continue; | |
8178 | ||
252b5132 | 8179 | case 'W': |
38487616 | 8180 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8181 | continue; |
8182 | ||
8183 | case 'V': | |
38487616 | 8184 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8185 | continue; |
8186 | } | |
8187 | break; | |
8188 | ||
8189 | case '(': | |
8190 | /* Handle optional base register. | |
8191 | Either the base register is omitted or | |
bdaaa2e1 | 8192 | we must have a left paren. */ |
252b5132 RH |
8193 | /* This is dependent on the next operand specifier |
8194 | is a base register specification. */ | |
8195 | assert (args[1] == 'b' || args[1] == '5' | |
8196 | || args[1] == '-' || args[1] == '4'); | |
8197 | if (*s == '\0') | |
8198 | return; | |
8199 | ||
8200 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8201 | case '[': |
8202 | case ']': | |
252b5132 RH |
8203 | if (*s++ == *args) |
8204 | continue; | |
8205 | break; | |
8206 | ||
af7ee8bf CD |
8207 | case '+': /* Opcode extension character. */ |
8208 | switch (*++args) | |
8209 | { | |
071742cf CD |
8210 | case 'A': /* ins/ext position, becomes LSB. */ |
8211 | limlo = 0; | |
8212 | limhi = 31; | |
5f74bc13 CD |
8213 | goto do_lsb; |
8214 | case 'E': | |
8215 | limlo = 32; | |
8216 | limhi = 63; | |
8217 | goto do_lsb; | |
8218 | do_lsb: | |
071742cf CD |
8219 | my_getExpression (&imm_expr, s); |
8220 | check_absolute_expr (ip, &imm_expr); | |
8221 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8222 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8223 | { | |
8224 | as_bad (_("Improper position (%lu)"), | |
8225 | (unsigned long) imm_expr.X_add_number); | |
8226 | imm_expr.X_add_number = limlo; | |
8227 | } | |
8228 | lastpos = imm_expr.X_add_number; | |
8229 | ip->insn_opcode |= (imm_expr.X_add_number | |
8230 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8231 | imm_expr.X_op = O_absent; | |
8232 | s = expr_end; | |
8233 | continue; | |
8234 | ||
8235 | case 'B': /* ins size, becomes MSB. */ | |
8236 | limlo = 1; | |
8237 | limhi = 32; | |
5f74bc13 CD |
8238 | goto do_msb; |
8239 | case 'F': | |
8240 | limlo = 33; | |
8241 | limhi = 64; | |
8242 | goto do_msb; | |
8243 | do_msb: | |
071742cf CD |
8244 | my_getExpression (&imm_expr, s); |
8245 | check_absolute_expr (ip, &imm_expr); | |
8246 | /* Check for negative input so that small negative numbers | |
8247 | will not succeed incorrectly. The checks against | |
8248 | (pos+size) transitively check "size" itself, | |
8249 | assuming that "pos" is reasonable. */ | |
8250 | if ((long) imm_expr.X_add_number < 0 | |
8251 | || ((unsigned long) imm_expr.X_add_number | |
8252 | + lastpos) < limlo | |
8253 | || ((unsigned long) imm_expr.X_add_number | |
8254 | + lastpos) > limhi) | |
8255 | { | |
8256 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8257 | (unsigned long) imm_expr.X_add_number, | |
8258 | (unsigned long) lastpos); | |
8259 | imm_expr.X_add_number = limlo - lastpos; | |
8260 | } | |
8261 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8262 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8263 | imm_expr.X_op = O_absent; | |
8264 | s = expr_end; | |
8265 | continue; | |
8266 | ||
8267 | case 'C': /* ext size, becomes MSBD. */ | |
8268 | limlo = 1; | |
8269 | limhi = 32; | |
5f74bc13 CD |
8270 | goto do_msbd; |
8271 | case 'G': | |
8272 | limlo = 33; | |
8273 | limhi = 64; | |
8274 | goto do_msbd; | |
8275 | case 'H': | |
8276 | limlo = 33; | |
8277 | limhi = 64; | |
8278 | goto do_msbd; | |
8279 | do_msbd: | |
071742cf CD |
8280 | my_getExpression (&imm_expr, s); |
8281 | check_absolute_expr (ip, &imm_expr); | |
8282 | /* Check for negative input so that small negative numbers | |
8283 | will not succeed incorrectly. The checks against | |
8284 | (pos+size) transitively check "size" itself, | |
8285 | assuming that "pos" is reasonable. */ | |
8286 | if ((long) imm_expr.X_add_number < 0 | |
8287 | || ((unsigned long) imm_expr.X_add_number | |
8288 | + lastpos) < limlo | |
8289 | || ((unsigned long) imm_expr.X_add_number | |
8290 | + lastpos) > limhi) | |
8291 | { | |
8292 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8293 | (unsigned long) imm_expr.X_add_number, | |
8294 | (unsigned long) lastpos); | |
8295 | imm_expr.X_add_number = limlo - lastpos; | |
8296 | } | |
8297 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8298 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8299 | imm_expr.X_op = O_absent; | |
8300 | s = expr_end; | |
8301 | continue; | |
af7ee8bf | 8302 | |
bbcc0807 CD |
8303 | case 'D': |
8304 | /* +D is for disassembly only; never match. */ | |
8305 | break; | |
8306 | ||
5f74bc13 CD |
8307 | case 'I': |
8308 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8309 | my_getExpression (&imm2_expr, s); | |
8310 | if (imm2_expr.X_op != O_big | |
8311 | && imm2_expr.X_op != O_constant) | |
8312 | insn_error = _("absolute expression required"); | |
13757d0c | 8313 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8314 | s = expr_end; |
8315 | continue; | |
8316 | ||
af7ee8bf CD |
8317 | default: |
8318 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8319 | *args, insn->name, insn->args); | |
8320 | /* Further processing is fruitless. */ | |
8321 | return; | |
8322 | } | |
8323 | break; | |
8324 | ||
252b5132 RH |
8325 | case '<': /* must be at least one digit */ |
8326 | /* | |
8327 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8328 | * than 31 or less than 0, then the shift amount should be |
8329 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8330 | * We issue a warning and mask out all but the low 5 bits. |
8331 | */ | |
8332 | my_getExpression (&imm_expr, s); | |
8333 | check_absolute_expr (ip, &imm_expr); | |
8334 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8335 | { | |
793b27f4 TS |
8336 | as_warn (_("Improper shift amount (%lu)"), |
8337 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8338 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8339 | } |
38487616 | 8340 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8341 | imm_expr.X_op = O_absent; |
8342 | s = expr_end; | |
8343 | continue; | |
8344 | ||
8345 | case '>': /* shift amount minus 32 */ | |
8346 | my_getExpression (&imm_expr, s); | |
8347 | check_absolute_expr (ip, &imm_expr); | |
8348 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8349 | || (unsigned long) imm_expr.X_add_number > 63) | |
8350 | break; | |
38487616 | 8351 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8352 | imm_expr.X_op = O_absent; |
8353 | s = expr_end; | |
8354 | continue; | |
8355 | ||
252b5132 RH |
8356 | case 'k': /* cache code */ |
8357 | case 'h': /* prefx code */ | |
8358 | my_getExpression (&imm_expr, s); | |
8359 | check_absolute_expr (ip, &imm_expr); | |
8360 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8361 | { | |
8362 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8363 | ip->insn_mo->name, | |
8364 | (unsigned long) imm_expr.X_add_number); | |
8365 | imm_expr.X_add_number &= 0x1f; | |
8366 | } | |
8367 | if (*args == 'k') | |
8368 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8369 | else | |
8370 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8371 | imm_expr.X_op = O_absent; | |
8372 | s = expr_end; | |
8373 | continue; | |
8374 | ||
8375 | case 'c': /* break code */ | |
8376 | my_getExpression (&imm_expr, s); | |
8377 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8378 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8379 | { |
793b27f4 TS |
8380 | as_warn (_("Illegal break code (%lu)"), |
8381 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8382 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8383 | } |
38487616 | 8384 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8385 | imm_expr.X_op = O_absent; |
8386 | s = expr_end; | |
8387 | continue; | |
8388 | ||
8389 | case 'q': /* lower break code */ | |
8390 | my_getExpression (&imm_expr, s); | |
8391 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8392 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8393 | { |
793b27f4 TS |
8394 | as_warn (_("Illegal lower break code (%lu)"), |
8395 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8396 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8397 | } |
38487616 | 8398 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8399 | imm_expr.X_op = O_absent; |
8400 | s = expr_end; | |
8401 | continue; | |
8402 | ||
4372b673 | 8403 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8404 | my_getExpression (&imm_expr, s); |
156c2f8b | 8405 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8406 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8407 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8408 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8409 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8410 | imm_expr.X_op = O_absent; |
8411 | s = expr_end; | |
8412 | continue; | |
8413 | ||
98d3f06f | 8414 | case 'C': /* Coprocessor code */ |
beae10d5 | 8415 | my_getExpression (&imm_expr, s); |
252b5132 | 8416 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8417 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8418 | { |
793b27f4 TS |
8419 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8420 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8421 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8422 | } |
beae10d5 KH |
8423 | ip->insn_opcode |= imm_expr.X_add_number; |
8424 | imm_expr.X_op = O_absent; | |
8425 | s = expr_end; | |
8426 | continue; | |
252b5132 | 8427 | |
4372b673 NC |
8428 | case 'J': /* 19-bit wait code. */ |
8429 | my_getExpression (&imm_expr, s); | |
8430 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8431 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8432 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8433 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8434 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8435 | imm_expr.X_op = O_absent; |
8436 | s = expr_end; | |
8437 | continue; | |
8438 | ||
252b5132 | 8439 | case 'P': /* Performance register */ |
beae10d5 | 8440 | my_getExpression (&imm_expr, s); |
252b5132 | 8441 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8442 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8443 | { |
793b27f4 TS |
8444 | as_warn (_("Invalid performance register (%lu)"), |
8445 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8446 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8447 | } |
38487616 | 8448 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8449 | imm_expr.X_op = O_absent; |
8450 | s = expr_end; | |
8451 | continue; | |
252b5132 RH |
8452 | |
8453 | case 'b': /* base register */ | |
8454 | case 'd': /* destination register */ | |
8455 | case 's': /* source register */ | |
8456 | case 't': /* target register */ | |
8457 | case 'r': /* both target and source */ | |
8458 | case 'v': /* both dest and source */ | |
8459 | case 'w': /* both dest and target */ | |
8460 | case 'E': /* coprocessor target register */ | |
8461 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8462 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8463 | case 'x': /* ignore register name */ |
8464 | case 'z': /* must be zero register */ | |
4372b673 | 8465 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8466 | s_reset = s; |
8467 | if (s[0] == '$') | |
8468 | { | |
8469 | ||
3882b010 | 8470 | if (ISDIGIT (s[1])) |
252b5132 RH |
8471 | { |
8472 | ++s; | |
8473 | regno = 0; | |
8474 | do | |
8475 | { | |
8476 | regno *= 10; | |
8477 | regno += *s - '0'; | |
8478 | ++s; | |
8479 | } | |
3882b010 | 8480 | while (ISDIGIT (*s)); |
252b5132 RH |
8481 | if (regno > 31) |
8482 | as_bad (_("Invalid register number (%d)"), regno); | |
8483 | } | |
af7ee8bf | 8484 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8485 | goto notreg; |
8486 | else | |
8487 | { | |
76db943d TS |
8488 | if (s[1] == 'r' && s[2] == 'a') |
8489 | { | |
8490 | s += 3; | |
8491 | regno = RA; | |
8492 | } | |
8493 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8494 | { |
8495 | s += 3; | |
8496 | regno = FP; | |
8497 | } | |
8498 | else if (s[1] == 's' && s[2] == 'p') | |
8499 | { | |
8500 | s += 3; | |
8501 | regno = SP; | |
8502 | } | |
8503 | else if (s[1] == 'g' && s[2] == 'p') | |
8504 | { | |
8505 | s += 3; | |
8506 | regno = GP; | |
8507 | } | |
8508 | else if (s[1] == 'a' && s[2] == 't') | |
8509 | { | |
8510 | s += 3; | |
8511 | regno = AT; | |
8512 | } | |
8513 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8514 | { | |
8515 | s += 4; | |
8516 | regno = KT0; | |
8517 | } | |
8518 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8519 | { | |
8520 | s += 4; | |
8521 | regno = KT1; | |
8522 | } | |
85b51719 TS |
8523 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8524 | { | |
8525 | s += 5; | |
8526 | regno = ZERO; | |
8527 | } | |
252b5132 RH |
8528 | else if (itbl_have_entries) |
8529 | { | |
8530 | char *p, *n; | |
d7ba4a77 | 8531 | unsigned long r; |
252b5132 | 8532 | |
d7ba4a77 | 8533 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8534 | n = itbl_get_field (&p); /* n is name */ |
8535 | ||
d7ba4a77 ILT |
8536 | /* See if this is a register defined in an |
8537 | itbl entry. */ | |
8538 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8539 | { |
8540 | /* Get_field advances to the start of | |
8541 | the next field, so we need to back | |
d7ba4a77 | 8542 | rack to the end of the last field. */ |
bdaaa2e1 | 8543 | if (p) |
252b5132 | 8544 | s = p - 1; |
bdaaa2e1 | 8545 | else |
d7ba4a77 | 8546 | s = strchr (s, '\0'); |
252b5132 RH |
8547 | regno = r; |
8548 | } | |
8549 | else | |
8550 | goto notreg; | |
beae10d5 | 8551 | } |
252b5132 RH |
8552 | else |
8553 | goto notreg; | |
8554 | } | |
8555 | if (regno == AT | |
8556 | && ! mips_opts.noat | |
8557 | && *args != 'E' | |
af7ee8bf CD |
8558 | && *args != 'G' |
8559 | && *args != 'K') | |
252b5132 RH |
8560 | as_warn (_("Used $at without \".set noat\"")); |
8561 | c = *args; | |
8562 | if (*s == ' ') | |
f9419b05 | 8563 | ++s; |
252b5132 RH |
8564 | if (args[1] != *s) |
8565 | { | |
8566 | if (c == 'r' || c == 'v' || c == 'w') | |
8567 | { | |
8568 | regno = lastregno; | |
8569 | s = s_reset; | |
f9419b05 | 8570 | ++args; |
252b5132 RH |
8571 | } |
8572 | } | |
8573 | /* 'z' only matches $0. */ | |
8574 | if (c == 'z' && regno != 0) | |
8575 | break; | |
8576 | ||
bdaaa2e1 KH |
8577 | /* Now that we have assembled one operand, we use the args string |
8578 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8579 | switch (c) |
8580 | { | |
8581 | case 'r': | |
8582 | case 's': | |
8583 | case 'v': | |
8584 | case 'b': | |
38487616 | 8585 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8586 | break; |
8587 | case 'd': | |
8588 | case 'G': | |
af7ee8bf | 8589 | case 'K': |
38487616 | 8590 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8591 | break; |
4372b673 | 8592 | case 'U': |
38487616 TS |
8593 | ip->insn_opcode |= regno << OP_SH_RD; |
8594 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8595 | break; |
252b5132 RH |
8596 | case 'w': |
8597 | case 't': | |
8598 | case 'E': | |
38487616 | 8599 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8600 | break; |
8601 | case 'x': | |
8602 | /* This case exists because on the r3000 trunc | |
8603 | expands into a macro which requires a gp | |
8604 | register. On the r6000 or r4000 it is | |
8605 | assembled into a single instruction which | |
8606 | ignores the register. Thus the insn version | |
8607 | is MIPS_ISA2 and uses 'x', and the macro | |
8608 | version is MIPS_ISA1 and uses 't'. */ | |
8609 | break; | |
8610 | case 'z': | |
8611 | /* This case is for the div instruction, which | |
8612 | acts differently if the destination argument | |
8613 | is $0. This only matches $0, and is checked | |
8614 | outside the switch. */ | |
8615 | break; | |
8616 | case 'D': | |
8617 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8618 | break; | |
8619 | /* What about all other operands like 'i', which | |
8620 | can be specified in the opcode table? */ | |
8621 | } | |
8622 | lastregno = regno; | |
8623 | continue; | |
8624 | } | |
8625 | notreg: | |
8626 | switch (*args++) | |
8627 | { | |
8628 | case 'r': | |
8629 | case 'v': | |
38487616 | 8630 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8631 | continue; |
8632 | case 'w': | |
38487616 | 8633 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8634 | continue; |
8635 | } | |
8636 | break; | |
8637 | ||
deec1734 CD |
8638 | case 'O': /* MDMX alignment immediate constant. */ |
8639 | my_getExpression (&imm_expr, s); | |
8640 | check_absolute_expr (ip, &imm_expr); | |
8641 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8642 | { | |
8643 | as_warn ("Improper align amount (%ld), using low bits", | |
8644 | (long) imm_expr.X_add_number); | |
8645 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8646 | } | |
8647 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8648 | imm_expr.X_op = O_absent; | |
8649 | s = expr_end; | |
8650 | continue; | |
8651 | ||
8652 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8653 | if (s[0] != '$') | |
8654 | { | |
8655 | /* MDMX Immediate. */ | |
8656 | my_getExpression (&imm_expr, s); | |
8657 | check_absolute_expr (ip, &imm_expr); | |
8658 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8659 | { | |
8660 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8661 | (long) imm_expr.X_add_number); | |
8662 | imm_expr.X_add_number &= OP_MASK_FT; | |
8663 | } | |
8664 | imm_expr.X_add_number &= OP_MASK_FT; | |
8665 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8666 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8667 | else | |
8668 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8669 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8670 | imm_expr.X_op = O_absent; | |
8671 | s = expr_end; | |
8672 | continue; | |
8673 | } | |
8674 | /* Not MDMX Immediate. Fall through. */ | |
8675 | case 'X': /* MDMX destination register. */ | |
8676 | case 'Y': /* MDMX source register. */ | |
8677 | case 'Z': /* MDMX target register. */ | |
8678 | is_mdmx = 1; | |
252b5132 RH |
8679 | case 'D': /* floating point destination register */ |
8680 | case 'S': /* floating point source register */ | |
8681 | case 'T': /* floating point target register */ | |
8682 | case 'R': /* floating point source register */ | |
8683 | case 'V': | |
8684 | case 'W': | |
8685 | s_reset = s; | |
deec1734 CD |
8686 | /* Accept $fN for FP and MDMX register numbers, and in |
8687 | addition accept $vN for MDMX register numbers. */ | |
8688 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8689 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8690 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8691 | { |
8692 | s += 2; | |
8693 | regno = 0; | |
8694 | do | |
8695 | { | |
8696 | regno *= 10; | |
8697 | regno += *s - '0'; | |
8698 | ++s; | |
8699 | } | |
3882b010 | 8700 | while (ISDIGIT (*s)); |
252b5132 RH |
8701 | |
8702 | if (regno > 31) | |
8703 | as_bad (_("Invalid float register number (%d)"), regno); | |
8704 | ||
8705 | if ((regno & 1) != 0 | |
ca4e0257 | 8706 | && HAVE_32BIT_FPRS |
252b5132 RH |
8707 | && ! (strcmp (str, "mtc1") == 0 |
8708 | || strcmp (str, "mfc1") == 0 | |
8709 | || strcmp (str, "lwc1") == 0 | |
8710 | || strcmp (str, "swc1") == 0 | |
8711 | || strcmp (str, "l.s") == 0 | |
8712 | || strcmp (str, "s.s") == 0)) | |
8713 | as_warn (_("Float register should be even, was %d"), | |
8714 | regno); | |
8715 | ||
8716 | c = *args; | |
8717 | if (*s == ' ') | |
f9419b05 | 8718 | ++s; |
252b5132 RH |
8719 | if (args[1] != *s) |
8720 | { | |
8721 | if (c == 'V' || c == 'W') | |
8722 | { | |
8723 | regno = lastregno; | |
8724 | s = s_reset; | |
f9419b05 | 8725 | ++args; |
252b5132 RH |
8726 | } |
8727 | } | |
8728 | switch (c) | |
8729 | { | |
8730 | case 'D': | |
deec1734 | 8731 | case 'X': |
38487616 | 8732 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8733 | break; |
8734 | case 'V': | |
8735 | case 'S': | |
deec1734 | 8736 | case 'Y': |
38487616 | 8737 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8738 | break; |
deec1734 CD |
8739 | case 'Q': |
8740 | /* This is like 'Z', but also needs to fix the MDMX | |
8741 | vector/scalar select bits. Note that the | |
8742 | scalar immediate case is handled above. */ | |
8743 | if (*s == '[') | |
8744 | { | |
8745 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8746 | int max_el = (is_qh ? 3 : 7); | |
8747 | s++; | |
8748 | my_getExpression(&imm_expr, s); | |
8749 | check_absolute_expr (ip, &imm_expr); | |
8750 | s = expr_end; | |
8751 | if (imm_expr.X_add_number > max_el) | |
8752 | as_bad(_("Bad element selector %ld"), | |
8753 | (long) imm_expr.X_add_number); | |
8754 | imm_expr.X_add_number &= max_el; | |
8755 | ip->insn_opcode |= (imm_expr.X_add_number | |
8756 | << (OP_SH_VSEL + | |
8757 | (is_qh ? 2 : 1))); | |
8758 | if (*s != ']') | |
8759 | as_warn(_("Expecting ']' found '%s'"), s); | |
8760 | else | |
8761 | s++; | |
8762 | } | |
8763 | else | |
8764 | { | |
8765 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8766 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8767 | << OP_SH_VSEL); | |
8768 | else | |
8769 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8770 | OP_SH_VSEL); | |
8771 | } | |
8772 | /* Fall through */ | |
252b5132 RH |
8773 | case 'W': |
8774 | case 'T': | |
deec1734 | 8775 | case 'Z': |
38487616 | 8776 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8777 | break; |
8778 | case 'R': | |
38487616 | 8779 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8780 | break; |
8781 | } | |
8782 | lastregno = regno; | |
8783 | continue; | |
8784 | } | |
8785 | ||
252b5132 RH |
8786 | switch (*args++) |
8787 | { | |
8788 | case 'V': | |
38487616 | 8789 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8790 | continue; |
8791 | case 'W': | |
38487616 | 8792 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8793 | continue; |
8794 | } | |
8795 | break; | |
8796 | ||
8797 | case 'I': | |
8798 | my_getExpression (&imm_expr, s); | |
8799 | if (imm_expr.X_op != O_big | |
8800 | && imm_expr.X_op != O_constant) | |
8801 | insn_error = _("absolute expression required"); | |
13757d0c | 8802 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8803 | s = expr_end; |
8804 | continue; | |
8805 | ||
8806 | case 'A': | |
8807 | my_getExpression (&offset_expr, s); | |
f6688943 | 8808 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8809 | s = expr_end; |
8810 | continue; | |
8811 | ||
8812 | case 'F': | |
8813 | case 'L': | |
8814 | case 'f': | |
8815 | case 'l': | |
8816 | { | |
8817 | int f64; | |
ca4e0257 | 8818 | int using_gprs; |
252b5132 RH |
8819 | char *save_in; |
8820 | char *err; | |
8821 | unsigned char temp[8]; | |
8822 | int len; | |
8823 | unsigned int length; | |
8824 | segT seg; | |
8825 | subsegT subseg; | |
8826 | char *p; | |
8827 | ||
8828 | /* These only appear as the last operand in an | |
8829 | instruction, and every instruction that accepts | |
8830 | them in any variant accepts them in all variants. | |
8831 | This means we don't have to worry about backing out | |
8832 | any changes if the instruction does not match. | |
8833 | ||
8834 | The difference between them is the size of the | |
8835 | floating point constant and where it goes. For 'F' | |
8836 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8837 | is 32 bits. Where the constant is placed is based | |
8838 | on how the MIPS assembler does things: | |
8839 | F -- .rdata | |
8840 | L -- .lit8 | |
8841 | f -- immediate value | |
8842 | l -- .lit4 | |
8843 | ||
8844 | The .lit4 and .lit8 sections are only used if | |
8845 | permitted by the -G argument. | |
8846 | ||
8847 | When generating embedded PIC code, we use the | |
8848 | .lit8 section but not the .lit4 section (we can do | |
8849 | .lit4 inline easily; we need to put .lit8 | |
8850 | somewhere in the data segment, and using .lit8 | |
8851 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8852 | .lit8 entries). |
8853 | ||
8854 | The code below needs to know whether the target register | |
8855 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8856 | 'F' are used with GPR-based instructions and 'l' and | |
8857 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8858 | |
8859 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8860 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8861 | |
8862 | save_in = input_line_pointer; | |
8863 | input_line_pointer = s; | |
8864 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8865 | length = len; | |
8866 | s = input_line_pointer; | |
8867 | input_line_pointer = save_in; | |
8868 | if (err != NULL && *err != '\0') | |
8869 | { | |
8870 | as_bad (_("Bad floating point constant: %s"), err); | |
8871 | memset (temp, '\0', sizeof temp); | |
8872 | length = f64 ? 8 : 4; | |
8873 | } | |
8874 | ||
156c2f8b | 8875 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8876 | |
8877 | if (*args == 'f' | |
8878 | || (*args == 'l' | |
8879 | && (! USE_GLOBAL_POINTER_OPT | |
8880 | || mips_pic == EMBEDDED_PIC | |
8881 | || g_switch_value < 4 | |
8882 | || (temp[0] == 0 && temp[1] == 0) | |
8883 | || (temp[2] == 0 && temp[3] == 0)))) | |
8884 | { | |
8885 | imm_expr.X_op = O_constant; | |
8886 | if (! target_big_endian) | |
8887 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8888 | else | |
8889 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8890 | } | |
8891 | else if (length > 4 | |
119d663a | 8892 | && ! mips_disable_float_construction |
ca4e0257 RS |
8893 | /* Constants can only be constructed in GPRs and |
8894 | copied to FPRs if the GPRs are at least as wide | |
8895 | as the FPRs. Force the constant into memory if | |
8896 | we are using 64-bit FPRs but the GPRs are only | |
8897 | 32 bits wide. */ | |
8898 | && (using_gprs | |
8899 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8900 | && ((temp[0] == 0 && temp[1] == 0) |
8901 | || (temp[2] == 0 && temp[3] == 0)) | |
8902 | && ((temp[4] == 0 && temp[5] == 0) | |
8903 | || (temp[6] == 0 && temp[7] == 0))) | |
8904 | { | |
ca4e0257 RS |
8905 | /* The value is simple enough to load with a couple of |
8906 | instructions. If using 32-bit registers, set | |
8907 | imm_expr to the high order 32 bits and offset_expr to | |
8908 | the low order 32 bits. Otherwise, set imm_expr to | |
8909 | the entire 64 bit constant. */ | |
8910 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8911 | { |
8912 | imm_expr.X_op = O_constant; | |
8913 | offset_expr.X_op = O_constant; | |
8914 | if (! target_big_endian) | |
8915 | { | |
8916 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8917 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8918 | } | |
8919 | else | |
8920 | { | |
8921 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8922 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8923 | } | |
8924 | if (offset_expr.X_add_number == 0) | |
8925 | offset_expr.X_op = O_absent; | |
8926 | } | |
8927 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8928 | { | |
8929 | imm_expr.X_op = O_constant; | |
8930 | if (! target_big_endian) | |
8931 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8932 | else | |
8933 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8934 | } | |
8935 | else | |
8936 | { | |
8937 | imm_expr.X_op = O_big; | |
8938 | imm_expr.X_add_number = 4; | |
8939 | if (! target_big_endian) | |
8940 | { | |
8941 | generic_bignum[0] = bfd_getl16 (temp); | |
8942 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8943 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8944 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8945 | } | |
8946 | else | |
8947 | { | |
8948 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8949 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8950 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8951 | generic_bignum[3] = bfd_getb16 (temp); | |
8952 | } | |
8953 | } | |
8954 | } | |
8955 | else | |
8956 | { | |
8957 | const char *newname; | |
8958 | segT new_seg; | |
8959 | ||
8960 | /* Switch to the right section. */ | |
8961 | seg = now_seg; | |
8962 | subseg = now_subseg; | |
8963 | switch (*args) | |
8964 | { | |
8965 | default: /* unused default case avoids warnings. */ | |
8966 | case 'L': | |
8967 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8968 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8969 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8970 | newname = ".lit8"; |
8971 | break; | |
8972 | case 'F': | |
bb2d6cd7 GK |
8973 | if (mips_pic == EMBEDDED_PIC) |
8974 | newname = ".lit8"; | |
8975 | else | |
8976 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8977 | break; |
8978 | case 'l': | |
8979 | assert (!USE_GLOBAL_POINTER_OPT | |
8980 | || g_switch_value >= 4); | |
8981 | newname = ".lit4"; | |
8982 | break; | |
8983 | } | |
8984 | new_seg = subseg_new (newname, (subsegT) 0); | |
8985 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8986 | bfd_set_section_flags (stdoutput, new_seg, | |
8987 | (SEC_ALLOC | |
8988 | | SEC_LOAD | |
8989 | | SEC_READONLY | |
8990 | | SEC_DATA)); | |
8991 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8992 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8993 | && strcmp (TARGET_OS, "elf") != 0) | |
8994 | record_alignment (new_seg, 4); | |
8995 | else | |
8996 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8997 | if (seg == now_seg) | |
8998 | as_bad (_("Can't use floating point insn in this section")); | |
8999 | ||
9000 | /* Set the argument to the current address in the | |
9001 | section. */ | |
9002 | offset_expr.X_op = O_symbol; | |
9003 | offset_expr.X_add_symbol = | |
9004 | symbol_new ("L0\001", now_seg, | |
9005 | (valueT) frag_now_fix (), frag_now); | |
9006 | offset_expr.X_add_number = 0; | |
9007 | ||
9008 | /* Put the floating point number into the section. */ | |
9009 | p = frag_more ((int) length); | |
9010 | memcpy (p, temp, length); | |
9011 | ||
9012 | /* Switch back to the original section. */ | |
9013 | subseg_set (seg, subseg); | |
9014 | } | |
9015 | } | |
9016 | continue; | |
9017 | ||
9018 | case 'i': /* 16 bit unsigned immediate */ | |
9019 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9020 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9021 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9022 | { |
9023 | int more; | |
5e0116d5 RS |
9024 | offsetT minval, maxval; |
9025 | ||
9026 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9027 | && strcmp (insn->name, insn[1].name) == 0); | |
9028 | ||
9029 | /* If the expression was written as an unsigned number, | |
9030 | only treat it as signed if there are no more | |
9031 | alternatives. */ | |
9032 | if (more | |
9033 | && *args == 'j' | |
9034 | && sizeof (imm_expr.X_add_number) <= 4 | |
9035 | && imm_expr.X_op == O_constant | |
9036 | && imm_expr.X_add_number < 0 | |
9037 | && imm_expr.X_unsigned | |
9038 | && HAVE_64BIT_GPRS) | |
9039 | break; | |
9040 | ||
9041 | /* For compatibility with older assemblers, we accept | |
9042 | 0x8000-0xffff as signed 16-bit numbers when only | |
9043 | signed numbers are allowed. */ | |
9044 | if (*args == 'i') | |
9045 | minval = 0, maxval = 0xffff; | |
9046 | else if (more) | |
9047 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9048 | else |
5e0116d5 RS |
9049 | minval = -0x8000, maxval = 0xffff; |
9050 | ||
9051 | if (imm_expr.X_op != O_constant | |
9052 | || imm_expr.X_add_number < minval | |
9053 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9054 | { |
9055 | if (more) | |
9056 | break; | |
2ae7e77b AH |
9057 | if (imm_expr.X_op == O_constant |
9058 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9059 | as_bad (_("expression out of range")); |
252b5132 RH |
9060 | } |
9061 | } | |
9062 | s = expr_end; | |
9063 | continue; | |
9064 | ||
9065 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9066 | /* Check whether there is only a single bracketed expression |
9067 | left. If so, it must be the base register and the | |
9068 | constant must be zero. */ | |
9069 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9070 | { | |
9071 | offset_expr.X_op = O_constant; | |
9072 | offset_expr.X_add_number = 0; | |
9073 | continue; | |
9074 | } | |
252b5132 RH |
9075 | |
9076 | /* If this value won't fit into a 16 bit offset, then go | |
9077 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9078 | code pattern. */ |
5e0116d5 | 9079 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9080 | && (offset_expr.X_op != O_constant |
9081 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9082 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9083 | break; |
9084 | ||
252b5132 RH |
9085 | s = expr_end; |
9086 | continue; | |
9087 | ||
9088 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9089 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9090 | my_getExpression (&offset_expr, s); |
9091 | s = expr_end; | |
9092 | continue; | |
9093 | ||
9094 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9095 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9096 | && imm_expr.X_op == O_constant | |
9097 | && (imm_expr.X_add_number < 0 | |
9098 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9099 | as_bad (_("lui expression not in range 0..65535")); |
9100 | s = expr_end; | |
9101 | continue; | |
9102 | ||
9103 | case 'a': /* 26 bit address */ | |
9104 | my_getExpression (&offset_expr, s); | |
9105 | s = expr_end; | |
f6688943 | 9106 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9107 | continue; |
9108 | ||
9109 | case 'N': /* 3 bit branch condition code */ | |
9110 | case 'M': /* 3 bit compare condition code */ | |
9111 | if (strncmp (s, "$fcc", 4) != 0) | |
9112 | break; | |
9113 | s += 4; | |
9114 | regno = 0; | |
9115 | do | |
9116 | { | |
9117 | regno *= 10; | |
9118 | regno += *s - '0'; | |
9119 | ++s; | |
9120 | } | |
3882b010 | 9121 | while (ISDIGIT (*s)); |
252b5132 | 9122 | if (regno > 7) |
30c378fd CD |
9123 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9124 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9125 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9126 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9127 | && (regno & 1) != 0) | |
9128 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9129 | str, regno); | |
9130 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9131 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9132 | && (regno & 3) != 0) | |
9133 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9134 | str, regno); | |
252b5132 RH |
9135 | if (*args == 'N') |
9136 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9137 | else | |
9138 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9139 | continue; |
252b5132 | 9140 | |
156c2f8b NC |
9141 | case 'H': |
9142 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9143 | s += 2; | |
3882b010 | 9144 | if (ISDIGIT (*s)) |
156c2f8b NC |
9145 | { |
9146 | c = 0; | |
9147 | do | |
9148 | { | |
9149 | c *= 10; | |
9150 | c += *s - '0'; | |
9151 | ++s; | |
9152 | } | |
3882b010 | 9153 | while (ISDIGIT (*s)); |
156c2f8b NC |
9154 | } |
9155 | else | |
9156 | c = 8; /* Invalid sel value. */ | |
9157 | ||
9158 | if (c > 7) | |
9159 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9160 | ip->insn_opcode |= c; | |
9161 | continue; | |
9162 | ||
60b63b72 RS |
9163 | case 'e': |
9164 | /* Must be at least one digit. */ | |
9165 | my_getExpression (&imm_expr, s); | |
9166 | check_absolute_expr (ip, &imm_expr); | |
9167 | ||
9168 | if ((unsigned long) imm_expr.X_add_number | |
9169 | > (unsigned long) OP_MASK_VECBYTE) | |
9170 | { | |
9171 | as_bad (_("bad byte vector index (%ld)"), | |
9172 | (long) imm_expr.X_add_number); | |
9173 | imm_expr.X_add_number = 0; | |
9174 | } | |
9175 | ||
9176 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9177 | imm_expr.X_op = O_absent; | |
9178 | s = expr_end; | |
9179 | continue; | |
9180 | ||
9181 | case '%': | |
9182 | my_getExpression (&imm_expr, s); | |
9183 | check_absolute_expr (ip, &imm_expr); | |
9184 | ||
9185 | if ((unsigned long) imm_expr.X_add_number | |
9186 | > (unsigned long) OP_MASK_VECALIGN) | |
9187 | { | |
9188 | as_bad (_("bad byte vector index (%ld)"), | |
9189 | (long) imm_expr.X_add_number); | |
9190 | imm_expr.X_add_number = 0; | |
9191 | } | |
9192 | ||
9193 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9194 | imm_expr.X_op = O_absent; | |
9195 | s = expr_end; | |
9196 | continue; | |
9197 | ||
252b5132 RH |
9198 | default: |
9199 | as_bad (_("bad char = '%c'\n"), *args); | |
9200 | internalError (); | |
9201 | } | |
9202 | break; | |
9203 | } | |
9204 | /* Args don't match. */ | |
9205 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9206 | !strcmp (insn->name, insn[1].name)) | |
9207 | { | |
9208 | ++insn; | |
9209 | s = argsStart; | |
268f6bed | 9210 | insn_error = _("illegal operands"); |
252b5132 RH |
9211 | continue; |
9212 | } | |
268f6bed L |
9213 | if (save_c) |
9214 | *(--s) = save_c; | |
252b5132 RH |
9215 | insn_error = _("illegal operands"); |
9216 | return; | |
9217 | } | |
9218 | } | |
9219 | ||
9220 | /* This routine assembles an instruction into its binary format when | |
9221 | assembling for the mips16. As a side effect, it sets one of the | |
9222 | global variables imm_reloc or offset_reloc to the type of | |
9223 | relocation to do if one of the operands is an address expression. | |
9224 | It also sets mips16_small and mips16_ext if the user explicitly | |
9225 | requested a small or extended instruction. */ | |
9226 | ||
9227 | static void | |
17a2f251 | 9228 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9229 | { |
9230 | char *s; | |
9231 | const char *args; | |
9232 | struct mips_opcode *insn; | |
9233 | char *argsstart; | |
9234 | unsigned int regno; | |
9235 | unsigned int lastregno = 0; | |
9236 | char *s_reset; | |
9237 | ||
9238 | insn_error = NULL; | |
9239 | ||
b34976b6 AM |
9240 | mips16_small = FALSE; |
9241 | mips16_ext = FALSE; | |
252b5132 | 9242 | |
3882b010 | 9243 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9244 | ; |
9245 | switch (*s) | |
9246 | { | |
9247 | case '\0': | |
9248 | break; | |
9249 | ||
9250 | case ' ': | |
9251 | *s++ = '\0'; | |
9252 | break; | |
9253 | ||
9254 | case '.': | |
9255 | if (s[1] == 't' && s[2] == ' ') | |
9256 | { | |
9257 | *s = '\0'; | |
b34976b6 | 9258 | mips16_small = TRUE; |
252b5132 RH |
9259 | s += 3; |
9260 | break; | |
9261 | } | |
9262 | else if (s[1] == 'e' && s[2] == ' ') | |
9263 | { | |
9264 | *s = '\0'; | |
b34976b6 | 9265 | mips16_ext = TRUE; |
252b5132 RH |
9266 | s += 3; |
9267 | break; | |
9268 | } | |
9269 | /* Fall through. */ | |
9270 | default: | |
9271 | insn_error = _("unknown opcode"); | |
9272 | return; | |
9273 | } | |
9274 | ||
9275 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9276 | mips16_small = TRUE; |
252b5132 RH |
9277 | |
9278 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9279 | { | |
9280 | insn_error = _("unrecognized opcode"); | |
9281 | return; | |
9282 | } | |
9283 | ||
9284 | argsstart = s; | |
9285 | for (;;) | |
9286 | { | |
9287 | assert (strcmp (insn->name, str) == 0); | |
9288 | ||
9289 | ip->insn_mo = insn; | |
9290 | ip->insn_opcode = insn->match; | |
b34976b6 | 9291 | ip->use_extend = FALSE; |
252b5132 | 9292 | imm_expr.X_op = O_absent; |
f6688943 TS |
9293 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9294 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9295 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9296 | imm2_expr.X_op = O_absent; |
252b5132 | 9297 | offset_expr.X_op = O_absent; |
f6688943 TS |
9298 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9299 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9300 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9301 | for (args = insn->args; 1; ++args) |
9302 | { | |
9303 | int c; | |
9304 | ||
9305 | if (*s == ' ') | |
9306 | ++s; | |
9307 | ||
9308 | /* In this switch statement we call break if we did not find | |
9309 | a match, continue if we did find a match, or return if we | |
9310 | are done. */ | |
9311 | ||
9312 | c = *args; | |
9313 | switch (c) | |
9314 | { | |
9315 | case '\0': | |
9316 | if (*s == '\0') | |
9317 | { | |
9318 | /* Stuff the immediate value in now, if we can. */ | |
9319 | if (imm_expr.X_op == O_constant | |
f6688943 | 9320 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9321 | && insn->pinfo != INSN_MACRO) |
9322 | { | |
c4e7957c | 9323 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9324 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9325 | mips16_ext, &ip->insn_opcode, |
9326 | &ip->use_extend, &ip->extend); | |
9327 | imm_expr.X_op = O_absent; | |
f6688943 | 9328 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9329 | } |
9330 | ||
9331 | return; | |
9332 | } | |
9333 | break; | |
9334 | ||
9335 | case ',': | |
9336 | if (*s++ == c) | |
9337 | continue; | |
9338 | s--; | |
9339 | switch (*++args) | |
9340 | { | |
9341 | case 'v': | |
9342 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9343 | continue; | |
9344 | case 'w': | |
9345 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9346 | continue; | |
9347 | } | |
9348 | break; | |
9349 | ||
9350 | case '(': | |
9351 | case ')': | |
9352 | if (*s++ == c) | |
9353 | continue; | |
9354 | break; | |
9355 | ||
9356 | case 'v': | |
9357 | case 'w': | |
9358 | if (s[0] != '$') | |
9359 | { | |
9360 | if (c == 'v') | |
9361 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9362 | else | |
9363 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9364 | ++args; | |
9365 | continue; | |
9366 | } | |
9367 | /* Fall through. */ | |
9368 | case 'x': | |
9369 | case 'y': | |
9370 | case 'z': | |
9371 | case 'Z': | |
9372 | case '0': | |
9373 | case 'S': | |
9374 | case 'R': | |
9375 | case 'X': | |
9376 | case 'Y': | |
9377 | if (s[0] != '$') | |
9378 | break; | |
9379 | s_reset = s; | |
3882b010 | 9380 | if (ISDIGIT (s[1])) |
252b5132 RH |
9381 | { |
9382 | ++s; | |
9383 | regno = 0; | |
9384 | do | |
9385 | { | |
9386 | regno *= 10; | |
9387 | regno += *s - '0'; | |
9388 | ++s; | |
9389 | } | |
3882b010 | 9390 | while (ISDIGIT (*s)); |
252b5132 RH |
9391 | if (regno > 31) |
9392 | { | |
9393 | as_bad (_("invalid register number (%d)"), regno); | |
9394 | regno = 2; | |
9395 | } | |
9396 | } | |
9397 | else | |
9398 | { | |
76db943d TS |
9399 | if (s[1] == 'r' && s[2] == 'a') |
9400 | { | |
9401 | s += 3; | |
9402 | regno = RA; | |
9403 | } | |
9404 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9405 | { |
9406 | s += 3; | |
9407 | regno = FP; | |
9408 | } | |
9409 | else if (s[1] == 's' && s[2] == 'p') | |
9410 | { | |
9411 | s += 3; | |
9412 | regno = SP; | |
9413 | } | |
9414 | else if (s[1] == 'g' && s[2] == 'p') | |
9415 | { | |
9416 | s += 3; | |
9417 | regno = GP; | |
9418 | } | |
9419 | else if (s[1] == 'a' && s[2] == 't') | |
9420 | { | |
9421 | s += 3; | |
9422 | regno = AT; | |
9423 | } | |
9424 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9425 | { | |
9426 | s += 4; | |
9427 | regno = KT0; | |
9428 | } | |
9429 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9430 | { | |
9431 | s += 4; | |
9432 | regno = KT1; | |
9433 | } | |
85b51719 TS |
9434 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9435 | { | |
9436 | s += 5; | |
9437 | regno = ZERO; | |
9438 | } | |
252b5132 RH |
9439 | else |
9440 | break; | |
9441 | } | |
9442 | ||
9443 | if (*s == ' ') | |
9444 | ++s; | |
9445 | if (args[1] != *s) | |
9446 | { | |
9447 | if (c == 'v' || c == 'w') | |
9448 | { | |
9449 | regno = mips16_to_32_reg_map[lastregno]; | |
9450 | s = s_reset; | |
f9419b05 | 9451 | ++args; |
252b5132 RH |
9452 | } |
9453 | } | |
9454 | ||
9455 | switch (c) | |
9456 | { | |
9457 | case 'x': | |
9458 | case 'y': | |
9459 | case 'z': | |
9460 | case 'v': | |
9461 | case 'w': | |
9462 | case 'Z': | |
9463 | regno = mips32_to_16_reg_map[regno]; | |
9464 | break; | |
9465 | ||
9466 | case '0': | |
9467 | if (regno != 0) | |
9468 | regno = ILLEGAL_REG; | |
9469 | break; | |
9470 | ||
9471 | case 'S': | |
9472 | if (regno != SP) | |
9473 | regno = ILLEGAL_REG; | |
9474 | break; | |
9475 | ||
9476 | case 'R': | |
9477 | if (regno != RA) | |
9478 | regno = ILLEGAL_REG; | |
9479 | break; | |
9480 | ||
9481 | case 'X': | |
9482 | case 'Y': | |
9483 | if (regno == AT && ! mips_opts.noat) | |
9484 | as_warn (_("used $at without \".set noat\"")); | |
9485 | break; | |
9486 | ||
9487 | default: | |
9488 | internalError (); | |
9489 | } | |
9490 | ||
9491 | if (regno == ILLEGAL_REG) | |
9492 | break; | |
9493 | ||
9494 | switch (c) | |
9495 | { | |
9496 | case 'x': | |
9497 | case 'v': | |
9498 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9499 | break; | |
9500 | case 'y': | |
9501 | case 'w': | |
9502 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9503 | break; | |
9504 | case 'z': | |
9505 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9506 | break; | |
9507 | case 'Z': | |
9508 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9509 | case '0': | |
9510 | case 'S': | |
9511 | case 'R': | |
9512 | break; | |
9513 | case 'X': | |
9514 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9515 | break; | |
9516 | case 'Y': | |
9517 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9518 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9519 | break; | |
9520 | default: | |
9521 | internalError (); | |
9522 | } | |
9523 | ||
9524 | lastregno = regno; | |
9525 | continue; | |
9526 | ||
9527 | case 'P': | |
9528 | if (strncmp (s, "$pc", 3) == 0) | |
9529 | { | |
9530 | s += 3; | |
9531 | continue; | |
9532 | } | |
9533 | break; | |
9534 | ||
9535 | case '<': | |
9536 | case '>': | |
9537 | case '[': | |
9538 | case ']': | |
9539 | case '4': | |
9540 | case '5': | |
9541 | case 'H': | |
9542 | case 'W': | |
9543 | case 'D': | |
9544 | case 'j': | |
9545 | case '8': | |
9546 | case 'V': | |
9547 | case 'C': | |
9548 | case 'U': | |
9549 | case 'k': | |
9550 | case 'K': | |
9551 | if (s[0] == '%' | |
9552 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9553 | { | |
9554 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9555 | and generate the appropriate reloc. If the text | |
9556 | inside %gprel is not a symbol name with an | |
9557 | optional offset, then we generate a normal reloc | |
9558 | and will probably fail later. */ | |
9559 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9560 | if (imm_expr.X_op == O_symbol) | |
9561 | { | |
b34976b6 | 9562 | mips16_ext = TRUE; |
f6688943 | 9563 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9564 | s = expr_end; |
b34976b6 | 9565 | ip->use_extend = TRUE; |
252b5132 RH |
9566 | ip->extend = 0; |
9567 | continue; | |
9568 | } | |
9569 | } | |
9570 | else | |
9571 | { | |
9572 | /* Just pick up a normal expression. */ | |
9573 | my_getExpression (&imm_expr, s); | |
9574 | } | |
9575 | ||
9576 | if (imm_expr.X_op == O_register) | |
9577 | { | |
9578 | /* What we thought was an expression turned out to | |
9579 | be a register. */ | |
9580 | ||
9581 | if (s[0] == '(' && args[1] == '(') | |
9582 | { | |
9583 | /* It looks like the expression was omitted | |
9584 | before a register indirection, which means | |
9585 | that the expression is implicitly zero. We | |
9586 | still set up imm_expr, so that we handle | |
9587 | explicit extensions correctly. */ | |
9588 | imm_expr.X_op = O_constant; | |
9589 | imm_expr.X_add_number = 0; | |
f6688943 | 9590 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9591 | continue; |
9592 | } | |
9593 | ||
9594 | break; | |
9595 | } | |
9596 | ||
9597 | /* We need to relax this instruction. */ | |
f6688943 | 9598 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9599 | s = expr_end; |
9600 | continue; | |
9601 | ||
9602 | case 'p': | |
9603 | case 'q': | |
9604 | case 'A': | |
9605 | case 'B': | |
9606 | case 'E': | |
9607 | /* We use offset_reloc rather than imm_reloc for the PC | |
9608 | relative operands. This lets macros with both | |
9609 | immediate and address operands work correctly. */ | |
9610 | my_getExpression (&offset_expr, s); | |
9611 | ||
9612 | if (offset_expr.X_op == O_register) | |
9613 | break; | |
9614 | ||
9615 | /* We need to relax this instruction. */ | |
f6688943 | 9616 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9617 | s = expr_end; |
9618 | continue; | |
9619 | ||
9620 | case '6': /* break code */ | |
9621 | my_getExpression (&imm_expr, s); | |
9622 | check_absolute_expr (ip, &imm_expr); | |
9623 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9624 | { | |
9625 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9626 | ip->insn_mo->name, | |
9627 | (unsigned long) imm_expr.X_add_number); | |
9628 | imm_expr.X_add_number &= 0x3f; | |
9629 | } | |
9630 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9631 | imm_expr.X_op = O_absent; | |
9632 | s = expr_end; | |
9633 | continue; | |
9634 | ||
9635 | case 'a': /* 26 bit address */ | |
9636 | my_getExpression (&offset_expr, s); | |
9637 | s = expr_end; | |
f6688943 | 9638 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9639 | ip->insn_opcode <<= 16; |
9640 | continue; | |
9641 | ||
9642 | case 'l': /* register list for entry macro */ | |
9643 | case 'L': /* register list for exit macro */ | |
9644 | { | |
9645 | int mask; | |
9646 | ||
9647 | if (c == 'l') | |
9648 | mask = 0; | |
9649 | else | |
9650 | mask = 7 << 3; | |
9651 | while (*s != '\0') | |
9652 | { | |
9653 | int freg, reg1, reg2; | |
9654 | ||
9655 | while (*s == ' ' || *s == ',') | |
9656 | ++s; | |
9657 | if (*s != '$') | |
9658 | { | |
9659 | as_bad (_("can't parse register list")); | |
9660 | break; | |
9661 | } | |
9662 | ++s; | |
9663 | if (*s != 'f') | |
9664 | freg = 0; | |
9665 | else | |
9666 | { | |
9667 | freg = 1; | |
9668 | ++s; | |
9669 | } | |
9670 | reg1 = 0; | |
3882b010 | 9671 | while (ISDIGIT (*s)) |
252b5132 RH |
9672 | { |
9673 | reg1 *= 10; | |
9674 | reg1 += *s - '0'; | |
9675 | ++s; | |
9676 | } | |
9677 | if (*s == ' ') | |
9678 | ++s; | |
9679 | if (*s != '-') | |
9680 | reg2 = reg1; | |
9681 | else | |
9682 | { | |
9683 | ++s; | |
9684 | if (*s != '$') | |
9685 | break; | |
9686 | ++s; | |
9687 | if (freg) | |
9688 | { | |
9689 | if (*s == 'f') | |
9690 | ++s; | |
9691 | else | |
9692 | { | |
9693 | as_bad (_("invalid register list")); | |
9694 | break; | |
9695 | } | |
9696 | } | |
9697 | reg2 = 0; | |
3882b010 | 9698 | while (ISDIGIT (*s)) |
252b5132 RH |
9699 | { |
9700 | reg2 *= 10; | |
9701 | reg2 += *s - '0'; | |
9702 | ++s; | |
9703 | } | |
9704 | } | |
9705 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9706 | { | |
9707 | mask &= ~ (7 << 3); | |
9708 | mask |= 5 << 3; | |
9709 | } | |
9710 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9711 | { | |
9712 | mask &= ~ (7 << 3); | |
9713 | mask |= 6 << 3; | |
9714 | } | |
9715 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9716 | mask |= (reg2 - 3) << 3; | |
9717 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9718 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9719 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9720 | mask |= 1; |
9721 | else | |
9722 | { | |
9723 | as_bad (_("invalid register list")); | |
9724 | break; | |
9725 | } | |
9726 | } | |
9727 | /* The mask is filled in in the opcode table for the | |
9728 | benefit of the disassembler. We remove it before | |
9729 | applying the actual mask. */ | |
9730 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9731 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9732 | } | |
9733 | continue; | |
9734 | ||
9735 | case 'e': /* extend code */ | |
9736 | my_getExpression (&imm_expr, s); | |
9737 | check_absolute_expr (ip, &imm_expr); | |
9738 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9739 | { | |
9740 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9741 | ip->insn_mo->name, | |
9742 | (unsigned long) imm_expr.X_add_number); | |
9743 | imm_expr.X_add_number &= 0x7ff; | |
9744 | } | |
9745 | ip->insn_opcode |= imm_expr.X_add_number; | |
9746 | imm_expr.X_op = O_absent; | |
9747 | s = expr_end; | |
9748 | continue; | |
9749 | ||
9750 | default: | |
9751 | internalError (); | |
9752 | } | |
9753 | break; | |
9754 | } | |
9755 | ||
9756 | /* Args don't match. */ | |
9757 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9758 | strcmp (insn->name, insn[1].name) == 0) | |
9759 | { | |
9760 | ++insn; | |
9761 | s = argsstart; | |
9762 | continue; | |
9763 | } | |
9764 | ||
9765 | insn_error = _("illegal operands"); | |
9766 | ||
9767 | return; | |
9768 | } | |
9769 | } | |
9770 | ||
9771 | /* This structure holds information we know about a mips16 immediate | |
9772 | argument type. */ | |
9773 | ||
e972090a NC |
9774 | struct mips16_immed_operand |
9775 | { | |
252b5132 RH |
9776 | /* The type code used in the argument string in the opcode table. */ |
9777 | int type; | |
9778 | /* The number of bits in the short form of the opcode. */ | |
9779 | int nbits; | |
9780 | /* The number of bits in the extended form of the opcode. */ | |
9781 | int extbits; | |
9782 | /* The amount by which the short form is shifted when it is used; | |
9783 | for example, the sw instruction has a shift count of 2. */ | |
9784 | int shift; | |
9785 | /* The amount by which the short form is shifted when it is stored | |
9786 | into the instruction code. */ | |
9787 | int op_shift; | |
9788 | /* Non-zero if the short form is unsigned. */ | |
9789 | int unsp; | |
9790 | /* Non-zero if the extended form is unsigned. */ | |
9791 | int extu; | |
9792 | /* Non-zero if the value is PC relative. */ | |
9793 | int pcrel; | |
9794 | }; | |
9795 | ||
9796 | /* The mips16 immediate operand types. */ | |
9797 | ||
9798 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9799 | { | |
9800 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9801 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9802 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9803 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9804 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9805 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9806 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9807 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9808 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9809 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9810 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9811 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9812 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9813 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9814 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9815 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9816 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9817 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9818 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9819 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9820 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9821 | }; | |
9822 | ||
9823 | #define MIPS16_NUM_IMMED \ | |
9824 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9825 | ||
9826 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9827 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9828 | whether an extended value is needed; if one is needed, it sets | |
9829 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9830 | If SMALL is true, an unextended opcode was explicitly requested. | |
9831 | If EXT is true, an extended opcode was explicitly requested. If | |
9832 | WARN is true, warn if EXT does not match reality. */ | |
9833 | ||
9834 | static void | |
17a2f251 TS |
9835 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9836 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9837 | unsigned long *insn, bfd_boolean *use_extend, | |
9838 | unsigned short *extend) | |
252b5132 RH |
9839 | { |
9840 | register const struct mips16_immed_operand *op; | |
9841 | int mintiny, maxtiny; | |
b34976b6 | 9842 | bfd_boolean needext; |
252b5132 RH |
9843 | |
9844 | op = mips16_immed_operands; | |
9845 | while (op->type != type) | |
9846 | { | |
9847 | ++op; | |
9848 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9849 | } | |
9850 | ||
9851 | if (op->unsp) | |
9852 | { | |
9853 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9854 | { | |
9855 | mintiny = 1; | |
9856 | maxtiny = 1 << op->nbits; | |
9857 | } | |
9858 | else | |
9859 | { | |
9860 | mintiny = 0; | |
9861 | maxtiny = (1 << op->nbits) - 1; | |
9862 | } | |
9863 | } | |
9864 | else | |
9865 | { | |
9866 | mintiny = - (1 << (op->nbits - 1)); | |
9867 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9868 | } | |
9869 | ||
9870 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9871 | if (type == 'p' || type == 'q') | |
9872 | val /= 2; | |
9873 | ||
9874 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9875 | || val < (mintiny << op->shift) | |
9876 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9877 | needext = TRUE; |
252b5132 | 9878 | else |
b34976b6 | 9879 | needext = FALSE; |
252b5132 RH |
9880 | |
9881 | if (warn && ext && ! needext) | |
beae10d5 KH |
9882 | as_warn_where (file, line, |
9883 | _("extended operand requested but not required")); | |
252b5132 RH |
9884 | if (small && needext) |
9885 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9886 | ||
9887 | if (small || (! ext && ! needext)) | |
9888 | { | |
9889 | int insnval; | |
9890 | ||
b34976b6 | 9891 | *use_extend = FALSE; |
252b5132 RH |
9892 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9893 | insnval <<= op->op_shift; | |
9894 | *insn |= insnval; | |
9895 | } | |
9896 | else | |
9897 | { | |
9898 | long minext, maxext; | |
9899 | int extval; | |
9900 | ||
9901 | if (op->extu) | |
9902 | { | |
9903 | minext = 0; | |
9904 | maxext = (1 << op->extbits) - 1; | |
9905 | } | |
9906 | else | |
9907 | { | |
9908 | minext = - (1 << (op->extbits - 1)); | |
9909 | maxext = (1 << (op->extbits - 1)) - 1; | |
9910 | } | |
9911 | if (val < minext || val > maxext) | |
9912 | as_bad_where (file, line, | |
9913 | _("operand value out of range for instruction")); | |
9914 | ||
b34976b6 | 9915 | *use_extend = TRUE; |
252b5132 RH |
9916 | if (op->extbits == 16) |
9917 | { | |
9918 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9919 | val &= 0x1f; | |
9920 | } | |
9921 | else if (op->extbits == 15) | |
9922 | { | |
9923 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9924 | val &= 0xf; | |
9925 | } | |
9926 | else | |
9927 | { | |
9928 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9929 | val = 0; | |
9930 | } | |
9931 | ||
9932 | *extend = (unsigned short) extval; | |
9933 | *insn |= val; | |
9934 | } | |
9935 | } | |
9936 | \f | |
5e0116d5 | 9937 | static const struct percent_op_match |
ad8d3bb3 | 9938 | { |
5e0116d5 RS |
9939 | const char *str; |
9940 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
9941 | } percent_op[] = |
9942 | { | |
5e0116d5 | 9943 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9944 | #ifdef OBJ_ELF |
5e0116d5 RS |
9945 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9946 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9947 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9948 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9949 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9950 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9951 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9952 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9953 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9954 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9955 | {"%half", BFD_RELOC_16}, | |
9956 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9957 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9958 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9959 | #endif |
5e0116d5 | 9960 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9961 | }; |
9962 | ||
252b5132 | 9963 | |
5e0116d5 RS |
9964 | /* Return true if *STR points to a relocation operator. When returning true, |
9965 | move *STR over the operator and store its relocation code in *RELOC. | |
9966 | Leave both *STR and *RELOC alone when returning false. */ | |
9967 | ||
9968 | static bfd_boolean | |
17a2f251 | 9969 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9970 | { |
5e0116d5 | 9971 | size_t i; |
76b3015f | 9972 | |
5e0116d5 RS |
9973 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
9974 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 9975 | { |
5e0116d5 RS |
9976 | *str += strlen (percent_op[i].str); |
9977 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9978 | |
5e0116d5 RS |
9979 | /* Check whether the output BFD supports this relocation. |
9980 | If not, issue an error and fall back on something safe. */ | |
9981 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9982 | { |
5e0116d5 RS |
9983 | as_bad ("relocation %s isn't supported by the current ABI", |
9984 | percent_op[i].str); | |
9985 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 9986 | } |
5e0116d5 | 9987 | return TRUE; |
394f9b3a | 9988 | } |
5e0116d5 | 9989 | return FALSE; |
394f9b3a | 9990 | } |
ad8d3bb3 | 9991 | |
ad8d3bb3 | 9992 | |
5e0116d5 RS |
9993 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9994 | expression in *EP and the relocations in the array starting | |
9995 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9996 | |
5e0116d5 RS |
9997 | On exit, EXPR_END points to the first character after the expression. |
9998 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 9999 | |
5e0116d5 | 10000 | static size_t |
17a2f251 TS |
10001 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10002 | char *str) | |
ad8d3bb3 | 10003 | { |
5e0116d5 RS |
10004 | bfd_reloc_code_real_type reversed_reloc[3]; |
10005 | size_t reloc_index, i; | |
09b8f35a RS |
10006 | int crux_depth, str_depth; |
10007 | char *crux; | |
5e0116d5 RS |
10008 | |
10009 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10010 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10011 | of the main expression and with CRUX_DEPTH containing the number | |
10012 | of open brackets at that point. */ | |
10013 | reloc_index = -1; | |
10014 | str_depth = 0; | |
10015 | do | |
fb1b3232 | 10016 | { |
09b8f35a RS |
10017 | reloc_index++; |
10018 | crux = str; | |
10019 | crux_depth = str_depth; | |
10020 | ||
10021 | /* Skip over whitespace and brackets, keeping count of the number | |
10022 | of brackets. */ | |
10023 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10024 | if (*str++ == '(') | |
10025 | str_depth++; | |
5e0116d5 | 10026 | } |
09b8f35a RS |
10027 | while (*str == '%' |
10028 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10029 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10030 | |
09b8f35a | 10031 | my_getExpression (ep, crux); |
5e0116d5 | 10032 | str = expr_end; |
394f9b3a | 10033 | |
5e0116d5 | 10034 | /* Match every open bracket. */ |
09b8f35a | 10035 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10036 | if (*str++ == ')') |
09b8f35a | 10037 | crux_depth--; |
394f9b3a | 10038 | |
09b8f35a | 10039 | if (crux_depth > 0) |
5e0116d5 | 10040 | as_bad ("unclosed '('"); |
394f9b3a | 10041 | |
5e0116d5 | 10042 | expr_end = str; |
252b5132 | 10043 | |
64bdfcaf RS |
10044 | if (reloc_index == 0) |
10045 | reloc[0] = BFD_RELOC_LO16; | |
10046 | else | |
10047 | { | |
10048 | prev_reloc_op_frag = frag_now; | |
10049 | for (i = 0; i < reloc_index; i++) | |
10050 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10051 | } | |
fb1b3232 | 10052 | |
5e0116d5 | 10053 | return reloc_index; |
252b5132 RH |
10054 | } |
10055 | ||
10056 | static void | |
17a2f251 | 10057 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10058 | { |
10059 | char *save_in; | |
98aa84af | 10060 | valueT val; |
252b5132 RH |
10061 | |
10062 | save_in = input_line_pointer; | |
10063 | input_line_pointer = str; | |
10064 | expression (ep); | |
10065 | expr_end = input_line_pointer; | |
10066 | input_line_pointer = save_in; | |
10067 | ||
10068 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10069 | then we bump the value of the symbol by 1 since that is how other | |
10070 | text symbols are handled. We don't bother to handle complex | |
10071 | expressions, just `.' plus or minus a constant. */ | |
10072 | if (mips_opts.mips16 | |
10073 | && ep->X_op == O_symbol | |
10074 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10075 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10076 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10077 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10078 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10079 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10080 | } |
10081 | ||
10082 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10083 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10084 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10085 | returned, or NULL on OK. */ |
10086 | ||
10087 | char * | |
17a2f251 | 10088 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10089 | { |
10090 | int prec; | |
10091 | LITTLENUM_TYPE words[4]; | |
10092 | char *t; | |
10093 | int i; | |
10094 | ||
10095 | switch (type) | |
10096 | { | |
10097 | case 'f': | |
10098 | prec = 2; | |
10099 | break; | |
10100 | ||
10101 | case 'd': | |
10102 | prec = 4; | |
10103 | break; | |
10104 | ||
10105 | default: | |
10106 | *sizeP = 0; | |
10107 | return _("bad call to md_atof"); | |
10108 | } | |
10109 | ||
10110 | t = atof_ieee (input_line_pointer, type, words); | |
10111 | if (t) | |
10112 | input_line_pointer = t; | |
10113 | ||
10114 | *sizeP = prec * 2; | |
10115 | ||
10116 | if (! target_big_endian) | |
10117 | { | |
10118 | for (i = prec - 1; i >= 0; i--) | |
10119 | { | |
17a2f251 | 10120 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10121 | litP += 2; |
10122 | } | |
10123 | } | |
10124 | else | |
10125 | { | |
10126 | for (i = 0; i < prec; i++) | |
10127 | { | |
17a2f251 | 10128 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10129 | litP += 2; |
10130 | } | |
10131 | } | |
bdaaa2e1 | 10132 | |
252b5132 RH |
10133 | return NULL; |
10134 | } | |
10135 | ||
10136 | void | |
17a2f251 | 10137 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10138 | { |
10139 | if (target_big_endian) | |
10140 | number_to_chars_bigendian (buf, val, n); | |
10141 | else | |
10142 | number_to_chars_littleendian (buf, val, n); | |
10143 | } | |
10144 | \f | |
ae948b86 | 10145 | #ifdef OBJ_ELF |
e013f690 TS |
10146 | static int support_64bit_objects(void) |
10147 | { | |
10148 | const char **list, **l; | |
aa3d8fdf | 10149 | int yes; |
e013f690 TS |
10150 | |
10151 | list = bfd_target_list (); | |
10152 | for (l = list; *l != NULL; l++) | |
10153 | #ifdef TE_TMIPS | |
10154 | /* This is traditional mips */ | |
10155 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10156 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10157 | #else | |
10158 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10159 | || strcmp (*l, "elf64-littlemips") == 0) | |
10160 | #endif | |
10161 | break; | |
aa3d8fdf | 10162 | yes = (*l != NULL); |
e013f690 | 10163 | free (list); |
aa3d8fdf | 10164 | return yes; |
e013f690 | 10165 | } |
ae948b86 | 10166 | #endif /* OBJ_ELF */ |
e013f690 | 10167 | |
78849248 | 10168 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10169 | |
e972090a NC |
10170 | struct option md_longopts[] = |
10171 | { | |
f9b4148d CD |
10172 | /* Options which specify architecture. */ |
10173 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10174 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10175 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10176 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10177 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10178 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10179 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10180 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10181 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10182 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10183 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10184 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10185 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10186 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10187 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10188 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10189 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10190 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10191 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10192 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10193 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10194 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10195 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10196 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10197 | |
10198 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10199 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10200 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10201 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10202 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10203 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10204 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10205 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10206 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10207 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10208 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10209 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10210 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10211 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10212 | ||
10213 | /* Old-style architecture options. Don't add more of these. */ | |
10214 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10215 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10216 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10217 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10218 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10219 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10220 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10221 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10222 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10223 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10224 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10225 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10226 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10227 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10228 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10229 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10230 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10231 | ||
10232 | /* Options which enable bug fixes. */ | |
10233 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10234 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10235 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10236 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10237 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10238 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10239 | #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) | |
10240 | #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) | |
10241 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10242 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
10243 | ||
10244 | /* Miscellaneous options. */ | |
10245 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10246 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10247 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10248 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10249 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10250 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10251 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10252 | {"break", no_argument, NULL, OPTION_BREAK}, |
10253 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10254 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10255 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10256 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10257 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10258 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10259 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10260 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10261 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10262 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10263 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10264 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10265 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10266 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10267 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10268 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10269 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10270 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10271 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10272 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10273 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10274 | |
10275 | /* ELF-specific options. */ | |
156c2f8b | 10276 | #ifdef OBJ_ELF |
f9b4148d | 10277 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10278 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10279 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10280 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10281 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10282 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10283 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10284 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10285 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10286 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10287 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10288 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10289 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10290 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10291 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10292 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10293 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10294 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10295 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10296 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10297 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10298 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10299 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10300 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10301 | #endif /* OBJ_ELF */ |
f9b4148d | 10302 | |
252b5132 RH |
10303 | {NULL, no_argument, NULL, 0} |
10304 | }; | |
156c2f8b | 10305 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10306 | |
316f5878 RS |
10307 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10308 | NEW_VALUE. Warn if another value was already specified. Note: | |
10309 | we have to defer parsing the -march and -mtune arguments in order | |
10310 | to handle 'from-abi' correctly, since the ABI might be specified | |
10311 | in a later argument. */ | |
10312 | ||
10313 | static void | |
17a2f251 | 10314 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10315 | { |
10316 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10317 | as_warn (_("A different %s was already specified, is now %s"), | |
10318 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10319 | new_value); | |
10320 | ||
10321 | *string_ptr = new_value; | |
10322 | } | |
10323 | ||
252b5132 | 10324 | int |
17a2f251 | 10325 | md_parse_option (int c, char *arg) |
252b5132 RH |
10326 | { |
10327 | switch (c) | |
10328 | { | |
119d663a NC |
10329 | case OPTION_CONSTRUCT_FLOATS: |
10330 | mips_disable_float_construction = 0; | |
10331 | break; | |
bdaaa2e1 | 10332 | |
119d663a NC |
10333 | case OPTION_NO_CONSTRUCT_FLOATS: |
10334 | mips_disable_float_construction = 1; | |
10335 | break; | |
bdaaa2e1 | 10336 | |
252b5132 RH |
10337 | case OPTION_TRAP: |
10338 | mips_trap = 1; | |
10339 | break; | |
10340 | ||
10341 | case OPTION_BREAK: | |
10342 | mips_trap = 0; | |
10343 | break; | |
10344 | ||
10345 | case OPTION_EB: | |
10346 | target_big_endian = 1; | |
10347 | break; | |
10348 | ||
10349 | case OPTION_EL: | |
10350 | target_big_endian = 0; | |
10351 | break; | |
10352 | ||
10353 | case 'O': | |
10354 | if (arg && arg[1] == '0') | |
10355 | mips_optimize = 1; | |
10356 | else | |
10357 | mips_optimize = 2; | |
10358 | break; | |
10359 | ||
10360 | case 'g': | |
10361 | if (arg == NULL) | |
10362 | mips_debug = 2; | |
10363 | else | |
10364 | mips_debug = atoi (arg); | |
10365 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10366 | optimizations which limit full symbolic debugging. We take | |
10367 | that to be equivalent to -O0. */ | |
10368 | if (mips_debug == 2) | |
10369 | mips_optimize = 1; | |
10370 | break; | |
10371 | ||
10372 | case OPTION_MIPS1: | |
316f5878 | 10373 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10374 | break; |
10375 | ||
10376 | case OPTION_MIPS2: | |
316f5878 | 10377 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10378 | break; |
10379 | ||
10380 | case OPTION_MIPS3: | |
316f5878 | 10381 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10382 | break; |
10383 | ||
10384 | case OPTION_MIPS4: | |
316f5878 | 10385 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10386 | break; |
10387 | ||
84ea6cf2 | 10388 | case OPTION_MIPS5: |
316f5878 | 10389 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10390 | break; |
10391 | ||
e7af610e | 10392 | case OPTION_MIPS32: |
316f5878 | 10393 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10394 | break; |
10395 | ||
af7ee8bf CD |
10396 | case OPTION_MIPS32R2: |
10397 | file_mips_isa = ISA_MIPS32R2; | |
10398 | break; | |
10399 | ||
5f74bc13 CD |
10400 | case OPTION_MIPS64R2: |
10401 | file_mips_isa = ISA_MIPS64R2; | |
10402 | break; | |
10403 | ||
84ea6cf2 | 10404 | case OPTION_MIPS64: |
316f5878 | 10405 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10406 | break; |
10407 | ||
ec68c924 | 10408 | case OPTION_MTUNE: |
316f5878 RS |
10409 | mips_set_option_string (&mips_tune_string, arg); |
10410 | break; | |
ec68c924 | 10411 | |
316f5878 RS |
10412 | case OPTION_MARCH: |
10413 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10414 | break; |
10415 | ||
10416 | case OPTION_M4650: | |
316f5878 RS |
10417 | mips_set_option_string (&mips_arch_string, "4650"); |
10418 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10419 | break; |
10420 | ||
10421 | case OPTION_NO_M4650: | |
10422 | break; | |
10423 | ||
10424 | case OPTION_M4010: | |
316f5878 RS |
10425 | mips_set_option_string (&mips_arch_string, "4010"); |
10426 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10427 | break; |
10428 | ||
10429 | case OPTION_NO_M4010: | |
10430 | break; | |
10431 | ||
10432 | case OPTION_M4100: | |
316f5878 RS |
10433 | mips_set_option_string (&mips_arch_string, "4100"); |
10434 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10435 | break; |
10436 | ||
10437 | case OPTION_NO_M4100: | |
10438 | break; | |
10439 | ||
252b5132 | 10440 | case OPTION_M3900: |
316f5878 RS |
10441 | mips_set_option_string (&mips_arch_string, "3900"); |
10442 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10443 | break; |
bdaaa2e1 | 10444 | |
252b5132 RH |
10445 | case OPTION_NO_M3900: |
10446 | break; | |
10447 | ||
deec1734 CD |
10448 | case OPTION_MDMX: |
10449 | mips_opts.ase_mdmx = 1; | |
10450 | break; | |
10451 | ||
10452 | case OPTION_NO_MDMX: | |
10453 | mips_opts.ase_mdmx = 0; | |
10454 | break; | |
10455 | ||
252b5132 RH |
10456 | case OPTION_MIPS16: |
10457 | mips_opts.mips16 = 1; | |
b34976b6 | 10458 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10459 | break; |
10460 | ||
10461 | case OPTION_NO_MIPS16: | |
10462 | mips_opts.mips16 = 0; | |
b34976b6 | 10463 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10464 | break; |
10465 | ||
1f25f5d3 CD |
10466 | case OPTION_MIPS3D: |
10467 | mips_opts.ase_mips3d = 1; | |
10468 | break; | |
10469 | ||
10470 | case OPTION_NO_MIPS3D: | |
10471 | mips_opts.ase_mips3d = 0; | |
10472 | break; | |
10473 | ||
252b5132 RH |
10474 | case OPTION_MEMBEDDED_PIC: |
10475 | mips_pic = EMBEDDED_PIC; | |
10476 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10477 | { | |
10478 | as_bad (_("-G may not be used with embedded PIC code")); | |
10479 | return 0; | |
10480 | } | |
10481 | g_switch_value = 0x7fffffff; | |
10482 | break; | |
10483 | ||
60b63b72 RS |
10484 | case OPTION_FIX_VR4122: |
10485 | mips_fix_4122_bugs = 1; | |
10486 | break; | |
10487 | ||
10488 | case OPTION_NO_FIX_VR4122: | |
10489 | mips_fix_4122_bugs = 0; | |
10490 | break; | |
10491 | ||
4a6a3df4 AO |
10492 | case OPTION_RELAX_BRANCH: |
10493 | mips_relax_branch = 1; | |
10494 | break; | |
10495 | ||
10496 | case OPTION_NO_RELAX_BRANCH: | |
10497 | mips_relax_branch = 0; | |
10498 | break; | |
10499 | ||
0f074f60 | 10500 | #ifdef OBJ_ELF |
252b5132 RH |
10501 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10502 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10503 | intended to be compatible with Irix 5. */ | |
10504 | case OPTION_CALL_SHARED: | |
10505 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10506 | { | |
10507 | as_bad (_("-call_shared is supported only for ELF format")); | |
10508 | return 0; | |
10509 | } | |
10510 | mips_pic = SVR4_PIC; | |
143d77c5 | 10511 | mips_abicalls = TRUE; |
252b5132 RH |
10512 | if (g_switch_seen && g_switch_value != 0) |
10513 | { | |
10514 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10515 | return 0; | |
10516 | } | |
10517 | g_switch_value = 0; | |
10518 | break; | |
10519 | ||
10520 | case OPTION_NON_SHARED: | |
10521 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10522 | { | |
10523 | as_bad (_("-non_shared is supported only for ELF format")); | |
10524 | return 0; | |
10525 | } | |
10526 | mips_pic = NO_PIC; | |
143d77c5 | 10527 | mips_abicalls = FALSE; |
252b5132 RH |
10528 | break; |
10529 | ||
10530 | /* The -xgot option tells the assembler to use 32 offsets when | |
10531 | accessing the got in SVR4_PIC mode. It is for Irix | |
10532 | compatibility. */ | |
10533 | case OPTION_XGOT: | |
10534 | mips_big_got = 1; | |
10535 | break; | |
0f074f60 | 10536 | #endif /* OBJ_ELF */ |
252b5132 RH |
10537 | |
10538 | case 'G': | |
10539 | if (! USE_GLOBAL_POINTER_OPT) | |
10540 | { | |
10541 | as_bad (_("-G is not supported for this configuration")); | |
10542 | return 0; | |
10543 | } | |
10544 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10545 | { | |
10546 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10547 | return 0; | |
10548 | } | |
10549 | else | |
10550 | g_switch_value = atoi (arg); | |
10551 | g_switch_seen = 1; | |
10552 | break; | |
10553 | ||
0f074f60 | 10554 | #ifdef OBJ_ELF |
34ba82a8 TS |
10555 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10556 | and -mabi=64. */ | |
252b5132 | 10557 | case OPTION_32: |
34ba82a8 TS |
10558 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10559 | { | |
10560 | as_bad (_("-32 is supported for ELF format only")); | |
10561 | return 0; | |
10562 | } | |
316f5878 | 10563 | mips_abi = O32_ABI; |
252b5132 RH |
10564 | break; |
10565 | ||
e013f690 | 10566 | case OPTION_N32: |
34ba82a8 TS |
10567 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10568 | { | |
10569 | as_bad (_("-n32 is supported for ELF format only")); | |
10570 | return 0; | |
10571 | } | |
316f5878 | 10572 | mips_abi = N32_ABI; |
e013f690 | 10573 | break; |
252b5132 | 10574 | |
e013f690 | 10575 | case OPTION_64: |
34ba82a8 TS |
10576 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10577 | { | |
10578 | as_bad (_("-64 is supported for ELF format only")); | |
10579 | return 0; | |
10580 | } | |
316f5878 | 10581 | mips_abi = N64_ABI; |
e013f690 TS |
10582 | if (! support_64bit_objects()) |
10583 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10584 | break; |
ae948b86 | 10585 | #endif /* OBJ_ELF */ |
252b5132 | 10586 | |
c97ef257 | 10587 | case OPTION_GP32: |
a325df1d | 10588 | file_mips_gp32 = 1; |
c97ef257 AH |
10589 | break; |
10590 | ||
10591 | case OPTION_GP64: | |
a325df1d | 10592 | file_mips_gp32 = 0; |
c97ef257 | 10593 | break; |
252b5132 | 10594 | |
ca4e0257 | 10595 | case OPTION_FP32: |
a325df1d | 10596 | file_mips_fp32 = 1; |
316f5878 RS |
10597 | break; |
10598 | ||
10599 | case OPTION_FP64: | |
10600 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10601 | break; |
10602 | ||
ae948b86 | 10603 | #ifdef OBJ_ELF |
252b5132 | 10604 | case OPTION_MABI: |
34ba82a8 TS |
10605 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10606 | { | |
10607 | as_bad (_("-mabi is supported for ELF format only")); | |
10608 | return 0; | |
10609 | } | |
e013f690 | 10610 | if (strcmp (arg, "32") == 0) |
316f5878 | 10611 | mips_abi = O32_ABI; |
e013f690 | 10612 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10613 | mips_abi = O64_ABI; |
e013f690 | 10614 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10615 | mips_abi = N32_ABI; |
e013f690 TS |
10616 | else if (strcmp (arg, "64") == 0) |
10617 | { | |
316f5878 | 10618 | mips_abi = N64_ABI; |
e013f690 TS |
10619 | if (! support_64bit_objects()) |
10620 | as_fatal (_("No compiled in support for 64 bit object file " | |
10621 | "format")); | |
10622 | } | |
10623 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10624 | mips_abi = EABI_ABI; |
e013f690 | 10625 | else |
da0e507f TS |
10626 | { |
10627 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10628 | return 0; | |
10629 | } | |
252b5132 | 10630 | break; |
e013f690 | 10631 | #endif /* OBJ_ELF */ |
252b5132 | 10632 | |
6b76fefe | 10633 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10634 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10635 | break; |
10636 | ||
9ee72ff1 | 10637 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10638 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10639 | break; |
10640 | ||
ecb4347a DJ |
10641 | #ifdef OBJ_ELF |
10642 | case OPTION_MDEBUG: | |
b34976b6 | 10643 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10644 | break; |
10645 | ||
10646 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10647 | mips_flag_mdebug = FALSE; |
ecb4347a | 10648 | break; |
dcd410fe RO |
10649 | |
10650 | case OPTION_PDR: | |
10651 | mips_flag_pdr = TRUE; | |
10652 | break; | |
10653 | ||
10654 | case OPTION_NO_PDR: | |
10655 | mips_flag_pdr = FALSE; | |
10656 | break; | |
ecb4347a DJ |
10657 | #endif /* OBJ_ELF */ |
10658 | ||
252b5132 RH |
10659 | default: |
10660 | return 0; | |
10661 | } | |
10662 | ||
10663 | return 1; | |
10664 | } | |
316f5878 RS |
10665 | \f |
10666 | /* Set up globals to generate code for the ISA or processor | |
10667 | described by INFO. */ | |
252b5132 | 10668 | |
252b5132 | 10669 | static void |
17a2f251 | 10670 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10671 | { |
316f5878 | 10672 | if (info != 0) |
252b5132 | 10673 | { |
fef14a42 TS |
10674 | file_mips_arch = info->cpu; |
10675 | mips_opts.arch = info->cpu; | |
316f5878 | 10676 | mips_opts.isa = info->isa; |
252b5132 | 10677 | } |
252b5132 RH |
10678 | } |
10679 | ||
252b5132 | 10680 | |
316f5878 | 10681 | /* Likewise for tuning. */ |
252b5132 | 10682 | |
316f5878 | 10683 | static void |
17a2f251 | 10684 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10685 | { |
10686 | if (info != 0) | |
fef14a42 | 10687 | mips_tune = info->cpu; |
316f5878 | 10688 | } |
80cc45a5 | 10689 | |
34ba82a8 | 10690 | |
252b5132 | 10691 | void |
17a2f251 | 10692 | mips_after_parse_args (void) |
e9670677 | 10693 | { |
fef14a42 TS |
10694 | const struct mips_cpu_info *arch_info = 0; |
10695 | const struct mips_cpu_info *tune_info = 0; | |
10696 | ||
e9670677 MR |
10697 | /* GP relative stuff not working for PE */ |
10698 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10699 | && g_switch_value != 0) | |
10700 | { | |
10701 | if (g_switch_seen) | |
10702 | as_bad (_("-G not supported in this configuration.")); | |
10703 | g_switch_value = 0; | |
10704 | } | |
10705 | ||
cac012d6 AO |
10706 | if (mips_abi == NO_ABI) |
10707 | mips_abi = MIPS_DEFAULT_ABI; | |
10708 | ||
22923709 RS |
10709 | /* The following code determines the architecture and register size. |
10710 | Similar code was added to GCC 3.3 (see override_options() in | |
10711 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10712 | as much as possible. */ | |
e9670677 | 10713 | |
316f5878 | 10714 | if (mips_arch_string != 0) |
fef14a42 | 10715 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10716 | |
316f5878 | 10717 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10718 | { |
316f5878 | 10719 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10720 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10721 | the -march selection (if any). */ |
fef14a42 | 10722 | if (arch_info != 0) |
e9670677 | 10723 | { |
316f5878 RS |
10724 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10725 | There's no harm in specifying both as long as the ISA levels | |
10726 | are the same. */ | |
fef14a42 | 10727 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10728 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10729 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10730 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10731 | } |
316f5878 | 10732 | else |
fef14a42 | 10733 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10734 | } |
10735 | ||
fef14a42 TS |
10736 | if (arch_info == 0) |
10737 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10738 | |
fef14a42 | 10739 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10740 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10741 | arch_info->name); |
10742 | ||
10743 | mips_set_architecture (arch_info); | |
10744 | ||
10745 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10746 | if (mips_tune_string != 0) | |
10747 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10748 | |
fef14a42 TS |
10749 | if (tune_info == 0) |
10750 | mips_set_tune (arch_info); | |
10751 | else | |
10752 | mips_set_tune (tune_info); | |
e9670677 | 10753 | |
316f5878 | 10754 | if (file_mips_gp32 >= 0) |
e9670677 | 10755 | { |
316f5878 RS |
10756 | /* The user specified the size of the integer registers. Make sure |
10757 | it agrees with the ABI and ISA. */ | |
10758 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10759 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10760 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10761 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10762 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10763 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10764 | } |
10765 | else | |
10766 | { | |
316f5878 RS |
10767 | /* Infer the integer register size from the ABI and processor. |
10768 | Restrict ourselves to 32-bit registers if that's all the | |
10769 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10770 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10771 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10772 | } |
10773 | ||
316f5878 RS |
10774 | /* ??? GAS treats single-float processors as though they had 64-bit |
10775 | float registers (although it complains when double-precision | |
10776 | instructions are used). As things stand, saying they have 32-bit | |
10777 | registers would lead to spurious "register must be even" messages. | |
10778 | So here we assume float registers are always the same size as | |
10779 | integer ones, unless the user says otherwise. */ | |
10780 | if (file_mips_fp32 < 0) | |
10781 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10782 | |
316f5878 | 10783 | /* End of GCC-shared inference code. */ |
e9670677 | 10784 | |
17a2f251 TS |
10785 | /* This flag is set when we have a 64-bit capable CPU but use only |
10786 | 32-bit wide registers. Note that EABI does not use it. */ | |
10787 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10788 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10789 | || mips_abi == O32_ABI)) | |
316f5878 | 10790 | mips_32bitmode = 1; |
e9670677 MR |
10791 | |
10792 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10793 | as_bad (_("trap exception not supported at ISA 1")); | |
10794 | ||
e9670677 MR |
10795 | /* If the selected architecture includes support for ASEs, enable |
10796 | generation of code for them. */ | |
a4672219 | 10797 | if (mips_opts.mips16 == -1) |
fef14a42 | 10798 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10799 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10800 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10801 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10802 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10803 | |
e9670677 | 10804 | file_mips_isa = mips_opts.isa; |
a4672219 | 10805 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10806 | file_ase_mips3d = mips_opts.ase_mips3d; |
10807 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10808 | mips_opts.gp32 = file_mips_gp32; | |
10809 | mips_opts.fp32 = file_mips_fp32; | |
10810 | ||
ecb4347a DJ |
10811 | if (mips_flag_mdebug < 0) |
10812 | { | |
10813 | #ifdef OBJ_MAYBE_ECOFF | |
10814 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10815 | mips_flag_mdebug = 1; | |
10816 | else | |
10817 | #endif /* OBJ_MAYBE_ECOFF */ | |
10818 | mips_flag_mdebug = 0; | |
10819 | } | |
e9670677 MR |
10820 | } |
10821 | \f | |
10822 | void | |
17a2f251 | 10823 | mips_init_after_args (void) |
252b5132 RH |
10824 | { |
10825 | /* initialize opcodes */ | |
10826 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10827 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10828 | } |
10829 | ||
10830 | long | |
17a2f251 | 10831 | md_pcrel_from (fixS *fixP) |
252b5132 | 10832 | { |
a7ebbfdf TS |
10833 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10834 | switch (fixP->fx_r_type) | |
10835 | { | |
10836 | case BFD_RELOC_16_PCREL_S2: | |
10837 | case BFD_RELOC_MIPS_JMP: | |
10838 | /* Return the address of the delay slot. */ | |
10839 | return addr + 4; | |
10840 | default: | |
10841 | return addr; | |
10842 | } | |
252b5132 RH |
10843 | } |
10844 | ||
252b5132 RH |
10845 | /* This is called before the symbol table is processed. In order to |
10846 | work with gcc when using mips-tfile, we must keep all local labels. | |
10847 | However, in other cases, we want to discard them. If we were | |
10848 | called with -g, but we didn't see any debugging information, it may | |
10849 | mean that gcc is smuggling debugging information through to | |
10850 | mips-tfile, in which case we must generate all local labels. */ | |
10851 | ||
10852 | void | |
17a2f251 | 10853 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10854 | { |
10855 | #ifndef NO_ECOFF_DEBUGGING | |
10856 | if (ECOFF_DEBUGGING | |
10857 | && mips_debug != 0 | |
10858 | && ! ecoff_debugging_seen) | |
10859 | flag_keep_locals = 1; | |
10860 | #endif | |
10861 | } | |
10862 | ||
10863 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10864 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10865 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10866 | explicit use of the %hi modifier. */ | |
10867 | ||
10868 | void | |
17a2f251 | 10869 | mips_frob_file (void) |
252b5132 RH |
10870 | { |
10871 | struct mips_hi_fixup *l; | |
10872 | ||
10873 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10874 | { | |
10875 | segment_info_type *seginfo; | |
10876 | int pass; | |
10877 | ||
5919d012 | 10878 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10879 | |
5919d012 RS |
10880 | /* If a GOT16 relocation turns out to be against a global symbol, |
10881 | there isn't supposed to be a matching LO. */ | |
10882 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10883 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10884 | continue; | |
10885 | ||
10886 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10887 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10888 | continue; |
10889 | ||
10890 | /* Look through the fixups for this segment for a matching %lo. | |
10891 | When we find one, move the %hi just in front of it. We do | |
10892 | this in two passes. In the first pass, we try to find a | |
10893 | unique %lo. In the second pass, we permit multiple %hi | |
10894 | relocs for a single %lo (this is a GNU extension). */ | |
10895 | seginfo = seg_info (l->seg); | |
10896 | for (pass = 0; pass < 2; pass++) | |
10897 | { | |
10898 | fixS *f, *prev; | |
10899 | ||
10900 | prev = NULL; | |
10901 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10902 | { | |
10903 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10904 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10905 | && f->fx_addsy == l->fixp->fx_addsy | |
10906 | && f->fx_offset == l->fixp->fx_offset | |
10907 | && (pass == 1 | |
10908 | || prev == NULL | |
5919d012 RS |
10909 | || !reloc_needs_lo_p (prev->fx_r_type) |
10910 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
10911 | { |
10912 | fixS **pf; | |
10913 | ||
10914 | /* Move l->fixp before f. */ | |
10915 | for (pf = &seginfo->fix_root; | |
10916 | *pf != l->fixp; | |
10917 | pf = &(*pf)->fx_next) | |
10918 | assert (*pf != NULL); | |
10919 | ||
10920 | *pf = l->fixp->fx_next; | |
10921 | ||
10922 | l->fixp->fx_next = f; | |
10923 | if (prev == NULL) | |
10924 | seginfo->fix_root = l->fixp; | |
10925 | else | |
10926 | prev->fx_next = l->fixp; | |
10927 | ||
10928 | break; | |
10929 | } | |
10930 | ||
10931 | prev = f; | |
10932 | } | |
10933 | ||
10934 | if (f != NULL) | |
10935 | break; | |
10936 | ||
10937 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10938 | can leave a %hi without a %lo. */ | |
10939 | if (pass == 1) | |
10940 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10941 | _("Unmatched %%hi reloc")); | |
10942 | #endif | |
10943 | } | |
10944 | } | |
10945 | } | |
10946 | ||
10947 | /* When generating embedded PIC code we need to use a special | |
10948 | relocation to represent the difference of two symbols in the .text | |
10949 | section (switch tables use a difference of this sort). See | |
10950 | include/coff/mips.h for details. This macro checks whether this | |
10951 | fixup requires the special reloc. */ | |
10952 | #define SWITCH_TABLE(fixp) \ | |
10953 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10954 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10955 | && (fixp)->fx_addsy != NULL \ |
10956 | && (fixp)->fx_subsy != NULL \ | |
10957 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10958 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10959 | ||
10960 | /* When generating embedded PIC code we must keep all PC relative | |
10961 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10962 | to keep relocations for switch table entries. |
10963 | ||
10964 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10965 | We have to prevent gas from dropping them. */ | |
252b5132 | 10966 | |
252b5132 | 10967 | int |
17a2f251 | 10968 | mips_force_relocation (fixS *fixp) |
252b5132 | 10969 | { |
ae6063d4 | 10970 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10971 | return 1; |
10972 | ||
f6688943 TS |
10973 | if (HAVE_NEWABI |
10974 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10975 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10976 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10977 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10978 | return 1; | |
10979 | ||
252b5132 RH |
10980 | return (mips_pic == EMBEDDED_PIC |
10981 | && (fixp->fx_pcrel | |
10982 | || SWITCH_TABLE (fixp) | |
10983 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10984 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10985 | } | |
10986 | ||
45f8dfe8 AO |
10987 | /* This hook is called before a fix is simplified. We don't really |
10988 | decide whether to skip a fix here. Rather, we turn global symbols | |
10989 | used as branch targets into local symbols, such that they undergo | |
10990 | simplification. We can only do this if the symbol is defined and | |
10991 | it is in the same section as the branch. If this doesn't hold, we | |
10992 | emit a better error message than just saying the relocation is not | |
10993 | valid for the selected object format. | |
10994 | ||
10995 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10996 | segment in which the fix up occurs. The return value should be | |
10997 | non-zero to indicate the fix-up is valid for further | |
10998 | simplifications. */ | |
10999 | ||
11000 | int | |
17a2f251 | 11001 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11002 | { |
11003 | /* There's a lot of discussion on whether it should be possible to | |
11004 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11005 | seems to be that it can, but gas/bfd are very broken in creating | |
11006 | RELA relocations for this, so for now we only accept branches to | |
11007 | symbols in the same section. Anything else is of dubious value, | |
11008 | since there's no guarantee that at link time the symbol would be | |
11009 | in range. Even for branches to local symbols this is arguably | |
11010 | wrong, since it we assume the symbol is not going to be | |
11011 | overridden, which should be possible per ELF library semantics, | |
11012 | but then, there isn't a dynamic relocation that could be used to | |
11013 | this effect, and the target would likely be out of range as well. | |
11014 | ||
11015 | Unfortunately, it seems that there is too much code out there | |
11016 | that relies on branches to symbols that are global to be resolved | |
11017 | as if they were local, like the IRIX tools do, so we do it as | |
11018 | well, but with a warning so that people are reminded to fix their | |
11019 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11020 | targets, this entire block should go away (and probably the | |
11021 | whole function). */ | |
11022 | ||
11023 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11024 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11025 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11026 | && mips_pic != EMBEDDED_PIC) | |
11027 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11028 | && fixP->fx_addsy) | |
11029 | { | |
11030 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11031 | { | |
11032 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11033 | _("Cannot branch to undefined symbol.")); | |
11034 | /* Avoid any further errors about this fixup. */ | |
11035 | fixP->fx_done = 1; | |
11036 | } | |
11037 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11038 | { | |
11039 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11040 | _("Cannot branch to symbol in another section.")); | |
11041 | fixP->fx_done = 1; | |
11042 | } | |
11043 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11044 | { | |
11045 | symbolS *sym = fixP->fx_addsy; | |
11046 | ||
115695a8 CD |
11047 | if (mips_pic == SVR4_PIC) |
11048 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11049 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11050 | |
11051 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11052 | S_GET_SEGMENT (sym), | |
11053 | S_GET_VALUE (sym), | |
11054 | symbol_get_frag (sym)); | |
11055 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11056 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11057 | assert (symbol_resolved_p (sym)); | |
11058 | symbol_mark_resolved (fixP->fx_addsy); | |
11059 | } | |
11060 | } | |
11061 | ||
11062 | return 1; | |
11063 | } | |
11064 | ||
252b5132 RH |
11065 | /* Apply a fixup to the object file. */ |
11066 | ||
94f592af | 11067 | void |
17a2f251 | 11068 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11069 | { |
874e8986 | 11070 | bfd_byte *buf; |
98aa84af | 11071 | long insn; |
ed6fb7bd | 11072 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11073 | reloc_howto_type *howto; |
252b5132 | 11074 | |
a7ebbfdf TS |
11075 | /* We ignore generic BFD relocations we don't know about. */ |
11076 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11077 | if (! howto) | |
11078 | return; | |
65551fa4 | 11079 | |
252b5132 RH |
11080 | assert (fixP->fx_size == 4 |
11081 | || fixP->fx_r_type == BFD_RELOC_16 | |
11082 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11083 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11084 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11085 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11086 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11087 | |
a7ebbfdf | 11088 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11089 | |
ed6fb7bd SC |
11090 | /* We are not done if this is a composite relocation to set up gp. */ |
11091 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11092 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11093 | || (fixP->fx_r_type == BFD_RELOC_64 |
11094 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11095 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11096 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11097 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11098 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11099 | fixP->fx_done = 1; |
ed6fb7bd | 11100 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11101 | |
11102 | switch (fixP->fx_r_type) | |
11103 | { | |
11104 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11105 | case BFD_RELOC_MIPS_SHIFT5: |
11106 | case BFD_RELOC_MIPS_SHIFT6: | |
11107 | case BFD_RELOC_MIPS_GOT_DISP: | |
11108 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11109 | case BFD_RELOC_MIPS_GOT_OFST: | |
11110 | case BFD_RELOC_MIPS_SUB: | |
11111 | case BFD_RELOC_MIPS_INSERT_A: | |
11112 | case BFD_RELOC_MIPS_INSERT_B: | |
11113 | case BFD_RELOC_MIPS_DELETE: | |
11114 | case BFD_RELOC_MIPS_HIGHEST: | |
11115 | case BFD_RELOC_MIPS_HIGHER: | |
11116 | case BFD_RELOC_MIPS_SCN_DISP: | |
11117 | case BFD_RELOC_MIPS_REL16: | |
11118 | case BFD_RELOC_MIPS_RELGOT: | |
11119 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11120 | case BFD_RELOC_HI16: |
11121 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11122 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11123 | case BFD_RELOC_MIPS_LITERAL: |
11124 | case BFD_RELOC_MIPS_CALL16: | |
11125 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11126 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11127 | case BFD_RELOC_MIPS_GOT_HI16: |
11128 | case BFD_RELOC_MIPS_GOT_LO16: | |
11129 | case BFD_RELOC_MIPS_CALL_HI16: | |
11130 | case BFD_RELOC_MIPS_CALL_LO16: | |
11131 | case BFD_RELOC_MIPS16_GPREL: | |
11132 | if (fixP->fx_pcrel) | |
11133 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11134 | _("Invalid PC relative reloc")); | |
11135 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11136 | break; | |
11137 | ||
11138 | case BFD_RELOC_MIPS16_JMP: | |
11139 | /* We currently always generate a reloc against a symbol, which | |
11140 | means that we don't want an addend even if the symbol is | |
11141 | defined. */ | |
a7ebbfdf | 11142 | *valP = 0; |
252b5132 RH |
11143 | break; |
11144 | ||
11145 | case BFD_RELOC_PCREL_HI16_S: | |
11146 | /* The addend for this is tricky if it is internal, so we just | |
11147 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11148 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11149 | break; |
11150 | if (fixP->fx_addsy | |
11151 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11152 | { |
11153 | /* For an external symbol adjust by the address to make it | |
11154 | pcrel_offset. We use the address of the RELLO reloc | |
11155 | which follows this one. */ | |
a7ebbfdf | 11156 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11157 | + fixP->fx_next->fx_where); |
11158 | } | |
a7ebbfdf | 11159 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11160 | if (target_big_endian) |
11161 | buf += 2; | |
17a2f251 | 11162 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11163 | break; |
11164 | ||
11165 | case BFD_RELOC_PCREL_LO16: | |
11166 | /* The addend for this is tricky if it is internal, so we just | |
11167 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11168 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11169 | break; |
11170 | if (fixP->fx_addsy | |
11171 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11172 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11173 | if (target_big_endian) |
11174 | buf += 2; | |
17a2f251 | 11175 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11176 | break; |
11177 | ||
11178 | case BFD_RELOC_64: | |
11179 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11180 | extended value if we are only 32 bits. */ | |
11181 | if (fixP->fx_done | |
11182 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11183 | { | |
11184 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11185 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11186 | else |
11187 | { | |
a7ebbfdf | 11188 | valueT hiv; |
252b5132 | 11189 | |
a7ebbfdf | 11190 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11191 | hiv = 0xffffffff; |
11192 | else | |
11193 | hiv = 0; | |
a7ebbfdf TS |
11194 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11195 | *valP, 4); | |
11196 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11197 | hiv, 4); | |
252b5132 RH |
11198 | } |
11199 | } | |
11200 | break; | |
11201 | ||
056350c6 | 11202 | case BFD_RELOC_RVA: |
252b5132 RH |
11203 | case BFD_RELOC_32: |
11204 | /* If we are deleting this reloc entry, we must fill in the | |
11205 | value now. This can happen if we have a .word which is not | |
11206 | resolved when it appears but is later defined. We also need | |
11207 | to fill in the value if this is an embedded PIC switch table | |
11208 | entry. */ | |
11209 | if (fixP->fx_done | |
11210 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11211 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11212 | break; |
11213 | ||
11214 | case BFD_RELOC_16: | |
11215 | /* If we are deleting this reloc entry, we must fill in the | |
11216 | value now. */ | |
11217 | assert (fixP->fx_size == 2); | |
11218 | if (fixP->fx_done) | |
a7ebbfdf | 11219 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11220 | break; |
11221 | ||
11222 | case BFD_RELOC_LO16: | |
11223 | /* When handling an embedded PIC switch statement, we can wind | |
11224 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11225 | if (fixP->fx_done) | |
11226 | { | |
a7ebbfdf | 11227 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11228 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11229 | _("relocation overflow")); | |
252b5132 RH |
11230 | if (target_big_endian) |
11231 | buf += 2; | |
17a2f251 | 11232 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11233 | } |
11234 | break; | |
11235 | ||
11236 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11237 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11238 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11239 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11240 | |
252b5132 RH |
11241 | /* |
11242 | * We need to save the bits in the instruction since fixup_segment() | |
11243 | * might be deleting the relocation entry (i.e., a branch within | |
11244 | * the current segment). | |
11245 | */ | |
a7ebbfdf | 11246 | if (! fixP->fx_done) |
bb2d6cd7 | 11247 | break; |
252b5132 RH |
11248 | |
11249 | /* update old instruction data */ | |
252b5132 RH |
11250 | if (target_big_endian) |
11251 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11252 | else | |
11253 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11254 | ||
a7ebbfdf TS |
11255 | if (*valP + 0x20000 <= 0x3ffff) |
11256 | { | |
11257 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11258 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11259 | } |
11260 | else if (mips_pic == NO_PIC | |
11261 | && fixP->fx_done | |
11262 | && fixP->fx_frag->fr_address >= text_section->vma | |
11263 | && (fixP->fx_frag->fr_address | |
11264 | < text_section->vma + text_section->_raw_size) | |
11265 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11266 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11267 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11268 | { |
11269 | /* The branch offset is too large. If this is an | |
11270 | unconditional branch, and we are not generating PIC code, | |
11271 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11272 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11273 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11274 | else |
a7ebbfdf TS |
11275 | insn = 0x08000000; /* j */ |
11276 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11277 | fixP->fx_done = 0; | |
11278 | fixP->fx_addsy = section_symbol (text_section); | |
11279 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11280 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11281 | } |
11282 | else | |
11283 | { | |
11284 | /* If we got here, we have branch-relaxation disabled, | |
11285 | and there's nothing we can do to fix this instruction | |
11286 | without turning it into a longer sequence. */ | |
11287 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11288 | _("Branch out of range")); | |
252b5132 | 11289 | } |
252b5132 RH |
11290 | break; |
11291 | ||
11292 | case BFD_RELOC_VTABLE_INHERIT: | |
11293 | fixP->fx_done = 0; | |
11294 | if (fixP->fx_addsy | |
11295 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11296 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11297 | S_SET_WEAK (fixP->fx_addsy); | |
11298 | break; | |
11299 | ||
11300 | case BFD_RELOC_VTABLE_ENTRY: | |
11301 | fixP->fx_done = 0; | |
11302 | break; | |
11303 | ||
11304 | default: | |
11305 | internalError (); | |
11306 | } | |
a7ebbfdf TS |
11307 | |
11308 | /* Remember value for tc_gen_reloc. */ | |
11309 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11310 | } |
11311 | ||
11312 | #if 0 | |
11313 | void | |
17a2f251 | 11314 | printInsn (unsigned long oc) |
252b5132 RH |
11315 | { |
11316 | const struct mips_opcode *p; | |
11317 | int treg, sreg, dreg, shamt; | |
11318 | short imm; | |
11319 | const char *args; | |
11320 | int i; | |
11321 | ||
11322 | for (i = 0; i < NUMOPCODES; ++i) | |
11323 | { | |
11324 | p = &mips_opcodes[i]; | |
11325 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11326 | { | |
11327 | printf ("%08lx %s\t", oc, p->name); | |
11328 | treg = (oc >> 16) & 0x1f; | |
11329 | sreg = (oc >> 21) & 0x1f; | |
11330 | dreg = (oc >> 11) & 0x1f; | |
11331 | shamt = (oc >> 6) & 0x1f; | |
11332 | imm = oc; | |
11333 | for (args = p->args;; ++args) | |
11334 | { | |
11335 | switch (*args) | |
11336 | { | |
11337 | case '\0': | |
11338 | printf ("\n"); | |
11339 | break; | |
11340 | ||
11341 | case ',': | |
11342 | case '(': | |
11343 | case ')': | |
11344 | printf ("%c", *args); | |
11345 | continue; | |
11346 | ||
11347 | case 'r': | |
11348 | assert (treg == sreg); | |
11349 | printf ("$%d,$%d", treg, sreg); | |
11350 | continue; | |
11351 | ||
11352 | case 'd': | |
11353 | case 'G': | |
11354 | printf ("$%d", dreg); | |
11355 | continue; | |
11356 | ||
11357 | case 't': | |
11358 | case 'E': | |
11359 | printf ("$%d", treg); | |
11360 | continue; | |
11361 | ||
11362 | case 'k': | |
11363 | printf ("0x%x", treg); | |
11364 | continue; | |
11365 | ||
11366 | case 'b': | |
11367 | case 's': | |
11368 | printf ("$%d", sreg); | |
11369 | continue; | |
11370 | ||
11371 | case 'a': | |
11372 | printf ("0x%08lx", oc & 0x1ffffff); | |
11373 | continue; | |
11374 | ||
11375 | case 'i': | |
11376 | case 'j': | |
11377 | case 'o': | |
11378 | case 'u': | |
11379 | printf ("%d", imm); | |
11380 | continue; | |
11381 | ||
11382 | case '<': | |
11383 | case '>': | |
11384 | printf ("$%d", shamt); | |
11385 | continue; | |
11386 | ||
11387 | default: | |
11388 | internalError (); | |
11389 | } | |
11390 | break; | |
11391 | } | |
11392 | return; | |
11393 | } | |
11394 | } | |
11395 | printf (_("%08lx UNDEFINED\n"), oc); | |
11396 | } | |
11397 | #endif | |
11398 | ||
11399 | static symbolS * | |
17a2f251 | 11400 | get_symbol (void) |
252b5132 RH |
11401 | { |
11402 | int c; | |
11403 | char *name; | |
11404 | symbolS *p; | |
11405 | ||
11406 | name = input_line_pointer; | |
11407 | c = get_symbol_end (); | |
11408 | p = (symbolS *) symbol_find_or_make (name); | |
11409 | *input_line_pointer = c; | |
11410 | return p; | |
11411 | } | |
11412 | ||
11413 | /* Align the current frag to a given power of two. The MIPS assembler | |
11414 | also automatically adjusts any preceding label. */ | |
11415 | ||
11416 | static void | |
17a2f251 | 11417 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11418 | { |
b34976b6 | 11419 | mips_emit_delays (FALSE); |
252b5132 RH |
11420 | frag_align (to, fill, 0); |
11421 | record_alignment (now_seg, to); | |
11422 | if (label != NULL) | |
11423 | { | |
11424 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11425 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11426 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11427 | } | |
11428 | } | |
11429 | ||
11430 | /* Align to a given power of two. .align 0 turns off the automatic | |
11431 | alignment used by the data creating pseudo-ops. */ | |
11432 | ||
11433 | static void | |
17a2f251 | 11434 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11435 | { |
11436 | register int temp; | |
11437 | register long temp_fill; | |
11438 | long max_alignment = 15; | |
11439 | ||
11440 | /* | |
11441 | ||
67c1ffbe | 11442 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11443 | to the aligned address. |
11444 | o It's not documented but auto alignment is reinstated by | |
11445 | a .align pseudo instruction. | |
11446 | o Note also that after auto alignment is turned off the mips assembler | |
11447 | issues an error on attempt to assemble an improperly aligned data item. | |
11448 | We don't. | |
11449 | ||
11450 | */ | |
11451 | ||
11452 | temp = get_absolute_expression (); | |
11453 | if (temp > max_alignment) | |
11454 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11455 | else if (temp < 0) | |
11456 | { | |
11457 | as_warn (_("Alignment negative: 0 assumed.")); | |
11458 | temp = 0; | |
11459 | } | |
11460 | if (*input_line_pointer == ',') | |
11461 | { | |
f9419b05 | 11462 | ++input_line_pointer; |
252b5132 RH |
11463 | temp_fill = get_absolute_expression (); |
11464 | } | |
11465 | else | |
11466 | temp_fill = 0; | |
11467 | if (temp) | |
11468 | { | |
11469 | auto_align = 1; | |
11470 | mips_align (temp, (int) temp_fill, | |
11471 | insn_labels != NULL ? insn_labels->label : NULL); | |
11472 | } | |
11473 | else | |
11474 | { | |
11475 | auto_align = 0; | |
11476 | } | |
11477 | ||
11478 | demand_empty_rest_of_line (); | |
11479 | } | |
11480 | ||
11481 | void | |
17a2f251 | 11482 | mips_flush_pending_output (void) |
252b5132 | 11483 | { |
b34976b6 | 11484 | mips_emit_delays (FALSE); |
252b5132 RH |
11485 | mips_clear_insn_labels (); |
11486 | } | |
11487 | ||
11488 | static void | |
17a2f251 | 11489 | s_change_sec (int sec) |
252b5132 RH |
11490 | { |
11491 | segT seg; | |
11492 | ||
11493 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11494 | .sdata and .sbss sections. We change the .data and .rdata | |
11495 | pseudo-ops to use .sdata. */ | |
11496 | if (mips_pic == EMBEDDED_PIC | |
11497 | && (sec == 'd' || sec == 'r')) | |
11498 | sec = 's'; | |
11499 | ||
11500 | #ifdef OBJ_ELF | |
11501 | /* The ELF backend needs to know that we are changing sections, so | |
11502 | that .previous works correctly. We could do something like check | |
b6ff326e | 11503 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11504 | as it would not be appropriate to use it in the section changing |
11505 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11506 | This should be cleaner, somehow. */ | |
11507 | obj_elf_section_change_hook (); | |
11508 | #endif | |
11509 | ||
b34976b6 | 11510 | mips_emit_delays (FALSE); |
252b5132 RH |
11511 | switch (sec) |
11512 | { | |
11513 | case 't': | |
11514 | s_text (0); | |
11515 | break; | |
11516 | case 'd': | |
11517 | s_data (0); | |
11518 | break; | |
11519 | case 'b': | |
11520 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11521 | demand_empty_rest_of_line (); | |
11522 | break; | |
11523 | ||
11524 | case 'r': | |
11525 | if (USE_GLOBAL_POINTER_OPT) | |
11526 | { | |
11527 | seg = subseg_new (RDATA_SECTION_NAME, | |
11528 | (subsegT) get_absolute_expression ()); | |
11529 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11530 | { | |
11531 | bfd_set_section_flags (stdoutput, seg, | |
11532 | (SEC_ALLOC | |
11533 | | SEC_LOAD | |
11534 | | SEC_READONLY | |
11535 | | SEC_RELOC | |
11536 | | SEC_DATA)); | |
11537 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11538 | record_alignment (seg, 4); |
252b5132 RH |
11539 | } |
11540 | demand_empty_rest_of_line (); | |
11541 | } | |
11542 | else | |
11543 | { | |
11544 | as_bad (_("No read only data section in this object file format")); | |
11545 | demand_empty_rest_of_line (); | |
11546 | return; | |
11547 | } | |
11548 | break; | |
11549 | ||
11550 | case 's': | |
11551 | if (USE_GLOBAL_POINTER_OPT) | |
11552 | { | |
11553 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11554 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11555 | { | |
11556 | bfd_set_section_flags (stdoutput, seg, | |
11557 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11558 | | SEC_DATA); | |
11559 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11560 | record_alignment (seg, 4); |
252b5132 RH |
11561 | } |
11562 | demand_empty_rest_of_line (); | |
11563 | break; | |
11564 | } | |
11565 | else | |
11566 | { | |
11567 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11568 | demand_empty_rest_of_line (); | |
11569 | return; | |
11570 | } | |
11571 | } | |
11572 | ||
11573 | auto_align = 1; | |
11574 | } | |
b34976b6 | 11575 | |
cca86cc8 | 11576 | void |
17a2f251 | 11577 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11578 | { |
7ed4a06a | 11579 | #ifdef OBJ_ELF |
cca86cc8 SC |
11580 | char *section_name; |
11581 | char c; | |
684022ea | 11582 | char next_c = 0; |
cca86cc8 SC |
11583 | int section_type; |
11584 | int section_flag; | |
11585 | int section_entry_size; | |
11586 | int section_alignment; | |
b34976b6 | 11587 | |
7ed4a06a TS |
11588 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11589 | return; | |
11590 | ||
cca86cc8 SC |
11591 | section_name = input_line_pointer; |
11592 | c = get_symbol_end (); | |
a816d1ed AO |
11593 | if (c) |
11594 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11595 | |
4cf0dd0d TS |
11596 | /* Do we have .section Name<,"flags">? */ |
11597 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11598 | { |
4cf0dd0d TS |
11599 | /* just after name is now '\0'. */ |
11600 | *input_line_pointer = c; | |
cca86cc8 SC |
11601 | input_line_pointer = section_name; |
11602 | obj_elf_section (ignore); | |
11603 | return; | |
11604 | } | |
11605 | input_line_pointer++; | |
11606 | ||
11607 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11608 | if (c == ',') | |
11609 | section_type = get_absolute_expression (); | |
11610 | else | |
11611 | section_type = 0; | |
11612 | if (*input_line_pointer++ == ',') | |
11613 | section_flag = get_absolute_expression (); | |
11614 | else | |
11615 | section_flag = 0; | |
11616 | if (*input_line_pointer++ == ',') | |
11617 | section_entry_size = get_absolute_expression (); | |
11618 | else | |
11619 | section_entry_size = 0; | |
11620 | if (*input_line_pointer++ == ',') | |
11621 | section_alignment = get_absolute_expression (); | |
11622 | else | |
11623 | section_alignment = 0; | |
11624 | ||
a816d1ed AO |
11625 | section_name = xstrdup (section_name); |
11626 | ||
8ab8a5c8 RS |
11627 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11628 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11629 | traditionally had to fall back on the more common @progbits instead. | |
11630 | ||
11631 | There's nothing really harmful in this, since bfd will correct | |
11632 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11633 | means that, for backwards compatibiltiy, the special_section entries | |
11634 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11635 | ||
11636 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11637 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11638 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11639 | generic type-checking code. */ | |
11640 | if (section_type == SHT_MIPS_DWARF) | |
11641 | section_type = SHT_PROGBITS; | |
11642 | ||
cca86cc8 SC |
11643 | obj_elf_change_section (section_name, section_type, section_flag, |
11644 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11645 | |
11646 | if (now_seg->name != section_name) | |
11647 | free (section_name); | |
7ed4a06a | 11648 | #endif /* OBJ_ELF */ |
cca86cc8 | 11649 | } |
252b5132 RH |
11650 | |
11651 | void | |
17a2f251 | 11652 | mips_enable_auto_align (void) |
252b5132 RH |
11653 | { |
11654 | auto_align = 1; | |
11655 | } | |
11656 | ||
11657 | static void | |
17a2f251 | 11658 | s_cons (int log_size) |
252b5132 RH |
11659 | { |
11660 | symbolS *label; | |
11661 | ||
11662 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11663 | mips_emit_delays (FALSE); |
252b5132 RH |
11664 | if (log_size > 0 && auto_align) |
11665 | mips_align (log_size, 0, label); | |
11666 | mips_clear_insn_labels (); | |
11667 | cons (1 << log_size); | |
11668 | } | |
11669 | ||
11670 | static void | |
17a2f251 | 11671 | s_float_cons (int type) |
252b5132 RH |
11672 | { |
11673 | symbolS *label; | |
11674 | ||
11675 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11676 | ||
b34976b6 | 11677 | mips_emit_delays (FALSE); |
252b5132 RH |
11678 | |
11679 | if (auto_align) | |
49309057 ILT |
11680 | { |
11681 | if (type == 'd') | |
11682 | mips_align (3, 0, label); | |
11683 | else | |
11684 | mips_align (2, 0, label); | |
11685 | } | |
252b5132 RH |
11686 | |
11687 | mips_clear_insn_labels (); | |
11688 | ||
11689 | float_cons (type); | |
11690 | } | |
11691 | ||
11692 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11693 | permitted to say | |
11694 | .globl foo .text | |
11695 | where foo is an undefined symbol, to mean that foo should be | |
11696 | considered to be the address of a function. */ | |
11697 | ||
11698 | static void | |
17a2f251 | 11699 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11700 | { |
11701 | char *name; | |
11702 | int c; | |
11703 | symbolS *symbolP; | |
11704 | flagword flag; | |
11705 | ||
11706 | name = input_line_pointer; | |
11707 | c = get_symbol_end (); | |
11708 | symbolP = symbol_find_or_make (name); | |
11709 | *input_line_pointer = c; | |
11710 | SKIP_WHITESPACE (); | |
11711 | ||
11712 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11713 | being a function is apparently labelled as being an object. */ | |
11714 | flag = BSF_OBJECT; | |
11715 | ||
11716 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11717 | { | |
11718 | char *secname; | |
11719 | asection *sec; | |
11720 | ||
11721 | secname = input_line_pointer; | |
11722 | c = get_symbol_end (); | |
11723 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11724 | if (sec == NULL) | |
11725 | as_bad (_("%s: no such section"), secname); | |
11726 | *input_line_pointer = c; | |
11727 | ||
11728 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11729 | flag = BSF_FUNCTION; | |
11730 | } | |
11731 | ||
49309057 | 11732 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11733 | |
11734 | S_SET_EXTERNAL (symbolP); | |
11735 | demand_empty_rest_of_line (); | |
11736 | } | |
11737 | ||
11738 | static void | |
17a2f251 | 11739 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11740 | { |
11741 | char *opt; | |
11742 | char c; | |
11743 | ||
11744 | opt = input_line_pointer; | |
11745 | c = get_symbol_end (); | |
11746 | ||
11747 | if (*opt == 'O') | |
11748 | { | |
11749 | /* FIXME: What does this mean? */ | |
11750 | } | |
11751 | else if (strncmp (opt, "pic", 3) == 0) | |
11752 | { | |
11753 | int i; | |
11754 | ||
11755 | i = atoi (opt + 3); | |
11756 | if (i == 0) | |
11757 | mips_pic = NO_PIC; | |
11758 | else if (i == 2) | |
143d77c5 | 11759 | { |
252b5132 | 11760 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11761 | mips_abicalls = TRUE; |
11762 | } | |
252b5132 RH |
11763 | else |
11764 | as_bad (_(".option pic%d not supported"), i); | |
11765 | ||
11766 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11767 | { | |
11768 | if (g_switch_seen && g_switch_value != 0) | |
11769 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11770 | g_switch_value = 0; | |
11771 | bfd_set_gp_size (stdoutput, 0); | |
11772 | } | |
11773 | } | |
11774 | else | |
11775 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11776 | ||
11777 | *input_line_pointer = c; | |
11778 | demand_empty_rest_of_line (); | |
11779 | } | |
11780 | ||
11781 | /* This structure is used to hold a stack of .set values. */ | |
11782 | ||
e972090a NC |
11783 | struct mips_option_stack |
11784 | { | |
252b5132 RH |
11785 | struct mips_option_stack *next; |
11786 | struct mips_set_options options; | |
11787 | }; | |
11788 | ||
11789 | static struct mips_option_stack *mips_opts_stack; | |
11790 | ||
11791 | /* Handle the .set pseudo-op. */ | |
11792 | ||
11793 | static void | |
17a2f251 | 11794 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11795 | { |
11796 | char *name = input_line_pointer, ch; | |
11797 | ||
11798 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11799 | ++input_line_pointer; |
252b5132 RH |
11800 | ch = *input_line_pointer; |
11801 | *input_line_pointer = '\0'; | |
11802 | ||
11803 | if (strcmp (name, "reorder") == 0) | |
11804 | { | |
11805 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11806 | { | |
11807 | /* If we still have pending nops, we can discard them. The | |
11808 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11809 | needed. */ |
252b5132 RH |
11810 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11811 | * (mips_opts.mips16 ? 2 : 4)); | |
11812 | prev_nop_frag = NULL; | |
11813 | } | |
11814 | mips_opts.noreorder = 0; | |
11815 | } | |
11816 | else if (strcmp (name, "noreorder") == 0) | |
11817 | { | |
b34976b6 | 11818 | mips_emit_delays (TRUE); |
252b5132 RH |
11819 | mips_opts.noreorder = 1; |
11820 | mips_any_noreorder = 1; | |
11821 | } | |
11822 | else if (strcmp (name, "at") == 0) | |
11823 | { | |
11824 | mips_opts.noat = 0; | |
11825 | } | |
11826 | else if (strcmp (name, "noat") == 0) | |
11827 | { | |
11828 | mips_opts.noat = 1; | |
11829 | } | |
11830 | else if (strcmp (name, "macro") == 0) | |
11831 | { | |
11832 | mips_opts.warn_about_macros = 0; | |
11833 | } | |
11834 | else if (strcmp (name, "nomacro") == 0) | |
11835 | { | |
11836 | if (mips_opts.noreorder == 0) | |
11837 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11838 | mips_opts.warn_about_macros = 1; | |
11839 | } | |
11840 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11841 | { | |
11842 | mips_opts.nomove = 0; | |
11843 | } | |
11844 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11845 | { | |
11846 | mips_opts.nomove = 1; | |
11847 | } | |
11848 | else if (strcmp (name, "bopt") == 0) | |
11849 | { | |
11850 | mips_opts.nobopt = 0; | |
11851 | } | |
11852 | else if (strcmp (name, "nobopt") == 0) | |
11853 | { | |
11854 | mips_opts.nobopt = 1; | |
11855 | } | |
11856 | else if (strcmp (name, "mips16") == 0 | |
11857 | || strcmp (name, "MIPS-16") == 0) | |
11858 | mips_opts.mips16 = 1; | |
11859 | else if (strcmp (name, "nomips16") == 0 | |
11860 | || strcmp (name, "noMIPS-16") == 0) | |
11861 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11862 | else if (strcmp (name, "mips3d") == 0) |
11863 | mips_opts.ase_mips3d = 1; | |
11864 | else if (strcmp (name, "nomips3d") == 0) | |
11865 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11866 | else if (strcmp (name, "mdmx") == 0) |
11867 | mips_opts.ase_mdmx = 1; | |
11868 | else if (strcmp (name, "nomdmx") == 0) | |
11869 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11870 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11871 | { |
af7ee8bf | 11872 | int reset = 0; |
252b5132 | 11873 | |
1a2c1fad CD |
11874 | /* Permit the user to change the ISA and architecture on the fly. |
11875 | Needless to say, misuse can cause serious problems. */ | |
af7ee8bf CD |
11876 | if (strcmp (name, "mips0") == 0) |
11877 | { | |
11878 | reset = 1; | |
11879 | mips_opts.isa = file_mips_isa; | |
11880 | } | |
11881 | else if (strcmp (name, "mips1") == 0) | |
11882 | mips_opts.isa = ISA_MIPS1; | |
11883 | else if (strcmp (name, "mips2") == 0) | |
11884 | mips_opts.isa = ISA_MIPS2; | |
11885 | else if (strcmp (name, "mips3") == 0) | |
11886 | mips_opts.isa = ISA_MIPS3; | |
11887 | else if (strcmp (name, "mips4") == 0) | |
11888 | mips_opts.isa = ISA_MIPS4; | |
11889 | else if (strcmp (name, "mips5") == 0) | |
11890 | mips_opts.isa = ISA_MIPS5; | |
11891 | else if (strcmp (name, "mips32") == 0) | |
11892 | mips_opts.isa = ISA_MIPS32; | |
11893 | else if (strcmp (name, "mips32r2") == 0) | |
11894 | mips_opts.isa = ISA_MIPS32R2; | |
11895 | else if (strcmp (name, "mips64") == 0) | |
11896 | mips_opts.isa = ISA_MIPS64; | |
5f74bc13 CD |
11897 | else if (strcmp (name, "mips64r2") == 0) |
11898 | mips_opts.isa = ISA_MIPS64R2; | |
1a2c1fad CD |
11899 | else if (strcmp (name, "arch=default") == 0) |
11900 | { | |
11901 | reset = 1; | |
11902 | mips_opts.arch = file_mips_arch; | |
11903 | mips_opts.isa = file_mips_isa; | |
11904 | } | |
11905 | else if (strncmp (name, "arch=", 5) == 0) | |
11906 | { | |
11907 | const struct mips_cpu_info *p; | |
11908 | ||
11909 | p = mips_parse_cpu("internal use", name + 5); | |
11910 | if (!p) | |
11911 | as_bad (_("unknown architecture %s"), name + 5); | |
11912 | else | |
11913 | { | |
11914 | mips_opts.arch = p->cpu; | |
11915 | mips_opts.isa = p->isa; | |
11916 | } | |
11917 | } | |
af7ee8bf CD |
11918 | else |
11919 | as_bad (_("unknown ISA level %s"), name + 4); | |
11920 | ||
11921 | switch (mips_opts.isa) | |
98d3f06f KH |
11922 | { |
11923 | case 0: | |
98d3f06f | 11924 | break; |
af7ee8bf CD |
11925 | case ISA_MIPS1: |
11926 | case ISA_MIPS2: | |
11927 | case ISA_MIPS32: | |
11928 | case ISA_MIPS32R2: | |
98d3f06f KH |
11929 | mips_opts.gp32 = 1; |
11930 | mips_opts.fp32 = 1; | |
11931 | break; | |
af7ee8bf CD |
11932 | case ISA_MIPS3: |
11933 | case ISA_MIPS4: | |
11934 | case ISA_MIPS5: | |
11935 | case ISA_MIPS64: | |
5f74bc13 | 11936 | case ISA_MIPS64R2: |
98d3f06f KH |
11937 | mips_opts.gp32 = 0; |
11938 | mips_opts.fp32 = 0; | |
11939 | break; | |
11940 | default: | |
11941 | as_bad (_("unknown ISA level %s"), name + 4); | |
11942 | break; | |
11943 | } | |
af7ee8bf | 11944 | if (reset) |
98d3f06f | 11945 | { |
af7ee8bf CD |
11946 | mips_opts.gp32 = file_mips_gp32; |
11947 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11948 | } |
252b5132 RH |
11949 | } |
11950 | else if (strcmp (name, "autoextend") == 0) | |
11951 | mips_opts.noautoextend = 0; | |
11952 | else if (strcmp (name, "noautoextend") == 0) | |
11953 | mips_opts.noautoextend = 1; | |
11954 | else if (strcmp (name, "push") == 0) | |
11955 | { | |
11956 | struct mips_option_stack *s; | |
11957 | ||
11958 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11959 | s->next = mips_opts_stack; | |
11960 | s->options = mips_opts; | |
11961 | mips_opts_stack = s; | |
11962 | } | |
11963 | else if (strcmp (name, "pop") == 0) | |
11964 | { | |
11965 | struct mips_option_stack *s; | |
11966 | ||
11967 | s = mips_opts_stack; | |
11968 | if (s == NULL) | |
11969 | as_bad (_(".set pop with no .set push")); | |
11970 | else | |
11971 | { | |
11972 | /* If we're changing the reorder mode we need to handle | |
11973 | delay slots correctly. */ | |
11974 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11975 | mips_emit_delays (TRUE); |
252b5132 RH |
11976 | else if (! s->options.noreorder && mips_opts.noreorder) |
11977 | { | |
11978 | if (prev_nop_frag != NULL) | |
11979 | { | |
11980 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11981 | * (mips_opts.mips16 ? 2 : 4)); | |
11982 | prev_nop_frag = NULL; | |
11983 | } | |
11984 | } | |
11985 | ||
11986 | mips_opts = s->options; | |
11987 | mips_opts_stack = s->next; | |
11988 | free (s); | |
11989 | } | |
11990 | } | |
11991 | else | |
11992 | { | |
11993 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11994 | } | |
11995 | *input_line_pointer = ch; | |
11996 | demand_empty_rest_of_line (); | |
11997 | } | |
11998 | ||
11999 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12000 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12001 | ||
12002 | static void | |
17a2f251 | 12003 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12004 | { |
12005 | mips_pic = SVR4_PIC; | |
143d77c5 | 12006 | mips_abicalls = TRUE; |
252b5132 RH |
12007 | if (USE_GLOBAL_POINTER_OPT) |
12008 | { | |
12009 | if (g_switch_seen && g_switch_value != 0) | |
12010 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12011 | g_switch_value = 0; | |
12012 | } | |
12013 | bfd_set_gp_size (stdoutput, 0); | |
12014 | demand_empty_rest_of_line (); | |
12015 | } | |
12016 | ||
12017 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12018 | PIC code. It sets the $gp register for the function based on the | |
12019 | function address, which is in the register named in the argument. | |
12020 | This uses a relocation against _gp_disp, which is handled specially | |
12021 | by the linker. The result is: | |
12022 | lui $gp,%hi(_gp_disp) | |
12023 | addiu $gp,$gp,%lo(_gp_disp) | |
12024 | addu $gp,$gp,.cpload argument | |
12025 | The .cpload argument is normally $25 == $t9. */ | |
12026 | ||
12027 | static void | |
17a2f251 | 12028 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12029 | { |
12030 | expressionS ex; | |
252b5132 | 12031 | |
6478892d TS |
12032 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12033 | .cpload is ignored. */ | |
12034 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12035 | { |
12036 | s_ignore (0); | |
12037 | return; | |
12038 | } | |
12039 | ||
d3ecfc59 | 12040 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12041 | if (mips_opts.noreorder == 0) |
12042 | as_warn (_(".cpload not in noreorder section")); | |
12043 | ||
12044 | ex.X_op = O_symbol; | |
12045 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12046 | ex.X_op_symbol = NULL; | |
12047 | ex.X_add_number = 0; | |
12048 | ||
12049 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12050 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12051 | |
584892a6 | 12052 | macro_start (); |
67c0d1eb RS |
12053 | macro_build_lui (&ex, mips_gp_register); |
12054 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12055 | mips_gp_register, BFD_RELOC_LO16); |
67c0d1eb | 12056 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, |
17a2f251 | 12057 | mips_gp_register, tc_get_register (0)); |
584892a6 | 12058 | macro_end (); |
252b5132 RH |
12059 | |
12060 | demand_empty_rest_of_line (); | |
12061 | } | |
12062 | ||
6478892d TS |
12063 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12064 | .cpsetup $reg1, offset|$reg2, label | |
12065 | ||
12066 | If offset is given, this results in: | |
12067 | sd $gp, offset($sp) | |
956cd1d6 | 12068 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12069 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12070 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12071 | |
12072 | If $reg2 is given, this results in: | |
12073 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12074 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12075 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12076 | daddu $gp, $gp, $reg1 | |
12077 | $reg1 is normally $25 == $t9. */ | |
6478892d | 12078 | static void |
17a2f251 | 12079 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12080 | { |
12081 | expressionS ex_off; | |
12082 | expressionS ex_sym; | |
12083 | int reg1; | |
f21f8242 | 12084 | char *f; |
6478892d | 12085 | |
8586fc66 | 12086 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12087 | We also need NewABI support. */ |
12088 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12089 | { | |
12090 | s_ignore (0); | |
12091 | return; | |
12092 | } | |
12093 | ||
12094 | reg1 = tc_get_register (0); | |
12095 | SKIP_WHITESPACE (); | |
12096 | if (*input_line_pointer != ',') | |
12097 | { | |
12098 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12099 | return; | |
12100 | } | |
12101 | else | |
80245285 | 12102 | ++input_line_pointer; |
6478892d TS |
12103 | SKIP_WHITESPACE (); |
12104 | if (*input_line_pointer == '$') | |
80245285 TS |
12105 | { |
12106 | mips_cpreturn_register = tc_get_register (0); | |
12107 | mips_cpreturn_offset = -1; | |
12108 | } | |
6478892d | 12109 | else |
80245285 TS |
12110 | { |
12111 | mips_cpreturn_offset = get_absolute_expression (); | |
12112 | mips_cpreturn_register = -1; | |
12113 | } | |
6478892d TS |
12114 | SKIP_WHITESPACE (); |
12115 | if (*input_line_pointer != ',') | |
12116 | { | |
12117 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12118 | return; | |
12119 | } | |
12120 | else | |
f9419b05 | 12121 | ++input_line_pointer; |
6478892d | 12122 | SKIP_WHITESPACE (); |
f21f8242 | 12123 | expression (&ex_sym); |
6478892d | 12124 | |
584892a6 | 12125 | macro_start (); |
6478892d TS |
12126 | if (mips_cpreturn_register == -1) |
12127 | { | |
12128 | ex_off.X_op = O_constant; | |
12129 | ex_off.X_add_symbol = NULL; | |
12130 | ex_off.X_op_symbol = NULL; | |
12131 | ex_off.X_add_number = mips_cpreturn_offset; | |
12132 | ||
67c0d1eb | 12133 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12134 | BFD_RELOC_LO16, SP); |
6478892d TS |
12135 | } |
12136 | else | |
67c0d1eb | 12137 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12138 | mips_gp_register, 0); |
6478892d | 12139 | |
f21f8242 AO |
12140 | /* Ensure there's room for the next two instructions, so that `f' |
12141 | doesn't end up with an address in the wrong frag. */ | |
12142 | frag_grow (8); | |
12143 | f = frag_more (0); | |
67c0d1eb | 12144 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 12145 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12146 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12147 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12148 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12149 | |
12150 | f = frag_more (0); | |
67c0d1eb | 12151 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, |
17a2f251 | 12152 | mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 12153 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12154 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12155 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12156 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12157 | |
67c0d1eb | 12158 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
17a2f251 | 12159 | mips_gp_register, reg1); |
584892a6 | 12160 | macro_end (); |
6478892d TS |
12161 | |
12162 | demand_empty_rest_of_line (); | |
12163 | } | |
12164 | ||
12165 | static void | |
17a2f251 | 12166 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12167 | { |
12168 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12169 | .cplocal is ignored. */ | |
12170 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12171 | { | |
12172 | s_ignore (0); | |
12173 | return; | |
12174 | } | |
12175 | ||
12176 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12177 | demand_empty_rest_of_line (); |
6478892d TS |
12178 | } |
12179 | ||
252b5132 RH |
12180 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12181 | offset from $sp. The offset is remembered, and after making a PIC | |
12182 | call $gp is restored from that location. */ | |
12183 | ||
12184 | static void | |
17a2f251 | 12185 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12186 | { |
12187 | expressionS ex; | |
252b5132 | 12188 | |
6478892d | 12189 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12190 | .cprestore is ignored. */ |
6478892d | 12191 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12192 | { |
12193 | s_ignore (0); | |
12194 | return; | |
12195 | } | |
12196 | ||
12197 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12198 | mips_cprestore_valid = 1; |
252b5132 RH |
12199 | |
12200 | ex.X_op = O_constant; | |
12201 | ex.X_add_symbol = NULL; | |
12202 | ex.X_op_symbol = NULL; | |
12203 | ex.X_add_number = mips_cprestore_offset; | |
12204 | ||
584892a6 | 12205 | macro_start (); |
67c0d1eb RS |
12206 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12207 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12208 | macro_end (); |
252b5132 RH |
12209 | |
12210 | demand_empty_rest_of_line (); | |
12211 | } | |
12212 | ||
6478892d | 12213 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12214 | was given in the preceding .cpsetup, it results in: |
6478892d | 12215 | ld $gp, offset($sp) |
76b3015f | 12216 | |
6478892d | 12217 | If a register $reg2 was given there, it results in: |
609f23f4 | 12218 | daddu $gp, $reg2, $0 |
6478892d TS |
12219 | */ |
12220 | static void | |
17a2f251 | 12221 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12222 | { |
12223 | expressionS ex; | |
6478892d TS |
12224 | |
12225 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12226 | We also need NewABI support. */ | |
12227 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12228 | { | |
12229 | s_ignore (0); | |
12230 | return; | |
12231 | } | |
12232 | ||
584892a6 | 12233 | macro_start (); |
6478892d TS |
12234 | if (mips_cpreturn_register == -1) |
12235 | { | |
12236 | ex.X_op = O_constant; | |
12237 | ex.X_add_symbol = NULL; | |
12238 | ex.X_op_symbol = NULL; | |
12239 | ex.X_add_number = mips_cpreturn_offset; | |
12240 | ||
67c0d1eb | 12241 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12242 | } |
12243 | else | |
67c0d1eb | 12244 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12245 | mips_cpreturn_register, 0); |
584892a6 | 12246 | macro_end (); |
6478892d TS |
12247 | |
12248 | demand_empty_rest_of_line (); | |
12249 | } | |
12250 | ||
12251 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12252 | code. It sets the offset to use in gp_rel relocations. */ | |
12253 | ||
12254 | static void | |
17a2f251 | 12255 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12256 | { |
12257 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12258 | We also need NewABI support. */ | |
12259 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12260 | { | |
12261 | s_ignore (0); | |
12262 | return; | |
12263 | } | |
12264 | ||
def2e0dd | 12265 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12266 | |
12267 | demand_empty_rest_of_line (); | |
12268 | } | |
12269 | ||
252b5132 RH |
12270 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12271 | code. It generates a 32 bit GP relative reloc. */ | |
12272 | ||
12273 | static void | |
17a2f251 | 12274 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12275 | { |
12276 | symbolS *label; | |
12277 | expressionS ex; | |
12278 | char *p; | |
12279 | ||
12280 | /* When not generating PIC code, this is treated as .word. */ | |
12281 | if (mips_pic != SVR4_PIC) | |
12282 | { | |
12283 | s_cons (2); | |
12284 | return; | |
12285 | } | |
12286 | ||
12287 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12288 | mips_emit_delays (TRUE); |
252b5132 RH |
12289 | if (auto_align) |
12290 | mips_align (2, 0, label); | |
12291 | mips_clear_insn_labels (); | |
12292 | ||
12293 | expression (&ex); | |
12294 | ||
12295 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12296 | { | |
12297 | as_bad (_("Unsupported use of .gpword")); | |
12298 | ignore_rest_of_line (); | |
12299 | } | |
12300 | ||
12301 | p = frag_more (4); | |
17a2f251 | 12302 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12303 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12304 | BFD_RELOC_GPREL32); |
252b5132 RH |
12305 | |
12306 | demand_empty_rest_of_line (); | |
12307 | } | |
12308 | ||
10181a0d | 12309 | static void |
17a2f251 | 12310 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12311 | { |
12312 | symbolS *label; | |
12313 | expressionS ex; | |
12314 | char *p; | |
12315 | ||
12316 | /* When not generating PIC code, this is treated as .dword. */ | |
12317 | if (mips_pic != SVR4_PIC) | |
12318 | { | |
12319 | s_cons (3); | |
12320 | return; | |
12321 | } | |
12322 | ||
12323 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12324 | mips_emit_delays (TRUE); |
10181a0d AO |
12325 | if (auto_align) |
12326 | mips_align (3, 0, label); | |
12327 | mips_clear_insn_labels (); | |
12328 | ||
12329 | expression (&ex); | |
12330 | ||
12331 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12332 | { | |
12333 | as_bad (_("Unsupported use of .gpdword")); | |
12334 | ignore_rest_of_line (); | |
12335 | } | |
12336 | ||
12337 | p = frag_more (8); | |
17a2f251 | 12338 | md_number_to_chars (p, 0, 8); |
a105a300 | 12339 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12340 | BFD_RELOC_GPREL32); |
12341 | ||
12342 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12343 | ex.X_op = O_absent; | |
12344 | ex.X_add_symbol = 0; | |
12345 | ex.X_add_number = 0; | |
b34976b6 | 12346 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12347 | BFD_RELOC_64); |
12348 | ||
12349 | demand_empty_rest_of_line (); | |
12350 | } | |
12351 | ||
252b5132 RH |
12352 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12353 | tables in SVR4 PIC code. */ | |
12354 | ||
12355 | static void | |
17a2f251 | 12356 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12357 | { |
252b5132 RH |
12358 | int reg; |
12359 | ||
10181a0d AO |
12360 | /* This is ignored when not generating SVR4 PIC code. */ |
12361 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12362 | { |
12363 | s_ignore (0); | |
12364 | return; | |
12365 | } | |
12366 | ||
12367 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12368 | macro_start (); |
252b5132 | 12369 | reg = tc_get_register (0); |
67c0d1eb | 12370 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12371 | macro_end (); |
252b5132 | 12372 | |
bdaaa2e1 | 12373 | demand_empty_rest_of_line (); |
252b5132 RH |
12374 | } |
12375 | ||
12376 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12377 | mips16 mode. This permits the linker to handle them specially, | |
12378 | such as generating jalx instructions when needed. We also make | |
12379 | them odd for the duration of the assembly, in order to generate the | |
12380 | right sort of code. We will make them even in the adjust_symtab | |
12381 | routine, while leaving them marked. This is convenient for the | |
12382 | debugger and the disassembler. The linker knows to make them odd | |
12383 | again. */ | |
12384 | ||
12385 | static void | |
17a2f251 | 12386 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12387 | { |
f9419b05 | 12388 | mips16_mark_labels (); |
252b5132 RH |
12389 | |
12390 | demand_empty_rest_of_line (); | |
12391 | } | |
12392 | ||
12393 | /* Handle a .stabn directive. We need these in order to mark a label | |
12394 | as being a mips16 text label correctly. Sometimes the compiler | |
12395 | will emit a label, followed by a .stabn, and then switch sections. | |
12396 | If the label and .stabn are in mips16 mode, then the label is | |
12397 | really a mips16 text label. */ | |
12398 | ||
12399 | static void | |
17a2f251 | 12400 | s_mips_stab (int type) |
252b5132 | 12401 | { |
f9419b05 | 12402 | if (type == 'n') |
252b5132 RH |
12403 | mips16_mark_labels (); |
12404 | ||
12405 | s_stab (type); | |
12406 | } | |
12407 | ||
12408 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12409 | */ | |
12410 | ||
12411 | static void | |
17a2f251 | 12412 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12413 | { |
12414 | char *name; | |
12415 | int c; | |
12416 | symbolS *symbolP; | |
12417 | expressionS exp; | |
12418 | ||
12419 | name = input_line_pointer; | |
12420 | c = get_symbol_end (); | |
12421 | symbolP = symbol_find_or_make (name); | |
12422 | S_SET_WEAK (symbolP); | |
12423 | *input_line_pointer = c; | |
12424 | ||
12425 | SKIP_WHITESPACE (); | |
12426 | ||
12427 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12428 | { | |
12429 | if (S_IS_DEFINED (symbolP)) | |
12430 | { | |
956cd1d6 | 12431 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12432 | S_GET_NAME (symbolP)); |
12433 | ignore_rest_of_line (); | |
12434 | return; | |
12435 | } | |
bdaaa2e1 | 12436 | |
252b5132 RH |
12437 | if (*input_line_pointer == ',') |
12438 | { | |
12439 | ++input_line_pointer; | |
12440 | SKIP_WHITESPACE (); | |
12441 | } | |
bdaaa2e1 | 12442 | |
252b5132 RH |
12443 | expression (&exp); |
12444 | if (exp.X_op != O_symbol) | |
12445 | { | |
12446 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12447 | ignore_rest_of_line (); |
252b5132 RH |
12448 | return; |
12449 | } | |
49309057 | 12450 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12451 | } |
12452 | ||
12453 | demand_empty_rest_of_line (); | |
12454 | } | |
12455 | ||
12456 | /* Parse a register string into a number. Called from the ECOFF code | |
12457 | to parse .frame. The argument is non-zero if this is the frame | |
12458 | register, so that we can record it in mips_frame_reg. */ | |
12459 | ||
12460 | int | |
17a2f251 | 12461 | tc_get_register (int frame) |
252b5132 RH |
12462 | { |
12463 | int reg; | |
12464 | ||
12465 | SKIP_WHITESPACE (); | |
12466 | if (*input_line_pointer++ != '$') | |
12467 | { | |
12468 | as_warn (_("expected `$'")); | |
85b51719 | 12469 | reg = ZERO; |
252b5132 | 12470 | } |
3882b010 | 12471 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12472 | { |
12473 | reg = get_absolute_expression (); | |
12474 | if (reg < 0 || reg >= 32) | |
12475 | { | |
12476 | as_warn (_("Bad register number")); | |
85b51719 | 12477 | reg = ZERO; |
252b5132 RH |
12478 | } |
12479 | } | |
12480 | else | |
12481 | { | |
76db943d | 12482 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12483 | { |
12484 | reg = RA; | |
12485 | input_line_pointer += 2; | |
12486 | } | |
76db943d | 12487 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12488 | { |
12489 | reg = FP; | |
12490 | input_line_pointer += 2; | |
12491 | } | |
252b5132 | 12492 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12493 | { |
12494 | reg = SP; | |
12495 | input_line_pointer += 2; | |
12496 | } | |
252b5132 | 12497 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12498 | { |
12499 | reg = GP; | |
12500 | input_line_pointer += 2; | |
12501 | } | |
252b5132 | 12502 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12503 | { |
12504 | reg = AT; | |
12505 | input_line_pointer += 2; | |
12506 | } | |
12507 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12508 | { | |
12509 | reg = KT0; | |
12510 | input_line_pointer += 3; | |
12511 | } | |
12512 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12513 | { | |
12514 | reg = KT1; | |
12515 | input_line_pointer += 3; | |
12516 | } | |
12517 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12518 | { | |
12519 | reg = ZERO; | |
12520 | input_line_pointer += 4; | |
12521 | } | |
252b5132 RH |
12522 | else |
12523 | { | |
12524 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12525 | reg = ZERO; |
12526 | while (ISALNUM(*input_line_pointer)) | |
12527 | input_line_pointer++; | |
252b5132 | 12528 | } |
252b5132 RH |
12529 | } |
12530 | if (frame) | |
7a621144 DJ |
12531 | { |
12532 | mips_frame_reg = reg != 0 ? reg : SP; | |
12533 | mips_frame_reg_valid = 1; | |
12534 | mips_cprestore_valid = 0; | |
12535 | } | |
252b5132 RH |
12536 | return reg; |
12537 | } | |
12538 | ||
12539 | valueT | |
17a2f251 | 12540 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12541 | { |
12542 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12543 | ||
12544 | #ifdef OBJ_ELF | |
12545 | /* We don't need to align ELF sections to the full alignment. | |
12546 | However, Irix 5 may prefer that we align them at least to a 16 | |
12547 | byte boundary. We don't bother to align the sections if we are | |
12548 | targeted for an embedded system. */ | |
12549 | if (strcmp (TARGET_OS, "elf") == 0) | |
12550 | return addr; | |
12551 | if (align > 4) | |
12552 | align = 4; | |
12553 | #endif | |
12554 | ||
12555 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12556 | } | |
12557 | ||
12558 | /* Utility routine, called from above as well. If called while the | |
12559 | input file is still being read, it's only an approximation. (For | |
12560 | example, a symbol may later become defined which appeared to be | |
12561 | undefined earlier.) */ | |
12562 | ||
12563 | static int | |
17a2f251 | 12564 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12565 | { |
12566 | if (sym == 0) | |
12567 | return 0; | |
12568 | ||
6478892d | 12569 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12570 | { |
12571 | const char *symname; | |
12572 | int change; | |
12573 | ||
c9914766 | 12574 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12575 | register. It can be if it is smaller than the -G size or if |
12576 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12577 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12578 | they can. */ |
12579 | symname = S_GET_NAME (sym); | |
12580 | if (symname != (const char *) NULL | |
12581 | && (strcmp (symname, "eprol") == 0 | |
12582 | || strcmp (symname, "etext") == 0 | |
12583 | || strcmp (symname, "_gp") == 0 | |
12584 | || strcmp (symname, "edata") == 0 | |
12585 | || strcmp (symname, "_fbss") == 0 | |
12586 | || strcmp (symname, "_fdata") == 0 | |
12587 | || strcmp (symname, "_ftext") == 0 | |
12588 | || strcmp (symname, "end") == 0 | |
12589 | || strcmp (symname, "_gp_disp") == 0)) | |
12590 | change = 1; | |
12591 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12592 | && (0 | |
12593 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12594 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12595 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12596 | <= g_switch_value)) | |
252b5132 RH |
12597 | #endif |
12598 | /* We must defer this decision until after the whole | |
12599 | file has been read, since there might be a .extern | |
12600 | after the first use of this symbol. */ | |
12601 | || (before_relaxing | |
12602 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12603 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12604 | #endif |
12605 | && S_GET_VALUE (sym) == 0) | |
12606 | || (S_GET_VALUE (sym) != 0 | |
12607 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12608 | change = 0; | |
12609 | else | |
12610 | { | |
12611 | const char *segname; | |
12612 | ||
12613 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12614 | assert (strcmp (segname, ".lit8") != 0 | |
12615 | && strcmp (segname, ".lit4") != 0); | |
12616 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12617 | && strcmp (segname, ".sbss") != 0 |
12618 | && strncmp (segname, ".sdata.", 7) != 0 | |
12619 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12620 | } |
12621 | return change; | |
12622 | } | |
12623 | else | |
c9914766 | 12624 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12625 | return 1; |
12626 | } | |
12627 | ||
5919d012 RS |
12628 | |
12629 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12630 | ||
12631 | static bfd_boolean | |
17a2f251 | 12632 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12633 | { |
12634 | asection *symsec; | |
12635 | bfd_boolean linkonce; | |
12636 | ||
12637 | /* Handle the case of a symbol equated to another symbol. */ | |
12638 | while (symbol_equated_reloc_p (sym)) | |
12639 | { | |
12640 | symbolS *n; | |
12641 | ||
12642 | /* It's possible to get a loop here in a badly written | |
12643 | program. */ | |
12644 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12645 | if (n == sym) | |
12646 | break; | |
12647 | sym = n; | |
12648 | } | |
12649 | ||
12650 | symsec = S_GET_SEGMENT (sym); | |
12651 | ||
12652 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12653 | linkonce = FALSE; | |
12654 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12655 | { | |
12656 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12657 | != 0) | |
12658 | linkonce = TRUE; | |
12659 | ||
12660 | /* The GNU toolchain uses an extension for ELF: a section | |
12661 | beginning with the magic string .gnu.linkonce is a linkonce | |
12662 | section. */ | |
12663 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12664 | sizeof ".gnu.linkonce" - 1) == 0) | |
12665 | linkonce = TRUE; | |
12666 | } | |
12667 | ||
12668 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12669 | return (symsec != &bfd_und_section | |
12670 | && symsec != &bfd_abs_section | |
12671 | && ! bfd_is_com_section (symsec) | |
12672 | && !linkonce | |
12673 | #ifdef OBJ_ELF | |
12674 | /* A global or weak symbol is treated as external. */ | |
12675 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
12676 | || (! S_IS_WEAK (sym) | |
12677 | && (! S_IS_EXTERNAL (sym) | |
12678 | || mips_pic == EMBEDDED_PIC))) | |
12679 | #endif | |
12680 | ); | |
12681 | } | |
12682 | ||
12683 | ||
252b5132 RH |
12684 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12685 | extended opcode. SEC is the section the frag is in. */ | |
12686 | ||
12687 | static int | |
17a2f251 | 12688 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12689 | { |
12690 | int type; | |
12691 | register const struct mips16_immed_operand *op; | |
12692 | offsetT val; | |
12693 | int mintiny, maxtiny; | |
12694 | segT symsec; | |
98aa84af | 12695 | fragS *sym_frag; |
252b5132 RH |
12696 | |
12697 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12698 | return 0; | |
12699 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12700 | return 1; | |
12701 | ||
12702 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12703 | op = mips16_immed_operands; | |
12704 | while (op->type != type) | |
12705 | { | |
12706 | ++op; | |
12707 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12708 | } | |
12709 | ||
12710 | if (op->unsp) | |
12711 | { | |
12712 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12713 | { | |
12714 | mintiny = 1; | |
12715 | maxtiny = 1 << op->nbits; | |
12716 | } | |
12717 | else | |
12718 | { | |
12719 | mintiny = 0; | |
12720 | maxtiny = (1 << op->nbits) - 1; | |
12721 | } | |
12722 | } | |
12723 | else | |
12724 | { | |
12725 | mintiny = - (1 << (op->nbits - 1)); | |
12726 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12727 | } | |
12728 | ||
98aa84af | 12729 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12730 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12731 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12732 | |
12733 | if (op->pcrel) | |
12734 | { | |
12735 | addressT addr; | |
12736 | ||
12737 | /* We won't have the section when we are called from | |
12738 | mips_relax_frag. However, we will always have been called | |
12739 | from md_estimate_size_before_relax first. If this is a | |
12740 | branch to a different section, we mark it as such. If SEC is | |
12741 | NULL, and the frag is not marked, then it must be a branch to | |
12742 | the same section. */ | |
12743 | if (sec == NULL) | |
12744 | { | |
12745 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12746 | return 1; | |
12747 | } | |
12748 | else | |
12749 | { | |
98aa84af | 12750 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12751 | if (symsec != sec) |
12752 | { | |
12753 | fragp->fr_subtype = | |
12754 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12755 | ||
12756 | /* FIXME: We should support this, and let the linker | |
12757 | catch branches and loads that are out of range. */ | |
12758 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12759 | _("unsupported PC relative reference to different section")); | |
12760 | ||
12761 | return 1; | |
12762 | } | |
98aa84af AM |
12763 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12764 | /* Assume non-extended on the first relaxation pass. | |
12765 | The address we have calculated will be bogus if this is | |
12766 | a forward branch to another frag, as the forward frag | |
12767 | will have fr_address == 0. */ | |
12768 | return 0; | |
252b5132 RH |
12769 | } |
12770 | ||
12771 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12772 | the same section. If the relax_marker of the symbol fragment |
12773 | differs from the relax_marker of this fragment, we have not | |
12774 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12775 | in STRETCH in order to get a better estimate of the address. |
12776 | This particularly matters because of the shift bits. */ | |
12777 | if (stretch != 0 | |
98aa84af | 12778 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12779 | { |
12780 | fragS *f; | |
12781 | ||
12782 | /* Adjust stretch for any alignment frag. Note that if have | |
12783 | been expanding the earlier code, the symbol may be | |
12784 | defined in what appears to be an earlier frag. FIXME: | |
12785 | This doesn't handle the fr_subtype field, which specifies | |
12786 | a maximum number of bytes to skip when doing an | |
12787 | alignment. */ | |
98aa84af | 12788 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12789 | { |
12790 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12791 | { | |
12792 | if (stretch < 0) | |
12793 | stretch = - ((- stretch) | |
12794 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12795 | else | |
12796 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12797 | if (stretch == 0) | |
12798 | break; | |
12799 | } | |
12800 | } | |
12801 | if (f != NULL) | |
12802 | val += stretch; | |
12803 | } | |
12804 | ||
12805 | addr = fragp->fr_address + fragp->fr_fix; | |
12806 | ||
12807 | /* The base address rules are complicated. The base address of | |
12808 | a branch is the following instruction. The base address of a | |
12809 | PC relative load or add is the instruction itself, but if it | |
12810 | is in a delay slot (in which case it can not be extended) use | |
12811 | the address of the instruction whose delay slot it is in. */ | |
12812 | if (type == 'p' || type == 'q') | |
12813 | { | |
12814 | addr += 2; | |
12815 | ||
12816 | /* If we are currently assuming that this frag should be | |
12817 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12818 | higher. */ |
252b5132 RH |
12819 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12820 | addr += 2; | |
12821 | ||
12822 | /* Ignore the low bit in the target, since it will be set | |
12823 | for a text label. */ | |
12824 | if ((val & 1) != 0) | |
12825 | --val; | |
12826 | } | |
12827 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12828 | addr -= 4; | |
12829 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12830 | addr -= 2; | |
12831 | ||
12832 | val -= addr & ~ ((1 << op->shift) - 1); | |
12833 | ||
12834 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12835 | if (type == 'p' || type == 'q') | |
12836 | val /= 2; | |
12837 | ||
12838 | /* If any of the shifted bits are set, we must use an extended | |
12839 | opcode. If the address depends on the size of this | |
12840 | instruction, this can lead to a loop, so we arrange to always | |
12841 | use an extended opcode. We only check this when we are in | |
12842 | the main relaxation loop, when SEC is NULL. */ | |
12843 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12844 | { | |
12845 | fragp->fr_subtype = | |
12846 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12847 | return 1; | |
12848 | } | |
12849 | ||
12850 | /* If we are about to mark a frag as extended because the value | |
12851 | is precisely maxtiny + 1, then there is a chance of an | |
12852 | infinite loop as in the following code: | |
12853 | la $4,foo | |
12854 | .skip 1020 | |
12855 | .align 2 | |
12856 | foo: | |
12857 | In this case when the la is extended, foo is 0x3fc bytes | |
12858 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12859 | the la must be extended. To avoid this loop, we mark the | |
12860 | frag as extended if it was small, and is about to become | |
12861 | extended with a value of maxtiny + 1. */ | |
12862 | if (val == ((maxtiny + 1) << op->shift) | |
12863 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12864 | && sec == NULL) | |
12865 | { | |
12866 | fragp->fr_subtype = | |
12867 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12868 | return 1; | |
12869 | } | |
12870 | } | |
12871 | else if (symsec != absolute_section && sec != NULL) | |
12872 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12873 | ||
12874 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12875 | || val < (mintiny << op->shift) | |
12876 | || val > (maxtiny << op->shift)) | |
12877 | return 1; | |
12878 | else | |
12879 | return 0; | |
12880 | } | |
12881 | ||
4a6a3df4 AO |
12882 | /* Compute the length of a branch sequence, and adjust the |
12883 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12884 | worst-case length is computed, with UPDATE being used to indicate | |
12885 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12886 | branch is to be computed. */ | |
12887 | static int | |
17a2f251 | 12888 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12889 | { |
b34976b6 | 12890 | bfd_boolean toofar; |
4a6a3df4 AO |
12891 | int length; |
12892 | ||
12893 | if (fragp | |
12894 | && S_IS_DEFINED (fragp->fr_symbol) | |
12895 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12896 | { | |
12897 | addressT addr; | |
12898 | offsetT val; | |
12899 | ||
12900 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12901 | ||
12902 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12903 | ||
12904 | val -= addr; | |
12905 | ||
12906 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12907 | } | |
12908 | else if (fragp) | |
12909 | /* If the symbol is not defined or it's in a different segment, | |
12910 | assume the user knows what's going on and emit a short | |
12911 | branch. */ | |
b34976b6 | 12912 | toofar = FALSE; |
4a6a3df4 | 12913 | else |
b34976b6 | 12914 | toofar = TRUE; |
4a6a3df4 AO |
12915 | |
12916 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12917 | fragp->fr_subtype | |
af6ae2ad | 12918 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12919 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12920 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12921 | toofar); | |
12922 | ||
12923 | length = 4; | |
12924 | if (toofar) | |
12925 | { | |
12926 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12927 | length += 8; | |
12928 | ||
12929 | if (mips_pic != NO_PIC) | |
12930 | { | |
12931 | /* Additional space for PIC loading of target address. */ | |
12932 | length += 8; | |
12933 | if (mips_opts.isa == ISA_MIPS1) | |
12934 | /* Additional space for $at-stabilizing nop. */ | |
12935 | length += 4; | |
12936 | } | |
12937 | ||
12938 | /* If branch is conditional. */ | |
12939 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12940 | length += 8; | |
12941 | } | |
b34976b6 | 12942 | |
4a6a3df4 AO |
12943 | return length; |
12944 | } | |
12945 | ||
252b5132 RH |
12946 | /* Estimate the size of a frag before relaxing. Unless this is the |
12947 | mips16, we are not really relaxing here, and the final size is | |
12948 | encoded in the subtype information. For the mips16, we have to | |
12949 | decide whether we are using an extended opcode or not. */ | |
12950 | ||
252b5132 | 12951 | int |
17a2f251 | 12952 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12953 | { |
5919d012 | 12954 | int change; |
252b5132 | 12955 | |
4a6a3df4 AO |
12956 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12957 | { | |
12958 | ||
b34976b6 AM |
12959 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12960 | ||
4a6a3df4 AO |
12961 | return fragp->fr_var; |
12962 | } | |
12963 | ||
252b5132 | 12964 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12965 | /* We don't want to modify the EXTENDED bit here; it might get us |
12966 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12967 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12968 | |
12969 | if (mips_pic == NO_PIC) | |
5919d012 | 12970 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12971 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12972 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12973 | else |
12974 | abort (); | |
12975 | ||
12976 | if (change) | |
12977 | { | |
4d7206a2 | 12978 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12979 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12980 | } |
4d7206a2 RS |
12981 | else |
12982 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12983 | } |
12984 | ||
12985 | /* This is called to see whether a reloc against a defined symbol | |
12986 | should be converted into a reloc against a section. Don't adjust | |
12987 | MIPS16 jump relocations, so we don't have to worry about the format | |
12988 | of the offset in the .o file. Don't adjust relocations against | |
12989 | mips16 symbols, so that the linker can find them if it needs to set | |
12990 | up a stub. */ | |
12991 | ||
12992 | int | |
17a2f251 | 12993 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
12994 | { |
12995 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
12996 | return 0; | |
a161fe53 | 12997 | |
252b5132 RH |
12998 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12999 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13000 | return 0; | |
a161fe53 | 13001 | |
252b5132 RH |
13002 | if (fixp->fx_addsy == NULL) |
13003 | return 1; | |
a161fe53 | 13004 | |
252b5132 RH |
13005 | #ifdef OBJ_ELF |
13006 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13007 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13008 | && fixp->fx_subsy == NULL) | |
13009 | return 0; | |
13010 | #endif | |
a161fe53 | 13011 | |
252b5132 RH |
13012 | return 1; |
13013 | } | |
13014 | ||
13015 | /* Translate internal representation of relocation info to BFD target | |
13016 | format. */ | |
13017 | ||
13018 | arelent ** | |
17a2f251 | 13019 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13020 | { |
13021 | static arelent *retval[4]; | |
13022 | arelent *reloc; | |
13023 | bfd_reloc_code_real_type code; | |
13024 | ||
4b0cff4e TS |
13025 | memset (retval, 0, sizeof(retval)); |
13026 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13027 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13028 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13029 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13030 | ||
13031 | if (mips_pic == EMBEDDED_PIC | |
13032 | && SWITCH_TABLE (fixp)) | |
13033 | { | |
13034 | /* For a switch table entry we use a special reloc. The addend | |
13035 | is actually the difference between the reloc address and the | |
13036 | subtrahend. */ | |
13037 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13038 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13039 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13040 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13041 | } | |
30ac9238 | 13042 | else if (fixp->fx_pcrel) |
252b5132 | 13043 | { |
30ac9238 RS |
13044 | bfd_vma pcrel_address; |
13045 | ||
13046 | /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high | |
13047 | high-part relocs is the address of the low-part reloc. */ | |
13048 | if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13049 | { | |
13050 | assert (fixp->fx_next != NULL | |
13051 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
13052 | pcrel_address = (fixp->fx_next->fx_where | |
13053 | + fixp->fx_next->fx_frag->fr_address); | |
13054 | } | |
252b5132 | 13055 | else |
30ac9238 RS |
13056 | pcrel_address = reloc->address; |
13057 | ||
13058 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13059 | { | |
13060 | /* At this point, fx_addnumber is "symbol offset - pcrel_address". | |
13061 | Relocations want only the symbol offset. */ | |
13062 | reloc->addend = fixp->fx_addnumber + pcrel_address; | |
13063 | } | |
13064 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16 | |
13065 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
4514d474 | 13066 | { |
30ac9238 | 13067 | /* We use a special addend for an internal RELLO or RELHI reloc. */ |
4514d474 | 13068 | if (symbol_section_p (fixp->fx_addsy)) |
30ac9238 | 13069 | reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy); |
4514d474 | 13070 | else |
30ac9238 | 13071 | reloc->addend = fixp->fx_addnumber + pcrel_address; |
4514d474 | 13072 | } |
252b5132 | 13073 | else |
4514d474 | 13074 | { |
30ac9238 RS |
13075 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
13076 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13077 | handling. */ | |
13078 | reloc->addend = pcrel_address; | |
4514d474 | 13079 | else |
30ac9238 | 13080 | reloc->addend = -pcrel_address; |
4514d474 | 13081 | } |
252b5132 | 13082 | } |
252b5132 | 13083 | else |
30ac9238 | 13084 | reloc->addend = fixp->fx_addnumber; |
252b5132 | 13085 | |
438c16b8 TS |
13086 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13087 | entry to be used in the relocation's section offset. */ | |
13088 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13089 | { |
13090 | reloc->address = reloc->addend; | |
13091 | reloc->addend = 0; | |
13092 | } | |
13093 | ||
13094 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13095 | fixup_segment converted a non-PC relative reloc into a PC | |
13096 | relative reloc. In such a case, we need to convert the reloc | |
13097 | code. */ | |
13098 | code = fixp->fx_r_type; | |
13099 | if (fixp->fx_pcrel) | |
13100 | { | |
13101 | switch (code) | |
13102 | { | |
13103 | case BFD_RELOC_8: | |
13104 | code = BFD_RELOC_8_PCREL; | |
13105 | break; | |
13106 | case BFD_RELOC_16: | |
13107 | code = BFD_RELOC_16_PCREL; | |
13108 | break; | |
13109 | case BFD_RELOC_32: | |
13110 | code = BFD_RELOC_32_PCREL; | |
13111 | break; | |
13112 | case BFD_RELOC_64: | |
13113 | code = BFD_RELOC_64_PCREL; | |
13114 | break; | |
13115 | case BFD_RELOC_8_PCREL: | |
13116 | case BFD_RELOC_16_PCREL: | |
13117 | case BFD_RELOC_32_PCREL: | |
13118 | case BFD_RELOC_64_PCREL: | |
13119 | case BFD_RELOC_16_PCREL_S2: | |
13120 | case BFD_RELOC_PCREL_HI16_S: | |
13121 | case BFD_RELOC_PCREL_LO16: | |
13122 | break; | |
13123 | default: | |
13124 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13125 | _("Cannot make %s relocation PC relative"), | |
13126 | bfd_get_reloc_code_name (code)); | |
13127 | } | |
13128 | } | |
13129 | ||
0b25d3e6 AO |
13130 | /* To support a PC relative reloc when generating embedded PIC code |
13131 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13132 | make sure that we don't let such a reloc escape normally. */ | |
13133 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13134 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13135 | && code == BFD_RELOC_16_PCREL_S2 | |
13136 | && mips_pic != EMBEDDED_PIC) | |
13137 | reloc->howto = NULL; | |
13138 | else | |
13139 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13140 | ||
252b5132 RH |
13141 | if (reloc->howto == NULL) |
13142 | { | |
13143 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13144 | _("Can not represent %s relocation in this object file format"), | |
13145 | bfd_get_reloc_code_name (code)); | |
13146 | retval[0] = NULL; | |
13147 | } | |
13148 | ||
13149 | return retval; | |
13150 | } | |
13151 | ||
13152 | /* Relax a machine dependent frag. This returns the amount by which | |
13153 | the current size of the frag should change. */ | |
13154 | ||
13155 | int | |
17a2f251 | 13156 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13157 | { |
4a6a3df4 AO |
13158 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13159 | { | |
13160 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13161 | |
13162 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13163 | |
13164 | return fragp->fr_var - old_var; | |
13165 | } | |
13166 | ||
252b5132 RH |
13167 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13168 | return 0; | |
13169 | ||
c4e7957c | 13170 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13171 | { |
13172 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13173 | return 0; | |
13174 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13175 | return 2; | |
13176 | } | |
13177 | else | |
13178 | { | |
13179 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13180 | return 0; | |
13181 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13182 | return -2; | |
13183 | } | |
13184 | ||
13185 | return 0; | |
13186 | } | |
13187 | ||
13188 | /* Convert a machine dependent frag. */ | |
13189 | ||
13190 | void | |
17a2f251 | 13191 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13192 | { |
4a6a3df4 AO |
13193 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13194 | { | |
13195 | bfd_byte *buf; | |
13196 | unsigned long insn; | |
13197 | expressionS exp; | |
13198 | fixS *fixp; | |
b34976b6 | 13199 | |
4a6a3df4 AO |
13200 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13201 | ||
13202 | if (target_big_endian) | |
13203 | insn = bfd_getb32 (buf); | |
13204 | else | |
13205 | insn = bfd_getl32 (buf); | |
b34976b6 | 13206 | |
4a6a3df4 AO |
13207 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13208 | { | |
13209 | /* We generate a fixup instead of applying it right now | |
13210 | because, if there are linker relaxations, we're going to | |
13211 | need the relocations. */ | |
13212 | exp.X_op = O_symbol; | |
13213 | exp.X_add_symbol = fragp->fr_symbol; | |
13214 | exp.X_add_number = fragp->fr_offset; | |
13215 | ||
13216 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13217 | 4, &exp, 1, |
13218 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13219 | fixp->fx_file = fragp->fr_file; |
13220 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13221 | |
17a2f251 | 13222 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13223 | buf += 4; |
13224 | } | |
13225 | else | |
13226 | { | |
13227 | int i; | |
13228 | ||
13229 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13230 | _("relaxed out-of-range branch into a jump")); | |
13231 | ||
13232 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13233 | goto uncond; | |
13234 | ||
13235 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13236 | { | |
13237 | /* Reverse the branch. */ | |
13238 | switch ((insn >> 28) & 0xf) | |
13239 | { | |
13240 | case 4: | |
13241 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13242 | have the condition reversed by tweaking a single | |
13243 | bit, and their opcodes all have 0x4???????. */ | |
13244 | assert ((insn & 0xf1000000) == 0x41000000); | |
13245 | insn ^= 0x00010000; | |
13246 | break; | |
13247 | ||
13248 | case 0: | |
13249 | /* bltz 0x04000000 bgez 0x04010000 | |
13250 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13251 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13252 | insn ^= 0x00010000; | |
13253 | break; | |
b34976b6 | 13254 | |
4a6a3df4 AO |
13255 | case 1: |
13256 | /* beq 0x10000000 bne 0x14000000 | |
13257 | blez 0x18000000 bgtz 0x1c000000 */ | |
13258 | insn ^= 0x04000000; | |
13259 | break; | |
13260 | ||
13261 | default: | |
13262 | abort (); | |
13263 | } | |
13264 | } | |
13265 | ||
13266 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13267 | { | |
13268 | /* Clear the and-link bit. */ | |
13269 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13270 | ||
13271 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13272 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13273 | insn &= ~0x00100000; | |
13274 | } | |
13275 | ||
13276 | /* Branch over the branch (if the branch was likely) or the | |
13277 | full jump (not likely case). Compute the offset from the | |
13278 | current instruction to branch to. */ | |
13279 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13280 | i = 16; | |
13281 | else | |
13282 | { | |
13283 | /* How many bytes in instructions we've already emitted? */ | |
13284 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13285 | /* How many bytes in instructions from here to the end? */ | |
13286 | i = fragp->fr_var - i; | |
13287 | } | |
13288 | /* Convert to instruction count. */ | |
13289 | i >>= 2; | |
13290 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13291 | i--; |
4a6a3df4 AO |
13292 | insn |= i; |
13293 | /* Branch over the jump. */ | |
17a2f251 | 13294 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13295 | buf += 4; |
13296 | ||
13297 | /* Nop */ | |
17a2f251 | 13298 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13299 | buf += 4; |
13300 | ||
13301 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13302 | { | |
13303 | /* beql $0, $0, 2f */ | |
13304 | insn = 0x50000000; | |
13305 | /* Compute the PC offset from the current instruction to | |
13306 | the end of the variable frag. */ | |
13307 | /* How many bytes in instructions we've already emitted? */ | |
13308 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13309 | /* How many bytes in instructions from here to the end? */ | |
13310 | i = fragp->fr_var - i; | |
13311 | /* Convert to instruction count. */ | |
13312 | i >>= 2; | |
13313 | /* Don't decrement i, because we want to branch over the | |
13314 | delay slot. */ | |
13315 | ||
13316 | insn |= i; | |
17a2f251 | 13317 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13318 | buf += 4; |
13319 | ||
17a2f251 | 13320 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13321 | buf += 4; |
13322 | } | |
13323 | ||
13324 | uncond: | |
13325 | if (mips_pic == NO_PIC) | |
13326 | { | |
13327 | /* j or jal. */ | |
13328 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13329 | ? 0x0c000000 : 0x08000000); | |
13330 | exp.X_op = O_symbol; | |
13331 | exp.X_add_symbol = fragp->fr_symbol; | |
13332 | exp.X_add_number = fragp->fr_offset; | |
13333 | ||
13334 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13335 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13336 | fixp->fx_file = fragp->fr_file; | |
13337 | fixp->fx_line = fragp->fr_line; | |
13338 | ||
17a2f251 | 13339 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13340 | buf += 4; |
13341 | } | |
13342 | else | |
13343 | { | |
13344 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13345 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13346 | exp.X_op = O_symbol; | |
13347 | exp.X_add_symbol = fragp->fr_symbol; | |
13348 | exp.X_add_number = fragp->fr_offset; | |
13349 | ||
13350 | if (fragp->fr_offset) | |
13351 | { | |
13352 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13353 | exp.X_add_number = 0; | |
13354 | } | |
13355 | ||
13356 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13357 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13358 | fixp->fx_file = fragp->fr_file; | |
13359 | fixp->fx_line = fragp->fr_line; | |
13360 | ||
17a2f251 | 13361 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13362 | buf += 4; |
b34976b6 | 13363 | |
4a6a3df4 AO |
13364 | if (mips_opts.isa == ISA_MIPS1) |
13365 | { | |
13366 | /* nop */ | |
17a2f251 | 13367 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13368 | buf += 4; |
13369 | } | |
13370 | ||
13371 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13372 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13373 | ||
13374 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13375 | 4, &exp, 0, BFD_RELOC_LO16); | |
13376 | fixp->fx_file = fragp->fr_file; | |
13377 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13378 | |
17a2f251 | 13379 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13380 | buf += 4; |
13381 | ||
13382 | /* j(al)r $at. */ | |
13383 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13384 | insn = 0x0020f809; | |
13385 | else | |
13386 | insn = 0x00200008; | |
13387 | ||
17a2f251 | 13388 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13389 | buf += 4; |
13390 | } | |
13391 | } | |
13392 | ||
13393 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13394 | + fragp->fr_fix + fragp->fr_var); | |
13395 | ||
13396 | fragp->fr_fix += fragp->fr_var; | |
13397 | ||
13398 | return; | |
13399 | } | |
13400 | ||
252b5132 RH |
13401 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13402 | { | |
13403 | int type; | |
13404 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13405 | bfd_boolean small, ext; |
252b5132 RH |
13406 | offsetT val; |
13407 | bfd_byte *buf; | |
13408 | unsigned long insn; | |
b34976b6 | 13409 | bfd_boolean use_extend; |
252b5132 RH |
13410 | unsigned short extend; |
13411 | ||
13412 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13413 | op = mips16_immed_operands; | |
13414 | while (op->type != type) | |
13415 | ++op; | |
13416 | ||
13417 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13418 | { | |
b34976b6 AM |
13419 | small = FALSE; |
13420 | ext = TRUE; | |
252b5132 RH |
13421 | } |
13422 | else | |
13423 | { | |
b34976b6 AM |
13424 | small = TRUE; |
13425 | ext = FALSE; | |
252b5132 RH |
13426 | } |
13427 | ||
6386f3a7 | 13428 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13429 | val = S_GET_VALUE (fragp->fr_symbol); |
13430 | if (op->pcrel) | |
13431 | { | |
13432 | addressT addr; | |
13433 | ||
13434 | addr = fragp->fr_address + fragp->fr_fix; | |
13435 | ||
13436 | /* The rules for the base address of a PC relative reloc are | |
13437 | complicated; see mips16_extended_frag. */ | |
13438 | if (type == 'p' || type == 'q') | |
13439 | { | |
13440 | addr += 2; | |
13441 | if (ext) | |
13442 | addr += 2; | |
13443 | /* Ignore the low bit in the target, since it will be | |
13444 | set for a text label. */ | |
13445 | if ((val & 1) != 0) | |
13446 | --val; | |
13447 | } | |
13448 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13449 | addr -= 4; | |
13450 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13451 | addr -= 2; | |
13452 | ||
13453 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13454 | val -= addr; | |
13455 | ||
13456 | /* Make sure the section winds up with the alignment we have | |
13457 | assumed. */ | |
13458 | if (op->shift > 0) | |
13459 | record_alignment (asec, op->shift); | |
13460 | } | |
13461 | ||
13462 | if (ext | |
13463 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13464 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13465 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13466 | _("extended instruction in delay slot")); | |
13467 | ||
13468 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13469 | ||
13470 | if (target_big_endian) | |
13471 | insn = bfd_getb16 (buf); | |
13472 | else | |
13473 | insn = bfd_getl16 (buf); | |
13474 | ||
13475 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13476 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13477 | small, ext, &insn, &use_extend, &extend); | |
13478 | ||
13479 | if (use_extend) | |
13480 | { | |
17a2f251 | 13481 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13482 | fragp->fr_fix += 2; |
13483 | buf += 2; | |
13484 | } | |
13485 | ||
17a2f251 | 13486 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13487 | fragp->fr_fix += 2; |
13488 | buf += 2; | |
13489 | } | |
13490 | else | |
13491 | { | |
4d7206a2 RS |
13492 | int first, second; |
13493 | fixS *fixp; | |
252b5132 | 13494 | |
4d7206a2 RS |
13495 | first = RELAX_FIRST (fragp->fr_subtype); |
13496 | second = RELAX_SECOND (fragp->fr_subtype); | |
13497 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13498 | |
584892a6 RS |
13499 | /* Possibly emit a warning if we've chosen the longer option. */ |
13500 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13501 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13502 | { | |
13503 | const char *msg = macro_warning (fragp->fr_subtype); | |
13504 | if (msg != 0) | |
13505 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13506 | } | |
13507 | ||
4d7206a2 RS |
13508 | /* Go through all the fixups for the first sequence. Disable them |
13509 | (by marking them as done) if we're going to use the second | |
13510 | sequence instead. */ | |
13511 | while (fixp | |
13512 | && fixp->fx_frag == fragp | |
13513 | && fixp->fx_where < fragp->fr_fix - second) | |
13514 | { | |
13515 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13516 | fixp->fx_done = 1; | |
13517 | fixp = fixp->fx_next; | |
13518 | } | |
252b5132 | 13519 | |
4d7206a2 RS |
13520 | /* Go through the fixups for the second sequence. Disable them if |
13521 | we're going to use the first sequence, otherwise adjust their | |
13522 | addresses to account for the relaxation. */ | |
13523 | while (fixp && fixp->fx_frag == fragp) | |
13524 | { | |
13525 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13526 | fixp->fx_where -= first; | |
13527 | else | |
13528 | fixp->fx_done = 1; | |
13529 | fixp = fixp->fx_next; | |
13530 | } | |
13531 | ||
13532 | /* Now modify the frag contents. */ | |
13533 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13534 | { | |
13535 | char *start; | |
13536 | ||
13537 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13538 | memmove (start, start + first, second); | |
13539 | fragp->fr_fix -= first; | |
13540 | } | |
13541 | else | |
13542 | fragp->fr_fix -= second; | |
252b5132 RH |
13543 | } |
13544 | } | |
13545 | ||
13546 | #ifdef OBJ_ELF | |
13547 | ||
13548 | /* This function is called after the relocs have been generated. | |
13549 | We've been storing mips16 text labels as odd. Here we convert them | |
13550 | back to even for the convenience of the debugger. */ | |
13551 | ||
13552 | void | |
17a2f251 | 13553 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13554 | { |
13555 | asymbol **syms; | |
13556 | unsigned int count, i; | |
13557 | ||
13558 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13559 | return; | |
13560 | ||
13561 | syms = bfd_get_outsymbols (stdoutput); | |
13562 | count = bfd_get_symcount (stdoutput); | |
13563 | for (i = 0; i < count; i++, syms++) | |
13564 | { | |
13565 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13566 | && ((*syms)->value & 1) != 0) | |
13567 | { | |
13568 | (*syms)->value &= ~1; | |
13569 | /* If the symbol has an odd size, it was probably computed | |
13570 | incorrectly, so adjust that as well. */ | |
13571 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13572 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13573 | } | |
13574 | } | |
13575 | } | |
13576 | ||
13577 | #endif | |
13578 | ||
13579 | /* This function is called whenever a label is defined. It is used | |
13580 | when handling branch delays; if a branch has a label, we assume we | |
13581 | can not move it. */ | |
13582 | ||
13583 | void | |
17a2f251 | 13584 | mips_define_label (symbolS *sym) |
252b5132 RH |
13585 | { |
13586 | struct insn_label_list *l; | |
13587 | ||
13588 | if (free_insn_labels == NULL) | |
13589 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13590 | else | |
13591 | { | |
13592 | l = free_insn_labels; | |
13593 | free_insn_labels = l->next; | |
13594 | } | |
13595 | ||
13596 | l->label = sym; | |
13597 | l->next = insn_labels; | |
13598 | insn_labels = l; | |
13599 | } | |
13600 | \f | |
13601 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13602 | ||
13603 | /* Some special processing for a MIPS ELF file. */ | |
13604 | ||
13605 | void | |
17a2f251 | 13606 | mips_elf_final_processing (void) |
252b5132 RH |
13607 | { |
13608 | /* Write out the register information. */ | |
316f5878 | 13609 | if (mips_abi != N64_ABI) |
252b5132 RH |
13610 | { |
13611 | Elf32_RegInfo s; | |
13612 | ||
13613 | s.ri_gprmask = mips_gprmask; | |
13614 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13615 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13616 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13617 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13618 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13619 | ||
13620 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13621 | ((Elf32_External_RegInfo *) | |
13622 | mips_regmask_frag)); | |
13623 | } | |
13624 | else | |
13625 | { | |
13626 | Elf64_Internal_RegInfo s; | |
13627 | ||
13628 | s.ri_gprmask = mips_gprmask; | |
13629 | s.ri_pad = 0; | |
13630 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13631 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13632 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13633 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13634 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13635 | ||
13636 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13637 | ((Elf64_External_RegInfo *) | |
13638 | mips_regmask_frag)); | |
13639 | } | |
13640 | ||
13641 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13642 | sort of BFD interface for this. */ | |
13643 | if (mips_any_noreorder) | |
13644 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13645 | if (mips_pic != NO_PIC) | |
143d77c5 | 13646 | { |
252b5132 | 13647 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13648 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13649 | } | |
13650 | if (mips_abicalls) | |
13651 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13652 | |
98d3f06f | 13653 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13654 | if (file_ase_mips16) |
13655 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13656 | #if 0 /* XXX FIXME */ |
13657 | if (file_ase_mips3d) | |
13658 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13659 | #endif | |
deec1734 CD |
13660 | if (file_ase_mdmx) |
13661 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13662 | |
bdaaa2e1 | 13663 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13664 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13665 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13666 | else if (mips_abi == O64_ABI) |
252b5132 | 13667 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13668 | else if (mips_abi == EABI_ABI) |
252b5132 | 13669 | { |
316f5878 | 13670 | if (!file_mips_gp32) |
252b5132 RH |
13671 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13672 | else | |
13673 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13674 | } | |
316f5878 | 13675 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13676 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13677 | ||
c9914766 | 13678 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13679 | |
13680 | if (mips_32bitmode) | |
13681 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13682 | } | |
13683 | ||
13684 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13685 | \f | |
beae10d5 KH |
13686 | typedef struct proc { |
13687 | symbolS *isym; | |
13688 | unsigned long reg_mask; | |
13689 | unsigned long reg_offset; | |
13690 | unsigned long fpreg_mask; | |
13691 | unsigned long fpreg_offset; | |
13692 | unsigned long frame_offset; | |
13693 | unsigned long frame_reg; | |
13694 | unsigned long pc_reg; | |
13695 | } procS; | |
252b5132 RH |
13696 | |
13697 | static procS cur_proc; | |
13698 | static procS *cur_proc_ptr; | |
13699 | static int numprocs; | |
13700 | ||
0a9ef439 | 13701 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13702 | |
0a9ef439 | 13703 | void |
17a2f251 | 13704 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13705 | { |
0a9ef439 RH |
13706 | if (fragp->fr_type != rs_align_code) |
13707 | return; | |
13708 | ||
13709 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13710 | { |
13711 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13712 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13713 | ||
0a9ef439 RH |
13714 | int bytes; |
13715 | char *p; | |
a19d8eb0 | 13716 | |
0a9ef439 RH |
13717 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13718 | p = fragp->fr_literal + fragp->fr_fix; | |
13719 | ||
13720 | if (bytes & 1) | |
13721 | { | |
13722 | *p++ = 0; | |
f9419b05 | 13723 | fragp->fr_fix++; |
0a9ef439 RH |
13724 | } |
13725 | ||
13726 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13727 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13728 | } |
13729 | ||
0a9ef439 | 13730 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13731 | } |
13732 | ||
252b5132 | 13733 | static void |
17a2f251 | 13734 | md_obj_begin (void) |
252b5132 RH |
13735 | { |
13736 | } | |
13737 | ||
13738 | static void | |
17a2f251 | 13739 | md_obj_end (void) |
252b5132 RH |
13740 | { |
13741 | /* check for premature end, nesting errors, etc */ | |
13742 | if (cur_proc_ptr) | |
9a41af64 | 13743 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13744 | } |
13745 | ||
13746 | static long | |
17a2f251 | 13747 | get_number (void) |
252b5132 RH |
13748 | { |
13749 | int negative = 0; | |
13750 | long val = 0; | |
13751 | ||
13752 | if (*input_line_pointer == '-') | |
13753 | { | |
13754 | ++input_line_pointer; | |
13755 | negative = 1; | |
13756 | } | |
3882b010 | 13757 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13758 | as_bad (_("expected simple number")); |
252b5132 RH |
13759 | if (input_line_pointer[0] == '0') |
13760 | { | |
13761 | if (input_line_pointer[1] == 'x') | |
13762 | { | |
13763 | input_line_pointer += 2; | |
3882b010 | 13764 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13765 | { |
13766 | val <<= 4; | |
13767 | val |= hex_value (*input_line_pointer++); | |
13768 | } | |
13769 | return negative ? -val : val; | |
13770 | } | |
13771 | else | |
13772 | { | |
13773 | ++input_line_pointer; | |
3882b010 | 13774 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13775 | { |
13776 | val <<= 3; | |
13777 | val |= *input_line_pointer++ - '0'; | |
13778 | } | |
13779 | return negative ? -val : val; | |
13780 | } | |
13781 | } | |
3882b010 | 13782 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13783 | { |
13784 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13785 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13786 | as_warn (_("invalid number")); |
252b5132 RH |
13787 | return -1; |
13788 | } | |
3882b010 | 13789 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13790 | { |
13791 | val *= 10; | |
13792 | val += *input_line_pointer++ - '0'; | |
13793 | } | |
13794 | return negative ? -val : val; | |
13795 | } | |
13796 | ||
13797 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13798 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13799 | case .file implies DWARF-2. */ | |
13800 | ||
13801 | static void | |
17a2f251 | 13802 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13803 | { |
ecb4347a DJ |
13804 | static int first_file_directive = 0; |
13805 | ||
c5dd6aab DJ |
13806 | if (ECOFF_DEBUGGING) |
13807 | { | |
13808 | get_number (); | |
13809 | s_app_file (0); | |
13810 | } | |
13811 | else | |
ecb4347a DJ |
13812 | { |
13813 | char *filename; | |
13814 | ||
13815 | filename = dwarf2_directive_file (0); | |
13816 | ||
13817 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13818 | directive even for stabs output. Make sure that this | |
13819 | ".file" is handled. Note that you need a version of GCC | |
13820 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13821 | if (filename != NULL && ! first_file_directive) | |
13822 | { | |
13823 | (void) new_logical_line (filename, -1); | |
13824 | s_app_file_string (filename); | |
13825 | } | |
13826 | first_file_directive = 1; | |
13827 | } | |
c5dd6aab DJ |
13828 | } |
13829 | ||
13830 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13831 | |
13832 | static void | |
17a2f251 | 13833 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13834 | { |
c5dd6aab DJ |
13835 | if (!ECOFF_DEBUGGING) |
13836 | dwarf2_directive_loc (0); | |
252b5132 RH |
13837 | } |
13838 | ||
252b5132 RH |
13839 | /* The .end directive. */ |
13840 | ||
13841 | static void | |
17a2f251 | 13842 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13843 | { |
13844 | symbolS *p; | |
252b5132 | 13845 | |
7a621144 DJ |
13846 | /* Following functions need their own .frame and .cprestore directives. */ |
13847 | mips_frame_reg_valid = 0; | |
13848 | mips_cprestore_valid = 0; | |
13849 | ||
252b5132 RH |
13850 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13851 | { | |
13852 | p = get_symbol (); | |
13853 | demand_empty_rest_of_line (); | |
13854 | } | |
13855 | else | |
13856 | p = NULL; | |
13857 | ||
14949570 | 13858 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13859 | as_warn (_(".end not in text section")); |
13860 | ||
13861 | if (!cur_proc_ptr) | |
13862 | { | |
13863 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13864 | demand_empty_rest_of_line (); | |
13865 | return; | |
13866 | } | |
13867 | ||
13868 | if (p != NULL) | |
13869 | { | |
13870 | assert (S_GET_NAME (p)); | |
13871 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13872 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13873 | |
13874 | if (debug_type == DEBUG_STABS) | |
13875 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13876 | S_GET_NAME (p)); | |
252b5132 RH |
13877 | } |
13878 | else | |
13879 | as_warn (_(".end directive missing or unknown symbol")); | |
13880 | ||
ecb4347a DJ |
13881 | #ifdef OBJ_ELF |
13882 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13883 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13884 | && mips_flag_pdr) | |
ecb4347a DJ |
13885 | { |
13886 | segT saved_seg = now_seg; | |
13887 | subsegT saved_subseg = now_subseg; | |
13888 | valueT dot; | |
13889 | expressionS exp; | |
13890 | char *fragp; | |
252b5132 | 13891 | |
ecb4347a | 13892 | dot = frag_now_fix (); |
252b5132 RH |
13893 | |
13894 | #ifdef md_flush_pending_output | |
ecb4347a | 13895 | md_flush_pending_output (); |
252b5132 RH |
13896 | #endif |
13897 | ||
ecb4347a DJ |
13898 | assert (pdr_seg); |
13899 | subseg_set (pdr_seg, 0); | |
252b5132 | 13900 | |
ecb4347a DJ |
13901 | /* Write the symbol. */ |
13902 | exp.X_op = O_symbol; | |
13903 | exp.X_add_symbol = p; | |
13904 | exp.X_add_number = 0; | |
13905 | emit_expr (&exp, 4); | |
252b5132 | 13906 | |
ecb4347a | 13907 | fragp = frag_more (7 * 4); |
252b5132 | 13908 | |
17a2f251 TS |
13909 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13910 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13911 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13912 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13913 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13914 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13915 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13916 | |
ecb4347a DJ |
13917 | subseg_set (saved_seg, saved_subseg); |
13918 | } | |
13919 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13920 | |
13921 | cur_proc_ptr = NULL; | |
13922 | } | |
13923 | ||
13924 | /* The .aent and .ent directives. */ | |
13925 | ||
13926 | static void | |
17a2f251 | 13927 | s_mips_ent (int aent) |
252b5132 | 13928 | { |
252b5132 | 13929 | symbolS *symbolP; |
252b5132 RH |
13930 | |
13931 | symbolP = get_symbol (); | |
13932 | if (*input_line_pointer == ',') | |
f9419b05 | 13933 | ++input_line_pointer; |
252b5132 | 13934 | SKIP_WHITESPACE (); |
3882b010 | 13935 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13936 | || *input_line_pointer == '-') |
874e8986 | 13937 | get_number (); |
252b5132 | 13938 | |
14949570 | 13939 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13940 | as_warn (_(".ent or .aent not in text section.")); |
13941 | ||
13942 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13943 | as_warn (_("missing .end")); |
252b5132 RH |
13944 | |
13945 | if (!aent) | |
13946 | { | |
7a621144 DJ |
13947 | /* This function needs its own .frame and .cprestore directives. */ |
13948 | mips_frame_reg_valid = 0; | |
13949 | mips_cprestore_valid = 0; | |
13950 | ||
252b5132 RH |
13951 | cur_proc_ptr = &cur_proc; |
13952 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13953 | ||
13954 | cur_proc_ptr->isym = symbolP; | |
13955 | ||
49309057 | 13956 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13957 | |
f9419b05 | 13958 | ++numprocs; |
ecb4347a DJ |
13959 | |
13960 | if (debug_type == DEBUG_STABS) | |
13961 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13962 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13963 | } |
13964 | ||
13965 | demand_empty_rest_of_line (); | |
13966 | } | |
13967 | ||
13968 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13969 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13970 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13971 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13972 | symbol table (in the mdebug section). */ |
13973 | ||
13974 | static void | |
17a2f251 | 13975 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13976 | { |
ecb4347a DJ |
13977 | #ifdef OBJ_ELF |
13978 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13979 | { | |
13980 | long val; | |
252b5132 | 13981 | |
ecb4347a DJ |
13982 | if (cur_proc_ptr == (procS *) NULL) |
13983 | { | |
13984 | as_warn (_(".frame outside of .ent")); | |
13985 | demand_empty_rest_of_line (); | |
13986 | return; | |
13987 | } | |
252b5132 | 13988 | |
ecb4347a DJ |
13989 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13990 | ||
13991 | SKIP_WHITESPACE (); | |
13992 | if (*input_line_pointer++ != ',' | |
13993 | || get_absolute_expression_and_terminator (&val) != ',') | |
13994 | { | |
13995 | as_warn (_("Bad .frame directive")); | |
13996 | --input_line_pointer; | |
13997 | demand_empty_rest_of_line (); | |
13998 | return; | |
13999 | } | |
252b5132 | 14000 | |
ecb4347a DJ |
14001 | cur_proc_ptr->frame_offset = val; |
14002 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14003 | |
252b5132 | 14004 | demand_empty_rest_of_line (); |
252b5132 | 14005 | } |
ecb4347a DJ |
14006 | else |
14007 | #endif /* OBJ_ELF */ | |
14008 | s_ignore (ignore); | |
252b5132 RH |
14009 | } |
14010 | ||
bdaaa2e1 KH |
14011 | /* The .fmask and .mask directives. If the mdebug section is present |
14012 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14013 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14014 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14015 | make reference to the ecoff symbol table (in the mdebug section). */ |
14016 | ||
14017 | static void | |
17a2f251 | 14018 | s_mips_mask (int reg_type) |
252b5132 | 14019 | { |
ecb4347a DJ |
14020 | #ifdef OBJ_ELF |
14021 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14022 | { |
ecb4347a | 14023 | long mask, off; |
252b5132 | 14024 | |
ecb4347a DJ |
14025 | if (cur_proc_ptr == (procS *) NULL) |
14026 | { | |
14027 | as_warn (_(".mask/.fmask outside of .ent")); | |
14028 | demand_empty_rest_of_line (); | |
14029 | return; | |
14030 | } | |
252b5132 | 14031 | |
ecb4347a DJ |
14032 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14033 | { | |
14034 | as_warn (_("Bad .mask/.fmask directive")); | |
14035 | --input_line_pointer; | |
14036 | demand_empty_rest_of_line (); | |
14037 | return; | |
14038 | } | |
252b5132 | 14039 | |
ecb4347a DJ |
14040 | off = get_absolute_expression (); |
14041 | ||
14042 | if (reg_type == 'F') | |
14043 | { | |
14044 | cur_proc_ptr->fpreg_mask = mask; | |
14045 | cur_proc_ptr->fpreg_offset = off; | |
14046 | } | |
14047 | else | |
14048 | { | |
14049 | cur_proc_ptr->reg_mask = mask; | |
14050 | cur_proc_ptr->reg_offset = off; | |
14051 | } | |
14052 | ||
14053 | demand_empty_rest_of_line (); | |
252b5132 RH |
14054 | } |
14055 | else | |
ecb4347a DJ |
14056 | #endif /* OBJ_ELF */ |
14057 | s_ignore (reg_type); | |
252b5132 RH |
14058 | } |
14059 | ||
14060 | /* The .loc directive. */ | |
14061 | ||
14062 | #if 0 | |
14063 | static void | |
17a2f251 | 14064 | s_loc (int x) |
252b5132 RH |
14065 | { |
14066 | symbolS *symbolP; | |
14067 | int lineno; | |
14068 | int addroff; | |
14069 | ||
14070 | assert (now_seg == text_section); | |
14071 | ||
14072 | lineno = get_number (); | |
14073 | addroff = frag_now_fix (); | |
14074 | ||
14075 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14076 | S_SET_TYPE (symbolP, N_SLINE); | |
14077 | S_SET_OTHER (symbolP, 0); | |
14078 | S_SET_DESC (symbolP, lineno); | |
14079 | symbolP->sy_segment = now_seg; | |
14080 | } | |
14081 | #endif | |
e7af610e | 14082 | |
316f5878 RS |
14083 | /* A table describing all the processors gas knows about. Names are |
14084 | matched in the order listed. | |
e7af610e | 14085 | |
316f5878 RS |
14086 | To ease comparison, please keep this table in the same order as |
14087 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14088 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14089 | { | |
316f5878 RS |
14090 | /* Entries for generic ISAs */ |
14091 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14092 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14093 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14094 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14095 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14096 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14097 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 14098 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 14099 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
14100 | |
14101 | /* MIPS I */ | |
14102 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14103 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14104 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14105 | ||
14106 | /* MIPS II */ | |
14107 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14108 | ||
14109 | /* MIPS III */ | |
14110 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14111 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14112 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14113 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14114 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14115 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14116 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14117 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14118 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14119 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14120 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14121 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14122 | ||
14123 | /* MIPS IV */ | |
14124 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14125 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14126 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14127 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14128 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14129 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14130 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14131 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14132 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14133 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14134 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
14135 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
14136 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
14137 | |
14138 | /* MIPS 32 */ | |
fef14a42 | 14139 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14140 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14141 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14142 | |
316f5878 RS |
14143 | /* MIPS 64 */ |
14144 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14145 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14146 | |
c7a23324 | 14147 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14148 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14149 | |
316f5878 RS |
14150 | /* End marker */ |
14151 | { NULL, 0, 0, 0 } | |
14152 | }; | |
e7af610e | 14153 | |
84ea6cf2 | 14154 | |
316f5878 RS |
14155 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14156 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14157 | |
316f5878 | 14158 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14159 | |
b34976b6 | 14160 | static bfd_boolean |
17a2f251 | 14161 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14162 | { |
14163 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14164 | given++, canonical++; | |
14165 | ||
14166 | return ((*given == 0 && *canonical == 0) | |
14167 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14168 | } | |
14169 | ||
14170 | ||
14171 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14172 | CPU name. We've traditionally allowed a lot of variation here. | |
14173 | ||
14174 | Note: this function is shared between GCC and GAS. */ | |
14175 | ||
b34976b6 | 14176 | static bfd_boolean |
17a2f251 | 14177 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14178 | { |
14179 | /* First see if the name matches exactly, or with a final "000" | |
14180 | turned into "k". */ | |
14181 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14182 | return TRUE; |
316f5878 RS |
14183 | |
14184 | /* If not, try comparing based on numerical designation alone. | |
14185 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14186 | if (TOLOWER (*given) == 'r') | |
14187 | given++; | |
14188 | if (!ISDIGIT (*given)) | |
b34976b6 | 14189 | return FALSE; |
316f5878 RS |
14190 | |
14191 | /* Skip over some well-known prefixes in the canonical name, | |
14192 | hoping to find a number there too. */ | |
14193 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14194 | canonical += 2; | |
14195 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14196 | canonical += 2; | |
14197 | else if (TOLOWER (canonical[0]) == 'r') | |
14198 | canonical += 1; | |
14199 | ||
14200 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14201 | } | |
14202 | ||
14203 | ||
14204 | /* Parse an option that takes the name of a processor as its argument. | |
14205 | OPTION is the name of the option and CPU_STRING is the argument. | |
14206 | Return the corresponding processor enumeration if the CPU_STRING is | |
14207 | recognized, otherwise report an error and return null. | |
14208 | ||
14209 | A similar function exists in GCC. */ | |
e7af610e NC |
14210 | |
14211 | static const struct mips_cpu_info * | |
17a2f251 | 14212 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14213 | { |
316f5878 | 14214 | const struct mips_cpu_info *p; |
e7af610e | 14215 | |
316f5878 RS |
14216 | /* 'from-abi' selects the most compatible architecture for the given |
14217 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14218 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14219 | version. Look first at the -mgp options, if given, otherwise base | |
14220 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14221 | |
316f5878 RS |
14222 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14223 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14224 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14225 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14226 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14227 | { | |
14228 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14229 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14230 | ||
14231 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14232 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14233 | ||
14234 | if (file_mips_gp32 >= 0) | |
14235 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14236 | ||
14237 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14238 | ? ISA_MIPS3 | |
14239 | : ISA_MIPS1); | |
14240 | } | |
14241 | ||
14242 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14243 | if (strcasecmp (cpu_string, "default") == 0) | |
14244 | return 0; | |
14245 | ||
14246 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14247 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14248 | return p; | |
14249 | ||
14250 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14251 | return 0; | |
e7af610e NC |
14252 | } |
14253 | ||
316f5878 RS |
14254 | /* Return the canonical processor information for ISA (a member of the |
14255 | ISA_MIPS* enumeration). */ | |
14256 | ||
e7af610e | 14257 | static const struct mips_cpu_info * |
17a2f251 | 14258 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14259 | { |
14260 | int i; | |
14261 | ||
14262 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14263 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14264 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14265 | return (&mips_cpu_info_table[i]); |
14266 | ||
e972090a | 14267 | return NULL; |
e7af610e | 14268 | } |
fef14a42 TS |
14269 | |
14270 | static const struct mips_cpu_info * | |
17a2f251 | 14271 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14272 | { |
14273 | int i; | |
14274 | ||
14275 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14276 | if (arch == mips_cpu_info_table[i].cpu) | |
14277 | return (&mips_cpu_info_table[i]); | |
14278 | ||
14279 | return NULL; | |
14280 | } | |
316f5878 RS |
14281 | \f |
14282 | static void | |
17a2f251 | 14283 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14284 | { |
14285 | if (*first_p) | |
14286 | { | |
14287 | fprintf (stream, "%24s", ""); | |
14288 | *col_p = 24; | |
14289 | } | |
14290 | else | |
14291 | { | |
14292 | fprintf (stream, ", "); | |
14293 | *col_p += 2; | |
14294 | } | |
e7af610e | 14295 | |
316f5878 RS |
14296 | if (*col_p + strlen (string) > 72) |
14297 | { | |
14298 | fprintf (stream, "\n%24s", ""); | |
14299 | *col_p = 24; | |
14300 | } | |
14301 | ||
14302 | fprintf (stream, "%s", string); | |
14303 | *col_p += strlen (string); | |
14304 | ||
14305 | *first_p = 0; | |
14306 | } | |
14307 | ||
14308 | void | |
17a2f251 | 14309 | md_show_usage (FILE *stream) |
e7af610e | 14310 | { |
316f5878 RS |
14311 | int column, first; |
14312 | size_t i; | |
14313 | ||
14314 | fprintf (stream, _("\ | |
14315 | MIPS options:\n\ | |
14316 | -membedded-pic generate embedded position independent code\n\ | |
14317 | -EB generate big endian output\n\ | |
14318 | -EL generate little endian output\n\ | |
14319 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14320 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14321 | implicitly with the gp register [default 8]\n")); | |
14322 | fprintf (stream, _("\ | |
14323 | -mips1 generate MIPS ISA I instructions\n\ | |
14324 | -mips2 generate MIPS ISA II instructions\n\ | |
14325 | -mips3 generate MIPS ISA III instructions\n\ | |
14326 | -mips4 generate MIPS ISA IV instructions\n\ | |
14327 | -mips5 generate MIPS ISA V instructions\n\ | |
14328 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14329 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14330 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14331 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14332 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14333 | ||
14334 | first = 1; | |
e7af610e NC |
14335 | |
14336 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14337 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14338 | show (stream, "from-abi", &column, &first); | |
14339 | fputc ('\n', stream); | |
e7af610e | 14340 | |
316f5878 RS |
14341 | fprintf (stream, _("\ |
14342 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14343 | -no-mCPU don't generate code specific to CPU.\n\ | |
14344 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14345 | ||
14346 | first = 1; | |
14347 | ||
14348 | show (stream, "3900", &column, &first); | |
14349 | show (stream, "4010", &column, &first); | |
14350 | show (stream, "4100", &column, &first); | |
14351 | show (stream, "4650", &column, &first); | |
14352 | fputc ('\n', stream); | |
14353 | ||
14354 | fprintf (stream, _("\ | |
14355 | -mips16 generate mips16 instructions\n\ | |
14356 | -no-mips16 do not generate mips16 instructions\n")); | |
14357 | fprintf (stream, _("\ | |
14358 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14359 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14360 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14361 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14362 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14363 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14364 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14365 | #ifdef OBJ_ELF | |
14366 | fprintf (stream, _("\ | |
14367 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14368 | -non_shared do not generate position independent code\n\ | |
14369 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14370 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14371 | -mabi=ABI create ABI conformant object file for:\n")); |
14372 | ||
14373 | first = 1; | |
14374 | ||
14375 | show (stream, "32", &column, &first); | |
14376 | show (stream, "o64", &column, &first); | |
14377 | show (stream, "n32", &column, &first); | |
14378 | show (stream, "64", &column, &first); | |
14379 | show (stream, "eabi", &column, &first); | |
14380 | ||
14381 | fputc ('\n', stream); | |
14382 | ||
14383 | fprintf (stream, _("\ | |
14384 | -32 create o32 ABI object file (default)\n\ | |
14385 | -n32 create n32 ABI object file\n\ | |
14386 | -64 create 64 ABI object file\n")); | |
14387 | #endif | |
e7af610e | 14388 | } |
14e777e0 KB |
14389 | |
14390 | enum dwarf2_format | |
17a2f251 | 14391 | mips_dwarf2_format (void) |
14e777e0 KB |
14392 | { |
14393 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14394 | { |
14395 | #ifdef TE_IRIX | |
14396 | return dwarf2_format_64bit_irix; | |
14397 | #else | |
14398 | return dwarf2_format_64bit; | |
14399 | #endif | |
14400 | } | |
14e777e0 KB |
14401 | else |
14402 | return dwarf2_format_32bit; | |
14403 | } |