Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
276c2d7d GRK |
151 | /* start-sanitize-r5900 */ |
152 | /* Whether Toshiba r5900 instructions are permitted. */ | |
153 | static int mips_5900 = -1; | |
154 | /* end-sanitize-r5900 */ | |
155 | ||
e532b44c ILT |
156 | /* Whether the processor uses hardware interlocks, and thus does not |
157 | require nops to be inserted. */ | |
158 | static int interlocks = -1; | |
159 | ||
344a8d61 JSC |
160 | /* As with "interlocks" this is used by hardware that has FP |
161 | (co-processor) interlocks. */ | |
162 | static int cop_interlocks = -1; | |
163 | ||
d9aba805 ILT |
164 | /* MIPS PIC level. */ |
165 | ||
166 | enum mips_pic_level | |
167 | { | |
168 | /* Do not generate PIC code. */ | |
169 | NO_PIC, | |
170 | ||
171 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
172 | not sure what it is supposed to do. */ | |
173 | IRIX4_PIC, | |
174 | ||
175 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
176 | SVR4_PIC, | |
177 | ||
178 | /* Generate PIC code without using a global offset table: the data | |
179 | segment has a maximum size of 64K, all data references are off | |
180 | the $gp register, and all text references are PC relative. This | |
181 | is used on some embedded systems. */ | |
182 | EMBEDDED_PIC | |
183 | }; | |
184 | ||
185 | static enum mips_pic_level mips_pic; | |
9226253a | 186 | |
fb251650 ILT |
187 | /* 1 if we should generate 32 bit offsets from the GP register in |
188 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
189 | static int mips_big_got; | |
190 | ||
8ea7f4e8 ILT |
191 | /* 1 if trap instructions should used for overflow rather than break |
192 | instructions. */ | |
193 | static int mips_trap; | |
194 | ||
cc5703cd ILT |
195 | /* 1 if we should autoextend mips16 instructions. */ |
196 | static int mips16_autoextend = 1; | |
197 | ||
3d3c5039 ILT |
198 | static int mips_warn_about_macros; |
199 | static int mips_noreorder; | |
0dd2d296 | 200 | static int mips_any_noreorder; |
3d3c5039 ILT |
201 | static int mips_nomove; |
202 | static int mips_noat; | |
203 | static int mips_nobopt; | |
204 | ||
670a50eb ILT |
205 | /* The size of the small data section. */ |
206 | static int g_switch_value = 8; | |
42562568 ILT |
207 | /* Whether the -G option was used. */ |
208 | static int g_switch_seen = 0; | |
670a50eb | 209 | |
3d3c5039 ILT |
210 | #define N_RMASK 0xc4 |
211 | #define N_VFP 0xd4 | |
212 | ||
d8a1c247 KR |
213 | /* If we can determine in advance that GP optimization won't be |
214 | possible, we can skip the relaxation stuff that tries to produce | |
215 | GP-relative references. This makes delay slot optimization work | |
216 | better. | |
217 | ||
218 | This function can only provide a guess, but it seems to work for | |
219 | gcc output. If it guesses wrong, the only loss should be in | |
220 | efficiency; it shouldn't introduce any bugs. | |
221 | ||
222 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
223 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
224 | static int nopic_need_relax PARAMS ((symbolS *)); | |
225 | ||
3d3c5039 ILT |
226 | /* handle of the OPCODE hash table */ |
227 | static struct hash_control *op_hash = NULL; | |
228 | ||
cc5703cd ILT |
229 | /* The opcode hash table we use for the mips16. */ |
230 | static struct hash_control *mips16_op_hash = NULL; | |
231 | ||
3d3c5039 ILT |
232 | /* This array holds the chars that always start a comment. If the |
233 | pre-processor is disabled, these aren't very useful */ | |
234 | const char comment_chars[] = "#"; | |
235 | ||
236 | /* This array holds the chars that only start a comment at the beginning of | |
237 | a line. If the line seems to have the form '# 123 filename' | |
238 | .line and .file directives will appear in the pre-processed output */ | |
239 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
240 | first line of the input file. This is because the compiler outputs | |
241 | #NO_APP at the beginning of its output. */ | |
242 | /* Also note that C style comments are always supported. */ | |
243 | const char line_comment_chars[] = "#"; | |
244 | ||
245 | /* This array holds machine specific line separator characters. */ | |
246 | const char line_separator_chars[] = ""; | |
247 | ||
248 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
249 | const char EXP_CHARS[] = "eE"; | |
250 | ||
251 | /* Chars that mean this number is a floating point constant */ | |
252 | /* As in 0f12.456 */ | |
253 | /* or 0d1.2345e12 */ | |
254 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
255 | ||
256 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
257 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
258 | but nothing is ideal around here. | |
259 | */ | |
260 | ||
670a50eb | 261 | static char *insn_error; |
3d3c5039 | 262 | |
3d3c5039 | 263 | static int auto_align = 1; |
becfe05e | 264 | |
9226253a ILT |
265 | /* When outputting SVR4 PIC code, the assembler needs to know the |
266 | offset in the stack frame from which to restore the $gp register. | |
267 | This is set by the .cprestore pseudo-op, and saved in this | |
268 | variable. */ | |
0dd2d296 ILT |
269 | static offsetT mips_cprestore_offset = -1; |
270 | ||
271 | /* This is the register which holds the stack frame, as set by the | |
272 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
273 | static int mips_frame_reg = SP; | |
9226253a | 274 | |
becfe05e ILT |
275 | /* To output NOP instructions correctly, we need to keep information |
276 | about the previous two instructions. */ | |
277 | ||
0aa07269 ILT |
278 | /* Whether we are optimizing. The default value of 2 means to remove |
279 | unneeded NOPs and swap branch instructions when possible. A value | |
280 | of 1 means to not swap branches. A value of 0 means to always | |
281 | insert NOPs. */ | |
282 | static int mips_optimize = 2; | |
4e95866e | 283 | |
22ba90ce ILT |
284 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
285 | equivalent to seeing no -g option at all. */ | |
286 | static int mips_debug = 0; | |
287 | ||
becfe05e ILT |
288 | /* The previous instruction. */ |
289 | static struct mips_cl_insn prev_insn; | |
290 | ||
291 | /* The instruction before prev_insn. */ | |
292 | static struct mips_cl_insn prev_prev_insn; | |
293 | ||
294 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
295 | point the insn_mo field at this dummy integer. */ | |
296 | static const struct mips_opcode dummy_opcode = { 0 }; | |
297 | ||
298 | /* Non-zero if prev_insn is valid. */ | |
299 | static int prev_insn_valid; | |
300 | ||
301 | /* The frag for the previous instruction. */ | |
302 | static struct frag *prev_insn_frag; | |
303 | ||
304 | /* The offset into prev_insn_frag for the previous instruction. */ | |
305 | static long prev_insn_where; | |
306 | ||
a677feeb ILT |
307 | /* The reloc type for the previous instruction, if any. */ |
308 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
309 | ||
becfe05e ILT |
310 | /* The reloc for the previous instruction, if any. */ |
311 | static fixS *prev_insn_fixp; | |
312 | ||
313 | /* Non-zero if the previous instruction was in a delay slot. */ | |
314 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
315 | |
316 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
317 | static int prev_insn_unreordered; | |
318 | ||
cc5703cd ILT |
319 | /* Non-zero if the previous instruction uses an extend opcode (if |
320 | mips16). */ | |
321 | static int prev_insn_extended; | |
322 | ||
4e95866e ILT |
323 | /* Non-zero if the previous previous instruction was in a .set |
324 | noreorder. */ | |
325 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
326 | |
327 | /* For ECOFF and ELF, relocations against symbols are done in two | |
328 | parts, with a HI relocation and a LO relocation. Each relocation | |
329 | has only 16 bits of space to store an addend. This means that in | |
330 | order for the linker to handle carries correctly, it must be able | |
331 | to locate both the HI and the LO relocation. This means that the | |
332 | relocations must appear in order in the relocation table. | |
333 | ||
334 | In order to implement this, we keep track of each unmatched HI | |
335 | relocation. We then sort them so that they immediately precede the | |
336 | corresponding LO relocation. */ | |
337 | ||
338 | struct mips_hi_fixup | |
339 | { | |
340 | /* Next HI fixup. */ | |
341 | struct mips_hi_fixup *next; | |
342 | /* This fixup. */ | |
343 | fixS *fixp; | |
344 | /* The section this fixup is in. */ | |
345 | segT seg; | |
346 | }; | |
347 | ||
348 | /* The list of unmatched HI relocs. */ | |
349 | ||
350 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
351 | |
352 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
353 | ||
354 | #define X ILLEGAL_REG | |
355 | static const int mips32_to_16_reg_map[] = | |
356 | { | |
357 | X, X, 2, 3, 4, 5, 6, 7, | |
358 | X, X, X, X, X, X, X, X, | |
359 | 0, 1, X, X, X, X, X, X, | |
360 | X, X, X, X, X, X, X, X | |
361 | }; | |
362 | #undef X | |
363 | ||
364 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
365 | ||
366 | static const int mips16_to_32_reg_map[] = | |
367 | { | |
368 | 16, 17, 2, 3, 4, 5, 6, 7 | |
369 | }; | |
3d3c5039 | 370 | \f |
0dd2d296 ILT |
371 | /* Since the MIPS does not have multiple forms of PC relative |
372 | instructions, we do not have to do relaxing as is done on other | |
373 | platforms. However, we do have to handle GP relative addressing | |
374 | correctly, which turns out to be a similar problem. | |
375 | ||
376 | Every macro that refers to a symbol can occur in (at least) two | |
377 | forms, one with GP relative addressing and one without. For | |
378 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 379 | a macro instruction like this: |
0dd2d296 ILT |
380 | lw $4,i |
381 | If i can be addressed off the GP register (this is true if it is in | |
382 | the .sbss or .sdata section, or if it is known to be smaller than | |
383 | the -G argument) this will generate the following instruction: | |
384 | lw $4,i($gp) | |
385 | This instruction will use a GPREL reloc. If i can not be addressed | |
386 | off the GP register, the following instruction sequence will be used: | |
387 | lui $at,i | |
388 | lw $4,i($at) | |
389 | In this case the first instruction will have a HI16 reloc, and the | |
390 | second reloc will have a LO16 reloc. Both relocs will be against | |
391 | the symbol i. | |
392 | ||
393 | The issue here is that we may not know whether i is GP addressable | |
394 | until after we see the instruction that uses it. Therefore, we | |
395 | want to be able to choose the final instruction sequence only at | |
396 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 397 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
398 | end of assembly. |
399 | ||
400 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
401 | addressing in quite the same way, but the issue still arises as |
402 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
403 | |
404 | We handle these issues by actually generating both possible | |
405 | instruction sequences. The longer one is put in a frag_var with | |
406 | type rs_machine_dependent. We encode what to do with the frag in | |
407 | the subtype field. We encode (1) the number of existing bytes to | |
408 | replace, (2) the number of new bytes to use, (3) the offset from | |
409 | the start of the existing bytes to the first reloc we must generate | |
410 | (that is, the offset is applied from the start of the existing | |
411 | bytes after they are replaced by the new bytes, if any), (4) the | |
412 | offset from the start of the existing bytes to the second reloc, | |
413 | (5) whether a third reloc is needed (the third reloc is always four | |
414 | bytes after the second reloc), and (6) whether to warn if this | |
415 | variant is used (this is sometimes needed if .set nomacro or .set | |
416 | noat is in effect). All these numbers are reasonably small. | |
417 | ||
418 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
419 | ensure that delay slots are handled correctly. Fortunately, there |
420 | are a limited number of cases. When the second instruction | |
421 | sequence is generated, append_insn is directed to maintain the | |
422 | existing delay slot information, so it continues to apply to any | |
423 | code after the second instruction sequence. This means that the | |
424 | second instruction sequence must not impose any requirements not | |
425 | required by the first instruction sequence. | |
0dd2d296 ILT |
426 | |
427 | These variant frags are then handled in functions called by the | |
428 | machine independent code. md_estimate_size_before_relax returns | |
429 | the final size of the frag. md_convert_frag sets up the final form | |
430 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
431 | one if needed. */ | |
432 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
433 | ((relax_substateT) \ | |
cc5703cd | 434 | (((old) << 23) \ |
0dd2d296 ILT |
435 | | ((new) << 16) \ |
436 | | (((reloc1) + 64) << 9) \ | |
437 | | (((reloc2) + 64) << 2) \ | |
438 | | ((reloc3) ? (1 << 1) : 0) \ | |
439 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
440 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
441 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
442 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
443 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
444 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
445 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
446 | |
447 | /* For mips16 code, we use an entirely different form of relaxation. | |
448 | mips16 supports two versions of most instructions which take | |
449 | immediate values: a small one which takes some small value, and a | |
450 | larger one which takes a 16 bit value. Since branches also follow | |
451 | this pattern, relaxing these values is required. | |
452 | ||
453 | We can assemble both mips16 and normal MIPS code in a single | |
454 | object. Therefore, we need to support this type of relaxation at | |
455 | the same time that we support the relaxation described above. We | |
456 | use the high bit of the subtype field to distinguish these cases. | |
457 | ||
a677feeb ILT |
458 | The information we store for this type of relaxation is the |
459 | argument code found in the opcode file for this relocation, whether | |
460 | the user explicitly requested a small or extended form, and whether | |
461 | the relocation is in a jump or jal delay slot. That tells us the | |
462 | size of the value, and how it should be stored. We also store | |
463 | whether the fragment is considered to be extended or not. We also | |
464 | store whether this is known to be a branch to a different section, | |
465 | whether we have tried to relax this frag yet, and whether we have | |
466 | ever extended a PC relative fragment because of a shift count. */ | |
467 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
468 | (0x80000000 \ | |
469 | | ((type) & 0xff) \ | |
470 | | ((small) ? 0x100 : 0) \ | |
471 | | ((ext) ? 0x200 : 0) \ | |
472 | | ((dslot) ? 0x400 : 0) \ | |
473 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
474 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
475 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
476 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
477 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
478 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
479 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
480 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
481 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
482 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
483 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
484 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
485 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 486 | \f |
3d3c5039 ILT |
487 | /* Prototypes for static functions. */ |
488 | ||
489 | #ifdef __STDC__ | |
490 | #define internalError() \ | |
491 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
492 | #else | |
493 | #define internalError() as_fatal ("MIPS internal Error"); | |
494 | #endif | |
495 | ||
cc5703cd ILT |
496 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
497 | ||
becfe05e | 498 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 499 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 500 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
501 | static void append_insn PARAMS ((char *place, |
502 | struct mips_cl_insn * ip, | |
670a50eb | 503 | expressionS * p, |
867a58b3 ILT |
504 | bfd_reloc_code_real_type r, |
505 | boolean)); | |
becfe05e | 506 | static void mips_no_prev_insn PARAMS ((void)); |
fbcfacb7 | 507 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 508 | #ifdef USE_STDARG |
0dd2d296 | 509 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
510 | const char *name, const char *fmt, |
511 | ...)); | |
c625fc23 JSC |
512 | #else |
513 | static void macro_build (); | |
514 | #endif | |
cc5703cd ILT |
515 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
516 | const char *, const char *, | |
517 | va_list)); | |
0dd2d296 ILT |
518 | static void macro_build_lui PARAMS ((char *place, int *counter, |
519 | expressionS * ep, int regnum)); | |
6e8dda9c | 520 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 521 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 522 | expressionS *)); |
d8a1c247 | 523 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 524 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 525 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 526 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
527 | #ifdef LOSING_COMPILER |
528 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
529 | #endif | |
670a50eb | 530 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 531 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
532 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
533 | boolean, boolean, unsigned long *, | |
534 | boolean *, unsigned short *)); | |
670a50eb ILT |
535 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
536 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 537 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 538 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
539 | static void s_align PARAMS ((int)); |
540 | static void s_change_sec PARAMS ((int)); | |
541 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 542 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 543 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
544 | static void s_option PARAMS ((int)); |
545 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
546 | static void s_abicalls PARAMS ((int)); |
547 | static void s_cpload PARAMS ((int)); | |
548 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
549 | static void s_gpword PARAMS ((int)); |
550 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
551 | static void md_obj_begin PARAMS ((void)); |
552 | static void md_obj_end PARAMS ((void)); | |
553 | static long get_number PARAMS ((void)); | |
554 | static void s_ent PARAMS ((int)); | |
555 | static void s_mipsend PARAMS ((int)); | |
556 | static void s_file PARAMS ((int)); | |
cc5703cd | 557 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
558 | \f |
559 | /* Pseudo-op table. | |
560 | ||
561 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
562 | should be defined here, but are currently unsupported: .alias, | |
563 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
564 | ||
565 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
566 | specific to the type of debugging information being generated, and | |
567 | should be defined by the object format: .aent, .begin, .bend, | |
568 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
569 | .vreg. | |
570 | ||
571 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
572 | not MIPS CPU specific, but are also not specific to the object file | |
573 | format. This file is probably the best place to define them, but | |
574 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
575 | .struct, .weakext. */ | |
576 | ||
739708fa | 577 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 578 | { |
670a50eb ILT |
579 | /* MIPS specific pseudo-ops. */ |
580 | {"option", s_option, 0}, | |
581 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
582 | {"rdata", s_change_sec, 'r'}, |
583 | {"sdata", s_change_sec, 's'}, | |
584 | {"livereg", s_ignore, 0}, | |
739708fa KR |
585 | {"abicalls", s_abicalls, 0}, |
586 | {"cpload", s_cpload, 0}, | |
587 | {"cprestore", s_cprestore, 0}, | |
588 | {"gpword", s_gpword, 0}, | |
589 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 590 | |
670a50eb | 591 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 592 | chips. */ |
739708fa | 593 | {"asciiz", stringer, 1}, |
670a50eb ILT |
594 | {"bss", s_change_sec, 'b'}, |
595 | {"err", s_err, 0}, | |
596 | {"half", s_cons, 1}, | |
52aa70b5 | 597 | {"dword", s_cons, 3}, |
3d3c5039 | 598 | |
670a50eb | 599 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 600 | here for one reason or another. */ |
670a50eb ILT |
601 | {"align", s_align, 0}, |
602 | {"byte", s_cons, 0}, | |
603 | {"data", s_change_sec, 'd'}, | |
becfe05e | 604 | {"double", s_float_cons, 'd'}, |
becfe05e | 605 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
606 | {"globl", s_mips_globl, 0}, |
607 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
608 | {"hword", s_cons, 1}, |
609 | {"int", s_cons, 2}, | |
610 | {"long", s_cons, 2}, | |
611 | {"octa", s_cons, 4}, | |
612 | {"quad", s_cons, 3}, | |
613 | {"short", s_cons, 1}, | |
614 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
615 | {"text", s_change_sec, 't'}, |
616 | {"word", s_cons, 2}, | |
739708fa KR |
617 | { 0 }, |
618 | }; | |
3d3c5039 | 619 | |
739708fa | 620 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 621 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 622 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 623 | {"aent", s_ent, 1}, |
9226253a | 624 | {"bgnb", s_ignore, 0}, |
670a50eb | 625 | {"end", s_mipsend, 0}, |
9226253a | 626 | {"endb", s_ignore, 0}, |
670a50eb ILT |
627 | {"ent", s_ent, 0}, |
628 | {"file", s_file, 0}, | |
629 | {"fmask", s_ignore, 'F'}, | |
630 | {"frame", s_ignore, 0}, | |
631 | {"loc", s_ignore, 0}, | |
632 | {"mask", s_ignore, 'R'}, | |
633 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
634 | { 0 }, |
635 | }; | |
61420a20 | 636 | |
739708fa KR |
637 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
638 | ||
639 | void | |
640 | mips_pop_insert () | |
641 | { | |
642 | pop_insert (mips_pseudo_table); | |
643 | if (! ECOFF_DEBUGGING) | |
644 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 645 | } |
3d3c5039 | 646 | \f |
fbcfacb7 ILT |
647 | /* Symbols labelling the current insn. */ |
648 | ||
649 | struct insn_label_list | |
650 | { | |
651 | struct insn_label_list *next; | |
652 | symbolS *label; | |
653 | }; | |
654 | ||
655 | static struct insn_label_list *insn_labels; | |
656 | static struct insn_label_list *free_insn_labels; | |
657 | ||
658 | static void mips_clear_insn_labels PARAMS ((void)); | |
659 | ||
660 | static inline void | |
661 | mips_clear_insn_labels () | |
662 | { | |
663 | register struct insn_label_list **pl; | |
664 | ||
665 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
666 | ; | |
667 | *pl = insn_labels; | |
668 | insn_labels = NULL; | |
669 | } | |
670 | \f | |
3d3c5039 ILT |
671 | static char *expr_end; |
672 | ||
867a58b3 ILT |
673 | /* Expressions which appear in instructions. These are set by |
674 | mips_ip. */ | |
675 | ||
3d3c5039 ILT |
676 | static expressionS imm_expr; |
677 | static expressionS offset_expr; | |
867a58b3 ILT |
678 | |
679 | /* Relocs associated with imm_expr and offset_expr. */ | |
680 | ||
3d3c5039 ILT |
681 | static bfd_reloc_code_real_type imm_reloc; |
682 | static bfd_reloc_code_real_type offset_reloc; | |
683 | ||
867a58b3 ILT |
684 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
685 | ||
686 | static boolean imm_unmatched_hi; | |
687 | ||
8728fa92 ILT |
688 | /* These are set by mips16_ip if an explicit extension is used. */ |
689 | ||
690 | static boolean mips16_small, mips16_ext; | |
691 | ||
3d3c5039 ILT |
692 | /* |
693 | * This function is called once, at assembler startup time. It should | |
694 | * set up all the tables, etc. that the MD part of the assembler will need. | |
695 | */ | |
696 | void | |
670a50eb | 697 | md_begin () |
3d3c5039 | 698 | { |
0dd2d296 | 699 | boolean ok = false; |
604633ae | 700 | register const char *retval = NULL; |
670a50eb | 701 | register unsigned int i = 0; |
3d3c5039 | 702 | |
8358c818 ILT |
703 | if (mips_isa == -1) |
704 | { | |
8c63448a ILT |
705 | const char *cpu; |
706 | char *a = NULL; | |
707 | ||
708 | cpu = TARGET_CPU; | |
709 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
710 | { | |
711 | a = xmalloc (sizeof TARGET_CPU); | |
712 | strcpy (a, TARGET_CPU); | |
713 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
714 | cpu = a; | |
715 | } | |
716 | ||
717 | if (strcmp (cpu, "mips") == 0) | |
718 | { | |
719 | mips_isa = 1; | |
4bb0cc41 ILT |
720 | if (mips_cpu == -1) |
721 | mips_cpu = 3000; | |
8c63448a ILT |
722 | } |
723 | else if (strcmp (cpu, "r6000") == 0 | |
724 | || strcmp (cpu, "mips2") == 0) | |
725 | { | |
726 | mips_isa = 2; | |
4bb0cc41 ILT |
727 | if (mips_cpu == -1) |
728 | mips_cpu = 6000; | |
8c63448a ILT |
729 | } |
730 | else if (strcmp (cpu, "mips64") == 0 | |
731 | || strcmp (cpu, "r4000") == 0 | |
732 | || strcmp (cpu, "mips3") == 0) | |
733 | { | |
734 | mips_isa = 3; | |
4bb0cc41 ILT |
735 | if (mips_cpu == -1) |
736 | mips_cpu = 4000; | |
8c63448a ILT |
737 | } |
738 | else if (strcmp (cpu, "r4400") == 0) | |
739 | { | |
740 | mips_isa = 3; | |
4bb0cc41 ILT |
741 | if (mips_cpu == -1) |
742 | mips_cpu = 4400; | |
8c63448a ILT |
743 | } |
744 | else if (strcmp (cpu, "mips64orion") == 0 | |
745 | || strcmp (cpu, "r4600") == 0) | |
746 | { | |
747 | mips_isa = 3; | |
4bb0cc41 ILT |
748 | if (mips_cpu == -1) |
749 | mips_cpu = 4600; | |
8c63448a | 750 | } |
b2b8c24e ILT |
751 | else if (strcmp (cpu, "r4650") == 0) |
752 | { | |
753 | mips_isa = 3; | |
754 | if (mips_cpu == -1) | |
755 | mips_cpu = 4650; | |
756 | if (mips_4650 == -1) | |
757 | mips_4650 = 1; | |
758 | } | |
c625fc23 JSC |
759 | else if (strcmp (cpu, "mips64vr4300") == 0) |
760 | { | |
761 | mips_isa = 3; | |
762 | if (mips_cpu == -1) | |
763 | mips_cpu = 4300; | |
764 | } | |
765 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
766 | { | |
767 | mips_isa = 3; | |
768 | if (mips_cpu == -1) | |
769 | mips_cpu = 4100; | |
770 | if (mips_4100 == -1) | |
771 | mips_4100 = 1; | |
772 | } | |
e532b44c ILT |
773 | else if (strcmp (cpu, "r4010") == 0) |
774 | { | |
775 | mips_isa = 2; | |
776 | if (mips_cpu == -1) | |
777 | mips_cpu = 4010; | |
778 | if (mips_4010 == -1) | |
779 | mips_4010 = 1; | |
780 | } | |
517078c1 ILT |
781 | else if (strcmp (cpu, "r5000") == 0 |
782 | || strcmp (cpu, "mips64vr5000") == 0) | |
783 | { | |
784 | mips_isa = 4; | |
785 | if (mips_cpu == -1) | |
786 | mips_cpu = 5000; | |
787 | } | |
276c2d7d GRK |
788 | /* start-sanitize-r5900 */ |
789 | else if (strcmp (cpu, "r5900") == 0 | |
790 | || strcmp (cpu, "mips64vr5900") == 0 | |
791 | || strcmp (cpu, "mips64vr5900el") == 0) | |
792 | { | |
793 | mips_isa = 3; | |
794 | if (mips_cpu == -1) | |
795 | mips_cpu = 5900; | |
16262668 | 796 | if (mips_5900 == -1) |
276c2d7d GRK |
797 | mips_5900 = 1; |
798 | } | |
799 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
800 | else if (strcmp (cpu, "r8000") == 0 |
801 | || strcmp (cpu, "mips4") == 0) | |
802 | { | |
803 | mips_isa = 4; | |
804 | if (mips_cpu == -1) | |
805 | mips_cpu = 8000; | |
806 | } | |
807 | else if (strcmp (cpu, "r10000") == 0) | |
808 | { | |
809 | mips_isa = 4; | |
810 | if (mips_cpu == -1) | |
811 | mips_cpu = 10000; | |
812 | } | |
cc5703cd ILT |
813 | else if (strcmp (cpu, "mips16") == 0) |
814 | { | |
815 | mips_isa = 3; | |
816 | if (mips_cpu == -1) | |
817 | mips_cpu = 0; /* FIXME */ | |
818 | } | |
8358c818 | 819 | else |
8c63448a ILT |
820 | { |
821 | mips_isa = 1; | |
4bb0cc41 ILT |
822 | if (mips_cpu == -1) |
823 | mips_cpu = 3000; | |
8c63448a ILT |
824 | } |
825 | ||
826 | if (a != NULL) | |
827 | free (a); | |
8358c818 ILT |
828 | } |
829 | ||
cc5703cd ILT |
830 | if (mips16 < 0) |
831 | { | |
832 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
833 | mips16 = 1; | |
834 | else | |
835 | mips16 = 0; | |
836 | } | |
837 | ||
b2b8c24e ILT |
838 | if (mips_4650 < 0) |
839 | mips_4650 = 0; | |
840 | ||
e532b44c ILT |
841 | if (mips_4010 < 0) |
842 | mips_4010 = 0; | |
843 | ||
c625fc23 JSC |
844 | if (mips_4100 < 0) |
845 | mips_4100 = 0; | |
846 | ||
276c2d7d GRK |
847 | /* start-sanitize-r5900 */ |
848 | if (mips_5900 < 0) | |
849 | mips_5900 = 0; | |
850 | /* end-sanitize-r5900 */ | |
851 | ||
c36a90ef | 852 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
853 | interlocks = 1; |
854 | else | |
855 | interlocks = 0; | |
856 | ||
ca296aab | 857 | if (mips_cpu == 4300) |
344a8d61 JSC |
858 | cop_interlocks = 1; |
859 | else | |
860 | cop_interlocks = 0; | |
861 | ||
8ea7f4e8 ILT |
862 | if (mips_isa < 2 && mips_trap) |
863 | as_bad ("trap exception not supported at ISA 1"); | |
864 | ||
97f99d11 ILT |
865 | switch (mips_isa) |
866 | { | |
867 | case 1: | |
868 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
869 | break; | |
870 | case 2: | |
871 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
872 | break; | |
873 | case 3: | |
874 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
875 | break; | |
d8a1c247 KR |
876 | case 4: |
877 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
878 | break; | |
97f99d11 ILT |
879 | } |
880 | if (! ok) | |
881 | as_warn ("Could not set architecture and machine"); | |
882 | ||
1051c97f ILT |
883 | file_mips_isa = mips_isa; |
884 | ||
13fe1379 ILT |
885 | op_hash = hash_new (); |
886 | ||
670a50eb ILT |
887 | for (i = 0; i < NUMOPCODES;) |
888 | { | |
889 | const char *name = mips_opcodes[i].name; | |
890 | ||
604633ae | 891 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 892 | if (retval != NULL) |
670a50eb ILT |
893 | { |
894 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
895 | mips_opcodes[i].name, retval); | |
896 | as_fatal ("Broken assembler. No assembly attempted."); | |
897 | } | |
898 | do | |
899 | { | |
8358c818 ILT |
900 | if (mips_opcodes[i].pinfo != INSN_MACRO |
901 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
902 | != mips_opcodes[i].match)) | |
670a50eb ILT |
903 | { |
904 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
905 | mips_opcodes[i].name, mips_opcodes[i].args); | |
906 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 907 | } |
670a50eb ILT |
908 | ++i; |
909 | } | |
910 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
911 | } |
912 | ||
cc5703cd ILT |
913 | mips16_op_hash = hash_new (); |
914 | ||
915 | i = 0; | |
916 | while (i < bfd_mips16_num_opcodes) | |
917 | { | |
918 | const char *name = mips16_opcodes[i].name; | |
919 | ||
920 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
921 | if (retval != NULL) | |
922 | as_fatal ("internal error: can't hash `%s': %s\n", | |
923 | mips16_opcodes[i].name, retval); | |
924 | do | |
925 | { | |
926 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
927 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
928 | != mips16_opcodes[i].match)) | |
929 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
930 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
931 | ++i; | |
932 | } | |
933 | while (i < bfd_mips16_num_opcodes | |
934 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
935 | } | |
936 | ||
ebf28372 ILT |
937 | /* We add all the general register names to the symbol table. This |
938 | helps us detect invalid uses of them. */ | |
939 | for (i = 0; i < 32; i++) | |
940 | { | |
941 | char buf[5]; | |
942 | ||
943 | sprintf (buf, "$%d", i); | |
944 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
945 | &zero_address_frag)); | |
946 | } | |
947 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
948 | &zero_address_frag)); | |
949 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
950 | &zero_address_frag)); | |
951 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
952 | &zero_address_frag)); | |
953 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
954 | &zero_address_frag)); | |
955 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
956 | &zero_address_frag)); | |
957 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
958 | &zero_address_frag)); | |
959 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
960 | &zero_address_frag)); | |
961 | ||
becfe05e ILT |
962 | mips_no_prev_insn (); |
963 | ||
1aa6938e ILT |
964 | mips_gprmask = 0; |
965 | mips_cprmask[0] = 0; | |
966 | mips_cprmask[1] = 0; | |
967 | mips_cprmask[2] = 0; | |
968 | mips_cprmask[3] = 0; | |
969 | ||
8358c818 | 970 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 971 | record_alignment (text_section, 2); |
8358c818 | 972 | |
1dc1e798 KR |
973 | if (USE_GLOBAL_POINTER_OPT) |
974 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 975 | |
1dc1e798 KR |
976 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
977 | { | |
08e17202 ILT |
978 | /* On a native system, sections must be aligned to 16 byte |
979 | boundaries. When configured for an embedded ELF target, we | |
980 | don't bother. */ | |
981 | if (strcmp (TARGET_OS, "elf") != 0) | |
982 | { | |
983 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
984 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
985 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
986 | } | |
1dc1e798 KR |
987 | |
988 | /* Create a .reginfo section for register masks and a .mdebug | |
989 | section for debugging information. */ | |
990 | { | |
991 | segT seg; | |
992 | subsegT subseg; | |
b3a64736 | 993 | flagword flags; |
1dc1e798 KR |
994 | segT sec; |
995 | ||
996 | seg = now_seg; | |
997 | subseg = now_subseg; | |
1dc1e798 | 998 | |
b3a64736 ILT |
999 | /* The ABI says this section should be loaded so that the |
1000 | running program can access it. However, we don't load it | |
1001 | if we are configured for an embedded target */ | |
1002 | flags = SEC_READONLY | SEC_DATA; | |
1003 | if (strcmp (TARGET_OS, "elf") != 0) | |
1004 | flags |= SEC_ALLOC | SEC_LOAD; | |
1005 | ||
87178180 ILT |
1006 | if (! mips_64) |
1007 | { | |
1008 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1009 | |
b3a64736 ILT |
1010 | |
1011 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1012 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1013 | ||
f2a663d3 | 1014 | #ifdef OBJ_ELF |
87178180 | 1015 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1016 | #endif |
87178180 ILT |
1017 | } |
1018 | else | |
1019 | { | |
1020 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1021 | .reginfo section. */ | |
1022 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1023 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1024 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1025 | ||
1026 | #ifdef OBJ_ELF | |
1027 | /* Set up the option header. */ | |
1028 | { | |
1029 | Elf_Internal_Options opthdr; | |
1030 | char *f; | |
1031 | ||
1032 | opthdr.kind = ODK_REGINFO; | |
1033 | opthdr.size = (sizeof (Elf_External_Options) | |
1034 | + sizeof (Elf64_External_RegInfo)); | |
1035 | opthdr.section = 0; | |
1036 | opthdr.info = 0; | |
1037 | f = frag_more (sizeof (Elf_External_Options)); | |
1038 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1039 | (Elf_External_Options *) f); | |
1040 | ||
1041 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1042 | } | |
1043 | #endif | |
1044 | } | |
f2a663d3 | 1045 | |
739708fa KR |
1046 | if (ECOFF_DEBUGGING) |
1047 | { | |
1048 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1049 | (void) bfd_set_section_flags (stdoutput, sec, | |
1050 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1051 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1052 | } | |
0dd2d296 | 1053 | |
1dc1e798 KR |
1054 | subseg_set (seg, subseg); |
1055 | } | |
1056 | } | |
f2a663d3 | 1057 | |
739708fa KR |
1058 | if (! ECOFF_DEBUGGING) |
1059 | md_obj_begin (); | |
3d3c5039 ILT |
1060 | } |
1061 | ||
1062 | void | |
13fe1379 | 1063 | md_mips_end () |
3d3c5039 | 1064 | { |
739708fa KR |
1065 | if (! ECOFF_DEBUGGING) |
1066 | md_obj_end (); | |
3d3c5039 ILT |
1067 | } |
1068 | ||
1069 | void | |
670a50eb ILT |
1070 | md_assemble (str) |
1071 | char *str; | |
3d3c5039 | 1072 | { |
670a50eb | 1073 | struct mips_cl_insn insn; |
3d3c5039 | 1074 | |
5ac34ac3 | 1075 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1076 | imm_reloc = BFD_RELOC_UNUSED; |
1077 | imm_unmatched_hi = false; | |
5ac34ac3 | 1078 | offset_expr.X_op = O_absent; |
867a58b3 | 1079 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1080 | |
cc5703cd ILT |
1081 | if (mips16) |
1082 | mips16_ip (str, &insn); | |
1083 | else | |
1084 | mips_ip (str, &insn); | |
1085 | ||
670a50eb ILT |
1086 | if (insn_error) |
1087 | { | |
1088 | as_bad ("%s `%s'", insn_error, str); | |
1089 | return; | |
1090 | } | |
cc5703cd | 1091 | |
670a50eb ILT |
1092 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1093 | { | |
cc5703cd ILT |
1094 | if (mips16) |
1095 | mips16_macro (&insn); | |
1096 | else | |
1097 | macro (&insn); | |
3d3c5039 | 1098 | } |
670a50eb ILT |
1099 | else |
1100 | { | |
5ac34ac3 | 1101 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1102 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1103 | imm_unmatched_hi); | |
5ac34ac3 | 1104 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1105 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1106 | else |
867a58b3 | 1107 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1108 | } |
1109 | } | |
1110 | ||
cc5703cd ILT |
1111 | /* See whether instruction IP reads register REG. CLASS is the type |
1112 | of register. */ | |
becfe05e ILT |
1113 | |
1114 | static int | |
cc5703cd | 1115 | insn_uses_reg (ip, reg, class) |
becfe05e | 1116 | struct mips_cl_insn *ip; |
604633ae | 1117 | unsigned int reg; |
cc5703cd | 1118 | enum mips_regclass class; |
becfe05e | 1119 | { |
cc5703cd ILT |
1120 | if (class == MIPS16_REG) |
1121 | { | |
1122 | assert (mips16); | |
1123 | reg = mips16_to_32_reg_map[reg]; | |
1124 | class = MIPS_GR_REG; | |
1125 | } | |
1126 | ||
becfe05e | 1127 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1128 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1129 | return 0; |
1130 | ||
cc5703cd | 1131 | if (class == MIPS_FP_REG) |
becfe05e | 1132 | { |
cc5703cd | 1133 | assert (! mips16); |
becfe05e ILT |
1134 | /* If we are called with either $f0 or $f1, we must check $f0. |
1135 | This is not optimal, because it will introduce an unnecessary | |
1136 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1137 | need to distinguish reading both $f0 and $f1 or just one of | |
1138 | them. Note that we don't have to check the other way, | |
1139 | because there is no instruction that sets both $f0 and $f1 | |
1140 | and requires a delay. */ | |
1141 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1142 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1143 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1144 | return 1; |
1145 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1146 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1147 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1148 | return 1; |
1149 | } | |
cc5703cd | 1150 | else if (! mips16) |
becfe05e ILT |
1151 | { |
1152 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1153 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1154 | return 1; | |
1155 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1156 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1157 | return 1; | |
1158 | } | |
cc5703cd ILT |
1159 | else |
1160 | { | |
1161 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1162 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1163 | return 1; | |
1164 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1165 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1166 | return 1; | |
1167 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1168 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1169 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1170 | return 1; | |
1171 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1172 | return 1; | |
1173 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1174 | return 1; | |
1175 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1176 | return 1; | |
1177 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1178 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1179 | & MIPS16OP_MASK_REGR32) == reg) | |
1180 | return 1; | |
1181 | } | |
becfe05e ILT |
1182 | |
1183 | return 0; | |
1184 | } | |
1185 | ||
fb251650 ILT |
1186 | /* This function returns true if modifying a register requires a |
1187 | delay. */ | |
1188 | ||
1189 | static int | |
1190 | reg_needs_delay (reg) | |
1191 | int reg; | |
1192 | { | |
1193 | unsigned long prev_pinfo; | |
1194 | ||
1195 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1196 | if (! mips_noreorder | |
1197 | && mips_isa < 4 | |
1198 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1199 | || (mips_isa < 2 | |
1200 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1201 | { | |
1202 | /* A load from a coprocessor or from memory. All load | |
1203 | delays delay the use of general register rt for one | |
1204 | instruction on the r3000. The r6000 and r4000 use | |
1205 | interlocks. */ | |
1206 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1207 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1208 | return 1; | |
1209 | } | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
0dd2d296 ILT |
1214 | /* Output an instruction. PLACE is where to put the instruction; if |
1215 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1216 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1217 | used with RELOC_TYPE. */ | |
3d3c5039 | 1218 | |
3d3c5039 | 1219 | static void |
867a58b3 | 1220 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1221 | char *place; |
670a50eb ILT |
1222 | struct mips_cl_insn *ip; |
1223 | expressionS *address_expr; | |
1224 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1225 | boolean unmatched_hi; |
3d3c5039 | 1226 | { |
1aa6938e | 1227 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1228 | char *f; |
becfe05e ILT |
1229 | fixS *fixp; |
1230 | int nops = 0; | |
3d3c5039 | 1231 | |
fbcfacb7 ILT |
1232 | /* Mark instruction labels in mips16 mode. This permits the linker |
1233 | to handle them specially, such as generating jalx instructions | |
1234 | when needed. We also make them odd for the duration of the | |
1235 | assembly, in order to generate the right sort of code. We will | |
1236 | make them even in the adjust_symtab routine, while leaving them | |
1237 | marked. This is convenient for the debugger and the | |
1238 | disassembler. The linker knows to make them odd again. */ | |
1239 | if (mips16) | |
1240 | { | |
1241 | struct insn_label_list *l; | |
1242 | ||
1243 | for (l = insn_labels; l != NULL; l = l->next) | |
1244 | { | |
1245 | #ifdef S_SET_OTHER | |
1246 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1247 | S_SET_OTHER (l->label, STO_MIPS16); | |
1248 | #endif | |
1249 | ++l->label->sy_value.X_add_number; | |
1250 | } | |
1251 | } | |
1252 | ||
1aa6938e ILT |
1253 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1254 | pinfo = ip->insn_mo->pinfo; | |
1255 | ||
0dd2d296 | 1256 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1257 | { |
1258 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1259 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1260 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1261 | (1) a load from memory delay |
1262 | (2) a load from a coprocessor delay | |
1263 | (3) an unconditional branch delay | |
1264 | (4) a conditional branch delay | |
1265 | (5) a move to coprocessor register delay | |
1266 | (6) a load coprocessor register from memory delay | |
1267 | (7) a coprocessor condition code delay | |
1268 | (8) a HI/LO special register delay | |
becfe05e ILT |
1269 | |
1270 | There are a lot of optimizations we could do that we don't. | |
1271 | In particular, we do not, in general, reorder instructions. | |
1272 | If you use gcc with optimization, it will reorder | |
1273 | instructions and generally do much more optimization then we | |
1274 | do here; repeating all that work in the assembler would only | |
1275 | benefit hand written assembly code, and does not seem worth | |
1276 | it. */ | |
1277 | ||
1278 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1279 | #define emit_nop() \ |
1280 | (mips16 \ | |
1281 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1282 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1283 | |
1284 | /* The previous insn might require a delay slot, depending upon | |
1285 | the contents of the current insn. */ | |
cc5703cd ILT |
1286 | if (! mips16 |
1287 | && mips_isa < 4 | |
5af96dce ILT |
1288 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1289 | && ! cop_interlocks) | |
d8a1c247 KR |
1290 | || (mips_isa < 2 |
1291 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1292 | { |
1293 | /* A load from a coprocessor or from memory. All load | |
1294 | delays delay the use of general register rt for one | |
1295 | instruction on the r3000. The r6000 and r4000 use | |
1296 | interlocks. */ | |
1aa6938e | 1297 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1298 | if (mips_optimize == 0 |
1299 | || insn_uses_reg (ip, | |
1300 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1301 | & OP_MASK_RT), | |
cc5703cd | 1302 | MIPS_GR_REG)) |
becfe05e ILT |
1303 | ++nops; |
1304 | } | |
cc5703cd ILT |
1305 | else if (! mips16 |
1306 | && mips_isa < 4 | |
5af96dce ILT |
1307 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1308 | && ! cop_interlocks) | |
d8a1c247 KR |
1309 | || (mips_isa < 2 |
1310 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1311 | { |
1312 | /* A generic coprocessor delay. The previous instruction | |
1313 | modified a coprocessor general or control register. If | |
1314 | it modified a control register, we need to avoid any | |
1315 | coprocessor instruction (this is probably not always | |
1316 | required, but it sometimes is). If it modified a general | |
1317 | register, we avoid using that register. | |
1318 | ||
8358c818 ILT |
1319 | On the r6000 and r4000 loading a coprocessor register |
1320 | from memory is interlocked, and does not require a delay. | |
1321 | ||
becfe05e ILT |
1322 | This case is not handled very well. There is no special |
1323 | knowledge of CP0 handling, and the coprocessors other | |
1324 | than the floating point unit are not distinguished at | |
1325 | all. */ | |
1aa6938e | 1326 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1327 | { |
0aa07269 ILT |
1328 | if (mips_optimize == 0 |
1329 | || insn_uses_reg (ip, | |
8358c818 ILT |
1330 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1331 | & OP_MASK_FT), | |
cc5703cd | 1332 | MIPS_FP_REG)) |
becfe05e ILT |
1333 | ++nops; |
1334 | } | |
1aa6938e | 1335 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1336 | { |
0aa07269 ILT |
1337 | if (mips_optimize == 0 |
1338 | || insn_uses_reg (ip, | |
8358c818 ILT |
1339 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1340 | & OP_MASK_FS), | |
cc5703cd | 1341 | MIPS_FP_REG)) |
becfe05e ILT |
1342 | ++nops; |
1343 | } | |
1344 | else | |
1345 | { | |
1346 | /* We don't know exactly what the previous instruction | |
1347 | does. If the current instruction uses a coprocessor | |
1348 | register, we must insert a NOP. If previous | |
1349 | instruction may set the condition codes, and the | |
1350 | current instruction uses them, we must insert two | |
1351 | NOPS. */ | |
0aa07269 | 1352 | if (mips_optimize == 0 |
1aa6938e ILT |
1353 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1354 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1355 | nops += 2; |
1aa6938e | 1356 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1357 | ++nops; |
1358 | } | |
1359 | } | |
cc5703cd ILT |
1360 | else if (! mips16 |
1361 | && mips_isa < 4 | |
344a8d61 JSC |
1362 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1363 | && ! cop_interlocks) | |
becfe05e ILT |
1364 | { |
1365 | /* The previous instruction sets the coprocessor condition | |
1366 | codes, but does not require a general coprocessor delay | |
1367 | (this means it is a floating point comparison | |
1368 | instruction). If this instruction uses the condition | |
1369 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1370 | if (mips_optimize == 0 |
1aa6938e | 1371 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1372 | ++nops; |
1373 | } | |
1aa6938e | 1374 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1375 | { |
1376 | /* The previous instruction reads the LO register; if the | |
1377 | current instruction writes to the LO register, we must | |
517078c1 | 1378 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1379 | if (! interlocks |
b2b8c24e ILT |
1380 | && (mips_optimize == 0 |
1381 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1382 | nops += 2; |
1383 | } | |
1384 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1385 | { | |
1386 | /* The previous instruction reads the HI register; if the | |
1387 | current instruction writes to the HI register, we must | |
517078c1 | 1388 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1389 | if (! interlocks |
b2b8c24e ILT |
1390 | && (mips_optimize == 0 |
1391 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1392 | nops += 2; |
1393 | } | |
1394 | ||
1395 | /* There are two cases which require two intervening | |
1396 | instructions: 1) setting the condition codes using a move to | |
1397 | coprocessor instruction which requires a general coprocessor | |
1398 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1399 | or LO register and then writing to it (except on processors |
1400 | which have interlocks). If we are not already emitting a NOP | |
1401 | instruction, we must check for these cases compared to the | |
1402 | instruction previous to the previous instruction. */ | |
becfe05e | 1403 | if (nops == 0 |
cc5703cd ILT |
1404 | && ((! mips16 |
1405 | && mips_isa < 4 | |
d8a1c247 | 1406 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1407 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1408 | && (pinfo & INSN_READ_COND_CODE) |
1409 | && ! cop_interlocks) | |
becfe05e | 1410 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1411 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1412 | && ! interlocks) |
becfe05e | 1413 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1414 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1415 | && ! interlocks))) |
becfe05e ILT |
1416 | ++nops; |
1417 | ||
0dd2d296 ILT |
1418 | /* If we are being given a nop instruction, don't bother with |
1419 | one of the nops we would otherwise output. This will only | |
1420 | happen when a nop instruction is used with mips_optimize set | |
1421 | to 0. */ | |
cc5703cd | 1422 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1423 | --nops; |
1424 | ||
becfe05e ILT |
1425 | /* Now emit the right number of NOP instructions. */ |
1426 | if (nops > 0) | |
1427 | { | |
5af96dce ILT |
1428 | fragS *old_frag; |
1429 | unsigned long old_frag_offset; | |
8c63448a | 1430 | int i; |
fbcfacb7 | 1431 | struct insn_label_list *l; |
8c63448a | 1432 | |
5af96dce ILT |
1433 | old_frag = frag_now; |
1434 | old_frag_offset = frag_now_fix (); | |
1435 | ||
8c63448a | 1436 | for (i = 0; i < nops; i++) |
becfe05e | 1437 | emit_nop (); |
5af96dce | 1438 | |
af255ca0 | 1439 | if (listing) |
546f5536 ILT |
1440 | { |
1441 | listing_prev_line (); | |
1442 | /* We may be at the start of a variant frag. In case we | |
1443 | are, make sure there is enough space for the frag | |
1444 | after the frags created by listing_prev_line. The | |
1445 | argument to frag_grow here must be at least as large | |
1446 | as the argument to all other calls to frag_grow in | |
1447 | this file. We don't have to worry about being in the | |
1448 | middle of a variant frag, because the variants insert | |
1449 | all needed nop instructions themselves. */ | |
1450 | frag_grow (40); | |
1451 | } | |
5af96dce | 1452 | |
fbcfacb7 | 1453 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1454 | { |
fbcfacb7 ILT |
1455 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1456 | l->label->sy_frag = frag_now; | |
1457 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1458 | /* mips16 text labels are stored as odd. */ | |
1459 | if (mips16) | |
1460 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1461 | } |
5af96dce ILT |
1462 | |
1463 | #ifndef NO_ECOFF_DEBUGGING | |
1464 | if (ECOFF_DEBUGGING) | |
1465 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1466 | #endif | |
becfe05e ILT |
1467 | } |
1468 | } | |
1469 | ||
cc5703cd ILT |
1470 | if (reloc_type > BFD_RELOC_UNUSED) |
1471 | { | |
1472 | /* We need to set up a variant frag. */ | |
1473 | assert (mips16 && address_expr != NULL); | |
1474 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1475 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1476 | mips16_small, mips16_ext, |
1477 | (prev_pinfo | |
1478 | & INSN_UNCOND_BRANCH_DELAY), | |
1479 | (prev_insn_reloc_type | |
1480 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1481 | make_expr_symbol (address_expr), (long) 0, |
1482 | (char *) NULL); | |
1483 | } | |
1484 | else if (place != NULL) | |
0dd2d296 | 1485 | f = place; |
cc5703cd | 1486 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1487 | { |
1488 | /* Make sure there is enough room to swap this instruction with | |
1489 | a following jump instruction. */ | |
1490 | frag_grow (6); | |
1491 | f = frag_more (2); | |
1492 | } | |
cc5703cd ILT |
1493 | else |
1494 | f = frag_more (4); | |
becfe05e | 1495 | fixp = NULL; |
cc5703cd | 1496 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1497 | { |
5ac34ac3 | 1498 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1499 | { |
1500 | switch (reloc_type) | |
1501 | { | |
3d3c5039 | 1502 | case BFD_RELOC_32: |
670a50eb ILT |
1503 | ip->insn_opcode |= address_expr->X_add_number; |
1504 | break; | |
3d3c5039 ILT |
1505 | |
1506 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1507 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1508 | break; | |
3d3c5039 ILT |
1509 | |
1510 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1511 | if ((address_expr->X_add_number & 3) != 0) |
1512 | as_bad ("jump to misaligned address (0x%lx)", | |
1513 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1514 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1515 | break; | |
1516 | ||
cc5703cd | 1517 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1518 | if ((address_expr->X_add_number & 3) != 0) |
1519 | as_bad ("jump to misaligned address (0x%lx)", | |
1520 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1521 | ip->insn_opcode |= |
1522 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1523 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1524 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1525 | break; | |
1526 | ||
3d3c5039 | 1527 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1528 | goto need_reloc; |
3d3c5039 ILT |
1529 | |
1530 | default: | |
670a50eb | 1531 | internalError (); |
3d3c5039 | 1532 | } |
670a50eb ILT |
1533 | } |
1534 | else | |
1535 | { | |
3d3c5039 | 1536 | need_reloc: |
0dd2d296 ILT |
1537 | /* Don't generate a reloc if we are writing into a variant |
1538 | frag. */ | |
1539 | if (place == NULL) | |
867a58b3 ILT |
1540 | { |
1541 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1542 | address_expr, | |
1543 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1544 | reloc_type); | |
1545 | if (unmatched_hi) | |
1546 | { | |
1547 | struct mips_hi_fixup *hi_fixup; | |
1548 | ||
1549 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1550 | hi_fixup = ((struct mips_hi_fixup *) | |
1551 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1552 | hi_fixup->fixp = fixp; | |
1553 | hi_fixup->seg = now_seg; | |
1554 | hi_fixup->next = mips_hi_fixup_list; | |
1555 | mips_hi_fixup_list = hi_fixup; | |
1556 | } | |
1557 | } | |
3d3c5039 ILT |
1558 | } |
1559 | } | |
becfe05e | 1560 | |
16262668 | 1561 | if (! mips16) |
cc5703cd | 1562 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1563 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1564 | { | |
1565 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1566 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1567 | } | |
cc5703cd ILT |
1568 | else |
1569 | { | |
1570 | if (ip->use_extend) | |
1571 | { | |
1572 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1573 | f += 2; | |
1574 | } | |
1575 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1576 | } | |
670a50eb | 1577 | |
1aa6938e | 1578 | /* Update the register mask information. */ |
cc5703cd ILT |
1579 | if (! mips16) |
1580 | { | |
1581 | if (pinfo & INSN_WRITE_GPR_D) | |
1582 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1583 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1584 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1585 | if (pinfo & INSN_READ_GPR_S) | |
1586 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1587 | if (pinfo & INSN_WRITE_GPR_31) | |
1588 | mips_gprmask |= 1 << 31; | |
1589 | if (pinfo & INSN_WRITE_FPR_D) | |
1590 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1591 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1592 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1593 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1594 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1595 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1596 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1597 | if (pinfo & INSN_COP) | |
1598 | { | |
1599 | /* We don't keep enough information to sort these cases out. */ | |
1600 | } | |
1601 | /* Never set the bit for $0, which is always zero. */ | |
1602 | mips_gprmask &=~ 1 << 0; | |
1603 | } | |
1604 | else | |
1aa6938e | 1605 | { |
cc5703cd ILT |
1606 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1607 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1608 | & MIPS16OP_MASK_RX); | |
1609 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1610 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1611 | & MIPS16OP_MASK_RY); | |
1612 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1613 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1614 | & MIPS16OP_MASK_RZ); | |
1615 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1616 | mips_gprmask |= 1 << TREG; | |
1617 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1618 | mips_gprmask |= 1 << SP; | |
1619 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1620 | mips_gprmask |= 1 << RA; | |
1621 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1622 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1623 | if (pinfo & MIPS16_INSN_READ_Z) | |
1624 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1625 | & MIPS16OP_MASK_MOVE32Z); | |
1626 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1627 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1628 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1629 | } |
1aa6938e | 1630 | |
0dd2d296 | 1631 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1632 | { |
becfe05e ILT |
1633 | /* Filling the branch delay slot is more complex. We try to |
1634 | switch the branch with the previous instruction, which we can | |
1635 | do if the previous instruction does not set up a condition | |
1636 | that the branch tests and if the branch is not itself the | |
1637 | target of any branch. */ | |
1aa6938e ILT |
1638 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1639 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1640 | { |
0aa07269 | 1641 | if (mips_optimize < 2 |
19ed8960 ILT |
1642 | /* If we have seen .set volatile or .set nomove, don't |
1643 | optimize. */ | |
1644 | || mips_nomove != 0 | |
4e95866e ILT |
1645 | /* If we had to emit any NOP instructions, then we |
1646 | already know we can not swap. */ | |
1647 | || nops != 0 | |
becfe05e ILT |
1648 | /* If we don't even know the previous insn, we can not |
1649 | swap. */ | |
1650 | || ! prev_insn_valid | |
1651 | /* If the previous insn is already in a branch delay | |
1652 | slot, then we can not swap. */ | |
1653 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1654 | /* If the previous previous insn was in a .set |
1655 | noreorder, we can't swap. Actually, the MIPS | |
1656 | assembler will swap in this situation. However, gcc | |
1657 | configured -with-gnu-as will generate code like | |
1658 | .set noreorder | |
1659 | lw $4,XXX | |
1660 | .set reorder | |
1661 | INSN | |
1662 | bne $4,$0,foo | |
1663 | in which we can not swap the bne and INSN. If gcc is | |
1664 | not configured -with-gnu-as, it does not output the | |
1665 | .set pseudo-ops. We don't have to check | |
1666 | prev_insn_unreordered, because prev_insn_valid will | |
1667 | be 0 in that case. We don't want to use | |
1668 | prev_prev_insn_valid, because we do want to be able | |
1669 | to swap at the start of a function. */ | |
1670 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1671 | /* If the branch is itself the target of a branch, we |
1672 | can not swap. We cheat on this; all we check for is | |
1673 | whether there is a label on this instruction. If | |
1674 | there are any branches to anything other than a | |
1675 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1676 | || insn_labels != NULL |
777ad64d | 1677 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1678 | can not do the swap. This does not apply to the |
1679 | mips16, which uses variant frags for different | |
1680 | purposes. */ | |
1681 | || (! mips16 | |
1682 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1683 | /* If the branch reads the condition codes, we don't |
1684 | even try to swap, because in the sequence | |
1685 | ctc1 $X,$31 | |
1686 | INSN | |
1687 | INSN | |
1688 | bc1t LABEL | |
1689 | we can not swap, and I don't feel like handling that | |
1690 | case. */ | |
cc5703cd ILT |
1691 | || (! mips16 |
1692 | && mips_isa < 4 | |
d8a1c247 | 1693 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1694 | /* We can not swap with an instruction that requires a |
1695 | delay slot, becase the target of the branch might | |
1696 | interfere with that instruction. */ | |
cc5703cd ILT |
1697 | || (! mips16 |
1698 | && mips_isa < 4 | |
d8a1c247 KR |
1699 | && (prev_pinfo |
1700 | & (INSN_LOAD_COPROC_DELAY | |
1701 | | INSN_COPROC_MOVE_DELAY | |
1702 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1703 | || (! interlocks |
b2b8c24e ILT |
1704 | && (prev_pinfo |
1705 | & (INSN_READ_LO | |
1706 | | INSN_READ_HI))) | |
cc5703cd ILT |
1707 | || (! mips16 |
1708 | && mips_isa < 2 | |
1aa6938e | 1709 | && (prev_pinfo |
8358c818 ILT |
1710 | & (INSN_LOAD_MEMORY_DELAY |
1711 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1712 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1713 | || (prev_pinfo |
6e8dda9c ILT |
1714 | & (INSN_UNCOND_BRANCH_DELAY |
1715 | | INSN_COND_BRANCH_DELAY | |
1716 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1717 | /* We do not swap with a trap instruction, since it |
1718 | complicates trap handlers to have the trap | |
1719 | instruction be in a delay slot. */ | |
1aa6938e | 1720 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1721 | /* If the branch reads a register that the previous |
1722 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1723 | || (! mips16 |
1724 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1725 | && insn_uses_reg (ip, |
1726 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1727 | & OP_MASK_RT), | |
cc5703cd ILT |
1728 | MIPS_GR_REG)) |
1729 | || (! mips16 | |
1730 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1731 | && insn_uses_reg (ip, |
1732 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1733 | & OP_MASK_RD), | |
cc5703cd ILT |
1734 | MIPS_GR_REG)) |
1735 | || (mips16 | |
1736 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1737 | && insn_uses_reg (ip, | |
1738 | ((prev_insn.insn_opcode | |
1739 | >> MIPS16OP_SH_RX) | |
1740 | & MIPS16OP_MASK_RX), | |
1741 | MIPS16_REG)) | |
1742 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1743 | && insn_uses_reg (ip, | |
1744 | ((prev_insn.insn_opcode | |
1745 | >> MIPS16OP_SH_RY) | |
1746 | & MIPS16OP_MASK_RY), | |
1747 | MIPS16_REG)) | |
1748 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1749 | && insn_uses_reg (ip, | |
1750 | ((prev_insn.insn_opcode | |
1751 | >> MIPS16OP_SH_RZ) | |
1752 | & MIPS16OP_MASK_RZ), | |
1753 | MIPS16_REG)) | |
1754 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1755 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1756 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1757 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1758 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1759 | && insn_uses_reg (ip, | |
1760 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1761 | insn_opcode), | |
1762 | MIPS_GR_REG)))) | |
1849d646 ILT |
1763 | /* If the branch writes a register that the previous |
1764 | instruction sets, we can not swap (we know that | |
1765 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1766 | || (! mips16 |
1767 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1768 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1769 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1770 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1771 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1772 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1773 | & OP_MASK_RT) | |
1774 | == 31)))) | |
cc5703cd ILT |
1775 | || (! mips16 |
1776 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1777 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1778 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1779 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1780 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1781 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1782 | & OP_MASK_RD) | |
1783 | == 31)))) | |
cc5703cd ILT |
1784 | || (mips16 |
1785 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1786 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1787 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1788 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1789 | == RA)))) | |
becfe05e ILT |
1790 | /* If the branch writes a register that the previous |
1791 | instruction reads, we can not swap (we know that | |
1792 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1793 | || (! mips16 |
1794 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1795 | && insn_uses_reg (&prev_insn, |
1796 | ((ip->insn_opcode >> OP_SH_RD) | |
1797 | & OP_MASK_RD), | |
cc5703cd ILT |
1798 | MIPS_GR_REG)) |
1799 | || (! mips16 | |
1800 | && (pinfo & INSN_WRITE_GPR_31) | |
1801 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1802 | || (mips16 | |
1803 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1804 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1805 | /* If we are generating embedded PIC code, the branch |
1806 | might be expanded into a sequence which uses $at, so | |
1807 | we can't swap with an instruction which reads it. */ | |
1808 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1809 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1810 | /* If the previous previous instruction has a load |
1811 | delay, and sets a register that the branch reads, we | |
1812 | can not swap. */ | |
cc5703cd ILT |
1813 | || (! mips16 |
1814 | && mips_isa < 4 | |
d8a1c247 KR |
1815 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1816 | || (mips_isa < 2 | |
1817 | && (prev_prev_insn.insn_mo->pinfo | |
1818 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1819 | && insn_uses_reg (ip, |
1820 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1821 | & OP_MASK_RT), | |
cc5703cd | 1822 | MIPS_GR_REG)) |
d31a3f5e ILT |
1823 | /* If one instruction sets a condition code and the |
1824 | other one uses a condition code, we can not swap. */ | |
1825 | || ((pinfo & INSN_READ_COND_CODE) | |
1826 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1827 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1828 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1829 | /* If the previous instruction uses the PC, we can not | |
1830 | swap. */ | |
1831 | || (mips16 | |
1832 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1833 | /* If the previous instruction was extended, we can not | |
1834 | swap. */ | |
1835 | || (mips16 && prev_insn_extended) | |
1836 | /* If the previous instruction had a fixup in mips16 | |
1837 | mode, we can not swap. This normally means that the | |
1838 | previous instruction was a 4 byte branch anyhow. */ | |
1839 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1840 | { |
1841 | /* We could do even better for unconditional branches to | |
1842 | portions of this object file; we could pick up the | |
1843 | instruction at the destination, put it in the delay | |
1844 | slot, and bump the destination address. */ | |
1845 | emit_nop (); | |
1846 | /* Update the previous insn information. */ | |
1847 | prev_prev_insn = *ip; | |
1848 | prev_insn.insn_mo = &dummy_opcode; | |
1849 | } | |
1850 | else | |
1851 | { | |
becfe05e | 1852 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1853 | if (! mips16) |
1854 | { | |
1855 | char *prev_f; | |
1856 | char temp[4]; | |
1857 | ||
1858 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1859 | memcpy (temp, prev_f, 4); | |
1860 | memcpy (prev_f, f, 4); | |
1861 | memcpy (f, temp, 4); | |
1862 | if (prev_insn_fixp) | |
1863 | { | |
1864 | prev_insn_fixp->fx_frag = frag_now; | |
1865 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1866 | } | |
1867 | if (fixp) | |
1868 | { | |
1869 | fixp->fx_frag = prev_insn_frag; | |
1870 | fixp->fx_where = prev_insn_where; | |
1871 | } | |
1872 | } | |
1873 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1874 | { |
cc5703cd ILT |
1875 | char *prev_f; |
1876 | char temp[2]; | |
1877 | ||
1878 | /* We are in mips16 mode, and we have just created a | |
1879 | variant frag. We need to extract the old | |
1880 | instruction from the end of the previous frag, | |
1881 | and add it to a new frag. */ | |
1882 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1883 | memcpy (temp, prev_f, 2); | |
1884 | prev_insn_frag->fr_fix -= 2; | |
1885 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1886 | { | |
1887 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1888 | memcpy (prev_f, prev_f + 2, 2); | |
1889 | } | |
1890 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1891 | } |
cc5703cd | 1892 | else |
becfe05e | 1893 | { |
cc5703cd ILT |
1894 | char *prev_f; |
1895 | char temp[2]; | |
1896 | ||
1897 | assert (prev_insn_fixp == NULL); | |
1898 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1899 | memcpy (temp, prev_f, 2); | |
1900 | memcpy (prev_f, f, 2); | |
1901 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1902 | memcpy (f, temp, 2); | |
1903 | else | |
1904 | { | |
1905 | memcpy (f, f + 2, 2); | |
1906 | memcpy (f + 2, temp, 2); | |
1907 | } | |
1908 | if (fixp) | |
1909 | { | |
1910 | fixp->fx_frag = prev_insn_frag; | |
1911 | fixp->fx_where = prev_insn_where; | |
1912 | } | |
becfe05e | 1913 | } |
cc5703cd | 1914 | |
becfe05e ILT |
1915 | /* Update the previous insn information; leave prev_insn |
1916 | unchanged. */ | |
1917 | prev_prev_insn = *ip; | |
1918 | } | |
1919 | prev_insn_is_delay_slot = 1; | |
1920 | ||
1921 | /* If that was an unconditional branch, forget the previous | |
1922 | insn information. */ | |
1aa6938e | 1923 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1924 | { |
1925 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1926 | prev_insn.insn_mo = &dummy_opcode; | |
1927 | } | |
a677feeb ILT |
1928 | |
1929 | prev_insn_fixp = NULL; | |
1930 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1931 | prev_insn_extended = 0; | |
becfe05e | 1932 | } |
1aa6938e | 1933 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1934 | { |
1935 | /* We don't yet optimize a branch likely. What we should do | |
1936 | is look at the target, copy the instruction found there | |
1937 | into the delay slot, and increment the branch to jump to | |
1938 | the next instruction. */ | |
1939 | emit_nop (); | |
1940 | /* Update the previous insn information. */ | |
1941 | prev_prev_insn = *ip; | |
1942 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
1943 | prev_insn_fixp = NULL; |
1944 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1945 | prev_insn_extended = 0; | |
8358c818 | 1946 | } |
becfe05e | 1947 | else |
670a50eb | 1948 | { |
becfe05e ILT |
1949 | /* Update the previous insn information. */ |
1950 | if (nops > 0) | |
1951 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1952 | else | |
1953 | prev_prev_insn = prev_insn; | |
1954 | prev_insn = *ip; | |
1955 | ||
1956 | /* Any time we see a branch, we always fill the delay slot | |
1957 | immediately; since this insn is not a branch, we know it | |
1958 | is not in a delay slot. */ | |
1959 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
1960 | |
1961 | prev_insn_fixp = fixp; | |
1962 | prev_insn_reloc_type = reloc_type; | |
1963 | if (mips16) | |
1964 | prev_insn_extended = (ip->use_extend | |
1965 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
1966 | } |
1967 | ||
4e95866e ILT |
1968 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1969 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1970 | prev_insn_frag = frag_now; |
1971 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
1972 | prev_insn_valid = 1; |
1973 | } | |
fbcfacb7 | 1974 | else if (place == NULL) |
a677feeb | 1975 | { |
fbcfacb7 | 1976 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
1977 | reordering, in order to determine the base address for mips16 |
1978 | PC relative relocs. */ | |
1979 | prev_insn = *ip; | |
1980 | prev_insn_reloc_type = reloc_type; | |
1981 | } | |
3d3c5039 | 1982 | |
becfe05e | 1983 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 1984 | mips_clear_insn_labels (); |
becfe05e ILT |
1985 | } |
1986 | ||
1987 | /* This function forgets that there was any previous instruction or | |
1988 | label. */ | |
1989 | ||
1990 | static void | |
1991 | mips_no_prev_insn () | |
1992 | { | |
1993 | prev_insn.insn_mo = &dummy_opcode; | |
1994 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1995 | prev_insn_valid = 0; | |
1996 | prev_insn_is_delay_slot = 0; | |
4e95866e | 1997 | prev_insn_unreordered = 0; |
cc5703cd | 1998 | prev_insn_extended = 0; |
a677feeb | 1999 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2000 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2001 | mips_clear_insn_labels (); |
becfe05e ILT |
2002 | } |
2003 | ||
2004 | /* This function must be called whenever we turn on noreorder or emit | |
2005 | something other than instructions. It inserts any NOPS which might | |
2006 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2007 | kept for the previous instructions. The INSNS parameter is true if |
2008 | instructions are to follow. */ | |
becfe05e ILT |
2009 | |
2010 | static void | |
fbcfacb7 ILT |
2011 | mips_emit_delays (insns) |
2012 | boolean insns; | |
becfe05e ILT |
2013 | { |
2014 | if (! mips_noreorder) | |
2015 | { | |
2016 | int nop; | |
2017 | ||
2018 | nop = 0; | |
cc5703cd ILT |
2019 | if ((! mips16 |
2020 | && mips_isa < 4 | |
344a8d61 JSC |
2021 | && (! cop_interlocks |
2022 | && (prev_insn.insn_mo->pinfo | |
2023 | & (INSN_LOAD_COPROC_DELAY | |
2024 | | INSN_COPROC_MOVE_DELAY | |
2025 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 2026 | || (! interlocks |
b2b8c24e ILT |
2027 | && (prev_insn.insn_mo->pinfo |
2028 | & (INSN_READ_LO | |
2029 | | INSN_READ_HI))) | |
cc5703cd ILT |
2030 | || (! mips16 |
2031 | && mips_isa < 2 | |
8358c818 ILT |
2032 | && (prev_insn.insn_mo->pinfo |
2033 | & (INSN_LOAD_MEMORY_DELAY | |
2034 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
2035 | { |
2036 | nop = 1; | |
cc5703cd ILT |
2037 | if ((! mips16 |
2038 | && mips_isa < 4 | |
344a8d61 JSC |
2039 | && (! cop_interlocks |
2040 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2041 | || (! interlocks |
b2b8c24e ILT |
2042 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2043 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2044 | emit_nop (); |
2045 | } | |
cc5703cd ILT |
2046 | else if ((! mips16 |
2047 | && mips_isa < 4 | |
344a8d61 JSC |
2048 | && (! cop_interlocks |
2049 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2050 | || (! interlocks |
b2b8c24e ILT |
2051 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2052 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2053 | nop = 1; |
2054 | if (nop) | |
670a50eb | 2055 | { |
fbcfacb7 ILT |
2056 | struct insn_label_list *l; |
2057 | ||
becfe05e | 2058 | emit_nop (); |
fbcfacb7 | 2059 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2060 | { |
fbcfacb7 ILT |
2061 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2062 | l->label->sy_frag = frag_now; | |
2063 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2064 | /* mips16 text labels are stored as odd. */ | |
2065 | if (mips16) | |
2066 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2067 | } |
3d3c5039 ILT |
2068 | } |
2069 | } | |
0221ddf7 | 2070 | |
fbcfacb7 ILT |
2071 | /* Mark instruction labels in mips16 mode. This permits the linker |
2072 | to handle them specially, such as generating jalx instructions | |
2073 | when needed. We also make them odd for the duration of the | |
2074 | assembly, in order to generate the right sort of code. We will | |
2075 | make them even in the adjust_symtab routine, while leaving them | |
2076 | marked. This is convenient for the debugger and the | |
2077 | disassembler. The linker knows to make them odd again. */ | |
2078 | if (mips16 && insns) | |
2079 | { | |
2080 | struct insn_label_list *l; | |
2081 | ||
2082 | for (l = insn_labels; l != NULL; l = l->next) | |
2083 | { | |
2084 | #ifdef S_SET_OTHER | |
2085 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2086 | S_SET_OTHER (l->label, STO_MIPS16); | |
2087 | #endif | |
2088 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2089 | ++l->label->sy_value.X_add_number; | |
2090 | } | |
2091 | } | |
2092 | ||
0221ddf7 | 2093 | mips_no_prev_insn (); |
3d3c5039 ILT |
2094 | } |
2095 | ||
670a50eb ILT |
2096 | /* Build an instruction created by a macro expansion. This is passed |
2097 | a pointer to the count of instructions created so far, an | |
2098 | expression, the name of the instruction to build, an operand format | |
2099 | string, and corresponding arguments. */ | |
2100 | ||
1dc1e798 | 2101 | #ifdef USE_STDARG |
3d3c5039 | 2102 | static void |
0dd2d296 ILT |
2103 | macro_build (char *place, |
2104 | int *counter, | |
670a50eb | 2105 | expressionS * ep, |
3d3c5039 ILT |
2106 | const char *name, |
2107 | const char *fmt, | |
2108 | ...) | |
1dc1e798 | 2109 | #else |
3d3c5039 | 2110 | static void |
0dd2d296 ILT |
2111 | macro_build (place, counter, ep, name, fmt, va_alist) |
2112 | char *place; | |
3d3c5039 ILT |
2113 | int *counter; |
2114 | expressionS *ep; | |
2115 | const char *name; | |
2116 | const char *fmt; | |
2117 | va_dcl | |
1dc1e798 | 2118 | #endif |
3d3c5039 | 2119 | { |
670a50eb ILT |
2120 | struct mips_cl_insn insn; |
2121 | bfd_reloc_code_real_type r; | |
2122 | va_list args; | |
3d3c5039 | 2123 | |
1dc1e798 | 2124 | #ifdef USE_STDARG |
670a50eb | 2125 | va_start (args, fmt); |
3d3c5039 | 2126 | #else |
670a50eb | 2127 | va_start (args); |
3d3c5039 ILT |
2128 | #endif |
2129 | ||
670a50eb ILT |
2130 | /* |
2131 | * If the macro is about to expand into a second instruction, | |
2132 | * print a warning if needed. We need to pass ip as a parameter | |
2133 | * to generate a better warning message here... | |
2134 | */ | |
0dd2d296 | 2135 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2136 | as_warn ("Macro instruction expanded into multiple instructions"); |
2137 | ||
0dd2d296 ILT |
2138 | if (place == NULL) |
2139 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2140 | |
cc5703cd ILT |
2141 | if (mips16) |
2142 | { | |
2143 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2144 | va_end (args); | |
2145 | return; | |
2146 | } | |
2147 | ||
670a50eb ILT |
2148 | r = BFD_RELOC_UNUSED; |
2149 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2150 | assert (insn.insn_mo); | |
2151 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2152 | ||
9226253a | 2153 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2154 | || insn.insn_mo->pinfo == INSN_MACRO |
2155 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2156 | && mips_isa < 2) | |
2157 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2158 | && mips_isa < 3) | |
2159 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2160 | && mips_isa < 4) | |
2161 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2162 | && ! mips_4650) | |
2163 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2164 | && ! mips_4010) | |
2165 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
2166 | && ! mips_4100) |
2167 | /* start-sanitize-r5900 */ | |
2168 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_5900 | |
2169 | && ! mips_5900) | |
2170 | /* end-sanitize-r5900 */ | |
2171 | ) | |
670a50eb ILT |
2172 | { |
2173 | ++insn.insn_mo; | |
2174 | assert (insn.insn_mo->name); | |
2175 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2176 | } |
670a50eb ILT |
2177 | insn.insn_opcode = insn.insn_mo->match; |
2178 | for (;;) | |
2179 | { | |
2180 | switch (*fmt++) | |
2181 | { | |
3d3c5039 | 2182 | case '\0': |
670a50eb | 2183 | break; |
3d3c5039 ILT |
2184 | |
2185 | case ',': | |
2186 | case '(': | |
2187 | case ')': | |
670a50eb | 2188 | continue; |
3d3c5039 ILT |
2189 | |
2190 | case 't': | |
2191 | case 'w': | |
918692a5 | 2192 | case 'E': |
670a50eb ILT |
2193 | insn.insn_opcode |= va_arg (args, int) << 16; |
2194 | continue; | |
3d3c5039 ILT |
2195 | |
2196 | case 'c': | |
2197 | case 'T': | |
2198 | case 'W': | |
670a50eb ILT |
2199 | insn.insn_opcode |= va_arg (args, int) << 16; |
2200 | continue; | |
3d3c5039 ILT |
2201 | |
2202 | case 'd': | |
918692a5 | 2203 | case 'G': |
670a50eb ILT |
2204 | insn.insn_opcode |= va_arg (args, int) << 11; |
2205 | continue; | |
3d3c5039 ILT |
2206 | |
2207 | case 'V': | |
2208 | case 'S': | |
670a50eb ILT |
2209 | insn.insn_opcode |= va_arg (args, int) << 11; |
2210 | continue; | |
3d3c5039 | 2211 | |
ff3a5c18 ILT |
2212 | case 'z': |
2213 | continue; | |
2214 | ||
3d3c5039 | 2215 | case '<': |
670a50eb ILT |
2216 | insn.insn_opcode |= va_arg (args, int) << 6; |
2217 | continue; | |
3d3c5039 ILT |
2218 | |
2219 | case 'D': | |
670a50eb ILT |
2220 | insn.insn_opcode |= va_arg (args, int) << 6; |
2221 | continue; | |
3d3c5039 | 2222 | |
918692a5 ILT |
2223 | case 'B': |
2224 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2225 | continue; | |
2226 | ||
3d3c5039 ILT |
2227 | case 'b': |
2228 | case 's': | |
2229 | case 'r': | |
2230 | case 'v': | |
670a50eb ILT |
2231 | insn.insn_opcode |= va_arg (args, int) << 21; |
2232 | continue; | |
3d3c5039 ILT |
2233 | |
2234 | case 'i': | |
2235 | case 'j': | |
2236 | case 'o': | |
9226253a | 2237 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2238 | assert (r == BFD_RELOC_MIPS_GPREL |
2239 | || r == BFD_RELOC_MIPS_LITERAL | |
2240 | || r == BFD_RELOC_LO16 | |
2241 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2242 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2243 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2244 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2245 | || (ep->X_op == O_subtract |
2246 | && now_seg == text_section | |
ecd4ca1c | 2247 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2248 | continue; |
3d3c5039 | 2249 | |
6e8dda9c | 2250 | case 'u': |
ecd4ca1c ILT |
2251 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2252 | assert (ep != NULL | |
2253 | && (ep->X_op == O_constant | |
2254 | || (ep->X_op == O_symbol | |
2255 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2256 | || r == BFD_RELOC_HI16 |
2257 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2258 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2259 | || (ep->X_op == O_subtract |
2260 | && now_seg == text_section | |
ecd4ca1c ILT |
2261 | && r == BFD_RELOC_PCREL_HI16_S))); |
2262 | if (ep->X_op == O_constant) | |
2263 | { | |
2264 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2265 | ep = NULL; | |
2266 | r = BFD_RELOC_UNUSED; | |
2267 | } | |
6e8dda9c ILT |
2268 | continue; |
2269 | ||
3d3c5039 | 2270 | case 'p': |
670a50eb ILT |
2271 | assert (ep != NULL); |
2272 | /* | |
2273 | * This allows macro() to pass an immediate expression for | |
2274 | * creating short branches without creating a symbol. | |
2275 | * Note that the expression still might come from the assembly | |
2276 | * input, in which case the value is not checked for range nor | |
2277 | * is a relocation entry generated (yuck). | |
2278 | */ | |
5ac34ac3 | 2279 | if (ep->X_op == O_constant) |
670a50eb ILT |
2280 | { |
2281 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2282 | ep = NULL; | |
2283 | } | |
2284 | else | |
2285 | r = BFD_RELOC_16_PCREL_S2; | |
2286 | continue; | |
3d3c5039 | 2287 | |
9226253a ILT |
2288 | case 'a': |
2289 | assert (ep != NULL); | |
2290 | r = BFD_RELOC_MIPS_JMP; | |
2291 | continue; | |
2292 | ||
3d3c5039 | 2293 | default: |
670a50eb | 2294 | internalError (); |
3d3c5039 | 2295 | } |
670a50eb | 2296 | break; |
3d3c5039 | 2297 | } |
670a50eb ILT |
2298 | va_end (args); |
2299 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2300 | ||
867a58b3 | 2301 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2302 | } |
2303 | ||
cc5703cd ILT |
2304 | static void |
2305 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2306 | char *place; | |
2307 | int *counter; | |
2308 | expressionS *ep; | |
2309 | const char *name; | |
2310 | const char *fmt; | |
2311 | va_list args; | |
2312 | { | |
2313 | struct mips_cl_insn insn; | |
2314 | bfd_reloc_code_real_type r; | |
2315 | ||
2316 | r = BFD_RELOC_UNUSED; | |
2317 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2318 | assert (insn.insn_mo); | |
2319 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2320 | ||
2321 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2322 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2323 | { | |
2324 | ++insn.insn_mo; | |
2325 | assert (insn.insn_mo->name); | |
2326 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2327 | } | |
2328 | ||
2329 | insn.insn_opcode = insn.insn_mo->match; | |
2330 | insn.use_extend = false; | |
2331 | ||
2332 | for (;;) | |
2333 | { | |
2334 | int c; | |
2335 | ||
2336 | c = *fmt++; | |
2337 | switch (c) | |
2338 | { | |
2339 | case '\0': | |
2340 | break; | |
2341 | ||
2342 | case ',': | |
2343 | case '(': | |
2344 | case ')': | |
2345 | continue; | |
2346 | ||
2347 | case 'y': | |
2348 | case 'w': | |
2349 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2350 | continue; | |
2351 | ||
2352 | case 'x': | |
2353 | case 'v': | |
2354 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2355 | continue; | |
2356 | ||
2357 | case 'z': | |
2358 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2359 | continue; | |
2360 | ||
2361 | case 'Z': | |
2362 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2363 | continue; | |
2364 | ||
2365 | case '0': | |
2366 | case 'S': | |
2367 | case 'P': | |
2368 | case 'R': | |
2369 | continue; | |
2370 | ||
2371 | case 'X': | |
2372 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2373 | continue; | |
2374 | ||
2375 | case 'Y': | |
2376 | { | |
2377 | int regno; | |
2378 | ||
2379 | regno = va_arg (args, int); | |
2380 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2381 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2382 | } | |
2383 | continue; | |
2384 | ||
2385 | case '<': | |
2386 | case '>': | |
2387 | case '4': | |
2388 | case '5': | |
2389 | case 'H': | |
2390 | case 'W': | |
2391 | case 'D': | |
2392 | case 'j': | |
2393 | case '8': | |
2394 | case 'V': | |
2395 | case 'C': | |
2396 | case 'U': | |
2397 | case 'k': | |
2398 | case 'K': | |
2399 | case 'p': | |
2400 | case 'q': | |
2401 | { | |
2402 | assert (ep != NULL); | |
2403 | ||
2404 | if (ep->X_op != O_constant) | |
2405 | r = BFD_RELOC_UNUSED + c; | |
2406 | else | |
2407 | { | |
15e69f98 ILT |
2408 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2409 | false, false, &insn.insn_opcode, | |
2410 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2411 | ep = NULL; |
2412 | r = BFD_RELOC_UNUSED; | |
2413 | } | |
2414 | } | |
2415 | continue; | |
2416 | ||
2417 | case '6': | |
2418 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2419 | continue; | |
2420 | } | |
2421 | ||
2422 | break; | |
2423 | } | |
2424 | ||
2425 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2426 | ||
2427 | append_insn (place, &insn, ep, r, false); | |
2428 | } | |
2429 | ||
3d3c5039 ILT |
2430 | /* |
2431 | * Generate a "lui" instruction. | |
2432 | */ | |
2433 | static void | |
0dd2d296 ILT |
2434 | macro_build_lui (place, counter, ep, regnum) |
2435 | char *place; | |
3d3c5039 ILT |
2436 | int *counter; |
2437 | expressionS *ep; | |
2438 | int regnum; | |
2439 | { | |
670a50eb ILT |
2440 | expressionS high_expr; |
2441 | struct mips_cl_insn insn; | |
2442 | bfd_reloc_code_real_type r; | |
2443 | CONST char *name = "lui"; | |
2444 | CONST char *fmt = "t,u"; | |
2445 | ||
cc5703cd ILT |
2446 | assert (! mips16); |
2447 | ||
0dd2d296 ILT |
2448 | if (place == NULL) |
2449 | high_expr = *ep; | |
2450 | else | |
2451 | { | |
2452 | high_expr.X_op = O_constant; | |
fb251650 | 2453 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2454 | } |
670a50eb | 2455 | |
5ac34ac3 | 2456 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2457 | { |
2458 | /* we can compute the instruction now without a relocation entry */ | |
2459 | if (high_expr.X_add_number & 0x8000) | |
2460 | high_expr.X_add_number += 0x10000; | |
2461 | high_expr.X_add_number = | |
2462 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2463 | r = BFD_RELOC_UNUSED; | |
2464 | } | |
2465 | else | |
0dd2d296 ILT |
2466 | { |
2467 | assert (ep->X_op == O_symbol); | |
2468 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2469 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2470 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2471 | r = BFD_RELOC_HI16_S; | |
2472 | } | |
670a50eb ILT |
2473 | |
2474 | /* | |
2475 | * If the macro is about to expand into a second instruction, | |
2476 | * print a warning if needed. We need to pass ip as a parameter | |
2477 | * to generate a better warning message here... | |
2478 | */ | |
0dd2d296 | 2479 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2480 | as_warn ("Macro instruction expanded into multiple instructions"); |
2481 | ||
0dd2d296 ILT |
2482 | if (place == NULL) |
2483 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2484 | |
2485 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2486 | assert (insn.insn_mo); | |
2487 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2488 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2489 | ||
0dd2d296 | 2490 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2491 | if (r == BFD_RELOC_UNUSED) |
2492 | { | |
2493 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2494 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2495 | } |
2496 | else | |
867a58b3 | 2497 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2498 | } |
2499 | ||
2500 | /* set_at() | |
2501 | * Generates code to set the $at register to true (one) | |
2502 | * if reg is less than the immediate expression. | |
2503 | */ | |
2504 | static void | |
6e8dda9c | 2505 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2506 | int *counter; |
2507 | int reg; | |
6e8dda9c | 2508 | int unsignedp; |
3d3c5039 | 2509 | { |
6e8dda9c | 2510 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2511 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2512 | unsignedp ? "sltiu" : "slti", |
9226253a | 2513 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2514 | else |
670a50eb | 2515 | { |
d8a1c247 | 2516 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2517 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2518 | unsignedp ? "sltu" : "slt", |
2519 | "d,v,t", AT, reg, AT); | |
670a50eb | 2520 | } |
3d3c5039 ILT |
2521 | } |
2522 | ||
6e8dda9c | 2523 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2524 | |
2525 | static void | |
19ed8960 | 2526 | check_absolute_expr (ip, ex) |
3d3c5039 | 2527 | struct mips_cl_insn *ip; |
19ed8960 | 2528 | expressionS *ex; |
3d3c5039 | 2529 | { |
19ed8960 | 2530 | if (ex->X_op != O_constant) |
670a50eb | 2531 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2532 | } |
2533 | ||
ff8716f5 JSC |
2534 | /* Count the leading zeroes by performing a binary chop. This is a |
2535 | bulky bit of source, but performance is a LOT better for the | |
2536 | majority of values than a simple loop to count the bits: | |
2537 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2538 | if ((v) & (1 << (31 - lcnt))) | |
2539 | break; | |
2540 | However it is not code size friendly, and the gain will drop a bit | |
2541 | on certain cached systems. | |
2542 | */ | |
2543 | #define COUNT_TOP_ZEROES(v) \ | |
2544 | (((v) & ~0xffff) == 0 \ | |
2545 | ? ((v) & ~0xff) == 0 \ | |
2546 | ? ((v) & ~0xf) == 0 \ | |
2547 | ? ((v) & ~0x3) == 0 \ | |
2548 | ? ((v) & ~0x1) == 0 \ | |
2549 | ? !(v) \ | |
2550 | ? 32 \ | |
2551 | : 31 \ | |
2552 | : 30 \ | |
2553 | : ((v) & ~0x7) == 0 \ | |
2554 | ? 29 \ | |
2555 | : 28 \ | |
2556 | : ((v) & ~0x3f) == 0 \ | |
2557 | ? ((v) & ~0x1f) == 0 \ | |
2558 | ? 27 \ | |
2559 | : 26 \ | |
2560 | : ((v) & ~0x7f) == 0 \ | |
2561 | ? 25 \ | |
2562 | : 24 \ | |
2563 | : ((v) & ~0xfff) == 0 \ | |
2564 | ? ((v) & ~0x3ff) == 0 \ | |
2565 | ? ((v) & ~0x1ff) == 0 \ | |
2566 | ? 23 \ | |
2567 | : 22 \ | |
2568 | : ((v) & ~0x7ff) == 0 \ | |
2569 | ? 21 \ | |
2570 | : 20 \ | |
2571 | : ((v) & ~0x3fff) == 0 \ | |
2572 | ? ((v) & ~0x1fff) == 0 \ | |
2573 | ? 19 \ | |
2574 | : 18 \ | |
2575 | : ((v) & ~0x7fff) == 0 \ | |
2576 | ? 17 \ | |
2577 | : 16 \ | |
2578 | : ((v) & ~0xffffff) == 0 \ | |
2579 | ? ((v) & ~0xfffff) == 0 \ | |
2580 | ? ((v) & ~0x3ffff) == 0 \ | |
2581 | ? ((v) & ~0x1ffff) == 0 \ | |
2582 | ? 15 \ | |
2583 | : 14 \ | |
2584 | : ((v) & ~0x7ffff) == 0 \ | |
2585 | ? 13 \ | |
2586 | : 12 \ | |
2587 | : ((v) & ~0x3fffff) == 0 \ | |
2588 | ? ((v) & ~0x1fffff) == 0 \ | |
2589 | ? 11 \ | |
2590 | : 10 \ | |
2591 | : ((v) & ~0x7fffff) == 0 \ | |
2592 | ? 9 \ | |
2593 | : 8 \ | |
2594 | : ((v) & ~0xfffffff) == 0 \ | |
2595 | ? ((v) & ~0x3ffffff) == 0 \ | |
2596 | ? ((v) & ~0x1ffffff) == 0 \ | |
2597 | ? 7 \ | |
2598 | : 6 \ | |
2599 | : ((v) & ~0x7ffffff) == 0 \ | |
2600 | ? 5 \ | |
2601 | : 4 \ | |
2602 | : ((v) & ~0x3fffffff) == 0 \ | |
2603 | ? ((v) & ~0x1fffffff) == 0 \ | |
2604 | ? 3 \ | |
2605 | : 2 \ | |
2606 | : ((v) & ~0x7fffffff) == 0 \ | |
2607 | ? 1 \ | |
2608 | : 0) | |
2609 | ||
3d3c5039 ILT |
2610 | /* load_register() |
2611 | * This routine generates the least number of instructions neccessary to load | |
2612 | * an absolute expression value into a register. | |
2613 | */ | |
2614 | static void | |
d8a1c247 | 2615 | load_register (counter, reg, ep, dbl) |
670a50eb | 2616 | int *counter; |
670a50eb ILT |
2617 | int reg; |
2618 | expressionS *ep; | |
d8a1c247 | 2619 | int dbl; |
3d3c5039 | 2620 | { |
c36a90ef ILT |
2621 | int freg; |
2622 | expressionS hi32, lo32; | |
847a01cd ILT |
2623 | |
2624 | if (ep->X_op != O_big) | |
6e8dda9c | 2625 | { |
847a01cd | 2626 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2627 | if (ep->X_add_number < 0x8000 |
2628 | && (ep->X_add_number >= 0 | |
2629 | || (ep->X_add_number >= -0x8000 | |
2630 | && (! dbl | |
2631 | || ! ep->X_unsigned | |
2632 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2633 | { |
2634 | /* We can handle 16 bit signed values with an addiu to | |
2635 | $zero. No need to ever use daddiu here, since $zero and | |
2636 | the result are always correct in 32 bit mode. */ | |
2637 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2638 | (int) BFD_RELOC_LO16); | |
2639 | return; | |
2640 | } | |
2641 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2642 | { | |
2643 | /* We can handle 16 bit unsigned values with an ori to | |
2644 | $zero. */ | |
2645 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2646 | (int) BFD_RELOC_LO16); | |
2647 | return; | |
2648 | } | |
98bfd087 ILT |
2649 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2650 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2651 | == ~ (offsetT) 0x7fffffff)) | |
2652 | && (! dbl | |
2653 | || ! ep->X_unsigned | |
2654 | || sizeof (ep->X_add_number) > 4 | |
2655 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2656 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2657 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2658 | { |
2659 | /* 32 bit values require an lui. */ | |
2660 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2661 | (int) BFD_RELOC_HI16); | |
2662 | if ((ep->X_add_number & 0xffff) != 0) | |
2663 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2664 | (int) BFD_RELOC_LO16); | |
2665 | return; | |
2666 | } | |
6e8dda9c | 2667 | } |
847a01cd ILT |
2668 | |
2669 | /* The value is larger than 32 bits. */ | |
2670 | ||
2671 | if (mips_isa < 3) | |
670a50eb | 2672 | { |
6e8dda9c | 2673 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2674 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2675 | (int) BFD_RELOC_LO16); |
847a01cd | 2676 | return; |
6e8dda9c | 2677 | } |
6e8dda9c | 2678 | |
847a01cd ILT |
2679 | if (ep->X_op != O_big) |
2680 | { | |
6e8dda9c | 2681 | hi32 = *ep; |
c36a90ef ILT |
2682 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2683 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2684 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2685 | lo32 = *ep; |
2686 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2687 | } |
847a01cd ILT |
2688 | else |
2689 | { | |
2690 | assert (ep->X_add_number > 2); | |
2691 | if (ep->X_add_number == 3) | |
2692 | generic_bignum[3] = 0; | |
2693 | else if (ep->X_add_number > 4) | |
2694 | as_bad ("Number larger than 64 bits"); | |
2695 | lo32.X_op = O_constant; | |
2696 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2697 | hi32.X_op = O_constant; | |
2698 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2699 | } | |
2700 | ||
d8a1c247 KR |
2701 | if (hi32.X_add_number == 0) |
2702 | freg = 0; | |
2703 | else | |
2704 | { | |
c36a90ef ILT |
2705 | int shift, bit; |
2706 | unsigned long hi, lo; | |
2707 | ||
fb251650 ILT |
2708 | if (hi32.X_add_number == 0xffffffff) |
2709 | { | |
2710 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2711 | { | |
c36a90ef ILT |
2712 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2713 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2714 | return; |
2715 | } | |
2716 | if (lo32.X_add_number & 0x80000000) | |
2717 | { | |
2718 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2719 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2720 | if (lo32.X_add_number & 0xffff) |
2721 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2722 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2723 | return; |
2724 | } | |
2725 | } | |
ff8716f5 | 2726 | |
c36a90ef ILT |
2727 | /* Check for 16bit shifted constant. We know that hi32 is |
2728 | non-zero, so start the mask on the first bit of the hi32 | |
2729 | value. */ | |
ff8716f5 JSC |
2730 | shift = 17; |
2731 | do | |
2732 | { | |
c36a90ef ILT |
2733 | unsigned long himask, lomask; |
2734 | ||
2735 | if (shift < 32) | |
2736 | { | |
2737 | himask = 0xffff >> (32 - shift); | |
2738 | lomask = (0xffff << shift) & 0xffffffff; | |
2739 | } | |
2740 | else | |
2741 | { | |
2742 | himask = 0xffff << (shift - 32); | |
2743 | lomask = 0; | |
2744 | } | |
2745 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2746 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2747 | { | |
2748 | expressionS tmp; | |
2749 | ||
2750 | tmp.X_op = O_constant; | |
2751 | if (shift < 32) | |
2752 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2753 | | (lo32.X_add_number >> shift)); | |
2754 | else | |
2755 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2756 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2757 | (int) BFD_RELOC_LO16); | |
2758 | macro_build ((char *) NULL, counter, NULL, | |
2759 | (shift >= 32) ? "dsll32" : "dsll", | |
2760 | "d,w,<", reg, reg, | |
2761 | (shift >= 32) ? shift - 32 : shift); | |
2762 | return; | |
2763 | } | |
ff8716f5 JSC |
2764 | shift++; |
2765 | } while (shift <= (64 - 16)); | |
2766 | ||
c36a90ef ILT |
2767 | /* Find the bit number of the lowest one bit, and store the |
2768 | shifted value in hi/lo. */ | |
2769 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2770 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2771 | if (lo != 0) | |
2772 | { | |
2773 | bit = 0; | |
2774 | while ((lo & 1) == 0) | |
2775 | { | |
2776 | lo >>= 1; | |
2777 | ++bit; | |
2778 | } | |
2779 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2780 | hi >>= bit; | |
2781 | } | |
2782 | else | |
2783 | { | |
2784 | bit = 32; | |
2785 | while ((hi & 1) == 0) | |
2786 | { | |
2787 | hi >>= 1; | |
2788 | ++bit; | |
2789 | } | |
2790 | lo = hi; | |
2791 | hi = 0; | |
2792 | } | |
2793 | ||
2794 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2795 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2796 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2797 | { |
c36a90ef | 2798 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2799 | if (shift != 0) |
2800 | { | |
c36a90ef ILT |
2801 | expressionS tmp; |
2802 | ||
2803 | /* This instruction will set the register to be all | |
2804 | ones. */ | |
ff8716f5 | 2805 | tmp.X_op = O_constant; |
c36a90ef ILT |
2806 | tmp.X_add_number = (offsetT) -1; |
2807 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2808 | reg, 0, (int) BFD_RELOC_LO16); | |
2809 | if (bit != 0) | |
ff8716f5 | 2810 | { |
c36a90ef | 2811 | bit += shift; |
ff8716f5 | 2812 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2813 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2814 | "d,w,<", reg, reg, |
c36a90ef | 2815 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2816 | } |
c36a90ef ILT |
2817 | macro_build ((char *) NULL, counter, NULL, |
2818 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2819 | "d,w,<", reg, reg, | |
2820 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2821 | return; |
2822 | } | |
2823 | } | |
c36a90ef ILT |
2824 | |
2825 | /* Sign extend hi32 before calling load_register, because we can | |
2826 | generally get better code when we load a sign extended value. */ | |
2827 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2828 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2829 | load_register (counter, reg, &hi32, 0); |
2830 | freg = reg; | |
2831 | } | |
847a01cd | 2832 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2833 | { |
2834 | if (freg != 0) | |
2835 | { | |
2836 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2837 | freg, 0); | |
2838 | freg = reg; | |
2839 | } | |
2840 | } | |
847a01cd ILT |
2841 | else |
2842 | { | |
2843 | expressionS mid16; | |
2844 | ||
fb251650 ILT |
2845 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2846 | { | |
2847 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2848 | (int) BFD_RELOC_HI16); | |
2849 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2850 | reg, 0); |
fb251650 ILT |
2851 | return; |
2852 | } | |
2853 | ||
d8a1c247 KR |
2854 | if (freg != 0) |
2855 | { | |
2856 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2857 | freg, 16); | |
2858 | freg = reg; | |
2859 | } | |
847a01cd ILT |
2860 | mid16 = lo32; |
2861 | mid16.X_add_number >>= 16; | |
2862 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2863 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2864 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2865 | reg, 16); | |
d8a1c247 | 2866 | freg = reg; |
847a01cd ILT |
2867 | } |
2868 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2869 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2870 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2871 | } |
2872 | ||
0dd2d296 ILT |
2873 | /* Load an address into a register. */ |
2874 | ||
2875 | static void | |
2876 | load_address (counter, reg, ep) | |
2877 | int *counter; | |
2878 | int reg; | |
2879 | expressionS *ep; | |
2880 | { | |
2881 | char *p; | |
2882 | ||
2883 | if (ep->X_op != O_constant | |
2884 | && ep->X_op != O_symbol) | |
2885 | { | |
2886 | as_bad ("expression too complex"); | |
2887 | ep->X_op = O_constant; | |
2888 | } | |
2889 | ||
2890 | if (ep->X_op == O_constant) | |
d9aba805 | 2891 | { |
d8a1c247 | 2892 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2893 | return; |
2894 | } | |
2895 | ||
2896 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2897 | { |
2898 | /* If this is a reference to a GP relative symbol, we want | |
2899 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2900 | Otherwise we want | |
04cb3372 | 2901 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2902 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2903 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2904 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2905 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2906 | p = NULL; |
2907 | else | |
2908 | { | |
8ea7f4e8 | 2909 | frag_grow (20); |
0dd2d296 ILT |
2910 | macro_build ((char *) NULL, counter, ep, |
2911 | mips_isa < 3 ? "addiu" : "daddiu", | |
2912 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2913 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2914 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2915 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2916 | } | |
2917 | macro_build_lui (p, counter, ep, reg); | |
2918 | if (p != NULL) | |
2919 | p += 4; | |
2920 | macro_build (p, counter, ep, | |
2921 | mips_isa < 3 ? "addiu" : "daddiu", | |
2922 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2923 | } | |
fb251650 | 2924 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2925 | { |
2926 | expressionS ex; | |
2927 | ||
2928 | /* If this is a reference to an external symbol, we want | |
2929 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2930 | Otherwise we want | |
2931 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2932 | nop | |
2933 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2934 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2935 | ex.X_add_number = ep->X_add_number; |
2936 | ep->X_add_number = 0; | |
8ea7f4e8 | 2937 | frag_grow (20); |
0dd2d296 ILT |
2938 | macro_build ((char *) NULL, counter, ep, |
2939 | mips_isa < 3 ? "lw" : "ld", | |
2940 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2941 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2942 | p = frag_var (rs_machine_dependent, 4, 0, | |
2943 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2944 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2945 | macro_build (p, counter, ep, | |
2946 | mips_isa < 3 ? "addiu" : "daddiu", | |
2947 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2948 | if (ex.X_add_number != 0) | |
2949 | { | |
2950 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2951 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2952 | ex.X_op = O_constant; | |
fb251650 ILT |
2953 | macro_build ((char *) NULL, counter, &ex, |
2954 | mips_isa < 3 ? "addiu" : "daddiu", | |
2955 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2956 | } | |
2957 | } | |
2958 | else if (mips_pic == SVR4_PIC) | |
2959 | { | |
2960 | expressionS ex; | |
2961 | int off; | |
2962 | ||
2963 | /* This is the large GOT case. If this is a reference to an | |
2964 | external symbol, we want | |
2965 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2966 | addu $reg,$reg,$gp | |
2967 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2968 | Otherwise, for a reference to a local symbol, we want | |
2969 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2970 | nop | |
2971 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2972 | If there is a constant, it must be added in after. */ | |
2973 | ex.X_add_number = ep->X_add_number; | |
2974 | ep->X_add_number = 0; | |
2975 | if (reg_needs_delay (GP)) | |
2976 | off = 4; | |
2977 | else | |
2978 | off = 0; | |
2979 | frag_grow (32); | |
2980 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2981 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2982 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2983 | mips_isa < 3 ? "addu" : "daddu", | |
2984 | "d,v,t", reg, reg, GP); | |
2985 | macro_build ((char *) NULL, counter, ep, | |
2986 | mips_isa < 3 ? "lw" : "ld", | |
2987 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2988 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2989 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2990 | mips_warn_about_macros), | |
2991 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2992 | if (off > 0) | |
2993 | { | |
2994 | /* We need a nop before loading from $gp. This special | |
2995 | check is required because the lui which starts the main | |
2996 | instruction stream does not refer to $gp, and so will not | |
2997 | insert the nop which may be required. */ | |
2998 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2999 | p += 4; | |
3000 | } | |
3001 | macro_build (p, counter, ep, | |
3002 | mips_isa < 3 ? "lw" : "ld", | |
3003 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3004 | p += 4; | |
3005 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3006 | p += 4; | |
3007 | macro_build (p, counter, ep, | |
3008 | mips_isa < 3 ? "addiu" : "daddiu", | |
3009 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3010 | if (ex.X_add_number != 0) | |
3011 | { | |
3012 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3013 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3014 | ex.X_op = O_constant; | |
3015 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
3016 | mips_isa < 3 ? "addiu" : "daddiu", |
3017 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3018 | } | |
d9aba805 ILT |
3019 | } |
3020 | else if (mips_pic == EMBEDDED_PIC) | |
3021 | { | |
3022 | /* We always do | |
3023 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3024 | */ | |
3025 | macro_build ((char *) NULL, counter, ep, | |
3026 | mips_isa < 3 ? "addiu" : "daddiu", | |
3027 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3028 | } | |
3029 | else | |
3030 | abort (); | |
0dd2d296 ILT |
3031 | } |
3032 | ||
3d3c5039 ILT |
3033 | /* |
3034 | * Build macros | |
3035 | * This routine implements the seemingly endless macro or synthesized | |
3036 | * instructions and addressing modes in the mips assembly language. Many | |
3037 | * of these macros are simple and are similar to each other. These could | |
3038 | * probably be handled by some kind of table or grammer aproach instead of | |
3039 | * this verbose method. Others are not simple macros but are more like | |
3040 | * optimizing code generation. | |
3041 | * One interesting optimization is when several store macros appear | |
3042 | * consecutivly that would load AT with the upper half of the same address. | |
3043 | * The ensuing load upper instructions are ommited. This implies some kind | |
3044 | * of global optimization. We currently only optimize within a single macro. | |
3045 | * For many of the load and store macros if the address is specified as a | |
3046 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3047 | * first load register 'at' with zero and use it as the base register. The | |
3048 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3049 | * we're missing. | |
3050 | */ | |
3051 | static void | |
3052 | macro (ip) | |
3053 | struct mips_cl_insn *ip; | |
3054 | { | |
670a50eb ILT |
3055 | register int treg, sreg, dreg, breg; |
3056 | int tempreg; | |
3057 | int mask; | |
3058 | int icnt = 0; | |
3059 | int used_at; | |
670a50eb ILT |
3060 | expressionS expr1; |
3061 | const char *s; | |
8358c818 | 3062 | const char *s2; |
670a50eb | 3063 | const char *fmt; |
8358c818 ILT |
3064 | int likely = 0; |
3065 | int dbl = 0; | |
3066 | int coproc = 0; | |
b2b8c24e | 3067 | int lr = 0; |
6e8dda9c | 3068 | offsetT maxnum; |
adcf2b9d | 3069 | int off; |
9226253a | 3070 | bfd_reloc_code_real_type r; |
0dd2d296 | 3071 | char *p; |
55933a58 | 3072 | int hold_mips_optimize; |
670a50eb | 3073 | |
cc5703cd ILT |
3074 | assert (! mips16); |
3075 | ||
670a50eb ILT |
3076 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3077 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3078 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3079 | mask = ip->insn_mo->mask; | |
3080 | ||
5ac34ac3 ILT |
3081 | expr1.X_op = O_constant; |
3082 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3083 | expr1.X_add_symbol = NULL; |
3084 | expr1.X_add_number = 1; | |
3085 | ||
3086 | switch (mask) | |
3087 | { | |
6e8dda9c ILT |
3088 | case M_DABS: |
3089 | dbl = 1; | |
3d3c5039 | 3090 | case M_ABS: |
6e8dda9c ILT |
3091 | /* bgez $a0,.+12 |
3092 | move v0,$a0 | |
3093 | sub v0,$zero,$a0 | |
3094 | */ | |
3d3c5039 | 3095 | |
fbcfacb7 | 3096 | mips_emit_delays (true); |
becfe05e | 3097 | ++mips_noreorder; |
0dd2d296 | 3098 | mips_any_noreorder = 1; |
3d3c5039 | 3099 | |
670a50eb | 3100 | expr1.X_add_number = 8; |
0dd2d296 | 3101 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3102 | if (dreg == sreg) |
0dd2d296 | 3103 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3104 | else |
0dd2d296 ILT |
3105 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3106 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3107 | dbl ? "dsub" : "sub", |
3108 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3109 | |
becfe05e | 3110 | --mips_noreorder; |
670a50eb | 3111 | return; |
3d3c5039 ILT |
3112 | |
3113 | case M_ADD_I: | |
8358c818 ILT |
3114 | s = "addi"; |
3115 | s2 = "add"; | |
3116 | goto do_addi; | |
3d3c5039 | 3117 | case M_ADDU_I: |
8358c818 ILT |
3118 | s = "addiu"; |
3119 | s2 = "addu"; | |
3120 | goto do_addi; | |
3121 | case M_DADD_I: | |
6e8dda9c | 3122 | dbl = 1; |
8358c818 ILT |
3123 | s = "daddi"; |
3124 | s2 = "dadd"; | |
3125 | goto do_addi; | |
3126 | case M_DADDU_I: | |
6e8dda9c | 3127 | dbl = 1; |
8358c818 ILT |
3128 | s = "daddiu"; |
3129 | s2 = "daddu"; | |
3130 | do_addi: | |
6e8dda9c | 3131 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3132 | { |
0dd2d296 | 3133 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3134 | (int) BFD_RELOC_LO16); |
670a50eb | 3135 | return; |
3d3c5039 | 3136 | } |
d8a1c247 | 3137 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3138 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3139 | break; |
3d3c5039 ILT |
3140 | |
3141 | case M_AND_I: | |
6e8dda9c ILT |
3142 | s = "andi"; |
3143 | s2 = "and"; | |
3144 | goto do_bit; | |
3d3c5039 | 3145 | case M_OR_I: |
6e8dda9c ILT |
3146 | s = "ori"; |
3147 | s2 = "or"; | |
3148 | goto do_bit; | |
3d3c5039 | 3149 | case M_NOR_I: |
6e8dda9c ILT |
3150 | s = ""; |
3151 | s2 = "nor"; | |
3152 | goto do_bit; | |
3d3c5039 | 3153 | case M_XOR_I: |
6e8dda9c ILT |
3154 | s = "xori"; |
3155 | s2 = "xor"; | |
3156 | do_bit: | |
3157 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3158 | { |
6e8dda9c | 3159 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3160 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3161 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3162 | else |
670a50eb | 3163 | { |
0dd2d296 ILT |
3164 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3165 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3166 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3167 | treg, treg, 0); |
3d3c5039 | 3168 | } |
6e8dda9c | 3169 | return; |
3d3c5039 | 3170 | } |
6e8dda9c | 3171 | |
d8a1c247 | 3172 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3173 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3174 | break; |
3d3c5039 ILT |
3175 | |
3176 | case M_BEQ_I: | |
8358c818 ILT |
3177 | s = "beq"; |
3178 | goto beq_i; | |
3179 | case M_BEQL_I: | |
3180 | s = "beql"; | |
3181 | likely = 1; | |
3182 | goto beq_i; | |
3d3c5039 | 3183 | case M_BNE_I: |
8358c818 ILT |
3184 | s = "bne"; |
3185 | goto beq_i; | |
3186 | case M_BNEL_I: | |
3187 | s = "bnel"; | |
3188 | likely = 1; | |
3189 | beq_i: | |
670a50eb ILT |
3190 | if (imm_expr.X_add_number == 0) |
3191 | { | |
0dd2d296 ILT |
3192 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3193 | 0); | |
670a50eb ILT |
3194 | return; |
3195 | } | |
d8a1c247 | 3196 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3197 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3198 | break; |
3d3c5039 | 3199 | |
8358c818 ILT |
3200 | case M_BGEL: |
3201 | likely = 1; | |
3d3c5039 | 3202 | case M_BGE: |
670a50eb ILT |
3203 | if (treg == 0) |
3204 | { | |
0dd2d296 | 3205 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3206 | likely ? "bgezl" : "bgez", |
3207 | "s,p", sreg); | |
670a50eb | 3208 | return; |
3d3c5039 | 3209 | } |
9a7d824a ILT |
3210 | if (sreg == 0) |
3211 | { | |
0dd2d296 | 3212 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3213 | likely ? "blezl" : "blez", |
3214 | "s,p", treg); | |
9a7d824a ILT |
3215 | return; |
3216 | } | |
0dd2d296 ILT |
3217 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3218 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3219 | likely ? "beql" : "beq", |
3220 | "s,t,p", AT, 0); | |
670a50eb | 3221 | break; |
3d3c5039 | 3222 | |
8358c818 ILT |
3223 | case M_BGTL_I: |
3224 | likely = 1; | |
3d3c5039 | 3225 | case M_BGT_I: |
9a7d824a | 3226 | /* check for > max integer */ |
6e8dda9c ILT |
3227 | maxnum = 0x7fffffff; |
3228 | if (mips_isa >= 3) | |
3229 | { | |
3230 | maxnum <<= 16; | |
3231 | maxnum |= 0xffff; | |
3232 | maxnum <<= 16; | |
3233 | maxnum |= 0xffff; | |
3234 | } | |
7b777690 ILT |
3235 | if (imm_expr.X_add_number >= maxnum |
3236 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3237 | { |
3238 | do_false: | |
3239 | /* result is always false */ | |
8358c818 ILT |
3240 | if (! likely) |
3241 | { | |
3242 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3243 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3244 | } |
3245 | else | |
3246 | { | |
3247 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3248 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3249 | "s,t,p", 0, 0); | |
8358c818 | 3250 | } |
9a7d824a ILT |
3251 | return; |
3252 | } | |
670a50eb ILT |
3253 | imm_expr.X_add_number++; |
3254 | /* FALLTHROUGH */ | |
3d3c5039 | 3255 | case M_BGE_I: |
8358c818 ILT |
3256 | case M_BGEL_I: |
3257 | if (mask == M_BGEL_I) | |
3258 | likely = 1; | |
670a50eb ILT |
3259 | if (imm_expr.X_add_number == 0) |
3260 | { | |
0dd2d296 | 3261 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3262 | likely ? "bgezl" : "bgez", |
3263 | "s,p", sreg); | |
670a50eb | 3264 | return; |
3d3c5039 | 3265 | } |
670a50eb ILT |
3266 | if (imm_expr.X_add_number == 1) |
3267 | { | |
0dd2d296 | 3268 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3269 | likely ? "bgtzl" : "bgtz", |
3270 | "s,p", sreg); | |
670a50eb | 3271 | return; |
3d3c5039 | 3272 | } |
6e8dda9c ILT |
3273 | maxnum = 0x7fffffff; |
3274 | if (mips_isa >= 3) | |
3275 | { | |
3276 | maxnum <<= 16; | |
3277 | maxnum |= 0xffff; | |
3278 | maxnum <<= 16; | |
3279 | maxnum |= 0xffff; | |
3280 | } | |
3281 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3282 | if (imm_expr.X_add_number <= maxnum |
3283 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3284 | { |
3285 | do_true: | |
3286 | /* result is always true */ | |
3287 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3288 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3289 | return; |
3290 | } | |
6e8dda9c | 3291 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3292 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3293 | likely ? "beql" : "beq", |
3294 | "s,t,p", AT, 0); | |
670a50eb | 3295 | break; |
3d3c5039 | 3296 | |
8358c818 ILT |
3297 | case M_BGEUL: |
3298 | likely = 1; | |
3d3c5039 | 3299 | case M_BGEU: |
670a50eb | 3300 | if (treg == 0) |
9a7d824a ILT |
3301 | goto do_true; |
3302 | if (sreg == 0) | |
670a50eb | 3303 | { |
0dd2d296 | 3304 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3305 | likely ? "beql" : "beq", |
3306 | "s,t,p", 0, treg); | |
670a50eb | 3307 | return; |
3d3c5039 | 3308 | } |
0dd2d296 ILT |
3309 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3310 | treg); | |
3311 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3312 | likely ? "beql" : "beq", |
3313 | "s,t,p", AT, 0); | |
670a50eb | 3314 | break; |
3d3c5039 | 3315 | |
8358c818 ILT |
3316 | case M_BGTUL_I: |
3317 | likely = 1; | |
9a7d824a | 3318 | case M_BGTU_I: |
6e8dda9c | 3319 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3320 | goto do_false; |
3321 | imm_expr.X_add_number++; | |
3322 | /* FALLTHROUGH */ | |
3d3c5039 | 3323 | case M_BGEU_I: |
8358c818 ILT |
3324 | case M_BGEUL_I: |
3325 | if (mask == M_BGEUL_I) | |
3326 | likely = 1; | |
670a50eb | 3327 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3328 | goto do_true; |
670a50eb ILT |
3329 | if (imm_expr.X_add_number == 1) |
3330 | { | |
0dd2d296 | 3331 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3332 | likely ? "bnel" : "bne", |
3333 | "s,t,p", sreg, 0); | |
670a50eb | 3334 | return; |
3d3c5039 | 3335 | } |
6e8dda9c | 3336 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3337 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3338 | likely ? "beql" : "beq", |
3339 | "s,t,p", AT, 0); | |
670a50eb | 3340 | break; |
3d3c5039 | 3341 | |
8358c818 ILT |
3342 | case M_BGTL: |
3343 | likely = 1; | |
3d3c5039 | 3344 | case M_BGT: |
670a50eb ILT |
3345 | if (treg == 0) |
3346 | { | |
0dd2d296 | 3347 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3348 | likely ? "bgtzl" : "bgtz", |
3349 | "s,p", sreg); | |
670a50eb | 3350 | return; |
3d3c5039 | 3351 | } |
9a7d824a ILT |
3352 | if (sreg == 0) |
3353 | { | |
0dd2d296 | 3354 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3355 | likely ? "bltzl" : "bltz", |
3356 | "s,p", treg); | |
9a7d824a ILT |
3357 | return; |
3358 | } | |
0dd2d296 ILT |
3359 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3360 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3361 | likely ? "bnel" : "bne", |
3362 | "s,t,p", AT, 0); | |
670a50eb | 3363 | break; |
3d3c5039 | 3364 | |
8358c818 ILT |
3365 | case M_BGTUL: |
3366 | likely = 1; | |
3d3c5039 | 3367 | case M_BGTU: |
670a50eb ILT |
3368 | if (treg == 0) |
3369 | { | |
0dd2d296 | 3370 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3371 | likely ? "bnel" : "bne", |
3372 | "s,t,p", sreg, 0); | |
670a50eb | 3373 | return; |
3d3c5039 | 3374 | } |
9a7d824a ILT |
3375 | if (sreg == 0) |
3376 | goto do_false; | |
0dd2d296 ILT |
3377 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3378 | sreg); | |
3379 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3380 | likely ? "bnel" : "bne", |
3381 | "s,t,p", AT, 0); | |
670a50eb | 3382 | break; |
3d3c5039 | 3383 | |
8358c818 ILT |
3384 | case M_BLEL: |
3385 | likely = 1; | |
3d3c5039 | 3386 | case M_BLE: |
670a50eb ILT |
3387 | if (treg == 0) |
3388 | { | |
0dd2d296 | 3389 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3390 | likely ? "blezl" : "blez", |
3391 | "s,p", sreg); | |
670a50eb ILT |
3392 | return; |
3393 | } | |
9a7d824a ILT |
3394 | if (sreg == 0) |
3395 | { | |
0dd2d296 | 3396 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3397 | likely ? "bgezl" : "bgez", |
3398 | "s,p", treg); | |
9a7d824a ILT |
3399 | return; |
3400 | } | |
0dd2d296 ILT |
3401 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3402 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3403 | likely ? "beql" : "beq", |
3404 | "s,t,p", AT, 0); | |
670a50eb | 3405 | break; |
3d3c5039 | 3406 | |
8358c818 ILT |
3407 | case M_BLEL_I: |
3408 | likely = 1; | |
3d3c5039 | 3409 | case M_BLE_I: |
6e8dda9c ILT |
3410 | maxnum = 0x7fffffff; |
3411 | if (mips_isa >= 3) | |
3412 | { | |
3413 | maxnum <<= 16; | |
3414 | maxnum |= 0xffff; | |
3415 | maxnum <<= 16; | |
3416 | maxnum |= 0xffff; | |
3417 | } | |
7b777690 ILT |
3418 | if (imm_expr.X_add_number >= maxnum |
3419 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3420 | goto do_true; |
3421 | imm_expr.X_add_number++; | |
3422 | /* FALLTHROUGH */ | |
9a7d824a | 3423 | case M_BLT_I: |
8358c818 ILT |
3424 | case M_BLTL_I: |
3425 | if (mask == M_BLTL_I) | |
3426 | likely = 1; | |
670a50eb ILT |
3427 | if (imm_expr.X_add_number == 0) |
3428 | { | |
0dd2d296 | 3429 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3430 | likely ? "bltzl" : "bltz", |
3431 | "s,p", sreg); | |
670a50eb ILT |
3432 | return; |
3433 | } | |
9a7d824a | 3434 | if (imm_expr.X_add_number == 1) |
670a50eb | 3435 | { |
0dd2d296 | 3436 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3437 | likely ? "blezl" : "blez", |
3438 | "s,p", sreg); | |
670a50eb ILT |
3439 | return; |
3440 | } | |
6e8dda9c | 3441 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3442 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3443 | likely ? "bnel" : "bne", |
3444 | "s,t,p", AT, 0); | |
670a50eb | 3445 | break; |
3d3c5039 | 3446 | |
8358c818 ILT |
3447 | case M_BLEUL: |
3448 | likely = 1; | |
3d3c5039 | 3449 | case M_BLEU: |
670a50eb ILT |
3450 | if (treg == 0) |
3451 | { | |
0dd2d296 | 3452 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3453 | likely ? "beql" : "beq", |
3454 | "s,t,p", sreg, 0); | |
670a50eb | 3455 | return; |
3d3c5039 | 3456 | } |
9a7d824a ILT |
3457 | if (sreg == 0) |
3458 | goto do_true; | |
0dd2d296 ILT |
3459 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3460 | sreg); | |
3461 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3462 | likely ? "beql" : "beq", |
3463 | "s,t,p", AT, 0); | |
670a50eb | 3464 | break; |
3d3c5039 | 3465 | |
8358c818 ILT |
3466 | case M_BLEUL_I: |
3467 | likely = 1; | |
3d3c5039 | 3468 | case M_BLEU_I: |
6e8dda9c | 3469 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3470 | goto do_true; |
3471 | imm_expr.X_add_number++; | |
3472 | /* FALLTHROUGH */ | |
9a7d824a | 3473 | case M_BLTU_I: |
8358c818 ILT |
3474 | case M_BLTUL_I: |
3475 | if (mask == M_BLTUL_I) | |
3476 | likely = 1; | |
670a50eb | 3477 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3478 | goto do_false; |
3479 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3480 | { |
0dd2d296 | 3481 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3482 | likely ? "beql" : "beq", |
3483 | "s,t,p", sreg, 0); | |
670a50eb | 3484 | return; |
3d3c5039 | 3485 | } |
6e8dda9c | 3486 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3487 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3488 | likely ? "bnel" : "bne", |
3489 | "s,t,p", AT, 0); | |
670a50eb | 3490 | break; |
3d3c5039 | 3491 | |
8358c818 ILT |
3492 | case M_BLTL: |
3493 | likely = 1; | |
3d3c5039 | 3494 | case M_BLT: |
670a50eb ILT |
3495 | if (treg == 0) |
3496 | { | |
0dd2d296 | 3497 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3498 | likely ? "bltzl" : "bltz", |
3499 | "s,p", sreg); | |
670a50eb | 3500 | return; |
3d3c5039 | 3501 | } |
9a7d824a | 3502 | if (sreg == 0) |
670a50eb | 3503 | { |
0dd2d296 | 3504 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3505 | likely ? "bgtzl" : "bgtz", |
3506 | "s,p", treg); | |
670a50eb | 3507 | return; |
3d3c5039 | 3508 | } |
0dd2d296 ILT |
3509 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3510 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3511 | likely ? "bnel" : "bne", |
3512 | "s,t,p", AT, 0); | |
670a50eb | 3513 | break; |
3d3c5039 | 3514 | |
8358c818 ILT |
3515 | case M_BLTUL: |
3516 | likely = 1; | |
3d3c5039 | 3517 | case M_BLTU: |
670a50eb | 3518 | if (treg == 0) |
9a7d824a ILT |
3519 | goto do_false; |
3520 | if (sreg == 0) | |
670a50eb | 3521 | { |
0dd2d296 | 3522 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3523 | likely ? "bnel" : "bne", |
3524 | "s,t,p", 0, treg); | |
670a50eb ILT |
3525 | return; |
3526 | } | |
0dd2d296 ILT |
3527 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3528 | treg); | |
3529 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3530 | likely ? "bnel" : "bne", |
3531 | "s,t,p", AT, 0); | |
670a50eb | 3532 | break; |
3d3c5039 | 3533 | |
8358c818 ILT |
3534 | case M_DDIV_3: |
3535 | dbl = 1; | |
3d3c5039 | 3536 | case M_DIV_3: |
8358c818 ILT |
3537 | s = "mflo"; |
3538 | goto do_div3; | |
3539 | case M_DREM_3: | |
3540 | dbl = 1; | |
3d3c5039 | 3541 | case M_REM_3: |
8358c818 ILT |
3542 | s = "mfhi"; |
3543 | do_div3: | |
670a50eb ILT |
3544 | if (treg == 0) |
3545 | { | |
3546 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3547 | if (mips_trap) |
3548 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3549 | else | |
3550 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3551 | return; |
3552 | } | |
3553 | ||
fbcfacb7 | 3554 | mips_emit_delays (true); |
becfe05e | 3555 | ++mips_noreorder; |
0dd2d296 ILT |
3556 | mips_any_noreorder = 1; |
3557 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3558 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3559 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3560 | if (mips_trap) |
3561 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3562 | else | |
3563 | { | |
3564 | expr1.X_add_number = 8; | |
3565 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3566 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3567 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3568 | } | |
670a50eb | 3569 | expr1.X_add_number = -1; |
0dd2d296 | 3570 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3571 | dbl ? "daddiu" : "addiu", |
9226253a | 3572 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3573 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3574 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3575 | if (dbl) |
3576 | { | |
3577 | expr1.X_add_number = 1; | |
0dd2d296 | 3578 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3579 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3580 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3581 | 31); | |
8358c818 ILT |
3582 | } |
3583 | else | |
3584 | { | |
3585 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3586 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3587 | (int) BFD_RELOC_HI16); | |
8358c818 | 3588 | } |
8ea7f4e8 ILT |
3589 | if (mips_trap) |
3590 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3591 | else | |
3592 | { | |
3593 | expr1.X_add_number = 8; | |
3594 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3595 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3596 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3597 | } | |
becfe05e | 3598 | --mips_noreorder; |
0dd2d296 | 3599 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3600 | break; |
3d3c5039 ILT |
3601 | |
3602 | case M_DIV_3I: | |
8358c818 ILT |
3603 | s = "div"; |
3604 | s2 = "mflo"; | |
3605 | goto do_divi; | |
3d3c5039 | 3606 | case M_DIVU_3I: |
8358c818 ILT |
3607 | s = "divu"; |
3608 | s2 = "mflo"; | |
3609 | goto do_divi; | |
3d3c5039 | 3610 | case M_REM_3I: |
8358c818 ILT |
3611 | s = "div"; |
3612 | s2 = "mfhi"; | |
3613 | goto do_divi; | |
3d3c5039 | 3614 | case M_REMU_3I: |
8358c818 ILT |
3615 | s = "divu"; |
3616 | s2 = "mfhi"; | |
3617 | goto do_divi; | |
3618 | case M_DDIV_3I: | |
3619 | dbl = 1; | |
3620 | s = "ddiv"; | |
3621 | s2 = "mflo"; | |
3622 | goto do_divi; | |
3623 | case M_DDIVU_3I: | |
3624 | dbl = 1; | |
3625 | s = "ddivu"; | |
3626 | s2 = "mflo"; | |
3627 | goto do_divi; | |
3628 | case M_DREM_3I: | |
3629 | dbl = 1; | |
3630 | s = "ddiv"; | |
3631 | s2 = "mfhi"; | |
3632 | goto do_divi; | |
3633 | case M_DREMU_3I: | |
3634 | dbl = 1; | |
3635 | s = "ddivu"; | |
3636 | s2 = "mfhi"; | |
3637 | do_divi: | |
670a50eb ILT |
3638 | if (imm_expr.X_add_number == 0) |
3639 | { | |
3640 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3641 | if (mips_trap) |
3642 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3643 | else | |
3644 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3645 | return; |
3646 | } | |
3647 | if (imm_expr.X_add_number == 1) | |
3648 | { | |
8358c818 | 3649 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3650 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3651 | sreg); | |
3d3c5039 | 3652 | else |
0dd2d296 | 3653 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3654 | return; |
3655 | } | |
8358c818 ILT |
3656 | if (imm_expr.X_add_number == -1 |
3657 | && s[strlen (s) - 1] != 'u') | |
3658 | { | |
3659 | if (strcmp (s2, "mflo") == 0) | |
3660 | { | |
3661 | if (dbl) | |
0dd2d296 ILT |
3662 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3663 | sreg); | |
8358c818 | 3664 | else |
0dd2d296 ILT |
3665 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3666 | sreg); | |
8358c818 ILT |
3667 | } |
3668 | else | |
0dd2d296 | 3669 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3670 | return; |
3671 | } | |
3d3c5039 | 3672 | |
d8a1c247 | 3673 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3674 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3675 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3676 | break; |
3677 | ||
3678 | case M_DIVU_3: | |
8358c818 ILT |
3679 | s = "divu"; |
3680 | s2 = "mflo"; | |
3681 | goto do_divu3; | |
670a50eb | 3682 | case M_REMU_3: |
8358c818 ILT |
3683 | s = "divu"; |
3684 | s2 = "mfhi"; | |
3685 | goto do_divu3; | |
3686 | case M_DDIVU_3: | |
3687 | s = "ddivu"; | |
3688 | s2 = "mflo"; | |
3689 | goto do_divu3; | |
3690 | case M_DREMU_3: | |
3691 | s = "ddivu"; | |
3692 | s2 = "mfhi"; | |
3693 | do_divu3: | |
fbcfacb7 | 3694 | mips_emit_delays (true); |
becfe05e | 3695 | ++mips_noreorder; |
0dd2d296 ILT |
3696 | mips_any_noreorder = 1; |
3697 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3698 | if (mips_trap) |
3699 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3700 | else | |
3701 | { | |
3702 | expr1.X_add_number = 8; | |
3703 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3704 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3705 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3706 | } | |
becfe05e | 3707 | --mips_noreorder; |
0dd2d296 | 3708 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3709 | return; |
3d3c5039 | 3710 | |
d8a1c247 KR |
3711 | case M_DLA_AB: |
3712 | dbl = 1; | |
0dd2d296 | 3713 | case M_LA_AB: |
d9aba805 ILT |
3714 | /* Load the address of a symbol into a register. If breg is not |
3715 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3716 | |
3717 | /* When generating embedded PIC code, we permit expressions of | |
3718 | the form | |
3719 | la $4,foo-bar | |
3720 | where bar is an address in the .text section. These are used | |
3721 | when getting the addresses of functions. We don't permit | |
3722 | X_add_number to be non-zero, because if the symbol is | |
3723 | external the relaxing code needs to know that any addend is | |
3724 | purely the offset to X_op_symbol. */ | |
3725 | if (mips_pic == EMBEDDED_PIC | |
3726 | && offset_expr.X_op == O_subtract | |
3727 | && now_seg == text_section | |
847a01cd ILT |
3728 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3729 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3730 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3731 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3732 | ->sy_value.X_add_symbol) | |
3733 | == text_section))) | |
ecd4ca1c ILT |
3734 | && breg == 0 |
3735 | && offset_expr.X_add_number == 0) | |
3736 | { | |
3737 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3738 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3739 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3740 | mips_isa < 3 ? "addiu" : "daddiu", | |
3741 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3742 | return; | |
3743 | } | |
3744 | ||
0dd2d296 ILT |
3745 | if (offset_expr.X_op != O_symbol |
3746 | && offset_expr.X_op != O_constant) | |
670a50eb | 3747 | { |
0dd2d296 ILT |
3748 | as_bad ("expression too complex"); |
3749 | offset_expr.X_op = O_constant; | |
3750 | } | |
3751 | ||
3752 | if (treg == breg) | |
3753 | { | |
3754 | tempreg = AT; | |
3755 | used_at = 1; | |
3d3c5039 | 3756 | } |
670a50eb ILT |
3757 | else |
3758 | { | |
0dd2d296 ILT |
3759 | tempreg = treg; |
3760 | used_at = 0; | |
670a50eb | 3761 | } |
3d3c5039 | 3762 | |
5ac34ac3 | 3763 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3764 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3765 | else if (mips_pic == NO_PIC) |
670a50eb | 3766 | { |
0dd2d296 ILT |
3767 | /* If this is a reference to an GP relative symbol, we want |
3768 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3769 | Otherwise we want | |
3770 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3771 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3772 | If we have a constant, we need two instructions anyhow, | |
3773 | so we may as well always use the latter form. */ | |
7a15a226 | 3774 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3775 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3776 | p = NULL; |
3777 | else | |
3778 | { | |
8ea7f4e8 | 3779 | frag_grow (20); |
0dd2d296 ILT |
3780 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3781 | mips_isa < 3 ? "addiu" : "daddiu", | |
3782 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3783 | p = frag_var (rs_machine_dependent, 8, 0, | |
3784 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3785 | mips_warn_about_macros), | |
3786 | offset_expr.X_add_symbol, (long) 0, | |
3787 | (char *) NULL); | |
3788 | } | |
3789 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3790 | if (p != NULL) | |
3791 | p += 4; | |
3792 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3793 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3794 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3795 | } | |
fb251650 | 3796 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3797 | { |
3798 | /* If this is a reference to an external symbol, and there | |
3799 | is no constant, we want | |
3800 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3801 | For a local symbol, we want | |
3802 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3803 | nop | |
3804 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3805 | ||
3806 | If we have a small constant, and this is a reference to | |
3807 | an external symbol, we want | |
3808 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3809 | nop | |
3810 | addiu $tempreg,$tempreg,<constant> | |
3811 | For a local symbol, we want the same instruction | |
3812 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3813 | addiu instruction. | |
3814 | ||
3815 | If we have a large constant, and this is a reference to | |
3816 | an external symbol, we want | |
3817 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3818 | lui $at,<hiconstant> | |
3819 | addiu $at,$at,<loconstant> | |
3820 | addu $tempreg,$tempreg,$at | |
3821 | For a local symbol, we want the same instruction | |
3822 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3823 | addiu instruction. */ | |
3824 | expr1.X_add_number = offset_expr.X_add_number; | |
3825 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3826 | frag_grow (32); |
0dd2d296 | 3827 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3828 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3829 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3830 | if (expr1.X_add_number == 0) | |
3831 | { | |
3832 | int off; | |
3833 | ||
3834 | if (breg == 0) | |
3835 | off = 0; | |
3836 | else | |
3837 | { | |
3838 | /* We're going to put in an addu instruction using | |
3839 | tempreg, so we may as well insert the nop right | |
3840 | now. */ | |
3841 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3842 | "nop", ""); | |
3843 | off = 4; | |
3844 | } | |
3845 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3846 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3847 | (breg == 0 | |
3848 | ? mips_warn_about_macros | |
3849 | : 0)), | |
3850 | offset_expr.X_add_symbol, (long) 0, | |
3851 | (char *) NULL); | |
3852 | if (breg == 0) | |
3853 | { | |
3854 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3855 | p += 4; | |
3856 | } | |
3857 | macro_build (p, &icnt, &expr1, | |
3858 | mips_isa < 3 ? "addiu" : "daddiu", | |
3859 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3860 | /* FIXME: If breg == 0, and the next instruction uses | |
3861 | $tempreg, then if this variant case is used an extra | |
3862 | nop will be generated. */ | |
3863 | } | |
3864 | else if (expr1.X_add_number >= -0x8000 | |
3865 | && expr1.X_add_number < 0x8000) | |
3866 | { | |
3867 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3868 | "nop", ""); | |
3869 | macro_build ((char *) NULL, &icnt, &expr1, | |
3870 | mips_isa < 3 ? "addiu" : "daddiu", | |
3871 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3872 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3873 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3874 | offset_expr.X_add_symbol, (long) 0, | |
3875 | (char *) NULL); | |
3876 | } | |
3877 | else | |
3878 | { | |
3879 | int off1; | |
3880 | ||
3881 | /* If we are going to add in a base register, and the | |
3882 | target register and the base register are the same, | |
3883 | then we are using AT as a temporary register. Since | |
3884 | we want to load the constant into AT, we add our | |
3885 | current AT (from the global offset table) and the | |
3886 | register into the register now, and pretend we were | |
3887 | not using a base register. */ | |
3888 | if (breg != treg) | |
3889 | off1 = 0; | |
3890 | else | |
3891 | { | |
3892 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3893 | "nop", ""); | |
3894 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3895 | mips_isa < 3 ? "addu" : "daddu", | |
3896 | "d,v,t", treg, AT, breg); | |
3897 | breg = 0; | |
3898 | tempreg = treg; | |
3899 | off1 = -8; | |
3900 | } | |
3901 | ||
55933a58 ILT |
3902 | /* Set mips_optimize around the lui instruction to avoid |
3903 | inserting an unnecessary nop after the lw. */ | |
3904 | hold_mips_optimize = mips_optimize; | |
3905 | mips_optimize = 2; | |
0dd2d296 | 3906 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3907 | mips_optimize = hold_mips_optimize; |
3908 | ||
0dd2d296 ILT |
3909 | macro_build ((char *) NULL, &icnt, &expr1, |
3910 | mips_isa < 3 ? "addiu" : "daddiu", | |
3911 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3912 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3913 | mips_isa < 3 ? "addu" : "daddu", | |
3914 | "d,v,t", tempreg, tempreg, AT); | |
3915 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3916 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3917 | offset_expr.X_add_symbol, (long) 0, | |
3918 | (char *) NULL); | |
3919 | used_at = 1; | |
3920 | } | |
670a50eb | 3921 | } |
fb251650 ILT |
3922 | else if (mips_pic == SVR4_PIC) |
3923 | { | |
3924 | int gpdel; | |
3925 | ||
3926 | /* This is the large GOT case. If this is a reference to an | |
3927 | external symbol, and there is no constant, we want | |
3928 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3929 | addu $tempreg,$tempreg,$gp | |
3930 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3931 | For a local symbol, we want | |
3932 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3933 | nop | |
3934 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3935 | ||
3936 | If we have a small constant, and this is a reference to | |
3937 | an external symbol, we want | |
3938 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3939 | addu $tempreg,$tempreg,$gp | |
3940 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3941 | nop | |
3942 | addiu $tempreg,$tempreg,<constant> | |
3943 | For a local symbol, we want | |
3944 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3945 | nop | |
3946 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3947 | ||
3948 | If we have a large constant, and this is a reference to | |
3949 | an external symbol, we want | |
3950 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3951 | addu $tempreg,$tempreg,$gp | |
3952 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3953 | lui $at,<hiconstant> | |
3954 | addiu $at,$at,<loconstant> | |
3955 | addu $tempreg,$tempreg,$at | |
3956 | For a local symbol, we want | |
3957 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3958 | lui $at,<hiconstant> | |
3959 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3960 | addu $tempreg,$tempreg,$at | |
3961 | */ | |
3962 | expr1.X_add_number = offset_expr.X_add_number; | |
3963 | offset_expr.X_add_number = 0; | |
3964 | frag_grow (52); | |
3965 | if (reg_needs_delay (GP)) | |
3966 | gpdel = 4; | |
3967 | else | |
3968 | gpdel = 0; | |
3969 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3970 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3971 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3972 | mips_isa < 3 ? "addu" : "daddu", | |
3973 | "d,v,t", tempreg, tempreg, GP); | |
3974 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3975 | dbl ? "ld" : "lw", | |
3976 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3977 | tempreg); | |
3978 | if (expr1.X_add_number == 0) | |
3979 | { | |
3980 | int off; | |
3981 | ||
3982 | if (breg == 0) | |
3983 | off = 0; | |
3984 | else | |
3985 | { | |
3986 | /* We're going to put in an addu instruction using | |
3987 | tempreg, so we may as well insert the nop right | |
3988 | now. */ | |
3989 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3990 | "nop", ""); | |
3991 | off = 4; | |
3992 | } | |
3993 | ||
3994 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3995 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3996 | 8 + gpdel, 0, | |
3997 | (breg == 0 | |
3998 | ? mips_warn_about_macros | |
3999 | : 0)), | |
4000 | offset_expr.X_add_symbol, (long) 0, | |
4001 | (char *) NULL); | |
4002 | } | |
4003 | else if (expr1.X_add_number >= -0x8000 | |
4004 | && expr1.X_add_number < 0x8000) | |
4005 | { | |
4006 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4007 | "nop", ""); | |
4008 | macro_build ((char *) NULL, &icnt, &expr1, | |
4009 | mips_isa < 3 ? "addiu" : "daddiu", | |
4010 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4011 | ||
4012 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4013 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4014 | (breg == 0 | |
4015 | ? mips_warn_about_macros | |
4016 | : 0)), | |
4017 | offset_expr.X_add_symbol, (long) 0, | |
4018 | (char *) NULL); | |
4019 | } | |
4020 | else | |
4021 | { | |
4022 | int adj, dreg; | |
4023 | ||
4024 | /* If we are going to add in a base register, and the | |
4025 | target register and the base register are the same, | |
4026 | then we are using AT as a temporary register. Since | |
4027 | we want to load the constant into AT, we add our | |
4028 | current AT (from the global offset table) and the | |
4029 | register into the register now, and pretend we were | |
4030 | not using a base register. */ | |
4031 | if (breg != treg) | |
4032 | { | |
4033 | adj = 0; | |
4034 | dreg = tempreg; | |
4035 | } | |
4036 | else | |
4037 | { | |
4038 | assert (tempreg == AT); | |
4039 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4040 | "nop", ""); | |
4041 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4042 | mips_isa < 3 ? "addu" : "daddu", | |
4043 | "d,v,t", treg, AT, breg); | |
4044 | dreg = treg; | |
4045 | adj = 8; | |
4046 | } | |
4047 | ||
4048 | /* Set mips_optimize around the lui instruction to avoid | |
4049 | inserting an unnecessary nop after the lw. */ | |
4050 | hold_mips_optimize = mips_optimize; | |
4051 | mips_optimize = 2; | |
4052 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4053 | mips_optimize = hold_mips_optimize; | |
4054 | ||
4055 | macro_build ((char *) NULL, &icnt, &expr1, | |
4056 | mips_isa < 3 ? "addiu" : "daddiu", | |
4057 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4058 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4059 | mips_isa < 3 ? "addu" : "daddu", | |
4060 | "d,v,t", dreg, dreg, AT); | |
4061 | ||
4062 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4063 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4064 | 8 + gpdel, 0, | |
4065 | (breg == 0 | |
4066 | ? mips_warn_about_macros | |
4067 | : 0)), | |
4068 | offset_expr.X_add_symbol, (long) 0, | |
4069 | (char *) NULL); | |
4070 | ||
4071 | used_at = 1; | |
4072 | } | |
4073 | ||
4074 | if (gpdel > 0) | |
4075 | { | |
4076 | /* This is needed because this instruction uses $gp, but | |
4077 | the first instruction on the main stream does not. */ | |
4078 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4079 | p += 4; | |
4080 | } | |
4081 | macro_build (p, &icnt, &offset_expr, | |
4082 | dbl ? "ld" : "lw", | |
4083 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4084 | p += 4; | |
4085 | if (expr1.X_add_number >= -0x8000 | |
4086 | && expr1.X_add_number < 0x8000) | |
4087 | { | |
4088 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4089 | p += 4; | |
4090 | macro_build (p, &icnt, &expr1, | |
4091 | mips_isa < 3 ? "addiu" : "daddiu", | |
4092 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4093 | /* FIXME: If add_number is 0, and there was no base | |
4094 | register, the external symbol case ended with a load, | |
4095 | so if the symbol turns out to not be external, and | |
4096 | the next instruction uses tempreg, an unnecessary nop | |
4097 | will be inserted. */ | |
4098 | } | |
4099 | else | |
4100 | { | |
4101 | if (breg == treg) | |
4102 | { | |
4103 | /* We must add in the base register now, as in the | |
4104 | external symbol case. */ | |
4105 | assert (tempreg == AT); | |
4106 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4107 | p += 4; | |
4108 | macro_build (p, &icnt, (expressionS *) NULL, | |
4109 | mips_isa < 3 ? "addu" : "daddu", | |
4110 | "d,v,t", treg, AT, breg); | |
4111 | p += 4; | |
4112 | tempreg = treg; | |
4113 | /* We set breg to 0 because we have arranged to add | |
4114 | it in in both cases. */ | |
4115 | breg = 0; | |
4116 | } | |
4117 | ||
4118 | macro_build_lui (p, &icnt, &expr1, AT); | |
4119 | p += 4; | |
4120 | macro_build (p, &icnt, &expr1, | |
4121 | mips_isa < 3 ? "addiu" : "daddiu", | |
4122 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4123 | p += 4; | |
4124 | macro_build (p, &icnt, (expressionS *) NULL, | |
4125 | mips_isa < 3 ? "addu" : "daddu", | |
4126 | "d,v,t", tempreg, tempreg, AT); | |
4127 | p += 4; | |
4128 | } | |
4129 | } | |
d9aba805 ILT |
4130 | else if (mips_pic == EMBEDDED_PIC) |
4131 | { | |
4132 | /* We use | |
4133 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4134 | */ | |
4135 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4136 | mips_isa < 3 ? "addiu" : "daddiu", | |
4137 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4138 | } | |
4139 | else | |
4140 | abort (); | |
0dd2d296 | 4141 | |
670a50eb | 4142 | if (breg != 0) |
0dd2d296 ILT |
4143 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4144 | mips_isa < 3 ? "addu" : "daddu", | |
4145 | "d,v,t", treg, tempreg, breg); | |
4146 | ||
4147 | if (! used_at) | |
4148 | return; | |
4149 | ||
4150 | break; | |
4151 | ||
4152 | case M_J_A: | |
4153 | /* The j instruction may not be used in PIC code, since it | |
4154 | requires an absolute address. We convert it to a b | |
4155 | instruction. */ | |
d9aba805 | 4156 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4157 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4158 | else | |
4159 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4160 | return; |
3d3c5039 | 4161 | |
9226253a ILT |
4162 | /* The jal instructions must be handled as macros because when |
4163 | generating PIC code they expand to multi-instruction | |
4164 | sequences. Normally they are simple instructions. */ | |
4165 | case M_JAL_1: | |
4166 | dreg = RA; | |
4167 | /* Fall through. */ | |
4168 | case M_JAL_2: | |
d9aba805 ILT |
4169 | if (mips_pic == NO_PIC |
4170 | || mips_pic == EMBEDDED_PIC) | |
4171 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4172 | "d,s", dreg, sreg); | |
4173 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4174 | { |
d9aba805 ILT |
4175 | if (sreg != PIC_CALL_REG) |
4176 | as_warn ("MIPS PIC call to register other than $25"); | |
4177 | ||
0dd2d296 ILT |
4178 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4179 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4180 | if (mips_cprestore_offset < 0) |
4181 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4182 | else | |
4183 | { | |
4184 | expr1.X_add_number = mips_cprestore_offset; | |
4185 | macro_build ((char *) NULL, &icnt, &expr1, | |
4186 | mips_isa < 3 ? "lw" : "ld", | |
4187 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4188 | } | |
9226253a | 4189 | } |
0dd2d296 | 4190 | else |
d9aba805 ILT |
4191 | abort (); |
4192 | ||
9226253a ILT |
4193 | return; |
4194 | ||
4195 | case M_JAL_A: | |
d9aba805 ILT |
4196 | if (mips_pic == NO_PIC) |
4197 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4198 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4199 | { |
fb251650 ILT |
4200 | /* If this is a reference to an external symbol, and we are |
4201 | using a small GOT, we want | |
d9aba805 ILT |
4202 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4203 | nop | |
4204 | jalr $25 | |
4205 | nop | |
4206 | lw $gp,cprestore($sp) | |
4207 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4208 | pseudo-op. If we are using a big GOT, we want |
4209 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4210 | addu $25,$25,$gp | |
4211 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4212 | nop | |
4213 | jalr $25 | |
4214 | nop | |
4215 | lw $gp,cprestore($sp) | |
4216 | If the symbol is not external, we want | |
d9aba805 ILT |
4217 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4218 | nop | |
4219 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4220 | jalr $25 | |
4221 | nop | |
fb251650 ILT |
4222 | lw $gp,cprestore($sp) */ |
4223 | frag_grow (40); | |
4224 | if (! mips_big_got) | |
4225 | { | |
4226 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4227 | mips_isa < 3 ? "lw" : "ld", | |
4228 | "t,o(b)", PIC_CALL_REG, | |
4229 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4230 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4231 | "nop", ""); | |
4232 | p = frag_var (rs_machine_dependent, 4, 0, | |
4233 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4234 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4235 | } | |
4236 | else | |
4237 | { | |
4238 | int gpdel; | |
4239 | ||
4240 | if (reg_needs_delay (GP)) | |
4241 | gpdel = 4; | |
4242 | else | |
4243 | gpdel = 0; | |
4244 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4245 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4246 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4247 | mips_isa < 3 ? "addu" : "daddu", | |
4248 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4249 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4250 | mips_isa < 3 ? "lw" : "ld", | |
4251 | "t,o(b)", PIC_CALL_REG, | |
4252 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4254 | "nop", ""); | |
4255 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4256 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4257 | 0, 0), | |
4258 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4259 | if (gpdel > 0) | |
4260 | { | |
4261 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4262 | p += 4; | |
4263 | } | |
4264 | macro_build (p, &icnt, &offset_expr, | |
4265 | mips_isa < 3 ? "lw" : "ld", | |
4266 | "t,o(b)", PIC_CALL_REG, | |
4267 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4268 | p += 4; | |
4269 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4270 | p += 4; | |
4271 | } | |
d9aba805 ILT |
4272 | macro_build (p, &icnt, &offset_expr, |
4273 | mips_isa < 3 ? "addiu" : "daddiu", | |
4274 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4275 | (int) BFD_RELOC_LO16); | |
4276 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4277 | "jalr", "s", PIC_CALL_REG); | |
4278 | if (mips_cprestore_offset < 0) | |
4279 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4280 | else | |
4281 | { | |
4282 | if (mips_noreorder) | |
4283 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4284 | "nop", ""); | |
4285 | expr1.X_add_number = mips_cprestore_offset; | |
4286 | macro_build ((char *) NULL, &icnt, &expr1, | |
4287 | mips_isa < 3 ? "lw" : "ld", | |
4288 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4289 | mips_frame_reg); | |
4290 | } | |
0dd2d296 | 4291 | } |
d9aba805 | 4292 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4293 | { |
4294 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4295 | /* The linker may expand the call to a longer sequence which | |
4296 | uses $at, so we must break rather than return. */ | |
4297 | break; | |
4298 | } | |
d9aba805 ILT |
4299 | else |
4300 | abort (); | |
4301 | ||
9226253a ILT |
4302 | return; |
4303 | ||
3d3c5039 | 4304 | case M_LB_AB: |
670a50eb ILT |
4305 | s = "lb"; |
4306 | goto ld; | |
3d3c5039 | 4307 | case M_LBU_AB: |
670a50eb ILT |
4308 | s = "lbu"; |
4309 | goto ld; | |
3d3c5039 | 4310 | case M_LH_AB: |
670a50eb ILT |
4311 | s = "lh"; |
4312 | goto ld; | |
3d3c5039 | 4313 | case M_LHU_AB: |
670a50eb ILT |
4314 | s = "lhu"; |
4315 | goto ld; | |
3d3c5039 | 4316 | case M_LW_AB: |
670a50eb ILT |
4317 | s = "lw"; |
4318 | goto ld; | |
3d3c5039 | 4319 | case M_LWC0_AB: |
670a50eb | 4320 | s = "lwc0"; |
8358c818 | 4321 | coproc = 1; |
670a50eb | 4322 | goto ld; |
3d3c5039 | 4323 | case M_LWC1_AB: |
670a50eb | 4324 | s = "lwc1"; |
8358c818 | 4325 | coproc = 1; |
670a50eb | 4326 | goto ld; |
3d3c5039 | 4327 | case M_LWC2_AB: |
670a50eb | 4328 | s = "lwc2"; |
8358c818 | 4329 | coproc = 1; |
670a50eb | 4330 | goto ld; |
3d3c5039 | 4331 | case M_LWC3_AB: |
670a50eb | 4332 | s = "lwc3"; |
8358c818 | 4333 | coproc = 1; |
670a50eb | 4334 | goto ld; |
3d3c5039 | 4335 | case M_LWL_AB: |
670a50eb | 4336 | s = "lwl"; |
b2b8c24e | 4337 | lr = 1; |
670a50eb | 4338 | goto ld; |
3d3c5039 | 4339 | case M_LWR_AB: |
670a50eb | 4340 | s = "lwr"; |
b2b8c24e | 4341 | lr = 1; |
8358c818 ILT |
4342 | goto ld; |
4343 | case M_LDC1_AB: | |
4344 | s = "ldc1"; | |
4345 | coproc = 1; | |
4346 | goto ld; | |
4347 | case M_LDC2_AB: | |
4348 | s = "ldc2"; | |
4349 | coproc = 1; | |
4350 | goto ld; | |
4351 | case M_LDC3_AB: | |
4352 | s = "ldc3"; | |
4353 | coproc = 1; | |
4354 | goto ld; | |
4355 | case M_LDL_AB: | |
4356 | s = "ldl"; | |
b2b8c24e | 4357 | lr = 1; |
8358c818 ILT |
4358 | goto ld; |
4359 | case M_LDR_AB: | |
4360 | s = "ldr"; | |
b2b8c24e | 4361 | lr = 1; |
8358c818 ILT |
4362 | goto ld; |
4363 | case M_LL_AB: | |
4364 | s = "ll"; | |
4365 | goto ld; | |
4366 | case M_LLD_AB: | |
4367 | s = "lld"; | |
4368 | goto ld; | |
4369 | case M_LWU_AB: | |
4370 | s = "lwu"; | |
3d3c5039 | 4371 | ld: |
b2b8c24e | 4372 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4373 | { |
4374 | tempreg = AT; | |
4375 | used_at = 1; | |
4376 | } | |
4377 | else | |
4378 | { | |
4379 | tempreg = treg; | |
4380 | used_at = 0; | |
4381 | } | |
4382 | goto ld_st; | |
3d3c5039 | 4383 | case M_SB_AB: |
670a50eb ILT |
4384 | s = "sb"; |
4385 | goto st; | |
3d3c5039 | 4386 | case M_SH_AB: |
670a50eb ILT |
4387 | s = "sh"; |
4388 | goto st; | |
3d3c5039 | 4389 | case M_SW_AB: |
670a50eb ILT |
4390 | s = "sw"; |
4391 | goto st; | |
3d3c5039 | 4392 | case M_SWC0_AB: |
670a50eb | 4393 | s = "swc0"; |
8358c818 | 4394 | coproc = 1; |
670a50eb | 4395 | goto st; |
3d3c5039 | 4396 | case M_SWC1_AB: |
670a50eb | 4397 | s = "swc1"; |
8358c818 | 4398 | coproc = 1; |
670a50eb | 4399 | goto st; |
3d3c5039 | 4400 | case M_SWC2_AB: |
670a50eb | 4401 | s = "swc2"; |
8358c818 | 4402 | coproc = 1; |
670a50eb | 4403 | goto st; |
3d3c5039 | 4404 | case M_SWC3_AB: |
670a50eb | 4405 | s = "swc3"; |
8358c818 | 4406 | coproc = 1; |
670a50eb | 4407 | goto st; |
3d3c5039 | 4408 | case M_SWL_AB: |
670a50eb ILT |
4409 | s = "swl"; |
4410 | goto st; | |
3d3c5039 | 4411 | case M_SWR_AB: |
670a50eb | 4412 | s = "swr"; |
8358c818 ILT |
4413 | goto st; |
4414 | case M_SC_AB: | |
4415 | s = "sc"; | |
4416 | goto st; | |
4417 | case M_SCD_AB: | |
4418 | s = "scd"; | |
4419 | goto st; | |
4420 | case M_SDC1_AB: | |
4421 | s = "sdc1"; | |
4422 | coproc = 1; | |
4423 | goto st; | |
4424 | case M_SDC2_AB: | |
4425 | s = "sdc2"; | |
4426 | coproc = 1; | |
4427 | goto st; | |
4428 | case M_SDC3_AB: | |
4429 | s = "sdc3"; | |
4430 | coproc = 1; | |
4431 | goto st; | |
4432 | case M_SDL_AB: | |
4433 | s = "sdl"; | |
4434 | goto st; | |
4435 | case M_SDR_AB: | |
4436 | s = "sdr"; | |
3d3c5039 | 4437 | st: |
670a50eb ILT |
4438 | tempreg = AT; |
4439 | used_at = 1; | |
3d3c5039 | 4440 | ld_st: |
8358c818 ILT |
4441 | if (mask == M_LWC1_AB |
4442 | || mask == M_SWC1_AB | |
8358c818 | 4443 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4444 | || mask == M_SDC1_AB |
4445 | || mask == M_L_DAB | |
4446 | || mask == M_S_DAB) | |
670a50eb | 4447 | fmt = "T,o(b)"; |
8358c818 | 4448 | else if (coproc) |
19ed8960 | 4449 | fmt = "E,o(b)"; |
670a50eb ILT |
4450 | else |
4451 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4452 | |
4453 | if (offset_expr.X_op != O_constant | |
4454 | && offset_expr.X_op != O_symbol) | |
4455 | { | |
4456 | as_bad ("expression too complex"); | |
4457 | offset_expr.X_op = O_constant; | |
4458 | } | |
4459 | ||
4460 | /* A constant expression in PIC code can be handled just as it | |
4461 | is in non PIC code. */ | |
d9aba805 | 4462 | if (mips_pic == NO_PIC |
0dd2d296 | 4463 | || offset_expr.X_op == O_constant) |
670a50eb | 4464 | { |
0dd2d296 ILT |
4465 | /* If this is a reference to a GP relative symbol, and there |
4466 | is no base register, we want | |
4467 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4468 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4469 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4470 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4471 | If we have a constant, we need two instructions anyhow, | |
4472 | so we always use the latter form. | |
4473 | ||
4474 | If we have a base register, and this is a reference to a | |
4475 | GP relative symbol, we want | |
4476 | addu $tempreg,$breg,$gp | |
4477 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4478 | Otherwise we want | |
4479 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4480 | addu $tempreg,$tempreg,$breg | |
4481 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4482 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4483 | if (breg == 0) |
4484 | { | |
7a15a226 | 4485 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4486 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4487 | p = NULL; |
4488 | else | |
4489 | { | |
8ea7f4e8 | 4490 | frag_grow (20); |
0dd2d296 ILT |
4491 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4492 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4493 | p = frag_var (rs_machine_dependent, 8, 0, | |
4494 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4495 | (mips_warn_about_macros |
4496 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4497 | offset_expr.X_add_symbol, (long) 0, |
4498 | (char *) NULL); | |
8197b589 | 4499 | used_at = 0; |
0dd2d296 ILT |
4500 | } |
4501 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4502 | if (p != NULL) | |
4503 | p += 4; | |
4504 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4505 | (int) BFD_RELOC_LO16, tempreg); | |
4506 | } | |
4507 | else | |
4508 | { | |
7a15a226 | 4509 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4510 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4511 | p = NULL; |
4512 | else | |
4513 | { | |
8ea7f4e8 | 4514 | frag_grow (28); |
0dd2d296 ILT |
4515 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4516 | mips_isa < 3 ? "addu" : "daddu", | |
4517 | "d,v,t", tempreg, breg, GP); | |
4518 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4519 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4520 | p = frag_var (rs_machine_dependent, 12, 0, | |
4521 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4522 | offset_expr.X_add_symbol, (long) 0, | |
4523 | (char *) NULL); | |
4524 | } | |
4525 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4526 | if (p != NULL) | |
4527 | p += 4; | |
4528 | macro_build (p, &icnt, (expressionS *) NULL, | |
4529 | mips_isa < 3 ? "addu" : "daddu", | |
4530 | "d,v,t", tempreg, tempreg, breg); | |
4531 | if (p != NULL) | |
4532 | p += 4; | |
4533 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4534 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4535 | } |
670a50eb | 4536 | } |
fb251650 | 4537 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4538 | { |
0dd2d296 ILT |
4539 | /* If this is a reference to an external symbol, we want |
4540 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4541 | nop | |
4542 | <op> $treg,0($tempreg) | |
4543 | Otherwise we want | |
4544 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4545 | nop | |
4546 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4547 | <op> $treg,0($tempreg) | |
4548 | If there is a base register, we add it to $tempreg before | |
4549 | the <op>. If there is a constant, we stick it in the | |
4550 | <op> instruction. We don't handle constants larger than | |
4551 | 16 bits, because we have no way to load the upper 16 bits | |
4552 | (actually, we could handle them for the subset of cases | |
4553 | in which we are not using $at). */ | |
4554 | assert (offset_expr.X_op == O_symbol); | |
4555 | expr1.X_add_number = offset_expr.X_add_number; | |
4556 | offset_expr.X_add_number = 0; | |
4557 | if (expr1.X_add_number < -0x8000 | |
4558 | || expr1.X_add_number >= 0x8000) | |
4559 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4560 | frag_grow (20); |
0dd2d296 ILT |
4561 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4562 | mips_isa < 3 ? "lw" : "ld", | |
4563 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4564 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4565 | p = frag_var (rs_machine_dependent, 4, 0, | |
4566 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4567 | offset_expr.X_add_symbol, (long) 0, | |
4568 | (char *) NULL); | |
4569 | macro_build (p, &icnt, &offset_expr, | |
4570 | mips_isa < 3 ? "addiu" : "daddiu", | |
4571 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4572 | if (breg != 0) |
0dd2d296 | 4573 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4574 | mips_isa < 3 ? "addu" : "daddu", |
4575 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4576 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4577 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4578 | } |
fb251650 ILT |
4579 | else if (mips_pic == SVR4_PIC) |
4580 | { | |
4581 | int gpdel; | |
4582 | ||
4583 | /* If this is a reference to an external symbol, we want | |
4584 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4585 | addu $tempreg,$tempreg,$gp | |
4586 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4587 | <op> $treg,0($tempreg) | |
4588 | Otherwise we want | |
4589 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4590 | nop | |
4591 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4592 | <op> $treg,0($tempreg) | |
4593 | If there is a base register, we add it to $tempreg before | |
4594 | the <op>. If there is a constant, we stick it in the | |
4595 | <op> instruction. We don't handle constants larger than | |
4596 | 16 bits, because we have no way to load the upper 16 bits | |
4597 | (actually, we could handle them for the subset of cases | |
4598 | in which we are not using $at). */ | |
4599 | assert (offset_expr.X_op == O_symbol); | |
4600 | expr1.X_add_number = offset_expr.X_add_number; | |
4601 | offset_expr.X_add_number = 0; | |
4602 | if (expr1.X_add_number < -0x8000 | |
4603 | || expr1.X_add_number >= 0x8000) | |
4604 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4605 | if (reg_needs_delay (GP)) | |
4606 | gpdel = 4; | |
4607 | else | |
4608 | gpdel = 0; | |
4609 | frag_grow (36); | |
4610 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4611 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4612 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4613 | mips_isa < 3 ? "addu" : "daddu", | |
4614 | "d,v,t", tempreg, tempreg, GP); | |
4615 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4616 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4617 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4618 | tempreg); | |
fb251650 ILT |
4619 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4620 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4621 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4622 | if (gpdel > 0) | |
4623 | { | |
4624 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4625 | p += 4; | |
4626 | } | |
4627 | macro_build (p, &icnt, &offset_expr, | |
4628 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4629 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4630 | p += 4; |
4631 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4632 | p += 4; | |
4633 | macro_build (p, &icnt, &offset_expr, | |
4634 | mips_isa < 3 ? "addiu" : "daddiu", | |
4635 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4636 | if (breg != 0) | |
4637 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4638 | mips_isa < 3 ? "addu" : "daddu", | |
4639 | "d,v,t", tempreg, tempreg, breg); | |
4640 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4641 | (int) BFD_RELOC_LO16, tempreg); | |
4642 | } | |
d9aba805 ILT |
4643 | else if (mips_pic == EMBEDDED_PIC) |
4644 | { | |
4645 | /* If there is no base register, we want | |
4646 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4647 | If there is a base register, we want | |
4648 | addu $tempreg,$breg,$gp | |
4649 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4650 | */ | |
4651 | assert (offset_expr.X_op == O_symbol); | |
4652 | if (breg == 0) | |
4653 | { | |
4654 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4655 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4656 | used_at = 0; | |
4657 | } | |
4658 | else | |
4659 | { | |
4660 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4661 | mips_isa < 3 ? "addu" : "daddu", | |
4662 | "d,v,t", tempreg, breg, GP); | |
4663 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4664 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4665 | } | |
4666 | } | |
4667 | else | |
4668 | abort (); | |
0dd2d296 ILT |
4669 | |
4670 | if (! used_at) | |
4671 | return; | |
4672 | ||
4673 | break; | |
3d3c5039 ILT |
4674 | |
4675 | case M_LI: | |
19ed8960 | 4676 | case M_LI_S: |
d8a1c247 KR |
4677 | load_register (&icnt, treg, &imm_expr, 0); |
4678 | return; | |
4679 | ||
4680 | case M_DLI: | |
4681 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4682 | return; |
3d3c5039 | 4683 | |
0dd2d296 | 4684 | case M_LI_SS: |
55933a58 | 4685 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4686 | { |
d8a1c247 | 4687 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4688 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4689 | "mtc1", "t,G", AT, treg); | |
4690 | break; | |
0dd2d296 | 4691 | } |
d9aba805 | 4692 | else |
d2c71068 | 4693 | { |
55933a58 ILT |
4694 | assert (offset_expr.X_op == O_symbol |
4695 | && strcmp (segment_name (S_GET_SEGMENT | |
4696 | (offset_expr.X_add_symbol)), | |
4697 | ".lit4") == 0 | |
4698 | && offset_expr.X_add_number == 0); | |
4699 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4700 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4701 | return; |
4702 | } | |
0dd2d296 | 4703 | |
3d3c5039 | 4704 | case M_LI_D: |
d9aba805 ILT |
4705 | /* We know that sym is in the .rdata section. First we get the |
4706 | upper 16 bits of the address. */ | |
4707 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4708 | { |
4709 | /* FIXME: This won't work for a 64 bit address. */ | |
4710 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4711 | } | |
d9aba805 | 4712 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4713 | { |
4714 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4715 | mips_isa < 3 ? "lw" : "ld", | |
4716 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4717 | } | |
d9aba805 ILT |
4718 | else if (mips_pic == EMBEDDED_PIC) |
4719 | { | |
4720 | /* For embedded PIC we pick up the entire address off $gp in | |
4721 | a single instruction. */ | |
4722 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4723 | mips_isa < 3 ? "addiu" : "daddiu", | |
4724 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4725 | offset_expr.X_op = O_constant; | |
4726 | offset_expr.X_add_number = 0; | |
4727 | } | |
4728 | else | |
4729 | abort (); | |
4730 | ||
0dd2d296 | 4731 | /* Now we load the register(s). */ |
8358c818 | 4732 | if (mips_isa >= 3) |
0dd2d296 ILT |
4733 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4734 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4735 | else |
4736 | { | |
0dd2d296 ILT |
4737 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4738 | treg, (int) BFD_RELOC_LO16, AT); | |
4739 | if (treg != 31) | |
4740 | { | |
4741 | /* FIXME: How in the world do we deal with the possible | |
4742 | overflow here? */ | |
4743 | offset_expr.X_add_number += 4; | |
4744 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4745 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4746 | } | |
8358c818 | 4747 | } |
d2c71068 ILT |
4748 | |
4749 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4750 | does not become a variant frag. */ | |
4751 | frag_wane (frag_now); | |
4752 | frag_new (0); | |
4753 | ||
670a50eb | 4754 | break; |
3d3c5039 ILT |
4755 | |
4756 | case M_LI_DD: | |
55933a58 ILT |
4757 | assert (offset_expr.X_op == O_symbol |
4758 | && offset_expr.X_add_number == 0); | |
4759 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4760 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4761 | { |
0dd2d296 ILT |
4762 | if (mips_isa >= 2) |
4763 | { | |
4764 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4765 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4766 | return; | |
4767 | } | |
4768 | breg = GP; | |
4769 | r = BFD_RELOC_MIPS_LITERAL; | |
4770 | goto dob; | |
4771 | } | |
55933a58 | 4772 | else |
0dd2d296 | 4773 | { |
55933a58 ILT |
4774 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4775 | if (mips_pic == SVR4_PIC) | |
4776 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4777 | mips_isa < 3 ? "lw" : "ld", | |
4778 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4779 | else | |
4780 | { | |
4781 | /* FIXME: This won't work for a 64 bit address. */ | |
4782 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4783 | } | |
4784 | ||
0dd2d296 ILT |
4785 | if (mips_isa >= 2) |
4786 | { | |
4787 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4788 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4789 | |
4790 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4791 | that this does not become a variant frag. */ | |
4792 | frag_wane (frag_now); | |
4793 | frag_new (0); | |
4794 | ||
0dd2d296 ILT |
4795 | break; |
4796 | } | |
4797 | breg = AT; | |
4798 | r = BFD_RELOC_LO16; | |
4799 | goto dob; | |
8358c818 | 4800 | } |
9226253a | 4801 | |
3d3c5039 | 4802 | case M_L_DOB: |
9a7d824a ILT |
4803 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4804 | to adjust when loading from memory. */ | |
9226253a ILT |
4805 | r = BFD_RELOC_LO16; |
4806 | dob: | |
8358c818 | 4807 | assert (mips_isa < 2); |
0dd2d296 | 4808 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4809 | target_big_endian ? treg + 1 : treg, |
9226253a | 4810 | (int) r, breg); |
0dd2d296 ILT |
4811 | /* FIXME: A possible overflow which I don't know how to deal |
4812 | with. */ | |
670a50eb | 4813 | offset_expr.X_add_number += 4; |
0dd2d296 | 4814 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4815 | target_big_endian ? treg : treg + 1, |
9226253a | 4816 | (int) r, breg); |
d2c71068 ILT |
4817 | |
4818 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4819 | does not become a variant frag. */ | |
4820 | frag_wane (frag_now); | |
4821 | frag_new (0); | |
4822 | ||
0dd2d296 ILT |
4823 | if (breg != AT) |
4824 | return; | |
4825 | break; | |
3d3c5039 ILT |
4826 | |
4827 | case M_L_DAB: | |
670a50eb ILT |
4828 | /* |
4829 | * The MIPS assembler seems to check for X_add_number not | |
4830 | * being double aligned and generating: | |
4831 | * lui at,%hi(foo+1) | |
4832 | * addu at,at,v1 | |
4833 | * addiu at,at,%lo(foo+1) | |
4834 | * lwc1 f2,0(at) | |
4835 | * lwc1 f3,4(at) | |
4836 | * But, the resulting address is the same after relocation so why | |
4837 | * generate the extra instruction? | |
4838 | */ | |
4032d3f0 | 4839 | coproc = 1; |
0dd2d296 | 4840 | if (mips_isa >= 2) |
670a50eb | 4841 | { |
0dd2d296 ILT |
4842 | s = "ldc1"; |
4843 | goto ld; | |
670a50eb | 4844 | } |
0dd2d296 ILT |
4845 | |
4846 | s = "lwc1"; | |
4847 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4848 | goto ldd_std; |
4849 | ||
4850 | case M_S_DAB: | |
8358c818 | 4851 | if (mips_isa >= 2) |
8358c818 | 4852 | { |
0dd2d296 ILT |
4853 | s = "sdc1"; |
4854 | goto st; | |
8358c818 | 4855 | } |
3d3c5039 | 4856 | |
0dd2d296 ILT |
4857 | s = "swc1"; |
4858 | fmt = "T,o(b)"; | |
4859 | coproc = 1; | |
4860 | goto ldd_std; | |
3d3c5039 ILT |
4861 | |
4862 | case M_LD_AB: | |
0dd2d296 | 4863 | if (mips_isa >= 3) |
670a50eb | 4864 | { |
0dd2d296 ILT |
4865 | s = "ld"; |
4866 | goto ld; | |
670a50eb | 4867 | } |
0dd2d296 ILT |
4868 | |
4869 | s = "lw"; | |
4870 | fmt = "t,o(b)"; | |
4871 | goto ldd_std; | |
4872 | ||
4873 | case M_SD_AB: | |
4874 | if (mips_isa >= 3) | |
670a50eb | 4875 | { |
0dd2d296 ILT |
4876 | s = "sd"; |
4877 | goto st; | |
670a50eb | 4878 | } |
0dd2d296 | 4879 | |
670a50eb | 4880 | s = "sw"; |
0dd2d296 ILT |
4881 | fmt = "t,o(b)"; |
4882 | ||
4883 | ldd_std: | |
4884 | if (offset_expr.X_op != O_symbol | |
4885 | && offset_expr.X_op != O_constant) | |
670a50eb | 4886 | { |
0dd2d296 ILT |
4887 | as_bad ("expression too complex"); |
4888 | offset_expr.X_op = O_constant; | |
4889 | } | |
4890 | ||
4891 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4892 | to adjust when loading from memory. We set coproc if we must | |
4893 | load $fn+1 first. */ | |
b9129c6f | 4894 | if (! target_big_endian) |
0dd2d296 ILT |
4895 | coproc = 0; |
4896 | ||
d9aba805 | 4897 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4898 | || offset_expr.X_op == O_constant) |
4899 | { | |
4900 | /* If this is a reference to a GP relative symbol, we want | |
4901 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4902 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4903 | If we have a base register, we use this | |
4904 | addu $at,$breg,$gp | |
4905 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4906 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4907 | If this is not a GP relative symbol, we want | |
4908 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4909 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4910 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4911 | If there is a base register, we add it to $at after the | |
4912 | lui instruction. If there is a constant, we always use | |
4913 | the last case. */ | |
7a15a226 | 4914 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4915 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4916 | { |
0dd2d296 ILT |
4917 | p = NULL; |
4918 | used_at = 1; | |
670a50eb ILT |
4919 | } |
4920 | else | |
0dd2d296 ILT |
4921 | { |
4922 | int off; | |
4923 | ||
4924 | if (breg == 0) | |
4925 | { | |
8ea7f4e8 | 4926 | frag_grow (28); |
0dd2d296 ILT |
4927 | tempreg = GP; |
4928 | off = 0; | |
4929 | used_at = 0; | |
4930 | } | |
4931 | else | |
4932 | { | |
8ea7f4e8 | 4933 | frag_grow (36); |
0dd2d296 ILT |
4934 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4935 | mips_isa < 3 ? "addu" : "daddu", | |
4936 | "d,v,t", AT, breg, GP); | |
4937 | tempreg = AT; | |
4938 | off = 4; | |
4939 | used_at = 1; | |
4940 | } | |
4941 | ||
4942 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4943 | coproc ? treg + 1 : treg, | |
4944 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4945 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4946 | |
4947 | /* Set mips_optimize to 2 to avoid inserting an | |
4948 | undesired nop. */ | |
4949 | hold_mips_optimize = mips_optimize; | |
4950 | mips_optimize = 2; | |
0dd2d296 ILT |
4951 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4952 | coproc ? treg : treg + 1, | |
4953 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4954 | mips_optimize = hold_mips_optimize; |
4955 | ||
0dd2d296 ILT |
4956 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4957 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4958 | used_at && mips_noat), |
0dd2d296 ILT |
4959 | offset_expr.X_add_symbol, (long) 0, |
4960 | (char *) NULL); | |
777ad64d ILT |
4961 | |
4962 | /* We just generated two relocs. When tc_gen_reloc | |
4963 | handles this case, it will skip the first reloc and | |
4964 | handle the second. The second reloc already has an | |
4965 | extra addend of 4, which we added above. We must | |
4966 | subtract it out, and then subtract another 4 to make | |
4967 | the first reloc come out right. The second reloc | |
4968 | will come out right because we are going to add 4 to | |
4969 | offset_expr when we build its instruction below. */ | |
4970 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4971 | offset_expr.X_op = O_constant; |
4972 | } | |
4973 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4974 | if (p != NULL) | |
4975 | p += 4; | |
4976 | if (breg != 0) | |
4977 | { | |
4978 | macro_build (p, &icnt, (expressionS *) NULL, | |
4979 | mips_isa < 3 ? "addu" : "daddu", | |
4980 | "d,v,t", AT, breg, AT); | |
4981 | if (p != NULL) | |
4982 | p += 4; | |
4983 | } | |
4984 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4985 | coproc ? treg + 1 : treg, | |
4986 | (int) BFD_RELOC_LO16, AT); | |
4987 | if (p != NULL) | |
4988 | p += 4; | |
4989 | /* FIXME: How do we handle overflow here? */ | |
4990 | offset_expr.X_add_number += 4; | |
4991 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4992 | coproc ? treg : treg + 1, | |
4993 | (int) BFD_RELOC_LO16, AT); | |
4994 | } | |
fb251650 | 4995 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4996 | { |
0dd2d296 ILT |
4997 | int off; |
4998 | ||
4999 | /* If this is a reference to an external symbol, we want | |
5000 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5001 | nop | |
5002 | <op> $treg,0($at) | |
5003 | <op> $treg+1,4($at) | |
5004 | Otherwise we want | |
5005 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5006 | nop | |
5007 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5008 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5009 | If there is a base register we add it to $at before the | |
5010 | lwc1 instructions. If there is a constant we include it | |
5011 | in the lwc1 instructions. */ | |
5012 | used_at = 1; | |
5013 | expr1.X_add_number = offset_expr.X_add_number; | |
5014 | offset_expr.X_add_number = 0; | |
5015 | if (expr1.X_add_number < -0x8000 | |
5016 | || expr1.X_add_number >= 0x8000 - 4) | |
5017 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5018 | if (breg == 0) | |
5019 | off = 0; | |
5020 | else | |
5021 | off = 4; | |
8ea7f4e8 | 5022 | frag_grow (24 + off); |
0dd2d296 ILT |
5023 | macro_build ((char *) NULL, &icnt, &offset_expr, |
5024 | mips_isa < 3 ? "lw" : "ld", | |
5025 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5026 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5027 | if (breg != 0) |
0dd2d296 | 5028 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 5029 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5030 | "d,v,t", AT, breg, AT); |
5031 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5032 | coproc ? treg + 1 : treg, | |
5033 | (int) BFD_RELOC_LO16, AT); | |
5034 | expr1.X_add_number += 4; | |
55933a58 ILT |
5035 | |
5036 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5037 | nop. */ | |
5038 | hold_mips_optimize = mips_optimize; | |
5039 | mips_optimize = 2; | |
0dd2d296 ILT |
5040 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5041 | coproc ? treg : treg + 1, | |
5042 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5043 | mips_optimize = hold_mips_optimize; |
5044 | ||
0dd2d296 ILT |
5045 | (void) frag_var (rs_machine_dependent, 0, 0, |
5046 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5047 | offset_expr.X_add_symbol, (long) 0, | |
5048 | (char *) NULL); | |
8358c818 | 5049 | } |
fb251650 ILT |
5050 | else if (mips_pic == SVR4_PIC) |
5051 | { | |
5052 | int gpdel, off; | |
5053 | ||
5054 | /* If this is a reference to an external symbol, we want | |
5055 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5056 | addu $at,$at,$gp | |
5057 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5058 | nop | |
5059 | <op> $treg,0($at) | |
5060 | <op> $treg+1,4($at) | |
5061 | Otherwise we want | |
5062 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5063 | nop | |
5064 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5065 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5066 | If there is a base register we add it to $at before the | |
5067 | lwc1 instructions. If there is a constant we include it | |
5068 | in the lwc1 instructions. */ | |
5069 | used_at = 1; | |
5070 | expr1.X_add_number = offset_expr.X_add_number; | |
5071 | offset_expr.X_add_number = 0; | |
5072 | if (expr1.X_add_number < -0x8000 | |
5073 | || expr1.X_add_number >= 0x8000 - 4) | |
5074 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5075 | if (reg_needs_delay (GP)) | |
5076 | gpdel = 4; | |
5077 | else | |
5078 | gpdel = 0; | |
5079 | if (breg == 0) | |
5080 | off = 0; | |
5081 | else | |
5082 | off = 4; | |
5083 | frag_grow (56); | |
5084 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5085 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5086 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5087 | mips_isa < 3 ? "addu" : "daddu", | |
5088 | "d,v,t", AT, AT, GP); | |
5089 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5090 | mips_isa < 3 ? "lw" : "ld", | |
5091 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5092 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5093 | if (breg != 0) | |
5094 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5095 | mips_isa < 3 ? "addu" : "daddu", | |
5096 | "d,v,t", AT, breg, AT); | |
5097 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5098 | coproc ? treg + 1 : treg, | |
5099 | (int) BFD_RELOC_LO16, AT); | |
5100 | expr1.X_add_number += 4; | |
5101 | ||
5102 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5103 | nop. */ | |
5104 | hold_mips_optimize = mips_optimize; | |
5105 | mips_optimize = 2; | |
5106 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5107 | coproc ? treg : treg + 1, | |
5108 | (int) BFD_RELOC_LO16, AT); | |
5109 | mips_optimize = hold_mips_optimize; | |
5110 | expr1.X_add_number -= 4; | |
5111 | ||
5112 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5113 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5114 | 8 + gpdel + off, 1, 0), | |
5115 | offset_expr.X_add_symbol, (long) 0, | |
5116 | (char *) NULL); | |
5117 | if (gpdel > 0) | |
5118 | { | |
5119 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5120 | p += 4; | |
5121 | } | |
5122 | macro_build (p, &icnt, &offset_expr, | |
5123 | mips_isa < 3 ? "lw" : "ld", | |
5124 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5125 | p += 4; | |
5126 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5127 | p += 4; | |
5128 | if (breg != 0) | |
5129 | { | |
5130 | macro_build (p, &icnt, (expressionS *) NULL, | |
5131 | mips_isa < 3 ? "addu" : "daddu", | |
5132 | "d,v,t", AT, breg, AT); | |
5133 | p += 4; | |
5134 | } | |
5135 | macro_build (p, &icnt, &expr1, s, fmt, | |
5136 | coproc ? treg + 1 : treg, | |
5137 | (int) BFD_RELOC_LO16, AT); | |
5138 | p += 4; | |
5139 | expr1.X_add_number += 4; | |
5140 | ||
5141 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5142 | nop. */ | |
5143 | hold_mips_optimize = mips_optimize; | |
5144 | mips_optimize = 2; | |
5145 | macro_build (p, &icnt, &expr1, s, fmt, | |
5146 | coproc ? treg : treg + 1, | |
5147 | (int) BFD_RELOC_LO16, AT); | |
5148 | mips_optimize = hold_mips_optimize; | |
5149 | } | |
d9aba805 ILT |
5150 | else if (mips_pic == EMBEDDED_PIC) |
5151 | { | |
5152 | /* If there is no base register, we use | |
5153 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5154 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5155 | If we have a base register, we use | |
5156 | addu $at,$breg,$gp | |
5157 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5158 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5159 | */ | |
5160 | if (breg == 0) | |
5161 | { | |
5162 | tempreg = GP; | |
5163 | used_at = 0; | |
5164 | } | |
5165 | else | |
5166 | { | |
5167 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5168 | mips_isa < 3 ? "addu" : "daddu", | |
5169 | "d,v,t", AT, breg, GP); | |
5170 | tempreg = AT; | |
5171 | used_at = 1; | |
5172 | } | |
5173 | ||
5174 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5175 | coproc ? treg + 1 : treg, | |
5176 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5177 | offset_expr.X_add_number += 4; | |
5178 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5179 | coproc ? treg : treg + 1, | |
5180 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5181 | } | |
5182 | else | |
5183 | abort (); | |
0dd2d296 ILT |
5184 | |
5185 | if (! used_at) | |
5186 | return; | |
5187 | ||
5188 | break; | |
5189 | ||
5190 | case M_LD_OB: | |
5191 | s = "lw"; | |
5192 | goto sd_ob; | |
5193 | case M_SD_OB: | |
5194 | s = "sw"; | |
5195 | sd_ob: | |
5196 | assert (mips_isa < 3); | |
5197 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5198 | (int) BFD_RELOC_LO16, breg); | |
5199 | offset_expr.X_add_number += 4; | |
5200 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5201 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5202 | return; |
917fae09 SS |
5203 | #ifdef LOSING_COMPILER |
5204 | default: | |
5205 | macro2 (ip); | |
5206 | return; | |
5207 | } | |
5208 | if (mips_noat) | |
5209 | as_warn ("Macro used $at after \".set noat\""); | |
5210 | } | |
5211 | ||
5212 | static void | |
5213 | macro2 (ip) | |
5214 | struct mips_cl_insn *ip; | |
5215 | { | |
5216 | register int treg, sreg, dreg, breg; | |
5217 | int tempreg; | |
5218 | int mask; | |
5219 | int icnt = 0; | |
5220 | int used_at; | |
5221 | expressionS expr1; | |
5222 | const char *s; | |
5223 | const char *s2; | |
5224 | const char *fmt; | |
5225 | int likely = 0; | |
5226 | int dbl = 0; | |
5227 | int coproc = 0; | |
adcf2b9d ILT |
5228 | int lr = 0; |
5229 | int off; | |
917fae09 SS |
5230 | offsetT maxnum; |
5231 | bfd_reloc_code_real_type r; | |
5232 | char *p; | |
5233 | ||
5234 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5235 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5236 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5237 | mask = ip->insn_mo->mask; | |
5238 | ||
5239 | expr1.X_op = O_constant; | |
5240 | expr1.X_op_symbol = NULL; | |
5241 | expr1.X_add_symbol = NULL; | |
5242 | expr1.X_add_number = 1; | |
5243 | ||
5244 | switch (mask) | |
5245 | { | |
5246 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5247 | |
8358c818 ILT |
5248 | case M_DMUL: |
5249 | dbl = 1; | |
3d3c5039 | 5250 | case M_MUL: |
0dd2d296 | 5251 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5252 | dbl ? "dmultu" : "multu", |
5253 | "s,t", sreg, treg); | |
0dd2d296 | 5254 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5255 | return; |
3d3c5039 | 5256 | |
8358c818 ILT |
5257 | case M_DMUL_I: |
5258 | dbl = 1; | |
3d3c5039 | 5259 | case M_MUL_I: |
8358c818 ILT |
5260 | /* The MIPS assembler some times generates shifts and adds. I'm |
5261 | not trying to be that fancy. GCC should do this for us | |
5262 | anyway. */ | |
d8a1c247 | 5263 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5264 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5265 | dbl ? "dmult" : "mult", |
5266 | "s,t", sreg, AT); | |
0dd2d296 | 5267 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5268 | break; |
3d3c5039 | 5269 | |
8358c818 ILT |
5270 | case M_DMULO: |
5271 | dbl = 1; | |
5272 | case M_MULO: | |
fbcfacb7 | 5273 | mips_emit_delays (true); |
8358c818 | 5274 | ++mips_noreorder; |
0dd2d296 ILT |
5275 | mips_any_noreorder = 1; |
5276 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5277 | dbl ? "dmult" : "mult", |
5278 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5279 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5280 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5281 | dbl ? "dsra32" : "sra", |
5282 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5283 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5284 | if (mips_trap) |
5285 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5286 | else | |
5287 | { | |
5288 | expr1.X_add_number = 8; | |
5289 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5290 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5291 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5292 | } | |
8358c818 | 5293 | --mips_noreorder; |
0dd2d296 | 5294 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5295 | break; |
5296 | ||
5297 | case M_DMULOU: | |
5298 | dbl = 1; | |
5299 | case M_MULOU: | |
fbcfacb7 | 5300 | mips_emit_delays (true); |
8358c818 | 5301 | ++mips_noreorder; |
0dd2d296 ILT |
5302 | mips_any_noreorder = 1; |
5303 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5304 | dbl ? "dmultu" : "multu", |
5305 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5306 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5307 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5308 | if (mips_trap) |
5309 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5310 | else | |
5311 | { | |
5312 | expr1.X_add_number = 8; | |
5313 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5314 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5315 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5316 | } | |
8358c818 ILT |
5317 | --mips_noreorder; |
5318 | break; | |
5319 | ||
3d3c5039 | 5320 | case M_ROL: |
0dd2d296 ILT |
5321 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5322 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5323 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5324 | treg); | |
5325 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5326 | break; |
3d3c5039 ILT |
5327 | |
5328 | case M_ROL_I: | |
0dd2d296 | 5329 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5330 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5331 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5332 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5333 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5334 | break; |
3d3c5039 ILT |
5335 | |
5336 | case M_ROR: | |
0dd2d296 ILT |
5337 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5338 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5339 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5340 | treg); | |
5341 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5342 | break; |
3d3c5039 ILT |
5343 | |
5344 | case M_ROR_I: | |
0dd2d296 | 5345 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5346 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5347 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5348 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5349 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5350 | break; |
3d3c5039 ILT |
5351 | |
5352 | case M_S_DOB: | |
8358c818 | 5353 | assert (mips_isa < 2); |
9a7d824a ILT |
5354 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5355 | to adjust when storing to memory. */ | |
0dd2d296 | 5356 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5357 | target_big_endian ? treg + 1 : treg, |
9226253a | 5358 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5359 | offset_expr.X_add_number += 4; |
0dd2d296 | 5360 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5361 | target_big_endian ? treg : treg + 1, |
9226253a | 5362 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5363 | return; |
3d3c5039 | 5364 | |
3d3c5039 | 5365 | case M_SEQ: |
670a50eb | 5366 | if (sreg == 0) |
0dd2d296 ILT |
5367 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5368 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5369 | else if (treg == 0) |
0dd2d296 ILT |
5370 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5371 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5372 | else |
5373 | { | |
0dd2d296 ILT |
5374 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5375 | sreg, treg); | |
5376 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5377 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5378 | } |
670a50eb | 5379 | return; |
3d3c5039 ILT |
5380 | |
5381 | case M_SEQ_I: | |
670a50eb ILT |
5382 | if (imm_expr.X_add_number == 0) |
5383 | { | |
0dd2d296 ILT |
5384 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5385 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5386 | return; |
3d3c5039 | 5387 | } |
670a50eb ILT |
5388 | if (sreg == 0) |
5389 | { | |
9a7d824a | 5390 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5391 | ip->insn_mo->name); |
0dd2d296 | 5392 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5393 | return; |
3d3c5039 | 5394 | } |
6e8dda9c | 5395 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5396 | { |
0dd2d296 ILT |
5397 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5398 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5399 | used_at = 0; |
6e8dda9c ILT |
5400 | } |
5401 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5402 | { | |
5403 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5404 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5405 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5406 | "t,r,j", dreg, sreg, |
5407 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5408 | used_at = 0; |
5409 | } | |
5410 | else | |
5411 | { | |
d8a1c247 | 5412 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5413 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5414 | sreg, AT); | |
670a50eb ILT |
5415 | used_at = 1; |
5416 | } | |
0dd2d296 | 5417 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5418 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5419 | if (used_at) |
5420 | break; | |
5421 | return; | |
3d3c5039 ILT |
5422 | |
5423 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5424 | s = "slt"; |
5425 | goto sge; | |
3d3c5039 | 5426 | case M_SGEU: |
670a50eb | 5427 | s = "sltu"; |
3d3c5039 | 5428 | sge: |
0dd2d296 ILT |
5429 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5430 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5431 | (int) BFD_RELOC_LO16); |
670a50eb | 5432 | return; |
3d3c5039 | 5433 | |
670a50eb | 5434 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5435 | case M_SGEU_I: |
6e8dda9c | 5436 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5437 | { |
0dd2d296 | 5438 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5439 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5440 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5441 | used_at = 0; |
5442 | } | |
5443 | else | |
5444 | { | |
d8a1c247 | 5445 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5446 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5447 | mask == M_SGE_I ? "slt" : "sltu", |
5448 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5449 | used_at = 1; |
5450 | } | |
0dd2d296 | 5451 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5452 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5453 | if (used_at) |
5454 | break; | |
5455 | return; | |
3d3c5039 ILT |
5456 | |
5457 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5458 | s = "slt"; |
5459 | goto sgt; | |
3d3c5039 | 5460 | case M_SGTU: |
670a50eb | 5461 | s = "sltu"; |
3d3c5039 | 5462 | sgt: |
0dd2d296 | 5463 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5464 | return; |
3d3c5039 | 5465 | |
670a50eb ILT |
5466 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5467 | s = "slt"; | |
5468 | goto sgti; | |
3d3c5039 | 5469 | case M_SGTU_I: |
670a50eb | 5470 | s = "sltu"; |
3d3c5039 | 5471 | sgti: |
d8a1c247 | 5472 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5473 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5474 | break; |
3d3c5039 | 5475 | |
670a50eb ILT |
5476 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5477 | s = "slt"; | |
5478 | goto sle; | |
3d3c5039 | 5479 | case M_SLEU: |
670a50eb | 5480 | s = "sltu"; |
3d3c5039 | 5481 | sle: |
0dd2d296 ILT |
5482 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5483 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5484 | (int) BFD_RELOC_LO16); |
670a50eb | 5485 | return; |
3d3c5039 | 5486 | |
670a50eb ILT |
5487 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5488 | s = "slt"; | |
5489 | goto slei; | |
3d3c5039 | 5490 | case M_SLEU_I: |
670a50eb | 5491 | s = "sltu"; |
3d3c5039 | 5492 | slei: |
d8a1c247 | 5493 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5494 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5495 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5496 | (int) BFD_RELOC_LO16); |
670a50eb | 5497 | break; |
3d3c5039 ILT |
5498 | |
5499 | case M_SLT_I: | |
6e8dda9c | 5500 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5501 | { |
0dd2d296 ILT |
5502 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5503 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5504 | return; |
3d3c5039 | 5505 | } |
d8a1c247 | 5506 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5507 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5508 | break; |
3d3c5039 ILT |
5509 | |
5510 | case M_SLTU_I: | |
6e8dda9c | 5511 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5512 | { |
0dd2d296 ILT |
5513 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5514 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5515 | return; |
3d3c5039 | 5516 | } |
d8a1c247 | 5517 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5518 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5519 | AT); | |
670a50eb | 5520 | break; |
3d3c5039 ILT |
5521 | |
5522 | case M_SNE: | |
670a50eb | 5523 | if (sreg == 0) |
0dd2d296 ILT |
5524 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5525 | treg); | |
670a50eb | 5526 | else if (treg == 0) |
0dd2d296 ILT |
5527 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5528 | sreg); | |
670a50eb ILT |
5529 | else |
5530 | { | |
0dd2d296 ILT |
5531 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5532 | sreg, treg); | |
5533 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5534 | dreg); | |
3d3c5039 | 5535 | } |
670a50eb | 5536 | return; |
3d3c5039 ILT |
5537 | |
5538 | case M_SNE_I: | |
670a50eb ILT |
5539 | if (imm_expr.X_add_number == 0) |
5540 | { | |
0dd2d296 ILT |
5541 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5542 | sreg); | |
670a50eb | 5543 | return; |
3d3c5039 | 5544 | } |
670a50eb ILT |
5545 | if (sreg == 0) |
5546 | { | |
9a7d824a | 5547 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5548 | ip->insn_mo->name); |
0dd2d296 | 5549 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5550 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5551 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5552 | return; |
3d3c5039 | 5553 | } |
6e8dda9c | 5554 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5555 | { |
0dd2d296 ILT |
5556 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5557 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5558 | used_at = 0; |
6e8dda9c ILT |
5559 | } |
5560 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5561 | { | |
5562 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5563 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5564 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5565 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5566 | used_at = 0; |
5567 | } | |
5568 | else | |
5569 | { | |
d8a1c247 | 5570 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5571 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5572 | sreg, AT); | |
670a50eb ILT |
5573 | used_at = 1; |
5574 | } | |
0dd2d296 | 5575 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5576 | if (used_at) |
5577 | break; | |
5578 | return; | |
3d3c5039 | 5579 | |
8358c818 ILT |
5580 | case M_DSUB_I: |
5581 | dbl = 1; | |
3d3c5039 | 5582 | case M_SUB_I: |
6e8dda9c | 5583 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5584 | { |
5585 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5586 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5587 | dbl ? "daddi" : "addi", |
9226253a | 5588 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5589 | return; |
3d3c5039 | 5590 | } |
d8a1c247 | 5591 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5592 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5593 | dbl ? "dsub" : "sub", |
5594 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5595 | break; |
3d3c5039 | 5596 | |
8358c818 ILT |
5597 | case M_DSUBU_I: |
5598 | dbl = 1; | |
3d3c5039 | 5599 | case M_SUBU_I: |
6e8dda9c | 5600 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5601 | { |
5602 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5603 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5604 | dbl ? "daddiu" : "addiu", |
9226253a | 5605 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5606 | return; |
3d3c5039 | 5607 | } |
d8a1c247 | 5608 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5609 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5610 | dbl ? "dsubu" : "subu", |
5611 | "d,v,t", dreg, sreg, AT); | |
5612 | break; | |
5613 | ||
5614 | case M_TEQ_I: | |
5615 | s = "teq"; | |
5616 | goto trap; | |
5617 | case M_TGE_I: | |
5618 | s = "tge"; | |
5619 | goto trap; | |
5620 | case M_TGEU_I: | |
5621 | s = "tgeu"; | |
5622 | goto trap; | |
5623 | case M_TLT_I: | |
5624 | s = "tlt"; | |
5625 | goto trap; | |
5626 | case M_TLTU_I: | |
5627 | s = "tltu"; | |
5628 | goto trap; | |
5629 | case M_TNE_I: | |
5630 | s = "tne"; | |
5631 | trap: | |
d8a1c247 | 5632 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5633 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5634 | break; |
3d3c5039 ILT |
5635 | |
5636 | case M_TRUNCWD: | |
5637 | case M_TRUNCWS: | |
8358c818 | 5638 | assert (mips_isa < 2); |
670a50eb ILT |
5639 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5640 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5641 | ||
5642 | /* | |
5643 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5644 | * or is there a reason for it? | |
5645 | */ | |
fbcfacb7 | 5646 | mips_emit_delays (true); |
becfe05e | 5647 | ++mips_noreorder; |
0dd2d296 ILT |
5648 | mips_any_noreorder = 1; |
5649 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5650 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5651 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5652 | expr1.X_add_number = 3; |
0dd2d296 | 5653 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5654 | (int) BFD_RELOC_LO16); |
670a50eb | 5655 | expr1.X_add_number = 2; |
0dd2d296 | 5656 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5657 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5658 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5659 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5660 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5661 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5662 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5663 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5664 | --mips_noreorder; |
670a50eb | 5665 | break; |
3d3c5039 ILT |
5666 | |
5667 | case M_ULH: | |
670a50eb ILT |
5668 | s = "lb"; |
5669 | goto ulh; | |
3d3c5039 | 5670 | case M_ULHU: |
670a50eb | 5671 | s = "lbu"; |
3d3c5039 | 5672 | ulh: |
8ea7f4e8 ILT |
5673 | if (offset_expr.X_add_number >= 0x7fff) |
5674 | as_bad ("operand overflow"); | |
670a50eb | 5675 | /* avoid load delay */ |
b9129c6f | 5676 | if (! target_big_endian) |
8ea7f4e8 | 5677 | offset_expr.X_add_number += 1; |
0dd2d296 | 5678 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5679 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5680 | if (! target_big_endian) |
8ea7f4e8 ILT |
5681 | offset_expr.X_add_number -= 1; |
5682 | else | |
5683 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5684 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5685 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5686 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5687 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5688 | break; |
3d3c5039 | 5689 | |
adcf2b9d ILT |
5690 | case M_ULD: |
5691 | s = "ldl"; | |
5692 | s2 = "ldr"; | |
5693 | off = 7; | |
5694 | goto ulw; | |
3d3c5039 | 5695 | case M_ULW: |
adcf2b9d ILT |
5696 | s = "lwl"; |
5697 | s2 = "lwr"; | |
5698 | off = 3; | |
5699 | ulw: | |
5700 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5701 | as_bad ("operand overflow"); |
b9129c6f | 5702 | if (! target_big_endian) |
adcf2b9d ILT |
5703 | offset_expr.X_add_number += off; |
5704 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5705 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5706 | if (! target_big_endian) |
adcf2b9d | 5707 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5708 | else |
adcf2b9d ILT |
5709 | offset_expr.X_add_number += off; |
5710 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5711 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5712 | return; |
3d3c5039 | 5713 | |
adcf2b9d ILT |
5714 | case M_ULD_A: |
5715 | s = "ldl"; | |
5716 | s2 = "ldr"; | |
5717 | off = 7; | |
5718 | goto ulwa; | |
5719 | case M_ULW_A: | |
5720 | s = "lwl"; | |
5721 | s2 = "lwr"; | |
5722 | off = 3; | |
5723 | ulwa: | |
5724 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5725 | if (breg != 0) |
5726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5727 | mips_isa < 3 ? "addu" : "daddu", | |
5728 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5729 | if (! target_big_endian) |
adcf2b9d ILT |
5730 | expr1.X_add_number = off; |
5731 | else | |
5732 | expr1.X_add_number = 0; | |
5733 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5734 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5735 | if (! target_big_endian) |
adcf2b9d ILT |
5736 | expr1.X_add_number = 0; |
5737 | else | |
5738 | expr1.X_add_number = off; | |
5739 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5740 | (int) BFD_RELOC_LO16, AT); | |
5741 | break; | |
5742 | ||
3d3c5039 ILT |
5743 | case M_ULH_A: |
5744 | case M_ULHU_A: | |
0dd2d296 | 5745 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5746 | if (breg != 0) |
5747 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5748 | mips_isa < 3 ? "addu" : "daddu", | |
5749 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5750 | if (target_big_endian) |
adcf2b9d ILT |
5751 | expr1.X_add_number = 0; |
5752 | macro_build ((char *) NULL, &icnt, &expr1, | |
5753 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5754 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5755 | if (target_big_endian) |
adcf2b9d | 5756 | expr1.X_add_number = 1; |
670a50eb | 5757 | else |
adcf2b9d ILT |
5758 | expr1.X_add_number = 0; |
5759 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5760 | (int) BFD_RELOC_LO16, AT); | |
5761 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5762 | treg, 8); | |
5763 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5764 | treg, AT); | |
670a50eb | 5765 | break; |
3d3c5039 ILT |
5766 | |
5767 | case M_USH: | |
8ea7f4e8 ILT |
5768 | if (offset_expr.X_add_number >= 0x7fff) |
5769 | as_bad ("operand overflow"); | |
b9129c6f | 5770 | if (target_big_endian) |
8ea7f4e8 | 5771 | offset_expr.X_add_number += 1; |
0dd2d296 | 5772 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5773 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5774 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5775 | if (target_big_endian) |
8ea7f4e8 ILT |
5776 | offset_expr.X_add_number -= 1; |
5777 | else | |
5778 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5779 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5780 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5781 | break; |
3d3c5039 | 5782 | |
adcf2b9d ILT |
5783 | case M_USD: |
5784 | s = "sdl"; | |
5785 | s2 = "sdr"; | |
5786 | off = 7; | |
5787 | goto usw; | |
3d3c5039 | 5788 | case M_USW: |
adcf2b9d ILT |
5789 | s = "swl"; |
5790 | s2 = "swr"; | |
5791 | off = 3; | |
5792 | usw: | |
5793 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5794 | as_bad ("operand overflow"); |
b9129c6f | 5795 | if (! target_big_endian) |
adcf2b9d ILT |
5796 | offset_expr.X_add_number += off; |
5797 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5798 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5799 | if (! target_big_endian) |
adcf2b9d | 5800 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5801 | else |
adcf2b9d ILT |
5802 | offset_expr.X_add_number += off; |
5803 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5804 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5805 | return; |
3d3c5039 | 5806 | |
adcf2b9d ILT |
5807 | case M_USD_A: |
5808 | s = "sdl"; | |
5809 | s2 = "sdr"; | |
5810 | off = 7; | |
5811 | goto uswa; | |
3d3c5039 | 5812 | case M_USW_A: |
adcf2b9d ILT |
5813 | s = "swl"; |
5814 | s2 = "swr"; | |
5815 | off = 3; | |
5816 | uswa: | |
0dd2d296 | 5817 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5818 | if (breg != 0) |
5819 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5820 | mips_isa < 3 ? "addu" : "daddu", | |
5821 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5822 | if (! target_big_endian) |
adcf2b9d | 5823 | expr1.X_add_number = off; |
670a50eb | 5824 | else |
adcf2b9d ILT |
5825 | expr1.X_add_number = 0; |
5826 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5827 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5828 | if (! target_big_endian) |
adcf2b9d ILT |
5829 | expr1.X_add_number = 0; |
5830 | else | |
5831 | expr1.X_add_number = off; | |
5832 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5833 | (int) BFD_RELOC_LO16, AT); | |
5834 | break; | |
5835 | ||
5836 | case M_USH_A: | |
5837 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5838 | if (breg != 0) |
5839 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5840 | mips_isa < 3 ? "addu" : "daddu", | |
5841 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5842 | if (! target_big_endian) |
adcf2b9d ILT |
5843 | expr1.X_add_number = 0; |
5844 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5845 | (int) BFD_RELOC_LO16, AT); | |
5846 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5847 | treg, 8); | |
b9129c6f | 5848 | if (! target_big_endian) |
adcf2b9d ILT |
5849 | expr1.X_add_number = 1; |
5850 | else | |
5851 | expr1.X_add_number = 0; | |
5852 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5853 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5854 | if (! target_big_endian) |
adcf2b9d ILT |
5855 | expr1.X_add_number = 0; |
5856 | else | |
5857 | expr1.X_add_number = 1; | |
5858 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5859 | (int) BFD_RELOC_LO16, AT); | |
5860 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5861 | treg, 8); | |
5862 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5863 | treg, AT); | |
670a50eb | 5864 | break; |
3d3c5039 ILT |
5865 | |
5866 | default: | |
670a50eb | 5867 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5868 | break; |
3d3c5039 | 5869 | } |
670a50eb ILT |
5870 | if (mips_noat) |
5871 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5872 | } |
5873 | ||
cc5703cd | 5874 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5875 | |
3d3c5039 | 5876 | static void |
cc5703cd | 5877 | mips16_macro (ip) |
3d3c5039 ILT |
5878 | struct mips_cl_insn *ip; |
5879 | { | |
cc5703cd ILT |
5880 | int mask; |
5881 | int xreg, yreg, zreg, tmp; | |
5882 | int icnt; | |
5883 | expressionS expr1; | |
5884 | int dbl; | |
5885 | const char *s, *s2, *s3; | |
3d3c5039 | 5886 | |
cc5703cd | 5887 | mask = ip->insn_mo->mask; |
3d3c5039 | 5888 | |
cc5703cd ILT |
5889 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5890 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5891 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5892 | |
cc5703cd | 5893 | icnt = 0; |
8358c818 | 5894 | |
cc5703cd ILT |
5895 | expr1.X_op = O_constant; |
5896 | expr1.X_op_symbol = NULL; | |
5897 | expr1.X_add_symbol = NULL; | |
5898 | expr1.X_add_number = 1; | |
8358c818 | 5899 | |
cc5703cd | 5900 | dbl = 0; |
517078c1 | 5901 | |
cc5703cd ILT |
5902 | switch (mask) |
5903 | { | |
5904 | default: | |
5905 | internalError (); | |
5906 | ||
5907 | case M_DDIV_3: | |
5908 | dbl = 1; | |
5909 | case M_DIV_3: | |
5910 | s = "mflo"; | |
5911 | goto do_div3; | |
5912 | case M_DREM_3: | |
5913 | dbl = 1; | |
5914 | case M_REM_3: | |
5915 | s = "mfhi"; | |
5916 | do_div3: | |
fbcfacb7 | 5917 | mips_emit_delays (true); |
cc5703cd ILT |
5918 | ++mips_noreorder; |
5919 | mips_any_noreorder = 1; | |
5920 | macro_build ((char *) NULL, &icnt, NULL, | |
5921 | dbl ? "ddiv" : "div", | |
5922 | "0,x,y", xreg, yreg); | |
8a8121d5 | 5923 | expr1.X_add_number = 2; |
cc5703cd | 5924 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5925 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5926 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5927 | since that causes an overflow. We should do that as well, | |
5928 | but I don't see how to do the comparisons without a temporary | |
5929 | register. */ | |
5930 | --mips_noreorder; | |
5931 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5932 | break; | |
5933 | ||
5934 | case M_DIVU_3: | |
5935 | s = "divu"; | |
5936 | s2 = "mflo"; | |
5937 | goto do_divu3; | |
5938 | case M_REMU_3: | |
5939 | s = "divu"; | |
5940 | s2 = "mfhi"; | |
5941 | goto do_divu3; | |
5942 | case M_DDIVU_3: | |
5943 | s = "ddivu"; | |
5944 | s2 = "mflo"; | |
5945 | goto do_divu3; | |
5946 | case M_DREMU_3: | |
5947 | s = "ddivu"; | |
5948 | s2 = "mfhi"; | |
5949 | do_divu3: | |
fbcfacb7 | 5950 | mips_emit_delays (true); |
cc5703cd ILT |
5951 | ++mips_noreorder; |
5952 | mips_any_noreorder = 1; | |
5953 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 5954 | expr1.X_add_number = 2; |
cc5703cd | 5955 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5956 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5957 | --mips_noreorder; | |
5958 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5959 | break; | |
5960 | ||
5961 | case M_DSUBU_I: | |
5962 | dbl = 1; | |
5963 | goto do_subu; | |
5964 | case M_SUBU_I: | |
5965 | do_subu: | |
5966 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5967 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5968 | dbl ? "daddiu" : "addiu", | |
5969 | "y,x,4", yreg, xreg); | |
5970 | break; | |
5971 | ||
5972 | case M_SUBU_I_2: | |
5973 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5974 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5975 | "x,k", xreg); | |
5976 | break; | |
5977 | ||
5978 | case M_DSUBU_I_2: | |
5979 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5980 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5981 | "y,j", yreg); | |
5982 | break; | |
5983 | ||
5984 | case M_BEQ: | |
5985 | s = "cmp"; | |
5986 | s2 = "bteqz"; | |
5987 | goto do_branch; | |
5988 | case M_BNE: | |
5989 | s = "cmp"; | |
5990 | s2 = "btnez"; | |
5991 | goto do_branch; | |
5992 | case M_BLT: | |
5993 | s = "slt"; | |
5994 | s2 = "btnez"; | |
5995 | goto do_branch; | |
5996 | case M_BLTU: | |
5997 | s = "sltu"; | |
5998 | s2 = "btnez"; | |
5999 | goto do_branch; | |
6000 | case M_BLE: | |
6001 | s = "slt"; | |
6002 | s2 = "bteqz"; | |
6003 | goto do_reverse_branch; | |
6004 | case M_BLEU: | |
6005 | s = "sltu"; | |
6006 | s2 = "bteqz"; | |
6007 | goto do_reverse_branch; | |
6008 | case M_BGE: | |
6009 | s = "slt"; | |
6010 | s2 = "bteqz"; | |
6011 | goto do_branch; | |
6012 | case M_BGEU: | |
6013 | s = "sltu"; | |
6014 | s2 = "bteqz"; | |
6015 | goto do_branch; | |
6016 | case M_BGT: | |
6017 | s = "slt"; | |
6018 | s2 = "btnez"; | |
6019 | goto do_reverse_branch; | |
6020 | case M_BGTU: | |
6021 | s = "sltu"; | |
6022 | s2 = "btnez"; | |
6023 | ||
6024 | do_reverse_branch: | |
6025 | tmp = xreg; | |
6026 | xreg = yreg; | |
6027 | yreg = tmp; | |
6028 | ||
6029 | do_branch: | |
6030 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6031 | xreg, yreg); | |
6032 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6033 | break; | |
6034 | ||
6035 | case M_BEQ_I: | |
6036 | s = "cmpi"; | |
6037 | s2 = "bteqz"; | |
6038 | s3 = "x,U"; | |
6039 | goto do_branch_i; | |
6040 | case M_BNE_I: | |
6041 | s = "cmpi"; | |
6042 | s2 = "btnez"; | |
6043 | s3 = "x,U"; | |
6044 | goto do_branch_i; | |
6045 | case M_BLT_I: | |
6046 | s = "slti"; | |
6047 | s2 = "btnez"; | |
6048 | s3 = "x,8"; | |
6049 | goto do_branch_i; | |
6050 | case M_BLTU_I: | |
6051 | s = "sltiu"; | |
6052 | s2 = "btnez"; | |
6053 | s3 = "x,8"; | |
6054 | goto do_branch_i; | |
6055 | case M_BLE_I: | |
6056 | s = "slti"; | |
6057 | s2 = "btnez"; | |
6058 | s3 = "x,8"; | |
6059 | goto do_addone_branch_i; | |
6060 | case M_BLEU_I: | |
6061 | s = "sltiu"; | |
6062 | s2 = "btnez"; | |
6063 | s3 = "x,8"; | |
6064 | goto do_addone_branch_i; | |
6065 | case M_BGE_I: | |
6066 | s = "slti"; | |
6067 | s2 = "bteqz"; | |
6068 | s3 = "x,8"; | |
6069 | goto do_branch_i; | |
6070 | case M_BGEU_I: | |
6071 | s = "sltiu"; | |
6072 | s2 = "bteqz"; | |
6073 | s3 = "x,8"; | |
6074 | goto do_branch_i; | |
6075 | case M_BGT_I: | |
6076 | s = "slti"; | |
6077 | s2 = "bteqz"; | |
6078 | s3 = "x,8"; | |
6079 | goto do_addone_branch_i; | |
6080 | case M_BGTU_I: | |
6081 | s = "sltiu"; | |
6082 | s2 = "bteqz"; | |
6083 | s3 = "x,8"; | |
6084 | ||
6085 | do_addone_branch_i: | |
6086 | ++imm_expr.X_add_number; | |
6087 | ||
6088 | do_branch_i: | |
6089 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6090 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6091 | break; | |
18e0764d ILT |
6092 | |
6093 | case M_ABS: | |
6094 | expr1.X_add_number = 0; | |
6095 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6096 | if (xreg != yreg) | |
6097 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6098 | "move", "y,X", xreg, yreg); | |
6099 | expr1.X_add_number = 2; | |
6100 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6101 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6102 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6103 | } |
6104 | } | |
6105 | ||
6106 | /* This routine assembles an instruction into its binary format. As a | |
6107 | side effect, it sets one of the global variables imm_reloc or | |
6108 | offset_reloc to the type of relocation to do if one of the operands | |
6109 | is an address expression. */ | |
6110 | ||
6111 | static void | |
6112 | mips_ip (str, ip) | |
6113 | char *str; | |
6114 | struct mips_cl_insn *ip; | |
6115 | { | |
6116 | char *s; | |
6117 | const char *args; | |
6118 | char c; | |
6119 | struct mips_opcode *insn; | |
6120 | char *argsStart; | |
6121 | unsigned int regno; | |
6122 | unsigned int lastregno = 0; | |
6123 | char *s_reset; | |
6124 | ||
6125 | insn_error = NULL; | |
6126 | ||
6127 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
6128 | continue; | |
6129 | switch (*s) | |
6130 | { | |
6131 | case '\0': | |
6132 | break; | |
6133 | ||
6134 | case ' ': | |
6135 | *s++ = '\0'; | |
6136 | break; | |
6137 | ||
6138 | default: | |
6139 | as_fatal ("Unknown opcode: `%s'", str); | |
6140 | } | |
6141 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6142 | { | |
6143 | insn_error = "unrecognized opcode"; | |
6144 | return; | |
6145 | } | |
6146 | argsStart = s; | |
6147 | for (;;) | |
6148 | { | |
6149 | int insn_isa; | |
6150 | ||
6151 | assert (strcmp (insn->name, str) == 0); | |
6152 | ||
6153 | if (insn->pinfo == INSN_MACRO) | |
6154 | insn_isa = insn->match; | |
6155 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6156 | insn_isa = 2; | |
6157 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6158 | insn_isa = 3; | |
6159 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6160 | insn_isa = 4; | |
6161 | else | |
6162 | insn_isa = 1; | |
6163 | ||
6164 | if (insn_isa > mips_isa | |
16262668 ILT |
6165 | || (insn->pinfo != INSN_MACRO |
6166 | && (((insn->pinfo & INSN_ISA) == INSN_4650 | |
6167 | && ! mips_4650) | |
6168 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6169 | && ! mips_4010) | |
6170 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6171 | && ! mips_4100) | |
6172 | /* start-sanitize-r5900 */ | |
6173 | || ((insn->pinfo & INSN_ISA) == INSN_5900 | |
6174 | && ! mips_5900) | |
6175 | /* end-sanitize-r5900 */ | |
6176 | ))) | |
cc5703cd ILT |
6177 | { |
6178 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6179 | && strcmp (insn->name, insn[1].name) == 0) | |
6180 | { | |
6181 | ++insn; | |
6182 | continue; | |
6183 | } | |
6184 | if (insn_isa <= mips_isa) | |
6185 | insn_error = "opcode not supported on this processor"; | |
6186 | else | |
6187 | { | |
6188 | static char buf[100]; | |
6189 | ||
6190 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6191 | insn_error = buf; | |
6192 | } | |
6193 | return; | |
6194 | } | |
8358c818 | 6195 | |
670a50eb ILT |
6196 | ip->insn_mo = insn; |
6197 | ip->insn_opcode = insn->match; | |
6198 | for (args = insn->args;; ++args) | |
6199 | { | |
6200 | if (*s == ' ') | |
6201 | ++s; | |
6202 | switch (*args) | |
6203 | { | |
6204 | case '\0': /* end of args */ | |
6205 | if (*s == '\0') | |
6206 | return; | |
6207 | break; | |
3d3c5039 ILT |
6208 | |
6209 | case ',': | |
670a50eb ILT |
6210 | if (*s++ == *args) |
6211 | continue; | |
6212 | s--; | |
6213 | switch (*++args) | |
6214 | { | |
3d3c5039 ILT |
6215 | case 'r': |
6216 | case 'v': | |
670a50eb ILT |
6217 | ip->insn_opcode |= lastregno << 21; |
6218 | continue; | |
3d3c5039 ILT |
6219 | |
6220 | case 'w': | |
6221 | case 'W': | |
670a50eb ILT |
6222 | ip->insn_opcode |= lastregno << 16; |
6223 | continue; | |
3d3c5039 ILT |
6224 | |
6225 | case 'V': | |
670a50eb ILT |
6226 | ip->insn_opcode |= lastregno << 11; |
6227 | continue; | |
3d3c5039 | 6228 | } |
670a50eb | 6229 | break; |
3d3c5039 ILT |
6230 | |
6231 | case '(': | |
670a50eb ILT |
6232 | /* handle optional base register. |
6233 | Either the base register is omitted or | |
6234 | we must have a left paren. */ | |
6235 | /* this is dependent on the next operand specifier | |
6236 | is a 'b' for base register */ | |
6237 | assert (args[1] == 'b'); | |
6238 | if (*s == '\0') | |
6239 | return; | |
3d3c5039 | 6240 | |
670a50eb ILT |
6241 | case ')': /* these must match exactly */ |
6242 | if (*s++ == *args) | |
3d3c5039 | 6243 | continue; |
670a50eb ILT |
6244 | break; |
6245 | ||
6246 | case '<': /* must be at least one digit */ | |
6247 | /* | |
6248 | * According to the manual, if the shift amount is greater | |
6249 | * than 31 or less than 0 the the shift amount should be | |
6250 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6251 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6252 | */ |
6253 | my_getExpression (&imm_expr, s); | |
6254 | check_absolute_expr (ip, &imm_expr); | |
6255 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6256 | { | |
58d4951d ILT |
6257 | as_warn ("Improper shift amount (%ld)", |
6258 | (long) imm_expr.X_add_number); | |
9226253a | 6259 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6260 | } |
6261 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6262 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6263 | s = expr_end; |
6264 | continue; | |
6265 | ||
56c96faa ILT |
6266 | case '>': /* shift amount minus 32 */ |
6267 | my_getExpression (&imm_expr, s); | |
6268 | check_absolute_expr (ip, &imm_expr); | |
6269 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6270 | || (unsigned long) imm_expr.X_add_number > 63) | |
6271 | break; | |
6272 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6273 | imm_expr.X_op = O_absent; | |
6274 | s = expr_end; | |
6275 | continue; | |
6276 | ||
9226253a | 6277 | case 'k': /* cache code */ |
d8a1c247 | 6278 | case 'h': /* prefx code */ |
9226253a ILT |
6279 | my_getExpression (&imm_expr, s); |
6280 | check_absolute_expr (ip, &imm_expr); | |
6281 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6282 | { | |
d8a1c247 KR |
6283 | as_warn ("Invalid value for `%s' (%lu)", |
6284 | ip->insn_mo->name, | |
9226253a ILT |
6285 | (unsigned long) imm_expr.X_add_number); |
6286 | imm_expr.X_add_number &= 0x1f; | |
6287 | } | |
d8a1c247 KR |
6288 | if (*args == 'k') |
6289 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6290 | else | |
6291 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6292 | imm_expr.X_op = O_absent; |
6293 | s = expr_end; | |
6294 | continue; | |
6295 | ||
670a50eb ILT |
6296 | case 'c': /* break code */ |
6297 | my_getExpression (&imm_expr, s); | |
6298 | check_absolute_expr (ip, &imm_expr); | |
6299 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6300 | as_warn ("Illegal break code (%ld)", |
6301 | (long) imm_expr.X_add_number); | |
670a50eb | 6302 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6303 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6304 | s = expr_end; |
6305 | continue; | |
6306 | ||
918692a5 ILT |
6307 | case 'B': /* syscall code */ |
6308 | my_getExpression (&imm_expr, s); | |
6309 | check_absolute_expr (ip, &imm_expr); | |
6310 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6311 | as_warn ("Illegal syscall code (%ld)", |
6312 | (long) imm_expr.X_add_number); | |
918692a5 | 6313 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6314 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6315 | s = expr_end; |
6316 | continue; | |
6317 | ||
0aa07269 ILT |
6318 | case 'C': /* Coprocessor code */ |
6319 | my_getExpression (&imm_expr, s); | |
6320 | check_absolute_expr (ip, &imm_expr); | |
6321 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6322 | { | |
58d4951d ILT |
6323 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6324 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6325 | imm_expr.X_add_number &= ((1<<25) - 1); |
6326 | } | |
6327 | ip->insn_opcode |= imm_expr.X_add_number; | |
6328 | imm_expr.X_op = O_absent; | |
6329 | s = expr_end; | |
6330 | continue; | |
6331 | ||
670a50eb ILT |
6332 | case 'b': /* base register */ |
6333 | case 'd': /* destination register */ | |
6334 | case 's': /* source register */ | |
6335 | case 't': /* target register */ | |
6336 | case 'r': /* both target and source */ | |
6337 | case 'v': /* both dest and source */ | |
6338 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6339 | case 'E': /* coprocessor target register */ |
6340 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6341 | case 'x': /* ignore register name */ |
ff3a5c18 | 6342 | case 'z': /* must be zero register */ |
670a50eb ILT |
6343 | s_reset = s; |
6344 | if (s[0] == '$') | |
6345 | { | |
6346 | if (isdigit (s[1])) | |
6347 | { | |
6348 | ++s; | |
6349 | regno = 0; | |
6350 | do | |
6351 | { | |
6352 | regno *= 10; | |
6353 | regno += *s - '0'; | |
6354 | ++s; | |
6355 | } | |
6356 | while (isdigit (*s)); | |
0aa07269 ILT |
6357 | if (regno > 31) |
6358 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6359 | } |
0dd2d296 ILT |
6360 | else if (*args == 'E' || *args == 'G') |
6361 | goto notreg; | |
6362 | else | |
670a50eb | 6363 | { |
0aa07269 ILT |
6364 | if (s[1] == 'f' && s[2] == 'p') |
6365 | { | |
6366 | s += 3; | |
9226253a | 6367 | regno = FP; |
0aa07269 ILT |
6368 | } |
6369 | else if (s[1] == 's' && s[2] == 'p') | |
6370 | { | |
6371 | s += 3; | |
9226253a | 6372 | regno = SP; |
0aa07269 ILT |
6373 | } |
6374 | else if (s[1] == 'g' && s[2] == 'p') | |
6375 | { | |
6376 | s += 3; | |
9226253a | 6377 | regno = GP; |
0aa07269 ILT |
6378 | } |
6379 | else if (s[1] == 'a' && s[2] == 't') | |
6380 | { | |
6381 | s += 3; | |
9226253a | 6382 | regno = AT; |
0aa07269 | 6383 | } |
b2b8c24e ILT |
6384 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6385 | { | |
6386 | s += 4; | |
6387 | regno = KT0; | |
6388 | } | |
6389 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6390 | { | |
6391 | s += 4; | |
6392 | regno = KT1; | |
6393 | } | |
0aa07269 ILT |
6394 | else |
6395 | goto notreg; | |
670a50eb | 6396 | } |
9753202d ILT |
6397 | if (regno == AT |
6398 | && ! mips_noat | |
6399 | && *args != 'E' | |
6400 | && *args != 'G') | |
13fe1379 | 6401 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6402 | c = *args; |
6403 | if (*s == ' ') | |
6404 | s++; | |
6405 | if (args[1] != *s) | |
6406 | { | |
6407 | if (c == 'r' || c == 'v' || c == 'w') | |
6408 | { | |
6409 | regno = lastregno; | |
6410 | s = s_reset; | |
6411 | args++; | |
6412 | } | |
6413 | } | |
ff3a5c18 ILT |
6414 | /* 'z' only matches $0. */ |
6415 | if (c == 'z' && regno != 0) | |
6416 | break; | |
670a50eb ILT |
6417 | switch (c) |
6418 | { | |
3d3c5039 ILT |
6419 | case 'r': |
6420 | case 's': | |
6421 | case 'v': | |
6422 | case 'b': | |
670a50eb ILT |
6423 | ip->insn_opcode |= regno << 21; |
6424 | break; | |
3d3c5039 | 6425 | case 'd': |
918692a5 | 6426 | case 'G': |
670a50eb ILT |
6427 | ip->insn_opcode |= regno << 11; |
6428 | break; | |
3d3c5039 ILT |
6429 | case 'w': |
6430 | case 't': | |
918692a5 | 6431 | case 'E': |
670a50eb | 6432 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6433 | break; |
6434 | case 'x': | |
6435 | /* This case exists because on the r3000 trunc | |
6436 | expands into a macro which requires a gp | |
6437 | register. On the r6000 or r4000 it is | |
6438 | assembled into a single instruction which | |
6439 | ignores the register. Thus the insn version | |
6440 | is MIPS_ISA2 and uses 'x', and the macro | |
6441 | version is MIPS_ISA1 and uses 't'. */ | |
6442 | break; | |
ff3a5c18 ILT |
6443 | case 'z': |
6444 | /* This case is for the div instruction, which | |
6445 | acts differently if the destination argument | |
6446 | is $0. This only matches $0, and is checked | |
6447 | outside the switch. */ | |
6448 | break; | |
3d3c5039 | 6449 | } |
670a50eb ILT |
6450 | lastregno = regno; |
6451 | continue; | |
3d3c5039 ILT |
6452 | } |
6453 | notreg: | |
670a50eb ILT |
6454 | switch (*args++) |
6455 | { | |
3d3c5039 ILT |
6456 | case 'r': |
6457 | case 'v': | |
670a50eb ILT |
6458 | ip->insn_opcode |= lastregno << 21; |
6459 | continue; | |
3d3c5039 | 6460 | case 'w': |
670a50eb ILT |
6461 | ip->insn_opcode |= lastregno << 16; |
6462 | continue; | |
3d3c5039 | 6463 | } |
670a50eb | 6464 | break; |
3d3c5039 | 6465 | |
670a50eb ILT |
6466 | case 'D': /* floating point destination register */ |
6467 | case 'S': /* floating point source register */ | |
6468 | case 'T': /* floating point target register */ | |
d8a1c247 | 6469 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6470 | case 'V': |
6471 | case 'W': | |
670a50eb ILT |
6472 | s_reset = s; |
6473 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6474 | { | |
6475 | s += 2; | |
6476 | regno = 0; | |
6477 | do | |
6478 | { | |
6479 | regno *= 10; | |
6480 | regno += *s - '0'; | |
6481 | ++s; | |
6482 | } | |
6483 | while (isdigit (*s)); | |
6484 | ||
6485 | if (regno > 31) | |
6486 | as_bad ("Invalid float register number (%d)", regno); | |
6487 | ||
9226253a ILT |
6488 | if ((regno & 1) != 0 |
6489 | && mips_isa < 3 | |
538034cf ILT |
6490 | && ! (strcmp (str, "mtc1") == 0 |
6491 | || strcmp (str, "mfc1") == 0 | |
6492 | || strcmp (str, "lwc1") == 0 | |
6493 | || strcmp (str, "swc1") == 0 | |
6494 | || strcmp (str, "l.s") == 0 | |
6495 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6496 | as_warn ("Float register should be even, was %d", |
6497 | regno); | |
6498 | ||
6499 | c = *args; | |
6500 | if (*s == ' ') | |
6501 | s++; | |
6502 | if (args[1] != *s) | |
6503 | { | |
6504 | if (c == 'V' || c == 'W') | |
6505 | { | |
6506 | regno = lastregno; | |
6507 | s = s_reset; | |
6508 | args++; | |
3d3c5039 ILT |
6509 | } |
6510 | } | |
670a50eb ILT |
6511 | switch (c) |
6512 | { | |
3d3c5039 | 6513 | case 'D': |
670a50eb ILT |
6514 | ip->insn_opcode |= regno << 6; |
6515 | break; | |
3d3c5039 ILT |
6516 | case 'V': |
6517 | case 'S': | |
670a50eb ILT |
6518 | ip->insn_opcode |= regno << 11; |
6519 | break; | |
3d3c5039 ILT |
6520 | case 'W': |
6521 | case 'T': | |
670a50eb | 6522 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6523 | break; |
6524 | case 'R': | |
6525 | ip->insn_opcode |= regno << 21; | |
6526 | break; | |
3d3c5039 | 6527 | } |
670a50eb ILT |
6528 | lastregno = regno; |
6529 | continue; | |
3d3c5039 | 6530 | } |
670a50eb ILT |
6531 | switch (*args++) |
6532 | { | |
3d3c5039 | 6533 | case 'V': |
670a50eb ILT |
6534 | ip->insn_opcode |= lastregno << 11; |
6535 | continue; | |
3d3c5039 | 6536 | case 'W': |
670a50eb ILT |
6537 | ip->insn_opcode |= lastregno << 16; |
6538 | continue; | |
3d3c5039 | 6539 | } |
670a50eb | 6540 | break; |
3d3c5039 ILT |
6541 | |
6542 | case 'I': | |
670a50eb | 6543 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6544 | if (imm_expr.X_op != O_big |
6545 | && imm_expr.X_op != O_constant) | |
6546 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6547 | s = expr_end; |
6548 | continue; | |
3d3c5039 ILT |
6549 | |
6550 | case 'A': | |
670a50eb ILT |
6551 | my_getExpression (&offset_expr, s); |
6552 | imm_reloc = BFD_RELOC_32; | |
6553 | s = expr_end; | |
6554 | continue; | |
3d3c5039 ILT |
6555 | |
6556 | case 'F': | |
19ed8960 ILT |
6557 | case 'L': |
6558 | case 'f': | |
6559 | case 'l': | |
6560 | { | |
6561 | int f64; | |
6562 | char *save_in; | |
6563 | char *err; | |
6564 | unsigned char temp[8]; | |
604633ae ILT |
6565 | int len; |
6566 | unsigned int length; | |
19ed8960 ILT |
6567 | segT seg; |
6568 | subsegT subseg; | |
6569 | char *p; | |
6570 | ||
6571 | /* These only appear as the last operand in an | |
6572 | instruction, and every instruction that accepts | |
6573 | them in any variant accepts them in all variants. | |
6574 | This means we don't have to worry about backing out | |
6575 | any changes if the instruction does not match. | |
6576 | ||
6577 | The difference between them is the size of the | |
6578 | floating point constant and where it goes. For 'F' | |
6579 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6580 | is 32 bits. Where the constant is placed is based | |
6581 | on how the MIPS assembler does things: | |
6582 | F -- .rdata | |
6583 | L -- .lit8 | |
6584 | f -- immediate value | |
6585 | l -- .lit4 | |
0dd2d296 | 6586 | |
55933a58 ILT |
6587 | The .lit4 and .lit8 sections are only used if |
6588 | permitted by the -G argument. | |
6589 | ||
6590 | When generating embedded PIC code, we use the | |
6591 | .lit8 section but not the .lit4 section (we can do | |
6592 | .lit4 inline easily; we need to put .lit8 | |
6593 | somewhere in the data segment, and using .lit8 | |
6594 | permits the linker to eventually combine identical | |
6595 | .lit8 entries). */ | |
19ed8960 ILT |
6596 | |
6597 | f64 = *args == 'F' || *args == 'L'; | |
6598 | ||
6599 | save_in = input_line_pointer; | |
6600 | input_line_pointer = s; | |
604633ae ILT |
6601 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6602 | length = len; | |
19ed8960 ILT |
6603 | s = input_line_pointer; |
6604 | input_line_pointer = save_in; | |
6605 | if (err != NULL && *err != '\0') | |
6606 | { | |
6607 | as_bad ("Bad floating point constant: %s", err); | |
6608 | memset (temp, '\0', sizeof temp); | |
6609 | length = f64 ? 8 : 4; | |
6610 | } | |
6611 | ||
6612 | assert (length == (f64 ? 8 : 4)); | |
6613 | ||
0dd2d296 | 6614 | if (*args == 'f' |
55933a58 | 6615 | || (*args == 'l' |
1dc1e798 KR |
6616 | && (! USE_GLOBAL_POINTER_OPT |
6617 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6618 | || g_switch_value < 4) |
1113140a | 6619 | )) |
19ed8960 ILT |
6620 | { |
6621 | imm_expr.X_op = O_constant; | |
b9129c6f | 6622 | if (! target_big_endian) |
19ed8960 ILT |
6623 | imm_expr.X_add_number = |
6624 | (((((((int) temp[3] << 8) | |
6625 | | temp[2]) << 8) | |
6626 | | temp[1]) << 8) | |
6627 | | temp[0]); | |
6628 | else | |
6629 | imm_expr.X_add_number = | |
6630 | (((((((int) temp[0] << 8) | |
6631 | | temp[1]) << 8) | |
6632 | | temp[2]) << 8) | |
6633 | | temp[3]); | |
6634 | } | |
6635 | else | |
6636 | { | |
0dd2d296 ILT |
6637 | const char *newname; |
6638 | segT new_seg; | |
6639 | ||
19ed8960 ILT |
6640 | /* Switch to the right section. */ |
6641 | seg = now_seg; | |
6642 | subseg = now_subseg; | |
6643 | switch (*args) | |
6644 | { | |
0dd2d296 | 6645 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6646 | case 'L': |
1113140a | 6647 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6648 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6649 | newname = ".lit8"; |
0dd2d296 ILT |
6650 | break; |
6651 | case 'F': | |
d2c71068 | 6652 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6653 | break; |
6654 | case 'l': | |
1dc1e798 KR |
6655 | assert (!USE_GLOBAL_POINTER_OPT |
6656 | || g_switch_value >= 4); | |
0dd2d296 | 6657 | newname = ".lit4"; |
19ed8960 ILT |
6658 | break; |
6659 | } | |
0dd2d296 | 6660 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6661 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6662 | bfd_set_section_flags (stdoutput, new_seg, | |
6663 | (SEC_ALLOC | |
6664 | | SEC_LOAD | |
6665 | | SEC_READONLY | |
6666 | | SEC_DATA)); | |
0221ddf7 | 6667 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6668 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6669 | record_alignment (new_seg, 4); | |
6670 | else | |
6671 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6672 | if (seg == now_seg) |
6673 | as_bad ("Can't use floating point insn in this section"); | |
6674 | ||
6675 | /* Set the argument to the current address in the | |
6e8dda9c | 6676 | section. */ |
19ed8960 ILT |
6677 | offset_expr.X_op = O_symbol; |
6678 | offset_expr.X_add_symbol = | |
6679 | symbol_new ("L0\001", now_seg, | |
6680 | (valueT) frag_now_fix (), frag_now); | |
6681 | offset_expr.X_add_number = 0; | |
6682 | ||
6683 | /* Put the floating point number into the section. */ | |
604633ae | 6684 | p = frag_more ((int) length); |
19ed8960 ILT |
6685 | memcpy (p, temp, length); |
6686 | ||
6687 | /* Switch back to the original section. */ | |
6688 | subseg_set (seg, subseg); | |
6689 | } | |
6690 | } | |
670a50eb ILT |
6691 | continue; |
6692 | ||
6693 | case 'i': /* 16 bit unsigned immediate */ | |
6694 | case 'j': /* 16 bit signed immediate */ | |
6695 | imm_reloc = BFD_RELOC_LO16; | |
6696 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6697 | if (c != '\0') |
670a50eb ILT |
6698 | { |
6699 | if (c != 'l') | |
6700 | { | |
5ac34ac3 | 6701 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6702 | imm_expr.X_add_number = |
6703 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6704 | else if (c == 'h') | |
867a58b3 ILT |
6705 | { |
6706 | imm_reloc = BFD_RELOC_HI16_S; | |
6707 | imm_unmatched_hi = true; | |
6708 | } | |
670a50eb ILT |
6709 | else |
6710 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6711 | } |
670a50eb | 6712 | } |
670a50eb ILT |
6713 | if (*args == 'i') |
6714 | { | |
344a8d61 | 6715 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6716 | || ((imm_expr.X_add_number < 0 |
6717 | || imm_expr.X_add_number >= 0x10000) | |
6718 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6719 | { |
6720 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6721 | !strcmp (insn->name, insn[1].name)) | |
6722 | break; | |
9753202d ILT |
6723 | if (imm_expr.X_op != O_constant |
6724 | && imm_expr.X_op != O_big) | |
6725 | insn_error = "absolute expression required"; | |
6726 | else | |
6727 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6728 | } |
670a50eb ILT |
6729 | } |
6730 | else | |
6731 | { | |
d9aba805 ILT |
6732 | int more; |
6733 | offsetT max; | |
6734 | ||
be22008b ILT |
6735 | /* The upper bound should be 0x8000, but |
6736 | unfortunately the MIPS assembler accepts numbers | |
6737 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6738 | we want to be compatible. We only permit this |
6739 | extended range for an instruction which does not | |
6740 | provide any further alternates, since those | |
6741 | alternates may handle other cases. People should | |
6742 | use the numbers they mean, rather than relying on | |
6743 | a mysterious sign extension. */ | |
6744 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6745 | strcmp (insn->name, insn[1].name) == 0); | |
6746 | if (more) | |
6747 | max = 0x8000; | |
6748 | else | |
6749 | max = 0x10000; | |
344a8d61 | 6750 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6751 | || ((imm_expr.X_add_number < -0x8000 |
6752 | || imm_expr.X_add_number >= max) | |
6753 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6754 | || (more |
6755 | && imm_expr.X_add_number < 0 | |
6756 | && mips_isa >= 3 | |
6757 | && imm_expr.X_unsigned | |
6758 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6759 | { |
d9aba805 | 6760 | if (more) |
99c24539 | 6761 | break; |
9753202d ILT |
6762 | if (imm_expr.X_op != O_constant |
6763 | && imm_expr.X_op != O_big) | |
6764 | insn_error = "absolute expression required"; | |
6765 | else | |
6766 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6767 | } |
3d3c5039 | 6768 | } |
670a50eb ILT |
6769 | s = expr_end; |
6770 | continue; | |
6771 | ||
6772 | case 'o': /* 16 bit offset */ | |
6773 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6774 | |
6775 | /* If this value won't fit into a 16 bit offset, then go | |
6776 | find a macro that will generate the 32 bit offset | |
6777 | code pattern. As a special hack, we accept the | |
6778 | difference of two local symbols as a constant. This | |
6779 | is required to suppose embedded PIC switches, which | |
6780 | use an instruction which looks like | |
6781 | lw $4,$L12-$LS12($4) | |
6782 | The problem with handling this in a more general | |
6783 | fashion is that the macro function doesn't expect to | |
6784 | see anything which can be handled in a single | |
6785 | constant instruction. */ | |
6f0b87c3 SS |
6786 | if (c == 0 |
6787 | && (offset_expr.X_op != O_constant | |
6788 | || offset_expr.X_add_number >= 0x8000 | |
6789 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6790 | && (mips_pic != EMBEDDED_PIC |
6791 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6792 | || now_seg != text_section |
6793 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6794 | != text_section))) | |
670a50eb | 6795 | break; |
3d3c5039 | 6796 | |
670a50eb ILT |
6797 | offset_reloc = BFD_RELOC_LO16; |
6798 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6799 | { |
6800 | assert (offset_expr.X_op == O_constant); | |
6801 | offset_expr.X_add_number = | |
6802 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6803 | } | |
cc5703cd ILT |
6804 | s = expr_end; |
6805 | continue; | |
6806 | ||
6807 | case 'p': /* pc relative offset */ | |
6808 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6809 | my_getExpression (&offset_expr, s); | |
6810 | s = expr_end; | |
6811 | continue; | |
6812 | ||
6813 | case 'u': /* upper 16 bits */ | |
6814 | c = my_getSmallExpression (&imm_expr, s); | |
6815 | if (imm_expr.X_op == O_constant | |
6816 | && (imm_expr.X_add_number < 0 | |
6817 | || imm_expr.X_add_number >= 0x10000)) | |
6818 | as_bad ("lui expression not in range 0..65535"); | |
6819 | imm_reloc = BFD_RELOC_LO16; | |
6820 | if (c) | |
6821 | { | |
6822 | if (c != 'l') | |
6823 | { | |
6824 | if (imm_expr.X_op == O_constant) | |
6825 | imm_expr.X_add_number = | |
6826 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6827 | else if (c == 'h') | |
6828 | { | |
6829 | imm_reloc = BFD_RELOC_HI16_S; | |
6830 | imm_unmatched_hi = true; | |
6831 | } | |
6832 | else | |
6833 | imm_reloc = BFD_RELOC_HI16; | |
6834 | } | |
6835 | } | |
6836 | s = expr_end; | |
6837 | continue; | |
6838 | ||
6839 | case 'a': /* 26 bit address */ | |
6840 | my_getExpression (&offset_expr, s); | |
6841 | s = expr_end; | |
6842 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6843 | continue; | |
6844 | ||
6845 | case 'N': /* 3 bit branch condition code */ | |
6846 | case 'M': /* 3 bit compare condition code */ | |
6847 | if (strncmp (s, "$fcc", 4) != 0) | |
6848 | break; | |
6849 | s += 4; | |
6850 | regno = 0; | |
6851 | do | |
6852 | { | |
6853 | regno *= 10; | |
6854 | regno += *s - '0'; | |
6855 | ++s; | |
6856 | } | |
6857 | while (isdigit (*s)); | |
6858 | if (regno > 7) | |
6859 | as_bad ("invalid condition code register $fcc%d", regno); | |
6860 | if (*args == 'N') | |
6861 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6862 | else | |
6863 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6864 | continue; | |
6865 | ||
6866 | default: | |
6867 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6868 | internalError (); | |
6869 | } | |
6870 | break; | |
6871 | } | |
6872 | /* Args don't match. */ | |
6873 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6874 | !strcmp (insn->name, insn[1].name)) | |
6875 | { | |
6876 | ++insn; | |
6877 | s = argsStart; | |
6878 | continue; | |
6879 | } | |
6880 | insn_error = "illegal operands"; | |
6881 | return; | |
6882 | } | |
6883 | } | |
6884 | ||
6885 | /* This routine assembles an instruction into its binary format when | |
6886 | assembling for the mips16. As a side effect, it sets one of the | |
6887 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
6888 | relocation to do if one of the operands is an address expression. |
6889 | It also sets mips16_small and mips16_ext if the user explicitly | |
6890 | requested a small or extended instruction. */ | |
cc5703cd ILT |
6891 | |
6892 | static void | |
6893 | mips16_ip (str, ip) | |
6894 | char *str; | |
6895 | struct mips_cl_insn *ip; | |
6896 | { | |
6897 | char *s; | |
cc5703cd ILT |
6898 | const char *args; |
6899 | struct mips_opcode *insn; | |
6900 | char *argsstart; | |
6901 | unsigned int regno; | |
6902 | unsigned int lastregno = 0; | |
6903 | char *s_reset; | |
6904 | ||
6905 | insn_error = NULL; | |
6906 | ||
8728fa92 ILT |
6907 | mips16_small = false; |
6908 | mips16_ext = false; | |
cc5703cd ILT |
6909 | |
6910 | for (s = str; islower (*s); ++s) | |
6911 | ; | |
6912 | switch (*s) | |
6913 | { | |
6914 | case '\0': | |
6915 | break; | |
6916 | ||
6917 | case ' ': | |
6918 | *s++ = '\0'; | |
6919 | break; | |
6920 | ||
6921 | case '.': | |
6922 | if (s[1] == 't' && s[2] == ' ') | |
6923 | { | |
6924 | *s = '\0'; | |
8728fa92 | 6925 | mips16_small = true; |
cc5703cd ILT |
6926 | s += 3; |
6927 | break; | |
6928 | } | |
6929 | else if (s[1] == 'e' && s[2] == ' ') | |
6930 | { | |
6931 | *s = '\0'; | |
8728fa92 | 6932 | mips16_ext = true; |
cc5703cd ILT |
6933 | s += 3; |
6934 | break; | |
6935 | } | |
6936 | /* Fall through. */ | |
6937 | default: | |
6938 | insn_error = "unknown opcode"; | |
6939 | return; | |
6940 | } | |
6941 | ||
8728fa92 ILT |
6942 | if (! mips16_autoextend && ! mips16_ext) |
6943 | mips16_small = true; | |
6944 | ||
cc5703cd ILT |
6945 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
6946 | { | |
6947 | insn_error = "unrecognized opcode"; | |
6948 | return; | |
6949 | } | |
6950 | ||
6951 | argsstart = s; | |
6952 | for (;;) | |
6953 | { | |
6954 | assert (strcmp (insn->name, str) == 0); | |
6955 | ||
6956 | ip->insn_mo = insn; | |
6957 | ip->insn_opcode = insn->match; | |
6958 | ip->use_extend = false; | |
6959 | imm_expr.X_op = O_absent; | |
6960 | imm_reloc = BFD_RELOC_UNUSED; | |
6961 | offset_expr.X_op = O_absent; | |
6962 | offset_reloc = BFD_RELOC_UNUSED; | |
6963 | for (args = insn->args; 1; ++args) | |
6964 | { | |
6965 | int c; | |
6966 | ||
6967 | if (*s == ' ') | |
6968 | ++s; | |
6969 | ||
6970 | /* In this switch statement we call break if we did not find | |
6971 | a match, continue if we did find a match, or return if we | |
6972 | are done. */ | |
6973 | ||
6974 | c = *args; | |
6975 | switch (c) | |
6976 | { | |
6977 | case '\0': | |
6978 | if (*s == '\0') | |
6979 | { | |
6980 | /* Stuff the immediate value in now, if we can. */ | |
6981 | if (imm_expr.X_op == O_constant | |
6982 | && imm_reloc > BFD_RELOC_UNUSED | |
6983 | && insn->pinfo != INSN_MACRO) | |
6984 | { | |
15e69f98 ILT |
6985 | mips16_immed ((char *) NULL, 0, |
6986 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
6987 | imm_expr.X_add_number, true, mips16_small, |
6988 | mips16_ext, &ip->insn_opcode, | |
6989 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
6990 | imm_expr.X_op = O_absent; |
6991 | imm_reloc = BFD_RELOC_UNUSED; | |
6992 | } | |
6993 | ||
6994 | return; | |
6995 | } | |
6996 | break; | |
6997 | ||
6998 | case ',': | |
6999 | if (*s++ == c) | |
7000 | continue; | |
7001 | s--; | |
7002 | switch (*++args) | |
7003 | { | |
7004 | case 'v': | |
7005 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7006 | continue; | |
7007 | case 'w': | |
7008 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7009 | continue; | |
7010 | } | |
7011 | break; | |
7012 | ||
7013 | case '(': | |
7014 | case ')': | |
7015 | if (*s++ == c) | |
7016 | continue; | |
7017 | break; | |
7018 | ||
7019 | case 'v': | |
7020 | case 'w': | |
7021 | if (s[0] != '$') | |
7022 | { | |
7023 | if (c == 'v') | |
7024 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7025 | else | |
7026 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7027 | ++args; | |
7028 | continue; | |
7029 | } | |
7030 | /* Fall through. */ | |
7031 | case 'x': | |
7032 | case 'y': | |
7033 | case 'z': | |
7034 | case 'Z': | |
7035 | case '0': | |
7036 | case 'S': | |
7037 | case 'R': | |
7038 | case 'X': | |
7039 | case 'Y': | |
7040 | if (s[0] != '$') | |
7041 | break; | |
7042 | s_reset = s; | |
7043 | if (isdigit (s[1])) | |
7044 | { | |
7045 | ++s; | |
7046 | regno = 0; | |
7047 | do | |
7048 | { | |
7049 | regno *= 10; | |
7050 | regno += *s - '0'; | |
7051 | ++s; | |
7052 | } | |
7053 | while (isdigit (*s)); | |
7054 | if (regno > 31) | |
7055 | { | |
7056 | as_bad ("invalid register number (%d)", regno); | |
7057 | regno = 2; | |
7058 | } | |
7059 | } | |
7060 | else | |
7061 | { | |
7062 | if (s[1] == 'f' && s[2] == 'p') | |
7063 | { | |
7064 | s += 3; | |
7065 | regno = FP; | |
7066 | } | |
7067 | else if (s[1] == 's' && s[2] == 'p') | |
7068 | { | |
7069 | s += 3; | |
7070 | regno = SP; | |
7071 | } | |
7072 | else if (s[1] == 'g' && s[2] == 'p') | |
7073 | { | |
7074 | s += 3; | |
7075 | regno = GP; | |
7076 | } | |
7077 | else if (s[1] == 'a' && s[2] == 't') | |
7078 | { | |
7079 | s += 3; | |
7080 | regno = AT; | |
7081 | } | |
7082 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7083 | { | |
7084 | s += 4; | |
7085 | regno = KT0; | |
7086 | } | |
7087 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7088 | { | |
7089 | s += 4; | |
7090 | regno = KT1; | |
7091 | } | |
7092 | else | |
7093 | break; | |
7094 | } | |
7095 | ||
7096 | if (*s == ' ') | |
7097 | ++s; | |
7098 | if (args[1] != *s) | |
7099 | { | |
7100 | if (c == 'v' || c == 'w') | |
7101 | { | |
7102 | regno = mips16_to_32_reg_map[lastregno]; | |
7103 | s = s_reset; | |
7104 | args++; | |
7105 | } | |
7106 | } | |
7107 | ||
7108 | switch (c) | |
7109 | { | |
7110 | case 'x': | |
7111 | case 'y': | |
7112 | case 'z': | |
7113 | case 'v': | |
7114 | case 'w': | |
7115 | case 'Z': | |
7116 | regno = mips32_to_16_reg_map[regno]; | |
7117 | break; | |
7118 | ||
7119 | case '0': | |
7120 | if (regno != 0) | |
7121 | regno = ILLEGAL_REG; | |
7122 | break; | |
7123 | ||
7124 | case 'S': | |
7125 | if (regno != SP) | |
7126 | regno = ILLEGAL_REG; | |
7127 | break; | |
7128 | ||
7129 | case 'R': | |
7130 | if (regno != RA) | |
7131 | regno = ILLEGAL_REG; | |
7132 | break; | |
7133 | ||
7134 | case 'X': | |
7135 | case 'Y': | |
7136 | if (regno == AT && ! mips_noat) | |
7137 | as_warn ("used $at without \".set noat\""); | |
7138 | break; | |
7139 | ||
7140 | default: | |
7141 | internalError (); | |
7142 | } | |
7143 | ||
7144 | if (regno == ILLEGAL_REG) | |
7145 | break; | |
7146 | ||
7147 | switch (c) | |
7148 | { | |
7149 | case 'x': | |
7150 | case 'v': | |
7151 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7152 | break; | |
7153 | case 'y': | |
7154 | case 'w': | |
7155 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7156 | break; | |
7157 | case 'z': | |
7158 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7159 | break; | |
7160 | case 'Z': | |
7161 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7162 | case '0': | |
7163 | case 'S': | |
7164 | case 'R': | |
7165 | break; | |
7166 | case 'X': | |
7167 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7168 | break; | |
7169 | case 'Y': | |
7170 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7171 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7172 | break; | |
7173 | default: | |
7174 | internalError (); | |
7175 | } | |
7176 | ||
7177 | lastregno = regno; | |
7178 | continue; | |
7179 | ||
7180 | case 'P': | |
7181 | if (strncmp (s, "$pc", 3) == 0) | |
7182 | { | |
7183 | s += 3; | |
7184 | continue; | |
7185 | } | |
7186 | break; | |
7187 | ||
7188 | case '<': | |
7189 | case '>': | |
7190 | case '[': | |
7191 | case ']': | |
7192 | case '4': | |
7193 | case '5': | |
7194 | case 'H': | |
7195 | case 'W': | |
7196 | case 'D': | |
7197 | case 'j': | |
7198 | case '8': | |
7199 | case 'V': | |
7200 | case 'C': | |
7201 | case 'U': | |
7202 | case 'k': | |
7203 | case 'K': | |
16262668 ILT |
7204 | if (s[0] == '%' |
7205 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7206 | { | |
7207 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7208 | and generate the appropriate reloc. If the text | |
7209 | inside %gprel is not a symbol name with an | |
7210 | optional offset, then we generate a normal reloc | |
7211 | and will probably fail later. */ | |
7212 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7213 | if (imm_expr.X_op == O_symbol) | |
7214 | { | |
7215 | mips16_ext = true; | |
7216 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7217 | s = expr_end; | |
7218 | ip->use_extend = true; | |
7219 | ip->extend = 0; | |
7220 | continue; | |
7221 | } | |
7222 | } | |
7223 | else | |
7224 | { | |
7225 | /* Just pick up a normal expression. */ | |
7226 | my_getExpression (&imm_expr, s); | |
7227 | } | |
7228 | ||
ebf28372 ILT |
7229 | if (imm_expr.X_op == O_register) |
7230 | { | |
7231 | /* What we thought was an expression turned out to | |
7232 | be a register. */ | |
7233 | ||
7234 | if (s[0] == '(' && args[1] == '(') | |
7235 | { | |
7236 | /* It looks like the expression was omitted | |
7237 | before a register indirection, which means | |
7238 | that the expression is implicitly zero. We | |
7239 | still set up imm_expr, so that we handle | |
7240 | explicit extensions correctly. */ | |
7241 | imm_expr.X_op = O_constant; | |
7242 | imm_expr.X_add_number = 0; | |
7243 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7244 | continue; | |
7245 | } | |
7246 | ||
7247 | break; | |
7248 | } | |
7249 | ||
cc5703cd ILT |
7250 | /* We need to relax this instruction. */ |
7251 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7252 | s = expr_end; | |
7253 | continue; | |
7254 | ||
7255 | case 'p': | |
7256 | case 'q': | |
7257 | case 'A': | |
7258 | case 'B': | |
7259 | case 'E': | |
7260 | /* We use offset_reloc rather than imm_reloc for the PC | |
7261 | relative operands. This lets macros with both | |
7262 | immediate and address operands work correctly. */ | |
670a50eb | 7263 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7264 | |
7265 | if (offset_expr.X_op == O_register) | |
7266 | break; | |
7267 | ||
cc5703cd ILT |
7268 | /* We need to relax this instruction. */ |
7269 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7270 | s = expr_end; |
7271 | continue; | |
7272 | ||
cc5703cd ILT |
7273 | case '6': /* break code */ |
7274 | my_getExpression (&imm_expr, s); | |
7275 | check_absolute_expr (ip, &imm_expr); | |
7276 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7277 | { |
cc5703cd ILT |
7278 | as_warn ("Invalid value for `%s' (%lu)", |
7279 | ip->insn_mo->name, | |
7280 | (unsigned long) imm_expr.X_add_number); | |
7281 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7282 | } |
cc5703cd ILT |
7283 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7284 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7285 | s = expr_end; |
7286 | continue; | |
3d3c5039 | 7287 | |
670a50eb ILT |
7288 | case 'a': /* 26 bit address */ |
7289 | my_getExpression (&offset_expr, s); | |
7290 | s = expr_end; | |
cc5703cd ILT |
7291 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7292 | ip->insn_opcode <<= 16; | |
670a50eb | 7293 | continue; |
3d3c5039 | 7294 | |
cc5703cd ILT |
7295 | case 'l': /* register list for entry macro */ |
7296 | case 'L': /* register list for exit macro */ | |
7297 | { | |
7298 | int mask; | |
7299 | ||
7300 | if (c == 'l') | |
7301 | mask = 0; | |
7302 | else | |
7303 | mask = 7 << 3; | |
7304 | while (*s != '\0') | |
7305 | { | |
c9167640 | 7306 | int freg, reg1, reg2; |
cc5703cd ILT |
7307 | |
7308 | while (*s == ' ' || *s == ',') | |
7309 | ++s; | |
7310 | if (*s != '$') | |
7311 | { | |
7312 | as_bad ("can't parse register list"); | |
7313 | break; | |
7314 | } | |
7315 | ++s; | |
c9167640 ILT |
7316 | if (*s != 'f') |
7317 | freg = 0; | |
7318 | else | |
7319 | { | |
7320 | freg = 1; | |
7321 | ++s; | |
7322 | } | |
cc5703cd ILT |
7323 | reg1 = 0; |
7324 | while (isdigit (*s)) | |
7325 | { | |
7326 | reg1 *= 10; | |
7327 | reg1 += *s - '0'; | |
7328 | ++s; | |
7329 | } | |
7330 | if (*s == ' ') | |
7331 | ++s; | |
7332 | if (*s != '-') | |
7333 | reg2 = reg1; | |
7334 | else | |
7335 | { | |
7336 | ++s; | |
7337 | if (*s != '$') | |
7338 | break; | |
7339 | ++s; | |
c9167640 ILT |
7340 | if (freg) |
7341 | { | |
7342 | if (*s == 'f') | |
7343 | ++s; | |
7344 | else | |
7345 | { | |
7346 | as_bad ("invalid register list"); | |
7347 | break; | |
7348 | } | |
7349 | } | |
cc5703cd ILT |
7350 | reg2 = 0; |
7351 | while (isdigit (*s)) | |
7352 | { | |
7353 | reg2 *= 10; | |
7354 | reg2 += *s - '0'; | |
7355 | ++s; | |
7356 | } | |
7357 | } | |
c9167640 ILT |
7358 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7359 | { | |
7360 | mask &= ~ (7 << 3); | |
7361 | mask |= 5 << 3; | |
7362 | } | |
7363 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7364 | { | |
7365 | mask &= ~ (7 << 3); | |
7366 | mask |= 6 << 3; | |
7367 | } | |
7368 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7369 | mask |= (reg2 - 3) << 3; |
7370 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7371 | mask |= (reg2 - 15) << 1; | |
7372 | else if (reg1 == 31 && reg2 == 31) | |
7373 | mask |= 1; | |
7374 | else | |
c9167640 ILT |
7375 | { |
7376 | as_bad ("invalid register list"); | |
7377 | break; | |
7378 | } | |
cc5703cd | 7379 | } |
c9167640 ILT |
7380 | /* The mask is filled in in the opcode table for the |
7381 | benefit of the disassembler. We remove it before | |
7382 | applying the actual mask. */ | |
7383 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7384 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7385 | } | |
7386 | continue; | |
d8a1c247 | 7387 | |
3d3c5039 | 7388 | default: |
670a50eb | 7389 | internalError (); |
3d3c5039 | 7390 | } |
670a50eb | 7391 | break; |
3d3c5039 | 7392 | } |
cc5703cd | 7393 | |
670a50eb | 7394 | /* Args don't match. */ |
cc5703cd ILT |
7395 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7396 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7397 | { |
7398 | ++insn; | |
cc5703cd | 7399 | s = argsstart; |
670a50eb | 7400 | continue; |
3d3c5039 | 7401 | } |
cc5703cd | 7402 | |
9753202d | 7403 | insn_error = "illegal operands"; |
cc5703cd | 7404 | |
670a50eb | 7405 | return; |
3d3c5039 ILT |
7406 | } |
7407 | } | |
7408 | ||
cc5703cd ILT |
7409 | /* This structure holds information we know about a mips16 immediate |
7410 | argument type. */ | |
7411 | ||
7412 | struct mips16_immed_operand | |
7413 | { | |
7414 | /* The type code used in the argument string in the opcode table. */ | |
7415 | int type; | |
7416 | /* The number of bits in the short form of the opcode. */ | |
7417 | int nbits; | |
7418 | /* The number of bits in the extended form of the opcode. */ | |
7419 | int extbits; | |
7420 | /* The amount by which the short form is shifted when it is used; | |
7421 | for example, the sw instruction has a shift count of 2. */ | |
7422 | int shift; | |
7423 | /* The amount by which the short form is shifted when it is stored | |
7424 | into the instruction code. */ | |
7425 | int op_shift; | |
7426 | /* Non-zero if the short form is unsigned. */ | |
7427 | int unsp; | |
7428 | /* Non-zero if the extended form is unsigned. */ | |
7429 | int extu; | |
7430 | /* Non-zero if the value is PC relative. */ | |
7431 | int pcrel; | |
7432 | }; | |
7433 | ||
7434 | /* The mips16 immediate operand types. */ | |
7435 | ||
7436 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7437 | { | |
7438 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7439 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7440 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7441 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7442 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7443 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7444 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7445 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7446 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7447 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7448 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7449 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7450 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7451 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7452 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7453 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7454 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7455 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7456 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7457 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7458 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7459 | }; | |
7460 | ||
7461 | #define MIPS16_NUM_IMMED \ | |
7462 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7463 | ||
7464 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7465 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7466 | whether an extended value is needed; if one is needed, it sets | |
7467 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7468 | If SMALL is true, an unextended opcode was explicitly requested. | |
7469 | If EXT is true, an extended opcode was explicitly requested. If | |
7470 | WARN is true, warn if EXT does not match reality. */ | |
7471 | ||
7472 | static void | |
15e69f98 ILT |
7473 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7474 | extend) | |
7475 | char *file; | |
7476 | unsigned int line; | |
cc5703cd ILT |
7477 | int type; |
7478 | offsetT val; | |
7479 | boolean warn; | |
7480 | boolean small; | |
7481 | boolean ext; | |
7482 | unsigned long *insn; | |
7483 | boolean *use_extend; | |
7484 | unsigned short *extend; | |
7485 | { | |
7486 | register const struct mips16_immed_operand *op; | |
7487 | int mintiny, maxtiny; | |
7488 | boolean needext; | |
7489 | ||
7490 | op = mips16_immed_operands; | |
7491 | while (op->type != type) | |
7492 | { | |
7493 | ++op; | |
7494 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7495 | } | |
7496 | ||
7497 | if (op->unsp) | |
7498 | { | |
7499 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7500 | { | |
7501 | mintiny = 1; | |
7502 | maxtiny = 1 << op->nbits; | |
7503 | } | |
7504 | else | |
7505 | { | |
7506 | mintiny = 0; | |
7507 | maxtiny = (1 << op->nbits) - 1; | |
7508 | } | |
7509 | } | |
7510 | else | |
7511 | { | |
7512 | mintiny = - (1 << (op->nbits - 1)); | |
7513 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7514 | } | |
7515 | ||
7516 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7517 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7518 | val /= 2; |
cc5703cd ILT |
7519 | |
7520 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7521 | || val < (mintiny << op->shift) | |
7522 | || val > (maxtiny << op->shift)) | |
7523 | needext = true; | |
7524 | else | |
7525 | needext = false; | |
7526 | ||
7527 | if (warn && ext && ! needext) | |
15e69f98 | 7528 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7529 | if (small && needext) |
15e69f98 | 7530 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7531 | |
7532 | if (small || (! ext && ! needext)) | |
7533 | { | |
7534 | int insnval; | |
7535 | ||
7536 | *use_extend = false; | |
7537 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7538 | insnval <<= op->op_shift; | |
7539 | *insn |= insnval; | |
7540 | } | |
7541 | else | |
7542 | { | |
7543 | long minext, maxext; | |
7544 | int extval; | |
7545 | ||
7546 | if (op->extu) | |
7547 | { | |
7548 | minext = 0; | |
7549 | maxext = (1 << op->extbits) - 1; | |
7550 | } | |
7551 | else | |
7552 | { | |
7553 | minext = - (1 << (op->extbits - 1)); | |
7554 | maxext = (1 << (op->extbits - 1)) - 1; | |
7555 | } | |
7556 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7557 | as_bad_where (file, line, |
7558 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7559 | |
7560 | *use_extend = true; | |
7561 | if (op->extbits == 16) | |
7562 | { | |
7563 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7564 | val &= 0x1f; | |
7565 | } | |
7566 | else if (op->extbits == 15) | |
7567 | { | |
7568 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7569 | val &= 0xf; | |
7570 | } | |
7571 | else | |
7572 | { | |
7573 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7574 | val = 0; | |
7575 | } | |
7576 | ||
7577 | *extend = (unsigned short) extval; | |
7578 | *insn |= val; | |
7579 | } | |
7580 | } | |
7581 | \f | |
3d3c5039 ILT |
7582 | #define LP '(' |
7583 | #define RP ')' | |
7584 | ||
7585 | static int | |
7586 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7587 | expressionS *ep; |
7588 | char *str; | |
3d3c5039 | 7589 | { |
670a50eb ILT |
7590 | char *sp; |
7591 | int c = 0; | |
7592 | ||
7593 | if (*str == ' ') | |
7594 | str++; | |
7595 | if (*str == LP | |
7596 | || (*str == '%' && | |
7597 | ((str[1] == 'h' && str[2] == 'i') | |
7598 | || (str[1] == 'H' && str[2] == 'I') | |
7599 | || (str[1] == 'l' && str[2] == 'o')) | |
7600 | && str[3] == LP)) | |
7601 | { | |
7602 | if (*str == LP) | |
7603 | c = 0; | |
7604 | else | |
7605 | { | |
7606 | c = str[1]; | |
7607 | str += 3; | |
7608 | } | |
7609 | ||
7610 | /* | |
7611 | * A small expression may be followed by a base register. | |
7612 | * Scan to the end of this operand, and then back over a possible | |
7613 | * base register. Then scan the small expression up to that | |
7614 | * point. (Based on code in sparc.c...) | |
7615 | */ | |
7616 | for (sp = str; *sp && *sp != ','; sp++) | |
7617 | ; | |
7618 | if (sp - 4 >= str && sp[-1] == RP) | |
7619 | { | |
7620 | if (isdigit (sp[-2])) | |
7621 | { | |
7622 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7623 | ; | |
7624 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7625 | { | |
7626 | sp--; | |
7627 | goto do_it; | |
3d3c5039 | 7628 | } |
670a50eb ILT |
7629 | } |
7630 | else if (sp - 5 >= str | |
7631 | && sp[-5] == LP | |
7632 | && sp[-4] == '$' | |
7633 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7634 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7635 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7636 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7637 | { | |
7638 | sp -= 5; | |
3d3c5039 | 7639 | do_it: |
670a50eb ILT |
7640 | if (sp == str) |
7641 | { | |
7642 | /* no expression means zero offset */ | |
7643 | if (c) | |
7644 | { | |
7645 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7646 | ep->X_op = O_absent; |
670a50eb | 7647 | expr_end = str - 3; |
3d3c5039 | 7648 | } |
670a50eb ILT |
7649 | else |
7650 | { | |
52aa70b5 | 7651 | ep->X_op = O_constant; |
670a50eb ILT |
7652 | expr_end = sp; |
7653 | } | |
7654 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7655 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7656 | ep->X_add_number = 0; |
7657 | } | |
7658 | else | |
7659 | { | |
7660 | *sp = '\0'; | |
7661 | my_getExpression (ep, str); | |
7662 | *sp = LP; | |
3d3c5039 | 7663 | } |
670a50eb | 7664 | return c; |
3d3c5039 ILT |
7665 | } |
7666 | } | |
7667 | } | |
670a50eb ILT |
7668 | my_getExpression (ep, str); |
7669 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7670 | } |
7671 | ||
7672 | static void | |
7673 | my_getExpression (ep, str) | |
670a50eb ILT |
7674 | expressionS *ep; |
7675 | char *str; | |
3d3c5039 | 7676 | { |
670a50eb | 7677 | char *save_in; |
670a50eb ILT |
7678 | |
7679 | save_in = input_line_pointer; | |
7680 | input_line_pointer = str; | |
5ac34ac3 | 7681 | expression (ep); |
670a50eb ILT |
7682 | expr_end = input_line_pointer; |
7683 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7684 | } |
7685 | ||
becfe05e ILT |
7686 | /* Turn a string in input_line_pointer into a floating point constant |
7687 | of type type, and store the appropriate bytes in *litP. The number | |
7688 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7689 | returned, or NULL on OK. */ | |
7690 | ||
3d3c5039 | 7691 | char * |
670a50eb | 7692 | md_atof (type, litP, sizeP) |
becfe05e | 7693 | int type; |
3d3c5039 ILT |
7694 | char *litP; |
7695 | int *sizeP; | |
7696 | { | |
becfe05e ILT |
7697 | int prec; |
7698 | LITTLENUM_TYPE words[4]; | |
7699 | char *t; | |
7700 | int i; | |
7701 | ||
7702 | switch (type) | |
7703 | { | |
7704 | case 'f': | |
7705 | prec = 2; | |
7706 | break; | |
7707 | ||
7708 | case 'd': | |
7709 | prec = 4; | |
7710 | break; | |
7711 | ||
7712 | default: | |
7713 | *sizeP = 0; | |
7714 | return "bad call to md_atof"; | |
7715 | } | |
7716 | ||
7717 | t = atof_ieee (input_line_pointer, type, words); | |
7718 | if (t) | |
7719 | input_line_pointer = t; | |
7720 | ||
7721 | *sizeP = prec * 2; | |
7722 | ||
b9129c6f | 7723 | if (! target_big_endian) |
becfe05e ILT |
7724 | { |
7725 | for (i = prec - 1; i >= 0; i--) | |
7726 | { | |
7727 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7728 | litP += 2; | |
7729 | } | |
7730 | } | |
7731 | else | |
7732 | { | |
7733 | for (i = 0; i < prec; i++) | |
7734 | { | |
7735 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7736 | litP += 2; | |
7737 | } | |
7738 | } | |
7739 | ||
670a50eb | 7740 | return NULL; |
3d3c5039 ILT |
7741 | } |
7742 | ||
7743 | void | |
7744 | md_number_to_chars (buf, val, n) | |
7745 | char *buf; | |
918692a5 | 7746 | valueT val; |
3d3c5039 ILT |
7747 | int n; |
7748 | { | |
b9129c6f ILT |
7749 | if (target_big_endian) |
7750 | number_to_chars_bigendian (buf, val, n); | |
7751 | else | |
7752 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 7753 | } |
f3d817d8 | 7754 | \f |
e8d4d475 | 7755 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7756 | |
f3d817d8 DM |
7757 | struct option md_longopts[] = { |
7758 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7759 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7760 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7761 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7762 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7763 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7764 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7765 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7766 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7767 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7768 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7769 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7770 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7771 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7772 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7773 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7774 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7775 | {"break", no_argument, NULL, OPTION_BREAK}, |
7776 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7777 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7778 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7779 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7780 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7781 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7782 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7783 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7784 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7785 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7786 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7787 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7788 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7789 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7790 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7791 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7792 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7793 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7794 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7795 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7796 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
276c2d7d GRK |
7797 | /* start-sanitize-5900 */ |
7798 | #define OPTION_M5900 (OPTION_MD_BASE + 24) | |
7799 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
7800 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
7801 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
7802 | /* end-sanitize-5900 */ | |
f3d817d8 | 7803 | |
d8a1c247 | 7804 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7805 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7806 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7807 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7808 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7809 | #ifdef OBJ_ELF |
f3d817d8 | 7810 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7811 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7812 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7813 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7814 | {"32", no_argument, NULL, OPTION_32}, |
7815 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7816 | #endif |
7817 | ||
7818 | {NULL, no_argument, NULL, 0} | |
7819 | }; | |
7820 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7821 | |
7822 | int | |
f3d817d8 DM |
7823 | md_parse_option (c, arg) |
7824 | int c; | |
7825 | char *arg; | |
3d3c5039 | 7826 | { |
f3d817d8 | 7827 | switch (c) |
670a50eb | 7828 | { |
f3d817d8 DM |
7829 | case OPTION_TRAP: |
7830 | mips_trap = 1; | |
7831 | break; | |
670a50eb | 7832 | |
f3d817d8 DM |
7833 | case OPTION_BREAK: |
7834 | mips_trap = 0; | |
7835 | break; | |
7836 | ||
e8d4d475 | 7837 | case OPTION_EB: |
1dc1e798 | 7838 | target_big_endian = 1; |
e8d4d475 | 7839 | break; |
04cb3372 | 7840 | |
e8d4d475 | 7841 | case OPTION_EL: |
1dc1e798 | 7842 | target_big_endian = 0; |
f3d817d8 | 7843 | break; |
670a50eb | 7844 | |
f3d817d8 DM |
7845 | case 'O': |
7846 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7847 | mips_optimize = 1; |
7848 | else | |
7849 | mips_optimize = 2; | |
f3d817d8 | 7850 | break; |
0aa07269 | 7851 | |
f3d817d8 | 7852 | case 'g': |
22ba90ce ILT |
7853 | if (arg == NULL) |
7854 | mips_debug = 2; | |
7855 | else | |
7856 | mips_debug = atoi (arg); | |
7857 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7858 | optimizations which limit full symbolic debugging. We take | |
7859 | that to be equivalent to -O0. */ | |
7860 | if (mips_debug == 2) | |
0aa07269 | 7861 | mips_optimize = 0; |
f3d817d8 | 7862 | break; |
4e95866e | 7863 | |
f3d817d8 DM |
7864 | case OPTION_MIPS1: |
7865 | mips_isa = 1; | |
4bb0cc41 ILT |
7866 | if (mips_cpu == -1) |
7867 | mips_cpu = 3000; | |
f3d817d8 | 7868 | break; |
8358c818 | 7869 | |
f3d817d8 DM |
7870 | case OPTION_MIPS2: |
7871 | mips_isa = 2; | |
4bb0cc41 ILT |
7872 | if (mips_cpu == -1) |
7873 | mips_cpu = 6000; | |
f3d817d8 | 7874 | break; |
8358c818 | 7875 | |
f3d817d8 DM |
7876 | case OPTION_MIPS3: |
7877 | mips_isa = 3; | |
4bb0cc41 ILT |
7878 | if (mips_cpu == -1) |
7879 | mips_cpu = 4000; | |
f3d817d8 | 7880 | break; |
8358c818 | 7881 | |
d8a1c247 KR |
7882 | case OPTION_MIPS4: |
7883 | mips_isa = 4; | |
7884 | if (mips_cpu == -1) | |
7885 | mips_cpu = 8000; | |
7886 | break; | |
7887 | ||
f3d817d8 DM |
7888 | case OPTION_MCPU: |
7889 | { | |
7890 | char *p; | |
7891 | ||
7892 | /* Identify the processor type */ | |
7893 | p = arg; | |
7894 | if (strcmp (p, "default") == 0 | |
7895 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7896 | mips_cpu = -1; |
f3d817d8 DM |
7897 | else |
7898 | { | |
c625fc23 JSC |
7899 | int sv = 0; |
7900 | ||
7901 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7902 | processor. */ | |
7903 | if (*p == 'v' || *p == 'V') | |
7904 | { | |
7905 | sv = 1; | |
7906 | p++; | |
7907 | } | |
7908 | ||
f3d817d8 DM |
7909 | if (*p == 'r' || *p == 'R') |
7910 | p++; | |
8358c818 | 7911 | |
4bb0cc41 | 7912 | mips_cpu = -1; |
f3d817d8 DM |
7913 | switch (*p) |
7914 | { | |
d8a1c247 KR |
7915 | case '1': |
7916 | if (strcmp (p, "10000") == 0 | |
7917 | || strcmp (p, "10k") == 0 | |
7918 | || strcmp (p, "10K") == 0) | |
7919 | mips_cpu = 10000; | |
7920 | break; | |
7921 | ||
f3d817d8 DM |
7922 | case '2': |
7923 | if (strcmp (p, "2000") == 0 | |
7924 | || strcmp (p, "2k") == 0 | |
7925 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7926 | mips_cpu = 2000; |
f3d817d8 | 7927 | break; |
8358c818 | 7928 | |
f3d817d8 DM |
7929 | case '3': |
7930 | if (strcmp (p, "3000") == 0 | |
7931 | || strcmp (p, "3k") == 0 | |
7932 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7933 | mips_cpu = 3000; |
f3d817d8 | 7934 | break; |
8358c818 | 7935 | |
f3d817d8 DM |
7936 | case '4': |
7937 | if (strcmp (p, "4000") == 0 | |
7938 | || strcmp (p, "4k") == 0 | |
8c63448a | 7939 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7940 | mips_cpu = 4000; |
c625fc23 JSC |
7941 | else if (strcmp (p, "4100") == 0) |
7942 | { | |
7943 | mips_cpu = 4100; | |
7944 | if (mips_4100 < 0) | |
7945 | mips_4100 = 1; | |
7946 | } | |
7947 | else if (strcmp (p, "4300") == 0) | |
7948 | mips_cpu = 4300; | |
8c63448a | 7949 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7950 | mips_cpu = 4400; |
8c63448a | 7951 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7952 | mips_cpu = 4600; |
b2b8c24e ILT |
7953 | else if (strcmp (p, "4650") == 0) |
7954 | { | |
7955 | mips_cpu = 4650; | |
7956 | if (mips_4650 < 0) | |
7957 | mips_4650 = 1; | |
7958 | } | |
e532b44c ILT |
7959 | else if (strcmp (p, "4010") == 0) |
7960 | { | |
7961 | mips_cpu = 4010; | |
7962 | if (mips_4010 < 0) | |
7963 | mips_4010 = 1; | |
7964 | } | |
f3d817d8 | 7965 | break; |
8358c818 | 7966 | |
517078c1 ILT |
7967 | case '5': |
7968 | if (strcmp (p, "5000") == 0 | |
7969 | || strcmp (p, "5k") == 0 | |
7970 | || strcmp (p, "5K") == 0) | |
7971 | mips_cpu = 5000; | |
276c2d7d GRK |
7972 | /* start-sanitize-r5900 */ |
7973 | else if (strcmp (p, "5900") == 0) | |
7974 | mips_cpu = 5900; | |
7975 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
7976 | break; |
7977 | ||
f3d817d8 DM |
7978 | case '6': |
7979 | if (strcmp (p, "6000") == 0 | |
7980 | || strcmp (p, "6k") == 0 | |
7981 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7982 | mips_cpu = 6000; |
f3d817d8 | 7983 | break; |
55933a58 | 7984 | |
d8a1c247 KR |
7985 | case '8': |
7986 | if (strcmp (p, "8000") == 0 | |
7987 | || strcmp (p, "8k") == 0 | |
7988 | || strcmp (p, "8K") == 0) | |
7989 | mips_cpu = 8000; | |
7990 | break; | |
7991 | ||
55933a58 ILT |
7992 | case 'o': |
7993 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 7994 | mips_cpu = 4600; |
55933a58 | 7995 | break; |
f3d817d8 | 7996 | } |
8358c818 | 7997 | |
517078c1 | 7998 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
7999 | { |
8000 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8001 | return 0; | |
8002 | } | |
8003 | ||
4bb0cc41 | 8004 | if (mips_cpu == -1) |
f3d817d8 DM |
8005 | { |
8006 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8007 | return 0; | |
8008 | } | |
8009 | } | |
8010 | } | |
8011 | break; | |
8358c818 | 8012 | |
b2b8c24e ILT |
8013 | case OPTION_M4650: |
8014 | mips_4650 = 1; | |
8015 | break; | |
8016 | ||
8017 | case OPTION_NO_M4650: | |
8018 | mips_4650 = 0; | |
8019 | break; | |
8020 | ||
e532b44c ILT |
8021 | case OPTION_M4010: |
8022 | mips_4010 = 1; | |
8023 | break; | |
8024 | ||
8025 | case OPTION_NO_M4010: | |
8026 | mips_4010 = 0; | |
8027 | break; | |
8028 | ||
c625fc23 JSC |
8029 | case OPTION_M4100: |
8030 | mips_4100 = 1; | |
8031 | break; | |
8032 | ||
8033 | case OPTION_NO_M4100: | |
8034 | mips_4100 = 0; | |
8035 | break; | |
8036 | ||
276c2d7d GRK |
8037 | /* start-sanitize-r5900 */ |
8038 | case OPTION_M5900: | |
8039 | mips_5900 = 1; | |
8040 | break; | |
8041 | ||
8042 | case OPTION_NO_M5900: | |
8043 | mips_5900 = 0; | |
8044 | break; | |
8045 | /* end-sanitize-r5900 */ | |
8046 | ||
cc5703cd ILT |
8047 | case OPTION_MIPS16: |
8048 | mips16 = 1; | |
8049 | mips_no_prev_insn (); | |
8050 | break; | |
8051 | ||
8052 | case OPTION_NO_MIPS16: | |
8053 | mips16 = 0; | |
8054 | mips_no_prev_insn (); | |
8055 | break; | |
8056 | ||
f3d817d8 | 8057 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8058 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8059 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8060 | { |
8061 | as_bad ("-G may not be used with embedded PIC code"); | |
8062 | return 0; | |
8063 | } | |
5b63f465 | 8064 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8065 | break; |
d9aba805 | 8066 | |
fb251650 ILT |
8067 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8068 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8069 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8070 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8071 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8072 | { | |
8073 | as_bad ("-call_shared is supported only for ELF format"); | |
8074 | return 0; | |
8075 | } | |
d9aba805 ILT |
8076 | mips_pic = SVR4_PIC; |
8077 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8078 | { |
8079 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8080 | return 0; | |
8081 | } | |
d9aba805 | 8082 | g_switch_value = 0; |
f3d817d8 DM |
8083 | break; |
8084 | ||
8085 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8086 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8087 | { | |
8088 | as_bad ("-non_shared is supported only for ELF format"); | |
8089 | return 0; | |
8090 | } | |
d9aba805 | 8091 | mips_pic = NO_PIC; |
f3d817d8 | 8092 | break; |
8358c818 | 8093 | |
fb251650 ILT |
8094 | /* The -xgot option tells the assembler to use 32 offsets when |
8095 | accessing the got in SVR4_PIC mode. It is for Irix | |
8096 | compatibility. */ | |
8097 | case OPTION_XGOT: | |
8098 | mips_big_got = 1; | |
8099 | break; | |
8100 | ||
f3d817d8 | 8101 | case 'G': |
1dc1e798 KR |
8102 | if (! USE_GLOBAL_POINTER_OPT) |
8103 | { | |
8104 | as_bad ("-G is not supported for this configuration"); | |
8105 | return 0; | |
8106 | } | |
8107 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8108 | { |
f3d817d8 DM |
8109 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8110 | return 0; | |
670a50eb ILT |
8111 | } |
8112 | else | |
f3d817d8 | 8113 | g_switch_value = atoi (arg); |
42562568 | 8114 | g_switch_seen = 1; |
f3d817d8 | 8115 | break; |
4e95866e | 8116 | |
7f9880e5 ILT |
8117 | /* The -32 and -64 options tell the assembler to output the 32 |
8118 | bit or the 64 bit MIPS ELF format. */ | |
8119 | case OPTION_32: | |
8120 | mips_64 = 0; | |
8121 | break; | |
8122 | ||
8123 | case OPTION_64: | |
9c44af60 ILT |
8124 | { |
8125 | const char **list, **l; | |
8126 | ||
8127 | list = bfd_target_list (); | |
8128 | for (l = list; *l != NULL; l++) | |
8129 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8130 | || strcmp (*l, "elf64-littlemips") == 0) | |
8131 | break; | |
8132 | if (*l == NULL) | |
8133 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8134 | free (list); | |
8135 | mips_64 = 1; | |
8136 | } | |
7f9880e5 ILT |
8137 | break; |
8138 | ||
f3d817d8 DM |
8139 | default: |
8140 | return 0; | |
8ea7f4e8 ILT |
8141 | } |
8142 | ||
f3d817d8 | 8143 | return 1; |
8ea7f4e8 ILT |
8144 | } |
8145 | ||
f3d817d8 DM |
8146 | void |
8147 | md_show_usage (stream) | |
8148 | FILE *stream; | |
8149 | { | |
8150 | fprintf(stream, "\ | |
8151 | MIPS options:\n\ | |
8152 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8153 | -EB generate big endian output\n\ |
8154 | -EL generate little endian output\n\ | |
8155 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8156 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8157 | implicitly with the gp register [default 8]\n"); |
8158 | fprintf(stream, "\ | |
f3d817d8 DM |
8159 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8160 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8161 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8162 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8163 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8164 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8165 | -m4650 permit R4650 instructions\n\ |
8166 | -no-m4650 do not permit R4650 instructions\n\ | |
8167 | -m4010 permit R4010 instructions\n\ | |
8168 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8169 | -m4100 permit VR4100 instructions\n\ |
8170 | -no-m4100 do not permit VR4100 instructions\n"); | |
8171 | fprintf(stream, "\ | |
cc5703cd ILT |
8172 | -mips16 generate mips16 instructions\n\ |
8173 | -no-mips16 do not generate mips16 instructions\n"); | |
8174 | fprintf(stream, "\ | |
f3d817d8 DM |
8175 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8176 | -O remove unneeded NOPs and swap branches\n\ | |
8177 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8178 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8179 | #ifdef OBJ_ELF | |
8180 | fprintf(stream, "\ | |
8181 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8182 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8183 | -xgot assume a 32 bit GOT\n\ |
8184 | -32 create 32 bit object file (default)\n\ | |
8185 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8186 | #endif |
8187 | } | |
8188 | \f | |
3d3c5039 ILT |
8189 | long |
8190 | md_pcrel_from (fixP) | |
8191 | fixS *fixP; | |
8192 | { | |
1dc1e798 KR |
8193 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8194 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8195 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8196 | { | |
8197 | /* This makes a branch to an undefined symbol be a branch to the | |
8198 | current location. */ | |
8199 | return 4; | |
8200 | } | |
5b63f465 | 8201 | |
670a50eb ILT |
8202 | /* return the address of the delay slot */ |
8203 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8204 | } |
8205 | ||
abdad6bc ILT |
8206 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8207 | reloc for a cons. We could use the definition there, except that | |
8208 | we want to handle 64 bit relocs specially. */ | |
8209 | ||
8210 | void | |
8211 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8212 | fragS *frag; | |
8213 | int where; | |
8214 | unsigned int nbytes; | |
8215 | expressionS *exp; | |
8216 | { | |
bf39474f | 8217 | #ifndef OBJ_ELF |
abdad6bc | 8218 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8219 | 4 byte reloc. */ |
8220 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8221 | { |
b9129c6f | 8222 | if (target_big_endian) |
abdad6bc ILT |
8223 | where += 4; |
8224 | nbytes = 4; | |
8225 | } | |
bf39474f | 8226 | #endif |
abdad6bc | 8227 | |
7f9880e5 | 8228 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8229 | as_bad ("Unsupported reloc size %d", nbytes); |
8230 | ||
8231 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8232 | (nbytes == 2 |
8233 | ? BFD_RELOC_16 | |
8234 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8235 | } |
8236 | ||
867a58b3 ILT |
8237 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8238 | the corresponding LO reloc. This is called before md_apply_fix and | |
8239 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8240 | explicit use of the %hi modifier. */ | |
8241 | ||
8242 | void | |
8243 | mips_frob_file () | |
8244 | { | |
8245 | struct mips_hi_fixup *l; | |
8246 | ||
8247 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8248 | { | |
8249 | segment_info_type *seginfo; | |
9b61d62b | 8250 | int pass; |
867a58b3 ILT |
8251 | |
8252 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8253 | ||
8254 | /* Check quickly whether the next fixup happens to be a matching | |
8255 | %lo. */ | |
8256 | if (l->fixp->fx_next != NULL | |
8257 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8258 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8259 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8260 | continue; | |
8261 | ||
8262 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8263 | When we find one, move the %hi just in front of it. We do |
8264 | this in two passes. In the first pass, we try to find a | |
8265 | unique %lo. In the second pass, we permit multiple %hi | |
8266 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8267 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8268 | for (pass = 0; pass < 2; pass++) |
8269 | { | |
8270 | fixS *f, *prev; | |
8271 | ||
8272 | prev = NULL; | |
8273 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8274 | { |
9b61d62b ILT |
8275 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8276 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8277 | && f->fx_addsy == l->fixp->fx_addsy | |
8278 | && f->fx_offset == l->fixp->fx_offset | |
8279 | && (pass == 1 | |
8280 | || prev == NULL | |
8281 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8282 | || prev->fx_addsy != f->fx_addsy | |
8283 | || prev->fx_offset != f->fx_offset)) | |
8284 | { | |
8285 | fixS **pf; | |
867a58b3 | 8286 | |
9b61d62b ILT |
8287 | /* Move l->fixp before f. */ |
8288 | for (pf = &seginfo->fix_root; | |
8289 | *pf != l->fixp; | |
8290 | pf = &(*pf)->fx_next) | |
8291 | assert (*pf != NULL); | |
867a58b3 | 8292 | |
9b61d62b | 8293 | *pf = l->fixp->fx_next; |
867a58b3 | 8294 | |
9b61d62b ILT |
8295 | l->fixp->fx_next = f; |
8296 | if (prev == NULL) | |
8297 | seginfo->fix_root = l->fixp; | |
8298 | else | |
8299 | prev->fx_next = l->fixp; | |
867a58b3 | 8300 | |
9b61d62b ILT |
8301 | break; |
8302 | } | |
8303 | ||
8304 | prev = f; | |
867a58b3 ILT |
8305 | } |
8306 | ||
9b61d62b ILT |
8307 | if (f != NULL) |
8308 | break; | |
867a58b3 | 8309 | |
9b61d62b ILT |
8310 | if (pass == 1) |
8311 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8312 | "Unmatched %%hi reloc"); | |
8313 | } | |
867a58b3 ILT |
8314 | } |
8315 | } | |
8316 | ||
1c803e52 ILT |
8317 | /* When generating embedded PIC code we need to use a special |
8318 | relocation to represent the difference of two symbols in the .text | |
8319 | section (switch tables use a difference of this sort). See | |
8320 | include/coff/mips.h for details. This macro checks whether this | |
8321 | fixup requires the special reloc. */ | |
8322 | #define SWITCH_TABLE(fixp) \ | |
8323 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8324 | && (fixp)->fx_addsy != NULL \ | |
8325 | && (fixp)->fx_subsy != NULL \ | |
8326 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8327 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8328 | ||
5b63f465 | 8329 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8330 | relocations, in case the linker has to relax a call. We also need |
8331 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8332 | |
8333 | /*ARGSUSED*/ | |
8334 | int | |
8335 | mips_force_relocation (fixp) | |
8336 | fixS *fixp; | |
8337 | { | |
1c803e52 | 8338 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8339 | && (fixp->fx_pcrel |
8340 | || SWITCH_TABLE (fixp) | |
8341 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8342 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8343 | } |
8344 | ||
8345 | /* Apply a fixup to the object file. */ | |
8346 | ||
3d3c5039 ILT |
8347 | int |
8348 | md_apply_fix (fixP, valueP) | |
8349 | fixS *fixP; | |
918692a5 | 8350 | valueT *valueP; |
3d3c5039 | 8351 | { |
670a50eb ILT |
8352 | unsigned char *buf; |
8353 | long insn, value; | |
3d3c5039 | 8354 | |
bf39474f ILT |
8355 | assert (fixP->fx_size == 4 |
8356 | || fixP->fx_r_type == BFD_RELOC_16 | |
8357 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8358 | |
670a50eb | 8359 | value = *valueP; |
1748b9d8 ILT |
8360 | |
8361 | /* If we aren't adjusting this fixup to be against the section | |
8362 | symbol, we need to adjust the value. */ | |
8363 | #ifdef S_GET_OTHER | |
8364 | if (fixP->fx_addsy != NULL | |
1748b9d8 ILT |
8365 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8366 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8367 | { | |
8368 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8369 | if (value != 0 && ! fixP->fx_pcrel) | |
8370 | { | |
8371 | /* In this case, the bfd_install_relocation routine will | |
8372 | incorrectly add the symbol value back in. We just want | |
8373 | the addend to appear in the object file. */ | |
8374 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8375 | } | |
8376 | } | |
8377 | #endif | |
8378 | ||
670a50eb | 8379 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8380 | |
5b63f465 ILT |
8381 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8382 | fixP->fx_done = 1; | |
8383 | ||
670a50eb ILT |
8384 | switch (fixP->fx_r_type) |
8385 | { | |
3d3c5039 ILT |
8386 | case BFD_RELOC_MIPS_JMP: |
8387 | case BFD_RELOC_HI16: | |
8388 | case BFD_RELOC_HI16_S: | |
670a50eb | 8389 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8390 | case BFD_RELOC_MIPS_LITERAL: |
8391 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8392 | case BFD_RELOC_MIPS_GOT16: |
8393 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8394 | case BFD_RELOC_MIPS_GOT_HI16: |
8395 | case BFD_RELOC_MIPS_GOT_LO16: | |
8396 | case BFD_RELOC_MIPS_CALL_HI16: | |
8397 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8398 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8399 | if (fixP->fx_pcrel) |
7b777690 ILT |
8400 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8401 | "Invalid PC relative reloc"); | |
670a50eb | 8402 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8403 | break; |
3d3c5039 | 8404 | |
cc5703cd ILT |
8405 | case BFD_RELOC_MIPS16_JMP: |
8406 | /* We currently always generate a reloc against a symbol, which | |
8407 | means that we don't want an addend even if the symbol is | |
8408 | defined. */ | |
8409 | fixP->fx_addnumber = 0; | |
8410 | break; | |
8411 | ||
ecd4ca1c ILT |
8412 | case BFD_RELOC_PCREL_HI16_S: |
8413 | /* The addend for this is tricky if it is internal, so we just | |
8414 | do everything here rather than in bfd_perform_relocation. */ | |
8415 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8416 | { | |
8417 | /* For an external symbol adjust by the address to make it | |
8418 | pcrel_offset. We use the address of the RELLO reloc | |
8419 | which follows this one. */ | |
8420 | value += (fixP->fx_next->fx_frag->fr_address | |
8421 | + fixP->fx_next->fx_where); | |
8422 | } | |
8423 | if (value & 0x8000) | |
8424 | value += 0x10000; | |
8425 | value >>= 16; | |
0221ddf7 | 8426 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8427 | if (target_big_endian) |
ecd4ca1c ILT |
8428 | buf += 2; |
8429 | md_number_to_chars (buf, value, 2); | |
8430 | break; | |
8431 | ||
8432 | case BFD_RELOC_PCREL_LO16: | |
8433 | /* The addend for this is tricky if it is internal, so we just | |
8434 | do everything here rather than in bfd_perform_relocation. */ | |
8435 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8436 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8437 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8438 | if (target_big_endian) |
ecd4ca1c ILT |
8439 | buf += 2; |
8440 | md_number_to_chars (buf, value, 2); | |
8441 | break; | |
8442 | ||
bf39474f ILT |
8443 | case BFD_RELOC_64: |
8444 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8445 | extended value if we are only 32 bits. */ | |
8446 | if (fixP->fx_done | |
8447 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8448 | { | |
8449 | if (8 <= sizeof (valueT)) | |
8450 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8451 | value, 8); | |
8452 | else | |
8453 | { | |
8454 | long w1, w2; | |
8455 | long hiv; | |
8456 | ||
8457 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8458 | if (target_big_endian) |
bf39474f ILT |
8459 | w1 += 4; |
8460 | else | |
8461 | w2 += 4; | |
8462 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8463 | if ((value & 0x80000000) != 0) | |
8464 | hiv = 0xffffffff; | |
8465 | else | |
8466 | hiv = 0; | |
8467 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8468 | } | |
8469 | } | |
8470 | break; | |
8471 | ||
f3645945 ILT |
8472 | case BFD_RELOC_32: |
8473 | /* If we are deleting this reloc entry, we must fill in the | |
8474 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8475 | resolved when it appears but is later defined. We also need |
8476 | to fill in the value if this is an embedded PIC switch table | |
8477 | entry. */ | |
8478 | if (fixP->fx_done | |
8479 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8480 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8481 | value, 4); | |
8482 | break; | |
8483 | ||
49ad0c4c ILT |
8484 | case BFD_RELOC_16: |
8485 | /* If we are deleting this reloc entry, we must fill in the | |
8486 | value now. */ | |
8487 | assert (fixP->fx_size == 2); | |
8488 | if (fixP->fx_done) | |
8489 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8490 | value, 2); | |
8491 | break; | |
8492 | ||
f3645945 ILT |
8493 | case BFD_RELOC_LO16: |
8494 | /* When handling an embedded PIC switch statement, we can wind | |
8495 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8496 | if (fixP->fx_done) | |
8497 | { | |
8498 | if (value < -0x8000 || value > 0x7fff) | |
8499 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8500 | "relocation overflow"); | |
0221ddf7 | 8501 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8502 | if (target_big_endian) |
f3645945 ILT |
8503 | buf += 2; |
8504 | md_number_to_chars (buf, value, 2); | |
8505 | } | |
8506 | break; | |
8507 | ||
3d3c5039 | 8508 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8509 | /* |
8510 | * We need to save the bits in the instruction since fixup_segment() | |
8511 | * might be deleting the relocation entry (i.e., a branch within | |
8512 | * the current segment). | |
8513 | */ | |
fbcfacb7 | 8514 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8515 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8516 | "Branch to odd address (%lx)", value); | |
670a50eb | 8517 | value >>= 2; |
670a50eb ILT |
8518 | |
8519 | /* update old instruction data */ | |
8520 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8521 | if (target_big_endian) |
8522 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8523 | else | |
8524 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8525 | |
8526 | if (value >= -0x8000 && value < 0x8000) | |
8527 | insn |= value & 0xffff; | |
8528 | else | |
8529 | { | |
8530 | /* The branch offset is too large. If this is an | |
8531 | unconditional branch, and we are not generating PIC code, | |
8532 | we can convert it to an absolute jump instruction. */ | |
8533 | if (mips_pic == NO_PIC | |
8534 | && fixP->fx_done | |
8535 | && fixP->fx_frag->fr_address >= text_section->vma | |
8536 | && (fixP->fx_frag->fr_address | |
8537 | < text_section->vma + text_section->_raw_size) | |
8538 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8539 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8540 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8541 | { | |
8542 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8543 | insn = 0x0c000000; /* jal */ | |
8544 | else | |
8545 | insn = 0x08000000; /* j */ | |
8546 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8547 | fixP->fx_done = 0; | |
8548 | fixP->fx_addsy = section_symbol (text_section); | |
8549 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8550 | } | |
8551 | else | |
8552 | { | |
8553 | /* FIXME. It would be possible in principle to handle | |
8554 | conditional branches which overflow. They could be | |
8555 | transformed into a branch around a jump. This would | |
8556 | require setting up variant frags for each different | |
8557 | branch type. The native MIPS assembler attempts to | |
8558 | handle these cases, but it appears to do it | |
8559 | incorrectly. */ | |
8560 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8561 | "Relocation overflow"); | |
8562 | } | |
8563 | } | |
8564 | ||
604633ae | 8565 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8566 | break; |
3d3c5039 ILT |
8567 | |
8568 | default: | |
670a50eb | 8569 | internalError (); |
3d3c5039 | 8570 | } |
5b63f465 | 8571 | |
670a50eb | 8572 | return 1; |
3d3c5039 ILT |
8573 | } |
8574 | ||
8575 | #if 0 | |
8576 | void | |
670a50eb ILT |
8577 | printInsn (oc) |
8578 | unsigned long oc; | |
3d3c5039 | 8579 | { |
670a50eb ILT |
8580 | const struct mips_opcode *p; |
8581 | int treg, sreg, dreg, shamt; | |
8582 | short imm; | |
8583 | const char *args; | |
8584 | int i; | |
3d3c5039 | 8585 | |
670a50eb ILT |
8586 | for (i = 0; i < NUMOPCODES; ++i) |
8587 | { | |
8588 | p = &mips_opcodes[i]; | |
8589 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8590 | { | |
8591 | printf ("%08lx %s\t", oc, p->name); | |
8592 | treg = (oc >> 16) & 0x1f; | |
8593 | sreg = (oc >> 21) & 0x1f; | |
8594 | dreg = (oc >> 11) & 0x1f; | |
8595 | shamt = (oc >> 6) & 0x1f; | |
8596 | imm = oc; | |
8597 | for (args = p->args;; ++args) | |
8598 | { | |
8599 | switch (*args) | |
8600 | { | |
3d3c5039 | 8601 | case '\0': |
670a50eb ILT |
8602 | printf ("\n"); |
8603 | break; | |
3d3c5039 ILT |
8604 | |
8605 | case ',': | |
8606 | case '(': | |
8607 | case ')': | |
670a50eb ILT |
8608 | printf ("%c", *args); |
8609 | continue; | |
3d3c5039 ILT |
8610 | |
8611 | case 'r': | |
670a50eb ILT |
8612 | assert (treg == sreg); |
8613 | printf ("$%d,$%d", treg, sreg); | |
8614 | continue; | |
3d3c5039 ILT |
8615 | |
8616 | case 'd': | |
918692a5 | 8617 | case 'G': |
670a50eb ILT |
8618 | printf ("$%d", dreg); |
8619 | continue; | |
3d3c5039 ILT |
8620 | |
8621 | case 't': | |
918692a5 | 8622 | case 'E': |
670a50eb ILT |
8623 | printf ("$%d", treg); |
8624 | continue; | |
3d3c5039 | 8625 | |
9226253a ILT |
8626 | case 'k': |
8627 | printf ("0x%x", treg); | |
8628 | continue; | |
8629 | ||
3d3c5039 ILT |
8630 | case 'b': |
8631 | case 's': | |
670a50eb ILT |
8632 | printf ("$%d", sreg); |
8633 | continue; | |
3d3c5039 ILT |
8634 | |
8635 | case 'a': | |
670a50eb ILT |
8636 | printf ("0x%08lx", oc & 0x1ffffff); |
8637 | continue; | |
3d3c5039 ILT |
8638 | |
8639 | case 'i': | |
8640 | case 'j': | |
8641 | case 'o': | |
8642 | case 'u': | |
670a50eb ILT |
8643 | printf ("%d", imm); |
8644 | continue; | |
3d3c5039 ILT |
8645 | |
8646 | case '<': | |
56c96faa | 8647 | case '>': |
670a50eb ILT |
8648 | printf ("$%d", shamt); |
8649 | continue; | |
3d3c5039 ILT |
8650 | |
8651 | default: | |
670a50eb | 8652 | internalError (); |
3d3c5039 | 8653 | } |
670a50eb | 8654 | break; |
3d3c5039 | 8655 | } |
670a50eb | 8656 | return; |
3d3c5039 ILT |
8657 | } |
8658 | } | |
670a50eb | 8659 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8660 | } |
8661 | #endif | |
8662 | ||
8663 | static symbolS * | |
8664 | get_symbol () | |
8665 | { | |
670a50eb ILT |
8666 | int c; |
8667 | char *name; | |
8668 | symbolS *p; | |
8669 | ||
8670 | name = input_line_pointer; | |
8671 | c = get_symbol_end (); | |
8672 | p = (symbolS *) symbol_find_or_make (name); | |
8673 | *input_line_pointer = c; | |
8674 | return p; | |
3d3c5039 ILT |
8675 | } |
8676 | ||
becfe05e ILT |
8677 | /* Align the current frag to a given power of two. The MIPS assembler |
8678 | also automatically adjusts any preceding label. */ | |
8679 | ||
8680 | static void | |
23dc1ae3 | 8681 | mips_align (to, fill, label) |
becfe05e ILT |
8682 | int to; |
8683 | int fill; | |
23dc1ae3 | 8684 | symbolS *label; |
becfe05e | 8685 | { |
fbcfacb7 | 8686 | mips_emit_delays (false); |
becfe05e ILT |
8687 | frag_align (to, fill); |
8688 | record_alignment (now_seg, to); | |
23dc1ae3 | 8689 | if (label != NULL) |
becfe05e | 8690 | { |
23dc1ae3 ILT |
8691 | assert (S_GET_SEGMENT (label) == now_seg); |
8692 | label->sy_frag = frag_now; | |
8693 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8694 | } |
8695 | } | |
8696 | ||
8697 | /* Align to a given power of two. .align 0 turns off the automatic | |
8698 | alignment used by the data creating pseudo-ops. */ | |
8699 | ||
3d3c5039 ILT |
8700 | static void |
8701 | s_align (x) | |
8702 | int x; | |
8703 | { | |
670a50eb ILT |
8704 | register int temp; |
8705 | register long temp_fill; | |
8706 | long max_alignment = 15; | |
3d3c5039 | 8707 | |
670a50eb | 8708 | /* |
3d3c5039 ILT |
8709 | |
8710 | o Note that the assembler pulls down any immediately preceeding label | |
8711 | to the aligned address. | |
8712 | o It's not documented but auto alignment is reinstated by | |
8713 | a .align pseudo instruction. | |
8714 | o Note also that after auto alignment is turned off the mips assembler | |
8715 | issues an error on attempt to assemble an improperly aligned data item. | |
8716 | We don't. | |
8717 | ||
8718 | */ | |
8719 | ||
670a50eb ILT |
8720 | temp = get_absolute_expression (); |
8721 | if (temp > max_alignment) | |
8722 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8723 | else if (temp < 0) | |
8724 | { | |
8725 | as_warn ("Alignment negative: 0 assumed."); | |
8726 | temp = 0; | |
8727 | } | |
8728 | if (*input_line_pointer == ',') | |
8729 | { | |
8730 | input_line_pointer++; | |
8731 | temp_fill = get_absolute_expression (); | |
8732 | } | |
8733 | else | |
8734 | temp_fill = 0; | |
8735 | if (temp) | |
8736 | { | |
8737 | auto_align = 1; | |
fbcfacb7 ILT |
8738 | mips_align (temp, (int) temp_fill, |
8739 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 8740 | } |
670a50eb ILT |
8741 | else |
8742 | { | |
8743 | auto_align = 0; | |
3d3c5039 ILT |
8744 | } |
8745 | ||
670a50eb | 8746 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8747 | } |
8748 | ||
739708fa KR |
8749 | void |
8750 | mips_flush_pending_output () | |
becfe05e | 8751 | { |
fbcfacb7 ILT |
8752 | mips_emit_delays (false); |
8753 | mips_clear_insn_labels (); | |
becfe05e ILT |
8754 | } |
8755 | ||
3d3c5039 ILT |
8756 | static void |
8757 | s_change_sec (sec) | |
8758 | int sec; | |
8759 | { | |
88225433 | 8760 | segT seg; |
becfe05e | 8761 | |
5b63f465 ILT |
8762 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8763 | .sdata and .sbss sections. We change the .data and .rdata | |
8764 | pseudo-ops to use .sdata. */ | |
8765 | if (mips_pic == EMBEDDED_PIC | |
8766 | && (sec == 'd' || sec == 'r')) | |
8767 | sec = 's'; | |
8768 | ||
fbcfacb7 | 8769 | mips_emit_delays (false); |
670a50eb ILT |
8770 | switch (sec) |
8771 | { | |
3d3c5039 | 8772 | case 't': |
604633ae | 8773 | s_text (0); |
670a50eb | 8774 | break; |
3d3c5039 | 8775 | case 'd': |
604633ae | 8776 | s_data (0); |
670a50eb | 8777 | break; |
3d3c5039 | 8778 | case 'b': |
670a50eb | 8779 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8780 | demand_empty_rest_of_line (); |
8781 | break; | |
88225433 ILT |
8782 | |
8783 | case 'r': | |
1dc1e798 KR |
8784 | if (USE_GLOBAL_POINTER_OPT) |
8785 | { | |
8786 | seg = subseg_new (RDATA_SECTION_NAME, | |
8787 | (subsegT) get_absolute_expression ()); | |
8788 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8789 | { | |
8790 | bfd_set_section_flags (stdoutput, seg, | |
8791 | (SEC_ALLOC | |
8792 | | SEC_LOAD | |
8793 | | SEC_READONLY | |
8794 | | SEC_RELOC | |
8795 | | SEC_DATA)); | |
08e17202 ILT |
8796 | if (strcmp (TARGET_OS, "elf") != 0) |
8797 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8798 | } |
8799 | demand_empty_rest_of_line (); | |
8800 | } | |
8801 | else | |
8802 | { | |
8803 | as_bad ("No read only data section in this object file format"); | |
8804 | demand_empty_rest_of_line (); | |
8805 | return; | |
8806 | } | |
88225433 | 8807 | break; |
88225433 ILT |
8808 | |
8809 | case 's': | |
1dc1e798 KR |
8810 | if (USE_GLOBAL_POINTER_OPT) |
8811 | { | |
8812 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8813 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8814 | { | |
8815 | bfd_set_section_flags (stdoutput, seg, | |
8816 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8817 | | SEC_DATA); | |
08e17202 ILT |
8818 | if (strcmp (TARGET_OS, "elf") != 0) |
8819 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8820 | } |
8821 | demand_empty_rest_of_line (); | |
8822 | break; | |
8823 | } | |
8824 | else | |
8825 | { | |
8826 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8827 | demand_empty_rest_of_line (); | |
8828 | return; | |
8829 | } | |
3d3c5039 | 8830 | } |
88225433 | 8831 | |
670a50eb | 8832 | auto_align = 1; |
3d3c5039 ILT |
8833 | } |
8834 | ||
739708fa KR |
8835 | void |
8836 | mips_enable_auto_align () | |
9da4c5d1 | 8837 | { |
9da4c5d1 ILT |
8838 | auto_align = 1; |
8839 | } | |
8840 | ||
3d3c5039 ILT |
8841 | static void |
8842 | s_cons (log_size) | |
8843 | int log_size; | |
8844 | { | |
23dc1ae3 ILT |
8845 | symbolS *label; |
8846 | ||
fbcfacb7 ILT |
8847 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8848 | mips_emit_delays (false); | |
670a50eb | 8849 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8850 | mips_align (log_size, 0, label); |
fbcfacb7 | 8851 | mips_clear_insn_labels (); |
670a50eb | 8852 | cons (1 << log_size); |
3d3c5039 ILT |
8853 | } |
8854 | ||
3d3c5039 | 8855 | static void |
becfe05e ILT |
8856 | s_float_cons (type) |
8857 | int type; | |
3d3c5039 | 8858 | { |
23dc1ae3 ILT |
8859 | symbolS *label; |
8860 | ||
fbcfacb7 | 8861 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 8862 | |
fbcfacb7 | 8863 | mips_emit_delays (false); |
670a50eb ILT |
8864 | |
8865 | if (auto_align) | |
becfe05e | 8866 | if (type == 'd') |
23dc1ae3 | 8867 | mips_align (3, 0, label); |
670a50eb | 8868 | else |
23dc1ae3 | 8869 | mips_align (2, 0, label); |
670a50eb | 8870 | |
fbcfacb7 | 8871 | mips_clear_insn_labels (); |
1849d646 | 8872 | |
becfe05e | 8873 | float_cons (type); |
3d3c5039 ILT |
8874 | } |
8875 | ||
c1444ec4 ILT |
8876 | /* Handle .globl. We need to override it because on Irix 5 you are |
8877 | permitted to say | |
8878 | .globl foo .text | |
8879 | where foo is an undefined symbol, to mean that foo should be | |
8880 | considered to be the address of a function. */ | |
8881 | ||
8882 | static void | |
8883 | s_mips_globl (x) | |
8884 | int x; | |
8885 | { | |
8886 | char *name; | |
8887 | int c; | |
8888 | symbolS *symbolP; | |
fb251650 | 8889 | flagword flag; |
c1444ec4 ILT |
8890 | |
8891 | name = input_line_pointer; | |
8892 | c = get_symbol_end (); | |
8893 | symbolP = symbol_find_or_make (name); | |
8894 | *input_line_pointer = c; | |
8895 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8896 | |
8897 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8898 | being a function is apparently labelled as being an object. */ | |
8899 | flag = BSF_OBJECT; | |
8900 | ||
c1444ec4 ILT |
8901 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8902 | { | |
8903 | char *secname; | |
8904 | asection *sec; | |
8905 | ||
8906 | secname = input_line_pointer; | |
8907 | c = get_symbol_end (); | |
8908 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8909 | if (sec == NULL) | |
8910 | as_bad ("%s: no such section", secname); | |
8911 | *input_line_pointer = c; | |
8912 | ||
8913 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8914 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8915 | } |
8916 | ||
fb251650 ILT |
8917 | symbolP->bsym->flags |= flag; |
8918 | ||
c1444ec4 ILT |
8919 | S_SET_EXTERNAL (symbolP); |
8920 | demand_empty_rest_of_line (); | |
8921 | } | |
8922 | ||
3d3c5039 ILT |
8923 | static void |
8924 | s_option (x) | |
8925 | int x; | |
8926 | { | |
dd3f1f76 ILT |
8927 | char *opt; |
8928 | char c; | |
8929 | ||
8930 | opt = input_line_pointer; | |
8931 | c = get_symbol_end (); | |
8932 | ||
dd3f1f76 | 8933 | if (*opt == 'O') |
9226253a ILT |
8934 | { |
8935 | /* FIXME: What does this mean? */ | |
8936 | } | |
dd3f1f76 | 8937 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8938 | { |
d9aba805 | 8939 | int i; |
42562568 | 8940 | |
d9aba805 ILT |
8941 | i = atoi (opt + 3); |
8942 | if (i == 0) | |
8943 | mips_pic = NO_PIC; | |
8944 | else if (i == 2) | |
8945 | mips_pic = SVR4_PIC; | |
8946 | else | |
8947 | as_bad (".option pic%d not supported", i); | |
8948 | ||
1dc1e798 | 8949 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8950 | { |
8951 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8952 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8953 | g_switch_value = 0; |
8954 | bfd_set_gp_size (stdoutput, 0); | |
8955 | } | |
9226253a | 8956 | } |
dd3f1f76 ILT |
8957 | else |
8958 | as_warn ("Unrecognized option \"%s\"", opt); | |
8959 | ||
8960 | *input_line_pointer = c; | |
670a50eb | 8961 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8962 | } |
8963 | ||
8964 | static void | |
8965 | s_mipsset (x) | |
8966 | int x; | |
8967 | { | |
670a50eb ILT |
8968 | char *name = input_line_pointer, ch; |
8969 | ||
8970 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8971 | input_line_pointer++; | |
8972 | ch = *input_line_pointer; | |
8973 | *input_line_pointer = '\0'; | |
8974 | ||
8975 | if (strcmp (name, "reorder") == 0) | |
8976 | { | |
4e95866e ILT |
8977 | if (mips_noreorder) |
8978 | { | |
8979 | prev_insn_unreordered = 1; | |
8980 | prev_prev_insn_unreordered = 1; | |
8981 | } | |
670a50eb ILT |
8982 | mips_noreorder = 0; |
8983 | } | |
8984 | else if (strcmp (name, "noreorder") == 0) | |
8985 | { | |
fbcfacb7 | 8986 | mips_emit_delays (true); |
670a50eb | 8987 | mips_noreorder = 1; |
0dd2d296 | 8988 | mips_any_noreorder = 1; |
670a50eb ILT |
8989 | } |
8990 | else if (strcmp (name, "at") == 0) | |
8991 | { | |
8992 | mips_noat = 0; | |
8993 | } | |
8994 | else if (strcmp (name, "noat") == 0) | |
8995 | { | |
8996 | mips_noat = 1; | |
3d3c5039 | 8997 | } |
670a50eb ILT |
8998 | else if (strcmp (name, "macro") == 0) |
8999 | { | |
9000 | mips_warn_about_macros = 0; | |
9001 | } | |
9002 | else if (strcmp (name, "nomacro") == 0) | |
9003 | { | |
9004 | if (mips_noreorder == 0) | |
9005 | as_bad ("`noreorder' must be set before `nomacro'"); | |
9006 | mips_warn_about_macros = 1; | |
9007 | } | |
9008 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9009 | { | |
9010 | mips_nomove = 0; | |
9011 | } | |
9012 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9013 | { | |
9014 | mips_nomove = 1; | |
9015 | } | |
9016 | else if (strcmp (name, "bopt") == 0) | |
9017 | { | |
9018 | mips_nobopt = 0; | |
9019 | } | |
9020 | else if (strcmp (name, "nobopt") == 0) | |
9021 | { | |
9022 | mips_nobopt = 1; | |
9023 | } | |
943321c0 ILT |
9024 | else if (strcmp (name, "mips16") == 0 |
9025 | || strcmp (name, "MIPS-16") == 0) | |
9026 | mips16 = 1; | |
9027 | else if (strcmp (name, "nomips16") == 0 | |
9028 | || strcmp (name, "noMIPS-16") == 0) | |
9029 | mips16 = 0; | |
1051c97f ILT |
9030 | else if (strncmp (name, "mips", 4) == 0) |
9031 | { | |
9032 | int isa; | |
9033 | ||
9034 | /* Permit the user to change the ISA on the fly. Needless to | |
9035 | say, misuse can cause serious problems. */ | |
9036 | isa = atoi (name + 4); | |
9037 | if (isa == 0) | |
9038 | mips_isa = file_mips_isa; | |
d8a1c247 | 9039 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9040 | as_bad ("unknown ISA level"); |
9041 | else | |
9042 | mips_isa = isa; | |
9043 | } | |
cc5703cd ILT |
9044 | else if (strcmp (name, "autoextend") == 0) |
9045 | mips16_autoextend = 1; | |
9046 | else if (strcmp (name, "noautoextend") == 0) | |
9047 | mips16_autoextend = 0; | |
670a50eb ILT |
9048 | else |
9049 | { | |
9050 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9051 | } | |
9052 | *input_line_pointer = ch; | |
9053 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9054 | } |
9055 | ||
9226253a ILT |
9056 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9057 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9058 | ||
9059 | static void | |
9060 | s_abicalls (ignore) | |
9061 | int ignore; | |
9062 | { | |
d9aba805 | 9063 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9064 | if (USE_GLOBAL_POINTER_OPT) |
9065 | { | |
9066 | if (g_switch_seen && g_switch_value != 0) | |
9067 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9068 | g_switch_value = 0; | |
9069 | } | |
d9aba805 | 9070 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9071 | demand_empty_rest_of_line (); |
9072 | } | |
9073 | ||
9074 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9075 | PIC code. It sets the $gp register for the function based on the | |
9076 | function address, which is in the register named in the argument. | |
9077 | This uses a relocation against _gp_disp, which is handled specially | |
9078 | by the linker. The result is: | |
9079 | lui $gp,%hi(_gp_disp) | |
9080 | addiu $gp,$gp,%lo(_gp_disp) | |
9081 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9082 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9083 | |
9084 | static void | |
9085 | s_cpload (ignore) | |
9086 | int ignore; | |
9087 | { | |
9088 | expressionS ex; | |
9089 | int icnt = 0; | |
9090 | ||
d9aba805 ILT |
9091 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9092 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9093 | { |
9094 | s_ignore (0); | |
9095 | return; | |
9096 | } | |
9097 | ||
9098 | /* .cpload should be a in .set noreorder section. */ | |
9099 | if (mips_noreorder == 0) | |
9100 | as_warn (".cpload not in noreorder section"); | |
9101 | ||
9226253a ILT |
9102 | ex.X_op = O_symbol; |
9103 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9104 | ex.X_op_symbol = NULL; | |
9105 | ex.X_add_number = 0; | |
9106 | ||
fb251650 ILT |
9107 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9108 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9109 | ||
0dd2d296 ILT |
9110 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9111 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9112 | (int) BFD_RELOC_LO16); |
9113 | ||
0dd2d296 ILT |
9114 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9115 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9116 | |
9117 | demand_empty_rest_of_line (); | |
9118 | } | |
9119 | ||
9120 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9121 | offset from $sp. The offset is remembered, and after making a PIC | |
9122 | call $gp is restored from that location. */ | |
9123 | ||
9124 | static void | |
9125 | s_cprestore (ignore) | |
9126 | int ignore; | |
9127 | { | |
9128 | expressionS ex; | |
9129 | int icnt = 0; | |
9130 | ||
d9aba805 ILT |
9131 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9132 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9133 | { |
9134 | s_ignore (0); | |
9135 | return; | |
9136 | } | |
9137 | ||
9226253a ILT |
9138 | mips_cprestore_offset = get_absolute_expression (); |
9139 | ||
9140 | ex.X_op = O_constant; | |
9141 | ex.X_add_symbol = NULL; | |
9142 | ex.X_op_symbol = NULL; | |
9143 | ex.X_add_number = mips_cprestore_offset; | |
9144 | ||
0dd2d296 | 9145 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
9146 | mips_isa < 3 ? "sw" : "sd", |
9147 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
9148 | ||
9149 | demand_empty_rest_of_line (); | |
9150 | } | |
9151 | ||
0dd2d296 ILT |
9152 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9153 | code. It generates a 32 bit GP relative reloc. */ | |
9154 | ||
9155 | static void | |
9156 | s_gpword (ignore) | |
9157 | int ignore; | |
9158 | { | |
23dc1ae3 | 9159 | symbolS *label; |
0dd2d296 ILT |
9160 | expressionS ex; |
9161 | char *p; | |
9162 | ||
9163 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9164 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9165 | { |
9166 | s_cons (2); | |
9167 | return; | |
9168 | } | |
9169 | ||
fbcfacb7 ILT |
9170 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9171 | mips_emit_delays (true); | |
0dd2d296 | 9172 | if (auto_align) |
23dc1ae3 | 9173 | mips_align (2, 0, label); |
fbcfacb7 | 9174 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9175 | |
9176 | expression (&ex); | |
9177 | ||
9178 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9179 | { | |
9180 | as_bad ("Unsupported use of .gpword"); | |
9181 | ignore_rest_of_line (); | |
9182 | } | |
9183 | ||
9184 | p = frag_more (4); | |
9185 | md_number_to_chars (p, (valueT) 0, 4); | |
9186 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9187 | BFD_RELOC_MIPS_GPREL32); | |
9188 | ||
9189 | demand_empty_rest_of_line (); | |
9190 | } | |
9191 | ||
9192 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9193 | tables in SVR4 PIC code. */ | |
9194 | ||
9195 | static void | |
9196 | s_cpadd (ignore) | |
9197 | int ignore; | |
9198 | { | |
9199 | int icnt = 0; | |
9200 | int reg; | |
9201 | ||
9202 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9203 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9204 | { |
9205 | s_ignore (0); | |
9206 | return; | |
9207 | } | |
9208 | ||
9209 | /* Add $gp to the register named as an argument. */ | |
9210 | reg = tc_get_register (0); | |
9211 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9212 | mips_isa < 3 ? "addu" : "daddu", | |
9213 | "d,v,t", reg, reg, GP); | |
9214 | ||
9215 | demand_empty_rest_of_line (); | |
9216 | } | |
9217 | ||
9226253a | 9218 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9219 | to parse .frame. The argument is non-zero if this is the frame |
9220 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9221 | |
3d3c5039 | 9222 | int |
0dd2d296 ILT |
9223 | tc_get_register (frame) |
9224 | int frame; | |
3d3c5039 ILT |
9225 | { |
9226 | int reg; | |
9227 | ||
9228 | SKIP_WHITESPACE (); | |
9229 | if (*input_line_pointer++ != '$') | |
9230 | { | |
9231 | as_warn ("expected `$'"); | |
0dd2d296 | 9232 | reg = 0; |
3d3c5039 | 9233 | } |
0dd2d296 | 9234 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9235 | { |
9236 | reg = get_absolute_expression (); | |
9237 | if (reg < 0 || reg >= 32) | |
9238 | { | |
9239 | as_warn ("Bad register number"); | |
9240 | reg = 0; | |
9241 | } | |
9242 | } | |
9243 | else | |
9244 | { | |
9245 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9246 | reg = FP; |
3d3c5039 | 9247 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9248 | reg = SP; |
3d3c5039 | 9249 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9250 | reg = GP; |
3d3c5039 | 9251 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9252 | reg = AT; |
3d3c5039 ILT |
9253 | else |
9254 | { | |
9255 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9256 | reg = 0; |
3d3c5039 ILT |
9257 | } |
9258 | input_line_pointer += 2; | |
9259 | } | |
0dd2d296 ILT |
9260 | if (frame) |
9261 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9262 | return reg; |
9263 | } | |
9264 | ||
0dd2d296 ILT |
9265 | valueT |
9266 | md_section_align (seg, addr) | |
9267 | asection *seg; | |
9268 | valueT addr; | |
9269 | { | |
9270 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9271 | ||
cf32394d ILT |
9272 | #ifdef OBJ_ELF |
9273 | /* We don't need to align ELF sections to the full alignment. | |
9274 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9275 | byte boundary. We don't bother to align the sections if we are |
9276 | targeted for an embedded system. */ | |
9277 | if (strcmp (TARGET_OS, "elf") == 0) | |
9278 | return addr; | |
943321c0 ILT |
9279 | if (align > 4) |
9280 | align = 4; | |
10a14e36 | 9281 | #endif |
cf32394d ILT |
9282 | |
9283 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9284 | } |
9285 | ||
d8a1c247 KR |
9286 | /* Utility routine, called from above as well. If called while the |
9287 | input file is still being read, it's only an approximation. (For | |
9288 | example, a symbol may later become defined which appeared to be | |
9289 | undefined earlier.) */ | |
22ba90ce ILT |
9290 | |
9291 | static int | |
9292 | nopic_need_relax (sym) | |
d8a1c247 KR |
9293 | symbolS *sym; |
9294 | { | |
9295 | if (sym == 0) | |
9296 | return 0; | |
9297 | ||
1dc1e798 KR |
9298 | if (USE_GLOBAL_POINTER_OPT) |
9299 | { | |
9300 | const char *symname; | |
9301 | int change; | |
9302 | ||
9303 | /* Find out whether this symbol can be referenced off the GP | |
9304 | register. It can be if it is smaller than the -G size or if | |
9305 | it is in the .sdata or .sbss section. Certain symbols can | |
9306 | not be referenced off the GP, although it appears as though | |
9307 | they can. */ | |
9308 | symname = S_GET_NAME (sym); | |
9309 | if (symname != (const char *) NULL | |
9310 | && (strcmp (symname, "eprol") == 0 | |
9311 | || strcmp (symname, "etext") == 0 | |
9312 | || strcmp (symname, "_gp") == 0 | |
9313 | || strcmp (symname, "edata") == 0 | |
9314 | || strcmp (symname, "_fbss") == 0 | |
9315 | || strcmp (symname, "_fdata") == 0 | |
9316 | || strcmp (symname, "_ftext") == 0 | |
9317 | || strcmp (symname, "end") == 0 | |
9318 | || strcmp (symname, "_gp_disp") == 0)) | |
9319 | change = 1; | |
9320 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9321 | && (0 |
9322 | #ifndef NO_ECOFF_DEBUGGING | |
9323 | || (sym->ecoff_extern_size != 0 | |
9324 | && sym->ecoff_extern_size <= g_switch_value) | |
9325 | #endif | |
1dc1e798 KR |
9326 | || (S_GET_VALUE (sym) != 0 |
9327 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9328 | change = 0; | |
9329 | else | |
9330 | { | |
9331 | const char *segname; | |
d8a1c247 | 9332 | |
1dc1e798 KR |
9333 | segname = segment_name (S_GET_SEGMENT (sym)); |
9334 | assert (strcmp (segname, ".lit8") != 0 | |
9335 | && strcmp (segname, ".lit4") != 0); | |
9336 | change = (strcmp (segname, ".sdata") != 0 | |
9337 | && strcmp (segname, ".sbss") != 0); | |
9338 | } | |
9339 | return change; | |
9340 | } | |
9341 | else | |
9342 | /* We are not optimizing for the GP register. */ | |
9343 | return 1; | |
d8a1c247 KR |
9344 | } |
9345 | ||
cc5703cd ILT |
9346 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9347 | extended opcode. SEC is the section the frag is in. */ | |
9348 | ||
9349 | static int | |
9350 | mips16_extended_frag (fragp, sec, stretch) | |
9351 | fragS *fragp; | |
9352 | asection *sec; | |
9353 | long stretch; | |
9354 | { | |
9355 | int type; | |
9356 | register const struct mips16_immed_operand *op; | |
9357 | offsetT val; | |
9358 | int mintiny, maxtiny; | |
f74ba7a3 | 9359 | segT symsec; |
cc5703cd | 9360 | |
8728fa92 ILT |
9361 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9362 | return 0; | |
9363 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9364 | return 1; | |
9365 | ||
cc5703cd ILT |
9366 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9367 | op = mips16_immed_operands; | |
9368 | while (op->type != type) | |
9369 | { | |
9370 | ++op; | |
9371 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9372 | } | |
9373 | ||
9374 | if (op->unsp) | |
9375 | { | |
9376 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9377 | { | |
9378 | mintiny = 1; | |
9379 | maxtiny = 1 << op->nbits; | |
9380 | } | |
9381 | else | |
9382 | { | |
9383 | mintiny = 0; | |
9384 | maxtiny = (1 << op->nbits) - 1; | |
9385 | } | |
9386 | } | |
9387 | else | |
9388 | { | |
9389 | mintiny = - (1 << (op->nbits - 1)); | |
9390 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9391 | } | |
9392 | ||
f74ba7a3 ILT |
9393 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9394 | a particular frag address. */ | |
9395 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9396 | { | |
9397 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9398 | + fragp->fr_symbol->sy_frag->fr_address); | |
9399 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9400 | } | |
9401 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9402 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9403 | == O_constant)) | |
9404 | { | |
9405 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9406 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9407 | + fragp->fr_symbol->sy_value.X_add_number | |
9408 | + fragp->fr_symbol->sy_frag->fr_address); | |
9409 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9410 | } | |
9411 | else | |
9412 | return 1; | |
cc5703cd ILT |
9413 | |
9414 | if (op->pcrel) | |
9415 | { | |
9416 | addressT addr; | |
9417 | ||
9418 | /* We won't have the section when we are called from | |
9419 | mips_relax_frag. However, we will always have been called | |
9420 | from md_estimate_size_before_relax first. If this is a | |
9421 | branch to a different section, we mark it as such. If SEC is | |
9422 | NULL, and the frag is not marked, then it must be a branch to | |
9423 | the same section. */ | |
9424 | if (sec == NULL) | |
9425 | { | |
9426 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9427 | return 1; | |
9428 | } | |
9429 | else | |
9430 | { | |
f74ba7a3 | 9431 | if (symsec != sec) |
cc5703cd ILT |
9432 | { |
9433 | fragp->fr_subtype = | |
9434 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9435 | ||
9436 | /* FIXME: We should support this, and let the linker | |
9437 | catch branches and loads that are out of range. */ | |
9438 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9439 | "unsupported PC relative reference to different section"); | |
9440 | ||
9441 | return 1; | |
9442 | } | |
9443 | } | |
9444 | ||
9445 | /* In this case, we know for sure that the symbol fragment is in | |
9446 | the same section. If the fr_address of the symbol fragment | |
9447 | is greater then the address of this fragment we want to add | |
9448 | in STRETCH in order to get a better estimate of the address. | |
9449 | This particularly matters because of the shift bits. */ | |
9450 | if (stretch != 0 | |
9451 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9452 | { | |
9453 | fragS *f; | |
9454 | ||
9455 | /* Adjust stretch for any alignment frag. */ | |
9456 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9457 | { | |
9458 | assert (f != NULL); | |
9459 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9460 | { | |
9461 | if (stretch < 0) | |
9462 | stretch = - ((- stretch) | |
9463 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9464 | else | |
9465 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9466 | if (stretch == 0) | |
9467 | break; | |
9468 | } | |
9469 | } | |
9470 | val += stretch; | |
9471 | } | |
9472 | ||
a677feeb ILT |
9473 | addr = fragp->fr_address + fragp->fr_fix; |
9474 | ||
9475 | /* The base address rules are complicated. The base address of | |
9476 | a branch is the following instruction. The base address of a | |
9477 | PC relative load or add is the instruction itself, but if it | |
9478 | is extended add 2, and if it is in a delay slot (in which | |
9479 | case it can not be extended) use the address of the | |
9480 | instruction whose delay slot it is in. */ | |
9481 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9482 | { |
9483 | addr += 2; | |
9484 | /* Ignore the low bit in the target, since it will be set | |
9485 | for a text label. */ | |
9486 | if ((val & 1) != 0) | |
9487 | --val; | |
9488 | } | |
a677feeb ILT |
9489 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9490 | addr -= 4; | |
9491 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9492 | addr -= 2; | |
cc5703cd ILT |
9493 | |
9494 | /* If we are currently assuming that this frag should be | |
9495 | extended, then the current address is two bytes higher. */ | |
9496 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9497 | addr += 2; | |
9498 | ||
9499 | val -= addr & ~ ((1 << op->shift) - 1); | |
9500 | ||
9501 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9502 | if (type == 'p' || type == 'q') | |
9503 | val /= 2; | |
9504 | ||
9505 | /* If any of the shifted bits are set, we must use an extended | |
9506 | opcode. If the address depends on the size of this | |
9507 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9508 | use an extended opcode. We only check this when we are in |
9509 | the main relaxation loop, when SEC is NULL. */ | |
9510 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9511 | { | |
9512 | fragp->fr_subtype = | |
9513 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9514 | return 1; | |
9515 | } | |
9516 | ||
9517 | /* If we are about to mark a frag as extended because the value | |
9518 | is precisely maxtiny + 1, then there is a chance of an | |
9519 | infinite loop as in the following code: | |
9520 | la $4,foo | |
9521 | .skip 1020 | |
9522 | .align 2 | |
9523 | foo: | |
9524 | In this case when the la is extended, foo is 0x3fc bytes | |
9525 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9526 | the la must be extended. To avoid this loop, we mark the | |
9527 | frag as extended if it was small, and is about to become | |
9528 | extended with a value of maxtiny + 1. */ | |
9529 | if (val == ((maxtiny + 1) << op->shift) | |
9530 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9531 | && sec == NULL) | |
cc5703cd ILT |
9532 | { |
9533 | fragp->fr_subtype = | |
9534 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9535 | return 1; | |
9536 | } | |
9537 | } | |
41a0ed22 ILT |
9538 | else if (symsec != absolute_section && sec != NULL) |
9539 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9540 | |
9541 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9542 | || val < (mintiny << op->shift) | |
9543 | || val > (maxtiny << op->shift)) | |
9544 | return 1; | |
9545 | else | |
9546 | return 0; | |
9547 | } | |
9548 | ||
9549 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9550 | mips16, we are not really relaxing here, and the final size is | |
9551 | encoded in the subtype information. For the mips16, we have to | |
9552 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9553 | |
0dd2d296 ILT |
9554 | /*ARGSUSED*/ |
9555 | int | |
9556 | md_estimate_size_before_relax (fragp, segtype) | |
9557 | fragS *fragp; | |
9558 | asection *segtype; | |
9559 | { | |
9560 | int change; | |
9561 | ||
cc5703cd ILT |
9562 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9563 | { | |
9564 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9565 | { | |
9566 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9567 | return 4; | |
9568 | } | |
9569 | else | |
9570 | { | |
9571 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9572 | return 2; | |
9573 | } | |
9574 | } | |
9575 | ||
d9aba805 | 9576 | if (mips_pic == NO_PIC) |
0dd2d296 | 9577 | { |
d8a1c247 | 9578 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9579 | } |
d9aba805 | 9580 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9581 | { |
9582 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9583 | ||
9584 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9585 | change = (symsec != &bfd_und_section | |
9586 | && symsec != &bfd_abs_section | |
9587 | && ! bfd_is_com_section (symsec)); | |
9588 | } | |
d9aba805 ILT |
9589 | else |
9590 | abort (); | |
0dd2d296 ILT |
9591 | |
9592 | if (change) | |
9593 | { | |
9594 | /* Record the offset to the first reloc in the fr_opcode field. | |
9595 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9596 | must be expanded. */ | |
9597 | fragp->fr_opcode = (fragp->fr_literal | |
9598 | + fragp->fr_fix | |
9599 | - RELAX_OLD (fragp->fr_subtype) | |
9600 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9601 | /* FIXME: This really needs as_warn_where. */ | |
9602 | if (RELAX_WARN (fragp->fr_subtype)) | |
9603 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9604 | } | |
9605 | ||
9606 | if (! change) | |
9607 | return 0; | |
9608 | else | |
9609 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9610 | } | |
9611 | ||
0d7f9025 ILT |
9612 | /* This is called to see whether a reloc against a defined symbol |
9613 | should be converted into a reloc against a section. Don't adjust | |
9614 | MIPS16 jump relocations, so we don't have to worry about the format | |
9615 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
9616 | mips16 symbols, so that the linker can find them if it needs to set |
9617 | up a stub. */ | |
0d7f9025 ILT |
9618 | |
9619 | int | |
9620 | mips_fix_adjustable (fixp) | |
9621 | fixS *fixp; | |
9622 | { | |
9623 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
9624 | return 0; | |
9625 | if (fixp->fx_addsy == NULL) | |
9626 | return 1; | |
0d7f9025 ILT |
9627 | #ifdef S_GET_OTHER |
9628 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9629 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16) | |
9630 | return 0; | |
9631 | #endif | |
9632 | return 1; | |
9633 | } | |
9634 | ||
0dd2d296 ILT |
9635 | /* Translate internal representation of relocation info to BFD target |
9636 | format. */ | |
9637 | ||
9638 | arelent ** | |
3d3c5039 ILT |
9639 | tc_gen_reloc (section, fixp) |
9640 | asection *section; | |
9641 | fixS *fixp; | |
9642 | { | |
0dd2d296 | 9643 | static arelent *retval[4]; |
3d3c5039 | 9644 | arelent *reloc; |
a8aed9dd | 9645 | bfd_reloc_code_real_type code; |
3d3c5039 | 9646 | |
0dd2d296 ILT |
9647 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9648 | retval[1] = NULL; | |
3d3c5039 ILT |
9649 | |
9650 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9651 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9652 | |
9653 | if (mips_pic == EMBEDDED_PIC | |
9654 | && SWITCH_TABLE (fixp)) | |
9655 | { | |
9656 | /* For a switch table entry we use a special reloc. The addend | |
9657 | is actually the difference between the reloc address and the | |
9658 | subtrahend. */ | |
9659 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9660 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9661 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9662 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9663 | } | |
ecd4ca1c ILT |
9664 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9665 | { | |
9666 | /* We use a special addend for an internal RELLO reloc. */ | |
9667 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9668 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9669 | else | |
9670 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9671 | } | |
9672 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9673 | { | |
9674 | assert (fixp->fx_next != NULL | |
9675 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9676 | /* We use a special addend for an internal RELHI reloc. The | |
9677 | reloc is relative to the RELLO; adjust the addend | |
9678 | accordingly. */ | |
9679 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9680 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9681 | + fixp->fx_next->fx_where | |
9682 | - S_GET_VALUE (fixp->fx_subsy)); | |
9683 | else | |
9684 | reloc->addend = (fixp->fx_addnumber | |
9685 | + fixp->fx_next->fx_frag->fr_address | |
9686 | + fixp->fx_next->fx_where); | |
9687 | } | |
1c803e52 | 9688 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9689 | reloc->addend = fixp->fx_addnumber; |
9690 | else | |
5b63f465 | 9691 | { |
1dc1e798 KR |
9692 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9693 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9694 | handling. */ | |
9695 | reloc->addend = reloc->address; | |
9696 | else | |
9697 | reloc->addend = -reloc->address; | |
5b63f465 | 9698 | } |
0dd2d296 ILT |
9699 | |
9700 | /* If this is a variant frag, we may need to adjust the existing | |
9701 | reloc and generate a new one. */ | |
9702 | if (fixp->fx_frag->fr_opcode != NULL | |
9703 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9704 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9705 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9706 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9707 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9708 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9709 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9710 | { |
9711 | arelent *reloc2; | |
9712 | ||
cc5703cd ILT |
9713 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9714 | ||
0dd2d296 | 9715 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9716 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9717 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9718 | the second one handle all of them. */ | |
0dd2d296 ILT |
9719 | if (fixp->fx_next != NULL |
9720 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9721 | { | |
fb251650 ILT |
9722 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9723 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9724 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9725 | && (fixp->fx_next->fx_r_type | |
9726 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9727 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9728 | && (fixp->fx_next->fx_r_type | |
9729 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9730 | retval[0] = NULL; |
9731 | return retval; | |
9732 | } | |
9733 | ||
9734 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9735 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9736 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9737 | retval[2] = NULL; | |
9738 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9739 | reloc2->address = (reloc->address | |
9740 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9741 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9742 | reloc2->addend = fixp->fx_addnumber; | |
9743 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9744 | assert (reloc2->howto != NULL); | |
9745 | ||
9746 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9747 | { | |
9748 | arelent *reloc3; | |
9749 | ||
9750 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9751 | retval[3] = NULL; | |
9752 | *reloc3 = *reloc2; | |
9753 | reloc3->address += 4; | |
9754 | } | |
9755 | ||
d9aba805 | 9756 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9757 | { |
9758 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9759 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9760 | } | |
d9aba805 | 9761 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9762 | { |
fb251650 | 9763 | switch (fixp->fx_r_type) |
0dd2d296 | 9764 | { |
fb251650 ILT |
9765 | default: |
9766 | abort (); | |
9767 | case BFD_RELOC_MIPS_GOT16: | |
9768 | break; | |
9769 | case BFD_RELOC_MIPS_CALL16: | |
9770 | case BFD_RELOC_MIPS_GOT_LO16: | |
9771 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9772 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9773 | break; |
0dd2d296 ILT |
9774 | } |
9775 | } | |
d9aba805 ILT |
9776 | else |
9777 | abort (); | |
0dd2d296 ILT |
9778 | } |
9779 | ||
a8aed9dd ILT |
9780 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9781 | fixup_segment converted a non-PC relative reloc into a PC | |
9782 | relative reloc. In such a case, we need to convert the reloc | |
9783 | code. */ | |
9784 | code = fixp->fx_r_type; | |
9785 | if (fixp->fx_pcrel) | |
9786 | { | |
9787 | switch (code) | |
9788 | { | |
9789 | case BFD_RELOC_8: | |
9790 | code = BFD_RELOC_8_PCREL; | |
9791 | break; | |
9792 | case BFD_RELOC_16: | |
9793 | code = BFD_RELOC_16_PCREL; | |
9794 | break; | |
9795 | case BFD_RELOC_32: | |
9796 | code = BFD_RELOC_32_PCREL; | |
9797 | break; | |
bf39474f ILT |
9798 | case BFD_RELOC_64: |
9799 | code = BFD_RELOC_64_PCREL; | |
9800 | break; | |
a8aed9dd ILT |
9801 | case BFD_RELOC_8_PCREL: |
9802 | case BFD_RELOC_16_PCREL: | |
9803 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9804 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9805 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9806 | case BFD_RELOC_PCREL_HI16_S: |
9807 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9808 | break; |
9809 | default: | |
9810 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9811 | "Cannot make %s relocation PC relative", | |
9812 | bfd_get_reloc_code_name (code)); | |
9813 | } | |
9814 | } | |
9815 | ||
d9aba805 ILT |
9816 | /* To support a PC relative reloc when generating embedded PIC code |
9817 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9818 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9819 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9820 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9821 | && mips_pic != EMBEDDED_PIC) |
9822 | reloc->howto = NULL; | |
9823 | else | |
a8aed9dd | 9824 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9825 | |
52aa70b5 JW |
9826 | if (reloc->howto == NULL) |
9827 | { | |
9828 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9829 | "Can not represent %s relocation in this object file format", |
9830 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9831 | retval[0] = NULL; |
52aa70b5 | 9832 | } |
3d3c5039 | 9833 | |
0dd2d296 | 9834 | return retval; |
3d3c5039 ILT |
9835 | } |
9836 | ||
cc5703cd ILT |
9837 | /* Relax a machine dependent frag. This returns the amount by which |
9838 | the current size of the frag should change. */ | |
9839 | ||
9840 | int | |
9841 | mips_relax_frag (fragp, stretch) | |
9842 | fragS *fragp; | |
9843 | long stretch; | |
9844 | { | |
9845 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9846 | return 0; | |
9847 | ||
9848 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9849 | { | |
9850 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9851 | return 0; | |
9852 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9853 | return 2; | |
9854 | } | |
9855 | else | |
9856 | { | |
9857 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9858 | return 0; | |
9859 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9860 | return -2; | |
9861 | } | |
9862 | ||
9863 | return 0; | |
9864 | } | |
9865 | ||
0dd2d296 ILT |
9866 | /* Convert a machine dependent frag. */ |
9867 | ||
9868 | void | |
9869 | md_convert_frag (abfd, asec, fragp) | |
9870 | bfd *abfd; | |
9871 | segT asec; | |
9872 | fragS *fragp; | |
3d3c5039 | 9873 | { |
0dd2d296 ILT |
9874 | int old, new; |
9875 | char *fixptr; | |
3d3c5039 | 9876 | |
cc5703cd ILT |
9877 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9878 | { | |
9879 | int type; | |
9880 | register const struct mips16_immed_operand *op; | |
9881 | boolean small, ext; | |
9882 | offsetT val; | |
9883 | bfd_byte *buf; | |
9884 | unsigned long insn; | |
9885 | boolean use_extend; | |
9886 | unsigned short extend; | |
9887 | ||
9888 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9889 | op = mips16_immed_operands; | |
9890 | while (op->type != type) | |
9891 | ++op; | |
9892 | ||
9893 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9894 | { | |
9895 | small = false; | |
9896 | ext = true; | |
9897 | } | |
9898 | else | |
9899 | { | |
9900 | small = true; | |
9901 | ext = false; | |
9902 | } | |
9903 | ||
f74ba7a3 | 9904 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 9905 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
9906 | if (op->pcrel) |
9907 | { | |
9908 | addressT addr; | |
9909 | ||
a677feeb ILT |
9910 | addr = fragp->fr_address + fragp->fr_fix; |
9911 | ||
9912 | /* The rules for the base address of a PC relative reloc are | |
9913 | complicated; see mips16_extended_frag. */ | |
9914 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9915 | { |
9916 | addr += 2; | |
9917 | /* Ignore the low bit in the target, since it will be | |
9918 | set for a text label. */ | |
9919 | if ((val & 1) != 0) | |
9920 | --val; | |
9921 | } | |
a677feeb ILT |
9922 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9923 | addr -= 4; | |
9924 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9925 | addr -= 2; | |
9926 | ||
cc5703cd ILT |
9927 | if (ext) |
9928 | addr += 2; | |
9929 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9930 | val -= addr; | |
a677feeb ILT |
9931 | |
9932 | /* Make sure the section winds up with the alignment we have | |
9933 | assumed. */ | |
9934 | if (op->shift > 0) | |
9935 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
9936 | } |
9937 | ||
9938 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
9939 | ||
b9129c6f ILT |
9940 | if (target_big_endian) |
9941 | insn = bfd_getb16 (buf); | |
9942 | else | |
9943 | insn = bfd_getl16 (buf); | |
cc5703cd | 9944 | |
31a2c6ff ILT |
9945 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
9946 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
9947 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
9948 | |
9949 | if (use_extend) | |
9950 | { | |
9951 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
9952 | fragp->fr_fix += 2; | |
9953 | buf += 2; | |
9954 | } | |
3d3c5039 | 9955 | |
cc5703cd ILT |
9956 | md_number_to_chars (buf, insn, 2); |
9957 | fragp->fr_fix += 2; | |
9958 | buf += 2; | |
9959 | } | |
9960 | else | |
9961 | { | |
9962 | if (fragp->fr_opcode == NULL) | |
9963 | return; | |
0dd2d296 | 9964 | |
cc5703cd ILT |
9965 | old = RELAX_OLD (fragp->fr_subtype); |
9966 | new = RELAX_NEW (fragp->fr_subtype); | |
9967 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 9968 | |
cc5703cd ILT |
9969 | if (new > 0) |
9970 | memcpy (fixptr - old, fixptr, new); | |
9971 | ||
9972 | fragp->fr_fix += new - old; | |
9973 | } | |
0dd2d296 | 9974 | } |
becfe05e | 9975 | |
fbcfacb7 ILT |
9976 | #ifdef OBJ_ELF |
9977 | ||
9978 | /* This function is called after the relocs have been generated. | |
9979 | We've been storing mips16 text labels as odd. Here we convert them | |
9980 | back to even for the convenience of the debugger. */ | |
9981 | ||
9982 | void | |
9983 | mips_frob_file_after_relocs () | |
9984 | { | |
9985 | asymbol **syms; | |
9986 | unsigned int count, i; | |
9987 | ||
9988 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9989 | return; | |
9990 | ||
9991 | syms = bfd_get_outsymbols (stdoutput); | |
9992 | count = bfd_get_symcount (stdoutput); | |
9993 | for (i = 0; i < count; i++, syms++) | |
9994 | { | |
9995 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
9996 | && ((*syms)->value & 1) != 0) | |
9997 | { | |
9998 | (*syms)->value &= ~1; | |
9999 | /* If the symbol has an odd size, it was probably computed | |
10000 | incorrectly, so adjust that as well. */ | |
10001 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10002 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10003 | } | |
10004 | } | |
10005 | } | |
10006 | ||
10007 | #endif | |
10008 | ||
becfe05e ILT |
10009 | /* This function is called whenever a label is defined. It is used |
10010 | when handling branch delays; if a branch has a label, we assume we | |
10011 | can not move it. */ | |
10012 | ||
10013 | void | |
10014 | mips_define_label (sym) | |
10015 | symbolS *sym; | |
10016 | { | |
fbcfacb7 ILT |
10017 | struct insn_label_list *l; |
10018 | ||
10019 | if (free_insn_labels == NULL) | |
10020 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10021 | else | |
10022 | { | |
10023 | l = free_insn_labels; | |
10024 | free_insn_labels = l->next; | |
10025 | } | |
10026 | ||
10027 | l->label = sym; | |
10028 | l->next = insn_labels; | |
10029 | insn_labels = l; | |
becfe05e | 10030 | } |
22ba90ce ILT |
10031 | |
10032 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
10033 | In order to work with gcc when using mips-tfile, we must keep all | |
10034 | local labels. However, in other cases, we want to discard them, | |
10035 | since they are useless. */ | |
10036 | ||
10037 | int | |
10038 | mips_local_label (name) | |
10039 | const char *name; | |
10040 | { | |
c625fc23 | 10041 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
10042 | if (ECOFF_DEBUGGING |
10043 | && mips_debug != 0 | |
10044 | && ! ecoff_debugging_seen) | |
10045 | { | |
10046 | /* We were called with -g, but we didn't see any debugging | |
10047 | information. That may mean that gcc is smuggling debugging | |
10048 | information through to mips-tfile, in which case we must | |
10049 | generate all local labels. */ | |
10050 | return 0; | |
10051 | } | |
c625fc23 | 10052 | #endif |
22ba90ce ILT |
10053 | |
10054 | /* Here it's OK to discard local labels. */ | |
10055 | ||
3af584b4 | 10056 | return name[0] == '$'; |
22ba90ce | 10057 | } |
3d3c5039 | 10058 | \f |
739708fa | 10059 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10060 | |
0dd2d296 | 10061 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10062 | |
10063 | void | |
10064 | mips_elf_final_processing () | |
10065 | { | |
87178180 ILT |
10066 | /* Write out the register information. */ |
10067 | if (! mips_64) | |
10068 | { | |
10069 | Elf32_RegInfo s; | |
10070 | ||
10071 | s.ri_gprmask = mips_gprmask; | |
10072 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10073 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10074 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10075 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10076 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10077 | ||
10078 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10079 | ((Elf32_External_RegInfo *) | |
10080 | mips_regmask_frag)); | |
10081 | } | |
10082 | else | |
10083 | { | |
10084 | Elf64_Internal_RegInfo s; | |
10085 | ||
10086 | s.ri_gprmask = mips_gprmask; | |
10087 | s.ri_pad = 0; | |
10088 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10089 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10090 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10091 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10092 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10093 | ||
10094 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10095 | ((Elf64_External_RegInfo *) | |
10096 | mips_regmask_frag)); | |
10097 | } | |
0dd2d296 ILT |
10098 | |
10099 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10100 | sort of BFD interface for this. */ | |
10101 | if (mips_any_noreorder) | |
10102 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10103 | if (mips_pic != NO_PIC) |
0dd2d296 | 10104 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10105 | } |
10106 | ||
739708fa | 10107 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10108 | \f |
3d3c5039 ILT |
10109 | /* These functions should really be defined by the object file format, |
10110 | since they are related to debugging information. However, this | |
10111 | code has to work for the a.out format, which does not define them, | |
10112 | so we provide simple versions here. These don't actually generate | |
10113 | any debugging information, but they do simple checking and someday | |
10114 | somebody may make them useful. */ | |
10115 | ||
670a50eb ILT |
10116 | typedef struct loc |
10117 | { | |
10118 | struct loc *loc_next; | |
10119 | unsigned long loc_fileno; | |
10120 | unsigned long loc_lineno; | |
10121 | unsigned long loc_offset; | |
10122 | unsigned short loc_delta; | |
10123 | unsigned short loc_count; | |
3d3c5039 | 10124 | #if 0 |
670a50eb | 10125 | fragS *loc_frag; |
3d3c5039 | 10126 | #endif |
670a50eb ILT |
10127 | } |
10128 | locS; | |
3d3c5039 | 10129 | |
670a50eb ILT |
10130 | typedef struct proc |
10131 | { | |
3d3c5039 ILT |
10132 | struct proc *proc_next; |
10133 | struct symbol *proc_isym; | |
10134 | struct symbol *proc_end; | |
10135 | unsigned long proc_reg_mask; | |
10136 | unsigned long proc_reg_offset; | |
10137 | unsigned long proc_fpreg_mask; | |
10138 | unsigned long proc_fpreg_offset; | |
10139 | unsigned long proc_frameoffset; | |
10140 | unsigned long proc_framereg; | |
10141 | unsigned long proc_pcreg; | |
10142 | locS *proc_iline; | |
10143 | struct file *proc_file; | |
10144 | int proc_index; | |
670a50eb ILT |
10145 | } |
10146 | procS; | |
3d3c5039 | 10147 | |
670a50eb ILT |
10148 | typedef struct file |
10149 | { | |
3d3c5039 ILT |
10150 | struct file *file_next; |
10151 | unsigned long file_fileno; | |
10152 | struct symbol *file_symbol; | |
10153 | struct symbol *file_end; | |
10154 | struct proc *file_proc; | |
10155 | int file_numprocs; | |
670a50eb ILT |
10156 | } |
10157 | fileS; | |
3d3c5039 ILT |
10158 | |
10159 | static struct obstack proc_frags; | |
10160 | static procS *proc_lastP; | |
10161 | static procS *proc_rootP; | |
10162 | static int numprocs; | |
10163 | ||
10164 | static void | |
10165 | md_obj_begin () | |
10166 | { | |
670a50eb | 10167 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10168 | } |
10169 | ||
10170 | static void | |
10171 | md_obj_end () | |
10172 | { | |
10173 | /* check for premature end, nesting errors, etc */ | |
10174 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10175 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10176 | } |
10177 | ||
3d3c5039 ILT |
10178 | static long |
10179 | get_number () | |
10180 | { | |
670a50eb ILT |
10181 | int negative = 0; |
10182 | long val = 0; | |
3d3c5039 | 10183 | |
670a50eb ILT |
10184 | if (*input_line_pointer == '-') |
10185 | { | |
10186 | ++input_line_pointer; | |
10187 | negative = 1; | |
3d3c5039 | 10188 | } |
670a50eb ILT |
10189 | if (!isdigit (*input_line_pointer)) |
10190 | as_bad ("Expected simple number."); | |
10191 | if (input_line_pointer[0] == '0') | |
10192 | { | |
10193 | if (input_line_pointer[1] == 'x') | |
10194 | { | |
10195 | input_line_pointer += 2; | |
10196 | while (isxdigit (*input_line_pointer)) | |
10197 | { | |
10198 | val <<= 4; | |
3a762a0b | 10199 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10200 | } |
670a50eb ILT |
10201 | return negative ? -val : val; |
10202 | } | |
10203 | else | |
10204 | { | |
10205 | ++input_line_pointer; | |
10206 | while (isdigit (*input_line_pointer)) | |
10207 | { | |
10208 | val <<= 3; | |
10209 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10210 | } |
670a50eb | 10211 | return negative ? -val : val; |
3d3c5039 ILT |
10212 | } |
10213 | } | |
670a50eb ILT |
10214 | if (!isdigit (*input_line_pointer)) |
10215 | { | |
10216 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10217 | *input_line_pointer, *input_line_pointer); | |
10218 | as_warn ("Invalid number"); | |
10219 | return -1; | |
3d3c5039 | 10220 | } |
670a50eb ILT |
10221 | while (isdigit (*input_line_pointer)) |
10222 | { | |
10223 | val *= 10; | |
10224 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10225 | } |
670a50eb | 10226 | return negative ? -val : val; |
3d3c5039 ILT |
10227 | } |
10228 | ||
10229 | /* The .file directive; just like the usual .file directive, but there | |
10230 | is an initial number which is the ECOFF file index. */ | |
10231 | ||
10232 | static void | |
10233 | s_file (x) | |
10234 | int x; | |
10235 | { | |
670a50eb | 10236 | int line; |
3d3c5039 | 10237 | |
670a50eb | 10238 | line = get_number (); |
9a7d824a | 10239 | s_app_file (0); |
3d3c5039 ILT |
10240 | } |
10241 | ||
10242 | ||
10243 | /* The .end directive. */ | |
10244 | ||
10245 | static void | |
10246 | s_mipsend (x) | |
10247 | int x; | |
10248 | { | |
670a50eb ILT |
10249 | symbolS *p; |
10250 | ||
10251 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10252 | { | |
10253 | p = get_symbol (); | |
10254 | demand_empty_rest_of_line (); | |
10255 | } | |
10256 | else | |
10257 | p = NULL; | |
10258 | if (now_seg != text_section) | |
10259 | as_warn (".end not in text section"); | |
10260 | if (!proc_lastP) | |
10261 | { | |
10262 | as_warn (".end and no .ent seen yet."); | |
10263 | return; | |
3d3c5039 ILT |
10264 | } |
10265 | ||
670a50eb ILT |
10266 | if (p != NULL) |
10267 | { | |
10268 | assert (S_GET_NAME (p)); | |
10269 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10270 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10271 | } |
10272 | ||
670a50eb | 10273 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10274 | } |
10275 | ||
10276 | /* The .aent and .ent directives. */ | |
10277 | ||
10278 | static void | |
10279 | s_ent (aent) | |
10280 | int aent; | |
10281 | { | |
670a50eb ILT |
10282 | int number = 0; |
10283 | procS *procP; | |
10284 | symbolS *symbolP; | |
10285 | ||
10286 | symbolP = get_symbol (); | |
10287 | if (*input_line_pointer == ',') | |
10288 | input_line_pointer++; | |
dd3f1f76 | 10289 | SKIP_WHITESPACE (); |
670a50eb ILT |
10290 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10291 | number = get_number (); | |
10292 | if (now_seg != text_section) | |
10293 | as_warn (".ent or .aent not in text section."); | |
10294 | ||
10295 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10296 | as_warn ("missing `.end'"); | |
10297 | ||
10298 | if (!aent) | |
10299 | { | |
10300 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10301 | procP->proc_isym = symbolP; | |
10302 | procP->proc_reg_mask = 0; | |
10303 | procP->proc_reg_offset = 0; | |
10304 | procP->proc_fpreg_mask = 0; | |
10305 | procP->proc_fpreg_offset = 0; | |
10306 | procP->proc_frameoffset = 0; | |
10307 | procP->proc_framereg = 0; | |
10308 | procP->proc_pcreg = 0; | |
10309 | procP->proc_end = NULL; | |
10310 | procP->proc_next = NULL; | |
10311 | if (proc_lastP) | |
10312 | proc_lastP->proc_next = procP; | |
10313 | else | |
10314 | proc_rootP = procP; | |
10315 | proc_lastP = procP; | |
10316 | numprocs++; | |
3d3c5039 | 10317 | } |
670a50eb | 10318 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10319 | } |
10320 | ||
10321 | /* The .frame directive. */ | |
10322 | ||
88225433 | 10323 | #if 0 |
3d3c5039 ILT |
10324 | static void |
10325 | s_frame (x) | |
670a50eb | 10326 | int x; |
3d3c5039 | 10327 | { |
670a50eb ILT |
10328 | char str[100]; |
10329 | symbolS *symP; | |
10330 | int frame_reg; | |
10331 | int frame_off; | |
10332 | int pcreg; | |
10333 | ||
0dd2d296 | 10334 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10335 | if (*input_line_pointer == ',') |
10336 | input_line_pointer++; | |
5ac34ac3 | 10337 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10338 | if (*input_line_pointer == ',') |
10339 | input_line_pointer++; | |
0dd2d296 | 10340 | pcreg = tc_get_register (0); |
670a50eb ILT |
10341 | |
10342 | /* bob third eye */ | |
10343 | assert (proc_rootP); | |
10344 | proc_rootP->proc_framereg = frame_reg; | |
10345 | proc_rootP->proc_frameoffset = frame_off; | |
10346 | proc_rootP->proc_pcreg = pcreg; | |
10347 | /* bob macho .frame */ | |
10348 | ||
10349 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10350 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10351 | { |
10352 | if (!proc_lastP) | |
10353 | as_warn ("No .ent for .frame to use."); | |
10354 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10355 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10356 | S_SET_TYPE (symP, N_RMASK); | |
10357 | S_SET_OTHER (symP, 0); | |
10358 | S_SET_DESC (symP, 0); | |
10359 | symP->sy_forward = proc_lastP->proc_isym; | |
10360 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10361 | } |
670a50eb | 10362 | demand_empty_rest_of_line (); |
3d3c5039 | 10363 | } |
88225433 | 10364 | #endif |
3d3c5039 ILT |
10365 | |
10366 | /* The .fmask and .mask directives. */ | |
10367 | ||
88225433 | 10368 | #if 0 |
3d3c5039 ILT |
10369 | static void |
10370 | s_mask (reg_type) | |
10371 | char reg_type; | |
10372 | { | |
670a50eb ILT |
10373 | char str[100], *strP; |
10374 | symbolS *symP; | |
10375 | int i; | |
10376 | unsigned int mask; | |
10377 | int off; | |
10378 | ||
10379 | mask = get_number (); | |
10380 | if (*input_line_pointer == ',') | |
10381 | input_line_pointer++; | |
10382 | off = get_absolute_expression (); | |
10383 | ||
10384 | /* bob only for coff */ | |
10385 | assert (proc_rootP); | |
10386 | if (reg_type == 'F') | |
10387 | { | |
10388 | proc_rootP->proc_fpreg_mask = mask; | |
10389 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10390 | } |
670a50eb ILT |
10391 | else |
10392 | { | |
10393 | proc_rootP->proc_reg_mask = mask; | |
10394 | proc_rootP->proc_reg_offset = off; | |
10395 | } | |
10396 | ||
10397 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10398 | |
670a50eb ILT |
10399 | /* We don't have to write out a mask stab if no saved regs. */ |
10400 | if (!(mask == 0)) | |
10401 | { | |
10402 | if (!proc_lastP) | |
10403 | as_warn ("No .ent for .mask to use."); | |
10404 | strP = str; | |
10405 | for (i = 0; i < 32; i++) | |
10406 | { | |
10407 | if (mask % 2) | |
10408 | { | |
10409 | sprintf (strP, "%c%d,", reg_type, i); | |
10410 | strP += strlen (strP); | |
10411 | } | |
3d3c5039 | 10412 | mask /= 2; |
670a50eb ILT |
10413 | } |
10414 | sprintf (strP, ";%d,", off); | |
10415 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10416 | S_SET_TYPE (symP, N_RMASK); | |
10417 | S_SET_OTHER (symP, 0); | |
10418 | S_SET_DESC (symP, 0); | |
10419 | symP->sy_forward = proc_lastP->proc_isym; | |
10420 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10421 | } |
3d3c5039 | 10422 | } |
88225433 | 10423 | #endif |
3d3c5039 ILT |
10424 | |
10425 | /* The .loc directive. */ | |
10426 | ||
88225433 | 10427 | #if 0 |
3d3c5039 ILT |
10428 | static void |
10429 | s_loc (x) | |
10430 | int x; | |
10431 | { | |
670a50eb ILT |
10432 | symbolS *symbolP; |
10433 | int lineno; | |
10434 | int addroff; | |
3d3c5039 | 10435 | |
670a50eb | 10436 | assert (now_seg == text_section); |
3d3c5039 | 10437 | |
670a50eb | 10438 | lineno = get_number (); |
87e48495 | 10439 | addroff = frag_now_fix (); |
3d3c5039 | 10440 | |
670a50eb ILT |
10441 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10442 | S_SET_TYPE (symbolP, N_SLINE); | |
10443 | S_SET_OTHER (symbolP, 0); | |
10444 | S_SET_DESC (symbolP, lineno); | |
10445 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10446 | } |
88225433 | 10447 | #endif |