Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
1f25f5d3 CD |
211 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
212 | if they have not been initialized. Changed by `.set <asename>', by | |
213 | command line options, and based on the default architecture. */ | |
214 | int ase_mips3d; | |
deec1734 | 215 | int ase_mdmx; |
e16bfa71 | 216 | int ase_smartmips; |
74cd071d | 217 | int ase_dsp; |
8b082fb1 | 218 | int ase_dspr2; |
ef2e4d86 | 219 | int ase_mt; |
dec0624d | 220 | int ase_mcu; |
b015e599 | 221 | int ase_virt; |
252b5132 RH |
222 | /* Whether we are assembling for the mips16 processor. 0 if we are |
223 | not, 1 if we are, and -1 if the value has not been initialized. | |
224 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
225 | -nomips16 command line options, and the default CPU. */ | |
226 | int mips16; | |
df58fc94 RS |
227 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
228 | 1 if we are, and -1 if the value has not been initialized. Changed | |
229 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
230 | and -mno-micromips command line options, and the default CPU. */ | |
231 | int micromips; | |
252b5132 RH |
232 | /* Non-zero if we should not reorder instructions. Changed by `.set |
233 | reorder' and `.set noreorder'. */ | |
234 | int noreorder; | |
741fe287 MR |
235 | /* Non-zero if we should not permit the register designated "assembler |
236 | temporary" to be used in instructions. The value is the register | |
237 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
238 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
239 | unsigned int at; | |
252b5132 RH |
240 | /* Non-zero if we should warn when a macro instruction expands into |
241 | more than one machine instruction. Changed by `.set nomacro' and | |
242 | `.set macro'. */ | |
243 | int warn_about_macros; | |
244 | /* Non-zero if we should not move instructions. Changed by `.set | |
245 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
246 | int nomove; | |
247 | /* Non-zero if we should not optimize branches by moving the target | |
248 | of the branch into the delay slot. Actually, we don't perform | |
249 | this optimization anyhow. Changed by `.set bopt' and `.set | |
250 | nobopt'. */ | |
251 | int nobopt; | |
252 | /* Non-zero if we should not autoextend mips16 instructions. | |
253 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
254 | int noautoextend; | |
a325df1d TS |
255 | /* Restrict general purpose registers and floating point registers |
256 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
257 | is passed but can changed if the assembler code uses .set mipsN. */ | |
258 | int gp32; | |
259 | int fp32; | |
fef14a42 TS |
260 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
261 | command line option, and the default CPU. */ | |
262 | int arch; | |
aed1a261 RS |
263 | /* True if ".set sym32" is in effect. */ |
264 | bfd_boolean sym32; | |
037b32b9 AN |
265 | /* True if floating-point operations are not allowed. Changed by .set |
266 | softfloat or .set hardfloat, by command line options -msoft-float or | |
267 | -mhard-float. The default is false. */ | |
268 | bfd_boolean soft_float; | |
269 | ||
270 | /* True if only single-precision floating-point operations are allowed. | |
271 | Changed by .set singlefloat or .set doublefloat, command-line options | |
272 | -msingle-float or -mdouble-float. The default is false. */ | |
273 | bfd_boolean single_float; | |
252b5132 RH |
274 | }; |
275 | ||
037b32b9 AN |
276 | /* This is the struct we use to hold the current set of options. Note |
277 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
278 | -1 to indicate that they have not been initialized. */ | |
279 | ||
a325df1d | 280 | /* True if -mgp32 was passed. */ |
a8e8e863 | 281 | static int file_mips_gp32 = -1; |
a325df1d TS |
282 | |
283 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 284 | static int file_mips_fp32 = -1; |
a325df1d | 285 | |
037b32b9 AN |
286 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
287 | static int file_mips_soft_float = 0; | |
288 | ||
289 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
290 | static int file_mips_single_float = 0; | |
252b5132 | 291 | |
e972090a NC |
292 | static struct mips_set_options mips_opts = |
293 | { | |
037b32b9 AN |
294 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
295 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
b015e599 AP |
296 | /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1, |
297 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
298 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
299 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
300 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 301 | }; |
252b5132 RH |
302 | |
303 | /* These variables are filled in with the masks of registers used. | |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
309 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 310 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 311 | |
738f4d98 | 312 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
313 | static int file_ase_mips16; |
314 | ||
3994f87e TS |
315 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
316 | || mips_opts.isa == ISA_MIPS32R2 \ | |
317 | || mips_opts.isa == ISA_MIPS64 \ | |
318 | || mips_opts.isa == ISA_MIPS64R2) | |
319 | ||
df58fc94 RS |
320 | /* True if any microMIPS code was produced. */ |
321 | static int file_ase_micromips; | |
322 | ||
b12dd2e4 CF |
323 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
324 | #ifdef TE_IRIX | |
1180b5a4 | 325 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 326 | #else |
1180b5a4 RS |
327 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
328 | because there's no place for any addend, the only acceptable | |
329 | expression is a bare symbol. */ | |
330 | #define MIPS_JALR_HINT_P(EXPR) \ | |
331 | (!HAVE_IN_PLACE_ADDENDS \ | |
332 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
333 | #endif |
334 | ||
1f25f5d3 CD |
335 | /* True if -mips3d was passed or implied by arguments passed on the |
336 | command line (e.g., by -march). */ | |
337 | static int file_ase_mips3d; | |
338 | ||
deec1734 CD |
339 | /* True if -mdmx was passed or implied by arguments passed on the |
340 | command line (e.g., by -march). */ | |
341 | static int file_ase_mdmx; | |
342 | ||
e16bfa71 TS |
343 | /* True if -msmartmips was passed or implied by arguments passed on the |
344 | command line (e.g., by -march). */ | |
345 | static int file_ase_smartmips; | |
346 | ||
ad3fea08 TS |
347 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
348 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 349 | |
74cd071d CF |
350 | /* True if -mdsp was passed or implied by arguments passed on the |
351 | command line (e.g., by -march). */ | |
352 | static int file_ase_dsp; | |
353 | ||
ad3fea08 | 354 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
355 | || mips_opts.isa == ISA_MIPS64R2 \ |
356 | || mips_opts.micromips) | |
ad3fea08 | 357 | |
65263ce3 TS |
358 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
359 | ||
8b082fb1 TS |
360 | /* True if -mdspr2 was passed or implied by arguments passed on the |
361 | command line (e.g., by -march). */ | |
362 | static int file_ase_dspr2; | |
363 | ||
364 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
365 | || mips_opts.isa == ISA_MIPS64R2 \ |
366 | || mips_opts.micromips) | |
8b082fb1 | 367 | |
ef2e4d86 CF |
368 | /* True if -mmt was passed or implied by arguments passed on the |
369 | command line (e.g., by -march). */ | |
370 | static int file_ase_mt; | |
371 | ||
ad3fea08 TS |
372 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
373 | || mips_opts.isa == ISA_MIPS64R2) | |
374 | ||
dec0624d | 375 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
376 | || mips_opts.isa == ISA_MIPS64R2 \ |
377 | || mips_opts.micromips) | |
dec0624d | 378 | |
b015e599 AP |
379 | /* True if -mvirt was passed or implied by arguments passed on the |
380 | command line (e.g., by -march). */ | |
381 | static int file_ase_virt; | |
382 | ||
383 | #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
f122319e CF |
384 | || mips_opts.isa == ISA_MIPS64R2 \ |
385 | || mips_opts.micromips) | |
b015e599 | 386 | |
f122319e CF |
387 | #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \ |
388 | || (mips_opts.micromips \ | |
389 | && ISA_HAS_64BIT_REGS (mips_opts.isa))) | |
b015e599 | 390 | |
ec68c924 | 391 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 392 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 393 | static const char *mips_arch_string; |
ec68c924 EC |
394 | |
395 | /* The argument of the -mtune= flag. The architecture for which we | |
396 | are optimizing. */ | |
397 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 398 | static const char *mips_tune_string; |
ec68c924 | 399 | |
316f5878 | 400 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
401 | static int mips_32bitmode = 0; |
402 | ||
316f5878 RS |
403 | /* True if the given ABI requires 32-bit registers. */ |
404 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
405 | ||
406 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
407 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
408 | ((ABI) == N32_ABI \ | |
409 | || (ABI) == N64_ABI \ | |
316f5878 RS |
410 | || (ABI) == O64_ABI) |
411 | ||
ad3fea08 | 412 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
413 | #define ISA_HAS_64BIT_REGS(ISA) \ |
414 | ((ISA) == ISA_MIPS3 \ | |
415 | || (ISA) == ISA_MIPS4 \ | |
416 | || (ISA) == ISA_MIPS5 \ | |
417 | || (ISA) == ISA_MIPS64 \ | |
418 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 419 | |
ad3fea08 TS |
420 | /* Return true if ISA supports 64 bit wide float registers. */ |
421 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
422 | ((ISA) == ISA_MIPS3 \ | |
423 | || (ISA) == ISA_MIPS4 \ | |
424 | || (ISA) == ISA_MIPS5 \ | |
425 | || (ISA) == ISA_MIPS32R2 \ | |
426 | || (ISA) == ISA_MIPS64 \ | |
427 | || (ISA) == ISA_MIPS64R2) | |
428 | ||
af7ee8bf CD |
429 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
430 | instructions. */ | |
707bfff6 | 431 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
432 | ((ISA) == ISA_MIPS64R2 \ |
433 | || (mips_opts.micromips \ | |
434 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
435 | ) | |
af7ee8bf CD |
436 | |
437 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
438 | instructions. */ | |
707bfff6 TS |
439 | #define ISA_HAS_ROR(ISA) \ |
440 | ((ISA) == ISA_MIPS32R2 \ | |
441 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
442 | || mips_opts.ase_smartmips \ |
443 | || mips_opts.micromips \ | |
444 | ) | |
707bfff6 | 445 | |
7455baf8 TS |
446 | /* Return true if ISA supports single-precision floats in odd registers. */ |
447 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
448 | ((ISA) == ISA_MIPS32 \ | |
449 | || (ISA) == ISA_MIPS32R2 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
451 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 452 | |
ad3fea08 TS |
453 | /* Return true if ISA supports move to/from high part of a 64-bit |
454 | floating-point register. */ | |
455 | #define ISA_HAS_MXHC1(ISA) \ | |
456 | ((ISA) == ISA_MIPS32R2 \ | |
457 | || (ISA) == ISA_MIPS64R2) | |
458 | ||
e013f690 | 459 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 460 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 461 | |
e013f690 | 462 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 463 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 464 | |
ad3fea08 TS |
465 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
466 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 467 | |
316f5878 | 468 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 469 | |
316f5878 | 470 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 471 | |
3b91255e RS |
472 | /* True if relocations are stored in-place. */ |
473 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
474 | ||
aed1a261 RS |
475 | /* The ABI-derived address size. */ |
476 | #define HAVE_64BIT_ADDRESSES \ | |
477 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
478 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 479 | |
aed1a261 RS |
480 | /* The size of symbolic constants (i.e., expressions of the form |
481 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
482 | #define HAVE_32BIT_SYMBOLS \ | |
483 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
484 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 485 | |
b7c7d6c1 TS |
486 | /* Addresses are loaded in different ways, depending on the address size |
487 | in use. The n32 ABI Documentation also mandates the use of additions | |
488 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 489 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 493 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
494 | |
495 | #define ADDRESS_LOAD_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
497 | ||
498 | #define ADDRESS_STORE_INSN \ | |
499 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
500 | ||
a4672219 | 501 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
502 | #define CPU_HAS_MIPS16(cpu) \ |
503 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
504 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 505 | |
2309ddf2 | 506 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
507 | #define CPU_HAS_MICROMIPS(cpu) 0 |
508 | ||
60b63b72 RS |
509 | /* True if CPU has a dror instruction. */ |
510 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
511 | ||
512 | /* True if CPU has a ror instruction. */ | |
513 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
514 | ||
dd6a37e7 | 515 | /* True if CPU is in the Octeon family */ |
432233b3 | 516 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 517 | |
dd3cbb7e | 518 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 519 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 520 | |
0aa27725 RS |
521 | /* True, if CPU has support for ldc1 and sdc1. */ |
522 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
523 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
524 | ||
c8978940 CD |
525 | /* True if mflo and mfhi can be immediately followed by instructions |
526 | which write to the HI and LO registers. | |
527 | ||
528 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
529 | (at least) two instructions between the reads of HI/LO and | |
530 | instructions which write them, and later ISAs do not. Contradicting | |
531 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
532 | the UM for the NEC Vr5000) document needing the instructions between | |
533 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
534 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
535 | earlier-ISA CPUs for which CPU documentation declares that the | |
536 | instructions are really interlocked. */ | |
537 | #define hilo_interlocks \ | |
538 | (mips_opts.isa == ISA_MIPS32 \ | |
539 | || mips_opts.isa == ISA_MIPS32R2 \ | |
540 | || mips_opts.isa == ISA_MIPS64 \ | |
541 | || mips_opts.isa == ISA_MIPS64R2 \ | |
542 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 543 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
544 | || mips_opts.arch == CPU_R10000 \ |
545 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
546 | || mips_opts.arch == CPU_R14000 \ |
547 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 548 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 549 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 550 | || mips_opts.micromips \ |
c8978940 | 551 | ) |
252b5132 RH |
552 | |
553 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
554 | from the GPRs after they are loaded from memory, and thus does not |
555 | require nops to be inserted. This applies to instructions marked | |
556 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
557 | level I and microMIPS mode instructions are always interlocked. */ |
558 | #define gpr_interlocks \ | |
559 | (mips_opts.isa != ISA_MIPS1 \ | |
560 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 561 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
562 | || mips_opts.micromips \ |
563 | ) | |
252b5132 | 564 | |
81912461 ILT |
565 | /* Whether the processor uses hardware interlocks to avoid delays |
566 | required by coprocessor instructions, and thus does not require | |
567 | nops to be inserted. This applies to instructions marked | |
568 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
569 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
570 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
571 | levels I, II, and III and microMIPS mode instructions are always |
572 | interlocked. */ | |
bdaaa2e1 | 573 | /* Itbl support may require additional care here. */ |
81912461 ILT |
574 | #define cop_interlocks \ |
575 | ((mips_opts.isa != ISA_MIPS1 \ | |
576 | && mips_opts.isa != ISA_MIPS2 \ | |
577 | && mips_opts.isa != ISA_MIPS3) \ | |
578 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 579 | || mips_opts.micromips \ |
81912461 ILT |
580 | ) |
581 | ||
582 | /* Whether the processor uses hardware interlocks to protect reads | |
583 | from coprocessor registers after they are loaded from memory, and | |
584 | thus does not require nops to be inserted. This applies to | |
585 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
586 | requires at MIPS ISA level I and microMIPS mode instructions are |
587 | always interlocked. */ | |
588 | #define cop_mem_interlocks \ | |
589 | (mips_opts.isa != ISA_MIPS1 \ | |
590 | || mips_opts.micromips \ | |
591 | ) | |
252b5132 | 592 | |
6b76fefe CM |
593 | /* Is this a mfhi or mflo instruction? */ |
594 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
595 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
596 | ||
df58fc94 RS |
597 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
598 | has been selected. This implies, in particular, that addresses of text | |
599 | labels have their LSB set. */ | |
600 | #define HAVE_CODE_COMPRESSION \ | |
601 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
602 | ||
252b5132 RH |
603 | /* MIPS PIC level. */ |
604 | ||
a161fe53 | 605 | enum mips_pic_level mips_pic; |
252b5132 | 606 | |
c9914766 | 607 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 608 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 609 | static int mips_big_got = 0; |
252b5132 RH |
610 | |
611 | /* 1 if trap instructions should used for overflow rather than break | |
612 | instructions. */ | |
c9914766 | 613 | static int mips_trap = 0; |
252b5132 | 614 | |
119d663a | 615 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 616 | by assembling two single width halves into two single width floating |
119d663a NC |
617 | point registers which just happen to alias the double width destination |
618 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 619 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
620 | automatically at assemble time. */ |
621 | static int mips_disable_float_construction; | |
622 | ||
252b5132 RH |
623 | /* Non-zero if any .set noreorder directives were used. */ |
624 | ||
625 | static int mips_any_noreorder; | |
626 | ||
6b76fefe CM |
627 | /* Non-zero if nops should be inserted when the register referenced in |
628 | an mfhi/mflo instruction is read in the next two instructions. */ | |
629 | static int mips_7000_hilo_fix; | |
630 | ||
02ffd3e4 | 631 | /* The size of objects in the small data section. */ |
156c2f8b | 632 | static unsigned int g_switch_value = 8; |
252b5132 RH |
633 | /* Whether the -G option was used. */ |
634 | static int g_switch_seen = 0; | |
635 | ||
636 | #define N_RMASK 0xc4 | |
637 | #define N_VFP 0xd4 | |
638 | ||
639 | /* If we can determine in advance that GP optimization won't be | |
640 | possible, we can skip the relaxation stuff that tries to produce | |
641 | GP-relative references. This makes delay slot optimization work | |
642 | better. | |
643 | ||
644 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
645 | gcc output. It needs to guess right for gcc, otherwise gcc |
646 | will put what it thinks is a GP-relative instruction in a branch | |
647 | delay slot. | |
252b5132 RH |
648 | |
649 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
650 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 651 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
652 | |
653 | /* handle of the OPCODE hash table */ | |
654 | static struct hash_control *op_hash = NULL; | |
655 | ||
656 | /* The opcode hash table we use for the mips16. */ | |
657 | static struct hash_control *mips16_op_hash = NULL; | |
658 | ||
df58fc94 RS |
659 | /* The opcode hash table we use for the microMIPS ASE. */ |
660 | static struct hash_control *micromips_op_hash = NULL; | |
661 | ||
252b5132 RH |
662 | /* This array holds the chars that always start a comment. If the |
663 | pre-processor is disabled, these aren't very useful */ | |
664 | const char comment_chars[] = "#"; | |
665 | ||
666 | /* This array holds the chars that only start a comment at the beginning of | |
667 | a line. If the line seems to have the form '# 123 filename' | |
668 | .line and .file directives will appear in the pre-processed output */ | |
669 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
670 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 671 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
672 | /* Also note that C style comments are always supported. */ |
673 | const char line_comment_chars[] = "#"; | |
674 | ||
bdaaa2e1 | 675 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 676 | const char line_separator_chars[] = ";"; |
252b5132 RH |
677 | |
678 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
679 | const char EXP_CHARS[] = "eE"; | |
680 | ||
681 | /* Chars that mean this number is a floating point constant */ | |
682 | /* As in 0f12.456 */ | |
683 | /* or 0d1.2345e12 */ | |
684 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
685 | ||
686 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
687 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
688 | but nothing is ideal around here. | |
689 | */ | |
690 | ||
691 | static char *insn_error; | |
692 | ||
693 | static int auto_align = 1; | |
694 | ||
695 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
696 | offset in the stack frame from which to restore the $gp register. | |
697 | This is set by the .cprestore pseudo-op, and saved in this | |
698 | variable. */ | |
699 | static offsetT mips_cprestore_offset = -1; | |
700 | ||
67c1ffbe | 701 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 702 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 703 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
704 | static offsetT mips_cpreturn_offset = -1; |
705 | static int mips_cpreturn_register = -1; | |
706 | static int mips_gp_register = GP; | |
def2e0dd | 707 | static int mips_gprel_offset = 0; |
6478892d | 708 | |
7a621144 DJ |
709 | /* Whether mips_cprestore_offset has been set in the current function |
710 | (or whether it has already been warned about, if not). */ | |
711 | static int mips_cprestore_valid = 0; | |
712 | ||
252b5132 RH |
713 | /* This is the register which holds the stack frame, as set by the |
714 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
715 | static int mips_frame_reg = SP; | |
716 | ||
7a621144 DJ |
717 | /* Whether mips_frame_reg has been set in the current function |
718 | (or whether it has already been warned about, if not). */ | |
719 | static int mips_frame_reg_valid = 0; | |
720 | ||
252b5132 RH |
721 | /* To output NOP instructions correctly, we need to keep information |
722 | about the previous two instructions. */ | |
723 | ||
724 | /* Whether we are optimizing. The default value of 2 means to remove | |
725 | unneeded NOPs and swap branch instructions when possible. A value | |
726 | of 1 means to not swap branches. A value of 0 means to always | |
727 | insert NOPs. */ | |
728 | static int mips_optimize = 2; | |
729 | ||
730 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
731 | equivalent to seeing no -g option at all. */ | |
732 | static int mips_debug = 0; | |
733 | ||
7d8e00cf RS |
734 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
735 | #define MAX_VR4130_NOPS 4 | |
736 | ||
737 | /* The maximum number of NOPs needed to fill delay slots. */ | |
738 | #define MAX_DELAY_NOPS 2 | |
739 | ||
740 | /* The maximum number of NOPs needed for any purpose. */ | |
741 | #define MAX_NOPS 4 | |
71400594 RS |
742 | |
743 | /* A list of previous instructions, with index 0 being the most recent. | |
744 | We need to look back MAX_NOPS instructions when filling delay slots | |
745 | or working around processor errata. We need to look back one | |
746 | instruction further if we're thinking about using history[0] to | |
747 | fill a branch delay slot. */ | |
748 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 749 | |
1e915849 | 750 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
751 | static struct mips_cl_insn nop_insn; |
752 | static struct mips_cl_insn mips16_nop_insn; | |
753 | static struct mips_cl_insn micromips_nop16_insn; | |
754 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
755 | |
756 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
757 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
758 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
759 | ||
760 | /* The size of NOP_INSN in bytes. */ | |
761 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 762 | |
252b5132 RH |
763 | /* If this is set, it points to a frag holding nop instructions which |
764 | were inserted before the start of a noreorder section. If those | |
765 | nops turn out to be unnecessary, the size of the frag can be | |
766 | decreased. */ | |
767 | static fragS *prev_nop_frag; | |
768 | ||
769 | /* The number of nop instructions we created in prev_nop_frag. */ | |
770 | static int prev_nop_frag_holds; | |
771 | ||
772 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 773 | prev_nop_frag. */ |
252b5132 RH |
774 | static int prev_nop_frag_required; |
775 | ||
776 | /* The number of instructions we've seen since prev_nop_frag. */ | |
777 | static int prev_nop_frag_since; | |
778 | ||
779 | /* For ECOFF and ELF, relocations against symbols are done in two | |
780 | parts, with a HI relocation and a LO relocation. Each relocation | |
781 | has only 16 bits of space to store an addend. This means that in | |
782 | order for the linker to handle carries correctly, it must be able | |
783 | to locate both the HI and the LO relocation. This means that the | |
784 | relocations must appear in order in the relocation table. | |
785 | ||
786 | In order to implement this, we keep track of each unmatched HI | |
787 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 788 | corresponding LO relocation. */ |
252b5132 | 789 | |
e972090a NC |
790 | struct mips_hi_fixup |
791 | { | |
252b5132 RH |
792 | /* Next HI fixup. */ |
793 | struct mips_hi_fixup *next; | |
794 | /* This fixup. */ | |
795 | fixS *fixp; | |
796 | /* The section this fixup is in. */ | |
797 | segT seg; | |
798 | }; | |
799 | ||
800 | /* The list of unmatched HI relocs. */ | |
801 | ||
802 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
803 | ||
64bdfcaf RS |
804 | /* The frag containing the last explicit relocation operator. |
805 | Null if explicit relocations have not been used. */ | |
806 | ||
807 | static fragS *prev_reloc_op_frag; | |
808 | ||
252b5132 RH |
809 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
810 | ||
811 | #define X ILLEGAL_REG | |
e972090a NC |
812 | static const int mips32_to_16_reg_map[] = |
813 | { | |
252b5132 RH |
814 | X, X, 2, 3, 4, 5, 6, 7, |
815 | X, X, X, X, X, X, X, X, | |
816 | 0, 1, X, X, X, X, X, X, | |
817 | X, X, X, X, X, X, X, X | |
818 | }; | |
819 | #undef X | |
820 | ||
821 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
822 | ||
e972090a NC |
823 | static const unsigned int mips16_to_32_reg_map[] = |
824 | { | |
252b5132 RH |
825 | 16, 17, 2, 3, 4, 5, 6, 7 |
826 | }; | |
60b63b72 | 827 | |
df58fc94 RS |
828 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
829 | ||
830 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
831 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
832 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
833 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
834 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
835 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
836 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
837 | ||
838 | #define X ILLEGAL_REG | |
839 | /* reg type h: 4, 5, 6. */ | |
840 | static const int mips32_to_micromips_reg_h_map[] = | |
841 | { | |
842 | X, X, X, X, 4, 5, 6, X, | |
843 | X, X, X, X, X, X, X, X, | |
844 | X, X, X, X, X, X, X, X, | |
845 | X, X, X, X, X, X, X, X | |
846 | }; | |
847 | ||
848 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
849 | static const int mips32_to_micromips_reg_m_map[] = | |
850 | { | |
851 | 0, X, 2, 3, X, X, X, X, | |
852 | X, X, X, X, X, X, X, X, | |
853 | 4, 1, 5, 6, 7, X, X, X, | |
854 | X, X, X, X, X, X, X, X | |
855 | }; | |
856 | ||
857 | /* reg type q: 0, 2-7. 17. */ | |
858 | static const int mips32_to_micromips_reg_q_map[] = | |
859 | { | |
860 | 0, X, 2, 3, 4, 5, 6, 7, | |
861 | X, X, X, X, X, X, X, X, | |
862 | X, 1, X, X, X, X, X, X, | |
863 | X, X, X, X, X, X, X, X | |
864 | }; | |
865 | ||
866 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
867 | #undef X | |
868 | ||
869 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
870 | ||
871 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
872 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
873 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
874 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
875 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
876 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
877 | ||
878 | /* The microMIPS registers with type h. */ | |
879 | static const unsigned int micromips_to_32_reg_h_map[] = | |
880 | { | |
881 | 5, 5, 6, 4, 4, 4, 4, 4 | |
882 | }; | |
883 | ||
884 | /* The microMIPS registers with type i. */ | |
885 | static const unsigned int micromips_to_32_reg_i_map[] = | |
886 | { | |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
890 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
891 | ||
892 | /* The microMIPS registers with type m. */ | |
893 | static const unsigned int micromips_to_32_reg_m_map[] = | |
894 | { | |
895 | 0, 17, 2, 3, 16, 18, 19, 20 | |
896 | }; | |
897 | ||
898 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
899 | ||
900 | /* The microMIPS registers with type q. */ | |
901 | static const unsigned int micromips_to_32_reg_q_map[] = | |
902 | { | |
903 | 0, 17, 2, 3, 4, 5, 6, 7 | |
904 | }; | |
905 | ||
906 | /* microMIPS imm type B. */ | |
907 | static const int micromips_imm_b_map[] = | |
908 | { | |
909 | 1, 4, 8, 12, 16, 20, 24, -1 | |
910 | }; | |
911 | ||
912 | /* microMIPS imm type C. */ | |
913 | static const int micromips_imm_c_map[] = | |
914 | { | |
915 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
916 | }; | |
917 | ||
71400594 RS |
918 | /* Classifies the kind of instructions we're interested in when |
919 | implementing -mfix-vr4120. */ | |
c67a084a NC |
920 | enum fix_vr4120_class |
921 | { | |
71400594 RS |
922 | FIX_VR4120_MACC, |
923 | FIX_VR4120_DMACC, | |
924 | FIX_VR4120_MULT, | |
925 | FIX_VR4120_DMULT, | |
926 | FIX_VR4120_DIV, | |
927 | FIX_VR4120_MTHILO, | |
928 | NUM_FIX_VR4120_CLASSES | |
929 | }; | |
930 | ||
c67a084a NC |
931 | /* ...likewise -mfix-loongson2f-jump. */ |
932 | static bfd_boolean mips_fix_loongson2f_jump; | |
933 | ||
934 | /* ...likewise -mfix-loongson2f-nop. */ | |
935 | static bfd_boolean mips_fix_loongson2f_nop; | |
936 | ||
937 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
938 | static bfd_boolean mips_fix_loongson2f; | |
939 | ||
71400594 RS |
940 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
941 | there must be at least one other instruction between an instruction | |
942 | of type X and an instruction of type Y. */ | |
943 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
944 | ||
945 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 946 | static int mips_fix_vr4120; |
4a6a3df4 | 947 | |
7d8e00cf RS |
948 | /* ...likewise -mfix-vr4130. */ |
949 | static int mips_fix_vr4130; | |
950 | ||
6a32d874 CM |
951 | /* ...likewise -mfix-24k. */ |
952 | static int mips_fix_24k; | |
953 | ||
d954098f DD |
954 | /* ...likewise -mfix-cn63xxp1 */ |
955 | static bfd_boolean mips_fix_cn63xxp1; | |
956 | ||
4a6a3df4 AO |
957 | /* We don't relax branches by default, since this causes us to expand |
958 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
959 | fail to compute the offset before expanding the macro to the most | |
960 | efficient expansion. */ | |
961 | ||
962 | static int mips_relax_branch; | |
252b5132 | 963 | \f |
4d7206a2 RS |
964 | /* The expansion of many macros depends on the type of symbol that |
965 | they refer to. For example, when generating position-dependent code, | |
966 | a macro that refers to a symbol may have two different expansions, | |
967 | one which uses GP-relative addresses and one which uses absolute | |
968 | addresses. When generating SVR4-style PIC, a macro may have | |
969 | different expansions for local and global symbols. | |
970 | ||
971 | We handle these situations by generating both sequences and putting | |
972 | them in variant frags. In position-dependent code, the first sequence | |
973 | will be the GP-relative one and the second sequence will be the | |
974 | absolute one. In SVR4 PIC, the first sequence will be for global | |
975 | symbols and the second will be for local symbols. | |
976 | ||
584892a6 RS |
977 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
978 | SECOND are the lengths of the two sequences in bytes. These fields | |
979 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
980 | the subtype has the following flags: | |
4d7206a2 | 981 | |
584892a6 RS |
982 | RELAX_USE_SECOND |
983 | Set if it has been decided that we should use the second | |
984 | sequence instead of the first. | |
985 | ||
986 | RELAX_SECOND_LONGER | |
987 | Set in the first variant frag if the macro's second implementation | |
988 | is longer than its first. This refers to the macro as a whole, | |
989 | not an individual relaxation. | |
990 | ||
991 | RELAX_NOMACRO | |
992 | Set in the first variant frag if the macro appeared in a .set nomacro | |
993 | block and if one alternative requires a warning but the other does not. | |
994 | ||
995 | RELAX_DELAY_SLOT | |
996 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
997 | delay slot. | |
4d7206a2 | 998 | |
df58fc94 RS |
999 | RELAX_DELAY_SLOT_16BIT |
1000 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
1001 | 16-bit instruction. | |
1002 | ||
1003 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1004 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1005 | the macro is of the wrong size for the branch delay slot. | |
1006 | ||
1007 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1008 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1009 | the macro is of the wrong size for the branch delay slot. | |
1010 | ||
4d7206a2 RS |
1011 | The frag's "opcode" points to the first fixup for relaxable code. |
1012 | ||
1013 | Relaxable macros are generated using a sequence such as: | |
1014 | ||
1015 | relax_start (SYMBOL); | |
1016 | ... generate first expansion ... | |
1017 | relax_switch (); | |
1018 | ... generate second expansion ... | |
1019 | relax_end (); | |
1020 | ||
1021 | The code and fixups for the unwanted alternative are discarded | |
1022 | by md_convert_frag. */ | |
584892a6 | 1023 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1024 | |
584892a6 RS |
1025 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1026 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1027 | #define RELAX_USE_SECOND 0x10000 | |
1028 | #define RELAX_SECOND_LONGER 0x20000 | |
1029 | #define RELAX_NOMACRO 0x40000 | |
1030 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1031 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1032 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1033 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1034 | |
4a6a3df4 AO |
1035 | /* Branch without likely bit. If label is out of range, we turn: |
1036 | ||
1037 | beq reg1, reg2, label | |
1038 | delay slot | |
1039 | ||
1040 | into | |
1041 | ||
1042 | bne reg1, reg2, 0f | |
1043 | nop | |
1044 | j label | |
1045 | 0: delay slot | |
1046 | ||
1047 | with the following opcode replacements: | |
1048 | ||
1049 | beq <-> bne | |
1050 | blez <-> bgtz | |
1051 | bltz <-> bgez | |
1052 | bc1f <-> bc1t | |
1053 | ||
1054 | bltzal <-> bgezal (with jal label instead of j label) | |
1055 | ||
1056 | Even though keeping the delay slot instruction in the delay slot of | |
1057 | the branch would be more efficient, it would be very tricky to do | |
1058 | correctly, because we'd have to introduce a variable frag *after* | |
1059 | the delay slot instruction, and expand that instead. Let's do it | |
1060 | the easy way for now, even if the branch-not-taken case now costs | |
1061 | one additional instruction. Out-of-range branches are not supposed | |
1062 | to be common, anyway. | |
1063 | ||
1064 | Branch likely. If label is out of range, we turn: | |
1065 | ||
1066 | beql reg1, reg2, label | |
1067 | delay slot (annulled if branch not taken) | |
1068 | ||
1069 | into | |
1070 | ||
1071 | beql reg1, reg2, 1f | |
1072 | nop | |
1073 | beql $0, $0, 2f | |
1074 | nop | |
1075 | 1: j[al] label | |
1076 | delay slot (executed only if branch taken) | |
1077 | 2: | |
1078 | ||
1079 | It would be possible to generate a shorter sequence by losing the | |
1080 | likely bit, generating something like: | |
b34976b6 | 1081 | |
4a6a3df4 AO |
1082 | bne reg1, reg2, 0f |
1083 | nop | |
1084 | j[al] label | |
1085 | delay slot (executed only if branch taken) | |
1086 | 0: | |
1087 | ||
1088 | beql -> bne | |
1089 | bnel -> beq | |
1090 | blezl -> bgtz | |
1091 | bgtzl -> blez | |
1092 | bltzl -> bgez | |
1093 | bgezl -> bltz | |
1094 | bc1fl -> bc1t | |
1095 | bc1tl -> bc1f | |
1096 | ||
1097 | bltzall -> bgezal (with jal label instead of j label) | |
1098 | bgezall -> bltzal (ditto) | |
1099 | ||
1100 | ||
1101 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1102 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1103 | ((relax_substateT) \ | |
1104 | (0xc0000000 \ | |
1105 | | ((at) & 0x1f) \ | |
1106 | | ((toofar) ? 0x20 : 0) \ | |
1107 | | ((link) ? 0x40 : 0) \ | |
1108 | | ((likely) ? 0x80 : 0) \ | |
1109 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1110 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1111 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1112 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1113 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1114 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1115 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1116 | |
252b5132 RH |
1117 | /* For mips16 code, we use an entirely different form of relaxation. |
1118 | mips16 supports two versions of most instructions which take | |
1119 | immediate values: a small one which takes some small value, and a | |
1120 | larger one which takes a 16 bit value. Since branches also follow | |
1121 | this pattern, relaxing these values is required. | |
1122 | ||
1123 | We can assemble both mips16 and normal MIPS code in a single | |
1124 | object. Therefore, we need to support this type of relaxation at | |
1125 | the same time that we support the relaxation described above. We | |
1126 | use the high bit of the subtype field to distinguish these cases. | |
1127 | ||
1128 | The information we store for this type of relaxation is the | |
1129 | argument code found in the opcode file for this relocation, whether | |
1130 | the user explicitly requested a small or extended form, and whether | |
1131 | the relocation is in a jump or jal delay slot. That tells us the | |
1132 | size of the value, and how it should be stored. We also store | |
1133 | whether the fragment is considered to be extended or not. We also | |
1134 | store whether this is known to be a branch to a different section, | |
1135 | whether we have tried to relax this frag yet, and whether we have | |
1136 | ever extended a PC relative fragment because of a shift count. */ | |
1137 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1138 | (0x80000000 \ | |
1139 | | ((type) & 0xff) \ | |
1140 | | ((small) ? 0x100 : 0) \ | |
1141 | | ((ext) ? 0x200 : 0) \ | |
1142 | | ((dslot) ? 0x400 : 0) \ | |
1143 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1144 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1145 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1146 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1147 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1148 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1149 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1150 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1151 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1152 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1153 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1154 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1155 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1156 | |
df58fc94 RS |
1157 | /* For microMIPS code, we use relaxation similar to one we use for |
1158 | MIPS16 code. Some instructions that take immediate values support | |
1159 | two encodings: a small one which takes some small value, and a | |
1160 | larger one which takes a 16 bit value. As some branches also follow | |
1161 | this pattern, relaxing these values is required. | |
1162 | ||
1163 | We can assemble both microMIPS and normal MIPS code in a single | |
1164 | object. Therefore, we need to support this type of relaxation at | |
1165 | the same time that we support the relaxation described above. We | |
1166 | use one of the high bits of the subtype field to distinguish these | |
1167 | cases. | |
1168 | ||
1169 | The information we store for this type of relaxation is the argument | |
1170 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1171 | selected as the assembler temporary, whether the branch is |
1172 | unconditional, whether it is compact, whether it stores the link | |
1173 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1174 | branches to a sequence of instructions is enabled, and whether the | |
1175 | displacement of a branch is too large to fit as an immediate argument | |
1176 | of a 16-bit and a 32-bit branch, respectively. */ | |
1177 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1178 | relax32, toofar16, toofar32) \ | |
1179 | (0x40000000 \ | |
1180 | | ((type) & 0xff) \ | |
1181 | | (((at) & 0x1f) << 8) \ | |
1182 | | ((uncond) ? 0x2000 : 0) \ | |
1183 | | ((compact) ? 0x4000 : 0) \ | |
1184 | | ((link) ? 0x8000 : 0) \ | |
1185 | | ((relax32) ? 0x10000 : 0) \ | |
1186 | | ((toofar16) ? 0x20000 : 0) \ | |
1187 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1188 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1189 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1190 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1191 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1192 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1193 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1194 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1195 | ||
1196 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1197 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1198 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1199 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1200 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1201 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1202 | |
43c0598f RS |
1203 | /* Sign-extend 16-bit value X. */ |
1204 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1205 | ||
885add95 CD |
1206 | /* Is the given value a sign-extended 32-bit value? */ |
1207 | #define IS_SEXT_32BIT_NUM(x) \ | |
1208 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1209 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1210 | ||
1211 | /* Is the given value a sign-extended 16-bit value? */ | |
1212 | #define IS_SEXT_16BIT_NUM(x) \ | |
1213 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1214 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1215 | ||
df58fc94 RS |
1216 | /* Is the given value a sign-extended 12-bit value? */ |
1217 | #define IS_SEXT_12BIT_NUM(x) \ | |
1218 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1219 | ||
2051e8c4 MR |
1220 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1221 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1222 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1223 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1224 | ||
bf12938e RS |
1225 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1226 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1227 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1228 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1229 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1230 | ||
1231 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1232 | SHIFT places. */ | |
1233 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1234 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1235 | ||
1236 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1237 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1238 | ||
1239 | include/opcode/mips.h specifies operand fields using the macros | |
1240 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1241 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1242 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1243 | do \ | |
1244 | if (!(MICROMIPS)) \ | |
1245 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1246 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1247 | else \ | |
1248 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1249 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1250 | while (0) | |
bf12938e RS |
1251 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1252 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1253 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1254 | ||
1255 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1256 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1257 | (!(MICROMIPS) \ | |
1258 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1259 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1260 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1261 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1262 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1263 | MIPS16OP_MASK_##FIELD, \ | |
1264 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1265 | |
1266 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1267 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1268 | \f |
df58fc94 RS |
1269 | /* Whether or not we are emitting a branch-likely macro. */ |
1270 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1271 | ||
4d7206a2 RS |
1272 | /* Global variables used when generating relaxable macros. See the |
1273 | comment above RELAX_ENCODE for more details about how relaxation | |
1274 | is used. */ | |
1275 | static struct { | |
1276 | /* 0 if we're not emitting a relaxable macro. | |
1277 | 1 if we're emitting the first of the two relaxation alternatives. | |
1278 | 2 if we're emitting the second alternative. */ | |
1279 | int sequence; | |
1280 | ||
1281 | /* The first relaxable fixup in the current frag. (In other words, | |
1282 | the first fixup that refers to relaxable code.) */ | |
1283 | fixS *first_fixup; | |
1284 | ||
1285 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1286 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1287 | unsigned int sizes[2]; | |
1288 | ||
1289 | /* The symbol on which the choice of sequence depends. */ | |
1290 | symbolS *symbol; | |
1291 | } mips_relax; | |
252b5132 | 1292 | \f |
584892a6 RS |
1293 | /* Global variables used to decide whether a macro needs a warning. */ |
1294 | static struct { | |
1295 | /* True if the macro is in a branch delay slot. */ | |
1296 | bfd_boolean delay_slot_p; | |
1297 | ||
df58fc94 RS |
1298 | /* Set to the length in bytes required if the macro is in a delay slot |
1299 | that requires a specific length of instruction, otherwise zero. */ | |
1300 | unsigned int delay_slot_length; | |
1301 | ||
584892a6 RS |
1302 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1303 | in bytes and sizes[1] is the length of the second alternative. | |
1304 | For non-relaxable macros, both elements give the length of the | |
1305 | macro in bytes. */ | |
1306 | unsigned int sizes[2]; | |
1307 | ||
df58fc94 RS |
1308 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1309 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1310 | is the length of the first instruction of the second alternative. | |
1311 | For non-relaxable macros, both elements give the length of the first | |
1312 | instruction in bytes. | |
1313 | ||
1314 | Set to zero if we haven't yet seen the first instruction. */ | |
1315 | unsigned int first_insn_sizes[2]; | |
1316 | ||
1317 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1318 | first alternative and insns[1] is the number of instructions for the | |
1319 | second alternative. | |
1320 | ||
1321 | For non-relaxable macros, both elements give the number of | |
1322 | instructions for the macro. */ | |
1323 | unsigned int insns[2]; | |
1324 | ||
584892a6 RS |
1325 | /* The first variant frag for this macro. */ |
1326 | fragS *first_frag; | |
1327 | } mips_macro_warning; | |
1328 | \f | |
252b5132 RH |
1329 | /* Prototypes for static functions. */ |
1330 | ||
252b5132 RH |
1331 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1332 | ||
b34976b6 | 1333 | static void append_insn |
df58fc94 RS |
1334 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1335 | bfd_boolean expansionp); | |
7d10b47d | 1336 | static void mips_no_prev_insn (void); |
c67a084a | 1337 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1338 | static void mips16_macro_build |
03ea81db | 1339 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1340 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1341 | static void macro_start (void); |
1342 | static void macro_end (void); | |
17a2f251 TS |
1343 | static void macro (struct mips_cl_insn * ip); |
1344 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1345 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1346 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1347 | static void mips16_immed |
43c0598f RS |
1348 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1349 | unsigned int, unsigned long *); | |
5e0116d5 | 1350 | static size_t my_getSmallExpression |
17a2f251 TS |
1351 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1352 | static void my_getExpression (expressionS *, char *); | |
1353 | static void s_align (int); | |
1354 | static void s_change_sec (int); | |
1355 | static void s_change_section (int); | |
1356 | static void s_cons (int); | |
1357 | static void s_float_cons (int); | |
1358 | static void s_mips_globl (int); | |
1359 | static void s_option (int); | |
1360 | static void s_mipsset (int); | |
1361 | static void s_abicalls (int); | |
1362 | static void s_cpload (int); | |
1363 | static void s_cpsetup (int); | |
1364 | static void s_cplocal (int); | |
1365 | static void s_cprestore (int); | |
1366 | static void s_cpreturn (int); | |
741d6ea8 JM |
1367 | static void s_dtprelword (int); |
1368 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1369 | static void s_tprelword (int); |
1370 | static void s_tpreldword (int); | |
17a2f251 TS |
1371 | static void s_gpvalue (int); |
1372 | static void s_gpword (int); | |
1373 | static void s_gpdword (int); | |
a3f278e2 | 1374 | static void s_ehword (int); |
17a2f251 TS |
1375 | static void s_cpadd (int); |
1376 | static void s_insn (int); | |
1377 | static void md_obj_begin (void); | |
1378 | static void md_obj_end (void); | |
1379 | static void s_mips_ent (int); | |
1380 | static void s_mips_end (int); | |
1381 | static void s_mips_frame (int); | |
1382 | static void s_mips_mask (int reg_type); | |
1383 | static void s_mips_stab (int); | |
1384 | static void s_mips_weakext (int); | |
1385 | static void s_mips_file (int); | |
1386 | static void s_mips_loc (int); | |
1387 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1388 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1389 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1390 | static int validate_micromips_insn (const struct mips_opcode *); |
1391 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1392 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1393 | |
1394 | /* Table and functions used to map between CPU/ISA names, and | |
1395 | ISA levels, and CPU numbers. */ | |
1396 | ||
e972090a NC |
1397 | struct mips_cpu_info |
1398 | { | |
e7af610e | 1399 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1400 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1401 | int isa; /* ISA level. */ |
1402 | int cpu; /* CPU number (default CPU if ISA). */ | |
1403 | }; | |
1404 | ||
ad3fea08 TS |
1405 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1406 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1407 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1408 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1409 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1410 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1411 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1412 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
b015e599 | 1413 | #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */ |
ad3fea08 | 1414 | |
17a2f251 TS |
1415 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1416 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1417 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1418 | \f |
1419 | /* Pseudo-op table. | |
1420 | ||
1421 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1422 | should be defined here, but are currently unsupported: .alias, | |
1423 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1424 | ||
1425 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1426 | specific to the type of debugging information being generated, and | |
1427 | should be defined by the object format: .aent, .begin, .bend, | |
1428 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1429 | .vreg. | |
1430 | ||
1431 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1432 | not MIPS CPU specific, but are also not specific to the object file | |
1433 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1434 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1435 | |
e972090a NC |
1436 | static const pseudo_typeS mips_pseudo_table[] = |
1437 | { | |
beae10d5 | 1438 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1439 | {"option", s_option, 0}, |
1440 | {"set", s_mipsset, 0}, | |
1441 | {"rdata", s_change_sec, 'r'}, | |
1442 | {"sdata", s_change_sec, 's'}, | |
1443 | {"livereg", s_ignore, 0}, | |
1444 | {"abicalls", s_abicalls, 0}, | |
1445 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1446 | {"cpsetup", s_cpsetup, 0}, |
1447 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1448 | {"cprestore", s_cprestore, 0}, |
6478892d | 1449 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1450 | {"dtprelword", s_dtprelword, 0}, |
1451 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1452 | {"tprelword", s_tprelword, 0}, |
1453 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1454 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1455 | {"gpword", s_gpword, 0}, |
10181a0d | 1456 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1457 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1458 | {"cpadd", s_cpadd, 0}, |
1459 | {"insn", s_insn, 0}, | |
1460 | ||
beae10d5 | 1461 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1462 | chips. */ |
38a57ae7 | 1463 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1464 | {"bss", s_change_sec, 'b'}, |
1465 | {"err", s_err, 0}, | |
1466 | {"half", s_cons, 1}, | |
1467 | {"dword", s_cons, 3}, | |
1468 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1469 | {"origin", s_org, 0}, |
1470 | {"repeat", s_rept, 0}, | |
252b5132 | 1471 | |
998b3c36 MR |
1472 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1473 | {"sbss", s_change_sec, 'B'}, | |
1474 | ||
beae10d5 | 1475 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1476 | here for one reason or another. */ |
1477 | {"align", s_align, 0}, | |
1478 | {"byte", s_cons, 0}, | |
1479 | {"data", s_change_sec, 'd'}, | |
1480 | {"double", s_float_cons, 'd'}, | |
1481 | {"float", s_float_cons, 'f'}, | |
1482 | {"globl", s_mips_globl, 0}, | |
1483 | {"global", s_mips_globl, 0}, | |
1484 | {"hword", s_cons, 1}, | |
1485 | {"int", s_cons, 2}, | |
1486 | {"long", s_cons, 2}, | |
1487 | {"octa", s_cons, 4}, | |
1488 | {"quad", s_cons, 3}, | |
cca86cc8 | 1489 | {"section", s_change_section, 0}, |
252b5132 RH |
1490 | {"short", s_cons, 1}, |
1491 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1492 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1493 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1494 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1495 | {"text", s_change_sec, 't'}, |
1496 | {"word", s_cons, 2}, | |
add56521 | 1497 | |
add56521 | 1498 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1499 | |
43841e91 | 1500 | { NULL, NULL, 0 }, |
252b5132 RH |
1501 | }; |
1502 | ||
e972090a NC |
1503 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1504 | { | |
beae10d5 KH |
1505 | /* These pseudo-ops should be defined by the object file format. |
1506 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1507 | {"aent", s_mips_ent, 1}, |
1508 | {"bgnb", s_ignore, 0}, | |
1509 | {"end", s_mips_end, 0}, | |
1510 | {"endb", s_ignore, 0}, | |
1511 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1512 | {"file", s_mips_file, 0}, |
252b5132 RH |
1513 | {"fmask", s_mips_mask, 'F'}, |
1514 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1515 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1516 | {"mask", s_mips_mask, 'R'}, |
1517 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1518 | { NULL, NULL, 0 }, |
252b5132 RH |
1519 | }; |
1520 | ||
3ae8dd8d MR |
1521 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1522 | purpose of the `.dc.a' internal pseudo-op. */ | |
1523 | ||
1524 | int | |
1525 | mips_address_bytes (void) | |
1526 | { | |
1527 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1528 | } | |
1529 | ||
17a2f251 | 1530 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1531 | |
1532 | void | |
17a2f251 | 1533 | mips_pop_insert (void) |
252b5132 RH |
1534 | { |
1535 | pop_insert (mips_pseudo_table); | |
1536 | if (! ECOFF_DEBUGGING) | |
1537 | pop_insert (mips_nonecoff_pseudo_table); | |
1538 | } | |
1539 | \f | |
1540 | /* Symbols labelling the current insn. */ | |
1541 | ||
e972090a NC |
1542 | struct insn_label_list |
1543 | { | |
252b5132 RH |
1544 | struct insn_label_list *next; |
1545 | symbolS *label; | |
1546 | }; | |
1547 | ||
252b5132 | 1548 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1549 | #define label_list tc_segment_info_data.labels |
252b5132 | 1550 | |
17a2f251 | 1551 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1552 | static void mips_mark_labels (void); |
1553 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1554 | |
1555 | static inline void | |
17a2f251 | 1556 | mips_clear_insn_labels (void) |
252b5132 RH |
1557 | { |
1558 | register struct insn_label_list **pl; | |
a8dbcb85 | 1559 | segment_info_type *si; |
252b5132 | 1560 | |
a8dbcb85 TS |
1561 | if (now_seg) |
1562 | { | |
1563 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1564 | ; | |
1565 | ||
1566 | si = seg_info (now_seg); | |
1567 | *pl = si->label_list; | |
1568 | si->label_list = NULL; | |
1569 | } | |
252b5132 | 1570 | } |
a8dbcb85 | 1571 | |
df58fc94 RS |
1572 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1573 | ||
1574 | static inline void | |
1575 | mips_mark_labels (void) | |
1576 | { | |
1577 | if (HAVE_CODE_COMPRESSION) | |
1578 | mips_compressed_mark_labels (); | |
1579 | } | |
252b5132 RH |
1580 | \f |
1581 | static char *expr_end; | |
1582 | ||
1583 | /* Expressions which appear in instructions. These are set by | |
1584 | mips_ip. */ | |
1585 | ||
1586 | static expressionS imm_expr; | |
5f74bc13 | 1587 | static expressionS imm2_expr; |
252b5132 RH |
1588 | static expressionS offset_expr; |
1589 | ||
1590 | /* Relocs associated with imm_expr and offset_expr. */ | |
1591 | ||
f6688943 TS |
1592 | static bfd_reloc_code_real_type imm_reloc[3] |
1593 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1594 | static bfd_reloc_code_real_type offset_reloc[3] | |
1595 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1596 | |
df58fc94 RS |
1597 | /* This is set to the resulting size of the instruction to be produced |
1598 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1599 | explicit size is supplied. */ | |
252b5132 | 1600 | |
df58fc94 | 1601 | static unsigned int forced_insn_length; |
252b5132 | 1602 | |
e1b47bd5 RS |
1603 | /* True if we are assembling an instruction. All dot symbols defined during |
1604 | this time should be treated as code labels. */ | |
1605 | ||
1606 | static bfd_boolean mips_assembling_insn; | |
1607 | ||
7ed4a06a | 1608 | #ifdef OBJ_ELF |
ecb4347a DJ |
1609 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1610 | ECOFF debugging. */ | |
252b5132 RH |
1611 | |
1612 | static segT pdr_seg; | |
7ed4a06a | 1613 | #endif |
252b5132 | 1614 | |
e013f690 TS |
1615 | /* The default target format to use. */ |
1616 | ||
aeffff67 RS |
1617 | #if defined (TE_FreeBSD) |
1618 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1619 | #elif defined (TE_TMIPS) | |
1620 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1621 | #else | |
1622 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1623 | #endif | |
1624 | ||
e013f690 | 1625 | const char * |
17a2f251 | 1626 | mips_target_format (void) |
e013f690 TS |
1627 | { |
1628 | switch (OUTPUT_FLAVOR) | |
1629 | { | |
e013f690 TS |
1630 | case bfd_target_ecoff_flavour: |
1631 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1632 | case bfd_target_coff_flavour: | |
1633 | return "pe-mips"; | |
1634 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1635 | #ifdef TE_VXWORKS |
1636 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1637 | return (target_big_endian | |
1638 | ? "elf32-bigmips-vxworks" | |
1639 | : "elf32-littlemips-vxworks"); | |
1640 | #endif | |
e013f690 | 1641 | return (target_big_endian |
cfe86eaa | 1642 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1643 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1644 | : (HAVE_NEWABI |
aeffff67 RS |
1645 | ? ELF_TARGET ("elf32-n", "big") |
1646 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1647 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1648 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1649 | : (HAVE_NEWABI |
aeffff67 RS |
1650 | ? ELF_TARGET ("elf32-n", "little") |
1651 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1652 | default: |
1653 | abort (); | |
1654 | return NULL; | |
1655 | } | |
1656 | } | |
1657 | ||
df58fc94 RS |
1658 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1659 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1660 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1661 | major opcode) will require further modifications to the opcode | |
1662 | table. */ | |
1663 | ||
1664 | static inline unsigned int | |
1665 | micromips_insn_length (const struct mips_opcode *mo) | |
1666 | { | |
1667 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1668 | } | |
1669 | ||
5c04167a RS |
1670 | /* Return the length of MIPS16 instruction OPCODE. */ |
1671 | ||
1672 | static inline unsigned int | |
1673 | mips16_opcode_length (unsigned long opcode) | |
1674 | { | |
1675 | return (opcode >> 16) == 0 ? 2 : 4; | |
1676 | } | |
1677 | ||
1e915849 RS |
1678 | /* Return the length of instruction INSN. */ |
1679 | ||
1680 | static inline unsigned int | |
1681 | insn_length (const struct mips_cl_insn *insn) | |
1682 | { | |
df58fc94 RS |
1683 | if (mips_opts.micromips) |
1684 | return micromips_insn_length (insn->insn_mo); | |
1685 | else if (mips_opts.mips16) | |
5c04167a | 1686 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1687 | else |
1e915849 | 1688 | return 4; |
1e915849 RS |
1689 | } |
1690 | ||
1691 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1692 | ||
1693 | static void | |
1694 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1695 | { | |
1696 | size_t i; | |
1697 | ||
1698 | insn->insn_mo = mo; | |
1e915849 RS |
1699 | insn->insn_opcode = mo->match; |
1700 | insn->frag = NULL; | |
1701 | insn->where = 0; | |
1702 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1703 | insn->fixp[i] = NULL; | |
1704 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1705 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1706 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1707 | insn->complete_p = 0; |
e407c74b | 1708 | insn->cleared_p = 0; |
1e915849 RS |
1709 | } |
1710 | ||
df58fc94 | 1711 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1712 | |
1713 | static void | |
df58fc94 | 1714 | mips_record_compressed_mode (void) |
742a56fe RS |
1715 | { |
1716 | segment_info_type *si; | |
1717 | ||
1718 | si = seg_info (now_seg); | |
1719 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1720 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1721 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1722 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1723 | } |
1724 | ||
4d68580a RS |
1725 | /* Read a standard MIPS instruction from BUF. */ |
1726 | ||
1727 | static unsigned long | |
1728 | read_insn (char *buf) | |
1729 | { | |
1730 | if (target_big_endian) | |
1731 | return bfd_getb32 ((bfd_byte *) buf); | |
1732 | else | |
1733 | return bfd_getl32 ((bfd_byte *) buf); | |
1734 | } | |
1735 | ||
1736 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1737 | the next byte. */ | |
1738 | ||
1739 | static char * | |
1740 | write_insn (char *buf, unsigned int insn) | |
1741 | { | |
1742 | md_number_to_chars (buf, insn, 4); | |
1743 | return buf + 4; | |
1744 | } | |
1745 | ||
1746 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1747 | has length LENGTH. */ | |
1748 | ||
1749 | static unsigned long | |
1750 | read_compressed_insn (char *buf, unsigned int length) | |
1751 | { | |
1752 | unsigned long insn; | |
1753 | unsigned int i; | |
1754 | ||
1755 | insn = 0; | |
1756 | for (i = 0; i < length; i += 2) | |
1757 | { | |
1758 | insn <<= 16; | |
1759 | if (target_big_endian) | |
1760 | insn |= bfd_getb16 ((char *) buf); | |
1761 | else | |
1762 | insn |= bfd_getl16 ((char *) buf); | |
1763 | buf += 2; | |
1764 | } | |
1765 | return insn; | |
1766 | } | |
1767 | ||
5c04167a RS |
1768 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1769 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1770 | ||
1771 | static char * | |
1772 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1773 | { | |
1774 | unsigned int i; | |
1775 | ||
1776 | for (i = 0; i < length; i += 2) | |
1777 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1778 | return buf + length; | |
1779 | } | |
1780 | ||
1e915849 RS |
1781 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1782 | ||
1783 | static void | |
1784 | install_insn (const struct mips_cl_insn *insn) | |
1785 | { | |
1786 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1787 | if (HAVE_CODE_COMPRESSION) |
1788 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1789 | else |
4d68580a | 1790 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1791 | mips_record_compressed_mode (); |
1e915849 RS |
1792 | } |
1793 | ||
1794 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1795 | and install the opcode in the new location. */ | |
1796 | ||
1797 | static void | |
1798 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1799 | { | |
1800 | size_t i; | |
1801 | ||
1802 | insn->frag = frag; | |
1803 | insn->where = where; | |
1804 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1805 | if (insn->fixp[i] != NULL) | |
1806 | { | |
1807 | insn->fixp[i]->fx_frag = frag; | |
1808 | insn->fixp[i]->fx_where = where; | |
1809 | } | |
1810 | install_insn (insn); | |
1811 | } | |
1812 | ||
1813 | /* Add INSN to the end of the output. */ | |
1814 | ||
1815 | static void | |
1816 | add_fixed_insn (struct mips_cl_insn *insn) | |
1817 | { | |
1818 | char *f = frag_more (insn_length (insn)); | |
1819 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1820 | } | |
1821 | ||
1822 | /* Start a variant frag and move INSN to the start of the variant part, | |
1823 | marking it as fixed. The other arguments are as for frag_var. */ | |
1824 | ||
1825 | static void | |
1826 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1827 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1828 | { | |
1829 | frag_grow (max_chars); | |
1830 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1831 | insn->fixed_p = 1; | |
1832 | frag_var (rs_machine_dependent, max_chars, var, | |
1833 | subtype, symbol, offset, NULL); | |
1834 | } | |
1835 | ||
1836 | /* Insert N copies of INSN into the history buffer, starting at | |
1837 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1838 | ||
1839 | static void | |
1840 | insert_into_history (unsigned int first, unsigned int n, | |
1841 | const struct mips_cl_insn *insn) | |
1842 | { | |
1843 | if (mips_relax.sequence != 2) | |
1844 | { | |
1845 | unsigned int i; | |
1846 | ||
1847 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1848 | if (i >= first + n) | |
1849 | history[i] = history[i - n]; | |
1850 | else | |
1851 | history[i] = *insn; | |
1852 | } | |
1853 | } | |
1854 | ||
71400594 RS |
1855 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1856 | the idea is to make it obvious at a glance that each errata is | |
1857 | included. */ | |
1858 | ||
1859 | static void | |
1860 | init_vr4120_conflicts (void) | |
1861 | { | |
1862 | #define CONFLICT(FIRST, SECOND) \ | |
1863 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1864 | ||
1865 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1866 | CONFLICT (MACC, DIV); | |
1867 | CONFLICT (DMACC, DIV); | |
1868 | ||
1869 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1870 | CONFLICT (DMULT, DMULT); | |
1871 | CONFLICT (DMULT, DMACC); | |
1872 | CONFLICT (DMACC, DMULT); | |
1873 | CONFLICT (DMACC, DMACC); | |
1874 | ||
1875 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1876 | CONFLICT (MACC, MTHILO); | |
1877 | CONFLICT (DMACC, MTHILO); | |
1878 | ||
1879 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1880 | instruction is executed immediately after a MACC or DMACC | |
1881 | instruction, the result of [either instruction] is incorrect." */ | |
1882 | CONFLICT (MACC, MULT); | |
1883 | CONFLICT (MACC, DMULT); | |
1884 | CONFLICT (DMACC, MULT); | |
1885 | CONFLICT (DMACC, DMULT); | |
1886 | ||
1887 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1888 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1889 | DDIV or DDIVU instruction, the result of the MACC or | |
1890 | DMACC instruction is incorrect.". */ | |
1891 | CONFLICT (DMULT, MACC); | |
1892 | CONFLICT (DMULT, DMACC); | |
1893 | CONFLICT (DIV, MACC); | |
1894 | CONFLICT (DIV, DMACC); | |
1895 | ||
1896 | #undef CONFLICT | |
1897 | } | |
1898 | ||
707bfff6 TS |
1899 | struct regname { |
1900 | const char *name; | |
1901 | unsigned int num; | |
1902 | }; | |
1903 | ||
1904 | #define RTYPE_MASK 0x1ff00 | |
1905 | #define RTYPE_NUM 0x00100 | |
1906 | #define RTYPE_FPU 0x00200 | |
1907 | #define RTYPE_FCC 0x00400 | |
1908 | #define RTYPE_VEC 0x00800 | |
1909 | #define RTYPE_GP 0x01000 | |
1910 | #define RTYPE_CP0 0x02000 | |
1911 | #define RTYPE_PC 0x04000 | |
1912 | #define RTYPE_ACC 0x08000 | |
1913 | #define RTYPE_CCC 0x10000 | |
1914 | #define RNUM_MASK 0x000ff | |
1915 | #define RWARN 0x80000 | |
1916 | ||
1917 | #define GENERIC_REGISTER_NUMBERS \ | |
1918 | {"$0", RTYPE_NUM | 0}, \ | |
1919 | {"$1", RTYPE_NUM | 1}, \ | |
1920 | {"$2", RTYPE_NUM | 2}, \ | |
1921 | {"$3", RTYPE_NUM | 3}, \ | |
1922 | {"$4", RTYPE_NUM | 4}, \ | |
1923 | {"$5", RTYPE_NUM | 5}, \ | |
1924 | {"$6", RTYPE_NUM | 6}, \ | |
1925 | {"$7", RTYPE_NUM | 7}, \ | |
1926 | {"$8", RTYPE_NUM | 8}, \ | |
1927 | {"$9", RTYPE_NUM | 9}, \ | |
1928 | {"$10", RTYPE_NUM | 10}, \ | |
1929 | {"$11", RTYPE_NUM | 11}, \ | |
1930 | {"$12", RTYPE_NUM | 12}, \ | |
1931 | {"$13", RTYPE_NUM | 13}, \ | |
1932 | {"$14", RTYPE_NUM | 14}, \ | |
1933 | {"$15", RTYPE_NUM | 15}, \ | |
1934 | {"$16", RTYPE_NUM | 16}, \ | |
1935 | {"$17", RTYPE_NUM | 17}, \ | |
1936 | {"$18", RTYPE_NUM | 18}, \ | |
1937 | {"$19", RTYPE_NUM | 19}, \ | |
1938 | {"$20", RTYPE_NUM | 20}, \ | |
1939 | {"$21", RTYPE_NUM | 21}, \ | |
1940 | {"$22", RTYPE_NUM | 22}, \ | |
1941 | {"$23", RTYPE_NUM | 23}, \ | |
1942 | {"$24", RTYPE_NUM | 24}, \ | |
1943 | {"$25", RTYPE_NUM | 25}, \ | |
1944 | {"$26", RTYPE_NUM | 26}, \ | |
1945 | {"$27", RTYPE_NUM | 27}, \ | |
1946 | {"$28", RTYPE_NUM | 28}, \ | |
1947 | {"$29", RTYPE_NUM | 29}, \ | |
1948 | {"$30", RTYPE_NUM | 30}, \ | |
1949 | {"$31", RTYPE_NUM | 31} | |
1950 | ||
1951 | #define FPU_REGISTER_NAMES \ | |
1952 | {"$f0", RTYPE_FPU | 0}, \ | |
1953 | {"$f1", RTYPE_FPU | 1}, \ | |
1954 | {"$f2", RTYPE_FPU | 2}, \ | |
1955 | {"$f3", RTYPE_FPU | 3}, \ | |
1956 | {"$f4", RTYPE_FPU | 4}, \ | |
1957 | {"$f5", RTYPE_FPU | 5}, \ | |
1958 | {"$f6", RTYPE_FPU | 6}, \ | |
1959 | {"$f7", RTYPE_FPU | 7}, \ | |
1960 | {"$f8", RTYPE_FPU | 8}, \ | |
1961 | {"$f9", RTYPE_FPU | 9}, \ | |
1962 | {"$f10", RTYPE_FPU | 10}, \ | |
1963 | {"$f11", RTYPE_FPU | 11}, \ | |
1964 | {"$f12", RTYPE_FPU | 12}, \ | |
1965 | {"$f13", RTYPE_FPU | 13}, \ | |
1966 | {"$f14", RTYPE_FPU | 14}, \ | |
1967 | {"$f15", RTYPE_FPU | 15}, \ | |
1968 | {"$f16", RTYPE_FPU | 16}, \ | |
1969 | {"$f17", RTYPE_FPU | 17}, \ | |
1970 | {"$f18", RTYPE_FPU | 18}, \ | |
1971 | {"$f19", RTYPE_FPU | 19}, \ | |
1972 | {"$f20", RTYPE_FPU | 20}, \ | |
1973 | {"$f21", RTYPE_FPU | 21}, \ | |
1974 | {"$f22", RTYPE_FPU | 22}, \ | |
1975 | {"$f23", RTYPE_FPU | 23}, \ | |
1976 | {"$f24", RTYPE_FPU | 24}, \ | |
1977 | {"$f25", RTYPE_FPU | 25}, \ | |
1978 | {"$f26", RTYPE_FPU | 26}, \ | |
1979 | {"$f27", RTYPE_FPU | 27}, \ | |
1980 | {"$f28", RTYPE_FPU | 28}, \ | |
1981 | {"$f29", RTYPE_FPU | 29}, \ | |
1982 | {"$f30", RTYPE_FPU | 30}, \ | |
1983 | {"$f31", RTYPE_FPU | 31} | |
1984 | ||
1985 | #define FPU_CONDITION_CODE_NAMES \ | |
1986 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1987 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1988 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1989 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1990 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1991 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1992 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1993 | {"$fcc7", RTYPE_FCC | 7} | |
1994 | ||
1995 | #define COPROC_CONDITION_CODE_NAMES \ | |
1996 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1997 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1998 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1999 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2000 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2001 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2002 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2003 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2004 | ||
2005 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2006 | {"$a4", RTYPE_GP | 8}, \ | |
2007 | {"$a5", RTYPE_GP | 9}, \ | |
2008 | {"$a6", RTYPE_GP | 10}, \ | |
2009 | {"$a7", RTYPE_GP | 11}, \ | |
2010 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2011 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2012 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2013 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2014 | {"$t0", RTYPE_GP | 12}, \ | |
2015 | {"$t1", RTYPE_GP | 13}, \ | |
2016 | {"$t2", RTYPE_GP | 14}, \ | |
2017 | {"$t3", RTYPE_GP | 15} | |
2018 | ||
2019 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2020 | {"$t0", RTYPE_GP | 8}, \ | |
2021 | {"$t1", RTYPE_GP | 9}, \ | |
2022 | {"$t2", RTYPE_GP | 10}, \ | |
2023 | {"$t3", RTYPE_GP | 11}, \ | |
2024 | {"$t4", RTYPE_GP | 12}, \ | |
2025 | {"$t5", RTYPE_GP | 13}, \ | |
2026 | {"$t6", RTYPE_GP | 14}, \ | |
2027 | {"$t7", RTYPE_GP | 15}, \ | |
2028 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2029 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2030 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2031 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2032 | ||
2033 | /* Remaining symbolic register names */ | |
2034 | #define SYMBOLIC_REGISTER_NAMES \ | |
2035 | {"$zero", RTYPE_GP | 0}, \ | |
2036 | {"$at", RTYPE_GP | 1}, \ | |
2037 | {"$AT", RTYPE_GP | 1}, \ | |
2038 | {"$v0", RTYPE_GP | 2}, \ | |
2039 | {"$v1", RTYPE_GP | 3}, \ | |
2040 | {"$a0", RTYPE_GP | 4}, \ | |
2041 | {"$a1", RTYPE_GP | 5}, \ | |
2042 | {"$a2", RTYPE_GP | 6}, \ | |
2043 | {"$a3", RTYPE_GP | 7}, \ | |
2044 | {"$s0", RTYPE_GP | 16}, \ | |
2045 | {"$s1", RTYPE_GP | 17}, \ | |
2046 | {"$s2", RTYPE_GP | 18}, \ | |
2047 | {"$s3", RTYPE_GP | 19}, \ | |
2048 | {"$s4", RTYPE_GP | 20}, \ | |
2049 | {"$s5", RTYPE_GP | 21}, \ | |
2050 | {"$s6", RTYPE_GP | 22}, \ | |
2051 | {"$s7", RTYPE_GP | 23}, \ | |
2052 | {"$t8", RTYPE_GP | 24}, \ | |
2053 | {"$t9", RTYPE_GP | 25}, \ | |
2054 | {"$k0", RTYPE_GP | 26}, \ | |
2055 | {"$kt0", RTYPE_GP | 26}, \ | |
2056 | {"$k1", RTYPE_GP | 27}, \ | |
2057 | {"$kt1", RTYPE_GP | 27}, \ | |
2058 | {"$gp", RTYPE_GP | 28}, \ | |
2059 | {"$sp", RTYPE_GP | 29}, \ | |
2060 | {"$s8", RTYPE_GP | 30}, \ | |
2061 | {"$fp", RTYPE_GP | 30}, \ | |
2062 | {"$ra", RTYPE_GP | 31} | |
2063 | ||
2064 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2065 | {"$pc", RTYPE_PC | 0} | |
2066 | ||
2067 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2068 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2069 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2070 | {"$v2", RTYPE_VEC | 2}, \ | |
2071 | {"$v3", RTYPE_VEC | 3}, \ | |
2072 | {"$v4", RTYPE_VEC | 4}, \ | |
2073 | {"$v5", RTYPE_VEC | 5}, \ | |
2074 | {"$v6", RTYPE_VEC | 6}, \ | |
2075 | {"$v7", RTYPE_VEC | 7}, \ | |
2076 | {"$v8", RTYPE_VEC | 8}, \ | |
2077 | {"$v9", RTYPE_VEC | 9}, \ | |
2078 | {"$v10", RTYPE_VEC | 10}, \ | |
2079 | {"$v11", RTYPE_VEC | 11}, \ | |
2080 | {"$v12", RTYPE_VEC | 12}, \ | |
2081 | {"$v13", RTYPE_VEC | 13}, \ | |
2082 | {"$v14", RTYPE_VEC | 14}, \ | |
2083 | {"$v15", RTYPE_VEC | 15}, \ | |
2084 | {"$v16", RTYPE_VEC | 16}, \ | |
2085 | {"$v17", RTYPE_VEC | 17}, \ | |
2086 | {"$v18", RTYPE_VEC | 18}, \ | |
2087 | {"$v19", RTYPE_VEC | 19}, \ | |
2088 | {"$v20", RTYPE_VEC | 20}, \ | |
2089 | {"$v21", RTYPE_VEC | 21}, \ | |
2090 | {"$v22", RTYPE_VEC | 22}, \ | |
2091 | {"$v23", RTYPE_VEC | 23}, \ | |
2092 | {"$v24", RTYPE_VEC | 24}, \ | |
2093 | {"$v25", RTYPE_VEC | 25}, \ | |
2094 | {"$v26", RTYPE_VEC | 26}, \ | |
2095 | {"$v27", RTYPE_VEC | 27}, \ | |
2096 | {"$v28", RTYPE_VEC | 28}, \ | |
2097 | {"$v29", RTYPE_VEC | 29}, \ | |
2098 | {"$v30", RTYPE_VEC | 30}, \ | |
2099 | {"$v31", RTYPE_VEC | 31} | |
2100 | ||
2101 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2102 | {"$ac0", RTYPE_ACC | 0}, \ | |
2103 | {"$ac1", RTYPE_ACC | 1}, \ | |
2104 | {"$ac2", RTYPE_ACC | 2}, \ | |
2105 | {"$ac3", RTYPE_ACC | 3} | |
2106 | ||
2107 | static const struct regname reg_names[] = { | |
2108 | GENERIC_REGISTER_NUMBERS, | |
2109 | FPU_REGISTER_NAMES, | |
2110 | FPU_CONDITION_CODE_NAMES, | |
2111 | COPROC_CONDITION_CODE_NAMES, | |
2112 | ||
2113 | /* The $txx registers depends on the abi, | |
2114 | these will be added later into the symbol table from | |
2115 | one of the tables below once mips_abi is set after | |
2116 | parsing of arguments from the command line. */ | |
2117 | SYMBOLIC_REGISTER_NAMES, | |
2118 | ||
2119 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2120 | MDMX_VECTOR_REGISTER_NAMES, | |
2121 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2122 | {0, 0} | |
2123 | }; | |
2124 | ||
2125 | static const struct regname reg_names_o32[] = { | |
2126 | O32_SYMBOLIC_REGISTER_NAMES, | |
2127 | {0, 0} | |
2128 | }; | |
2129 | ||
2130 | static const struct regname reg_names_n32n64[] = { | |
2131 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2132 | {0, 0} | |
2133 | }; | |
2134 | ||
df58fc94 RS |
2135 | /* Check if S points at a valid register specifier according to TYPES. |
2136 | If so, then return 1, advance S to consume the specifier and store | |
2137 | the register's number in REGNOP, otherwise return 0. */ | |
2138 | ||
707bfff6 TS |
2139 | static int |
2140 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2141 | { | |
2142 | symbolS *symbolP; | |
2143 | char *e; | |
2144 | char save_c; | |
2145 | int reg = -1; | |
2146 | ||
2147 | /* Find end of name. */ | |
2148 | e = *s; | |
2149 | if (is_name_beginner (*e)) | |
2150 | ++e; | |
2151 | while (is_part_of_name (*e)) | |
2152 | ++e; | |
2153 | ||
2154 | /* Terminate name. */ | |
2155 | save_c = *e; | |
2156 | *e = '\0'; | |
2157 | ||
2158 | /* Look for a register symbol. */ | |
2159 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2160 | { | |
2161 | int r = S_GET_VALUE (symbolP); | |
2162 | if (r & types) | |
2163 | reg = r & RNUM_MASK; | |
2164 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2165 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2166 | reg = (r & RNUM_MASK) - 2; | |
2167 | } | |
2168 | /* Else see if this is a register defined in an itbl entry. */ | |
2169 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2170 | { | |
2171 | char *n = *s; | |
2172 | unsigned long r; | |
2173 | ||
2174 | if (*n == '$') | |
2175 | ++n; | |
2176 | if (itbl_get_reg_val (n, &r)) | |
2177 | reg = r & RNUM_MASK; | |
2178 | } | |
2179 | ||
2180 | /* Advance to next token if a register was recognised. */ | |
2181 | if (reg >= 0) | |
2182 | *s = e; | |
2183 | else if (types & RWARN) | |
20203fb9 | 2184 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2185 | |
2186 | *e = save_c; | |
2187 | if (regnop) | |
2188 | *regnop = reg; | |
2189 | return reg >= 0; | |
2190 | } | |
2191 | ||
df58fc94 RS |
2192 | /* Check if S points at a valid register list according to TYPES. |
2193 | If so, then return 1, advance S to consume the list and store | |
2194 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2195 | otherwise return 0. A valid list comprises a comma-separated | |
2196 | enumeration of valid single registers and/or dash-separated | |
2197 | contiguous register ranges as determined by their numbers. | |
2198 | ||
2199 | As a special exception if one of s0-s7 registers is specified as | |
2200 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2201 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2202 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2203 | |
2204 | static int | |
2205 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2206 | { | |
2207 | unsigned int reglist = 0; | |
2208 | unsigned int lastregno; | |
2209 | bfd_boolean ok = TRUE; | |
2210 | unsigned int regmask; | |
2309ddf2 | 2211 | char *s_endlist = *s; |
df58fc94 | 2212 | char *s_reset = *s; |
2309ddf2 | 2213 | unsigned int regno; |
df58fc94 RS |
2214 | |
2215 | while (reg_lookup (s, types, ®no)) | |
2216 | { | |
2217 | lastregno = regno; | |
2218 | if (**s == '-') | |
2219 | { | |
2220 | (*s)++; | |
2221 | ok = reg_lookup (s, types, &lastregno); | |
2222 | if (ok && lastregno < regno) | |
2223 | ok = FALSE; | |
2224 | if (!ok) | |
2225 | break; | |
2226 | } | |
2227 | ||
2228 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2229 | { | |
2230 | lastregno = S7; | |
2231 | reglist |= 1 << FP; | |
2232 | } | |
2233 | regmask = 1 << lastregno; | |
2234 | regmask = (regmask << 1) - 1; | |
2235 | regmask ^= (1 << regno) - 1; | |
2236 | reglist |= regmask; | |
2237 | ||
2309ddf2 | 2238 | s_endlist = *s; |
df58fc94 RS |
2239 | if (**s != ',') |
2240 | break; | |
2241 | (*s)++; | |
2242 | } | |
2243 | ||
2244 | if (ok) | |
2309ddf2 | 2245 | *s = s_endlist; |
df58fc94 RS |
2246 | else |
2247 | *s = s_reset; | |
2248 | if (reglistp) | |
2249 | *reglistp = reglist; | |
2250 | return ok && reglist != 0; | |
2251 | } | |
2252 | ||
d301a56b RS |
2253 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2254 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2255 | |
2256 | static bfd_boolean | |
f79e2745 | 2257 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2258 | { |
2259 | int isa = mips_opts.isa; | |
d301a56b | 2260 | int ase = 0; |
037b32b9 AN |
2261 | int fp_s, fp_d; |
2262 | ||
2263 | if (mips_opts.ase_mdmx) | |
d301a56b | 2264 | ase |= ASE_MDMX; |
037b32b9 | 2265 | if (mips_opts.ase_dsp) |
d301a56b | 2266 | ase |= ASE_DSP; |
037b32b9 | 2267 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
d301a56b | 2268 | ase |= ASE_DSP64; |
037b32b9 | 2269 | if (mips_opts.ase_dspr2) |
d301a56b | 2270 | ase |= ASE_DSPR2; |
037b32b9 | 2271 | if (mips_opts.ase_mt) |
d301a56b | 2272 | ase |= ASE_MT; |
037b32b9 | 2273 | if (mips_opts.ase_mips3d) |
d301a56b | 2274 | ase |= ASE_MIPS3D; |
037b32b9 | 2275 | if (mips_opts.ase_smartmips) |
d301a56b | 2276 | ase |= ASE_SMARTMIPS; |
dec0624d | 2277 | if (mips_opts.ase_mcu) |
d301a56b | 2278 | ase |= ASE_MCU; |
b015e599 | 2279 | if (mips_opts.ase_virt) |
d301a56b | 2280 | ase |= ASE_VIRT; |
b015e599 | 2281 | if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE) |
d301a56b | 2282 | ase |= ASE_VIRT64; |
037b32b9 | 2283 | |
d301a56b | 2284 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2285 | return FALSE; |
2286 | ||
2287 | /* Check whether the instruction or macro requires single-precision or | |
2288 | double-precision floating-point support. Note that this information is | |
2289 | stored differently in the opcode table for insns and macros. */ | |
2290 | if (mo->pinfo == INSN_MACRO) | |
2291 | { | |
2292 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2293 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2294 | } | |
2295 | else | |
2296 | { | |
2297 | fp_s = mo->pinfo & FP_S; | |
2298 | fp_d = mo->pinfo & FP_D; | |
2299 | } | |
2300 | ||
2301 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2302 | return FALSE; | |
2303 | ||
2304 | if (fp_s && mips_opts.soft_float) | |
2305 | return FALSE; | |
2306 | ||
2307 | return TRUE; | |
2308 | } | |
2309 | ||
2310 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2311 | selected ISA and architecture. */ | |
2312 | ||
2313 | static bfd_boolean | |
2314 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2315 | { | |
d301a56b | 2316 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2317 | } |
2318 | ||
df58fc94 RS |
2319 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2320 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2321 | ||
2322 | static bfd_boolean | |
2323 | is_size_valid (const struct mips_opcode *mo) | |
2324 | { | |
2325 | if (!mips_opts.micromips) | |
2326 | return TRUE; | |
2327 | ||
2328 | if (!forced_insn_length) | |
2329 | return TRUE; | |
2330 | if (mo->pinfo == INSN_MACRO) | |
2331 | return FALSE; | |
2332 | return forced_insn_length == micromips_insn_length (mo); | |
2333 | } | |
2334 | ||
2335 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2336 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2337 | ||
2338 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2339 | a macro expansion fails because it relies on a preceding 32-bit real | |
2340 | instruction to have matched and does not handle the operands correctly. | |
2341 | The only macros that may expand to 16-bit instructions are JAL that | |
2342 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2343 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2344 | a NOP. In all these cases the macros precede any corresponding real | |
2345 | instruction definitions in the opcode table, so they will match in the | |
2346 | second pass where the size of the delay slot is ignored and therefore | |
2347 | produce correct code. */ | |
df58fc94 RS |
2348 | |
2349 | static bfd_boolean | |
2350 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2351 | { | |
2352 | if (!mips_opts.micromips) | |
2353 | return TRUE; | |
2354 | ||
2355 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2356 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2357 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2358 | && micromips_insn_length (mo) != 4) | |
2359 | return FALSE; | |
2360 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2361 | && micromips_insn_length (mo) != 2) | |
2362 | return FALSE; | |
2363 | ||
2364 | return TRUE; | |
2365 | } | |
2366 | ||
707bfff6 TS |
2367 | /* This function is called once, at assembler startup time. It should set up |
2368 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2369 | |
252b5132 | 2370 | void |
17a2f251 | 2371 | md_begin (void) |
252b5132 | 2372 | { |
3994f87e | 2373 | const char *retval = NULL; |
156c2f8b | 2374 | int i = 0; |
252b5132 | 2375 | int broken = 0; |
1f25f5d3 | 2376 | |
0a44bf69 RS |
2377 | if (mips_pic != NO_PIC) |
2378 | { | |
2379 | if (g_switch_seen && g_switch_value != 0) | |
2380 | as_bad (_("-G may not be used in position-independent code")); | |
2381 | g_switch_value = 0; | |
2382 | } | |
2383 | ||
fef14a42 | 2384 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2385 | as_warn (_("Could not set architecture and machine")); |
2386 | ||
252b5132 RH |
2387 | op_hash = hash_new (); |
2388 | ||
2389 | for (i = 0; i < NUMOPCODES;) | |
2390 | { | |
2391 | const char *name = mips_opcodes[i].name; | |
2392 | ||
17a2f251 | 2393 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2394 | if (retval != NULL) |
2395 | { | |
2396 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2397 | mips_opcodes[i].name, retval); | |
2398 | /* Probably a memory allocation problem? Give up now. */ | |
2399 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2400 | } | |
2401 | do | |
2402 | { | |
2403 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2404 | { | |
2405 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2406 | broken = 1; | |
1e915849 RS |
2407 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2408 | { | |
2409 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2410 | if (mips_fix_loongson2f_nop) |
2411 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2412 | nop_insn.fixed_p = 1; |
2413 | } | |
252b5132 RH |
2414 | } |
2415 | ++i; | |
2416 | } | |
2417 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2418 | } | |
2419 | ||
2420 | mips16_op_hash = hash_new (); | |
2421 | ||
2422 | i = 0; | |
2423 | while (i < bfd_mips16_num_opcodes) | |
2424 | { | |
2425 | const char *name = mips16_opcodes[i].name; | |
2426 | ||
17a2f251 | 2427 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2428 | if (retval != NULL) |
2429 | as_fatal (_("internal: can't hash `%s': %s"), | |
2430 | mips16_opcodes[i].name, retval); | |
2431 | do | |
2432 | { | |
2433 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2434 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2435 | != mips16_opcodes[i].match)) | |
2436 | { | |
2437 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2438 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2439 | broken = 1; | |
2440 | } | |
1e915849 RS |
2441 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2442 | { | |
2443 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2444 | mips16_nop_insn.fixed_p = 1; | |
2445 | } | |
252b5132 RH |
2446 | ++i; |
2447 | } | |
2448 | while (i < bfd_mips16_num_opcodes | |
2449 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2450 | } | |
2451 | ||
df58fc94 RS |
2452 | micromips_op_hash = hash_new (); |
2453 | ||
2454 | i = 0; | |
2455 | while (i < bfd_micromips_num_opcodes) | |
2456 | { | |
2457 | const char *name = micromips_opcodes[i].name; | |
2458 | ||
2459 | retval = hash_insert (micromips_op_hash, name, | |
2460 | (void *) µmips_opcodes[i]); | |
2461 | if (retval != NULL) | |
2462 | as_fatal (_("internal: can't hash `%s': %s"), | |
2463 | micromips_opcodes[i].name, retval); | |
2464 | do | |
2465 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2466 | { | |
2467 | struct mips_cl_insn *micromips_nop_insn; | |
2468 | ||
2469 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2470 | broken = 1; | |
2471 | ||
2472 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2473 | micromips_nop_insn = µmips_nop16_insn; | |
2474 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2475 | micromips_nop_insn = µmips_nop32_insn; | |
2476 | else | |
2477 | continue; | |
2478 | ||
2479 | if (micromips_nop_insn->insn_mo == NULL | |
2480 | && strcmp (name, "nop") == 0) | |
2481 | { | |
2482 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2483 | micromips_nop_insn->fixed_p = 1; | |
2484 | } | |
2485 | } | |
2486 | while (++i < bfd_micromips_num_opcodes | |
2487 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2488 | } | |
2489 | ||
252b5132 RH |
2490 | if (broken) |
2491 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2492 | ||
2493 | /* We add all the general register names to the symbol table. This | |
2494 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2495 | for (i = 0; reg_names[i].name; i++) |
2496 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2497 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2498 | &zero_address_frag)); |
2499 | if (HAVE_NEWABI) | |
2500 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2501 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2502 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2503 | &zero_address_frag)); |
707bfff6 TS |
2504 | else |
2505 | for (i = 0; reg_names_o32[i].name; i++) | |
2506 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2507 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2508 | &zero_address_frag)); |
6047c971 | 2509 | |
7d10b47d | 2510 | mips_no_prev_insn (); |
252b5132 RH |
2511 | |
2512 | mips_gprmask = 0; | |
2513 | mips_cprmask[0] = 0; | |
2514 | mips_cprmask[1] = 0; | |
2515 | mips_cprmask[2] = 0; | |
2516 | mips_cprmask[3] = 0; | |
2517 | ||
2518 | /* set the default alignment for the text section (2**2) */ | |
2519 | record_alignment (text_section, 2); | |
2520 | ||
4d0d148d | 2521 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2522 | |
707bfff6 | 2523 | #ifdef OBJ_ELF |
f43abd2b | 2524 | if (IS_ELF) |
252b5132 | 2525 | { |
0a44bf69 RS |
2526 | /* On a native system other than VxWorks, sections must be aligned |
2527 | to 16 byte boundaries. When configured for an embedded ELF | |
2528 | target, we don't bother. */ | |
c41e87e3 CF |
2529 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2530 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2531 | { |
2532 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2533 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2534 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2535 | } | |
2536 | ||
2537 | /* Create a .reginfo section for register masks and a .mdebug | |
2538 | section for debugging information. */ | |
2539 | { | |
2540 | segT seg; | |
2541 | subsegT subseg; | |
2542 | flagword flags; | |
2543 | segT sec; | |
2544 | ||
2545 | seg = now_seg; | |
2546 | subseg = now_subseg; | |
2547 | ||
2548 | /* The ABI says this section should be loaded so that the | |
2549 | running program can access it. However, we don't load it | |
2550 | if we are configured for an embedded target */ | |
2551 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2552 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2553 | flags |= SEC_ALLOC | SEC_LOAD; |
2554 | ||
316f5878 | 2555 | if (mips_abi != N64_ABI) |
252b5132 RH |
2556 | { |
2557 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2558 | ||
195325d2 TS |
2559 | bfd_set_section_flags (stdoutput, sec, flags); |
2560 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2561 | |
252b5132 | 2562 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2563 | } |
2564 | else | |
2565 | { | |
2566 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2567 | .reginfo section. */ | |
2568 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2569 | bfd_set_section_flags (stdoutput, sec, flags); |
2570 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2571 | |
252b5132 RH |
2572 | /* Set up the option header. */ |
2573 | { | |
2574 | Elf_Internal_Options opthdr; | |
2575 | char *f; | |
2576 | ||
2577 | opthdr.kind = ODK_REGINFO; | |
2578 | opthdr.size = (sizeof (Elf_External_Options) | |
2579 | + sizeof (Elf64_External_RegInfo)); | |
2580 | opthdr.section = 0; | |
2581 | opthdr.info = 0; | |
2582 | f = frag_more (sizeof (Elf_External_Options)); | |
2583 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2584 | (Elf_External_Options *) f); | |
2585 | ||
2586 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2587 | } | |
252b5132 RH |
2588 | } |
2589 | ||
2590 | if (ECOFF_DEBUGGING) | |
2591 | { | |
2592 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2593 | (void) bfd_set_section_flags (stdoutput, sec, | |
2594 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2595 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2596 | } | |
f43abd2b | 2597 | else if (mips_flag_pdr) |
ecb4347a DJ |
2598 | { |
2599 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2600 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2601 | SEC_READONLY | SEC_RELOC | |
2602 | | SEC_DEBUGGING); | |
2603 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2604 | } | |
252b5132 RH |
2605 | |
2606 | subseg_set (seg, subseg); | |
2607 | } | |
2608 | } | |
707bfff6 | 2609 | #endif /* OBJ_ELF */ |
252b5132 RH |
2610 | |
2611 | if (! ECOFF_DEBUGGING) | |
2612 | md_obj_begin (); | |
71400594 RS |
2613 | |
2614 | if (mips_fix_vr4120) | |
2615 | init_vr4120_conflicts (); | |
252b5132 RH |
2616 | } |
2617 | ||
2618 | void | |
17a2f251 | 2619 | md_mips_end (void) |
252b5132 | 2620 | { |
02b1ab82 | 2621 | mips_emit_delays (); |
252b5132 RH |
2622 | if (! ECOFF_DEBUGGING) |
2623 | md_obj_end (); | |
2624 | } | |
2625 | ||
2626 | void | |
17a2f251 | 2627 | md_assemble (char *str) |
252b5132 RH |
2628 | { |
2629 | struct mips_cl_insn insn; | |
f6688943 TS |
2630 | bfd_reloc_code_real_type unused_reloc[3] |
2631 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2632 | |
2633 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2634 | imm2_expr.X_op = O_absent; |
252b5132 | 2635 | offset_expr.X_op = O_absent; |
f6688943 TS |
2636 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2637 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2638 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2639 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2640 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2641 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2642 | |
e1b47bd5 RS |
2643 | mips_mark_labels (); |
2644 | mips_assembling_insn = TRUE; | |
2645 | ||
252b5132 RH |
2646 | if (mips_opts.mips16) |
2647 | mips16_ip (str, &insn); | |
2648 | else | |
2649 | { | |
2650 | mips_ip (str, &insn); | |
beae10d5 KH |
2651 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2652 | str, insn.insn_opcode)); | |
252b5132 RH |
2653 | } |
2654 | ||
2655 | if (insn_error) | |
e1b47bd5 RS |
2656 | as_bad ("%s `%s'", insn_error, str); |
2657 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2658 | { |
584892a6 | 2659 | macro_start (); |
252b5132 RH |
2660 | if (mips_opts.mips16) |
2661 | mips16_macro (&insn); | |
2662 | else | |
2663 | macro (&insn); | |
584892a6 | 2664 | macro_end (); |
252b5132 RH |
2665 | } |
2666 | else | |
2667 | { | |
2668 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2669 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2670 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2671 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2672 | else |
df58fc94 | 2673 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2674 | } |
e1b47bd5 RS |
2675 | |
2676 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2677 | } |
2678 | ||
738e5348 RS |
2679 | /* Convenience functions for abstracting away the differences between |
2680 | MIPS16 and non-MIPS16 relocations. */ | |
2681 | ||
2682 | static inline bfd_boolean | |
2683 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2684 | { | |
2685 | switch (reloc) | |
2686 | { | |
2687 | case BFD_RELOC_MIPS16_JMP: | |
2688 | case BFD_RELOC_MIPS16_GPREL: | |
2689 | case BFD_RELOC_MIPS16_GOT16: | |
2690 | case BFD_RELOC_MIPS16_CALL16: | |
2691 | case BFD_RELOC_MIPS16_HI16_S: | |
2692 | case BFD_RELOC_MIPS16_HI16: | |
2693 | case BFD_RELOC_MIPS16_LO16: | |
2694 | return TRUE; | |
2695 | ||
2696 | default: | |
2697 | return FALSE; | |
2698 | } | |
2699 | } | |
2700 | ||
df58fc94 RS |
2701 | static inline bfd_boolean |
2702 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2703 | { | |
2704 | switch (reloc) | |
2705 | { | |
2706 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2707 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2708 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2709 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2710 | case BFD_RELOC_MICROMIPS_JMP: | |
2711 | case BFD_RELOC_MICROMIPS_HI16: | |
2712 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2713 | case BFD_RELOC_MICROMIPS_LO16: | |
2714 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2715 | case BFD_RELOC_MICROMIPS_GOT16: | |
2716 | case BFD_RELOC_MICROMIPS_CALL16: | |
2717 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2718 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2719 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2720 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2721 | case BFD_RELOC_MICROMIPS_SUB: | |
2722 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2723 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2724 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2725 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2726 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2727 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2728 | case BFD_RELOC_MICROMIPS_JALR: | |
2729 | return TRUE; | |
2730 | ||
2731 | default: | |
2732 | return FALSE; | |
2733 | } | |
2734 | } | |
2735 | ||
2309ddf2 MR |
2736 | static inline bfd_boolean |
2737 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2738 | { | |
2739 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2740 | } | |
2741 | ||
738e5348 RS |
2742 | static inline bfd_boolean |
2743 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2744 | { | |
2309ddf2 | 2745 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2746 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2747 | } |
2748 | ||
2749 | static inline bfd_boolean | |
2750 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2751 | { | |
2309ddf2 | 2752 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2753 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2754 | } |
2755 | ||
2756 | static inline bfd_boolean | |
2757 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2758 | { | |
2309ddf2 | 2759 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2760 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2761 | } | |
2762 | ||
df58fc94 RS |
2763 | static inline bfd_boolean |
2764 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2765 | { | |
2309ddf2 | 2766 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2767 | } |
2768 | ||
2de39019 CM |
2769 | /* Return true if RELOC is a PC-relative relocation that does not have |
2770 | full address range. */ | |
2771 | ||
2772 | static inline bfd_boolean | |
2773 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
2774 | { | |
2775 | switch (reloc) | |
2776 | { | |
2777 | case BFD_RELOC_16_PCREL_S2: | |
2778 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2779 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2780 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2781 | return TRUE; | |
2782 | ||
b47468a6 CM |
2783 | case BFD_RELOC_32_PCREL: |
2784 | return HAVE_64BIT_ADDRESSES; | |
2785 | ||
2de39019 CM |
2786 | default: |
2787 | return FALSE; | |
2788 | } | |
2789 | } | |
b47468a6 | 2790 | |
5919d012 | 2791 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2792 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2793 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2794 | |
2795 | static inline bfd_boolean | |
17a2f251 | 2796 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2797 | { |
3b91255e | 2798 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2799 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2800 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2801 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2802 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2803 | } | |
2804 | ||
2805 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2806 | reloc_needs_lo_p. */ | |
2807 | ||
2808 | static inline bfd_reloc_code_real_type | |
2809 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2810 | { | |
df58fc94 RS |
2811 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2812 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2813 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2814 | } |
2815 | ||
2816 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2817 | relocation. */ | |
2818 | ||
2819 | static inline bfd_boolean | |
17a2f251 | 2820 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2821 | { |
2822 | return (fixp->fx_next != NULL | |
738e5348 | 2823 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2824 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2825 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2826 | } | |
2827 | ||
252b5132 RH |
2828 | /* This function returns true if modifying a register requires a |
2829 | delay. */ | |
2830 | ||
2831 | static int | |
17a2f251 | 2832 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2833 | { |
2834 | unsigned long prev_pinfo; | |
2835 | ||
47e39b9d | 2836 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2837 | if (! mips_opts.noreorder |
81912461 ILT |
2838 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2839 | && ! gpr_interlocks) | |
2840 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2841 | && ! cop_interlocks))) | |
252b5132 | 2842 | { |
81912461 ILT |
2843 | /* A load from a coprocessor or from memory. All load delays |
2844 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2845 | /* Itbl support may require additional care here. */ |
252b5132 | 2846 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2847 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2848 | return 1; |
2849 | } | |
2850 | ||
2851 | return 0; | |
2852 | } | |
2853 | ||
462427c4 RS |
2854 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2855 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2856 | |
2857 | static void | |
462427c4 | 2858 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2859 | { |
2860 | struct insn_label_list *l; | |
2861 | valueT val; | |
2862 | ||
462427c4 | 2863 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2864 | { |
9c2799c2 | 2865 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2866 | symbol_set_frag (l->label, frag_now); |
2867 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2868 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2869 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2870 | ++val; |
2871 | S_SET_VALUE (l->label, val); | |
2872 | } | |
2873 | } | |
2874 | ||
462427c4 RS |
2875 | /* Move all labels in insn_labels to the current insertion point |
2876 | and treat them as text labels. */ | |
2877 | ||
2878 | static void | |
2879 | mips_move_text_labels (void) | |
2880 | { | |
2881 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2882 | } | |
2883 | ||
5f0fe04b TS |
2884 | static bfd_boolean |
2885 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2886 | { | |
2887 | bfd_boolean linkonce = FALSE; | |
2888 | segT symseg = S_GET_SEGMENT (sym); | |
2889 | ||
2890 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2891 | { | |
2892 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2893 | linkonce = TRUE; | |
2894 | #ifdef OBJ_ELF | |
2895 | /* The GNU toolchain uses an extension for ELF: a section | |
2896 | beginning with the magic string .gnu.linkonce is a | |
2897 | linkonce section. */ | |
2898 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2899 | sizeof ".gnu.linkonce" - 1) == 0) | |
2900 | linkonce = TRUE; | |
2901 | #endif | |
2902 | } | |
2903 | return linkonce; | |
2904 | } | |
2905 | ||
e1b47bd5 | 2906 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2907 | linker to handle them specially, such as generating jalx instructions |
2908 | when needed. We also make them odd for the duration of the assembly, | |
2909 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2910 | in the adjust_symtab routine, while leaving them marked. This is |
2911 | convenient for the debugger and the disassembler. The linker knows | |
2912 | to make them odd again. */ | |
2913 | ||
2914 | static void | |
e1b47bd5 | 2915 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2916 | { |
df58fc94 | 2917 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2918 | |
a8dbcb85 | 2919 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2920 | if (IS_ELF) |
2921 | { | |
2922 | if (mips_opts.mips16) | |
2923 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2924 | else | |
2925 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2926 | } |
e1b47bd5 RS |
2927 | #endif |
2928 | if ((S_GET_VALUE (label) & 1) == 0 | |
2929 | /* Don't adjust the address if the label is global or weak, or | |
2930 | in a link-once section, since we'll be emitting symbol reloc | |
2931 | references to it which will be patched up by the linker, and | |
2932 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2933 | && !S_IS_WEAK (label) | |
2934 | && !S_IS_EXTERNAL (label) | |
2935 | && !s_is_linkonce (label, now_seg)) | |
2936 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2937 | } | |
2938 | ||
2939 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2940 | ||
2941 | static void | |
2942 | mips_compressed_mark_labels (void) | |
2943 | { | |
2944 | struct insn_label_list *l; | |
2945 | ||
2946 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2947 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2948 | } |
2949 | ||
4d7206a2 RS |
2950 | /* End the current frag. Make it a variant frag and record the |
2951 | relaxation info. */ | |
2952 | ||
2953 | static void | |
2954 | relax_close_frag (void) | |
2955 | { | |
584892a6 | 2956 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2957 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2958 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2959 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2960 | ||
2961 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2962 | mips_relax.first_fixup = 0; | |
2963 | } | |
2964 | ||
2965 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2966 | See the comment above RELAX_ENCODE for more details. */ | |
2967 | ||
2968 | static void | |
2969 | relax_start (symbolS *symbol) | |
2970 | { | |
9c2799c2 | 2971 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2972 | mips_relax.sequence = 1; |
2973 | mips_relax.symbol = symbol; | |
2974 | } | |
2975 | ||
2976 | /* Start generating the second version of a relaxable sequence. | |
2977 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2978 | |
2979 | static void | |
4d7206a2 RS |
2980 | relax_switch (void) |
2981 | { | |
9c2799c2 | 2982 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2983 | mips_relax.sequence = 2; |
2984 | } | |
2985 | ||
2986 | /* End the current relaxable sequence. */ | |
2987 | ||
2988 | static void | |
2989 | relax_end (void) | |
2990 | { | |
9c2799c2 | 2991 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2992 | relax_close_frag (); |
2993 | mips_relax.sequence = 0; | |
2994 | } | |
2995 | ||
11625dd8 RS |
2996 | /* Return true if IP is a delayed branch or jump. */ |
2997 | ||
2998 | static inline bfd_boolean | |
2999 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3000 | { | |
3001 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3002 | | INSN_COND_BRANCH_DELAY | |
3003 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3004 | } | |
3005 | ||
3006 | /* Return true if IP is a compact branch or jump. */ | |
3007 | ||
3008 | static inline bfd_boolean | |
3009 | compact_branch_p (const struct mips_cl_insn *ip) | |
3010 | { | |
3011 | if (mips_opts.mips16) | |
3012 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3013 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3014 | else | |
3015 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3016 | | INSN2_COND_BRANCH)) != 0; | |
3017 | } | |
3018 | ||
3019 | /* Return true if IP is an unconditional branch or jump. */ | |
3020 | ||
3021 | static inline bfd_boolean | |
3022 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3023 | { | |
3024 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3025 | || (mips_opts.mips16 | |
3026 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3027 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3028 | } | |
3029 | ||
3030 | /* Return true if IP is a branch-likely instruction. */ | |
3031 | ||
3032 | static inline bfd_boolean | |
3033 | branch_likely_p (const struct mips_cl_insn *ip) | |
3034 | { | |
3035 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3036 | } | |
3037 | ||
14fe068b RS |
3038 | /* Return the type of nop that should be used to fill the delay slot |
3039 | of delayed branch IP. */ | |
3040 | ||
3041 | static struct mips_cl_insn * | |
3042 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3043 | { | |
3044 | if (mips_opts.micromips | |
3045 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3046 | return µmips_nop32_insn; | |
3047 | return NOP_INSN; | |
3048 | } | |
3049 | ||
2309ddf2 | 3050 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3051 | |
3052 | static unsigned int | |
3053 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3054 | { | |
2309ddf2 | 3055 | unsigned long pinfo2; |
df58fc94 RS |
3056 | unsigned int mask; |
3057 | ||
3058 | mask = 0; | |
df58fc94 RS |
3059 | pinfo2 = ip->insn_mo->pinfo2; |
3060 | if (mips_opts.micromips) | |
3061 | { | |
df58fc94 RS |
3062 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3063 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3064 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3065 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3066 | if (pinfo2 & INSN2_MOD_SP) |
3067 | mask |= 1 << SP; | |
3068 | } | |
3069 | return mask; | |
3070 | } | |
3071 | ||
4c260379 RS |
3072 | /* Return the mask of core registers that IP reads. */ |
3073 | ||
3074 | static unsigned int | |
3075 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3076 | { | |
3077 | unsigned long pinfo, pinfo2; | |
3078 | unsigned int mask; | |
3079 | ||
df58fc94 | 3080 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3081 | pinfo = ip->insn_mo->pinfo; |
3082 | pinfo2 = ip->insn_mo->pinfo2; | |
3083 | if (mips_opts.mips16) | |
3084 | { | |
3085 | if (pinfo & MIPS16_INSN_READ_X) | |
3086 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3087 | if (pinfo & MIPS16_INSN_READ_Y) | |
3088 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3089 | if (pinfo & MIPS16_INSN_READ_T) | |
3090 | mask |= 1 << TREG; | |
3091 | if (pinfo & MIPS16_INSN_READ_SP) | |
3092 | mask |= 1 << SP; | |
3093 | if (pinfo & MIPS16_INSN_READ_31) | |
3094 | mask |= 1 << RA; | |
3095 | if (pinfo & MIPS16_INSN_READ_Z) | |
3096 | mask |= 1 << (mips16_to_32_reg_map | |
3097 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3098 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3099 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3100 | } | |
3101 | else | |
3102 | { | |
3103 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3104 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3105 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3106 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3107 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3108 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3109 | if (pinfo2 & INSN2_READ_GP) | |
3110 | mask |= 1 << GP; | |
3111 | if (pinfo2 & INSN2_READ_GPR_31) | |
3112 | mask |= 1 << RA; | |
4c260379 | 3113 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3114 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3115 | } |
2b0c8b40 MR |
3116 | if (mips_opts.micromips) |
3117 | { | |
3118 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3119 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3120 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3121 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3122 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3123 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3124 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3125 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3126 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3127 | { | |
3128 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3129 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3130 | } | |
3131 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3132 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3133 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3134 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3135 | } | |
fe35f09f RS |
3136 | /* Don't include register 0. */ |
3137 | return mask & ~1; | |
4c260379 RS |
3138 | } |
3139 | ||
3140 | /* Return the mask of core registers that IP writes. */ | |
3141 | ||
3142 | static unsigned int | |
3143 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3144 | { | |
3145 | unsigned long pinfo, pinfo2; | |
3146 | unsigned int mask; | |
3147 | ||
df58fc94 | 3148 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3149 | pinfo = ip->insn_mo->pinfo; |
3150 | pinfo2 = ip->insn_mo->pinfo2; | |
3151 | if (mips_opts.mips16) | |
3152 | { | |
3153 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3154 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3155 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3156 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3157 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3158 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3159 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3160 | mask |= 1 << TREG; | |
3161 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3162 | mask |= 1 << SP; | |
3163 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3164 | mask |= 1 << RA; | |
3165 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3166 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3167 | } | |
3168 | else | |
3169 | { | |
3170 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3171 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3172 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3173 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3174 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3175 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3176 | if (pinfo & INSN_WRITE_GPR_31) |
3177 | mask |= 1 << RA; | |
3178 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3179 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3180 | } |
2b0c8b40 MR |
3181 | if (mips_opts.micromips) |
3182 | { | |
3183 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3184 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3185 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3186 | { | |
3187 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3188 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3189 | } | |
3190 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3191 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3192 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3193 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3194 | } | |
fe35f09f RS |
3195 | /* Don't include register 0. */ |
3196 | return mask & ~1; | |
4c260379 RS |
3197 | } |
3198 | ||
3199 | /* Return the mask of floating-point registers that IP reads. */ | |
3200 | ||
3201 | static unsigned int | |
3202 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3203 | { | |
3204 | unsigned long pinfo, pinfo2; | |
3205 | unsigned int mask; | |
3206 | ||
3207 | mask = 0; | |
3208 | pinfo = ip->insn_mo->pinfo; | |
3209 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3210 | if (!mips_opts.mips16) |
df58fc94 RS |
3211 | { |
3212 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3213 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3214 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3215 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3216 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3217 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3218 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3219 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3220 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3221 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3222 | } |
3223 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3224 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3225 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3226 | mask |= mask << 1; | |
3227 | return mask; | |
3228 | } | |
3229 | ||
3230 | /* Return the mask of floating-point registers that IP writes. */ | |
3231 | ||
3232 | static unsigned int | |
3233 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3234 | { | |
3235 | unsigned long pinfo, pinfo2; | |
3236 | unsigned int mask; | |
3237 | ||
3238 | mask = 0; | |
3239 | pinfo = ip->insn_mo->pinfo; | |
3240 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3241 | if (!mips_opts.mips16) |
4c260379 RS |
3242 | { |
3243 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3244 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3245 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3246 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3247 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3248 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3249 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3250 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3251 | } |
3252 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3253 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3254 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3255 | mask |= mask << 1; | |
3256 | return mask; | |
3257 | } | |
3258 | ||
71400594 RS |
3259 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3260 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3261 | by VR4120 errata. */ | |
4d7206a2 | 3262 | |
71400594 RS |
3263 | static unsigned int |
3264 | classify_vr4120_insn (const char *name) | |
252b5132 | 3265 | { |
71400594 RS |
3266 | if (strncmp (name, "macc", 4) == 0) |
3267 | return FIX_VR4120_MACC; | |
3268 | if (strncmp (name, "dmacc", 5) == 0) | |
3269 | return FIX_VR4120_DMACC; | |
3270 | if (strncmp (name, "mult", 4) == 0) | |
3271 | return FIX_VR4120_MULT; | |
3272 | if (strncmp (name, "dmult", 5) == 0) | |
3273 | return FIX_VR4120_DMULT; | |
3274 | if (strstr (name, "div")) | |
3275 | return FIX_VR4120_DIV; | |
3276 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3277 | return FIX_VR4120_MTHILO; | |
3278 | return NUM_FIX_VR4120_CLASSES; | |
3279 | } | |
252b5132 | 3280 | |
ff239038 CM |
3281 | #define INSN_ERET 0x42000018 |
3282 | #define INSN_DERET 0x4200001f | |
3283 | ||
71400594 RS |
3284 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3285 | where INSN1 is the earlier instruction. Return the worst-case value | |
3286 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3287 | |
71400594 RS |
3288 | static unsigned int |
3289 | insns_between (const struct mips_cl_insn *insn1, | |
3290 | const struct mips_cl_insn *insn2) | |
3291 | { | |
3292 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3293 | unsigned int mask; |
71400594 RS |
3294 | |
3295 | /* This function needs to know which pinfo flags are set for INSN2 | |
3296 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3297 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3298 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3299 | pinfo1 = insn1->insn_mo->pinfo; |
3300 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3301 | |
4c260379 RS |
3302 | #define INSN2_USES_GPR(REG) \ |
3303 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3304 | |
3305 | /* For most targets, write-after-read dependencies on the HI and LO | |
3306 | registers must be separated by at least two instructions. */ | |
3307 | if (!hilo_interlocks) | |
252b5132 | 3308 | { |
71400594 RS |
3309 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3310 | return 2; | |
3311 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3312 | return 2; | |
3313 | } | |
3314 | ||
3315 | /* If we're working around r7000 errata, there must be two instructions | |
3316 | between an mfhi or mflo and any instruction that uses the result. */ | |
3317 | if (mips_7000_hilo_fix | |
df58fc94 | 3318 | && !mips_opts.micromips |
71400594 | 3319 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3320 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3321 | return 2; |
3322 | ||
ff239038 CM |
3323 | /* If we're working around 24K errata, one instruction is required |
3324 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3325 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3326 | { |
3327 | if (insn1->insn_opcode == INSN_ERET | |
3328 | || insn1->insn_opcode == INSN_DERET) | |
3329 | { | |
3330 | if (insn2 == NULL | |
3331 | || insn2->insn_opcode == INSN_ERET | |
3332 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3333 | || delayed_branch_p (insn2)) |
ff239038 CM |
3334 | return 1; |
3335 | } | |
3336 | } | |
3337 | ||
71400594 RS |
3338 | /* If working around VR4120 errata, check for combinations that need |
3339 | a single intervening instruction. */ | |
df58fc94 | 3340 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3341 | { |
3342 | unsigned int class1, class2; | |
252b5132 | 3343 | |
71400594 RS |
3344 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3345 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3346 | { |
71400594 RS |
3347 | if (insn2 == NULL) |
3348 | return 1; | |
3349 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3350 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3351 | return 1; | |
252b5132 | 3352 | } |
71400594 RS |
3353 | } |
3354 | ||
df58fc94 | 3355 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3356 | { |
3357 | /* Check for GPR or coprocessor load delays. All such delays | |
3358 | are on the RT register. */ | |
3359 | /* Itbl support may require additional care here. */ | |
3360 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3361 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3362 | { |
71400594 | 3363 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3364 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3365 | return 1; |
3366 | } | |
3367 | ||
3368 | /* Check for generic coprocessor hazards. | |
3369 | ||
3370 | This case is not handled very well. There is no special | |
3371 | knowledge of CP0 handling, and the coprocessors other than | |
3372 | the floating point unit are not distinguished at all. */ | |
3373 | /* Itbl support may require additional care here. FIXME! | |
3374 | Need to modify this to include knowledge about | |
3375 | user specified delays! */ | |
3376 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3377 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3378 | { | |
3379 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3380 | register. There must be a one instruction delay before INSN2 | |
3381 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3382 | mask = fpr_write_mask (insn1); |
3383 | if (mask != 0) | |
252b5132 | 3384 | { |
4c260379 | 3385 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3386 | return 1; |
252b5132 RH |
3387 | } |
3388 | else | |
3389 | { | |
71400594 RS |
3390 | /* Read-after-write dependencies on the control registers |
3391 | require a two-instruction gap. */ | |
3392 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3393 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3394 | return 2; | |
3395 | ||
3396 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3397 | also a coprocessor instruction, assume there must be | |
3398 | a one instruction gap. */ | |
3399 | if (pinfo2 & INSN_COP) | |
3400 | return 1; | |
252b5132 RH |
3401 | } |
3402 | } | |
6b76fefe | 3403 | |
71400594 RS |
3404 | /* Check for read-after-write dependencies on the coprocessor |
3405 | control registers in cases where INSN1 does not need a general | |
3406 | coprocessor delay. This means that INSN1 is a floating point | |
3407 | comparison instruction. */ | |
3408 | /* Itbl support may require additional care here. */ | |
3409 | else if (!cop_interlocks | |
3410 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3411 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3412 | return 1; | |
3413 | } | |
6b76fefe | 3414 | |
4c260379 | 3415 | #undef INSN2_USES_GPR |
6b76fefe | 3416 | |
71400594 RS |
3417 | return 0; |
3418 | } | |
6b76fefe | 3419 | |
7d8e00cf RS |
3420 | /* Return the number of nops that would be needed to work around the |
3421 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3422 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3423 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3424 | |
3425 | static int | |
932d1a1b | 3426 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3427 | const struct mips_cl_insn *insn) |
3428 | { | |
4c260379 RS |
3429 | int i, j; |
3430 | unsigned int mask; | |
7d8e00cf RS |
3431 | |
3432 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3433 | are not affected by the errata. */ | |
3434 | if (insn != 0 | |
3435 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3436 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3437 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3438 | return 0; | |
3439 | ||
3440 | /* Search for the first MFLO or MFHI. */ | |
3441 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3442 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3443 | { |
3444 | /* Extract the destination register. */ | |
4c260379 | 3445 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3446 | |
3447 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3448 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3449 | return 0; |
3450 | ||
3451 | /* ...or if any of the intervening instructions do. */ | |
3452 | for (j = 0; j < i; j++) | |
4c260379 | 3453 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3454 | return 0; |
3455 | ||
932d1a1b RS |
3456 | if (i >= ignore) |
3457 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3458 | } |
3459 | return 0; | |
3460 | } | |
3461 | ||
15be625d CM |
3462 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3463 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3464 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3465 | ||
3466 | /* Return the minimum alignment for this store instruction. */ | |
3467 | ||
3468 | static int | |
3469 | fix_24k_align_to (const struct mips_opcode *mo) | |
3470 | { | |
3471 | if (strcmp (mo->name, "sh") == 0) | |
3472 | return 2; | |
3473 | ||
3474 | if (strcmp (mo->name, "swc1") == 0 | |
3475 | || strcmp (mo->name, "swc2") == 0 | |
3476 | || strcmp (mo->name, "sw") == 0 | |
3477 | || strcmp (mo->name, "sc") == 0 | |
3478 | || strcmp (mo->name, "s.s") == 0) | |
3479 | return 4; | |
3480 | ||
3481 | if (strcmp (mo->name, "sdc1") == 0 | |
3482 | || strcmp (mo->name, "sdc2") == 0 | |
3483 | || strcmp (mo->name, "s.d") == 0) | |
3484 | return 8; | |
3485 | ||
3486 | /* sb, swl, swr */ | |
3487 | return 1; | |
3488 | } | |
3489 | ||
3490 | struct fix_24k_store_info | |
3491 | { | |
3492 | /* Immediate offset, if any, for this store instruction. */ | |
3493 | short off; | |
3494 | /* Alignment required by this store instruction. */ | |
3495 | int align_to; | |
3496 | /* True for register offsets. */ | |
3497 | int register_offset; | |
3498 | }; | |
3499 | ||
3500 | /* Comparison function used by qsort. */ | |
3501 | ||
3502 | static int | |
3503 | fix_24k_sort (const void *a, const void *b) | |
3504 | { | |
3505 | const struct fix_24k_store_info *pos1 = a; | |
3506 | const struct fix_24k_store_info *pos2 = b; | |
3507 | ||
3508 | return (pos1->off - pos2->off); | |
3509 | } | |
3510 | ||
3511 | /* INSN is a store instruction. Try to record the store information | |
3512 | in STINFO. Return false if the information isn't known. */ | |
3513 | ||
3514 | static bfd_boolean | |
3515 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3516 | const struct mips_cl_insn *insn) |
15be625d CM |
3517 | { |
3518 | /* The instruction must have a known offset. */ | |
3519 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3520 | return FALSE; | |
3521 | ||
3522 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3523 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3524 | return TRUE; | |
3525 | } | |
3526 | ||
932d1a1b RS |
3527 | /* Return the number of nops that would be needed to work around the 24k |
3528 | "lost data on stores during refill" errata if instruction INSN | |
3529 | immediately followed the 2 instructions described by HIST. | |
3530 | Ignore hazards that are contained within the first IGNORE | |
3531 | instructions of HIST. | |
3532 | ||
3533 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3534 | for the data cache refills and store data. The following describes | |
3535 | the scenario where the store data could be lost. | |
3536 | ||
3537 | * A data cache miss, due to either a load or a store, causing fill | |
3538 | data to be supplied by the memory subsystem | |
3539 | * The first three doublewords of fill data are returned and written | |
3540 | into the cache | |
3541 | * A sequence of four stores occurs in consecutive cycles around the | |
3542 | final doubleword of the fill: | |
3543 | * Store A | |
3544 | * Store B | |
3545 | * Store C | |
3546 | * Zero, One or more instructions | |
3547 | * Store D | |
3548 | ||
3549 | The four stores A-D must be to different doublewords of the line that | |
3550 | is being filled. The fourth instruction in the sequence above permits | |
3551 | the fill of the final doubleword to be transferred from the FSB into | |
3552 | the cache. In the sequence above, the stores may be either integer | |
3553 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3554 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3555 | different doublewords on the line. If the floating point unit is | |
3556 | running in 1:2 mode, it is not possible to create the sequence above | |
3557 | using only floating point store instructions. | |
15be625d CM |
3558 | |
3559 | In this case, the cache line being filled is incorrectly marked | |
3560 | invalid, thereby losing the data from any store to the line that | |
3561 | occurs between the original miss and the completion of the five | |
3562 | cycle sequence shown above. | |
3563 | ||
932d1a1b | 3564 | The workarounds are: |
15be625d | 3565 | |
932d1a1b RS |
3566 | * Run the data cache in write-through mode. |
3567 | * Insert a non-store instruction between | |
3568 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3569 | |
3570 | static int | |
932d1a1b | 3571 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3572 | const struct mips_cl_insn *insn) |
3573 | { | |
3574 | struct fix_24k_store_info pos[3]; | |
3575 | int align, i, base_offset; | |
3576 | ||
932d1a1b RS |
3577 | if (ignore >= 2) |
3578 | return 0; | |
3579 | ||
ab9794cf RS |
3580 | /* If the previous instruction wasn't a store, there's nothing to |
3581 | worry about. */ | |
15be625d CM |
3582 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3583 | return 0; | |
3584 | ||
ab9794cf RS |
3585 | /* If the instructions after the previous one are unknown, we have |
3586 | to assume the worst. */ | |
3587 | if (!insn) | |
15be625d CM |
3588 | return 1; |
3589 | ||
ab9794cf RS |
3590 | /* Check whether we are dealing with three consecutive stores. */ |
3591 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3592 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3593 | return 0; |
3594 | ||
3595 | /* If we don't know the relationship between the store addresses, | |
3596 | assume the worst. */ | |
ab9794cf | 3597 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3598 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3599 | return 1; | |
3600 | ||
3601 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3602 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3603 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3604 | return 1; | |
3605 | ||
3606 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3607 | ||
3608 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3609 | X bytes and such that the base register + X is known to be aligned | |
3610 | to align bytes. */ | |
3611 | ||
3612 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3613 | align = 8; | |
3614 | else | |
3615 | { | |
3616 | align = pos[0].align_to; | |
3617 | base_offset = pos[0].off; | |
3618 | for (i = 1; i < 3; i++) | |
3619 | if (align < pos[i].align_to) | |
3620 | { | |
3621 | align = pos[i].align_to; | |
3622 | base_offset = pos[i].off; | |
3623 | } | |
3624 | for (i = 0; i < 3; i++) | |
3625 | pos[i].off -= base_offset; | |
3626 | } | |
3627 | ||
3628 | pos[0].off &= ~align + 1; | |
3629 | pos[1].off &= ~align + 1; | |
3630 | pos[2].off &= ~align + 1; | |
3631 | ||
3632 | /* If any two stores write to the same chunk, they also write to the | |
3633 | same doubleword. The offsets are still sorted at this point. */ | |
3634 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3635 | return 0; | |
3636 | ||
3637 | /* A range of at least 9 bytes is needed for the stores to be in | |
3638 | non-overlapping doublewords. */ | |
3639 | if (pos[2].off - pos[0].off <= 8) | |
3640 | return 0; | |
3641 | ||
3642 | if (pos[2].off - pos[1].off >= 24 | |
3643 | || pos[1].off - pos[0].off >= 24 | |
3644 | || pos[2].off - pos[0].off >= 32) | |
3645 | return 0; | |
3646 | ||
3647 | return 1; | |
3648 | } | |
3649 | ||
71400594 | 3650 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3651 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3652 | where HIST[0] is the most recent instruction. Ignore hazards |
3653 | between INSN and the first IGNORE instructions in HIST. | |
3654 | ||
3655 | If INSN is null, return the worse-case number of nops for any | |
3656 | instruction. */ | |
bdaaa2e1 | 3657 | |
71400594 | 3658 | static int |
932d1a1b | 3659 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3660 | const struct mips_cl_insn *insn) |
3661 | { | |
3662 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3663 | |
71400594 | 3664 | nops = 0; |
932d1a1b | 3665 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3666 | { |
91d6fa6a | 3667 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3668 | if (tmp_nops > nops) |
3669 | nops = tmp_nops; | |
3670 | } | |
7d8e00cf | 3671 | |
df58fc94 | 3672 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3673 | { |
932d1a1b | 3674 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3675 | if (tmp_nops > nops) |
3676 | nops = tmp_nops; | |
3677 | } | |
3678 | ||
df58fc94 | 3679 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3680 | { |
932d1a1b | 3681 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3682 | if (tmp_nops > nops) |
3683 | nops = tmp_nops; | |
3684 | } | |
3685 | ||
71400594 RS |
3686 | return nops; |
3687 | } | |
252b5132 | 3688 | |
71400594 | 3689 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3690 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3691 | would be needed after the extended sequence, ignoring hazards |
3692 | in the first IGNORE instructions. */ | |
252b5132 | 3693 | |
71400594 | 3694 | static int |
932d1a1b RS |
3695 | nops_for_sequence (int num_insns, int ignore, |
3696 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3697 | { |
3698 | va_list args; | |
3699 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3700 | struct mips_cl_insn *cursor; | |
3701 | int nops; | |
3702 | ||
91d6fa6a | 3703 | va_start (args, hist); |
71400594 | 3704 | cursor = buffer + num_insns; |
91d6fa6a | 3705 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3706 | while (cursor > buffer) |
3707 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3708 | ||
932d1a1b | 3709 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3710 | va_end (args); |
3711 | return nops; | |
3712 | } | |
252b5132 | 3713 | |
71400594 RS |
3714 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3715 | worst-case delay for the branch target. */ | |
252b5132 | 3716 | |
71400594 | 3717 | static int |
932d1a1b | 3718 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3719 | const struct mips_cl_insn *insn) |
3720 | { | |
3721 | int nops, tmp_nops; | |
60b63b72 | 3722 | |
932d1a1b | 3723 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3724 | if (delayed_branch_p (insn)) |
71400594 | 3725 | { |
932d1a1b | 3726 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3727 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3728 | if (tmp_nops > nops) |
3729 | nops = tmp_nops; | |
3730 | } | |
11625dd8 | 3731 | else if (compact_branch_p (insn)) |
71400594 | 3732 | { |
932d1a1b | 3733 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3734 | if (tmp_nops > nops) |
3735 | nops = tmp_nops; | |
3736 | } | |
3737 | return nops; | |
3738 | } | |
3739 | ||
c67a084a NC |
3740 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3741 | ||
3742 | static void | |
3743 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3744 | { | |
df58fc94 | 3745 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3746 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3747 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3748 | } | |
3749 | ||
3750 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3751 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3752 | ||
3753 | static void | |
3754 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3755 | { | |
df58fc94 | 3756 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3757 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3758 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3759 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3760 | { | |
3761 | int sreg; | |
3762 | expressionS ep; | |
3763 | ||
3764 | if (! mips_opts.at) | |
3765 | return; | |
3766 | ||
df58fc94 | 3767 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3768 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3769 | return; | |
3770 | ||
3771 | ep.X_op = O_constant; | |
3772 | ep.X_add_number = 0xcfff0000; | |
3773 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3774 | ep.X_add_number = 0xffff; | |
3775 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3776 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3777 | } | |
3778 | } | |
3779 | ||
3780 | static void | |
3781 | fix_loongson2f (struct mips_cl_insn * ip) | |
3782 | { | |
3783 | if (mips_fix_loongson2f_nop) | |
3784 | fix_loongson2f_nop (ip); | |
3785 | ||
3786 | if (mips_fix_loongson2f_jump) | |
3787 | fix_loongson2f_jump (ip); | |
3788 | } | |
3789 | ||
a4e06468 RS |
3790 | /* IP is a branch that has a delay slot, and we need to fill it |
3791 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3792 | with the previous instruction. |
3793 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3794 | RELOC_TYPE. */ | |
a4e06468 RS |
3795 | |
3796 | static bfd_boolean | |
e407c74b NC |
3797 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3798 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3799 | { |
2b0c8b40 | 3800 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3801 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3802 | ||
3803 | /* -O2 and above is required for this optimization. */ | |
3804 | if (mips_optimize < 2) | |
3805 | return FALSE; | |
3806 | ||
3807 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3808 | if (mips_opts.nomove) | |
3809 | return FALSE; | |
3810 | ||
3811 | /* We can't swap if the previous instruction's position is fixed. */ | |
3812 | if (history[0].fixed_p) | |
3813 | return FALSE; | |
3814 | ||
3815 | /* If the previous previous insn was in a .set noreorder, we can't | |
3816 | swap. Actually, the MIPS assembler will swap in this situation. | |
3817 | However, gcc configured -with-gnu-as will generate code like | |
3818 | ||
3819 | .set noreorder | |
3820 | lw $4,XXX | |
3821 | .set reorder | |
3822 | INSN | |
3823 | bne $4,$0,foo | |
3824 | ||
3825 | in which we can not swap the bne and INSN. If gcc is not configured | |
3826 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3827 | if (history[1].noreorder_p) | |
3828 | return FALSE; | |
3829 | ||
87333bb7 MR |
3830 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3831 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3832 | if (mips_opts.mips16 && history[0].fixp[0]) |
3833 | return FALSE; | |
3834 | ||
3835 | /* If the branch is itself the target of a branch, we can not swap. | |
3836 | We cheat on this; all we check for is whether there is a label on | |
3837 | this instruction. If there are any branches to anything other than | |
3838 | a label, users must use .set noreorder. */ | |
3839 | if (seg_info (now_seg)->label_list) | |
3840 | return FALSE; | |
3841 | ||
3842 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3843 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3844 | MIPS16 code, which uses variant frags for different purposes. */ |
3845 | if (!mips_opts.mips16 | |
a4e06468 RS |
3846 | && history[0].frag |
3847 | && history[0].frag->fr_type == rs_machine_dependent) | |
3848 | return FALSE; | |
3849 | ||
bcd530a7 RS |
3850 | /* We do not swap with instructions that cannot architecturally |
3851 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3852 | also refrain from swapping with a trap instruction, since it | |
3853 | complicates trap handlers to have the trap instruction be in | |
3854 | a delay slot. */ | |
a4e06468 | 3855 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3856 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3857 | return FALSE; |
3858 | ||
3859 | /* Check for conflicts between the branch and the instructions | |
3860 | before the candidate delay slot. */ | |
3861 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3862 | return FALSE; | |
3863 | ||
3864 | /* Check for conflicts between the swapped sequence and the | |
3865 | target of the branch. */ | |
3866 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3867 | return FALSE; | |
3868 | ||
3869 | /* If the branch reads a register that the previous | |
3870 | instruction sets, we can not swap. */ | |
3871 | gpr_read = gpr_read_mask (ip); | |
3872 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3873 | if (gpr_read & prev_gpr_write) | |
3874 | return FALSE; | |
3875 | ||
3876 | /* If the branch writes a register that the previous | |
3877 | instruction sets, we can not swap. */ | |
3878 | gpr_write = gpr_write_mask (ip); | |
3879 | if (gpr_write & prev_gpr_write) | |
3880 | return FALSE; | |
3881 | ||
3882 | /* If the branch writes a register that the previous | |
3883 | instruction reads, we can not swap. */ | |
3884 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3885 | if (gpr_write & prev_gpr_read) | |
3886 | return FALSE; | |
3887 | ||
3888 | /* If one instruction sets a condition code and the | |
3889 | other one uses a condition code, we can not swap. */ | |
3890 | pinfo = ip->insn_mo->pinfo; | |
3891 | if ((pinfo & INSN_READ_COND_CODE) | |
3892 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3893 | return FALSE; | |
3894 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3895 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3896 | return FALSE; | |
3897 | ||
3898 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3899 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3900 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3901 | return FALSE; | |
2b0c8b40 MR |
3902 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3903 | return FALSE; | |
a4e06468 | 3904 | |
df58fc94 RS |
3905 | /* If the previous instruction has an incorrect size for a fixed |
3906 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3907 | pinfo2 = ip->insn_mo->pinfo2; |
3908 | if (mips_opts.micromips | |
3909 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3910 | && insn_length (history) != 2) | |
3911 | return FALSE; | |
3912 | if (mips_opts.micromips | |
3913 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3914 | && insn_length (history) != 4) | |
3915 | return FALSE; | |
3916 | ||
e407c74b NC |
3917 | /* On R5900 short loops need to be fixed by inserting a nop in |
3918 | the branch delay slots. | |
3919 | A short loop can be terminated too early. */ | |
3920 | if (mips_opts.arch == CPU_R5900 | |
3921 | /* Check if instruction has a parameter, ignore "j $31". */ | |
3922 | && (address_expr != NULL) | |
3923 | /* Parameter must be 16 bit. */ | |
3924 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
3925 | /* Branch to same segment. */ | |
3926 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
3927 | /* Branch to same code fragment. */ | |
3928 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
3929 | /* Can only calculate branch offset if value is known. */ | |
3930 | && symbol_constant_p(address_expr->X_add_symbol) | |
3931 | /* Check if branch is really conditional. */ | |
3932 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
3933 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
3934 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
3935 | { | |
3936 | int distance; | |
3937 | /* Check if loop is shorter than 6 instructions including | |
3938 | branch and delay slot. */ | |
3939 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
3940 | if (distance <= 20) | |
3941 | { | |
3942 | int i; | |
3943 | int rv; | |
3944 | ||
3945 | rv = FALSE; | |
3946 | /* When the loop includes branches or jumps, | |
3947 | it is not a short loop. */ | |
3948 | for (i = 0; i < (distance / 4); i++) | |
3949 | { | |
3950 | if ((history[i].cleared_p) | |
3951 | || delayed_branch_p(&history[i])) | |
3952 | { | |
3953 | rv = TRUE; | |
3954 | break; | |
3955 | } | |
3956 | } | |
3957 | if (rv == FALSE) | |
3958 | { | |
3959 | /* Insert nop after branch to fix short loop. */ | |
3960 | return FALSE; | |
3961 | } | |
3962 | } | |
3963 | } | |
3964 | ||
a4e06468 RS |
3965 | return TRUE; |
3966 | } | |
3967 | ||
e407c74b NC |
3968 | /* Decide how we should add IP to the instruction stream. |
3969 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3970 | RELOC_TYPE. */ | |
a4e06468 RS |
3971 | |
3972 | static enum append_method | |
e407c74b NC |
3973 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
3974 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
3975 | { |
3976 | unsigned long pinfo; | |
3977 | ||
3978 | /* The relaxed version of a macro sequence must be inherently | |
3979 | hazard-free. */ | |
3980 | if (mips_relax.sequence == 2) | |
3981 | return APPEND_ADD; | |
3982 | ||
3983 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3984 | if (mips_opts.noreorder) | |
3985 | return APPEND_ADD; | |
3986 | ||
3987 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3988 | if (delayed_branch_p (ip)) |
a4e06468 | 3989 | { |
e407c74b NC |
3990 | if (!branch_likely_p (ip) |
3991 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
3992 | return APPEND_SWAP; |
3993 | ||
11625dd8 | 3994 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3995 | if (mips_opts.mips16 |
3996 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3997 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3998 | return APPEND_ADD_COMPACT; | |
3999 | ||
4000 | return APPEND_ADD_WITH_NOP; | |
4001 | } | |
4002 | ||
a4e06468 RS |
4003 | return APPEND_ADD; |
4004 | } | |
4005 | ||
ceb94aa5 RS |
4006 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4007 | Point IP->insn_mo to the new opcode's definition. */ | |
4008 | ||
4009 | static void | |
4010 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4011 | { | |
4012 | const struct mips_opcode *mo, *end; | |
4013 | ||
4014 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4015 | for (mo = ip->insn_mo; mo < end; mo++) | |
4016 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4017 | { | |
4018 | ip->insn_mo = mo; | |
4019 | return; | |
4020 | } | |
4021 | abort (); | |
4022 | } | |
4023 | ||
df58fc94 RS |
4024 | /* For microMIPS macros, we need to generate a local number label |
4025 | as the target of branches. */ | |
4026 | #define MICROMIPS_LABEL_CHAR '\037' | |
4027 | static unsigned long micromips_target_label; | |
4028 | static char micromips_target_name[32]; | |
4029 | ||
4030 | static char * | |
4031 | micromips_label_name (void) | |
4032 | { | |
4033 | char *p = micromips_target_name; | |
4034 | char symbol_name_temporary[24]; | |
4035 | unsigned long l; | |
4036 | int i; | |
4037 | ||
4038 | if (*p) | |
4039 | return p; | |
4040 | ||
4041 | i = 0; | |
4042 | l = micromips_target_label; | |
4043 | #ifdef LOCAL_LABEL_PREFIX | |
4044 | *p++ = LOCAL_LABEL_PREFIX; | |
4045 | #endif | |
4046 | *p++ = 'L'; | |
4047 | *p++ = MICROMIPS_LABEL_CHAR; | |
4048 | do | |
4049 | { | |
4050 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4051 | l /= 10; | |
4052 | } | |
4053 | while (l != 0); | |
4054 | while (i > 0) | |
4055 | *p++ = symbol_name_temporary[--i]; | |
4056 | *p = '\0'; | |
4057 | ||
4058 | return micromips_target_name; | |
4059 | } | |
4060 | ||
4061 | static void | |
4062 | micromips_label_expr (expressionS *label_expr) | |
4063 | { | |
4064 | label_expr->X_op = O_symbol; | |
4065 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4066 | label_expr->X_add_number = 0; | |
4067 | } | |
4068 | ||
4069 | static void | |
4070 | micromips_label_inc (void) | |
4071 | { | |
4072 | micromips_target_label++; | |
4073 | *micromips_target_name = '\0'; | |
4074 | } | |
4075 | ||
4076 | static void | |
4077 | micromips_add_label (void) | |
4078 | { | |
4079 | symbolS *s; | |
4080 | ||
4081 | s = colon (micromips_label_name ()); | |
4082 | micromips_label_inc (); | |
4083 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4084 | if (IS_ELF) | |
4085 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4086 | #else |
4087 | (void) s; | |
df58fc94 RS |
4088 | #endif |
4089 | } | |
4090 | ||
4091 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4092 | corresponding to the requested one if any. Otherwise return | |
4093 | the reloc unchanged. */ | |
4094 | ||
4095 | static bfd_reloc_code_real_type | |
4096 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4097 | { | |
4098 | static const bfd_reloc_code_real_type relocs[][2] = | |
4099 | { | |
4100 | /* Keep sorted incrementally by the left-hand key. */ | |
4101 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4102 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4103 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4104 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4105 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4106 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4107 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4108 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4109 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4110 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4111 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4112 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4113 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4114 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4115 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4116 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4117 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4118 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4119 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4120 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4121 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4122 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4123 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4124 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4125 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4126 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4127 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4128 | }; | |
4129 | bfd_reloc_code_real_type r; | |
4130 | size_t i; | |
4131 | ||
4132 | if (!mips_opts.micromips) | |
4133 | return reloc; | |
4134 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4135 | { | |
4136 | r = relocs[i][0]; | |
4137 | if (r > reloc) | |
4138 | return reloc; | |
4139 | if (r == reloc) | |
4140 | return relocs[i][1]; | |
4141 | } | |
4142 | return reloc; | |
4143 | } | |
4144 | ||
b886a2ab RS |
4145 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4146 | Return true on success, storing the resolved value in RESULT. */ | |
4147 | ||
4148 | static bfd_boolean | |
4149 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4150 | offsetT *result) | |
4151 | { | |
4152 | switch (reloc) | |
4153 | { | |
4154 | case BFD_RELOC_MIPS_HIGHEST: | |
4155 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4156 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4157 | return TRUE; | |
4158 | ||
4159 | case BFD_RELOC_MIPS_HIGHER: | |
4160 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4161 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4162 | return TRUE; | |
4163 | ||
4164 | case BFD_RELOC_HI16_S: | |
4165 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4166 | case BFD_RELOC_MIPS16_HI16_S: | |
4167 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4168 | return TRUE; | |
4169 | ||
4170 | case BFD_RELOC_HI16: | |
4171 | case BFD_RELOC_MICROMIPS_HI16: | |
4172 | case BFD_RELOC_MIPS16_HI16: | |
4173 | *result = (operand >> 16) & 0xffff; | |
4174 | return TRUE; | |
4175 | ||
4176 | case BFD_RELOC_LO16: | |
4177 | case BFD_RELOC_MICROMIPS_LO16: | |
4178 | case BFD_RELOC_MIPS16_LO16: | |
4179 | *result = operand & 0xffff; | |
4180 | return TRUE; | |
4181 | ||
4182 | case BFD_RELOC_UNUSED: | |
4183 | *result = operand; | |
4184 | return TRUE; | |
4185 | ||
4186 | default: | |
4187 | return FALSE; | |
4188 | } | |
4189 | } | |
4190 | ||
71400594 RS |
4191 | /* Output an instruction. IP is the instruction information. |
4192 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4193 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4194 | a macro expansion. */ | |
71400594 RS |
4195 | |
4196 | static void | |
4197 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4198 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4199 | { |
14fe068b | 4200 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4201 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4202 | enum append_method method; |
2309ddf2 | 4203 | bfd_boolean relax32; |
2b0c8b40 | 4204 | int branch_disp; |
71400594 | 4205 | |
2309ddf2 | 4206 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4207 | fix_loongson2f (ip); |
4208 | ||
738f4d98 | 4209 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4210 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4211 | |
df58fc94 | 4212 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4213 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4214 | |
4215 | if (mips_opts.micromips | |
4216 | && !expansionp | |
4217 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4218 | && micromips_insn_length (ip->insn_mo) != 2) | |
4219 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4220 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4221 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4222 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4223 | |
15be625d CM |
4224 | if (address_expr == NULL) |
4225 | ip->complete_p = 1; | |
b886a2ab RS |
4226 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4227 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4228 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4229 | && address_expr->X_op == O_constant) |
4230 | { | |
15be625d CM |
4231 | switch (*reloc_type) |
4232 | { | |
15be625d | 4233 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4234 | { |
4235 | int shift; | |
4236 | ||
4237 | shift = mips_opts.micromips ? 1 : 2; | |
4238 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4239 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4240 | (unsigned long) address_expr->X_add_number); | |
4241 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4242 | & 0x3ffffff); | |
335574df | 4243 | ip->complete_p = 1; |
df58fc94 | 4244 | } |
15be625d CM |
4245 | break; |
4246 | ||
4247 | case BFD_RELOC_MIPS16_JMP: | |
4248 | if ((address_expr->X_add_number & 3) != 0) | |
4249 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4250 | (unsigned long) address_expr->X_add_number); | |
4251 | ip->insn_opcode |= | |
4252 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4253 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4254 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4255 | ip->complete_p = 1; |
15be625d CM |
4256 | break; |
4257 | ||
4258 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4259 | { |
4260 | int shift; | |
4261 | ||
4262 | shift = mips_opts.micromips ? 1 : 2; | |
4263 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4264 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4265 | (unsigned long) address_expr->X_add_number); | |
4266 | if (!mips_relax_branch) | |
4267 | { | |
4268 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4269 | & ~((1 << (shift + 16)) - 1)) | |
4270 | as_bad (_("branch address range overflow (0x%lx)"), | |
4271 | (unsigned long) address_expr->X_add_number); | |
4272 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4273 | & 0xffff); | |
4274 | } | |
df58fc94 | 4275 | } |
15be625d CM |
4276 | break; |
4277 | ||
4278 | default: | |
b886a2ab RS |
4279 | { |
4280 | offsetT value; | |
4281 | ||
4282 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4283 | &value)) | |
4284 | { | |
4285 | ip->insn_opcode |= value & 0xffff; | |
4286 | ip->complete_p = 1; | |
4287 | } | |
4288 | } | |
4289 | break; | |
4290 | } | |
15be625d CM |
4291 | } |
4292 | ||
71400594 RS |
4293 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4294 | { | |
4295 | /* There are a lot of optimizations we could do that we don't. | |
4296 | In particular, we do not, in general, reorder instructions. | |
4297 | If you use gcc with optimization, it will reorder | |
4298 | instructions and generally do much more optimization then we | |
4299 | do here; repeating all that work in the assembler would only | |
4300 | benefit hand written assembly code, and does not seem worth | |
4301 | it. */ | |
4302 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4303 | ? nops_for_insn (0, history, NULL) |
4304 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4305 | if (nops > 0) |
252b5132 RH |
4306 | { |
4307 | fragS *old_frag; | |
4308 | unsigned long old_frag_offset; | |
4309 | int i; | |
252b5132 RH |
4310 | |
4311 | old_frag = frag_now; | |
4312 | old_frag_offset = frag_now_fix (); | |
4313 | ||
4314 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4315 | add_fixed_insn (NOP_INSN); |
4316 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4317 | |
4318 | if (listing) | |
4319 | { | |
4320 | listing_prev_line (); | |
4321 | /* We may be at the start of a variant frag. In case we | |
4322 | are, make sure there is enough space for the frag | |
4323 | after the frags created by listing_prev_line. The | |
4324 | argument to frag_grow here must be at least as large | |
4325 | as the argument to all other calls to frag_grow in | |
4326 | this file. We don't have to worry about being in the | |
4327 | middle of a variant frag, because the variants insert | |
4328 | all needed nop instructions themselves. */ | |
4329 | frag_grow (40); | |
4330 | } | |
4331 | ||
462427c4 | 4332 | mips_move_text_labels (); |
252b5132 RH |
4333 | |
4334 | #ifndef NO_ECOFF_DEBUGGING | |
4335 | if (ECOFF_DEBUGGING) | |
4336 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4337 | #endif | |
4338 | } | |
71400594 RS |
4339 | } |
4340 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4341 | { | |
932d1a1b RS |
4342 | int nops; |
4343 | ||
4344 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4345 | ignoring hazards generated by the first prev_nop_frag_since | |
4346 | instructions. */ | |
4347 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4348 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4349 | |
71400594 RS |
4350 | /* Enforce NOPS as a minimum. */ |
4351 | if (nops > prev_nop_frag_required) | |
4352 | prev_nop_frag_required = nops; | |
252b5132 | 4353 | |
71400594 RS |
4354 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4355 | { | |
4356 | /* Settle for the current number of nops. Update the history | |
4357 | accordingly (for the benefit of any future .set reorder code). */ | |
4358 | prev_nop_frag = NULL; | |
4359 | insert_into_history (prev_nop_frag_since, | |
4360 | prev_nop_frag_holds, NOP_INSN); | |
4361 | } | |
4362 | else | |
4363 | { | |
4364 | /* Allow this instruction to replace one of the nops that was | |
4365 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4366 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4367 | prev_nop_frag_holds--; |
4368 | prev_nop_frag_since++; | |
252b5132 RH |
4369 | } |
4370 | } | |
4371 | ||
e407c74b | 4372 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4373 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4374 | |
58e2ea4d MR |
4375 | #ifdef OBJ_ELF |
4376 | /* The value passed to dwarf2_emit_insn is the distance between | |
4377 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4378 | should be recorded in the debug tables. This is normally the |
4379 | current address. | |
4380 | ||
df58fc94 RS |
4381 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4382 | addresses, so we use -1 for an address higher by one than the | |
4383 | current one. | |
e3a82c8e MR |
4384 | |
4385 | If the instruction produced is a branch that we will swap with | |
4386 | the preceding instruction, then we add the displacement by which | |
4387 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4388 | and for MIPS16/microMIPS code also prevents a debugger from |
4389 | placing a breakpoint in the middle of the branch (and corrupting | |
4390 | code if software breakpoints are used). */ | |
2b0c8b40 | 4391 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4392 | #endif |
4393 | ||
df58fc94 RS |
4394 | relax32 = (mips_relax_branch |
4395 | /* Don't try branch relaxation within .set nomacro, or within | |
4396 | .set noat if we use $at for PIC computations. If it turns | |
4397 | out that the branch was out-of-range, we'll get an error. */ | |
4398 | && !mips_opts.warn_about_macros | |
4399 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4400 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4401 | as they have no complementing branches. */ | |
4402 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4403 | |
4404 | if (!HAVE_CODE_COMPRESSION | |
4405 | && address_expr | |
4406 | && relax32 | |
0b25d3e6 | 4407 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4408 | && delayed_branch_p (ip)) |
4a6a3df4 | 4409 | { |
895921c9 | 4410 | relaxed_branch = TRUE; |
1e915849 RS |
4411 | add_relaxed_insn (ip, (relaxed_branch_length |
4412 | (NULL, NULL, | |
11625dd8 RS |
4413 | uncond_branch_p (ip) ? -1 |
4414 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4415 | : 0)), 4, |
4416 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4417 | (AT, |
11625dd8 RS |
4418 | uncond_branch_p (ip), |
4419 | branch_likely_p (ip), | |
1e915849 RS |
4420 | pinfo & INSN_WRITE_GPR_31, |
4421 | 0), | |
4422 | address_expr->X_add_symbol, | |
4423 | address_expr->X_add_number); | |
4a6a3df4 AO |
4424 | *reloc_type = BFD_RELOC_UNUSED; |
4425 | } | |
df58fc94 RS |
4426 | else if (mips_opts.micromips |
4427 | && address_expr | |
4428 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4429 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4430 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4431 | /* Don't try branch relaxation when users specify | |
4432 | 16-bit/32-bit instructions. */ | |
4433 | && !forced_insn_length) | |
df58fc94 RS |
4434 | { |
4435 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4436 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4437 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4438 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4439 | int al = pinfo & INSN_WRITE_GPR_31; |
4440 | int length32; | |
4441 | ||
4442 | gas_assert (address_expr != NULL); | |
4443 | gas_assert (!mips_relax.sequence); | |
4444 | ||
2b0c8b40 | 4445 | relaxed_branch = TRUE; |
df58fc94 RS |
4446 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4447 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4448 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4449 | relax32, 0, 0), | |
df58fc94 RS |
4450 | address_expr->X_add_symbol, |
4451 | address_expr->X_add_number); | |
4452 | *reloc_type = BFD_RELOC_UNUSED; | |
4453 | } | |
4454 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4455 | { |
4456 | /* We need to set up a variant frag. */ | |
df58fc94 | 4457 | gas_assert (address_expr != NULL); |
1e915849 RS |
4458 | add_relaxed_insn (ip, 4, 0, |
4459 | RELAX_MIPS16_ENCODE | |
4460 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4461 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4462 | delayed_branch_p (&history[0]), |
1e915849 RS |
4463 | history[0].mips16_absolute_jump_p), |
4464 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4465 | } |
5c04167a | 4466 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4467 | { |
11625dd8 | 4468 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4469 | /* Make sure there is enough room to swap this instruction with |
4470 | a following jump instruction. */ | |
4471 | frag_grow (6); | |
1e915849 | 4472 | add_fixed_insn (ip); |
252b5132 RH |
4473 | } |
4474 | else | |
4475 | { | |
4476 | if (mips_opts.mips16 | |
4477 | && mips_opts.noreorder | |
11625dd8 | 4478 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4479 | as_warn (_("extended instruction in delay slot")); |
4480 | ||
4d7206a2 RS |
4481 | if (mips_relax.sequence) |
4482 | { | |
4483 | /* If we've reached the end of this frag, turn it into a variant | |
4484 | frag and record the information for the instructions we've | |
4485 | written so far. */ | |
4486 | if (frag_room () < 4) | |
4487 | relax_close_frag (); | |
df58fc94 | 4488 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4489 | } |
4490 | ||
584892a6 | 4491 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4492 | { |
4493 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4494 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4495 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4496 | mips_macro_warning.insns[0]++; | |
4497 | } | |
584892a6 | 4498 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4499 | { |
4500 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4501 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4502 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4503 | mips_macro_warning.insns[1]++; | |
4504 | } | |
584892a6 | 4505 | |
1e915849 RS |
4506 | if (mips_opts.mips16) |
4507 | { | |
4508 | ip->fixed_p = 1; | |
4509 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4510 | } | |
4511 | add_fixed_insn (ip); | |
252b5132 RH |
4512 | } |
4513 | ||
9fe77896 | 4514 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4515 | { |
df58fc94 | 4516 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4517 | reloc_howto_type *howto0; |
9fe77896 RS |
4518 | reloc_howto_type *howto; |
4519 | int i; | |
34ce925e | 4520 | |
df58fc94 RS |
4521 | /* Perform any necessary conversion to microMIPS relocations |
4522 | and find out how many relocations there actually are. */ | |
4523 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4524 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4525 | ||
9fe77896 RS |
4526 | /* In a compound relocation, it is the final (outermost) |
4527 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4528 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4529 | ||
9fe77896 RS |
4530 | if (howto == NULL) |
4531 | { | |
4532 | /* To reproduce this failure try assembling gas/testsuites/ | |
4533 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4534 | assembler. */ | |
df58fc94 RS |
4535 | as_bad (_("Unsupported MIPS relocation number %d"), |
4536 | final_type[i - 1]); | |
9fe77896 RS |
4537 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4538 | } | |
2309ddf2 MR |
4539 | |
4540 | if (i > 1) | |
4541 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4542 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4543 | bfd_get_reloc_size (howto), | |
4544 | address_expr, | |
2309ddf2 MR |
4545 | howto0 && howto0->pc_relative, |
4546 | final_type[0]); | |
9fe77896 RS |
4547 | |
4548 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4549 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4550 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4551 | ||
4552 | /* These relocations can have an addend that won't fit in | |
4553 | 4 octets for 64bit assembly. */ | |
4554 | if (HAVE_64BIT_GPRS | |
4555 | && ! howto->partial_inplace | |
4556 | && (reloc_type[0] == BFD_RELOC_16 | |
4557 | || reloc_type[0] == BFD_RELOC_32 | |
4558 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4559 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4560 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4561 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4562 | || reloc_type[0] == BFD_RELOC_64 | |
4563 | || reloc_type[0] == BFD_RELOC_CTOR | |
4564 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4565 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4566 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4567 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4568 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4569 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4570 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4571 | || hi16_reloc_p (reloc_type[0]) | |
4572 | || lo16_reloc_p (reloc_type[0]))) | |
4573 | ip->fixp[0]->fx_no_overflow = 1; | |
4574 | ||
ddaf2c41 MR |
4575 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4576 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4577 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4578 | ip->fixp[0]->fx_no_overflow = 1; | |
4579 | ||
9fe77896 RS |
4580 | if (mips_relax.sequence) |
4581 | { | |
4582 | if (mips_relax.first_fixup == 0) | |
4583 | mips_relax.first_fixup = ip->fixp[0]; | |
4584 | } | |
4585 | else if (reloc_needs_lo_p (*reloc_type)) | |
4586 | { | |
4587 | struct mips_hi_fixup *hi_fixup; | |
4588 | ||
4589 | /* Reuse the last entry if it already has a matching %lo. */ | |
4590 | hi_fixup = mips_hi_fixup_list; | |
4591 | if (hi_fixup == 0 | |
4592 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4593 | { |
9fe77896 RS |
4594 | hi_fixup = ((struct mips_hi_fixup *) |
4595 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4596 | hi_fixup->next = mips_hi_fixup_list; | |
4597 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4598 | } |
9fe77896 RS |
4599 | hi_fixup->fixp = ip->fixp[0]; |
4600 | hi_fixup->seg = now_seg; | |
4601 | } | |
252b5132 | 4602 | |
9fe77896 RS |
4603 | /* Add fixups for the second and third relocations, if given. |
4604 | Note that the ABI allows the second relocation to be | |
4605 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4606 | moment we only use RSS_UNDEF, but we could add support | |
4607 | for the others if it ever becomes necessary. */ | |
4608 | for (i = 1; i < 3; i++) | |
4609 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4610 | { | |
4611 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4612 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4613 | FALSE, final_type[i]); |
f6688943 | 4614 | |
9fe77896 RS |
4615 | /* Use fx_tcbit to mark compound relocs. */ |
4616 | ip->fixp[0]->fx_tcbit = 1; | |
4617 | ip->fixp[i]->fx_tcbit = 1; | |
4618 | } | |
252b5132 | 4619 | } |
1e915849 | 4620 | install_insn (ip); |
252b5132 RH |
4621 | |
4622 | /* Update the register mask information. */ | |
4c260379 RS |
4623 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4624 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4625 | |
a4e06468 | 4626 | switch (method) |
252b5132 | 4627 | { |
a4e06468 RS |
4628 | case APPEND_ADD: |
4629 | insert_into_history (0, 1, ip); | |
4630 | break; | |
4631 | ||
4632 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4633 | { |
4634 | struct mips_cl_insn *nop; | |
4635 | ||
4636 | insert_into_history (0, 1, ip); | |
4637 | nop = get_delay_slot_nop (ip); | |
4638 | add_fixed_insn (nop); | |
4639 | insert_into_history (0, 1, nop); | |
4640 | if (mips_relax.sequence) | |
4641 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4642 | } | |
a4e06468 RS |
4643 | break; |
4644 | ||
4645 | case APPEND_ADD_COMPACT: | |
4646 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4647 | gas_assert (mips_opts.mips16); | |
4648 | ip->insn_opcode |= 0x0080; | |
4649 | find_altered_mips16_opcode (ip); | |
4650 | install_insn (ip); | |
4651 | insert_into_history (0, 1, ip); | |
4652 | break; | |
4653 | ||
4654 | case APPEND_SWAP: | |
4655 | { | |
4656 | struct mips_cl_insn delay = history[0]; | |
4657 | if (mips_opts.mips16) | |
4658 | { | |
4659 | know (delay.frag == ip->frag); | |
4660 | move_insn (ip, delay.frag, delay.where); | |
4661 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4662 | } | |
464ab0e5 | 4663 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4664 | { |
4665 | /* Add the delay slot instruction to the end of the | |
4666 | current frag and shrink the fixed part of the | |
4667 | original frag. If the branch occupies the tail of | |
4668 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4669 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4670 | if (delay.frag == ip->frag) |
2b0c8b40 | 4671 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4672 | add_fixed_insn (&delay); |
4673 | } | |
4674 | else | |
4675 | { | |
2b0c8b40 MR |
4676 | move_insn (&delay, ip->frag, |
4677 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4678 | move_insn (ip, history[0].frag, history[0].where); |
4679 | } | |
4680 | history[0] = *ip; | |
4681 | delay.fixed_p = 1; | |
4682 | insert_into_history (0, 1, &delay); | |
4683 | } | |
4684 | break; | |
252b5132 RH |
4685 | } |
4686 | ||
13408f1e | 4687 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4688 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4689 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4690 | { |
4691 | unsigned int i; | |
4692 | ||
79850f26 | 4693 | mips_no_prev_insn (); |
13408f1e | 4694 | |
e407c74b | 4695 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4696 | history[i].cleared_p = 1; |
e407c74b NC |
4697 | } |
4698 | ||
df58fc94 RS |
4699 | /* We need to emit a label at the end of branch-likely macros. */ |
4700 | if (emit_branch_likely_macro) | |
4701 | { | |
4702 | emit_branch_likely_macro = FALSE; | |
4703 | micromips_add_label (); | |
4704 | } | |
4705 | ||
252b5132 RH |
4706 | /* We just output an insn, so the next one doesn't have a label. */ |
4707 | mips_clear_insn_labels (); | |
252b5132 RH |
4708 | } |
4709 | ||
e407c74b NC |
4710 | /* Forget that there was any previous instruction or label. |
4711 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4712 | |
4713 | static void | |
7d10b47d | 4714 | mips_no_prev_insn (void) |
252b5132 | 4715 | { |
7d10b47d RS |
4716 | prev_nop_frag = NULL; |
4717 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4718 | mips_clear_insn_labels (); |
4719 | } | |
4720 | ||
7d10b47d RS |
4721 | /* This function must be called before we emit something other than |
4722 | instructions. It is like mips_no_prev_insn except that it inserts | |
4723 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4724 | |
7d10b47d RS |
4725 | void |
4726 | mips_emit_delays (void) | |
252b5132 RH |
4727 | { |
4728 | if (! mips_opts.noreorder) | |
4729 | { | |
932d1a1b | 4730 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4731 | if (nops > 0) |
4732 | { | |
7d10b47d RS |
4733 | while (nops-- > 0) |
4734 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4735 | mips_move_text_labels (); |
7d10b47d RS |
4736 | } |
4737 | } | |
4738 | mips_no_prev_insn (); | |
4739 | } | |
4740 | ||
4741 | /* Start a (possibly nested) noreorder block. */ | |
4742 | ||
4743 | static void | |
4744 | start_noreorder (void) | |
4745 | { | |
4746 | if (mips_opts.noreorder == 0) | |
4747 | { | |
4748 | unsigned int i; | |
4749 | int nops; | |
4750 | ||
4751 | /* None of the instructions before the .set noreorder can be moved. */ | |
4752 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4753 | history[i].fixed_p = 1; | |
4754 | ||
4755 | /* Insert any nops that might be needed between the .set noreorder | |
4756 | block and the previous instructions. We will later remove any | |
4757 | nops that turn out not to be needed. */ | |
932d1a1b | 4758 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4759 | if (nops > 0) |
4760 | { | |
4761 | if (mips_optimize != 0) | |
252b5132 RH |
4762 | { |
4763 | /* Record the frag which holds the nop instructions, so | |
4764 | that we can remove them if we don't need them. */ | |
df58fc94 | 4765 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4766 | prev_nop_frag = frag_now; |
4767 | prev_nop_frag_holds = nops; | |
4768 | prev_nop_frag_required = 0; | |
4769 | prev_nop_frag_since = 0; | |
4770 | } | |
4771 | ||
4772 | for (; nops > 0; --nops) | |
1e915849 | 4773 | add_fixed_insn (NOP_INSN); |
252b5132 | 4774 | |
7d10b47d RS |
4775 | /* Move on to a new frag, so that it is safe to simply |
4776 | decrease the size of prev_nop_frag. */ | |
4777 | frag_wane (frag_now); | |
4778 | frag_new (0); | |
462427c4 | 4779 | mips_move_text_labels (); |
252b5132 | 4780 | } |
df58fc94 | 4781 | mips_mark_labels (); |
7d10b47d | 4782 | mips_clear_insn_labels (); |
252b5132 | 4783 | } |
7d10b47d RS |
4784 | mips_opts.noreorder++; |
4785 | mips_any_noreorder = 1; | |
4786 | } | |
252b5132 | 4787 | |
7d10b47d | 4788 | /* End a nested noreorder block. */ |
252b5132 | 4789 | |
7d10b47d RS |
4790 | static void |
4791 | end_noreorder (void) | |
4792 | { | |
4793 | mips_opts.noreorder--; | |
4794 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4795 | { | |
4796 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4797 | handling nop insertion the .set reorder way. */ | |
4798 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4799 | * NOP_INSN_SIZE); |
7d10b47d RS |
4800 | insert_into_history (prev_nop_frag_since, |
4801 | prev_nop_frag_required, NOP_INSN); | |
4802 | prev_nop_frag = NULL; | |
4803 | } | |
252b5132 RH |
4804 | } |
4805 | ||
584892a6 RS |
4806 | /* Set up global variables for the start of a new macro. */ |
4807 | ||
4808 | static void | |
4809 | macro_start (void) | |
4810 | { | |
4811 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4812 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4813 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4814 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4815 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4816 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4817 | switch (history[0].insn_mo->pinfo2 |
4818 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4819 | { | |
4820 | case INSN2_BRANCH_DELAY_32BIT: | |
4821 | mips_macro_warning.delay_slot_length = 4; | |
4822 | break; | |
4823 | case INSN2_BRANCH_DELAY_16BIT: | |
4824 | mips_macro_warning.delay_slot_length = 2; | |
4825 | break; | |
4826 | default: | |
4827 | mips_macro_warning.delay_slot_length = 0; | |
4828 | break; | |
4829 | } | |
4830 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4831 | } |
4832 | ||
df58fc94 RS |
4833 | /* Given that a macro is longer than one instruction or of the wrong size, |
4834 | return the appropriate warning for it. Return null if no warning is | |
4835 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4836 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4837 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4838 | |
4839 | static const char * | |
4840 | macro_warning (relax_substateT subtype) | |
4841 | { | |
4842 | if (subtype & RELAX_DELAY_SLOT) | |
4843 | return _("Macro instruction expanded into multiple instructions" | |
4844 | " in a branch delay slot"); | |
4845 | else if (subtype & RELAX_NOMACRO) | |
4846 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4847 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4848 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4849 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4850 | ? _("Macro instruction expanded into a wrong size instruction" | |
4851 | " in a 16-bit branch delay slot") | |
4852 | : _("Macro instruction expanded into a wrong size instruction" | |
4853 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4854 | else |
4855 | return 0; | |
4856 | } | |
4857 | ||
4858 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4859 | ||
4860 | static void | |
4861 | macro_end (void) | |
4862 | { | |
df58fc94 RS |
4863 | /* Relaxation warning flags. */ |
4864 | relax_substateT subtype = 0; | |
4865 | ||
4866 | /* Check delay slot size requirements. */ | |
4867 | if (mips_macro_warning.delay_slot_length == 2) | |
4868 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4869 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4870 | { |
df58fc94 RS |
4871 | if (mips_macro_warning.delay_slot_length |
4872 | != mips_macro_warning.first_insn_sizes[0]) | |
4873 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4874 | if (mips_macro_warning.delay_slot_length | |
4875 | != mips_macro_warning.first_insn_sizes[1]) | |
4876 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4877 | } | |
584892a6 | 4878 | |
df58fc94 RS |
4879 | /* Check instruction count requirements. */ |
4880 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4881 | { | |
4882 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4883 | subtype |= RELAX_SECOND_LONGER; |
4884 | if (mips_opts.warn_about_macros) | |
4885 | subtype |= RELAX_NOMACRO; | |
4886 | if (mips_macro_warning.delay_slot_p) | |
4887 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4888 | } |
584892a6 | 4889 | |
df58fc94 RS |
4890 | /* If both alternatives fail to fill a delay slot correctly, |
4891 | emit the warning now. */ | |
4892 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4893 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4894 | { | |
4895 | relax_substateT s; | |
4896 | const char *msg; | |
4897 | ||
4898 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4899 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4900 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4901 | msg = macro_warning (s); | |
4902 | if (msg != NULL) | |
4903 | as_warn ("%s", msg); | |
4904 | subtype &= ~s; | |
4905 | } | |
4906 | ||
4907 | /* If both implementations are longer than 1 instruction, then emit the | |
4908 | warning now. */ | |
4909 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4910 | { | |
4911 | relax_substateT s; | |
4912 | const char *msg; | |
4913 | ||
4914 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4915 | msg = macro_warning (s); | |
4916 | if (msg != NULL) | |
4917 | as_warn ("%s", msg); | |
4918 | subtype &= ~s; | |
584892a6 | 4919 | } |
df58fc94 RS |
4920 | |
4921 | /* If any flags still set, then one implementation might need a warning | |
4922 | and the other either will need one of a different kind or none at all. | |
4923 | Pass any remaining flags over to relaxation. */ | |
4924 | if (mips_macro_warning.first_frag != NULL) | |
4925 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4926 | } |
4927 | ||
df58fc94 RS |
4928 | /* Instruction operand formats used in macros that vary between |
4929 | standard MIPS and microMIPS code. */ | |
4930 | ||
4931 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4932 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4933 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4934 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4935 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4936 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4937 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4938 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4939 | ||
4940 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4941 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4942 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4943 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4944 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4945 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4946 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4947 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4948 | ||
6e1304d8 RS |
4949 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4950 | The first argument in *ARGS will be either the code for a single | |
4951 | relocation or -1 followed by the three codes that make up a | |
4952 | composite relocation. */ | |
4953 | ||
4954 | static void | |
4955 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4956 | { | |
4957 | int i, next; | |
4958 | ||
4959 | next = va_arg (*args, int); | |
4960 | if (next >= 0) | |
4961 | r[0] = (bfd_reloc_code_real_type) next; | |
4962 | else | |
4963 | for (i = 0; i < 3; i++) | |
4964 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4965 | } | |
4966 | ||
252b5132 RH |
4967 | /* Build an instruction created by a macro expansion. This is passed |
4968 | a pointer to the count of instructions created so far, an | |
4969 | expression, the name of the instruction to build, an operand format | |
4970 | string, and corresponding arguments. */ | |
4971 | ||
252b5132 | 4972 | static void |
67c0d1eb | 4973 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4974 | { |
df58fc94 | 4975 | const struct mips_opcode *mo = NULL; |
f6688943 | 4976 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4977 | const struct mips_opcode *amo; |
4978 | struct hash_control *hash; | |
4979 | struct mips_cl_insn insn; | |
252b5132 | 4980 | va_list args; |
252b5132 | 4981 | |
252b5132 | 4982 | va_start (args, fmt); |
252b5132 | 4983 | |
252b5132 RH |
4984 | if (mips_opts.mips16) |
4985 | { | |
03ea81db | 4986 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4987 | va_end (args); |
4988 | return; | |
4989 | } | |
4990 | ||
f6688943 TS |
4991 | r[0] = BFD_RELOC_UNUSED; |
4992 | r[1] = BFD_RELOC_UNUSED; | |
4993 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4994 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4995 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4996 | gas_assert (amo); | |
4997 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4998 | |
df58fc94 | 4999 | do |
8b082fb1 TS |
5000 | { |
5001 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5002 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5003 | We try to match an instruction that fulfils the branch delay | |
5004 | slot instruction length requirement (if any) of the previous | |
5005 | instruction. While doing this we record the first instruction | |
5006 | seen that matches all the other conditions and use it anyway | |
5007 | if the requirement cannot be met; we will issue an appropriate | |
5008 | warning later on. */ | |
5009 | if (strcmp (fmt, amo->args) == 0 | |
5010 | && amo->pinfo != INSN_MACRO | |
5011 | && is_opcode_valid (amo) | |
5012 | && is_size_valid (amo)) | |
5013 | { | |
5014 | if (is_delay_slot_valid (amo)) | |
5015 | { | |
5016 | mo = amo; | |
5017 | break; | |
5018 | } | |
5019 | else if (!mo) | |
5020 | mo = amo; | |
5021 | } | |
8b082fb1 | 5022 | |
df58fc94 RS |
5023 | ++amo; |
5024 | gas_assert (amo->name); | |
252b5132 | 5025 | } |
df58fc94 | 5026 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5027 | |
df58fc94 | 5028 | gas_assert (mo); |
1e915849 | 5029 | create_insn (&insn, mo); |
252b5132 RH |
5030 | for (;;) |
5031 | { | |
5032 | switch (*fmt++) | |
5033 | { | |
5034 | case '\0': | |
5035 | break; | |
5036 | ||
5037 | case ',': | |
5038 | case '(': | |
5039 | case ')': | |
5040 | continue; | |
5041 | ||
5f74bc13 CD |
5042 | case '+': |
5043 | switch (*fmt++) | |
5044 | { | |
5045 | case 'A': | |
5046 | case 'E': | |
df58fc94 RS |
5047 | INSERT_OPERAND (mips_opts.micromips, |
5048 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5049 | continue; |
5050 | ||
5051 | case 'B': | |
5052 | case 'F': | |
5053 | /* Note that in the macro case, these arguments are already | |
5054 | in MSB form. (When handling the instruction in the | |
5055 | non-macro case, these arguments are sizes from which | |
5056 | MSB values must be calculated.) */ | |
df58fc94 RS |
5057 | INSERT_OPERAND (mips_opts.micromips, |
5058 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5059 | continue; |
5060 | ||
b015e599 AP |
5061 | case 'J': |
5062 | gas_assert (!mips_opts.micromips); | |
5063 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5064 | continue; | |
5065 | ||
5f74bc13 CD |
5066 | case 'C': |
5067 | case 'G': | |
5068 | case 'H': | |
5069 | /* Note that in the macro case, these arguments are already | |
5070 | in MSBD form. (When handling the instruction in the | |
5071 | non-macro case, these arguments are sizes from which | |
5072 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5073 | INSERT_OPERAND (mips_opts.micromips, |
5074 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5075 | continue; |
5076 | ||
dd3cbb7e | 5077 | case 'Q': |
df58fc94 RS |
5078 | gas_assert (!mips_opts.micromips); |
5079 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5080 | continue; |
5081 | ||
5f74bc13 | 5082 | default: |
b37df7c4 | 5083 | abort (); |
5f74bc13 CD |
5084 | } |
5085 | continue; | |
5086 | ||
8b082fb1 | 5087 | case '2': |
03f66e8a | 5088 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5089 | continue; |
5090 | ||
df58fc94 RS |
5091 | case 'n': |
5092 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5093 | case 't': |
5094 | case 'w': | |
5095 | case 'E': | |
df58fc94 | 5096 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5097 | continue; |
5098 | ||
5099 | case 'c': | |
df58fc94 RS |
5100 | gas_assert (!mips_opts.micromips); |
5101 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5102 | continue; |
5103 | ||
252b5132 | 5104 | case 'W': |
df58fc94 RS |
5105 | gas_assert (!mips_opts.micromips); |
5106 | case 'T': | |
5107 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5108 | continue; |
5109 | ||
252b5132 | 5110 | case 'G': |
df58fc94 RS |
5111 | if (mips_opts.micromips) |
5112 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5113 | else | |
5114 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5115 | continue; | |
5116 | ||
af7ee8bf | 5117 | case 'K': |
df58fc94 RS |
5118 | gas_assert (!mips_opts.micromips); |
5119 | case 'd': | |
5120 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5121 | continue; |
5122 | ||
4372b673 | 5123 | case 'U': |
df58fc94 | 5124 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5125 | { |
5126 | int tmp = va_arg (args, int); | |
5127 | ||
df58fc94 RS |
5128 | INSERT_OPERAND (0, RT, insn, tmp); |
5129 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5130 | } |
df58fc94 | 5131 | continue; |
4372b673 | 5132 | |
252b5132 RH |
5133 | case 'V': |
5134 | case 'S': | |
df58fc94 RS |
5135 | gas_assert (!mips_opts.micromips); |
5136 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5137 | continue; |
5138 | ||
5139 | case 'z': | |
5140 | continue; | |
5141 | ||
5142 | case '<': | |
df58fc94 RS |
5143 | INSERT_OPERAND (mips_opts.micromips, |
5144 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5145 | continue; |
5146 | ||
5147 | case 'D': | |
df58fc94 RS |
5148 | gas_assert (!mips_opts.micromips); |
5149 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5150 | continue; |
5151 | ||
5152 | case 'B': | |
df58fc94 RS |
5153 | gas_assert (!mips_opts.micromips); |
5154 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5155 | continue; |
5156 | ||
4372b673 | 5157 | case 'J': |
df58fc94 RS |
5158 | gas_assert (!mips_opts.micromips); |
5159 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5160 | continue; |
5161 | ||
252b5132 | 5162 | case 'q': |
df58fc94 RS |
5163 | gas_assert (!mips_opts.micromips); |
5164 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5165 | continue; |
5166 | ||
5167 | case 'b': | |
5168 | case 's': | |
5169 | case 'r': | |
5170 | case 'v': | |
df58fc94 | 5171 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5172 | continue; |
5173 | ||
5174 | case 'i': | |
5175 | case 'j': | |
6e1304d8 | 5176 | macro_read_relocs (&args, r); |
9c2799c2 | 5177 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5178 | || *r == BFD_RELOC_MIPS_HIGHER |
5179 | || *r == BFD_RELOC_HI16_S | |
5180 | || *r == BFD_RELOC_LO16 | |
5181 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5182 | continue; | |
5183 | ||
5184 | case 'o': | |
5185 | macro_read_relocs (&args, r); | |
252b5132 RH |
5186 | continue; |
5187 | ||
5188 | case 'u': | |
6e1304d8 | 5189 | macro_read_relocs (&args, r); |
9c2799c2 | 5190 | gas_assert (ep != NULL |
90ecf173 MR |
5191 | && (ep->X_op == O_constant |
5192 | || (ep->X_op == O_symbol | |
5193 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5194 | || *r == BFD_RELOC_HI16_S | |
5195 | || *r == BFD_RELOC_HI16 | |
5196 | || *r == BFD_RELOC_GPREL16 | |
5197 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5198 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5199 | continue; |
5200 | ||
5201 | case 'p': | |
9c2799c2 | 5202 | gas_assert (ep != NULL); |
bad36eac | 5203 | |
252b5132 RH |
5204 | /* |
5205 | * This allows macro() to pass an immediate expression for | |
5206 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5207 | * |
5208 | * We don't allow branch relaxation for these branches, as | |
5209 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5210 | */ |
5211 | if (ep->X_op == O_constant) | |
5212 | { | |
df58fc94 RS |
5213 | /* For microMIPS we always use relocations for branches. |
5214 | So we should not resolve immediate values. */ | |
5215 | gas_assert (!mips_opts.micromips); | |
5216 | ||
bad36eac DJ |
5217 | if ((ep->X_add_number & 3) != 0) |
5218 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5219 | (unsigned long) ep->X_add_number); | |
5220 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5221 | as_bad (_("branch address range overflow (0x%lx)"), | |
5222 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5223 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5224 | ep = NULL; | |
5225 | } | |
5226 | else | |
0b25d3e6 | 5227 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5228 | continue; |
5229 | ||
5230 | case 'a': | |
9c2799c2 | 5231 | gas_assert (ep != NULL); |
f6688943 | 5232 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5233 | continue; |
5234 | ||
5235 | case 'C': | |
df58fc94 RS |
5236 | gas_assert (!mips_opts.micromips); |
5237 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5238 | continue; |
5239 | ||
d43b4baf | 5240 | case 'k': |
df58fc94 RS |
5241 | INSERT_OPERAND (mips_opts.micromips, |
5242 | CACHE, insn, va_arg (args, unsigned long)); | |
5243 | continue; | |
5244 | ||
5245 | case '|': | |
5246 | gas_assert (mips_opts.micromips); | |
5247 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5248 | continue; | |
5249 | ||
5250 | case '.': | |
5251 | gas_assert (mips_opts.micromips); | |
5252 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5253 | continue; | |
5254 | ||
dec0624d MR |
5255 | case '\\': |
5256 | INSERT_OPERAND (mips_opts.micromips, | |
5257 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5258 | continue; | |
5259 | ||
df58fc94 | 5260 | case '~': |
dec0624d MR |
5261 | INSERT_OPERAND (mips_opts.micromips, |
5262 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5263 | continue; |
5264 | ||
5265 | case 'N': | |
5266 | gas_assert (mips_opts.micromips); | |
5267 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5268 | continue; | |
5269 | ||
5270 | case 'm': /* Opcode extension character. */ | |
5271 | gas_assert (mips_opts.micromips); | |
5272 | switch (*fmt++) | |
5273 | { | |
5274 | case 'j': | |
5275 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5276 | break; | |
5277 | ||
5278 | case 'p': | |
5279 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5280 | break; | |
5281 | ||
5282 | case 'F': | |
5283 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5284 | break; | |
5285 | ||
5286 | default: | |
b37df7c4 | 5287 | abort (); |
df58fc94 | 5288 | } |
d43b4baf TS |
5289 | continue; |
5290 | ||
252b5132 | 5291 | default: |
b37df7c4 | 5292 | abort (); |
252b5132 RH |
5293 | } |
5294 | break; | |
5295 | } | |
5296 | va_end (args); | |
9c2799c2 | 5297 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5298 | |
df58fc94 | 5299 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5300 | } |
5301 | ||
5302 | static void | |
67c0d1eb | 5303 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5304 | va_list *args) |
252b5132 | 5305 | { |
1e915849 | 5306 | struct mips_opcode *mo; |
252b5132 | 5307 | struct mips_cl_insn insn; |
f6688943 TS |
5308 | bfd_reloc_code_real_type r[3] |
5309 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5310 | |
1e915849 | 5311 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5312 | gas_assert (mo); |
5313 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5314 | |
1e915849 | 5315 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5316 | { |
1e915849 | 5317 | ++mo; |
9c2799c2 NC |
5318 | gas_assert (mo->name); |
5319 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5320 | } |
5321 | ||
1e915849 | 5322 | create_insn (&insn, mo); |
252b5132 RH |
5323 | for (;;) |
5324 | { | |
5325 | int c; | |
5326 | ||
5327 | c = *fmt++; | |
5328 | switch (c) | |
5329 | { | |
5330 | case '\0': | |
5331 | break; | |
5332 | ||
5333 | case ',': | |
5334 | case '(': | |
5335 | case ')': | |
5336 | continue; | |
5337 | ||
5338 | case 'y': | |
5339 | case 'w': | |
03ea81db | 5340 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5341 | continue; |
5342 | ||
5343 | case 'x': | |
5344 | case 'v': | |
03ea81db | 5345 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5346 | continue; |
5347 | ||
5348 | case 'z': | |
03ea81db | 5349 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5350 | continue; |
5351 | ||
5352 | case 'Z': | |
03ea81db | 5353 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5354 | continue; |
5355 | ||
5356 | case '0': | |
5357 | case 'S': | |
5358 | case 'P': | |
5359 | case 'R': | |
5360 | continue; | |
5361 | ||
5362 | case 'X': | |
03ea81db | 5363 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5364 | continue; |
5365 | ||
5366 | case 'Y': | |
5367 | { | |
5368 | int regno; | |
5369 | ||
03ea81db | 5370 | regno = va_arg (*args, int); |
252b5132 | 5371 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5372 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5373 | } |
5374 | continue; | |
5375 | ||
5376 | case '<': | |
5377 | case '>': | |
5378 | case '4': | |
5379 | case '5': | |
5380 | case 'H': | |
5381 | case 'W': | |
5382 | case 'D': | |
5383 | case 'j': | |
5384 | case '8': | |
5385 | case 'V': | |
5386 | case 'C': | |
5387 | case 'U': | |
5388 | case 'k': | |
5389 | case 'K': | |
5390 | case 'p': | |
5391 | case 'q': | |
5392 | { | |
b886a2ab RS |
5393 | offsetT value; |
5394 | ||
9c2799c2 | 5395 | gas_assert (ep != NULL); |
252b5132 RH |
5396 | |
5397 | if (ep->X_op != O_constant) | |
874e8986 | 5398 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5399 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5400 | { |
b886a2ab | 5401 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5402 | ep = NULL; |
f6688943 | 5403 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5404 | } |
5405 | } | |
5406 | continue; | |
5407 | ||
5408 | case '6': | |
03ea81db | 5409 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5410 | continue; |
5411 | } | |
5412 | ||
5413 | break; | |
5414 | } | |
5415 | ||
9c2799c2 | 5416 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5417 | |
df58fc94 | 5418 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5419 | } |
5420 | ||
2051e8c4 MR |
5421 | /* |
5422 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5423 | * higher bits unset. | |
5424 | */ | |
9f872bbe | 5425 | static void |
2051e8c4 MR |
5426 | normalize_constant_expr (expressionS *ex) |
5427 | { | |
9ee2a2d4 | 5428 | if (ex->X_op == O_constant |
2051e8c4 MR |
5429 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5430 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5431 | - 0x80000000); | |
5432 | } | |
5433 | ||
5434 | /* | |
5435 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5436 | * all higher bits unset. | |
5437 | */ | |
5438 | static void | |
5439 | normalize_address_expr (expressionS *ex) | |
5440 | { | |
5441 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5442 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5443 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5444 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5445 | - 0x80000000); | |
5446 | } | |
5447 | ||
438c16b8 TS |
5448 | /* |
5449 | * Generate a "jalr" instruction with a relocation hint to the called | |
5450 | * function. This occurs in NewABI PIC code. | |
5451 | */ | |
5452 | static void | |
df58fc94 | 5453 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5454 | { |
df58fc94 RS |
5455 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5456 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5457 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5458 | const char *jalr; | |
685736be | 5459 | char *f = NULL; |
b34976b6 | 5460 | |
1180b5a4 | 5461 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5462 | { |
cc3d92a5 | 5463 | frag_grow (8); |
f21f8242 AO |
5464 | f = frag_more (0); |
5465 | } | |
2906b037 | 5466 | if (mips_opts.micromips) |
df58fc94 RS |
5467 | { |
5468 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5469 | if (MIPS_JALR_HINT_P (ep) |
5470 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5471 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5472 | else | |
5473 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5474 | } | |
2906b037 MR |
5475 | else |
5476 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5477 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5478 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5479 | } |
5480 | ||
252b5132 RH |
5481 | /* |
5482 | * Generate a "lui" instruction. | |
5483 | */ | |
5484 | static void | |
67c0d1eb | 5485 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5486 | { |
9c2799c2 | 5487 | gas_assert (! mips_opts.mips16); |
252b5132 | 5488 | |
df58fc94 | 5489 | if (ep->X_op != O_constant) |
252b5132 | 5490 | { |
9c2799c2 | 5491 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5492 | /* _gp_disp is a special case, used from s_cpload. |
5493 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5494 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5495 | || (! HAVE_NEWABI |
aa6975fb ILT |
5496 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5497 | || (! mips_in_shared | |
bbe506e8 TS |
5498 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5499 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5500 | } |
5501 | ||
df58fc94 | 5502 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5503 | } |
5504 | ||
885add95 CD |
5505 | /* Generate a sequence of instructions to do a load or store from a constant |
5506 | offset off of a base register (breg) into/from a target register (treg), | |
5507 | using AT if necessary. */ | |
5508 | static void | |
67c0d1eb RS |
5509 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5510 | int treg, int breg, int dbl) | |
885add95 | 5511 | { |
9c2799c2 | 5512 | gas_assert (ep->X_op == O_constant); |
885add95 | 5513 | |
256ab948 | 5514 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5515 | if (!dbl) |
5516 | normalize_constant_expr (ep); | |
256ab948 | 5517 | |
67c1ffbe | 5518 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5519 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5520 | as_warn (_("operand overflow")); |
5521 | ||
5522 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5523 | { | |
5524 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5525 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5526 | } |
5527 | else | |
5528 | { | |
5529 | /* 32-bit offset, need multiple instructions and AT, like: | |
5530 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5531 | addu $tempreg,$tempreg,$breg | |
5532 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5533 | to handle the complete offset. */ | |
67c0d1eb RS |
5534 | macro_build_lui (ep, AT); |
5535 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5536 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5537 | |
741fe287 | 5538 | if (!mips_opts.at) |
8fc2e39e | 5539 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5540 | } |
5541 | } | |
5542 | ||
252b5132 RH |
5543 | /* set_at() |
5544 | * Generates code to set the $at register to true (one) | |
5545 | * if reg is less than the immediate expression. | |
5546 | */ | |
5547 | static void | |
67c0d1eb | 5548 | set_at (int reg, int unsignedp) |
252b5132 RH |
5549 | { |
5550 | if (imm_expr.X_op == O_constant | |
5551 | && imm_expr.X_add_number >= -0x8000 | |
5552 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5553 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5554 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5555 | else |
5556 | { | |
67c0d1eb RS |
5557 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5558 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5559 | } |
5560 | } | |
5561 | ||
5562 | /* Warn if an expression is not a constant. */ | |
5563 | ||
5564 | static void | |
17a2f251 | 5565 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5566 | { |
5567 | if (ex->X_op == O_big) | |
5568 | as_bad (_("unsupported large constant")); | |
5569 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5570 | as_bad (_("Instruction %s requires absolute expression"), |
5571 | ip->insn_mo->name); | |
13757d0c | 5572 | |
9ee2a2d4 MR |
5573 | if (HAVE_32BIT_GPRS) |
5574 | normalize_constant_expr (ex); | |
252b5132 RH |
5575 | } |
5576 | ||
5577 | /* Count the leading zeroes by performing a binary chop. This is a | |
5578 | bulky bit of source, but performance is a LOT better for the | |
5579 | majority of values than a simple loop to count the bits: | |
5580 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5581 | if ((v) & (1 << (31 - lcnt))) | |
5582 | break; | |
5583 | However it is not code size friendly, and the gain will drop a bit | |
5584 | on certain cached systems. | |
5585 | */ | |
5586 | #define COUNT_TOP_ZEROES(v) \ | |
5587 | (((v) & ~0xffff) == 0 \ | |
5588 | ? ((v) & ~0xff) == 0 \ | |
5589 | ? ((v) & ~0xf) == 0 \ | |
5590 | ? ((v) & ~0x3) == 0 \ | |
5591 | ? ((v) & ~0x1) == 0 \ | |
5592 | ? !(v) \ | |
5593 | ? 32 \ | |
5594 | : 31 \ | |
5595 | : 30 \ | |
5596 | : ((v) & ~0x7) == 0 \ | |
5597 | ? 29 \ | |
5598 | : 28 \ | |
5599 | : ((v) & ~0x3f) == 0 \ | |
5600 | ? ((v) & ~0x1f) == 0 \ | |
5601 | ? 27 \ | |
5602 | : 26 \ | |
5603 | : ((v) & ~0x7f) == 0 \ | |
5604 | ? 25 \ | |
5605 | : 24 \ | |
5606 | : ((v) & ~0xfff) == 0 \ | |
5607 | ? ((v) & ~0x3ff) == 0 \ | |
5608 | ? ((v) & ~0x1ff) == 0 \ | |
5609 | ? 23 \ | |
5610 | : 22 \ | |
5611 | : ((v) & ~0x7ff) == 0 \ | |
5612 | ? 21 \ | |
5613 | : 20 \ | |
5614 | : ((v) & ~0x3fff) == 0 \ | |
5615 | ? ((v) & ~0x1fff) == 0 \ | |
5616 | ? 19 \ | |
5617 | : 18 \ | |
5618 | : ((v) & ~0x7fff) == 0 \ | |
5619 | ? 17 \ | |
5620 | : 16 \ | |
5621 | : ((v) & ~0xffffff) == 0 \ | |
5622 | ? ((v) & ~0xfffff) == 0 \ | |
5623 | ? ((v) & ~0x3ffff) == 0 \ | |
5624 | ? ((v) & ~0x1ffff) == 0 \ | |
5625 | ? 15 \ | |
5626 | : 14 \ | |
5627 | : ((v) & ~0x7ffff) == 0 \ | |
5628 | ? 13 \ | |
5629 | : 12 \ | |
5630 | : ((v) & ~0x3fffff) == 0 \ | |
5631 | ? ((v) & ~0x1fffff) == 0 \ | |
5632 | ? 11 \ | |
5633 | : 10 \ | |
5634 | : ((v) & ~0x7fffff) == 0 \ | |
5635 | ? 9 \ | |
5636 | : 8 \ | |
5637 | : ((v) & ~0xfffffff) == 0 \ | |
5638 | ? ((v) & ~0x3ffffff) == 0 \ | |
5639 | ? ((v) & ~0x1ffffff) == 0 \ | |
5640 | ? 7 \ | |
5641 | : 6 \ | |
5642 | : ((v) & ~0x7ffffff) == 0 \ | |
5643 | ? 5 \ | |
5644 | : 4 \ | |
5645 | : ((v) & ~0x3fffffff) == 0 \ | |
5646 | ? ((v) & ~0x1fffffff) == 0 \ | |
5647 | ? 3 \ | |
5648 | : 2 \ | |
5649 | : ((v) & ~0x7fffffff) == 0 \ | |
5650 | ? 1 \ | |
5651 | : 0) | |
5652 | ||
5653 | /* load_register() | |
67c1ffbe | 5654 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5655 | * an absolute expression value into a register. |
5656 | */ | |
5657 | static void | |
67c0d1eb | 5658 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5659 | { |
5660 | int freg; | |
5661 | expressionS hi32, lo32; | |
5662 | ||
5663 | if (ep->X_op != O_big) | |
5664 | { | |
9c2799c2 | 5665 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5666 | |
5667 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5668 | if (!dbl) |
5669 | normalize_constant_expr (ep); | |
256ab948 TS |
5670 | |
5671 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5672 | { |
5673 | /* We can handle 16 bit signed values with an addiu to | |
5674 | $zero. No need to ever use daddiu here, since $zero and | |
5675 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5676 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5677 | return; |
5678 | } | |
5679 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5680 | { | |
5681 | /* We can handle 16 bit unsigned values with an ori to | |
5682 | $zero. */ | |
67c0d1eb | 5683 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5684 | return; |
5685 | } | |
256ab948 | 5686 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5687 | { |
5688 | /* 32 bit values require an lui. */ | |
df58fc94 | 5689 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5690 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5691 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5692 | return; |
5693 | } | |
5694 | } | |
5695 | ||
5696 | /* The value is larger than 32 bits. */ | |
5697 | ||
2051e8c4 | 5698 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5699 | { |
55e08f71 NC |
5700 | char value[32]; |
5701 | ||
5702 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5703 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5704 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5705 | return; |
5706 | } | |
5707 | ||
5708 | if (ep->X_op != O_big) | |
5709 | { | |
5710 | hi32 = *ep; | |
5711 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5712 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5713 | hi32.X_add_number &= 0xffffffff; | |
5714 | lo32 = *ep; | |
5715 | lo32.X_add_number &= 0xffffffff; | |
5716 | } | |
5717 | else | |
5718 | { | |
9c2799c2 | 5719 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5720 | if (ep->X_add_number == 3) |
5721 | generic_bignum[3] = 0; | |
5722 | else if (ep->X_add_number > 4) | |
5723 | as_bad (_("Number larger than 64 bits")); | |
5724 | lo32.X_op = O_constant; | |
5725 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5726 | hi32.X_op = O_constant; | |
5727 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5728 | } | |
5729 | ||
5730 | if (hi32.X_add_number == 0) | |
5731 | freg = 0; | |
5732 | else | |
5733 | { | |
5734 | int shift, bit; | |
5735 | unsigned long hi, lo; | |
5736 | ||
956cd1d6 | 5737 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5738 | { |
5739 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5740 | { | |
67c0d1eb | 5741 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5742 | return; |
5743 | } | |
5744 | if (lo32.X_add_number & 0x80000000) | |
5745 | { | |
df58fc94 | 5746 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5747 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5748 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5749 | return; |
5750 | } | |
5751 | } | |
252b5132 RH |
5752 | |
5753 | /* Check for 16bit shifted constant. We know that hi32 is | |
5754 | non-zero, so start the mask on the first bit of the hi32 | |
5755 | value. */ | |
5756 | shift = 17; | |
5757 | do | |
beae10d5 KH |
5758 | { |
5759 | unsigned long himask, lomask; | |
5760 | ||
5761 | if (shift < 32) | |
5762 | { | |
5763 | himask = 0xffff >> (32 - shift); | |
5764 | lomask = (0xffff << shift) & 0xffffffff; | |
5765 | } | |
5766 | else | |
5767 | { | |
5768 | himask = 0xffff << (shift - 32); | |
5769 | lomask = 0; | |
5770 | } | |
5771 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5772 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5773 | { | |
5774 | expressionS tmp; | |
5775 | ||
5776 | tmp.X_op = O_constant; | |
5777 | if (shift < 32) | |
5778 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5779 | | (lo32.X_add_number >> shift)); | |
5780 | else | |
5781 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5782 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5783 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5784 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5785 | return; |
5786 | } | |
f9419b05 | 5787 | ++shift; |
beae10d5 KH |
5788 | } |
5789 | while (shift <= (64 - 16)); | |
252b5132 RH |
5790 | |
5791 | /* Find the bit number of the lowest one bit, and store the | |
5792 | shifted value in hi/lo. */ | |
5793 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5794 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5795 | if (lo != 0) | |
5796 | { | |
5797 | bit = 0; | |
5798 | while ((lo & 1) == 0) | |
5799 | { | |
5800 | lo >>= 1; | |
5801 | ++bit; | |
5802 | } | |
5803 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5804 | hi >>= bit; | |
5805 | } | |
5806 | else | |
5807 | { | |
5808 | bit = 32; | |
5809 | while ((hi & 1) == 0) | |
5810 | { | |
5811 | hi >>= 1; | |
5812 | ++bit; | |
5813 | } | |
5814 | lo = hi; | |
5815 | hi = 0; | |
5816 | } | |
5817 | ||
5818 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5819 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5820 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5821 | { |
5822 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5823 | if (shift != 0) |
beae10d5 | 5824 | { |
252b5132 RH |
5825 | expressionS tmp; |
5826 | ||
5827 | /* This instruction will set the register to be all | |
5828 | ones. */ | |
beae10d5 KH |
5829 | tmp.X_op = O_constant; |
5830 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5831 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5832 | if (bit != 0) |
5833 | { | |
5834 | bit += shift; | |
df58fc94 | 5835 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5836 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5837 | } |
df58fc94 | 5838 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5839 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5840 | return; |
5841 | } | |
5842 | } | |
252b5132 RH |
5843 | |
5844 | /* Sign extend hi32 before calling load_register, because we can | |
5845 | generally get better code when we load a sign extended value. */ | |
5846 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5847 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5848 | load_register (reg, &hi32, 0); |
252b5132 RH |
5849 | freg = reg; |
5850 | } | |
5851 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5852 | { | |
5853 | if (freg != 0) | |
5854 | { | |
df58fc94 | 5855 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5856 | freg = reg; |
5857 | } | |
5858 | } | |
5859 | else | |
5860 | { | |
5861 | expressionS mid16; | |
5862 | ||
956cd1d6 | 5863 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5864 | { |
df58fc94 RS |
5865 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5866 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5867 | return; |
5868 | } | |
252b5132 RH |
5869 | |
5870 | if (freg != 0) | |
5871 | { | |
df58fc94 | 5872 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5873 | freg = reg; |
5874 | } | |
5875 | mid16 = lo32; | |
5876 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5877 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5878 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5879 | freg = reg; |
5880 | } | |
5881 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5882 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5883 | } |
5884 | ||
269137b2 TS |
5885 | static inline void |
5886 | load_delay_nop (void) | |
5887 | { | |
5888 | if (!gpr_interlocks) | |
5889 | macro_build (NULL, "nop", ""); | |
5890 | } | |
5891 | ||
252b5132 RH |
5892 | /* Load an address into a register. */ |
5893 | ||
5894 | static void | |
67c0d1eb | 5895 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5896 | { |
252b5132 RH |
5897 | if (ep->X_op != O_constant |
5898 | && ep->X_op != O_symbol) | |
5899 | { | |
5900 | as_bad (_("expression too complex")); | |
5901 | ep->X_op = O_constant; | |
5902 | } | |
5903 | ||
5904 | if (ep->X_op == O_constant) | |
5905 | { | |
67c0d1eb | 5906 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5907 | return; |
5908 | } | |
5909 | ||
5910 | if (mips_pic == NO_PIC) | |
5911 | { | |
5912 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5913 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5914 | Otherwise we want |
5915 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5916 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5917 | If we have an addend, we always use the latter form. |
76b3015f | 5918 | |
d6bc6245 TS |
5919 | With 64bit address space and a usable $at we want |
5920 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5921 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5922 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5923 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5924 | dsll32 $reg,0 | |
3a482fd5 | 5925 | daddu $reg,$reg,$at |
76b3015f | 5926 | |
c03099e6 | 5927 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5928 | on superscalar processors. |
5929 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5930 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5931 | dsll $reg,16 | |
5932 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5933 | dsll $reg,16 | |
5934 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5935 | |
5936 | For GP relative symbols in 64bit address space we can use | |
5937 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5938 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5939 | { |
6caf9ef4 TS |
5940 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5941 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5942 | { | |
5943 | relax_start (ep->X_add_symbol); | |
5944 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5945 | mips_gp_register, BFD_RELOC_GPREL16); | |
5946 | relax_switch (); | |
5947 | } | |
d6bc6245 | 5948 | |
741fe287 | 5949 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5950 | { |
df58fc94 RS |
5951 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5952 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5953 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5954 | BFD_RELOC_MIPS_HIGHER); | |
5955 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5956 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5957 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5958 | *used_at = 1; |
5959 | } | |
5960 | else | |
5961 | { | |
df58fc94 | 5962 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5963 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5964 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5965 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5966 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5967 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5968 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5969 | } |
6caf9ef4 TS |
5970 | |
5971 | if (mips_relax.sequence) | |
5972 | relax_end (); | |
d6bc6245 | 5973 | } |
252b5132 RH |
5974 | else |
5975 | { | |
d6bc6245 | 5976 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5977 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5978 | { |
4d7206a2 | 5979 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5980 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5981 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5982 | relax_switch (); |
d6bc6245 | 5983 | } |
67c0d1eb RS |
5984 | macro_build_lui (ep, reg); |
5985 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5986 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5987 | if (mips_relax.sequence) |
5988 | relax_end (); | |
d6bc6245 | 5989 | } |
252b5132 | 5990 | } |
0a44bf69 | 5991 | else if (!mips_big_got) |
252b5132 RH |
5992 | { |
5993 | expressionS ex; | |
5994 | ||
5995 | /* If this is a reference to an external symbol, we want | |
5996 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5997 | Otherwise we want | |
5998 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5999 | nop | |
6000 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6001 | If there is a constant, it must be added in after. |
6002 | ||
ed6fb7bd | 6003 | If we have NewABI, we want |
f5040a92 AO |
6004 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6005 | unless we're referencing a global symbol with a non-zero | |
6006 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6007 | if (HAVE_NEWABI) |
6008 | { | |
f5040a92 AO |
6009 | if (ep->X_add_number) |
6010 | { | |
4d7206a2 | 6011 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6012 | ep->X_add_number = 0; |
4d7206a2 | 6013 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6014 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6015 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6016 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6017 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6018 | ex.X_op = O_constant; | |
67c0d1eb | 6019 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6020 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6021 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6022 | relax_switch (); |
f5040a92 | 6023 | } |
67c0d1eb | 6024 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6025 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6026 | if (mips_relax.sequence) |
6027 | relax_end (); | |
ed6fb7bd SC |
6028 | } |
6029 | else | |
6030 | { | |
f5040a92 AO |
6031 | ex.X_add_number = ep->X_add_number; |
6032 | ep->X_add_number = 0; | |
67c0d1eb RS |
6033 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6034 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6035 | load_delay_nop (); |
4d7206a2 RS |
6036 | relax_start (ep->X_add_symbol); |
6037 | relax_switch (); | |
67c0d1eb | 6038 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6039 | BFD_RELOC_LO16); |
4d7206a2 | 6040 | relax_end (); |
ed6fb7bd | 6041 | |
f5040a92 AO |
6042 | if (ex.X_add_number != 0) |
6043 | { | |
6044 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6045 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6046 | ex.X_op = O_constant; | |
67c0d1eb | 6047 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6048 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6049 | } |
252b5132 RH |
6050 | } |
6051 | } | |
0a44bf69 | 6052 | else if (mips_big_got) |
252b5132 RH |
6053 | { |
6054 | expressionS ex; | |
252b5132 RH |
6055 | |
6056 | /* This is the large GOT case. If this is a reference to an | |
6057 | external symbol, we want | |
6058 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6059 | addu $reg,$reg,$gp | |
6060 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6061 | |
6062 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6063 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6064 | nop | |
6065 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6066 | If there is a constant, it must be added in after. |
f5040a92 AO |
6067 | |
6068 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6069 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6070 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6071 | */ |
438c16b8 TS |
6072 | if (HAVE_NEWABI) |
6073 | { | |
4d7206a2 | 6074 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6075 | ep->X_add_number = 0; |
4d7206a2 | 6076 | relax_start (ep->X_add_symbol); |
df58fc94 | 6077 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6078 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6079 | reg, reg, mips_gp_register); | |
6080 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6081 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6082 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6083 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6084 | else if (ex.X_add_number) | |
6085 | { | |
6086 | ex.X_op = O_constant; | |
67c0d1eb RS |
6087 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6088 | BFD_RELOC_LO16); | |
f5040a92 AO |
6089 | } |
6090 | ||
6091 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6092 | relax_switch (); |
67c0d1eb | 6093 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6094 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6095 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6096 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6097 | relax_end (); |
438c16b8 | 6098 | } |
252b5132 | 6099 | else |
438c16b8 | 6100 | { |
f5040a92 AO |
6101 | ex.X_add_number = ep->X_add_number; |
6102 | ep->X_add_number = 0; | |
4d7206a2 | 6103 | relax_start (ep->X_add_symbol); |
df58fc94 | 6104 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6105 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6106 | reg, reg, mips_gp_register); | |
6107 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6108 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6109 | relax_switch (); |
6110 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6111 | { |
6112 | /* We need a nop before loading from $gp. This special | |
6113 | check is required because the lui which starts the main | |
6114 | instruction stream does not refer to $gp, and so will not | |
6115 | insert the nop which may be required. */ | |
67c0d1eb | 6116 | macro_build (NULL, "nop", ""); |
438c16b8 | 6117 | } |
67c0d1eb | 6118 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6119 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6120 | load_delay_nop (); |
67c0d1eb | 6121 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6122 | BFD_RELOC_LO16); |
4d7206a2 | 6123 | relax_end (); |
438c16b8 | 6124 | |
f5040a92 AO |
6125 | if (ex.X_add_number != 0) |
6126 | { | |
6127 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6128 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6129 | ex.X_op = O_constant; | |
67c0d1eb RS |
6130 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6131 | BFD_RELOC_LO16); | |
f5040a92 | 6132 | } |
252b5132 RH |
6133 | } |
6134 | } | |
252b5132 RH |
6135 | else |
6136 | abort (); | |
8fc2e39e | 6137 | |
741fe287 | 6138 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6139 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6140 | } |
6141 | ||
ea1fb5dc RS |
6142 | /* Move the contents of register SOURCE into register DEST. */ |
6143 | ||
6144 | static void | |
67c0d1eb | 6145 | move_register (int dest, int source) |
ea1fb5dc | 6146 | { |
df58fc94 RS |
6147 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6148 | instruction specifically requires a 32-bit one. */ | |
6149 | if (mips_opts.micromips | |
6150 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6151 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6152 | else |
6153 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6154 | dest, source, 0); | |
ea1fb5dc RS |
6155 | } |
6156 | ||
4d7206a2 | 6157 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6158 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6159 | The two alternatives are: | |
4d7206a2 RS |
6160 | |
6161 | Global symbol Local sybmol | |
6162 | ------------- ------------ | |
6163 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6164 | ... ... | |
6165 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6166 | ||
6167 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6168 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6169 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6170 | |
6171 | static void | |
67c0d1eb | 6172 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6173 | { |
6174 | expressionS global; | |
6175 | ||
6176 | global = *local; | |
6177 | global.X_add_number = 0; | |
6178 | ||
6179 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6180 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6181 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6182 | relax_switch (); |
67c0d1eb RS |
6183 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6184 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6185 | relax_end (); |
6186 | } | |
6187 | ||
6188 | static void | |
67c0d1eb | 6189 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6190 | { |
6191 | expressionS global; | |
6192 | ||
6193 | global.X_op = O_constant; | |
6194 | global.X_op_symbol = NULL; | |
6195 | global.X_add_symbol = NULL; | |
6196 | global.X_add_number = local->X_add_number; | |
6197 | ||
6198 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6199 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6200 | dest, dest, BFD_RELOC_LO16); |
6201 | relax_switch (); | |
67c0d1eb | 6202 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6203 | relax_end (); |
6204 | } | |
6205 | ||
f6a22291 MR |
6206 | static void |
6207 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6208 | { | |
6209 | expressionS global; | |
6210 | int hold_mips_optimize; | |
6211 | ||
6212 | global.X_op = O_constant; | |
6213 | global.X_op_symbol = NULL; | |
6214 | global.X_add_symbol = NULL; | |
6215 | global.X_add_number = local->X_add_number; | |
6216 | ||
6217 | relax_start (local->X_add_symbol); | |
6218 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6219 | relax_switch (); | |
6220 | /* Set mips_optimize around the lui instruction to avoid | |
6221 | inserting an unnecessary nop after the lw. */ | |
6222 | hold_mips_optimize = mips_optimize; | |
6223 | mips_optimize = 2; | |
6224 | macro_build_lui (&global, tmp); | |
6225 | mips_optimize = hold_mips_optimize; | |
6226 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6227 | relax_end (); | |
6228 | ||
6229 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6230 | } | |
6231 | ||
df58fc94 RS |
6232 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6233 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6234 | is its complementing branch with the original condition negated. | |
6235 | CALL is set if the original branch specified the link operation. | |
6236 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6237 | ||
6238 | Code like this is produced in the noreorder mode: | |
6239 | ||
6240 | BRNEG <args>, 1f | |
6241 | nop | |
6242 | b <sym> | |
6243 | delay slot (executed only if branch taken) | |
6244 | 1: | |
6245 | ||
6246 | or, if CALL is set: | |
6247 | ||
6248 | BRNEG <args>, 1f | |
6249 | nop | |
6250 | bal <sym> | |
6251 | delay slot (executed only if branch taken) | |
6252 | 1: | |
6253 | ||
6254 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6255 | so code produced is simply: | |
6256 | ||
6257 | BR <args>, <sym> | |
6258 | nop | |
6259 | ||
6260 | This function is used when producing code for the microMIPS ASE that | |
6261 | does not implement branch likely instructions in hardware. */ | |
6262 | ||
6263 | static void | |
6264 | macro_build_branch_likely (const char *br, const char *brneg, | |
6265 | int call, expressionS *ep, const char *fmt, | |
6266 | unsigned int sreg, unsigned int treg) | |
6267 | { | |
6268 | int noreorder = mips_opts.noreorder; | |
6269 | expressionS expr1; | |
6270 | ||
6271 | gas_assert (mips_opts.micromips); | |
6272 | start_noreorder (); | |
6273 | if (noreorder) | |
6274 | { | |
6275 | micromips_label_expr (&expr1); | |
6276 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6277 | macro_build (NULL, "nop", ""); | |
6278 | macro_build (ep, call ? "bal" : "b", "p"); | |
6279 | ||
6280 | /* Set to true so that append_insn adds a label. */ | |
6281 | emit_branch_likely_macro = TRUE; | |
6282 | } | |
6283 | else | |
6284 | { | |
6285 | macro_build (ep, br, fmt, sreg, treg); | |
6286 | macro_build (NULL, "nop", ""); | |
6287 | } | |
6288 | end_noreorder (); | |
6289 | } | |
6290 | ||
6291 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6292 | the condition code tested. EP specifies the branch target. */ | |
6293 | ||
6294 | static void | |
6295 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6296 | { | |
6297 | const int call = 0; | |
6298 | const char *brneg; | |
6299 | const char *br; | |
6300 | ||
6301 | switch (type) | |
6302 | { | |
6303 | case M_BC1FL: | |
6304 | br = "bc1f"; | |
6305 | brneg = "bc1t"; | |
6306 | break; | |
6307 | case M_BC1TL: | |
6308 | br = "bc1t"; | |
6309 | brneg = "bc1f"; | |
6310 | break; | |
6311 | case M_BC2FL: | |
6312 | br = "bc2f"; | |
6313 | brneg = "bc2t"; | |
6314 | break; | |
6315 | case M_BC2TL: | |
6316 | br = "bc2t"; | |
6317 | brneg = "bc2f"; | |
6318 | break; | |
6319 | default: | |
6320 | abort (); | |
6321 | } | |
6322 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6323 | } | |
6324 | ||
6325 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6326 | the register tested. EP specifies the branch target. */ | |
6327 | ||
6328 | static void | |
6329 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6330 | { | |
6331 | const char *brneg = NULL; | |
6332 | const char *br; | |
6333 | int call = 0; | |
6334 | ||
6335 | switch (type) | |
6336 | { | |
6337 | case M_BGEZ: | |
6338 | br = "bgez"; | |
6339 | break; | |
6340 | case M_BGEZL: | |
6341 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6342 | brneg = "bltz"; | |
6343 | break; | |
6344 | case M_BGEZALL: | |
6345 | gas_assert (mips_opts.micromips); | |
6346 | br = "bgezals"; | |
6347 | brneg = "bltz"; | |
6348 | call = 1; | |
6349 | break; | |
6350 | case M_BGTZ: | |
6351 | br = "bgtz"; | |
6352 | break; | |
6353 | case M_BGTZL: | |
6354 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6355 | brneg = "blez"; | |
6356 | break; | |
6357 | case M_BLEZ: | |
6358 | br = "blez"; | |
6359 | break; | |
6360 | case M_BLEZL: | |
6361 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6362 | brneg = "bgtz"; | |
6363 | break; | |
6364 | case M_BLTZ: | |
6365 | br = "bltz"; | |
6366 | break; | |
6367 | case M_BLTZL: | |
6368 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6369 | brneg = "bgez"; | |
6370 | break; | |
6371 | case M_BLTZALL: | |
6372 | gas_assert (mips_opts.micromips); | |
6373 | br = "bltzals"; | |
6374 | brneg = "bgez"; | |
6375 | call = 1; | |
6376 | break; | |
6377 | default: | |
6378 | abort (); | |
6379 | } | |
6380 | if (mips_opts.micromips && brneg) | |
6381 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6382 | else | |
6383 | macro_build (ep, br, "s,p", sreg); | |
6384 | } | |
6385 | ||
6386 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6387 | TREG as the registers tested. EP specifies the branch target. */ | |
6388 | ||
6389 | static void | |
6390 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6391 | unsigned int sreg, unsigned int treg) | |
6392 | { | |
6393 | const char *brneg = NULL; | |
6394 | const int call = 0; | |
6395 | const char *br; | |
6396 | ||
6397 | switch (type) | |
6398 | { | |
6399 | case M_BEQ: | |
6400 | case M_BEQ_I: | |
6401 | br = "beq"; | |
6402 | break; | |
6403 | case M_BEQL: | |
6404 | case M_BEQL_I: | |
6405 | br = mips_opts.micromips ? "beq" : "beql"; | |
6406 | brneg = "bne"; | |
6407 | break; | |
6408 | case M_BNE: | |
6409 | case M_BNE_I: | |
6410 | br = "bne"; | |
6411 | break; | |
6412 | case M_BNEL: | |
6413 | case M_BNEL_I: | |
6414 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6415 | brneg = "beq"; | |
6416 | break; | |
6417 | default: | |
6418 | abort (); | |
6419 | } | |
6420 | if (mips_opts.micromips && brneg) | |
6421 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6422 | else | |
6423 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6424 | } | |
6425 | ||
252b5132 RH |
6426 | /* |
6427 | * Build macros | |
6428 | * This routine implements the seemingly endless macro or synthesized | |
6429 | * instructions and addressing modes in the mips assembly language. Many | |
6430 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6431 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6432 | * this verbose method. Others are not simple macros but are more like |
6433 | * optimizing code generation. | |
6434 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6435 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6436 | * The ensuing load upper instructions are ommited. This implies some kind |
6437 | * of global optimization. We currently only optimize within a single macro. | |
6438 | * For many of the load and store macros if the address is specified as a | |
6439 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6440 | * first load register 'at' with zero and use it as the base register. The | |
6441 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6442 | * we're missing. | |
6443 | */ | |
6444 | static void | |
17a2f251 | 6445 | macro (struct mips_cl_insn *ip) |
252b5132 | 6446 | { |
741fe287 MR |
6447 | unsigned int treg, sreg, dreg, breg; |
6448 | unsigned int tempreg; | |
252b5132 | 6449 | int mask; |
43841e91 | 6450 | int used_at = 0; |
df58fc94 | 6451 | expressionS label_expr; |
252b5132 | 6452 | expressionS expr1; |
df58fc94 | 6453 | expressionS *ep; |
252b5132 RH |
6454 | const char *s; |
6455 | const char *s2; | |
6456 | const char *fmt; | |
6457 | int likely = 0; | |
252b5132 | 6458 | int coproc = 0; |
df58fc94 | 6459 | int off12 = 0; |
1abe91b1 | 6460 | int call = 0; |
df58fc94 RS |
6461 | int jals = 0; |
6462 | int dbl = 0; | |
6463 | int imm = 0; | |
6464 | int ust = 0; | |
6465 | int lp = 0; | |
6466 | int ab = 0; | |
dd6a37e7 | 6467 | int off0 = 0; |
252b5132 | 6468 | int off; |
67c0d1eb | 6469 | offsetT maxnum; |
252b5132 | 6470 | bfd_reloc_code_real_type r; |
252b5132 RH |
6471 | int hold_mips_optimize; |
6472 | ||
9c2799c2 | 6473 | gas_assert (! mips_opts.mips16); |
252b5132 | 6474 | |
df58fc94 RS |
6475 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6476 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6477 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6478 | mask = ip->insn_mo->mask; |
6479 | ||
df58fc94 RS |
6480 | label_expr.X_op = O_constant; |
6481 | label_expr.X_op_symbol = NULL; | |
6482 | label_expr.X_add_symbol = NULL; | |
6483 | label_expr.X_add_number = 0; | |
6484 | ||
252b5132 RH |
6485 | expr1.X_op = O_constant; |
6486 | expr1.X_op_symbol = NULL; | |
6487 | expr1.X_add_symbol = NULL; | |
6488 | expr1.X_add_number = 1; | |
6489 | ||
6490 | switch (mask) | |
6491 | { | |
6492 | case M_DABS: | |
6493 | dbl = 1; | |
6494 | case M_ABS: | |
df58fc94 RS |
6495 | /* bgez $a0,1f |
6496 | move v0,$a0 | |
6497 | sub v0,$zero,$a0 | |
6498 | 1: | |
6499 | */ | |
252b5132 | 6500 | |
7d10b47d | 6501 | start_noreorder (); |
252b5132 | 6502 | |
df58fc94 RS |
6503 | if (mips_opts.micromips) |
6504 | micromips_label_expr (&label_expr); | |
6505 | else | |
6506 | label_expr.X_add_number = 8; | |
6507 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6508 | if (dreg == sreg) |
a605d2b3 | 6509 | macro_build (NULL, "nop", ""); |
252b5132 | 6510 | else |
67c0d1eb RS |
6511 | move_register (dreg, sreg); |
6512 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6513 | if (mips_opts.micromips) |
6514 | micromips_add_label (); | |
252b5132 | 6515 | |
7d10b47d | 6516 | end_noreorder (); |
8fc2e39e | 6517 | break; |
252b5132 RH |
6518 | |
6519 | case M_ADD_I: | |
6520 | s = "addi"; | |
6521 | s2 = "add"; | |
6522 | goto do_addi; | |
6523 | case M_ADDU_I: | |
6524 | s = "addiu"; | |
6525 | s2 = "addu"; | |
6526 | goto do_addi; | |
6527 | case M_DADD_I: | |
6528 | dbl = 1; | |
6529 | s = "daddi"; | |
6530 | s2 = "dadd"; | |
df58fc94 RS |
6531 | if (!mips_opts.micromips) |
6532 | goto do_addi; | |
6533 | if (imm_expr.X_op == O_constant | |
6534 | && imm_expr.X_add_number >= -0x200 | |
6535 | && imm_expr.X_add_number < 0x200) | |
6536 | { | |
6537 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6538 | break; | |
6539 | } | |
6540 | goto do_addi_i; | |
252b5132 RH |
6541 | case M_DADDU_I: |
6542 | dbl = 1; | |
6543 | s = "daddiu"; | |
6544 | s2 = "daddu"; | |
6545 | do_addi: | |
6546 | if (imm_expr.X_op == O_constant | |
6547 | && imm_expr.X_add_number >= -0x8000 | |
6548 | && imm_expr.X_add_number < 0x8000) | |
6549 | { | |
67c0d1eb | 6550 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6551 | break; |
252b5132 | 6552 | } |
df58fc94 | 6553 | do_addi_i: |
8fc2e39e | 6554 | used_at = 1; |
67c0d1eb RS |
6555 | load_register (AT, &imm_expr, dbl); |
6556 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6557 | break; |
6558 | ||
6559 | case M_AND_I: | |
6560 | s = "andi"; | |
6561 | s2 = "and"; | |
6562 | goto do_bit; | |
6563 | case M_OR_I: | |
6564 | s = "ori"; | |
6565 | s2 = "or"; | |
6566 | goto do_bit; | |
6567 | case M_NOR_I: | |
6568 | s = ""; | |
6569 | s2 = "nor"; | |
6570 | goto do_bit; | |
6571 | case M_XOR_I: | |
6572 | s = "xori"; | |
6573 | s2 = "xor"; | |
6574 | do_bit: | |
6575 | if (imm_expr.X_op == O_constant | |
6576 | && imm_expr.X_add_number >= 0 | |
6577 | && imm_expr.X_add_number < 0x10000) | |
6578 | { | |
6579 | if (mask != M_NOR_I) | |
67c0d1eb | 6580 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6581 | else |
6582 | { | |
67c0d1eb RS |
6583 | macro_build (&imm_expr, "ori", "t,r,i", |
6584 | treg, sreg, BFD_RELOC_LO16); | |
6585 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6586 | } |
8fc2e39e | 6587 | break; |
252b5132 RH |
6588 | } |
6589 | ||
8fc2e39e | 6590 | used_at = 1; |
67c0d1eb RS |
6591 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6592 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6593 | break; |
6594 | ||
8b082fb1 TS |
6595 | case M_BALIGN: |
6596 | switch (imm_expr.X_add_number) | |
6597 | { | |
6598 | case 0: | |
6599 | macro_build (NULL, "nop", ""); | |
6600 | break; | |
6601 | case 2: | |
6602 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6603 | break; | |
03f66e8a MR |
6604 | case 1: |
6605 | case 3: | |
8b082fb1 | 6606 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6607 | (int) imm_expr.X_add_number); |
8b082fb1 | 6608 | break; |
03f66e8a MR |
6609 | default: |
6610 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6611 | (unsigned long) imm_expr.X_add_number); | |
6612 | break; | |
8b082fb1 TS |
6613 | } |
6614 | break; | |
6615 | ||
df58fc94 RS |
6616 | case M_BC1FL: |
6617 | case M_BC1TL: | |
6618 | case M_BC2FL: | |
6619 | case M_BC2TL: | |
6620 | gas_assert (mips_opts.micromips); | |
6621 | macro_build_branch_ccl (mask, &offset_expr, | |
6622 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6623 | break; | |
6624 | ||
252b5132 | 6625 | case M_BEQ_I: |
252b5132 | 6626 | case M_BEQL_I: |
252b5132 | 6627 | case M_BNE_I: |
252b5132 | 6628 | case M_BNEL_I: |
252b5132 | 6629 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6630 | treg = 0; |
6631 | else | |
252b5132 | 6632 | { |
df58fc94 RS |
6633 | treg = AT; |
6634 | used_at = 1; | |
6635 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6636 | } |
df58fc94 RS |
6637 | /* Fall through. */ |
6638 | case M_BEQL: | |
6639 | case M_BNEL: | |
6640 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6641 | break; |
6642 | ||
6643 | case M_BGEL: | |
6644 | likely = 1; | |
6645 | case M_BGE: | |
6646 | if (treg == 0) | |
df58fc94 RS |
6647 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6648 | else if (sreg == 0) | |
6649 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6650 | else | |
252b5132 | 6651 | { |
df58fc94 RS |
6652 | used_at = 1; |
6653 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6654 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6655 | &offset_expr, AT, ZERO); | |
252b5132 | 6656 | } |
df58fc94 RS |
6657 | break; |
6658 | ||
6659 | case M_BGEZL: | |
6660 | case M_BGEZALL: | |
6661 | case M_BGTZL: | |
6662 | case M_BLEZL: | |
6663 | case M_BLTZL: | |
6664 | case M_BLTZALL: | |
6665 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6666 | break; |
6667 | ||
6668 | case M_BGTL_I: | |
6669 | likely = 1; | |
6670 | case M_BGT_I: | |
90ecf173 | 6671 | /* Check for > max integer. */ |
252b5132 | 6672 | maxnum = 0x7fffffff; |
ca4e0257 | 6673 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6674 | { |
6675 | maxnum <<= 16; | |
6676 | maxnum |= 0xffff; | |
6677 | maxnum <<= 16; | |
6678 | maxnum |= 0xffff; | |
6679 | } | |
6680 | if (imm_expr.X_op == O_constant | |
6681 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6682 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6683 | { |
6684 | do_false: | |
90ecf173 | 6685 | /* Result is always false. */ |
252b5132 | 6686 | if (! likely) |
a605d2b3 | 6687 | macro_build (NULL, "nop", ""); |
252b5132 | 6688 | else |
df58fc94 | 6689 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6690 | break; |
252b5132 RH |
6691 | } |
6692 | if (imm_expr.X_op != O_constant) | |
6693 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6694 | ++imm_expr.X_add_number; |
252b5132 RH |
6695 | /* FALLTHROUGH */ |
6696 | case M_BGE_I: | |
6697 | case M_BGEL_I: | |
6698 | if (mask == M_BGEL_I) | |
6699 | likely = 1; | |
6700 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6701 | { | |
df58fc94 RS |
6702 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6703 | &offset_expr, sreg); | |
8fc2e39e | 6704 | break; |
252b5132 RH |
6705 | } |
6706 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6707 | { | |
df58fc94 RS |
6708 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6709 | &offset_expr, sreg); | |
8fc2e39e | 6710 | break; |
252b5132 RH |
6711 | } |
6712 | maxnum = 0x7fffffff; | |
ca4e0257 | 6713 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6714 | { |
6715 | maxnum <<= 16; | |
6716 | maxnum |= 0xffff; | |
6717 | maxnum <<= 16; | |
6718 | maxnum |= 0xffff; | |
6719 | } | |
6720 | maxnum = - maxnum - 1; | |
6721 | if (imm_expr.X_op == O_constant | |
6722 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6723 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6724 | { |
6725 | do_true: | |
6726 | /* result is always true */ | |
6727 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6728 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6729 | break; |
252b5132 | 6730 | } |
8fc2e39e | 6731 | used_at = 1; |
67c0d1eb | 6732 | set_at (sreg, 0); |
df58fc94 RS |
6733 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6734 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6735 | break; |
6736 | ||
6737 | case M_BGEUL: | |
6738 | likely = 1; | |
6739 | case M_BGEU: | |
6740 | if (treg == 0) | |
6741 | goto do_true; | |
df58fc94 RS |
6742 | else if (sreg == 0) |
6743 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6744 | &offset_expr, ZERO, treg); | |
6745 | else | |
252b5132 | 6746 | { |
df58fc94 RS |
6747 | used_at = 1; |
6748 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6749 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6750 | &offset_expr, AT, ZERO); | |
252b5132 | 6751 | } |
252b5132 RH |
6752 | break; |
6753 | ||
6754 | case M_BGTUL_I: | |
6755 | likely = 1; | |
6756 | case M_BGTU_I: | |
6757 | if (sreg == 0 | |
ca4e0257 | 6758 | || (HAVE_32BIT_GPRS |
252b5132 | 6759 | && imm_expr.X_op == O_constant |
f01dc953 | 6760 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6761 | goto do_false; |
6762 | if (imm_expr.X_op != O_constant) | |
6763 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6764 | ++imm_expr.X_add_number; |
252b5132 RH |
6765 | /* FALLTHROUGH */ |
6766 | case M_BGEU_I: | |
6767 | case M_BGEUL_I: | |
6768 | if (mask == M_BGEUL_I) | |
6769 | likely = 1; | |
6770 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6771 | goto do_true; | |
df58fc94 RS |
6772 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6773 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6774 | &offset_expr, sreg, ZERO); | |
6775 | else | |
252b5132 | 6776 | { |
df58fc94 RS |
6777 | used_at = 1; |
6778 | set_at (sreg, 1); | |
6779 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6780 | &offset_expr, AT, ZERO); | |
252b5132 | 6781 | } |
252b5132 RH |
6782 | break; |
6783 | ||
6784 | case M_BGTL: | |
6785 | likely = 1; | |
6786 | case M_BGT: | |
6787 | if (treg == 0) | |
df58fc94 RS |
6788 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6789 | else if (sreg == 0) | |
6790 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6791 | else | |
252b5132 | 6792 | { |
df58fc94 RS |
6793 | used_at = 1; |
6794 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6795 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6796 | &offset_expr, AT, ZERO); | |
252b5132 | 6797 | } |
252b5132 RH |
6798 | break; |
6799 | ||
6800 | case M_BGTUL: | |
6801 | likely = 1; | |
6802 | case M_BGTU: | |
6803 | if (treg == 0) | |
df58fc94 RS |
6804 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6805 | &offset_expr, sreg, ZERO); | |
6806 | else if (sreg == 0) | |
6807 | goto do_false; | |
6808 | else | |
252b5132 | 6809 | { |
df58fc94 RS |
6810 | used_at = 1; |
6811 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6812 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6813 | &offset_expr, AT, ZERO); | |
252b5132 | 6814 | } |
252b5132 RH |
6815 | break; |
6816 | ||
6817 | case M_BLEL: | |
6818 | likely = 1; | |
6819 | case M_BLE: | |
6820 | if (treg == 0) | |
df58fc94 RS |
6821 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6822 | else if (sreg == 0) | |
6823 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6824 | else | |
252b5132 | 6825 | { |
df58fc94 RS |
6826 | used_at = 1; |
6827 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6828 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6829 | &offset_expr, AT, ZERO); | |
252b5132 | 6830 | } |
252b5132 RH |
6831 | break; |
6832 | ||
6833 | case M_BLEL_I: | |
6834 | likely = 1; | |
6835 | case M_BLE_I: | |
6836 | maxnum = 0x7fffffff; | |
ca4e0257 | 6837 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6838 | { |
6839 | maxnum <<= 16; | |
6840 | maxnum |= 0xffff; | |
6841 | maxnum <<= 16; | |
6842 | maxnum |= 0xffff; | |
6843 | } | |
6844 | if (imm_expr.X_op == O_constant | |
6845 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6846 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6847 | goto do_true; |
6848 | if (imm_expr.X_op != O_constant) | |
6849 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6850 | ++imm_expr.X_add_number; |
252b5132 RH |
6851 | /* FALLTHROUGH */ |
6852 | case M_BLT_I: | |
6853 | case M_BLTL_I: | |
6854 | if (mask == M_BLTL_I) | |
6855 | likely = 1; | |
6856 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6857 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6858 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6859 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6860 | else | |
252b5132 | 6861 | { |
df58fc94 RS |
6862 | used_at = 1; |
6863 | set_at (sreg, 0); | |
6864 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6865 | &offset_expr, AT, ZERO); | |
252b5132 | 6866 | } |
252b5132 RH |
6867 | break; |
6868 | ||
6869 | case M_BLEUL: | |
6870 | likely = 1; | |
6871 | case M_BLEU: | |
6872 | if (treg == 0) | |
df58fc94 RS |
6873 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6874 | &offset_expr, sreg, ZERO); | |
6875 | else if (sreg == 0) | |
6876 | goto do_true; | |
6877 | else | |
252b5132 | 6878 | { |
df58fc94 RS |
6879 | used_at = 1; |
6880 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6881 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6882 | &offset_expr, AT, ZERO); | |
252b5132 | 6883 | } |
252b5132 RH |
6884 | break; |
6885 | ||
6886 | case M_BLEUL_I: | |
6887 | likely = 1; | |
6888 | case M_BLEU_I: | |
6889 | if (sreg == 0 | |
ca4e0257 | 6890 | || (HAVE_32BIT_GPRS |
252b5132 | 6891 | && imm_expr.X_op == O_constant |
f01dc953 | 6892 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6893 | goto do_true; |
6894 | if (imm_expr.X_op != O_constant) | |
6895 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6896 | ++imm_expr.X_add_number; |
252b5132 RH |
6897 | /* FALLTHROUGH */ |
6898 | case M_BLTU_I: | |
6899 | case M_BLTUL_I: | |
6900 | if (mask == M_BLTUL_I) | |
6901 | likely = 1; | |
6902 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6903 | goto do_false; | |
df58fc94 RS |
6904 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6905 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6906 | &offset_expr, sreg, ZERO); | |
6907 | else | |
252b5132 | 6908 | { |
df58fc94 RS |
6909 | used_at = 1; |
6910 | set_at (sreg, 1); | |
6911 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6912 | &offset_expr, AT, ZERO); | |
252b5132 | 6913 | } |
252b5132 RH |
6914 | break; |
6915 | ||
6916 | case M_BLTL: | |
6917 | likely = 1; | |
6918 | case M_BLT: | |
6919 | if (treg == 0) | |
df58fc94 RS |
6920 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6921 | else if (sreg == 0) | |
6922 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6923 | else | |
252b5132 | 6924 | { |
df58fc94 RS |
6925 | used_at = 1; |
6926 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6927 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6928 | &offset_expr, AT, ZERO); | |
252b5132 | 6929 | } |
252b5132 RH |
6930 | break; |
6931 | ||
6932 | case M_BLTUL: | |
6933 | likely = 1; | |
6934 | case M_BLTU: | |
6935 | if (treg == 0) | |
6936 | goto do_false; | |
df58fc94 RS |
6937 | else if (sreg == 0) |
6938 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6939 | &offset_expr, ZERO, treg); | |
6940 | else | |
252b5132 | 6941 | { |
df58fc94 RS |
6942 | used_at = 1; |
6943 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6944 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6945 | &offset_expr, AT, ZERO); | |
252b5132 | 6946 | } |
252b5132 RH |
6947 | break; |
6948 | ||
5f74bc13 CD |
6949 | case M_DEXT: |
6950 | { | |
d5818fca MR |
6951 | /* Use unsigned arithmetic. */ |
6952 | addressT pos; | |
6953 | addressT size; | |
5f74bc13 | 6954 | |
90ecf173 | 6955 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6956 | { |
6957 | as_bad (_("Unsupported large constant")); | |
6958 | pos = size = 1; | |
6959 | } | |
6960 | else | |
6961 | { | |
d5818fca MR |
6962 | pos = imm_expr.X_add_number; |
6963 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6964 | } |
6965 | ||
6966 | if (pos > 63) | |
6967 | { | |
d5818fca | 6968 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6969 | pos = 1; |
6970 | } | |
90ecf173 | 6971 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6972 | { |
6973 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6974 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6975 | size = 1; |
6976 | } | |
6977 | ||
6978 | if (size <= 32 && pos < 32) | |
6979 | { | |
6980 | s = "dext"; | |
6981 | fmt = "t,r,+A,+C"; | |
6982 | } | |
6983 | else if (size <= 32) | |
6984 | { | |
6985 | s = "dextu"; | |
6986 | fmt = "t,r,+E,+H"; | |
6987 | } | |
6988 | else | |
6989 | { | |
6990 | s = "dextm"; | |
6991 | fmt = "t,r,+A,+G"; | |
6992 | } | |
d5818fca MR |
6993 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6994 | (int) (size - 1)); | |
5f74bc13 | 6995 | } |
8fc2e39e | 6996 | break; |
5f74bc13 CD |
6997 | |
6998 | case M_DINS: | |
6999 | { | |
d5818fca MR |
7000 | /* Use unsigned arithmetic. */ |
7001 | addressT pos; | |
7002 | addressT size; | |
5f74bc13 | 7003 | |
90ecf173 | 7004 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7005 | { |
7006 | as_bad (_("Unsupported large constant")); | |
7007 | pos = size = 1; | |
7008 | } | |
7009 | else | |
7010 | { | |
d5818fca MR |
7011 | pos = imm_expr.X_add_number; |
7012 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7013 | } |
7014 | ||
7015 | if (pos > 63) | |
7016 | { | |
d5818fca | 7017 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7018 | pos = 1; |
7019 | } | |
90ecf173 | 7020 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7021 | { |
7022 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7023 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7024 | size = 1; |
7025 | } | |
7026 | ||
7027 | if (pos < 32 && (pos + size - 1) < 32) | |
7028 | { | |
7029 | s = "dins"; | |
7030 | fmt = "t,r,+A,+B"; | |
7031 | } | |
7032 | else if (pos >= 32) | |
7033 | { | |
7034 | s = "dinsu"; | |
7035 | fmt = "t,r,+E,+F"; | |
7036 | } | |
7037 | else | |
7038 | { | |
7039 | s = "dinsm"; | |
7040 | fmt = "t,r,+A,+F"; | |
7041 | } | |
750bdd57 AS |
7042 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7043 | (int) (pos + size - 1)); | |
5f74bc13 | 7044 | } |
8fc2e39e | 7045 | break; |
5f74bc13 | 7046 | |
252b5132 RH |
7047 | case M_DDIV_3: |
7048 | dbl = 1; | |
7049 | case M_DIV_3: | |
7050 | s = "mflo"; | |
7051 | goto do_div3; | |
7052 | case M_DREM_3: | |
7053 | dbl = 1; | |
7054 | case M_REM_3: | |
7055 | s = "mfhi"; | |
7056 | do_div3: | |
7057 | if (treg == 0) | |
7058 | { | |
7059 | as_warn (_("Divide by zero.")); | |
7060 | if (mips_trap) | |
df58fc94 | 7061 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7062 | else |
df58fc94 | 7063 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7064 | break; |
252b5132 RH |
7065 | } |
7066 | ||
7d10b47d | 7067 | start_noreorder (); |
252b5132 RH |
7068 | if (mips_trap) |
7069 | { | |
df58fc94 | 7070 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7071 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7072 | } |
7073 | else | |
7074 | { | |
df58fc94 RS |
7075 | if (mips_opts.micromips) |
7076 | micromips_label_expr (&label_expr); | |
7077 | else | |
7078 | label_expr.X_add_number = 8; | |
7079 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7080 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7081 | macro_build (NULL, "break", BRK_FMT, 7); |
7082 | if (mips_opts.micromips) | |
7083 | micromips_add_label (); | |
252b5132 RH |
7084 | } |
7085 | expr1.X_add_number = -1; | |
8fc2e39e | 7086 | used_at = 1; |
f6a22291 | 7087 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7088 | if (mips_opts.micromips) |
7089 | micromips_label_expr (&label_expr); | |
7090 | else | |
7091 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7092 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7093 | if (dbl) |
7094 | { | |
7095 | expr1.X_add_number = 1; | |
f6a22291 | 7096 | load_register (AT, &expr1, dbl); |
df58fc94 | 7097 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7098 | } |
7099 | else | |
7100 | { | |
7101 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7102 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7103 | } |
7104 | if (mips_trap) | |
7105 | { | |
df58fc94 | 7106 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7107 | /* We want to close the noreorder block as soon as possible, so |
7108 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7109 | end_noreorder (); |
252b5132 RH |
7110 | } |
7111 | else | |
7112 | { | |
df58fc94 RS |
7113 | if (mips_opts.micromips) |
7114 | micromips_label_expr (&label_expr); | |
7115 | else | |
7116 | label_expr.X_add_number = 8; | |
7117 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7118 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7119 | |
7120 | /* We want to close the noreorder block as soon as possible, so | |
7121 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7122 | end_noreorder (); |
252b5132 | 7123 | |
df58fc94 | 7124 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7125 | } |
df58fc94 RS |
7126 | if (mips_opts.micromips) |
7127 | micromips_add_label (); | |
7128 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7129 | break; |
7130 | ||
7131 | case M_DIV_3I: | |
7132 | s = "div"; | |
7133 | s2 = "mflo"; | |
7134 | goto do_divi; | |
7135 | case M_DIVU_3I: | |
7136 | s = "divu"; | |
7137 | s2 = "mflo"; | |
7138 | goto do_divi; | |
7139 | case M_REM_3I: | |
7140 | s = "div"; | |
7141 | s2 = "mfhi"; | |
7142 | goto do_divi; | |
7143 | case M_REMU_3I: | |
7144 | s = "divu"; | |
7145 | s2 = "mfhi"; | |
7146 | goto do_divi; | |
7147 | case M_DDIV_3I: | |
7148 | dbl = 1; | |
7149 | s = "ddiv"; | |
7150 | s2 = "mflo"; | |
7151 | goto do_divi; | |
7152 | case M_DDIVU_3I: | |
7153 | dbl = 1; | |
7154 | s = "ddivu"; | |
7155 | s2 = "mflo"; | |
7156 | goto do_divi; | |
7157 | case M_DREM_3I: | |
7158 | dbl = 1; | |
7159 | s = "ddiv"; | |
7160 | s2 = "mfhi"; | |
7161 | goto do_divi; | |
7162 | case M_DREMU_3I: | |
7163 | dbl = 1; | |
7164 | s = "ddivu"; | |
7165 | s2 = "mfhi"; | |
7166 | do_divi: | |
7167 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7168 | { | |
7169 | as_warn (_("Divide by zero.")); | |
7170 | if (mips_trap) | |
df58fc94 | 7171 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7172 | else |
df58fc94 | 7173 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7174 | break; |
252b5132 RH |
7175 | } |
7176 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7177 | { | |
7178 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7179 | move_register (dreg, sreg); |
252b5132 | 7180 | else |
c80c840e | 7181 | move_register (dreg, ZERO); |
8fc2e39e | 7182 | break; |
252b5132 RH |
7183 | } |
7184 | if (imm_expr.X_op == O_constant | |
7185 | && imm_expr.X_add_number == -1 | |
7186 | && s[strlen (s) - 1] != 'u') | |
7187 | { | |
7188 | if (strcmp (s2, "mflo") == 0) | |
7189 | { | |
67c0d1eb | 7190 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7191 | } |
7192 | else | |
c80c840e | 7193 | move_register (dreg, ZERO); |
8fc2e39e | 7194 | break; |
252b5132 RH |
7195 | } |
7196 | ||
8fc2e39e | 7197 | used_at = 1; |
67c0d1eb RS |
7198 | load_register (AT, &imm_expr, dbl); |
7199 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7200 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7201 | break; |
7202 | ||
7203 | case M_DIVU_3: | |
7204 | s = "divu"; | |
7205 | s2 = "mflo"; | |
7206 | goto do_divu3; | |
7207 | case M_REMU_3: | |
7208 | s = "divu"; | |
7209 | s2 = "mfhi"; | |
7210 | goto do_divu3; | |
7211 | case M_DDIVU_3: | |
7212 | s = "ddivu"; | |
7213 | s2 = "mflo"; | |
7214 | goto do_divu3; | |
7215 | case M_DREMU_3: | |
7216 | s = "ddivu"; | |
7217 | s2 = "mfhi"; | |
7218 | do_divu3: | |
7d10b47d | 7219 | start_noreorder (); |
252b5132 RH |
7220 | if (mips_trap) |
7221 | { | |
df58fc94 | 7222 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7223 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7224 | /* We want to close the noreorder block as soon as possible, so |
7225 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7226 | end_noreorder (); |
252b5132 RH |
7227 | } |
7228 | else | |
7229 | { | |
df58fc94 RS |
7230 | if (mips_opts.micromips) |
7231 | micromips_label_expr (&label_expr); | |
7232 | else | |
7233 | label_expr.X_add_number = 8; | |
7234 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7235 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7236 | |
7237 | /* We want to close the noreorder block as soon as possible, so | |
7238 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7239 | end_noreorder (); |
df58fc94 RS |
7240 | macro_build (NULL, "break", BRK_FMT, 7); |
7241 | if (mips_opts.micromips) | |
7242 | micromips_add_label (); | |
252b5132 | 7243 | } |
df58fc94 | 7244 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7245 | break; |
252b5132 | 7246 | |
1abe91b1 MR |
7247 | case M_DLCA_AB: |
7248 | dbl = 1; | |
7249 | case M_LCA_AB: | |
7250 | call = 1; | |
7251 | goto do_la; | |
252b5132 RH |
7252 | case M_DLA_AB: |
7253 | dbl = 1; | |
7254 | case M_LA_AB: | |
1abe91b1 | 7255 | do_la: |
252b5132 RH |
7256 | /* Load the address of a symbol into a register. If breg is not |
7257 | zero, we then add a base register to it. */ | |
7258 | ||
3bec30a8 TS |
7259 | if (dbl && HAVE_32BIT_GPRS) |
7260 | as_warn (_("dla used to load 32-bit register")); | |
7261 | ||
90ecf173 | 7262 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7263 | as_warn (_("la used to load 64-bit address")); |
7264 | ||
0c11417f MR |
7265 | if (offset_expr.X_op == O_constant |
7266 | && offset_expr.X_add_number >= -0x8000 | |
7267 | && offset_expr.X_add_number < 0x8000) | |
7268 | { | |
aed1a261 | 7269 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7270 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7271 | break; |
0c11417f MR |
7272 | } |
7273 | ||
741fe287 | 7274 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7275 | { |
7276 | tempreg = AT; | |
7277 | used_at = 1; | |
7278 | } | |
7279 | else | |
7280 | { | |
7281 | tempreg = treg; | |
afdbd6d0 CD |
7282 | } |
7283 | ||
252b5132 RH |
7284 | if (offset_expr.X_op != O_symbol |
7285 | && offset_expr.X_op != O_constant) | |
7286 | { | |
f71d0d44 | 7287 | as_bad (_("Expression too complex")); |
252b5132 RH |
7288 | offset_expr.X_op = O_constant; |
7289 | } | |
7290 | ||
252b5132 | 7291 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7292 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7293 | else if (mips_pic == NO_PIC) |
7294 | { | |
d6bc6245 | 7295 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7296 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7297 | Otherwise we want |
7298 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7299 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7300 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7301 | so we may as well always use the latter form. |
76b3015f | 7302 | |
6caf9ef4 TS |
7303 | With 64bit address space and a usable $at we want |
7304 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7305 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7306 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7307 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7308 | dsll32 $tempreg,0 | |
7309 | daddu $tempreg,$tempreg,$at | |
7310 | ||
7311 | If $at is already in use, we use a path which is suboptimal | |
7312 | on superscalar processors. | |
7313 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7314 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7315 | dsll $tempreg,16 | |
7316 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7317 | dsll $tempreg,16 | |
7318 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7319 | ||
7320 | For GP relative symbols in 64bit address space we can use | |
7321 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7322 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7323 | { |
6caf9ef4 TS |
7324 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7325 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7326 | { | |
7327 | relax_start (offset_expr.X_add_symbol); | |
7328 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7329 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7330 | relax_switch (); | |
7331 | } | |
d6bc6245 | 7332 | |
741fe287 | 7333 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7334 | { |
df58fc94 | 7335 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7336 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7337 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7338 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7339 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7340 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7341 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7342 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7343 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7344 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7345 | used_at = 1; |
7346 | } | |
7347 | else | |
7348 | { | |
df58fc94 | 7349 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7350 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7351 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7352 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7353 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7354 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7355 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7356 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7357 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7358 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7359 | } |
6caf9ef4 TS |
7360 | |
7361 | if (mips_relax.sequence) | |
7362 | relax_end (); | |
98d3f06f KH |
7363 | } |
7364 | else | |
7365 | { | |
7366 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7367 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7368 | { |
4d7206a2 | 7369 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7370 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7371 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7372 | relax_switch (); |
98d3f06f | 7373 | } |
6943caf0 | 7374 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7375 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7376 | macro_build_lui (&offset_expr, tempreg); |
7377 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7378 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7379 | if (mips_relax.sequence) |
7380 | relax_end (); | |
98d3f06f | 7381 | } |
252b5132 | 7382 | } |
0a44bf69 | 7383 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7384 | { |
9117d219 NC |
7385 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7386 | ||
252b5132 RH |
7387 | /* If this is a reference to an external symbol, and there |
7388 | is no constant, we want | |
7389 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7390 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7391 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7392 | For a local symbol, we want |
7393 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7394 | nop | |
7395 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7396 | ||
7397 | If we have a small constant, and this is a reference to | |
7398 | an external symbol, we want | |
7399 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7400 | nop | |
7401 | addiu $tempreg,$tempreg,<constant> | |
7402 | For a local symbol, we want the same instruction | |
7403 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7404 | addiu instruction. | |
7405 | ||
7406 | If we have a large constant, and this is a reference to | |
7407 | an external symbol, we want | |
7408 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7409 | lui $at,<hiconstant> | |
7410 | addiu $at,$at,<loconstant> | |
7411 | addu $tempreg,$tempreg,$at | |
7412 | For a local symbol, we want the same instruction | |
7413 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7414 | addiu instruction. |
ed6fb7bd SC |
7415 | */ |
7416 | ||
4d7206a2 | 7417 | if (offset_expr.X_add_number == 0) |
252b5132 | 7418 | { |
0a44bf69 RS |
7419 | if (mips_pic == SVR4_PIC |
7420 | && breg == 0 | |
7421 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7422 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7423 | ||
7424 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7425 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7426 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7427 | if (breg != 0) |
252b5132 RH |
7428 | { |
7429 | /* We're going to put in an addu instruction using | |
7430 | tempreg, so we may as well insert the nop right | |
7431 | now. */ | |
269137b2 | 7432 | load_delay_nop (); |
252b5132 | 7433 | } |
4d7206a2 | 7434 | relax_switch (); |
67c0d1eb RS |
7435 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7436 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7437 | load_delay_nop (); |
67c0d1eb RS |
7438 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7439 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7440 | relax_end (); |
252b5132 RH |
7441 | /* FIXME: If breg == 0, and the next instruction uses |
7442 | $tempreg, then if this variant case is used an extra | |
7443 | nop will be generated. */ | |
7444 | } | |
4d7206a2 RS |
7445 | else if (offset_expr.X_add_number >= -0x8000 |
7446 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7447 | { |
67c0d1eb | 7448 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7449 | load_delay_nop (); |
67c0d1eb | 7450 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7451 | } |
7452 | else | |
7453 | { | |
4d7206a2 RS |
7454 | expr1.X_add_number = offset_expr.X_add_number; |
7455 | offset_expr.X_add_number = | |
43c0598f | 7456 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7457 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7458 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7459 | /* If we are going to add in a base register, and the |
7460 | target register and the base register are the same, | |
7461 | then we are using AT as a temporary register. Since | |
7462 | we want to load the constant into AT, we add our | |
7463 | current AT (from the global offset table) and the | |
7464 | register into the register now, and pretend we were | |
7465 | not using a base register. */ | |
67c0d1eb | 7466 | if (breg == treg) |
252b5132 | 7467 | { |
269137b2 | 7468 | load_delay_nop (); |
67c0d1eb | 7469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7470 | treg, AT, breg); |
252b5132 RH |
7471 | breg = 0; |
7472 | tempreg = treg; | |
252b5132 | 7473 | } |
f6a22291 | 7474 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7475 | used_at = 1; |
7476 | } | |
7477 | } | |
0a44bf69 | 7478 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7479 | { |
67c0d1eb | 7480 | int add_breg_early = 0; |
f5040a92 AO |
7481 | |
7482 | /* If this is a reference to an external, and there is no | |
7483 | constant, or local symbol (*), with or without a | |
7484 | constant, we want | |
7485 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7486 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7487 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7488 | ||
7489 | If we have a small constant, and this is a reference to | |
7490 | an external symbol, we want | |
7491 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7492 | addiu $tempreg,$tempreg,<constant> | |
7493 | ||
7494 | If we have a large constant, and this is a reference to | |
7495 | an external symbol, we want | |
7496 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7497 | lui $at,<hiconstant> | |
7498 | addiu $at,$at,<loconstant> | |
7499 | addu $tempreg,$tempreg,$at | |
7500 | ||
7501 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7502 | local symbols, even though it introduces an additional | |
7503 | instruction. */ | |
7504 | ||
f5040a92 AO |
7505 | if (offset_expr.X_add_number) |
7506 | { | |
4d7206a2 | 7507 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7508 | offset_expr.X_add_number = 0; |
7509 | ||
4d7206a2 | 7510 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7511 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7512 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7513 | |
7514 | if (expr1.X_add_number >= -0x8000 | |
7515 | && expr1.X_add_number < 0x8000) | |
7516 | { | |
67c0d1eb RS |
7517 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7518 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7519 | } |
ecd13cd3 | 7520 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7521 | { |
f5040a92 AO |
7522 | /* If we are going to add in a base register, and the |
7523 | target register and the base register are the same, | |
7524 | then we are using AT as a temporary register. Since | |
7525 | we want to load the constant into AT, we add our | |
7526 | current AT (from the global offset table) and the | |
7527 | register into the register now, and pretend we were | |
7528 | not using a base register. */ | |
7529 | if (breg != treg) | |
7530 | dreg = tempreg; | |
7531 | else | |
7532 | { | |
9c2799c2 | 7533 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7534 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7535 | treg, AT, breg); | |
f5040a92 | 7536 | dreg = treg; |
67c0d1eb | 7537 | add_breg_early = 1; |
f5040a92 AO |
7538 | } |
7539 | ||
f6a22291 | 7540 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7541 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7542 | dreg, dreg, AT); |
f5040a92 | 7543 | |
f5040a92 AO |
7544 | used_at = 1; |
7545 | } | |
7546 | else | |
7547 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7548 | ||
4d7206a2 | 7549 | relax_switch (); |
f5040a92 AO |
7550 | offset_expr.X_add_number = expr1.X_add_number; |
7551 | ||
67c0d1eb RS |
7552 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7553 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7554 | if (add_breg_early) | |
f5040a92 | 7555 | { |
67c0d1eb | 7556 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7557 | treg, tempreg, breg); |
f5040a92 AO |
7558 | breg = 0; |
7559 | tempreg = treg; | |
7560 | } | |
4d7206a2 | 7561 | relax_end (); |
f5040a92 | 7562 | } |
4d7206a2 | 7563 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7564 | { |
4d7206a2 | 7565 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7566 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7567 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7568 | relax_switch (); |
67c0d1eb RS |
7569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7570 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7571 | relax_end (); |
f5040a92 | 7572 | } |
4d7206a2 | 7573 | else |
f5040a92 | 7574 | { |
67c0d1eb RS |
7575 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7576 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7577 | } |
7578 | } | |
0a44bf69 | 7579 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7580 | { |
67c0d1eb | 7581 | int gpdelay; |
9117d219 NC |
7582 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7583 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7584 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7585 | |
7586 | /* This is the large GOT case. If this is a reference to an | |
7587 | external symbol, and there is no constant, we want | |
7588 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7589 | addu $tempreg,$tempreg,$gp | |
7590 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7591 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7592 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7593 | addu $tempreg,$tempreg,$gp | |
7594 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7595 | For a local symbol, we want |
7596 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7597 | nop | |
7598 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7599 | ||
7600 | If we have a small constant, and this is a reference to | |
7601 | an external symbol, we want | |
7602 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7603 | addu $tempreg,$tempreg,$gp | |
7604 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7605 | nop | |
7606 | addiu $tempreg,$tempreg,<constant> | |
7607 | For a local symbol, we want | |
7608 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7609 | nop | |
7610 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7611 | ||
7612 | If we have a large constant, and this is a reference to | |
7613 | an external symbol, we want | |
7614 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7615 | addu $tempreg,$tempreg,$gp | |
7616 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7617 | lui $at,<hiconstant> | |
7618 | addiu $at,$at,<loconstant> | |
7619 | addu $tempreg,$tempreg,$at | |
7620 | For a local symbol, we want | |
7621 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7622 | lui $at,<hiconstant> | |
7623 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7624 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7625 | */ |
438c16b8 | 7626 | |
252b5132 RH |
7627 | expr1.X_add_number = offset_expr.X_add_number; |
7628 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7629 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7630 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7631 | if (expr1.X_add_number == 0 && breg == 0 |
7632 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7633 | { |
7634 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7635 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7636 | } | |
df58fc94 | 7637 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7638 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7639 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7640 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7641 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7642 | if (expr1.X_add_number == 0) |
7643 | { | |
67c0d1eb | 7644 | if (breg != 0) |
252b5132 RH |
7645 | { |
7646 | /* We're going to put in an addu instruction using | |
7647 | tempreg, so we may as well insert the nop right | |
7648 | now. */ | |
269137b2 | 7649 | load_delay_nop (); |
252b5132 | 7650 | } |
252b5132 RH |
7651 | } |
7652 | else if (expr1.X_add_number >= -0x8000 | |
7653 | && expr1.X_add_number < 0x8000) | |
7654 | { | |
269137b2 | 7655 | load_delay_nop (); |
67c0d1eb | 7656 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7657 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7658 | } |
7659 | else | |
7660 | { | |
252b5132 RH |
7661 | /* If we are going to add in a base register, and the |
7662 | target register and the base register are the same, | |
7663 | then we are using AT as a temporary register. Since | |
7664 | we want to load the constant into AT, we add our | |
7665 | current AT (from the global offset table) and the | |
7666 | register into the register now, and pretend we were | |
7667 | not using a base register. */ | |
7668 | if (breg != treg) | |
67c0d1eb | 7669 | dreg = tempreg; |
252b5132 RH |
7670 | else |
7671 | { | |
9c2799c2 | 7672 | gas_assert (tempreg == AT); |
269137b2 | 7673 | load_delay_nop (); |
67c0d1eb | 7674 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7675 | treg, AT, breg); |
252b5132 | 7676 | dreg = treg; |
252b5132 RH |
7677 | } |
7678 | ||
f6a22291 | 7679 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7680 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7681 | |
252b5132 RH |
7682 | used_at = 1; |
7683 | } | |
43c0598f | 7684 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7685 | relax_switch (); |
252b5132 | 7686 | |
67c0d1eb | 7687 | if (gpdelay) |
252b5132 RH |
7688 | { |
7689 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7690 | the first instruction on the main stream does not. */ |
67c0d1eb | 7691 | macro_build (NULL, "nop", ""); |
252b5132 | 7692 | } |
ed6fb7bd | 7693 | |
67c0d1eb RS |
7694 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7695 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7696 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7697 | && expr1.X_add_number < 0x8000) |
7698 | { | |
269137b2 | 7699 | load_delay_nop (); |
67c0d1eb RS |
7700 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7701 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7702 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7703 | register, the external symbol case ended with a load, |
7704 | so if the symbol turns out to not be external, and | |
7705 | the next instruction uses tempreg, an unnecessary nop | |
7706 | will be inserted. */ | |
252b5132 RH |
7707 | } |
7708 | else | |
7709 | { | |
7710 | if (breg == treg) | |
7711 | { | |
7712 | /* We must add in the base register now, as in the | |
f5040a92 | 7713 | external symbol case. */ |
9c2799c2 | 7714 | gas_assert (tempreg == AT); |
269137b2 | 7715 | load_delay_nop (); |
67c0d1eb | 7716 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7717 | treg, AT, breg); |
252b5132 RH |
7718 | tempreg = treg; |
7719 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7720 | it in in both cases. */ |
252b5132 RH |
7721 | breg = 0; |
7722 | } | |
7723 | ||
67c0d1eb RS |
7724 | macro_build_lui (&expr1, AT); |
7725 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7726 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7727 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7728 | tempreg, tempreg, AT); |
8fc2e39e | 7729 | used_at = 1; |
252b5132 | 7730 | } |
4d7206a2 | 7731 | relax_end (); |
252b5132 | 7732 | } |
0a44bf69 | 7733 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7734 | { |
f5040a92 AO |
7735 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7736 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7737 | int add_breg_early = 0; |
f5040a92 AO |
7738 | |
7739 | /* This is the large GOT case. If this is a reference to an | |
7740 | external symbol, and there is no constant, we want | |
7741 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7742 | add $tempreg,$tempreg,$gp | |
7743 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7744 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7745 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7746 | add $tempreg,$tempreg,$gp | |
7747 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7748 | ||
7749 | If we have a small constant, and this is a reference to | |
7750 | an external symbol, we want | |
7751 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7752 | add $tempreg,$tempreg,$gp | |
7753 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7754 | addi $tempreg,$tempreg,<constant> | |
7755 | ||
7756 | If we have a large constant, and this is a reference to | |
7757 | an external symbol, we want | |
7758 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7759 | addu $tempreg,$tempreg,$gp | |
7760 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7761 | lui $at,<hiconstant> | |
7762 | addi $at,$at,<loconstant> | |
7763 | add $tempreg,$tempreg,$at | |
7764 | ||
7765 | If we have NewABI, and we know it's a local symbol, we want | |
7766 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7767 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7768 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7769 | ||
4d7206a2 | 7770 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7771 | |
4d7206a2 | 7772 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7773 | offset_expr.X_add_number = 0; |
7774 | ||
1abe91b1 MR |
7775 | if (expr1.X_add_number == 0 && breg == 0 |
7776 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7777 | { |
7778 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7779 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7780 | } | |
df58fc94 | 7781 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7782 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7783 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7784 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7785 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7786 | |
7787 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7788 | ; |
f5040a92 AO |
7789 | else if (expr1.X_add_number >= -0x8000 |
7790 | && expr1.X_add_number < 0x8000) | |
7791 | { | |
67c0d1eb | 7792 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7793 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7794 | } |
ecd13cd3 | 7795 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7796 | { |
f5040a92 AO |
7797 | /* If we are going to add in a base register, and the |
7798 | target register and the base register are the same, | |
7799 | then we are using AT as a temporary register. Since | |
7800 | we want to load the constant into AT, we add our | |
7801 | current AT (from the global offset table) and the | |
7802 | register into the register now, and pretend we were | |
7803 | not using a base register. */ | |
7804 | if (breg != treg) | |
7805 | dreg = tempreg; | |
7806 | else | |
7807 | { | |
9c2799c2 | 7808 | gas_assert (tempreg == AT); |
67c0d1eb | 7809 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7810 | treg, AT, breg); |
f5040a92 | 7811 | dreg = treg; |
67c0d1eb | 7812 | add_breg_early = 1; |
f5040a92 AO |
7813 | } |
7814 | ||
f6a22291 | 7815 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7816 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7817 | |
f5040a92 AO |
7818 | used_at = 1; |
7819 | } | |
7820 | else | |
7821 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7822 | ||
4d7206a2 | 7823 | relax_switch (); |
f5040a92 | 7824 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7825 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7826 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7827 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7828 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7829 | if (add_breg_early) | |
f5040a92 | 7830 | { |
67c0d1eb | 7831 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7832 | treg, tempreg, breg); |
f5040a92 AO |
7833 | breg = 0; |
7834 | tempreg = treg; | |
7835 | } | |
4d7206a2 | 7836 | relax_end (); |
f5040a92 | 7837 | } |
252b5132 RH |
7838 | else |
7839 | abort (); | |
7840 | ||
7841 | if (breg != 0) | |
aed1a261 | 7842 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7843 | break; |
7844 | ||
52b6b6b9 | 7845 | case M_MSGSND: |
df58fc94 | 7846 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7847 | { |
7848 | unsigned long temp = (treg << 16) | (0x01); | |
7849 | macro_build (NULL, "c2", "C", temp); | |
7850 | } | |
c7af4273 | 7851 | break; |
52b6b6b9 JM |
7852 | |
7853 | case M_MSGLD: | |
df58fc94 | 7854 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7855 | { |
7856 | unsigned long temp = (0x02); | |
7857 | macro_build (NULL, "c2", "C", temp); | |
7858 | } | |
c7af4273 | 7859 | break; |
52b6b6b9 JM |
7860 | |
7861 | case M_MSGLD_T: | |
df58fc94 | 7862 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7863 | { |
7864 | unsigned long temp = (treg << 16) | (0x02); | |
7865 | macro_build (NULL, "c2", "C", temp); | |
7866 | } | |
c7af4273 | 7867 | break; |
52b6b6b9 JM |
7868 | |
7869 | case M_MSGWAIT: | |
df58fc94 | 7870 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7871 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7872 | break; |
52b6b6b9 JM |
7873 | |
7874 | case M_MSGWAIT_T: | |
df58fc94 | 7875 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7876 | { |
7877 | unsigned long temp = (treg << 16) | 0x03; | |
7878 | macro_build (NULL, "c2", "C", temp); | |
7879 | } | |
c7af4273 | 7880 | break; |
52b6b6b9 | 7881 | |
252b5132 RH |
7882 | case M_J_A: |
7883 | /* The j instruction may not be used in PIC code, since it | |
7884 | requires an absolute address. We convert it to a b | |
7885 | instruction. */ | |
7886 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7887 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7888 | else |
67c0d1eb | 7889 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7890 | break; |
252b5132 RH |
7891 | |
7892 | /* The jal instructions must be handled as macros because when | |
7893 | generating PIC code they expand to multi-instruction | |
7894 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7895 | case M_JALS_1: |
7896 | dreg = RA; | |
7897 | /* Fall through. */ | |
7898 | case M_JALS_2: | |
7899 | gas_assert (mips_opts.micromips); | |
7900 | jals = 1; | |
7901 | goto jal; | |
252b5132 RH |
7902 | case M_JAL_1: |
7903 | dreg = RA; | |
7904 | /* Fall through. */ | |
7905 | case M_JAL_2: | |
df58fc94 | 7906 | jal: |
3e722fb5 | 7907 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7908 | { |
7909 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7910 | if (mips_opts.micromips |
7911 | && dreg == RA | |
7912 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7913 | macro_build (NULL, s, "mj", sreg); |
7914 | else | |
7915 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7916 | } | |
0a44bf69 | 7917 | else |
252b5132 | 7918 | { |
df58fc94 RS |
7919 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7920 | && mips_cprestore_offset >= 0); | |
7921 | ||
252b5132 RH |
7922 | if (sreg != PIC_CALL_REG) |
7923 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7924 | |
df58fc94 RS |
7925 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7926 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7927 | if (mips_opts.micromips |
7928 | && dreg == RA | |
7929 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7930 | macro_build (NULL, s, "mj", sreg); |
7931 | else | |
7932 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7933 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7934 | { |
6478892d TS |
7935 | if (mips_cprestore_offset < 0) |
7936 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7937 | else | |
7938 | { | |
90ecf173 | 7939 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7940 | { |
7941 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7942 | /* Quiet this warning. */ | |
7943 | mips_frame_reg_valid = 1; | |
7944 | } | |
90ecf173 | 7945 | if (!mips_cprestore_valid) |
7a621144 DJ |
7946 | { |
7947 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7948 | /* Quiet this warning. */ | |
7949 | mips_cprestore_valid = 1; | |
7950 | } | |
d3fca0b5 MR |
7951 | if (mips_opts.noreorder) |
7952 | macro_build (NULL, "nop", ""); | |
6478892d | 7953 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7954 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7955 | mips_gp_register, |
256ab948 TS |
7956 | mips_frame_reg, |
7957 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7958 | } |
252b5132 RH |
7959 | } |
7960 | } | |
252b5132 | 7961 | |
8fc2e39e | 7962 | break; |
252b5132 | 7963 | |
df58fc94 RS |
7964 | case M_JALS_A: |
7965 | gas_assert (mips_opts.micromips); | |
7966 | jals = 1; | |
7967 | /* Fall through. */ | |
252b5132 RH |
7968 | case M_JAL_A: |
7969 | if (mips_pic == NO_PIC) | |
df58fc94 | 7970 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7971 | else if (mips_pic == SVR4_PIC) |
7972 | { | |
7973 | /* If this is a reference to an external symbol, and we are | |
7974 | using a small GOT, we want | |
7975 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7976 | nop | |
f9419b05 | 7977 | jalr $ra,$25 |
252b5132 RH |
7978 | nop |
7979 | lw $gp,cprestore($sp) | |
7980 | The cprestore value is set using the .cprestore | |
7981 | pseudo-op. If we are using a big GOT, we want | |
7982 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7983 | addu $25,$25,$gp | |
7984 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7985 | nop | |
f9419b05 | 7986 | jalr $ra,$25 |
252b5132 RH |
7987 | nop |
7988 | lw $gp,cprestore($sp) | |
7989 | If the symbol is not external, we want | |
7990 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7991 | nop | |
7992 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7993 | jalr $ra,$25 |
252b5132 | 7994 | nop |
438c16b8 | 7995 | lw $gp,cprestore($sp) |
f5040a92 AO |
7996 | |
7997 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7998 | sequences above, minus nops, unless the symbol is local, | |
7999 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8000 | GOT_DISP. */ | |
438c16b8 | 8001 | if (HAVE_NEWABI) |
252b5132 | 8002 | { |
90ecf173 | 8003 | if (!mips_big_got) |
f5040a92 | 8004 | { |
4d7206a2 | 8005 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8006 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8007 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8008 | mips_gp_register); |
4d7206a2 | 8009 | relax_switch (); |
67c0d1eb RS |
8010 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8011 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8012 | mips_gp_register); |
8013 | relax_end (); | |
f5040a92 AO |
8014 | } |
8015 | else | |
8016 | { | |
4d7206a2 | 8017 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8018 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8019 | BFD_RELOC_MIPS_CALL_HI16); |
8020 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8021 | PIC_CALL_REG, mips_gp_register); | |
8022 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8023 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8024 | PIC_CALL_REG); | |
4d7206a2 | 8025 | relax_switch (); |
67c0d1eb RS |
8026 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8027 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8028 | mips_gp_register); | |
8029 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8030 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8031 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8032 | relax_end (); |
f5040a92 | 8033 | } |
684022ea | 8034 | |
df58fc94 | 8035 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8036 | } |
8037 | else | |
8038 | { | |
4d7206a2 | 8039 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8040 | if (!mips_big_got) |
438c16b8 | 8041 | { |
67c0d1eb RS |
8042 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8043 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8044 | mips_gp_register); |
269137b2 | 8045 | load_delay_nop (); |
4d7206a2 | 8046 | relax_switch (); |
438c16b8 | 8047 | } |
252b5132 | 8048 | else |
252b5132 | 8049 | { |
67c0d1eb RS |
8050 | int gpdelay; |
8051 | ||
8052 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8053 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8054 | BFD_RELOC_MIPS_CALL_HI16); |
8055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8056 | PIC_CALL_REG, mips_gp_register); | |
8057 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8058 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8059 | PIC_CALL_REG); | |
269137b2 | 8060 | load_delay_nop (); |
4d7206a2 | 8061 | relax_switch (); |
67c0d1eb RS |
8062 | if (gpdelay) |
8063 | macro_build (NULL, "nop", ""); | |
252b5132 | 8064 | } |
67c0d1eb RS |
8065 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8066 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8067 | mips_gp_register); |
269137b2 | 8068 | load_delay_nop (); |
67c0d1eb RS |
8069 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8070 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8071 | relax_end (); |
df58fc94 | 8072 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8073 | |
6478892d TS |
8074 | if (mips_cprestore_offset < 0) |
8075 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8076 | else | |
8077 | { | |
90ecf173 | 8078 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8079 | { |
8080 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8081 | /* Quiet this warning. */ | |
8082 | mips_frame_reg_valid = 1; | |
8083 | } | |
90ecf173 | 8084 | if (!mips_cprestore_valid) |
7a621144 DJ |
8085 | { |
8086 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8087 | /* Quiet this warning. */ | |
8088 | mips_cprestore_valid = 1; | |
8089 | } | |
6478892d | 8090 | if (mips_opts.noreorder) |
67c0d1eb | 8091 | macro_build (NULL, "nop", ""); |
6478892d | 8092 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8093 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8094 | mips_gp_register, |
256ab948 TS |
8095 | mips_frame_reg, |
8096 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8097 | } |
252b5132 RH |
8098 | } |
8099 | } | |
0a44bf69 RS |
8100 | else if (mips_pic == VXWORKS_PIC) |
8101 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8102 | else |
8103 | abort (); | |
8104 | ||
8fc2e39e | 8105 | break; |
252b5132 | 8106 | |
dec0624d MR |
8107 | case M_ACLR_AB: |
8108 | ab = 1; | |
8109 | case M_ACLR_OB: | |
8110 | s = "aclr"; | |
8111 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8112 | fmt = "\\,~(b)"; | |
8113 | off12 = 1; | |
8114 | goto ld_st; | |
8115 | case M_ASET_AB: | |
8116 | ab = 1; | |
8117 | case M_ASET_OB: | |
8118 | s = "aset"; | |
8119 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8120 | fmt = "\\,~(b)"; | |
8121 | off12 = 1; | |
8122 | goto ld_st; | |
252b5132 | 8123 | case M_LB_AB: |
df58fc94 | 8124 | ab = 1; |
252b5132 | 8125 | s = "lb"; |
df58fc94 | 8126 | fmt = "t,o(b)"; |
252b5132 RH |
8127 | goto ld; |
8128 | case M_LBU_AB: | |
df58fc94 | 8129 | ab = 1; |
252b5132 | 8130 | s = "lbu"; |
df58fc94 | 8131 | fmt = "t,o(b)"; |
252b5132 RH |
8132 | goto ld; |
8133 | case M_LH_AB: | |
df58fc94 | 8134 | ab = 1; |
252b5132 | 8135 | s = "lh"; |
df58fc94 | 8136 | fmt = "t,o(b)"; |
252b5132 RH |
8137 | goto ld; |
8138 | case M_LHU_AB: | |
df58fc94 | 8139 | ab = 1; |
252b5132 | 8140 | s = "lhu"; |
df58fc94 | 8141 | fmt = "t,o(b)"; |
252b5132 RH |
8142 | goto ld; |
8143 | case M_LW_AB: | |
df58fc94 | 8144 | ab = 1; |
252b5132 | 8145 | s = "lw"; |
df58fc94 | 8146 | fmt = "t,o(b)"; |
252b5132 RH |
8147 | goto ld; |
8148 | case M_LWC0_AB: | |
df58fc94 RS |
8149 | ab = 1; |
8150 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8151 | s = "lwc0"; |
df58fc94 | 8152 | fmt = "E,o(b)"; |
bdaaa2e1 | 8153 | /* Itbl support may require additional care here. */ |
252b5132 | 8154 | coproc = 1; |
df58fc94 | 8155 | goto ld_st; |
252b5132 | 8156 | case M_LWC1_AB: |
df58fc94 | 8157 | ab = 1; |
252b5132 | 8158 | s = "lwc1"; |
df58fc94 | 8159 | fmt = "T,o(b)"; |
bdaaa2e1 | 8160 | /* Itbl support may require additional care here. */ |
252b5132 | 8161 | coproc = 1; |
df58fc94 | 8162 | goto ld_st; |
252b5132 | 8163 | case M_LWC2_AB: |
df58fc94 RS |
8164 | ab = 1; |
8165 | case M_LWC2_OB: | |
252b5132 | 8166 | s = "lwc2"; |
df58fc94 RS |
8167 | fmt = COP12_FMT; |
8168 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8169 | /* Itbl support may require additional care here. */ |
252b5132 | 8170 | coproc = 1; |
df58fc94 | 8171 | goto ld_st; |
252b5132 | 8172 | case M_LWC3_AB: |
df58fc94 RS |
8173 | ab = 1; |
8174 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8175 | s = "lwc3"; |
df58fc94 | 8176 | fmt = "E,o(b)"; |
bdaaa2e1 | 8177 | /* Itbl support may require additional care here. */ |
252b5132 | 8178 | coproc = 1; |
df58fc94 | 8179 | goto ld_st; |
252b5132 | 8180 | case M_LWL_AB: |
df58fc94 RS |
8181 | ab = 1; |
8182 | case M_LWL_OB: | |
252b5132 | 8183 | s = "lwl"; |
df58fc94 RS |
8184 | fmt = MEM12_FMT; |
8185 | off12 = mips_opts.micromips; | |
8186 | goto ld_st; | |
252b5132 | 8187 | case M_LWR_AB: |
df58fc94 RS |
8188 | ab = 1; |
8189 | case M_LWR_OB: | |
252b5132 | 8190 | s = "lwr"; |
df58fc94 RS |
8191 | fmt = MEM12_FMT; |
8192 | off12 = mips_opts.micromips; | |
8193 | goto ld_st; | |
252b5132 | 8194 | case M_LDC1_AB: |
df58fc94 | 8195 | ab = 1; |
252b5132 | 8196 | s = "ldc1"; |
df58fc94 | 8197 | fmt = "T,o(b)"; |
bdaaa2e1 | 8198 | /* Itbl support may require additional care here. */ |
252b5132 | 8199 | coproc = 1; |
df58fc94 | 8200 | goto ld_st; |
252b5132 | 8201 | case M_LDC2_AB: |
df58fc94 RS |
8202 | ab = 1; |
8203 | case M_LDC2_OB: | |
252b5132 | 8204 | s = "ldc2"; |
df58fc94 RS |
8205 | fmt = COP12_FMT; |
8206 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8207 | /* Itbl support may require additional care here. */ |
252b5132 | 8208 | coproc = 1; |
df58fc94 | 8209 | goto ld_st; |
c77c0862 RS |
8210 | case M_LQC2_AB: |
8211 | ab = 1; | |
8212 | s = "lqc2"; | |
8213 | fmt = "E,o(b)"; | |
8214 | /* Itbl support may require additional care here. */ | |
8215 | coproc = 1; | |
8216 | goto ld_st; | |
252b5132 | 8217 | case M_LDC3_AB: |
df58fc94 | 8218 | ab = 1; |
252b5132 | 8219 | s = "ldc3"; |
df58fc94 | 8220 | fmt = "E,o(b)"; |
bdaaa2e1 | 8221 | /* Itbl support may require additional care here. */ |
252b5132 | 8222 | coproc = 1; |
df58fc94 | 8223 | goto ld_st; |
252b5132 | 8224 | case M_LDL_AB: |
df58fc94 RS |
8225 | ab = 1; |
8226 | case M_LDL_OB: | |
252b5132 | 8227 | s = "ldl"; |
df58fc94 RS |
8228 | fmt = MEM12_FMT; |
8229 | off12 = mips_opts.micromips; | |
8230 | goto ld_st; | |
252b5132 | 8231 | case M_LDR_AB: |
df58fc94 RS |
8232 | ab = 1; |
8233 | case M_LDR_OB: | |
252b5132 | 8234 | s = "ldr"; |
df58fc94 RS |
8235 | fmt = MEM12_FMT; |
8236 | off12 = mips_opts.micromips; | |
8237 | goto ld_st; | |
252b5132 | 8238 | case M_LL_AB: |
df58fc94 RS |
8239 | ab = 1; |
8240 | case M_LL_OB: | |
252b5132 | 8241 | s = "ll"; |
df58fc94 RS |
8242 | fmt = MEM12_FMT; |
8243 | off12 = mips_opts.micromips; | |
252b5132 RH |
8244 | goto ld; |
8245 | case M_LLD_AB: | |
df58fc94 RS |
8246 | ab = 1; |
8247 | case M_LLD_OB: | |
252b5132 | 8248 | s = "lld"; |
df58fc94 RS |
8249 | fmt = MEM12_FMT; |
8250 | off12 = mips_opts.micromips; | |
252b5132 RH |
8251 | goto ld; |
8252 | case M_LWU_AB: | |
df58fc94 RS |
8253 | ab = 1; |
8254 | case M_LWU_OB: | |
252b5132 | 8255 | s = "lwu"; |
df58fc94 RS |
8256 | fmt = MEM12_FMT; |
8257 | off12 = mips_opts.micromips; | |
8258 | goto ld; | |
8259 | case M_LWP_AB: | |
8260 | ab = 1; | |
8261 | case M_LWP_OB: | |
8262 | gas_assert (mips_opts.micromips); | |
8263 | s = "lwp"; | |
8264 | fmt = "t,~(b)"; | |
8265 | off12 = 1; | |
8266 | lp = 1; | |
8267 | goto ld; | |
8268 | case M_LDP_AB: | |
8269 | ab = 1; | |
8270 | case M_LDP_OB: | |
8271 | gas_assert (mips_opts.micromips); | |
8272 | s = "ldp"; | |
8273 | fmt = "t,~(b)"; | |
8274 | off12 = 1; | |
8275 | lp = 1; | |
8276 | goto ld; | |
8277 | case M_LWM_AB: | |
8278 | ab = 1; | |
8279 | case M_LWM_OB: | |
8280 | gas_assert (mips_opts.micromips); | |
8281 | s = "lwm"; | |
8282 | fmt = "n,~(b)"; | |
8283 | off12 = 1; | |
8284 | goto ld_st; | |
8285 | case M_LDM_AB: | |
8286 | ab = 1; | |
8287 | case M_LDM_OB: | |
8288 | gas_assert (mips_opts.micromips); | |
8289 | s = "ldm"; | |
8290 | fmt = "n,~(b)"; | |
8291 | off12 = 1; | |
8292 | goto ld_st; | |
8293 | ||
252b5132 | 8294 | ld: |
f19ccbda MR |
8295 | /* We don't want to use $0 as tempreg. */ |
8296 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8297 | goto ld_st; |
252b5132 | 8298 | else |
df58fc94 RS |
8299 | tempreg = treg + lp; |
8300 | goto ld_noat; | |
8301 | ||
252b5132 | 8302 | case M_SB_AB: |
df58fc94 | 8303 | ab = 1; |
252b5132 | 8304 | s = "sb"; |
df58fc94 RS |
8305 | fmt = "t,o(b)"; |
8306 | goto ld_st; | |
252b5132 | 8307 | case M_SH_AB: |
df58fc94 | 8308 | ab = 1; |
252b5132 | 8309 | s = "sh"; |
df58fc94 RS |
8310 | fmt = "t,o(b)"; |
8311 | goto ld_st; | |
252b5132 | 8312 | case M_SW_AB: |
df58fc94 | 8313 | ab = 1; |
252b5132 | 8314 | s = "sw"; |
df58fc94 RS |
8315 | fmt = "t,o(b)"; |
8316 | goto ld_st; | |
252b5132 | 8317 | case M_SWC0_AB: |
df58fc94 RS |
8318 | ab = 1; |
8319 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8320 | s = "swc0"; |
df58fc94 | 8321 | fmt = "E,o(b)"; |
bdaaa2e1 | 8322 | /* Itbl support may require additional care here. */ |
252b5132 | 8323 | coproc = 1; |
df58fc94 | 8324 | goto ld_st; |
252b5132 | 8325 | case M_SWC1_AB: |
df58fc94 | 8326 | ab = 1; |
252b5132 | 8327 | s = "swc1"; |
df58fc94 | 8328 | fmt = "T,o(b)"; |
bdaaa2e1 | 8329 | /* Itbl support may require additional care here. */ |
252b5132 | 8330 | coproc = 1; |
df58fc94 | 8331 | goto ld_st; |
252b5132 | 8332 | case M_SWC2_AB: |
df58fc94 RS |
8333 | ab = 1; |
8334 | case M_SWC2_OB: | |
252b5132 | 8335 | s = "swc2"; |
df58fc94 RS |
8336 | fmt = COP12_FMT; |
8337 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8338 | /* Itbl support may require additional care here. */ |
252b5132 | 8339 | coproc = 1; |
df58fc94 | 8340 | goto ld_st; |
252b5132 | 8341 | case M_SWC3_AB: |
df58fc94 RS |
8342 | ab = 1; |
8343 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8344 | s = "swc3"; |
df58fc94 | 8345 | fmt = "E,o(b)"; |
bdaaa2e1 | 8346 | /* Itbl support may require additional care here. */ |
252b5132 | 8347 | coproc = 1; |
df58fc94 | 8348 | goto ld_st; |
252b5132 | 8349 | case M_SWL_AB: |
df58fc94 RS |
8350 | ab = 1; |
8351 | case M_SWL_OB: | |
252b5132 | 8352 | s = "swl"; |
df58fc94 RS |
8353 | fmt = MEM12_FMT; |
8354 | off12 = mips_opts.micromips; | |
8355 | goto ld_st; | |
252b5132 | 8356 | case M_SWR_AB: |
df58fc94 RS |
8357 | ab = 1; |
8358 | case M_SWR_OB: | |
252b5132 | 8359 | s = "swr"; |
df58fc94 RS |
8360 | fmt = MEM12_FMT; |
8361 | off12 = mips_opts.micromips; | |
8362 | goto ld_st; | |
252b5132 | 8363 | case M_SC_AB: |
df58fc94 RS |
8364 | ab = 1; |
8365 | case M_SC_OB: | |
252b5132 | 8366 | s = "sc"; |
df58fc94 RS |
8367 | fmt = MEM12_FMT; |
8368 | off12 = mips_opts.micromips; | |
8369 | goto ld_st; | |
252b5132 | 8370 | case M_SCD_AB: |
df58fc94 RS |
8371 | ab = 1; |
8372 | case M_SCD_OB: | |
252b5132 | 8373 | s = "scd"; |
df58fc94 RS |
8374 | fmt = MEM12_FMT; |
8375 | off12 = mips_opts.micromips; | |
8376 | goto ld_st; | |
d43b4baf | 8377 | case M_CACHE_AB: |
df58fc94 RS |
8378 | ab = 1; |
8379 | case M_CACHE_OB: | |
d43b4baf | 8380 | s = "cache"; |
df58fc94 RS |
8381 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8382 | off12 = mips_opts.micromips; | |
8383 | goto ld_st; | |
3eebd5eb | 8384 | case M_PREF_AB: |
df58fc94 RS |
8385 | ab = 1; |
8386 | case M_PREF_OB: | |
3eebd5eb | 8387 | s = "pref"; |
df58fc94 RS |
8388 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8389 | off12 = mips_opts.micromips; | |
8390 | goto ld_st; | |
252b5132 | 8391 | case M_SDC1_AB: |
df58fc94 | 8392 | ab = 1; |
252b5132 | 8393 | s = "sdc1"; |
df58fc94 | 8394 | fmt = "T,o(b)"; |
252b5132 | 8395 | coproc = 1; |
bdaaa2e1 | 8396 | /* Itbl support may require additional care here. */ |
df58fc94 | 8397 | goto ld_st; |
252b5132 | 8398 | case M_SDC2_AB: |
df58fc94 RS |
8399 | ab = 1; |
8400 | case M_SDC2_OB: | |
252b5132 | 8401 | s = "sdc2"; |
df58fc94 RS |
8402 | fmt = COP12_FMT; |
8403 | off12 = mips_opts.micromips; | |
c77c0862 RS |
8404 | /* Itbl support may require additional care here. */ |
8405 | coproc = 1; | |
8406 | goto ld_st; | |
8407 | case M_SQC2_AB: | |
8408 | ab = 1; | |
8409 | s = "sqc2"; | |
8410 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8411 | /* Itbl support may require additional care here. */ |
252b5132 | 8412 | coproc = 1; |
df58fc94 | 8413 | goto ld_st; |
252b5132 | 8414 | case M_SDC3_AB: |
df58fc94 RS |
8415 | ab = 1; |
8416 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8417 | s = "sdc3"; |
df58fc94 | 8418 | fmt = "E,o(b)"; |
bdaaa2e1 | 8419 | /* Itbl support may require additional care here. */ |
252b5132 | 8420 | coproc = 1; |
df58fc94 | 8421 | goto ld_st; |
252b5132 | 8422 | case M_SDL_AB: |
df58fc94 RS |
8423 | ab = 1; |
8424 | case M_SDL_OB: | |
252b5132 | 8425 | s = "sdl"; |
df58fc94 RS |
8426 | fmt = MEM12_FMT; |
8427 | off12 = mips_opts.micromips; | |
8428 | goto ld_st; | |
252b5132 | 8429 | case M_SDR_AB: |
df58fc94 RS |
8430 | ab = 1; |
8431 | case M_SDR_OB: | |
252b5132 | 8432 | s = "sdr"; |
df58fc94 RS |
8433 | fmt = MEM12_FMT; |
8434 | off12 = mips_opts.micromips; | |
8435 | goto ld_st; | |
8436 | case M_SWP_AB: | |
8437 | ab = 1; | |
8438 | case M_SWP_OB: | |
8439 | gas_assert (mips_opts.micromips); | |
8440 | s = "swp"; | |
8441 | fmt = "t,~(b)"; | |
8442 | off12 = 1; | |
8443 | goto ld_st; | |
8444 | case M_SDP_AB: | |
8445 | ab = 1; | |
8446 | case M_SDP_OB: | |
8447 | gas_assert (mips_opts.micromips); | |
8448 | s = "sdp"; | |
8449 | fmt = "t,~(b)"; | |
8450 | off12 = 1; | |
8451 | goto ld_st; | |
8452 | case M_SWM_AB: | |
8453 | ab = 1; | |
8454 | case M_SWM_OB: | |
8455 | gas_assert (mips_opts.micromips); | |
8456 | s = "swm"; | |
8457 | fmt = "n,~(b)"; | |
8458 | off12 = 1; | |
8459 | goto ld_st; | |
8460 | case M_SDM_AB: | |
8461 | ab = 1; | |
8462 | case M_SDM_OB: | |
8463 | gas_assert (mips_opts.micromips); | |
8464 | s = "sdm"; | |
8465 | fmt = "n,~(b)"; | |
8466 | off12 = 1; | |
8467 | ||
8468 | ld_st: | |
8fc2e39e TS |
8469 | tempreg = AT; |
8470 | used_at = 1; | |
df58fc94 | 8471 | ld_noat: |
252b5132 RH |
8472 | if (offset_expr.X_op != O_constant |
8473 | && offset_expr.X_op != O_symbol) | |
8474 | { | |
f71d0d44 | 8475 | as_bad (_("Expression too complex")); |
252b5132 RH |
8476 | offset_expr.X_op = O_constant; |
8477 | } | |
8478 | ||
2051e8c4 MR |
8479 | if (HAVE_32BIT_ADDRESSES |
8480 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8481 | { |
8482 | char value [32]; | |
8483 | ||
8484 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8485 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8486 | } |
2051e8c4 | 8487 | |
252b5132 RH |
8488 | /* A constant expression in PIC code can be handled just as it |
8489 | is in non PIC code. */ | |
aed1a261 RS |
8490 | if (offset_expr.X_op == O_constant) |
8491 | { | |
df58fc94 RS |
8492 | int hipart = 0; |
8493 | ||
842f8b2a | 8494 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8495 | normalize_address_expr (&expr1); |
df58fc94 | 8496 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8497 | { |
8498 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8499 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8500 | hipart = 1; |
8501 | } | |
8502 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8503 | { | |
8504 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8505 | & ~(bfd_vma) 0xfff); | |
8506 | hipart = 1; | |
8507 | } | |
8508 | if (hipart) | |
8509 | { | |
842f8b2a MR |
8510 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8511 | if (breg != 0) | |
8512 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8513 | tempreg, tempreg, breg); | |
8514 | breg = tempreg; | |
8515 | } | |
dd6a37e7 AP |
8516 | if (off0) |
8517 | { | |
8518 | if (offset_expr.X_add_number == 0) | |
8519 | tempreg = breg; | |
8520 | else | |
8521 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8522 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8523 | macro_build (NULL, s, fmt, treg, tempreg); | |
8524 | } | |
8525 | else if (!off12) | |
df58fc94 RS |
8526 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8527 | else | |
8528 | macro_build (NULL, s, fmt, | |
8529 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8530 | } | |
dd6a37e7 | 8531 | else if (off12 || off0) |
df58fc94 | 8532 | { |
dd6a37e7 AP |
8533 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8534 | for a low-part relocation, so load the whole address into | |
8535 | the auxillary register. In the case of "A(b)" addresses, | |
8536 | we first load absolute address "A" into the register and | |
8537 | then add base register "b". In the case of "o(b)" addresses, | |
8538 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8539 | offset_reloc already contains the relocations associated |
8540 | with "o". */ | |
8541 | if (ab) | |
8542 | { | |
8543 | load_address (tempreg, &offset_expr, &used_at); | |
8544 | if (breg != 0) | |
8545 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8546 | tempreg, tempreg, breg); | |
8547 | } | |
8548 | else | |
8549 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8550 | tempreg, breg, -1, | |
8551 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8552 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8553 | if (off0) |
8554 | macro_build (NULL, s, fmt, treg, tempreg); | |
8555 | else | |
8556 | macro_build (NULL, s, fmt, | |
8557 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8558 | } |
8559 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8560 | { |
8561 | /* If this is a reference to a GP relative symbol, and there | |
8562 | is no base register, we want | |
cdf6fd85 | 8563 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8564 | Otherwise, if there is no base register, we want |
8565 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8566 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8567 | If we have a constant, we need two instructions anyhow, | |
8568 | so we always use the latter form. | |
8569 | ||
8570 | If we have a base register, and this is a reference to a | |
8571 | GP relative symbol, we want | |
8572 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8573 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8574 | Otherwise we want |
8575 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8576 | addu $tempreg,$tempreg,$breg | |
8577 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8578 | With a constant we always use the latter case. |
76b3015f | 8579 | |
d6bc6245 TS |
8580 | With 64bit address space and no base register and $at usable, |
8581 | we want | |
8582 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8583 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8584 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8585 | dsll32 $tempreg,0 | |
8586 | daddu $tempreg,$at | |
8587 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8588 | If we have a base register, we want | |
8589 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8590 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8591 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8592 | daddu $at,$breg | |
8593 | dsll32 $tempreg,0 | |
8594 | daddu $tempreg,$at | |
8595 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8596 | ||
8597 | Without $at we can't generate the optimal path for superscalar | |
8598 | processors here since this would require two temporary registers. | |
8599 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8600 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8601 | dsll $tempreg,16 | |
8602 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8603 | dsll $tempreg,16 | |
8604 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8605 | If we have a base register, we want | |
8606 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8607 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8608 | dsll $tempreg,16 | |
8609 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8610 | dsll $tempreg,16 | |
8611 | daddu $tempreg,$tempreg,$breg | |
8612 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8613 | |
6caf9ef4 | 8614 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8615 | the same sequence as in 32bit address space. */ |
8616 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8617 | { |
aed1a261 | 8618 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8619 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8620 | { | |
8621 | relax_start (offset_expr.X_add_symbol); | |
8622 | if (breg == 0) | |
8623 | { | |
8624 | macro_build (&offset_expr, s, fmt, treg, | |
8625 | BFD_RELOC_GPREL16, mips_gp_register); | |
8626 | } | |
8627 | else | |
8628 | { | |
8629 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8630 | tempreg, breg, mips_gp_register); | |
8631 | macro_build (&offset_expr, s, fmt, treg, | |
8632 | BFD_RELOC_GPREL16, tempreg); | |
8633 | } | |
8634 | relax_switch (); | |
8635 | } | |
d6bc6245 | 8636 | |
741fe287 | 8637 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8638 | { |
df58fc94 | 8639 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8640 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8641 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8642 | BFD_RELOC_HI16_S); |
8643 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8644 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8645 | if (breg != 0) |
67c0d1eb | 8646 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8647 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8648 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8649 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8650 | tempreg); | |
d6bc6245 TS |
8651 | used_at = 1; |
8652 | } | |
8653 | else | |
8654 | { | |
df58fc94 | 8655 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8656 | BFD_RELOC_MIPS_HIGHEST); |
8657 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8658 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8659 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8660 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8661 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8662 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8663 | if (breg != 0) |
67c0d1eb | 8664 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8665 | tempreg, tempreg, breg); |
67c0d1eb | 8666 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8667 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8668 | } |
6caf9ef4 TS |
8669 | |
8670 | if (mips_relax.sequence) | |
8671 | relax_end (); | |
8fc2e39e | 8672 | break; |
d6bc6245 | 8673 | } |
256ab948 | 8674 | |
252b5132 RH |
8675 | if (breg == 0) |
8676 | { | |
67c0d1eb | 8677 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8678 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8679 | { |
4d7206a2 | 8680 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8681 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8682 | mips_gp_register); | |
4d7206a2 | 8683 | relax_switch (); |
252b5132 | 8684 | } |
67c0d1eb RS |
8685 | macro_build_lui (&offset_expr, tempreg); |
8686 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8687 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8688 | if (mips_relax.sequence) |
8689 | relax_end (); | |
252b5132 RH |
8690 | } |
8691 | else | |
8692 | { | |
67c0d1eb | 8693 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8694 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8695 | { |
4d7206a2 | 8696 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8698 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8699 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8700 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8701 | relax_switch (); |
252b5132 | 8702 | } |
67c0d1eb RS |
8703 | macro_build_lui (&offset_expr, tempreg); |
8704 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8705 | tempreg, tempreg, breg); |
67c0d1eb | 8706 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8707 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8708 | if (mips_relax.sequence) |
8709 | relax_end (); | |
252b5132 RH |
8710 | } |
8711 | } | |
0a44bf69 | 8712 | else if (!mips_big_got) |
252b5132 | 8713 | { |
ed6fb7bd | 8714 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8715 | |
252b5132 RH |
8716 | /* If this is a reference to an external symbol, we want |
8717 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8718 | nop | |
8719 | <op> $treg,0($tempreg) | |
8720 | Otherwise we want | |
8721 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8722 | nop | |
8723 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8724 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8725 | |
8726 | For NewABI, we want | |
8727 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8728 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8729 | ||
252b5132 RH |
8730 | If there is a base register, we add it to $tempreg before |
8731 | the <op>. If there is a constant, we stick it in the | |
8732 | <op> instruction. We don't handle constants larger than | |
8733 | 16 bits, because we have no way to load the upper 16 bits | |
8734 | (actually, we could handle them for the subset of cases | |
8735 | in which we are not using $at). */ | |
9c2799c2 | 8736 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8737 | if (HAVE_NEWABI) |
8738 | { | |
67c0d1eb RS |
8739 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8740 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8741 | if (breg != 0) |
67c0d1eb | 8742 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8743 | tempreg, tempreg, breg); |
67c0d1eb | 8744 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8745 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8746 | break; |
8747 | } | |
252b5132 RH |
8748 | expr1.X_add_number = offset_expr.X_add_number; |
8749 | offset_expr.X_add_number = 0; | |
8750 | if (expr1.X_add_number < -0x8000 | |
8751 | || expr1.X_add_number >= 0x8000) | |
8752 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8753 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8754 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8755 | load_delay_nop (); |
4d7206a2 RS |
8756 | relax_start (offset_expr.X_add_symbol); |
8757 | relax_switch (); | |
67c0d1eb RS |
8758 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8759 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8760 | relax_end (); |
252b5132 | 8761 | if (breg != 0) |
67c0d1eb | 8762 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8763 | tempreg, tempreg, breg); |
67c0d1eb | 8764 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8765 | } |
0a44bf69 | 8766 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8767 | { |
67c0d1eb | 8768 | int gpdelay; |
252b5132 RH |
8769 | |
8770 | /* If this is a reference to an external symbol, we want | |
8771 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8772 | addu $tempreg,$tempreg,$gp | |
8773 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8774 | <op> $treg,0($tempreg) | |
8775 | Otherwise we want | |
8776 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8777 | nop | |
8778 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8779 | <op> $treg,0($tempreg) | |
8780 | If there is a base register, we add it to $tempreg before | |
8781 | the <op>. If there is a constant, we stick it in the | |
8782 | <op> instruction. We don't handle constants larger than | |
8783 | 16 bits, because we have no way to load the upper 16 bits | |
8784 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8785 | in which we are not using $at). */ |
9c2799c2 | 8786 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8787 | expr1.X_add_number = offset_expr.X_add_number; |
8788 | offset_expr.X_add_number = 0; | |
8789 | if (expr1.X_add_number < -0x8000 | |
8790 | || expr1.X_add_number >= 0x8000) | |
8791 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8792 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8793 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8794 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8795 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8796 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8797 | mips_gp_register); | |
8798 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8799 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8800 | relax_switch (); |
67c0d1eb RS |
8801 | if (gpdelay) |
8802 | macro_build (NULL, "nop", ""); | |
8803 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8804 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8805 | load_delay_nop (); |
67c0d1eb RS |
8806 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8807 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8808 | relax_end (); |
8809 | ||
252b5132 | 8810 | if (breg != 0) |
67c0d1eb | 8811 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8812 | tempreg, tempreg, breg); |
67c0d1eb | 8813 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8814 | } |
0a44bf69 | 8815 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8816 | { |
f5040a92 AO |
8817 | /* If this is a reference to an external symbol, we want |
8818 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8819 | add $tempreg,$tempreg,$gp | |
8820 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8821 | <op> $treg,<ofst>($tempreg) | |
8822 | Otherwise, for local symbols, we want: | |
8823 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8824 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8825 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8826 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8827 | offset_expr.X_add_number = 0; |
8828 | if (expr1.X_add_number < -0x8000 | |
8829 | || expr1.X_add_number >= 0x8000) | |
8830 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8831 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8832 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8833 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8834 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8835 | mips_gp_register); | |
8836 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8837 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8838 | if (breg != 0) |
67c0d1eb | 8839 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8840 | tempreg, tempreg, breg); |
67c0d1eb | 8841 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8842 | |
4d7206a2 | 8843 | relax_switch (); |
f5040a92 | 8844 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8845 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8846 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8847 | if (breg != 0) |
67c0d1eb | 8848 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8849 | tempreg, tempreg, breg); |
67c0d1eb | 8850 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8851 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8852 | relax_end (); |
f5040a92 | 8853 | } |
252b5132 RH |
8854 | else |
8855 | abort (); | |
8856 | ||
252b5132 RH |
8857 | break; |
8858 | ||
8859 | case M_LI: | |
8860 | case M_LI_S: | |
67c0d1eb | 8861 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8862 | break; |
252b5132 RH |
8863 | |
8864 | case M_DLI: | |
67c0d1eb | 8865 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8866 | break; |
252b5132 RH |
8867 | |
8868 | case M_LI_SS: | |
8869 | if (imm_expr.X_op == O_constant) | |
8870 | { | |
8fc2e39e | 8871 | used_at = 1; |
67c0d1eb RS |
8872 | load_register (AT, &imm_expr, 0); |
8873 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8874 | break; |
8875 | } | |
8876 | else | |
8877 | { | |
9c2799c2 | 8878 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8879 | && strcmp (segment_name (S_GET_SEGMENT |
8880 | (offset_expr.X_add_symbol)), | |
8881 | ".lit4") == 0 | |
8882 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8883 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8884 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8885 | break; |
252b5132 RH |
8886 | } |
8887 | ||
8888 | case M_LI_D: | |
ca4e0257 RS |
8889 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8890 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8891 | order 32 bits of the value and the low order 32 bits are either | |
8892 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8893 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8894 | { | |
ca4e0257 | 8895 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8896 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8897 | else |
8898 | { | |
8899 | int hreg, lreg; | |
8900 | ||
8901 | if (target_big_endian) | |
8902 | { | |
8903 | hreg = treg; | |
8904 | lreg = treg + 1; | |
8905 | } | |
8906 | else | |
8907 | { | |
8908 | hreg = treg + 1; | |
8909 | lreg = treg; | |
8910 | } | |
8911 | ||
8912 | if (hreg <= 31) | |
67c0d1eb | 8913 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8914 | if (lreg <= 31) |
8915 | { | |
8916 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8917 | move_register (lreg, 0); |
252b5132 RH |
8918 | else |
8919 | { | |
9c2799c2 | 8920 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8921 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8922 | } |
8923 | } | |
8924 | } | |
8fc2e39e | 8925 | break; |
252b5132 RH |
8926 | } |
8927 | ||
8928 | /* We know that sym is in the .rdata section. First we get the | |
8929 | upper 16 bits of the address. */ | |
8930 | if (mips_pic == NO_PIC) | |
8931 | { | |
67c0d1eb | 8932 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8933 | used_at = 1; |
252b5132 | 8934 | } |
0a44bf69 | 8935 | else |
252b5132 | 8936 | { |
67c0d1eb RS |
8937 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8938 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8939 | used_at = 1; |
252b5132 | 8940 | } |
bdaaa2e1 | 8941 | |
252b5132 | 8942 | /* Now we load the register(s). */ |
ca4e0257 | 8943 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8944 | { |
8945 | used_at = 1; | |
8946 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8947 | } | |
252b5132 RH |
8948 | else |
8949 | { | |
8fc2e39e | 8950 | used_at = 1; |
67c0d1eb | 8951 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8952 | if (treg != RA) |
252b5132 RH |
8953 | { |
8954 | /* FIXME: How in the world do we deal with the possible | |
8955 | overflow here? */ | |
8956 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8957 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8958 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8959 | } |
8960 | } | |
252b5132 RH |
8961 | break; |
8962 | ||
8963 | case M_LI_DD: | |
ca4e0257 RS |
8964 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8965 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8966 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8967 | the value and the low order 32 bits are either zero or in | |
8968 | OFFSET_EXPR. */ | |
252b5132 RH |
8969 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8970 | { | |
8fc2e39e | 8971 | used_at = 1; |
67c0d1eb | 8972 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8973 | if (HAVE_64BIT_FPRS) |
8974 | { | |
9c2799c2 | 8975 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8976 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8977 | } |
252b5132 RH |
8978 | else |
8979 | { | |
67c0d1eb | 8980 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8981 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8982 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8983 | else |
8984 | { | |
9c2799c2 | 8985 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8986 | load_register (AT, &offset_expr, 0); |
8987 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8988 | } |
8989 | } | |
8990 | break; | |
8991 | } | |
8992 | ||
9c2799c2 | 8993 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8994 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8995 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8996 | if (strcmp (s, ".lit8") == 0) | |
8997 | { | |
0aa27725 | 8998 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 8999 | { |
67c0d1eb | 9000 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 9001 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9002 | break; |
252b5132 | 9003 | } |
c9914766 | 9004 | breg = mips_gp_register; |
252b5132 RH |
9005 | r = BFD_RELOC_MIPS_LITERAL; |
9006 | goto dob; | |
9007 | } | |
9008 | else | |
9009 | { | |
9c2799c2 | 9010 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9011 | used_at = 1; |
0a44bf69 | 9012 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9013 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9014 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9015 | else |
9016 | { | |
9017 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9018 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9019 | } |
bdaaa2e1 | 9020 | |
0aa27725 | 9021 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9022 | { |
67c0d1eb RS |
9023 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9024 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9025 | break; |
9026 | } | |
9027 | breg = AT; | |
9028 | r = BFD_RELOC_LO16; | |
9029 | goto dob; | |
9030 | } | |
9031 | ||
9032 | case M_L_DOB: | |
252b5132 RH |
9033 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9034 | to adjust when loading from memory. */ | |
9035 | r = BFD_RELOC_LO16; | |
9036 | dob: | |
df58fc94 | 9037 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9038 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9039 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9040 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9041 | /* FIXME: A possible overflow which I don't know how to deal |
9042 | with. */ | |
9043 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9044 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9045 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9046 | break; |
9047 | ||
c4a68bea | 9048 | case M_S_DOB: |
df58fc94 | 9049 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9050 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9051 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9052 | to adjust when storing to memory. */ | |
9053 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9054 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9055 | offset_expr.X_add_number += 4; | |
9056 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9057 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9058 | break; | |
9059 | ||
252b5132 | 9060 | case M_L_DAB: |
df58fc94 | 9061 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9062 | /* |
9063 | * The MIPS assembler seems to check for X_add_number not | |
9064 | * being double aligned and generating: | |
9065 | * lui at,%hi(foo+1) | |
9066 | * addu at,at,v1 | |
9067 | * addiu at,at,%lo(foo+1) | |
9068 | * lwc1 f2,0(at) | |
9069 | * lwc1 f3,4(at) | |
9070 | * But, the resulting address is the same after relocation so why | |
9071 | * generate the extra instruction? | |
9072 | */ | |
bdaaa2e1 | 9073 | /* Itbl support may require additional care here. */ |
252b5132 | 9074 | coproc = 1; |
df58fc94 | 9075 | fmt = "T,o(b)"; |
0aa27725 | 9076 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9077 | { |
9078 | s = "ldc1"; | |
df58fc94 | 9079 | goto ld_st; |
252b5132 | 9080 | } |
252b5132 | 9081 | s = "lwc1"; |
252b5132 RH |
9082 | goto ldd_std; |
9083 | ||
9084 | case M_S_DAB: | |
df58fc94 RS |
9085 | gas_assert (!mips_opts.micromips); |
9086 | /* Itbl support may require additional care here. */ | |
9087 | coproc = 1; | |
9088 | fmt = "T,o(b)"; | |
0aa27725 | 9089 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9090 | { |
9091 | s = "sdc1"; | |
df58fc94 | 9092 | goto ld_st; |
252b5132 | 9093 | } |
252b5132 | 9094 | s = "swc1"; |
252b5132 RH |
9095 | goto ldd_std; |
9096 | ||
e407c74b NC |
9097 | case M_LQ_AB: |
9098 | fmt = "t,o(b)"; | |
9099 | s = "lq"; | |
9100 | goto ld; | |
9101 | ||
9102 | case M_SQ_AB: | |
9103 | fmt = "t,o(b)"; | |
9104 | s = "sq"; | |
9105 | goto ld_st; | |
9106 | ||
252b5132 | 9107 | case M_LD_AB: |
df58fc94 | 9108 | fmt = "t,o(b)"; |
ca4e0257 | 9109 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9110 | { |
9111 | s = "ld"; | |
9112 | goto ld; | |
9113 | } | |
252b5132 | 9114 | s = "lw"; |
252b5132 RH |
9115 | goto ldd_std; |
9116 | ||
9117 | case M_SD_AB: | |
df58fc94 | 9118 | fmt = "t,o(b)"; |
ca4e0257 | 9119 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9120 | { |
9121 | s = "sd"; | |
df58fc94 | 9122 | goto ld_st; |
252b5132 | 9123 | } |
252b5132 | 9124 | s = "sw"; |
252b5132 RH |
9125 | |
9126 | ldd_std: | |
9127 | if (offset_expr.X_op != O_symbol | |
9128 | && offset_expr.X_op != O_constant) | |
9129 | { | |
f71d0d44 | 9130 | as_bad (_("Expression too complex")); |
252b5132 RH |
9131 | offset_expr.X_op = O_constant; |
9132 | } | |
9133 | ||
2051e8c4 MR |
9134 | if (HAVE_32BIT_ADDRESSES |
9135 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9136 | { |
9137 | char value [32]; | |
9138 | ||
9139 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9140 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9141 | } |
2051e8c4 | 9142 | |
252b5132 RH |
9143 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9144 | to adjust when loading from memory. We set coproc if we must | |
9145 | load $fn+1 first. */ | |
bdaaa2e1 | 9146 | /* Itbl support may require additional care here. */ |
90ecf173 | 9147 | if (!target_big_endian) |
252b5132 RH |
9148 | coproc = 0; |
9149 | ||
90ecf173 | 9150 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9151 | { |
9152 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9153 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9154 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9155 | If we have a base register, we use this |
9156 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9157 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9158 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9159 | If this is not a GP relative symbol, we want |
9160 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9161 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9162 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9163 | If there is a base register, we add it to $at after the | |
9164 | lui instruction. If there is a constant, we always use | |
9165 | the last case. */ | |
39a59cf8 MR |
9166 | if (offset_expr.X_op == O_symbol |
9167 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9168 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9169 | { |
4d7206a2 | 9170 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9171 | if (breg == 0) |
9172 | { | |
c9914766 | 9173 | tempreg = mips_gp_register; |
252b5132 RH |
9174 | } |
9175 | else | |
9176 | { | |
67c0d1eb | 9177 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9178 | AT, breg, mips_gp_register); |
252b5132 | 9179 | tempreg = AT; |
252b5132 RH |
9180 | used_at = 1; |
9181 | } | |
9182 | ||
beae10d5 | 9183 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9184 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9185 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9186 | offset_expr.X_add_number += 4; |
9187 | ||
9188 | /* Set mips_optimize to 2 to avoid inserting an | |
9189 | undesired nop. */ | |
9190 | hold_mips_optimize = mips_optimize; | |
9191 | mips_optimize = 2; | |
beae10d5 | 9192 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9193 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9194 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9195 | mips_optimize = hold_mips_optimize; |
9196 | ||
4d7206a2 | 9197 | relax_switch (); |
252b5132 | 9198 | |
0970e49e | 9199 | offset_expr.X_add_number -= 4; |
252b5132 | 9200 | } |
8fc2e39e | 9201 | used_at = 1; |
67c0d1eb | 9202 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9203 | if (breg != 0) |
67c0d1eb | 9204 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9205 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9206 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9207 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9208 | /* FIXME: How do we handle overflow here? */ |
9209 | offset_expr.X_add_number += 4; | |
beae10d5 | 9210 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9211 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9212 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9213 | if (mips_relax.sequence) |
9214 | relax_end (); | |
bdaaa2e1 | 9215 | } |
0a44bf69 | 9216 | else if (!mips_big_got) |
252b5132 | 9217 | { |
252b5132 RH |
9218 | /* If this is a reference to an external symbol, we want |
9219 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9220 | nop | |
9221 | <op> $treg,0($at) | |
9222 | <op> $treg+1,4($at) | |
9223 | Otherwise we want | |
9224 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9225 | nop | |
9226 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9227 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9228 | If there is a base register we add it to $at before the | |
9229 | lwc1 instructions. If there is a constant we include it | |
9230 | in the lwc1 instructions. */ | |
9231 | used_at = 1; | |
9232 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9233 | if (expr1.X_add_number < -0x8000 |
9234 | || expr1.X_add_number >= 0x8000 - 4) | |
9235 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9236 | load_got_offset (AT, &offset_expr); |
269137b2 | 9237 | load_delay_nop (); |
252b5132 | 9238 | if (breg != 0) |
67c0d1eb | 9239 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9240 | |
9241 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9242 | nop. */ | |
9243 | hold_mips_optimize = mips_optimize; | |
9244 | mips_optimize = 2; | |
4d7206a2 | 9245 | |
beae10d5 | 9246 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9247 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9248 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9249 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9250 | expr1.X_add_number += 4; |
67c0d1eb RS |
9251 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9252 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9253 | relax_switch (); |
67c0d1eb RS |
9254 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9255 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9256 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9257 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9258 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9259 | relax_end (); |
252b5132 | 9260 | |
4d7206a2 | 9261 | mips_optimize = hold_mips_optimize; |
252b5132 | 9262 | } |
0a44bf69 | 9263 | else if (mips_big_got) |
252b5132 | 9264 | { |
67c0d1eb | 9265 | int gpdelay; |
252b5132 RH |
9266 | |
9267 | /* If this is a reference to an external symbol, we want | |
9268 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9269 | addu $at,$at,$gp | |
9270 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9271 | nop | |
9272 | <op> $treg,0($at) | |
9273 | <op> $treg+1,4($at) | |
9274 | Otherwise we want | |
9275 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9276 | nop | |
9277 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9278 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9279 | If there is a base register we add it to $at before the | |
9280 | lwc1 instructions. If there is a constant we include it | |
9281 | in the lwc1 instructions. */ | |
9282 | used_at = 1; | |
9283 | expr1.X_add_number = offset_expr.X_add_number; | |
9284 | offset_expr.X_add_number = 0; | |
9285 | if (expr1.X_add_number < -0x8000 | |
9286 | || expr1.X_add_number >= 0x8000 - 4) | |
9287 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9288 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9289 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9290 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9291 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9292 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9293 | AT, AT, mips_gp_register); |
67c0d1eb | 9294 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9295 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9296 | load_delay_nop (); |
252b5132 | 9297 | if (breg != 0) |
67c0d1eb | 9298 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9299 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9300 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9301 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9302 | expr1.X_add_number += 4; |
9303 | ||
9304 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9305 | nop. */ | |
9306 | hold_mips_optimize = mips_optimize; | |
9307 | mips_optimize = 2; | |
beae10d5 | 9308 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9309 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9310 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9311 | mips_optimize = hold_mips_optimize; |
9312 | expr1.X_add_number -= 4; | |
9313 | ||
4d7206a2 RS |
9314 | relax_switch (); |
9315 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9316 | if (gpdelay) |
9317 | macro_build (NULL, "nop", ""); | |
9318 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9319 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9320 | load_delay_nop (); |
252b5132 | 9321 | if (breg != 0) |
67c0d1eb | 9322 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9323 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9324 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9325 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9326 | offset_expr.X_add_number += 4; |
252b5132 RH |
9327 | |
9328 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9329 | nop. */ | |
9330 | hold_mips_optimize = mips_optimize; | |
9331 | mips_optimize = 2; | |
beae10d5 | 9332 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9333 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9334 | BFD_RELOC_LO16, AT); | |
252b5132 | 9335 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9336 | relax_end (); |
252b5132 | 9337 | } |
252b5132 RH |
9338 | else |
9339 | abort (); | |
9340 | ||
252b5132 RH |
9341 | break; |
9342 | ||
9343 | case M_LD_OB: | |
704897fb | 9344 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9345 | goto sd_ob; |
9346 | case M_SD_OB: | |
704897fb | 9347 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9348 | sd_ob: |
4614d845 MR |
9349 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9350 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9351 | breg); | |
704897fb MR |
9352 | if (!HAVE_64BIT_GPRS) |
9353 | { | |
9354 | offset_expr.X_add_number += 4; | |
9355 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9356 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9357 | breg); | |
704897fb | 9358 | } |
8fc2e39e | 9359 | break; |
252b5132 | 9360 | |
dd6a37e7 AP |
9361 | |
9362 | case M_SAA_AB: | |
9363 | ab = 1; | |
9364 | case M_SAA_OB: | |
9365 | s = "saa"; | |
9366 | off0 = 1; | |
9367 | fmt = "t,(b)"; | |
9368 | goto ld_st; | |
9369 | case M_SAAD_AB: | |
9370 | ab = 1; | |
9371 | case M_SAAD_OB: | |
9372 | s = "saad"; | |
9373 | off0 = 1; | |
9374 | fmt = "t,(b)"; | |
9375 | goto ld_st; | |
9376 | ||
252b5132 RH |
9377 | /* New code added to support COPZ instructions. |
9378 | This code builds table entries out of the macros in mip_opcodes. | |
9379 | R4000 uses interlocks to handle coproc delays. | |
9380 | Other chips (like the R3000) require nops to be inserted for delays. | |
9381 | ||
f72c8c98 | 9382 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9383 | In order to fill delay slots for non-interlocked chips, |
9384 | we must have a way to specify delays based on the coprocessor. | |
9385 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9386 | What are the side-effects of the cop instruction? | |
9387 | What cache support might we have and what are its effects? | |
9388 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9389 | What registers are read/set/modified? |
252b5132 RH |
9390 | |
9391 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9392 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9393 | |
9394 | case M_COP0: | |
9395 | s = "c0"; | |
9396 | goto copz; | |
9397 | case M_COP1: | |
9398 | s = "c1"; | |
9399 | goto copz; | |
9400 | case M_COP2: | |
9401 | s = "c2"; | |
9402 | goto copz; | |
9403 | case M_COP3: | |
9404 | s = "c3"; | |
9405 | copz: | |
df58fc94 | 9406 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9407 | /* For now we just do C (same as Cz). The parameter will be |
9408 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9409 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9410 | break; |
252b5132 | 9411 | |
ea1fb5dc | 9412 | case M_MOVE: |
67c0d1eb | 9413 | move_register (dreg, sreg); |
8fc2e39e | 9414 | break; |
ea1fb5dc | 9415 | |
252b5132 RH |
9416 | case M_DMUL: |
9417 | dbl = 1; | |
9418 | case M_MUL: | |
e407c74b NC |
9419 | if (mips_opts.arch == CPU_R5900) |
9420 | { | |
9421 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9422 | } | |
9423 | else | |
9424 | { | |
67c0d1eb | 9425 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9426 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9427 | } |
8fc2e39e | 9428 | break; |
252b5132 RH |
9429 | |
9430 | case M_DMUL_I: | |
9431 | dbl = 1; | |
9432 | case M_MUL_I: | |
9433 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9434 | not trying to be that fancy. GCC should do this for us | |
9435 | anyway. */ | |
8fc2e39e | 9436 | used_at = 1; |
67c0d1eb RS |
9437 | load_register (AT, &imm_expr, dbl); |
9438 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9439 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9440 | break; |
9441 | ||
9442 | case M_DMULO_I: | |
9443 | dbl = 1; | |
9444 | case M_MULO_I: | |
9445 | imm = 1; | |
9446 | goto do_mulo; | |
9447 | ||
9448 | case M_DMULO: | |
9449 | dbl = 1; | |
9450 | case M_MULO: | |
9451 | do_mulo: | |
7d10b47d | 9452 | start_noreorder (); |
8fc2e39e | 9453 | used_at = 1; |
252b5132 | 9454 | if (imm) |
67c0d1eb RS |
9455 | load_register (AT, &imm_expr, dbl); |
9456 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9457 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9458 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9459 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9460 | if (mips_trap) |
df58fc94 | 9461 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9462 | else |
9463 | { | |
df58fc94 RS |
9464 | if (mips_opts.micromips) |
9465 | micromips_label_expr (&label_expr); | |
9466 | else | |
9467 | label_expr.X_add_number = 8; | |
9468 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9469 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9470 | macro_build (NULL, "break", BRK_FMT, 6); |
9471 | if (mips_opts.micromips) | |
9472 | micromips_add_label (); | |
252b5132 | 9473 | } |
7d10b47d | 9474 | end_noreorder (); |
df58fc94 | 9475 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9476 | break; |
9477 | ||
9478 | case M_DMULOU_I: | |
9479 | dbl = 1; | |
9480 | case M_MULOU_I: | |
9481 | imm = 1; | |
9482 | goto do_mulou; | |
9483 | ||
9484 | case M_DMULOU: | |
9485 | dbl = 1; | |
9486 | case M_MULOU: | |
9487 | do_mulou: | |
7d10b47d | 9488 | start_noreorder (); |
8fc2e39e | 9489 | used_at = 1; |
252b5132 | 9490 | if (imm) |
67c0d1eb RS |
9491 | load_register (AT, &imm_expr, dbl); |
9492 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9493 | sreg, imm ? AT : treg); |
df58fc94 RS |
9494 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9495 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9496 | if (mips_trap) |
df58fc94 | 9497 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9498 | else |
9499 | { | |
df58fc94 RS |
9500 | if (mips_opts.micromips) |
9501 | micromips_label_expr (&label_expr); | |
9502 | else | |
9503 | label_expr.X_add_number = 8; | |
9504 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9505 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9506 | macro_build (NULL, "break", BRK_FMT, 6); |
9507 | if (mips_opts.micromips) | |
9508 | micromips_add_label (); | |
252b5132 | 9509 | } |
7d10b47d | 9510 | end_noreorder (); |
252b5132 RH |
9511 | break; |
9512 | ||
771c7ce4 | 9513 | case M_DROL: |
fef14a42 | 9514 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9515 | { |
9516 | if (dreg == sreg) | |
9517 | { | |
9518 | tempreg = AT; | |
9519 | used_at = 1; | |
9520 | } | |
9521 | else | |
9522 | { | |
9523 | tempreg = dreg; | |
82dd0097 | 9524 | } |
67c0d1eb RS |
9525 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9526 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9527 | break; |
82dd0097 | 9528 | } |
8fc2e39e | 9529 | used_at = 1; |
c80c840e | 9530 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9531 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9532 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9533 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9534 | break; |
9535 | ||
252b5132 | 9536 | case M_ROL: |
fef14a42 | 9537 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9538 | { |
9539 | if (dreg == sreg) | |
9540 | { | |
9541 | tempreg = AT; | |
9542 | used_at = 1; | |
9543 | } | |
9544 | else | |
9545 | { | |
9546 | tempreg = dreg; | |
82dd0097 | 9547 | } |
67c0d1eb RS |
9548 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9549 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9550 | break; |
82dd0097 | 9551 | } |
8fc2e39e | 9552 | used_at = 1; |
c80c840e | 9553 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9554 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9555 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9556 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9557 | break; |
9558 | ||
771c7ce4 TS |
9559 | case M_DROL_I: |
9560 | { | |
9561 | unsigned int rot; | |
91d6fa6a NC |
9562 | char *l; |
9563 | char *rr; | |
771c7ce4 TS |
9564 | |
9565 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9566 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9567 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9568 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9569 | { |
9570 | rot = (64 - rot) & 0x3f; | |
9571 | if (rot >= 32) | |
df58fc94 | 9572 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9573 | else |
df58fc94 | 9574 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9575 | break; |
60b63b72 | 9576 | } |
483fc7cd | 9577 | if (rot == 0) |
483fc7cd | 9578 | { |
df58fc94 | 9579 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9580 | break; |
483fc7cd | 9581 | } |
82dd0097 | 9582 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9583 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9584 | rot &= 0x1f; |
8fc2e39e | 9585 | used_at = 1; |
df58fc94 RS |
9586 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9587 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9588 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9589 | } |
9590 | break; | |
9591 | ||
252b5132 | 9592 | case M_ROL_I: |
771c7ce4 TS |
9593 | { |
9594 | unsigned int rot; | |
9595 | ||
9596 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9597 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9598 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9599 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9600 | { |
df58fc94 | 9601 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9602 | break; |
60b63b72 | 9603 | } |
483fc7cd | 9604 | if (rot == 0) |
483fc7cd | 9605 | { |
df58fc94 | 9606 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9607 | break; |
483fc7cd | 9608 | } |
8fc2e39e | 9609 | used_at = 1; |
df58fc94 RS |
9610 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9611 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9612 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9613 | } |
9614 | break; | |
9615 | ||
9616 | case M_DROR: | |
fef14a42 | 9617 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9618 | { |
67c0d1eb | 9619 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9620 | break; |
82dd0097 | 9621 | } |
8fc2e39e | 9622 | used_at = 1; |
c80c840e | 9623 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9624 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9625 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9626 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9627 | break; |
9628 | ||
9629 | case M_ROR: | |
fef14a42 | 9630 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9631 | { |
67c0d1eb | 9632 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9633 | break; |
82dd0097 | 9634 | } |
8fc2e39e | 9635 | used_at = 1; |
c80c840e | 9636 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9637 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9638 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9639 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9640 | break; |
9641 | ||
771c7ce4 TS |
9642 | case M_DROR_I: |
9643 | { | |
9644 | unsigned int rot; | |
91d6fa6a NC |
9645 | char *l; |
9646 | char *rr; | |
771c7ce4 TS |
9647 | |
9648 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9649 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9650 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9651 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9652 | { |
9653 | if (rot >= 32) | |
df58fc94 | 9654 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9655 | else |
df58fc94 | 9656 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9657 | break; |
82dd0097 | 9658 | } |
483fc7cd | 9659 | if (rot == 0) |
483fc7cd | 9660 | { |
df58fc94 | 9661 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9662 | break; |
483fc7cd | 9663 | } |
91d6fa6a | 9664 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9665 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9666 | rot &= 0x1f; | |
8fc2e39e | 9667 | used_at = 1; |
df58fc94 RS |
9668 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9669 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9670 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9671 | } |
9672 | break; | |
9673 | ||
252b5132 | 9674 | case M_ROR_I: |
771c7ce4 TS |
9675 | { |
9676 | unsigned int rot; | |
9677 | ||
9678 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9679 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9680 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9681 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9682 | { |
df58fc94 | 9683 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9684 | break; |
82dd0097 | 9685 | } |
483fc7cd | 9686 | if (rot == 0) |
483fc7cd | 9687 | { |
df58fc94 | 9688 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9689 | break; |
483fc7cd | 9690 | } |
8fc2e39e | 9691 | used_at = 1; |
df58fc94 RS |
9692 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9693 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9694 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9695 | } |
252b5132 RH |
9696 | break; |
9697 | ||
252b5132 RH |
9698 | case M_SEQ: |
9699 | if (sreg == 0) | |
67c0d1eb | 9700 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9701 | else if (treg == 0) |
67c0d1eb | 9702 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9703 | else |
9704 | { | |
67c0d1eb RS |
9705 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9706 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9707 | } |
8fc2e39e | 9708 | break; |
252b5132 RH |
9709 | |
9710 | case M_SEQ_I: | |
9711 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9712 | { | |
67c0d1eb | 9713 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9714 | break; |
252b5132 RH |
9715 | } |
9716 | if (sreg == 0) | |
9717 | { | |
9718 | as_warn (_("Instruction %s: result is always false"), | |
9719 | ip->insn_mo->name); | |
67c0d1eb | 9720 | move_register (dreg, 0); |
8fc2e39e | 9721 | break; |
252b5132 | 9722 | } |
dd3cbb7e NC |
9723 | if (CPU_HAS_SEQ (mips_opts.arch) |
9724 | && -512 <= imm_expr.X_add_number | |
9725 | && imm_expr.X_add_number < 512) | |
9726 | { | |
9727 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9728 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9729 | break; |
9730 | } | |
252b5132 RH |
9731 | if (imm_expr.X_op == O_constant |
9732 | && imm_expr.X_add_number >= 0 | |
9733 | && imm_expr.X_add_number < 0x10000) | |
9734 | { | |
67c0d1eb | 9735 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9736 | } |
9737 | else if (imm_expr.X_op == O_constant | |
9738 | && imm_expr.X_add_number > -0x8000 | |
9739 | && imm_expr.X_add_number < 0) | |
9740 | { | |
9741 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9742 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9743 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9744 | } |
dd3cbb7e NC |
9745 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9746 | { | |
9747 | used_at = 1; | |
9748 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9749 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9750 | break; | |
9751 | } | |
252b5132 RH |
9752 | else |
9753 | { | |
67c0d1eb RS |
9754 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9755 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9756 | used_at = 1; |
9757 | } | |
67c0d1eb | 9758 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9759 | break; |
252b5132 RH |
9760 | |
9761 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9762 | s = "slt"; | |
9763 | goto sge; | |
9764 | case M_SGEU: | |
9765 | s = "sltu"; | |
9766 | sge: | |
67c0d1eb RS |
9767 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9768 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9769 | break; |
252b5132 RH |
9770 | |
9771 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9772 | case M_SGEU_I: | |
9773 | if (imm_expr.X_op == O_constant | |
9774 | && imm_expr.X_add_number >= -0x8000 | |
9775 | && imm_expr.X_add_number < 0x8000) | |
9776 | { | |
67c0d1eb RS |
9777 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9778 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9779 | } |
9780 | else | |
9781 | { | |
67c0d1eb RS |
9782 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9783 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9784 | dreg, sreg, AT); | |
252b5132 RH |
9785 | used_at = 1; |
9786 | } | |
67c0d1eb | 9787 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9788 | break; |
252b5132 RH |
9789 | |
9790 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9791 | s = "slt"; | |
9792 | goto sgt; | |
9793 | case M_SGTU: | |
9794 | s = "sltu"; | |
9795 | sgt: | |
67c0d1eb | 9796 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9797 | break; |
252b5132 RH |
9798 | |
9799 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9800 | s = "slt"; | |
9801 | goto sgti; | |
9802 | case M_SGTU_I: | |
9803 | s = "sltu"; | |
9804 | sgti: | |
8fc2e39e | 9805 | used_at = 1; |
67c0d1eb RS |
9806 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9807 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9808 | break; |
9809 | ||
2396cfb9 | 9810 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9811 | s = "slt"; |
9812 | goto sle; | |
9813 | case M_SLEU: | |
9814 | s = "sltu"; | |
9815 | sle: | |
67c0d1eb RS |
9816 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9817 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9818 | break; |
252b5132 | 9819 | |
2396cfb9 | 9820 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9821 | s = "slt"; |
9822 | goto slei; | |
9823 | case M_SLEU_I: | |
9824 | s = "sltu"; | |
9825 | slei: | |
8fc2e39e | 9826 | used_at = 1; |
67c0d1eb RS |
9827 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9828 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9829 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9830 | break; |
9831 | ||
9832 | case M_SLT_I: | |
9833 | if (imm_expr.X_op == O_constant | |
9834 | && imm_expr.X_add_number >= -0x8000 | |
9835 | && imm_expr.X_add_number < 0x8000) | |
9836 | { | |
67c0d1eb | 9837 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9838 | break; |
252b5132 | 9839 | } |
8fc2e39e | 9840 | used_at = 1; |
67c0d1eb RS |
9841 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9842 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9843 | break; |
9844 | ||
9845 | case M_SLTU_I: | |
9846 | if (imm_expr.X_op == O_constant | |
9847 | && imm_expr.X_add_number >= -0x8000 | |
9848 | && imm_expr.X_add_number < 0x8000) | |
9849 | { | |
67c0d1eb | 9850 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9851 | BFD_RELOC_LO16); |
8fc2e39e | 9852 | break; |
252b5132 | 9853 | } |
8fc2e39e | 9854 | used_at = 1; |
67c0d1eb RS |
9855 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9856 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9857 | break; |
9858 | ||
9859 | case M_SNE: | |
9860 | if (sreg == 0) | |
67c0d1eb | 9861 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9862 | else if (treg == 0) |
67c0d1eb | 9863 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9864 | else |
9865 | { | |
67c0d1eb RS |
9866 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9867 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9868 | } |
8fc2e39e | 9869 | break; |
252b5132 RH |
9870 | |
9871 | case M_SNE_I: | |
9872 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9873 | { | |
67c0d1eb | 9874 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9875 | break; |
252b5132 RH |
9876 | } |
9877 | if (sreg == 0) | |
9878 | { | |
9879 | as_warn (_("Instruction %s: result is always true"), | |
9880 | ip->insn_mo->name); | |
67c0d1eb RS |
9881 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9882 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9883 | break; |
252b5132 | 9884 | } |
dd3cbb7e NC |
9885 | if (CPU_HAS_SEQ (mips_opts.arch) |
9886 | && -512 <= imm_expr.X_add_number | |
9887 | && imm_expr.X_add_number < 512) | |
9888 | { | |
9889 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9890 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9891 | break; |
9892 | } | |
252b5132 RH |
9893 | if (imm_expr.X_op == O_constant |
9894 | && imm_expr.X_add_number >= 0 | |
9895 | && imm_expr.X_add_number < 0x10000) | |
9896 | { | |
67c0d1eb | 9897 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9898 | } |
9899 | else if (imm_expr.X_op == O_constant | |
9900 | && imm_expr.X_add_number > -0x8000 | |
9901 | && imm_expr.X_add_number < 0) | |
9902 | { | |
9903 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9904 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9905 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9906 | } |
dd3cbb7e NC |
9907 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9908 | { | |
9909 | used_at = 1; | |
9910 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9911 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9912 | break; | |
9913 | } | |
252b5132 RH |
9914 | else |
9915 | { | |
67c0d1eb RS |
9916 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9917 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9918 | used_at = 1; |
9919 | } | |
67c0d1eb | 9920 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9921 | break; |
252b5132 | 9922 | |
df58fc94 RS |
9923 | case M_SUB_I: |
9924 | s = "addi"; | |
9925 | s2 = "sub"; | |
9926 | goto do_subi; | |
9927 | case M_SUBU_I: | |
9928 | s = "addiu"; | |
9929 | s2 = "subu"; | |
9930 | goto do_subi; | |
252b5132 RH |
9931 | case M_DSUB_I: |
9932 | dbl = 1; | |
df58fc94 RS |
9933 | s = "daddi"; |
9934 | s2 = "dsub"; | |
9935 | if (!mips_opts.micromips) | |
9936 | goto do_subi; | |
252b5132 | 9937 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9938 | && imm_expr.X_add_number > -0x200 |
9939 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9940 | { |
df58fc94 | 9941 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9942 | break; |
252b5132 | 9943 | } |
df58fc94 | 9944 | goto do_subi_i; |
252b5132 RH |
9945 | case M_DSUBU_I: |
9946 | dbl = 1; | |
df58fc94 RS |
9947 | s = "daddiu"; |
9948 | s2 = "dsubu"; | |
9949 | do_subi: | |
252b5132 RH |
9950 | if (imm_expr.X_op == O_constant |
9951 | && imm_expr.X_add_number > -0x8000 | |
9952 | && imm_expr.X_add_number <= 0x8000) | |
9953 | { | |
9954 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9955 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9956 | break; |
252b5132 | 9957 | } |
df58fc94 | 9958 | do_subi_i: |
8fc2e39e | 9959 | used_at = 1; |
67c0d1eb | 9960 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9961 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9962 | break; |
9963 | ||
9964 | case M_TEQ_I: | |
9965 | s = "teq"; | |
9966 | goto trap; | |
9967 | case M_TGE_I: | |
9968 | s = "tge"; | |
9969 | goto trap; | |
9970 | case M_TGEU_I: | |
9971 | s = "tgeu"; | |
9972 | goto trap; | |
9973 | case M_TLT_I: | |
9974 | s = "tlt"; | |
9975 | goto trap; | |
9976 | case M_TLTU_I: | |
9977 | s = "tltu"; | |
9978 | goto trap; | |
9979 | case M_TNE_I: | |
9980 | s = "tne"; | |
9981 | trap: | |
8fc2e39e | 9982 | used_at = 1; |
67c0d1eb RS |
9983 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9984 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9985 | break; |
9986 | ||
252b5132 | 9987 | case M_TRUNCWS: |
43841e91 | 9988 | case M_TRUNCWD: |
df58fc94 | 9989 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9990 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9991 | used_at = 1; |
252b5132 RH |
9992 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9993 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9994 | ||
9995 | /* | |
9996 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9997 | * or is there a reason for it? | |
9998 | */ | |
7d10b47d | 9999 | start_noreorder (); |
67c0d1eb RS |
10000 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10001 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10002 | macro_build (NULL, "nop", ""); | |
252b5132 | 10003 | expr1.X_add_number = 3; |
67c0d1eb | 10004 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10005 | expr1.X_add_number = 2; |
67c0d1eb RS |
10006 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10007 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10008 | macro_build (NULL, "nop", ""); | |
10009 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10010 | dreg, sreg); | |
10011 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10012 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10013 | end_noreorder (); |
252b5132 RH |
10014 | break; |
10015 | ||
df58fc94 RS |
10016 | case M_ULH_A: |
10017 | ab = 1; | |
252b5132 RH |
10018 | case M_ULH: |
10019 | s = "lb"; | |
df58fc94 RS |
10020 | s2 = "lbu"; |
10021 | off = 1; | |
10022 | goto uld_st; | |
10023 | case M_ULHU_A: | |
10024 | ab = 1; | |
252b5132 RH |
10025 | case M_ULHU: |
10026 | s = "lbu"; | |
df58fc94 RS |
10027 | s2 = "lbu"; |
10028 | off = 1; | |
10029 | goto uld_st; | |
10030 | case M_ULW_A: | |
10031 | ab = 1; | |
10032 | case M_ULW: | |
10033 | s = "lwl"; | |
10034 | s2 = "lwr"; | |
10035 | off12 = mips_opts.micromips; | |
10036 | off = 3; | |
10037 | goto uld_st; | |
10038 | case M_ULD_A: | |
10039 | ab = 1; | |
252b5132 RH |
10040 | case M_ULD: |
10041 | s = "ldl"; | |
10042 | s2 = "ldr"; | |
df58fc94 | 10043 | off12 = mips_opts.micromips; |
252b5132 | 10044 | off = 7; |
df58fc94 RS |
10045 | goto uld_st; |
10046 | case M_USH_A: | |
10047 | ab = 1; | |
10048 | case M_USH: | |
10049 | s = "sb"; | |
10050 | s2 = "sb"; | |
10051 | off = 1; | |
10052 | ust = 1; | |
10053 | goto uld_st; | |
10054 | case M_USW_A: | |
10055 | ab = 1; | |
10056 | case M_USW: | |
10057 | s = "swl"; | |
10058 | s2 = "swr"; | |
10059 | off12 = mips_opts.micromips; | |
252b5132 | 10060 | off = 3; |
df58fc94 RS |
10061 | ust = 1; |
10062 | goto uld_st; | |
10063 | case M_USD_A: | |
10064 | ab = 1; | |
10065 | case M_USD: | |
10066 | s = "sdl"; | |
10067 | s2 = "sdr"; | |
10068 | off12 = mips_opts.micromips; | |
10069 | off = 7; | |
10070 | ust = 1; | |
10071 | ||
10072 | uld_st: | |
10073 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10074 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10075 | |
10076 | ep = &offset_expr; | |
10077 | expr1.X_add_number = 0; | |
10078 | if (ab) | |
10079 | { | |
10080 | used_at = 1; | |
10081 | tempreg = AT; | |
10082 | load_address (tempreg, ep, &used_at); | |
10083 | if (breg != 0) | |
10084 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10085 | tempreg, tempreg, breg); | |
10086 | breg = tempreg; | |
10087 | tempreg = treg; | |
10088 | ep = &expr1; | |
10089 | } | |
10090 | else if (off12 | |
10091 | && (offset_expr.X_op != O_constant | |
10092 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10093 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10094 | { | |
10095 | used_at = 1; | |
10096 | tempreg = AT; | |
10097 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10098 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10099 | breg = tempreg; | |
10100 | tempreg = treg; | |
10101 | ep = &expr1; | |
10102 | } | |
10103 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10104 | { |
10105 | used_at = 1; | |
10106 | tempreg = AT; | |
10107 | } | |
252b5132 | 10108 | else |
df58fc94 | 10109 | tempreg = treg; |
af22f5b2 | 10110 | |
df58fc94 RS |
10111 | if (off == 1) |
10112 | goto ulh_sh; | |
252b5132 | 10113 | |
90ecf173 | 10114 | if (!target_big_endian) |
df58fc94 RS |
10115 | ep->X_add_number += off; |
10116 | if (!off12) | |
10117 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10118 | else |
df58fc94 RS |
10119 | macro_build (NULL, s, "t,~(b)", |
10120 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10121 | ||
90ecf173 | 10122 | if (!target_big_endian) |
df58fc94 | 10123 | ep->X_add_number -= off; |
252b5132 | 10124 | else |
df58fc94 RS |
10125 | ep->X_add_number += off; |
10126 | if (!off12) | |
10127 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10128 | else | |
10129 | macro_build (NULL, s2, "t,~(b)", | |
10130 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10131 | |
df58fc94 RS |
10132 | /* If necessary, move the result in tempreg to the final destination. */ |
10133 | if (!ust && treg != tempreg) | |
10134 | { | |
10135 | /* Protect second load's delay slot. */ | |
10136 | load_delay_nop (); | |
10137 | move_register (treg, tempreg); | |
10138 | } | |
8fc2e39e | 10139 | break; |
252b5132 | 10140 | |
df58fc94 | 10141 | ulh_sh: |
d6bc6245 | 10142 | used_at = 1; |
df58fc94 RS |
10143 | if (target_big_endian == ust) |
10144 | ep->X_add_number += off; | |
10145 | tempreg = ust || ab ? treg : AT; | |
10146 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10147 | ||
10148 | /* For halfword transfers we need a temporary register to shuffle | |
10149 | bytes. Unfortunately for M_USH_A we have none available before | |
10150 | the next store as AT holds the base address. We deal with this | |
10151 | case by clobbering TREG and then restoring it as with ULH. */ | |
10152 | tempreg = ust == ab ? treg : AT; | |
10153 | if (ust) | |
10154 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10155 | ||
10156 | if (target_big_endian == ust) | |
10157 | ep->X_add_number -= off; | |
252b5132 | 10158 | else |
df58fc94 RS |
10159 | ep->X_add_number += off; |
10160 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10161 | |
df58fc94 RS |
10162 | /* For M_USH_A re-retrieve the LSB. */ |
10163 | if (ust && ab) | |
10164 | { | |
10165 | if (target_big_endian) | |
10166 | ep->X_add_number += off; | |
10167 | else | |
10168 | ep->X_add_number -= off; | |
10169 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10170 | } | |
10171 | /* For ULH and M_USH_A OR the LSB in. */ | |
10172 | if (!ust || ab) | |
10173 | { | |
10174 | tempreg = !ab ? AT : treg; | |
10175 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10176 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10177 | } | |
252b5132 RH |
10178 | break; |
10179 | ||
10180 | default: | |
10181 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10182 | are added dynamically. */ |
252b5132 RH |
10183 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10184 | break; | |
10185 | } | |
741fe287 | 10186 | if (!mips_opts.at && used_at) |
8fc2e39e | 10187 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10188 | } |
10189 | ||
10190 | /* Implement macros in mips16 mode. */ | |
10191 | ||
10192 | static void | |
17a2f251 | 10193 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10194 | { |
10195 | int mask; | |
10196 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10197 | expressionS expr1; |
10198 | int dbl; | |
10199 | const char *s, *s2, *s3; | |
10200 | ||
10201 | mask = ip->insn_mo->mask; | |
10202 | ||
bf12938e RS |
10203 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10204 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10205 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10206 | |
252b5132 RH |
10207 | expr1.X_op = O_constant; |
10208 | expr1.X_op_symbol = NULL; | |
10209 | expr1.X_add_symbol = NULL; | |
10210 | expr1.X_add_number = 1; | |
10211 | ||
10212 | dbl = 0; | |
10213 | ||
10214 | switch (mask) | |
10215 | { | |
10216 | default: | |
b37df7c4 | 10217 | abort (); |
252b5132 RH |
10218 | |
10219 | case M_DDIV_3: | |
10220 | dbl = 1; | |
10221 | case M_DIV_3: | |
10222 | s = "mflo"; | |
10223 | goto do_div3; | |
10224 | case M_DREM_3: | |
10225 | dbl = 1; | |
10226 | case M_REM_3: | |
10227 | s = "mfhi"; | |
10228 | do_div3: | |
7d10b47d | 10229 | start_noreorder (); |
67c0d1eb | 10230 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10231 | expr1.X_add_number = 2; |
67c0d1eb RS |
10232 | macro_build (&expr1, "bnez", "x,p", yreg); |
10233 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10234 | |
252b5132 RH |
10235 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10236 | since that causes an overflow. We should do that as well, | |
10237 | but I don't see how to do the comparisons without a temporary | |
10238 | register. */ | |
7d10b47d | 10239 | end_noreorder (); |
67c0d1eb | 10240 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10241 | break; |
10242 | ||
10243 | case M_DIVU_3: | |
10244 | s = "divu"; | |
10245 | s2 = "mflo"; | |
10246 | goto do_divu3; | |
10247 | case M_REMU_3: | |
10248 | s = "divu"; | |
10249 | s2 = "mfhi"; | |
10250 | goto do_divu3; | |
10251 | case M_DDIVU_3: | |
10252 | s = "ddivu"; | |
10253 | s2 = "mflo"; | |
10254 | goto do_divu3; | |
10255 | case M_DREMU_3: | |
10256 | s = "ddivu"; | |
10257 | s2 = "mfhi"; | |
10258 | do_divu3: | |
7d10b47d | 10259 | start_noreorder (); |
67c0d1eb | 10260 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10261 | expr1.X_add_number = 2; |
67c0d1eb RS |
10262 | macro_build (&expr1, "bnez", "x,p", yreg); |
10263 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10264 | end_noreorder (); |
67c0d1eb | 10265 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10266 | break; |
10267 | ||
10268 | case M_DMUL: | |
10269 | dbl = 1; | |
10270 | case M_MUL: | |
67c0d1eb RS |
10271 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10272 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10273 | break; |
252b5132 RH |
10274 | |
10275 | case M_DSUBU_I: | |
10276 | dbl = 1; | |
10277 | goto do_subu; | |
10278 | case M_SUBU_I: | |
10279 | do_subu: | |
10280 | if (imm_expr.X_op != O_constant) | |
10281 | as_bad (_("Unsupported large constant")); | |
10282 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10283 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10284 | break; |
10285 | ||
10286 | case M_SUBU_I_2: | |
10287 | if (imm_expr.X_op != O_constant) | |
10288 | as_bad (_("Unsupported large constant")); | |
10289 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10290 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10291 | break; |
10292 | ||
10293 | case M_DSUBU_I_2: | |
10294 | if (imm_expr.X_op != O_constant) | |
10295 | as_bad (_("Unsupported large constant")); | |
10296 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10297 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10298 | break; |
10299 | ||
10300 | case M_BEQ: | |
10301 | s = "cmp"; | |
10302 | s2 = "bteqz"; | |
10303 | goto do_branch; | |
10304 | case M_BNE: | |
10305 | s = "cmp"; | |
10306 | s2 = "btnez"; | |
10307 | goto do_branch; | |
10308 | case M_BLT: | |
10309 | s = "slt"; | |
10310 | s2 = "btnez"; | |
10311 | goto do_branch; | |
10312 | case M_BLTU: | |
10313 | s = "sltu"; | |
10314 | s2 = "btnez"; | |
10315 | goto do_branch; | |
10316 | case M_BLE: | |
10317 | s = "slt"; | |
10318 | s2 = "bteqz"; | |
10319 | goto do_reverse_branch; | |
10320 | case M_BLEU: | |
10321 | s = "sltu"; | |
10322 | s2 = "bteqz"; | |
10323 | goto do_reverse_branch; | |
10324 | case M_BGE: | |
10325 | s = "slt"; | |
10326 | s2 = "bteqz"; | |
10327 | goto do_branch; | |
10328 | case M_BGEU: | |
10329 | s = "sltu"; | |
10330 | s2 = "bteqz"; | |
10331 | goto do_branch; | |
10332 | case M_BGT: | |
10333 | s = "slt"; | |
10334 | s2 = "btnez"; | |
10335 | goto do_reverse_branch; | |
10336 | case M_BGTU: | |
10337 | s = "sltu"; | |
10338 | s2 = "btnez"; | |
10339 | ||
10340 | do_reverse_branch: | |
10341 | tmp = xreg; | |
10342 | xreg = yreg; | |
10343 | yreg = tmp; | |
10344 | ||
10345 | do_branch: | |
67c0d1eb RS |
10346 | macro_build (NULL, s, "x,y", xreg, yreg); |
10347 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10348 | break; |
10349 | ||
10350 | case M_BEQ_I: | |
10351 | s = "cmpi"; | |
10352 | s2 = "bteqz"; | |
10353 | s3 = "x,U"; | |
10354 | goto do_branch_i; | |
10355 | case M_BNE_I: | |
10356 | s = "cmpi"; | |
10357 | s2 = "btnez"; | |
10358 | s3 = "x,U"; | |
10359 | goto do_branch_i; | |
10360 | case M_BLT_I: | |
10361 | s = "slti"; | |
10362 | s2 = "btnez"; | |
10363 | s3 = "x,8"; | |
10364 | goto do_branch_i; | |
10365 | case M_BLTU_I: | |
10366 | s = "sltiu"; | |
10367 | s2 = "btnez"; | |
10368 | s3 = "x,8"; | |
10369 | goto do_branch_i; | |
10370 | case M_BLE_I: | |
10371 | s = "slti"; | |
10372 | s2 = "btnez"; | |
10373 | s3 = "x,8"; | |
10374 | goto do_addone_branch_i; | |
10375 | case M_BLEU_I: | |
10376 | s = "sltiu"; | |
10377 | s2 = "btnez"; | |
10378 | s3 = "x,8"; | |
10379 | goto do_addone_branch_i; | |
10380 | case M_BGE_I: | |
10381 | s = "slti"; | |
10382 | s2 = "bteqz"; | |
10383 | s3 = "x,8"; | |
10384 | goto do_branch_i; | |
10385 | case M_BGEU_I: | |
10386 | s = "sltiu"; | |
10387 | s2 = "bteqz"; | |
10388 | s3 = "x,8"; | |
10389 | goto do_branch_i; | |
10390 | case M_BGT_I: | |
10391 | s = "slti"; | |
10392 | s2 = "bteqz"; | |
10393 | s3 = "x,8"; | |
10394 | goto do_addone_branch_i; | |
10395 | case M_BGTU_I: | |
10396 | s = "sltiu"; | |
10397 | s2 = "bteqz"; | |
10398 | s3 = "x,8"; | |
10399 | ||
10400 | do_addone_branch_i: | |
10401 | if (imm_expr.X_op != O_constant) | |
10402 | as_bad (_("Unsupported large constant")); | |
10403 | ++imm_expr.X_add_number; | |
10404 | ||
10405 | do_branch_i: | |
67c0d1eb RS |
10406 | macro_build (&imm_expr, s, s3, xreg); |
10407 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10408 | break; |
10409 | ||
10410 | case M_ABS: | |
10411 | expr1.X_add_number = 0; | |
67c0d1eb | 10412 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10413 | if (xreg != yreg) |
67c0d1eb | 10414 | move_register (xreg, yreg); |
252b5132 | 10415 | expr1.X_add_number = 2; |
67c0d1eb RS |
10416 | macro_build (&expr1, "bteqz", "p"); |
10417 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10418 | } |
10419 | } | |
10420 | ||
10421 | /* For consistency checking, verify that all bits are specified either | |
10422 | by the match/mask part of the instruction definition, or by the | |
10423 | operand list. */ | |
10424 | static int | |
17a2f251 | 10425 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10426 | { |
10427 | const char *p = opc->args; | |
10428 | char c; | |
10429 | unsigned long used_bits = opc->mask; | |
10430 | ||
10431 | if ((used_bits & opc->match) != opc->match) | |
10432 | { | |
10433 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10434 | opc->name, opc->args); | |
10435 | return 0; | |
10436 | } | |
10437 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10438 | while (*p) | |
10439 | switch (c = *p++) | |
10440 | { | |
10441 | case ',': break; | |
10442 | case '(': break; | |
10443 | case ')': break; | |
af7ee8bf CD |
10444 | case '+': |
10445 | switch (c = *p++) | |
10446 | { | |
9bcd4f99 TS |
10447 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10448 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10449 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10450 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10451 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10452 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10453 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10454 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10455 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10456 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10457 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10458 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10459 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10460 | case 'I': break; | |
b015e599 | 10461 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10462 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10463 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10464 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10465 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10466 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10467 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10468 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10469 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10470 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10471 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10472 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10473 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10474 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10475 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10476 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10477 | |
af7ee8bf CD |
10478 | default: |
10479 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10480 | c, opc->name, opc->args); | |
10481 | return 0; | |
10482 | } | |
10483 | break; | |
252b5132 RH |
10484 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10485 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10486 | case 'A': break; | |
4372b673 | 10487 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10488 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10489 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10490 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10491 | case 'F': break; | |
10492 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10493 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10494 | case 'I': break; |
e972090a | 10495 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10496 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10497 | case 'L': break; |
10498 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10499 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10500 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10501 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10502 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10503 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10504 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10505 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10506 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10507 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10508 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10509 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10510 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10511 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10512 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10513 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10514 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10515 | case 'f': break; | |
10516 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10517 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10518 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10519 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10520 | case 'l': break; | |
10521 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10522 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10523 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10524 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10525 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10526 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10527 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10528 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10529 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10530 | case 'x': break; | |
10531 | case 'z': break; | |
10532 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10533 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10534 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10535 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10536 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10537 | case '[': break; | |
10538 | case ']': break; | |
620edafd | 10539 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10540 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10541 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10542 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10543 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10544 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10545 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10546 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10547 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10548 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10549 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10550 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10551 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10552 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10553 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10554 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10555 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10556 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10557 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10558 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10559 | default: |
10560 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10561 | c, opc->name, opc->args); | |
10562 | return 0; | |
10563 | } | |
10564 | #undef USE_BITS | |
10565 | if (used_bits != 0xffffffff) | |
10566 | { | |
10567 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10568 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10569 | return 0; | |
10570 | } | |
10571 | return 1; | |
10572 | } | |
10573 | ||
df58fc94 RS |
10574 | /* For consistency checking, verify that the length implied matches the |
10575 | major opcode and that all bits are specified either by the match/mask | |
10576 | part of the instruction definition, or by the operand list. */ | |
10577 | ||
10578 | static int | |
10579 | validate_micromips_insn (const struct mips_opcode *opc) | |
10580 | { | |
10581 | unsigned long match = opc->match; | |
10582 | unsigned long mask = opc->mask; | |
10583 | const char *p = opc->args; | |
10584 | unsigned long insn_bits; | |
10585 | unsigned long used_bits; | |
10586 | unsigned long major; | |
10587 | unsigned int length; | |
10588 | char e; | |
10589 | char c; | |
10590 | ||
10591 | if ((mask & match) != match) | |
10592 | { | |
10593 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10594 | opc->name, opc->args); | |
10595 | return 0; | |
10596 | } | |
10597 | length = micromips_insn_length (opc); | |
10598 | if (length != 2 && length != 4) | |
10599 | { | |
10600 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10601 | "%s %s"), length, opc->name, opc->args); | |
10602 | return 0; | |
10603 | } | |
10604 | major = match >> (10 + 8 * (length - 2)); | |
10605 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10606 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10607 | { | |
10608 | as_bad (_("Internal error: bad microMIPS opcode " | |
10609 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10610 | return 0; | |
10611 | } | |
10612 | ||
10613 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10614 | insn_bits = 1 << 4 * length; | |
10615 | insn_bits <<= 4 * length; | |
10616 | insn_bits -= 1; | |
10617 | used_bits = mask; | |
10618 | #define USE_BITS(field) \ | |
10619 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10620 | while (*p) | |
10621 | switch (c = *p++) | |
10622 | { | |
10623 | case ',': break; | |
10624 | case '(': break; | |
10625 | case ')': break; | |
10626 | case '+': | |
10627 | e = c; | |
10628 | switch (c = *p++) | |
10629 | { | |
10630 | case 'A': USE_BITS (EXTLSB); break; | |
10631 | case 'B': USE_BITS (INSMSB); break; | |
10632 | case 'C': USE_BITS (EXTMSBD); break; | |
10633 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10634 | case 'E': USE_BITS (EXTLSB); break; | |
10635 | case 'F': USE_BITS (INSMSB); break; | |
10636 | case 'G': USE_BITS (EXTMSBD); break; | |
10637 | case 'H': USE_BITS (EXTMSBD); break; | |
10638 | default: | |
10639 | as_bad (_("Internal error: bad mips opcode " | |
10640 | "(unknown extension operand type `%c%c'): %s %s"), | |
10641 | e, c, opc->name, opc->args); | |
10642 | return 0; | |
10643 | } | |
10644 | break; | |
10645 | case 'm': | |
10646 | e = c; | |
10647 | switch (c = *p++) | |
10648 | { | |
10649 | case 'A': USE_BITS (IMMA); break; | |
10650 | case 'B': USE_BITS (IMMB); break; | |
10651 | case 'C': USE_BITS (IMMC); break; | |
10652 | case 'D': USE_BITS (IMMD); break; | |
10653 | case 'E': USE_BITS (IMME); break; | |
10654 | case 'F': USE_BITS (IMMF); break; | |
10655 | case 'G': USE_BITS (IMMG); break; | |
10656 | case 'H': USE_BITS (IMMH); break; | |
10657 | case 'I': USE_BITS (IMMI); break; | |
10658 | case 'J': USE_BITS (IMMJ); break; | |
10659 | case 'L': USE_BITS (IMML); break; | |
10660 | case 'M': USE_BITS (IMMM); break; | |
10661 | case 'N': USE_BITS (IMMN); break; | |
10662 | case 'O': USE_BITS (IMMO); break; | |
10663 | case 'P': USE_BITS (IMMP); break; | |
10664 | case 'Q': USE_BITS (IMMQ); break; | |
10665 | case 'U': USE_BITS (IMMU); break; | |
10666 | case 'W': USE_BITS (IMMW); break; | |
10667 | case 'X': USE_BITS (IMMX); break; | |
10668 | case 'Y': USE_BITS (IMMY); break; | |
10669 | case 'Z': break; | |
10670 | case 'a': break; | |
10671 | case 'b': USE_BITS (MB); break; | |
10672 | case 'c': USE_BITS (MC); break; | |
10673 | case 'd': USE_BITS (MD); break; | |
10674 | case 'e': USE_BITS (ME); break; | |
10675 | case 'f': USE_BITS (MF); break; | |
10676 | case 'g': USE_BITS (MG); break; | |
10677 | case 'h': USE_BITS (MH); break; | |
10678 | case 'i': USE_BITS (MI); break; | |
10679 | case 'j': USE_BITS (MJ); break; | |
10680 | case 'l': USE_BITS (ML); break; | |
10681 | case 'm': USE_BITS (MM); break; | |
10682 | case 'n': USE_BITS (MN); break; | |
10683 | case 'p': USE_BITS (MP); break; | |
10684 | case 'q': USE_BITS (MQ); break; | |
10685 | case 'r': break; | |
10686 | case 's': break; | |
10687 | case 't': break; | |
10688 | case 'x': break; | |
10689 | case 'y': break; | |
10690 | case 'z': break; | |
10691 | default: | |
10692 | as_bad (_("Internal error: bad mips opcode " | |
10693 | "(unknown extension operand type `%c%c'): %s %s"), | |
10694 | e, c, opc->name, opc->args); | |
10695 | return 0; | |
10696 | } | |
10697 | break; | |
10698 | case '.': USE_BITS (OFFSET10); break; | |
10699 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10700 | case '2': USE_BITS (BP); break; |
10701 | case '3': USE_BITS (SA3); break; | |
10702 | case '4': USE_BITS (SA4); break; | |
10703 | case '5': USE_BITS (IMM8); break; | |
10704 | case '6': USE_BITS (RS); break; | |
10705 | case '7': USE_BITS (DSPACC); break; | |
10706 | case '8': USE_BITS (WRDSP); break; | |
10707 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10708 | case '<': USE_BITS (SHAMT); break; |
10709 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10710 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10711 | case 'B': USE_BITS (CODE10); break; |
10712 | case 'C': USE_BITS (COPZ); break; | |
10713 | case 'D': USE_BITS (FD); break; | |
10714 | case 'E': USE_BITS (RT); break; | |
10715 | case 'G': USE_BITS (RS); break; | |
444d75be | 10716 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10717 | case 'K': USE_BITS (RS); break; |
10718 | case 'M': USE_BITS (CCC); break; | |
10719 | case 'N': USE_BITS (BCC); break; | |
10720 | case 'R': USE_BITS (FR); break; | |
10721 | case 'S': USE_BITS (FS); break; | |
10722 | case 'T': USE_BITS (FT); break; | |
10723 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10724 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10725 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10726 | case 'a': USE_BITS (TARGET); break; |
10727 | case 'b': USE_BITS (RS); break; | |
10728 | case 'c': USE_BITS (CODE); break; | |
10729 | case 'd': USE_BITS (RD); break; | |
10730 | case 'h': USE_BITS (PREFX); break; | |
10731 | case 'i': USE_BITS (IMMEDIATE); break; | |
10732 | case 'j': USE_BITS (DELTA); break; | |
10733 | case 'k': USE_BITS (CACHE); break; | |
10734 | case 'n': USE_BITS (RT); break; | |
10735 | case 'o': USE_BITS (DELTA); break; | |
10736 | case 'p': USE_BITS (DELTA); break; | |
10737 | case 'q': USE_BITS (CODE2); break; | |
10738 | case 'r': USE_BITS (RS); break; | |
10739 | case 's': USE_BITS (RS); break; | |
10740 | case 't': USE_BITS (RT); break; | |
10741 | case 'u': USE_BITS (IMMEDIATE); break; | |
10742 | case 'v': USE_BITS (RS); break; | |
10743 | case 'w': USE_BITS (RT); break; | |
10744 | case 'y': USE_BITS (RS3); break; | |
10745 | case 'z': break; | |
10746 | case '|': USE_BITS (TRAP); break; | |
10747 | case '~': USE_BITS (OFFSET12); break; | |
10748 | default: | |
10749 | as_bad (_("Internal error: bad microMIPS opcode " | |
10750 | "(unknown operand type `%c'): %s %s"), | |
10751 | c, opc->name, opc->args); | |
10752 | return 0; | |
10753 | } | |
10754 | #undef USE_BITS | |
10755 | if (used_bits != insn_bits) | |
10756 | { | |
10757 | if (~used_bits & insn_bits) | |
10758 | as_bad (_("Internal error: bad microMIPS opcode " | |
10759 | "(bits 0x%lx undefined): %s %s"), | |
10760 | ~used_bits & insn_bits, opc->name, opc->args); | |
10761 | if (used_bits & ~insn_bits) | |
10762 | as_bad (_("Internal error: bad microMIPS opcode " | |
10763 | "(bits 0x%lx defined): %s %s"), | |
10764 | used_bits & ~insn_bits, opc->name, opc->args); | |
10765 | return 0; | |
10766 | } | |
10767 | return 1; | |
10768 | } | |
10769 | ||
9bcd4f99 TS |
10770 | /* UDI immediates. */ |
10771 | struct mips_immed { | |
10772 | char type; | |
10773 | unsigned int shift; | |
10774 | unsigned long mask; | |
10775 | const char * desc; | |
10776 | }; | |
10777 | ||
10778 | static const struct mips_immed mips_immed[] = { | |
10779 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10780 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10781 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10782 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10783 | { 0,0,0,0 } | |
10784 | }; | |
10785 | ||
7455baf8 TS |
10786 | /* Check whether an odd floating-point register is allowed. */ |
10787 | static int | |
10788 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10789 | { | |
10790 | const char *s = insn->name; | |
10791 | ||
10792 | if (insn->pinfo == INSN_MACRO) | |
10793 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10794 | return 1; | |
10795 | ||
e407c74b | 10796 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
10797 | { |
10798 | /* Allow odd registers for single-precision ops. */ | |
10799 | switch (insn->pinfo & (FP_S | FP_D)) | |
10800 | { | |
10801 | case FP_S: | |
10802 | case 0: | |
10803 | return 1; /* both single precision - ok */ | |
10804 | case FP_D: | |
10805 | return 0; /* both double precision - fail */ | |
10806 | default: | |
10807 | break; | |
10808 | } | |
10809 | ||
10810 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10811 | s = strchr (insn->name, '.'); | |
10812 | if (argnum == 2) | |
10813 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10814 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10815 | } | |
10816 | ||
10817 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10818 | if ((insn->pinfo & FP_S) | |
10819 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10820 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10821 | return 1; | |
10822 | ||
10823 | return 0; | |
10824 | } | |
10825 | ||
df58fc94 RS |
10826 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10827 | taking bits from BIT up. */ | |
10828 | static int | |
10829 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10830 | { | |
10831 | return (ep->X_op == O_constant | |
10832 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10833 | && ep->X_add_number >= min << bit | |
10834 | && ep->X_add_number < max << bit); | |
10835 | } | |
10836 | ||
252b5132 RH |
10837 | /* This routine assembles an instruction into its binary format. As a |
10838 | side effect, it sets one of the global variables imm_reloc or | |
10839 | offset_reloc to the type of relocation to do if one of the operands | |
10840 | is an address expression. */ | |
10841 | ||
10842 | static void | |
17a2f251 | 10843 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10844 | { |
df58fc94 RS |
10845 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10846 | bfd_boolean need_delay_slot_ok = TRUE; | |
10847 | struct mips_opcode *firstinsn = NULL; | |
10848 | const struct mips_opcode *past; | |
10849 | struct hash_control *hash; | |
252b5132 RH |
10850 | char *s; |
10851 | const char *args; | |
43841e91 | 10852 | char c = 0; |
252b5132 RH |
10853 | struct mips_opcode *insn; |
10854 | char *argsStart; | |
10855 | unsigned int regno; | |
34224acf | 10856 | unsigned int lastregno; |
df58fc94 | 10857 | unsigned int destregno = 0; |
af7ee8bf | 10858 | unsigned int lastpos = 0; |
071742cf | 10859 | unsigned int limlo, limhi; |
f02d8318 | 10860 | int sizelo; |
252b5132 | 10861 | char *s_reset; |
74cd071d | 10862 | offsetT min_range, max_range; |
df58fc94 | 10863 | long opend; |
a40bc9dd | 10864 | char *name; |
707bfff6 TS |
10865 | int argnum; |
10866 | unsigned int rtype; | |
df58fc94 | 10867 | char *dot; |
a40bc9dd | 10868 | long end; |
252b5132 RH |
10869 | |
10870 | insn_error = NULL; | |
10871 | ||
df58fc94 RS |
10872 | if (mips_opts.micromips) |
10873 | { | |
10874 | hash = micromips_op_hash; | |
10875 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10876 | } | |
10877 | else | |
10878 | { | |
10879 | hash = op_hash; | |
10880 | past = &mips_opcodes[NUMOPCODES]; | |
10881 | } | |
10882 | forced_insn_length = 0; | |
252b5132 | 10883 | insn = NULL; |
252b5132 | 10884 | |
df58fc94 | 10885 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10886 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10887 | continue; | |
bdaaa2e1 | 10888 | |
a40bc9dd RS |
10889 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10890 | name = alloca (end + 1); | |
10891 | memcpy (name, str, end); | |
10892 | name[end] = '\0'; | |
252b5132 | 10893 | |
df58fc94 RS |
10894 | for (;;) |
10895 | { | |
10896 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10897 | ||
10898 | if (insn != NULL || !mips_opts.micromips) | |
10899 | break; | |
10900 | if (forced_insn_length) | |
10901 | break; | |
10902 | ||
10903 | /* See if there's an instruction size override suffix, | |
10904 | either `16' or `32', at the end of the mnemonic proper, | |
10905 | that defines the operation, i.e. before the first `.' | |
10906 | character if any. Strip it and retry. */ | |
10907 | dot = strchr (name, '.'); | |
10908 | opend = dot != NULL ? dot - name : end; | |
10909 | if (opend < 3) | |
10910 | break; | |
10911 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10912 | forced_insn_length = 2; | |
10913 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10914 | forced_insn_length = 4; | |
10915 | else | |
10916 | break; | |
10917 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10918 | } | |
252b5132 RH |
10919 | if (insn == NULL) |
10920 | { | |
a40bc9dd RS |
10921 | insn_error = _("Unrecognized opcode"); |
10922 | return; | |
252b5132 RH |
10923 | } |
10924 | ||
df58fc94 RS |
10925 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10926 | we make up to two passes over the relevant fragment of the opcode | |
10927 | table. First we try instructions that meet the delay slot's length | |
10928 | requirement. If none matched, then we retry with the remaining ones | |
10929 | and if one matches, then we use it and then issue an appropriate | |
10930 | warning later on. */ | |
a40bc9dd | 10931 | argsStart = s = str + end; |
252b5132 RH |
10932 | for (;;) |
10933 | { | |
df58fc94 RS |
10934 | bfd_boolean delay_slot_ok; |
10935 | bfd_boolean size_ok; | |
b34976b6 | 10936 | bfd_boolean ok; |
252b5132 | 10937 | |
a40bc9dd | 10938 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10939 | |
f79e2745 | 10940 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10941 | size_ok = is_size_valid (insn); |
10942 | delay_slot_ok = is_delay_slot_valid (insn); | |
10943 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10944 | { |
df58fc94 RS |
10945 | firstinsn = insn; |
10946 | wrong_delay_slot_insns = TRUE; | |
10947 | } | |
10948 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10949 | { | |
10950 | static char buf[256]; | |
10951 | ||
10952 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10953 | { |
10954 | ++insn; | |
10955 | continue; | |
10956 | } | |
df58fc94 | 10957 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10958 | { |
df58fc94 RS |
10959 | gas_assert (firstinsn); |
10960 | need_delay_slot_ok = FALSE; | |
10961 | past = insn + 1; | |
10962 | insn = firstinsn; | |
10963 | continue; | |
252b5132 | 10964 | } |
df58fc94 RS |
10965 | |
10966 | if (insn_error) | |
10967 | return; | |
10968 | ||
10969 | if (!ok) | |
7bd942df | 10970 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10971 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10972 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10973 | else | |
10974 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10975 | 8 * forced_insn_length); | |
10976 | insn_error = buf; | |
10977 | ||
10978 | return; | |
252b5132 RH |
10979 | } |
10980 | ||
1e915849 | 10981 | create_insn (ip, insn); |
268f6bed | 10982 | insn_error = NULL; |
707bfff6 | 10983 | argnum = 1; |
24864476 | 10984 | lastregno = 0xffffffff; |
252b5132 RH |
10985 | for (args = insn->args;; ++args) |
10986 | { | |
deec1734 CD |
10987 | int is_mdmx; |
10988 | ||
ad8d3bb3 | 10989 | s += strspn (s, " \t"); |
deec1734 | 10990 | is_mdmx = 0; |
252b5132 RH |
10991 | switch (*args) |
10992 | { | |
10993 | case '\0': /* end of args */ | |
10994 | if (*s == '\0') | |
10995 | return; | |
10996 | break; | |
10997 | ||
03f66e8a MR |
10998 | case '2': |
10999 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11000 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11001 | my_getExpression (&imm_expr, s); |
11002 | check_absolute_expr (ip, &imm_expr); | |
11003 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11004 | && (unsigned long) imm_expr.X_add_number != 3) | |
11005 | { | |
11006 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11007 | (unsigned long) imm_expr.X_add_number); | |
11008 | } | |
03f66e8a MR |
11009 | INSERT_OPERAND (mips_opts.micromips, |
11010 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11011 | imm_expr.X_op = O_absent; |
11012 | s = expr_end; | |
11013 | continue; | |
11014 | ||
03f66e8a MR |
11015 | case '3': |
11016 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11017 | code) or 21 (for microMIPS code). */ | |
11018 | { | |
11019 | unsigned long mask = (mips_opts.micromips | |
11020 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11021 | ||
11022 | my_getExpression (&imm_expr, s); | |
11023 | check_absolute_expr (ip, &imm_expr); | |
11024 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11025 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11026 | mask, (unsigned long) imm_expr.X_add_number); | |
11027 | INSERT_OPERAND (mips_opts.micromips, | |
11028 | SA3, *ip, imm_expr.X_add_number); | |
11029 | imm_expr.X_op = O_absent; | |
11030 | s = expr_end; | |
11031 | } | |
74cd071d CF |
11032 | continue; |
11033 | ||
03f66e8a MR |
11034 | case '4': |
11035 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11036 | code) or 21 (for microMIPS code). */ | |
11037 | { | |
11038 | unsigned long mask = (mips_opts.micromips | |
11039 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11040 | ||
11041 | my_getExpression (&imm_expr, s); | |
11042 | check_absolute_expr (ip, &imm_expr); | |
11043 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11044 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11045 | mask, (unsigned long) imm_expr.X_add_number); | |
11046 | INSERT_OPERAND (mips_opts.micromips, | |
11047 | SA4, *ip, imm_expr.X_add_number); | |
11048 | imm_expr.X_op = O_absent; | |
11049 | s = expr_end; | |
11050 | } | |
74cd071d CF |
11051 | continue; |
11052 | ||
03f66e8a MR |
11053 | case '5': |
11054 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11055 | code) or 16 (for microMIPS code). */ | |
11056 | { | |
11057 | unsigned long mask = (mips_opts.micromips | |
11058 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11059 | ||
11060 | my_getExpression (&imm_expr, s); | |
11061 | check_absolute_expr (ip, &imm_expr); | |
11062 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11063 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11064 | mask, (unsigned long) imm_expr.X_add_number); | |
11065 | INSERT_OPERAND (mips_opts.micromips, | |
11066 | IMM8, *ip, imm_expr.X_add_number); | |
11067 | imm_expr.X_op = O_absent; | |
11068 | s = expr_end; | |
11069 | } | |
74cd071d CF |
11070 | continue; |
11071 | ||
03f66e8a MR |
11072 | case '6': |
11073 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11074 | code) or 21 (for microMIPS code). */ | |
11075 | { | |
11076 | unsigned long mask = (mips_opts.micromips | |
11077 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11078 | ||
11079 | my_getExpression (&imm_expr, s); | |
11080 | check_absolute_expr (ip, &imm_expr); | |
11081 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11082 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11083 | mask, (unsigned long) imm_expr.X_add_number); | |
11084 | INSERT_OPERAND (mips_opts.micromips, | |
11085 | RS, *ip, imm_expr.X_add_number); | |
11086 | imm_expr.X_op = O_absent; | |
11087 | s = expr_end; | |
11088 | } | |
74cd071d CF |
11089 | continue; |
11090 | ||
90ecf173 | 11091 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11092 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11093 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11094 | { |
11095 | regno = s[3] - '0'; | |
11096 | s += 4; | |
03f66e8a | 11097 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11098 | continue; |
11099 | } | |
11100 | else | |
11101 | as_bad (_("Invalid dsp acc register")); | |
11102 | break; | |
11103 | ||
03f66e8a MR |
11104 | case '8': |
11105 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11106 | code) or 14 (for microMIPS code). */ | |
11107 | { | |
11108 | unsigned long mask = (mips_opts.micromips | |
11109 | ? MICROMIPSOP_MASK_WRDSP | |
11110 | : OP_MASK_WRDSP); | |
11111 | ||
11112 | my_getExpression (&imm_expr, s); | |
11113 | check_absolute_expr (ip, &imm_expr); | |
11114 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11115 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11116 | mask, (unsigned long) imm_expr.X_add_number); | |
11117 | INSERT_OPERAND (mips_opts.micromips, | |
11118 | WRDSP, *ip, imm_expr.X_add_number); | |
11119 | imm_expr.X_op = O_absent; | |
11120 | s = expr_end; | |
11121 | } | |
74cd071d CF |
11122 | continue; |
11123 | ||
90ecf173 | 11124 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11125 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11126 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11127 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11128 | { |
11129 | regno = s[3] - '0'; | |
11130 | s += 4; | |
df58fc94 | 11131 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11132 | continue; |
11133 | } | |
11134 | else | |
11135 | as_bad (_("Invalid dsp acc register")); | |
11136 | break; | |
11137 | ||
03f66e8a MR |
11138 | case '0': |
11139 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11140 | code) or 20 (for microMIPS code). */ | |
11141 | { | |
11142 | long mask = (mips_opts.micromips | |
11143 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11144 | ||
11145 | my_getExpression (&imm_expr, s); | |
11146 | check_absolute_expr (ip, &imm_expr); | |
11147 | min_range = -((mask + 1) >> 1); | |
11148 | max_range = ((mask + 1) >> 1) - 1; | |
11149 | if (imm_expr.X_add_number < min_range | |
11150 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11151 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11152 | (long) min_range, (long) max_range, | |
11153 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11154 | INSERT_OPERAND (mips_opts.micromips, |
11155 | DSPSFT, *ip, imm_expr.X_add_number); | |
11156 | imm_expr.X_op = O_absent; | |
11157 | s = expr_end; | |
11158 | } | |
74cd071d CF |
11159 | continue; |
11160 | ||
90ecf173 | 11161 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11162 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11163 | my_getExpression (&imm_expr, s); |
11164 | check_absolute_expr (ip, &imm_expr); | |
11165 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11166 | { | |
a9e24354 TS |
11167 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11168 | OP_MASK_RDDSP, | |
11169 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11170 | } |
df58fc94 | 11171 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11172 | imm_expr.X_op = O_absent; |
11173 | s = expr_end; | |
11174 | continue; | |
11175 | ||
90ecf173 | 11176 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11177 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11178 | my_getExpression (&imm_expr, s); |
11179 | check_absolute_expr (ip, &imm_expr); | |
11180 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11181 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11182 | if (imm_expr.X_add_number < min_range || | |
11183 | imm_expr.X_add_number > max_range) | |
11184 | { | |
a9e24354 TS |
11185 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11186 | (long) min_range, (long) max_range, | |
11187 | (long) imm_expr.X_add_number); | |
74cd071d | 11188 | } |
df58fc94 | 11189 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11190 | imm_expr.X_op = O_absent; |
11191 | s = expr_end; | |
11192 | continue; | |
11193 | ||
90ecf173 | 11194 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11195 | { |
11196 | long mask = (mips_opts.micromips | |
11197 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11198 | ||
11199 | my_getExpression (&imm_expr, s); | |
11200 | check_absolute_expr (ip, &imm_expr); | |
11201 | min_range = -((mask + 1) >> 1); | |
11202 | max_range = ((mask + 1) >> 1) - 1; | |
11203 | if (imm_expr.X_add_number < min_range | |
11204 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11205 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11206 | (long) min_range, (long) max_range, | |
11207 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11208 | INSERT_OPERAND (mips_opts.micromips, |
11209 | IMM10, *ip, imm_expr.X_add_number); | |
11210 | imm_expr.X_op = O_absent; | |
11211 | s = expr_end; | |
11212 | } | |
11213 | continue; | |
11214 | ||
11215 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11216 | gas_assert (mips_opts.micromips); | |
11217 | my_getExpression (&imm_expr, s); | |
11218 | check_absolute_expr (ip, &imm_expr); | |
11219 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11220 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11221 | MICROMIPSOP_MASK_RD, | |
11222 | (unsigned long) imm_expr.X_add_number); | |
11223 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11224 | imm_expr.X_op = O_absent; |
11225 | s = expr_end; | |
11226 | continue; | |
11227 | ||
a9e24354 | 11228 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11229 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11230 | my_getExpression (&imm_expr, s); |
11231 | check_absolute_expr (ip, &imm_expr); | |
11232 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11233 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11234 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11235 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11236 | imm_expr.X_op = O_absent; |
11237 | s = expr_end; | |
11238 | continue; | |
11239 | ||
a9e24354 | 11240 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11241 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11242 | my_getExpression (&imm_expr, s); |
11243 | check_absolute_expr (ip, &imm_expr); | |
11244 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11245 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11246 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11247 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11248 | imm_expr.X_op = O_absent; |
11249 | s = expr_end; | |
11250 | continue; | |
11251 | ||
90ecf173 | 11252 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11253 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11254 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11255 | s[3] >= '0' && s[3] <= '3') | |
11256 | { | |
11257 | regno = s[3] - '0'; | |
11258 | s += 4; | |
df58fc94 | 11259 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11260 | continue; |
11261 | } | |
11262 | else | |
11263 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11264 | break; | |
11265 | ||
90ecf173 | 11266 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11267 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11268 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11269 | s[3] >= '0' && s[3] <= '3') | |
11270 | { | |
11271 | regno = s[3] - '0'; | |
11272 | s += 4; | |
df58fc94 | 11273 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11274 | continue; |
11275 | } | |
11276 | else | |
11277 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11278 | break; | |
11279 | ||
dec0624d MR |
11280 | case '\\': /* 3-bit bit position. */ |
11281 | { | |
2906b037 MR |
11282 | unsigned long mask = (mips_opts.micromips |
11283 | ? MICROMIPSOP_MASK_3BITPOS | |
11284 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11285 | |
11286 | my_getExpression (&imm_expr, s); | |
11287 | check_absolute_expr (ip, &imm_expr); | |
11288 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11289 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11290 | ip->insn_mo->name, | |
11291 | mask, (unsigned long) imm_expr.X_add_number); | |
11292 | INSERT_OPERAND (mips_opts.micromips, | |
11293 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11294 | imm_expr.X_op = O_absent; | |
11295 | s = expr_end; | |
11296 | } | |
11297 | continue; | |
11298 | ||
252b5132 | 11299 | case ',': |
a339155f | 11300 | ++argnum; |
252b5132 RH |
11301 | if (*s++ == *args) |
11302 | continue; | |
11303 | s--; | |
11304 | switch (*++args) | |
11305 | { | |
11306 | case 'r': | |
11307 | case 'v': | |
df58fc94 | 11308 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11309 | continue; |
11310 | ||
11311 | case 'w': | |
df58fc94 | 11312 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11313 | continue; |
11314 | ||
252b5132 | 11315 | case 'W': |
df58fc94 RS |
11316 | gas_assert (!mips_opts.micromips); |
11317 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11318 | continue; |
11319 | ||
11320 | case 'V': | |
df58fc94 | 11321 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11322 | continue; |
11323 | } | |
11324 | break; | |
11325 | ||
11326 | case '(': | |
11327 | /* Handle optional base register. | |
11328 | Either the base register is omitted or | |
bdaaa2e1 | 11329 | we must have a left paren. */ |
252b5132 RH |
11330 | /* This is dependent on the next operand specifier |
11331 | is a base register specification. */ | |
df58fc94 RS |
11332 | gas_assert (args[1] == 'b' |
11333 | || (mips_opts.micromips | |
11334 | && args[1] == 'm' | |
11335 | && (args[2] == 'l' || args[2] == 'n' | |
11336 | || args[2] == 's' || args[2] == 'a'))); | |
11337 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11338 | return; |
df58fc94 | 11339 | /* Fall through. */ |
252b5132 | 11340 | |
90ecf173 | 11341 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11342 | if (*s++ == *args) |
11343 | continue; | |
11344 | break; | |
11345 | ||
11346 | case '[': /* These must match exactly. */ | |
60b63b72 | 11347 | case ']': |
df58fc94 | 11348 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11349 | if (*s++ == *args) |
11350 | continue; | |
11351 | break; | |
11352 | ||
af7ee8bf CD |
11353 | case '+': /* Opcode extension character. */ |
11354 | switch (*++args) | |
11355 | { | |
9bcd4f99 TS |
11356 | case '1': /* UDI immediates. */ |
11357 | case '2': | |
11358 | case '3': | |
11359 | case '4': | |
df58fc94 | 11360 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11361 | { |
11362 | const struct mips_immed *imm = mips_immed; | |
11363 | ||
11364 | while (imm->type && imm->type != *args) | |
11365 | ++imm; | |
11366 | if (! imm->type) | |
b37df7c4 | 11367 | abort (); |
9bcd4f99 TS |
11368 | my_getExpression (&imm_expr, s); |
11369 | check_absolute_expr (ip, &imm_expr); | |
11370 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11371 | { | |
11372 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11373 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11374 | (unsigned long) imm_expr.X_add_number, | |
11375 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11376 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11377 | } |
11378 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11379 | << imm->shift); | |
11380 | imm_expr.X_op = O_absent; | |
11381 | s = expr_end; | |
11382 | } | |
11383 | continue; | |
90ecf173 | 11384 | |
b015e599 AP |
11385 | case 'J': /* 10-bit hypcall code. */ |
11386 | gas_assert (!mips_opts.micromips); | |
11387 | { | |
11388 | unsigned long mask = OP_MASK_CODE10; | |
11389 | ||
11390 | my_getExpression (&imm_expr, s); | |
11391 | check_absolute_expr (ip, &imm_expr); | |
11392 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11393 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11394 | ip->insn_mo->name, | |
11395 | mask, (unsigned long) imm_expr.X_add_number); | |
11396 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11397 | imm_expr.X_op = O_absent; | |
11398 | s = expr_end; | |
11399 | } | |
11400 | continue; | |
11401 | ||
071742cf CD |
11402 | case 'A': /* ins/ext position, becomes LSB. */ |
11403 | limlo = 0; | |
11404 | limhi = 31; | |
5f74bc13 CD |
11405 | goto do_lsb; |
11406 | case 'E': | |
11407 | limlo = 32; | |
11408 | limhi = 63; | |
11409 | goto do_lsb; | |
90ecf173 | 11410 | do_lsb: |
071742cf CD |
11411 | my_getExpression (&imm_expr, s); |
11412 | check_absolute_expr (ip, &imm_expr); | |
11413 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11414 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11415 | { | |
11416 | as_bad (_("Improper position (%lu)"), | |
11417 | (unsigned long) imm_expr.X_add_number); | |
11418 | imm_expr.X_add_number = limlo; | |
11419 | } | |
11420 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11421 | INSERT_OPERAND (mips_opts.micromips, |
11422 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11423 | imm_expr.X_op = O_absent; |
11424 | s = expr_end; | |
11425 | continue; | |
11426 | ||
11427 | case 'B': /* ins size, becomes MSB. */ | |
11428 | limlo = 1; | |
11429 | limhi = 32; | |
5f74bc13 CD |
11430 | goto do_msb; |
11431 | case 'F': | |
11432 | limlo = 33; | |
11433 | limhi = 64; | |
11434 | goto do_msb; | |
90ecf173 | 11435 | do_msb: |
071742cf CD |
11436 | my_getExpression (&imm_expr, s); |
11437 | check_absolute_expr (ip, &imm_expr); | |
11438 | /* Check for negative input so that small negative numbers | |
11439 | will not succeed incorrectly. The checks against | |
11440 | (pos+size) transitively check "size" itself, | |
11441 | assuming that "pos" is reasonable. */ | |
11442 | if ((long) imm_expr.X_add_number < 0 | |
11443 | || ((unsigned long) imm_expr.X_add_number | |
11444 | + lastpos) < limlo | |
11445 | || ((unsigned long) imm_expr.X_add_number | |
11446 | + lastpos) > limhi) | |
11447 | { | |
11448 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11449 | (unsigned long) imm_expr.X_add_number, | |
11450 | (unsigned long) lastpos); | |
11451 | imm_expr.X_add_number = limlo - lastpos; | |
11452 | } | |
df58fc94 RS |
11453 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11454 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11455 | imm_expr.X_op = O_absent; |
11456 | s = expr_end; | |
11457 | continue; | |
11458 | ||
11459 | case 'C': /* ext size, becomes MSBD. */ | |
11460 | limlo = 1; | |
11461 | limhi = 32; | |
f02d8318 | 11462 | sizelo = 1; |
5f74bc13 CD |
11463 | goto do_msbd; |
11464 | case 'G': | |
11465 | limlo = 33; | |
11466 | limhi = 64; | |
f02d8318 | 11467 | sizelo = 33; |
5f74bc13 CD |
11468 | goto do_msbd; |
11469 | case 'H': | |
11470 | limlo = 33; | |
11471 | limhi = 64; | |
f02d8318 | 11472 | sizelo = 1; |
5f74bc13 | 11473 | goto do_msbd; |
90ecf173 | 11474 | do_msbd: |
071742cf CD |
11475 | my_getExpression (&imm_expr, s); |
11476 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11477 | /* The checks against (pos+size) don't transitively check |
11478 | "size" itself, assuming that "pos" is reasonable. | |
11479 | We also need to check the lower bound of "size". */ | |
11480 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11481 | || ((unsigned long) imm_expr.X_add_number |
11482 | + lastpos) < limlo | |
11483 | || ((unsigned long) imm_expr.X_add_number | |
11484 | + lastpos) > limhi) | |
11485 | { | |
11486 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11487 | (unsigned long) imm_expr.X_add_number, | |
11488 | (unsigned long) lastpos); | |
11489 | imm_expr.X_add_number = limlo - lastpos; | |
11490 | } | |
df58fc94 RS |
11491 | INSERT_OPERAND (mips_opts.micromips, |
11492 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11493 | imm_expr.X_op = O_absent; |
11494 | s = expr_end; | |
11495 | continue; | |
af7ee8bf | 11496 | |
bbcc0807 CD |
11497 | case 'D': |
11498 | /* +D is for disassembly only; never match. */ | |
11499 | break; | |
11500 | ||
5f74bc13 CD |
11501 | case 'I': |
11502 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11503 | my_getExpression (&imm2_expr, s); | |
11504 | if (imm2_expr.X_op != O_big | |
11505 | && imm2_expr.X_op != O_constant) | |
11506 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11507 | if (HAVE_32BIT_GPRS) |
11508 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11509 | s = expr_end; |
11510 | continue; | |
11511 | ||
707bfff6 | 11512 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11513 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11514 | /* +T is for disassembly only; never match. */ |
11515 | break; | |
11516 | ||
707bfff6 | 11517 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11518 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11519 | if (s[0] == '$' && ISDIGIT (s[1])) |
11520 | { | |
11521 | ++s; | |
11522 | regno = 0; | |
11523 | do | |
11524 | { | |
11525 | regno *= 10; | |
11526 | regno += *s - '0'; | |
11527 | ++s; | |
11528 | } | |
11529 | while (ISDIGIT (*s)); | |
11530 | if (regno > 31) | |
11531 | as_bad (_("Invalid register number (%d)"), regno); | |
11532 | else | |
11533 | { | |
df58fc94 | 11534 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11535 | continue; |
11536 | } | |
11537 | } | |
11538 | else | |
11539 | as_bad (_("Invalid coprocessor 0 register number")); | |
11540 | break; | |
11541 | ||
bb35fb24 NC |
11542 | case 'x': |
11543 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11544 | is not in the valid range. */ | |
df58fc94 | 11545 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11546 | my_getExpression (&imm_expr, s); |
11547 | check_absolute_expr (ip, &imm_expr); | |
11548 | if ((unsigned) imm_expr.X_add_number > 31) | |
11549 | { | |
11550 | as_bad (_("Improper bit index (%lu)"), | |
11551 | (unsigned long) imm_expr.X_add_number); | |
11552 | imm_expr.X_add_number = 0; | |
11553 | } | |
df58fc94 | 11554 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11555 | imm_expr.X_op = O_absent; |
11556 | s = expr_end; | |
11557 | continue; | |
11558 | ||
11559 | case 'X': | |
11560 | /* bbit[01] bit index when bbit is used but we generate | |
11561 | bbit[01]32 because the index is over 32. Move to the | |
11562 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11563 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11564 | my_getExpression (&imm_expr, s); |
11565 | check_absolute_expr (ip, &imm_expr); | |
11566 | if ((unsigned) imm_expr.X_add_number < 32 | |
11567 | || (unsigned) imm_expr.X_add_number > 63) | |
11568 | break; | |
df58fc94 | 11569 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11570 | imm_expr.X_op = O_absent; |
11571 | s = expr_end; | |
11572 | continue; | |
11573 | ||
11574 | case 'p': | |
11575 | /* cins, cins32, exts and exts32 position field. Give error | |
11576 | if it's not in the valid range. */ | |
df58fc94 | 11577 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11578 | my_getExpression (&imm_expr, s); |
11579 | check_absolute_expr (ip, &imm_expr); | |
11580 | if ((unsigned) imm_expr.X_add_number > 31) | |
11581 | { | |
11582 | as_bad (_("Improper position (%lu)"), | |
11583 | (unsigned long) imm_expr.X_add_number); | |
11584 | imm_expr.X_add_number = 0; | |
11585 | } | |
11586 | /* Make the pos explicit to simplify +S. */ | |
11587 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11588 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11589 | imm_expr.X_op = O_absent; |
11590 | s = expr_end; | |
11591 | continue; | |
11592 | ||
11593 | case 'P': | |
11594 | /* cins, cins32, exts and exts32 position field. Move to | |
11595 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11596 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11597 | my_getExpression (&imm_expr, s); |
11598 | check_absolute_expr (ip, &imm_expr); | |
11599 | if ((unsigned) imm_expr.X_add_number < 32 | |
11600 | || (unsigned) imm_expr.X_add_number > 63) | |
11601 | break; | |
11602 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11603 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11604 | imm_expr.X_op = O_absent; |
11605 | s = expr_end; | |
11606 | continue; | |
11607 | ||
11608 | case 's': | |
11609 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11610 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11611 | my_getExpression (&imm_expr, s); |
11612 | check_absolute_expr (ip, &imm_expr); | |
11613 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11614 | { | |
11615 | as_bad (_("Improper size (%lu)"), | |
11616 | (unsigned long) imm_expr.X_add_number); | |
11617 | imm_expr.X_add_number = 0; | |
11618 | } | |
df58fc94 | 11619 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11620 | imm_expr.X_op = O_absent; |
11621 | s = expr_end; | |
11622 | continue; | |
11623 | ||
11624 | case 'S': | |
11625 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11626 | length-minus-one field. */ | |
df58fc94 | 11627 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11628 | my_getExpression (&imm_expr, s); |
11629 | check_absolute_expr (ip, &imm_expr); | |
11630 | if ((long) imm_expr.X_add_number < 0 | |
11631 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11632 | { | |
11633 | as_bad (_("Improper size (%lu)"), | |
11634 | (unsigned long) imm_expr.X_add_number); | |
11635 | imm_expr.X_add_number = 0; | |
11636 | } | |
df58fc94 | 11637 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11638 | imm_expr.X_op = O_absent; |
11639 | s = expr_end; | |
11640 | continue; | |
11641 | ||
dd3cbb7e NC |
11642 | case 'Q': |
11643 | /* seqi/snei immediate field. */ | |
df58fc94 | 11644 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11645 | my_getExpression (&imm_expr, s); |
11646 | check_absolute_expr (ip, &imm_expr); | |
11647 | if ((long) imm_expr.X_add_number < -512 | |
11648 | || (long) imm_expr.X_add_number >= 512) | |
11649 | { | |
11650 | as_bad (_("Improper immediate (%ld)"), | |
11651 | (long) imm_expr.X_add_number); | |
11652 | imm_expr.X_add_number = 0; | |
11653 | } | |
df58fc94 | 11654 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11655 | imm_expr.X_op = O_absent; |
11656 | s = expr_end; | |
11657 | continue; | |
11658 | ||
98675402 | 11659 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11660 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11661 | my_getExpression (&imm_expr, s); |
11662 | check_absolute_expr (ip, &imm_expr); | |
11663 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11664 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11665 | if (imm_expr.X_add_number < min_range | |
11666 | || imm_expr.X_add_number > max_range) | |
11667 | { | |
c95354ed | 11668 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11669 | (long) min_range, (long) max_range, |
11670 | (long) imm_expr.X_add_number); | |
11671 | } | |
df58fc94 | 11672 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11673 | imm_expr.X_op = O_absent; |
11674 | s = expr_end; | |
11675 | continue; | |
11676 | ||
11677 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11678 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11679 | my_getExpression (&imm_expr, s); |
11680 | check_absolute_expr (ip, &imm_expr); | |
11681 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11682 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11683 | if (imm_expr.X_add_number < min_range | |
11684 | || imm_expr.X_add_number > max_range) | |
11685 | { | |
c95354ed | 11686 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11687 | (long) min_range, (long) max_range, |
11688 | (long) imm_expr.X_add_number); | |
11689 | } | |
df58fc94 | 11690 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11691 | imm_expr.X_op = O_absent; |
11692 | s = expr_end; | |
11693 | continue; | |
11694 | ||
11695 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11696 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11697 | my_getExpression (&imm_expr, s); |
11698 | check_absolute_expr (ip, &imm_expr); | |
11699 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11700 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11701 | /* We check the offset range before adjusted. */ |
11702 | min_range <<= 4; | |
11703 | max_range <<= 4; | |
98675402 RS |
11704 | if (imm_expr.X_add_number < min_range |
11705 | || imm_expr.X_add_number > max_range) | |
11706 | { | |
c95354ed | 11707 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11708 | (long) min_range, (long) max_range, |
11709 | (long) imm_expr.X_add_number); | |
11710 | } | |
c95354ed MX |
11711 | if (imm_expr.X_add_number & 0xf) |
11712 | { | |
11713 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11714 | (long) imm_expr.X_add_number); | |
11715 | } | |
11716 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11717 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11718 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11719 | imm_expr.X_op = O_absent; |
11720 | s = expr_end; | |
11721 | continue; | |
11722 | ||
11723 | case 'z': | |
df58fc94 | 11724 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11725 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11726 | break; | |
11727 | if (regno == AT && mips_opts.at) | |
11728 | { | |
11729 | if (mips_opts.at == ATREG) | |
11730 | as_warn (_("used $at without \".set noat\"")); | |
11731 | else | |
11732 | as_warn (_("used $%u with \".set at=$%u\""), | |
11733 | regno, mips_opts.at); | |
11734 | } | |
df58fc94 | 11735 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11736 | continue; |
11737 | ||
11738 | case 'Z': | |
df58fc94 | 11739 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11740 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11741 | break; | |
df58fc94 | 11742 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11743 | continue; |
11744 | ||
af7ee8bf | 11745 | default: |
df58fc94 | 11746 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11747 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11748 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11749 | *args, insn->name, insn->args); |
af7ee8bf CD |
11750 | /* Further processing is fruitless. */ |
11751 | return; | |
11752 | } | |
11753 | break; | |
11754 | ||
df58fc94 | 11755 | case '.': /* 10-bit offset. */ |
df58fc94 | 11756 | gas_assert (mips_opts.micromips); |
dec0624d | 11757 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11758 | { |
11759 | int shift = *args == '.' ? 9 : 11; | |
11760 | size_t i; | |
11761 | ||
11762 | /* Check whether there is only a single bracketed expression | |
11763 | left. If so, it must be the base register and the | |
11764 | constant must be zero. */ | |
11765 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11766 | continue; | |
11767 | ||
11768 | /* If this value won't fit into the offset, then go find | |
11769 | a macro that will generate a 16- or 32-bit offset code | |
11770 | pattern. */ | |
11771 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11772 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11773 | || imm_expr.X_add_number >= 1 << shift | |
11774 | || imm_expr.X_add_number < -1 << shift)) | |
11775 | || i > 0) | |
11776 | { | |
11777 | imm_expr.X_op = O_absent; | |
11778 | break; | |
11779 | } | |
11780 | if (shift == 9) | |
11781 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11782 | else | |
dec0624d MR |
11783 | INSERT_OPERAND (mips_opts.micromips, |
11784 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11785 | imm_expr.X_op = O_absent; |
11786 | s = expr_end; | |
11787 | } | |
11788 | continue; | |
11789 | ||
252b5132 RH |
11790 | case '<': /* must be at least one digit */ |
11791 | /* | |
11792 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11793 | * than 31 or less than 0, then the shift amount should be |
11794 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11795 | * We issue a warning and mask out all but the low 5 bits. |
11796 | */ | |
11797 | my_getExpression (&imm_expr, s); | |
11798 | check_absolute_expr (ip, &imm_expr); | |
11799 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11800 | as_warn (_("Improper shift amount (%lu)"), |
11801 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11802 | INSERT_OPERAND (mips_opts.micromips, |
11803 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11804 | imm_expr.X_op = O_absent; |
11805 | s = expr_end; | |
11806 | continue; | |
11807 | ||
11808 | case '>': /* shift amount minus 32 */ | |
11809 | my_getExpression (&imm_expr, s); | |
11810 | check_absolute_expr (ip, &imm_expr); | |
11811 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11812 | || (unsigned long) imm_expr.X_add_number > 63) | |
11813 | break; | |
df58fc94 RS |
11814 | INSERT_OPERAND (mips_opts.micromips, |
11815 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11816 | imm_expr.X_op = O_absent; |
11817 | s = expr_end; | |
11818 | continue; | |
11819 | ||
90ecf173 MR |
11820 | case 'k': /* CACHE code. */ |
11821 | case 'h': /* PREFX code. */ | |
11822 | case '1': /* SYNC type. */ | |
252b5132 RH |
11823 | my_getExpression (&imm_expr, s); |
11824 | check_absolute_expr (ip, &imm_expr); | |
11825 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11826 | as_warn (_("Invalid value for `%s' (%lu)"), |
11827 | ip->insn_mo->name, | |
11828 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11829 | switch (*args) |
d954098f | 11830 | { |
df58fc94 RS |
11831 | case 'k': |
11832 | if (mips_fix_cn63xxp1 | |
11833 | && !mips_opts.micromips | |
11834 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11835 | switch (imm_expr.X_add_number) |
11836 | { | |
11837 | case 5: | |
11838 | case 25: | |
11839 | case 26: | |
11840 | case 27: | |
11841 | case 28: | |
11842 | case 29: | |
11843 | case 30: | |
11844 | case 31: /* These are ok. */ | |
11845 | break; | |
11846 | ||
11847 | default: /* The rest must be changed to 28. */ | |
11848 | imm_expr.X_add_number = 28; | |
11849 | break; | |
11850 | } | |
df58fc94 RS |
11851 | INSERT_OPERAND (mips_opts.micromips, |
11852 | CACHE, *ip, imm_expr.X_add_number); | |
11853 | break; | |
11854 | case 'h': | |
11855 | INSERT_OPERAND (mips_opts.micromips, | |
11856 | PREFX, *ip, imm_expr.X_add_number); | |
11857 | break; | |
11858 | case '1': | |
11859 | INSERT_OPERAND (mips_opts.micromips, | |
11860 | STYPE, *ip, imm_expr.X_add_number); | |
11861 | break; | |
d954098f | 11862 | } |
252b5132 RH |
11863 | imm_expr.X_op = O_absent; |
11864 | s = expr_end; | |
11865 | continue; | |
11866 | ||
90ecf173 | 11867 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11868 | { |
11869 | unsigned long mask = (mips_opts.micromips | |
11870 | ? MICROMIPSOP_MASK_CODE | |
11871 | : OP_MASK_CODE); | |
11872 | ||
11873 | my_getExpression (&imm_expr, s); | |
11874 | check_absolute_expr (ip, &imm_expr); | |
11875 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11876 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11877 | ip->insn_mo->name, | |
11878 | mask, (unsigned long) imm_expr.X_add_number); | |
11879 | INSERT_OPERAND (mips_opts.micromips, | |
11880 | CODE, *ip, imm_expr.X_add_number); | |
11881 | imm_expr.X_op = O_absent; | |
11882 | s = expr_end; | |
11883 | } | |
252b5132 RH |
11884 | continue; |
11885 | ||
90ecf173 | 11886 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11887 | { |
11888 | unsigned long mask = (mips_opts.micromips | |
11889 | ? MICROMIPSOP_MASK_CODE2 | |
11890 | : OP_MASK_CODE2); | |
11891 | ||
11892 | my_getExpression (&imm_expr, s); | |
11893 | check_absolute_expr (ip, &imm_expr); | |
11894 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11895 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11896 | ip->insn_mo->name, | |
11897 | mask, (unsigned long) imm_expr.X_add_number); | |
11898 | INSERT_OPERAND (mips_opts.micromips, | |
11899 | CODE2, *ip, imm_expr.X_add_number); | |
11900 | imm_expr.X_op = O_absent; | |
11901 | s = expr_end; | |
11902 | } | |
252b5132 RH |
11903 | continue; |
11904 | ||
df58fc94 RS |
11905 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11906 | { | |
11907 | unsigned long mask = (mips_opts.micromips | |
11908 | ? MICROMIPSOP_MASK_CODE10 | |
11909 | : OP_MASK_CODE20); | |
11910 | ||
11911 | my_getExpression (&imm_expr, s); | |
11912 | check_absolute_expr (ip, &imm_expr); | |
11913 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11914 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11915 | ip->insn_mo->name, | |
11916 | mask, (unsigned long) imm_expr.X_add_number); | |
11917 | if (mips_opts.micromips) | |
11918 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11919 | else | |
11920 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11921 | imm_expr.X_op = O_absent; | |
11922 | s = expr_end; | |
11923 | } | |
252b5132 RH |
11924 | continue; |
11925 | ||
df58fc94 RS |
11926 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11927 | { | |
11928 | unsigned long mask = (mips_opts.micromips | |
11929 | ? MICROMIPSOP_MASK_COPZ | |
11930 | : OP_MASK_COPZ); | |
11931 | ||
11932 | my_getExpression (&imm_expr, s); | |
11933 | check_absolute_expr (ip, &imm_expr); | |
11934 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11935 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11936 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11937 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11938 | INSERT_OPERAND (mips_opts.micromips, |
11939 | COPZ, *ip, imm_expr.X_add_number); | |
11940 | imm_expr.X_op = O_absent; | |
11941 | s = expr_end; | |
11942 | } | |
beae10d5 | 11943 | continue; |
252b5132 | 11944 | |
df58fc94 RS |
11945 | case 'J': /* 19-bit WAIT code. */ |
11946 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11947 | my_getExpression (&imm_expr, s); |
11948 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11949 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11950 | { |
11951 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11952 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11953 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11954 | } | |
11955 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11956 | imm_expr.X_op = O_absent; |
11957 | s = expr_end; | |
11958 | continue; | |
11959 | ||
707bfff6 | 11960 | case 'P': /* Performance register. */ |
df58fc94 | 11961 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11962 | my_getExpression (&imm_expr, s); |
252b5132 | 11963 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11964 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11965 | as_warn (_("Invalid performance register (%lu)"), |
11966 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
11967 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
11968 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
11969 | as_warn (_("Invalid performance register (%lu)"), | |
11970 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11971 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11972 | imm_expr.X_op = O_absent; |
11973 | s = expr_end; | |
11974 | continue; | |
252b5132 | 11975 | |
707bfff6 | 11976 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11977 | { |
11978 | unsigned long opcode = ip->insn_opcode; | |
11979 | unsigned long mask; | |
11980 | unsigned int types; | |
11981 | int cop0; | |
11982 | ||
11983 | if (mips_opts.micromips) | |
11984 | { | |
11985 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11986 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11987 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11988 | opcode &= mask; | |
11989 | switch (opcode) | |
11990 | { | |
11991 | case 0x000000fc: /* mfc0 */ | |
11992 | case 0x000002fc: /* mtc0 */ | |
11993 | case 0x580000fc: /* dmfc0 */ | |
11994 | case 0x580002fc: /* dmtc0 */ | |
11995 | cop0 = 1; | |
11996 | break; | |
11997 | default: | |
11998 | cop0 = 0; | |
11999 | break; | |
12000 | } | |
12001 | } | |
12002 | else | |
12003 | { | |
12004 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12005 | cop0 = opcode == OP_OP_COP0; | |
12006 | } | |
12007 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12008 | ok = reg_lookup (&s, types, ®no); | |
12009 | if (mips_opts.micromips) | |
12010 | INSERT_OPERAND (1, RS, *ip, regno); | |
12011 | else | |
12012 | INSERT_OPERAND (0, RD, *ip, regno); | |
12013 | if (ok) | |
12014 | { | |
12015 | lastregno = regno; | |
12016 | continue; | |
12017 | } | |
12018 | } | |
12019 | break; | |
707bfff6 | 12020 | |
df58fc94 RS |
12021 | case 'y': /* ALNV.PS source register. */ |
12022 | gas_assert (mips_opts.micromips); | |
12023 | goto do_reg; | |
12024 | case 'x': /* Ignore register name. */ | |
12025 | case 'U': /* Destination register (CLO/CLZ). */ | |
12026 | case 'g': /* Coprocessor destination register. */ | |
12027 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12028 | case 'b': /* Base register. */ |
12029 | case 'd': /* Destination register. */ | |
12030 | case 's': /* Source register. */ | |
12031 | case 't': /* Target register. */ | |
12032 | case 'r': /* Both target and source. */ | |
12033 | case 'v': /* Both dest and source. */ | |
12034 | case 'w': /* Both dest and target. */ | |
12035 | case 'E': /* Coprocessor target register. */ | |
12036 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12037 | case 'z': /* Must be zero register. */ |
df58fc94 | 12038 | do_reg: |
90ecf173 | 12039 | s_reset = s; |
707bfff6 TS |
12040 | if (*args == 'E' || *args == 'K') |
12041 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12042 | else | |
12043 | { | |
12044 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12045 | if (regno == AT && mips_opts.at) |
12046 | { | |
12047 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12048 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12049 | else |
f71d0d44 | 12050 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12051 | regno, mips_opts.at); |
12052 | } | |
707bfff6 TS |
12053 | } |
12054 | if (ok) | |
252b5132 | 12055 | { |
252b5132 RH |
12056 | c = *args; |
12057 | if (*s == ' ') | |
f9419b05 | 12058 | ++s; |
252b5132 RH |
12059 | if (args[1] != *s) |
12060 | { | |
12061 | if (c == 'r' || c == 'v' || c == 'w') | |
12062 | { | |
12063 | regno = lastregno; | |
12064 | s = s_reset; | |
f9419b05 | 12065 | ++args; |
252b5132 RH |
12066 | } |
12067 | } | |
12068 | /* 'z' only matches $0. */ | |
12069 | if (c == 'z' && regno != 0) | |
12070 | break; | |
12071 | ||
24864476 | 12072 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12073 | { |
12074 | if (regno == lastregno) | |
90ecf173 MR |
12075 | { |
12076 | insn_error | |
f71d0d44 | 12077 | = _("Source and destination must be different"); |
e7c604dd | 12078 | continue; |
90ecf173 | 12079 | } |
24864476 | 12080 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12081 | { |
12082 | insn_error | |
f71d0d44 | 12083 | = _("A destination register must be supplied"); |
e7c604dd | 12084 | continue; |
90ecf173 | 12085 | } |
e7c604dd | 12086 | } |
90ecf173 MR |
12087 | /* Now that we have assembled one operand, we use the args |
12088 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12089 | switch (c) |
12090 | { | |
12091 | case 'r': | |
12092 | case 's': | |
12093 | case 'v': | |
12094 | case 'b': | |
df58fc94 | 12095 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12096 | break; |
df58fc94 | 12097 | |
af7ee8bf | 12098 | case 'K': |
df58fc94 RS |
12099 | if (mips_opts.micromips) |
12100 | INSERT_OPERAND (1, RS, *ip, regno); | |
12101 | else | |
12102 | INSERT_OPERAND (0, RD, *ip, regno); | |
12103 | break; | |
12104 | ||
12105 | case 'd': | |
ef2e4d86 | 12106 | case 'g': |
df58fc94 | 12107 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12108 | break; |
df58fc94 | 12109 | |
4372b673 | 12110 | case 'U': |
df58fc94 RS |
12111 | gas_assert (!mips_opts.micromips); |
12112 | INSERT_OPERAND (0, RD, *ip, regno); | |
12113 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12114 | break; |
df58fc94 | 12115 | |
252b5132 RH |
12116 | case 'w': |
12117 | case 't': | |
12118 | case 'E': | |
df58fc94 RS |
12119 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12120 | break; | |
12121 | ||
12122 | case 'y': | |
12123 | gas_assert (mips_opts.micromips); | |
12124 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12125 | break; |
df58fc94 | 12126 | |
252b5132 RH |
12127 | case 'x': |
12128 | /* This case exists because on the r3000 trunc | |
12129 | expands into a macro which requires a gp | |
12130 | register. On the r6000 or r4000 it is | |
12131 | assembled into a single instruction which | |
12132 | ignores the register. Thus the insn version | |
12133 | is MIPS_ISA2 and uses 'x', and the macro | |
12134 | version is MIPS_ISA1 and uses 't'. */ | |
12135 | break; | |
df58fc94 | 12136 | |
252b5132 RH |
12137 | case 'z': |
12138 | /* This case is for the div instruction, which | |
12139 | acts differently if the destination argument | |
12140 | is $0. This only matches $0, and is checked | |
12141 | outside the switch. */ | |
12142 | break; | |
252b5132 RH |
12143 | } |
12144 | lastregno = regno; | |
12145 | continue; | |
12146 | } | |
252b5132 RH |
12147 | switch (*args++) |
12148 | { | |
12149 | case 'r': | |
12150 | case 'v': | |
df58fc94 | 12151 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12152 | continue; |
df58fc94 | 12153 | |
252b5132 | 12154 | case 'w': |
df58fc94 | 12155 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12156 | continue; |
12157 | } | |
12158 | break; | |
12159 | ||
deec1734 | 12160 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12161 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12162 | my_getExpression (&imm_expr, s); |
12163 | check_absolute_expr (ip, &imm_expr); | |
12164 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12165 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12166 | (long) imm_expr.X_add_number); |
df58fc94 | 12167 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12168 | imm_expr.X_op = O_absent; |
12169 | s = expr_end; | |
12170 | continue; | |
12171 | ||
12172 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12173 | if (s[0] != '$') | |
12174 | { | |
12175 | /* MDMX Immediate. */ | |
df58fc94 | 12176 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12177 | my_getExpression (&imm_expr, s); |
12178 | check_absolute_expr (ip, &imm_expr); | |
12179 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12180 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12181 | (long) imm_expr.X_add_number); | |
df58fc94 | 12182 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12183 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12184 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12185 | else | |
12186 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12187 | imm_expr.X_op = O_absent; |
12188 | s = expr_end; | |
12189 | continue; | |
12190 | } | |
12191 | /* Not MDMX Immediate. Fall through. */ | |
12192 | case 'X': /* MDMX destination register. */ | |
12193 | case 'Y': /* MDMX source register. */ | |
12194 | case 'Z': /* MDMX target register. */ | |
12195 | is_mdmx = 1; | |
df58fc94 RS |
12196 | case 'W': |
12197 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12198 | case 'D': /* Floating point destination register. */ |
12199 | case 'S': /* Floating point source register. */ | |
12200 | case 'T': /* Floating point target register. */ | |
12201 | case 'R': /* Floating point source register. */ | |
252b5132 | 12202 | case 'V': |
707bfff6 TS |
12203 | rtype = RTYPE_FPU; |
12204 | if (is_mdmx | |
12205 | || (mips_opts.ase_mdmx | |
12206 | && (ip->insn_mo->pinfo & FP_D) | |
12207 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12208 | | INSN_COPROC_MEMORY_DELAY | |
12209 | | INSN_LOAD_COPROC_DELAY | |
12210 | | INSN_LOAD_MEMORY_DELAY | |
12211 | | INSN_STORE_MEMORY)))) | |
12212 | rtype |= RTYPE_VEC; | |
252b5132 | 12213 | s_reset = s; |
707bfff6 | 12214 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12215 | { |
252b5132 | 12216 | if ((regno & 1) != 0 |
ca4e0257 | 12217 | && HAVE_32BIT_FPRS |
90ecf173 | 12218 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12219 | as_warn (_("Float register should be even, was %d"), |
12220 | regno); | |
12221 | ||
12222 | c = *args; | |
12223 | if (*s == ' ') | |
f9419b05 | 12224 | ++s; |
252b5132 RH |
12225 | if (args[1] != *s) |
12226 | { | |
12227 | if (c == 'V' || c == 'W') | |
12228 | { | |
12229 | regno = lastregno; | |
12230 | s = s_reset; | |
f9419b05 | 12231 | ++args; |
252b5132 RH |
12232 | } |
12233 | } | |
12234 | switch (c) | |
12235 | { | |
12236 | case 'D': | |
deec1734 | 12237 | case 'X': |
df58fc94 | 12238 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12239 | break; |
df58fc94 | 12240 | |
252b5132 RH |
12241 | case 'V': |
12242 | case 'S': | |
deec1734 | 12243 | case 'Y': |
df58fc94 | 12244 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12245 | break; |
df58fc94 | 12246 | |
deec1734 CD |
12247 | case 'Q': |
12248 | /* This is like 'Z', but also needs to fix the MDMX | |
12249 | vector/scalar select bits. Note that the | |
12250 | scalar immediate case is handled above. */ | |
12251 | if (*s == '[') | |
12252 | { | |
12253 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12254 | int max_el = (is_qh ? 3 : 7); | |
12255 | s++; | |
12256 | my_getExpression(&imm_expr, s); | |
12257 | check_absolute_expr (ip, &imm_expr); | |
12258 | s = expr_end; | |
12259 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12260 | as_bad (_("Bad element selector %ld"), |
12261 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12262 | imm_expr.X_add_number &= max_el; |
12263 | ip->insn_opcode |= (imm_expr.X_add_number | |
12264 | << (OP_SH_VSEL + | |
12265 | (is_qh ? 2 : 1))); | |
01a3f561 | 12266 | imm_expr.X_op = O_absent; |
deec1734 | 12267 | if (*s != ']') |
20203fb9 | 12268 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12269 | else |
12270 | s++; | |
12271 | } | |
12272 | else | |
12273 | { | |
12274 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12275 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12276 | << OP_SH_VSEL); | |
12277 | else | |
12278 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12279 | OP_SH_VSEL); | |
12280 | } | |
90ecf173 | 12281 | /* Fall through. */ |
252b5132 RH |
12282 | case 'W': |
12283 | case 'T': | |
deec1734 | 12284 | case 'Z': |
df58fc94 | 12285 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12286 | break; |
df58fc94 | 12287 | |
252b5132 | 12288 | case 'R': |
df58fc94 | 12289 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12290 | break; |
12291 | } | |
12292 | lastregno = regno; | |
12293 | continue; | |
12294 | } | |
12295 | ||
252b5132 RH |
12296 | switch (*args++) |
12297 | { | |
12298 | case 'V': | |
df58fc94 | 12299 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12300 | continue; |
df58fc94 | 12301 | |
252b5132 | 12302 | case 'W': |
df58fc94 | 12303 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12304 | continue; |
12305 | } | |
12306 | break; | |
12307 | ||
12308 | case 'I': | |
12309 | my_getExpression (&imm_expr, s); | |
12310 | if (imm_expr.X_op != O_big | |
12311 | && imm_expr.X_op != O_constant) | |
12312 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12313 | if (HAVE_32BIT_GPRS) |
12314 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12315 | s = expr_end; |
12316 | continue; | |
12317 | ||
12318 | case 'A': | |
12319 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12320 | normalize_address_expr (&offset_expr); |
f6688943 | 12321 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12322 | s = expr_end; |
12323 | continue; | |
12324 | ||
12325 | case 'F': | |
12326 | case 'L': | |
12327 | case 'f': | |
12328 | case 'l': | |
12329 | { | |
12330 | int f64; | |
ca4e0257 | 12331 | int using_gprs; |
252b5132 RH |
12332 | char *save_in; |
12333 | char *err; | |
12334 | unsigned char temp[8]; | |
12335 | int len; | |
12336 | unsigned int length; | |
12337 | segT seg; | |
12338 | subsegT subseg; | |
12339 | char *p; | |
12340 | ||
12341 | /* These only appear as the last operand in an | |
12342 | instruction, and every instruction that accepts | |
12343 | them in any variant accepts them in all variants. | |
12344 | This means we don't have to worry about backing out | |
12345 | any changes if the instruction does not match. | |
12346 | ||
12347 | The difference between them is the size of the | |
12348 | floating point constant and where it goes. For 'F' | |
12349 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12350 | is 32 bits. Where the constant is placed is based | |
12351 | on how the MIPS assembler does things: | |
12352 | F -- .rdata | |
12353 | L -- .lit8 | |
12354 | f -- immediate value | |
12355 | l -- .lit4 | |
12356 | ||
12357 | The .lit4 and .lit8 sections are only used if | |
12358 | permitted by the -G argument. | |
12359 | ||
ca4e0257 RS |
12360 | The code below needs to know whether the target register |
12361 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12362 | 'F' are used with GPR-based instructions and 'l' and | |
12363 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12364 | |
12365 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12366 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12367 | |
12368 | save_in = input_line_pointer; | |
12369 | input_line_pointer = s; | |
12370 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12371 | length = len; | |
12372 | s = input_line_pointer; | |
12373 | input_line_pointer = save_in; | |
12374 | if (err != NULL && *err != '\0') | |
12375 | { | |
12376 | as_bad (_("Bad floating point constant: %s"), err); | |
12377 | memset (temp, '\0', sizeof temp); | |
12378 | length = f64 ? 8 : 4; | |
12379 | } | |
12380 | ||
9c2799c2 | 12381 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12382 | |
12383 | if (*args == 'f' | |
12384 | || (*args == 'l' | |
3e722fb5 | 12385 | && (g_switch_value < 4 |
252b5132 RH |
12386 | || (temp[0] == 0 && temp[1] == 0) |
12387 | || (temp[2] == 0 && temp[3] == 0)))) | |
12388 | { | |
12389 | imm_expr.X_op = O_constant; | |
90ecf173 | 12390 | if (!target_big_endian) |
252b5132 RH |
12391 | imm_expr.X_add_number = bfd_getl32 (temp); |
12392 | else | |
12393 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12394 | } | |
12395 | else if (length > 4 | |
90ecf173 | 12396 | && !mips_disable_float_construction |
ca4e0257 RS |
12397 | /* Constants can only be constructed in GPRs and |
12398 | copied to FPRs if the GPRs are at least as wide | |
12399 | as the FPRs. Force the constant into memory if | |
12400 | we are using 64-bit FPRs but the GPRs are only | |
12401 | 32 bits wide. */ | |
12402 | && (using_gprs | |
90ecf173 | 12403 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12404 | && ((temp[0] == 0 && temp[1] == 0) |
12405 | || (temp[2] == 0 && temp[3] == 0)) | |
12406 | && ((temp[4] == 0 && temp[5] == 0) | |
12407 | || (temp[6] == 0 && temp[7] == 0))) | |
12408 | { | |
ca4e0257 | 12409 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12410 | instructions. If using 32-bit registers, set |
12411 | imm_expr to the high order 32 bits and offset_expr to | |
12412 | the low order 32 bits. Otherwise, set imm_expr to | |
12413 | the entire 64 bit constant. */ | |
ca4e0257 | 12414 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12415 | { |
12416 | imm_expr.X_op = O_constant; | |
12417 | offset_expr.X_op = O_constant; | |
90ecf173 | 12418 | if (!target_big_endian) |
252b5132 RH |
12419 | { |
12420 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12421 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12422 | } | |
12423 | else | |
12424 | { | |
12425 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12426 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12427 | } | |
12428 | if (offset_expr.X_add_number == 0) | |
12429 | offset_expr.X_op = O_absent; | |
12430 | } | |
12431 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12432 | { | |
12433 | imm_expr.X_op = O_constant; | |
90ecf173 | 12434 | if (!target_big_endian) |
252b5132 RH |
12435 | imm_expr.X_add_number = bfd_getl64 (temp); |
12436 | else | |
12437 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12438 | } | |
12439 | else | |
12440 | { | |
12441 | imm_expr.X_op = O_big; | |
12442 | imm_expr.X_add_number = 4; | |
90ecf173 | 12443 | if (!target_big_endian) |
252b5132 RH |
12444 | { |
12445 | generic_bignum[0] = bfd_getl16 (temp); | |
12446 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12447 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12448 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12449 | } | |
12450 | else | |
12451 | { | |
12452 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12453 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12454 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12455 | generic_bignum[3] = bfd_getb16 (temp); | |
12456 | } | |
12457 | } | |
12458 | } | |
12459 | else | |
12460 | { | |
12461 | const char *newname; | |
12462 | segT new_seg; | |
12463 | ||
12464 | /* Switch to the right section. */ | |
12465 | seg = now_seg; | |
12466 | subseg = now_subseg; | |
12467 | switch (*args) | |
12468 | { | |
12469 | default: /* unused default case avoids warnings. */ | |
12470 | case 'L': | |
12471 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12472 | if (g_switch_value >= 8) |
252b5132 RH |
12473 | newname = ".lit8"; |
12474 | break; | |
12475 | case 'F': | |
3e722fb5 | 12476 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12477 | break; |
12478 | case 'l': | |
9c2799c2 | 12479 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12480 | newname = ".lit4"; |
12481 | break; | |
12482 | } | |
12483 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12484 | if (IS_ELF) |
252b5132 RH |
12485 | bfd_set_section_flags (stdoutput, new_seg, |
12486 | (SEC_ALLOC | |
12487 | | SEC_LOAD | |
12488 | | SEC_READONLY | |
12489 | | SEC_DATA)); | |
12490 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12491 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12492 | record_alignment (new_seg, 4); |
12493 | else | |
12494 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12495 | if (seg == now_seg) | |
12496 | as_bad (_("Can't use floating point insn in this section")); | |
12497 | ||
df58fc94 RS |
12498 | /* Set the argument to the current address in the |
12499 | section. */ | |
12500 | offset_expr.X_op = O_symbol; | |
12501 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12502 | offset_expr.X_add_number = 0; | |
12503 | ||
12504 | /* Put the floating point number into the section. */ | |
12505 | p = frag_more ((int) length); | |
12506 | memcpy (p, temp, length); | |
12507 | ||
12508 | /* Switch back to the original section. */ | |
12509 | subseg_set (seg, subseg); | |
12510 | } | |
12511 | } | |
12512 | continue; | |
12513 | ||
12514 | case 'i': /* 16-bit unsigned immediate. */ | |
12515 | case 'j': /* 16-bit signed immediate. */ | |
12516 | *imm_reloc = BFD_RELOC_LO16; | |
12517 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12518 | { | |
12519 | int more; | |
12520 | offsetT minval, maxval; | |
12521 | ||
12522 | more = (insn + 1 < past | |
12523 | && strcmp (insn->name, insn[1].name) == 0); | |
12524 | ||
12525 | /* If the expression was written as an unsigned number, | |
12526 | only treat it as signed if there are no more | |
12527 | alternatives. */ | |
12528 | if (more | |
12529 | && *args == 'j' | |
12530 | && sizeof (imm_expr.X_add_number) <= 4 | |
12531 | && imm_expr.X_op == O_constant | |
12532 | && imm_expr.X_add_number < 0 | |
12533 | && imm_expr.X_unsigned | |
12534 | && HAVE_64BIT_GPRS) | |
12535 | break; | |
12536 | ||
12537 | /* For compatibility with older assemblers, we accept | |
12538 | 0x8000-0xffff as signed 16-bit numbers when only | |
12539 | signed numbers are allowed. */ | |
12540 | if (*args == 'i') | |
12541 | minval = 0, maxval = 0xffff; | |
12542 | else if (more) | |
12543 | minval = -0x8000, maxval = 0x7fff; | |
12544 | else | |
12545 | minval = -0x8000, maxval = 0xffff; | |
12546 | ||
12547 | if (imm_expr.X_op != O_constant | |
12548 | || imm_expr.X_add_number < minval | |
12549 | || imm_expr.X_add_number > maxval) | |
12550 | { | |
12551 | if (more) | |
12552 | break; | |
12553 | if (imm_expr.X_op == O_constant | |
12554 | || imm_expr.X_op == O_big) | |
12555 | as_bad (_("Expression out of range")); | |
12556 | } | |
12557 | } | |
12558 | s = expr_end; | |
12559 | continue; | |
12560 | ||
12561 | case 'o': /* 16-bit offset. */ | |
12562 | offset_reloc[0] = BFD_RELOC_LO16; | |
12563 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12564 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12565 | ||
12566 | /* Check whether there is only a single bracketed expression | |
12567 | left. If so, it must be the base register and the | |
12568 | constant must be zero. */ | |
12569 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12570 | { | |
12571 | offset_expr.X_op = O_constant; | |
12572 | offset_expr.X_add_number = 0; | |
12573 | continue; | |
12574 | } | |
12575 | ||
12576 | /* If this value won't fit into a 16 bit offset, then go | |
12577 | find a macro that will generate the 32 bit offset | |
12578 | code pattern. */ | |
12579 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12580 | && (offset_expr.X_op != O_constant | |
12581 | || offset_expr.X_add_number >= 0x8000 | |
12582 | || offset_expr.X_add_number < -0x8000)) | |
12583 | break; | |
12584 | ||
12585 | s = expr_end; | |
12586 | continue; | |
12587 | ||
12588 | case 'p': /* PC-relative offset. */ | |
12589 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12590 | my_getExpression (&offset_expr, s); | |
12591 | s = expr_end; | |
12592 | continue; | |
12593 | ||
12594 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12595 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12596 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12597 | && imm_expr.X_op == O_constant | |
12598 | && (imm_expr.X_add_number < 0 | |
12599 | || imm_expr.X_add_number >= 0x10000)) | |
12600 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12601 | (unsigned long) imm_expr.X_add_number); | |
12602 | s = expr_end; | |
12603 | continue; | |
12604 | ||
12605 | case 'a': /* 26-bit address. */ | |
12606 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12607 | my_getExpression (&offset_expr, s); | |
12608 | s = expr_end; | |
12609 | continue; | |
12610 | ||
12611 | case 'N': /* 3-bit branch condition code. */ | |
12612 | case 'M': /* 3-bit compare condition code. */ | |
12613 | rtype = RTYPE_CCC; | |
12614 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12615 | rtype |= RTYPE_FCC; | |
12616 | if (!reg_lookup (&s, rtype, ®no)) | |
12617 | break; | |
12618 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12619 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12620 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12621 | && (regno & 1) != 0) | |
12622 | as_warn (_("Condition code register should be even for %s, " | |
12623 | "was %d"), | |
12624 | str, regno); | |
12625 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12626 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12627 | && (regno & 3) != 0) | |
12628 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12629 | "was %d"), | |
12630 | str, regno); | |
12631 | if (*args == 'N') | |
12632 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12633 | else | |
12634 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12635 | continue; | |
12636 | ||
12637 | case 'H': | |
12638 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12639 | s += 2; | |
12640 | if (ISDIGIT (*s)) | |
12641 | { | |
12642 | c = 0; | |
12643 | do | |
12644 | { | |
12645 | c *= 10; | |
12646 | c += *s - '0'; | |
12647 | ++s; | |
12648 | } | |
12649 | while (ISDIGIT (*s)); | |
12650 | } | |
12651 | else | |
12652 | c = 8; /* Invalid sel value. */ | |
12653 | ||
12654 | if (c > 7) | |
12655 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12656 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12657 | continue; | |
12658 | ||
12659 | case 'e': | |
12660 | gas_assert (!mips_opts.micromips); | |
12661 | /* Must be at least one digit. */ | |
12662 | my_getExpression (&imm_expr, s); | |
12663 | check_absolute_expr (ip, &imm_expr); | |
12664 | ||
12665 | if ((unsigned long) imm_expr.X_add_number | |
12666 | > (unsigned long) OP_MASK_VECBYTE) | |
12667 | { | |
12668 | as_bad (_("bad byte vector index (%ld)"), | |
12669 | (long) imm_expr.X_add_number); | |
12670 | imm_expr.X_add_number = 0; | |
12671 | } | |
12672 | ||
12673 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12674 | imm_expr.X_op = O_absent; | |
12675 | s = expr_end; | |
12676 | continue; | |
12677 | ||
12678 | case '%': | |
12679 | gas_assert (!mips_opts.micromips); | |
12680 | my_getExpression (&imm_expr, s); | |
12681 | check_absolute_expr (ip, &imm_expr); | |
12682 | ||
12683 | if ((unsigned long) imm_expr.X_add_number | |
12684 | > (unsigned long) OP_MASK_VECALIGN) | |
12685 | { | |
12686 | as_bad (_("bad byte vector index (%ld)"), | |
12687 | (long) imm_expr.X_add_number); | |
12688 | imm_expr.X_add_number = 0; | |
12689 | } | |
12690 | ||
12691 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12692 | imm_expr.X_op = O_absent; | |
12693 | s = expr_end; | |
12694 | continue; | |
12695 | ||
12696 | case 'm': /* Opcode extension character. */ | |
12697 | gas_assert (mips_opts.micromips); | |
12698 | c = *++args; | |
12699 | switch (c) | |
12700 | { | |
12701 | case 'r': | |
12702 | if (strncmp (s, "$pc", 3) == 0) | |
12703 | { | |
12704 | s += 3; | |
12705 | continue; | |
12706 | } | |
12707 | break; | |
12708 | ||
12709 | case 'a': | |
12710 | case 'b': | |
12711 | case 'c': | |
12712 | case 'd': | |
12713 | case 'e': | |
12714 | case 'f': | |
12715 | case 'g': | |
12716 | case 'h': | |
12717 | case 'i': | |
12718 | case 'j': | |
12719 | case 'l': | |
12720 | case 'm': | |
12721 | case 'n': | |
12722 | case 'p': | |
12723 | case 'q': | |
12724 | case 's': | |
12725 | case 't': | |
12726 | case 'x': | |
12727 | case 'y': | |
12728 | case 'z': | |
12729 | s_reset = s; | |
12730 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12731 | if (regno == AT && mips_opts.at) | |
12732 | { | |
12733 | if (mips_opts.at == ATREG) | |
12734 | as_warn (_("Used $at without \".set noat\"")); | |
12735 | else | |
12736 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12737 | regno, mips_opts.at); | |
12738 | } | |
12739 | if (!ok) | |
12740 | { | |
12741 | if (c == 'c') | |
12742 | { | |
12743 | gas_assert (args[1] == ','); | |
12744 | regno = lastregno; | |
12745 | ++args; | |
12746 | } | |
12747 | else if (c == 't') | |
12748 | { | |
12749 | gas_assert (args[1] == ','); | |
12750 | ++args; | |
12751 | continue; /* Nothing to do. */ | |
12752 | } | |
12753 | else | |
12754 | break; | |
12755 | } | |
12756 | ||
12757 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12758 | { | |
12759 | if (regno == lastregno) | |
12760 | { | |
12761 | insn_error | |
12762 | = _("Source and destination must be different"); | |
12763 | continue; | |
12764 | } | |
12765 | if (regno == 31 && lastregno == 0xffffffff) | |
12766 | { | |
12767 | insn_error | |
12768 | = _("A destination register must be supplied"); | |
12769 | continue; | |
12770 | } | |
12771 | } | |
12772 | ||
12773 | if (*s == ' ') | |
12774 | ++s; | |
12775 | if (args[1] != *s) | |
12776 | { | |
12777 | if (c == 'e') | |
12778 | { | |
12779 | gas_assert (args[1] == ','); | |
12780 | regno = lastregno; | |
12781 | s = s_reset; | |
12782 | ++args; | |
12783 | } | |
12784 | else if (c == 't') | |
12785 | { | |
12786 | gas_assert (args[1] == ','); | |
12787 | s = s_reset; | |
12788 | ++args; | |
12789 | continue; /* Nothing to do. */ | |
12790 | } | |
12791 | } | |
12792 | ||
12793 | /* Make sure regno is the same as lastregno. */ | |
12794 | if (c == 't' && regno != lastregno) | |
12795 | break; | |
12796 | ||
12797 | /* Make sure regno is the same as destregno. */ | |
12798 | if (c == 'x' && regno != destregno) | |
12799 | break; | |
12800 | ||
12801 | /* We need to save regno, before regno maps to the | |
12802 | microMIPS register encoding. */ | |
12803 | lastregno = regno; | |
12804 | ||
12805 | if (c == 'f') | |
12806 | destregno = regno; | |
12807 | ||
12808 | switch (c) | |
12809 | { | |
12810 | case 'a': | |
12811 | if (regno != GP) | |
12812 | regno = ILLEGAL_REG; | |
12813 | break; | |
12814 | ||
12815 | case 'b': | |
12816 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12817 | break; | |
12818 | ||
12819 | case 'c': | |
12820 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12821 | break; | |
12822 | ||
12823 | case 'd': | |
12824 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12825 | break; | |
12826 | ||
12827 | case 'e': | |
12828 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12829 | break; | |
12830 | ||
12831 | case 'f': | |
12832 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12833 | break; | |
12834 | ||
12835 | case 'g': | |
12836 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12837 | break; | |
12838 | ||
12839 | case 'h': | |
12840 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12841 | break; | |
12842 | ||
12843 | case 'i': | |
12844 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12845 | { | |
12846 | case 4: | |
12847 | if (regno == 21) | |
12848 | regno = 3; | |
12849 | else if (regno == 22) | |
12850 | regno = 4; | |
12851 | else if (regno == 5) | |
12852 | regno = 5; | |
12853 | else if (regno == 6) | |
12854 | regno = 6; | |
12855 | else if (regno == 7) | |
12856 | regno = 7; | |
12857 | else | |
12858 | regno = ILLEGAL_REG; | |
12859 | break; | |
12860 | ||
12861 | case 5: | |
12862 | if (regno == 6) | |
12863 | regno = 0; | |
12864 | else if (regno == 7) | |
12865 | regno = 1; | |
12866 | else | |
12867 | regno = ILLEGAL_REG; | |
12868 | break; | |
12869 | ||
12870 | case 6: | |
12871 | if (regno == 7) | |
12872 | regno = 2; | |
12873 | else | |
12874 | regno = ILLEGAL_REG; | |
12875 | break; | |
12876 | ||
12877 | default: | |
12878 | regno = ILLEGAL_REG; | |
12879 | break; | |
12880 | } | |
12881 | break; | |
12882 | ||
12883 | case 'l': | |
12884 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12885 | break; | |
12886 | ||
12887 | case 'm': | |
12888 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12889 | break; | |
12890 | ||
12891 | case 'n': | |
12892 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12893 | break; | |
12894 | ||
12895 | case 'q': | |
12896 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12897 | break; | |
12898 | ||
12899 | case 's': | |
12900 | if (regno != SP) | |
12901 | regno = ILLEGAL_REG; | |
12902 | break; | |
12903 | ||
12904 | case 'y': | |
12905 | if (regno != 31) | |
12906 | regno = ILLEGAL_REG; | |
12907 | break; | |
12908 | ||
12909 | case 'z': | |
12910 | if (regno != ZERO) | |
12911 | regno = ILLEGAL_REG; | |
12912 | break; | |
12913 | ||
12914 | case 'j': /* Do nothing. */ | |
12915 | case 'p': | |
12916 | case 't': | |
12917 | case 'x': | |
12918 | break; | |
12919 | ||
12920 | default: | |
b37df7c4 | 12921 | abort (); |
df58fc94 RS |
12922 | } |
12923 | ||
12924 | if (regno == ILLEGAL_REG) | |
12925 | break; | |
12926 | ||
12927 | switch (c) | |
12928 | { | |
12929 | case 'b': | |
12930 | INSERT_OPERAND (1, MB, *ip, regno); | |
12931 | break; | |
12932 | ||
12933 | case 'c': | |
12934 | INSERT_OPERAND (1, MC, *ip, regno); | |
12935 | break; | |
12936 | ||
12937 | case 'd': | |
12938 | INSERT_OPERAND (1, MD, *ip, regno); | |
12939 | break; | |
12940 | ||
12941 | case 'e': | |
12942 | INSERT_OPERAND (1, ME, *ip, regno); | |
12943 | break; | |
12944 | ||
12945 | case 'f': | |
12946 | INSERT_OPERAND (1, MF, *ip, regno); | |
12947 | break; | |
12948 | ||
12949 | case 'g': | |
12950 | INSERT_OPERAND (1, MG, *ip, regno); | |
12951 | break; | |
12952 | ||
12953 | case 'h': | |
12954 | INSERT_OPERAND (1, MH, *ip, regno); | |
12955 | break; | |
12956 | ||
12957 | case 'i': | |
12958 | INSERT_OPERAND (1, MI, *ip, regno); | |
12959 | break; | |
12960 | ||
12961 | case 'j': | |
12962 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12963 | break; | |
12964 | ||
12965 | case 'l': | |
12966 | INSERT_OPERAND (1, ML, *ip, regno); | |
12967 | break; | |
12968 | ||
12969 | case 'm': | |
12970 | INSERT_OPERAND (1, MM, *ip, regno); | |
12971 | break; | |
12972 | ||
12973 | case 'n': | |
12974 | INSERT_OPERAND (1, MN, *ip, regno); | |
12975 | break; | |
12976 | ||
12977 | case 'p': | |
12978 | INSERT_OPERAND (1, MP, *ip, regno); | |
12979 | break; | |
12980 | ||
12981 | case 'q': | |
12982 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12983 | break; | |
12984 | ||
12985 | case 'a': /* Do nothing. */ | |
12986 | case 's': /* Do nothing. */ | |
12987 | case 't': /* Do nothing. */ | |
12988 | case 'x': /* Do nothing. */ | |
12989 | case 'y': /* Do nothing. */ | |
12990 | case 'z': /* Do nothing. */ | |
12991 | break; | |
12992 | ||
12993 | default: | |
b37df7c4 | 12994 | abort (); |
df58fc94 RS |
12995 | } |
12996 | continue; | |
12997 | ||
12998 | case 'A': | |
12999 | { | |
13000 | bfd_reloc_code_real_type r[3]; | |
13001 | expressionS ep; | |
13002 | int imm; | |
13003 | ||
13004 | /* Check whether there is only a single bracketed | |
13005 | expression left. If so, it must be the base register | |
13006 | and the constant must be zero. */ | |
13007 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13008 | { | |
13009 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13010 | continue; | |
13011 | } | |
13012 | ||
13013 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13014 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13015 | break; | |
13016 | ||
13017 | imm = ep.X_add_number >> 2; | |
13018 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13019 | } | |
13020 | s = expr_end; | |
13021 | continue; | |
13022 | ||
13023 | case 'B': | |
13024 | { | |
13025 | bfd_reloc_code_real_type r[3]; | |
13026 | expressionS ep; | |
13027 | int imm; | |
13028 | ||
13029 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13030 | || ep.X_op != O_constant) | |
13031 | break; | |
13032 | ||
13033 | for (imm = 0; imm < 8; imm++) | |
13034 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13035 | break; | |
13036 | if (imm >= 8) | |
13037 | break; | |
13038 | ||
13039 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13040 | } | |
13041 | s = expr_end; | |
13042 | continue; | |
13043 | ||
13044 | case 'C': | |
13045 | { | |
13046 | bfd_reloc_code_real_type r[3]; | |
13047 | expressionS ep; | |
13048 | int imm; | |
13049 | ||
13050 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13051 | || ep.X_op != O_constant) | |
13052 | break; | |
13053 | ||
13054 | for (imm = 0; imm < 16; imm++) | |
13055 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13056 | break; | |
13057 | if (imm >= 16) | |
13058 | break; | |
13059 | ||
13060 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13061 | } | |
13062 | s = expr_end; | |
13063 | continue; | |
13064 | ||
13065 | case 'D': /* pc relative offset */ | |
13066 | case 'E': /* pc relative offset */ | |
13067 | my_getExpression (&offset_expr, s); | |
13068 | if (offset_expr.X_op == O_register) | |
13069 | break; | |
13070 | ||
40209cad MR |
13071 | if (!forced_insn_length) |
13072 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13073 | else if (c == 'D') | |
13074 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13075 | else | |
13076 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13077 | s = expr_end; |
13078 | continue; | |
13079 | ||
13080 | case 'F': | |
13081 | { | |
13082 | bfd_reloc_code_real_type r[3]; | |
13083 | expressionS ep; | |
13084 | int imm; | |
13085 | ||
13086 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13087 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13088 | break; | |
13089 | ||
13090 | imm = ep.X_add_number; | |
13091 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13092 | } | |
13093 | s = expr_end; | |
13094 | continue; | |
13095 | ||
13096 | case 'G': | |
13097 | { | |
13098 | bfd_reloc_code_real_type r[3]; | |
13099 | expressionS ep; | |
13100 | int imm; | |
13101 | ||
13102 | /* Check whether there is only a single bracketed | |
13103 | expression left. If so, it must be the base register | |
13104 | and the constant must be zero. */ | |
13105 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13106 | { | |
13107 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13108 | continue; | |
13109 | } | |
13110 | ||
13111 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13112 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13113 | break; | |
13114 | ||
13115 | imm = ep.X_add_number & 15; | |
13116 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13117 | } | |
13118 | s = expr_end; | |
13119 | continue; | |
13120 | ||
13121 | case 'H': | |
13122 | { | |
13123 | bfd_reloc_code_real_type r[3]; | |
13124 | expressionS ep; | |
13125 | int imm; | |
13126 | ||
13127 | /* Check whether there is only a single bracketed | |
13128 | expression left. If so, it must be the base register | |
13129 | and the constant must be zero. */ | |
13130 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13131 | { | |
13132 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13133 | continue; | |
13134 | } | |
13135 | ||
13136 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13137 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13138 | break; | |
13139 | ||
13140 | imm = ep.X_add_number >> 1; | |
13141 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13142 | } | |
13143 | s = expr_end; | |
13144 | continue; | |
13145 | ||
13146 | case 'I': | |
13147 | { | |
13148 | bfd_reloc_code_real_type r[3]; | |
13149 | expressionS ep; | |
13150 | int imm; | |
13151 | ||
13152 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13153 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13154 | break; | |
13155 | ||
13156 | imm = ep.X_add_number & 127; | |
13157 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13158 | } | |
13159 | s = expr_end; | |
13160 | continue; | |
13161 | ||
13162 | case 'J': | |
13163 | { | |
13164 | bfd_reloc_code_real_type r[3]; | |
13165 | expressionS ep; | |
13166 | int imm; | |
13167 | ||
13168 | /* Check whether there is only a single bracketed | |
13169 | expression left. If so, it must be the base register | |
13170 | and the constant must be zero. */ | |
13171 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13172 | { | |
13173 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13174 | continue; | |
13175 | } | |
13176 | ||
13177 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13178 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13179 | break; | |
13180 | ||
13181 | imm = ep.X_add_number >> 2; | |
13182 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13183 | } | |
13184 | s = expr_end; | |
13185 | continue; | |
13186 | ||
13187 | case 'L': | |
13188 | { | |
13189 | bfd_reloc_code_real_type r[3]; | |
13190 | expressionS ep; | |
13191 | int imm; | |
13192 | ||
13193 | /* Check whether there is only a single bracketed | |
13194 | expression left. If so, it must be the base register | |
13195 | and the constant must be zero. */ | |
13196 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13197 | { | |
13198 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13199 | continue; | |
13200 | } | |
13201 | ||
13202 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13203 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13204 | break; | |
13205 | ||
13206 | imm = ep.X_add_number; | |
13207 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13208 | } | |
13209 | s = expr_end; | |
13210 | continue; | |
13211 | ||
13212 | case 'M': | |
13213 | { | |
13214 | bfd_reloc_code_real_type r[3]; | |
13215 | expressionS ep; | |
13216 | int imm; | |
13217 | ||
13218 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13219 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13220 | break; | |
13221 | ||
13222 | imm = ep.X_add_number & 7; | |
13223 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13224 | } | |
13225 | s = expr_end; | |
13226 | continue; | |
13227 | ||
13228 | case 'N': /* Register list for lwm and swm. */ | |
13229 | { | |
13230 | /* A comma-separated list of registers and/or | |
13231 | dash-separated contiguous ranges including | |
13232 | both ra and a set of one or more registers | |
13233 | starting at s0 up to s3 which have to be | |
13234 | consecutive, e.g.: | |
13235 | ||
13236 | s0, ra | |
13237 | s0, s1, ra, s2, s3 | |
13238 | s0-s2, ra | |
13239 | ||
13240 | and any permutations of these. */ | |
13241 | unsigned int reglist; | |
13242 | int imm; | |
13243 | ||
13244 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13245 | break; | |
13246 | ||
13247 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13248 | break; | |
13249 | ||
13250 | reglist = (reglist >> 17) & 7; | |
13251 | reglist += 1; | |
13252 | if ((reglist & -reglist) != reglist) | |
13253 | break; | |
252b5132 | 13254 | |
df58fc94 RS |
13255 | imm = ffs (reglist) - 1; |
13256 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13257 | } | |
13258 | continue; | |
252b5132 | 13259 | |
df58fc94 RS |
13260 | case 'O': /* sdbbp 4-bit code. */ |
13261 | { | |
13262 | bfd_reloc_code_real_type r[3]; | |
13263 | expressionS ep; | |
13264 | int imm; | |
13265 | ||
13266 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13267 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13268 | break; | |
13269 | ||
13270 | imm = ep.X_add_number; | |
13271 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13272 | } |
df58fc94 RS |
13273 | s = expr_end; |
13274 | continue; | |
252b5132 | 13275 | |
df58fc94 RS |
13276 | case 'P': |
13277 | { | |
13278 | bfd_reloc_code_real_type r[3]; | |
13279 | expressionS ep; | |
13280 | int imm; | |
5e0116d5 | 13281 | |
df58fc94 RS |
13282 | if (my_getSmallExpression (&ep, r, s) > 0 |
13283 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13284 | break; | |
5e0116d5 | 13285 | |
df58fc94 RS |
13286 | imm = ep.X_add_number >> 2; |
13287 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13288 | } | |
13289 | s = expr_end; | |
13290 | continue; | |
5e0116d5 | 13291 | |
df58fc94 RS |
13292 | case 'Q': |
13293 | { | |
13294 | bfd_reloc_code_real_type r[3]; | |
13295 | expressionS ep; | |
13296 | int imm; | |
5e0116d5 | 13297 | |
df58fc94 RS |
13298 | if (my_getSmallExpression (&ep, r, s) > 0 |
13299 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13300 | break; | |
252b5132 | 13301 | |
df58fc94 RS |
13302 | imm = ep.X_add_number >> 2; |
13303 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13304 | } | |
13305 | s = expr_end; | |
13306 | continue; | |
4614d845 | 13307 | |
df58fc94 RS |
13308 | case 'U': |
13309 | { | |
13310 | bfd_reloc_code_real_type r[3]; | |
13311 | expressionS ep; | |
13312 | int imm; | |
13313 | ||
13314 | /* Check whether there is only a single bracketed | |
13315 | expression left. If so, it must be the base register | |
13316 | and the constant must be zero. */ | |
13317 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13318 | { | |
13319 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13320 | continue; | |
13321 | } | |
13322 | ||
13323 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13324 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13325 | break; | |
13326 | ||
13327 | imm = ep.X_add_number >> 2; | |
13328 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13329 | } | |
13330 | s = expr_end; | |
5e0116d5 | 13331 | continue; |
252b5132 | 13332 | |
df58fc94 RS |
13333 | case 'W': |
13334 | { | |
13335 | bfd_reloc_code_real_type r[3]; | |
13336 | expressionS ep; | |
13337 | int imm; | |
252b5132 | 13338 | |
df58fc94 RS |
13339 | if (my_getSmallExpression (&ep, r, s) > 0 |
13340 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13341 | break; | |
252b5132 | 13342 | |
df58fc94 RS |
13343 | imm = ep.X_add_number >> 2; |
13344 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13345 | } | |
13346 | s = expr_end; | |
13347 | continue; | |
252b5132 | 13348 | |
df58fc94 RS |
13349 | case 'X': |
13350 | { | |
13351 | bfd_reloc_code_real_type r[3]; | |
13352 | expressionS ep; | |
13353 | int imm; | |
252b5132 | 13354 | |
df58fc94 RS |
13355 | if (my_getSmallExpression (&ep, r, s) > 0 |
13356 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13357 | break; | |
252b5132 | 13358 | |
df58fc94 RS |
13359 | imm = ep.X_add_number; |
13360 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13361 | } | |
13362 | s = expr_end; | |
13363 | continue; | |
252b5132 | 13364 | |
df58fc94 RS |
13365 | case 'Y': |
13366 | { | |
13367 | bfd_reloc_code_real_type r[3]; | |
13368 | expressionS ep; | |
13369 | int imm; | |
156c2f8b | 13370 | |
df58fc94 RS |
13371 | if (my_getSmallExpression (&ep, r, s) > 0 |
13372 | || expr_const_in_range (&ep, -2, 2, 2) | |
13373 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13374 | break; | |
156c2f8b | 13375 | |
df58fc94 RS |
13376 | imm = ep.X_add_number >> 2; |
13377 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13378 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13379 | } | |
13380 | s = expr_end; | |
13381 | continue; | |
60b63b72 | 13382 | |
df58fc94 RS |
13383 | case 'Z': |
13384 | { | |
13385 | bfd_reloc_code_real_type r[3]; | |
13386 | expressionS ep; | |
13387 | ||
13388 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13389 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13390 | break; | |
13391 | } | |
13392 | s = expr_end; | |
13393 | continue; | |
13394 | ||
13395 | default: | |
13396 | as_bad (_("Internal error: bad microMIPS opcode " | |
13397 | "(unknown extension operand type `m%c'): %s %s"), | |
13398 | *args, insn->name, insn->args); | |
13399 | /* Further processing is fruitless. */ | |
13400 | return; | |
60b63b72 | 13401 | } |
df58fc94 | 13402 | break; |
60b63b72 | 13403 | |
df58fc94 RS |
13404 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13405 | gas_assert (mips_opts.micromips); | |
13406 | { | |
13407 | /* A comma-separated list of registers and/or | |
13408 | dash-separated contiguous ranges including | |
13409 | at least one of ra and a set of one or more | |
13410 | registers starting at s0 up to s7 and then | |
13411 | s8 which have to be consecutive, e.g.: | |
13412 | ||
13413 | ra | |
13414 | s0 | |
13415 | ra, s0, s1, s2 | |
13416 | s0-s8 | |
13417 | s0-s5, ra | |
13418 | ||
13419 | and any permutations of these. */ | |
13420 | unsigned int reglist; | |
13421 | int imm; | |
13422 | int ra; | |
13423 | ||
13424 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13425 | break; | |
13426 | ||
13427 | if ((reglist & 0x3f00ffff) != 0) | |
13428 | break; | |
13429 | ||
13430 | ra = (reglist >> 27) & 0x10; | |
13431 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13432 | reglist += 1; | |
13433 | if ((reglist & -reglist) != reglist) | |
13434 | break; | |
13435 | ||
13436 | imm = (ffs (reglist) - 1) | ra; | |
13437 | INSERT_OPERAND (1, RT, *ip, imm); | |
13438 | imm_expr.X_op = O_absent; | |
13439 | } | |
60b63b72 RS |
13440 | continue; |
13441 | ||
df58fc94 RS |
13442 | case '|': /* 4-bit trap code. */ |
13443 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13444 | my_getExpression (&imm_expr, s); |
13445 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13446 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13447 | > MICROMIPSOP_MASK_TRAP) |
13448 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13449 | (unsigned long) imm_expr.X_add_number, | |
13450 | ip->insn_mo->name); | |
13451 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13452 | imm_expr.X_op = O_absent; |
13453 | s = expr_end; | |
13454 | continue; | |
13455 | ||
252b5132 | 13456 | default: |
f71d0d44 | 13457 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13458 | abort (); |
252b5132 RH |
13459 | } |
13460 | break; | |
13461 | } | |
13462 | /* Args don't match. */ | |
df58fc94 RS |
13463 | s = argsStart; |
13464 | insn_error = _("Illegal operands"); | |
13465 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13466 | { |
13467 | ++insn; | |
252b5132 RH |
13468 | continue; |
13469 | } | |
df58fc94 RS |
13470 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13471 | { | |
13472 | gas_assert (firstinsn); | |
13473 | need_delay_slot_ok = FALSE; | |
13474 | past = insn + 1; | |
13475 | insn = firstinsn; | |
13476 | continue; | |
13477 | } | |
252b5132 RH |
13478 | return; |
13479 | } | |
13480 | } | |
13481 | ||
0499d65b TS |
13482 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13483 | ||
252b5132 RH |
13484 | /* This routine assembles an instruction into its binary format when |
13485 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13486 | global variables imm_reloc or offset_reloc to the type of relocation |
13487 | to do if one of the operands is an address expression. It also sets | |
13488 | forced_insn_length to the resulting instruction size in bytes if the | |
13489 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13490 | |
13491 | static void | |
17a2f251 | 13492 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13493 | { |
13494 | char *s; | |
13495 | const char *args; | |
13496 | struct mips_opcode *insn; | |
13497 | char *argsstart; | |
13498 | unsigned int regno; | |
13499 | unsigned int lastregno = 0; | |
13500 | char *s_reset; | |
d6f16593 | 13501 | size_t i; |
252b5132 RH |
13502 | |
13503 | insn_error = NULL; | |
13504 | ||
df58fc94 | 13505 | forced_insn_length = 0; |
252b5132 | 13506 | |
3882b010 | 13507 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13508 | ; |
13509 | switch (*s) | |
13510 | { | |
13511 | case '\0': | |
13512 | break; | |
13513 | ||
13514 | case ' ': | |
13515 | *s++ = '\0'; | |
13516 | break; | |
13517 | ||
13518 | case '.': | |
13519 | if (s[1] == 't' && s[2] == ' ') | |
13520 | { | |
13521 | *s = '\0'; | |
df58fc94 | 13522 | forced_insn_length = 2; |
252b5132 RH |
13523 | s += 3; |
13524 | break; | |
13525 | } | |
13526 | else if (s[1] == 'e' && s[2] == ' ') | |
13527 | { | |
13528 | *s = '\0'; | |
df58fc94 | 13529 | forced_insn_length = 4; |
252b5132 RH |
13530 | s += 3; |
13531 | break; | |
13532 | } | |
13533 | /* Fall through. */ | |
13534 | default: | |
13535 | insn_error = _("unknown opcode"); | |
13536 | return; | |
13537 | } | |
13538 | ||
df58fc94 RS |
13539 | if (mips_opts.noautoextend && !forced_insn_length) |
13540 | forced_insn_length = 2; | |
252b5132 RH |
13541 | |
13542 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13543 | { | |
13544 | insn_error = _("unrecognized opcode"); | |
13545 | return; | |
13546 | } | |
13547 | ||
13548 | argsstart = s; | |
13549 | for (;;) | |
13550 | { | |
9b3f89ee TS |
13551 | bfd_boolean ok; |
13552 | ||
9c2799c2 | 13553 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13554 | |
037b32b9 | 13555 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13556 | if (! ok) |
13557 | { | |
13558 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13559 | && strcmp (insn->name, insn[1].name) == 0) | |
13560 | { | |
13561 | ++insn; | |
13562 | continue; | |
13563 | } | |
13564 | else | |
13565 | { | |
13566 | if (!insn_error) | |
13567 | { | |
13568 | static char buf[100]; | |
13569 | sprintf (buf, | |
7bd942df | 13570 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13571 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13572 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13573 | insn_error = buf; | |
13574 | } | |
13575 | return; | |
13576 | } | |
13577 | } | |
13578 | ||
1e915849 | 13579 | create_insn (ip, insn); |
252b5132 | 13580 | imm_expr.X_op = O_absent; |
f6688943 TS |
13581 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13582 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13583 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13584 | imm2_expr.X_op = O_absent; |
252b5132 | 13585 | offset_expr.X_op = O_absent; |
f6688943 TS |
13586 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13587 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13588 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13589 | for (args = insn->args; 1; ++args) |
13590 | { | |
13591 | int c; | |
13592 | ||
13593 | if (*s == ' ') | |
13594 | ++s; | |
13595 | ||
13596 | /* In this switch statement we call break if we did not find | |
13597 | a match, continue if we did find a match, or return if we | |
13598 | are done. */ | |
13599 | ||
13600 | c = *args; | |
13601 | switch (c) | |
13602 | { | |
13603 | case '\0': | |
13604 | if (*s == '\0') | |
13605 | { | |
b886a2ab RS |
13606 | offsetT value; |
13607 | ||
252b5132 RH |
13608 | /* Stuff the immediate value in now, if we can. */ |
13609 | if (imm_expr.X_op == O_constant | |
f6688943 | 13610 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13611 | && insn->pinfo != INSN_MACRO |
13612 | && calculate_reloc (*offset_reloc, | |
13613 | imm_expr.X_add_number, &value)) | |
252b5132 | 13614 | { |
c4e7957c | 13615 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13616 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13617 | &ip->insn_opcode); |
252b5132 | 13618 | imm_expr.X_op = O_absent; |
f6688943 | 13619 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13620 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13621 | } |
13622 | ||
13623 | return; | |
13624 | } | |
13625 | break; | |
13626 | ||
13627 | case ',': | |
13628 | if (*s++ == c) | |
13629 | continue; | |
13630 | s--; | |
13631 | switch (*++args) | |
13632 | { | |
13633 | case 'v': | |
bf12938e | 13634 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13635 | continue; |
13636 | case 'w': | |
bf12938e | 13637 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13638 | continue; |
13639 | } | |
13640 | break; | |
13641 | ||
13642 | case '(': | |
13643 | case ')': | |
13644 | if (*s++ == c) | |
13645 | continue; | |
13646 | break; | |
13647 | ||
13648 | case 'v': | |
13649 | case 'w': | |
13650 | if (s[0] != '$') | |
13651 | { | |
13652 | if (c == 'v') | |
bf12938e | 13653 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13654 | else |
bf12938e | 13655 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13656 | ++args; |
13657 | continue; | |
13658 | } | |
13659 | /* Fall through. */ | |
13660 | case 'x': | |
13661 | case 'y': | |
13662 | case 'z': | |
13663 | case 'Z': | |
13664 | case '0': | |
13665 | case 'S': | |
13666 | case 'R': | |
13667 | case 'X': | |
13668 | case 'Y': | |
707bfff6 TS |
13669 | s_reset = s; |
13670 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13671 | { |
707bfff6 | 13672 | if (c == 'v' || c == 'w') |
85b51719 | 13673 | { |
707bfff6 | 13674 | if (c == 'v') |
a9e24354 | 13675 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13676 | else |
a9e24354 | 13677 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13678 | ++args; |
13679 | continue; | |
85b51719 | 13680 | } |
707bfff6 | 13681 | break; |
252b5132 RH |
13682 | } |
13683 | ||
13684 | if (*s == ' ') | |
13685 | ++s; | |
13686 | if (args[1] != *s) | |
13687 | { | |
13688 | if (c == 'v' || c == 'w') | |
13689 | { | |
13690 | regno = mips16_to_32_reg_map[lastregno]; | |
13691 | s = s_reset; | |
f9419b05 | 13692 | ++args; |
252b5132 RH |
13693 | } |
13694 | } | |
13695 | ||
13696 | switch (c) | |
13697 | { | |
13698 | case 'x': | |
13699 | case 'y': | |
13700 | case 'z': | |
13701 | case 'v': | |
13702 | case 'w': | |
13703 | case 'Z': | |
13704 | regno = mips32_to_16_reg_map[regno]; | |
13705 | break; | |
13706 | ||
13707 | case '0': | |
13708 | if (regno != 0) | |
13709 | regno = ILLEGAL_REG; | |
13710 | break; | |
13711 | ||
13712 | case 'S': | |
13713 | if (regno != SP) | |
13714 | regno = ILLEGAL_REG; | |
13715 | break; | |
13716 | ||
13717 | case 'R': | |
13718 | if (regno != RA) | |
13719 | regno = ILLEGAL_REG; | |
13720 | break; | |
13721 | ||
13722 | case 'X': | |
13723 | case 'Y': | |
741fe287 MR |
13724 | if (regno == AT && mips_opts.at) |
13725 | { | |
13726 | if (mips_opts.at == ATREG) | |
13727 | as_warn (_("used $at without \".set noat\"")); | |
13728 | else | |
13729 | as_warn (_("used $%u with \".set at=$%u\""), | |
13730 | regno, mips_opts.at); | |
13731 | } | |
252b5132 RH |
13732 | break; |
13733 | ||
13734 | default: | |
b37df7c4 | 13735 | abort (); |
252b5132 RH |
13736 | } |
13737 | ||
13738 | if (regno == ILLEGAL_REG) | |
13739 | break; | |
13740 | ||
13741 | switch (c) | |
13742 | { | |
13743 | case 'x': | |
13744 | case 'v': | |
bf12938e | 13745 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13746 | break; |
13747 | case 'y': | |
13748 | case 'w': | |
bf12938e | 13749 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13750 | break; |
13751 | case 'z': | |
bf12938e | 13752 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13753 | break; |
13754 | case 'Z': | |
bf12938e | 13755 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13756 | case '0': |
13757 | case 'S': | |
13758 | case 'R': | |
13759 | break; | |
13760 | case 'X': | |
bf12938e | 13761 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13762 | break; |
13763 | case 'Y': | |
13764 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13765 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13766 | break; |
13767 | default: | |
b37df7c4 | 13768 | abort (); |
252b5132 RH |
13769 | } |
13770 | ||
13771 | lastregno = regno; | |
13772 | continue; | |
13773 | ||
13774 | case 'P': | |
13775 | if (strncmp (s, "$pc", 3) == 0) | |
13776 | { | |
13777 | s += 3; | |
13778 | continue; | |
13779 | } | |
13780 | break; | |
13781 | ||
252b5132 RH |
13782 | case '5': |
13783 | case 'H': | |
13784 | case 'W': | |
13785 | case 'D': | |
13786 | case 'j': | |
252b5132 RH |
13787 | case 'V': |
13788 | case 'C': | |
13789 | case 'U': | |
13790 | case 'k': | |
13791 | case 'K': | |
d6f16593 MR |
13792 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13793 | if (i > 0) | |
252b5132 | 13794 | { |
d6f16593 | 13795 | if (imm_expr.X_op != O_constant) |
252b5132 | 13796 | { |
df58fc94 | 13797 | forced_insn_length = 4; |
5c04167a | 13798 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13799 | } |
d6f16593 MR |
13800 | else |
13801 | { | |
13802 | /* We need to relax this instruction. */ | |
13803 | *offset_reloc = *imm_reloc; | |
13804 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13805 | } | |
13806 | s = expr_end; | |
13807 | continue; | |
252b5132 | 13808 | } |
d6f16593 MR |
13809 | *imm_reloc = BFD_RELOC_UNUSED; |
13810 | /* Fall through. */ | |
13811 | case '<': | |
13812 | case '>': | |
13813 | case '[': | |
13814 | case ']': | |
13815 | case '4': | |
13816 | case '8': | |
13817 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13818 | if (imm_expr.X_op == O_register) |
13819 | { | |
13820 | /* What we thought was an expression turned out to | |
13821 | be a register. */ | |
13822 | ||
13823 | if (s[0] == '(' && args[1] == '(') | |
13824 | { | |
13825 | /* It looks like the expression was omitted | |
13826 | before a register indirection, which means | |
13827 | that the expression is implicitly zero. We | |
13828 | still set up imm_expr, so that we handle | |
13829 | explicit extensions correctly. */ | |
13830 | imm_expr.X_op = O_constant; | |
13831 | imm_expr.X_add_number = 0; | |
f6688943 | 13832 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13833 | continue; |
13834 | } | |
13835 | ||
13836 | break; | |
13837 | } | |
13838 | ||
13839 | /* We need to relax this instruction. */ | |
f6688943 | 13840 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13841 | s = expr_end; |
13842 | continue; | |
13843 | ||
13844 | case 'p': | |
13845 | case 'q': | |
13846 | case 'A': | |
13847 | case 'B': | |
13848 | case 'E': | |
13849 | /* We use offset_reloc rather than imm_reloc for the PC | |
13850 | relative operands. This lets macros with both | |
13851 | immediate and address operands work correctly. */ | |
13852 | my_getExpression (&offset_expr, s); | |
13853 | ||
13854 | if (offset_expr.X_op == O_register) | |
13855 | break; | |
13856 | ||
13857 | /* We need to relax this instruction. */ | |
f6688943 | 13858 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13859 | s = expr_end; |
13860 | continue; | |
13861 | ||
13862 | case '6': /* break code */ | |
13863 | my_getExpression (&imm_expr, s); | |
13864 | check_absolute_expr (ip, &imm_expr); | |
13865 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13866 | as_warn (_("Invalid value for `%s' (%lu)"), |
13867 | ip->insn_mo->name, | |
13868 | (unsigned long) imm_expr.X_add_number); | |
13869 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13870 | imm_expr.X_op = O_absent; |
13871 | s = expr_end; | |
13872 | continue; | |
13873 | ||
13874 | case 'a': /* 26 bit address */ | |
13875 | my_getExpression (&offset_expr, s); | |
13876 | s = expr_end; | |
f6688943 | 13877 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13878 | ip->insn_opcode <<= 16; |
13879 | continue; | |
13880 | ||
13881 | case 'l': /* register list for entry macro */ | |
13882 | case 'L': /* register list for exit macro */ | |
13883 | { | |
13884 | int mask; | |
13885 | ||
13886 | if (c == 'l') | |
13887 | mask = 0; | |
13888 | else | |
13889 | mask = 7 << 3; | |
13890 | while (*s != '\0') | |
13891 | { | |
707bfff6 | 13892 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13893 | |
13894 | while (*s == ' ' || *s == ',') | |
13895 | ++s; | |
707bfff6 | 13896 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13897 | freg = 0; |
707bfff6 TS |
13898 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13899 | freg = 1; | |
252b5132 RH |
13900 | else |
13901 | { | |
707bfff6 TS |
13902 | as_bad (_("can't parse register list")); |
13903 | break; | |
252b5132 RH |
13904 | } |
13905 | if (*s == ' ') | |
13906 | ++s; | |
13907 | if (*s != '-') | |
13908 | reg2 = reg1; | |
13909 | else | |
13910 | { | |
13911 | ++s; | |
707bfff6 TS |
13912 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13913 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13914 | { |
707bfff6 TS |
13915 | as_bad (_("invalid register list")); |
13916 | break; | |
252b5132 RH |
13917 | } |
13918 | } | |
13919 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13920 | { | |
13921 | mask &= ~ (7 << 3); | |
13922 | mask |= 5 << 3; | |
13923 | } | |
13924 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13925 | { | |
13926 | mask &= ~ (7 << 3); | |
13927 | mask |= 6 << 3; | |
13928 | } | |
13929 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13930 | mask |= (reg2 - 3) << 3; | |
13931 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13932 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13933 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13934 | mask |= 1; |
13935 | else | |
13936 | { | |
13937 | as_bad (_("invalid register list")); | |
13938 | break; | |
13939 | } | |
13940 | } | |
13941 | /* The mask is filled in in the opcode table for the | |
13942 | benefit of the disassembler. We remove it before | |
13943 | applying the actual mask. */ | |
13944 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13945 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13946 | } | |
13947 | continue; | |
13948 | ||
0499d65b TS |
13949 | case 'm': /* Register list for save insn. */ |
13950 | case 'M': /* Register list for restore insn. */ | |
13951 | { | |
5c04167a | 13952 | int opcode = ip->insn_opcode; |
0499d65b | 13953 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13954 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13955 | |
13956 | while (*s != '\0') | |
13957 | { | |
13958 | unsigned int reg1, reg2; | |
13959 | ||
13960 | SKIP_SPACE_TABS (s); | |
13961 | while (*s == ',') | |
13962 | ++s; | |
13963 | SKIP_SPACE_TABS (s); | |
13964 | ||
13965 | my_getExpression (&imm_expr, s); | |
13966 | if (imm_expr.X_op == O_constant) | |
13967 | { | |
13968 | /* Handle the frame size. */ | |
13969 | if (seen_framesz) | |
13970 | { | |
13971 | as_bad (_("more than one frame size in list")); | |
13972 | break; | |
13973 | } | |
13974 | seen_framesz = 1; | |
13975 | framesz = imm_expr.X_add_number; | |
13976 | imm_expr.X_op = O_absent; | |
13977 | s = expr_end; | |
13978 | continue; | |
13979 | } | |
13980 | ||
707bfff6 | 13981 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13982 | { |
13983 | as_bad (_("can't parse register list")); | |
13984 | break; | |
13985 | } | |
0499d65b | 13986 | |
707bfff6 TS |
13987 | while (*s == ' ') |
13988 | ++s; | |
13989 | ||
0499d65b TS |
13990 | if (*s != '-') |
13991 | reg2 = reg1; | |
13992 | else | |
13993 | { | |
13994 | ++s; | |
707bfff6 TS |
13995 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13996 | || reg2 < reg1) | |
0499d65b TS |
13997 | { |
13998 | as_bad (_("can't parse register list")); | |
13999 | break; | |
14000 | } | |
0499d65b TS |
14001 | } |
14002 | ||
14003 | while (reg1 <= reg2) | |
14004 | { | |
14005 | if (reg1 >= 4 && reg1 <= 7) | |
14006 | { | |
3a93f742 | 14007 | if (!seen_framesz) |
0499d65b | 14008 | /* args $a0-$a3 */ |
91d6fa6a | 14009 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14010 | else |
14011 | /* statics $a0-$a3 */ | |
14012 | statics |= 1 << (reg1 - 4); | |
14013 | } | |
14014 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14015 | { | |
14016 | /* $s0-$s8 */ | |
14017 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14018 | } | |
14019 | else if (reg1 == 31) | |
14020 | { | |
14021 | /* Add $ra to insn. */ | |
14022 | opcode |= 0x40; | |
14023 | } | |
14024 | else | |
14025 | { | |
14026 | as_bad (_("unexpected register in list")); | |
14027 | break; | |
14028 | } | |
14029 | if (++reg1 == 24) | |
14030 | reg1 = 30; | |
14031 | } | |
14032 | } | |
14033 | ||
14034 | /* Encode args/statics combination. */ | |
91d6fa6a | 14035 | if (nargs & statics) |
0499d65b | 14036 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14037 | else if (nargs == 0xf) |
0499d65b TS |
14038 | /* All $a0-$a3 are args. */ |
14039 | opcode |= MIPS16_ALL_ARGS << 16; | |
14040 | else if (statics == 0xf) | |
14041 | /* All $a0-$a3 are statics. */ | |
14042 | opcode |= MIPS16_ALL_STATICS << 16; | |
14043 | else | |
14044 | { | |
14045 | int narg = 0, nstat = 0; | |
14046 | ||
14047 | /* Count arg registers. */ | |
91d6fa6a | 14048 | while (nargs & 0x1) |
0499d65b | 14049 | { |
91d6fa6a | 14050 | nargs >>= 1; |
0499d65b TS |
14051 | narg++; |
14052 | } | |
91d6fa6a | 14053 | if (nargs != 0) |
0499d65b TS |
14054 | as_bad (_("invalid arg register list")); |
14055 | ||
14056 | /* Count static registers. */ | |
14057 | while (statics & 0x8) | |
14058 | { | |
14059 | statics = (statics << 1) & 0xf; | |
14060 | nstat++; | |
14061 | } | |
14062 | if (statics != 0) | |
14063 | as_bad (_("invalid static register list")); | |
14064 | ||
14065 | /* Encode args/statics. */ | |
14066 | opcode |= ((narg << 2) | nstat) << 16; | |
14067 | } | |
14068 | ||
14069 | /* Encode $s0/$s1. */ | |
14070 | if (sregs & (1 << 0)) /* $s0 */ | |
14071 | opcode |= 0x20; | |
14072 | if (sregs & (1 << 1)) /* $s1 */ | |
14073 | opcode |= 0x10; | |
14074 | sregs >>= 2; | |
14075 | ||
14076 | if (sregs != 0) | |
14077 | { | |
14078 | /* Count regs $s2-$s8. */ | |
14079 | int nsreg = 0; | |
14080 | while (sregs & 1) | |
14081 | { | |
14082 | sregs >>= 1; | |
14083 | nsreg++; | |
14084 | } | |
14085 | if (sregs != 0) | |
14086 | as_bad (_("invalid static register list")); | |
14087 | /* Encode $s2-$s8. */ | |
14088 | opcode |= nsreg << 24; | |
14089 | } | |
14090 | ||
14091 | /* Encode frame size. */ | |
14092 | if (!seen_framesz) | |
14093 | as_bad (_("missing frame size")); | |
14094 | else if ((framesz & 7) != 0 || framesz < 0 | |
14095 | || framesz > 0xff * 8) | |
14096 | as_bad (_("invalid frame size")); | |
14097 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14098 | { | |
14099 | framesz /= 8; | |
14100 | opcode |= (((framesz & 0xf0) << 16) | |
14101 | | (framesz & 0x0f)); | |
14102 | } | |
14103 | ||
14104 | /* Finally build the instruction. */ | |
14105 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14106 | opcode |= MIPS16_EXTEND; |
14107 | ip->insn_opcode = opcode; | |
0499d65b TS |
14108 | } |
14109 | continue; | |
14110 | ||
252b5132 RH |
14111 | case 'e': /* extend code */ |
14112 | my_getExpression (&imm_expr, s); | |
14113 | check_absolute_expr (ip, &imm_expr); | |
14114 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14115 | { | |
14116 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14117 | ip->insn_mo->name, | |
14118 | (unsigned long) imm_expr.X_add_number); | |
14119 | imm_expr.X_add_number &= 0x7ff; | |
14120 | } | |
14121 | ip->insn_opcode |= imm_expr.X_add_number; | |
14122 | imm_expr.X_op = O_absent; | |
14123 | s = expr_end; | |
14124 | continue; | |
14125 | ||
14126 | default: | |
b37df7c4 | 14127 | abort (); |
252b5132 RH |
14128 | } |
14129 | break; | |
14130 | } | |
14131 | ||
14132 | /* Args don't match. */ | |
14133 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14134 | strcmp (insn->name, insn[1].name) == 0) | |
14135 | { | |
14136 | ++insn; | |
14137 | s = argsstart; | |
14138 | continue; | |
14139 | } | |
14140 | ||
14141 | insn_error = _("illegal operands"); | |
14142 | ||
14143 | return; | |
14144 | } | |
14145 | } | |
14146 | ||
14147 | /* This structure holds information we know about a mips16 immediate | |
14148 | argument type. */ | |
14149 | ||
e972090a NC |
14150 | struct mips16_immed_operand |
14151 | { | |
252b5132 RH |
14152 | /* The type code used in the argument string in the opcode table. */ |
14153 | int type; | |
14154 | /* The number of bits in the short form of the opcode. */ | |
14155 | int nbits; | |
14156 | /* The number of bits in the extended form of the opcode. */ | |
14157 | int extbits; | |
14158 | /* The amount by which the short form is shifted when it is used; | |
14159 | for example, the sw instruction has a shift count of 2. */ | |
14160 | int shift; | |
14161 | /* The amount by which the short form is shifted when it is stored | |
14162 | into the instruction code. */ | |
14163 | int op_shift; | |
14164 | /* Non-zero if the short form is unsigned. */ | |
14165 | int unsp; | |
14166 | /* Non-zero if the extended form is unsigned. */ | |
14167 | int extu; | |
14168 | /* Non-zero if the value is PC relative. */ | |
14169 | int pcrel; | |
14170 | }; | |
14171 | ||
14172 | /* The mips16 immediate operand types. */ | |
14173 | ||
14174 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14175 | { | |
14176 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14177 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14178 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14179 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14180 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14181 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14182 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14183 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14184 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14185 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14186 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14187 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14188 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14189 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14190 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14191 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14192 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14193 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14194 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14195 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14196 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14197 | }; | |
14198 | ||
14199 | #define MIPS16_NUM_IMMED \ | |
14200 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14201 | ||
b886a2ab RS |
14202 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14203 | NBITS is the number of significant bits in VAL. */ | |
14204 | ||
14205 | static unsigned long | |
14206 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14207 | { | |
14208 | int extval; | |
14209 | if (nbits == 16) | |
14210 | { | |
14211 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14212 | val &= 0x1f; | |
14213 | } | |
14214 | else if (nbits == 15) | |
14215 | { | |
14216 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14217 | val &= 0xf; | |
14218 | } | |
14219 | else | |
14220 | { | |
14221 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14222 | val = 0; | |
14223 | } | |
14224 | return (extval << 16) | val; | |
14225 | } | |
14226 | ||
5c04167a RS |
14227 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14228 | extending it if necessary. The instruction in *INSN may | |
14229 | already be extended. | |
14230 | ||
43c0598f RS |
14231 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14232 | if none. In the former case, VAL is a 16-bit number with no | |
14233 | defined signedness. | |
14234 | ||
14235 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14236 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14237 | |
14238 | static void | |
43c0598f RS |
14239 | mips16_immed (char *file, unsigned int line, int type, |
14240 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14241 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14242 | { |
3994f87e | 14243 | const struct mips16_immed_operand *op; |
252b5132 | 14244 | int mintiny, maxtiny; |
252b5132 RH |
14245 | |
14246 | op = mips16_immed_operands; | |
14247 | while (op->type != type) | |
14248 | { | |
14249 | ++op; | |
9c2799c2 | 14250 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14251 | } |
14252 | ||
14253 | if (op->unsp) | |
14254 | { | |
14255 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14256 | { | |
14257 | mintiny = 1; | |
14258 | maxtiny = 1 << op->nbits; | |
14259 | } | |
14260 | else | |
14261 | { | |
14262 | mintiny = 0; | |
14263 | maxtiny = (1 << op->nbits) - 1; | |
14264 | } | |
43c0598f RS |
14265 | if (reloc != BFD_RELOC_UNUSED) |
14266 | val &= 0xffff; | |
252b5132 RH |
14267 | } |
14268 | else | |
14269 | { | |
14270 | mintiny = - (1 << (op->nbits - 1)); | |
14271 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14272 | if (reloc != BFD_RELOC_UNUSED) |
14273 | val = SEXT_16BIT (val); | |
252b5132 RH |
14274 | } |
14275 | ||
14276 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14277 | if (type == 'p' || type == 'q') | |
14278 | val /= 2; | |
14279 | ||
14280 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14281 | || val < (mintiny << op->shift) | |
14282 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14283 | { |
14284 | /* We need an extended instruction. */ | |
14285 | if (user_insn_length == 2) | |
14286 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14287 | else | |
14288 | *insn |= MIPS16_EXTEND; | |
14289 | } | |
14290 | else if (user_insn_length == 4) | |
14291 | { | |
14292 | /* The operand doesn't force an unextended instruction to be extended. | |
14293 | Warn if the user wanted an extended instruction anyway. */ | |
14294 | *insn |= MIPS16_EXTEND; | |
14295 | as_warn_where (file, line, | |
14296 | _("extended operand requested but not required")); | |
14297 | } | |
252b5132 | 14298 | |
5c04167a | 14299 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14300 | { |
14301 | int insnval; | |
14302 | ||
252b5132 RH |
14303 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14304 | insnval <<= op->op_shift; | |
14305 | *insn |= insnval; | |
14306 | } | |
14307 | else | |
14308 | { | |
14309 | long minext, maxext; | |
252b5132 | 14310 | |
43c0598f | 14311 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14312 | { |
43c0598f RS |
14313 | if (op->extu) |
14314 | { | |
14315 | minext = 0; | |
14316 | maxext = (1 << op->extbits) - 1; | |
14317 | } | |
14318 | else | |
14319 | { | |
14320 | minext = - (1 << (op->extbits - 1)); | |
14321 | maxext = (1 << (op->extbits - 1)) - 1; | |
14322 | } | |
14323 | if (val < minext || val > maxext) | |
14324 | as_bad_where (file, line, | |
14325 | _("operand value out of range for instruction")); | |
252b5132 | 14326 | } |
252b5132 | 14327 | |
b886a2ab | 14328 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14329 | } |
14330 | } | |
14331 | \f | |
d6f16593 | 14332 | struct percent_op_match |
ad8d3bb3 | 14333 | { |
5e0116d5 RS |
14334 | const char *str; |
14335 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14336 | }; |
14337 | ||
14338 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14339 | { |
5e0116d5 | 14340 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14341 | #ifdef OBJ_ELF |
5e0116d5 RS |
14342 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14343 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14344 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14345 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14346 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14347 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14348 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14349 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14350 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14351 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14352 | {"%half", BFD_RELOC_16}, | |
14353 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14354 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14355 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14356 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14357 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14358 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14359 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14360 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14361 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14362 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14363 | #endif |
5e0116d5 | 14364 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14365 | }; |
14366 | ||
d6f16593 MR |
14367 | static const struct percent_op_match mips16_percent_op[] = |
14368 | { | |
14369 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14370 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14371 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14372 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14373 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14374 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14375 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14376 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14377 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14378 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14379 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14380 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14381 | }; |
14382 | ||
252b5132 | 14383 | |
5e0116d5 RS |
14384 | /* Return true if *STR points to a relocation operator. When returning true, |
14385 | move *STR over the operator and store its relocation code in *RELOC. | |
14386 | Leave both *STR and *RELOC alone when returning false. */ | |
14387 | ||
14388 | static bfd_boolean | |
17a2f251 | 14389 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14390 | { |
d6f16593 MR |
14391 | const struct percent_op_match *percent_op; |
14392 | size_t limit, i; | |
14393 | ||
14394 | if (mips_opts.mips16) | |
14395 | { | |
14396 | percent_op = mips16_percent_op; | |
14397 | limit = ARRAY_SIZE (mips16_percent_op); | |
14398 | } | |
14399 | else | |
14400 | { | |
14401 | percent_op = mips_percent_op; | |
14402 | limit = ARRAY_SIZE (mips_percent_op); | |
14403 | } | |
76b3015f | 14404 | |
d6f16593 | 14405 | for (i = 0; i < limit; i++) |
5e0116d5 | 14406 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14407 | { |
3f98094e DJ |
14408 | int len = strlen (percent_op[i].str); |
14409 | ||
14410 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14411 | continue; | |
14412 | ||
5e0116d5 RS |
14413 | *str += strlen (percent_op[i].str); |
14414 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14415 | |
5e0116d5 RS |
14416 | /* Check whether the output BFD supports this relocation. |
14417 | If not, issue an error and fall back on something safe. */ | |
14418 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14419 | { |
20203fb9 | 14420 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14421 | percent_op[i].str); |
01a3f561 | 14422 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14423 | } |
5e0116d5 | 14424 | return TRUE; |
394f9b3a | 14425 | } |
5e0116d5 | 14426 | return FALSE; |
394f9b3a | 14427 | } |
ad8d3bb3 | 14428 | |
ad8d3bb3 | 14429 | |
5e0116d5 RS |
14430 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14431 | expression in *EP and the relocations in the array starting | |
14432 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14433 | |
01a3f561 | 14434 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14435 | |
5e0116d5 | 14436 | static size_t |
17a2f251 TS |
14437 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14438 | char *str) | |
ad8d3bb3 | 14439 | { |
5e0116d5 RS |
14440 | bfd_reloc_code_real_type reversed_reloc[3]; |
14441 | size_t reloc_index, i; | |
09b8f35a RS |
14442 | int crux_depth, str_depth; |
14443 | char *crux; | |
5e0116d5 RS |
14444 | |
14445 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14446 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14447 | of the main expression and with CRUX_DEPTH containing the number | |
14448 | of open brackets at that point. */ | |
14449 | reloc_index = -1; | |
14450 | str_depth = 0; | |
14451 | do | |
fb1b3232 | 14452 | { |
09b8f35a RS |
14453 | reloc_index++; |
14454 | crux = str; | |
14455 | crux_depth = str_depth; | |
14456 | ||
14457 | /* Skip over whitespace and brackets, keeping count of the number | |
14458 | of brackets. */ | |
14459 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14460 | if (*str++ == '(') | |
14461 | str_depth++; | |
5e0116d5 | 14462 | } |
09b8f35a RS |
14463 | while (*str == '%' |
14464 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14465 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14466 | |
09b8f35a | 14467 | my_getExpression (ep, crux); |
5e0116d5 | 14468 | str = expr_end; |
394f9b3a | 14469 | |
5e0116d5 | 14470 | /* Match every open bracket. */ |
09b8f35a | 14471 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14472 | if (*str++ == ')') |
09b8f35a | 14473 | crux_depth--; |
394f9b3a | 14474 | |
09b8f35a | 14475 | if (crux_depth > 0) |
20203fb9 | 14476 | as_bad (_("unclosed '('")); |
394f9b3a | 14477 | |
5e0116d5 | 14478 | expr_end = str; |
252b5132 | 14479 | |
01a3f561 | 14480 | if (reloc_index != 0) |
64bdfcaf RS |
14481 | { |
14482 | prev_reloc_op_frag = frag_now; | |
14483 | for (i = 0; i < reloc_index; i++) | |
14484 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14485 | } | |
fb1b3232 | 14486 | |
5e0116d5 | 14487 | return reloc_index; |
252b5132 RH |
14488 | } |
14489 | ||
14490 | static void | |
17a2f251 | 14491 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14492 | { |
14493 | char *save_in; | |
14494 | ||
14495 | save_in = input_line_pointer; | |
14496 | input_line_pointer = str; | |
14497 | expression (ep); | |
14498 | expr_end = input_line_pointer; | |
14499 | input_line_pointer = save_in; | |
252b5132 RH |
14500 | } |
14501 | ||
252b5132 | 14502 | char * |
17a2f251 | 14503 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14504 | { |
499ac353 | 14505 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14506 | } |
14507 | ||
14508 | void | |
17a2f251 | 14509 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14510 | { |
14511 | if (target_big_endian) | |
14512 | number_to_chars_bigendian (buf, val, n); | |
14513 | else | |
14514 | number_to_chars_littleendian (buf, val, n); | |
14515 | } | |
14516 | \f | |
ae948b86 | 14517 | #ifdef OBJ_ELF |
e013f690 TS |
14518 | static int support_64bit_objects(void) |
14519 | { | |
14520 | const char **list, **l; | |
aa3d8fdf | 14521 | int yes; |
e013f690 TS |
14522 | |
14523 | list = bfd_target_list (); | |
14524 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14525 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14526 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14527 | break; |
aa3d8fdf | 14528 | yes = (*l != NULL); |
e013f690 | 14529 | free (list); |
aa3d8fdf | 14530 | return yes; |
e013f690 | 14531 | } |
ae948b86 | 14532 | #endif /* OBJ_ELF */ |
e013f690 | 14533 | |
78849248 | 14534 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14535 | |
23fce1e3 NC |
14536 | enum options |
14537 | { | |
14538 | OPTION_MARCH = OPTION_MD_BASE, | |
14539 | OPTION_MTUNE, | |
14540 | OPTION_MIPS1, | |
14541 | OPTION_MIPS2, | |
14542 | OPTION_MIPS3, | |
14543 | OPTION_MIPS4, | |
14544 | OPTION_MIPS5, | |
14545 | OPTION_MIPS32, | |
14546 | OPTION_MIPS64, | |
14547 | OPTION_MIPS32R2, | |
14548 | OPTION_MIPS64R2, | |
14549 | OPTION_MIPS16, | |
14550 | OPTION_NO_MIPS16, | |
14551 | OPTION_MIPS3D, | |
14552 | OPTION_NO_MIPS3D, | |
14553 | OPTION_MDMX, | |
14554 | OPTION_NO_MDMX, | |
14555 | OPTION_DSP, | |
14556 | OPTION_NO_DSP, | |
14557 | OPTION_MT, | |
14558 | OPTION_NO_MT, | |
b015e599 AP |
14559 | OPTION_VIRT, |
14560 | OPTION_NO_VIRT, | |
23fce1e3 NC |
14561 | OPTION_SMARTMIPS, |
14562 | OPTION_NO_SMARTMIPS, | |
14563 | OPTION_DSPR2, | |
14564 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14565 | OPTION_MICROMIPS, |
14566 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14567 | OPTION_MCU, |
14568 | OPTION_NO_MCU, | |
23fce1e3 NC |
14569 | OPTION_COMPAT_ARCH_BASE, |
14570 | OPTION_M4650, | |
14571 | OPTION_NO_M4650, | |
14572 | OPTION_M4010, | |
14573 | OPTION_NO_M4010, | |
14574 | OPTION_M4100, | |
14575 | OPTION_NO_M4100, | |
14576 | OPTION_M3900, | |
14577 | OPTION_NO_M3900, | |
14578 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14579 | OPTION_MNO_7000_HILO_FIX, |
14580 | OPTION_FIX_24K, | |
14581 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14582 | OPTION_FIX_LOONGSON2F_JUMP, |
14583 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14584 | OPTION_FIX_LOONGSON2F_NOP, | |
14585 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14586 | OPTION_FIX_VR4120, |
14587 | OPTION_NO_FIX_VR4120, | |
14588 | OPTION_FIX_VR4130, | |
14589 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14590 | OPTION_FIX_CN63XXP1, |
14591 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14592 | OPTION_TRAP, |
14593 | OPTION_BREAK, | |
14594 | OPTION_EB, | |
14595 | OPTION_EL, | |
14596 | OPTION_FP32, | |
14597 | OPTION_GP32, | |
14598 | OPTION_CONSTRUCT_FLOATS, | |
14599 | OPTION_NO_CONSTRUCT_FLOATS, | |
14600 | OPTION_FP64, | |
14601 | OPTION_GP64, | |
14602 | OPTION_RELAX_BRANCH, | |
14603 | OPTION_NO_RELAX_BRANCH, | |
14604 | OPTION_MSHARED, | |
14605 | OPTION_MNO_SHARED, | |
14606 | OPTION_MSYM32, | |
14607 | OPTION_MNO_SYM32, | |
14608 | OPTION_SOFT_FLOAT, | |
14609 | OPTION_HARD_FLOAT, | |
14610 | OPTION_SINGLE_FLOAT, | |
14611 | OPTION_DOUBLE_FLOAT, | |
14612 | OPTION_32, | |
14613 | #ifdef OBJ_ELF | |
14614 | OPTION_CALL_SHARED, | |
14615 | OPTION_CALL_NONPIC, | |
14616 | OPTION_NON_SHARED, | |
14617 | OPTION_XGOT, | |
14618 | OPTION_MABI, | |
14619 | OPTION_N32, | |
14620 | OPTION_64, | |
14621 | OPTION_MDEBUG, | |
14622 | OPTION_NO_MDEBUG, | |
14623 | OPTION_PDR, | |
14624 | OPTION_NO_PDR, | |
14625 | OPTION_MVXWORKS_PIC, | |
14626 | #endif /* OBJ_ELF */ | |
14627 | OPTION_END_OF_ENUM | |
14628 | }; | |
14629 | ||
e972090a NC |
14630 | struct option md_longopts[] = |
14631 | { | |
f9b4148d | 14632 | /* Options which specify architecture. */ |
f9b4148d | 14633 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14634 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14635 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14636 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14637 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14638 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14639 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14640 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14641 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14642 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14643 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14644 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14645 | |
14646 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14647 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14648 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14649 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14650 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14651 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14652 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14653 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14654 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14655 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14656 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14657 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14658 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14659 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14660 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14661 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14662 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14663 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14664 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
b015e599 AP |
14665 | {"mvirt", no_argument, NULL, OPTION_VIRT}, |
14666 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
f9b4148d CD |
14667 | |
14668 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14669 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14670 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14671 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14672 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14673 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14674 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14675 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14676 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14677 | ||
14678 | /* Options which enable bug fixes. */ | |
f9b4148d | 14679 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14680 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14681 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14682 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14683 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14684 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14685 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14686 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14687 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14688 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14689 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14690 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14691 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14692 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14693 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14694 | |
14695 | /* Miscellaneous options. */ | |
252b5132 RH |
14696 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14697 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14698 | {"break", no_argument, NULL, OPTION_BREAK}, |
14699 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14700 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14701 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14702 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14703 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14704 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14705 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14706 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14707 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14708 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14709 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14710 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14711 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14712 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14713 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14714 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14715 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14716 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14717 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14718 | |
14719 | /* Strictly speaking this next option is ELF specific, | |
14720 | but we allow it for other ports as well in order to | |
14721 | make testing easier. */ | |
14722 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14723 | |
f9b4148d | 14724 | /* ELF-specific options. */ |
156c2f8b | 14725 | #ifdef OBJ_ELF |
156c2f8b NC |
14726 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14727 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14728 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14729 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14730 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14731 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14732 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14733 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14734 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14735 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14736 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14737 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14738 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14739 | #endif /* OBJ_ELF */ |
f9b4148d | 14740 | |
252b5132 RH |
14741 | {NULL, no_argument, NULL, 0} |
14742 | }; | |
156c2f8b | 14743 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14744 | |
316f5878 RS |
14745 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14746 | NEW_VALUE. Warn if another value was already specified. Note: | |
14747 | we have to defer parsing the -march and -mtune arguments in order | |
14748 | to handle 'from-abi' correctly, since the ABI might be specified | |
14749 | in a later argument. */ | |
14750 | ||
14751 | static void | |
17a2f251 | 14752 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14753 | { |
14754 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14755 | as_warn (_("A different %s was already specified, is now %s"), | |
14756 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14757 | new_value); | |
14758 | ||
14759 | *string_ptr = new_value; | |
14760 | } | |
14761 | ||
252b5132 | 14762 | int |
17a2f251 | 14763 | md_parse_option (int c, char *arg) |
252b5132 RH |
14764 | { |
14765 | switch (c) | |
14766 | { | |
119d663a NC |
14767 | case OPTION_CONSTRUCT_FLOATS: |
14768 | mips_disable_float_construction = 0; | |
14769 | break; | |
bdaaa2e1 | 14770 | |
119d663a NC |
14771 | case OPTION_NO_CONSTRUCT_FLOATS: |
14772 | mips_disable_float_construction = 1; | |
14773 | break; | |
bdaaa2e1 | 14774 | |
252b5132 RH |
14775 | case OPTION_TRAP: |
14776 | mips_trap = 1; | |
14777 | break; | |
14778 | ||
14779 | case OPTION_BREAK: | |
14780 | mips_trap = 0; | |
14781 | break; | |
14782 | ||
14783 | case OPTION_EB: | |
14784 | target_big_endian = 1; | |
14785 | break; | |
14786 | ||
14787 | case OPTION_EL: | |
14788 | target_big_endian = 0; | |
14789 | break; | |
14790 | ||
14791 | case 'O': | |
4ffff32f TS |
14792 | if (arg == NULL) |
14793 | mips_optimize = 1; | |
14794 | else if (arg[0] == '0') | |
14795 | mips_optimize = 0; | |
14796 | else if (arg[0] == '1') | |
252b5132 RH |
14797 | mips_optimize = 1; |
14798 | else | |
14799 | mips_optimize = 2; | |
14800 | break; | |
14801 | ||
14802 | case 'g': | |
14803 | if (arg == NULL) | |
14804 | mips_debug = 2; | |
14805 | else | |
14806 | mips_debug = atoi (arg); | |
252b5132 RH |
14807 | break; |
14808 | ||
14809 | case OPTION_MIPS1: | |
316f5878 | 14810 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14811 | break; |
14812 | ||
14813 | case OPTION_MIPS2: | |
316f5878 | 14814 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14815 | break; |
14816 | ||
14817 | case OPTION_MIPS3: | |
316f5878 | 14818 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14819 | break; |
14820 | ||
14821 | case OPTION_MIPS4: | |
316f5878 | 14822 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14823 | break; |
14824 | ||
84ea6cf2 | 14825 | case OPTION_MIPS5: |
316f5878 | 14826 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14827 | break; |
14828 | ||
e7af610e | 14829 | case OPTION_MIPS32: |
316f5878 | 14830 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14831 | break; |
14832 | ||
af7ee8bf CD |
14833 | case OPTION_MIPS32R2: |
14834 | file_mips_isa = ISA_MIPS32R2; | |
14835 | break; | |
14836 | ||
5f74bc13 CD |
14837 | case OPTION_MIPS64R2: |
14838 | file_mips_isa = ISA_MIPS64R2; | |
14839 | break; | |
14840 | ||
84ea6cf2 | 14841 | case OPTION_MIPS64: |
316f5878 | 14842 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14843 | break; |
14844 | ||
ec68c924 | 14845 | case OPTION_MTUNE: |
316f5878 RS |
14846 | mips_set_option_string (&mips_tune_string, arg); |
14847 | break; | |
ec68c924 | 14848 | |
316f5878 RS |
14849 | case OPTION_MARCH: |
14850 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14851 | break; |
14852 | ||
14853 | case OPTION_M4650: | |
316f5878 RS |
14854 | mips_set_option_string (&mips_arch_string, "4650"); |
14855 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14856 | break; |
14857 | ||
14858 | case OPTION_NO_M4650: | |
14859 | break; | |
14860 | ||
14861 | case OPTION_M4010: | |
316f5878 RS |
14862 | mips_set_option_string (&mips_arch_string, "4010"); |
14863 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14864 | break; |
14865 | ||
14866 | case OPTION_NO_M4010: | |
14867 | break; | |
14868 | ||
14869 | case OPTION_M4100: | |
316f5878 RS |
14870 | mips_set_option_string (&mips_arch_string, "4100"); |
14871 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14872 | break; |
14873 | ||
14874 | case OPTION_NO_M4100: | |
14875 | break; | |
14876 | ||
252b5132 | 14877 | case OPTION_M3900: |
316f5878 RS |
14878 | mips_set_option_string (&mips_arch_string, "3900"); |
14879 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14880 | break; |
bdaaa2e1 | 14881 | |
252b5132 RH |
14882 | case OPTION_NO_M3900: |
14883 | break; | |
14884 | ||
deec1734 CD |
14885 | case OPTION_MDMX: |
14886 | mips_opts.ase_mdmx = 1; | |
14887 | break; | |
14888 | ||
14889 | case OPTION_NO_MDMX: | |
14890 | mips_opts.ase_mdmx = 0; | |
14891 | break; | |
14892 | ||
74cd071d CF |
14893 | case OPTION_DSP: |
14894 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14895 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14896 | break; |
14897 | ||
14898 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14899 | mips_opts.ase_dsp = 0; |
14900 | mips_opts.ase_dspr2 = 0; | |
14901 | break; | |
14902 | ||
14903 | case OPTION_DSPR2: | |
14904 | mips_opts.ase_dspr2 = 1; | |
14905 | mips_opts.ase_dsp = 1; | |
14906 | break; | |
14907 | ||
14908 | case OPTION_NO_DSPR2: | |
14909 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14910 | mips_opts.ase_dsp = 0; |
14911 | break; | |
14912 | ||
ef2e4d86 CF |
14913 | case OPTION_MT: |
14914 | mips_opts.ase_mt = 1; | |
14915 | break; | |
14916 | ||
14917 | case OPTION_NO_MT: | |
14918 | mips_opts.ase_mt = 0; | |
14919 | break; | |
14920 | ||
dec0624d MR |
14921 | case OPTION_MCU: |
14922 | mips_opts.ase_mcu = 1; | |
14923 | break; | |
14924 | ||
14925 | case OPTION_NO_MCU: | |
14926 | mips_opts.ase_mcu = 0; | |
14927 | break; | |
14928 | ||
df58fc94 RS |
14929 | case OPTION_MICROMIPS: |
14930 | if (mips_opts.mips16 == 1) | |
14931 | { | |
14932 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14933 | return 0; | |
14934 | } | |
14935 | mips_opts.micromips = 1; | |
14936 | mips_no_prev_insn (); | |
14937 | break; | |
14938 | ||
14939 | case OPTION_NO_MICROMIPS: | |
14940 | mips_opts.micromips = 0; | |
14941 | mips_no_prev_insn (); | |
14942 | break; | |
14943 | ||
b015e599 AP |
14944 | case OPTION_VIRT: |
14945 | mips_opts.ase_virt = 1; | |
14946 | break; | |
14947 | ||
14948 | case OPTION_NO_VIRT: | |
14949 | mips_opts.ase_virt = 0; | |
14950 | break; | |
14951 | ||
252b5132 | 14952 | case OPTION_MIPS16: |
df58fc94 RS |
14953 | if (mips_opts.micromips == 1) |
14954 | { | |
14955 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14956 | return 0; | |
14957 | } | |
252b5132 | 14958 | mips_opts.mips16 = 1; |
7d10b47d | 14959 | mips_no_prev_insn (); |
252b5132 RH |
14960 | break; |
14961 | ||
14962 | case OPTION_NO_MIPS16: | |
14963 | mips_opts.mips16 = 0; | |
7d10b47d | 14964 | mips_no_prev_insn (); |
252b5132 RH |
14965 | break; |
14966 | ||
1f25f5d3 CD |
14967 | case OPTION_MIPS3D: |
14968 | mips_opts.ase_mips3d = 1; | |
14969 | break; | |
14970 | ||
14971 | case OPTION_NO_MIPS3D: | |
14972 | mips_opts.ase_mips3d = 0; | |
14973 | break; | |
14974 | ||
e16bfa71 TS |
14975 | case OPTION_SMARTMIPS: |
14976 | mips_opts.ase_smartmips = 1; | |
14977 | break; | |
14978 | ||
14979 | case OPTION_NO_SMARTMIPS: | |
14980 | mips_opts.ase_smartmips = 0; | |
14981 | break; | |
14982 | ||
6a32d874 CM |
14983 | case OPTION_FIX_24K: |
14984 | mips_fix_24k = 1; | |
14985 | break; | |
14986 | ||
14987 | case OPTION_NO_FIX_24K: | |
14988 | mips_fix_24k = 0; | |
14989 | break; | |
14990 | ||
c67a084a NC |
14991 | case OPTION_FIX_LOONGSON2F_JUMP: |
14992 | mips_fix_loongson2f_jump = TRUE; | |
14993 | break; | |
14994 | ||
14995 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14996 | mips_fix_loongson2f_jump = FALSE; | |
14997 | break; | |
14998 | ||
14999 | case OPTION_FIX_LOONGSON2F_NOP: | |
15000 | mips_fix_loongson2f_nop = TRUE; | |
15001 | break; | |
15002 | ||
15003 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15004 | mips_fix_loongson2f_nop = FALSE; | |
15005 | break; | |
15006 | ||
d766e8ec RS |
15007 | case OPTION_FIX_VR4120: |
15008 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15009 | break; |
15010 | ||
d766e8ec RS |
15011 | case OPTION_NO_FIX_VR4120: |
15012 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15013 | break; |
15014 | ||
7d8e00cf RS |
15015 | case OPTION_FIX_VR4130: |
15016 | mips_fix_vr4130 = 1; | |
15017 | break; | |
15018 | ||
15019 | case OPTION_NO_FIX_VR4130: | |
15020 | mips_fix_vr4130 = 0; | |
15021 | break; | |
15022 | ||
d954098f DD |
15023 | case OPTION_FIX_CN63XXP1: |
15024 | mips_fix_cn63xxp1 = TRUE; | |
15025 | break; | |
15026 | ||
15027 | case OPTION_NO_FIX_CN63XXP1: | |
15028 | mips_fix_cn63xxp1 = FALSE; | |
15029 | break; | |
15030 | ||
4a6a3df4 AO |
15031 | case OPTION_RELAX_BRANCH: |
15032 | mips_relax_branch = 1; | |
15033 | break; | |
15034 | ||
15035 | case OPTION_NO_RELAX_BRANCH: | |
15036 | mips_relax_branch = 0; | |
15037 | break; | |
15038 | ||
aa6975fb ILT |
15039 | case OPTION_MSHARED: |
15040 | mips_in_shared = TRUE; | |
15041 | break; | |
15042 | ||
15043 | case OPTION_MNO_SHARED: | |
15044 | mips_in_shared = FALSE; | |
15045 | break; | |
15046 | ||
aed1a261 RS |
15047 | case OPTION_MSYM32: |
15048 | mips_opts.sym32 = TRUE; | |
15049 | break; | |
15050 | ||
15051 | case OPTION_MNO_SYM32: | |
15052 | mips_opts.sym32 = FALSE; | |
15053 | break; | |
15054 | ||
0f074f60 | 15055 | #ifdef OBJ_ELF |
252b5132 RH |
15056 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15057 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15058 | intended to be compatible with Irix 5. */ | |
15059 | case OPTION_CALL_SHARED: | |
f43abd2b | 15060 | if (!IS_ELF) |
252b5132 RH |
15061 | { |
15062 | as_bad (_("-call_shared is supported only for ELF format")); | |
15063 | return 0; | |
15064 | } | |
15065 | mips_pic = SVR4_PIC; | |
143d77c5 | 15066 | mips_abicalls = TRUE; |
252b5132 RH |
15067 | break; |
15068 | ||
861fb55a DJ |
15069 | case OPTION_CALL_NONPIC: |
15070 | if (!IS_ELF) | |
15071 | { | |
15072 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
15073 | return 0; | |
15074 | } | |
15075 | mips_pic = NO_PIC; | |
15076 | mips_abicalls = TRUE; | |
15077 | break; | |
15078 | ||
252b5132 | 15079 | case OPTION_NON_SHARED: |
f43abd2b | 15080 | if (!IS_ELF) |
252b5132 RH |
15081 | { |
15082 | as_bad (_("-non_shared is supported only for ELF format")); | |
15083 | return 0; | |
15084 | } | |
15085 | mips_pic = NO_PIC; | |
143d77c5 | 15086 | mips_abicalls = FALSE; |
252b5132 RH |
15087 | break; |
15088 | ||
44075ae2 TS |
15089 | /* The -xgot option tells the assembler to use 32 bit offsets |
15090 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15091 | compatibility. */ |
15092 | case OPTION_XGOT: | |
15093 | mips_big_got = 1; | |
15094 | break; | |
0f074f60 | 15095 | #endif /* OBJ_ELF */ |
252b5132 RH |
15096 | |
15097 | case 'G': | |
6caf9ef4 TS |
15098 | g_switch_value = atoi (arg); |
15099 | g_switch_seen = 1; | |
252b5132 RH |
15100 | break; |
15101 | ||
34ba82a8 TS |
15102 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15103 | and -mabi=64. */ | |
252b5132 | 15104 | case OPTION_32: |
23fce1e3 NC |
15105 | if (IS_ELF) |
15106 | mips_abi = O32_ABI; | |
15107 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15108 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15109 | break; |
15110 | ||
23fce1e3 | 15111 | #ifdef OBJ_ELF |
e013f690 | 15112 | case OPTION_N32: |
f43abd2b | 15113 | if (!IS_ELF) |
34ba82a8 TS |
15114 | { |
15115 | as_bad (_("-n32 is supported for ELF format only")); | |
15116 | return 0; | |
15117 | } | |
316f5878 | 15118 | mips_abi = N32_ABI; |
e013f690 | 15119 | break; |
252b5132 | 15120 | |
e013f690 | 15121 | case OPTION_64: |
f43abd2b | 15122 | if (!IS_ELF) |
34ba82a8 TS |
15123 | { |
15124 | as_bad (_("-64 is supported for ELF format only")); | |
15125 | return 0; | |
15126 | } | |
316f5878 | 15127 | mips_abi = N64_ABI; |
f43abd2b | 15128 | if (!support_64bit_objects()) |
e013f690 | 15129 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15130 | break; |
ae948b86 | 15131 | #endif /* OBJ_ELF */ |
252b5132 | 15132 | |
c97ef257 | 15133 | case OPTION_GP32: |
a325df1d | 15134 | file_mips_gp32 = 1; |
c97ef257 AH |
15135 | break; |
15136 | ||
15137 | case OPTION_GP64: | |
a325df1d | 15138 | file_mips_gp32 = 0; |
c97ef257 | 15139 | break; |
252b5132 | 15140 | |
ca4e0257 | 15141 | case OPTION_FP32: |
a325df1d | 15142 | file_mips_fp32 = 1; |
316f5878 RS |
15143 | break; |
15144 | ||
15145 | case OPTION_FP64: | |
15146 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15147 | break; |
15148 | ||
037b32b9 AN |
15149 | case OPTION_SINGLE_FLOAT: |
15150 | file_mips_single_float = 1; | |
15151 | break; | |
15152 | ||
15153 | case OPTION_DOUBLE_FLOAT: | |
15154 | file_mips_single_float = 0; | |
15155 | break; | |
15156 | ||
15157 | case OPTION_SOFT_FLOAT: | |
15158 | file_mips_soft_float = 1; | |
15159 | break; | |
15160 | ||
15161 | case OPTION_HARD_FLOAT: | |
15162 | file_mips_soft_float = 0; | |
15163 | break; | |
15164 | ||
ae948b86 | 15165 | #ifdef OBJ_ELF |
252b5132 | 15166 | case OPTION_MABI: |
f43abd2b | 15167 | if (!IS_ELF) |
34ba82a8 TS |
15168 | { |
15169 | as_bad (_("-mabi is supported for ELF format only")); | |
15170 | return 0; | |
15171 | } | |
e013f690 | 15172 | if (strcmp (arg, "32") == 0) |
316f5878 | 15173 | mips_abi = O32_ABI; |
e013f690 | 15174 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15175 | mips_abi = O64_ABI; |
e013f690 | 15176 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15177 | mips_abi = N32_ABI; |
e013f690 TS |
15178 | else if (strcmp (arg, "64") == 0) |
15179 | { | |
316f5878 | 15180 | mips_abi = N64_ABI; |
e013f690 TS |
15181 | if (! support_64bit_objects()) |
15182 | as_fatal (_("No compiled in support for 64 bit object file " | |
15183 | "format")); | |
15184 | } | |
15185 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15186 | mips_abi = EABI_ABI; |
e013f690 | 15187 | else |
da0e507f TS |
15188 | { |
15189 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15190 | return 0; | |
15191 | } | |
252b5132 | 15192 | break; |
e013f690 | 15193 | #endif /* OBJ_ELF */ |
252b5132 | 15194 | |
6b76fefe | 15195 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15196 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15197 | break; |
15198 | ||
9ee72ff1 | 15199 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15200 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15201 | break; |
15202 | ||
ecb4347a DJ |
15203 | #ifdef OBJ_ELF |
15204 | case OPTION_MDEBUG: | |
b34976b6 | 15205 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15206 | break; |
15207 | ||
15208 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15209 | mips_flag_mdebug = FALSE; |
ecb4347a | 15210 | break; |
dcd410fe RO |
15211 | |
15212 | case OPTION_PDR: | |
15213 | mips_flag_pdr = TRUE; | |
15214 | break; | |
15215 | ||
15216 | case OPTION_NO_PDR: | |
15217 | mips_flag_pdr = FALSE; | |
15218 | break; | |
0a44bf69 RS |
15219 | |
15220 | case OPTION_MVXWORKS_PIC: | |
15221 | mips_pic = VXWORKS_PIC; | |
15222 | break; | |
ecb4347a DJ |
15223 | #endif /* OBJ_ELF */ |
15224 | ||
252b5132 RH |
15225 | default: |
15226 | return 0; | |
15227 | } | |
15228 | ||
c67a084a NC |
15229 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15230 | ||
252b5132 RH |
15231 | return 1; |
15232 | } | |
316f5878 RS |
15233 | \f |
15234 | /* Set up globals to generate code for the ISA or processor | |
15235 | described by INFO. */ | |
252b5132 | 15236 | |
252b5132 | 15237 | static void |
17a2f251 | 15238 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15239 | { |
316f5878 | 15240 | if (info != 0) |
252b5132 | 15241 | { |
fef14a42 TS |
15242 | file_mips_arch = info->cpu; |
15243 | mips_opts.arch = info->cpu; | |
316f5878 | 15244 | mips_opts.isa = info->isa; |
252b5132 | 15245 | } |
252b5132 RH |
15246 | } |
15247 | ||
252b5132 | 15248 | |
316f5878 | 15249 | /* Likewise for tuning. */ |
252b5132 | 15250 | |
316f5878 | 15251 | static void |
17a2f251 | 15252 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15253 | { |
15254 | if (info != 0) | |
fef14a42 | 15255 | mips_tune = info->cpu; |
316f5878 | 15256 | } |
80cc45a5 | 15257 | |
34ba82a8 | 15258 | |
252b5132 | 15259 | void |
17a2f251 | 15260 | mips_after_parse_args (void) |
e9670677 | 15261 | { |
fef14a42 TS |
15262 | const struct mips_cpu_info *arch_info = 0; |
15263 | const struct mips_cpu_info *tune_info = 0; | |
15264 | ||
e9670677 | 15265 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15266 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15267 | { |
6caf9ef4 | 15268 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15269 | as_bad (_("-G not supported in this configuration.")); |
15270 | g_switch_value = 0; | |
15271 | } | |
15272 | ||
cac012d6 AO |
15273 | if (mips_abi == NO_ABI) |
15274 | mips_abi = MIPS_DEFAULT_ABI; | |
15275 | ||
22923709 RS |
15276 | /* The following code determines the architecture and register size. |
15277 | Similar code was added to GCC 3.3 (see override_options() in | |
15278 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15279 | as much as possible. */ | |
e9670677 | 15280 | |
316f5878 | 15281 | if (mips_arch_string != 0) |
fef14a42 | 15282 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15283 | |
316f5878 | 15284 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15285 | { |
316f5878 | 15286 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15287 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15288 | the -march selection (if any). */ |
fef14a42 | 15289 | if (arch_info != 0) |
e9670677 | 15290 | { |
316f5878 RS |
15291 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15292 | There's no harm in specifying both as long as the ISA levels | |
15293 | are the same. */ | |
fef14a42 | 15294 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15295 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15296 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15297 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15298 | } |
316f5878 | 15299 | else |
fef14a42 | 15300 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15301 | } |
15302 | ||
fef14a42 | 15303 | if (arch_info == 0) |
95bfe26e MF |
15304 | { |
15305 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15306 | gas_assert (arch_info); | |
15307 | } | |
e9670677 | 15308 | |
fef14a42 | 15309 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15310 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15311 | arch_info->name); |
15312 | ||
15313 | mips_set_architecture (arch_info); | |
15314 | ||
15315 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15316 | if (mips_tune_string != 0) | |
15317 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15318 | |
fef14a42 TS |
15319 | if (tune_info == 0) |
15320 | mips_set_tune (arch_info); | |
15321 | else | |
15322 | mips_set_tune (tune_info); | |
e9670677 | 15323 | |
316f5878 | 15324 | if (file_mips_gp32 >= 0) |
e9670677 | 15325 | { |
316f5878 RS |
15326 | /* The user specified the size of the integer registers. Make sure |
15327 | it agrees with the ABI and ISA. */ | |
15328 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15329 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15330 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15331 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15332 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15333 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15334 | } |
15335 | else | |
15336 | { | |
316f5878 RS |
15337 | /* Infer the integer register size from the ABI and processor. |
15338 | Restrict ourselves to 32-bit registers if that's all the | |
15339 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15340 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15341 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15342 | } |
15343 | ||
ad3fea08 TS |
15344 | switch (file_mips_fp32) |
15345 | { | |
15346 | default: | |
15347 | case -1: | |
15348 | /* No user specified float register size. | |
15349 | ??? GAS treats single-float processors as though they had 64-bit | |
15350 | float registers (although it complains when double-precision | |
15351 | instructions are used). As things stand, saying they have 32-bit | |
15352 | registers would lead to spurious "register must be even" messages. | |
15353 | So here we assume float registers are never smaller than the | |
15354 | integer ones. */ | |
15355 | if (file_mips_gp32 == 0) | |
15356 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15357 | file_mips_fp32 = 0; | |
15358 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15359 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15360 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15361 | file_mips_fp32 = 0; | |
15362 | else | |
15363 | /* 32-bit float registers. */ | |
15364 | file_mips_fp32 = 1; | |
15365 | break; | |
15366 | ||
15367 | /* The user specified the size of the float registers. Check if it | |
15368 | agrees with the ABI and ISA. */ | |
15369 | case 0: | |
15370 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15371 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15372 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15373 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15374 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15375 | break; | |
15376 | case 1: | |
15377 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15378 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15379 | break; | |
15380 | } | |
e9670677 | 15381 | |
316f5878 | 15382 | /* End of GCC-shared inference code. */ |
e9670677 | 15383 | |
17a2f251 TS |
15384 | /* This flag is set when we have a 64-bit capable CPU but use only |
15385 | 32-bit wide registers. Note that EABI does not use it. */ | |
15386 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15387 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15388 | || mips_abi == O32_ABI)) | |
316f5878 | 15389 | mips_32bitmode = 1; |
e9670677 MR |
15390 | |
15391 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15392 | as_bad (_("trap exception not supported at ISA 1")); | |
15393 | ||
e9670677 MR |
15394 | /* If the selected architecture includes support for ASEs, enable |
15395 | generation of code for them. */ | |
a4672219 | 15396 | if (mips_opts.mips16 == -1) |
fef14a42 | 15397 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15398 | if (mips_opts.micromips == -1) |
15399 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15400 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15401 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15402 | && file_mips_fp32 == 0) ? 1 : 0; |
15403 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15404 | as_bad (_("-mfp32 used with -mips3d")); | |
15405 | ||
ffdefa66 | 15406 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15407 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15408 | && file_mips_fp32 == 0) ? 1 : 0; |
15409 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15410 | as_bad (_("-mfp32 used with -mdmx")); | |
15411 | ||
15412 | if (mips_opts.ase_smartmips == -1) | |
15413 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15414 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15415 | as_warn (_("%s ISA does not support SmartMIPS"), |
15416 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15417 | |
74cd071d | 15418 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15419 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15420 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15421 | as_warn (_("%s ISA does not support DSP ASE"), |
15422 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15423 | |
8b082fb1 TS |
15424 | if (mips_opts.ase_dspr2 == -1) |
15425 | { | |
15426 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15427 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15428 | } | |
15429 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15430 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15431 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15432 | |
ef2e4d86 | 15433 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15434 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15435 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15436 | as_warn (_("%s ISA does not support MT ASE"), |
15437 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15438 | |
dec0624d MR |
15439 | if (mips_opts.ase_mcu == -1) |
15440 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15441 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15442 | as_warn (_("%s ISA does not support MCU ASE"), | |
15443 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15444 | ||
b015e599 AP |
15445 | if (mips_opts.ase_virt == -1) |
15446 | mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0; | |
15447 | if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE) | |
15448 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
15449 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15450 | ||
e9670677 | 15451 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15452 | file_ase_mips3d = mips_opts.ase_mips3d; |
15453 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15454 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15455 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15456 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15457 | file_ase_mt = mips_opts.ase_mt; |
b015e599 | 15458 | file_ase_virt = mips_opts.ase_virt; |
e9670677 MR |
15459 | mips_opts.gp32 = file_mips_gp32; |
15460 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15461 | mips_opts.soft_float = file_mips_soft_float; |
15462 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15463 | |
ecb4347a DJ |
15464 | if (mips_flag_mdebug < 0) |
15465 | { | |
15466 | #ifdef OBJ_MAYBE_ECOFF | |
15467 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15468 | mips_flag_mdebug = 1; | |
15469 | else | |
15470 | #endif /* OBJ_MAYBE_ECOFF */ | |
15471 | mips_flag_mdebug = 0; | |
15472 | } | |
e9670677 MR |
15473 | } |
15474 | \f | |
15475 | void | |
17a2f251 | 15476 | mips_init_after_args (void) |
252b5132 RH |
15477 | { |
15478 | /* initialize opcodes */ | |
15479 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15480 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15481 | } |
15482 | ||
15483 | long | |
17a2f251 | 15484 | md_pcrel_from (fixS *fixP) |
252b5132 | 15485 | { |
a7ebbfdf TS |
15486 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15487 | switch (fixP->fx_r_type) | |
15488 | { | |
df58fc94 RS |
15489 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15490 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15491 | /* Return the address of the delay slot. */ | |
15492 | return addr + 2; | |
15493 | ||
15494 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15495 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15496 | case BFD_RELOC_16_PCREL_S2: |
15497 | case BFD_RELOC_MIPS_JMP: | |
15498 | /* Return the address of the delay slot. */ | |
15499 | return addr + 4; | |
df58fc94 | 15500 | |
b47468a6 CM |
15501 | case BFD_RELOC_32_PCREL: |
15502 | return addr; | |
15503 | ||
a7ebbfdf | 15504 | default: |
58ea3d6a | 15505 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15506 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15507 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15508 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15509 | return addr; |
15510 | } | |
252b5132 RH |
15511 | } |
15512 | ||
252b5132 RH |
15513 | /* This is called before the symbol table is processed. In order to |
15514 | work with gcc when using mips-tfile, we must keep all local labels. | |
15515 | However, in other cases, we want to discard them. If we were | |
15516 | called with -g, but we didn't see any debugging information, it may | |
15517 | mean that gcc is smuggling debugging information through to | |
15518 | mips-tfile, in which case we must generate all local labels. */ | |
15519 | ||
15520 | void | |
17a2f251 | 15521 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15522 | { |
15523 | #ifndef NO_ECOFF_DEBUGGING | |
15524 | if (ECOFF_DEBUGGING | |
15525 | && mips_debug != 0 | |
15526 | && ! ecoff_debugging_seen) | |
15527 | flag_keep_locals = 1; | |
15528 | #endif | |
15529 | } | |
15530 | ||
3b91255e | 15531 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15532 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15533 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15534 | relocation operators. | |
15535 | ||
15536 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15537 | expression if: | |
15538 | ||
15539 | (a) it refers to the same symbol; and | |
15540 | (b) the offset applied in the %lo() expression is no lower than | |
15541 | the offset applied in the %got() or %hi(). | |
15542 | ||
15543 | (b) allows us to cope with code like: | |
15544 | ||
15545 | lui $4,%hi(foo) | |
15546 | lh $4,%lo(foo+2)($4) | |
15547 | ||
15548 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15549 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15550 | the high 16 bits. | |
15551 | ||
15552 | When several %lo()s match a particular %got() or %hi(), we use the | |
15553 | following rules to distinguish them: | |
15554 | ||
15555 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15556 | higher offsets. | |
15557 | ||
15558 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15559 | that already have a matching %got() or %hi(). | |
15560 | ||
15561 | (3) later %lo()s are better than earlier %lo()s. | |
15562 | ||
15563 | These rules are applied in order. | |
15564 | ||
15565 | (1) means, among other things, that %lo()s with identical offsets are | |
15566 | chosen if they exist. | |
15567 | ||
15568 | (2) means that we won't associate several high-part relocations with | |
15569 | the same low-part relocation unless there's no alternative. Having | |
15570 | several high parts for the same low part is a GNU extension; this rule | |
15571 | allows careful users to avoid it. | |
15572 | ||
15573 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15574 | with the last high-part relocation being at the front of the list. | |
15575 | It therefore makes sense to choose the last matching low-part | |
15576 | relocation, all other things being equal. It's also easier | |
15577 | to code that way. */ | |
252b5132 RH |
15578 | |
15579 | void | |
17a2f251 | 15580 | mips_frob_file (void) |
252b5132 RH |
15581 | { |
15582 | struct mips_hi_fixup *l; | |
35903be0 | 15583 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15584 | |
15585 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15586 | { | |
15587 | segment_info_type *seginfo; | |
3b91255e RS |
15588 | bfd_boolean matched_lo_p; |
15589 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15590 | |
9c2799c2 | 15591 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15592 | |
5919d012 | 15593 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15594 | there isn't supposed to be a matching LO. Ignore %gots against |
15595 | constants; we'll report an error for those later. */ | |
738e5348 | 15596 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15597 | && !(l->fixp->fx_addsy |
15598 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15599 | continue; |
15600 | ||
15601 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15602 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15603 | continue; |
15604 | ||
252b5132 | 15605 | seginfo = seg_info (l->seg); |
252b5132 | 15606 | |
3b91255e RS |
15607 | /* Set HI_POS to the position of this relocation in the chain. |
15608 | Set LO_POS to the position of the chosen low-part relocation. | |
15609 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15610 | relocation that matches an immediately-preceding high-part | |
15611 | relocation. */ | |
15612 | hi_pos = NULL; | |
15613 | lo_pos = NULL; | |
15614 | matched_lo_p = FALSE; | |
738e5348 | 15615 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15616 | |
3b91255e RS |
15617 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15618 | { | |
15619 | if (*pos == l->fixp) | |
15620 | hi_pos = pos; | |
15621 | ||
35903be0 | 15622 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15623 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15624 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15625 | && (lo_pos == NULL | |
15626 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15627 | || (!matched_lo_p | |
15628 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15629 | lo_pos = pos; | |
15630 | ||
15631 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15632 | && fixup_has_matching_lo_p (*pos)); | |
15633 | } | |
15634 | ||
15635 | /* If we found a match, remove the high-part relocation from its | |
15636 | current position and insert it before the low-part relocation. | |
15637 | Make the offsets match so that fixup_has_matching_lo_p() | |
15638 | will return true. | |
15639 | ||
15640 | We don't warn about unmatched high-part relocations since some | |
15641 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15642 | instructions. */ | |
15643 | if (lo_pos != NULL) | |
15644 | { | |
15645 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15646 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15647 | { |
3b91255e RS |
15648 | *hi_pos = l->fixp->fx_next; |
15649 | l->fixp->fx_next = *lo_pos; | |
15650 | *lo_pos = l->fixp; | |
252b5132 | 15651 | } |
252b5132 RH |
15652 | } |
15653 | } | |
15654 | } | |
15655 | ||
252b5132 | 15656 | int |
17a2f251 | 15657 | mips_force_relocation (fixS *fixp) |
252b5132 | 15658 | { |
ae6063d4 | 15659 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15660 | return 1; |
15661 | ||
df58fc94 RS |
15662 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15663 | so that the linker relaxation can update targets. */ | |
15664 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15665 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15666 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15667 | return 1; | |
15668 | ||
3e722fb5 | 15669 | return 0; |
252b5132 RH |
15670 | } |
15671 | ||
b886a2ab RS |
15672 | /* Read the instruction associated with RELOC from BUF. */ |
15673 | ||
15674 | static unsigned int | |
15675 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15676 | { | |
15677 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15678 | return read_compressed_insn (buf, 4); | |
15679 | else | |
15680 | return read_insn (buf); | |
15681 | } | |
15682 | ||
15683 | /* Write instruction INSN to BUF, given that it has been relocated | |
15684 | by RELOC. */ | |
15685 | ||
15686 | static void | |
15687 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15688 | unsigned long insn) | |
15689 | { | |
15690 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15691 | write_compressed_insn (buf, insn, 4); | |
15692 | else | |
15693 | write_insn (buf, insn); | |
15694 | } | |
15695 | ||
252b5132 RH |
15696 | /* Apply a fixup to the object file. */ |
15697 | ||
94f592af | 15698 | void |
55cf6793 | 15699 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15700 | { |
4d68580a | 15701 | char *buf; |
b886a2ab | 15702 | unsigned long insn; |
a7ebbfdf | 15703 | reloc_howto_type *howto; |
252b5132 | 15704 | |
a7ebbfdf TS |
15705 | /* We ignore generic BFD relocations we don't know about. */ |
15706 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15707 | if (! howto) | |
15708 | return; | |
65551fa4 | 15709 | |
df58fc94 RS |
15710 | gas_assert (fixP->fx_size == 2 |
15711 | || fixP->fx_size == 4 | |
90ecf173 MR |
15712 | || fixP->fx_r_type == BFD_RELOC_16 |
15713 | || fixP->fx_r_type == BFD_RELOC_64 | |
15714 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15715 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15716 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15717 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15718 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15719 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15720 | |
4d68580a | 15721 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15722 | |
df58fc94 RS |
15723 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15724 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15725 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15726 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15727 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15728 | |
15729 | /* Don't treat parts of a composite relocation as done. There are two | |
15730 | reasons for this: | |
15731 | ||
15732 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15733 | should nevertheless be emitted if the first part is. | |
15734 | ||
15735 | (2) In normal usage, composite relocations are never assembly-time | |
15736 | constants. The easiest way of dealing with the pathological | |
15737 | exceptions is to generate a relocation against STN_UNDEF and | |
15738 | leave everything up to the linker. */ | |
3994f87e | 15739 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15740 | fixP->fx_done = 1; |
15741 | ||
15742 | switch (fixP->fx_r_type) | |
15743 | { | |
3f98094e DJ |
15744 | case BFD_RELOC_MIPS_TLS_GD: |
15745 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15746 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15747 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15748 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15749 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15750 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15751 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15752 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15753 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15754 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15755 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15756 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15757 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15758 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15759 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15760 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15761 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15762 | case BFD_RELOC_MIPS16_TLS_GD: |
15763 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15764 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15765 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15766 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15767 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15768 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15769 | if (!fixP->fx_addsy) |
15770 | { | |
15771 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15772 | _("TLS relocation against a constant")); | |
15773 | break; | |
15774 | } | |
3f98094e DJ |
15775 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15776 | /* fall through */ | |
15777 | ||
252b5132 | 15778 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15779 | case BFD_RELOC_MIPS_SHIFT5: |
15780 | case BFD_RELOC_MIPS_SHIFT6: | |
15781 | case BFD_RELOC_MIPS_GOT_DISP: | |
15782 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15783 | case BFD_RELOC_MIPS_GOT_OFST: | |
15784 | case BFD_RELOC_MIPS_SUB: | |
15785 | case BFD_RELOC_MIPS_INSERT_A: | |
15786 | case BFD_RELOC_MIPS_INSERT_B: | |
15787 | case BFD_RELOC_MIPS_DELETE: | |
15788 | case BFD_RELOC_MIPS_HIGHEST: | |
15789 | case BFD_RELOC_MIPS_HIGHER: | |
15790 | case BFD_RELOC_MIPS_SCN_DISP: | |
15791 | case BFD_RELOC_MIPS_REL16: | |
15792 | case BFD_RELOC_MIPS_RELGOT: | |
15793 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15794 | case BFD_RELOC_HI16: |
15795 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15796 | case BFD_RELOC_LO16: |
cdf6fd85 | 15797 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15798 | case BFD_RELOC_MIPS_LITERAL: |
15799 | case BFD_RELOC_MIPS_CALL16: | |
15800 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15801 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15802 | case BFD_RELOC_MIPS_GOT_HI16: |
15803 | case BFD_RELOC_MIPS_GOT_LO16: | |
15804 | case BFD_RELOC_MIPS_CALL_HI16: | |
15805 | case BFD_RELOC_MIPS_CALL_LO16: | |
15806 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15807 | case BFD_RELOC_MIPS16_GOT16: |
15808 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15809 | case BFD_RELOC_MIPS16_HI16: |
15810 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15811 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15812 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15813 | case BFD_RELOC_MICROMIPS_JMP: |
15814 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15815 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15816 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15817 | case BFD_RELOC_MICROMIPS_SUB: | |
15818 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15819 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15820 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15821 | case BFD_RELOC_MICROMIPS_JALR: | |
15822 | case BFD_RELOC_MICROMIPS_HI16: | |
15823 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15824 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15825 | case BFD_RELOC_MICROMIPS_GPREL16: |
15826 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15827 | case BFD_RELOC_MICROMIPS_CALL16: | |
15828 | case BFD_RELOC_MICROMIPS_GOT16: | |
15829 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15830 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15831 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15832 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15833 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15834 | if (fixP->fx_done) |
15835 | { | |
15836 | offsetT value; | |
15837 | ||
15838 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15839 | { | |
15840 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15841 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15842 | insn |= mips16_immed_extend (value, 16); | |
15843 | else | |
15844 | insn |= (value & 0xffff); | |
15845 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15846 | } | |
15847 | else | |
15848 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15849 | _("Unsupported constant in relocation")); | |
15850 | } | |
252b5132 RH |
15851 | break; |
15852 | ||
252b5132 RH |
15853 | case BFD_RELOC_64: |
15854 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15855 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15856 | if (fixP->fx_done) |
252b5132 RH |
15857 | { |
15858 | if (8 <= sizeof (valueT)) | |
4d68580a | 15859 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15860 | else |
15861 | { | |
a7ebbfdf | 15862 | valueT hiv; |
252b5132 | 15863 | |
a7ebbfdf | 15864 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15865 | hiv = 0xffffffff; |
15866 | else | |
15867 | hiv = 0; | |
4d68580a RS |
15868 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15869 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15870 | } |
15871 | } | |
15872 | break; | |
15873 | ||
056350c6 | 15874 | case BFD_RELOC_RVA: |
252b5132 | 15875 | case BFD_RELOC_32: |
b47468a6 | 15876 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15877 | case BFD_RELOC_16: |
15878 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15879 | value now. This can happen if we have a .word which is not |
15880 | resolved when it appears but is later defined. */ | |
252b5132 | 15881 | if (fixP->fx_done) |
4d68580a | 15882 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15883 | break; |
15884 | ||
252b5132 | 15885 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15886 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15887 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15888 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15889 | |
54f4ddb3 TS |
15890 | /* We need to save the bits in the instruction since fixup_segment() |
15891 | might be deleting the relocation entry (i.e., a branch within | |
15892 | the current segment). */ | |
a7ebbfdf | 15893 | if (! fixP->fx_done) |
bb2d6cd7 | 15894 | break; |
252b5132 | 15895 | |
54f4ddb3 | 15896 | /* Update old instruction data. */ |
4d68580a | 15897 | insn = read_insn (buf); |
252b5132 | 15898 | |
a7ebbfdf TS |
15899 | if (*valP + 0x20000 <= 0x3ffff) |
15900 | { | |
15901 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15902 | write_insn (buf, insn); |
a7ebbfdf TS |
15903 | } |
15904 | else if (mips_pic == NO_PIC | |
15905 | && fixP->fx_done | |
15906 | && fixP->fx_frag->fr_address >= text_section->vma | |
15907 | && (fixP->fx_frag->fr_address | |
587aac4e | 15908 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15909 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15910 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15911 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15912 | { |
15913 | /* The branch offset is too large. If this is an | |
15914 | unconditional branch, and we are not generating PIC code, | |
15915 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15916 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15917 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15918 | else |
a7ebbfdf TS |
15919 | insn = 0x08000000; /* j */ |
15920 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15921 | fixP->fx_done = 0; | |
15922 | fixP->fx_addsy = section_symbol (text_section); | |
15923 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15924 | write_insn (buf, insn); |
a7ebbfdf TS |
15925 | } |
15926 | else | |
15927 | { | |
15928 | /* If we got here, we have branch-relaxation disabled, | |
15929 | and there's nothing we can do to fix this instruction | |
15930 | without turning it into a longer sequence. */ | |
15931 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15932 | _("Branch out of range")); | |
252b5132 | 15933 | } |
252b5132 RH |
15934 | break; |
15935 | ||
df58fc94 RS |
15936 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15937 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15938 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15939 | /* We adjust the offset back to even. */ | |
15940 | if ((*valP & 0x1) != 0) | |
15941 | --(*valP); | |
15942 | ||
15943 | if (! fixP->fx_done) | |
15944 | break; | |
15945 | ||
15946 | /* Should never visit here, because we keep the relocation. */ | |
15947 | abort (); | |
15948 | break; | |
15949 | ||
252b5132 RH |
15950 | case BFD_RELOC_VTABLE_INHERIT: |
15951 | fixP->fx_done = 0; | |
15952 | if (fixP->fx_addsy | |
15953 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15954 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15955 | S_SET_WEAK (fixP->fx_addsy); | |
15956 | break; | |
15957 | ||
15958 | case BFD_RELOC_VTABLE_ENTRY: | |
15959 | fixP->fx_done = 0; | |
15960 | break; | |
15961 | ||
15962 | default: | |
b37df7c4 | 15963 | abort (); |
252b5132 | 15964 | } |
a7ebbfdf TS |
15965 | |
15966 | /* Remember value for tc_gen_reloc. */ | |
15967 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15968 | } |
15969 | ||
252b5132 | 15970 | static symbolS * |
17a2f251 | 15971 | get_symbol (void) |
252b5132 RH |
15972 | { |
15973 | int c; | |
15974 | char *name; | |
15975 | symbolS *p; | |
15976 | ||
15977 | name = input_line_pointer; | |
15978 | c = get_symbol_end (); | |
15979 | p = (symbolS *) symbol_find_or_make (name); | |
15980 | *input_line_pointer = c; | |
15981 | return p; | |
15982 | } | |
15983 | ||
742a56fe RS |
15984 | /* Align the current frag to a given power of two. If a particular |
15985 | fill byte should be used, FILL points to an integer that contains | |
15986 | that byte, otherwise FILL is null. | |
15987 | ||
462427c4 RS |
15988 | This function used to have the comment: |
15989 | ||
15990 | The MIPS assembler also automatically adjusts any preceding label. | |
15991 | ||
15992 | The implementation therefore applied the adjustment to a maximum of | |
15993 | one label. However, other label adjustments are applied to batches | |
15994 | of labels, and adjusting just one caused problems when new labels | |
15995 | were added for the sake of debugging or unwind information. | |
15996 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15997 | |
15998 | static void | |
462427c4 | 15999 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16000 | { |
7d10b47d | 16001 | mips_emit_delays (); |
df58fc94 | 16002 | mips_record_compressed_mode (); |
742a56fe RS |
16003 | if (fill == NULL && subseg_text_p (now_seg)) |
16004 | frag_align_code (to, 0); | |
16005 | else | |
16006 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16007 | record_alignment (now_seg, to); |
462427c4 | 16008 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16009 | } |
16010 | ||
16011 | /* Align to a given power of two. .align 0 turns off the automatic | |
16012 | alignment used by the data creating pseudo-ops. */ | |
16013 | ||
16014 | static void | |
17a2f251 | 16015 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16016 | { |
742a56fe | 16017 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16018 | long max_alignment = 28; |
252b5132 | 16019 | |
54f4ddb3 | 16020 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16021 | to the aligned address. |
54f4ddb3 | 16022 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16023 | a .align pseudo instruction. |
54f4ddb3 | 16024 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16025 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16026 | We don't. */ |
252b5132 RH |
16027 | |
16028 | temp = get_absolute_expression (); | |
16029 | if (temp > max_alignment) | |
16030 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16031 | else if (temp < 0) | |
16032 | { | |
16033 | as_warn (_("Alignment negative: 0 assumed.")); | |
16034 | temp = 0; | |
16035 | } | |
16036 | if (*input_line_pointer == ',') | |
16037 | { | |
f9419b05 | 16038 | ++input_line_pointer; |
742a56fe RS |
16039 | fill_value = get_absolute_expression (); |
16040 | fill_ptr = &fill_value; | |
252b5132 RH |
16041 | } |
16042 | else | |
742a56fe | 16043 | fill_ptr = 0; |
252b5132 RH |
16044 | if (temp) |
16045 | { | |
a8dbcb85 TS |
16046 | segment_info_type *si = seg_info (now_seg); |
16047 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16048 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16049 | auto_align = 1; |
462427c4 | 16050 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16051 | } |
16052 | else | |
16053 | { | |
16054 | auto_align = 0; | |
16055 | } | |
16056 | ||
16057 | demand_empty_rest_of_line (); | |
16058 | } | |
16059 | ||
252b5132 | 16060 | static void |
17a2f251 | 16061 | s_change_sec (int sec) |
252b5132 RH |
16062 | { |
16063 | segT seg; | |
16064 | ||
252b5132 RH |
16065 | #ifdef OBJ_ELF |
16066 | /* The ELF backend needs to know that we are changing sections, so | |
16067 | that .previous works correctly. We could do something like check | |
b6ff326e | 16068 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16069 | as it would not be appropriate to use it in the section changing |
16070 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16071 | This should be cleaner, somehow. */ | |
f43abd2b TS |
16072 | if (IS_ELF) |
16073 | obj_elf_section_change_hook (); | |
252b5132 RH |
16074 | #endif |
16075 | ||
7d10b47d | 16076 | mips_emit_delays (); |
6a32d874 | 16077 | |
252b5132 RH |
16078 | switch (sec) |
16079 | { | |
16080 | case 't': | |
16081 | s_text (0); | |
16082 | break; | |
16083 | case 'd': | |
16084 | s_data (0); | |
16085 | break; | |
16086 | case 'b': | |
16087 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16088 | demand_empty_rest_of_line (); | |
16089 | break; | |
16090 | ||
16091 | case 'r': | |
4d0d148d TS |
16092 | seg = subseg_new (RDATA_SECTION_NAME, |
16093 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 16094 | if (IS_ELF) |
252b5132 | 16095 | { |
4d0d148d TS |
16096 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16097 | | SEC_READONLY | SEC_RELOC | |
16098 | | SEC_DATA)); | |
c41e87e3 | 16099 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16100 | record_alignment (seg, 4); |
252b5132 | 16101 | } |
4d0d148d | 16102 | demand_empty_rest_of_line (); |
252b5132 RH |
16103 | break; |
16104 | ||
16105 | case 's': | |
4d0d148d | 16106 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 16107 | if (IS_ELF) |
252b5132 | 16108 | { |
4d0d148d TS |
16109 | bfd_set_section_flags (stdoutput, seg, |
16110 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16111 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16112 | record_alignment (seg, 4); |
252b5132 | 16113 | } |
4d0d148d TS |
16114 | demand_empty_rest_of_line (); |
16115 | break; | |
998b3c36 MR |
16116 | |
16117 | case 'B': | |
16118 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16119 | if (IS_ELF) | |
16120 | { | |
16121 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16122 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16123 | record_alignment (seg, 4); | |
16124 | } | |
16125 | demand_empty_rest_of_line (); | |
16126 | break; | |
252b5132 RH |
16127 | } |
16128 | ||
16129 | auto_align = 1; | |
16130 | } | |
b34976b6 | 16131 | |
cca86cc8 | 16132 | void |
17a2f251 | 16133 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16134 | { |
7ed4a06a | 16135 | #ifdef OBJ_ELF |
cca86cc8 SC |
16136 | char *section_name; |
16137 | char c; | |
684022ea | 16138 | char next_c = 0; |
cca86cc8 SC |
16139 | int section_type; |
16140 | int section_flag; | |
16141 | int section_entry_size; | |
16142 | int section_alignment; | |
b34976b6 | 16143 | |
f43abd2b | 16144 | if (!IS_ELF) |
7ed4a06a TS |
16145 | return; |
16146 | ||
cca86cc8 SC |
16147 | section_name = input_line_pointer; |
16148 | c = get_symbol_end (); | |
a816d1ed AO |
16149 | if (c) |
16150 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16151 | |
4cf0dd0d TS |
16152 | /* Do we have .section Name<,"flags">? */ |
16153 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16154 | { |
4cf0dd0d TS |
16155 | /* just after name is now '\0'. */ |
16156 | *input_line_pointer = c; | |
cca86cc8 SC |
16157 | input_line_pointer = section_name; |
16158 | obj_elf_section (ignore); | |
16159 | return; | |
16160 | } | |
16161 | input_line_pointer++; | |
16162 | ||
16163 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16164 | if (c == ',') | |
16165 | section_type = get_absolute_expression (); | |
16166 | else | |
16167 | section_type = 0; | |
16168 | if (*input_line_pointer++ == ',') | |
16169 | section_flag = get_absolute_expression (); | |
16170 | else | |
16171 | section_flag = 0; | |
16172 | if (*input_line_pointer++ == ',') | |
16173 | section_entry_size = get_absolute_expression (); | |
16174 | else | |
16175 | section_entry_size = 0; | |
16176 | if (*input_line_pointer++ == ',') | |
16177 | section_alignment = get_absolute_expression (); | |
16178 | else | |
16179 | section_alignment = 0; | |
87975d2a AM |
16180 | /* FIXME: really ignore? */ |
16181 | (void) section_alignment; | |
cca86cc8 | 16182 | |
a816d1ed AO |
16183 | section_name = xstrdup (section_name); |
16184 | ||
8ab8a5c8 RS |
16185 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16186 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16187 | traditionally had to fall back on the more common @progbits instead. | |
16188 | ||
16189 | There's nothing really harmful in this, since bfd will correct | |
16190 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16191 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16192 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16193 | ||
16194 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16195 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16196 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16197 | generic type-checking code. */ | |
16198 | if (section_type == SHT_MIPS_DWARF) | |
16199 | section_type = SHT_PROGBITS; | |
16200 | ||
cca86cc8 SC |
16201 | obj_elf_change_section (section_name, section_type, section_flag, |
16202 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16203 | |
16204 | if (now_seg->name != section_name) | |
16205 | free (section_name); | |
7ed4a06a | 16206 | #endif /* OBJ_ELF */ |
cca86cc8 | 16207 | } |
252b5132 RH |
16208 | |
16209 | void | |
17a2f251 | 16210 | mips_enable_auto_align (void) |
252b5132 RH |
16211 | { |
16212 | auto_align = 1; | |
16213 | } | |
16214 | ||
16215 | static void | |
17a2f251 | 16216 | s_cons (int log_size) |
252b5132 | 16217 | { |
a8dbcb85 TS |
16218 | segment_info_type *si = seg_info (now_seg); |
16219 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16220 | |
7d10b47d | 16221 | mips_emit_delays (); |
252b5132 | 16222 | if (log_size > 0 && auto_align) |
462427c4 | 16223 | mips_align (log_size, 0, l); |
252b5132 | 16224 | cons (1 << log_size); |
a1facbec | 16225 | mips_clear_insn_labels (); |
252b5132 RH |
16226 | } |
16227 | ||
16228 | static void | |
17a2f251 | 16229 | s_float_cons (int type) |
252b5132 | 16230 | { |
a8dbcb85 TS |
16231 | segment_info_type *si = seg_info (now_seg); |
16232 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16233 | |
7d10b47d | 16234 | mips_emit_delays (); |
252b5132 RH |
16235 | |
16236 | if (auto_align) | |
49309057 ILT |
16237 | { |
16238 | if (type == 'd') | |
462427c4 | 16239 | mips_align (3, 0, l); |
49309057 | 16240 | else |
462427c4 | 16241 | mips_align (2, 0, l); |
49309057 | 16242 | } |
252b5132 | 16243 | |
252b5132 | 16244 | float_cons (type); |
a1facbec | 16245 | mips_clear_insn_labels (); |
252b5132 RH |
16246 | } |
16247 | ||
16248 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16249 | permitted to say | |
16250 | .globl foo .text | |
16251 | where foo is an undefined symbol, to mean that foo should be | |
16252 | considered to be the address of a function. */ | |
16253 | ||
16254 | static void | |
17a2f251 | 16255 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16256 | { |
16257 | char *name; | |
16258 | int c; | |
16259 | symbolS *symbolP; | |
16260 | flagword flag; | |
16261 | ||
8a06b769 | 16262 | do |
252b5132 | 16263 | { |
8a06b769 | 16264 | name = input_line_pointer; |
252b5132 | 16265 | c = get_symbol_end (); |
8a06b769 TS |
16266 | symbolP = symbol_find_or_make (name); |
16267 | S_SET_EXTERNAL (symbolP); | |
16268 | ||
252b5132 | 16269 | *input_line_pointer = c; |
8a06b769 | 16270 | SKIP_WHITESPACE (); |
252b5132 | 16271 | |
8a06b769 TS |
16272 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16273 | being a function is apparently labelled as being an object. */ | |
16274 | flag = BSF_OBJECT; | |
252b5132 | 16275 | |
8a06b769 TS |
16276 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16277 | && (*input_line_pointer != ',')) | |
16278 | { | |
16279 | char *secname; | |
16280 | asection *sec; | |
16281 | ||
16282 | secname = input_line_pointer; | |
16283 | c = get_symbol_end (); | |
16284 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16285 | if (sec == NULL) | |
16286 | as_bad (_("%s: no such section"), secname); | |
16287 | *input_line_pointer = c; | |
16288 | ||
16289 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16290 | flag = BSF_FUNCTION; | |
16291 | } | |
16292 | ||
16293 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16294 | ||
16295 | c = *input_line_pointer; | |
16296 | if (c == ',') | |
16297 | { | |
16298 | input_line_pointer++; | |
16299 | SKIP_WHITESPACE (); | |
16300 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16301 | c = '\n'; | |
16302 | } | |
16303 | } | |
16304 | while (c == ','); | |
252b5132 | 16305 | |
252b5132 RH |
16306 | demand_empty_rest_of_line (); |
16307 | } | |
16308 | ||
16309 | static void | |
17a2f251 | 16310 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16311 | { |
16312 | char *opt; | |
16313 | char c; | |
16314 | ||
16315 | opt = input_line_pointer; | |
16316 | c = get_symbol_end (); | |
16317 | ||
16318 | if (*opt == 'O') | |
16319 | { | |
16320 | /* FIXME: What does this mean? */ | |
16321 | } | |
16322 | else if (strncmp (opt, "pic", 3) == 0) | |
16323 | { | |
16324 | int i; | |
16325 | ||
16326 | i = atoi (opt + 3); | |
16327 | if (i == 0) | |
16328 | mips_pic = NO_PIC; | |
16329 | else if (i == 2) | |
143d77c5 | 16330 | { |
8b828383 | 16331 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16332 | mips_abicalls = TRUE; |
16333 | } | |
252b5132 RH |
16334 | else |
16335 | as_bad (_(".option pic%d not supported"), i); | |
16336 | ||
4d0d148d | 16337 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16338 | { |
16339 | if (g_switch_seen && g_switch_value != 0) | |
16340 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16341 | g_switch_value = 0; | |
16342 | bfd_set_gp_size (stdoutput, 0); | |
16343 | } | |
16344 | } | |
16345 | else | |
16346 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16347 | ||
16348 | *input_line_pointer = c; | |
16349 | demand_empty_rest_of_line (); | |
16350 | } | |
16351 | ||
16352 | /* This structure is used to hold a stack of .set values. */ | |
16353 | ||
e972090a NC |
16354 | struct mips_option_stack |
16355 | { | |
252b5132 RH |
16356 | struct mips_option_stack *next; |
16357 | struct mips_set_options options; | |
16358 | }; | |
16359 | ||
16360 | static struct mips_option_stack *mips_opts_stack; | |
16361 | ||
16362 | /* Handle the .set pseudo-op. */ | |
16363 | ||
16364 | static void | |
17a2f251 | 16365 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16366 | { |
16367 | char *name = input_line_pointer, ch; | |
16368 | ||
16369 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16370 | ++input_line_pointer; |
252b5132 RH |
16371 | ch = *input_line_pointer; |
16372 | *input_line_pointer = '\0'; | |
16373 | ||
16374 | if (strcmp (name, "reorder") == 0) | |
16375 | { | |
7d10b47d RS |
16376 | if (mips_opts.noreorder) |
16377 | end_noreorder (); | |
252b5132 RH |
16378 | } |
16379 | else if (strcmp (name, "noreorder") == 0) | |
16380 | { | |
7d10b47d RS |
16381 | if (!mips_opts.noreorder) |
16382 | start_noreorder (); | |
252b5132 | 16383 | } |
741fe287 MR |
16384 | else if (strncmp (name, "at=", 3) == 0) |
16385 | { | |
16386 | char *s = name + 3; | |
16387 | ||
16388 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16389 | as_bad (_("Unrecognized register name `%s'"), s); | |
16390 | } | |
252b5132 RH |
16391 | else if (strcmp (name, "at") == 0) |
16392 | { | |
741fe287 | 16393 | mips_opts.at = ATREG; |
252b5132 RH |
16394 | } |
16395 | else if (strcmp (name, "noat") == 0) | |
16396 | { | |
741fe287 | 16397 | mips_opts.at = ZERO; |
252b5132 RH |
16398 | } |
16399 | else if (strcmp (name, "macro") == 0) | |
16400 | { | |
16401 | mips_opts.warn_about_macros = 0; | |
16402 | } | |
16403 | else if (strcmp (name, "nomacro") == 0) | |
16404 | { | |
16405 | if (mips_opts.noreorder == 0) | |
16406 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16407 | mips_opts.warn_about_macros = 1; | |
16408 | } | |
16409 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16410 | { | |
16411 | mips_opts.nomove = 0; | |
16412 | } | |
16413 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16414 | { | |
16415 | mips_opts.nomove = 1; | |
16416 | } | |
16417 | else if (strcmp (name, "bopt") == 0) | |
16418 | { | |
16419 | mips_opts.nobopt = 0; | |
16420 | } | |
16421 | else if (strcmp (name, "nobopt") == 0) | |
16422 | { | |
16423 | mips_opts.nobopt = 1; | |
16424 | } | |
ad3fea08 TS |
16425 | else if (strcmp (name, "gp=default") == 0) |
16426 | mips_opts.gp32 = file_mips_gp32; | |
16427 | else if (strcmp (name, "gp=32") == 0) | |
16428 | mips_opts.gp32 = 1; | |
16429 | else if (strcmp (name, "gp=64") == 0) | |
16430 | { | |
16431 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16432 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16433 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16434 | mips_opts.gp32 = 0; | |
16435 | } | |
16436 | else if (strcmp (name, "fp=default") == 0) | |
16437 | mips_opts.fp32 = file_mips_fp32; | |
16438 | else if (strcmp (name, "fp=32") == 0) | |
16439 | mips_opts.fp32 = 1; | |
16440 | else if (strcmp (name, "fp=64") == 0) | |
16441 | { | |
16442 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16443 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16444 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16445 | mips_opts.fp32 = 0; | |
16446 | } | |
037b32b9 AN |
16447 | else if (strcmp (name, "softfloat") == 0) |
16448 | mips_opts.soft_float = 1; | |
16449 | else if (strcmp (name, "hardfloat") == 0) | |
16450 | mips_opts.soft_float = 0; | |
16451 | else if (strcmp (name, "singlefloat") == 0) | |
16452 | mips_opts.single_float = 1; | |
16453 | else if (strcmp (name, "doublefloat") == 0) | |
16454 | mips_opts.single_float = 0; | |
252b5132 RH |
16455 | else if (strcmp (name, "mips16") == 0 |
16456 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16457 | { |
16458 | if (mips_opts.micromips == 1) | |
16459 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16460 | mips_opts.mips16 = 1; | |
16461 | } | |
252b5132 RH |
16462 | else if (strcmp (name, "nomips16") == 0 |
16463 | || strcmp (name, "noMIPS-16") == 0) | |
16464 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16465 | else if (strcmp (name, "micromips") == 0) |
16466 | { | |
16467 | if (mips_opts.mips16 == 1) | |
16468 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16469 | mips_opts.micromips = 1; | |
16470 | } | |
16471 | else if (strcmp (name, "nomicromips") == 0) | |
16472 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16473 | else if (strcmp (name, "smartmips") == 0) |
16474 | { | |
ad3fea08 | 16475 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16476 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16477 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16478 | mips_opts.ase_smartmips = 1; | |
16479 | } | |
16480 | else if (strcmp (name, "nosmartmips") == 0) | |
16481 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16482 | else if (strcmp (name, "mips3d") == 0) |
16483 | mips_opts.ase_mips3d = 1; | |
16484 | else if (strcmp (name, "nomips3d") == 0) | |
16485 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16486 | else if (strcmp (name, "mdmx") == 0) |
16487 | mips_opts.ase_mdmx = 1; | |
16488 | else if (strcmp (name, "nomdmx") == 0) | |
16489 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16490 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16491 | { |
16492 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16493 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16494 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16495 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16496 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16497 | } |
74cd071d | 16498 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16499 | { |
16500 | mips_opts.ase_dsp = 0; | |
16501 | mips_opts.ase_dspr2 = 0; | |
16502 | } | |
16503 | else if (strcmp (name, "dspr2") == 0) | |
16504 | { | |
16505 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16506 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16507 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16508 | mips_opts.ase_dspr2 = 1; | |
16509 | mips_opts.ase_dsp = 1; | |
16510 | } | |
16511 | else if (strcmp (name, "nodspr2") == 0) | |
16512 | { | |
16513 | mips_opts.ase_dspr2 = 0; | |
16514 | mips_opts.ase_dsp = 0; | |
16515 | } | |
ef2e4d86 | 16516 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16517 | { |
16518 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16519 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16520 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16521 | mips_opts.ase_mt = 1; | |
16522 | } | |
ef2e4d86 CF |
16523 | else if (strcmp (name, "nomt") == 0) |
16524 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16525 | else if (strcmp (name, "mcu") == 0) |
16526 | mips_opts.ase_mcu = 1; | |
16527 | else if (strcmp (name, "nomcu") == 0) | |
16528 | mips_opts.ase_mcu = 0; | |
b015e599 AP |
16529 | else if (strcmp (name, "virt") == 0) |
16530 | { | |
16531 | if (!ISA_SUPPORTS_VIRT_ASE) | |
16532 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
16533 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
16534 | mips_opts.ase_virt = 1; | |
16535 | } | |
16536 | else if (strcmp (name, "novirt") == 0) | |
16537 | mips_opts.ase_virt = 0; | |
1a2c1fad | 16538 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16539 | { |
af7ee8bf | 16540 | int reset = 0; |
252b5132 | 16541 | |
1a2c1fad CD |
16542 | /* Permit the user to change the ISA and architecture on the fly. |
16543 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16544 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16545 | { |
16546 | reset = 1; | |
16547 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16548 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16549 | } |
16550 | else if (strncmp (name, "arch=", 5) == 0) | |
16551 | { | |
16552 | const struct mips_cpu_info *p; | |
16553 | ||
16554 | p = mips_parse_cpu("internal use", name + 5); | |
16555 | if (!p) | |
16556 | as_bad (_("unknown architecture %s"), name + 5); | |
16557 | else | |
16558 | { | |
16559 | mips_opts.arch = p->cpu; | |
16560 | mips_opts.isa = p->isa; | |
16561 | } | |
16562 | } | |
81a21e38 TS |
16563 | else if (strncmp (name, "mips", 4) == 0) |
16564 | { | |
16565 | const struct mips_cpu_info *p; | |
16566 | ||
16567 | p = mips_parse_cpu("internal use", name); | |
16568 | if (!p) | |
16569 | as_bad (_("unknown ISA level %s"), name + 4); | |
16570 | else | |
16571 | { | |
16572 | mips_opts.arch = p->cpu; | |
16573 | mips_opts.isa = p->isa; | |
16574 | } | |
16575 | } | |
af7ee8bf | 16576 | else |
81a21e38 | 16577 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16578 | |
16579 | switch (mips_opts.isa) | |
98d3f06f KH |
16580 | { |
16581 | case 0: | |
98d3f06f | 16582 | break; |
af7ee8bf CD |
16583 | case ISA_MIPS1: |
16584 | case ISA_MIPS2: | |
16585 | case ISA_MIPS32: | |
16586 | case ISA_MIPS32R2: | |
98d3f06f KH |
16587 | mips_opts.gp32 = 1; |
16588 | mips_opts.fp32 = 1; | |
16589 | break; | |
af7ee8bf CD |
16590 | case ISA_MIPS3: |
16591 | case ISA_MIPS4: | |
16592 | case ISA_MIPS5: | |
16593 | case ISA_MIPS64: | |
5f74bc13 | 16594 | case ISA_MIPS64R2: |
98d3f06f | 16595 | mips_opts.gp32 = 0; |
e407c74b NC |
16596 | if (mips_opts.arch == CPU_R5900) |
16597 | { | |
16598 | mips_opts.fp32 = 1; | |
16599 | } | |
16600 | else | |
16601 | { | |
98d3f06f | 16602 | mips_opts.fp32 = 0; |
e407c74b | 16603 | } |
98d3f06f KH |
16604 | break; |
16605 | default: | |
16606 | as_bad (_("unknown ISA level %s"), name + 4); | |
16607 | break; | |
16608 | } | |
af7ee8bf | 16609 | if (reset) |
98d3f06f | 16610 | { |
af7ee8bf CD |
16611 | mips_opts.gp32 = file_mips_gp32; |
16612 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16613 | } |
252b5132 RH |
16614 | } |
16615 | else if (strcmp (name, "autoextend") == 0) | |
16616 | mips_opts.noautoextend = 0; | |
16617 | else if (strcmp (name, "noautoextend") == 0) | |
16618 | mips_opts.noautoextend = 1; | |
16619 | else if (strcmp (name, "push") == 0) | |
16620 | { | |
16621 | struct mips_option_stack *s; | |
16622 | ||
16623 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16624 | s->next = mips_opts_stack; | |
16625 | s->options = mips_opts; | |
16626 | mips_opts_stack = s; | |
16627 | } | |
16628 | else if (strcmp (name, "pop") == 0) | |
16629 | { | |
16630 | struct mips_option_stack *s; | |
16631 | ||
16632 | s = mips_opts_stack; | |
16633 | if (s == NULL) | |
16634 | as_bad (_(".set pop with no .set push")); | |
16635 | else | |
16636 | { | |
16637 | /* If we're changing the reorder mode we need to handle | |
16638 | delay slots correctly. */ | |
16639 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16640 | start_noreorder (); |
252b5132 | 16641 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16642 | end_noreorder (); |
252b5132 RH |
16643 | |
16644 | mips_opts = s->options; | |
16645 | mips_opts_stack = s->next; | |
16646 | free (s); | |
16647 | } | |
16648 | } | |
aed1a261 RS |
16649 | else if (strcmp (name, "sym32") == 0) |
16650 | mips_opts.sym32 = TRUE; | |
16651 | else if (strcmp (name, "nosym32") == 0) | |
16652 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16653 | else if (strchr (name, ',')) |
16654 | { | |
16655 | /* Generic ".set" directive; use the generic handler. */ | |
16656 | *input_line_pointer = ch; | |
16657 | input_line_pointer = name; | |
16658 | s_set (0); | |
16659 | return; | |
16660 | } | |
252b5132 RH |
16661 | else |
16662 | { | |
16663 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16664 | } | |
16665 | *input_line_pointer = ch; | |
16666 | demand_empty_rest_of_line (); | |
16667 | } | |
16668 | ||
16669 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16670 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16671 | ||
16672 | static void | |
17a2f251 | 16673 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16674 | { |
16675 | mips_pic = SVR4_PIC; | |
143d77c5 | 16676 | mips_abicalls = TRUE; |
4d0d148d TS |
16677 | |
16678 | if (g_switch_seen && g_switch_value != 0) | |
16679 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16680 | g_switch_value = 0; | |
16681 | ||
252b5132 RH |
16682 | bfd_set_gp_size (stdoutput, 0); |
16683 | demand_empty_rest_of_line (); | |
16684 | } | |
16685 | ||
16686 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16687 | PIC code. It sets the $gp register for the function based on the | |
16688 | function address, which is in the register named in the argument. | |
16689 | This uses a relocation against _gp_disp, which is handled specially | |
16690 | by the linker. The result is: | |
16691 | lui $gp,%hi(_gp_disp) | |
16692 | addiu $gp,$gp,%lo(_gp_disp) | |
16693 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16694 | The .cpload argument is normally $25 == $t9. |
16695 | ||
16696 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16697 | lui $gp,%hi(__gnu_local_gp) |
16698 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16699 | and the argument is ignored. This saves an instruction, but the |
16700 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16701 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16702 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16703 | |
16704 | static void | |
17a2f251 | 16705 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16706 | { |
16707 | expressionS ex; | |
aa6975fb ILT |
16708 | int reg; |
16709 | int in_shared; | |
252b5132 | 16710 | |
6478892d TS |
16711 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16712 | .cpload is ignored. */ | |
16713 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16714 | { |
16715 | s_ignore (0); | |
16716 | return; | |
16717 | } | |
16718 | ||
a276b80c MR |
16719 | if (mips_opts.mips16) |
16720 | { | |
16721 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16722 | ignore_rest_of_line (); | |
16723 | return; | |
16724 | } | |
16725 | ||
d3ecfc59 | 16726 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16727 | if (mips_opts.noreorder == 0) |
16728 | as_warn (_(".cpload not in noreorder section")); | |
16729 | ||
aa6975fb ILT |
16730 | reg = tc_get_register (0); |
16731 | ||
16732 | /* If we need to produce a 64-bit address, we are better off using | |
16733 | the default instruction sequence. */ | |
aed1a261 | 16734 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16735 | |
252b5132 | 16736 | ex.X_op = O_symbol; |
bbe506e8 TS |
16737 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16738 | "__gnu_local_gp"); | |
252b5132 RH |
16739 | ex.X_op_symbol = NULL; |
16740 | ex.X_add_number = 0; | |
16741 | ||
16742 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16743 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16744 | |
8a75745d MR |
16745 | mips_mark_labels (); |
16746 | mips_assembling_insn = TRUE; | |
16747 | ||
584892a6 | 16748 | macro_start (); |
67c0d1eb RS |
16749 | macro_build_lui (&ex, mips_gp_register); |
16750 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16751 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16752 | if (in_shared) |
16753 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16754 | mips_gp_register, reg); | |
584892a6 | 16755 | macro_end (); |
252b5132 | 16756 | |
8a75745d | 16757 | mips_assembling_insn = FALSE; |
252b5132 RH |
16758 | demand_empty_rest_of_line (); |
16759 | } | |
16760 | ||
6478892d TS |
16761 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16762 | .cpsetup $reg1, offset|$reg2, label | |
16763 | ||
16764 | If offset is given, this results in: | |
16765 | sd $gp, offset($sp) | |
956cd1d6 | 16766 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16767 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16768 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16769 | |
16770 | If $reg2 is given, this results in: | |
16771 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16772 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16773 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16774 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16775 | $reg1 is normally $25 == $t9. |
16776 | ||
16777 | The -mno-shared option replaces the last three instructions with | |
16778 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16779 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16780 | |
6478892d | 16781 | static void |
17a2f251 | 16782 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16783 | { |
16784 | expressionS ex_off; | |
16785 | expressionS ex_sym; | |
16786 | int reg1; | |
6478892d | 16787 | |
8586fc66 | 16788 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16789 | We also need NewABI support. */ |
16790 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16791 | { | |
16792 | s_ignore (0); | |
16793 | return; | |
16794 | } | |
16795 | ||
a276b80c MR |
16796 | if (mips_opts.mips16) |
16797 | { | |
16798 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16799 | ignore_rest_of_line (); | |
16800 | return; | |
16801 | } | |
16802 | ||
6478892d TS |
16803 | reg1 = tc_get_register (0); |
16804 | SKIP_WHITESPACE (); | |
16805 | if (*input_line_pointer != ',') | |
16806 | { | |
16807 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16808 | return; | |
16809 | } | |
16810 | else | |
80245285 | 16811 | ++input_line_pointer; |
6478892d TS |
16812 | SKIP_WHITESPACE (); |
16813 | if (*input_line_pointer == '$') | |
80245285 TS |
16814 | { |
16815 | mips_cpreturn_register = tc_get_register (0); | |
16816 | mips_cpreturn_offset = -1; | |
16817 | } | |
6478892d | 16818 | else |
80245285 TS |
16819 | { |
16820 | mips_cpreturn_offset = get_absolute_expression (); | |
16821 | mips_cpreturn_register = -1; | |
16822 | } | |
6478892d TS |
16823 | SKIP_WHITESPACE (); |
16824 | if (*input_line_pointer != ',') | |
16825 | { | |
16826 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16827 | return; | |
16828 | } | |
16829 | else | |
f9419b05 | 16830 | ++input_line_pointer; |
6478892d | 16831 | SKIP_WHITESPACE (); |
f21f8242 | 16832 | expression (&ex_sym); |
6478892d | 16833 | |
8a75745d MR |
16834 | mips_mark_labels (); |
16835 | mips_assembling_insn = TRUE; | |
16836 | ||
584892a6 | 16837 | macro_start (); |
6478892d TS |
16838 | if (mips_cpreturn_register == -1) |
16839 | { | |
16840 | ex_off.X_op = O_constant; | |
16841 | ex_off.X_add_symbol = NULL; | |
16842 | ex_off.X_op_symbol = NULL; | |
16843 | ex_off.X_add_number = mips_cpreturn_offset; | |
16844 | ||
67c0d1eb | 16845 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16846 | BFD_RELOC_LO16, SP); |
6478892d TS |
16847 | } |
16848 | else | |
67c0d1eb | 16849 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16850 | mips_gp_register, 0); |
6478892d | 16851 | |
aed1a261 | 16852 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16853 | { |
df58fc94 | 16854 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16855 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16856 | BFD_RELOC_HI16_S); | |
16857 | ||
16858 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16859 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16860 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16861 | ||
16862 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16863 | mips_gp_register, reg1); | |
16864 | } | |
16865 | else | |
16866 | { | |
16867 | expressionS ex; | |
16868 | ||
16869 | ex.X_op = O_symbol; | |
4184909a | 16870 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16871 | ex.X_op_symbol = NULL; |
16872 | ex.X_add_number = 0; | |
6e1304d8 | 16873 | |
aa6975fb ILT |
16874 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16875 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16876 | ||
16877 | macro_build_lui (&ex, mips_gp_register); | |
16878 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16879 | mips_gp_register, BFD_RELOC_LO16); | |
16880 | } | |
f21f8242 | 16881 | |
584892a6 | 16882 | macro_end (); |
6478892d | 16883 | |
8a75745d | 16884 | mips_assembling_insn = FALSE; |
6478892d TS |
16885 | demand_empty_rest_of_line (); |
16886 | } | |
16887 | ||
16888 | static void | |
17a2f251 | 16889 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16890 | { |
16891 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16892 | .cplocal is ignored. */ |
6478892d TS |
16893 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16894 | { | |
16895 | s_ignore (0); | |
16896 | return; | |
16897 | } | |
16898 | ||
a276b80c MR |
16899 | if (mips_opts.mips16) |
16900 | { | |
16901 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16902 | ignore_rest_of_line (); | |
16903 | return; | |
16904 | } | |
16905 | ||
6478892d | 16906 | mips_gp_register = tc_get_register (0); |
85b51719 | 16907 | demand_empty_rest_of_line (); |
6478892d TS |
16908 | } |
16909 | ||
252b5132 RH |
16910 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16911 | offset from $sp. The offset is remembered, and after making a PIC | |
16912 | call $gp is restored from that location. */ | |
16913 | ||
16914 | static void | |
17a2f251 | 16915 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16916 | { |
16917 | expressionS ex; | |
252b5132 | 16918 | |
6478892d | 16919 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16920 | .cprestore is ignored. */ |
6478892d | 16921 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16922 | { |
16923 | s_ignore (0); | |
16924 | return; | |
16925 | } | |
16926 | ||
a276b80c MR |
16927 | if (mips_opts.mips16) |
16928 | { | |
16929 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16930 | ignore_rest_of_line (); | |
16931 | return; | |
16932 | } | |
16933 | ||
252b5132 | 16934 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16935 | mips_cprestore_valid = 1; |
252b5132 RH |
16936 | |
16937 | ex.X_op = O_constant; | |
16938 | ex.X_add_symbol = NULL; | |
16939 | ex.X_op_symbol = NULL; | |
16940 | ex.X_add_number = mips_cprestore_offset; | |
16941 | ||
8a75745d MR |
16942 | mips_mark_labels (); |
16943 | mips_assembling_insn = TRUE; | |
16944 | ||
584892a6 | 16945 | macro_start (); |
67c0d1eb RS |
16946 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16947 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16948 | macro_end (); |
252b5132 | 16949 | |
8a75745d | 16950 | mips_assembling_insn = FALSE; |
252b5132 RH |
16951 | demand_empty_rest_of_line (); |
16952 | } | |
16953 | ||
6478892d | 16954 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16955 | was given in the preceding .cpsetup, it results in: |
6478892d | 16956 | ld $gp, offset($sp) |
76b3015f | 16957 | |
6478892d | 16958 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16959 | daddu $gp, $reg2, $0 */ |
16960 | ||
6478892d | 16961 | static void |
17a2f251 | 16962 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16963 | { |
16964 | expressionS ex; | |
6478892d TS |
16965 | |
16966 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16967 | We also need NewABI support. */ | |
16968 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16969 | { | |
16970 | s_ignore (0); | |
16971 | return; | |
16972 | } | |
16973 | ||
a276b80c MR |
16974 | if (mips_opts.mips16) |
16975 | { | |
16976 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16977 | ignore_rest_of_line (); | |
16978 | return; | |
16979 | } | |
16980 | ||
8a75745d MR |
16981 | mips_mark_labels (); |
16982 | mips_assembling_insn = TRUE; | |
16983 | ||
584892a6 | 16984 | macro_start (); |
6478892d TS |
16985 | if (mips_cpreturn_register == -1) |
16986 | { | |
16987 | ex.X_op = O_constant; | |
16988 | ex.X_add_symbol = NULL; | |
16989 | ex.X_op_symbol = NULL; | |
16990 | ex.X_add_number = mips_cpreturn_offset; | |
16991 | ||
67c0d1eb | 16992 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16993 | } |
16994 | else | |
67c0d1eb | 16995 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16996 | mips_cpreturn_register, 0); |
584892a6 | 16997 | macro_end (); |
6478892d | 16998 | |
8a75745d | 16999 | mips_assembling_insn = FALSE; |
6478892d TS |
17000 | demand_empty_rest_of_line (); |
17001 | } | |
17002 | ||
d0f13682 CLT |
17003 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17004 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17005 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17006 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17007 | |
17008 | static void | |
d0f13682 CLT |
17009 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17010 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17011 | { |
17012 | expressionS ex; | |
17013 | char *p; | |
17014 | ||
17015 | expression (&ex); | |
17016 | ||
17017 | if (ex.X_op != O_symbol) | |
17018 | { | |
d0f13682 | 17019 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
17020 | ignore_rest_of_line (); |
17021 | } | |
17022 | ||
17023 | p = frag_more (bytes); | |
17024 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17025 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17026 | demand_empty_rest_of_line (); |
de64cffd | 17027 | mips_clear_insn_labels (); |
741d6ea8 JM |
17028 | } |
17029 | ||
17030 | /* Handle .dtprelword. */ | |
17031 | ||
17032 | static void | |
17033 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17034 | { | |
d0f13682 | 17035 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17036 | } |
17037 | ||
17038 | /* Handle .dtpreldword. */ | |
17039 | ||
17040 | static void | |
17041 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17042 | { | |
d0f13682 CLT |
17043 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17044 | } | |
17045 | ||
17046 | /* Handle .tprelword. */ | |
17047 | ||
17048 | static void | |
17049 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17050 | { | |
17051 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17052 | } | |
17053 | ||
17054 | /* Handle .tpreldword. */ | |
17055 | ||
17056 | static void | |
17057 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17058 | { | |
17059 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17060 | } |
17061 | ||
6478892d TS |
17062 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17063 | code. It sets the offset to use in gp_rel relocations. */ | |
17064 | ||
17065 | static void | |
17a2f251 | 17066 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17067 | { |
17068 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17069 | We also need NewABI support. */ | |
17070 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17071 | { | |
17072 | s_ignore (0); | |
17073 | return; | |
17074 | } | |
17075 | ||
def2e0dd | 17076 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17077 | |
17078 | demand_empty_rest_of_line (); | |
17079 | } | |
17080 | ||
252b5132 RH |
17081 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17082 | code. It generates a 32 bit GP relative reloc. */ | |
17083 | ||
17084 | static void | |
17a2f251 | 17085 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17086 | { |
a8dbcb85 TS |
17087 | segment_info_type *si; |
17088 | struct insn_label_list *l; | |
252b5132 RH |
17089 | expressionS ex; |
17090 | char *p; | |
17091 | ||
17092 | /* When not generating PIC code, this is treated as .word. */ | |
17093 | if (mips_pic != SVR4_PIC) | |
17094 | { | |
17095 | s_cons (2); | |
17096 | return; | |
17097 | } | |
17098 | ||
a8dbcb85 TS |
17099 | si = seg_info (now_seg); |
17100 | l = si->label_list; | |
7d10b47d | 17101 | mips_emit_delays (); |
252b5132 | 17102 | if (auto_align) |
462427c4 | 17103 | mips_align (2, 0, l); |
252b5132 RH |
17104 | |
17105 | expression (&ex); | |
a1facbec | 17106 | mips_clear_insn_labels (); |
252b5132 RH |
17107 | |
17108 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17109 | { | |
17110 | as_bad (_("Unsupported use of .gpword")); | |
17111 | ignore_rest_of_line (); | |
17112 | } | |
17113 | ||
17114 | p = frag_more (4); | |
17a2f251 | 17115 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17116 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17117 | BFD_RELOC_GPREL32); |
252b5132 RH |
17118 | |
17119 | demand_empty_rest_of_line (); | |
17120 | } | |
17121 | ||
10181a0d | 17122 | static void |
17a2f251 | 17123 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17124 | { |
a8dbcb85 TS |
17125 | segment_info_type *si; |
17126 | struct insn_label_list *l; | |
10181a0d AO |
17127 | expressionS ex; |
17128 | char *p; | |
17129 | ||
17130 | /* When not generating PIC code, this is treated as .dword. */ | |
17131 | if (mips_pic != SVR4_PIC) | |
17132 | { | |
17133 | s_cons (3); | |
17134 | return; | |
17135 | } | |
17136 | ||
a8dbcb85 TS |
17137 | si = seg_info (now_seg); |
17138 | l = si->label_list; | |
7d10b47d | 17139 | mips_emit_delays (); |
10181a0d | 17140 | if (auto_align) |
462427c4 | 17141 | mips_align (3, 0, l); |
10181a0d AO |
17142 | |
17143 | expression (&ex); | |
a1facbec | 17144 | mips_clear_insn_labels (); |
10181a0d AO |
17145 | |
17146 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17147 | { | |
17148 | as_bad (_("Unsupported use of .gpdword")); | |
17149 | ignore_rest_of_line (); | |
17150 | } | |
17151 | ||
17152 | p = frag_more (8); | |
17a2f251 | 17153 | md_number_to_chars (p, 0, 8); |
a105a300 | 17154 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17155 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17156 | |
17157 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17158 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17159 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17160 | |
17161 | demand_empty_rest_of_line (); | |
17162 | } | |
17163 | ||
a3f278e2 CM |
17164 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17165 | tables. It generates a R_MIPS_EH reloc. */ | |
17166 | ||
17167 | static void | |
17168 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17169 | { | |
17170 | expressionS ex; | |
17171 | char *p; | |
17172 | ||
17173 | mips_emit_delays (); | |
17174 | ||
17175 | expression (&ex); | |
17176 | mips_clear_insn_labels (); | |
17177 | ||
17178 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17179 | { | |
17180 | as_bad (_("Unsupported use of .ehword")); | |
17181 | ignore_rest_of_line (); | |
17182 | } | |
17183 | ||
17184 | p = frag_more (4); | |
17185 | md_number_to_chars (p, 0, 4); | |
17186 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17187 | BFD_RELOC_MIPS_EH); | |
17188 | ||
17189 | demand_empty_rest_of_line (); | |
17190 | } | |
17191 | ||
252b5132 RH |
17192 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17193 | tables in SVR4 PIC code. */ | |
17194 | ||
17195 | static void | |
17a2f251 | 17196 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17197 | { |
252b5132 RH |
17198 | int reg; |
17199 | ||
10181a0d AO |
17200 | /* This is ignored when not generating SVR4 PIC code. */ |
17201 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17202 | { |
17203 | s_ignore (0); | |
17204 | return; | |
17205 | } | |
17206 | ||
8a75745d MR |
17207 | mips_mark_labels (); |
17208 | mips_assembling_insn = TRUE; | |
17209 | ||
252b5132 | 17210 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17211 | macro_start (); |
252b5132 | 17212 | reg = tc_get_register (0); |
67c0d1eb | 17213 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17214 | macro_end (); |
252b5132 | 17215 | |
8a75745d | 17216 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17217 | demand_empty_rest_of_line (); |
252b5132 RH |
17218 | } |
17219 | ||
17220 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17221 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17222 | such as generating jalx instructions when needed. We also make |
17223 | them odd for the duration of the assembly, in order to generate the | |
17224 | right sort of code. We will make them even in the adjust_symtab | |
17225 | routine, while leaving them marked. This is convenient for the | |
17226 | debugger and the disassembler. The linker knows to make them odd | |
17227 | again. */ | |
17228 | ||
17229 | static void | |
17a2f251 | 17230 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17231 | { |
df58fc94 | 17232 | mips_mark_labels (); |
252b5132 RH |
17233 | |
17234 | demand_empty_rest_of_line (); | |
17235 | } | |
17236 | ||
754e2bb9 RS |
17237 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17238 | implemented in a transparent way, so that removing them would not | |
17239 | have any effect on the generated instructions. However, s_stab | |
17240 | internally changes the section, so in practice we need to decide | |
17241 | now whether the preceding label marks compressed code. We do not | |
17242 | support changing the compression mode of a label after a .stab* | |
17243 | directive, such as in: | |
17244 | ||
17245 | foo: | |
17246 | .stabs ... | |
17247 | .set mips16 | |
17248 | ||
17249 | so the current mode wins. */ | |
252b5132 RH |
17250 | |
17251 | static void | |
17a2f251 | 17252 | s_mips_stab (int type) |
252b5132 | 17253 | { |
754e2bb9 | 17254 | mips_mark_labels (); |
252b5132 RH |
17255 | s_stab (type); |
17256 | } | |
17257 | ||
54f4ddb3 | 17258 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17259 | |
17260 | static void | |
17a2f251 | 17261 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17262 | { |
17263 | char *name; | |
17264 | int c; | |
17265 | symbolS *symbolP; | |
17266 | expressionS exp; | |
17267 | ||
17268 | name = input_line_pointer; | |
17269 | c = get_symbol_end (); | |
17270 | symbolP = symbol_find_or_make (name); | |
17271 | S_SET_WEAK (symbolP); | |
17272 | *input_line_pointer = c; | |
17273 | ||
17274 | SKIP_WHITESPACE (); | |
17275 | ||
17276 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17277 | { | |
17278 | if (S_IS_DEFINED (symbolP)) | |
17279 | { | |
20203fb9 | 17280 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17281 | S_GET_NAME (symbolP)); |
17282 | ignore_rest_of_line (); | |
17283 | return; | |
17284 | } | |
bdaaa2e1 | 17285 | |
252b5132 RH |
17286 | if (*input_line_pointer == ',') |
17287 | { | |
17288 | ++input_line_pointer; | |
17289 | SKIP_WHITESPACE (); | |
17290 | } | |
bdaaa2e1 | 17291 | |
252b5132 RH |
17292 | expression (&exp); |
17293 | if (exp.X_op != O_symbol) | |
17294 | { | |
20203fb9 | 17295 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17296 | ignore_rest_of_line (); |
252b5132 RH |
17297 | return; |
17298 | } | |
49309057 | 17299 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17300 | } |
17301 | ||
17302 | demand_empty_rest_of_line (); | |
17303 | } | |
17304 | ||
17305 | /* Parse a register string into a number. Called from the ECOFF code | |
17306 | to parse .frame. The argument is non-zero if this is the frame | |
17307 | register, so that we can record it in mips_frame_reg. */ | |
17308 | ||
17309 | int | |
17a2f251 | 17310 | tc_get_register (int frame) |
252b5132 | 17311 | { |
707bfff6 | 17312 | unsigned int reg; |
252b5132 RH |
17313 | |
17314 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17315 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17316 | reg = 0; | |
252b5132 | 17317 | if (frame) |
7a621144 DJ |
17318 | { |
17319 | mips_frame_reg = reg != 0 ? reg : SP; | |
17320 | mips_frame_reg_valid = 1; | |
17321 | mips_cprestore_valid = 0; | |
17322 | } | |
252b5132 RH |
17323 | return reg; |
17324 | } | |
17325 | ||
17326 | valueT | |
17a2f251 | 17327 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17328 | { |
17329 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17330 | ||
b4c71f56 TS |
17331 | if (IS_ELF) |
17332 | { | |
17333 | /* We don't need to align ELF sections to the full alignment. | |
17334 | However, Irix 5 may prefer that we align them at least to a 16 | |
17335 | byte boundary. We don't bother to align the sections if we | |
17336 | are targeted for an embedded system. */ | |
c41e87e3 | 17337 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17338 | return addr; |
17339 | if (align > 4) | |
17340 | align = 4; | |
17341 | } | |
252b5132 RH |
17342 | |
17343 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17344 | } | |
17345 | ||
17346 | /* Utility routine, called from above as well. If called while the | |
17347 | input file is still being read, it's only an approximation. (For | |
17348 | example, a symbol may later become defined which appeared to be | |
17349 | undefined earlier.) */ | |
17350 | ||
17351 | static int | |
17a2f251 | 17352 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17353 | { |
17354 | if (sym == 0) | |
17355 | return 0; | |
17356 | ||
4d0d148d | 17357 | if (g_switch_value > 0) |
252b5132 RH |
17358 | { |
17359 | const char *symname; | |
17360 | int change; | |
17361 | ||
c9914766 | 17362 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17363 | register. It can be if it is smaller than the -G size or if |
17364 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17365 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17366 | they can. */ |
17367 | symname = S_GET_NAME (sym); | |
17368 | if (symname != (const char *) NULL | |
17369 | && (strcmp (symname, "eprol") == 0 | |
17370 | || strcmp (symname, "etext") == 0 | |
17371 | || strcmp (symname, "_gp") == 0 | |
17372 | || strcmp (symname, "edata") == 0 | |
17373 | || strcmp (symname, "_fbss") == 0 | |
17374 | || strcmp (symname, "_fdata") == 0 | |
17375 | || strcmp (symname, "_ftext") == 0 | |
17376 | || strcmp (symname, "end") == 0 | |
17377 | || strcmp (symname, "_gp_disp") == 0)) | |
17378 | change = 1; | |
17379 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17380 | && (0 | |
17381 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17382 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17383 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17384 | <= g_switch_value)) | |
252b5132 RH |
17385 | #endif |
17386 | /* We must defer this decision until after the whole | |
17387 | file has been read, since there might be a .extern | |
17388 | after the first use of this symbol. */ | |
17389 | || (before_relaxing | |
17390 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17391 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17392 | #endif |
17393 | && S_GET_VALUE (sym) == 0) | |
17394 | || (S_GET_VALUE (sym) != 0 | |
17395 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17396 | change = 0; | |
17397 | else | |
17398 | { | |
17399 | const char *segname; | |
17400 | ||
17401 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17402 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17403 | && strcmp (segname, ".lit4") != 0); |
17404 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17405 | && strcmp (segname, ".sbss") != 0 |
17406 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17407 | && strncmp (segname, ".sbss.", 6) != 0 |
17408 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17409 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17410 | } |
17411 | return change; | |
17412 | } | |
17413 | else | |
c9914766 | 17414 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17415 | return 1; |
17416 | } | |
17417 | ||
5919d012 RS |
17418 | |
17419 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17420 | ||
17421 | static bfd_boolean | |
17a2f251 | 17422 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17423 | { |
17424 | asection *symsec; | |
5919d012 RS |
17425 | |
17426 | /* Handle the case of a symbol equated to another symbol. */ | |
17427 | while (symbol_equated_reloc_p (sym)) | |
17428 | { | |
17429 | symbolS *n; | |
17430 | ||
5f0fe04b | 17431 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17432 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17433 | if (n == sym) | |
17434 | break; | |
17435 | sym = n; | |
17436 | } | |
17437 | ||
df1f3cda DD |
17438 | if (symbol_section_p (sym)) |
17439 | return TRUE; | |
17440 | ||
5919d012 RS |
17441 | symsec = S_GET_SEGMENT (sym); |
17442 | ||
5919d012 | 17443 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17444 | return (!bfd_is_und_section (symsec) |
17445 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17446 | && !bfd_is_com_section (symsec) |
17447 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17448 | #ifdef OBJ_ELF |
17449 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17450 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17451 | #endif |
17452 | ); | |
17453 | } | |
17454 | ||
17455 | ||
252b5132 RH |
17456 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17457 | extended opcode. SEC is the section the frag is in. */ | |
17458 | ||
17459 | static int | |
17a2f251 | 17460 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17461 | { |
17462 | int type; | |
3994f87e | 17463 | const struct mips16_immed_operand *op; |
252b5132 RH |
17464 | offsetT val; |
17465 | int mintiny, maxtiny; | |
17466 | segT symsec; | |
98aa84af | 17467 | fragS *sym_frag; |
252b5132 RH |
17468 | |
17469 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17470 | return 0; | |
17471 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17472 | return 1; | |
17473 | ||
17474 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17475 | op = mips16_immed_operands; | |
17476 | while (op->type != type) | |
17477 | { | |
17478 | ++op; | |
9c2799c2 | 17479 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17480 | } |
17481 | ||
17482 | if (op->unsp) | |
17483 | { | |
17484 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17485 | { | |
17486 | mintiny = 1; | |
17487 | maxtiny = 1 << op->nbits; | |
17488 | } | |
17489 | else | |
17490 | { | |
17491 | mintiny = 0; | |
17492 | maxtiny = (1 << op->nbits) - 1; | |
17493 | } | |
17494 | } | |
17495 | else | |
17496 | { | |
17497 | mintiny = - (1 << (op->nbits - 1)); | |
17498 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17499 | } | |
17500 | ||
98aa84af | 17501 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17502 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17503 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17504 | |
17505 | if (op->pcrel) | |
17506 | { | |
17507 | addressT addr; | |
17508 | ||
17509 | /* We won't have the section when we are called from | |
17510 | mips_relax_frag. However, we will always have been called | |
17511 | from md_estimate_size_before_relax first. If this is a | |
17512 | branch to a different section, we mark it as such. If SEC is | |
17513 | NULL, and the frag is not marked, then it must be a branch to | |
17514 | the same section. */ | |
17515 | if (sec == NULL) | |
17516 | { | |
17517 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17518 | return 1; | |
17519 | } | |
17520 | else | |
17521 | { | |
98aa84af | 17522 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17523 | if (symsec != sec) |
17524 | { | |
17525 | fragp->fr_subtype = | |
17526 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17527 | ||
17528 | /* FIXME: We should support this, and let the linker | |
17529 | catch branches and loads that are out of range. */ | |
17530 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17531 | _("unsupported PC relative reference to different section")); | |
17532 | ||
17533 | return 1; | |
17534 | } | |
98aa84af AM |
17535 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17536 | /* Assume non-extended on the first relaxation pass. | |
17537 | The address we have calculated will be bogus if this is | |
17538 | a forward branch to another frag, as the forward frag | |
17539 | will have fr_address == 0. */ | |
17540 | return 0; | |
252b5132 RH |
17541 | } |
17542 | ||
17543 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17544 | the same section. If the relax_marker of the symbol fragment |
17545 | differs from the relax_marker of this fragment, we have not | |
17546 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17547 | in STRETCH in order to get a better estimate of the address. |
17548 | This particularly matters because of the shift bits. */ | |
17549 | if (stretch != 0 | |
98aa84af | 17550 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17551 | { |
17552 | fragS *f; | |
17553 | ||
17554 | /* Adjust stretch for any alignment frag. Note that if have | |
17555 | been expanding the earlier code, the symbol may be | |
17556 | defined in what appears to be an earlier frag. FIXME: | |
17557 | This doesn't handle the fr_subtype field, which specifies | |
17558 | a maximum number of bytes to skip when doing an | |
17559 | alignment. */ | |
98aa84af | 17560 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17561 | { |
17562 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17563 | { | |
17564 | if (stretch < 0) | |
17565 | stretch = - ((- stretch) | |
17566 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17567 | else | |
17568 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17569 | if (stretch == 0) | |
17570 | break; | |
17571 | } | |
17572 | } | |
17573 | if (f != NULL) | |
17574 | val += stretch; | |
17575 | } | |
17576 | ||
17577 | addr = fragp->fr_address + fragp->fr_fix; | |
17578 | ||
17579 | /* The base address rules are complicated. The base address of | |
17580 | a branch is the following instruction. The base address of a | |
17581 | PC relative load or add is the instruction itself, but if it | |
17582 | is in a delay slot (in which case it can not be extended) use | |
17583 | the address of the instruction whose delay slot it is in. */ | |
17584 | if (type == 'p' || type == 'q') | |
17585 | { | |
17586 | addr += 2; | |
17587 | ||
17588 | /* If we are currently assuming that this frag should be | |
17589 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17590 | higher. */ |
252b5132 RH |
17591 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17592 | addr += 2; | |
17593 | ||
17594 | /* Ignore the low bit in the target, since it will be set | |
17595 | for a text label. */ | |
17596 | if ((val & 1) != 0) | |
17597 | --val; | |
17598 | } | |
17599 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17600 | addr -= 4; | |
17601 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17602 | addr -= 2; | |
17603 | ||
17604 | val -= addr & ~ ((1 << op->shift) - 1); | |
17605 | ||
17606 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17607 | if (type == 'p' || type == 'q') | |
17608 | val /= 2; | |
17609 | ||
17610 | /* If any of the shifted bits are set, we must use an extended | |
17611 | opcode. If the address depends on the size of this | |
17612 | instruction, this can lead to a loop, so we arrange to always | |
17613 | use an extended opcode. We only check this when we are in | |
17614 | the main relaxation loop, when SEC is NULL. */ | |
17615 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17616 | { | |
17617 | fragp->fr_subtype = | |
17618 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17619 | return 1; | |
17620 | } | |
17621 | ||
17622 | /* If we are about to mark a frag as extended because the value | |
17623 | is precisely maxtiny + 1, then there is a chance of an | |
17624 | infinite loop as in the following code: | |
17625 | la $4,foo | |
17626 | .skip 1020 | |
17627 | .align 2 | |
17628 | foo: | |
17629 | In this case when the la is extended, foo is 0x3fc bytes | |
17630 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17631 | the la must be extended. To avoid this loop, we mark the | |
17632 | frag as extended if it was small, and is about to become | |
17633 | extended with a value of maxtiny + 1. */ | |
17634 | if (val == ((maxtiny + 1) << op->shift) | |
17635 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17636 | && sec == NULL) | |
17637 | { | |
17638 | fragp->fr_subtype = | |
17639 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17640 | return 1; | |
17641 | } | |
17642 | } | |
17643 | else if (symsec != absolute_section && sec != NULL) | |
17644 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17645 | ||
17646 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17647 | || val < (mintiny << op->shift) | |
17648 | || val > (maxtiny << op->shift)) | |
17649 | return 1; | |
17650 | else | |
17651 | return 0; | |
17652 | } | |
17653 | ||
4a6a3df4 AO |
17654 | /* Compute the length of a branch sequence, and adjust the |
17655 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17656 | worst-case length is computed, with UPDATE being used to indicate | |
17657 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17658 | branch is to be computed. */ | |
17659 | static int | |
17a2f251 | 17660 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17661 | { |
b34976b6 | 17662 | bfd_boolean toofar; |
4a6a3df4 AO |
17663 | int length; |
17664 | ||
17665 | if (fragp | |
17666 | && S_IS_DEFINED (fragp->fr_symbol) | |
17667 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17668 | { | |
17669 | addressT addr; | |
17670 | offsetT val; | |
17671 | ||
17672 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17673 | ||
17674 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17675 | ||
17676 | val -= addr; | |
17677 | ||
17678 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17679 | } | |
17680 | else if (fragp) | |
17681 | /* If the symbol is not defined or it's in a different segment, | |
17682 | assume the user knows what's going on and emit a short | |
17683 | branch. */ | |
b34976b6 | 17684 | toofar = FALSE; |
4a6a3df4 | 17685 | else |
b34976b6 | 17686 | toofar = TRUE; |
4a6a3df4 AO |
17687 | |
17688 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17689 | fragp->fr_subtype | |
66b3e8da MR |
17690 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17691 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17692 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17693 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17694 | toofar); | |
17695 | ||
17696 | length = 4; | |
17697 | if (toofar) | |
17698 | { | |
17699 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17700 | length += 8; | |
17701 | ||
17702 | if (mips_pic != NO_PIC) | |
17703 | { | |
17704 | /* Additional space for PIC loading of target address. */ | |
17705 | length += 8; | |
17706 | if (mips_opts.isa == ISA_MIPS1) | |
17707 | /* Additional space for $at-stabilizing nop. */ | |
17708 | length += 4; | |
17709 | } | |
17710 | ||
17711 | /* If branch is conditional. */ | |
17712 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17713 | length += 8; | |
17714 | } | |
b34976b6 | 17715 | |
4a6a3df4 AO |
17716 | return length; |
17717 | } | |
17718 | ||
df58fc94 RS |
17719 | /* Compute the length of a branch sequence, and adjust the |
17720 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17721 | worst-case length is computed, with UPDATE being used to indicate | |
17722 | whether an unconditional (-1), or regular (0) branch is to be | |
17723 | computed. */ | |
17724 | ||
17725 | static int | |
17726 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17727 | { | |
17728 | bfd_boolean toofar; | |
17729 | int length; | |
17730 | ||
17731 | if (fragp | |
17732 | && S_IS_DEFINED (fragp->fr_symbol) | |
17733 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17734 | { | |
17735 | addressT addr; | |
17736 | offsetT val; | |
17737 | ||
17738 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17739 | /* Ignore the low bit in the target, since it will be set | |
17740 | for a text label. */ | |
17741 | if ((val & 1) != 0) | |
17742 | --val; | |
17743 | ||
17744 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17745 | ||
17746 | val -= addr; | |
17747 | ||
17748 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17749 | } | |
17750 | else if (fragp) | |
17751 | /* If the symbol is not defined or it's in a different segment, | |
17752 | assume the user knows what's going on and emit a short | |
17753 | branch. */ | |
17754 | toofar = FALSE; | |
17755 | else | |
17756 | toofar = TRUE; | |
17757 | ||
17758 | if (fragp && update | |
17759 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17760 | fragp->fr_subtype = (toofar | |
17761 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17762 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17763 | ||
17764 | length = 4; | |
17765 | if (toofar) | |
17766 | { | |
17767 | bfd_boolean compact_known = fragp != NULL; | |
17768 | bfd_boolean compact = FALSE; | |
17769 | bfd_boolean uncond; | |
17770 | ||
17771 | if (compact_known) | |
17772 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17773 | if (fragp) | |
17774 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17775 | else | |
17776 | uncond = update < 0; | |
17777 | ||
17778 | /* If label is out of range, we turn branch <br>: | |
17779 | ||
17780 | <br> label # 4 bytes | |
17781 | 0: | |
17782 | ||
17783 | into: | |
17784 | ||
17785 | j label # 4 bytes | |
17786 | nop # 2 bytes if compact && !PIC | |
17787 | 0: | |
17788 | */ | |
17789 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17790 | length += 2; | |
17791 | ||
17792 | /* If assembling PIC code, we further turn: | |
17793 | ||
17794 | j label # 4 bytes | |
17795 | ||
17796 | into: | |
17797 | ||
17798 | lw/ld at, %got(label)(gp) # 4 bytes | |
17799 | d/addiu at, %lo(label) # 4 bytes | |
17800 | jr/c at # 2 bytes | |
17801 | */ | |
17802 | if (mips_pic != NO_PIC) | |
17803 | length += 6; | |
17804 | ||
17805 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17806 | ||
17807 | <brneg> 0f # 4 bytes | |
17808 | nop # 2 bytes if !compact | |
17809 | */ | |
17810 | if (!uncond) | |
17811 | length += (compact_known && compact) ? 4 : 6; | |
17812 | } | |
17813 | ||
17814 | return length; | |
17815 | } | |
17816 | ||
17817 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17818 | bit accordingly. */ | |
17819 | ||
17820 | static int | |
17821 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17822 | { | |
17823 | bfd_boolean toofar; | |
17824 | ||
df58fc94 RS |
17825 | if (fragp |
17826 | && S_IS_DEFINED (fragp->fr_symbol) | |
17827 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17828 | { | |
17829 | addressT addr; | |
17830 | offsetT val; | |
17831 | int type; | |
17832 | ||
17833 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17834 | /* Ignore the low bit in the target, since it will be set | |
17835 | for a text label. */ | |
17836 | if ((val & 1) != 0) | |
17837 | --val; | |
17838 | ||
17839 | /* Assume this is a 2-byte branch. */ | |
17840 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17841 | ||
17842 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17843 | long branches. */ | |
17844 | ||
17845 | val -= addr; | |
17846 | ||
17847 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17848 | if (type == 'D') | |
17849 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17850 | else if (type == 'E') | |
17851 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17852 | else | |
17853 | abort (); | |
17854 | } | |
17855 | else | |
17856 | /* If the symbol is not defined or it's in a different segment, | |
17857 | we emit a normal 32-bit branch. */ | |
17858 | toofar = TRUE; | |
17859 | ||
17860 | if (fragp && update | |
17861 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17862 | fragp->fr_subtype | |
17863 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17864 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17865 | ||
17866 | if (toofar) | |
17867 | return 4; | |
17868 | ||
17869 | return 2; | |
17870 | } | |
17871 | ||
252b5132 RH |
17872 | /* Estimate the size of a frag before relaxing. Unless this is the |
17873 | mips16, we are not really relaxing here, and the final size is | |
17874 | encoded in the subtype information. For the mips16, we have to | |
17875 | decide whether we are using an extended opcode or not. */ | |
17876 | ||
252b5132 | 17877 | int |
17a2f251 | 17878 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17879 | { |
5919d012 | 17880 | int change; |
252b5132 | 17881 | |
4a6a3df4 AO |
17882 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17883 | { | |
17884 | ||
b34976b6 AM |
17885 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17886 | ||
4a6a3df4 AO |
17887 | return fragp->fr_var; |
17888 | } | |
17889 | ||
252b5132 | 17890 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17891 | /* We don't want to modify the EXTENDED bit here; it might get us |
17892 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17893 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17894 | |
df58fc94 RS |
17895 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17896 | { | |
17897 | int length = 4; | |
17898 | ||
17899 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17900 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17901 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17902 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17903 | fragp->fr_var = length; | |
17904 | ||
17905 | return length; | |
17906 | } | |
17907 | ||
252b5132 | 17908 | if (mips_pic == NO_PIC) |
5919d012 | 17909 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17910 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17911 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17912 | else if (mips_pic == VXWORKS_PIC) |
17913 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17914 | change = 0; | |
252b5132 RH |
17915 | else |
17916 | abort (); | |
17917 | ||
17918 | if (change) | |
17919 | { | |
4d7206a2 | 17920 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17921 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17922 | } |
4d7206a2 RS |
17923 | else |
17924 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17925 | } |
17926 | ||
17927 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17928 | should be converted into a reloc against a section. */ |
252b5132 RH |
17929 | |
17930 | int | |
17a2f251 | 17931 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17932 | { |
252b5132 RH |
17933 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17934 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17935 | return 0; | |
a161fe53 | 17936 | |
252b5132 RH |
17937 | if (fixp->fx_addsy == NULL) |
17938 | return 1; | |
a161fe53 | 17939 | |
de7e6852 RS |
17940 | /* If symbol SYM is in a mergeable section, relocations of the form |
17941 | SYM + 0 can usually be made section-relative. The mergeable data | |
17942 | is then identified by the section offset rather than by the symbol. | |
17943 | ||
17944 | However, if we're generating REL LO16 relocations, the offset is split | |
17945 | between the LO16 and parterning high part relocation. The linker will | |
17946 | need to recalculate the complete offset in order to correctly identify | |
17947 | the merge data. | |
17948 | ||
17949 | The linker has traditionally not looked for the parterning high part | |
17950 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17951 | placed anywhere. Rather than break backwards compatibility by changing | |
17952 | this, it seems better not to force the issue, and instead keep the | |
17953 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17954 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17955 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17956 | && HAVE_IN_PLACE_ADDENDS |
17957 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17958 | return 0; | |
17959 | ||
ce70d90a | 17960 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17961 | Likewise an in-range offset of limited PC-relative relocations may |
17962 | overflow the in-place relocatable field if recalculated against the | |
17963 | start address of the symbol's containing section. */ | |
ce70d90a | 17964 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17965 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17966 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17967 | return 0; |
17968 | ||
252b5132 | 17969 | #ifdef OBJ_ELF |
b314ec0e RS |
17970 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17971 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17972 | relocations against MIPS16 functions; in this case, the stub becomes | |
17973 | the function's canonical address. | |
17974 | ||
17975 | Floating-point stubs are stored in unique .mips16.call.* or | |
17976 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17977 | the first relocation in section S must be against F; this is how the | |
17978 | linker determines the target function. All relocations that might | |
17979 | resolve to T must also be against F. We therefore have the following | |
17980 | restrictions, which are given in an intentionally-redundant way: | |
17981 | ||
17982 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17983 | symbols. | |
17984 | ||
17985 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17986 | if that stub might be used. | |
17987 | ||
17988 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17989 | symbols. | |
17990 | ||
17991 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17992 | that stub might be used. | |
17993 | ||
17994 | There is a further restriction: | |
17995 | ||
df58fc94 RS |
17996 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17997 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17998 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17999 | encode the low bit. |
18000 | ||
df58fc94 RS |
18001 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
18002 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
18003 | such relocations on REL targets. | |
b314ec0e RS |
18004 | |
18005 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18006 | relocation against some symbol R, no relocation against R may be | |
18007 | reduced. (Note that this deals with (2) as well as (1) because | |
18008 | relocations against global symbols will never be reduced on ELF | |
18009 | targets.) This approach is a little simpler than trying to detect | |
18010 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18011 | that we have for MIPS16 symbols. */ | |
f43abd2b | 18012 | if (IS_ELF |
b314ec0e | 18013 | && fixp->fx_subsy == NULL |
30c09090 | 18014 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
18015 | || *symbol_get_tc (fixp->fx_addsy) |
18016 | || (HAVE_IN_PLACE_ADDENDS | |
18017 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
18018 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
18019 | return 0; |
18020 | #endif | |
a161fe53 | 18021 | |
252b5132 RH |
18022 | return 1; |
18023 | } | |
18024 | ||
18025 | /* Translate internal representation of relocation info to BFD target | |
18026 | format. */ | |
18027 | ||
18028 | arelent ** | |
17a2f251 | 18029 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18030 | { |
18031 | static arelent *retval[4]; | |
18032 | arelent *reloc; | |
18033 | bfd_reloc_code_real_type code; | |
18034 | ||
4b0cff4e TS |
18035 | memset (retval, 0, sizeof(retval)); |
18036 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
18037 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
18038 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
18039 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18040 | ||
bad36eac DJ |
18041 | if (fixp->fx_pcrel) |
18042 | { | |
df58fc94 RS |
18043 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18044 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18045 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18046 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18047 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18048 | |
18049 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18050 | Relocations want only the symbol offset. */ | |
18051 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 18052 | if (!IS_ELF) |
bad36eac DJ |
18053 | { |
18054 | /* A gruesome hack which is a result of the gruesome gas | |
18055 | reloc handling. What's worse, for COFF (as opposed to | |
18056 | ECOFF), we might need yet another copy of reloc->address. | |
18057 | See bfd_install_relocation. */ | |
18058 | reloc->addend += reloc->address; | |
18059 | } | |
18060 | } | |
18061 | else | |
18062 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18063 | |
438c16b8 TS |
18064 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18065 | entry to be used in the relocation's section offset. */ | |
18066 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18067 | { |
18068 | reloc->address = reloc->addend; | |
18069 | reloc->addend = 0; | |
18070 | } | |
18071 | ||
252b5132 | 18072 | code = fixp->fx_r_type; |
252b5132 | 18073 | |
bad36eac | 18074 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18075 | if (reloc->howto == NULL) |
18076 | { | |
18077 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18078 | _("Can not represent %s relocation in this object file format"), | |
18079 | bfd_get_reloc_code_name (code)); | |
18080 | retval[0] = NULL; | |
18081 | } | |
18082 | ||
18083 | return retval; | |
18084 | } | |
18085 | ||
18086 | /* Relax a machine dependent frag. This returns the amount by which | |
18087 | the current size of the frag should change. */ | |
18088 | ||
18089 | int | |
17a2f251 | 18090 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18091 | { |
4a6a3df4 AO |
18092 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18093 | { | |
18094 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18095 | |
18096 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18097 | |
18098 | return fragp->fr_var - old_var; | |
18099 | } | |
18100 | ||
df58fc94 RS |
18101 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18102 | { | |
18103 | offsetT old_var = fragp->fr_var; | |
18104 | offsetT new_var = 4; | |
18105 | ||
18106 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18107 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18108 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18109 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18110 | fragp->fr_var = new_var; | |
18111 | ||
18112 | return new_var - old_var; | |
18113 | } | |
18114 | ||
252b5132 RH |
18115 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18116 | return 0; | |
18117 | ||
c4e7957c | 18118 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18119 | { |
18120 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18121 | return 0; | |
18122 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18123 | return 2; | |
18124 | } | |
18125 | else | |
18126 | { | |
18127 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18128 | return 0; | |
18129 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18130 | return -2; | |
18131 | } | |
18132 | ||
18133 | return 0; | |
18134 | } | |
18135 | ||
18136 | /* Convert a machine dependent frag. */ | |
18137 | ||
18138 | void | |
17a2f251 | 18139 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18140 | { |
4a6a3df4 AO |
18141 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18142 | { | |
4d68580a | 18143 | char *buf; |
4a6a3df4 AO |
18144 | unsigned long insn; |
18145 | expressionS exp; | |
18146 | fixS *fixp; | |
b34976b6 | 18147 | |
4d68580a RS |
18148 | buf = fragp->fr_literal + fragp->fr_fix; |
18149 | insn = read_insn (buf); | |
b34976b6 | 18150 | |
4a6a3df4 AO |
18151 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18152 | { | |
18153 | /* We generate a fixup instead of applying it right now | |
18154 | because, if there are linker relaxations, we're going to | |
18155 | need the relocations. */ | |
18156 | exp.X_op = O_symbol; | |
18157 | exp.X_add_symbol = fragp->fr_symbol; | |
18158 | exp.X_add_number = fragp->fr_offset; | |
18159 | ||
4d68580a RS |
18160 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18161 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18162 | fixp->fx_file = fragp->fr_file; |
18163 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18164 | |
4d68580a | 18165 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18166 | } |
18167 | else | |
18168 | { | |
18169 | int i; | |
18170 | ||
18171 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18172 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18173 | |
18174 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18175 | goto uncond; | |
18176 | ||
18177 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18178 | { | |
18179 | /* Reverse the branch. */ | |
18180 | switch ((insn >> 28) & 0xf) | |
18181 | { | |
18182 | case 4: | |
3bf0dbfb MR |
18183 | /* bc[0-3][tf]l? instructions can have the condition |
18184 | reversed by tweaking a single TF bit, and their | |
18185 | opcodes all have 0x4???????. */ | |
18186 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18187 | insn ^= 0x00010000; |
18188 | break; | |
18189 | ||
18190 | case 0: | |
18191 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18192 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18193 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18194 | insn ^= 0x00010000; |
18195 | break; | |
b34976b6 | 18196 | |
4a6a3df4 AO |
18197 | case 1: |
18198 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18199 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18200 | insn ^= 0x04000000; |
18201 | break; | |
18202 | ||
18203 | default: | |
18204 | abort (); | |
18205 | } | |
18206 | } | |
18207 | ||
18208 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18209 | { | |
18210 | /* Clear the and-link bit. */ | |
9c2799c2 | 18211 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18212 | |
54f4ddb3 TS |
18213 | /* bltzal 0x04100000 bgezal 0x04110000 |
18214 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18215 | insn &= ~0x00100000; |
18216 | } | |
18217 | ||
18218 | /* Branch over the branch (if the branch was likely) or the | |
18219 | full jump (not likely case). Compute the offset from the | |
18220 | current instruction to branch to. */ | |
18221 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18222 | i = 16; | |
18223 | else | |
18224 | { | |
18225 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18226 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18227 | /* How many bytes in instructions from here to the end? */ |
18228 | i = fragp->fr_var - i; | |
18229 | } | |
18230 | /* Convert to instruction count. */ | |
18231 | i >>= 2; | |
18232 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18233 | i--; |
4a6a3df4 AO |
18234 | insn |= i; |
18235 | /* Branch over the jump. */ | |
4d68580a | 18236 | buf = write_insn (buf, insn); |
4a6a3df4 | 18237 | |
54f4ddb3 | 18238 | /* nop */ |
4d68580a | 18239 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18240 | |
18241 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18242 | { | |
18243 | /* beql $0, $0, 2f */ | |
18244 | insn = 0x50000000; | |
18245 | /* Compute the PC offset from the current instruction to | |
18246 | the end of the variable frag. */ | |
18247 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18248 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18249 | /* How many bytes in instructions from here to the end? */ |
18250 | i = fragp->fr_var - i; | |
18251 | /* Convert to instruction count. */ | |
18252 | i >>= 2; | |
18253 | /* Don't decrement i, because we want to branch over the | |
18254 | delay slot. */ | |
4a6a3df4 | 18255 | insn |= i; |
4a6a3df4 | 18256 | |
4d68580a RS |
18257 | buf = write_insn (buf, insn); |
18258 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18259 | } |
18260 | ||
18261 | uncond: | |
18262 | if (mips_pic == NO_PIC) | |
18263 | { | |
18264 | /* j or jal. */ | |
18265 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18266 | ? 0x0c000000 : 0x08000000); | |
18267 | exp.X_op = O_symbol; | |
18268 | exp.X_add_symbol = fragp->fr_symbol; | |
18269 | exp.X_add_number = fragp->fr_offset; | |
18270 | ||
4d68580a RS |
18271 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18272 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18273 | fixp->fx_file = fragp->fr_file; |
18274 | fixp->fx_line = fragp->fr_line; | |
18275 | ||
4d68580a | 18276 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18277 | } |
18278 | else | |
18279 | { | |
66b3e8da MR |
18280 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18281 | ||
4a6a3df4 | 18282 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18283 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18284 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18285 | exp.X_op = O_symbol; |
18286 | exp.X_add_symbol = fragp->fr_symbol; | |
18287 | exp.X_add_number = fragp->fr_offset; | |
18288 | ||
18289 | if (fragp->fr_offset) | |
18290 | { | |
18291 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18292 | exp.X_add_number = 0; | |
18293 | } | |
18294 | ||
4d68580a RS |
18295 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18296 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18297 | fixp->fx_file = fragp->fr_file; |
18298 | fixp->fx_line = fragp->fr_line; | |
18299 | ||
4d68580a | 18300 | buf = write_insn (buf, insn); |
b34976b6 | 18301 | |
4a6a3df4 | 18302 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18303 | /* nop */ |
18304 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18305 | |
18306 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18307 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18308 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18309 | |
4d68580a RS |
18310 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18311 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18312 | fixp->fx_file = fragp->fr_file; |
18313 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18314 | |
4d68580a | 18315 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18316 | |
18317 | /* j(al)r $at. */ | |
18318 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18319 | insn = 0x0000f809; |
4a6a3df4 | 18320 | else |
66b3e8da MR |
18321 | insn = 0x00000008; |
18322 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18323 | |
4d68580a | 18324 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18325 | } |
18326 | } | |
18327 | ||
4a6a3df4 | 18328 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18329 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18330 | return; |
18331 | } | |
18332 | ||
df58fc94 RS |
18333 | /* Relax microMIPS branches. */ |
18334 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18335 | { | |
4d68580a | 18336 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18337 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18338 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18339 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18340 | bfd_boolean short_ds; |
df58fc94 RS |
18341 | unsigned long insn; |
18342 | expressionS exp; | |
18343 | fixS *fixp; | |
18344 | ||
18345 | exp.X_op = O_symbol; | |
18346 | exp.X_add_symbol = fragp->fr_symbol; | |
18347 | exp.X_add_number = fragp->fr_offset; | |
18348 | ||
18349 | fragp->fr_fix += fragp->fr_var; | |
18350 | ||
18351 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18352 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18353 | { | |
18354 | /* We generate a fixup instead of applying it right now, | |
18355 | because if there is linker relaxation, we're going to | |
18356 | need the relocations. */ | |
18357 | if (type == 'D') | |
4d68580a | 18358 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18359 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18360 | else if (type == 'E') | |
4d68580a | 18361 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18362 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18363 | else | |
18364 | abort (); | |
18365 | ||
18366 | fixp->fx_file = fragp->fr_file; | |
18367 | fixp->fx_line = fragp->fr_line; | |
18368 | ||
18369 | /* These relocations can have an addend that won't fit in | |
18370 | 2 octets. */ | |
18371 | fixp->fx_no_overflow = 1; | |
18372 | ||
18373 | return; | |
18374 | } | |
18375 | ||
2309ddf2 | 18376 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18377 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18378 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18379 | { | |
18380 | /* We generate a fixup instead of applying it right now, | |
18381 | because if there is linker relaxation, we're going to | |
18382 | need the relocations. */ | |
4d68580a RS |
18383 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18384 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18385 | fixp->fx_file = fragp->fr_file; |
18386 | fixp->fx_line = fragp->fr_line; | |
18387 | ||
18388 | if (type == 0) | |
18389 | return; | |
18390 | } | |
18391 | ||
18392 | /* Relax 16-bit branches to 32-bit branches. */ | |
18393 | if (type != 0) | |
18394 | { | |
4d68580a | 18395 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18396 | |
18397 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18398 | insn = 0x94000000; /* beq */ | |
18399 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18400 | { | |
18401 | unsigned long regno; | |
18402 | ||
18403 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18404 | regno = micromips_to_32_reg_d_map [regno]; | |
18405 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18406 | insn |= regno << MICROMIPSOP_SH_RS; | |
18407 | } | |
18408 | else | |
18409 | abort (); | |
18410 | ||
18411 | /* Nothing else to do, just write it out. */ | |
18412 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18413 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18414 | { | |
4d68580a RS |
18415 | buf = write_compressed_insn (buf, insn, 4); |
18416 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18417 | return; |
18418 | } | |
18419 | } | |
18420 | else | |
4d68580a | 18421 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18422 | |
18423 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18424 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18425 | _("Relaxed out-of-range branch into a jump")); | |
18426 | ||
2309ddf2 MR |
18427 | /* Set the short-delay-slot bit. */ |
18428 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18429 | |
18430 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18431 | { | |
18432 | symbolS *l; | |
18433 | ||
18434 | /* Reverse the branch. */ | |
18435 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18436 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18437 | insn ^= 0x20000000; | |
18438 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18439 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18440 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18441 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18442 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18443 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18444 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18445 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18446 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18447 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18448 | insn ^= 0x00400000; | |
18449 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18450 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18451 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18452 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18453 | insn ^= 0x00200000; | |
18454 | else | |
18455 | abort (); | |
18456 | ||
18457 | if (al) | |
18458 | { | |
18459 | /* Clear the and-link and short-delay-slot bits. */ | |
18460 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18461 | ||
18462 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18463 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18464 | insn &= ~0x02200000; | |
18465 | } | |
18466 | ||
18467 | /* Make a label at the end for use with the branch. */ | |
18468 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18469 | micromips_label_inc (); | |
18470 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18471 | if (IS_ELF) | |
18472 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18473 | #endif | |
18474 | ||
18475 | /* Refer to it. */ | |
4d68580a RS |
18476 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18477 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18478 | fixp->fx_file = fragp->fr_file; |
18479 | fixp->fx_line = fragp->fr_line; | |
18480 | ||
18481 | /* Branch over the jump. */ | |
4d68580a | 18482 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18483 | if (!compact) |
4d68580a RS |
18484 | /* nop */ |
18485 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18486 | } |
18487 | ||
18488 | if (mips_pic == NO_PIC) | |
18489 | { | |
2309ddf2 MR |
18490 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18491 | ||
df58fc94 RS |
18492 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18493 | insn = al ? jal : 0xd4000000; | |
18494 | ||
4d68580a RS |
18495 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18496 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18497 | fixp->fx_file = fragp->fr_file; |
18498 | fixp->fx_line = fragp->fr_line; | |
18499 | ||
4d68580a | 18500 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18501 | if (compact) |
4d68580a RS |
18502 | /* nop */ |
18503 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18504 | } |
18505 | else | |
18506 | { | |
18507 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18508 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18509 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18510 | |
18511 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18512 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18513 | insn |= at << MICROMIPSOP_SH_RT; | |
18514 | ||
18515 | if (exp.X_add_number) | |
18516 | { | |
18517 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18518 | exp.X_add_number = 0; | |
18519 | } | |
18520 | ||
4d68580a RS |
18521 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18522 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18523 | fixp->fx_file = fragp->fr_file; |
18524 | fixp->fx_line = fragp->fr_line; | |
18525 | ||
4d68580a | 18526 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18527 | |
18528 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18529 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18530 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18531 | ||
4d68580a RS |
18532 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18533 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18534 | fixp->fx_file = fragp->fr_file; |
18535 | fixp->fx_line = fragp->fr_line; | |
18536 | ||
4d68580a | 18537 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18538 | |
18539 | /* jr/jrc/jalr/jalrs $at */ | |
18540 | insn = al ? jalr : jr; | |
18541 | insn |= at << MICROMIPSOP_SH_MJ; | |
18542 | ||
4d68580a | 18543 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18544 | } |
18545 | ||
4d68580a | 18546 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18547 | return; |
18548 | } | |
18549 | ||
252b5132 RH |
18550 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18551 | { | |
18552 | int type; | |
3994f87e | 18553 | const struct mips16_immed_operand *op; |
252b5132 | 18554 | offsetT val; |
5c04167a RS |
18555 | char *buf; |
18556 | unsigned int user_length, length; | |
252b5132 | 18557 | unsigned long insn; |
5c04167a | 18558 | bfd_boolean ext; |
252b5132 RH |
18559 | |
18560 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18561 | op = mips16_immed_operands; | |
18562 | while (op->type != type) | |
18563 | ++op; | |
18564 | ||
5c04167a | 18565 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18566 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18567 | if (op->pcrel) |
18568 | { | |
18569 | addressT addr; | |
18570 | ||
18571 | addr = fragp->fr_address + fragp->fr_fix; | |
18572 | ||
18573 | /* The rules for the base address of a PC relative reloc are | |
18574 | complicated; see mips16_extended_frag. */ | |
18575 | if (type == 'p' || type == 'q') | |
18576 | { | |
18577 | addr += 2; | |
18578 | if (ext) | |
18579 | addr += 2; | |
18580 | /* Ignore the low bit in the target, since it will be | |
18581 | set for a text label. */ | |
18582 | if ((val & 1) != 0) | |
18583 | --val; | |
18584 | } | |
18585 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18586 | addr -= 4; | |
18587 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18588 | addr -= 2; | |
18589 | ||
18590 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18591 | val -= addr; | |
18592 | ||
18593 | /* Make sure the section winds up with the alignment we have | |
18594 | assumed. */ | |
18595 | if (op->shift > 0) | |
18596 | record_alignment (asec, op->shift); | |
18597 | } | |
18598 | ||
18599 | if (ext | |
18600 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18601 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18602 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18603 | _("extended instruction in delay slot")); | |
18604 | ||
5c04167a | 18605 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18606 | |
4d68580a | 18607 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18608 | if (ext) |
18609 | insn |= MIPS16_EXTEND; | |
252b5132 | 18610 | |
5c04167a RS |
18611 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18612 | user_length = 4; | |
18613 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18614 | user_length = 2; | |
18615 | else | |
18616 | user_length = 0; | |
18617 | ||
43c0598f | 18618 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18619 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18620 | |
5c04167a RS |
18621 | length = (ext ? 4 : 2); |
18622 | gas_assert (mips16_opcode_length (insn) == length); | |
18623 | write_compressed_insn (buf, insn, length); | |
18624 | fragp->fr_fix += length; | |
252b5132 RH |
18625 | } |
18626 | else | |
18627 | { | |
df58fc94 RS |
18628 | relax_substateT subtype = fragp->fr_subtype; |
18629 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18630 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18631 | int first, second; |
18632 | fixS *fixp; | |
252b5132 | 18633 | |
df58fc94 RS |
18634 | first = RELAX_FIRST (subtype); |
18635 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18636 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18637 | |
df58fc94 RS |
18638 | /* If the delay slot chosen does not match the size of the instruction, |
18639 | then emit a warning. */ | |
18640 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18641 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18642 | { | |
18643 | relax_substateT s; | |
18644 | const char *msg; | |
18645 | ||
18646 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18647 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18648 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18649 | msg = macro_warning (s); | |
18650 | if (msg != NULL) | |
db9b2be4 | 18651 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18652 | subtype &= ~s; |
18653 | } | |
18654 | ||
584892a6 | 18655 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18656 | if (use_second == second_longer) |
584892a6 | 18657 | { |
df58fc94 RS |
18658 | relax_substateT s; |
18659 | const char *msg; | |
18660 | ||
18661 | s = (subtype | |
18662 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18663 | msg = macro_warning (s); | |
18664 | if (msg != NULL) | |
db9b2be4 | 18665 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18666 | subtype &= ~s; |
584892a6 RS |
18667 | } |
18668 | ||
4d7206a2 RS |
18669 | /* Go through all the fixups for the first sequence. Disable them |
18670 | (by marking them as done) if we're going to use the second | |
18671 | sequence instead. */ | |
18672 | while (fixp | |
18673 | && fixp->fx_frag == fragp | |
18674 | && fixp->fx_where < fragp->fr_fix - second) | |
18675 | { | |
df58fc94 | 18676 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18677 | fixp->fx_done = 1; |
18678 | fixp = fixp->fx_next; | |
18679 | } | |
252b5132 | 18680 | |
4d7206a2 RS |
18681 | /* Go through the fixups for the second sequence. Disable them if |
18682 | we're going to use the first sequence, otherwise adjust their | |
18683 | addresses to account for the relaxation. */ | |
18684 | while (fixp && fixp->fx_frag == fragp) | |
18685 | { | |
df58fc94 | 18686 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18687 | fixp->fx_where -= first; |
18688 | else | |
18689 | fixp->fx_done = 1; | |
18690 | fixp = fixp->fx_next; | |
18691 | } | |
18692 | ||
18693 | /* Now modify the frag contents. */ | |
df58fc94 | 18694 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18695 | { |
18696 | char *start; | |
18697 | ||
18698 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18699 | memmove (start, start + first, second); | |
18700 | fragp->fr_fix -= first; | |
18701 | } | |
18702 | else | |
18703 | fragp->fr_fix -= second; | |
252b5132 RH |
18704 | } |
18705 | } | |
18706 | ||
18707 | #ifdef OBJ_ELF | |
18708 | ||
18709 | /* This function is called after the relocs have been generated. | |
18710 | We've been storing mips16 text labels as odd. Here we convert them | |
18711 | back to even for the convenience of the debugger. */ | |
18712 | ||
18713 | void | |
17a2f251 | 18714 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18715 | { |
18716 | asymbol **syms; | |
18717 | unsigned int count, i; | |
18718 | ||
f43abd2b | 18719 | if (!IS_ELF) |
252b5132 RH |
18720 | return; |
18721 | ||
18722 | syms = bfd_get_outsymbols (stdoutput); | |
18723 | count = bfd_get_symcount (stdoutput); | |
18724 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18725 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18726 | && ((*syms)->value & 1) != 0) | |
18727 | { | |
18728 | (*syms)->value &= ~1; | |
18729 | /* If the symbol has an odd size, it was probably computed | |
18730 | incorrectly, so adjust that as well. */ | |
18731 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18732 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18733 | } | |
252b5132 RH |
18734 | } |
18735 | ||
18736 | #endif | |
18737 | ||
a1facbec MR |
18738 | /* This function is called whenever a label is defined, including fake |
18739 | labels instantiated off the dot special symbol. It is used when | |
18740 | handling branch delays; if a branch has a label, we assume we cannot | |
18741 | move it. This also bumps the value of the symbol by 1 in compressed | |
18742 | code. */ | |
252b5132 | 18743 | |
e1b47bd5 | 18744 | static void |
a1facbec | 18745 | mips_record_label (symbolS *sym) |
252b5132 | 18746 | { |
a8dbcb85 | 18747 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18748 | struct insn_label_list *l; |
18749 | ||
18750 | if (free_insn_labels == NULL) | |
18751 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18752 | else | |
18753 | { | |
18754 | l = free_insn_labels; | |
18755 | free_insn_labels = l->next; | |
18756 | } | |
18757 | ||
18758 | l->label = sym; | |
a8dbcb85 TS |
18759 | l->next = si->label_list; |
18760 | si->label_list = l; | |
a1facbec | 18761 | } |
07a53e5c | 18762 | |
a1facbec MR |
18763 | /* This function is called as tc_frob_label() whenever a label is defined |
18764 | and adds a DWARF-2 record we only want for true labels. */ | |
18765 | ||
18766 | void | |
18767 | mips_define_label (symbolS *sym) | |
18768 | { | |
18769 | mips_record_label (sym); | |
07a53e5c RH |
18770 | #ifdef OBJ_ELF |
18771 | dwarf2_emit_label (sym); | |
18772 | #endif | |
252b5132 | 18773 | } |
e1b47bd5 RS |
18774 | |
18775 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18776 | is defined. */ | |
18777 | ||
18778 | void | |
18779 | mips_add_dot_label (symbolS *sym) | |
18780 | { | |
18781 | mips_record_label (sym); | |
18782 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18783 | mips_compressed_mark_label (sym); | |
18784 | } | |
252b5132 RH |
18785 | \f |
18786 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18787 | ||
18788 | /* Some special processing for a MIPS ELF file. */ | |
18789 | ||
18790 | void | |
17a2f251 | 18791 | mips_elf_final_processing (void) |
252b5132 RH |
18792 | { |
18793 | /* Write out the register information. */ | |
316f5878 | 18794 | if (mips_abi != N64_ABI) |
252b5132 RH |
18795 | { |
18796 | Elf32_RegInfo s; | |
18797 | ||
18798 | s.ri_gprmask = mips_gprmask; | |
18799 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18800 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18801 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18802 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18803 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18804 | ||
18805 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18806 | ((Elf32_External_RegInfo *) | |
18807 | mips_regmask_frag)); | |
18808 | } | |
18809 | else | |
18810 | { | |
18811 | Elf64_Internal_RegInfo s; | |
18812 | ||
18813 | s.ri_gprmask = mips_gprmask; | |
18814 | s.ri_pad = 0; | |
18815 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18816 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18817 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18818 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18819 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18820 | ||
18821 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18822 | ((Elf64_External_RegInfo *) | |
18823 | mips_regmask_frag)); | |
18824 | } | |
18825 | ||
18826 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18827 | sort of BFD interface for this. */ | |
18828 | if (mips_any_noreorder) | |
18829 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18830 | if (mips_pic != NO_PIC) | |
143d77c5 | 18831 | { |
8b828383 | 18832 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18833 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18834 | } | |
18835 | if (mips_abicalls) | |
18836 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18837 | |
b015e599 AP |
18838 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18839 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18840 | if (file_ase_mips16) |
18841 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18842 | if (file_ase_micromips) |
18843 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18844 | #if 0 /* XXX FIXME */ |
18845 | if (file_ase_mips3d) | |
18846 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18847 | #endif | |
deec1734 CD |
18848 | if (file_ase_mdmx) |
18849 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18850 | |
bdaaa2e1 | 18851 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18852 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18853 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18854 | else if (mips_abi == O64_ABI) |
252b5132 | 18855 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18856 | else if (mips_abi == EABI_ABI) |
252b5132 | 18857 | { |
316f5878 | 18858 | if (!file_mips_gp32) |
252b5132 RH |
18859 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18860 | else | |
18861 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18862 | } | |
316f5878 | 18863 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18864 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18865 | ||
c9914766 | 18866 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18867 | |
18868 | if (mips_32bitmode) | |
18869 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18870 | |
18871 | #if 0 /* XXX FIXME */ | |
18872 | /* 32 bit code with 64 bit FP registers. */ | |
18873 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18874 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18875 | #endif | |
252b5132 RH |
18876 | } |
18877 | ||
18878 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18879 | \f | |
beae10d5 | 18880 | typedef struct proc { |
9b2f1d35 EC |
18881 | symbolS *func_sym; |
18882 | symbolS *func_end_sym; | |
beae10d5 KH |
18883 | unsigned long reg_mask; |
18884 | unsigned long reg_offset; | |
18885 | unsigned long fpreg_mask; | |
18886 | unsigned long fpreg_offset; | |
18887 | unsigned long frame_offset; | |
18888 | unsigned long frame_reg; | |
18889 | unsigned long pc_reg; | |
18890 | } procS; | |
252b5132 RH |
18891 | |
18892 | static procS cur_proc; | |
18893 | static procS *cur_proc_ptr; | |
18894 | static int numprocs; | |
18895 | ||
df58fc94 RS |
18896 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18897 | as "2", and a normal nop as "0". */ | |
18898 | ||
18899 | #define NOP_OPCODE_MIPS 0 | |
18900 | #define NOP_OPCODE_MIPS16 1 | |
18901 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18902 | |
18903 | char | |
18904 | mips_nop_opcode (void) | |
18905 | { | |
df58fc94 RS |
18906 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18907 | return NOP_OPCODE_MICROMIPS; | |
18908 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18909 | return NOP_OPCODE_MIPS16; | |
18910 | else | |
18911 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18912 | } |
18913 | ||
df58fc94 RS |
18914 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18915 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18916 | |
0a9ef439 | 18917 | void |
17a2f251 | 18918 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18919 | { |
df58fc94 | 18920 | char nop_opcode; |
742a56fe | 18921 | char *p; |
c67a084a NC |
18922 | int bytes, size, excess; |
18923 | valueT opcode; | |
742a56fe | 18924 | |
0a9ef439 RH |
18925 | if (fragp->fr_type != rs_align_code) |
18926 | return; | |
18927 | ||
742a56fe | 18928 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18929 | nop_opcode = *p; |
18930 | switch (nop_opcode) | |
a19d8eb0 | 18931 | { |
df58fc94 RS |
18932 | case NOP_OPCODE_MICROMIPS: |
18933 | opcode = micromips_nop32_insn.insn_opcode; | |
18934 | size = 4; | |
18935 | break; | |
18936 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18937 | opcode = mips16_nop_insn.insn_opcode; |
18938 | size = 2; | |
df58fc94 RS |
18939 | break; |
18940 | case NOP_OPCODE_MIPS: | |
18941 | default: | |
c67a084a NC |
18942 | opcode = nop_insn.insn_opcode; |
18943 | size = 4; | |
df58fc94 | 18944 | break; |
c67a084a | 18945 | } |
a19d8eb0 | 18946 | |
c67a084a NC |
18947 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18948 | excess = bytes % size; | |
df58fc94 RS |
18949 | |
18950 | /* Handle the leading part if we're not inserting a whole number of | |
18951 | instructions, and make it the end of the fixed part of the frag. | |
18952 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18953 | and use zeroes otherwise. */ | |
18954 | gas_assert (excess < 4); | |
18955 | fragp->fr_fix += excess; | |
18956 | switch (excess) | |
c67a084a | 18957 | { |
df58fc94 RS |
18958 | case 3: |
18959 | *p++ = '\0'; | |
18960 | /* Fall through. */ | |
18961 | case 2: | |
18962 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18963 | { | |
4d68580a | 18964 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18965 | break; |
18966 | } | |
18967 | *p++ = '\0'; | |
18968 | /* Fall through. */ | |
18969 | case 1: | |
18970 | *p++ = '\0'; | |
18971 | /* Fall through. */ | |
18972 | case 0: | |
18973 | break; | |
a19d8eb0 | 18974 | } |
c67a084a NC |
18975 | |
18976 | md_number_to_chars (p, opcode, size); | |
18977 | fragp->fr_var = size; | |
a19d8eb0 CP |
18978 | } |
18979 | ||
252b5132 | 18980 | static void |
17a2f251 | 18981 | md_obj_begin (void) |
252b5132 RH |
18982 | { |
18983 | } | |
18984 | ||
18985 | static void | |
17a2f251 | 18986 | md_obj_end (void) |
252b5132 | 18987 | { |
54f4ddb3 | 18988 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18989 | if (cur_proc_ptr) |
9a41af64 | 18990 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18991 | } |
18992 | ||
18993 | static long | |
17a2f251 | 18994 | get_number (void) |
252b5132 RH |
18995 | { |
18996 | int negative = 0; | |
18997 | long val = 0; | |
18998 | ||
18999 | if (*input_line_pointer == '-') | |
19000 | { | |
19001 | ++input_line_pointer; | |
19002 | negative = 1; | |
19003 | } | |
3882b010 | 19004 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19005 | as_bad (_("expected simple number")); |
252b5132 RH |
19006 | if (input_line_pointer[0] == '0') |
19007 | { | |
19008 | if (input_line_pointer[1] == 'x') | |
19009 | { | |
19010 | input_line_pointer += 2; | |
3882b010 | 19011 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19012 | { |
19013 | val <<= 4; | |
19014 | val |= hex_value (*input_line_pointer++); | |
19015 | } | |
19016 | return negative ? -val : val; | |
19017 | } | |
19018 | else | |
19019 | { | |
19020 | ++input_line_pointer; | |
3882b010 | 19021 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19022 | { |
19023 | val <<= 3; | |
19024 | val |= *input_line_pointer++ - '0'; | |
19025 | } | |
19026 | return negative ? -val : val; | |
19027 | } | |
19028 | } | |
3882b010 | 19029 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19030 | { |
19031 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19032 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19033 | as_warn (_("invalid number")); |
252b5132 RH |
19034 | return -1; |
19035 | } | |
3882b010 | 19036 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19037 | { |
19038 | val *= 10; | |
19039 | val += *input_line_pointer++ - '0'; | |
19040 | } | |
19041 | return negative ? -val : val; | |
19042 | } | |
19043 | ||
19044 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19045 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19046 | case .file implies DWARF-2. */ | |
19047 | ||
19048 | static void | |
17a2f251 | 19049 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19050 | { |
ecb4347a DJ |
19051 | static int first_file_directive = 0; |
19052 | ||
c5dd6aab DJ |
19053 | if (ECOFF_DEBUGGING) |
19054 | { | |
19055 | get_number (); | |
19056 | s_app_file (0); | |
19057 | } | |
19058 | else | |
ecb4347a DJ |
19059 | { |
19060 | char *filename; | |
19061 | ||
19062 | filename = dwarf2_directive_file (0); | |
19063 | ||
19064 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19065 | directive even for stabs output. Make sure that this | |
19066 | ".file" is handled. Note that you need a version of GCC | |
19067 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19068 | if (filename != NULL && ! first_file_directive) | |
19069 | { | |
19070 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19071 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19072 | } |
19073 | first_file_directive = 1; | |
19074 | } | |
c5dd6aab DJ |
19075 | } |
19076 | ||
19077 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19078 | |
19079 | static void | |
17a2f251 | 19080 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19081 | { |
c5dd6aab DJ |
19082 | if (!ECOFF_DEBUGGING) |
19083 | dwarf2_directive_loc (0); | |
252b5132 RH |
19084 | } |
19085 | ||
252b5132 RH |
19086 | /* The .end directive. */ |
19087 | ||
19088 | static void | |
17a2f251 | 19089 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19090 | { |
19091 | symbolS *p; | |
252b5132 | 19092 | |
7a621144 DJ |
19093 | /* Following functions need their own .frame and .cprestore directives. */ |
19094 | mips_frame_reg_valid = 0; | |
19095 | mips_cprestore_valid = 0; | |
19096 | ||
252b5132 RH |
19097 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19098 | { | |
19099 | p = get_symbol (); | |
19100 | demand_empty_rest_of_line (); | |
19101 | } | |
19102 | else | |
19103 | p = NULL; | |
19104 | ||
14949570 | 19105 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19106 | as_warn (_(".end not in text section")); |
19107 | ||
19108 | if (!cur_proc_ptr) | |
19109 | { | |
19110 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19111 | demand_empty_rest_of_line (); | |
19112 | return; | |
19113 | } | |
19114 | ||
19115 | if (p != NULL) | |
19116 | { | |
9c2799c2 | 19117 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19118 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19119 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19120 | |
19121 | if (debug_type == DEBUG_STABS) | |
19122 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19123 | S_GET_NAME (p)); | |
252b5132 RH |
19124 | } |
19125 | else | |
19126 | as_warn (_(".end directive missing or unknown symbol")); | |
19127 | ||
2132e3a3 | 19128 | #ifdef OBJ_ELF |
9b2f1d35 EC |
19129 | /* Create an expression to calculate the size of the function. */ |
19130 | if (p && cur_proc_ptr) | |
19131 | { | |
19132 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19133 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19134 | ||
19135 | obj->size = exp; | |
19136 | exp->X_op = O_subtract; | |
19137 | exp->X_add_symbol = symbol_temp_new_now (); | |
19138 | exp->X_op_symbol = p; | |
19139 | exp->X_add_number = 0; | |
19140 | ||
19141 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19142 | } | |
19143 | ||
ecb4347a | 19144 | /* Generate a .pdr section. */ |
f43abd2b | 19145 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19146 | { |
19147 | segT saved_seg = now_seg; | |
19148 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19149 | expressionS exp; |
19150 | char *fragp; | |
252b5132 | 19151 | |
252b5132 | 19152 | #ifdef md_flush_pending_output |
ecb4347a | 19153 | md_flush_pending_output (); |
252b5132 RH |
19154 | #endif |
19155 | ||
9c2799c2 | 19156 | gas_assert (pdr_seg); |
ecb4347a | 19157 | subseg_set (pdr_seg, 0); |
252b5132 | 19158 | |
ecb4347a DJ |
19159 | /* Write the symbol. */ |
19160 | exp.X_op = O_symbol; | |
19161 | exp.X_add_symbol = p; | |
19162 | exp.X_add_number = 0; | |
19163 | emit_expr (&exp, 4); | |
252b5132 | 19164 | |
ecb4347a | 19165 | fragp = frag_more (7 * 4); |
252b5132 | 19166 | |
17a2f251 TS |
19167 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19168 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19169 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19170 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19171 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19172 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19173 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19174 | |
ecb4347a DJ |
19175 | subseg_set (saved_seg, saved_subseg); |
19176 | } | |
19177 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19178 | |
19179 | cur_proc_ptr = NULL; | |
19180 | } | |
19181 | ||
19182 | /* The .aent and .ent directives. */ | |
19183 | ||
19184 | static void | |
17a2f251 | 19185 | s_mips_ent (int aent) |
252b5132 | 19186 | { |
252b5132 | 19187 | symbolS *symbolP; |
252b5132 RH |
19188 | |
19189 | symbolP = get_symbol (); | |
19190 | if (*input_line_pointer == ',') | |
f9419b05 | 19191 | ++input_line_pointer; |
252b5132 | 19192 | SKIP_WHITESPACE (); |
3882b010 | 19193 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19194 | || *input_line_pointer == '-') |
874e8986 | 19195 | get_number (); |
252b5132 | 19196 | |
14949570 | 19197 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19198 | as_warn (_(".ent or .aent not in text section.")); |
19199 | ||
19200 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19201 | as_warn (_("missing .end")); |
252b5132 RH |
19202 | |
19203 | if (!aent) | |
19204 | { | |
7a621144 DJ |
19205 | /* This function needs its own .frame and .cprestore directives. */ |
19206 | mips_frame_reg_valid = 0; | |
19207 | mips_cprestore_valid = 0; | |
19208 | ||
252b5132 RH |
19209 | cur_proc_ptr = &cur_proc; |
19210 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19211 | ||
9b2f1d35 | 19212 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19213 | |
f9419b05 | 19214 | ++numprocs; |
ecb4347a DJ |
19215 | |
19216 | if (debug_type == DEBUG_STABS) | |
19217 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19218 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19219 | } |
19220 | ||
7c0fc524 MR |
19221 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19222 | ||
252b5132 RH |
19223 | demand_empty_rest_of_line (); |
19224 | } | |
19225 | ||
19226 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19227 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19228 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19229 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19230 | symbol table (in the mdebug section). */ |
19231 | ||
19232 | static void | |
17a2f251 | 19233 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19234 | { |
ecb4347a | 19235 | #ifdef OBJ_ELF |
f43abd2b | 19236 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19237 | { |
19238 | long val; | |
252b5132 | 19239 | |
ecb4347a DJ |
19240 | if (cur_proc_ptr == (procS *) NULL) |
19241 | { | |
19242 | as_warn (_(".frame outside of .ent")); | |
19243 | demand_empty_rest_of_line (); | |
19244 | return; | |
19245 | } | |
252b5132 | 19246 | |
ecb4347a DJ |
19247 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19248 | ||
19249 | SKIP_WHITESPACE (); | |
19250 | if (*input_line_pointer++ != ',' | |
19251 | || get_absolute_expression_and_terminator (&val) != ',') | |
19252 | { | |
19253 | as_warn (_("Bad .frame directive")); | |
19254 | --input_line_pointer; | |
19255 | demand_empty_rest_of_line (); | |
19256 | return; | |
19257 | } | |
252b5132 | 19258 | |
ecb4347a DJ |
19259 | cur_proc_ptr->frame_offset = val; |
19260 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19261 | |
252b5132 | 19262 | demand_empty_rest_of_line (); |
252b5132 | 19263 | } |
ecb4347a DJ |
19264 | else |
19265 | #endif /* OBJ_ELF */ | |
19266 | s_ignore (ignore); | |
252b5132 RH |
19267 | } |
19268 | ||
bdaaa2e1 KH |
19269 | /* The .fmask and .mask directives. If the mdebug section is present |
19270 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19271 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19272 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19273 | make reference to the ecoff symbol table (in the mdebug section). */ |
19274 | ||
19275 | static void | |
17a2f251 | 19276 | s_mips_mask (int reg_type) |
252b5132 | 19277 | { |
ecb4347a | 19278 | #ifdef OBJ_ELF |
f43abd2b | 19279 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19280 | { |
ecb4347a | 19281 | long mask, off; |
252b5132 | 19282 | |
ecb4347a DJ |
19283 | if (cur_proc_ptr == (procS *) NULL) |
19284 | { | |
19285 | as_warn (_(".mask/.fmask outside of .ent")); | |
19286 | demand_empty_rest_of_line (); | |
19287 | return; | |
19288 | } | |
252b5132 | 19289 | |
ecb4347a DJ |
19290 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19291 | { | |
19292 | as_warn (_("Bad .mask/.fmask directive")); | |
19293 | --input_line_pointer; | |
19294 | demand_empty_rest_of_line (); | |
19295 | return; | |
19296 | } | |
252b5132 | 19297 | |
ecb4347a DJ |
19298 | off = get_absolute_expression (); |
19299 | ||
19300 | if (reg_type == 'F') | |
19301 | { | |
19302 | cur_proc_ptr->fpreg_mask = mask; | |
19303 | cur_proc_ptr->fpreg_offset = off; | |
19304 | } | |
19305 | else | |
19306 | { | |
19307 | cur_proc_ptr->reg_mask = mask; | |
19308 | cur_proc_ptr->reg_offset = off; | |
19309 | } | |
19310 | ||
19311 | demand_empty_rest_of_line (); | |
252b5132 RH |
19312 | } |
19313 | else | |
ecb4347a DJ |
19314 | #endif /* OBJ_ELF */ |
19315 | s_ignore (reg_type); | |
252b5132 RH |
19316 | } |
19317 | ||
316f5878 RS |
19318 | /* A table describing all the processors gas knows about. Names are |
19319 | matched in the order listed. | |
e7af610e | 19320 | |
316f5878 RS |
19321 | To ease comparison, please keep this table in the same order as |
19322 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19323 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19324 | { | |
316f5878 | 19325 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19326 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19327 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19328 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19329 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19330 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19331 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19332 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19333 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19334 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19335 | |
19336 | /* MIPS I */ | |
ad3fea08 TS |
19337 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19338 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19339 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19340 | |
19341 | /* MIPS II */ | |
ad3fea08 | 19342 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19343 | |
19344 | /* MIPS III */ | |
ad3fea08 TS |
19345 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19346 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19347 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19348 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19349 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19350 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19351 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19352 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19353 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19354 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19355 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19356 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
e407c74b | 19357 | { "r5900", 0, ISA_MIPS3, CPU_R5900 }, |
b15591bb AN |
19358 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19359 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19360 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19361 | |
19362 | /* MIPS IV */ | |
ad3fea08 TS |
19363 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19364 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19365 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19366 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19367 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19368 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19369 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19370 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19371 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19372 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19373 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19374 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19375 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19376 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19377 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19378 | |
19379 | /* MIPS 32 */ | |
ad3fea08 TS |
19380 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19381 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19382 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19383 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19384 | ||
19385 | /* MIPS 32 Release 2 */ | |
19386 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19387 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19388 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19389 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19390 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19391 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19392 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19393 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19394 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19395 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19396 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19397 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19398 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19399 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19400 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19401 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19402 | /* Deprecated forms of the above. */ | |
19403 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19404 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19405 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19406 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19407 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19408 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19409 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19410 | /* Deprecated forms of the above. */ | |
19411 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19412 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19413 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19414 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19415 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19416 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19417 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19418 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19419 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19420 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19421 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19422 | /* Deprecated forms of the above. */ | |
19423 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19424 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19425 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19426 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19427 | /* 34Kn is a 34kc without DSP. */ |
19428 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19429 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19430 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19431 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19432 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19433 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19434 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19435 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19436 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19437 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19438 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19439 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19440 | /* Deprecated forms of the above. */ | |
19441 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19442 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19443 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19444 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19445 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19446 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19447 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19448 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19449 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19450 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19451 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19452 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19453 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19454 | |
316f5878 | 19455 | /* MIPS 64 */ |
ad3fea08 TS |
19456 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19457 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19458 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19459 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19460 | |
c7a23324 | 19461 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19462 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19463 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19464 | /* Broadcom SB-1A CPU core */ |
19465 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19466 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19467 | |
19468 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19469 | |
ed163775 MR |
19470 | /* MIPS 64 Release 2 */ |
19471 | ||
967344c6 AN |
19472 | /* Cavium Networks Octeon CPU core */ |
19473 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19474 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19475 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19476 | |
52b6b6b9 JM |
19477 | /* RMI Xlr */ |
19478 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19479 | ||
55a36193 MK |
19480 | /* Broadcom XLP. |
19481 | XLP is mostly like XLR, with the prominent exception that it is | |
19482 | MIPS64R2 rather than MIPS64. */ | |
19483 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19484 | ||
316f5878 RS |
19485 | /* End marker */ |
19486 | { NULL, 0, 0, 0 } | |
19487 | }; | |
e7af610e | 19488 | |
84ea6cf2 | 19489 | |
316f5878 RS |
19490 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19491 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19492 | |
316f5878 | 19493 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19494 | |
b34976b6 | 19495 | static bfd_boolean |
17a2f251 | 19496 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19497 | { |
19498 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19499 | given++, canonical++; | |
19500 | ||
19501 | return ((*given == 0 && *canonical == 0) | |
19502 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19503 | } | |
19504 | ||
19505 | ||
19506 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19507 | CPU name. We've traditionally allowed a lot of variation here. | |
19508 | ||
19509 | Note: this function is shared between GCC and GAS. */ | |
19510 | ||
b34976b6 | 19511 | static bfd_boolean |
17a2f251 | 19512 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19513 | { |
19514 | /* First see if the name matches exactly, or with a final "000" | |
19515 | turned into "k". */ | |
19516 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19517 | return TRUE; |
316f5878 RS |
19518 | |
19519 | /* If not, try comparing based on numerical designation alone. | |
19520 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19521 | if (TOLOWER (*given) == 'r') | |
19522 | given++; | |
19523 | if (!ISDIGIT (*given)) | |
b34976b6 | 19524 | return FALSE; |
316f5878 RS |
19525 | |
19526 | /* Skip over some well-known prefixes in the canonical name, | |
19527 | hoping to find a number there too. */ | |
19528 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19529 | canonical += 2; | |
19530 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19531 | canonical += 2; | |
19532 | else if (TOLOWER (canonical[0]) == 'r') | |
19533 | canonical += 1; | |
19534 | ||
19535 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19536 | } | |
19537 | ||
19538 | ||
19539 | /* Parse an option that takes the name of a processor as its argument. | |
19540 | OPTION is the name of the option and CPU_STRING is the argument. | |
19541 | Return the corresponding processor enumeration if the CPU_STRING is | |
19542 | recognized, otherwise report an error and return null. | |
19543 | ||
19544 | A similar function exists in GCC. */ | |
e7af610e NC |
19545 | |
19546 | static const struct mips_cpu_info * | |
17a2f251 | 19547 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19548 | { |
316f5878 | 19549 | const struct mips_cpu_info *p; |
e7af610e | 19550 | |
316f5878 RS |
19551 | /* 'from-abi' selects the most compatible architecture for the given |
19552 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19553 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19554 | version. Look first at the -mgp options, if given, otherwise base | |
19555 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19556 | |
316f5878 RS |
19557 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19558 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19559 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19560 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19561 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19562 | { | |
19563 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19564 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19565 | ||
19566 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19567 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19568 | ||
19569 | if (file_mips_gp32 >= 0) | |
19570 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19571 | ||
19572 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19573 | ? ISA_MIPS3 | |
19574 | : ISA_MIPS1); | |
19575 | } | |
19576 | ||
19577 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19578 | if (strcasecmp (cpu_string, "default") == 0) | |
19579 | return 0; | |
19580 | ||
19581 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19582 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19583 | return p; | |
19584 | ||
20203fb9 | 19585 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19586 | return 0; |
e7af610e NC |
19587 | } |
19588 | ||
316f5878 RS |
19589 | /* Return the canonical processor information for ISA (a member of the |
19590 | ISA_MIPS* enumeration). */ | |
19591 | ||
e7af610e | 19592 | static const struct mips_cpu_info * |
17a2f251 | 19593 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19594 | { |
19595 | int i; | |
19596 | ||
19597 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19598 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19599 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19600 | return (&mips_cpu_info_table[i]); |
19601 | ||
e972090a | 19602 | return NULL; |
e7af610e | 19603 | } |
fef14a42 TS |
19604 | |
19605 | static const struct mips_cpu_info * | |
17a2f251 | 19606 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19607 | { |
19608 | int i; | |
19609 | ||
19610 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19611 | if (arch == mips_cpu_info_table[i].cpu) | |
19612 | return (&mips_cpu_info_table[i]); | |
19613 | ||
19614 | return NULL; | |
19615 | } | |
316f5878 RS |
19616 | \f |
19617 | static void | |
17a2f251 | 19618 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19619 | { |
19620 | if (*first_p) | |
19621 | { | |
19622 | fprintf (stream, "%24s", ""); | |
19623 | *col_p = 24; | |
19624 | } | |
19625 | else | |
19626 | { | |
19627 | fprintf (stream, ", "); | |
19628 | *col_p += 2; | |
19629 | } | |
e7af610e | 19630 | |
316f5878 RS |
19631 | if (*col_p + strlen (string) > 72) |
19632 | { | |
19633 | fprintf (stream, "\n%24s", ""); | |
19634 | *col_p = 24; | |
19635 | } | |
19636 | ||
19637 | fprintf (stream, "%s", string); | |
19638 | *col_p += strlen (string); | |
19639 | ||
19640 | *first_p = 0; | |
19641 | } | |
19642 | ||
19643 | void | |
17a2f251 | 19644 | md_show_usage (FILE *stream) |
e7af610e | 19645 | { |
316f5878 RS |
19646 | int column, first; |
19647 | size_t i; | |
19648 | ||
19649 | fprintf (stream, _("\ | |
19650 | MIPS options:\n\ | |
316f5878 RS |
19651 | -EB generate big endian output\n\ |
19652 | -EL generate little endian output\n\ | |
19653 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19654 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19655 | implicitly with the gp register [default 8]\n")); | |
19656 | fprintf (stream, _("\ | |
19657 | -mips1 generate MIPS ISA I instructions\n\ | |
19658 | -mips2 generate MIPS ISA II instructions\n\ | |
19659 | -mips3 generate MIPS ISA III instructions\n\ | |
19660 | -mips4 generate MIPS ISA IV instructions\n\ | |
19661 | -mips5 generate MIPS ISA V instructions\n\ | |
19662 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19663 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19664 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19665 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19666 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19667 | ||
19668 | first = 1; | |
e7af610e NC |
19669 | |
19670 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19671 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19672 | show (stream, "from-abi", &column, &first); | |
19673 | fputc ('\n', stream); | |
e7af610e | 19674 | |
316f5878 RS |
19675 | fprintf (stream, _("\ |
19676 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19677 | -no-mCPU don't generate code specific to CPU.\n\ | |
19678 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19679 | ||
19680 | first = 1; | |
19681 | ||
19682 | show (stream, "3900", &column, &first); | |
19683 | show (stream, "4010", &column, &first); | |
19684 | show (stream, "4100", &column, &first); | |
19685 | show (stream, "4650", &column, &first); | |
19686 | fputc ('\n', stream); | |
19687 | ||
19688 | fprintf (stream, _("\ | |
19689 | -mips16 generate mips16 instructions\n\ | |
19690 | -no-mips16 do not generate mips16 instructions\n")); | |
19691 | fprintf (stream, _("\ | |
df58fc94 RS |
19692 | -mmicromips generate microMIPS instructions\n\ |
19693 | -mno-micromips do not generate microMIPS instructions\n")); | |
19694 | fprintf (stream, _("\ | |
e16bfa71 TS |
19695 | -msmartmips generate smartmips instructions\n\ |
19696 | -mno-smartmips do not generate smartmips instructions\n")); | |
19697 | fprintf (stream, _("\ | |
74cd071d CF |
19698 | -mdsp generate DSP instructions\n\ |
19699 | -mno-dsp do not generate DSP instructions\n")); | |
19700 | fprintf (stream, _("\ | |
8b082fb1 TS |
19701 | -mdspr2 generate DSP R2 instructions\n\ |
19702 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19703 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19704 | -mmt generate MT instructions\n\ |
19705 | -mno-mt do not generate MT instructions\n")); | |
19706 | fprintf (stream, _("\ | |
dec0624d MR |
19707 | -mmcu generate MCU instructions\n\ |
19708 | -mno-mcu do not generate MCU instructions\n")); | |
19709 | fprintf (stream, _("\ | |
b015e599 AP |
19710 | -mvirt generate Virtualization instructions\n\ |
19711 | -mno-virt do not generate Virtualization instructions\n")); | |
19712 | fprintf (stream, _("\ | |
c67a084a NC |
19713 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19714 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19715 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19716 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19717 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19718 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19719 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19720 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19721 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19722 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19723 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19724 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19725 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19726 | fprintf (stream, _("\ |
19727 | -mhard-float allow floating-point instructions\n\ | |
19728 | -msoft-float do not allow floating-point instructions\n\ | |
19729 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19730 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb MR |
19731 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
19732 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n" | |
037b32b9 | 19733 | )); |
316f5878 RS |
19734 | #ifdef OBJ_ELF |
19735 | fprintf (stream, _("\ | |
19736 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19737 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19738 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19739 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19740 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19741 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19742 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19743 | position dependent (non shared) code\n\ |
316f5878 RS |
19744 | -mabi=ABI create ABI conformant object file for:\n")); |
19745 | ||
19746 | first = 1; | |
19747 | ||
19748 | show (stream, "32", &column, &first); | |
19749 | show (stream, "o64", &column, &first); | |
19750 | show (stream, "n32", &column, &first); | |
19751 | show (stream, "64", &column, &first); | |
19752 | show (stream, "eabi", &column, &first); | |
19753 | ||
19754 | fputc ('\n', stream); | |
19755 | ||
19756 | fprintf (stream, _("\ | |
19757 | -32 create o32 ABI object file (default)\n\ | |
19758 | -n32 create n32 ABI object file\n\ | |
19759 | -64 create 64 ABI object file\n")); | |
19760 | #endif | |
e7af610e | 19761 | } |
14e777e0 | 19762 | |
1575952e | 19763 | #ifdef TE_IRIX |
14e777e0 | 19764 | enum dwarf2_format |
413a266c | 19765 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19766 | { |
369943fe | 19767 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19768 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19769 | else |
19770 | return dwarf2_format_32bit; | |
19771 | } | |
1575952e | 19772 | #endif |
73369e65 EC |
19773 | |
19774 | int | |
19775 | mips_dwarf2_addr_size (void) | |
19776 | { | |
6b6b3450 | 19777 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19778 | return 8; |
73369e65 EC |
19779 | else |
19780 | return 4; | |
19781 | } | |
5862107c EC |
19782 | |
19783 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19784 | void | |
19785 | mips_cfi_frame_initial_instructions (void) | |
19786 | { | |
19787 | cfi_add_CFA_def_cfa_register (SP); | |
19788 | } | |
19789 | ||
707bfff6 TS |
19790 | int |
19791 | tc_mips_regname_to_dw2regnum (char *regname) | |
19792 | { | |
19793 | unsigned int regnum = -1; | |
19794 | unsigned int reg; | |
19795 | ||
19796 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19797 | regnum = reg; | |
19798 | ||
19799 | return regnum; | |
19800 | } |