Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
a325df1d TS |
122 | /* The ABI to use. */ |
123 | enum mips_abi_level | |
124 | { | |
125 | NO_ABI = 0, | |
126 | O32_ABI, | |
127 | O64_ABI, | |
128 | N32_ABI, | |
129 | N64_ABI, | |
130 | EABI_ABI | |
131 | }; | |
132 | ||
133 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 134 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 135 | |
143d77c5 EC |
136 | /* Whether or not we have code that can call pic code. */ |
137 | int mips_abicalls = FALSE; | |
138 | ||
aa6975fb ILT |
139 | /* Whether or not we have code which can be put into a shared |
140 | library. */ | |
141 | static bfd_boolean mips_in_shared = TRUE; | |
142 | ||
252b5132 RH |
143 | /* This is the set of options which may be modified by the .set |
144 | pseudo-op. We use a struct so that .set push and .set pop are more | |
145 | reliable. */ | |
146 | ||
e972090a NC |
147 | struct mips_set_options |
148 | { | |
252b5132 RH |
149 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
150 | if it has not been initialized. Changed by `.set mipsN', and the | |
151 | -mipsN command line option, and the default CPU. */ | |
152 | int isa; | |
1f25f5d3 CD |
153 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
154 | if they have not been initialized. Changed by `.set <asename>', by | |
155 | command line options, and based on the default architecture. */ | |
156 | int ase_mips3d; | |
deec1734 | 157 | int ase_mdmx; |
252b5132 RH |
158 | /* Whether we are assembling for the mips16 processor. 0 if we are |
159 | not, 1 if we are, and -1 if the value has not been initialized. | |
160 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
161 | -nomips16 command line options, and the default CPU. */ | |
162 | int mips16; | |
163 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
164 | reorder' and `.set noreorder'. */ | |
165 | int noreorder; | |
166 | /* Non-zero if we should not permit the $at ($1) register to be used | |
167 | in instructions. Changed by `.set at' and `.set noat'. */ | |
168 | int noat; | |
169 | /* Non-zero if we should warn when a macro instruction expands into | |
170 | more than one machine instruction. Changed by `.set nomacro' and | |
171 | `.set macro'. */ | |
172 | int warn_about_macros; | |
173 | /* Non-zero if we should not move instructions. Changed by `.set | |
174 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
175 | int nomove; | |
176 | /* Non-zero if we should not optimize branches by moving the target | |
177 | of the branch into the delay slot. Actually, we don't perform | |
178 | this optimization anyhow. Changed by `.set bopt' and `.set | |
179 | nobopt'. */ | |
180 | int nobopt; | |
181 | /* Non-zero if we should not autoextend mips16 instructions. | |
182 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
183 | int noautoextend; | |
a325df1d TS |
184 | /* Restrict general purpose registers and floating point registers |
185 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
186 | is passed but can changed if the assembler code uses .set mipsN. */ | |
187 | int gp32; | |
188 | int fp32; | |
fef14a42 TS |
189 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
190 | command line option, and the default CPU. */ | |
191 | int arch; | |
252b5132 RH |
192 | }; |
193 | ||
a325df1d | 194 | /* True if -mgp32 was passed. */ |
a8e8e863 | 195 | static int file_mips_gp32 = -1; |
a325df1d TS |
196 | |
197 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 198 | static int file_mips_fp32 = -1; |
a325df1d | 199 | |
252b5132 | 200 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 201 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 202 | -1 to indicate that they have not been initialized. */ |
252b5132 | 203 | |
e972090a NC |
204 | static struct mips_set_options mips_opts = |
205 | { | |
fef14a42 | 206 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 207 | }; |
252b5132 RH |
208 | |
209 | /* These variables are filled in with the masks of registers used. | |
210 | The object format code reads them and puts them in the appropriate | |
211 | place. */ | |
212 | unsigned long mips_gprmask; | |
213 | unsigned long mips_cprmask[4]; | |
214 | ||
215 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 216 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 217 | |
a4672219 TS |
218 | /* True if -mips16 was passed or implied by arguments passed on the |
219 | command line (e.g., by -march). */ | |
220 | static int file_ase_mips16; | |
221 | ||
1f25f5d3 CD |
222 | /* True if -mips3d was passed or implied by arguments passed on the |
223 | command line (e.g., by -march). */ | |
224 | static int file_ase_mips3d; | |
225 | ||
deec1734 CD |
226 | /* True if -mdmx was passed or implied by arguments passed on the |
227 | command line (e.g., by -march). */ | |
228 | static int file_ase_mdmx; | |
229 | ||
ec68c924 | 230 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 231 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 232 | static const char *mips_arch_string; |
ec68c924 EC |
233 | |
234 | /* The argument of the -mtune= flag. The architecture for which we | |
235 | are optimizing. */ | |
236 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 237 | static const char *mips_tune_string; |
ec68c924 | 238 | |
316f5878 | 239 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
240 | static int mips_32bitmode = 0; |
241 | ||
316f5878 RS |
242 | /* True if the given ABI requires 32-bit registers. */ |
243 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
244 | ||
245 | /* Likewise 64-bit registers. */ | |
246 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
247 | ((ABI) == N32_ABI \ | |
248 | || (ABI) == N64_ABI \ | |
249 | || (ABI) == O64_ABI) | |
250 | ||
bdaaa2e1 | 251 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 252 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
253 | (ISA) == ISA_MIPS3 \ |
254 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 255 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 256 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 257 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
258 | ) |
259 | ||
af7ee8bf CD |
260 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
261 | instructions. */ | |
262 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 263 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
264 | ) |
265 | ||
266 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
267 | instructions. */ | |
268 | #define ISA_HAS_ROR(ISA) ( \ | |
269 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 270 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
271 | ) |
272 | ||
e013f690 | 273 | #define HAVE_32BIT_GPRS \ |
316f5878 | 274 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 275 | |
e013f690 | 276 | #define HAVE_32BIT_FPRS \ |
316f5878 | 277 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
278 | |
279 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
280 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
281 | ||
316f5878 | 282 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 283 | |
316f5878 | 284 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 285 | |
3b91255e RS |
286 | /* True if relocations are stored in-place. */ |
287 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
288 | ||
3e722fb5 | 289 | /* We can only have 64bit addresses if the object file format supports it. */ |
afdbd6d0 CD |
290 | #define HAVE_32BIT_ADDRESSES \ |
291 | (HAVE_32BIT_GPRS \ | |
3e722fb5 CD |
292 | || (bfd_arch_bits_per_address (stdoutput) == 32 \ |
293 | || ! HAVE_64BIT_OBJECTS)) \ | |
e013f690 TS |
294 | |
295 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 296 | |
b7c7d6c1 TS |
297 | /* Addresses are loaded in different ways, depending on the address size |
298 | in use. The n32 ABI Documentation also mandates the use of additions | |
299 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 300 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 301 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
302 | |
303 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 304 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
305 | |
306 | #define ADDRESS_LOAD_INSN \ | |
307 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
308 | ||
309 | #define ADDRESS_STORE_INSN \ | |
310 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
311 | ||
a4672219 | 312 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
313 | #define CPU_HAS_MIPS16(cpu) \ |
314 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
315 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 316 | |
1f25f5d3 CD |
317 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
318 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
319 | ) | |
320 | ||
deec1734 | 321 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 322 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
323 | ) |
324 | ||
60b63b72 RS |
325 | /* True if CPU has a dror instruction. */ |
326 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
327 | ||
328 | /* True if CPU has a ror instruction. */ | |
329 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
330 | ||
c8978940 CD |
331 | /* True if mflo and mfhi can be immediately followed by instructions |
332 | which write to the HI and LO registers. | |
333 | ||
334 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
335 | (at least) two instructions between the reads of HI/LO and | |
336 | instructions which write them, and later ISAs do not. Contradicting | |
337 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
338 | the UM for the NEC Vr5000) document needing the instructions between | |
339 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
340 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
341 | earlier-ISA CPUs for which CPU documentation declares that the | |
342 | instructions are really interlocked. */ | |
343 | #define hilo_interlocks \ | |
344 | (mips_opts.isa == ISA_MIPS32 \ | |
345 | || mips_opts.isa == ISA_MIPS32R2 \ | |
346 | || mips_opts.isa == ISA_MIPS64 \ | |
347 | || mips_opts.isa == ISA_MIPS64R2 \ | |
348 | || mips_opts.arch == CPU_R4010 \ | |
349 | || mips_opts.arch == CPU_R10000 \ | |
350 | || mips_opts.arch == CPU_R12000 \ | |
351 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
352 | || mips_opts.arch == CPU_VR5500 \ |
353 | ) | |
252b5132 RH |
354 | |
355 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
356 | from the GPRs after they are loaded from memory, and thus does not |
357 | require nops to be inserted. This applies to instructions marked | |
358 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
359 | level I. */ | |
252b5132 | 360 | #define gpr_interlocks \ |
e7af610e | 361 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 362 | || mips_opts.arch == CPU_R3900) |
252b5132 | 363 | |
81912461 ILT |
364 | /* Whether the processor uses hardware interlocks to avoid delays |
365 | required by coprocessor instructions, and thus does not require | |
366 | nops to be inserted. This applies to instructions marked | |
367 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
368 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
369 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
370 | levels I, II, and III. */ | |
bdaaa2e1 | 371 | /* Itbl support may require additional care here. */ |
81912461 ILT |
372 | #define cop_interlocks \ |
373 | ((mips_opts.isa != ISA_MIPS1 \ | |
374 | && mips_opts.isa != ISA_MIPS2 \ | |
375 | && mips_opts.isa != ISA_MIPS3) \ | |
376 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
377 | ) |
378 | ||
379 | /* Whether the processor uses hardware interlocks to protect reads | |
380 | from coprocessor registers after they are loaded from memory, and | |
381 | thus does not require nops to be inserted. This applies to | |
382 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
383 | requires at MIPS ISA level I. */ | |
384 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 385 | |
6b76fefe CM |
386 | /* Is this a mfhi or mflo instruction? */ |
387 | #define MF_HILO_INSN(PINFO) \ | |
388 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
389 | ||
252b5132 RH |
390 | /* MIPS PIC level. */ |
391 | ||
a161fe53 | 392 | enum mips_pic_level mips_pic; |
252b5132 | 393 | |
c9914766 | 394 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 395 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 396 | static int mips_big_got = 0; |
252b5132 RH |
397 | |
398 | /* 1 if trap instructions should used for overflow rather than break | |
399 | instructions. */ | |
c9914766 | 400 | static int mips_trap = 0; |
252b5132 | 401 | |
119d663a | 402 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 403 | by assembling two single width halves into two single width floating |
119d663a NC |
404 | point registers which just happen to alias the double width destination |
405 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 406 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
407 | automatically at assemble time. */ |
408 | static int mips_disable_float_construction; | |
409 | ||
252b5132 RH |
410 | /* Non-zero if any .set noreorder directives were used. */ |
411 | ||
412 | static int mips_any_noreorder; | |
413 | ||
6b76fefe CM |
414 | /* Non-zero if nops should be inserted when the register referenced in |
415 | an mfhi/mflo instruction is read in the next two instructions. */ | |
416 | static int mips_7000_hilo_fix; | |
417 | ||
252b5132 | 418 | /* The size of the small data section. */ |
156c2f8b | 419 | static unsigned int g_switch_value = 8; |
252b5132 RH |
420 | /* Whether the -G option was used. */ |
421 | static int g_switch_seen = 0; | |
422 | ||
423 | #define N_RMASK 0xc4 | |
424 | #define N_VFP 0xd4 | |
425 | ||
426 | /* If we can determine in advance that GP optimization won't be | |
427 | possible, we can skip the relaxation stuff that tries to produce | |
428 | GP-relative references. This makes delay slot optimization work | |
429 | better. | |
430 | ||
431 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
432 | gcc output. It needs to guess right for gcc, otherwise gcc |
433 | will put what it thinks is a GP-relative instruction in a branch | |
434 | delay slot. | |
252b5132 RH |
435 | |
436 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
437 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 438 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
439 | |
440 | /* handle of the OPCODE hash table */ | |
441 | static struct hash_control *op_hash = NULL; | |
442 | ||
443 | /* The opcode hash table we use for the mips16. */ | |
444 | static struct hash_control *mips16_op_hash = NULL; | |
445 | ||
446 | /* This array holds the chars that always start a comment. If the | |
447 | pre-processor is disabled, these aren't very useful */ | |
448 | const char comment_chars[] = "#"; | |
449 | ||
450 | /* This array holds the chars that only start a comment at the beginning of | |
451 | a line. If the line seems to have the form '# 123 filename' | |
452 | .line and .file directives will appear in the pre-processed output */ | |
453 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
454 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 455 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
456 | /* Also note that C style comments are always supported. */ |
457 | const char line_comment_chars[] = "#"; | |
458 | ||
bdaaa2e1 | 459 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 460 | const char line_separator_chars[] = ";"; |
252b5132 RH |
461 | |
462 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
463 | const char EXP_CHARS[] = "eE"; | |
464 | ||
465 | /* Chars that mean this number is a floating point constant */ | |
466 | /* As in 0f12.456 */ | |
467 | /* or 0d1.2345e12 */ | |
468 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
469 | ||
470 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
471 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
472 | but nothing is ideal around here. | |
473 | */ | |
474 | ||
475 | static char *insn_error; | |
476 | ||
477 | static int auto_align = 1; | |
478 | ||
479 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
480 | offset in the stack frame from which to restore the $gp register. | |
481 | This is set by the .cprestore pseudo-op, and saved in this | |
482 | variable. */ | |
483 | static offsetT mips_cprestore_offset = -1; | |
484 | ||
67c1ffbe | 485 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 486 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 487 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
488 | static offsetT mips_cpreturn_offset = -1; |
489 | static int mips_cpreturn_register = -1; | |
490 | static int mips_gp_register = GP; | |
def2e0dd | 491 | static int mips_gprel_offset = 0; |
6478892d | 492 | |
7a621144 DJ |
493 | /* Whether mips_cprestore_offset has been set in the current function |
494 | (or whether it has already been warned about, if not). */ | |
495 | static int mips_cprestore_valid = 0; | |
496 | ||
252b5132 RH |
497 | /* This is the register which holds the stack frame, as set by the |
498 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
499 | static int mips_frame_reg = SP; | |
500 | ||
7a621144 DJ |
501 | /* Whether mips_frame_reg has been set in the current function |
502 | (or whether it has already been warned about, if not). */ | |
503 | static int mips_frame_reg_valid = 0; | |
504 | ||
252b5132 RH |
505 | /* To output NOP instructions correctly, we need to keep information |
506 | about the previous two instructions. */ | |
507 | ||
508 | /* Whether we are optimizing. The default value of 2 means to remove | |
509 | unneeded NOPs and swap branch instructions when possible. A value | |
510 | of 1 means to not swap branches. A value of 0 means to always | |
511 | insert NOPs. */ | |
512 | static int mips_optimize = 2; | |
513 | ||
514 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
515 | equivalent to seeing no -g option at all. */ | |
516 | static int mips_debug = 0; | |
517 | ||
518 | /* The previous instruction. */ | |
519 | static struct mips_cl_insn prev_insn; | |
520 | ||
521 | /* The instruction before prev_insn. */ | |
522 | static struct mips_cl_insn prev_prev_insn; | |
523 | ||
524 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
525 | point the insn_mo field at this dummy integer. */ | |
9c6ed8e6 | 526 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0 }; |
252b5132 RH |
527 | |
528 | /* Non-zero if prev_insn is valid. */ | |
529 | static int prev_insn_valid; | |
530 | ||
531 | /* The frag for the previous instruction. */ | |
532 | static struct frag *prev_insn_frag; | |
533 | ||
534 | /* The offset into prev_insn_frag for the previous instruction. */ | |
535 | static long prev_insn_where; | |
536 | ||
537 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 538 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
539 | |
540 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 541 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
542 | |
543 | /* Non-zero if the previous instruction was in a delay slot. */ | |
544 | static int prev_insn_is_delay_slot; | |
545 | ||
546 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
547 | static int prev_insn_unreordered; | |
548 | ||
549 | /* Non-zero if the previous instruction uses an extend opcode (if | |
550 | mips16). */ | |
551 | static int prev_insn_extended; | |
552 | ||
553 | /* Non-zero if the previous previous instruction was in a .set | |
554 | noreorder. */ | |
555 | static int prev_prev_insn_unreordered; | |
556 | ||
557 | /* If this is set, it points to a frag holding nop instructions which | |
558 | were inserted before the start of a noreorder section. If those | |
559 | nops turn out to be unnecessary, the size of the frag can be | |
560 | decreased. */ | |
561 | static fragS *prev_nop_frag; | |
562 | ||
563 | /* The number of nop instructions we created in prev_nop_frag. */ | |
564 | static int prev_nop_frag_holds; | |
565 | ||
566 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 567 | prev_nop_frag. */ |
252b5132 RH |
568 | static int prev_nop_frag_required; |
569 | ||
570 | /* The number of instructions we've seen since prev_nop_frag. */ | |
571 | static int prev_nop_frag_since; | |
572 | ||
573 | /* For ECOFF and ELF, relocations against symbols are done in two | |
574 | parts, with a HI relocation and a LO relocation. Each relocation | |
575 | has only 16 bits of space to store an addend. This means that in | |
576 | order for the linker to handle carries correctly, it must be able | |
577 | to locate both the HI and the LO relocation. This means that the | |
578 | relocations must appear in order in the relocation table. | |
579 | ||
580 | In order to implement this, we keep track of each unmatched HI | |
581 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 582 | corresponding LO relocation. */ |
252b5132 | 583 | |
e972090a NC |
584 | struct mips_hi_fixup |
585 | { | |
252b5132 RH |
586 | /* Next HI fixup. */ |
587 | struct mips_hi_fixup *next; | |
588 | /* This fixup. */ | |
589 | fixS *fixp; | |
590 | /* The section this fixup is in. */ | |
591 | segT seg; | |
592 | }; | |
593 | ||
594 | /* The list of unmatched HI relocs. */ | |
595 | ||
596 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
597 | ||
64bdfcaf RS |
598 | /* The frag containing the last explicit relocation operator. |
599 | Null if explicit relocations have not been used. */ | |
600 | ||
601 | static fragS *prev_reloc_op_frag; | |
602 | ||
252b5132 RH |
603 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
604 | ||
605 | #define X ILLEGAL_REG | |
e972090a NC |
606 | static const int mips32_to_16_reg_map[] = |
607 | { | |
252b5132 RH |
608 | X, X, 2, 3, 4, 5, 6, 7, |
609 | X, X, X, X, X, X, X, X, | |
610 | 0, 1, X, X, X, X, X, X, | |
611 | X, X, X, X, X, X, X, X | |
612 | }; | |
613 | #undef X | |
614 | ||
615 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
616 | ||
e972090a NC |
617 | static const unsigned int mips16_to_32_reg_map[] = |
618 | { | |
252b5132 RH |
619 | 16, 17, 2, 3, 4, 5, 6, 7 |
620 | }; | |
60b63b72 | 621 | |
d766e8ec | 622 | static int mips_fix_vr4120; |
4a6a3df4 AO |
623 | |
624 | /* We don't relax branches by default, since this causes us to expand | |
625 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
626 | fail to compute the offset before expanding the macro to the most | |
627 | efficient expansion. */ | |
628 | ||
629 | static int mips_relax_branch; | |
252b5132 | 630 | \f |
4d7206a2 RS |
631 | /* The expansion of many macros depends on the type of symbol that |
632 | they refer to. For example, when generating position-dependent code, | |
633 | a macro that refers to a symbol may have two different expansions, | |
634 | one which uses GP-relative addresses and one which uses absolute | |
635 | addresses. When generating SVR4-style PIC, a macro may have | |
636 | different expansions for local and global symbols. | |
637 | ||
638 | We handle these situations by generating both sequences and putting | |
639 | them in variant frags. In position-dependent code, the first sequence | |
640 | will be the GP-relative one and the second sequence will be the | |
641 | absolute one. In SVR4 PIC, the first sequence will be for global | |
642 | symbols and the second will be for local symbols. | |
643 | ||
584892a6 RS |
644 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
645 | SECOND are the lengths of the two sequences in bytes. These fields | |
646 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
647 | the subtype has the following flags: | |
4d7206a2 | 648 | |
584892a6 RS |
649 | RELAX_USE_SECOND |
650 | Set if it has been decided that we should use the second | |
651 | sequence instead of the first. | |
652 | ||
653 | RELAX_SECOND_LONGER | |
654 | Set in the first variant frag if the macro's second implementation | |
655 | is longer than its first. This refers to the macro as a whole, | |
656 | not an individual relaxation. | |
657 | ||
658 | RELAX_NOMACRO | |
659 | Set in the first variant frag if the macro appeared in a .set nomacro | |
660 | block and if one alternative requires a warning but the other does not. | |
661 | ||
662 | RELAX_DELAY_SLOT | |
663 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
664 | delay slot. | |
4d7206a2 RS |
665 | |
666 | The frag's "opcode" points to the first fixup for relaxable code. | |
667 | ||
668 | Relaxable macros are generated using a sequence such as: | |
669 | ||
670 | relax_start (SYMBOL); | |
671 | ... generate first expansion ... | |
672 | relax_switch (); | |
673 | ... generate second expansion ... | |
674 | relax_end (); | |
675 | ||
676 | The code and fixups for the unwanted alternative are discarded | |
677 | by md_convert_frag. */ | |
584892a6 | 678 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 679 | |
584892a6 RS |
680 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
681 | #define RELAX_SECOND(X) ((X) & 0xff) | |
682 | #define RELAX_USE_SECOND 0x10000 | |
683 | #define RELAX_SECOND_LONGER 0x20000 | |
684 | #define RELAX_NOMACRO 0x40000 | |
685 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 686 | |
4a6a3df4 AO |
687 | /* Branch without likely bit. If label is out of range, we turn: |
688 | ||
689 | beq reg1, reg2, label | |
690 | delay slot | |
691 | ||
692 | into | |
693 | ||
694 | bne reg1, reg2, 0f | |
695 | nop | |
696 | j label | |
697 | 0: delay slot | |
698 | ||
699 | with the following opcode replacements: | |
700 | ||
701 | beq <-> bne | |
702 | blez <-> bgtz | |
703 | bltz <-> bgez | |
704 | bc1f <-> bc1t | |
705 | ||
706 | bltzal <-> bgezal (with jal label instead of j label) | |
707 | ||
708 | Even though keeping the delay slot instruction in the delay slot of | |
709 | the branch would be more efficient, it would be very tricky to do | |
710 | correctly, because we'd have to introduce a variable frag *after* | |
711 | the delay slot instruction, and expand that instead. Let's do it | |
712 | the easy way for now, even if the branch-not-taken case now costs | |
713 | one additional instruction. Out-of-range branches are not supposed | |
714 | to be common, anyway. | |
715 | ||
716 | Branch likely. If label is out of range, we turn: | |
717 | ||
718 | beql reg1, reg2, label | |
719 | delay slot (annulled if branch not taken) | |
720 | ||
721 | into | |
722 | ||
723 | beql reg1, reg2, 1f | |
724 | nop | |
725 | beql $0, $0, 2f | |
726 | nop | |
727 | 1: j[al] label | |
728 | delay slot (executed only if branch taken) | |
729 | 2: | |
730 | ||
731 | It would be possible to generate a shorter sequence by losing the | |
732 | likely bit, generating something like: | |
b34976b6 | 733 | |
4a6a3df4 AO |
734 | bne reg1, reg2, 0f |
735 | nop | |
736 | j[al] label | |
737 | delay slot (executed only if branch taken) | |
738 | 0: | |
739 | ||
740 | beql -> bne | |
741 | bnel -> beq | |
742 | blezl -> bgtz | |
743 | bgtzl -> blez | |
744 | bltzl -> bgez | |
745 | bgezl -> bltz | |
746 | bc1fl -> bc1t | |
747 | bc1tl -> bc1f | |
748 | ||
749 | bltzall -> bgezal (with jal label instead of j label) | |
750 | bgezall -> bltzal (ditto) | |
751 | ||
752 | ||
753 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 754 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
755 | ((relax_substateT) \ |
756 | (0xc0000000 \ | |
757 | | ((toofar) ? 1 : 0) \ | |
758 | | ((link) ? 2 : 0) \ | |
759 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 760 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 761 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
762 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
763 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
764 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 765 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 766 | |
252b5132 RH |
767 | /* For mips16 code, we use an entirely different form of relaxation. |
768 | mips16 supports two versions of most instructions which take | |
769 | immediate values: a small one which takes some small value, and a | |
770 | larger one which takes a 16 bit value. Since branches also follow | |
771 | this pattern, relaxing these values is required. | |
772 | ||
773 | We can assemble both mips16 and normal MIPS code in a single | |
774 | object. Therefore, we need to support this type of relaxation at | |
775 | the same time that we support the relaxation described above. We | |
776 | use the high bit of the subtype field to distinguish these cases. | |
777 | ||
778 | The information we store for this type of relaxation is the | |
779 | argument code found in the opcode file for this relocation, whether | |
780 | the user explicitly requested a small or extended form, and whether | |
781 | the relocation is in a jump or jal delay slot. That tells us the | |
782 | size of the value, and how it should be stored. We also store | |
783 | whether the fragment is considered to be extended or not. We also | |
784 | store whether this is known to be a branch to a different section, | |
785 | whether we have tried to relax this frag yet, and whether we have | |
786 | ever extended a PC relative fragment because of a shift count. */ | |
787 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
788 | (0x80000000 \ | |
789 | | ((type) & 0xff) \ | |
790 | | ((small) ? 0x100 : 0) \ | |
791 | | ((ext) ? 0x200 : 0) \ | |
792 | | ((dslot) ? 0x400 : 0) \ | |
793 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 794 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
795 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
796 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
797 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
798 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
799 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
800 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
801 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
802 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
803 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
804 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
805 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
806 | |
807 | /* Is the given value a sign-extended 32-bit value? */ | |
808 | #define IS_SEXT_32BIT_NUM(x) \ | |
809 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
810 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
811 | ||
812 | /* Is the given value a sign-extended 16-bit value? */ | |
813 | #define IS_SEXT_16BIT_NUM(x) \ | |
814 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
815 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
816 | ||
4d7206a2 RS |
817 | \f |
818 | /* Global variables used when generating relaxable macros. See the | |
819 | comment above RELAX_ENCODE for more details about how relaxation | |
820 | is used. */ | |
821 | static struct { | |
822 | /* 0 if we're not emitting a relaxable macro. | |
823 | 1 if we're emitting the first of the two relaxation alternatives. | |
824 | 2 if we're emitting the second alternative. */ | |
825 | int sequence; | |
826 | ||
827 | /* The first relaxable fixup in the current frag. (In other words, | |
828 | the first fixup that refers to relaxable code.) */ | |
829 | fixS *first_fixup; | |
830 | ||
831 | /* sizes[0] says how many bytes of the first alternative are stored in | |
832 | the current frag. Likewise sizes[1] for the second alternative. */ | |
833 | unsigned int sizes[2]; | |
834 | ||
835 | /* The symbol on which the choice of sequence depends. */ | |
836 | symbolS *symbol; | |
837 | } mips_relax; | |
252b5132 | 838 | \f |
584892a6 RS |
839 | /* Global variables used to decide whether a macro needs a warning. */ |
840 | static struct { | |
841 | /* True if the macro is in a branch delay slot. */ | |
842 | bfd_boolean delay_slot_p; | |
843 | ||
844 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
845 | in bytes and sizes[1] is the length of the second alternative. | |
846 | For non-relaxable macros, both elements give the length of the | |
847 | macro in bytes. */ | |
848 | unsigned int sizes[2]; | |
849 | ||
850 | /* The first variant frag for this macro. */ | |
851 | fragS *first_frag; | |
852 | } mips_macro_warning; | |
853 | \f | |
252b5132 RH |
854 | /* Prototypes for static functions. */ |
855 | ||
17a2f251 | 856 | #define internalError() \ |
252b5132 | 857 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
858 | |
859 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
860 | ||
b34976b6 | 861 | static void append_insn |
4d7206a2 | 862 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 863 | static void mips_no_prev_insn (int); |
b34976b6 | 864 | static void mips16_macro_build |
67c0d1eb RS |
865 | (expressionS *, const char *, const char *, va_list); |
866 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
867 | static void macro_start (void); |
868 | static void macro_end (void); | |
17a2f251 TS |
869 | static void macro (struct mips_cl_insn * ip); |
870 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 871 | #ifdef LOSING_COMPILER |
17a2f251 | 872 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 873 | #endif |
17a2f251 TS |
874 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
875 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 876 | static void mips16_immed |
17a2f251 TS |
877 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
878 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 879 | static size_t my_getSmallExpression |
17a2f251 TS |
880 | (expressionS *, bfd_reloc_code_real_type *, char *); |
881 | static void my_getExpression (expressionS *, char *); | |
882 | static void s_align (int); | |
883 | static void s_change_sec (int); | |
884 | static void s_change_section (int); | |
885 | static void s_cons (int); | |
886 | static void s_float_cons (int); | |
887 | static void s_mips_globl (int); | |
888 | static void s_option (int); | |
889 | static void s_mipsset (int); | |
890 | static void s_abicalls (int); | |
891 | static void s_cpload (int); | |
892 | static void s_cpsetup (int); | |
893 | static void s_cplocal (int); | |
894 | static void s_cprestore (int); | |
895 | static void s_cpreturn (int); | |
896 | static void s_gpvalue (int); | |
897 | static void s_gpword (int); | |
898 | static void s_gpdword (int); | |
899 | static void s_cpadd (int); | |
900 | static void s_insn (int); | |
901 | static void md_obj_begin (void); | |
902 | static void md_obj_end (void); | |
903 | static void s_mips_ent (int); | |
904 | static void s_mips_end (int); | |
905 | static void s_mips_frame (int); | |
906 | static void s_mips_mask (int reg_type); | |
907 | static void s_mips_stab (int); | |
908 | static void s_mips_weakext (int); | |
909 | static void s_mips_file (int); | |
910 | static void s_mips_loc (int); | |
911 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 912 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 913 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
914 | |
915 | /* Table and functions used to map between CPU/ISA names, and | |
916 | ISA levels, and CPU numbers. */ | |
917 | ||
e972090a NC |
918 | struct mips_cpu_info |
919 | { | |
e7af610e NC |
920 | const char *name; /* CPU or ISA name. */ |
921 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
922 | int isa; /* ISA level. */ | |
923 | int cpu; /* CPU number (default CPU if ISA). */ | |
924 | }; | |
925 | ||
17a2f251 TS |
926 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
927 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
928 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
929 | \f |
930 | /* Pseudo-op table. | |
931 | ||
932 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
933 | should be defined here, but are currently unsupported: .alias, | |
934 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
935 | ||
936 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
937 | specific to the type of debugging information being generated, and | |
938 | should be defined by the object format: .aent, .begin, .bend, | |
939 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
940 | .vreg. | |
941 | ||
942 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
943 | not MIPS CPU specific, but are also not specific to the object file | |
944 | format. This file is probably the best place to define them, but | |
945 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
946 | .struct. */ | |
947 | ||
e972090a NC |
948 | static const pseudo_typeS mips_pseudo_table[] = |
949 | { | |
beae10d5 | 950 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
951 | {"option", s_option, 0}, |
952 | {"set", s_mipsset, 0}, | |
953 | {"rdata", s_change_sec, 'r'}, | |
954 | {"sdata", s_change_sec, 's'}, | |
955 | {"livereg", s_ignore, 0}, | |
956 | {"abicalls", s_abicalls, 0}, | |
957 | {"cpload", s_cpload, 0}, | |
6478892d TS |
958 | {"cpsetup", s_cpsetup, 0}, |
959 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 960 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
961 | {"cpreturn", s_cpreturn, 0}, |
962 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 963 | {"gpword", s_gpword, 0}, |
10181a0d | 964 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
965 | {"cpadd", s_cpadd, 0}, |
966 | {"insn", s_insn, 0}, | |
967 | ||
beae10d5 | 968 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
969 | chips. */ |
970 | {"asciiz", stringer, 1}, | |
971 | {"bss", s_change_sec, 'b'}, | |
972 | {"err", s_err, 0}, | |
973 | {"half", s_cons, 1}, | |
974 | {"dword", s_cons, 3}, | |
975 | {"weakext", s_mips_weakext, 0}, | |
976 | ||
beae10d5 | 977 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
978 | here for one reason or another. */ |
979 | {"align", s_align, 0}, | |
980 | {"byte", s_cons, 0}, | |
981 | {"data", s_change_sec, 'd'}, | |
982 | {"double", s_float_cons, 'd'}, | |
983 | {"float", s_float_cons, 'f'}, | |
984 | {"globl", s_mips_globl, 0}, | |
985 | {"global", s_mips_globl, 0}, | |
986 | {"hword", s_cons, 1}, | |
987 | {"int", s_cons, 2}, | |
988 | {"long", s_cons, 2}, | |
989 | {"octa", s_cons, 4}, | |
990 | {"quad", s_cons, 3}, | |
cca86cc8 | 991 | {"section", s_change_section, 0}, |
252b5132 RH |
992 | {"short", s_cons, 1}, |
993 | {"single", s_float_cons, 'f'}, | |
994 | {"stabn", s_mips_stab, 'n'}, | |
995 | {"text", s_change_sec, 't'}, | |
996 | {"word", s_cons, 2}, | |
add56521 | 997 | |
add56521 | 998 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 999 | |
43841e91 | 1000 | { NULL, NULL, 0 }, |
252b5132 RH |
1001 | }; |
1002 | ||
e972090a NC |
1003 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1004 | { | |
beae10d5 KH |
1005 | /* These pseudo-ops should be defined by the object file format. |
1006 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1007 | {"aent", s_mips_ent, 1}, |
1008 | {"bgnb", s_ignore, 0}, | |
1009 | {"end", s_mips_end, 0}, | |
1010 | {"endb", s_ignore, 0}, | |
1011 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1012 | {"file", s_mips_file, 0}, |
252b5132 RH |
1013 | {"fmask", s_mips_mask, 'F'}, |
1014 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1015 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1016 | {"mask", s_mips_mask, 'R'}, |
1017 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1018 | { NULL, NULL, 0 }, |
252b5132 RH |
1019 | }; |
1020 | ||
17a2f251 | 1021 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1022 | |
1023 | void | |
17a2f251 | 1024 | mips_pop_insert (void) |
252b5132 RH |
1025 | { |
1026 | pop_insert (mips_pseudo_table); | |
1027 | if (! ECOFF_DEBUGGING) | |
1028 | pop_insert (mips_nonecoff_pseudo_table); | |
1029 | } | |
1030 | \f | |
1031 | /* Symbols labelling the current insn. */ | |
1032 | ||
e972090a NC |
1033 | struct insn_label_list |
1034 | { | |
252b5132 RH |
1035 | struct insn_label_list *next; |
1036 | symbolS *label; | |
1037 | }; | |
1038 | ||
1039 | static struct insn_label_list *insn_labels; | |
1040 | static struct insn_label_list *free_insn_labels; | |
1041 | ||
17a2f251 | 1042 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1043 | |
1044 | static inline void | |
17a2f251 | 1045 | mips_clear_insn_labels (void) |
252b5132 RH |
1046 | { |
1047 | register struct insn_label_list **pl; | |
1048 | ||
1049 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1050 | ; | |
1051 | *pl = insn_labels; | |
1052 | insn_labels = NULL; | |
1053 | } | |
1054 | \f | |
1055 | static char *expr_end; | |
1056 | ||
1057 | /* Expressions which appear in instructions. These are set by | |
1058 | mips_ip. */ | |
1059 | ||
1060 | static expressionS imm_expr; | |
5f74bc13 | 1061 | static expressionS imm2_expr; |
252b5132 RH |
1062 | static expressionS offset_expr; |
1063 | ||
1064 | /* Relocs associated with imm_expr and offset_expr. */ | |
1065 | ||
f6688943 TS |
1066 | static bfd_reloc_code_real_type imm_reloc[3] |
1067 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1068 | static bfd_reloc_code_real_type offset_reloc[3] | |
1069 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1070 | |
252b5132 RH |
1071 | /* These are set by mips16_ip if an explicit extension is used. */ |
1072 | ||
b34976b6 | 1073 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1074 | |
7ed4a06a | 1075 | #ifdef OBJ_ELF |
ecb4347a DJ |
1076 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1077 | ECOFF debugging. */ | |
252b5132 RH |
1078 | |
1079 | static segT pdr_seg; | |
7ed4a06a | 1080 | #endif |
252b5132 | 1081 | |
e013f690 TS |
1082 | /* The default target format to use. */ |
1083 | ||
1084 | const char * | |
17a2f251 | 1085 | mips_target_format (void) |
e013f690 TS |
1086 | { |
1087 | switch (OUTPUT_FLAVOR) | |
1088 | { | |
e013f690 TS |
1089 | case bfd_target_ecoff_flavour: |
1090 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1091 | case bfd_target_coff_flavour: | |
1092 | return "pe-mips"; | |
1093 | case bfd_target_elf_flavour: | |
1094 | #ifdef TE_TMIPS | |
cfe86eaa | 1095 | /* This is traditional mips. */ |
e013f690 | 1096 | return (target_big_endian |
cfe86eaa TS |
1097 | ? (HAVE_64BIT_OBJECTS |
1098 | ? "elf64-tradbigmips" | |
1099 | : (HAVE_NEWABI | |
1100 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1101 | : (HAVE_64BIT_OBJECTS | |
1102 | ? "elf64-tradlittlemips" | |
1103 | : (HAVE_NEWABI | |
1104 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1105 | #else |
1106 | return (target_big_endian | |
cfe86eaa TS |
1107 | ? (HAVE_64BIT_OBJECTS |
1108 | ? "elf64-bigmips" | |
1109 | : (HAVE_NEWABI | |
1110 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1111 | : (HAVE_64BIT_OBJECTS | |
1112 | ? "elf64-littlemips" | |
1113 | : (HAVE_NEWABI | |
1114 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1115 | #endif |
1116 | default: | |
1117 | abort (); | |
1118 | return NULL; | |
1119 | } | |
1120 | } | |
1121 | ||
156c2f8b NC |
1122 | /* This function is called once, at assembler startup time. It should |
1123 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1124 | ||
252b5132 | 1125 | void |
17a2f251 | 1126 | md_begin (void) |
252b5132 | 1127 | { |
252b5132 | 1128 | register const char *retval = NULL; |
156c2f8b | 1129 | int i = 0; |
252b5132 | 1130 | int broken = 0; |
1f25f5d3 | 1131 | |
fef14a42 | 1132 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1133 | as_warn (_("Could not set architecture and machine")); |
1134 | ||
252b5132 RH |
1135 | op_hash = hash_new (); |
1136 | ||
1137 | for (i = 0; i < NUMOPCODES;) | |
1138 | { | |
1139 | const char *name = mips_opcodes[i].name; | |
1140 | ||
17a2f251 | 1141 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1142 | if (retval != NULL) |
1143 | { | |
1144 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1145 | mips_opcodes[i].name, retval); | |
1146 | /* Probably a memory allocation problem? Give up now. */ | |
1147 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1148 | } | |
1149 | do | |
1150 | { | |
1151 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1152 | { | |
1153 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1154 | broken = 1; | |
1155 | } | |
1156 | ++i; | |
1157 | } | |
1158 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1159 | } | |
1160 | ||
1161 | mips16_op_hash = hash_new (); | |
1162 | ||
1163 | i = 0; | |
1164 | while (i < bfd_mips16_num_opcodes) | |
1165 | { | |
1166 | const char *name = mips16_opcodes[i].name; | |
1167 | ||
17a2f251 | 1168 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1169 | if (retval != NULL) |
1170 | as_fatal (_("internal: can't hash `%s': %s"), | |
1171 | mips16_opcodes[i].name, retval); | |
1172 | do | |
1173 | { | |
1174 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1175 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1176 | != mips16_opcodes[i].match)) | |
1177 | { | |
1178 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1179 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1180 | broken = 1; | |
1181 | } | |
1182 | ++i; | |
1183 | } | |
1184 | while (i < bfd_mips16_num_opcodes | |
1185 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1186 | } | |
1187 | ||
1188 | if (broken) | |
1189 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1190 | ||
1191 | /* We add all the general register names to the symbol table. This | |
1192 | helps us detect invalid uses of them. */ | |
1193 | for (i = 0; i < 32; i++) | |
1194 | { | |
1195 | char buf[5]; | |
1196 | ||
1197 | sprintf (buf, "$%d", i); | |
1198 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1199 | &zero_address_frag)); | |
1200 | } | |
76db943d TS |
1201 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1202 | &zero_address_frag)); | |
252b5132 RH |
1203 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1204 | &zero_address_frag)); | |
1205 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1206 | &zero_address_frag)); | |
1207 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1208 | &zero_address_frag)); | |
1209 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1210 | &zero_address_frag)); | |
1211 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1212 | &zero_address_frag)); | |
1213 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1214 | &zero_address_frag)); | |
85b51719 TS |
1215 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1216 | &zero_address_frag)); | |
252b5132 RH |
1217 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1218 | &zero_address_frag)); | |
1219 | ||
6047c971 AO |
1220 | /* If we don't add these register names to the symbol table, they |
1221 | may end up being added as regular symbols by operand(), and then | |
1222 | make it to the object file as undefined in case they're not | |
1223 | regarded as local symbols. They're local in o32, since `$' is a | |
1224 | local symbol prefix, but not in n32 or n64. */ | |
1225 | for (i = 0; i < 8; i++) | |
1226 | { | |
1227 | char buf[6]; | |
1228 | ||
1229 | sprintf (buf, "$fcc%i", i); | |
1230 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1231 | &zero_address_frag)); | |
1232 | } | |
1233 | ||
b34976b6 | 1234 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1235 | |
1236 | mips_gprmask = 0; | |
1237 | mips_cprmask[0] = 0; | |
1238 | mips_cprmask[1] = 0; | |
1239 | mips_cprmask[2] = 0; | |
1240 | mips_cprmask[3] = 0; | |
1241 | ||
1242 | /* set the default alignment for the text section (2**2) */ | |
1243 | record_alignment (text_section, 2); | |
1244 | ||
4d0d148d | 1245 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1246 | |
1247 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1248 | { | |
1249 | /* On a native system, sections must be aligned to 16 byte | |
1250 | boundaries. When configured for an embedded ELF target, we | |
1251 | don't bother. */ | |
1252 | if (strcmp (TARGET_OS, "elf") != 0) | |
1253 | { | |
1254 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1255 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1256 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1257 | } | |
1258 | ||
1259 | /* Create a .reginfo section for register masks and a .mdebug | |
1260 | section for debugging information. */ | |
1261 | { | |
1262 | segT seg; | |
1263 | subsegT subseg; | |
1264 | flagword flags; | |
1265 | segT sec; | |
1266 | ||
1267 | seg = now_seg; | |
1268 | subseg = now_subseg; | |
1269 | ||
1270 | /* The ABI says this section should be loaded so that the | |
1271 | running program can access it. However, we don't load it | |
1272 | if we are configured for an embedded target */ | |
1273 | flags = SEC_READONLY | SEC_DATA; | |
1274 | if (strcmp (TARGET_OS, "elf") != 0) | |
1275 | flags |= SEC_ALLOC | SEC_LOAD; | |
1276 | ||
316f5878 | 1277 | if (mips_abi != N64_ABI) |
252b5132 RH |
1278 | { |
1279 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1280 | ||
195325d2 TS |
1281 | bfd_set_section_flags (stdoutput, sec, flags); |
1282 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1283 | |
252b5132 RH |
1284 | #ifdef OBJ_ELF |
1285 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1286 | #endif | |
1287 | } | |
1288 | else | |
1289 | { | |
1290 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1291 | .reginfo section. */ | |
1292 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1293 | bfd_set_section_flags (stdoutput, sec, flags); |
1294 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1295 | |
1296 | #ifdef OBJ_ELF | |
1297 | /* Set up the option header. */ | |
1298 | { | |
1299 | Elf_Internal_Options opthdr; | |
1300 | char *f; | |
1301 | ||
1302 | opthdr.kind = ODK_REGINFO; | |
1303 | opthdr.size = (sizeof (Elf_External_Options) | |
1304 | + sizeof (Elf64_External_RegInfo)); | |
1305 | opthdr.section = 0; | |
1306 | opthdr.info = 0; | |
1307 | f = frag_more (sizeof (Elf_External_Options)); | |
1308 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1309 | (Elf_External_Options *) f); | |
1310 | ||
1311 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1312 | } | |
1313 | #endif | |
1314 | } | |
1315 | ||
1316 | if (ECOFF_DEBUGGING) | |
1317 | { | |
1318 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1319 | (void) bfd_set_section_flags (stdoutput, sec, | |
1320 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1321 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1322 | } | |
ecb4347a | 1323 | #ifdef OBJ_ELF |
dcd410fe | 1324 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1325 | { |
1326 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1327 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1328 | SEC_READONLY | SEC_RELOC | |
1329 | | SEC_DEBUGGING); | |
1330 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1331 | } | |
252b5132 RH |
1332 | #endif |
1333 | ||
1334 | subseg_set (seg, subseg); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | if (! ECOFF_DEBUGGING) | |
1339 | md_obj_begin (); | |
1340 | } | |
1341 | ||
1342 | void | |
17a2f251 | 1343 | md_mips_end (void) |
252b5132 RH |
1344 | { |
1345 | if (! ECOFF_DEBUGGING) | |
1346 | md_obj_end (); | |
1347 | } | |
1348 | ||
1349 | void | |
17a2f251 | 1350 | md_assemble (char *str) |
252b5132 RH |
1351 | { |
1352 | struct mips_cl_insn insn; | |
f6688943 TS |
1353 | bfd_reloc_code_real_type unused_reloc[3] |
1354 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1355 | |
1356 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1357 | imm2_expr.X_op = O_absent; |
252b5132 | 1358 | offset_expr.X_op = O_absent; |
f6688943 TS |
1359 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1360 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1361 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1362 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1363 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1364 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1365 | |
1366 | if (mips_opts.mips16) | |
1367 | mips16_ip (str, &insn); | |
1368 | else | |
1369 | { | |
1370 | mips_ip (str, &insn); | |
beae10d5 KH |
1371 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1372 | str, insn.insn_opcode)); | |
252b5132 RH |
1373 | } |
1374 | ||
1375 | if (insn_error) | |
1376 | { | |
1377 | as_bad ("%s `%s'", insn_error, str); | |
1378 | return; | |
1379 | } | |
1380 | ||
1381 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1382 | { | |
584892a6 | 1383 | macro_start (); |
252b5132 RH |
1384 | if (mips_opts.mips16) |
1385 | mips16_macro (&insn); | |
1386 | else | |
1387 | macro (&insn); | |
584892a6 | 1388 | macro_end (); |
252b5132 RH |
1389 | } |
1390 | else | |
1391 | { | |
1392 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1393 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1394 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1395 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1396 | else |
4d7206a2 | 1397 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1398 | } |
1399 | } | |
1400 | ||
5919d012 RS |
1401 | /* Return true if the given relocation might need a matching %lo(). |
1402 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1403 | applied to local symbols. */ | |
1404 | ||
1405 | static inline bfd_boolean | |
17a2f251 | 1406 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1407 | { |
3b91255e RS |
1408 | return (HAVE_IN_PLACE_ADDENDS |
1409 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1410 | || reloc == BFD_RELOC_MIPS_GOT16 |
1411 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1412 | } |
1413 | ||
1414 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1415 | relocation. */ | |
1416 | ||
1417 | static inline bfd_boolean | |
17a2f251 | 1418 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1419 | { |
1420 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1421 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1422 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1423 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1424 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1425 | } | |
1426 | ||
252b5132 RH |
1427 | /* See whether instruction IP reads register REG. CLASS is the type |
1428 | of register. */ | |
1429 | ||
1430 | static int | |
17a2f251 TS |
1431 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1432 | enum mips_regclass class) | |
252b5132 RH |
1433 | { |
1434 | if (class == MIPS16_REG) | |
1435 | { | |
1436 | assert (mips_opts.mips16); | |
1437 | reg = mips16_to_32_reg_map[reg]; | |
1438 | class = MIPS_GR_REG; | |
1439 | } | |
1440 | ||
85b51719 TS |
1441 | /* Don't report on general register ZERO, since it never changes. */ |
1442 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1443 | return 0; |
1444 | ||
1445 | if (class == MIPS_FP_REG) | |
1446 | { | |
1447 | assert (! mips_opts.mips16); | |
1448 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1449 | This is not optimal, because it will introduce an unnecessary | |
1450 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1451 | need to distinguish reading both $f0 and $f1 or just one of | |
1452 | them. Note that we don't have to check the other way, | |
1453 | because there is no instruction that sets both $f0 and $f1 | |
1454 | and requires a delay. */ | |
1455 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1456 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1457 | == (reg &~ (unsigned) 1))) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1460 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1461 | == (reg &~ (unsigned) 1))) | |
1462 | return 1; | |
1463 | } | |
1464 | else if (! mips_opts.mips16) | |
1465 | { | |
1466 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1467 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1468 | return 1; | |
1469 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1470 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1471 | return 1; | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1476 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1477 | & MIPS16OP_MASK_RX)] | |
1478 | == reg)) | |
1479 | return 1; | |
1480 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1481 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1482 | & MIPS16OP_MASK_RY)] | |
1483 | == reg)) | |
1484 | return 1; | |
1485 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1486 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1487 | & MIPS16OP_MASK_MOVE32Z)] | |
1488 | == reg)) | |
1489 | return 1; | |
1490 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1491 | return 1; | |
1492 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1493 | return 1; | |
1494 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1495 | return 1; | |
1496 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1497 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1498 | & MIPS16OP_MASK_REGR32) == reg) | |
1499 | return 1; | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | /* This function returns true if modifying a register requires a | |
1506 | delay. */ | |
1507 | ||
1508 | static int | |
17a2f251 | 1509 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1510 | { |
1511 | unsigned long prev_pinfo; | |
1512 | ||
1513 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1514 | if (! mips_opts.noreorder | |
81912461 ILT |
1515 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1516 | && ! gpr_interlocks) | |
1517 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1518 | && ! cop_interlocks))) | |
252b5132 | 1519 | { |
81912461 ILT |
1520 | /* A load from a coprocessor or from memory. All load delays |
1521 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1522 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1523 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1524 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1525 | return 1; | |
1526 | } | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1532 | handle them specially, such as generating jalx instructions when | |
1533 | needed. We also make them odd for the duration of the assembly, in | |
1534 | order to generate the right sort of code. We will make them even | |
1535 | in the adjust_symtab routine, while leaving them marked. This is | |
1536 | convenient for the debugger and the disassembler. The linker knows | |
1537 | to make them odd again. */ | |
1538 | ||
1539 | static void | |
17a2f251 | 1540 | mips16_mark_labels (void) |
252b5132 RH |
1541 | { |
1542 | if (mips_opts.mips16) | |
1543 | { | |
1544 | struct insn_label_list *l; | |
98aa84af | 1545 | valueT val; |
252b5132 RH |
1546 | |
1547 | for (l = insn_labels; l != NULL; l = l->next) | |
1548 | { | |
1549 | #ifdef OBJ_ELF | |
1550 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1551 | S_SET_OTHER (l->label, STO_MIPS16); | |
1552 | #endif | |
98aa84af AM |
1553 | val = S_GET_VALUE (l->label); |
1554 | if ((val & 1) == 0) | |
1555 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1556 | } |
1557 | } | |
1558 | } | |
1559 | ||
4d7206a2 RS |
1560 | /* End the current frag. Make it a variant frag and record the |
1561 | relaxation info. */ | |
1562 | ||
1563 | static void | |
1564 | relax_close_frag (void) | |
1565 | { | |
584892a6 | 1566 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1567 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1568 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1569 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1570 | ||
1571 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1572 | mips_relax.first_fixup = 0; | |
1573 | } | |
1574 | ||
1575 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1576 | See the comment above RELAX_ENCODE for more details. */ | |
1577 | ||
1578 | static void | |
1579 | relax_start (symbolS *symbol) | |
1580 | { | |
1581 | assert (mips_relax.sequence == 0); | |
1582 | mips_relax.sequence = 1; | |
1583 | mips_relax.symbol = symbol; | |
1584 | } | |
1585 | ||
1586 | /* Start generating the second version of a relaxable sequence. | |
1587 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1588 | |
1589 | static void | |
4d7206a2 RS |
1590 | relax_switch (void) |
1591 | { | |
1592 | assert (mips_relax.sequence == 1); | |
1593 | mips_relax.sequence = 2; | |
1594 | } | |
1595 | ||
1596 | /* End the current relaxable sequence. */ | |
1597 | ||
1598 | static void | |
1599 | relax_end (void) | |
1600 | { | |
1601 | assert (mips_relax.sequence == 2); | |
1602 | relax_close_frag (); | |
1603 | mips_relax.sequence = 0; | |
1604 | } | |
1605 | ||
1606 | /* Output an instruction. IP is the instruction information. | |
1607 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1608 | RELOC_TYPE. */ | |
1609 | ||
1610 | static void | |
1611 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1612 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1613 | { |
1614 | register unsigned long prev_pinfo, pinfo; | |
1615 | char *f; | |
f6688943 | 1616 | fixS *fixp[3]; |
252b5132 | 1617 | int nops = 0; |
895921c9 MR |
1618 | relax_stateT prev_insn_frag_type = 0; |
1619 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1620 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1621 | |
1622 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1623 | mips16_mark_labels (); |
252b5132 RH |
1624 | |
1625 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1626 | pinfo = ip->insn_mo->pinfo; | |
1627 | ||
4d7206a2 RS |
1628 | if (mips_relax.sequence != 2 |
1629 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1630 | { |
1631 | int prev_prev_nop; | |
1632 | ||
1633 | /* If the previous insn required any delay slots, see if we need | |
1634 | to insert a NOP or two. There are eight kinds of possible | |
1635 | hazards, of which an instruction can have at most one type. | |
1636 | (1) a load from memory delay | |
1637 | (2) a load from a coprocessor delay | |
1638 | (3) an unconditional branch delay | |
1639 | (4) a conditional branch delay | |
1640 | (5) a move to coprocessor register delay | |
1641 | (6) a load coprocessor register from memory delay | |
1642 | (7) a coprocessor condition code delay | |
1643 | (8) a HI/LO special register delay | |
1644 | ||
1645 | There are a lot of optimizations we could do that we don't. | |
1646 | In particular, we do not, in general, reorder instructions. | |
1647 | If you use gcc with optimization, it will reorder | |
1648 | instructions and generally do much more optimization then we | |
1649 | do here; repeating all that work in the assembler would only | |
1650 | benefit hand written assembly code, and does not seem worth | |
1651 | it. */ | |
1652 | ||
1653 | /* This is how a NOP is emitted. */ | |
1654 | #define emit_nop() \ | |
1655 | (mips_opts.mips16 \ | |
1656 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1657 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1658 | ||
1659 | /* The previous insn might require a delay slot, depending upon | |
1660 | the contents of the current insn. */ | |
1661 | if (! mips_opts.mips16 | |
81912461 ILT |
1662 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1663 | && ! gpr_interlocks) | |
1664 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1665 | && ! cop_interlocks))) | |
252b5132 RH |
1666 | { |
1667 | /* A load from a coprocessor or from memory. All load | |
1668 | delays delay the use of general register rt for one | |
81912461 | 1669 | instruction. */ |
beae10d5 | 1670 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1671 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1672 | if (mips_optimize == 0 | |
1673 | || insn_uses_reg (ip, | |
1674 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1675 | & OP_MASK_RT), | |
1676 | MIPS_GR_REG)) | |
1677 | ++nops; | |
1678 | } | |
1679 | else if (! mips_opts.mips16 | |
252b5132 | 1680 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1681 | && ! cop_interlocks) |
81912461 ILT |
1682 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1683 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1684 | { |
1685 | /* A generic coprocessor delay. The previous instruction | |
1686 | modified a coprocessor general or control register. If | |
1687 | it modified a control register, we need to avoid any | |
1688 | coprocessor instruction (this is probably not always | |
1689 | required, but it sometimes is). If it modified a general | |
1690 | register, we avoid using that register. | |
1691 | ||
252b5132 RH |
1692 | This case is not handled very well. There is no special |
1693 | knowledge of CP0 handling, and the coprocessors other | |
1694 | than the floating point unit are not distinguished at | |
1695 | all. */ | |
1696 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1697 | Need to modify this to include knowledge about |
252b5132 RH |
1698 | user specified delays! */ |
1699 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1700 | { | |
1701 | if (mips_optimize == 0 | |
1702 | || insn_uses_reg (ip, | |
1703 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1704 | & OP_MASK_FT), | |
1705 | MIPS_FP_REG)) | |
1706 | ++nops; | |
1707 | } | |
1708 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1709 | { | |
1710 | if (mips_optimize == 0 | |
1711 | || insn_uses_reg (ip, | |
1712 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1713 | & OP_MASK_FS), | |
1714 | MIPS_FP_REG)) | |
1715 | ++nops; | |
1716 | } | |
1717 | else | |
1718 | { | |
1719 | /* We don't know exactly what the previous instruction | |
1720 | does. If the current instruction uses a coprocessor | |
1721 | register, we must insert a NOP. If previous | |
1722 | instruction may set the condition codes, and the | |
1723 | current instruction uses them, we must insert two | |
1724 | NOPS. */ | |
bdaaa2e1 | 1725 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1726 | if (mips_optimize == 0 |
1727 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1728 | && (pinfo & INSN_READ_COND_CODE))) | |
1729 | nops += 2; | |
1730 | else if (pinfo & INSN_COP) | |
1731 | ++nops; | |
1732 | } | |
1733 | } | |
1734 | else if (! mips_opts.mips16 | |
252b5132 RH |
1735 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1736 | && ! cop_interlocks) | |
1737 | { | |
1738 | /* The previous instruction sets the coprocessor condition | |
1739 | codes, but does not require a general coprocessor delay | |
1740 | (this means it is a floating point comparison | |
1741 | instruction). If this instruction uses the condition | |
1742 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1743 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1744 | if (mips_optimize == 0 |
1745 | || (pinfo & INSN_READ_COND_CODE)) | |
1746 | ++nops; | |
1747 | } | |
6b76fefe CM |
1748 | |
1749 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1750 | previous insn was an mfhi/mflo and the current insn | |
1751 | reads the register that the mfhi/mflo wrote to, then | |
1752 | insert two nops. */ | |
1753 | ||
1754 | else if (mips_7000_hilo_fix | |
1755 | && MF_HILO_INSN (prev_pinfo) | |
1756 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1757 | & OP_MASK_RD), |
1758 | MIPS_GR_REG)) | |
6b76fefe CM |
1759 | { |
1760 | nops += 2; | |
1761 | } | |
1762 | ||
1763 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1764 | 2nd previous insn was an mfhi/mflo and the current insn | |
1765 | reads the register that the mfhi/mflo wrote to, then | |
1766 | insert one nop. */ | |
1767 | ||
1768 | else if (mips_7000_hilo_fix | |
1769 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1770 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1771 | & OP_MASK_RD), | |
1772 | MIPS_GR_REG)) | |
bdaaa2e1 | 1773 | |
6b76fefe | 1774 | { |
f9419b05 | 1775 | ++nops; |
6b76fefe | 1776 | } |
bdaaa2e1 | 1777 | |
252b5132 RH |
1778 | else if (prev_pinfo & INSN_READ_LO) |
1779 | { | |
1780 | /* The previous instruction reads the LO register; if the | |
1781 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1782 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1783 | Also the tx39's multiply instructions can be executed |
1784 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1785 | though the tx39's divide insns still do require the |
1786 | delay. */ | |
252b5132 | 1787 | if (! (hilo_interlocks |
048cdf86 | 1788 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1789 | && (mips_optimize == 0 |
1790 | || (pinfo & INSN_WRITE_LO))) | |
1791 | nops += 2; | |
1792 | /* Most mips16 branch insns don't have a delay slot. | |
1793 | If a read from LO is immediately followed by a branch | |
1794 | to a write to LO we have a read followed by a write | |
1795 | less than 2 insns away. We assume the target of | |
1796 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1797 | between a read and an immediately following branch. */ |
252b5132 RH |
1798 | else if (mips_opts.mips16 |
1799 | && (mips_optimize == 0 | |
1800 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1801 | ++nops; |
252b5132 RH |
1802 | } |
1803 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1804 | { | |
1805 | /* The previous instruction reads the HI register; if the | |
1806 | current instruction writes to the HI register, we must | |
1807 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1808 | Also the note tx39's multiply above. */ |
252b5132 | 1809 | if (! (hilo_interlocks |
048cdf86 | 1810 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1811 | && (mips_optimize == 0 |
1812 | || (pinfo & INSN_WRITE_HI))) | |
1813 | nops += 2; | |
1814 | /* Most mips16 branch insns don't have a delay slot. | |
1815 | If a read from HI is immediately followed by a branch | |
1816 | to a write to HI we have a read followed by a write | |
1817 | less than 2 insns away. We assume the target of | |
1818 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1819 | between a read and an immediately following branch. */ |
252b5132 RH |
1820 | else if (mips_opts.mips16 |
1821 | && (mips_optimize == 0 | |
1822 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1823 | ++nops; |
252b5132 RH |
1824 | } |
1825 | ||
1826 | /* If the previous instruction was in a noreorder section, then | |
1827 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1828 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1829 | if (prev_insn_unreordered) |
1830 | nops = 0; | |
1831 | ||
1832 | /* There are two cases which require two intervening | |
1833 | instructions: 1) setting the condition codes using a move to | |
1834 | coprocessor instruction which requires a general coprocessor | |
1835 | delay and then reading the condition codes 2) reading the HI | |
1836 | or LO register and then writing to it (except on processors | |
1837 | which have interlocks). If we are not already emitting a NOP | |
1838 | instruction, we must check for these cases compared to the | |
1839 | instruction previous to the previous instruction. */ | |
1840 | if ((! mips_opts.mips16 | |
252b5132 RH |
1841 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1842 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1843 | && (pinfo & INSN_READ_COND_CODE) | |
1844 | && ! cop_interlocks) | |
1845 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1846 | && (pinfo & INSN_WRITE_LO) | |
1847 | && ! (hilo_interlocks | |
048cdf86 | 1848 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1849 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1850 | && (pinfo & INSN_WRITE_HI) | |
1851 | && ! (hilo_interlocks | |
048cdf86 | 1852 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1853 | prev_prev_nop = 1; |
1854 | else | |
1855 | prev_prev_nop = 0; | |
1856 | ||
1857 | if (prev_prev_insn_unreordered) | |
1858 | prev_prev_nop = 0; | |
1859 | ||
1860 | if (prev_prev_nop && nops == 0) | |
1861 | ++nops; | |
1862 | ||
d766e8ec | 1863 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1864 | { |
1865 | /* We're out of bits in pinfo, so we must resort to string | |
1866 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1867 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1868 | int min_nops = 0; |
1869 | const char *pn = prev_insn.insn_mo->name; | |
1870 | const char *tn = ip->insn_mo->name; | |
532c738a RS |
1871 | if (strncmp (pn, "macc", 4) == 0 |
1872 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1873 | { |
1874 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1875 | if (strstr (tn, "div")) | |
532c738a | 1876 | min_nops = 1; |
60b63b72 | 1877 | |
532c738a RS |
1878 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1879 | instruction is executed immediately after a MACC or | |
1880 | DMACC instruction, the result of [either instruction] | |
1881 | is incorrect." */ | |
1882 | if (strncmp (tn, "mult", 4) == 0 | |
1883 | || strncmp (tn, "dmult", 5) == 0) | |
1884 | min_nops = 1; | |
1885 | ||
1886 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1887 | Applies on top of VR4181A MD(1) errata. */ | |
1888 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1889 | min_nops = 1; | |
60b63b72 RS |
1890 | |
1891 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1892 | if (strcmp (tn, "mtlo") == 0 | |
1893 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1894 | min_nops = 1; |
60b63b72 | 1895 | } |
532c738a RS |
1896 | else if (strncmp (pn, "dmult", 5) == 0 |
1897 | && (strncmp (tn, "dmult", 5) == 0 | |
1898 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1899 | { |
1900 | /* Here is the rest of errata 23. */ | |
1901 | min_nops = 1; | |
1902 | } | |
532c738a RS |
1903 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1904 | && (strncmp (tn, "macc", 4) == 0 | |
1905 | || strncmp (tn, "dmacc", 5) == 0)) | |
1906 | { | |
1907 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1908 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1909 | DDIV or DDIVU instruction, the result of the MACC or | |
1910 | DMACC instruction is incorrect.". This partly overlaps | |
1911 | the workaround for errata 23. */ | |
1912 | min_nops = 1; | |
1913 | } | |
60b63b72 RS |
1914 | if (nops < min_nops) |
1915 | nops = min_nops; | |
1916 | } | |
1917 | ||
252b5132 RH |
1918 | /* If we are being given a nop instruction, don't bother with |
1919 | one of the nops we would otherwise output. This will only | |
1920 | happen when a nop instruction is used with mips_optimize set | |
1921 | to 0. */ | |
1922 | if (nops > 0 | |
1923 | && ! mips_opts.noreorder | |
156c2f8b | 1924 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1925 | --nops; |
1926 | ||
1927 | /* Now emit the right number of NOP instructions. */ | |
1928 | if (nops > 0 && ! mips_opts.noreorder) | |
1929 | { | |
1930 | fragS *old_frag; | |
1931 | unsigned long old_frag_offset; | |
1932 | int i; | |
1933 | struct insn_label_list *l; | |
1934 | ||
1935 | old_frag = frag_now; | |
1936 | old_frag_offset = frag_now_fix (); | |
1937 | ||
1938 | for (i = 0; i < nops; i++) | |
1939 | emit_nop (); | |
1940 | ||
1941 | if (listing) | |
1942 | { | |
1943 | listing_prev_line (); | |
1944 | /* We may be at the start of a variant frag. In case we | |
1945 | are, make sure there is enough space for the frag | |
1946 | after the frags created by listing_prev_line. The | |
1947 | argument to frag_grow here must be at least as large | |
1948 | as the argument to all other calls to frag_grow in | |
1949 | this file. We don't have to worry about being in the | |
1950 | middle of a variant frag, because the variants insert | |
1951 | all needed nop instructions themselves. */ | |
1952 | frag_grow (40); | |
1953 | } | |
1954 | ||
1955 | for (l = insn_labels; l != NULL; l = l->next) | |
1956 | { | |
98aa84af AM |
1957 | valueT val; |
1958 | ||
252b5132 | 1959 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1960 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1961 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1962 | /* mips16 text labels are stored as odd. */ |
1963 | if (mips_opts.mips16) | |
f9419b05 | 1964 | ++val; |
98aa84af | 1965 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1966 | } |
1967 | ||
1968 | #ifndef NO_ECOFF_DEBUGGING | |
1969 | if (ECOFF_DEBUGGING) | |
1970 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1971 | #endif | |
1972 | } | |
1973 | else if (prev_nop_frag != NULL) | |
1974 | { | |
1975 | /* We have a frag holding nops we may be able to remove. If | |
1976 | we don't need any nops, we can decrease the size of | |
1977 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1978 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1979 | if (prev_nop_frag_since == 0) |
1980 | { | |
1981 | if (nops == 0) | |
1982 | { | |
1983 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1984 | --prev_nop_frag_holds; | |
1985 | } | |
1986 | else | |
1987 | prev_nop_frag_required += nops; | |
1988 | } | |
1989 | else | |
1990 | { | |
1991 | if (prev_prev_nop == 0) | |
1992 | { | |
1993 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1994 | --prev_nop_frag_holds; | |
1995 | } | |
1996 | else | |
1997 | ++prev_nop_frag_required; | |
1998 | } | |
1999 | ||
2000 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2001 | prev_nop_frag = NULL; | |
2002 | ||
2003 | ++prev_nop_frag_since; | |
2004 | ||
2005 | /* Sanity check: by the time we reach the second instruction | |
2006 | after prev_nop_frag, we should have used up all the nops | |
2007 | one way or another. */ | |
2008 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2009 | } | |
2010 | } | |
2011 | ||
895921c9 MR |
2012 | /* Record the frag type before frag_var. */ |
2013 | if (prev_insn_frag) | |
2014 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2015 | ||
4d7206a2 | 2016 | if (address_expr |
0b25d3e6 | 2017 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2018 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2019 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2020 | && mips_relax_branch | |
2021 | /* Don't try branch relaxation within .set nomacro, or within | |
2022 | .set noat if we use $at for PIC computations. If it turns | |
2023 | out that the branch was out-of-range, we'll get an error. */ | |
2024 | && !mips_opts.warn_about_macros | |
2025 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2026 | && !mips_opts.mips16) | |
2027 | { | |
895921c9 | 2028 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2029 | f = frag_var (rs_machine_dependent, |
2030 | relaxed_branch_length | |
2031 | (NULL, NULL, | |
2032 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2033 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2034 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2035 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2036 | pinfo & INSN_COND_BRANCH_LIKELY, |
2037 | pinfo & INSN_WRITE_GPR_31, | |
2038 | 0), | |
2039 | address_expr->X_add_symbol, | |
2040 | address_expr->X_add_number, | |
2041 | 0); | |
2042 | *reloc_type = BFD_RELOC_UNUSED; | |
2043 | } | |
2044 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2045 | { |
2046 | /* We need to set up a variant frag. */ | |
2047 | assert (mips_opts.mips16 && address_expr != NULL); | |
2048 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2049 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2050 | mips16_small, mips16_ext, |
2051 | (prev_pinfo | |
2052 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2053 | (*prev_insn_reloc_type |
252b5132 | 2054 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2055 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2056 | } |
252b5132 RH |
2057 | else if (mips_opts.mips16 |
2058 | && ! ip->use_extend | |
f6688943 | 2059 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2060 | { |
2061 | /* Make sure there is enough room to swap this instruction with | |
2062 | a following jump instruction. */ | |
2063 | frag_grow (6); | |
2064 | f = frag_more (2); | |
2065 | } | |
2066 | else | |
2067 | { | |
2068 | if (mips_opts.mips16 | |
2069 | && mips_opts.noreorder | |
2070 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2071 | as_warn (_("extended instruction in delay slot")); | |
2072 | ||
4d7206a2 RS |
2073 | if (mips_relax.sequence) |
2074 | { | |
2075 | /* If we've reached the end of this frag, turn it into a variant | |
2076 | frag and record the information for the instructions we've | |
2077 | written so far. */ | |
2078 | if (frag_room () < 4) | |
2079 | relax_close_frag (); | |
2080 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2081 | } | |
2082 | ||
584892a6 RS |
2083 | if (mips_relax.sequence != 2) |
2084 | mips_macro_warning.sizes[0] += 4; | |
2085 | if (mips_relax.sequence != 1) | |
2086 | mips_macro_warning.sizes[1] += 4; | |
2087 | ||
252b5132 RH |
2088 | f = frag_more (4); |
2089 | } | |
2090 | ||
f6688943 | 2091 | fixp[0] = fixp[1] = fixp[2] = NULL; |
01a3f561 | 2092 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2093 | { |
2094 | if (address_expr->X_op == O_constant) | |
2095 | { | |
f17c130b | 2096 | unsigned int tmp; |
f6688943 TS |
2097 | |
2098 | switch (*reloc_type) | |
252b5132 RH |
2099 | { |
2100 | case BFD_RELOC_32: | |
2101 | ip->insn_opcode |= address_expr->X_add_number; | |
2102 | break; | |
2103 | ||
f6688943 | 2104 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2105 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2106 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2107 | break; |
2108 | ||
2109 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2110 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2111 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2112 | break; |
2113 | ||
2114 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2115 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2116 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2117 | break; |
2118 | ||
2119 | case BFD_RELOC_HI16: | |
2120 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2121 | break; | |
2122 | ||
01a3f561 | 2123 | case BFD_RELOC_UNUSED: |
252b5132 | 2124 | case BFD_RELOC_LO16: |
ed6fb7bd | 2125 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2126 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2127 | break; | |
2128 | ||
2129 | case BFD_RELOC_MIPS_JMP: | |
2130 | if ((address_expr->X_add_number & 3) != 0) | |
2131 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2132 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2133 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2134 | as_bad (_("jump address range overflow (0x%lx)"), |
2135 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2136 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2137 | break; | |
2138 | ||
2139 | case BFD_RELOC_MIPS16_JMP: | |
2140 | if ((address_expr->X_add_number & 3) != 0) | |
2141 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2142 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2143 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2144 | as_bad (_("jump address range overflow (0x%lx)"), |
2145 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2146 | ip->insn_opcode |= |
2147 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2148 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2149 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2150 | break; | |
2151 | ||
252b5132 RH |
2152 | case BFD_RELOC_16_PCREL_S2: |
2153 | goto need_reloc; | |
2154 | ||
2155 | default: | |
2156 | internalError (); | |
2157 | } | |
2158 | } | |
01a3f561 | 2159 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2160 | need_reloc: |
4d7206a2 RS |
2161 | { |
2162 | reloc_howto_type *howto; | |
2163 | int i; | |
34ce925e | 2164 | |
4d7206a2 RS |
2165 | /* In a compound relocation, it is the final (outermost) |
2166 | operator that determines the relocated field. */ | |
2167 | for (i = 1; i < 3; i++) | |
2168 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2169 | break; | |
34ce925e | 2170 | |
4d7206a2 RS |
2171 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2172 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2173 | bfd_get_reloc_size(howto), | |
2174 | address_expr, | |
2175 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2176 | reloc_type[0]); | |
2177 | ||
2178 | /* These relocations can have an addend that won't fit in | |
2179 | 4 octets for 64bit assembly. */ | |
2180 | if (HAVE_64BIT_GPRS | |
2181 | && ! howto->partial_inplace | |
2182 | && (reloc_type[0] == BFD_RELOC_16 | |
2183 | || reloc_type[0] == BFD_RELOC_32 | |
2184 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2185 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2186 | || reloc_type[0] == BFD_RELOC_LO16 | |
2187 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2188 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2189 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2190 | || reloc_type[0] == BFD_RELOC_64 | |
2191 | || reloc_type[0] == BFD_RELOC_CTOR | |
2192 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2193 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2194 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2195 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2196 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2197 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2198 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2199 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2200 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
4d7206a2 RS |
2201 | fixp[0]->fx_no_overflow = 1; |
2202 | ||
2203 | if (mips_relax.sequence) | |
2204 | { | |
2205 | if (mips_relax.first_fixup == 0) | |
2206 | mips_relax.first_fixup = fixp[0]; | |
2207 | } | |
2208 | else if (reloc_needs_lo_p (*reloc_type)) | |
2209 | { | |
2210 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2211 | |
4d7206a2 RS |
2212 | /* Reuse the last entry if it already has a matching %lo. */ |
2213 | hi_fixup = mips_hi_fixup_list; | |
2214 | if (hi_fixup == 0 | |
2215 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2216 | { | |
2217 | hi_fixup = ((struct mips_hi_fixup *) | |
2218 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2219 | hi_fixup->next = mips_hi_fixup_list; | |
2220 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2221 | } |
4d7206a2 RS |
2222 | hi_fixup->fixp = fixp[0]; |
2223 | hi_fixup->seg = now_seg; | |
2224 | } | |
f6688943 | 2225 | |
4d7206a2 RS |
2226 | /* Add fixups for the second and third relocations, if given. |
2227 | Note that the ABI allows the second relocation to be | |
2228 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2229 | moment we only use RSS_UNDEF, but we could add support | |
2230 | for the others if it ever becomes necessary. */ | |
2231 | for (i = 1; i < 3; i++) | |
2232 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2233 | { | |
6e1304d8 RS |
2234 | fixp[i] = fix_new (frag_now, fixp[0]->fx_where, |
2235 | fixp[0]->fx_size, NULL, 0, | |
2236 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2237 | |
2238 | /* Use fx_tcbit to mark compound relocs. */ | |
2239 | fixp[0]->fx_tcbit = 1; | |
2240 | fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2241 | } |
252b5132 RH |
2242 | } |
2243 | } | |
2244 | ||
2245 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2246 | { |
2247 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2248 | #ifdef OBJ_ELF | |
2249 | dwarf2_emit_insn (4); | |
2250 | #endif | |
2251 | } | |
f6688943 | 2252 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2253 | { |
2254 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2255 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab | 2256 | #ifdef OBJ_ELF |
20e56c33 RS |
2257 | /* The value passed to dwarf2_emit_insn is the distance between |
2258 | the end of the current instruction and the address that should | |
2259 | be recorded in the debug tables. Since we want to use ISA-encoded | |
2260 | addresses in MIPS16 debug info, the value is one byte less than | |
2261 | the real instruction length. */ | |
2262 | dwarf2_emit_insn (3); | |
c5dd6aab | 2263 | #endif |
252b5132 RH |
2264 | } |
2265 | else | |
2266 | { | |
2267 | if (ip->use_extend) | |
2268 | { | |
2269 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2270 | f += 2; | |
2271 | } | |
2272 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab | 2273 | #ifdef OBJ_ELF |
20e56c33 | 2274 | dwarf2_emit_insn (ip->use_extend ? 3 : 1); |
c5dd6aab | 2275 | #endif |
252b5132 RH |
2276 | } |
2277 | ||
2278 | /* Update the register mask information. */ | |
2279 | if (! mips_opts.mips16) | |
2280 | { | |
2281 | if (pinfo & INSN_WRITE_GPR_D) | |
2282 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2283 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2284 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2285 | if (pinfo & INSN_READ_GPR_S) | |
2286 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2287 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2288 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2289 | if (pinfo & INSN_WRITE_FPR_D) |
2290 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2291 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2292 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2293 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2294 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2295 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2296 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2297 | if (pinfo & INSN_COP) | |
2298 | { | |
bdaaa2e1 KH |
2299 | /* We don't keep enough information to sort these cases out. |
2300 | The itbl support does keep this information however, although | |
2301 | we currently don't support itbl fprmats as part of the cop | |
2302 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2303 | } |
2304 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2305 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2306 | } |
2307 | else | |
2308 | { | |
2309 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2310 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2311 | & MIPS16OP_MASK_RX); | |
2312 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2313 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2314 | & MIPS16OP_MASK_RY); | |
2315 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2316 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2317 | & MIPS16OP_MASK_RZ); | |
2318 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2319 | mips_gprmask |= 1 << TREG; | |
2320 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2321 | mips_gprmask |= 1 << SP; | |
2322 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2323 | mips_gprmask |= 1 << RA; | |
2324 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2325 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2326 | if (pinfo & MIPS16_INSN_READ_Z) | |
2327 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2328 | & MIPS16OP_MASK_MOVE32Z); | |
2329 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2330 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2331 | & MIPS16OP_MASK_REGR32); | |
2332 | } | |
2333 | ||
4d7206a2 | 2334 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2335 | { |
2336 | /* Filling the branch delay slot is more complex. We try to | |
2337 | switch the branch with the previous instruction, which we can | |
2338 | do if the previous instruction does not set up a condition | |
2339 | that the branch tests and if the branch is not itself the | |
2340 | target of any branch. */ | |
2341 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2342 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2343 | { | |
2344 | if (mips_optimize < 2 | |
2345 | /* If we have seen .set volatile or .set nomove, don't | |
2346 | optimize. */ | |
2347 | || mips_opts.nomove != 0 | |
2348 | /* If we had to emit any NOP instructions, then we | |
2349 | already know we can not swap. */ | |
2350 | || nops != 0 | |
2351 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2352 | swap. */ |
252b5132 RH |
2353 | || ! prev_insn_valid |
2354 | /* If the previous insn is already in a branch delay | |
2355 | slot, then we can not swap. */ | |
2356 | || prev_insn_is_delay_slot | |
2357 | /* If the previous previous insn was in a .set | |
2358 | noreorder, we can't swap. Actually, the MIPS | |
2359 | assembler will swap in this situation. However, gcc | |
2360 | configured -with-gnu-as will generate code like | |
2361 | .set noreorder | |
2362 | lw $4,XXX | |
2363 | .set reorder | |
2364 | INSN | |
2365 | bne $4,$0,foo | |
2366 | in which we can not swap the bne and INSN. If gcc is | |
2367 | not configured -with-gnu-as, it does not output the | |
2368 | .set pseudo-ops. We don't have to check | |
2369 | prev_insn_unreordered, because prev_insn_valid will | |
2370 | be 0 in that case. We don't want to use | |
2371 | prev_prev_insn_valid, because we do want to be able | |
2372 | to swap at the start of a function. */ | |
2373 | || prev_prev_insn_unreordered | |
2374 | /* If the branch is itself the target of a branch, we | |
2375 | can not swap. We cheat on this; all we check for is | |
2376 | whether there is a label on this instruction. If | |
2377 | there are any branches to anything other than a | |
2378 | label, users must use .set noreorder. */ | |
2379 | || insn_labels != NULL | |
895921c9 MR |
2380 | /* If the previous instruction is in a variant frag |
2381 | other than this branch's one, we cannot do the swap. | |
2382 | This does not apply to the mips16, which uses variant | |
2383 | frags for different purposes. */ | |
252b5132 | 2384 | || (! mips_opts.mips16 |
895921c9 | 2385 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2386 | /* If the branch reads the condition codes, we don't |
2387 | even try to swap, because in the sequence | |
2388 | ctc1 $X,$31 | |
2389 | INSN | |
2390 | INSN | |
2391 | bc1t LABEL | |
2392 | we can not swap, and I don't feel like handling that | |
2393 | case. */ | |
2394 | || (! mips_opts.mips16 | |
81912461 ILT |
2395 | && (pinfo & INSN_READ_COND_CODE) |
2396 | && ! cop_interlocks) | |
252b5132 | 2397 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2398 | delay slot, because the target of the branch might |
252b5132 RH |
2399 | interfere with that instruction. */ |
2400 | || (! mips_opts.mips16 | |
252b5132 | 2401 | && (prev_pinfo |
bdaaa2e1 | 2402 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2403 | & (INSN_LOAD_COPROC_DELAY |
2404 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2405 | | INSN_WRITE_COND_CODE)) |
2406 | && ! cop_interlocks) | |
252b5132 | 2407 | || (! (hilo_interlocks |
048cdf86 | 2408 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2409 | && (prev_pinfo |
2410 | & (INSN_READ_LO | |
2411 | | INSN_READ_HI))) | |
2412 | || (! mips_opts.mips16 | |
81912461 ILT |
2413 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2414 | && ! gpr_interlocks) | |
252b5132 | 2415 | || (! mips_opts.mips16 |
bdaaa2e1 | 2416 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2417 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2418 | && ! cop_mem_interlocks) | |
252b5132 RH |
2419 | /* We can not swap with a branch instruction. */ |
2420 | || (prev_pinfo | |
2421 | & (INSN_UNCOND_BRANCH_DELAY | |
2422 | | INSN_COND_BRANCH_DELAY | |
2423 | | INSN_COND_BRANCH_LIKELY)) | |
2424 | /* We do not swap with a trap instruction, since it | |
2425 | complicates trap handlers to have the trap | |
2426 | instruction be in a delay slot. */ | |
2427 | || (prev_pinfo & INSN_TRAP) | |
2428 | /* If the branch reads a register that the previous | |
2429 | instruction sets, we can not swap. */ | |
2430 | || (! mips_opts.mips16 | |
2431 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2432 | && insn_uses_reg (ip, | |
2433 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2434 | & OP_MASK_RT), | |
2435 | MIPS_GR_REG)) | |
2436 | || (! mips_opts.mips16 | |
2437 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2438 | && insn_uses_reg (ip, | |
2439 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2440 | & OP_MASK_RD), | |
2441 | MIPS_GR_REG)) | |
2442 | || (mips_opts.mips16 | |
2443 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2444 | && insn_uses_reg (ip, | |
2445 | ((prev_insn.insn_opcode | |
2446 | >> MIPS16OP_SH_RX) | |
2447 | & MIPS16OP_MASK_RX), | |
2448 | MIPS16_REG)) | |
2449 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2450 | && insn_uses_reg (ip, | |
2451 | ((prev_insn.insn_opcode | |
2452 | >> MIPS16OP_SH_RY) | |
2453 | & MIPS16OP_MASK_RY), | |
2454 | MIPS16_REG)) | |
2455 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2456 | && insn_uses_reg (ip, | |
2457 | ((prev_insn.insn_opcode | |
2458 | >> MIPS16OP_SH_RZ) | |
2459 | & MIPS16OP_MASK_RZ), | |
2460 | MIPS16_REG)) | |
2461 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2462 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2463 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2464 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2465 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2466 | && insn_uses_reg (ip, | |
2467 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2468 | insn_opcode), | |
2469 | MIPS_GR_REG)))) | |
2470 | /* If the branch writes a register that the previous | |
2471 | instruction sets, we can not swap (we know that | |
2472 | branches write only to RD or to $31). */ | |
2473 | || (! mips_opts.mips16 | |
2474 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2475 | && (((pinfo & INSN_WRITE_GPR_D) | |
2476 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2477 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2478 | || ((pinfo & INSN_WRITE_GPR_31) | |
2479 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2480 | & OP_MASK_RT) | |
f9419b05 | 2481 | == RA)))) |
252b5132 RH |
2482 | || (! mips_opts.mips16 |
2483 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2484 | && (((pinfo & INSN_WRITE_GPR_D) | |
2485 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2486 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2487 | || ((pinfo & INSN_WRITE_GPR_31) | |
2488 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2489 | & OP_MASK_RD) | |
f9419b05 | 2490 | == RA)))) |
252b5132 RH |
2491 | || (mips_opts.mips16 |
2492 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2493 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2494 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2495 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2496 | == RA)))) | |
2497 | /* If the branch writes a register that the previous | |
2498 | instruction reads, we can not swap (we know that | |
2499 | branches only write to RD or to $31). */ | |
2500 | || (! mips_opts.mips16 | |
2501 | && (pinfo & INSN_WRITE_GPR_D) | |
2502 | && insn_uses_reg (&prev_insn, | |
2503 | ((ip->insn_opcode >> OP_SH_RD) | |
2504 | & OP_MASK_RD), | |
2505 | MIPS_GR_REG)) | |
2506 | || (! mips_opts.mips16 | |
2507 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2508 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2509 | || (mips_opts.mips16 |
2510 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2511 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
252b5132 RH |
2512 | /* If the previous previous instruction has a load |
2513 | delay, and sets a register that the branch reads, we | |
2514 | can not swap. */ | |
2515 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2516 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2517 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2518 | && ! cop_interlocks) | |
2519 | || ((prev_prev_insn.insn_mo->pinfo | |
2520 | & INSN_LOAD_MEMORY_DELAY) | |
2521 | && ! gpr_interlocks)) | |
252b5132 RH |
2522 | && insn_uses_reg (ip, |
2523 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2524 | & OP_MASK_RT), | |
2525 | MIPS_GR_REG)) | |
2526 | /* If one instruction sets a condition code and the | |
2527 | other one uses a condition code, we can not swap. */ | |
2528 | || ((pinfo & INSN_READ_COND_CODE) | |
2529 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2530 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2531 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2532 | /* If the previous instruction uses the PC, we can not | |
2533 | swap. */ | |
2534 | || (mips_opts.mips16 | |
2535 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2536 | /* If the previous instruction was extended, we can not | |
2537 | swap. */ | |
2538 | || (mips_opts.mips16 && prev_insn_extended) | |
2539 | /* If the previous instruction had a fixup in mips16 | |
2540 | mode, we can not swap. This normally means that the | |
2541 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2542 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2543 | /* If the previous instruction is a sync, sync.l, or |
2544 | sync.p, we can not swap. */ | |
f173e82e | 2545 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2546 | { |
2547 | /* We could do even better for unconditional branches to | |
2548 | portions of this object file; we could pick up the | |
2549 | instruction at the destination, put it in the delay | |
2550 | slot, and bump the destination address. */ | |
2551 | emit_nop (); | |
dd22970f ILT |
2552 | if (mips_relax.sequence) |
2553 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2554 | /* Update the previous insn information. */ |
2555 | prev_prev_insn = *ip; | |
2556 | prev_insn.insn_mo = &dummy_opcode; | |
2557 | } | |
2558 | else | |
2559 | { | |
2560 | /* It looks like we can actually do the swap. */ | |
2561 | if (! mips_opts.mips16) | |
2562 | { | |
2563 | char *prev_f; | |
2564 | char temp[4]; | |
2565 | ||
2566 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2567 | if (!relaxed_branch) |
2568 | { | |
2569 | /* If this is not a relaxed branch, then just | |
2570 | swap the instructions. */ | |
2571 | memcpy (temp, prev_f, 4); | |
2572 | memcpy (prev_f, f, 4); | |
2573 | memcpy (f, temp, 4); | |
2574 | } | |
2575 | else | |
2576 | { | |
2577 | /* If this is a relaxed branch, then we move the | |
2578 | instruction to be placed in the delay slot to | |
2579 | the current frag, shrinking the fixed part of | |
2580 | the originating frag. If the branch occupies | |
2581 | the tail of the latter, we move it backwards, | |
2582 | into the space freed by the moved instruction. */ | |
2583 | f = frag_more (4); | |
2584 | memcpy (f, prev_f, 4); | |
2585 | prev_insn_frag->fr_fix -= 4; | |
2586 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2587 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2588 | } | |
2589 | ||
f6688943 TS |
2590 | if (prev_insn_fixp[0]) |
2591 | { | |
2592 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2593 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2594 | } | |
2595 | if (prev_insn_fixp[1]) | |
2596 | { | |
2597 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2598 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2599 | } | |
2600 | if (prev_insn_fixp[2]) | |
252b5132 | 2601 | { |
f6688943 TS |
2602 | prev_insn_fixp[2]->fx_frag = frag_now; |
2603 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2604 | } |
f5040a92 AO |
2605 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2606 | && prev_insn_frag != frag_now | |
2607 | && (prev_insn_fixp[0]->fx_r_type | |
2608 | == BFD_RELOC_MIPS_GOT_DISP | |
2609 | || (prev_insn_fixp[0]->fx_r_type | |
2610 | == BFD_RELOC_MIPS_CALL16))) | |
2611 | { | |
2612 | /* To avoid confusion in tc_gen_reloc, we must | |
2613 | ensure that this does not become a variant | |
2614 | frag. */ | |
2615 | force_new_frag = TRUE; | |
2616 | } | |
895921c9 MR |
2617 | |
2618 | if (!relaxed_branch) | |
f6688943 | 2619 | { |
895921c9 MR |
2620 | if (fixp[0]) |
2621 | { | |
2622 | fixp[0]->fx_frag = prev_insn_frag; | |
2623 | fixp[0]->fx_where = prev_insn_where; | |
2624 | } | |
2625 | if (fixp[1]) | |
2626 | { | |
2627 | fixp[1]->fx_frag = prev_insn_frag; | |
2628 | fixp[1]->fx_where = prev_insn_where; | |
2629 | } | |
2630 | if (fixp[2]) | |
2631 | { | |
2632 | fixp[2]->fx_frag = prev_insn_frag; | |
2633 | fixp[2]->fx_where = prev_insn_where; | |
2634 | } | |
f6688943 | 2635 | } |
895921c9 | 2636 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2637 | { |
895921c9 MR |
2638 | if (fixp[0]) |
2639 | fixp[0]->fx_where -= 4; | |
2640 | if (fixp[1]) | |
2641 | fixp[1]->fx_where -= 4; | |
2642 | if (fixp[2]) | |
2643 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2644 | } |
2645 | } | |
2646 | else | |
2647 | { | |
2648 | char *prev_f; | |
2649 | char temp[2]; | |
2650 | ||
f6688943 TS |
2651 | assert (prev_insn_fixp[0] == NULL); |
2652 | assert (prev_insn_fixp[1] == NULL); | |
2653 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2654 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2655 | memcpy (temp, prev_f, 2); | |
2656 | memcpy (prev_f, f, 2); | |
f6688943 | 2657 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2658 | { |
f6688943 | 2659 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2660 | memcpy (f, temp, 2); |
2661 | } | |
2662 | else | |
2663 | { | |
2664 | memcpy (f, f + 2, 2); | |
2665 | memcpy (f + 2, temp, 2); | |
2666 | } | |
f6688943 TS |
2667 | if (fixp[0]) |
2668 | { | |
2669 | fixp[0]->fx_frag = prev_insn_frag; | |
2670 | fixp[0]->fx_where = prev_insn_where; | |
2671 | } | |
2672 | if (fixp[1]) | |
2673 | { | |
2674 | fixp[1]->fx_frag = prev_insn_frag; | |
2675 | fixp[1]->fx_where = prev_insn_where; | |
2676 | } | |
2677 | if (fixp[2]) | |
252b5132 | 2678 | { |
f6688943 TS |
2679 | fixp[2]->fx_frag = prev_insn_frag; |
2680 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2681 | } |
2682 | } | |
2683 | ||
2684 | /* Update the previous insn information; leave prev_insn | |
2685 | unchanged. */ | |
2686 | prev_prev_insn = *ip; | |
2687 | } | |
2688 | prev_insn_is_delay_slot = 1; | |
2689 | ||
2690 | /* If that was an unconditional branch, forget the previous | |
2691 | insn information. */ | |
2692 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2693 | { | |
2694 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2695 | prev_insn.insn_mo = &dummy_opcode; | |
2696 | } | |
2697 | ||
f6688943 TS |
2698 | prev_insn_fixp[0] = NULL; |
2699 | prev_insn_fixp[1] = NULL; | |
2700 | prev_insn_fixp[2] = NULL; | |
2701 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2702 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2703 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2704 | prev_insn_extended = 0; |
2705 | } | |
2706 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2707 | { | |
2708 | /* We don't yet optimize a branch likely. What we should do | |
2709 | is look at the target, copy the instruction found there | |
2710 | into the delay slot, and increment the branch to jump to | |
2711 | the next instruction. */ | |
2712 | emit_nop (); | |
2713 | /* Update the previous insn information. */ | |
2714 | prev_prev_insn = *ip; | |
2715 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2716 | prev_insn_fixp[0] = NULL; |
2717 | prev_insn_fixp[1] = NULL; | |
2718 | prev_insn_fixp[2] = NULL; | |
2719 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2720 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2721 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2722 | prev_insn_extended = 0; |
f7870c8d | 2723 | prev_insn_is_delay_slot = 1; |
252b5132 RH |
2724 | } |
2725 | else | |
2726 | { | |
2727 | /* Update the previous insn information. */ | |
2728 | if (nops > 0) | |
2729 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2730 | else | |
2731 | prev_prev_insn = prev_insn; | |
2732 | prev_insn = *ip; | |
2733 | ||
2734 | /* Any time we see a branch, we always fill the delay slot | |
2735 | immediately; since this insn is not a branch, we know it | |
2736 | is not in a delay slot. */ | |
2737 | prev_insn_is_delay_slot = 0; | |
2738 | ||
f6688943 TS |
2739 | prev_insn_fixp[0] = fixp[0]; |
2740 | prev_insn_fixp[1] = fixp[1]; | |
2741 | prev_insn_fixp[2] = fixp[2]; | |
2742 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2743 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2744 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2745 | if (mips_opts.mips16) |
2746 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2747 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2748 | } |
2749 | ||
2750 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2751 | prev_insn_unreordered = 0; | |
2752 | prev_insn_frag = frag_now; | |
2753 | prev_insn_where = f - frag_now->fr_literal; | |
2754 | prev_insn_valid = 1; | |
2755 | } | |
4d7206a2 | 2756 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2757 | { |
2758 | /* We need to record a bit of information even when we are not | |
2759 | reordering, in order to determine the base address for mips16 | |
2760 | PC relative relocs. */ | |
2761 | prev_prev_insn = prev_insn; | |
2762 | prev_insn = *ip; | |
f6688943 TS |
2763 | prev_insn_reloc_type[0] = reloc_type[0]; |
2764 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2765 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2766 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2767 | prev_insn_unreordered = 1; | |
2768 | } | |
2769 | ||
2770 | /* We just output an insn, so the next one doesn't have a label. */ | |
2771 | mips_clear_insn_labels (); | |
252b5132 RH |
2772 | } |
2773 | ||
2774 | /* This function forgets that there was any previous instruction or | |
2775 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2776 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2777 | |
2778 | static void | |
17a2f251 | 2779 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2780 | { |
2781 | if (! preserve) | |
2782 | { | |
2783 | prev_insn.insn_mo = &dummy_opcode; | |
2784 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2785 | prev_nop_frag = NULL; | |
2786 | prev_nop_frag_holds = 0; | |
2787 | prev_nop_frag_required = 0; | |
2788 | prev_nop_frag_since = 0; | |
2789 | } | |
2790 | prev_insn_valid = 0; | |
2791 | prev_insn_is_delay_slot = 0; | |
2792 | prev_insn_unreordered = 0; | |
2793 | prev_insn_extended = 0; | |
f6688943 TS |
2794 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2795 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2796 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2797 | prev_prev_insn_unreordered = 0; |
2798 | mips_clear_insn_labels (); | |
2799 | } | |
2800 | ||
2801 | /* This function must be called whenever we turn on noreorder or emit | |
2802 | something other than instructions. It inserts any NOPS which might | |
2803 | be needed by the previous instruction, and clears the information | |
2804 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2805 | instructions are to follow. */ |
252b5132 RH |
2806 | |
2807 | static void | |
17a2f251 | 2808 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2809 | { |
2810 | if (! mips_opts.noreorder) | |
2811 | { | |
2812 | int nops; | |
2813 | ||
2814 | nops = 0; | |
2815 | if ((! mips_opts.mips16 | |
81912461 ILT |
2816 | && ((prev_insn.insn_mo->pinfo |
2817 | & (INSN_LOAD_COPROC_DELAY | |
2818 | | INSN_COPROC_MOVE_DELAY | |
2819 | | INSN_WRITE_COND_CODE)) | |
2820 | && ! cop_interlocks)) | |
252b5132 RH |
2821 | || (! hilo_interlocks |
2822 | && (prev_insn.insn_mo->pinfo | |
2823 | & (INSN_READ_LO | |
2824 | | INSN_READ_HI))) | |
2825 | || (! mips_opts.mips16 | |
81912461 ILT |
2826 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2827 | && ! gpr_interlocks) | |
252b5132 | 2828 | || (! mips_opts.mips16 |
81912461 ILT |
2829 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2830 | && ! cop_mem_interlocks)) | |
252b5132 | 2831 | { |
beae10d5 | 2832 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2833 | ++nops; |
2834 | if ((! mips_opts.mips16 | |
81912461 ILT |
2835 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2836 | && ! cop_interlocks)) | |
252b5132 RH |
2837 | || (! hilo_interlocks |
2838 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2839 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2840 | ++nops; | |
2841 | ||
2842 | if (prev_insn_unreordered) | |
2843 | nops = 0; | |
2844 | } | |
2845 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2846 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2847 | && ! cop_interlocks)) | |
252b5132 RH |
2848 | || (! hilo_interlocks |
2849 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2850 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2851 | { | |
beae10d5 | 2852 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2853 | if (! prev_prev_insn_unreordered) |
2854 | ++nops; | |
2855 | } | |
2856 | ||
d766e8ec | 2857 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2858 | { |
2859 | int min_nops = 0; | |
2860 | const char *pn = prev_insn.insn_mo->name; | |
532c738a RS |
2861 | if (strncmp (pn, "macc", 4) == 0 |
2862 | || strncmp (pn, "dmacc", 5) == 0 | |
2863 | || strncmp (pn, "dmult", 5) == 0 | |
2864 | || strstr (pn, "div")) | |
2865 | min_nops = 1; | |
60b63b72 RS |
2866 | if (nops < min_nops) |
2867 | nops = min_nops; | |
2868 | } | |
2869 | ||
252b5132 RH |
2870 | if (nops > 0) |
2871 | { | |
2872 | struct insn_label_list *l; | |
2873 | ||
2874 | if (insns) | |
2875 | { | |
2876 | /* Record the frag which holds the nop instructions, so | |
2877 | that we can remove them if we don't need them. */ | |
2878 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2879 | prev_nop_frag = frag_now; | |
2880 | prev_nop_frag_holds = nops; | |
2881 | prev_nop_frag_required = 0; | |
2882 | prev_nop_frag_since = 0; | |
2883 | } | |
2884 | ||
2885 | for (; nops > 0; --nops) | |
2886 | emit_nop (); | |
2887 | ||
2888 | if (insns) | |
2889 | { | |
2890 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2891 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2892 | frag_wane (frag_now); |
2893 | frag_new (0); | |
2894 | } | |
2895 | ||
2896 | for (l = insn_labels; l != NULL; l = l->next) | |
2897 | { | |
98aa84af AM |
2898 | valueT val; |
2899 | ||
252b5132 | 2900 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2901 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2902 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2903 | /* mips16 text labels are stored as odd. */ |
2904 | if (mips_opts.mips16) | |
f9419b05 | 2905 | ++val; |
98aa84af | 2906 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2907 | } |
2908 | } | |
2909 | } | |
2910 | ||
2911 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2912 | if (insns) |
252b5132 RH |
2913 | mips16_mark_labels (); |
2914 | ||
2915 | mips_no_prev_insn (insns); | |
2916 | } | |
2917 | ||
584892a6 RS |
2918 | /* Set up global variables for the start of a new macro. */ |
2919 | ||
2920 | static void | |
2921 | macro_start (void) | |
2922 | { | |
2923 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2924 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2925 | && (prev_insn.insn_mo->pinfo | |
2926 | & (INSN_UNCOND_BRANCH_DELAY | |
2927 | | INSN_COND_BRANCH_DELAY | |
2928 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2929 | } | |
2930 | ||
2931 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2932 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2933 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2934 | ||
2935 | static const char * | |
2936 | macro_warning (relax_substateT subtype) | |
2937 | { | |
2938 | if (subtype & RELAX_DELAY_SLOT) | |
2939 | return _("Macro instruction expanded into multiple instructions" | |
2940 | " in a branch delay slot"); | |
2941 | else if (subtype & RELAX_NOMACRO) | |
2942 | return _("Macro instruction expanded into multiple instructions"); | |
2943 | else | |
2944 | return 0; | |
2945 | } | |
2946 | ||
2947 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2948 | ||
2949 | static void | |
2950 | macro_end (void) | |
2951 | { | |
2952 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2953 | { | |
2954 | relax_substateT subtype; | |
2955 | ||
2956 | /* Set up the relaxation warning flags. */ | |
2957 | subtype = 0; | |
2958 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2959 | subtype |= RELAX_SECOND_LONGER; | |
2960 | if (mips_opts.warn_about_macros) | |
2961 | subtype |= RELAX_NOMACRO; | |
2962 | if (mips_macro_warning.delay_slot_p) | |
2963 | subtype |= RELAX_DELAY_SLOT; | |
2964 | ||
2965 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2966 | { | |
2967 | /* Either the macro has a single implementation or both | |
2968 | implementations are longer than 4 bytes. Emit the | |
2969 | warning now. */ | |
2970 | const char *msg = macro_warning (subtype); | |
2971 | if (msg != 0) | |
2972 | as_warn (msg); | |
2973 | } | |
2974 | else | |
2975 | { | |
2976 | /* One implementation might need a warning but the other | |
2977 | definitely doesn't. */ | |
2978 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2979 | } | |
2980 | } | |
2981 | } | |
2982 | ||
6e1304d8 RS |
2983 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2984 | The first argument in *ARGS will be either the code for a single | |
2985 | relocation or -1 followed by the three codes that make up a | |
2986 | composite relocation. */ | |
2987 | ||
2988 | static void | |
2989 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2990 | { | |
2991 | int i, next; | |
2992 | ||
2993 | next = va_arg (*args, int); | |
2994 | if (next >= 0) | |
2995 | r[0] = (bfd_reloc_code_real_type) next; | |
2996 | else | |
2997 | for (i = 0; i < 3; i++) | |
2998 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2999 | } | |
3000 | ||
252b5132 RH |
3001 | /* Build an instruction created by a macro expansion. This is passed |
3002 | a pointer to the count of instructions created so far, an | |
3003 | expression, the name of the instruction to build, an operand format | |
3004 | string, and corresponding arguments. */ | |
3005 | ||
252b5132 | 3006 | static void |
67c0d1eb | 3007 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
3008 | { |
3009 | struct mips_cl_insn insn; | |
f6688943 | 3010 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3011 | va_list args; |
252b5132 | 3012 | |
252b5132 | 3013 | va_start (args, fmt); |
252b5132 | 3014 | |
252b5132 RH |
3015 | if (mips_opts.mips16) |
3016 | { | |
67c0d1eb | 3017 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3018 | va_end (args); |
3019 | return; | |
3020 | } | |
3021 | ||
f6688943 TS |
3022 | r[0] = BFD_RELOC_UNUSED; |
3023 | r[1] = BFD_RELOC_UNUSED; | |
3024 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
3025 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3026 | assert (insn.insn_mo); | |
3027 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3028 | ||
3029 | /* Search until we get a match for NAME. */ | |
3030 | while (1) | |
3031 | { | |
b34976b6 | 3032 | /* It is assumed here that macros will never generate |
deec1734 | 3033 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3034 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3035 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3036 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3037 | (mips_opts.isa | |
3396de36 | 3038 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3039 | mips_opts.arch) |
3040 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3041 | break; |
3042 | ||
3043 | ++insn.insn_mo; | |
3044 | assert (insn.insn_mo->name); | |
3045 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3046 | } | |
3047 | ||
3048 | insn.insn_opcode = insn.insn_mo->match; | |
3049 | for (;;) | |
3050 | { | |
3051 | switch (*fmt++) | |
3052 | { | |
3053 | case '\0': | |
3054 | break; | |
3055 | ||
3056 | case ',': | |
3057 | case '(': | |
3058 | case ')': | |
3059 | continue; | |
3060 | ||
5f74bc13 CD |
3061 | case '+': |
3062 | switch (*fmt++) | |
3063 | { | |
3064 | case 'A': | |
3065 | case 'E': | |
3066 | insn.insn_opcode |= (va_arg (args, int) | |
3067 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3068 | continue; | |
3069 | ||
3070 | case 'B': | |
3071 | case 'F': | |
3072 | /* Note that in the macro case, these arguments are already | |
3073 | in MSB form. (When handling the instruction in the | |
3074 | non-macro case, these arguments are sizes from which | |
3075 | MSB values must be calculated.) */ | |
3076 | insn.insn_opcode |= (va_arg (args, int) | |
3077 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3078 | continue; | |
3079 | ||
3080 | case 'C': | |
3081 | case 'G': | |
3082 | case 'H': | |
3083 | /* Note that in the macro case, these arguments are already | |
3084 | in MSBD form. (When handling the instruction in the | |
3085 | non-macro case, these arguments are sizes from which | |
3086 | MSBD values must be calculated.) */ | |
3087 | insn.insn_opcode |= (va_arg (args, int) | |
3088 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3089 | continue; | |
3090 | ||
3091 | default: | |
3092 | internalError (); | |
3093 | } | |
3094 | continue; | |
3095 | ||
252b5132 RH |
3096 | case 't': |
3097 | case 'w': | |
3098 | case 'E': | |
38487616 | 3099 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3100 | continue; |
3101 | ||
3102 | case 'c': | |
38487616 TS |
3103 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3104 | continue; | |
3105 | ||
252b5132 RH |
3106 | case 'T': |
3107 | case 'W': | |
38487616 | 3108 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3109 | continue; |
3110 | ||
3111 | case 'd': | |
3112 | case 'G': | |
af7ee8bf | 3113 | case 'K': |
38487616 | 3114 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3115 | continue; |
3116 | ||
4372b673 NC |
3117 | case 'U': |
3118 | { | |
3119 | int tmp = va_arg (args, int); | |
3120 | ||
38487616 TS |
3121 | insn.insn_opcode |= tmp << OP_SH_RT; |
3122 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3123 | continue; |
4372b673 NC |
3124 | } |
3125 | ||
252b5132 RH |
3126 | case 'V': |
3127 | case 'S': | |
38487616 | 3128 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3129 | continue; |
3130 | ||
3131 | case 'z': | |
3132 | continue; | |
3133 | ||
3134 | case '<': | |
38487616 | 3135 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3136 | continue; |
3137 | ||
3138 | case 'D': | |
38487616 | 3139 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3140 | continue; |
3141 | ||
3142 | case 'B': | |
38487616 | 3143 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3144 | continue; |
3145 | ||
4372b673 | 3146 | case 'J': |
38487616 | 3147 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3148 | continue; |
3149 | ||
252b5132 | 3150 | case 'q': |
38487616 | 3151 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3152 | continue; |
3153 | ||
3154 | case 'b': | |
3155 | case 's': | |
3156 | case 'r': | |
3157 | case 'v': | |
38487616 | 3158 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3159 | continue; |
3160 | ||
3161 | case 'i': | |
3162 | case 'j': | |
3163 | case 'o': | |
6e1304d8 | 3164 | macro_read_relocs (&args, r); |
cdf6fd85 | 3165 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3166 | || *r == BFD_RELOC_MIPS_LITERAL |
3167 | || *r == BFD_RELOC_MIPS_HIGHER | |
3168 | || *r == BFD_RELOC_HI16_S | |
3169 | || *r == BFD_RELOC_LO16 | |
3170 | || *r == BFD_RELOC_MIPS_GOT16 | |
3171 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3172 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3173 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3174 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3175 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3176 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3177 | continue; |
3178 | ||
3179 | case 'u': | |
6e1304d8 | 3180 | macro_read_relocs (&args, r); |
252b5132 RH |
3181 | assert (ep != NULL |
3182 | && (ep->X_op == O_constant | |
3183 | || (ep->X_op == O_symbol | |
f6688943 TS |
3184 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3185 | || *r == BFD_RELOC_HI16_S | |
3186 | || *r == BFD_RELOC_HI16 | |
3187 | || *r == BFD_RELOC_GPREL16 | |
3188 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3189 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3190 | continue; |
3191 | ||
3192 | case 'p': | |
3193 | assert (ep != NULL); | |
3194 | /* | |
3195 | * This allows macro() to pass an immediate expression for | |
3196 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3197 | * Note that the expression still might come from the assembly |
3198 | * input, in which case the value is not checked for range nor | |
3199 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3200 | */ |
3201 | if (ep->X_op == O_constant) | |
3202 | { | |
3203 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3204 | ep = NULL; | |
3205 | } | |
3206 | else | |
0b25d3e6 | 3207 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3208 | continue; |
3209 | ||
3210 | case 'a': | |
3211 | assert (ep != NULL); | |
f6688943 | 3212 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3213 | continue; |
3214 | ||
3215 | case 'C': | |
3216 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3217 | continue; | |
3218 | ||
3219 | default: | |
3220 | internalError (); | |
3221 | } | |
3222 | break; | |
3223 | } | |
3224 | va_end (args); | |
f6688943 | 3225 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3226 | |
4d7206a2 | 3227 | append_insn (&insn, ep, r); |
252b5132 RH |
3228 | } |
3229 | ||
3230 | static void | |
67c0d1eb | 3231 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3232 | va_list args) |
252b5132 RH |
3233 | { |
3234 | struct mips_cl_insn insn; | |
f6688943 TS |
3235 | bfd_reloc_code_real_type r[3] |
3236 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3237 | |
252b5132 RH |
3238 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3239 | assert (insn.insn_mo); | |
3240 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3241 | ||
3242 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3243 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3244 | { | |
3245 | ++insn.insn_mo; | |
3246 | assert (insn.insn_mo->name); | |
3247 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3248 | } | |
3249 | ||
3250 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3251 | insn.use_extend = FALSE; |
252b5132 RH |
3252 | |
3253 | for (;;) | |
3254 | { | |
3255 | int c; | |
3256 | ||
3257 | c = *fmt++; | |
3258 | switch (c) | |
3259 | { | |
3260 | case '\0': | |
3261 | break; | |
3262 | ||
3263 | case ',': | |
3264 | case '(': | |
3265 | case ')': | |
3266 | continue; | |
3267 | ||
3268 | case 'y': | |
3269 | case 'w': | |
3270 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3271 | continue; | |
3272 | ||
3273 | case 'x': | |
3274 | case 'v': | |
3275 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3276 | continue; | |
3277 | ||
3278 | case 'z': | |
3279 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3280 | continue; | |
3281 | ||
3282 | case 'Z': | |
3283 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3284 | continue; | |
3285 | ||
3286 | case '0': | |
3287 | case 'S': | |
3288 | case 'P': | |
3289 | case 'R': | |
3290 | continue; | |
3291 | ||
3292 | case 'X': | |
3293 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3294 | continue; | |
3295 | ||
3296 | case 'Y': | |
3297 | { | |
3298 | int regno; | |
3299 | ||
3300 | regno = va_arg (args, int); | |
3301 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3302 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3303 | } | |
3304 | continue; | |
3305 | ||
3306 | case '<': | |
3307 | case '>': | |
3308 | case '4': | |
3309 | case '5': | |
3310 | case 'H': | |
3311 | case 'W': | |
3312 | case 'D': | |
3313 | case 'j': | |
3314 | case '8': | |
3315 | case 'V': | |
3316 | case 'C': | |
3317 | case 'U': | |
3318 | case 'k': | |
3319 | case 'K': | |
3320 | case 'p': | |
3321 | case 'q': | |
3322 | { | |
3323 | assert (ep != NULL); | |
3324 | ||
3325 | if (ep->X_op != O_constant) | |
874e8986 | 3326 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3327 | else |
3328 | { | |
b34976b6 AM |
3329 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3330 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3331 | &insn.extend); |
252b5132 | 3332 | ep = NULL; |
f6688943 | 3333 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3334 | } |
3335 | } | |
3336 | continue; | |
3337 | ||
3338 | case '6': | |
3339 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3340 | continue; | |
3341 | } | |
3342 | ||
3343 | break; | |
3344 | } | |
3345 | ||
f6688943 | 3346 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3347 | |
4d7206a2 | 3348 | append_insn (&insn, ep, r); |
252b5132 RH |
3349 | } |
3350 | ||
438c16b8 TS |
3351 | /* |
3352 | * Generate a "jalr" instruction with a relocation hint to the called | |
3353 | * function. This occurs in NewABI PIC code. | |
3354 | */ | |
3355 | static void | |
67c0d1eb | 3356 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3357 | { |
685736be | 3358 | char *f = NULL; |
b34976b6 | 3359 | |
438c16b8 | 3360 | if (HAVE_NEWABI) |
f21f8242 | 3361 | { |
cc3d92a5 | 3362 | frag_grow (8); |
f21f8242 AO |
3363 | f = frag_more (0); |
3364 | } | |
67c0d1eb | 3365 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3366 | if (HAVE_NEWABI) |
f21f8242 | 3367 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3368 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3369 | } |
3370 | ||
252b5132 RH |
3371 | /* |
3372 | * Generate a "lui" instruction. | |
3373 | */ | |
3374 | static void | |
67c0d1eb | 3375 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3376 | { |
3377 | expressionS high_expr; | |
3378 | struct mips_cl_insn insn; | |
f6688943 TS |
3379 | bfd_reloc_code_real_type r[3] |
3380 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3381 | const char *name = "lui"; |
3382 | const char *fmt = "t,u"; | |
252b5132 RH |
3383 | |
3384 | assert (! mips_opts.mips16); | |
3385 | ||
4d7206a2 | 3386 | high_expr = *ep; |
252b5132 RH |
3387 | |
3388 | if (high_expr.X_op == O_constant) | |
3389 | { | |
3390 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3391 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3392 | >> 16) & 0xffff; | |
f6688943 | 3393 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3394 | } |
78e1bb40 | 3395 | else |
252b5132 RH |
3396 | { |
3397 | assert (ep->X_op == O_symbol); | |
aa6975fb ILT |
3398 | /* _gp_disp is a special case, used from s_cpload. _gp is used |
3399 | if mips_no_shared. */ | |
252b5132 | 3400 | assert (mips_pic == NO_PIC |
78e1bb40 | 3401 | || (! HAVE_NEWABI |
aa6975fb ILT |
3402 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3403 | || (! mips_in_shared | |
3404 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp") == 0)); | |
f6688943 | 3405 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3406 | } |
3407 | ||
252b5132 RH |
3408 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3409 | assert (insn.insn_mo); | |
3410 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3411 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3412 | ||
3413 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3414 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3415 | { |
3416 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3417 | append_insn (&insn, NULL, r); |
252b5132 RH |
3418 | } |
3419 | else | |
4d7206a2 | 3420 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3421 | } |
3422 | ||
885add95 CD |
3423 | /* Generate a sequence of instructions to do a load or store from a constant |
3424 | offset off of a base register (breg) into/from a target register (treg), | |
3425 | using AT if necessary. */ | |
3426 | static void | |
67c0d1eb RS |
3427 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3428 | int treg, int breg, int dbl) | |
885add95 CD |
3429 | { |
3430 | assert (ep->X_op == O_constant); | |
3431 | ||
256ab948 | 3432 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3433 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3434 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3435 | { |
d17e7bce | 3436 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3437 | as_bad (_("constant too large")); |
ae826530 | 3438 | |
1b8e29e5 TS |
3439 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3440 | - 0x80000000); | |
ae826530 | 3441 | } |
256ab948 | 3442 | |
67c1ffbe | 3443 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3444 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3445 | as_warn (_("operand overflow")); |
3446 | ||
3447 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3448 | { | |
3449 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3450 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3451 | } |
3452 | else | |
3453 | { | |
3454 | /* 32-bit offset, need multiple instructions and AT, like: | |
3455 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3456 | addu $tempreg,$tempreg,$breg | |
3457 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3458 | to handle the complete offset. */ | |
67c0d1eb RS |
3459 | macro_build_lui (ep, AT); |
3460 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3461 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3462 | |
3463 | if (mips_opts.noat) | |
3464 | as_warn (_("Macro used $at after \".set noat\"")); | |
3465 | } | |
3466 | } | |
3467 | ||
252b5132 RH |
3468 | /* set_at() |
3469 | * Generates code to set the $at register to true (one) | |
3470 | * if reg is less than the immediate expression. | |
3471 | */ | |
3472 | static void | |
67c0d1eb | 3473 | set_at (int reg, int unsignedp) |
252b5132 RH |
3474 | { |
3475 | if (imm_expr.X_op == O_constant | |
3476 | && imm_expr.X_add_number >= -0x8000 | |
3477 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3478 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3479 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3480 | else |
3481 | { | |
67c0d1eb RS |
3482 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3483 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3484 | } |
3485 | } | |
3486 | ||
13757d0c TS |
3487 | static void |
3488 | normalize_constant_expr (expressionS *ex) | |
3489 | { | |
3490 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3491 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3492 | - 0x80000000); | |
3493 | } | |
3494 | ||
252b5132 RH |
3495 | /* Warn if an expression is not a constant. */ |
3496 | ||
3497 | static void | |
17a2f251 | 3498 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3499 | { |
3500 | if (ex->X_op == O_big) | |
3501 | as_bad (_("unsupported large constant")); | |
3502 | else if (ex->X_op != O_constant) | |
3503 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3504 | |
3505 | normalize_constant_expr (ex); | |
252b5132 RH |
3506 | } |
3507 | ||
3508 | /* Count the leading zeroes by performing a binary chop. This is a | |
3509 | bulky bit of source, but performance is a LOT better for the | |
3510 | majority of values than a simple loop to count the bits: | |
3511 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3512 | if ((v) & (1 << (31 - lcnt))) | |
3513 | break; | |
3514 | However it is not code size friendly, and the gain will drop a bit | |
3515 | on certain cached systems. | |
3516 | */ | |
3517 | #define COUNT_TOP_ZEROES(v) \ | |
3518 | (((v) & ~0xffff) == 0 \ | |
3519 | ? ((v) & ~0xff) == 0 \ | |
3520 | ? ((v) & ~0xf) == 0 \ | |
3521 | ? ((v) & ~0x3) == 0 \ | |
3522 | ? ((v) & ~0x1) == 0 \ | |
3523 | ? !(v) \ | |
3524 | ? 32 \ | |
3525 | : 31 \ | |
3526 | : 30 \ | |
3527 | : ((v) & ~0x7) == 0 \ | |
3528 | ? 29 \ | |
3529 | : 28 \ | |
3530 | : ((v) & ~0x3f) == 0 \ | |
3531 | ? ((v) & ~0x1f) == 0 \ | |
3532 | ? 27 \ | |
3533 | : 26 \ | |
3534 | : ((v) & ~0x7f) == 0 \ | |
3535 | ? 25 \ | |
3536 | : 24 \ | |
3537 | : ((v) & ~0xfff) == 0 \ | |
3538 | ? ((v) & ~0x3ff) == 0 \ | |
3539 | ? ((v) & ~0x1ff) == 0 \ | |
3540 | ? 23 \ | |
3541 | : 22 \ | |
3542 | : ((v) & ~0x7ff) == 0 \ | |
3543 | ? 21 \ | |
3544 | : 20 \ | |
3545 | : ((v) & ~0x3fff) == 0 \ | |
3546 | ? ((v) & ~0x1fff) == 0 \ | |
3547 | ? 19 \ | |
3548 | : 18 \ | |
3549 | : ((v) & ~0x7fff) == 0 \ | |
3550 | ? 17 \ | |
3551 | : 16 \ | |
3552 | : ((v) & ~0xffffff) == 0 \ | |
3553 | ? ((v) & ~0xfffff) == 0 \ | |
3554 | ? ((v) & ~0x3ffff) == 0 \ | |
3555 | ? ((v) & ~0x1ffff) == 0 \ | |
3556 | ? 15 \ | |
3557 | : 14 \ | |
3558 | : ((v) & ~0x7ffff) == 0 \ | |
3559 | ? 13 \ | |
3560 | : 12 \ | |
3561 | : ((v) & ~0x3fffff) == 0 \ | |
3562 | ? ((v) & ~0x1fffff) == 0 \ | |
3563 | ? 11 \ | |
3564 | : 10 \ | |
3565 | : ((v) & ~0x7fffff) == 0 \ | |
3566 | ? 9 \ | |
3567 | : 8 \ | |
3568 | : ((v) & ~0xfffffff) == 0 \ | |
3569 | ? ((v) & ~0x3ffffff) == 0 \ | |
3570 | ? ((v) & ~0x1ffffff) == 0 \ | |
3571 | ? 7 \ | |
3572 | : 6 \ | |
3573 | : ((v) & ~0x7ffffff) == 0 \ | |
3574 | ? 5 \ | |
3575 | : 4 \ | |
3576 | : ((v) & ~0x3fffffff) == 0 \ | |
3577 | ? ((v) & ~0x1fffffff) == 0 \ | |
3578 | ? 3 \ | |
3579 | : 2 \ | |
3580 | : ((v) & ~0x7fffffff) == 0 \ | |
3581 | ? 1 \ | |
3582 | : 0) | |
3583 | ||
3584 | /* load_register() | |
67c1ffbe | 3585 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3586 | * an absolute expression value into a register. |
3587 | */ | |
3588 | static void | |
67c0d1eb | 3589 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3590 | { |
3591 | int freg; | |
3592 | expressionS hi32, lo32; | |
3593 | ||
3594 | if (ep->X_op != O_big) | |
3595 | { | |
3596 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3597 | |
3598 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3599 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3600 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3601 | { |
d17e7bce | 3602 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3603 | as_bad (_("constant too large")); |
ae826530 | 3604 | |
1b8e29e5 TS |
3605 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3606 | - 0x80000000); | |
ae826530 | 3607 | } |
256ab948 TS |
3608 | |
3609 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3610 | { |
3611 | /* We can handle 16 bit signed values with an addiu to | |
3612 | $zero. No need to ever use daddiu here, since $zero and | |
3613 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3614 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3615 | return; |
3616 | } | |
3617 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3618 | { | |
3619 | /* We can handle 16 bit unsigned values with an ori to | |
3620 | $zero. */ | |
67c0d1eb | 3621 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3622 | return; |
3623 | } | |
256ab948 | 3624 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3625 | { |
3626 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3627 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3628 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3629 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3630 | return; |
3631 | } | |
3632 | } | |
3633 | ||
3634 | /* The value is larger than 32 bits. */ | |
3635 | ||
ca4e0257 | 3636 | if (HAVE_32BIT_GPRS) |
252b5132 | 3637 | { |
956cd1d6 TS |
3638 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3639 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3640 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3641 | return; |
3642 | } | |
3643 | ||
3644 | if (ep->X_op != O_big) | |
3645 | { | |
3646 | hi32 = *ep; | |
3647 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3648 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3649 | hi32.X_add_number &= 0xffffffff; | |
3650 | lo32 = *ep; | |
3651 | lo32.X_add_number &= 0xffffffff; | |
3652 | } | |
3653 | else | |
3654 | { | |
3655 | assert (ep->X_add_number > 2); | |
3656 | if (ep->X_add_number == 3) | |
3657 | generic_bignum[3] = 0; | |
3658 | else if (ep->X_add_number > 4) | |
3659 | as_bad (_("Number larger than 64 bits")); | |
3660 | lo32.X_op = O_constant; | |
3661 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3662 | hi32.X_op = O_constant; | |
3663 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3664 | } | |
3665 | ||
3666 | if (hi32.X_add_number == 0) | |
3667 | freg = 0; | |
3668 | else | |
3669 | { | |
3670 | int shift, bit; | |
3671 | unsigned long hi, lo; | |
3672 | ||
956cd1d6 | 3673 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3674 | { |
3675 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3676 | { | |
67c0d1eb | 3677 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3678 | return; |
3679 | } | |
3680 | if (lo32.X_add_number & 0x80000000) | |
3681 | { | |
67c0d1eb | 3682 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3683 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3684 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3685 | return; |
3686 | } | |
3687 | } | |
252b5132 RH |
3688 | |
3689 | /* Check for 16bit shifted constant. We know that hi32 is | |
3690 | non-zero, so start the mask on the first bit of the hi32 | |
3691 | value. */ | |
3692 | shift = 17; | |
3693 | do | |
beae10d5 KH |
3694 | { |
3695 | unsigned long himask, lomask; | |
3696 | ||
3697 | if (shift < 32) | |
3698 | { | |
3699 | himask = 0xffff >> (32 - shift); | |
3700 | lomask = (0xffff << shift) & 0xffffffff; | |
3701 | } | |
3702 | else | |
3703 | { | |
3704 | himask = 0xffff << (shift - 32); | |
3705 | lomask = 0; | |
3706 | } | |
3707 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3708 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3709 | { | |
3710 | expressionS tmp; | |
3711 | ||
3712 | tmp.X_op = O_constant; | |
3713 | if (shift < 32) | |
3714 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3715 | | (lo32.X_add_number >> shift)); | |
3716 | else | |
3717 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3718 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3719 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3720 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3721 | return; |
3722 | } | |
f9419b05 | 3723 | ++shift; |
beae10d5 KH |
3724 | } |
3725 | while (shift <= (64 - 16)); | |
252b5132 RH |
3726 | |
3727 | /* Find the bit number of the lowest one bit, and store the | |
3728 | shifted value in hi/lo. */ | |
3729 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3730 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3731 | if (lo != 0) | |
3732 | { | |
3733 | bit = 0; | |
3734 | while ((lo & 1) == 0) | |
3735 | { | |
3736 | lo >>= 1; | |
3737 | ++bit; | |
3738 | } | |
3739 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3740 | hi >>= bit; | |
3741 | } | |
3742 | else | |
3743 | { | |
3744 | bit = 32; | |
3745 | while ((hi & 1) == 0) | |
3746 | { | |
3747 | hi >>= 1; | |
3748 | ++bit; | |
3749 | } | |
3750 | lo = hi; | |
3751 | hi = 0; | |
3752 | } | |
3753 | ||
3754 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3755 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3756 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3757 | { |
3758 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3759 | if (shift != 0) |
beae10d5 | 3760 | { |
252b5132 RH |
3761 | expressionS tmp; |
3762 | ||
3763 | /* This instruction will set the register to be all | |
3764 | ones. */ | |
beae10d5 KH |
3765 | tmp.X_op = O_constant; |
3766 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3767 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3768 | if (bit != 0) |
3769 | { | |
3770 | bit += shift; | |
67c0d1eb RS |
3771 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3772 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3773 | } |
67c0d1eb RS |
3774 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3775 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3776 | return; |
3777 | } | |
3778 | } | |
252b5132 RH |
3779 | |
3780 | /* Sign extend hi32 before calling load_register, because we can | |
3781 | generally get better code when we load a sign extended value. */ | |
3782 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3783 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3784 | load_register (reg, &hi32, 0); |
252b5132 RH |
3785 | freg = reg; |
3786 | } | |
3787 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3788 | { | |
3789 | if (freg != 0) | |
3790 | { | |
67c0d1eb | 3791 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3792 | freg = reg; |
3793 | } | |
3794 | } | |
3795 | else | |
3796 | { | |
3797 | expressionS mid16; | |
3798 | ||
956cd1d6 | 3799 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3800 | { |
67c0d1eb RS |
3801 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3802 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3803 | return; |
3804 | } | |
252b5132 RH |
3805 | |
3806 | if (freg != 0) | |
3807 | { | |
67c0d1eb | 3808 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3809 | freg = reg; |
3810 | } | |
3811 | mid16 = lo32; | |
3812 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3813 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3814 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3815 | freg = reg; |
3816 | } | |
3817 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3818 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3819 | } |
3820 | ||
269137b2 TS |
3821 | static inline void |
3822 | load_delay_nop (void) | |
3823 | { | |
3824 | if (!gpr_interlocks) | |
3825 | macro_build (NULL, "nop", ""); | |
3826 | } | |
3827 | ||
252b5132 RH |
3828 | /* Load an address into a register. */ |
3829 | ||
3830 | static void | |
67c0d1eb | 3831 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3832 | { |
252b5132 RH |
3833 | if (ep->X_op != O_constant |
3834 | && ep->X_op != O_symbol) | |
3835 | { | |
3836 | as_bad (_("expression too complex")); | |
3837 | ep->X_op = O_constant; | |
3838 | } | |
3839 | ||
3840 | if (ep->X_op == O_constant) | |
3841 | { | |
67c0d1eb | 3842 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3843 | return; |
3844 | } | |
3845 | ||
3846 | if (mips_pic == NO_PIC) | |
3847 | { | |
3848 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3849 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3850 | Otherwise we want |
3851 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3852 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3853 | If we have an addend, we always use the latter form. |
76b3015f | 3854 | |
d6bc6245 TS |
3855 | With 64bit address space and a usable $at we want |
3856 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3857 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3858 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3859 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3860 | dsll32 $reg,0 | |
3a482fd5 | 3861 | daddu $reg,$reg,$at |
76b3015f | 3862 | |
c03099e6 | 3863 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3864 | on superscalar processors. |
3865 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3866 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3867 | dsll $reg,16 | |
3868 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3869 | dsll $reg,16 | |
3870 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3871 | */ | |
c9914766 | 3872 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3873 | { |
e864ceca RS |
3874 | /* ??? We don't provide a GP-relative alternative for these macros. |
3875 | It used not to be possible with the original relaxation code, | |
3876 | but it could be done now. */ | |
d6bc6245 | 3877 | |
b8285c27 | 3878 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3879 | { |
67c0d1eb RS |
3880 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3881 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3882 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3883 | BFD_RELOC_MIPS_HIGHER); | |
3884 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3885 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3886 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3887 | *used_at = 1; |
3888 | } | |
3889 | else | |
3890 | { | |
67c0d1eb RS |
3891 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3892 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3893 | BFD_RELOC_MIPS_HIGHER); | |
3894 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3895 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3896 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3897 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3898 | } |
3899 | } | |
252b5132 RH |
3900 | else |
3901 | { | |
d6bc6245 TS |
3902 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3903 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3904 | { | |
4d7206a2 | 3905 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3906 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3907 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3908 | relax_switch (); |
d6bc6245 | 3909 | } |
67c0d1eb RS |
3910 | macro_build_lui (ep, reg); |
3911 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3912 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3913 | if (mips_relax.sequence) |
3914 | relax_end (); | |
d6bc6245 | 3915 | } |
252b5132 RH |
3916 | } |
3917 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3918 | { | |
3919 | expressionS ex; | |
3920 | ||
3921 | /* If this is a reference to an external symbol, we want | |
3922 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3923 | Otherwise we want | |
3924 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3925 | nop | |
3926 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3927 | If there is a constant, it must be added in after. |
3928 | ||
ed6fb7bd | 3929 | If we have NewABI, we want |
f5040a92 AO |
3930 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3931 | unless we're referencing a global symbol with a non-zero | |
3932 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3933 | if (HAVE_NEWABI) |
3934 | { | |
f5040a92 AO |
3935 | if (ep->X_add_number) |
3936 | { | |
4d7206a2 | 3937 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3938 | ep->X_add_number = 0; |
4d7206a2 | 3939 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3940 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3941 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3942 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3943 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3944 | ex.X_op = O_constant; | |
67c0d1eb | 3945 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3946 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3947 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3948 | relax_switch (); |
f5040a92 | 3949 | } |
67c0d1eb | 3950 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3951 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3952 | if (mips_relax.sequence) |
3953 | relax_end (); | |
ed6fb7bd SC |
3954 | } |
3955 | else | |
3956 | { | |
f5040a92 AO |
3957 | ex.X_add_number = ep->X_add_number; |
3958 | ep->X_add_number = 0; | |
67c0d1eb RS |
3959 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3960 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3961 | load_delay_nop (); |
4d7206a2 RS |
3962 | relax_start (ep->X_add_symbol); |
3963 | relax_switch (); | |
67c0d1eb | 3964 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3965 | BFD_RELOC_LO16); |
4d7206a2 | 3966 | relax_end (); |
ed6fb7bd | 3967 | |
f5040a92 AO |
3968 | if (ex.X_add_number != 0) |
3969 | { | |
3970 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3971 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3972 | ex.X_op = O_constant; | |
67c0d1eb | 3973 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3974 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3975 | } |
252b5132 RH |
3976 | } |
3977 | } | |
3978 | else if (mips_pic == SVR4_PIC) | |
3979 | { | |
3980 | expressionS ex; | |
252b5132 RH |
3981 | |
3982 | /* This is the large GOT case. If this is a reference to an | |
3983 | external symbol, we want | |
3984 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3985 | addu $reg,$reg,$gp | |
3986 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3987 | |
3988 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3989 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3990 | nop | |
3991 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3992 | If there is a constant, it must be added in after. |
f5040a92 AO |
3993 | |
3994 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3995 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3996 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3997 | */ |
438c16b8 TS |
3998 | if (HAVE_NEWABI) |
3999 | { | |
4d7206a2 | 4000 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4001 | ep->X_add_number = 0; |
4d7206a2 | 4002 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4003 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4004 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4005 | reg, reg, mips_gp_register); | |
4006 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4007 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4008 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4009 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4010 | else if (ex.X_add_number) | |
4011 | { | |
4012 | ex.X_op = O_constant; | |
67c0d1eb RS |
4013 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4014 | BFD_RELOC_LO16); | |
f5040a92 AO |
4015 | } |
4016 | ||
4017 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4018 | relax_switch (); |
67c0d1eb | 4019 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4020 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4021 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4022 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4023 | relax_end (); |
438c16b8 | 4024 | } |
252b5132 | 4025 | else |
438c16b8 | 4026 | { |
f5040a92 AO |
4027 | ex.X_add_number = ep->X_add_number; |
4028 | ep->X_add_number = 0; | |
4d7206a2 | 4029 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4030 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4031 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4032 | reg, reg, mips_gp_register); | |
4033 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4034 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4035 | relax_switch (); |
4036 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4037 | { |
4038 | /* We need a nop before loading from $gp. This special | |
4039 | check is required because the lui which starts the main | |
4040 | instruction stream does not refer to $gp, and so will not | |
4041 | insert the nop which may be required. */ | |
67c0d1eb | 4042 | macro_build (NULL, "nop", ""); |
438c16b8 | 4043 | } |
67c0d1eb | 4044 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4045 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4046 | load_delay_nop (); |
67c0d1eb | 4047 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4048 | BFD_RELOC_LO16); |
4d7206a2 | 4049 | relax_end (); |
438c16b8 | 4050 | |
f5040a92 AO |
4051 | if (ex.X_add_number != 0) |
4052 | { | |
4053 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4054 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4055 | ex.X_op = O_constant; | |
67c0d1eb RS |
4056 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4057 | BFD_RELOC_LO16); | |
f5040a92 | 4058 | } |
252b5132 RH |
4059 | } |
4060 | } | |
252b5132 RH |
4061 | else |
4062 | abort (); | |
4063 | } | |
4064 | ||
ea1fb5dc RS |
4065 | /* Move the contents of register SOURCE into register DEST. */ |
4066 | ||
4067 | static void | |
67c0d1eb | 4068 | move_register (int dest, int source) |
ea1fb5dc | 4069 | { |
67c0d1eb RS |
4070 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4071 | dest, source, 0); | |
ea1fb5dc RS |
4072 | } |
4073 | ||
4d7206a2 | 4074 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4075 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4076 | The two alternatives are: | |
4d7206a2 RS |
4077 | |
4078 | Global symbol Local sybmol | |
4079 | ------------- ------------ | |
4080 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4081 | ... ... | |
4082 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4083 | ||
4084 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4085 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4086 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4087 | |
4088 | static void | |
67c0d1eb | 4089 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4090 | { |
4091 | expressionS global; | |
4092 | ||
4093 | global = *local; | |
4094 | global.X_add_number = 0; | |
4095 | ||
4096 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4097 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4098 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4099 | relax_switch (); |
67c0d1eb RS |
4100 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4101 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4102 | relax_end (); |
4103 | } | |
4104 | ||
4105 | static void | |
67c0d1eb | 4106 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4107 | { |
4108 | expressionS global; | |
4109 | ||
4110 | global.X_op = O_constant; | |
4111 | global.X_op_symbol = NULL; | |
4112 | global.X_add_symbol = NULL; | |
4113 | global.X_add_number = local->X_add_number; | |
4114 | ||
4115 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4116 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4117 | dest, dest, BFD_RELOC_LO16); |
4118 | relax_switch (); | |
67c0d1eb | 4119 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4120 | relax_end (); |
4121 | } | |
4122 | ||
f6a22291 MR |
4123 | static void |
4124 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4125 | { | |
4126 | expressionS global; | |
4127 | int hold_mips_optimize; | |
4128 | ||
4129 | global.X_op = O_constant; | |
4130 | global.X_op_symbol = NULL; | |
4131 | global.X_add_symbol = NULL; | |
4132 | global.X_add_number = local->X_add_number; | |
4133 | ||
4134 | relax_start (local->X_add_symbol); | |
4135 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4136 | relax_switch (); | |
4137 | /* Set mips_optimize around the lui instruction to avoid | |
4138 | inserting an unnecessary nop after the lw. */ | |
4139 | hold_mips_optimize = mips_optimize; | |
4140 | mips_optimize = 2; | |
4141 | macro_build_lui (&global, tmp); | |
4142 | mips_optimize = hold_mips_optimize; | |
4143 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4144 | relax_end (); | |
4145 | ||
4146 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4147 | } | |
4148 | ||
252b5132 RH |
4149 | /* |
4150 | * Build macros | |
4151 | * This routine implements the seemingly endless macro or synthesized | |
4152 | * instructions and addressing modes in the mips assembly language. Many | |
4153 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4154 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4155 | * this verbose method. Others are not simple macros but are more like |
4156 | * optimizing code generation. | |
4157 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4158 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4159 | * The ensuing load upper instructions are ommited. This implies some kind |
4160 | * of global optimization. We currently only optimize within a single macro. | |
4161 | * For many of the load and store macros if the address is specified as a | |
4162 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4163 | * first load register 'at' with zero and use it as the base register. The | |
4164 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4165 | * we're missing. | |
4166 | */ | |
4167 | static void | |
17a2f251 | 4168 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4169 | { |
4170 | register int treg, sreg, dreg, breg; | |
4171 | int tempreg; | |
4172 | int mask; | |
43841e91 | 4173 | int used_at = 0; |
252b5132 RH |
4174 | expressionS expr1; |
4175 | const char *s; | |
4176 | const char *s2; | |
4177 | const char *fmt; | |
4178 | int likely = 0; | |
4179 | int dbl = 0; | |
4180 | int coproc = 0; | |
4181 | int lr = 0; | |
4182 | int imm = 0; | |
1abe91b1 | 4183 | int call = 0; |
252b5132 | 4184 | int off; |
67c0d1eb | 4185 | offsetT maxnum; |
252b5132 | 4186 | bfd_reloc_code_real_type r; |
252b5132 RH |
4187 | int hold_mips_optimize; |
4188 | ||
4189 | assert (! mips_opts.mips16); | |
4190 | ||
4191 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4192 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4193 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4194 | mask = ip->insn_mo->mask; | |
4195 | ||
4196 | expr1.X_op = O_constant; | |
4197 | expr1.X_op_symbol = NULL; | |
4198 | expr1.X_add_symbol = NULL; | |
4199 | expr1.X_add_number = 1; | |
4200 | ||
4201 | switch (mask) | |
4202 | { | |
4203 | case M_DABS: | |
4204 | dbl = 1; | |
4205 | case M_ABS: | |
4206 | /* bgez $a0,.+12 | |
4207 | move v0,$a0 | |
4208 | sub v0,$zero,$a0 | |
4209 | */ | |
4210 | ||
b34976b6 | 4211 | mips_emit_delays (TRUE); |
252b5132 RH |
4212 | ++mips_opts.noreorder; |
4213 | mips_any_noreorder = 1; | |
4214 | ||
4215 | expr1.X_add_number = 8; | |
67c0d1eb | 4216 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4217 | if (dreg == sreg) |
67c0d1eb | 4218 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4219 | else |
67c0d1eb RS |
4220 | move_register (dreg, sreg); |
4221 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4222 | |
4223 | --mips_opts.noreorder; | |
4224 | return; | |
4225 | ||
4226 | case M_ADD_I: | |
4227 | s = "addi"; | |
4228 | s2 = "add"; | |
4229 | goto do_addi; | |
4230 | case M_ADDU_I: | |
4231 | s = "addiu"; | |
4232 | s2 = "addu"; | |
4233 | goto do_addi; | |
4234 | case M_DADD_I: | |
4235 | dbl = 1; | |
4236 | s = "daddi"; | |
4237 | s2 = "dadd"; | |
4238 | goto do_addi; | |
4239 | case M_DADDU_I: | |
4240 | dbl = 1; | |
4241 | s = "daddiu"; | |
4242 | s2 = "daddu"; | |
4243 | do_addi: | |
4244 | if (imm_expr.X_op == O_constant | |
4245 | && imm_expr.X_add_number >= -0x8000 | |
4246 | && imm_expr.X_add_number < 0x8000) | |
4247 | { | |
67c0d1eb | 4248 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4249 | return; |
4250 | } | |
67c0d1eb RS |
4251 | load_register (AT, &imm_expr, dbl); |
4252 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4253 | break; |
4254 | ||
4255 | case M_AND_I: | |
4256 | s = "andi"; | |
4257 | s2 = "and"; | |
4258 | goto do_bit; | |
4259 | case M_OR_I: | |
4260 | s = "ori"; | |
4261 | s2 = "or"; | |
4262 | goto do_bit; | |
4263 | case M_NOR_I: | |
4264 | s = ""; | |
4265 | s2 = "nor"; | |
4266 | goto do_bit; | |
4267 | case M_XOR_I: | |
4268 | s = "xori"; | |
4269 | s2 = "xor"; | |
4270 | do_bit: | |
4271 | if (imm_expr.X_op == O_constant | |
4272 | && imm_expr.X_add_number >= 0 | |
4273 | && imm_expr.X_add_number < 0x10000) | |
4274 | { | |
4275 | if (mask != M_NOR_I) | |
67c0d1eb | 4276 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4277 | else |
4278 | { | |
67c0d1eb RS |
4279 | macro_build (&imm_expr, "ori", "t,r,i", |
4280 | treg, sreg, BFD_RELOC_LO16); | |
4281 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4282 | } |
4283 | return; | |
4284 | } | |
4285 | ||
67c0d1eb RS |
4286 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4287 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4288 | break; |
4289 | ||
4290 | case M_BEQ_I: | |
4291 | s = "beq"; | |
4292 | goto beq_i; | |
4293 | case M_BEQL_I: | |
4294 | s = "beql"; | |
4295 | likely = 1; | |
4296 | goto beq_i; | |
4297 | case M_BNE_I: | |
4298 | s = "bne"; | |
4299 | goto beq_i; | |
4300 | case M_BNEL_I: | |
4301 | s = "bnel"; | |
4302 | likely = 1; | |
4303 | beq_i: | |
4304 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4305 | { | |
67c0d1eb | 4306 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4307 | return; |
4308 | } | |
67c0d1eb RS |
4309 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4310 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4311 | break; |
4312 | ||
4313 | case M_BGEL: | |
4314 | likely = 1; | |
4315 | case M_BGE: | |
4316 | if (treg == 0) | |
4317 | { | |
67c0d1eb | 4318 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4319 | return; |
4320 | } | |
4321 | if (sreg == 0) | |
4322 | { | |
67c0d1eb | 4323 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4324 | return; |
4325 | } | |
67c0d1eb RS |
4326 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4327 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4328 | break; |
4329 | ||
4330 | case M_BGTL_I: | |
4331 | likely = 1; | |
4332 | case M_BGT_I: | |
4333 | /* check for > max integer */ | |
4334 | maxnum = 0x7fffffff; | |
ca4e0257 | 4335 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4336 | { |
4337 | maxnum <<= 16; | |
4338 | maxnum |= 0xffff; | |
4339 | maxnum <<= 16; | |
4340 | maxnum |= 0xffff; | |
4341 | } | |
4342 | if (imm_expr.X_op == O_constant | |
4343 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4344 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4345 | { |
4346 | do_false: | |
4347 | /* result is always false */ | |
4348 | if (! likely) | |
67c0d1eb | 4349 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4350 | else |
67c0d1eb | 4351 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4352 | return; |
4353 | } | |
4354 | if (imm_expr.X_op != O_constant) | |
4355 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4356 | ++imm_expr.X_add_number; |
252b5132 RH |
4357 | /* FALLTHROUGH */ |
4358 | case M_BGE_I: | |
4359 | case M_BGEL_I: | |
4360 | if (mask == M_BGEL_I) | |
4361 | likely = 1; | |
4362 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4363 | { | |
67c0d1eb | 4364 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4365 | return; |
4366 | } | |
4367 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4368 | { | |
67c0d1eb | 4369 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4370 | return; |
4371 | } | |
4372 | maxnum = 0x7fffffff; | |
ca4e0257 | 4373 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4374 | { |
4375 | maxnum <<= 16; | |
4376 | maxnum |= 0xffff; | |
4377 | maxnum <<= 16; | |
4378 | maxnum |= 0xffff; | |
4379 | } | |
4380 | maxnum = - maxnum - 1; | |
4381 | if (imm_expr.X_op == O_constant | |
4382 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4383 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4384 | { |
4385 | do_true: | |
4386 | /* result is always true */ | |
4387 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4388 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4389 | return; |
4390 | } | |
67c0d1eb RS |
4391 | set_at (sreg, 0); |
4392 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4393 | break; |
4394 | ||
4395 | case M_BGEUL: | |
4396 | likely = 1; | |
4397 | case M_BGEU: | |
4398 | if (treg == 0) | |
4399 | goto do_true; | |
4400 | if (sreg == 0) | |
4401 | { | |
67c0d1eb | 4402 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4403 | "s,t,p", 0, treg); |
252b5132 RH |
4404 | return; |
4405 | } | |
67c0d1eb RS |
4406 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4407 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4408 | break; |
4409 | ||
4410 | case M_BGTUL_I: | |
4411 | likely = 1; | |
4412 | case M_BGTU_I: | |
4413 | if (sreg == 0 | |
ca4e0257 | 4414 | || (HAVE_32BIT_GPRS |
252b5132 | 4415 | && imm_expr.X_op == O_constant |
956cd1d6 | 4416 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4417 | goto do_false; |
4418 | if (imm_expr.X_op != O_constant) | |
4419 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4420 | ++imm_expr.X_add_number; |
252b5132 RH |
4421 | /* FALLTHROUGH */ |
4422 | case M_BGEU_I: | |
4423 | case M_BGEUL_I: | |
4424 | if (mask == M_BGEUL_I) | |
4425 | likely = 1; | |
4426 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4427 | goto do_true; | |
4428 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4429 | { | |
67c0d1eb | 4430 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4431 | "s,t,p", sreg, 0); |
252b5132 RH |
4432 | return; |
4433 | } | |
67c0d1eb RS |
4434 | set_at (sreg, 1); |
4435 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4436 | break; |
4437 | ||
4438 | case M_BGTL: | |
4439 | likely = 1; | |
4440 | case M_BGT: | |
4441 | if (treg == 0) | |
4442 | { | |
67c0d1eb | 4443 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4444 | return; |
4445 | } | |
4446 | if (sreg == 0) | |
4447 | { | |
67c0d1eb | 4448 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4449 | return; |
4450 | } | |
67c0d1eb RS |
4451 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4452 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4453 | break; |
4454 | ||
4455 | case M_BGTUL: | |
4456 | likely = 1; | |
4457 | case M_BGTU: | |
4458 | if (treg == 0) | |
4459 | { | |
67c0d1eb | 4460 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4461 | "s,t,p", sreg, 0); |
252b5132 RH |
4462 | return; |
4463 | } | |
4464 | if (sreg == 0) | |
4465 | goto do_false; | |
67c0d1eb RS |
4466 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4467 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4468 | break; |
4469 | ||
4470 | case M_BLEL: | |
4471 | likely = 1; | |
4472 | case M_BLE: | |
4473 | if (treg == 0) | |
4474 | { | |
67c0d1eb | 4475 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4476 | return; |
4477 | } | |
4478 | if (sreg == 0) | |
4479 | { | |
67c0d1eb | 4480 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4481 | return; |
4482 | } | |
67c0d1eb RS |
4483 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4484 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4485 | break; |
4486 | ||
4487 | case M_BLEL_I: | |
4488 | likely = 1; | |
4489 | case M_BLE_I: | |
4490 | maxnum = 0x7fffffff; | |
ca4e0257 | 4491 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4492 | { |
4493 | maxnum <<= 16; | |
4494 | maxnum |= 0xffff; | |
4495 | maxnum <<= 16; | |
4496 | maxnum |= 0xffff; | |
4497 | } | |
4498 | if (imm_expr.X_op == O_constant | |
4499 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4500 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4501 | goto do_true; |
4502 | if (imm_expr.X_op != O_constant) | |
4503 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4504 | ++imm_expr.X_add_number; |
252b5132 RH |
4505 | /* FALLTHROUGH */ |
4506 | case M_BLT_I: | |
4507 | case M_BLTL_I: | |
4508 | if (mask == M_BLTL_I) | |
4509 | likely = 1; | |
4510 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4511 | { | |
67c0d1eb | 4512 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4513 | return; |
4514 | } | |
4515 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4516 | { | |
67c0d1eb | 4517 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4518 | return; |
4519 | } | |
67c0d1eb RS |
4520 | set_at (sreg, 0); |
4521 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4522 | break; |
4523 | ||
4524 | case M_BLEUL: | |
4525 | likely = 1; | |
4526 | case M_BLEU: | |
4527 | if (treg == 0) | |
4528 | { | |
67c0d1eb | 4529 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4530 | "s,t,p", sreg, 0); |
252b5132 RH |
4531 | return; |
4532 | } | |
4533 | if (sreg == 0) | |
4534 | goto do_true; | |
67c0d1eb RS |
4535 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4536 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4537 | break; |
4538 | ||
4539 | case M_BLEUL_I: | |
4540 | likely = 1; | |
4541 | case M_BLEU_I: | |
4542 | if (sreg == 0 | |
ca4e0257 | 4543 | || (HAVE_32BIT_GPRS |
252b5132 | 4544 | && imm_expr.X_op == O_constant |
956cd1d6 | 4545 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4546 | goto do_true; |
4547 | if (imm_expr.X_op != O_constant) | |
4548 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4549 | ++imm_expr.X_add_number; |
252b5132 RH |
4550 | /* FALLTHROUGH */ |
4551 | case M_BLTU_I: | |
4552 | case M_BLTUL_I: | |
4553 | if (mask == M_BLTUL_I) | |
4554 | likely = 1; | |
4555 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4556 | goto do_false; | |
4557 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4558 | { | |
67c0d1eb | 4559 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4560 | "s,t,p", sreg, 0); |
4561 | return; | |
4562 | } | |
67c0d1eb RS |
4563 | set_at (sreg, 1); |
4564 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4565 | break; |
4566 | ||
4567 | case M_BLTL: | |
4568 | likely = 1; | |
4569 | case M_BLT: | |
4570 | if (treg == 0) | |
4571 | { | |
67c0d1eb | 4572 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4573 | return; |
4574 | } | |
4575 | if (sreg == 0) | |
4576 | { | |
67c0d1eb | 4577 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4578 | return; |
4579 | } | |
67c0d1eb RS |
4580 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4581 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4582 | break; |
4583 | ||
4584 | case M_BLTUL: | |
4585 | likely = 1; | |
4586 | case M_BLTU: | |
4587 | if (treg == 0) | |
4588 | goto do_false; | |
4589 | if (sreg == 0) | |
4590 | { | |
67c0d1eb | 4591 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4592 | "s,t,p", 0, treg); |
252b5132 RH |
4593 | return; |
4594 | } | |
67c0d1eb RS |
4595 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4596 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4597 | break; |
4598 | ||
5f74bc13 CD |
4599 | case M_DEXT: |
4600 | { | |
4601 | unsigned long pos; | |
4602 | unsigned long size; | |
4603 | ||
4604 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4605 | { | |
4606 | as_bad (_("Unsupported large constant")); | |
4607 | pos = size = 1; | |
4608 | } | |
4609 | else | |
4610 | { | |
4611 | pos = (unsigned long) imm_expr.X_add_number; | |
4612 | size = (unsigned long) imm2_expr.X_add_number; | |
4613 | } | |
4614 | ||
4615 | if (pos > 63) | |
4616 | { | |
4617 | as_bad (_("Improper position (%lu)"), pos); | |
4618 | pos = 1; | |
4619 | } | |
4620 | if (size == 0 || size > 64 | |
4621 | || (pos + size - 1) > 63) | |
4622 | { | |
4623 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4624 | size, pos); | |
4625 | size = 1; | |
4626 | } | |
4627 | ||
4628 | if (size <= 32 && pos < 32) | |
4629 | { | |
4630 | s = "dext"; | |
4631 | fmt = "t,r,+A,+C"; | |
4632 | } | |
4633 | else if (size <= 32) | |
4634 | { | |
4635 | s = "dextu"; | |
4636 | fmt = "t,r,+E,+H"; | |
4637 | } | |
4638 | else | |
4639 | { | |
4640 | s = "dextm"; | |
4641 | fmt = "t,r,+A,+G"; | |
4642 | } | |
67c0d1eb | 4643 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4644 | } |
4645 | return; | |
4646 | ||
4647 | case M_DINS: | |
4648 | { | |
4649 | unsigned long pos; | |
4650 | unsigned long size; | |
4651 | ||
4652 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4653 | { | |
4654 | as_bad (_("Unsupported large constant")); | |
4655 | pos = size = 1; | |
4656 | } | |
4657 | else | |
4658 | { | |
4659 | pos = (unsigned long) imm_expr.X_add_number; | |
4660 | size = (unsigned long) imm2_expr.X_add_number; | |
4661 | } | |
4662 | ||
4663 | if (pos > 63) | |
4664 | { | |
4665 | as_bad (_("Improper position (%lu)"), pos); | |
4666 | pos = 1; | |
4667 | } | |
4668 | if (size == 0 || size > 64 | |
4669 | || (pos + size - 1) > 63) | |
4670 | { | |
4671 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4672 | size, pos); | |
4673 | size = 1; | |
4674 | } | |
4675 | ||
4676 | if (pos < 32 && (pos + size - 1) < 32) | |
4677 | { | |
4678 | s = "dins"; | |
4679 | fmt = "t,r,+A,+B"; | |
4680 | } | |
4681 | else if (pos >= 32) | |
4682 | { | |
4683 | s = "dinsu"; | |
4684 | fmt = "t,r,+E,+F"; | |
4685 | } | |
4686 | else | |
4687 | { | |
4688 | s = "dinsm"; | |
4689 | fmt = "t,r,+A,+F"; | |
4690 | } | |
67c0d1eb RS |
4691 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4692 | pos + size - 1); | |
5f74bc13 CD |
4693 | } |
4694 | return; | |
4695 | ||
252b5132 RH |
4696 | case M_DDIV_3: |
4697 | dbl = 1; | |
4698 | case M_DIV_3: | |
4699 | s = "mflo"; | |
4700 | goto do_div3; | |
4701 | case M_DREM_3: | |
4702 | dbl = 1; | |
4703 | case M_REM_3: | |
4704 | s = "mfhi"; | |
4705 | do_div3: | |
4706 | if (treg == 0) | |
4707 | { | |
4708 | as_warn (_("Divide by zero.")); | |
4709 | if (mips_trap) | |
67c0d1eb | 4710 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4711 | else |
67c0d1eb | 4712 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4713 | return; |
4714 | } | |
4715 | ||
b34976b6 | 4716 | mips_emit_delays (TRUE); |
252b5132 RH |
4717 | ++mips_opts.noreorder; |
4718 | mips_any_noreorder = 1; | |
4719 | if (mips_trap) | |
4720 | { | |
67c0d1eb RS |
4721 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4722 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4723 | } |
4724 | else | |
4725 | { | |
4726 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4727 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4728 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4729 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4730 | } |
4731 | expr1.X_add_number = -1; | |
f6a22291 | 4732 | load_register (AT, &expr1, dbl); |
252b5132 | 4733 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4734 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4735 | if (dbl) |
4736 | { | |
4737 | expr1.X_add_number = 1; | |
f6a22291 | 4738 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4739 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4740 | } |
4741 | else | |
4742 | { | |
4743 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4744 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4745 | } |
4746 | if (mips_trap) | |
4747 | { | |
67c0d1eb | 4748 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4749 | /* We want to close the noreorder block as soon as possible, so |
4750 | that later insns are available for delay slot filling. */ | |
4751 | --mips_opts.noreorder; | |
4752 | } | |
4753 | else | |
4754 | { | |
4755 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4756 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4757 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4758 | |
4759 | /* We want to close the noreorder block as soon as possible, so | |
4760 | that later insns are available for delay slot filling. */ | |
4761 | --mips_opts.noreorder; | |
4762 | ||
67c0d1eb | 4763 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4764 | } |
67c0d1eb | 4765 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4766 | break; |
4767 | ||
4768 | case M_DIV_3I: | |
4769 | s = "div"; | |
4770 | s2 = "mflo"; | |
4771 | goto do_divi; | |
4772 | case M_DIVU_3I: | |
4773 | s = "divu"; | |
4774 | s2 = "mflo"; | |
4775 | goto do_divi; | |
4776 | case M_REM_3I: | |
4777 | s = "div"; | |
4778 | s2 = "mfhi"; | |
4779 | goto do_divi; | |
4780 | case M_REMU_3I: | |
4781 | s = "divu"; | |
4782 | s2 = "mfhi"; | |
4783 | goto do_divi; | |
4784 | case M_DDIV_3I: | |
4785 | dbl = 1; | |
4786 | s = "ddiv"; | |
4787 | s2 = "mflo"; | |
4788 | goto do_divi; | |
4789 | case M_DDIVU_3I: | |
4790 | dbl = 1; | |
4791 | s = "ddivu"; | |
4792 | s2 = "mflo"; | |
4793 | goto do_divi; | |
4794 | case M_DREM_3I: | |
4795 | dbl = 1; | |
4796 | s = "ddiv"; | |
4797 | s2 = "mfhi"; | |
4798 | goto do_divi; | |
4799 | case M_DREMU_3I: | |
4800 | dbl = 1; | |
4801 | s = "ddivu"; | |
4802 | s2 = "mfhi"; | |
4803 | do_divi: | |
4804 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4805 | { | |
4806 | as_warn (_("Divide by zero.")); | |
4807 | if (mips_trap) | |
67c0d1eb | 4808 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4809 | else |
67c0d1eb | 4810 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4811 | return; |
4812 | } | |
4813 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4814 | { | |
4815 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4816 | move_register (dreg, sreg); |
252b5132 | 4817 | else |
67c0d1eb | 4818 | move_register (dreg, 0); |
252b5132 RH |
4819 | return; |
4820 | } | |
4821 | if (imm_expr.X_op == O_constant | |
4822 | && imm_expr.X_add_number == -1 | |
4823 | && s[strlen (s) - 1] != 'u') | |
4824 | { | |
4825 | if (strcmp (s2, "mflo") == 0) | |
4826 | { | |
67c0d1eb | 4827 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4828 | } |
4829 | else | |
67c0d1eb | 4830 | move_register (dreg, 0); |
252b5132 RH |
4831 | return; |
4832 | } | |
4833 | ||
67c0d1eb RS |
4834 | load_register (AT, &imm_expr, dbl); |
4835 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4836 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4837 | break; |
4838 | ||
4839 | case M_DIVU_3: | |
4840 | s = "divu"; | |
4841 | s2 = "mflo"; | |
4842 | goto do_divu3; | |
4843 | case M_REMU_3: | |
4844 | s = "divu"; | |
4845 | s2 = "mfhi"; | |
4846 | goto do_divu3; | |
4847 | case M_DDIVU_3: | |
4848 | s = "ddivu"; | |
4849 | s2 = "mflo"; | |
4850 | goto do_divu3; | |
4851 | case M_DREMU_3: | |
4852 | s = "ddivu"; | |
4853 | s2 = "mfhi"; | |
4854 | do_divu3: | |
b34976b6 | 4855 | mips_emit_delays (TRUE); |
252b5132 RH |
4856 | ++mips_opts.noreorder; |
4857 | mips_any_noreorder = 1; | |
4858 | if (mips_trap) | |
4859 | { | |
67c0d1eb RS |
4860 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4861 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4862 | /* We want to close the noreorder block as soon as possible, so |
4863 | that later insns are available for delay slot filling. */ | |
4864 | --mips_opts.noreorder; | |
4865 | } | |
4866 | else | |
4867 | { | |
4868 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4869 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4870 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4871 | |
4872 | /* We want to close the noreorder block as soon as possible, so | |
4873 | that later insns are available for delay slot filling. */ | |
4874 | --mips_opts.noreorder; | |
67c0d1eb | 4875 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4876 | } |
67c0d1eb | 4877 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4878 | return; |
4879 | ||
1abe91b1 MR |
4880 | case M_DLCA_AB: |
4881 | dbl = 1; | |
4882 | case M_LCA_AB: | |
4883 | call = 1; | |
4884 | goto do_la; | |
252b5132 RH |
4885 | case M_DLA_AB: |
4886 | dbl = 1; | |
4887 | case M_LA_AB: | |
1abe91b1 | 4888 | do_la: |
252b5132 RH |
4889 | /* Load the address of a symbol into a register. If breg is not |
4890 | zero, we then add a base register to it. */ | |
4891 | ||
3bec30a8 TS |
4892 | if (dbl && HAVE_32BIT_GPRS) |
4893 | as_warn (_("dla used to load 32-bit register")); | |
4894 | ||
c90bbe5b | 4895 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4896 | as_warn (_("la used to load 64-bit address")); |
4897 | ||
0c11417f MR |
4898 | if (offset_expr.X_op == O_constant |
4899 | && offset_expr.X_add_number >= -0x8000 | |
4900 | && offset_expr.X_add_number < 0x8000) | |
4901 | { | |
67c0d1eb | 4902 | macro_build (&offset_expr, |
b7c7d6c1 | 4903 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4904 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4905 | return; |
4906 | } | |
4907 | ||
b8285c27 | 4908 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4909 | { |
4910 | tempreg = AT; | |
4911 | used_at = 1; | |
4912 | } | |
4913 | else | |
4914 | { | |
4915 | tempreg = treg; | |
afdbd6d0 CD |
4916 | } |
4917 | ||
252b5132 RH |
4918 | if (offset_expr.X_op != O_symbol |
4919 | && offset_expr.X_op != O_constant) | |
4920 | { | |
4921 | as_bad (_("expression too complex")); | |
4922 | offset_expr.X_op = O_constant; | |
4923 | } | |
4924 | ||
252b5132 | 4925 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4926 | load_register (tempreg, &offset_expr, |
3e722fb5 | 4927 | (mips_pic == NO_PIC |
4d34fb5f TS |
4928 | ? (dbl || HAVE_64BIT_ADDRESSES) |
4929 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4930 | else if (mips_pic == NO_PIC) |
4931 | { | |
d6bc6245 | 4932 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4933 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4934 | Otherwise we want |
4935 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4936 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4937 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4938 | so we may as well always use the latter form. |
76b3015f | 4939 | |
d6bc6245 TS |
4940 | With 64bit address space and a usable $at we want |
4941 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4942 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4943 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4944 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4945 | dsll32 $tempreg,0 | |
3a482fd5 | 4946 | daddu $tempreg,$tempreg,$at |
76b3015f | 4947 | |
c03099e6 | 4948 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4949 | on superscalar processors. |
4950 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4951 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4952 | dsll $tempreg,16 | |
4953 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4954 | dsll $tempreg,16 | |
4955 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4956 | */ | |
d6bc6245 | 4957 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4958 | { |
e864ceca RS |
4959 | /* ??? We don't provide a GP-relative alternative for |
4960 | these macros. It used not to be possible with the | |
4961 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4962 | |
b8285c27 | 4963 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4964 | { |
67c0d1eb | 4965 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4966 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4967 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4968 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4969 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4970 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4971 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4972 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4973 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4974 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4975 | used_at = 1; |
4976 | } | |
4977 | else | |
4978 | { | |
67c0d1eb | 4979 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4980 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4981 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4982 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4983 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4984 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4985 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4986 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4987 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4988 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4989 | } |
4990 | } | |
4991 | else | |
4992 | { | |
4993 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4994 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4995 | { | |
4d7206a2 | 4996 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4997 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4998 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4999 | relax_switch (); |
98d3f06f | 5000 | } |
6943caf0 ILT |
5001 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5002 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5003 | macro_build_lui (&offset_expr, tempreg); |
5004 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5005 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5006 | if (mips_relax.sequence) |
5007 | relax_end (); | |
98d3f06f | 5008 | } |
252b5132 | 5009 | } |
f5040a92 | 5010 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5011 | { |
9117d219 NC |
5012 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5013 | ||
252b5132 RH |
5014 | /* If this is a reference to an external symbol, and there |
5015 | is no constant, we want | |
5016 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5017 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5018 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5019 | For a local symbol, we want |
5020 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5021 | nop | |
5022 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5023 | ||
5024 | If we have a small constant, and this is a reference to | |
5025 | an external symbol, we want | |
5026 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5027 | nop | |
5028 | addiu $tempreg,$tempreg,<constant> | |
5029 | For a local symbol, we want the same instruction | |
5030 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5031 | addiu instruction. | |
5032 | ||
5033 | If we have a large constant, and this is a reference to | |
5034 | an external symbol, we want | |
5035 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5036 | lui $at,<hiconstant> | |
5037 | addiu $at,$at,<loconstant> | |
5038 | addu $tempreg,$tempreg,$at | |
5039 | For a local symbol, we want the same instruction | |
5040 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5041 | addiu instruction. |
ed6fb7bd SC |
5042 | */ |
5043 | ||
4d7206a2 | 5044 | if (offset_expr.X_add_number == 0) |
252b5132 | 5045 | { |
4d7206a2 RS |
5046 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5047 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5048 | ||
5049 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5050 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5051 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5052 | if (breg != 0) |
252b5132 RH |
5053 | { |
5054 | /* We're going to put in an addu instruction using | |
5055 | tempreg, so we may as well insert the nop right | |
5056 | now. */ | |
269137b2 | 5057 | load_delay_nop (); |
252b5132 | 5058 | } |
4d7206a2 | 5059 | relax_switch (); |
67c0d1eb RS |
5060 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5061 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5062 | load_delay_nop (); |
67c0d1eb RS |
5063 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5064 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5065 | relax_end (); |
252b5132 RH |
5066 | /* FIXME: If breg == 0, and the next instruction uses |
5067 | $tempreg, then if this variant case is used an extra | |
5068 | nop will be generated. */ | |
5069 | } | |
4d7206a2 RS |
5070 | else if (offset_expr.X_add_number >= -0x8000 |
5071 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5072 | { |
67c0d1eb | 5073 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5074 | load_delay_nop (); |
67c0d1eb | 5075 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5076 | } |
5077 | else | |
5078 | { | |
4d7206a2 RS |
5079 | expr1.X_add_number = offset_expr.X_add_number; |
5080 | offset_expr.X_add_number = | |
5081 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5082 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5083 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5084 | /* If we are going to add in a base register, and the |
5085 | target register and the base register are the same, | |
5086 | then we are using AT as a temporary register. Since | |
5087 | we want to load the constant into AT, we add our | |
5088 | current AT (from the global offset table) and the | |
5089 | register into the register now, and pretend we were | |
5090 | not using a base register. */ | |
67c0d1eb | 5091 | if (breg == treg) |
252b5132 | 5092 | { |
269137b2 | 5093 | load_delay_nop (); |
67c0d1eb | 5094 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5095 | treg, AT, breg); |
252b5132 RH |
5096 | breg = 0; |
5097 | tempreg = treg; | |
252b5132 | 5098 | } |
f6a22291 | 5099 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5100 | used_at = 1; |
5101 | } | |
5102 | } | |
f5040a92 AO |
5103 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5104 | { | |
67c0d1eb | 5105 | int add_breg_early = 0; |
f5040a92 AO |
5106 | |
5107 | /* If this is a reference to an external, and there is no | |
5108 | constant, or local symbol (*), with or without a | |
5109 | constant, we want | |
5110 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5111 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5112 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5113 | ||
5114 | If we have a small constant, and this is a reference to | |
5115 | an external symbol, we want | |
5116 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5117 | addiu $tempreg,$tempreg,<constant> | |
5118 | ||
5119 | If we have a large constant, and this is a reference to | |
5120 | an external symbol, we want | |
5121 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5122 | lui $at,<hiconstant> | |
5123 | addiu $at,$at,<loconstant> | |
5124 | addu $tempreg,$tempreg,$at | |
5125 | ||
5126 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5127 | local symbols, even though it introduces an additional | |
5128 | instruction. */ | |
5129 | ||
f5040a92 AO |
5130 | if (offset_expr.X_add_number) |
5131 | { | |
4d7206a2 | 5132 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5133 | offset_expr.X_add_number = 0; |
5134 | ||
4d7206a2 | 5135 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5136 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5137 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5138 | |
5139 | if (expr1.X_add_number >= -0x8000 | |
5140 | && expr1.X_add_number < 0x8000) | |
5141 | { | |
67c0d1eb RS |
5142 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5143 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5144 | } |
ecd13cd3 | 5145 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5146 | { |
5147 | int dreg; | |
5148 | ||
5149 | /* If we are going to add in a base register, and the | |
5150 | target register and the base register are the same, | |
5151 | then we are using AT as a temporary register. Since | |
5152 | we want to load the constant into AT, we add our | |
5153 | current AT (from the global offset table) and the | |
5154 | register into the register now, and pretend we were | |
5155 | not using a base register. */ | |
5156 | if (breg != treg) | |
5157 | dreg = tempreg; | |
5158 | else | |
5159 | { | |
5160 | assert (tempreg == AT); | |
67c0d1eb RS |
5161 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5162 | treg, AT, breg); | |
f5040a92 | 5163 | dreg = treg; |
67c0d1eb | 5164 | add_breg_early = 1; |
f5040a92 AO |
5165 | } |
5166 | ||
f6a22291 | 5167 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5168 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5169 | dreg, dreg, AT); |
f5040a92 | 5170 | |
f5040a92 AO |
5171 | used_at = 1; |
5172 | } | |
5173 | else | |
5174 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5175 | ||
4d7206a2 | 5176 | relax_switch (); |
f5040a92 AO |
5177 | offset_expr.X_add_number = expr1.X_add_number; |
5178 | ||
67c0d1eb RS |
5179 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5180 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5181 | if (add_breg_early) | |
f5040a92 | 5182 | { |
67c0d1eb | 5183 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5184 | treg, tempreg, breg); |
f5040a92 AO |
5185 | breg = 0; |
5186 | tempreg = treg; | |
5187 | } | |
4d7206a2 | 5188 | relax_end (); |
f5040a92 | 5189 | } |
4d7206a2 | 5190 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5191 | { |
4d7206a2 | 5192 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5193 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5194 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5195 | relax_switch (); |
67c0d1eb RS |
5196 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5197 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5198 | relax_end (); |
f5040a92 | 5199 | } |
4d7206a2 | 5200 | else |
f5040a92 | 5201 | { |
67c0d1eb RS |
5202 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5203 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5204 | } |
5205 | } | |
5206 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5207 | { |
67c0d1eb | 5208 | int gpdelay; |
9117d219 NC |
5209 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5210 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5211 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5212 | |
5213 | /* This is the large GOT case. If this is a reference to an | |
5214 | external symbol, and there is no constant, we want | |
5215 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5216 | addu $tempreg,$tempreg,$gp | |
5217 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5218 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5219 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5220 | addu $tempreg,$tempreg,$gp | |
5221 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5222 | For a local symbol, we want |
5223 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5224 | nop | |
5225 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5226 | ||
5227 | If we have a small constant, and this is a reference to | |
5228 | an external symbol, we want | |
5229 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5230 | addu $tempreg,$tempreg,$gp | |
5231 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5232 | nop | |
5233 | addiu $tempreg,$tempreg,<constant> | |
5234 | For a local symbol, we want | |
5235 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5236 | nop | |
5237 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5238 | ||
5239 | If we have a large constant, and this is a reference to | |
5240 | an external symbol, we want | |
5241 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5242 | addu $tempreg,$tempreg,$gp | |
5243 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5244 | lui $at,<hiconstant> | |
5245 | addiu $at,$at,<loconstant> | |
5246 | addu $tempreg,$tempreg,$at | |
5247 | For a local symbol, we want | |
5248 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5249 | lui $at,<hiconstant> | |
5250 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5251 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5252 | */ |
438c16b8 | 5253 | |
252b5132 RH |
5254 | expr1.X_add_number = offset_expr.X_add_number; |
5255 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5256 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5257 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5258 | if (expr1.X_add_number == 0 && breg == 0 |
5259 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5260 | { |
5261 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5262 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5263 | } | |
67c0d1eb RS |
5264 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5265 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5266 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5267 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5268 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5269 | if (expr1.X_add_number == 0) |
5270 | { | |
67c0d1eb | 5271 | if (breg != 0) |
252b5132 RH |
5272 | { |
5273 | /* We're going to put in an addu instruction using | |
5274 | tempreg, so we may as well insert the nop right | |
5275 | now. */ | |
269137b2 | 5276 | load_delay_nop (); |
252b5132 | 5277 | } |
252b5132 RH |
5278 | } |
5279 | else if (expr1.X_add_number >= -0x8000 | |
5280 | && expr1.X_add_number < 0x8000) | |
5281 | { | |
269137b2 | 5282 | load_delay_nop (); |
67c0d1eb | 5283 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5284 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5285 | } |
5286 | else | |
5287 | { | |
67c0d1eb | 5288 | int dreg; |
252b5132 RH |
5289 | |
5290 | /* If we are going to add in a base register, and the | |
5291 | target register and the base register are the same, | |
5292 | then we are using AT as a temporary register. Since | |
5293 | we want to load the constant into AT, we add our | |
5294 | current AT (from the global offset table) and the | |
5295 | register into the register now, and pretend we were | |
5296 | not using a base register. */ | |
5297 | if (breg != treg) | |
67c0d1eb | 5298 | dreg = tempreg; |
252b5132 RH |
5299 | else |
5300 | { | |
5301 | assert (tempreg == AT); | |
269137b2 | 5302 | load_delay_nop (); |
67c0d1eb | 5303 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5304 | treg, AT, breg); |
252b5132 | 5305 | dreg = treg; |
252b5132 RH |
5306 | } |
5307 | ||
f6a22291 | 5308 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5309 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5310 | |
252b5132 RH |
5311 | used_at = 1; |
5312 | } | |
4d7206a2 RS |
5313 | offset_expr.X_add_number = |
5314 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5315 | relax_switch (); | |
252b5132 | 5316 | |
67c0d1eb | 5317 | if (gpdelay) |
252b5132 RH |
5318 | { |
5319 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5320 | the first instruction on the main stream does not. */ |
67c0d1eb | 5321 | macro_build (NULL, "nop", ""); |
252b5132 | 5322 | } |
ed6fb7bd | 5323 | |
67c0d1eb RS |
5324 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5325 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5326 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5327 | && expr1.X_add_number < 0x8000) |
5328 | { | |
269137b2 | 5329 | load_delay_nop (); |
67c0d1eb RS |
5330 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5331 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5332 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5333 | register, the external symbol case ended with a load, |
5334 | so if the symbol turns out to not be external, and | |
5335 | the next instruction uses tempreg, an unnecessary nop | |
5336 | will be inserted. */ | |
252b5132 RH |
5337 | } |
5338 | else | |
5339 | { | |
5340 | if (breg == treg) | |
5341 | { | |
5342 | /* We must add in the base register now, as in the | |
f5040a92 | 5343 | external symbol case. */ |
252b5132 | 5344 | assert (tempreg == AT); |
269137b2 | 5345 | load_delay_nop (); |
67c0d1eb | 5346 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5347 | treg, AT, breg); |
252b5132 RH |
5348 | tempreg = treg; |
5349 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5350 | it in in both cases. */ |
252b5132 RH |
5351 | breg = 0; |
5352 | } | |
5353 | ||
67c0d1eb RS |
5354 | macro_build_lui (&expr1, AT); |
5355 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5356 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5357 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5358 | tempreg, tempreg, AT); |
252b5132 | 5359 | } |
4d7206a2 | 5360 | relax_end (); |
252b5132 | 5361 | } |
f5040a92 AO |
5362 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5363 | { | |
f5040a92 AO |
5364 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5365 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5366 | int add_breg_early = 0; |
f5040a92 AO |
5367 | |
5368 | /* This is the large GOT case. If this is a reference to an | |
5369 | external symbol, and there is no constant, we want | |
5370 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5371 | add $tempreg,$tempreg,$gp | |
5372 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5373 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5374 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5375 | add $tempreg,$tempreg,$gp | |
5376 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5377 | ||
5378 | If we have a small constant, and this is a reference to | |
5379 | an external symbol, we want | |
5380 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5381 | add $tempreg,$tempreg,$gp | |
5382 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5383 | addi $tempreg,$tempreg,<constant> | |
5384 | ||
5385 | If we have a large constant, and this is a reference to | |
5386 | an external symbol, we want | |
5387 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5388 | addu $tempreg,$tempreg,$gp | |
5389 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5390 | lui $at,<hiconstant> | |
5391 | addi $at,$at,<loconstant> | |
5392 | add $tempreg,$tempreg,$at | |
5393 | ||
5394 | If we have NewABI, and we know it's a local symbol, we want | |
5395 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5396 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5397 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5398 | ||
4d7206a2 | 5399 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5400 | |
4d7206a2 | 5401 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5402 | offset_expr.X_add_number = 0; |
5403 | ||
1abe91b1 MR |
5404 | if (expr1.X_add_number == 0 && breg == 0 |
5405 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5406 | { |
5407 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5408 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5409 | } | |
67c0d1eb RS |
5410 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5411 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5412 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5413 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5414 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5415 | |
5416 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5417 | ; |
f5040a92 AO |
5418 | else if (expr1.X_add_number >= -0x8000 |
5419 | && expr1.X_add_number < 0x8000) | |
5420 | { | |
67c0d1eb | 5421 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5422 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5423 | } |
ecd13cd3 | 5424 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5425 | { |
5426 | int dreg; | |
5427 | ||
5428 | /* If we are going to add in a base register, and the | |
5429 | target register and the base register are the same, | |
5430 | then we are using AT as a temporary register. Since | |
5431 | we want to load the constant into AT, we add our | |
5432 | current AT (from the global offset table) and the | |
5433 | register into the register now, and pretend we were | |
5434 | not using a base register. */ | |
5435 | if (breg != treg) | |
5436 | dreg = tempreg; | |
5437 | else | |
5438 | { | |
5439 | assert (tempreg == AT); | |
67c0d1eb | 5440 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5441 | treg, AT, breg); |
f5040a92 | 5442 | dreg = treg; |
67c0d1eb | 5443 | add_breg_early = 1; |
f5040a92 AO |
5444 | } |
5445 | ||
f6a22291 | 5446 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5447 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5448 | |
f5040a92 AO |
5449 | used_at = 1; |
5450 | } | |
5451 | else | |
5452 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5453 | ||
4d7206a2 | 5454 | relax_switch (); |
f5040a92 | 5455 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5456 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5457 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5458 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5459 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5460 | if (add_breg_early) | |
f5040a92 | 5461 | { |
67c0d1eb | 5462 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5463 | treg, tempreg, breg); |
f5040a92 AO |
5464 | breg = 0; |
5465 | tempreg = treg; | |
5466 | } | |
4d7206a2 | 5467 | relax_end (); |
f5040a92 | 5468 | } |
252b5132 RH |
5469 | else |
5470 | abort (); | |
5471 | ||
5472 | if (breg != 0) | |
4d34fb5f TS |
5473 | { |
5474 | char *s; | |
5475 | ||
3e722fb5 | 5476 | if (mips_pic == NO_PIC) |
b7c7d6c1 | 5477 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5478 | else |
f899b4b8 | 5479 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5480 | |
67c0d1eb | 5481 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5482 | } |
252b5132 | 5483 | |
b8285c27 | 5484 | if (!used_at) |
252b5132 RH |
5485 | return; |
5486 | ||
5487 | break; | |
5488 | ||
5489 | case M_J_A: | |
5490 | /* The j instruction may not be used in PIC code, since it | |
5491 | requires an absolute address. We convert it to a b | |
5492 | instruction. */ | |
5493 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5494 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5495 | else |
67c0d1eb | 5496 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5497 | return; |
5498 | ||
5499 | /* The jal instructions must be handled as macros because when | |
5500 | generating PIC code they expand to multi-instruction | |
5501 | sequences. Normally they are simple instructions. */ | |
5502 | case M_JAL_1: | |
5503 | dreg = RA; | |
5504 | /* Fall through. */ | |
5505 | case M_JAL_2: | |
3e722fb5 | 5506 | if (mips_pic == NO_PIC) |
67c0d1eb | 5507 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5508 | else if (mips_pic == SVR4_PIC) |
5509 | { | |
5510 | if (sreg != PIC_CALL_REG) | |
5511 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5512 | |
67c0d1eb | 5513 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5514 | if (! HAVE_NEWABI) |
252b5132 | 5515 | { |
6478892d TS |
5516 | if (mips_cprestore_offset < 0) |
5517 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5518 | else | |
5519 | { | |
7a621144 DJ |
5520 | if (! mips_frame_reg_valid) |
5521 | { | |
5522 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5523 | /* Quiet this warning. */ | |
5524 | mips_frame_reg_valid = 1; | |
5525 | } | |
5526 | if (! mips_cprestore_valid) | |
5527 | { | |
5528 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5529 | /* Quiet this warning. */ | |
5530 | mips_cprestore_valid = 1; | |
5531 | } | |
6478892d | 5532 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5533 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5534 | mips_gp_register, |
256ab948 TS |
5535 | mips_frame_reg, |
5536 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5537 | } |
252b5132 RH |
5538 | } |
5539 | } | |
5540 | else | |
5541 | abort (); | |
5542 | ||
5543 | return; | |
5544 | ||
5545 | case M_JAL_A: | |
5546 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5547 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5548 | else if (mips_pic == SVR4_PIC) |
5549 | { | |
5550 | /* If this is a reference to an external symbol, and we are | |
5551 | using a small GOT, we want | |
5552 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5553 | nop | |
f9419b05 | 5554 | jalr $ra,$25 |
252b5132 RH |
5555 | nop |
5556 | lw $gp,cprestore($sp) | |
5557 | The cprestore value is set using the .cprestore | |
5558 | pseudo-op. If we are using a big GOT, we want | |
5559 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5560 | addu $25,$25,$gp | |
5561 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5562 | nop | |
f9419b05 | 5563 | jalr $ra,$25 |
252b5132 RH |
5564 | nop |
5565 | lw $gp,cprestore($sp) | |
5566 | If the symbol is not external, we want | |
5567 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5568 | nop | |
5569 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5570 | jalr $ra,$25 |
252b5132 | 5571 | nop |
438c16b8 | 5572 | lw $gp,cprestore($sp) |
f5040a92 AO |
5573 | |
5574 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5575 | sequences above, minus nops, unless the symbol is local, | |
5576 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5577 | GOT_DISP. */ | |
438c16b8 | 5578 | if (HAVE_NEWABI) |
252b5132 | 5579 | { |
f5040a92 AO |
5580 | if (! mips_big_got) |
5581 | { | |
4d7206a2 | 5582 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5583 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5584 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5585 | mips_gp_register); |
4d7206a2 | 5586 | relax_switch (); |
67c0d1eb RS |
5587 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5588 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5589 | mips_gp_register); |
5590 | relax_end (); | |
f5040a92 AO |
5591 | } |
5592 | else | |
5593 | { | |
4d7206a2 | 5594 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5595 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5596 | BFD_RELOC_MIPS_CALL_HI16); | |
5597 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5598 | PIC_CALL_REG, mips_gp_register); | |
5599 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5600 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5601 | PIC_CALL_REG); | |
4d7206a2 | 5602 | relax_switch (); |
67c0d1eb RS |
5603 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5604 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5605 | mips_gp_register); | |
5606 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5607 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5608 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5609 | relax_end (); |
f5040a92 | 5610 | } |
684022ea | 5611 | |
67c0d1eb | 5612 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5613 | } |
5614 | else | |
5615 | { | |
4d7206a2 | 5616 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5617 | if (! mips_big_got) |
5618 | { | |
67c0d1eb RS |
5619 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5620 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5621 | mips_gp_register); |
269137b2 | 5622 | load_delay_nop (); |
4d7206a2 | 5623 | relax_switch (); |
438c16b8 | 5624 | } |
252b5132 | 5625 | else |
252b5132 | 5626 | { |
67c0d1eb RS |
5627 | int gpdelay; |
5628 | ||
5629 | gpdelay = reg_needs_delay (mips_gp_register); | |
5630 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5631 | BFD_RELOC_MIPS_CALL_HI16); | |
5632 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5633 | PIC_CALL_REG, mips_gp_register); | |
5634 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5635 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5636 | PIC_CALL_REG); | |
269137b2 | 5637 | load_delay_nop (); |
4d7206a2 | 5638 | relax_switch (); |
67c0d1eb RS |
5639 | if (gpdelay) |
5640 | macro_build (NULL, "nop", ""); | |
252b5132 | 5641 | } |
67c0d1eb RS |
5642 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5643 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5644 | mips_gp_register); |
269137b2 | 5645 | load_delay_nop (); |
67c0d1eb RS |
5646 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5647 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5648 | relax_end (); |
67c0d1eb | 5649 | macro_build_jalr (&offset_expr); |
438c16b8 | 5650 | |
6478892d TS |
5651 | if (mips_cprestore_offset < 0) |
5652 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5653 | else | |
5654 | { | |
7a621144 DJ |
5655 | if (! mips_frame_reg_valid) |
5656 | { | |
5657 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5658 | /* Quiet this warning. */ | |
5659 | mips_frame_reg_valid = 1; | |
5660 | } | |
5661 | if (! mips_cprestore_valid) | |
5662 | { | |
5663 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5664 | /* Quiet this warning. */ | |
5665 | mips_cprestore_valid = 1; | |
5666 | } | |
6478892d | 5667 | if (mips_opts.noreorder) |
67c0d1eb | 5668 | macro_build (NULL, "nop", ""); |
6478892d | 5669 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5670 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5671 | mips_gp_register, |
256ab948 TS |
5672 | mips_frame_reg, |
5673 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5674 | } |
252b5132 RH |
5675 | } |
5676 | } | |
252b5132 RH |
5677 | else |
5678 | abort (); | |
5679 | ||
5680 | return; | |
5681 | ||
5682 | case M_LB_AB: | |
5683 | s = "lb"; | |
5684 | goto ld; | |
5685 | case M_LBU_AB: | |
5686 | s = "lbu"; | |
5687 | goto ld; | |
5688 | case M_LH_AB: | |
5689 | s = "lh"; | |
5690 | goto ld; | |
5691 | case M_LHU_AB: | |
5692 | s = "lhu"; | |
5693 | goto ld; | |
5694 | case M_LW_AB: | |
5695 | s = "lw"; | |
5696 | goto ld; | |
5697 | case M_LWC0_AB: | |
5698 | s = "lwc0"; | |
bdaaa2e1 | 5699 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5700 | coproc = 1; |
5701 | goto ld; | |
5702 | case M_LWC1_AB: | |
5703 | s = "lwc1"; | |
bdaaa2e1 | 5704 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5705 | coproc = 1; |
5706 | goto ld; | |
5707 | case M_LWC2_AB: | |
5708 | s = "lwc2"; | |
bdaaa2e1 | 5709 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5710 | coproc = 1; |
5711 | goto ld; | |
5712 | case M_LWC3_AB: | |
5713 | s = "lwc3"; | |
bdaaa2e1 | 5714 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5715 | coproc = 1; |
5716 | goto ld; | |
5717 | case M_LWL_AB: | |
5718 | s = "lwl"; | |
5719 | lr = 1; | |
5720 | goto ld; | |
5721 | case M_LWR_AB: | |
5722 | s = "lwr"; | |
5723 | lr = 1; | |
5724 | goto ld; | |
5725 | case M_LDC1_AB: | |
fef14a42 | 5726 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5727 | { |
5728 | as_bad (_("opcode not supported on this processor")); | |
5729 | return; | |
5730 | } | |
5731 | s = "ldc1"; | |
bdaaa2e1 | 5732 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5733 | coproc = 1; |
5734 | goto ld; | |
5735 | case M_LDC2_AB: | |
5736 | s = "ldc2"; | |
bdaaa2e1 | 5737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5738 | coproc = 1; |
5739 | goto ld; | |
5740 | case M_LDC3_AB: | |
5741 | s = "ldc3"; | |
bdaaa2e1 | 5742 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5743 | coproc = 1; |
5744 | goto ld; | |
5745 | case M_LDL_AB: | |
5746 | s = "ldl"; | |
5747 | lr = 1; | |
5748 | goto ld; | |
5749 | case M_LDR_AB: | |
5750 | s = "ldr"; | |
5751 | lr = 1; | |
5752 | goto ld; | |
5753 | case M_LL_AB: | |
5754 | s = "ll"; | |
5755 | goto ld; | |
5756 | case M_LLD_AB: | |
5757 | s = "lld"; | |
5758 | goto ld; | |
5759 | case M_LWU_AB: | |
5760 | s = "lwu"; | |
5761 | ld: | |
b8285c27 TS |
5762 | /* XXX Why don't we try to use AT for all expansions? */ |
5763 | if (!mips_opts.noat && (breg == treg || coproc || lr)) | |
252b5132 RH |
5764 | { |
5765 | tempreg = AT; | |
5766 | used_at = 1; | |
5767 | } | |
b8285c27 TS |
5768 | else if (breg == treg |
5769 | && (offset_expr.X_op != O_constant | |
5770 | || (offset_expr.X_add_number > 0x7fff | |
5771 | || offset_expr.X_add_number < -0x8000))) | |
5772 | { | |
5773 | as_bad(_("load expansion needs $at register")); | |
5774 | } | |
252b5132 RH |
5775 | else |
5776 | { | |
5777 | tempreg = treg; | |
5778 | used_at = 0; | |
5779 | } | |
5780 | goto ld_st; | |
5781 | case M_SB_AB: | |
5782 | s = "sb"; | |
5783 | goto st; | |
5784 | case M_SH_AB: | |
5785 | s = "sh"; | |
5786 | goto st; | |
5787 | case M_SW_AB: | |
5788 | s = "sw"; | |
5789 | goto st; | |
5790 | case M_SWC0_AB: | |
5791 | s = "swc0"; | |
bdaaa2e1 | 5792 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5793 | coproc = 1; |
5794 | goto st; | |
5795 | case M_SWC1_AB: | |
5796 | s = "swc1"; | |
bdaaa2e1 | 5797 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5798 | coproc = 1; |
5799 | goto st; | |
5800 | case M_SWC2_AB: | |
5801 | s = "swc2"; | |
bdaaa2e1 | 5802 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5803 | coproc = 1; |
5804 | goto st; | |
5805 | case M_SWC3_AB: | |
5806 | s = "swc3"; | |
bdaaa2e1 | 5807 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5808 | coproc = 1; |
5809 | goto st; | |
5810 | case M_SWL_AB: | |
5811 | s = "swl"; | |
5812 | goto st; | |
5813 | case M_SWR_AB: | |
5814 | s = "swr"; | |
5815 | goto st; | |
5816 | case M_SC_AB: | |
5817 | s = "sc"; | |
5818 | goto st; | |
5819 | case M_SCD_AB: | |
5820 | s = "scd"; | |
5821 | goto st; | |
5822 | case M_SDC1_AB: | |
fef14a42 | 5823 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5824 | { |
5825 | as_bad (_("opcode not supported on this processor")); | |
5826 | return; | |
5827 | } | |
5828 | s = "sdc1"; | |
5829 | coproc = 1; | |
bdaaa2e1 | 5830 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5831 | goto st; |
5832 | case M_SDC2_AB: | |
5833 | s = "sdc2"; | |
bdaaa2e1 | 5834 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5835 | coproc = 1; |
5836 | goto st; | |
5837 | case M_SDC3_AB: | |
5838 | s = "sdc3"; | |
bdaaa2e1 | 5839 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5840 | coproc = 1; |
5841 | goto st; | |
5842 | case M_SDL_AB: | |
5843 | s = "sdl"; | |
5844 | goto st; | |
5845 | case M_SDR_AB: | |
5846 | s = "sdr"; | |
5847 | st: | |
b8285c27 TS |
5848 | if (!mips_opts.noat) |
5849 | { | |
5850 | tempreg = AT; | |
5851 | used_at = 1; | |
5852 | } | |
5853 | else if (breg == treg | |
5854 | && (offset_expr.X_op != O_constant | |
5855 | || (offset_expr.X_add_number > 0x7fff | |
5856 | || offset_expr.X_add_number < -0x8000))) | |
5857 | { | |
5858 | as_bad(_("store expansion needs $at register")); | |
5859 | } | |
5860 | else | |
5861 | { | |
5862 | tempreg = treg; | |
5863 | used_at = 0; | |
5864 | } | |
252b5132 | 5865 | ld_st: |
bdaaa2e1 | 5866 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5867 | if (mask == M_LWC1_AB |
5868 | || mask == M_SWC1_AB | |
5869 | || mask == M_LDC1_AB | |
5870 | || mask == M_SDC1_AB | |
5871 | || mask == M_L_DAB | |
5872 | || mask == M_S_DAB) | |
5873 | fmt = "T,o(b)"; | |
5874 | else if (coproc) | |
5875 | fmt = "E,o(b)"; | |
5876 | else | |
5877 | fmt = "t,o(b)"; | |
5878 | ||
256ab948 TS |
5879 | /* Sign-extending 32-bit constants makes their handling easier. |
5880 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5881 | described below. */ | |
5882 | if ((! HAVE_64BIT_ADDRESSES | |
5883 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5884 | && (offset_expr.X_op == O_constant) |
5885 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5886 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5887 | { |
d17e7bce | 5888 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5889 | as_bad (_("constant too large")); |
ae826530 | 5890 | |
1b8e29e5 TS |
5891 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5892 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5893 | } |
256ab948 | 5894 | |
252b5132 RH |
5895 | if (offset_expr.X_op != O_constant |
5896 | && offset_expr.X_op != O_symbol) | |
5897 | { | |
5898 | as_bad (_("expression too complex")); | |
5899 | offset_expr.X_op = O_constant; | |
5900 | } | |
5901 | ||
5902 | /* A constant expression in PIC code can be handled just as it | |
5903 | is in non PIC code. */ | |
5904 | if (mips_pic == NO_PIC | |
5905 | || offset_expr.X_op == O_constant) | |
5906 | { | |
5907 | /* If this is a reference to a GP relative symbol, and there | |
5908 | is no base register, we want | |
cdf6fd85 | 5909 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5910 | Otherwise, if there is no base register, we want |
5911 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5912 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5913 | If we have a constant, we need two instructions anyhow, | |
5914 | so we always use the latter form. | |
5915 | ||
5916 | If we have a base register, and this is a reference to a | |
5917 | GP relative symbol, we want | |
5918 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5919 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5920 | Otherwise we want |
5921 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5922 | addu $tempreg,$tempreg,$breg | |
5923 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5924 | With a constant we always use the latter case. |
76b3015f | 5925 | |
d6bc6245 TS |
5926 | With 64bit address space and no base register and $at usable, |
5927 | we want | |
5928 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5929 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5930 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5931 | dsll32 $tempreg,0 | |
5932 | daddu $tempreg,$at | |
5933 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5934 | If we have a base register, we want | |
5935 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5936 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5937 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5938 | daddu $at,$breg | |
5939 | dsll32 $tempreg,0 | |
5940 | daddu $tempreg,$at | |
5941 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5942 | ||
5943 | Without $at we can't generate the optimal path for superscalar | |
5944 | processors here since this would require two temporary registers. | |
5945 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5946 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5947 | dsll $tempreg,16 | |
5948 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5949 | dsll $tempreg,16 | |
5950 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5951 | If we have a base register, we want | |
5952 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5953 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5954 | dsll $tempreg,16 | |
5955 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5956 | dsll $tempreg,16 | |
5957 | daddu $tempreg,$tempreg,$breg | |
5958 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5959 | |
5960 | If we have 64-bit addresses, as an optimization, for | |
5961 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5962 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5963 | mechanism since it is more efficient. Note that due to |
5964 | the signed offset used by memory operations, the 32-bit | |
5965 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5966 | probably attempt to generate 64-bit constants more |
5967 | efficiently in general. | |
9214dd3b AO |
5968 | |
5969 | As an extension for architectures with 64-bit registers, | |
5970 | we don't truncate 64-bit addresses given as literal | |
5971 | constants down to 32 bits, to support existing practice | |
5972 | in the mips64 Linux (the kernel), that compiles source | |
5973 | files with -mabi=64, assembling them as o32 or n32 (with | |
5974 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5975 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 5976 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
5977 | wasteful to compute the upper 32 bits of every |
5978 | non-literal address, that takes more space and time. | |
5979 | Some day this should probably be implemented as an | |
5980 | assembler option, such that the kernel doesn't have to | |
5981 | use such ugly hacks, even though it will still have to | |
5982 | end up converting the binary to ELF32 for a number of | |
5983 | platforms whose boot loaders don't support ELF64 | |
5984 | binaries. */ | |
256ab948 TS |
5985 | if ((HAVE_64BIT_ADDRESSES |
5986 | && ! (offset_expr.X_op == O_constant | |
5987 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5988 | || (HAVE_64BIT_GPRS | |
5989 | && offset_expr.X_op == O_constant | |
5990 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 5991 | { |
e864ceca RS |
5992 | /* ??? We don't provide a GP-relative alternative for |
5993 | these macros. It used not to be possible with the | |
5994 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 5995 | |
b8285c27 | 5996 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5997 | { |
67c0d1eb RS |
5998 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5999 | BFD_RELOC_MIPS_HIGHEST); | |
6000 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6001 | BFD_RELOC_HI16_S); | |
6002 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6003 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6004 | if (breg != 0) |
67c0d1eb RS |
6005 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6006 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6007 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6008 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6009 | tempreg); | |
d6bc6245 TS |
6010 | used_at = 1; |
6011 | } | |
6012 | else | |
6013 | { | |
67c0d1eb RS |
6014 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6015 | BFD_RELOC_MIPS_HIGHEST); | |
6016 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6017 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6018 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6019 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6020 | tempreg, BFD_RELOC_HI16_S); | |
6021 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6022 | if (breg != 0) |
67c0d1eb | 6023 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6024 | tempreg, tempreg, breg); |
67c0d1eb | 6025 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6026 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
6027 | } |
6028 | ||
b8285c27 TS |
6029 | if (used_at) |
6030 | break; | |
6031 | ||
d6bc6245 TS |
6032 | return; |
6033 | } | |
256ab948 TS |
6034 | |
6035 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 6036 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6037 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6038 | |
252b5132 RH |
6039 | if (breg == 0) |
6040 | { | |
67c0d1eb RS |
6041 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6042 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6043 | { |
4d7206a2 | 6044 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6045 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6046 | mips_gp_register); | |
4d7206a2 | 6047 | relax_switch (); |
252b5132 | 6048 | } |
67c0d1eb RS |
6049 | macro_build_lui (&offset_expr, tempreg); |
6050 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6051 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6052 | if (mips_relax.sequence) |
6053 | relax_end (); | |
252b5132 RH |
6054 | } |
6055 | else | |
6056 | { | |
67c0d1eb RS |
6057 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6058 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6059 | { |
4d7206a2 | 6060 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6061 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6062 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6063 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6064 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6065 | relax_switch (); |
252b5132 | 6066 | } |
67c0d1eb RS |
6067 | macro_build_lui (&offset_expr, tempreg); |
6068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6069 | tempreg, tempreg, breg); |
67c0d1eb | 6070 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6071 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6072 | if (mips_relax.sequence) |
6073 | relax_end (); | |
252b5132 RH |
6074 | } |
6075 | } | |
6076 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6077 | { | |
ed6fb7bd | 6078 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6079 | |
252b5132 RH |
6080 | /* If this is a reference to an external symbol, we want |
6081 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6082 | nop | |
6083 | <op> $treg,0($tempreg) | |
6084 | Otherwise we want | |
6085 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6086 | nop | |
6087 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6088 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6089 | |
6090 | For NewABI, we want | |
6091 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6092 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6093 | ||
252b5132 RH |
6094 | If there is a base register, we add it to $tempreg before |
6095 | the <op>. If there is a constant, we stick it in the | |
6096 | <op> instruction. We don't handle constants larger than | |
6097 | 16 bits, because we have no way to load the upper 16 bits | |
6098 | (actually, we could handle them for the subset of cases | |
6099 | in which we are not using $at). */ | |
6100 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6101 | if (HAVE_NEWABI) |
6102 | { | |
67c0d1eb RS |
6103 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6104 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6105 | if (breg != 0) |
67c0d1eb | 6106 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6107 | tempreg, tempreg, breg); |
67c0d1eb | 6108 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6109 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 | 6110 | |
b8285c27 | 6111 | if (!used_at) |
f5040a92 AO |
6112 | return; |
6113 | ||
6114 | break; | |
6115 | } | |
252b5132 RH |
6116 | expr1.X_add_number = offset_expr.X_add_number; |
6117 | offset_expr.X_add_number = 0; | |
6118 | if (expr1.X_add_number < -0x8000 | |
6119 | || expr1.X_add_number >= 0x8000) | |
6120 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6121 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6122 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6123 | load_delay_nop (); |
4d7206a2 RS |
6124 | relax_start (offset_expr.X_add_symbol); |
6125 | relax_switch (); | |
67c0d1eb RS |
6126 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6127 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6128 | relax_end (); |
252b5132 | 6129 | if (breg != 0) |
67c0d1eb | 6130 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6131 | tempreg, tempreg, breg); |
67c0d1eb | 6132 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6133 | } |
f5040a92 | 6134 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6135 | { |
67c0d1eb | 6136 | int gpdelay; |
252b5132 RH |
6137 | |
6138 | /* If this is a reference to an external symbol, we want | |
6139 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6140 | addu $tempreg,$tempreg,$gp | |
6141 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6142 | <op> $treg,0($tempreg) | |
6143 | Otherwise we want | |
6144 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6145 | nop | |
6146 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6147 | <op> $treg,0($tempreg) | |
6148 | If there is a base register, we add it to $tempreg before | |
6149 | the <op>. If there is a constant, we stick it in the | |
6150 | <op> instruction. We don't handle constants larger than | |
6151 | 16 bits, because we have no way to load the upper 16 bits | |
6152 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6153 | in which we are not using $at). */ |
252b5132 RH |
6154 | assert (offset_expr.X_op == O_symbol); |
6155 | expr1.X_add_number = offset_expr.X_add_number; | |
6156 | offset_expr.X_add_number = 0; | |
6157 | if (expr1.X_add_number < -0x8000 | |
6158 | || expr1.X_add_number >= 0x8000) | |
6159 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6160 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6161 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6162 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6163 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6164 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6165 | mips_gp_register); | |
6166 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6167 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6168 | relax_switch (); |
67c0d1eb RS |
6169 | if (gpdelay) |
6170 | macro_build (NULL, "nop", ""); | |
6171 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6172 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6173 | load_delay_nop (); |
67c0d1eb RS |
6174 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6175 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6176 | relax_end (); |
6177 | ||
252b5132 | 6178 | if (breg != 0) |
67c0d1eb | 6179 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6180 | tempreg, tempreg, breg); |
67c0d1eb | 6181 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6182 | } |
f5040a92 AO |
6183 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6184 | { | |
f5040a92 AO |
6185 | /* If this is a reference to an external symbol, we want |
6186 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6187 | add $tempreg,$tempreg,$gp | |
6188 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6189 | <op> $treg,<ofst>($tempreg) | |
6190 | Otherwise, for local symbols, we want: | |
6191 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6192 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6193 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6194 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6195 | offset_expr.X_add_number = 0; |
6196 | if (expr1.X_add_number < -0x8000 | |
6197 | || expr1.X_add_number >= 0x8000) | |
6198 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6199 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6200 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6201 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6202 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6203 | mips_gp_register); | |
6204 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6205 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6206 | if (breg != 0) |
67c0d1eb | 6207 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6208 | tempreg, tempreg, breg); |
67c0d1eb | 6209 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6210 | |
4d7206a2 | 6211 | relax_switch (); |
f5040a92 | 6212 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6213 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6214 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6215 | if (breg != 0) |
67c0d1eb | 6216 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6217 | tempreg, tempreg, breg); |
67c0d1eb | 6218 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6219 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6220 | relax_end (); |
f5040a92 | 6221 | } |
252b5132 RH |
6222 | else |
6223 | abort (); | |
6224 | ||
b8285c27 | 6225 | if (!used_at) |
252b5132 RH |
6226 | return; |
6227 | ||
6228 | break; | |
6229 | ||
6230 | case M_LI: | |
6231 | case M_LI_S: | |
67c0d1eb | 6232 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6233 | return; |
6234 | ||
6235 | case M_DLI: | |
67c0d1eb | 6236 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6237 | return; |
6238 | ||
6239 | case M_LI_SS: | |
6240 | if (imm_expr.X_op == O_constant) | |
6241 | { | |
67c0d1eb RS |
6242 | load_register (AT, &imm_expr, 0); |
6243 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6244 | break; |
6245 | } | |
6246 | else | |
6247 | { | |
6248 | assert (offset_expr.X_op == O_symbol | |
6249 | && strcmp (segment_name (S_GET_SEGMENT | |
6250 | (offset_expr.X_add_symbol)), | |
6251 | ".lit4") == 0 | |
6252 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6253 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6254 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6255 | return; |
6256 | } | |
6257 | ||
6258 | case M_LI_D: | |
ca4e0257 RS |
6259 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6260 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6261 | order 32 bits of the value and the low order 32 bits are either | |
6262 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6263 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6264 | { | |
ca4e0257 | 6265 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6266 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6267 | else |
6268 | { | |
6269 | int hreg, lreg; | |
6270 | ||
6271 | if (target_big_endian) | |
6272 | { | |
6273 | hreg = treg; | |
6274 | lreg = treg + 1; | |
6275 | } | |
6276 | else | |
6277 | { | |
6278 | hreg = treg + 1; | |
6279 | lreg = treg; | |
6280 | } | |
6281 | ||
6282 | if (hreg <= 31) | |
67c0d1eb | 6283 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6284 | if (lreg <= 31) |
6285 | { | |
6286 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6287 | move_register (lreg, 0); |
252b5132 RH |
6288 | else |
6289 | { | |
6290 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6291 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6292 | } |
6293 | } | |
6294 | } | |
6295 | return; | |
6296 | } | |
6297 | ||
6298 | /* We know that sym is in the .rdata section. First we get the | |
6299 | upper 16 bits of the address. */ | |
6300 | if (mips_pic == NO_PIC) | |
6301 | { | |
67c0d1eb | 6302 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6303 | } |
6304 | else if (mips_pic == SVR4_PIC) | |
6305 | { | |
67c0d1eb RS |
6306 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6307 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6308 | } |
252b5132 RH |
6309 | else |
6310 | abort (); | |
bdaaa2e1 | 6311 | |
252b5132 | 6312 | /* Now we load the register(s). */ |
ca4e0257 | 6313 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6314 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6315 | else |
6316 | { | |
67c0d1eb | 6317 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6318 | if (treg != RA) |
252b5132 RH |
6319 | { |
6320 | /* FIXME: How in the world do we deal with the possible | |
6321 | overflow here? */ | |
6322 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6323 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6324 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6325 | } |
6326 | } | |
252b5132 RH |
6327 | break; |
6328 | ||
6329 | case M_LI_DD: | |
ca4e0257 RS |
6330 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6331 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6332 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6333 | the value and the low order 32 bits are either zero or in | |
6334 | OFFSET_EXPR. */ | |
252b5132 RH |
6335 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6336 | { | |
67c0d1eb | 6337 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6338 | if (HAVE_64BIT_FPRS) |
6339 | { | |
6340 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6341 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6342 | } |
252b5132 RH |
6343 | else |
6344 | { | |
67c0d1eb | 6345 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6346 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6347 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6348 | else |
6349 | { | |
6350 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6351 | load_register (AT, &offset_expr, 0); |
6352 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6353 | } |
6354 | } | |
6355 | break; | |
6356 | } | |
6357 | ||
6358 | assert (offset_expr.X_op == O_symbol | |
6359 | && offset_expr.X_add_number == 0); | |
6360 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6361 | if (strcmp (s, ".lit8") == 0) | |
6362 | { | |
e7af610e | 6363 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6364 | { |
67c0d1eb | 6365 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6366 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6367 | return; |
6368 | } | |
c9914766 | 6369 | breg = mips_gp_register; |
252b5132 RH |
6370 | r = BFD_RELOC_MIPS_LITERAL; |
6371 | goto dob; | |
6372 | } | |
6373 | else | |
6374 | { | |
6375 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6376 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6377 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6378 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6379 | else |
6380 | { | |
6381 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6382 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6383 | } |
bdaaa2e1 | 6384 | |
e7af610e | 6385 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6386 | { |
67c0d1eb RS |
6387 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6388 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6389 | break; |
6390 | } | |
6391 | breg = AT; | |
6392 | r = BFD_RELOC_LO16; | |
6393 | goto dob; | |
6394 | } | |
6395 | ||
6396 | case M_L_DOB: | |
fef14a42 | 6397 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6398 | { |
6399 | as_bad (_("opcode not supported on this processor")); | |
6400 | return; | |
6401 | } | |
6402 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6403 | to adjust when loading from memory. */ | |
6404 | r = BFD_RELOC_LO16; | |
6405 | dob: | |
e7af610e | 6406 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6407 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6408 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6409 | /* FIXME: A possible overflow which I don't know how to deal |
6410 | with. */ | |
6411 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6412 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6413 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6414 | |
252b5132 RH |
6415 | if (breg != AT) |
6416 | return; | |
6417 | break; | |
6418 | ||
6419 | case M_L_DAB: | |
6420 | /* | |
6421 | * The MIPS assembler seems to check for X_add_number not | |
6422 | * being double aligned and generating: | |
6423 | * lui at,%hi(foo+1) | |
6424 | * addu at,at,v1 | |
6425 | * addiu at,at,%lo(foo+1) | |
6426 | * lwc1 f2,0(at) | |
6427 | * lwc1 f3,4(at) | |
6428 | * But, the resulting address is the same after relocation so why | |
6429 | * generate the extra instruction? | |
6430 | */ | |
fef14a42 | 6431 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6432 | { |
6433 | as_bad (_("opcode not supported on this processor")); | |
6434 | return; | |
6435 | } | |
bdaaa2e1 | 6436 | /* Itbl support may require additional care here. */ |
252b5132 | 6437 | coproc = 1; |
e7af610e | 6438 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6439 | { |
6440 | s = "ldc1"; | |
6441 | goto ld; | |
6442 | } | |
6443 | ||
6444 | s = "lwc1"; | |
6445 | fmt = "T,o(b)"; | |
6446 | goto ldd_std; | |
6447 | ||
6448 | case M_S_DAB: | |
fef14a42 | 6449 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6450 | { |
6451 | as_bad (_("opcode not supported on this processor")); | |
6452 | return; | |
6453 | } | |
6454 | ||
e7af610e | 6455 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6456 | { |
6457 | s = "sdc1"; | |
6458 | goto st; | |
6459 | } | |
6460 | ||
6461 | s = "swc1"; | |
6462 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6463 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6464 | coproc = 1; |
6465 | goto ldd_std; | |
6466 | ||
6467 | case M_LD_AB: | |
ca4e0257 | 6468 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6469 | { |
6470 | s = "ld"; | |
6471 | goto ld; | |
6472 | } | |
6473 | ||
6474 | s = "lw"; | |
6475 | fmt = "t,o(b)"; | |
6476 | goto ldd_std; | |
6477 | ||
6478 | case M_SD_AB: | |
ca4e0257 | 6479 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6480 | { |
6481 | s = "sd"; | |
6482 | goto st; | |
6483 | } | |
6484 | ||
6485 | s = "sw"; | |
6486 | fmt = "t,o(b)"; | |
6487 | ||
6488 | ldd_std: | |
6489 | if (offset_expr.X_op != O_symbol | |
6490 | && offset_expr.X_op != O_constant) | |
6491 | { | |
6492 | as_bad (_("expression too complex")); | |
6493 | offset_expr.X_op = O_constant; | |
6494 | } | |
6495 | ||
6496 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6497 | to adjust when loading from memory. We set coproc if we must | |
6498 | load $fn+1 first. */ | |
bdaaa2e1 | 6499 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6500 | if (! target_big_endian) |
6501 | coproc = 0; | |
6502 | ||
6503 | if (mips_pic == NO_PIC | |
6504 | || offset_expr.X_op == O_constant) | |
6505 | { | |
6506 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6507 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6508 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6509 | If we have a base register, we use this |
6510 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6511 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6512 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6513 | If this is not a GP relative symbol, we want |
6514 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6515 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6516 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6517 | If there is a base register, we add it to $at after the | |
6518 | lui instruction. If there is a constant, we always use | |
6519 | the last case. */ | |
e7d556df | 6520 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6521 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6522 | used_at = 1; |
252b5132 RH |
6523 | else |
6524 | { | |
4d7206a2 | 6525 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6526 | if (breg == 0) |
6527 | { | |
c9914766 | 6528 | tempreg = mips_gp_register; |
252b5132 RH |
6529 | } |
6530 | else | |
6531 | { | |
67c0d1eb | 6532 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6533 | AT, breg, mips_gp_register); |
252b5132 | 6534 | tempreg = AT; |
252b5132 RH |
6535 | used_at = 1; |
6536 | } | |
6537 | ||
beae10d5 | 6538 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6539 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6540 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6541 | offset_expr.X_add_number += 4; |
6542 | ||
6543 | /* Set mips_optimize to 2 to avoid inserting an | |
6544 | undesired nop. */ | |
6545 | hold_mips_optimize = mips_optimize; | |
6546 | mips_optimize = 2; | |
beae10d5 | 6547 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6548 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6549 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6550 | mips_optimize = hold_mips_optimize; |
6551 | ||
4d7206a2 | 6552 | relax_switch (); |
252b5132 RH |
6553 | |
6554 | /* We just generated two relocs. When tc_gen_reloc | |
6555 | handles this case, it will skip the first reloc and | |
6556 | handle the second. The second reloc already has an | |
6557 | extra addend of 4, which we added above. We must | |
6558 | subtract it out, and then subtract another 4 to make | |
6559 | the first reloc come out right. The second reloc | |
6560 | will come out right because we are going to add 4 to | |
6561 | offset_expr when we build its instruction below. | |
6562 | ||
6563 | If we have a symbol, then we don't want to include | |
6564 | the offset, because it will wind up being included | |
6565 | when we generate the reloc. */ | |
6566 | ||
6567 | if (offset_expr.X_op == O_constant) | |
6568 | offset_expr.X_add_number -= 8; | |
6569 | else | |
6570 | { | |
6571 | offset_expr.X_add_number = -4; | |
6572 | offset_expr.X_op = O_constant; | |
6573 | } | |
6574 | } | |
67c0d1eb | 6575 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6576 | if (breg != 0) |
67c0d1eb | 6577 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6578 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6579 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6580 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6581 | /* FIXME: How do we handle overflow here? */ |
6582 | offset_expr.X_add_number += 4; | |
beae10d5 | 6583 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6584 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6585 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6586 | if (mips_relax.sequence) |
6587 | relax_end (); | |
bdaaa2e1 | 6588 | } |
252b5132 RH |
6589 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6590 | { | |
252b5132 RH |
6591 | /* If this is a reference to an external symbol, we want |
6592 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6593 | nop | |
6594 | <op> $treg,0($at) | |
6595 | <op> $treg+1,4($at) | |
6596 | Otherwise we want | |
6597 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6598 | nop | |
6599 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6600 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6601 | If there is a base register we add it to $at before the | |
6602 | lwc1 instructions. If there is a constant we include it | |
6603 | in the lwc1 instructions. */ | |
6604 | used_at = 1; | |
6605 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6606 | if (expr1.X_add_number < -0x8000 |
6607 | || expr1.X_add_number >= 0x8000 - 4) | |
6608 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6609 | load_got_offset (AT, &offset_expr); |
269137b2 | 6610 | load_delay_nop (); |
252b5132 | 6611 | if (breg != 0) |
67c0d1eb | 6612 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6613 | |
6614 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6615 | nop. */ | |
6616 | hold_mips_optimize = mips_optimize; | |
6617 | mips_optimize = 2; | |
4d7206a2 | 6618 | |
beae10d5 | 6619 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6620 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6621 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6622 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6623 | expr1.X_add_number += 4; |
67c0d1eb RS |
6624 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6625 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6626 | relax_switch (); |
67c0d1eb RS |
6627 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6628 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6629 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6630 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6631 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6632 | relax_end (); |
252b5132 | 6633 | |
4d7206a2 | 6634 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6635 | } |
6636 | else if (mips_pic == SVR4_PIC) | |
6637 | { | |
67c0d1eb | 6638 | int gpdelay; |
252b5132 RH |
6639 | |
6640 | /* If this is a reference to an external symbol, we want | |
6641 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6642 | addu $at,$at,$gp | |
6643 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6644 | nop | |
6645 | <op> $treg,0($at) | |
6646 | <op> $treg+1,4($at) | |
6647 | Otherwise we want | |
6648 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6649 | nop | |
6650 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6651 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6652 | If there is a base register we add it to $at before the | |
6653 | lwc1 instructions. If there is a constant we include it | |
6654 | in the lwc1 instructions. */ | |
6655 | used_at = 1; | |
6656 | expr1.X_add_number = offset_expr.X_add_number; | |
6657 | offset_expr.X_add_number = 0; | |
6658 | if (expr1.X_add_number < -0x8000 | |
6659 | || expr1.X_add_number >= 0x8000 - 4) | |
6660 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6661 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6662 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6663 | macro_build (&offset_expr, "lui", "t,u", |
6664 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6665 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6666 | AT, AT, mips_gp_register); |
67c0d1eb | 6667 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6668 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6669 | load_delay_nop (); |
252b5132 | 6670 | if (breg != 0) |
67c0d1eb | 6671 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6672 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6673 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6674 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6675 | expr1.X_add_number += 4; |
6676 | ||
6677 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6678 | nop. */ | |
6679 | hold_mips_optimize = mips_optimize; | |
6680 | mips_optimize = 2; | |
beae10d5 | 6681 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6682 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6683 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6684 | mips_optimize = hold_mips_optimize; |
6685 | expr1.X_add_number -= 4; | |
6686 | ||
4d7206a2 RS |
6687 | relax_switch (); |
6688 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6689 | if (gpdelay) |
6690 | macro_build (NULL, "nop", ""); | |
6691 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6692 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6693 | load_delay_nop (); |
252b5132 | 6694 | if (breg != 0) |
67c0d1eb | 6695 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6696 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6697 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6698 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6699 | offset_expr.X_add_number += 4; |
252b5132 RH |
6700 | |
6701 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6702 | nop. */ | |
6703 | hold_mips_optimize = mips_optimize; | |
6704 | mips_optimize = 2; | |
beae10d5 | 6705 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6706 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6707 | BFD_RELOC_LO16, AT); | |
252b5132 | 6708 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6709 | relax_end (); |
252b5132 | 6710 | } |
252b5132 RH |
6711 | else |
6712 | abort (); | |
6713 | ||
b8285c27 | 6714 | if (!used_at) |
252b5132 RH |
6715 | return; |
6716 | ||
6717 | break; | |
6718 | ||
6719 | case M_LD_OB: | |
6720 | s = "lw"; | |
6721 | goto sd_ob; | |
6722 | case M_SD_OB: | |
6723 | s = "sw"; | |
6724 | sd_ob: | |
ca4e0257 | 6725 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6726 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6727 | offset_expr.X_add_number += 4; |
67c0d1eb | 6728 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6729 | return; |
6730 | ||
6731 | /* New code added to support COPZ instructions. | |
6732 | This code builds table entries out of the macros in mip_opcodes. | |
6733 | R4000 uses interlocks to handle coproc delays. | |
6734 | Other chips (like the R3000) require nops to be inserted for delays. | |
6735 | ||
f72c8c98 | 6736 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6737 | In order to fill delay slots for non-interlocked chips, |
6738 | we must have a way to specify delays based on the coprocessor. | |
6739 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6740 | What are the side-effects of the cop instruction? | |
6741 | What cache support might we have and what are its effects? | |
6742 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6743 | What registers are read/set/modified? |
252b5132 RH |
6744 | |
6745 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6746 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6747 | |
6748 | case M_COP0: | |
6749 | s = "c0"; | |
6750 | goto copz; | |
6751 | case M_COP1: | |
6752 | s = "c1"; | |
6753 | goto copz; | |
6754 | case M_COP2: | |
6755 | s = "c2"; | |
6756 | goto copz; | |
6757 | case M_COP3: | |
6758 | s = "c3"; | |
6759 | copz: | |
6760 | /* For now we just do C (same as Cz). The parameter will be | |
6761 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6762 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6763 | return; |
6764 | ||
ea1fb5dc | 6765 | case M_MOVE: |
67c0d1eb | 6766 | move_register (dreg, sreg); |
ea1fb5dc RS |
6767 | return; |
6768 | ||
252b5132 RH |
6769 | #ifdef LOSING_COMPILER |
6770 | default: | |
6771 | /* Try and see if this is a new itbl instruction. | |
6772 | This code builds table entries out of the macros in mip_opcodes. | |
6773 | FIXME: For now we just assemble the expression and pass it's | |
6774 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6775 | We may want to have the assembler assemble this value, |
252b5132 RH |
6776 | so that we gain the assembler's knowledge of delay slots, |
6777 | symbols, etc. | |
6778 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6779 | if (itbl_have_entries |
252b5132 | 6780 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6781 | { |
252b5132 RH |
6782 | s = ip->insn_mo->name; |
6783 | s2 = "cop3"; | |
6784 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6785 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6786 | return; |
beae10d5 | 6787 | } |
252b5132 RH |
6788 | macro2 (ip); |
6789 | return; | |
6790 | } | |
6791 | if (mips_opts.noat) | |
6792 | as_warn (_("Macro used $at after \".set noat\"")); | |
6793 | } | |
bdaaa2e1 | 6794 | |
252b5132 | 6795 | static void |
17a2f251 | 6796 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6797 | { |
6798 | register int treg, sreg, dreg, breg; | |
6799 | int tempreg; | |
6800 | int mask; | |
252b5132 RH |
6801 | int used_at; |
6802 | expressionS expr1; | |
6803 | const char *s; | |
6804 | const char *s2; | |
6805 | const char *fmt; | |
6806 | int likely = 0; | |
6807 | int dbl = 0; | |
6808 | int coproc = 0; | |
6809 | int lr = 0; | |
6810 | int imm = 0; | |
6811 | int off; | |
6812 | offsetT maxnum; | |
6813 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6814 | |
252b5132 RH |
6815 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6816 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6817 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6818 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6819 | |
252b5132 RH |
6820 | expr1.X_op = O_constant; |
6821 | expr1.X_op_symbol = NULL; | |
6822 | expr1.X_add_symbol = NULL; | |
6823 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6824 | |
252b5132 RH |
6825 | switch (mask) |
6826 | { | |
6827 | #endif /* LOSING_COMPILER */ | |
6828 | ||
6829 | case M_DMUL: | |
6830 | dbl = 1; | |
6831 | case M_MUL: | |
67c0d1eb RS |
6832 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6833 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6834 | return; |
6835 | ||
6836 | case M_DMUL_I: | |
6837 | dbl = 1; | |
6838 | case M_MUL_I: | |
6839 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6840 | not trying to be that fancy. GCC should do this for us | |
6841 | anyway. */ | |
67c0d1eb RS |
6842 | load_register (AT, &imm_expr, dbl); |
6843 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6844 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6845 | break; |
6846 | ||
6847 | case M_DMULO_I: | |
6848 | dbl = 1; | |
6849 | case M_MULO_I: | |
6850 | imm = 1; | |
6851 | goto do_mulo; | |
6852 | ||
6853 | case M_DMULO: | |
6854 | dbl = 1; | |
6855 | case M_MULO: | |
6856 | do_mulo: | |
b34976b6 | 6857 | mips_emit_delays (TRUE); |
252b5132 RH |
6858 | ++mips_opts.noreorder; |
6859 | mips_any_noreorder = 1; | |
6860 | if (imm) | |
67c0d1eb RS |
6861 | load_register (AT, &imm_expr, dbl); |
6862 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6863 | macro_build (NULL, "mflo", "d", dreg); | |
6864 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6865 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6866 | if (mips_trap) |
67c0d1eb | 6867 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6868 | else |
6869 | { | |
6870 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6871 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6872 | macro_build (NULL, "nop", "", 0); | |
6873 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6874 | } |
6875 | --mips_opts.noreorder; | |
67c0d1eb | 6876 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6877 | break; |
6878 | ||
6879 | case M_DMULOU_I: | |
6880 | dbl = 1; | |
6881 | case M_MULOU_I: | |
6882 | imm = 1; | |
6883 | goto do_mulou; | |
6884 | ||
6885 | case M_DMULOU: | |
6886 | dbl = 1; | |
6887 | case M_MULOU: | |
6888 | do_mulou: | |
b34976b6 | 6889 | mips_emit_delays (TRUE); |
252b5132 RH |
6890 | ++mips_opts.noreorder; |
6891 | mips_any_noreorder = 1; | |
6892 | if (imm) | |
67c0d1eb RS |
6893 | load_register (AT, &imm_expr, dbl); |
6894 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6895 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6896 | macro_build (NULL, "mfhi", "d", AT); |
6897 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6898 | if (mips_trap) |
67c0d1eb | 6899 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6900 | else |
6901 | { | |
6902 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6903 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6904 | macro_build (NULL, "nop", "", 0); | |
6905 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6906 | } |
6907 | --mips_opts.noreorder; | |
6908 | break; | |
6909 | ||
771c7ce4 | 6910 | case M_DROL: |
fef14a42 | 6911 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6912 | { |
6913 | if (dreg == sreg) | |
6914 | { | |
6915 | tempreg = AT; | |
6916 | used_at = 1; | |
6917 | } | |
6918 | else | |
6919 | { | |
6920 | tempreg = dreg; | |
82dd0097 | 6921 | } |
67c0d1eb RS |
6922 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6923 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6924 | if (used_at) |
6925 | break; | |
6926 | return; | |
6927 | } | |
67c0d1eb RS |
6928 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6929 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6930 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6931 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6932 | break; |
6933 | ||
252b5132 | 6934 | case M_ROL: |
fef14a42 | 6935 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6936 | { |
6937 | if (dreg == sreg) | |
6938 | { | |
6939 | tempreg = AT; | |
6940 | used_at = 1; | |
6941 | } | |
6942 | else | |
6943 | { | |
6944 | tempreg = dreg; | |
82dd0097 | 6945 | } |
67c0d1eb RS |
6946 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6947 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6948 | if (used_at) |
6949 | break; | |
6950 | return; | |
6951 | } | |
67c0d1eb RS |
6952 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6953 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6954 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6955 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6956 | break; |
6957 | ||
771c7ce4 TS |
6958 | case M_DROL_I: |
6959 | { | |
6960 | unsigned int rot; | |
82dd0097 | 6961 | char *l, *r; |
771c7ce4 TS |
6962 | |
6963 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6964 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6965 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6966 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6967 | { |
6968 | rot = (64 - rot) & 0x3f; | |
6969 | if (rot >= 32) | |
67c0d1eb | 6970 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6971 | else |
67c0d1eb | 6972 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 6973 | return; |
60b63b72 | 6974 | } |
483fc7cd | 6975 | if (rot == 0) |
483fc7cd | 6976 | { |
67c0d1eb | 6977 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6978 | return; |
483fc7cd | 6979 | } |
82dd0097 CD |
6980 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6981 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6982 | rot &= 0x1f; | |
67c0d1eb RS |
6983 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6984 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6985 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6986 | } |
6987 | break; | |
6988 | ||
252b5132 | 6989 | case M_ROL_I: |
771c7ce4 TS |
6990 | { |
6991 | unsigned int rot; | |
6992 | ||
6993 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6994 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6995 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6996 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6997 | { |
67c0d1eb | 6998 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 6999 | return; |
60b63b72 | 7000 | } |
483fc7cd | 7001 | if (rot == 0) |
483fc7cd | 7002 | { |
67c0d1eb | 7003 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7004 | return; |
483fc7cd | 7005 | } |
67c0d1eb RS |
7006 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7007 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7008 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7009 | } |
7010 | break; | |
7011 | ||
7012 | case M_DROR: | |
fef14a42 | 7013 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7014 | { |
67c0d1eb | 7015 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7016 | return; |
7017 | } | |
67c0d1eb RS |
7018 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7019 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7020 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7021 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7022 | break; |
7023 | ||
7024 | case M_ROR: | |
fef14a42 | 7025 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7026 | { |
67c0d1eb | 7027 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7028 | return; |
7029 | } | |
67c0d1eb RS |
7030 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7031 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7032 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7033 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7034 | break; |
7035 | ||
771c7ce4 TS |
7036 | case M_DROR_I: |
7037 | { | |
7038 | unsigned int rot; | |
82dd0097 | 7039 | char *l, *r; |
771c7ce4 TS |
7040 | |
7041 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7042 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7043 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7044 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7045 | { |
7046 | if (rot >= 32) | |
67c0d1eb | 7047 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7048 | else |
67c0d1eb | 7049 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7050 | return; |
7051 | } | |
483fc7cd | 7052 | if (rot == 0) |
483fc7cd | 7053 | { |
67c0d1eb | 7054 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7055 | return; |
483fc7cd | 7056 | } |
82dd0097 CD |
7057 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7058 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7059 | rot &= 0x1f; | |
67c0d1eb RS |
7060 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7061 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7062 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7063 | } |
7064 | break; | |
7065 | ||
252b5132 | 7066 | case M_ROR_I: |
771c7ce4 TS |
7067 | { |
7068 | unsigned int rot; | |
7069 | ||
7070 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7071 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7072 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7073 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7074 | { |
67c0d1eb | 7075 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7076 | return; |
7077 | } | |
483fc7cd | 7078 | if (rot == 0) |
483fc7cd | 7079 | { |
67c0d1eb | 7080 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7081 | return; |
483fc7cd | 7082 | } |
67c0d1eb RS |
7083 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7084 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7085 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7086 | } |
252b5132 RH |
7087 | break; |
7088 | ||
7089 | case M_S_DOB: | |
fef14a42 | 7090 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7091 | { |
7092 | as_bad (_("opcode not supported on this processor")); | |
7093 | return; | |
7094 | } | |
e7af610e | 7095 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7096 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7097 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7098 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7099 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7100 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7101 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7102 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7103 | return; |
7104 | ||
7105 | case M_SEQ: | |
7106 | if (sreg == 0) | |
67c0d1eb | 7107 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7108 | else if (treg == 0) |
67c0d1eb | 7109 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7110 | else |
7111 | { | |
67c0d1eb RS |
7112 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7113 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7114 | } |
7115 | return; | |
7116 | ||
7117 | case M_SEQ_I: | |
7118 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7119 | { | |
67c0d1eb | 7120 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7121 | return; |
7122 | } | |
7123 | if (sreg == 0) | |
7124 | { | |
7125 | as_warn (_("Instruction %s: result is always false"), | |
7126 | ip->insn_mo->name); | |
67c0d1eb | 7127 | move_register (dreg, 0); |
252b5132 RH |
7128 | return; |
7129 | } | |
7130 | if (imm_expr.X_op == O_constant | |
7131 | && imm_expr.X_add_number >= 0 | |
7132 | && imm_expr.X_add_number < 0x10000) | |
7133 | { | |
67c0d1eb | 7134 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7135 | } |
7136 | else if (imm_expr.X_op == O_constant | |
7137 | && imm_expr.X_add_number > -0x8000 | |
7138 | && imm_expr.X_add_number < 0) | |
7139 | { | |
7140 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7141 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7142 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7143 | } |
7144 | else | |
7145 | { | |
67c0d1eb RS |
7146 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7147 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7148 | used_at = 1; |
7149 | } | |
67c0d1eb | 7150 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7151 | if (used_at) |
7152 | break; | |
7153 | return; | |
7154 | ||
7155 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7156 | s = "slt"; | |
7157 | goto sge; | |
7158 | case M_SGEU: | |
7159 | s = "sltu"; | |
7160 | sge: | |
67c0d1eb RS |
7161 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7162 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7163 | return; |
7164 | ||
7165 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7166 | case M_SGEU_I: | |
7167 | if (imm_expr.X_op == O_constant | |
7168 | && imm_expr.X_add_number >= -0x8000 | |
7169 | && imm_expr.X_add_number < 0x8000) | |
7170 | { | |
67c0d1eb RS |
7171 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7172 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7173 | } |
7174 | else | |
7175 | { | |
67c0d1eb RS |
7176 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7177 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7178 | dreg, sreg, AT); | |
252b5132 RH |
7179 | used_at = 1; |
7180 | } | |
67c0d1eb | 7181 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7182 | if (used_at) |
7183 | break; | |
7184 | return; | |
7185 | ||
7186 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7187 | s = "slt"; | |
7188 | goto sgt; | |
7189 | case M_SGTU: | |
7190 | s = "sltu"; | |
7191 | sgt: | |
67c0d1eb | 7192 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7193 | return; |
7194 | ||
7195 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7196 | s = "slt"; | |
7197 | goto sgti; | |
7198 | case M_SGTU_I: | |
7199 | s = "sltu"; | |
7200 | sgti: | |
67c0d1eb RS |
7201 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7202 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7203 | break; |
7204 | ||
2396cfb9 | 7205 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7206 | s = "slt"; |
7207 | goto sle; | |
7208 | case M_SLEU: | |
7209 | s = "sltu"; | |
7210 | sle: | |
67c0d1eb RS |
7211 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7212 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7213 | return; |
7214 | ||
2396cfb9 | 7215 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7216 | s = "slt"; |
7217 | goto slei; | |
7218 | case M_SLEU_I: | |
7219 | s = "sltu"; | |
7220 | slei: | |
67c0d1eb RS |
7221 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7222 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7223 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7224 | break; |
7225 | ||
7226 | case M_SLT_I: | |
7227 | if (imm_expr.X_op == O_constant | |
7228 | && imm_expr.X_add_number >= -0x8000 | |
7229 | && imm_expr.X_add_number < 0x8000) | |
7230 | { | |
67c0d1eb | 7231 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7232 | return; |
7233 | } | |
67c0d1eb RS |
7234 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7235 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7236 | break; |
7237 | ||
7238 | case M_SLTU_I: | |
7239 | if (imm_expr.X_op == O_constant | |
7240 | && imm_expr.X_add_number >= -0x8000 | |
7241 | && imm_expr.X_add_number < 0x8000) | |
7242 | { | |
67c0d1eb | 7243 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7244 | BFD_RELOC_LO16); |
252b5132 RH |
7245 | return; |
7246 | } | |
67c0d1eb RS |
7247 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7248 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7249 | break; |
7250 | ||
7251 | case M_SNE: | |
7252 | if (sreg == 0) | |
67c0d1eb | 7253 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7254 | else if (treg == 0) |
67c0d1eb | 7255 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7256 | else |
7257 | { | |
67c0d1eb RS |
7258 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7259 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7260 | } |
7261 | return; | |
7262 | ||
7263 | case M_SNE_I: | |
7264 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7265 | { | |
67c0d1eb | 7266 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7267 | return; |
7268 | } | |
7269 | if (sreg == 0) | |
7270 | { | |
7271 | as_warn (_("Instruction %s: result is always true"), | |
7272 | ip->insn_mo->name); | |
67c0d1eb RS |
7273 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7274 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7275 | return; |
7276 | } | |
7277 | if (imm_expr.X_op == O_constant | |
7278 | && imm_expr.X_add_number >= 0 | |
7279 | && imm_expr.X_add_number < 0x10000) | |
7280 | { | |
67c0d1eb | 7281 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7282 | } |
7283 | else if (imm_expr.X_op == O_constant | |
7284 | && imm_expr.X_add_number > -0x8000 | |
7285 | && imm_expr.X_add_number < 0) | |
7286 | { | |
7287 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7288 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7289 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7290 | } |
7291 | else | |
7292 | { | |
67c0d1eb RS |
7293 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7294 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7295 | used_at = 1; |
7296 | } | |
67c0d1eb | 7297 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7298 | if (used_at) |
7299 | break; | |
7300 | return; | |
7301 | ||
7302 | case M_DSUB_I: | |
7303 | dbl = 1; | |
7304 | case M_SUB_I: | |
7305 | if (imm_expr.X_op == O_constant | |
7306 | && imm_expr.X_add_number > -0x8000 | |
7307 | && imm_expr.X_add_number <= 0x8000) | |
7308 | { | |
7309 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7310 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7311 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7312 | return; |
7313 | } | |
67c0d1eb RS |
7314 | load_register (AT, &imm_expr, dbl); |
7315 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7316 | break; |
7317 | ||
7318 | case M_DSUBU_I: | |
7319 | dbl = 1; | |
7320 | case M_SUBU_I: | |
7321 | if (imm_expr.X_op == O_constant | |
7322 | && imm_expr.X_add_number > -0x8000 | |
7323 | && imm_expr.X_add_number <= 0x8000) | |
7324 | { | |
7325 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7326 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7327 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7328 | return; |
7329 | } | |
67c0d1eb RS |
7330 | load_register (AT, &imm_expr, dbl); |
7331 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7332 | break; |
7333 | ||
7334 | case M_TEQ_I: | |
7335 | s = "teq"; | |
7336 | goto trap; | |
7337 | case M_TGE_I: | |
7338 | s = "tge"; | |
7339 | goto trap; | |
7340 | case M_TGEU_I: | |
7341 | s = "tgeu"; | |
7342 | goto trap; | |
7343 | case M_TLT_I: | |
7344 | s = "tlt"; | |
7345 | goto trap; | |
7346 | case M_TLTU_I: | |
7347 | s = "tltu"; | |
7348 | goto trap; | |
7349 | case M_TNE_I: | |
7350 | s = "tne"; | |
7351 | trap: | |
67c0d1eb RS |
7352 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7353 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7354 | break; |
7355 | ||
252b5132 | 7356 | case M_TRUNCWS: |
43841e91 | 7357 | case M_TRUNCWD: |
e7af610e | 7358 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7359 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7360 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7361 | ||
7362 | /* | |
7363 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7364 | * or is there a reason for it? | |
7365 | */ | |
b34976b6 | 7366 | mips_emit_delays (TRUE); |
252b5132 RH |
7367 | ++mips_opts.noreorder; |
7368 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7369 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7370 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7371 | macro_build (NULL, "nop", ""); | |
252b5132 | 7372 | expr1.X_add_number = 3; |
67c0d1eb | 7373 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7374 | expr1.X_add_number = 2; |
67c0d1eb RS |
7375 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7376 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7377 | macro_build (NULL, "nop", ""); | |
7378 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7379 | dreg, sreg); | |
7380 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7381 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7382 | --mips_opts.noreorder; |
7383 | break; | |
7384 | ||
7385 | case M_ULH: | |
7386 | s = "lb"; | |
7387 | goto ulh; | |
7388 | case M_ULHU: | |
7389 | s = "lbu"; | |
7390 | ulh: | |
7391 | if (offset_expr.X_add_number >= 0x7fff) | |
7392 | as_bad (_("operand overflow")); | |
252b5132 | 7393 | if (! target_big_endian) |
f9419b05 | 7394 | ++offset_expr.X_add_number; |
67c0d1eb | 7395 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7396 | if (! target_big_endian) |
f9419b05 | 7397 | --offset_expr.X_add_number; |
252b5132 | 7398 | else |
f9419b05 | 7399 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7400 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7401 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7402 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7403 | break; |
7404 | ||
7405 | case M_ULD: | |
7406 | s = "ldl"; | |
7407 | s2 = "ldr"; | |
7408 | off = 7; | |
7409 | goto ulw; | |
7410 | case M_ULW: | |
7411 | s = "lwl"; | |
7412 | s2 = "lwr"; | |
7413 | off = 3; | |
7414 | ulw: | |
7415 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7416 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7417 | if (treg != breg) |
7418 | tempreg = treg; | |
7419 | else | |
7420 | tempreg = AT; | |
252b5132 RH |
7421 | if (! target_big_endian) |
7422 | offset_expr.X_add_number += off; | |
67c0d1eb | 7423 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7424 | if (! target_big_endian) |
7425 | offset_expr.X_add_number -= off; | |
7426 | else | |
7427 | offset_expr.X_add_number += off; | |
67c0d1eb | 7428 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7429 | |
7430 | /* If necessary, move the result in tempreg the final destination. */ | |
7431 | if (treg == tempreg) | |
7432 | return; | |
7433 | /* Protect second load's delay slot. */ | |
017315e4 | 7434 | load_delay_nop (); |
67c0d1eb | 7435 | move_register (treg, tempreg); |
af22f5b2 | 7436 | break; |
252b5132 RH |
7437 | |
7438 | case M_ULD_A: | |
7439 | s = "ldl"; | |
7440 | s2 = "ldr"; | |
7441 | off = 7; | |
7442 | goto ulwa; | |
7443 | case M_ULW_A: | |
7444 | s = "lwl"; | |
7445 | s2 = "lwr"; | |
7446 | off = 3; | |
7447 | ulwa: | |
d6bc6245 | 7448 | used_at = 1; |
67c0d1eb | 7449 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7450 | if (breg != 0) |
67c0d1eb | 7451 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7452 | if (! target_big_endian) |
7453 | expr1.X_add_number = off; | |
7454 | else | |
7455 | expr1.X_add_number = 0; | |
67c0d1eb | 7456 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7457 | if (! target_big_endian) |
7458 | expr1.X_add_number = 0; | |
7459 | else | |
7460 | expr1.X_add_number = off; | |
67c0d1eb | 7461 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7462 | break; |
7463 | ||
7464 | case M_ULH_A: | |
7465 | case M_ULHU_A: | |
d6bc6245 | 7466 | used_at = 1; |
67c0d1eb | 7467 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7468 | if (breg != 0) |
67c0d1eb | 7469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7470 | if (target_big_endian) |
7471 | expr1.X_add_number = 0; | |
67c0d1eb | 7472 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7473 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7474 | if (target_big_endian) |
7475 | expr1.X_add_number = 1; | |
7476 | else | |
7477 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7478 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7479 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7480 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7481 | break; |
7482 | ||
7483 | case M_USH: | |
7484 | if (offset_expr.X_add_number >= 0x7fff) | |
7485 | as_bad (_("operand overflow")); | |
7486 | if (target_big_endian) | |
f9419b05 | 7487 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7488 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7489 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7490 | if (target_big_endian) |
f9419b05 | 7491 | --offset_expr.X_add_number; |
252b5132 | 7492 | else |
f9419b05 | 7493 | ++offset_expr.X_add_number; |
67c0d1eb | 7494 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7495 | break; |
7496 | ||
7497 | case M_USD: | |
7498 | s = "sdl"; | |
7499 | s2 = "sdr"; | |
7500 | off = 7; | |
7501 | goto usw; | |
7502 | case M_USW: | |
7503 | s = "swl"; | |
7504 | s2 = "swr"; | |
7505 | off = 3; | |
7506 | usw: | |
7507 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7508 | as_bad (_("operand overflow")); | |
7509 | if (! target_big_endian) | |
7510 | offset_expr.X_add_number += off; | |
67c0d1eb | 7511 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7512 | if (! target_big_endian) |
7513 | offset_expr.X_add_number -= off; | |
7514 | else | |
7515 | offset_expr.X_add_number += off; | |
67c0d1eb | 7516 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7517 | return; |
7518 | ||
7519 | case M_USD_A: | |
7520 | s = "sdl"; | |
7521 | s2 = "sdr"; | |
7522 | off = 7; | |
7523 | goto uswa; | |
7524 | case M_USW_A: | |
7525 | s = "swl"; | |
7526 | s2 = "swr"; | |
7527 | off = 3; | |
7528 | uswa: | |
d6bc6245 | 7529 | used_at = 1; |
67c0d1eb | 7530 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7531 | if (breg != 0) |
67c0d1eb | 7532 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7533 | if (! target_big_endian) |
7534 | expr1.X_add_number = off; | |
7535 | else | |
7536 | expr1.X_add_number = 0; | |
67c0d1eb | 7537 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7538 | if (! target_big_endian) |
7539 | expr1.X_add_number = 0; | |
7540 | else | |
7541 | expr1.X_add_number = off; | |
67c0d1eb | 7542 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7543 | break; |
7544 | ||
7545 | case M_USH_A: | |
d6bc6245 | 7546 | used_at = 1; |
67c0d1eb | 7547 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7548 | if (breg != 0) |
67c0d1eb | 7549 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7550 | if (! target_big_endian) |
7551 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7552 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7553 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7554 | if (! target_big_endian) |
7555 | expr1.X_add_number = 1; | |
7556 | else | |
7557 | expr1.X_add_number = 0; | |
67c0d1eb | 7558 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7559 | if (! target_big_endian) |
7560 | expr1.X_add_number = 0; | |
7561 | else | |
7562 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7563 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7564 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7565 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7566 | break; |
7567 | ||
7568 | default: | |
7569 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7570 | are added dynamically. */ |
252b5132 RH |
7571 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7572 | break; | |
7573 | } | |
7574 | if (mips_opts.noat) | |
7575 | as_warn (_("Macro used $at after \".set noat\"")); | |
7576 | } | |
7577 | ||
7578 | /* Implement macros in mips16 mode. */ | |
7579 | ||
7580 | static void | |
17a2f251 | 7581 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7582 | { |
7583 | int mask; | |
7584 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7585 | expressionS expr1; |
7586 | int dbl; | |
7587 | const char *s, *s2, *s3; | |
7588 | ||
7589 | mask = ip->insn_mo->mask; | |
7590 | ||
7591 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7592 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7593 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7594 | ||
252b5132 RH |
7595 | expr1.X_op = O_constant; |
7596 | expr1.X_op_symbol = NULL; | |
7597 | expr1.X_add_symbol = NULL; | |
7598 | expr1.X_add_number = 1; | |
7599 | ||
7600 | dbl = 0; | |
7601 | ||
7602 | switch (mask) | |
7603 | { | |
7604 | default: | |
7605 | internalError (); | |
7606 | ||
7607 | case M_DDIV_3: | |
7608 | dbl = 1; | |
7609 | case M_DIV_3: | |
7610 | s = "mflo"; | |
7611 | goto do_div3; | |
7612 | case M_DREM_3: | |
7613 | dbl = 1; | |
7614 | case M_REM_3: | |
7615 | s = "mfhi"; | |
7616 | do_div3: | |
b34976b6 | 7617 | mips_emit_delays (TRUE); |
252b5132 RH |
7618 | ++mips_opts.noreorder; |
7619 | mips_any_noreorder = 1; | |
67c0d1eb | 7620 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7621 | expr1.X_add_number = 2; |
67c0d1eb RS |
7622 | macro_build (&expr1, "bnez", "x,p", yreg); |
7623 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7624 | |
252b5132 RH |
7625 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7626 | since that causes an overflow. We should do that as well, | |
7627 | but I don't see how to do the comparisons without a temporary | |
7628 | register. */ | |
7629 | --mips_opts.noreorder; | |
67c0d1eb | 7630 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7631 | break; |
7632 | ||
7633 | case M_DIVU_3: | |
7634 | s = "divu"; | |
7635 | s2 = "mflo"; | |
7636 | goto do_divu3; | |
7637 | case M_REMU_3: | |
7638 | s = "divu"; | |
7639 | s2 = "mfhi"; | |
7640 | goto do_divu3; | |
7641 | case M_DDIVU_3: | |
7642 | s = "ddivu"; | |
7643 | s2 = "mflo"; | |
7644 | goto do_divu3; | |
7645 | case M_DREMU_3: | |
7646 | s = "ddivu"; | |
7647 | s2 = "mfhi"; | |
7648 | do_divu3: | |
b34976b6 | 7649 | mips_emit_delays (TRUE); |
252b5132 RH |
7650 | ++mips_opts.noreorder; |
7651 | mips_any_noreorder = 1; | |
67c0d1eb | 7652 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7653 | expr1.X_add_number = 2; |
67c0d1eb RS |
7654 | macro_build (&expr1, "bnez", "x,p", yreg); |
7655 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7656 | --mips_opts.noreorder; |
67c0d1eb | 7657 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7658 | break; |
7659 | ||
7660 | case M_DMUL: | |
7661 | dbl = 1; | |
7662 | case M_MUL: | |
67c0d1eb RS |
7663 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7664 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7665 | return; |
7666 | ||
7667 | case M_DSUBU_I: | |
7668 | dbl = 1; | |
7669 | goto do_subu; | |
7670 | case M_SUBU_I: | |
7671 | do_subu: | |
7672 | if (imm_expr.X_op != O_constant) | |
7673 | as_bad (_("Unsupported large constant")); | |
7674 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7675 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7676 | break; |
7677 | ||
7678 | case M_SUBU_I_2: | |
7679 | if (imm_expr.X_op != O_constant) | |
7680 | as_bad (_("Unsupported large constant")); | |
7681 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7682 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7683 | break; |
7684 | ||
7685 | case M_DSUBU_I_2: | |
7686 | if (imm_expr.X_op != O_constant) | |
7687 | as_bad (_("Unsupported large constant")); | |
7688 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7689 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7690 | break; |
7691 | ||
7692 | case M_BEQ: | |
7693 | s = "cmp"; | |
7694 | s2 = "bteqz"; | |
7695 | goto do_branch; | |
7696 | case M_BNE: | |
7697 | s = "cmp"; | |
7698 | s2 = "btnez"; | |
7699 | goto do_branch; | |
7700 | case M_BLT: | |
7701 | s = "slt"; | |
7702 | s2 = "btnez"; | |
7703 | goto do_branch; | |
7704 | case M_BLTU: | |
7705 | s = "sltu"; | |
7706 | s2 = "btnez"; | |
7707 | goto do_branch; | |
7708 | case M_BLE: | |
7709 | s = "slt"; | |
7710 | s2 = "bteqz"; | |
7711 | goto do_reverse_branch; | |
7712 | case M_BLEU: | |
7713 | s = "sltu"; | |
7714 | s2 = "bteqz"; | |
7715 | goto do_reverse_branch; | |
7716 | case M_BGE: | |
7717 | s = "slt"; | |
7718 | s2 = "bteqz"; | |
7719 | goto do_branch; | |
7720 | case M_BGEU: | |
7721 | s = "sltu"; | |
7722 | s2 = "bteqz"; | |
7723 | goto do_branch; | |
7724 | case M_BGT: | |
7725 | s = "slt"; | |
7726 | s2 = "btnez"; | |
7727 | goto do_reverse_branch; | |
7728 | case M_BGTU: | |
7729 | s = "sltu"; | |
7730 | s2 = "btnez"; | |
7731 | ||
7732 | do_reverse_branch: | |
7733 | tmp = xreg; | |
7734 | xreg = yreg; | |
7735 | yreg = tmp; | |
7736 | ||
7737 | do_branch: | |
67c0d1eb RS |
7738 | macro_build (NULL, s, "x,y", xreg, yreg); |
7739 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7740 | break; |
7741 | ||
7742 | case M_BEQ_I: | |
7743 | s = "cmpi"; | |
7744 | s2 = "bteqz"; | |
7745 | s3 = "x,U"; | |
7746 | goto do_branch_i; | |
7747 | case M_BNE_I: | |
7748 | s = "cmpi"; | |
7749 | s2 = "btnez"; | |
7750 | s3 = "x,U"; | |
7751 | goto do_branch_i; | |
7752 | case M_BLT_I: | |
7753 | s = "slti"; | |
7754 | s2 = "btnez"; | |
7755 | s3 = "x,8"; | |
7756 | goto do_branch_i; | |
7757 | case M_BLTU_I: | |
7758 | s = "sltiu"; | |
7759 | s2 = "btnez"; | |
7760 | s3 = "x,8"; | |
7761 | goto do_branch_i; | |
7762 | case M_BLE_I: | |
7763 | s = "slti"; | |
7764 | s2 = "btnez"; | |
7765 | s3 = "x,8"; | |
7766 | goto do_addone_branch_i; | |
7767 | case M_BLEU_I: | |
7768 | s = "sltiu"; | |
7769 | s2 = "btnez"; | |
7770 | s3 = "x,8"; | |
7771 | goto do_addone_branch_i; | |
7772 | case M_BGE_I: | |
7773 | s = "slti"; | |
7774 | s2 = "bteqz"; | |
7775 | s3 = "x,8"; | |
7776 | goto do_branch_i; | |
7777 | case M_BGEU_I: | |
7778 | s = "sltiu"; | |
7779 | s2 = "bteqz"; | |
7780 | s3 = "x,8"; | |
7781 | goto do_branch_i; | |
7782 | case M_BGT_I: | |
7783 | s = "slti"; | |
7784 | s2 = "bteqz"; | |
7785 | s3 = "x,8"; | |
7786 | goto do_addone_branch_i; | |
7787 | case M_BGTU_I: | |
7788 | s = "sltiu"; | |
7789 | s2 = "bteqz"; | |
7790 | s3 = "x,8"; | |
7791 | ||
7792 | do_addone_branch_i: | |
7793 | if (imm_expr.X_op != O_constant) | |
7794 | as_bad (_("Unsupported large constant")); | |
7795 | ++imm_expr.X_add_number; | |
7796 | ||
7797 | do_branch_i: | |
67c0d1eb RS |
7798 | macro_build (&imm_expr, s, s3, xreg); |
7799 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7800 | break; |
7801 | ||
7802 | case M_ABS: | |
7803 | expr1.X_add_number = 0; | |
67c0d1eb | 7804 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7805 | if (xreg != yreg) |
67c0d1eb | 7806 | move_register (xreg, yreg); |
252b5132 | 7807 | expr1.X_add_number = 2; |
67c0d1eb RS |
7808 | macro_build (&expr1, "bteqz", "p"); |
7809 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7810 | } |
7811 | } | |
7812 | ||
7813 | /* For consistency checking, verify that all bits are specified either | |
7814 | by the match/mask part of the instruction definition, or by the | |
7815 | operand list. */ | |
7816 | static int | |
17a2f251 | 7817 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7818 | { |
7819 | const char *p = opc->args; | |
7820 | char c; | |
7821 | unsigned long used_bits = opc->mask; | |
7822 | ||
7823 | if ((used_bits & opc->match) != opc->match) | |
7824 | { | |
7825 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7826 | opc->name, opc->args); | |
7827 | return 0; | |
7828 | } | |
7829 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7830 | while (*p) | |
7831 | switch (c = *p++) | |
7832 | { | |
7833 | case ',': break; | |
7834 | case '(': break; | |
7835 | case ')': break; | |
af7ee8bf CD |
7836 | case '+': |
7837 | switch (c = *p++) | |
7838 | { | |
7839 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7840 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7841 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7842 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7843 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7844 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7845 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7846 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7847 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7848 | case 'I': break; | |
af7ee8bf CD |
7849 | default: |
7850 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7851 | c, opc->name, opc->args); | |
7852 | return 0; | |
7853 | } | |
7854 | break; | |
252b5132 RH |
7855 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7856 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7857 | case 'A': break; | |
4372b673 | 7858 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7859 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7860 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7861 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7862 | case 'F': break; | |
7863 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7864 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7865 | case 'I': break; |
e972090a | 7866 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7867 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7868 | case 'L': break; |
7869 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7870 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7871 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7872 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7873 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7874 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7875 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7876 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7877 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7878 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7879 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7880 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7881 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7882 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7883 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7884 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7885 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7886 | case 'f': break; | |
7887 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7888 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7889 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7890 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7891 | case 'l': break; | |
7892 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7893 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7894 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7895 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7896 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7897 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7898 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7899 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7900 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7901 | case 'x': break; | |
7902 | case 'z': break; | |
7903 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7904 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7905 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7906 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7907 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7908 | case '[': break; | |
7909 | case ']': break; | |
252b5132 RH |
7910 | default: |
7911 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7912 | c, opc->name, opc->args); | |
7913 | return 0; | |
7914 | } | |
7915 | #undef USE_BITS | |
7916 | if (used_bits != 0xffffffff) | |
7917 | { | |
7918 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7919 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7920 | return 0; | |
7921 | } | |
7922 | return 1; | |
7923 | } | |
7924 | ||
7925 | /* This routine assembles an instruction into its binary format. As a | |
7926 | side effect, it sets one of the global variables imm_reloc or | |
7927 | offset_reloc to the type of relocation to do if one of the operands | |
7928 | is an address expression. */ | |
7929 | ||
7930 | static void | |
17a2f251 | 7931 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7932 | { |
7933 | char *s; | |
7934 | const char *args; | |
43841e91 | 7935 | char c = 0; |
252b5132 RH |
7936 | struct mips_opcode *insn; |
7937 | char *argsStart; | |
7938 | unsigned int regno; | |
7939 | unsigned int lastregno = 0; | |
af7ee8bf | 7940 | unsigned int lastpos = 0; |
071742cf | 7941 | unsigned int limlo, limhi; |
252b5132 RH |
7942 | char *s_reset; |
7943 | char save_c = 0; | |
252b5132 RH |
7944 | |
7945 | insn_error = NULL; | |
7946 | ||
7947 | /* If the instruction contains a '.', we first try to match an instruction | |
7948 | including the '.'. Then we try again without the '.'. */ | |
7949 | insn = NULL; | |
3882b010 | 7950 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7951 | continue; |
7952 | ||
7953 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7954 | the call to hash_find. Save the character we replaced just in case we | |
7955 | have to re-parse the instruction. */ | |
3882b010 | 7956 | if (ISSPACE (*s)) |
252b5132 RH |
7957 | { |
7958 | save_c = *s; | |
7959 | *s++ = '\0'; | |
7960 | } | |
bdaaa2e1 | 7961 | |
252b5132 RH |
7962 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7963 | ||
7964 | /* If we didn't find the instruction in the opcode table, try again, but | |
7965 | this time with just the instruction up to, but not including the | |
7966 | first '.'. */ | |
7967 | if (insn == NULL) | |
7968 | { | |
bdaaa2e1 | 7969 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7970 | if (save_c) |
7971 | *(--s) = save_c; | |
7972 | ||
7973 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7974 | for (s = str; |
7975 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7976 | ++s) | |
252b5132 RH |
7977 | continue; |
7978 | ||
7979 | /* If we did not find a '.', then we can quit now. */ | |
7980 | if (*s != '.') | |
7981 | { | |
7982 | insn_error = "unrecognized opcode"; | |
7983 | return; | |
7984 | } | |
7985 | ||
7986 | /* Lookup the instruction in the hash table. */ | |
7987 | *s++ = '\0'; | |
7988 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7989 | { | |
7990 | insn_error = "unrecognized opcode"; | |
7991 | return; | |
7992 | } | |
252b5132 RH |
7993 | } |
7994 | ||
7995 | argsStart = s; | |
7996 | for (;;) | |
7997 | { | |
b34976b6 | 7998 | bfd_boolean ok; |
252b5132 RH |
7999 | |
8000 | assert (strcmp (insn->name, str) == 0); | |
8001 | ||
1f25f5d3 CD |
8002 | if (OPCODE_IS_MEMBER (insn, |
8003 | (mips_opts.isa | |
3396de36 | 8004 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8005 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8006 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8007 | mips_opts.arch)) |
b34976b6 | 8008 | ok = TRUE; |
bdaaa2e1 | 8009 | else |
b34976b6 | 8010 | ok = FALSE; |
bdaaa2e1 | 8011 | |
252b5132 RH |
8012 | if (insn->pinfo != INSN_MACRO) |
8013 | { | |
fef14a42 | 8014 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8015 | ok = FALSE; |
252b5132 RH |
8016 | } |
8017 | ||
8018 | if (! ok) | |
8019 | { | |
8020 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8021 | && strcmp (insn->name, insn[1].name) == 0) | |
8022 | { | |
8023 | ++insn; | |
8024 | continue; | |
8025 | } | |
252b5132 | 8026 | else |
beae10d5 | 8027 | { |
268f6bed L |
8028 | if (!insn_error) |
8029 | { | |
8030 | static char buf[100]; | |
fef14a42 TS |
8031 | sprintf (buf, |
8032 | _("opcode not supported on this processor: %s (%s)"), | |
8033 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8034 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8035 | insn_error = buf; |
8036 | } | |
8037 | if (save_c) | |
8038 | *(--s) = save_c; | |
2bd7f1f3 | 8039 | return; |
252b5132 | 8040 | } |
252b5132 RH |
8041 | } |
8042 | ||
8043 | ip->insn_mo = insn; | |
8044 | ip->insn_opcode = insn->match; | |
268f6bed | 8045 | insn_error = NULL; |
252b5132 RH |
8046 | for (args = insn->args;; ++args) |
8047 | { | |
deec1734 CD |
8048 | int is_mdmx; |
8049 | ||
ad8d3bb3 | 8050 | s += strspn (s, " \t"); |
deec1734 | 8051 | is_mdmx = 0; |
252b5132 RH |
8052 | switch (*args) |
8053 | { | |
8054 | case '\0': /* end of args */ | |
8055 | if (*s == '\0') | |
8056 | return; | |
8057 | break; | |
8058 | ||
8059 | case ',': | |
8060 | if (*s++ == *args) | |
8061 | continue; | |
8062 | s--; | |
8063 | switch (*++args) | |
8064 | { | |
8065 | case 'r': | |
8066 | case 'v': | |
38487616 | 8067 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8068 | continue; |
8069 | ||
8070 | case 'w': | |
38487616 TS |
8071 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8072 | continue; | |
8073 | ||
252b5132 | 8074 | case 'W': |
38487616 | 8075 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8076 | continue; |
8077 | ||
8078 | case 'V': | |
38487616 | 8079 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8080 | continue; |
8081 | } | |
8082 | break; | |
8083 | ||
8084 | case '(': | |
8085 | /* Handle optional base register. | |
8086 | Either the base register is omitted or | |
bdaaa2e1 | 8087 | we must have a left paren. */ |
252b5132 RH |
8088 | /* This is dependent on the next operand specifier |
8089 | is a base register specification. */ | |
8090 | assert (args[1] == 'b' || args[1] == '5' | |
8091 | || args[1] == '-' || args[1] == '4'); | |
8092 | if (*s == '\0') | |
8093 | return; | |
8094 | ||
8095 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8096 | case '[': |
8097 | case ']': | |
252b5132 RH |
8098 | if (*s++ == *args) |
8099 | continue; | |
8100 | break; | |
8101 | ||
af7ee8bf CD |
8102 | case '+': /* Opcode extension character. */ |
8103 | switch (*++args) | |
8104 | { | |
071742cf CD |
8105 | case 'A': /* ins/ext position, becomes LSB. */ |
8106 | limlo = 0; | |
8107 | limhi = 31; | |
5f74bc13 CD |
8108 | goto do_lsb; |
8109 | case 'E': | |
8110 | limlo = 32; | |
8111 | limhi = 63; | |
8112 | goto do_lsb; | |
8113 | do_lsb: | |
071742cf CD |
8114 | my_getExpression (&imm_expr, s); |
8115 | check_absolute_expr (ip, &imm_expr); | |
8116 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8117 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8118 | { | |
8119 | as_bad (_("Improper position (%lu)"), | |
8120 | (unsigned long) imm_expr.X_add_number); | |
8121 | imm_expr.X_add_number = limlo; | |
8122 | } | |
8123 | lastpos = imm_expr.X_add_number; | |
8124 | ip->insn_opcode |= (imm_expr.X_add_number | |
8125 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8126 | imm_expr.X_op = O_absent; | |
8127 | s = expr_end; | |
8128 | continue; | |
8129 | ||
8130 | case 'B': /* ins size, becomes MSB. */ | |
8131 | limlo = 1; | |
8132 | limhi = 32; | |
5f74bc13 CD |
8133 | goto do_msb; |
8134 | case 'F': | |
8135 | limlo = 33; | |
8136 | limhi = 64; | |
8137 | goto do_msb; | |
8138 | do_msb: | |
071742cf CD |
8139 | my_getExpression (&imm_expr, s); |
8140 | check_absolute_expr (ip, &imm_expr); | |
8141 | /* Check for negative input so that small negative numbers | |
8142 | will not succeed incorrectly. The checks against | |
8143 | (pos+size) transitively check "size" itself, | |
8144 | assuming that "pos" is reasonable. */ | |
8145 | if ((long) imm_expr.X_add_number < 0 | |
8146 | || ((unsigned long) imm_expr.X_add_number | |
8147 | + lastpos) < limlo | |
8148 | || ((unsigned long) imm_expr.X_add_number | |
8149 | + lastpos) > limhi) | |
8150 | { | |
8151 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8152 | (unsigned long) imm_expr.X_add_number, | |
8153 | (unsigned long) lastpos); | |
8154 | imm_expr.X_add_number = limlo - lastpos; | |
8155 | } | |
8156 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8157 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8158 | imm_expr.X_op = O_absent; | |
8159 | s = expr_end; | |
8160 | continue; | |
8161 | ||
8162 | case 'C': /* ext size, becomes MSBD. */ | |
8163 | limlo = 1; | |
8164 | limhi = 32; | |
5f74bc13 CD |
8165 | goto do_msbd; |
8166 | case 'G': | |
8167 | limlo = 33; | |
8168 | limhi = 64; | |
8169 | goto do_msbd; | |
8170 | case 'H': | |
8171 | limlo = 33; | |
8172 | limhi = 64; | |
8173 | goto do_msbd; | |
8174 | do_msbd: | |
071742cf CD |
8175 | my_getExpression (&imm_expr, s); |
8176 | check_absolute_expr (ip, &imm_expr); | |
8177 | /* Check for negative input so that small negative numbers | |
8178 | will not succeed incorrectly. The checks against | |
8179 | (pos+size) transitively check "size" itself, | |
8180 | assuming that "pos" is reasonable. */ | |
8181 | if ((long) imm_expr.X_add_number < 0 | |
8182 | || ((unsigned long) imm_expr.X_add_number | |
8183 | + lastpos) < limlo | |
8184 | || ((unsigned long) imm_expr.X_add_number | |
8185 | + lastpos) > limhi) | |
8186 | { | |
8187 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8188 | (unsigned long) imm_expr.X_add_number, | |
8189 | (unsigned long) lastpos); | |
8190 | imm_expr.X_add_number = limlo - lastpos; | |
8191 | } | |
8192 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8193 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8194 | imm_expr.X_op = O_absent; | |
8195 | s = expr_end; | |
8196 | continue; | |
af7ee8bf | 8197 | |
bbcc0807 CD |
8198 | case 'D': |
8199 | /* +D is for disassembly only; never match. */ | |
8200 | break; | |
8201 | ||
5f74bc13 CD |
8202 | case 'I': |
8203 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8204 | my_getExpression (&imm2_expr, s); | |
8205 | if (imm2_expr.X_op != O_big | |
8206 | && imm2_expr.X_op != O_constant) | |
8207 | insn_error = _("absolute expression required"); | |
13757d0c | 8208 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8209 | s = expr_end; |
8210 | continue; | |
8211 | ||
af7ee8bf CD |
8212 | default: |
8213 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8214 | *args, insn->name, insn->args); | |
8215 | /* Further processing is fruitless. */ | |
8216 | return; | |
8217 | } | |
8218 | break; | |
8219 | ||
252b5132 RH |
8220 | case '<': /* must be at least one digit */ |
8221 | /* | |
8222 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8223 | * than 31 or less than 0, then the shift amount should be |
8224 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8225 | * We issue a warning and mask out all but the low 5 bits. |
8226 | */ | |
8227 | my_getExpression (&imm_expr, s); | |
8228 | check_absolute_expr (ip, &imm_expr); | |
8229 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8230 | { | |
793b27f4 TS |
8231 | as_warn (_("Improper shift amount (%lu)"), |
8232 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8233 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8234 | } |
38487616 | 8235 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8236 | imm_expr.X_op = O_absent; |
8237 | s = expr_end; | |
8238 | continue; | |
8239 | ||
8240 | case '>': /* shift amount minus 32 */ | |
8241 | my_getExpression (&imm_expr, s); | |
8242 | check_absolute_expr (ip, &imm_expr); | |
8243 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8244 | || (unsigned long) imm_expr.X_add_number > 63) | |
8245 | break; | |
38487616 | 8246 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8247 | imm_expr.X_op = O_absent; |
8248 | s = expr_end; | |
8249 | continue; | |
8250 | ||
252b5132 RH |
8251 | case 'k': /* cache code */ |
8252 | case 'h': /* prefx code */ | |
8253 | my_getExpression (&imm_expr, s); | |
8254 | check_absolute_expr (ip, &imm_expr); | |
8255 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8256 | { | |
8257 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8258 | ip->insn_mo->name, | |
8259 | (unsigned long) imm_expr.X_add_number); | |
8260 | imm_expr.X_add_number &= 0x1f; | |
8261 | } | |
8262 | if (*args == 'k') | |
8263 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8264 | else | |
8265 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8266 | imm_expr.X_op = O_absent; | |
8267 | s = expr_end; | |
8268 | continue; | |
8269 | ||
8270 | case 'c': /* break code */ | |
8271 | my_getExpression (&imm_expr, s); | |
8272 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8273 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8274 | { |
793b27f4 TS |
8275 | as_warn (_("Illegal break code (%lu)"), |
8276 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8277 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8278 | } |
38487616 | 8279 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8280 | imm_expr.X_op = O_absent; |
8281 | s = expr_end; | |
8282 | continue; | |
8283 | ||
8284 | case 'q': /* lower break code */ | |
8285 | my_getExpression (&imm_expr, s); | |
8286 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8287 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8288 | { |
793b27f4 TS |
8289 | as_warn (_("Illegal lower break code (%lu)"), |
8290 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8291 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8292 | } |
38487616 | 8293 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8294 | imm_expr.X_op = O_absent; |
8295 | s = expr_end; | |
8296 | continue; | |
8297 | ||
4372b673 | 8298 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8299 | my_getExpression (&imm_expr, s); |
156c2f8b | 8300 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8301 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8302 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8303 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8304 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8305 | imm_expr.X_op = O_absent; |
8306 | s = expr_end; | |
8307 | continue; | |
8308 | ||
98d3f06f | 8309 | case 'C': /* Coprocessor code */ |
beae10d5 | 8310 | my_getExpression (&imm_expr, s); |
252b5132 | 8311 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8312 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8313 | { |
793b27f4 TS |
8314 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8315 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8316 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8317 | } |
beae10d5 KH |
8318 | ip->insn_opcode |= imm_expr.X_add_number; |
8319 | imm_expr.X_op = O_absent; | |
8320 | s = expr_end; | |
8321 | continue; | |
252b5132 | 8322 | |
4372b673 NC |
8323 | case 'J': /* 19-bit wait code. */ |
8324 | my_getExpression (&imm_expr, s); | |
8325 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8326 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8327 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8328 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8329 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8330 | imm_expr.X_op = O_absent; |
8331 | s = expr_end; | |
8332 | continue; | |
8333 | ||
252b5132 | 8334 | case 'P': /* Performance register */ |
beae10d5 | 8335 | my_getExpression (&imm_expr, s); |
252b5132 | 8336 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8337 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8338 | { |
793b27f4 TS |
8339 | as_warn (_("Invalid performance register (%lu)"), |
8340 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8341 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8342 | } |
38487616 | 8343 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8344 | imm_expr.X_op = O_absent; |
8345 | s = expr_end; | |
8346 | continue; | |
252b5132 RH |
8347 | |
8348 | case 'b': /* base register */ | |
8349 | case 'd': /* destination register */ | |
8350 | case 's': /* source register */ | |
8351 | case 't': /* target register */ | |
8352 | case 'r': /* both target and source */ | |
8353 | case 'v': /* both dest and source */ | |
8354 | case 'w': /* both dest and target */ | |
8355 | case 'E': /* coprocessor target register */ | |
8356 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8357 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8358 | case 'x': /* ignore register name */ |
8359 | case 'z': /* must be zero register */ | |
4372b673 | 8360 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8361 | s_reset = s; |
8362 | if (s[0] == '$') | |
8363 | { | |
8364 | ||
3882b010 | 8365 | if (ISDIGIT (s[1])) |
252b5132 RH |
8366 | { |
8367 | ++s; | |
8368 | regno = 0; | |
8369 | do | |
8370 | { | |
8371 | regno *= 10; | |
8372 | regno += *s - '0'; | |
8373 | ++s; | |
8374 | } | |
3882b010 | 8375 | while (ISDIGIT (*s)); |
252b5132 RH |
8376 | if (regno > 31) |
8377 | as_bad (_("Invalid register number (%d)"), regno); | |
8378 | } | |
af7ee8bf | 8379 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8380 | goto notreg; |
8381 | else | |
8382 | { | |
76db943d TS |
8383 | if (s[1] == 'r' && s[2] == 'a') |
8384 | { | |
8385 | s += 3; | |
8386 | regno = RA; | |
8387 | } | |
8388 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8389 | { |
8390 | s += 3; | |
8391 | regno = FP; | |
8392 | } | |
8393 | else if (s[1] == 's' && s[2] == 'p') | |
8394 | { | |
8395 | s += 3; | |
8396 | regno = SP; | |
8397 | } | |
8398 | else if (s[1] == 'g' && s[2] == 'p') | |
8399 | { | |
8400 | s += 3; | |
8401 | regno = GP; | |
8402 | } | |
8403 | else if (s[1] == 'a' && s[2] == 't') | |
8404 | { | |
8405 | s += 3; | |
8406 | regno = AT; | |
8407 | } | |
8408 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8409 | { | |
8410 | s += 4; | |
8411 | regno = KT0; | |
8412 | } | |
8413 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8414 | { | |
8415 | s += 4; | |
8416 | regno = KT1; | |
8417 | } | |
85b51719 TS |
8418 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8419 | { | |
8420 | s += 5; | |
8421 | regno = ZERO; | |
8422 | } | |
252b5132 RH |
8423 | else if (itbl_have_entries) |
8424 | { | |
8425 | char *p, *n; | |
d7ba4a77 | 8426 | unsigned long r; |
252b5132 | 8427 | |
d7ba4a77 | 8428 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8429 | n = itbl_get_field (&p); /* n is name */ |
8430 | ||
d7ba4a77 ILT |
8431 | /* See if this is a register defined in an |
8432 | itbl entry. */ | |
8433 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8434 | { |
8435 | /* Get_field advances to the start of | |
8436 | the next field, so we need to back | |
d7ba4a77 | 8437 | rack to the end of the last field. */ |
bdaaa2e1 | 8438 | if (p) |
252b5132 | 8439 | s = p - 1; |
bdaaa2e1 | 8440 | else |
d7ba4a77 | 8441 | s = strchr (s, '\0'); |
252b5132 RH |
8442 | regno = r; |
8443 | } | |
8444 | else | |
8445 | goto notreg; | |
beae10d5 | 8446 | } |
252b5132 RH |
8447 | else |
8448 | goto notreg; | |
8449 | } | |
8450 | if (regno == AT | |
8451 | && ! mips_opts.noat | |
8452 | && *args != 'E' | |
af7ee8bf CD |
8453 | && *args != 'G' |
8454 | && *args != 'K') | |
252b5132 RH |
8455 | as_warn (_("Used $at without \".set noat\"")); |
8456 | c = *args; | |
8457 | if (*s == ' ') | |
f9419b05 | 8458 | ++s; |
252b5132 RH |
8459 | if (args[1] != *s) |
8460 | { | |
8461 | if (c == 'r' || c == 'v' || c == 'w') | |
8462 | { | |
8463 | regno = lastregno; | |
8464 | s = s_reset; | |
f9419b05 | 8465 | ++args; |
252b5132 RH |
8466 | } |
8467 | } | |
8468 | /* 'z' only matches $0. */ | |
8469 | if (c == 'z' && regno != 0) | |
8470 | break; | |
8471 | ||
bdaaa2e1 KH |
8472 | /* Now that we have assembled one operand, we use the args string |
8473 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8474 | switch (c) |
8475 | { | |
8476 | case 'r': | |
8477 | case 's': | |
8478 | case 'v': | |
8479 | case 'b': | |
38487616 | 8480 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8481 | break; |
8482 | case 'd': | |
8483 | case 'G': | |
af7ee8bf | 8484 | case 'K': |
38487616 | 8485 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8486 | break; |
4372b673 | 8487 | case 'U': |
38487616 TS |
8488 | ip->insn_opcode |= regno << OP_SH_RD; |
8489 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8490 | break; |
252b5132 RH |
8491 | case 'w': |
8492 | case 't': | |
8493 | case 'E': | |
38487616 | 8494 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8495 | break; |
8496 | case 'x': | |
8497 | /* This case exists because on the r3000 trunc | |
8498 | expands into a macro which requires a gp | |
8499 | register. On the r6000 or r4000 it is | |
8500 | assembled into a single instruction which | |
8501 | ignores the register. Thus the insn version | |
8502 | is MIPS_ISA2 and uses 'x', and the macro | |
8503 | version is MIPS_ISA1 and uses 't'. */ | |
8504 | break; | |
8505 | case 'z': | |
8506 | /* This case is for the div instruction, which | |
8507 | acts differently if the destination argument | |
8508 | is $0. This only matches $0, and is checked | |
8509 | outside the switch. */ | |
8510 | break; | |
8511 | case 'D': | |
8512 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8513 | break; | |
8514 | /* What about all other operands like 'i', which | |
8515 | can be specified in the opcode table? */ | |
8516 | } | |
8517 | lastregno = regno; | |
8518 | continue; | |
8519 | } | |
8520 | notreg: | |
8521 | switch (*args++) | |
8522 | { | |
8523 | case 'r': | |
8524 | case 'v': | |
38487616 | 8525 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8526 | continue; |
8527 | case 'w': | |
38487616 | 8528 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8529 | continue; |
8530 | } | |
8531 | break; | |
8532 | ||
deec1734 CD |
8533 | case 'O': /* MDMX alignment immediate constant. */ |
8534 | my_getExpression (&imm_expr, s); | |
8535 | check_absolute_expr (ip, &imm_expr); | |
8536 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8537 | { | |
8538 | as_warn ("Improper align amount (%ld), using low bits", | |
8539 | (long) imm_expr.X_add_number); | |
8540 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8541 | } | |
8542 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8543 | imm_expr.X_op = O_absent; | |
8544 | s = expr_end; | |
8545 | continue; | |
8546 | ||
8547 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8548 | if (s[0] != '$') | |
8549 | { | |
8550 | /* MDMX Immediate. */ | |
8551 | my_getExpression (&imm_expr, s); | |
8552 | check_absolute_expr (ip, &imm_expr); | |
8553 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8554 | { | |
8555 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8556 | (long) imm_expr.X_add_number); | |
8557 | imm_expr.X_add_number &= OP_MASK_FT; | |
8558 | } | |
8559 | imm_expr.X_add_number &= OP_MASK_FT; | |
8560 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8561 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8562 | else | |
8563 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8564 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8565 | imm_expr.X_op = O_absent; | |
8566 | s = expr_end; | |
8567 | continue; | |
8568 | } | |
8569 | /* Not MDMX Immediate. Fall through. */ | |
8570 | case 'X': /* MDMX destination register. */ | |
8571 | case 'Y': /* MDMX source register. */ | |
8572 | case 'Z': /* MDMX target register. */ | |
8573 | is_mdmx = 1; | |
252b5132 RH |
8574 | case 'D': /* floating point destination register */ |
8575 | case 'S': /* floating point source register */ | |
8576 | case 'T': /* floating point target register */ | |
8577 | case 'R': /* floating point source register */ | |
8578 | case 'V': | |
8579 | case 'W': | |
8580 | s_reset = s; | |
deec1734 CD |
8581 | /* Accept $fN for FP and MDMX register numbers, and in |
8582 | addition accept $vN for MDMX register numbers. */ | |
8583 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8584 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8585 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8586 | { |
8587 | s += 2; | |
8588 | regno = 0; | |
8589 | do | |
8590 | { | |
8591 | regno *= 10; | |
8592 | regno += *s - '0'; | |
8593 | ++s; | |
8594 | } | |
3882b010 | 8595 | while (ISDIGIT (*s)); |
252b5132 RH |
8596 | |
8597 | if (regno > 31) | |
8598 | as_bad (_("Invalid float register number (%d)"), regno); | |
8599 | ||
8600 | if ((regno & 1) != 0 | |
ca4e0257 | 8601 | && HAVE_32BIT_FPRS |
252b5132 RH |
8602 | && ! (strcmp (str, "mtc1") == 0 |
8603 | || strcmp (str, "mfc1") == 0 | |
8604 | || strcmp (str, "lwc1") == 0 | |
8605 | || strcmp (str, "swc1") == 0 | |
8606 | || strcmp (str, "l.s") == 0 | |
8607 | || strcmp (str, "s.s") == 0)) | |
8608 | as_warn (_("Float register should be even, was %d"), | |
8609 | regno); | |
8610 | ||
8611 | c = *args; | |
8612 | if (*s == ' ') | |
f9419b05 | 8613 | ++s; |
252b5132 RH |
8614 | if (args[1] != *s) |
8615 | { | |
8616 | if (c == 'V' || c == 'W') | |
8617 | { | |
8618 | regno = lastregno; | |
8619 | s = s_reset; | |
f9419b05 | 8620 | ++args; |
252b5132 RH |
8621 | } |
8622 | } | |
8623 | switch (c) | |
8624 | { | |
8625 | case 'D': | |
deec1734 | 8626 | case 'X': |
38487616 | 8627 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8628 | break; |
8629 | case 'V': | |
8630 | case 'S': | |
deec1734 | 8631 | case 'Y': |
38487616 | 8632 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8633 | break; |
deec1734 CD |
8634 | case 'Q': |
8635 | /* This is like 'Z', but also needs to fix the MDMX | |
8636 | vector/scalar select bits. Note that the | |
8637 | scalar immediate case is handled above. */ | |
8638 | if (*s == '[') | |
8639 | { | |
8640 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8641 | int max_el = (is_qh ? 3 : 7); | |
8642 | s++; | |
8643 | my_getExpression(&imm_expr, s); | |
8644 | check_absolute_expr (ip, &imm_expr); | |
8645 | s = expr_end; | |
8646 | if (imm_expr.X_add_number > max_el) | |
8647 | as_bad(_("Bad element selector %ld"), | |
8648 | (long) imm_expr.X_add_number); | |
8649 | imm_expr.X_add_number &= max_el; | |
8650 | ip->insn_opcode |= (imm_expr.X_add_number | |
8651 | << (OP_SH_VSEL + | |
8652 | (is_qh ? 2 : 1))); | |
01a3f561 | 8653 | imm_expr.X_op = O_absent; |
deec1734 CD |
8654 | if (*s != ']') |
8655 | as_warn(_("Expecting ']' found '%s'"), s); | |
8656 | else | |
8657 | s++; | |
8658 | } | |
8659 | else | |
8660 | { | |
8661 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8662 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8663 | << OP_SH_VSEL); | |
8664 | else | |
8665 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8666 | OP_SH_VSEL); | |
8667 | } | |
8668 | /* Fall through */ | |
252b5132 RH |
8669 | case 'W': |
8670 | case 'T': | |
deec1734 | 8671 | case 'Z': |
38487616 | 8672 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8673 | break; |
8674 | case 'R': | |
38487616 | 8675 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8676 | break; |
8677 | } | |
8678 | lastregno = regno; | |
8679 | continue; | |
8680 | } | |
8681 | ||
252b5132 RH |
8682 | switch (*args++) |
8683 | { | |
8684 | case 'V': | |
38487616 | 8685 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8686 | continue; |
8687 | case 'W': | |
38487616 | 8688 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8689 | continue; |
8690 | } | |
8691 | break; | |
8692 | ||
8693 | case 'I': | |
8694 | my_getExpression (&imm_expr, s); | |
8695 | if (imm_expr.X_op != O_big | |
8696 | && imm_expr.X_op != O_constant) | |
8697 | insn_error = _("absolute expression required"); | |
13757d0c | 8698 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8699 | s = expr_end; |
8700 | continue; | |
8701 | ||
8702 | case 'A': | |
8703 | my_getExpression (&offset_expr, s); | |
f6688943 | 8704 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8705 | s = expr_end; |
8706 | continue; | |
8707 | ||
8708 | case 'F': | |
8709 | case 'L': | |
8710 | case 'f': | |
8711 | case 'l': | |
8712 | { | |
8713 | int f64; | |
ca4e0257 | 8714 | int using_gprs; |
252b5132 RH |
8715 | char *save_in; |
8716 | char *err; | |
8717 | unsigned char temp[8]; | |
8718 | int len; | |
8719 | unsigned int length; | |
8720 | segT seg; | |
8721 | subsegT subseg; | |
8722 | char *p; | |
8723 | ||
8724 | /* These only appear as the last operand in an | |
8725 | instruction, and every instruction that accepts | |
8726 | them in any variant accepts them in all variants. | |
8727 | This means we don't have to worry about backing out | |
8728 | any changes if the instruction does not match. | |
8729 | ||
8730 | The difference between them is the size of the | |
8731 | floating point constant and where it goes. For 'F' | |
8732 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8733 | is 32 bits. Where the constant is placed is based | |
8734 | on how the MIPS assembler does things: | |
8735 | F -- .rdata | |
8736 | L -- .lit8 | |
8737 | f -- immediate value | |
8738 | l -- .lit4 | |
8739 | ||
8740 | The .lit4 and .lit8 sections are only used if | |
8741 | permitted by the -G argument. | |
8742 | ||
ca4e0257 RS |
8743 | The code below needs to know whether the target register |
8744 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8745 | 'F' are used with GPR-based instructions and 'l' and | |
8746 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8747 | |
8748 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8749 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8750 | |
8751 | save_in = input_line_pointer; | |
8752 | input_line_pointer = s; | |
8753 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8754 | length = len; | |
8755 | s = input_line_pointer; | |
8756 | input_line_pointer = save_in; | |
8757 | if (err != NULL && *err != '\0') | |
8758 | { | |
8759 | as_bad (_("Bad floating point constant: %s"), err); | |
8760 | memset (temp, '\0', sizeof temp); | |
8761 | length = f64 ? 8 : 4; | |
8762 | } | |
8763 | ||
156c2f8b | 8764 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8765 | |
8766 | if (*args == 'f' | |
8767 | || (*args == 'l' | |
3e722fb5 | 8768 | && (g_switch_value < 4 |
252b5132 RH |
8769 | || (temp[0] == 0 && temp[1] == 0) |
8770 | || (temp[2] == 0 && temp[3] == 0)))) | |
8771 | { | |
8772 | imm_expr.X_op = O_constant; | |
8773 | if (! target_big_endian) | |
8774 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8775 | else | |
8776 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8777 | } | |
8778 | else if (length > 4 | |
119d663a | 8779 | && ! mips_disable_float_construction |
ca4e0257 RS |
8780 | /* Constants can only be constructed in GPRs and |
8781 | copied to FPRs if the GPRs are at least as wide | |
8782 | as the FPRs. Force the constant into memory if | |
8783 | we are using 64-bit FPRs but the GPRs are only | |
8784 | 32 bits wide. */ | |
8785 | && (using_gprs | |
8786 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8787 | && ((temp[0] == 0 && temp[1] == 0) |
8788 | || (temp[2] == 0 && temp[3] == 0)) | |
8789 | && ((temp[4] == 0 && temp[5] == 0) | |
8790 | || (temp[6] == 0 && temp[7] == 0))) | |
8791 | { | |
ca4e0257 RS |
8792 | /* The value is simple enough to load with a couple of |
8793 | instructions. If using 32-bit registers, set | |
8794 | imm_expr to the high order 32 bits and offset_expr to | |
8795 | the low order 32 bits. Otherwise, set imm_expr to | |
8796 | the entire 64 bit constant. */ | |
8797 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8798 | { |
8799 | imm_expr.X_op = O_constant; | |
8800 | offset_expr.X_op = O_constant; | |
8801 | if (! target_big_endian) | |
8802 | { | |
8803 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8804 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8805 | } | |
8806 | else | |
8807 | { | |
8808 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8809 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8810 | } | |
8811 | if (offset_expr.X_add_number == 0) | |
8812 | offset_expr.X_op = O_absent; | |
8813 | } | |
8814 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8815 | { | |
8816 | imm_expr.X_op = O_constant; | |
8817 | if (! target_big_endian) | |
8818 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8819 | else | |
8820 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8821 | } | |
8822 | else | |
8823 | { | |
8824 | imm_expr.X_op = O_big; | |
8825 | imm_expr.X_add_number = 4; | |
8826 | if (! target_big_endian) | |
8827 | { | |
8828 | generic_bignum[0] = bfd_getl16 (temp); | |
8829 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8830 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8831 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8832 | } | |
8833 | else | |
8834 | { | |
8835 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8836 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8837 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8838 | generic_bignum[3] = bfd_getb16 (temp); | |
8839 | } | |
8840 | } | |
8841 | } | |
8842 | else | |
8843 | { | |
8844 | const char *newname; | |
8845 | segT new_seg; | |
8846 | ||
8847 | /* Switch to the right section. */ | |
8848 | seg = now_seg; | |
8849 | subseg = now_subseg; | |
8850 | switch (*args) | |
8851 | { | |
8852 | default: /* unused default case avoids warnings. */ | |
8853 | case 'L': | |
8854 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8855 | if (g_switch_value >= 8) |
252b5132 RH |
8856 | newname = ".lit8"; |
8857 | break; | |
8858 | case 'F': | |
3e722fb5 | 8859 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8860 | break; |
8861 | case 'l': | |
4d0d148d | 8862 | assert (g_switch_value >= 4); |
252b5132 RH |
8863 | newname = ".lit4"; |
8864 | break; | |
8865 | } | |
8866 | new_seg = subseg_new (newname, (subsegT) 0); | |
8867 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8868 | bfd_set_section_flags (stdoutput, new_seg, | |
8869 | (SEC_ALLOC | |
8870 | | SEC_LOAD | |
8871 | | SEC_READONLY | |
8872 | | SEC_DATA)); | |
8873 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8874 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8875 | && strcmp (TARGET_OS, "elf") != 0) | |
8876 | record_alignment (new_seg, 4); | |
8877 | else | |
8878 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8879 | if (seg == now_seg) | |
8880 | as_bad (_("Can't use floating point insn in this section")); | |
8881 | ||
8882 | /* Set the argument to the current address in the | |
8883 | section. */ | |
8884 | offset_expr.X_op = O_symbol; | |
8885 | offset_expr.X_add_symbol = | |
8886 | symbol_new ("L0\001", now_seg, | |
8887 | (valueT) frag_now_fix (), frag_now); | |
8888 | offset_expr.X_add_number = 0; | |
8889 | ||
8890 | /* Put the floating point number into the section. */ | |
8891 | p = frag_more ((int) length); | |
8892 | memcpy (p, temp, length); | |
8893 | ||
8894 | /* Switch back to the original section. */ | |
8895 | subseg_set (seg, subseg); | |
8896 | } | |
8897 | } | |
8898 | continue; | |
8899 | ||
8900 | case 'i': /* 16 bit unsigned immediate */ | |
8901 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8902 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8903 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8904 | { |
8905 | int more; | |
5e0116d5 RS |
8906 | offsetT minval, maxval; |
8907 | ||
8908 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8909 | && strcmp (insn->name, insn[1].name) == 0); | |
8910 | ||
8911 | /* If the expression was written as an unsigned number, | |
8912 | only treat it as signed if there are no more | |
8913 | alternatives. */ | |
8914 | if (more | |
8915 | && *args == 'j' | |
8916 | && sizeof (imm_expr.X_add_number) <= 4 | |
8917 | && imm_expr.X_op == O_constant | |
8918 | && imm_expr.X_add_number < 0 | |
8919 | && imm_expr.X_unsigned | |
8920 | && HAVE_64BIT_GPRS) | |
8921 | break; | |
8922 | ||
8923 | /* For compatibility with older assemblers, we accept | |
8924 | 0x8000-0xffff as signed 16-bit numbers when only | |
8925 | signed numbers are allowed. */ | |
8926 | if (*args == 'i') | |
8927 | minval = 0, maxval = 0xffff; | |
8928 | else if (more) | |
8929 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8930 | else |
5e0116d5 RS |
8931 | minval = -0x8000, maxval = 0xffff; |
8932 | ||
8933 | if (imm_expr.X_op != O_constant | |
8934 | || imm_expr.X_add_number < minval | |
8935 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8936 | { |
8937 | if (more) | |
8938 | break; | |
2ae7e77b AH |
8939 | if (imm_expr.X_op == O_constant |
8940 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8941 | as_bad (_("expression out of range")); |
252b5132 RH |
8942 | } |
8943 | } | |
8944 | s = expr_end; | |
8945 | continue; | |
8946 | ||
8947 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8948 | /* Check whether there is only a single bracketed expression |
8949 | left. If so, it must be the base register and the | |
8950 | constant must be zero. */ | |
8951 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8952 | { | |
8953 | offset_expr.X_op = O_constant; | |
8954 | offset_expr.X_add_number = 0; | |
8955 | continue; | |
8956 | } | |
252b5132 RH |
8957 | |
8958 | /* If this value won't fit into a 16 bit offset, then go | |
8959 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8960 | code pattern. */ |
5e0116d5 | 8961 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8962 | && (offset_expr.X_op != O_constant |
8963 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8964 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8965 | break; |
8966 | ||
252b5132 RH |
8967 | s = expr_end; |
8968 | continue; | |
8969 | ||
8970 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8971 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8972 | my_getExpression (&offset_expr, s); |
8973 | s = expr_end; | |
8974 | continue; | |
8975 | ||
8976 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8977 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8978 | && imm_expr.X_op == O_constant | |
8979 | && (imm_expr.X_add_number < 0 | |
8980 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8981 | as_bad (_("lui expression not in range 0..65535")); |
8982 | s = expr_end; | |
8983 | continue; | |
8984 | ||
8985 | case 'a': /* 26 bit address */ | |
8986 | my_getExpression (&offset_expr, s); | |
8987 | s = expr_end; | |
f6688943 | 8988 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8989 | continue; |
8990 | ||
8991 | case 'N': /* 3 bit branch condition code */ | |
8992 | case 'M': /* 3 bit compare condition code */ | |
8993 | if (strncmp (s, "$fcc", 4) != 0) | |
8994 | break; | |
8995 | s += 4; | |
8996 | regno = 0; | |
8997 | do | |
8998 | { | |
8999 | regno *= 10; | |
9000 | regno += *s - '0'; | |
9001 | ++s; | |
9002 | } | |
3882b010 | 9003 | while (ISDIGIT (*s)); |
252b5132 | 9004 | if (regno > 7) |
30c378fd CD |
9005 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9006 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9007 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9008 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9009 | && (regno & 1) != 0) | |
9010 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9011 | str, regno); | |
9012 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9013 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9014 | && (regno & 3) != 0) | |
9015 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9016 | str, regno); | |
252b5132 RH |
9017 | if (*args == 'N') |
9018 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9019 | else | |
9020 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9021 | continue; |
252b5132 | 9022 | |
156c2f8b NC |
9023 | case 'H': |
9024 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9025 | s += 2; | |
3882b010 | 9026 | if (ISDIGIT (*s)) |
156c2f8b NC |
9027 | { |
9028 | c = 0; | |
9029 | do | |
9030 | { | |
9031 | c *= 10; | |
9032 | c += *s - '0'; | |
9033 | ++s; | |
9034 | } | |
3882b010 | 9035 | while (ISDIGIT (*s)); |
156c2f8b NC |
9036 | } |
9037 | else | |
9038 | c = 8; /* Invalid sel value. */ | |
9039 | ||
9040 | if (c > 7) | |
9041 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9042 | ip->insn_opcode |= c; | |
9043 | continue; | |
9044 | ||
60b63b72 RS |
9045 | case 'e': |
9046 | /* Must be at least one digit. */ | |
9047 | my_getExpression (&imm_expr, s); | |
9048 | check_absolute_expr (ip, &imm_expr); | |
9049 | ||
9050 | if ((unsigned long) imm_expr.X_add_number | |
9051 | > (unsigned long) OP_MASK_VECBYTE) | |
9052 | { | |
9053 | as_bad (_("bad byte vector index (%ld)"), | |
9054 | (long) imm_expr.X_add_number); | |
9055 | imm_expr.X_add_number = 0; | |
9056 | } | |
9057 | ||
9058 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9059 | imm_expr.X_op = O_absent; | |
9060 | s = expr_end; | |
9061 | continue; | |
9062 | ||
9063 | case '%': | |
9064 | my_getExpression (&imm_expr, s); | |
9065 | check_absolute_expr (ip, &imm_expr); | |
9066 | ||
9067 | if ((unsigned long) imm_expr.X_add_number | |
9068 | > (unsigned long) OP_MASK_VECALIGN) | |
9069 | { | |
9070 | as_bad (_("bad byte vector index (%ld)"), | |
9071 | (long) imm_expr.X_add_number); | |
9072 | imm_expr.X_add_number = 0; | |
9073 | } | |
9074 | ||
9075 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9076 | imm_expr.X_op = O_absent; | |
9077 | s = expr_end; | |
9078 | continue; | |
9079 | ||
252b5132 RH |
9080 | default: |
9081 | as_bad (_("bad char = '%c'\n"), *args); | |
9082 | internalError (); | |
9083 | } | |
9084 | break; | |
9085 | } | |
9086 | /* Args don't match. */ | |
9087 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9088 | !strcmp (insn->name, insn[1].name)) | |
9089 | { | |
9090 | ++insn; | |
9091 | s = argsStart; | |
268f6bed | 9092 | insn_error = _("illegal operands"); |
252b5132 RH |
9093 | continue; |
9094 | } | |
268f6bed L |
9095 | if (save_c) |
9096 | *(--s) = save_c; | |
252b5132 RH |
9097 | insn_error = _("illegal operands"); |
9098 | return; | |
9099 | } | |
9100 | } | |
9101 | ||
9102 | /* This routine assembles an instruction into its binary format when | |
9103 | assembling for the mips16. As a side effect, it sets one of the | |
9104 | global variables imm_reloc or offset_reloc to the type of | |
9105 | relocation to do if one of the operands is an address expression. | |
9106 | It also sets mips16_small and mips16_ext if the user explicitly | |
9107 | requested a small or extended instruction. */ | |
9108 | ||
9109 | static void | |
17a2f251 | 9110 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9111 | { |
9112 | char *s; | |
9113 | const char *args; | |
9114 | struct mips_opcode *insn; | |
9115 | char *argsstart; | |
9116 | unsigned int regno; | |
9117 | unsigned int lastregno = 0; | |
9118 | char *s_reset; | |
d6f16593 | 9119 | size_t i; |
252b5132 RH |
9120 | |
9121 | insn_error = NULL; | |
9122 | ||
b34976b6 AM |
9123 | mips16_small = FALSE; |
9124 | mips16_ext = FALSE; | |
252b5132 | 9125 | |
3882b010 | 9126 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9127 | ; |
9128 | switch (*s) | |
9129 | { | |
9130 | case '\0': | |
9131 | break; | |
9132 | ||
9133 | case ' ': | |
9134 | *s++ = '\0'; | |
9135 | break; | |
9136 | ||
9137 | case '.': | |
9138 | if (s[1] == 't' && s[2] == ' ') | |
9139 | { | |
9140 | *s = '\0'; | |
b34976b6 | 9141 | mips16_small = TRUE; |
252b5132 RH |
9142 | s += 3; |
9143 | break; | |
9144 | } | |
9145 | else if (s[1] == 'e' && s[2] == ' ') | |
9146 | { | |
9147 | *s = '\0'; | |
b34976b6 | 9148 | mips16_ext = TRUE; |
252b5132 RH |
9149 | s += 3; |
9150 | break; | |
9151 | } | |
9152 | /* Fall through. */ | |
9153 | default: | |
9154 | insn_error = _("unknown opcode"); | |
9155 | return; | |
9156 | } | |
9157 | ||
9158 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9159 | mips16_small = TRUE; |
252b5132 RH |
9160 | |
9161 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9162 | { | |
9163 | insn_error = _("unrecognized opcode"); | |
9164 | return; | |
9165 | } | |
9166 | ||
9167 | argsstart = s; | |
9168 | for (;;) | |
9169 | { | |
9170 | assert (strcmp (insn->name, str) == 0); | |
9171 | ||
9172 | ip->insn_mo = insn; | |
9173 | ip->insn_opcode = insn->match; | |
b34976b6 | 9174 | ip->use_extend = FALSE; |
252b5132 | 9175 | imm_expr.X_op = O_absent; |
f6688943 TS |
9176 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9177 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9178 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9179 | imm2_expr.X_op = O_absent; |
252b5132 | 9180 | offset_expr.X_op = O_absent; |
f6688943 TS |
9181 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9182 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9183 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9184 | for (args = insn->args; 1; ++args) |
9185 | { | |
9186 | int c; | |
9187 | ||
9188 | if (*s == ' ') | |
9189 | ++s; | |
9190 | ||
9191 | /* In this switch statement we call break if we did not find | |
9192 | a match, continue if we did find a match, or return if we | |
9193 | are done. */ | |
9194 | ||
9195 | c = *args; | |
9196 | switch (c) | |
9197 | { | |
9198 | case '\0': | |
9199 | if (*s == '\0') | |
9200 | { | |
9201 | /* Stuff the immediate value in now, if we can. */ | |
9202 | if (imm_expr.X_op == O_constant | |
f6688943 | 9203 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9204 | && insn->pinfo != INSN_MACRO) |
9205 | { | |
d6f16593 MR |
9206 | valueT tmp; |
9207 | ||
9208 | switch (*offset_reloc) | |
9209 | { | |
9210 | case BFD_RELOC_MIPS16_HI16_S: | |
9211 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9212 | break; | |
9213 | ||
9214 | case BFD_RELOC_MIPS16_HI16: | |
9215 | tmp = imm_expr.X_add_number >> 16; | |
9216 | break; | |
9217 | ||
9218 | case BFD_RELOC_MIPS16_LO16: | |
9219 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9220 | - 0x8000; | |
9221 | break; | |
9222 | ||
9223 | case BFD_RELOC_UNUSED: | |
9224 | tmp = imm_expr.X_add_number; | |
9225 | break; | |
9226 | ||
9227 | default: | |
9228 | internalError (); | |
9229 | } | |
9230 | *offset_reloc = BFD_RELOC_UNUSED; | |
9231 | ||
c4e7957c | 9232 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9233 | tmp, TRUE, mips16_small, |
252b5132 RH |
9234 | mips16_ext, &ip->insn_opcode, |
9235 | &ip->use_extend, &ip->extend); | |
9236 | imm_expr.X_op = O_absent; | |
f6688943 | 9237 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9238 | } |
9239 | ||
9240 | return; | |
9241 | } | |
9242 | break; | |
9243 | ||
9244 | case ',': | |
9245 | if (*s++ == c) | |
9246 | continue; | |
9247 | s--; | |
9248 | switch (*++args) | |
9249 | { | |
9250 | case 'v': | |
9251 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9252 | continue; | |
9253 | case 'w': | |
9254 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9255 | continue; | |
9256 | } | |
9257 | break; | |
9258 | ||
9259 | case '(': | |
9260 | case ')': | |
9261 | if (*s++ == c) | |
9262 | continue; | |
9263 | break; | |
9264 | ||
9265 | case 'v': | |
9266 | case 'w': | |
9267 | if (s[0] != '$') | |
9268 | { | |
9269 | if (c == 'v') | |
9270 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9271 | else | |
9272 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9273 | ++args; | |
9274 | continue; | |
9275 | } | |
9276 | /* Fall through. */ | |
9277 | case 'x': | |
9278 | case 'y': | |
9279 | case 'z': | |
9280 | case 'Z': | |
9281 | case '0': | |
9282 | case 'S': | |
9283 | case 'R': | |
9284 | case 'X': | |
9285 | case 'Y': | |
9286 | if (s[0] != '$') | |
9287 | break; | |
9288 | s_reset = s; | |
3882b010 | 9289 | if (ISDIGIT (s[1])) |
252b5132 RH |
9290 | { |
9291 | ++s; | |
9292 | regno = 0; | |
9293 | do | |
9294 | { | |
9295 | regno *= 10; | |
9296 | regno += *s - '0'; | |
9297 | ++s; | |
9298 | } | |
3882b010 | 9299 | while (ISDIGIT (*s)); |
252b5132 RH |
9300 | if (regno > 31) |
9301 | { | |
9302 | as_bad (_("invalid register number (%d)"), regno); | |
9303 | regno = 2; | |
9304 | } | |
9305 | } | |
9306 | else | |
9307 | { | |
76db943d TS |
9308 | if (s[1] == 'r' && s[2] == 'a') |
9309 | { | |
9310 | s += 3; | |
9311 | regno = RA; | |
9312 | } | |
9313 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9314 | { |
9315 | s += 3; | |
9316 | regno = FP; | |
9317 | } | |
9318 | else if (s[1] == 's' && s[2] == 'p') | |
9319 | { | |
9320 | s += 3; | |
9321 | regno = SP; | |
9322 | } | |
9323 | else if (s[1] == 'g' && s[2] == 'p') | |
9324 | { | |
9325 | s += 3; | |
9326 | regno = GP; | |
9327 | } | |
9328 | else if (s[1] == 'a' && s[2] == 't') | |
9329 | { | |
9330 | s += 3; | |
9331 | regno = AT; | |
9332 | } | |
9333 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9334 | { | |
9335 | s += 4; | |
9336 | regno = KT0; | |
9337 | } | |
9338 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9339 | { | |
9340 | s += 4; | |
9341 | regno = KT1; | |
9342 | } | |
85b51719 TS |
9343 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9344 | { | |
9345 | s += 5; | |
9346 | regno = ZERO; | |
9347 | } | |
252b5132 RH |
9348 | else |
9349 | break; | |
9350 | } | |
9351 | ||
9352 | if (*s == ' ') | |
9353 | ++s; | |
9354 | if (args[1] != *s) | |
9355 | { | |
9356 | if (c == 'v' || c == 'w') | |
9357 | { | |
9358 | regno = mips16_to_32_reg_map[lastregno]; | |
9359 | s = s_reset; | |
f9419b05 | 9360 | ++args; |
252b5132 RH |
9361 | } |
9362 | } | |
9363 | ||
9364 | switch (c) | |
9365 | { | |
9366 | case 'x': | |
9367 | case 'y': | |
9368 | case 'z': | |
9369 | case 'v': | |
9370 | case 'w': | |
9371 | case 'Z': | |
9372 | regno = mips32_to_16_reg_map[regno]; | |
9373 | break; | |
9374 | ||
9375 | case '0': | |
9376 | if (regno != 0) | |
9377 | regno = ILLEGAL_REG; | |
9378 | break; | |
9379 | ||
9380 | case 'S': | |
9381 | if (regno != SP) | |
9382 | regno = ILLEGAL_REG; | |
9383 | break; | |
9384 | ||
9385 | case 'R': | |
9386 | if (regno != RA) | |
9387 | regno = ILLEGAL_REG; | |
9388 | break; | |
9389 | ||
9390 | case 'X': | |
9391 | case 'Y': | |
9392 | if (regno == AT && ! mips_opts.noat) | |
9393 | as_warn (_("used $at without \".set noat\"")); | |
9394 | break; | |
9395 | ||
9396 | default: | |
9397 | internalError (); | |
9398 | } | |
9399 | ||
9400 | if (regno == ILLEGAL_REG) | |
9401 | break; | |
9402 | ||
9403 | switch (c) | |
9404 | { | |
9405 | case 'x': | |
9406 | case 'v': | |
9407 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9408 | break; | |
9409 | case 'y': | |
9410 | case 'w': | |
9411 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9412 | break; | |
9413 | case 'z': | |
9414 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9415 | break; | |
9416 | case 'Z': | |
9417 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9418 | case '0': | |
9419 | case 'S': | |
9420 | case 'R': | |
9421 | break; | |
9422 | case 'X': | |
9423 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9424 | break; | |
9425 | case 'Y': | |
9426 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9427 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9428 | break; | |
9429 | default: | |
9430 | internalError (); | |
9431 | } | |
9432 | ||
9433 | lastregno = regno; | |
9434 | continue; | |
9435 | ||
9436 | case 'P': | |
9437 | if (strncmp (s, "$pc", 3) == 0) | |
9438 | { | |
9439 | s += 3; | |
9440 | continue; | |
9441 | } | |
9442 | break; | |
9443 | ||
252b5132 RH |
9444 | case '5': |
9445 | case 'H': | |
9446 | case 'W': | |
9447 | case 'D': | |
9448 | case 'j': | |
252b5132 RH |
9449 | case 'V': |
9450 | case 'C': | |
9451 | case 'U': | |
9452 | case 'k': | |
9453 | case 'K': | |
d6f16593 MR |
9454 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9455 | if (i > 0) | |
252b5132 | 9456 | { |
d6f16593 | 9457 | if (imm_expr.X_op != O_constant) |
252b5132 | 9458 | { |
b34976b6 | 9459 | mips16_ext = TRUE; |
b34976b6 | 9460 | ip->use_extend = TRUE; |
252b5132 | 9461 | ip->extend = 0; |
252b5132 | 9462 | } |
d6f16593 MR |
9463 | else |
9464 | { | |
9465 | /* We need to relax this instruction. */ | |
9466 | *offset_reloc = *imm_reloc; | |
9467 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9468 | } | |
9469 | s = expr_end; | |
9470 | continue; | |
252b5132 | 9471 | } |
d6f16593 MR |
9472 | *imm_reloc = BFD_RELOC_UNUSED; |
9473 | /* Fall through. */ | |
9474 | case '<': | |
9475 | case '>': | |
9476 | case '[': | |
9477 | case ']': | |
9478 | case '4': | |
9479 | case '8': | |
9480 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9481 | if (imm_expr.X_op == O_register) |
9482 | { | |
9483 | /* What we thought was an expression turned out to | |
9484 | be a register. */ | |
9485 | ||
9486 | if (s[0] == '(' && args[1] == '(') | |
9487 | { | |
9488 | /* It looks like the expression was omitted | |
9489 | before a register indirection, which means | |
9490 | that the expression is implicitly zero. We | |
9491 | still set up imm_expr, so that we handle | |
9492 | explicit extensions correctly. */ | |
9493 | imm_expr.X_op = O_constant; | |
9494 | imm_expr.X_add_number = 0; | |
f6688943 | 9495 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9496 | continue; |
9497 | } | |
9498 | ||
9499 | break; | |
9500 | } | |
9501 | ||
9502 | /* We need to relax this instruction. */ | |
f6688943 | 9503 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9504 | s = expr_end; |
9505 | continue; | |
9506 | ||
9507 | case 'p': | |
9508 | case 'q': | |
9509 | case 'A': | |
9510 | case 'B': | |
9511 | case 'E': | |
9512 | /* We use offset_reloc rather than imm_reloc for the PC | |
9513 | relative operands. This lets macros with both | |
9514 | immediate and address operands work correctly. */ | |
9515 | my_getExpression (&offset_expr, s); | |
9516 | ||
9517 | if (offset_expr.X_op == O_register) | |
9518 | break; | |
9519 | ||
9520 | /* We need to relax this instruction. */ | |
f6688943 | 9521 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9522 | s = expr_end; |
9523 | continue; | |
9524 | ||
9525 | case '6': /* break code */ | |
9526 | my_getExpression (&imm_expr, s); | |
9527 | check_absolute_expr (ip, &imm_expr); | |
9528 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9529 | { | |
9530 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9531 | ip->insn_mo->name, | |
9532 | (unsigned long) imm_expr.X_add_number); | |
9533 | imm_expr.X_add_number &= 0x3f; | |
9534 | } | |
9535 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9536 | imm_expr.X_op = O_absent; | |
9537 | s = expr_end; | |
9538 | continue; | |
9539 | ||
9540 | case 'a': /* 26 bit address */ | |
9541 | my_getExpression (&offset_expr, s); | |
9542 | s = expr_end; | |
f6688943 | 9543 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9544 | ip->insn_opcode <<= 16; |
9545 | continue; | |
9546 | ||
9547 | case 'l': /* register list for entry macro */ | |
9548 | case 'L': /* register list for exit macro */ | |
9549 | { | |
9550 | int mask; | |
9551 | ||
9552 | if (c == 'l') | |
9553 | mask = 0; | |
9554 | else | |
9555 | mask = 7 << 3; | |
9556 | while (*s != '\0') | |
9557 | { | |
9558 | int freg, reg1, reg2; | |
9559 | ||
9560 | while (*s == ' ' || *s == ',') | |
9561 | ++s; | |
9562 | if (*s != '$') | |
9563 | { | |
9564 | as_bad (_("can't parse register list")); | |
9565 | break; | |
9566 | } | |
9567 | ++s; | |
9568 | if (*s != 'f') | |
9569 | freg = 0; | |
9570 | else | |
9571 | { | |
9572 | freg = 1; | |
9573 | ++s; | |
9574 | } | |
9575 | reg1 = 0; | |
3882b010 | 9576 | while (ISDIGIT (*s)) |
252b5132 RH |
9577 | { |
9578 | reg1 *= 10; | |
9579 | reg1 += *s - '0'; | |
9580 | ++s; | |
9581 | } | |
9582 | if (*s == ' ') | |
9583 | ++s; | |
9584 | if (*s != '-') | |
9585 | reg2 = reg1; | |
9586 | else | |
9587 | { | |
9588 | ++s; | |
9589 | if (*s != '$') | |
9590 | break; | |
9591 | ++s; | |
9592 | if (freg) | |
9593 | { | |
9594 | if (*s == 'f') | |
9595 | ++s; | |
9596 | else | |
9597 | { | |
9598 | as_bad (_("invalid register list")); | |
9599 | break; | |
9600 | } | |
9601 | } | |
9602 | reg2 = 0; | |
3882b010 | 9603 | while (ISDIGIT (*s)) |
252b5132 RH |
9604 | { |
9605 | reg2 *= 10; | |
9606 | reg2 += *s - '0'; | |
9607 | ++s; | |
9608 | } | |
9609 | } | |
9610 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9611 | { | |
9612 | mask &= ~ (7 << 3); | |
9613 | mask |= 5 << 3; | |
9614 | } | |
9615 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9616 | { | |
9617 | mask &= ~ (7 << 3); | |
9618 | mask |= 6 << 3; | |
9619 | } | |
9620 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9621 | mask |= (reg2 - 3) << 3; | |
9622 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9623 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9624 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9625 | mask |= 1; |
9626 | else | |
9627 | { | |
9628 | as_bad (_("invalid register list")); | |
9629 | break; | |
9630 | } | |
9631 | } | |
9632 | /* The mask is filled in in the opcode table for the | |
9633 | benefit of the disassembler. We remove it before | |
9634 | applying the actual mask. */ | |
9635 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9636 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9637 | } | |
9638 | continue; | |
9639 | ||
9640 | case 'e': /* extend code */ | |
9641 | my_getExpression (&imm_expr, s); | |
9642 | check_absolute_expr (ip, &imm_expr); | |
9643 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9644 | { | |
9645 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9646 | ip->insn_mo->name, | |
9647 | (unsigned long) imm_expr.X_add_number); | |
9648 | imm_expr.X_add_number &= 0x7ff; | |
9649 | } | |
9650 | ip->insn_opcode |= imm_expr.X_add_number; | |
9651 | imm_expr.X_op = O_absent; | |
9652 | s = expr_end; | |
9653 | continue; | |
9654 | ||
9655 | default: | |
9656 | internalError (); | |
9657 | } | |
9658 | break; | |
9659 | } | |
9660 | ||
9661 | /* Args don't match. */ | |
9662 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9663 | strcmp (insn->name, insn[1].name) == 0) | |
9664 | { | |
9665 | ++insn; | |
9666 | s = argsstart; | |
9667 | continue; | |
9668 | } | |
9669 | ||
9670 | insn_error = _("illegal operands"); | |
9671 | ||
9672 | return; | |
9673 | } | |
9674 | } | |
9675 | ||
9676 | /* This structure holds information we know about a mips16 immediate | |
9677 | argument type. */ | |
9678 | ||
e972090a NC |
9679 | struct mips16_immed_operand |
9680 | { | |
252b5132 RH |
9681 | /* The type code used in the argument string in the opcode table. */ |
9682 | int type; | |
9683 | /* The number of bits in the short form of the opcode. */ | |
9684 | int nbits; | |
9685 | /* The number of bits in the extended form of the opcode. */ | |
9686 | int extbits; | |
9687 | /* The amount by which the short form is shifted when it is used; | |
9688 | for example, the sw instruction has a shift count of 2. */ | |
9689 | int shift; | |
9690 | /* The amount by which the short form is shifted when it is stored | |
9691 | into the instruction code. */ | |
9692 | int op_shift; | |
9693 | /* Non-zero if the short form is unsigned. */ | |
9694 | int unsp; | |
9695 | /* Non-zero if the extended form is unsigned. */ | |
9696 | int extu; | |
9697 | /* Non-zero if the value is PC relative. */ | |
9698 | int pcrel; | |
9699 | }; | |
9700 | ||
9701 | /* The mips16 immediate operand types. */ | |
9702 | ||
9703 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9704 | { | |
9705 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9706 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9707 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9708 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9709 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9710 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9711 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9712 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9713 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9714 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9715 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9716 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9717 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9718 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9719 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9720 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9721 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9722 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9723 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9724 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9725 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9726 | }; | |
9727 | ||
9728 | #define MIPS16_NUM_IMMED \ | |
9729 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9730 | ||
9731 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9732 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9733 | whether an extended value is needed; if one is needed, it sets | |
9734 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9735 | If SMALL is true, an unextended opcode was explicitly requested. | |
9736 | If EXT is true, an extended opcode was explicitly requested. If | |
9737 | WARN is true, warn if EXT does not match reality. */ | |
9738 | ||
9739 | static void | |
17a2f251 TS |
9740 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9741 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9742 | unsigned long *insn, bfd_boolean *use_extend, | |
9743 | unsigned short *extend) | |
252b5132 RH |
9744 | { |
9745 | register const struct mips16_immed_operand *op; | |
9746 | int mintiny, maxtiny; | |
b34976b6 | 9747 | bfd_boolean needext; |
252b5132 RH |
9748 | |
9749 | op = mips16_immed_operands; | |
9750 | while (op->type != type) | |
9751 | { | |
9752 | ++op; | |
9753 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9754 | } | |
9755 | ||
9756 | if (op->unsp) | |
9757 | { | |
9758 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9759 | { | |
9760 | mintiny = 1; | |
9761 | maxtiny = 1 << op->nbits; | |
9762 | } | |
9763 | else | |
9764 | { | |
9765 | mintiny = 0; | |
9766 | maxtiny = (1 << op->nbits) - 1; | |
9767 | } | |
9768 | } | |
9769 | else | |
9770 | { | |
9771 | mintiny = - (1 << (op->nbits - 1)); | |
9772 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9773 | } | |
9774 | ||
9775 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9776 | if (type == 'p' || type == 'q') | |
9777 | val /= 2; | |
9778 | ||
9779 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9780 | || val < (mintiny << op->shift) | |
9781 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9782 | needext = TRUE; |
252b5132 | 9783 | else |
b34976b6 | 9784 | needext = FALSE; |
252b5132 RH |
9785 | |
9786 | if (warn && ext && ! needext) | |
beae10d5 KH |
9787 | as_warn_where (file, line, |
9788 | _("extended operand requested but not required")); | |
252b5132 RH |
9789 | if (small && needext) |
9790 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9791 | ||
9792 | if (small || (! ext && ! needext)) | |
9793 | { | |
9794 | int insnval; | |
9795 | ||
b34976b6 | 9796 | *use_extend = FALSE; |
252b5132 RH |
9797 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9798 | insnval <<= op->op_shift; | |
9799 | *insn |= insnval; | |
9800 | } | |
9801 | else | |
9802 | { | |
9803 | long minext, maxext; | |
9804 | int extval; | |
9805 | ||
9806 | if (op->extu) | |
9807 | { | |
9808 | minext = 0; | |
9809 | maxext = (1 << op->extbits) - 1; | |
9810 | } | |
9811 | else | |
9812 | { | |
9813 | minext = - (1 << (op->extbits - 1)); | |
9814 | maxext = (1 << (op->extbits - 1)) - 1; | |
9815 | } | |
9816 | if (val < minext || val > maxext) | |
9817 | as_bad_where (file, line, | |
9818 | _("operand value out of range for instruction")); | |
9819 | ||
b34976b6 | 9820 | *use_extend = TRUE; |
252b5132 RH |
9821 | if (op->extbits == 16) |
9822 | { | |
9823 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9824 | val &= 0x1f; | |
9825 | } | |
9826 | else if (op->extbits == 15) | |
9827 | { | |
9828 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9829 | val &= 0xf; | |
9830 | } | |
9831 | else | |
9832 | { | |
9833 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9834 | val = 0; | |
9835 | } | |
9836 | ||
9837 | *extend = (unsigned short) extval; | |
9838 | *insn |= val; | |
9839 | } | |
9840 | } | |
9841 | \f | |
d6f16593 | 9842 | struct percent_op_match |
ad8d3bb3 | 9843 | { |
5e0116d5 RS |
9844 | const char *str; |
9845 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9846 | }; |
9847 | ||
9848 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9849 | { |
5e0116d5 | 9850 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9851 | #ifdef OBJ_ELF |
5e0116d5 RS |
9852 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9853 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9854 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9855 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9856 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9857 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9858 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9859 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9860 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9861 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9862 | {"%half", BFD_RELOC_16}, | |
9863 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9864 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9865 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9866 | #endif |
5e0116d5 | 9867 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9868 | }; |
9869 | ||
d6f16593 MR |
9870 | static const struct percent_op_match mips16_percent_op[] = |
9871 | { | |
9872 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9873 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9874 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9875 | }; | |
9876 | ||
252b5132 | 9877 | |
5e0116d5 RS |
9878 | /* Return true if *STR points to a relocation operator. When returning true, |
9879 | move *STR over the operator and store its relocation code in *RELOC. | |
9880 | Leave both *STR and *RELOC alone when returning false. */ | |
9881 | ||
9882 | static bfd_boolean | |
17a2f251 | 9883 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9884 | { |
d6f16593 MR |
9885 | const struct percent_op_match *percent_op; |
9886 | size_t limit, i; | |
9887 | ||
9888 | if (mips_opts.mips16) | |
9889 | { | |
9890 | percent_op = mips16_percent_op; | |
9891 | limit = ARRAY_SIZE (mips16_percent_op); | |
9892 | } | |
9893 | else | |
9894 | { | |
9895 | percent_op = mips_percent_op; | |
9896 | limit = ARRAY_SIZE (mips_percent_op); | |
9897 | } | |
76b3015f | 9898 | |
d6f16593 | 9899 | for (i = 0; i < limit; i++) |
5e0116d5 | 9900 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9901 | { |
5e0116d5 RS |
9902 | *str += strlen (percent_op[i].str); |
9903 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9904 | |
5e0116d5 RS |
9905 | /* Check whether the output BFD supports this relocation. |
9906 | If not, issue an error and fall back on something safe. */ | |
9907 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9908 | { |
5e0116d5 RS |
9909 | as_bad ("relocation %s isn't supported by the current ABI", |
9910 | percent_op[i].str); | |
01a3f561 | 9911 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9912 | } |
5e0116d5 | 9913 | return TRUE; |
394f9b3a | 9914 | } |
5e0116d5 | 9915 | return FALSE; |
394f9b3a | 9916 | } |
ad8d3bb3 | 9917 | |
ad8d3bb3 | 9918 | |
5e0116d5 RS |
9919 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9920 | expression in *EP and the relocations in the array starting | |
9921 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9922 | |
01a3f561 | 9923 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9924 | |
5e0116d5 | 9925 | static size_t |
17a2f251 TS |
9926 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9927 | char *str) | |
ad8d3bb3 | 9928 | { |
5e0116d5 RS |
9929 | bfd_reloc_code_real_type reversed_reloc[3]; |
9930 | size_t reloc_index, i; | |
09b8f35a RS |
9931 | int crux_depth, str_depth; |
9932 | char *crux; | |
5e0116d5 RS |
9933 | |
9934 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9935 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9936 | of the main expression and with CRUX_DEPTH containing the number | |
9937 | of open brackets at that point. */ | |
9938 | reloc_index = -1; | |
9939 | str_depth = 0; | |
9940 | do | |
fb1b3232 | 9941 | { |
09b8f35a RS |
9942 | reloc_index++; |
9943 | crux = str; | |
9944 | crux_depth = str_depth; | |
9945 | ||
9946 | /* Skip over whitespace and brackets, keeping count of the number | |
9947 | of brackets. */ | |
9948 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9949 | if (*str++ == '(') | |
9950 | str_depth++; | |
5e0116d5 | 9951 | } |
09b8f35a RS |
9952 | while (*str == '%' |
9953 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9954 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9955 | |
09b8f35a | 9956 | my_getExpression (ep, crux); |
5e0116d5 | 9957 | str = expr_end; |
394f9b3a | 9958 | |
5e0116d5 | 9959 | /* Match every open bracket. */ |
09b8f35a | 9960 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9961 | if (*str++ == ')') |
09b8f35a | 9962 | crux_depth--; |
394f9b3a | 9963 | |
09b8f35a | 9964 | if (crux_depth > 0) |
5e0116d5 | 9965 | as_bad ("unclosed '('"); |
394f9b3a | 9966 | |
5e0116d5 | 9967 | expr_end = str; |
252b5132 | 9968 | |
01a3f561 | 9969 | if (reloc_index != 0) |
64bdfcaf RS |
9970 | { |
9971 | prev_reloc_op_frag = frag_now; | |
9972 | for (i = 0; i < reloc_index; i++) | |
9973 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9974 | } | |
fb1b3232 | 9975 | |
5e0116d5 | 9976 | return reloc_index; |
252b5132 RH |
9977 | } |
9978 | ||
9979 | static void | |
17a2f251 | 9980 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9981 | { |
9982 | char *save_in; | |
98aa84af | 9983 | valueT val; |
252b5132 RH |
9984 | |
9985 | save_in = input_line_pointer; | |
9986 | input_line_pointer = str; | |
9987 | expression (ep); | |
9988 | expr_end = input_line_pointer; | |
9989 | input_line_pointer = save_in; | |
9990 | ||
9991 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9992 | then we bump the value of the symbol by 1 since that is how other | |
9993 | text symbols are handled. We don't bother to handle complex | |
9994 | expressions, just `.' plus or minus a constant. */ | |
9995 | if (mips_opts.mips16 | |
9996 | && ep->X_op == O_symbol | |
9997 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9998 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9999 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10000 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10001 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10002 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10003 | } |
10004 | ||
10005 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10006 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10007 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10008 | returned, or NULL on OK. */ |
10009 | ||
10010 | char * | |
17a2f251 | 10011 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10012 | { |
10013 | int prec; | |
10014 | LITTLENUM_TYPE words[4]; | |
10015 | char *t; | |
10016 | int i; | |
10017 | ||
10018 | switch (type) | |
10019 | { | |
10020 | case 'f': | |
10021 | prec = 2; | |
10022 | break; | |
10023 | ||
10024 | case 'd': | |
10025 | prec = 4; | |
10026 | break; | |
10027 | ||
10028 | default: | |
10029 | *sizeP = 0; | |
10030 | return _("bad call to md_atof"); | |
10031 | } | |
10032 | ||
10033 | t = atof_ieee (input_line_pointer, type, words); | |
10034 | if (t) | |
10035 | input_line_pointer = t; | |
10036 | ||
10037 | *sizeP = prec * 2; | |
10038 | ||
10039 | if (! target_big_endian) | |
10040 | { | |
10041 | for (i = prec - 1; i >= 0; i--) | |
10042 | { | |
17a2f251 | 10043 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10044 | litP += 2; |
10045 | } | |
10046 | } | |
10047 | else | |
10048 | { | |
10049 | for (i = 0; i < prec; i++) | |
10050 | { | |
17a2f251 | 10051 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10052 | litP += 2; |
10053 | } | |
10054 | } | |
bdaaa2e1 | 10055 | |
252b5132 RH |
10056 | return NULL; |
10057 | } | |
10058 | ||
10059 | void | |
17a2f251 | 10060 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10061 | { |
10062 | if (target_big_endian) | |
10063 | number_to_chars_bigendian (buf, val, n); | |
10064 | else | |
10065 | number_to_chars_littleendian (buf, val, n); | |
10066 | } | |
10067 | \f | |
ae948b86 | 10068 | #ifdef OBJ_ELF |
e013f690 TS |
10069 | static int support_64bit_objects(void) |
10070 | { | |
10071 | const char **list, **l; | |
aa3d8fdf | 10072 | int yes; |
e013f690 TS |
10073 | |
10074 | list = bfd_target_list (); | |
10075 | for (l = list; *l != NULL; l++) | |
10076 | #ifdef TE_TMIPS | |
10077 | /* This is traditional mips */ | |
10078 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10079 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10080 | #else | |
10081 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10082 | || strcmp (*l, "elf64-littlemips") == 0) | |
10083 | #endif | |
10084 | break; | |
aa3d8fdf | 10085 | yes = (*l != NULL); |
e013f690 | 10086 | free (list); |
aa3d8fdf | 10087 | return yes; |
e013f690 | 10088 | } |
ae948b86 | 10089 | #endif /* OBJ_ELF */ |
e013f690 | 10090 | |
78849248 | 10091 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10092 | |
e972090a NC |
10093 | struct option md_longopts[] = |
10094 | { | |
f9b4148d CD |
10095 | /* Options which specify architecture. */ |
10096 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10097 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10098 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10099 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10100 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10101 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10102 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10103 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10104 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10105 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10106 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10107 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10108 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10109 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10110 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10111 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10112 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10113 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10114 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10115 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10116 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10117 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10118 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10119 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10120 | |
10121 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10122 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10123 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10124 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10125 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10126 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10127 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10128 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10129 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10130 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10131 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10132 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10133 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10134 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10135 | ||
10136 | /* Old-style architecture options. Don't add more of these. */ | |
10137 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10138 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10139 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10140 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10141 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10142 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10143 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10144 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10145 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10146 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10147 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10148 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10149 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10150 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10151 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10152 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10153 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10154 | ||
10155 | /* Options which enable bug fixes. */ | |
10156 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10157 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10158 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10159 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10160 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10161 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10162 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10163 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10164 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10165 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10166 | |
10167 | /* Miscellaneous options. */ | |
10168 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10169 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10170 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10171 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10172 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10173 | {"break", no_argument, NULL, OPTION_BREAK}, |
10174 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10175 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10176 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10177 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10178 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10179 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10180 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10181 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10182 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10183 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10184 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10185 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10186 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10187 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10188 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10189 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10190 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10191 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10192 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10193 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10194 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10195 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10196 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10197 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10198 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
f9b4148d CD |
10199 | |
10200 | /* ELF-specific options. */ | |
156c2f8b | 10201 | #ifdef OBJ_ELF |
aa6975fb | 10202 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14) |
156c2f8b | 10203 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10204 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10205 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10206 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10207 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10208 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10209 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10210 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10211 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10212 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10213 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10214 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10215 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10216 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10217 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10218 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10219 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10220 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10221 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10222 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10223 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10224 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10225 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10226 | #endif /* OBJ_ELF */ |
f9b4148d | 10227 | |
252b5132 RH |
10228 | {NULL, no_argument, NULL, 0} |
10229 | }; | |
156c2f8b | 10230 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10231 | |
316f5878 RS |
10232 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10233 | NEW_VALUE. Warn if another value was already specified. Note: | |
10234 | we have to defer parsing the -march and -mtune arguments in order | |
10235 | to handle 'from-abi' correctly, since the ABI might be specified | |
10236 | in a later argument. */ | |
10237 | ||
10238 | static void | |
17a2f251 | 10239 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10240 | { |
10241 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10242 | as_warn (_("A different %s was already specified, is now %s"), | |
10243 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10244 | new_value); | |
10245 | ||
10246 | *string_ptr = new_value; | |
10247 | } | |
10248 | ||
252b5132 | 10249 | int |
17a2f251 | 10250 | md_parse_option (int c, char *arg) |
252b5132 RH |
10251 | { |
10252 | switch (c) | |
10253 | { | |
119d663a NC |
10254 | case OPTION_CONSTRUCT_FLOATS: |
10255 | mips_disable_float_construction = 0; | |
10256 | break; | |
bdaaa2e1 | 10257 | |
119d663a NC |
10258 | case OPTION_NO_CONSTRUCT_FLOATS: |
10259 | mips_disable_float_construction = 1; | |
10260 | break; | |
bdaaa2e1 | 10261 | |
252b5132 RH |
10262 | case OPTION_TRAP: |
10263 | mips_trap = 1; | |
10264 | break; | |
10265 | ||
10266 | case OPTION_BREAK: | |
10267 | mips_trap = 0; | |
10268 | break; | |
10269 | ||
10270 | case OPTION_EB: | |
10271 | target_big_endian = 1; | |
10272 | break; | |
10273 | ||
10274 | case OPTION_EL: | |
10275 | target_big_endian = 0; | |
10276 | break; | |
10277 | ||
10278 | case 'O': | |
10279 | if (arg && arg[1] == '0') | |
10280 | mips_optimize = 1; | |
10281 | else | |
10282 | mips_optimize = 2; | |
10283 | break; | |
10284 | ||
10285 | case 'g': | |
10286 | if (arg == NULL) | |
10287 | mips_debug = 2; | |
10288 | else | |
10289 | mips_debug = atoi (arg); | |
10290 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10291 | optimizations which limit full symbolic debugging. We take | |
10292 | that to be equivalent to -O0. */ | |
10293 | if (mips_debug == 2) | |
10294 | mips_optimize = 1; | |
10295 | break; | |
10296 | ||
10297 | case OPTION_MIPS1: | |
316f5878 | 10298 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10299 | break; |
10300 | ||
10301 | case OPTION_MIPS2: | |
316f5878 | 10302 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10303 | break; |
10304 | ||
10305 | case OPTION_MIPS3: | |
316f5878 | 10306 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10307 | break; |
10308 | ||
10309 | case OPTION_MIPS4: | |
316f5878 | 10310 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10311 | break; |
10312 | ||
84ea6cf2 | 10313 | case OPTION_MIPS5: |
316f5878 | 10314 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10315 | break; |
10316 | ||
e7af610e | 10317 | case OPTION_MIPS32: |
316f5878 | 10318 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10319 | break; |
10320 | ||
af7ee8bf CD |
10321 | case OPTION_MIPS32R2: |
10322 | file_mips_isa = ISA_MIPS32R2; | |
10323 | break; | |
10324 | ||
5f74bc13 CD |
10325 | case OPTION_MIPS64R2: |
10326 | file_mips_isa = ISA_MIPS64R2; | |
10327 | break; | |
10328 | ||
84ea6cf2 | 10329 | case OPTION_MIPS64: |
316f5878 | 10330 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10331 | break; |
10332 | ||
ec68c924 | 10333 | case OPTION_MTUNE: |
316f5878 RS |
10334 | mips_set_option_string (&mips_tune_string, arg); |
10335 | break; | |
ec68c924 | 10336 | |
316f5878 RS |
10337 | case OPTION_MARCH: |
10338 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10339 | break; |
10340 | ||
10341 | case OPTION_M4650: | |
316f5878 RS |
10342 | mips_set_option_string (&mips_arch_string, "4650"); |
10343 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10344 | break; |
10345 | ||
10346 | case OPTION_NO_M4650: | |
10347 | break; | |
10348 | ||
10349 | case OPTION_M4010: | |
316f5878 RS |
10350 | mips_set_option_string (&mips_arch_string, "4010"); |
10351 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10352 | break; |
10353 | ||
10354 | case OPTION_NO_M4010: | |
10355 | break; | |
10356 | ||
10357 | case OPTION_M4100: | |
316f5878 RS |
10358 | mips_set_option_string (&mips_arch_string, "4100"); |
10359 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10360 | break; |
10361 | ||
10362 | case OPTION_NO_M4100: | |
10363 | break; | |
10364 | ||
252b5132 | 10365 | case OPTION_M3900: |
316f5878 RS |
10366 | mips_set_option_string (&mips_arch_string, "3900"); |
10367 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10368 | break; |
bdaaa2e1 | 10369 | |
252b5132 RH |
10370 | case OPTION_NO_M3900: |
10371 | break; | |
10372 | ||
deec1734 CD |
10373 | case OPTION_MDMX: |
10374 | mips_opts.ase_mdmx = 1; | |
10375 | break; | |
10376 | ||
10377 | case OPTION_NO_MDMX: | |
10378 | mips_opts.ase_mdmx = 0; | |
10379 | break; | |
10380 | ||
252b5132 RH |
10381 | case OPTION_MIPS16: |
10382 | mips_opts.mips16 = 1; | |
b34976b6 | 10383 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10384 | break; |
10385 | ||
10386 | case OPTION_NO_MIPS16: | |
10387 | mips_opts.mips16 = 0; | |
b34976b6 | 10388 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10389 | break; |
10390 | ||
1f25f5d3 CD |
10391 | case OPTION_MIPS3D: |
10392 | mips_opts.ase_mips3d = 1; | |
10393 | break; | |
10394 | ||
10395 | case OPTION_NO_MIPS3D: | |
10396 | mips_opts.ase_mips3d = 0; | |
10397 | break; | |
10398 | ||
d766e8ec RS |
10399 | case OPTION_FIX_VR4120: |
10400 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10401 | break; |
10402 | ||
d766e8ec RS |
10403 | case OPTION_NO_FIX_VR4120: |
10404 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10405 | break; |
10406 | ||
4a6a3df4 AO |
10407 | case OPTION_RELAX_BRANCH: |
10408 | mips_relax_branch = 1; | |
10409 | break; | |
10410 | ||
10411 | case OPTION_NO_RELAX_BRANCH: | |
10412 | mips_relax_branch = 0; | |
10413 | break; | |
10414 | ||
aa6975fb ILT |
10415 | case OPTION_MSHARED: |
10416 | mips_in_shared = TRUE; | |
10417 | break; | |
10418 | ||
10419 | case OPTION_MNO_SHARED: | |
10420 | mips_in_shared = FALSE; | |
10421 | break; | |
10422 | ||
0f074f60 | 10423 | #ifdef OBJ_ELF |
252b5132 RH |
10424 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10425 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10426 | intended to be compatible with Irix 5. */ | |
10427 | case OPTION_CALL_SHARED: | |
10428 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10429 | { | |
10430 | as_bad (_("-call_shared is supported only for ELF format")); | |
10431 | return 0; | |
10432 | } | |
10433 | mips_pic = SVR4_PIC; | |
143d77c5 | 10434 | mips_abicalls = TRUE; |
252b5132 RH |
10435 | if (g_switch_seen && g_switch_value != 0) |
10436 | { | |
10437 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10438 | return 0; | |
10439 | } | |
10440 | g_switch_value = 0; | |
10441 | break; | |
10442 | ||
10443 | case OPTION_NON_SHARED: | |
10444 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10445 | { | |
10446 | as_bad (_("-non_shared is supported only for ELF format")); | |
10447 | return 0; | |
10448 | } | |
10449 | mips_pic = NO_PIC; | |
143d77c5 | 10450 | mips_abicalls = FALSE; |
252b5132 RH |
10451 | break; |
10452 | ||
10453 | /* The -xgot option tells the assembler to use 32 offsets when | |
10454 | accessing the got in SVR4_PIC mode. It is for Irix | |
10455 | compatibility. */ | |
10456 | case OPTION_XGOT: | |
10457 | mips_big_got = 1; | |
10458 | break; | |
0f074f60 | 10459 | #endif /* OBJ_ELF */ |
252b5132 RH |
10460 | |
10461 | case 'G': | |
3e722fb5 | 10462 | if (mips_pic == SVR4_PIC) |
252b5132 | 10463 | { |
3e722fb5 | 10464 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10465 | return 0; |
10466 | } | |
10467 | else | |
10468 | g_switch_value = atoi (arg); | |
10469 | g_switch_seen = 1; | |
10470 | break; | |
10471 | ||
0f074f60 | 10472 | #ifdef OBJ_ELF |
34ba82a8 TS |
10473 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10474 | and -mabi=64. */ | |
252b5132 | 10475 | case OPTION_32: |
34ba82a8 TS |
10476 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10477 | { | |
10478 | as_bad (_("-32 is supported for ELF format only")); | |
10479 | return 0; | |
10480 | } | |
316f5878 | 10481 | mips_abi = O32_ABI; |
252b5132 RH |
10482 | break; |
10483 | ||
e013f690 | 10484 | case OPTION_N32: |
34ba82a8 TS |
10485 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10486 | { | |
10487 | as_bad (_("-n32 is supported for ELF format only")); | |
10488 | return 0; | |
10489 | } | |
316f5878 | 10490 | mips_abi = N32_ABI; |
e013f690 | 10491 | break; |
252b5132 | 10492 | |
e013f690 | 10493 | case OPTION_64: |
34ba82a8 TS |
10494 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10495 | { | |
10496 | as_bad (_("-64 is supported for ELF format only")); | |
10497 | return 0; | |
10498 | } | |
316f5878 | 10499 | mips_abi = N64_ABI; |
e013f690 TS |
10500 | if (! support_64bit_objects()) |
10501 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10502 | break; |
ae948b86 | 10503 | #endif /* OBJ_ELF */ |
252b5132 | 10504 | |
c97ef257 | 10505 | case OPTION_GP32: |
a325df1d | 10506 | file_mips_gp32 = 1; |
c97ef257 AH |
10507 | break; |
10508 | ||
10509 | case OPTION_GP64: | |
a325df1d | 10510 | file_mips_gp32 = 0; |
c97ef257 | 10511 | break; |
252b5132 | 10512 | |
ca4e0257 | 10513 | case OPTION_FP32: |
a325df1d | 10514 | file_mips_fp32 = 1; |
316f5878 RS |
10515 | break; |
10516 | ||
10517 | case OPTION_FP64: | |
10518 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10519 | break; |
10520 | ||
ae948b86 | 10521 | #ifdef OBJ_ELF |
252b5132 | 10522 | case OPTION_MABI: |
34ba82a8 TS |
10523 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10524 | { | |
10525 | as_bad (_("-mabi is supported for ELF format only")); | |
10526 | return 0; | |
10527 | } | |
e013f690 | 10528 | if (strcmp (arg, "32") == 0) |
316f5878 | 10529 | mips_abi = O32_ABI; |
e013f690 | 10530 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10531 | mips_abi = O64_ABI; |
e013f690 | 10532 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10533 | mips_abi = N32_ABI; |
e013f690 TS |
10534 | else if (strcmp (arg, "64") == 0) |
10535 | { | |
316f5878 | 10536 | mips_abi = N64_ABI; |
e013f690 TS |
10537 | if (! support_64bit_objects()) |
10538 | as_fatal (_("No compiled in support for 64 bit object file " | |
10539 | "format")); | |
10540 | } | |
10541 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10542 | mips_abi = EABI_ABI; |
e013f690 | 10543 | else |
da0e507f TS |
10544 | { |
10545 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10546 | return 0; | |
10547 | } | |
252b5132 | 10548 | break; |
e013f690 | 10549 | #endif /* OBJ_ELF */ |
252b5132 | 10550 | |
6b76fefe | 10551 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10552 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10553 | break; |
10554 | ||
9ee72ff1 | 10555 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10556 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10557 | break; |
10558 | ||
ecb4347a DJ |
10559 | #ifdef OBJ_ELF |
10560 | case OPTION_MDEBUG: | |
b34976b6 | 10561 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10562 | break; |
10563 | ||
10564 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10565 | mips_flag_mdebug = FALSE; |
ecb4347a | 10566 | break; |
dcd410fe RO |
10567 | |
10568 | case OPTION_PDR: | |
10569 | mips_flag_pdr = TRUE; | |
10570 | break; | |
10571 | ||
10572 | case OPTION_NO_PDR: | |
10573 | mips_flag_pdr = FALSE; | |
10574 | break; | |
ecb4347a DJ |
10575 | #endif /* OBJ_ELF */ |
10576 | ||
252b5132 RH |
10577 | default: |
10578 | return 0; | |
10579 | } | |
10580 | ||
10581 | return 1; | |
10582 | } | |
316f5878 RS |
10583 | \f |
10584 | /* Set up globals to generate code for the ISA or processor | |
10585 | described by INFO. */ | |
252b5132 | 10586 | |
252b5132 | 10587 | static void |
17a2f251 | 10588 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10589 | { |
316f5878 | 10590 | if (info != 0) |
252b5132 | 10591 | { |
fef14a42 TS |
10592 | file_mips_arch = info->cpu; |
10593 | mips_opts.arch = info->cpu; | |
316f5878 | 10594 | mips_opts.isa = info->isa; |
252b5132 | 10595 | } |
252b5132 RH |
10596 | } |
10597 | ||
252b5132 | 10598 | |
316f5878 | 10599 | /* Likewise for tuning. */ |
252b5132 | 10600 | |
316f5878 | 10601 | static void |
17a2f251 | 10602 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10603 | { |
10604 | if (info != 0) | |
fef14a42 | 10605 | mips_tune = info->cpu; |
316f5878 | 10606 | } |
80cc45a5 | 10607 | |
34ba82a8 | 10608 | |
252b5132 | 10609 | void |
17a2f251 | 10610 | mips_after_parse_args (void) |
e9670677 | 10611 | { |
fef14a42 TS |
10612 | const struct mips_cpu_info *arch_info = 0; |
10613 | const struct mips_cpu_info *tune_info = 0; | |
10614 | ||
e9670677 MR |
10615 | /* GP relative stuff not working for PE */ |
10616 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10617 | && g_switch_value != 0) | |
10618 | { | |
10619 | if (g_switch_seen) | |
10620 | as_bad (_("-G not supported in this configuration.")); | |
10621 | g_switch_value = 0; | |
10622 | } | |
10623 | ||
cac012d6 AO |
10624 | if (mips_abi == NO_ABI) |
10625 | mips_abi = MIPS_DEFAULT_ABI; | |
10626 | ||
22923709 RS |
10627 | /* The following code determines the architecture and register size. |
10628 | Similar code was added to GCC 3.3 (see override_options() in | |
10629 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10630 | as much as possible. */ | |
e9670677 | 10631 | |
316f5878 | 10632 | if (mips_arch_string != 0) |
fef14a42 | 10633 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10634 | |
316f5878 | 10635 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10636 | { |
316f5878 | 10637 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10638 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10639 | the -march selection (if any). */ |
fef14a42 | 10640 | if (arch_info != 0) |
e9670677 | 10641 | { |
316f5878 RS |
10642 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10643 | There's no harm in specifying both as long as the ISA levels | |
10644 | are the same. */ | |
fef14a42 | 10645 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10646 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10647 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10648 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10649 | } |
316f5878 | 10650 | else |
fef14a42 | 10651 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10652 | } |
10653 | ||
fef14a42 TS |
10654 | if (arch_info == 0) |
10655 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10656 | |
fef14a42 | 10657 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10658 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10659 | arch_info->name); |
10660 | ||
10661 | mips_set_architecture (arch_info); | |
10662 | ||
10663 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10664 | if (mips_tune_string != 0) | |
10665 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10666 | |
fef14a42 TS |
10667 | if (tune_info == 0) |
10668 | mips_set_tune (arch_info); | |
10669 | else | |
10670 | mips_set_tune (tune_info); | |
e9670677 | 10671 | |
316f5878 | 10672 | if (file_mips_gp32 >= 0) |
e9670677 | 10673 | { |
316f5878 RS |
10674 | /* The user specified the size of the integer registers. Make sure |
10675 | it agrees with the ABI and ISA. */ | |
10676 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10677 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10678 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10679 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10680 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10681 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10682 | } |
10683 | else | |
10684 | { | |
316f5878 RS |
10685 | /* Infer the integer register size from the ABI and processor. |
10686 | Restrict ourselves to 32-bit registers if that's all the | |
10687 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10688 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10689 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10690 | } |
10691 | ||
316f5878 RS |
10692 | /* ??? GAS treats single-float processors as though they had 64-bit |
10693 | float registers (although it complains when double-precision | |
10694 | instructions are used). As things stand, saying they have 32-bit | |
10695 | registers would lead to spurious "register must be even" messages. | |
10696 | So here we assume float registers are always the same size as | |
10697 | integer ones, unless the user says otherwise. */ | |
10698 | if (file_mips_fp32 < 0) | |
10699 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10700 | |
316f5878 | 10701 | /* End of GCC-shared inference code. */ |
e9670677 | 10702 | |
17a2f251 TS |
10703 | /* This flag is set when we have a 64-bit capable CPU but use only |
10704 | 32-bit wide registers. Note that EABI does not use it. */ | |
10705 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10706 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10707 | || mips_abi == O32_ABI)) | |
316f5878 | 10708 | mips_32bitmode = 1; |
e9670677 MR |
10709 | |
10710 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10711 | as_bad (_("trap exception not supported at ISA 1")); | |
10712 | ||
e9670677 MR |
10713 | /* If the selected architecture includes support for ASEs, enable |
10714 | generation of code for them. */ | |
a4672219 | 10715 | if (mips_opts.mips16 == -1) |
fef14a42 | 10716 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10717 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10718 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10719 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10720 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10721 | |
e9670677 | 10722 | file_mips_isa = mips_opts.isa; |
a4672219 | 10723 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10724 | file_ase_mips3d = mips_opts.ase_mips3d; |
10725 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10726 | mips_opts.gp32 = file_mips_gp32; | |
10727 | mips_opts.fp32 = file_mips_fp32; | |
10728 | ||
ecb4347a DJ |
10729 | if (mips_flag_mdebug < 0) |
10730 | { | |
10731 | #ifdef OBJ_MAYBE_ECOFF | |
10732 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10733 | mips_flag_mdebug = 1; | |
10734 | else | |
10735 | #endif /* OBJ_MAYBE_ECOFF */ | |
10736 | mips_flag_mdebug = 0; | |
10737 | } | |
e9670677 MR |
10738 | } |
10739 | \f | |
10740 | void | |
17a2f251 | 10741 | mips_init_after_args (void) |
252b5132 RH |
10742 | { |
10743 | /* initialize opcodes */ | |
10744 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10745 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10746 | } |
10747 | ||
10748 | long | |
17a2f251 | 10749 | md_pcrel_from (fixS *fixP) |
252b5132 | 10750 | { |
a7ebbfdf TS |
10751 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10752 | switch (fixP->fx_r_type) | |
10753 | { | |
10754 | case BFD_RELOC_16_PCREL_S2: | |
10755 | case BFD_RELOC_MIPS_JMP: | |
10756 | /* Return the address of the delay slot. */ | |
10757 | return addr + 4; | |
10758 | default: | |
10759 | return addr; | |
10760 | } | |
252b5132 RH |
10761 | } |
10762 | ||
252b5132 RH |
10763 | /* This is called before the symbol table is processed. In order to |
10764 | work with gcc when using mips-tfile, we must keep all local labels. | |
10765 | However, in other cases, we want to discard them. If we were | |
10766 | called with -g, but we didn't see any debugging information, it may | |
10767 | mean that gcc is smuggling debugging information through to | |
10768 | mips-tfile, in which case we must generate all local labels. */ | |
10769 | ||
10770 | void | |
17a2f251 | 10771 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10772 | { |
10773 | #ifndef NO_ECOFF_DEBUGGING | |
10774 | if (ECOFF_DEBUGGING | |
10775 | && mips_debug != 0 | |
10776 | && ! ecoff_debugging_seen) | |
10777 | flag_keep_locals = 1; | |
10778 | #endif | |
10779 | } | |
10780 | ||
3b91255e RS |
10781 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10782 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10783 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10784 | relocation operators. | |
10785 | ||
10786 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10787 | expression if: | |
10788 | ||
10789 | (a) it refers to the same symbol; and | |
10790 | (b) the offset applied in the %lo() expression is no lower than | |
10791 | the offset applied in the %got() or %hi(). | |
10792 | ||
10793 | (b) allows us to cope with code like: | |
10794 | ||
10795 | lui $4,%hi(foo) | |
10796 | lh $4,%lo(foo+2)($4) | |
10797 | ||
10798 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10799 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10800 | the high 16 bits. | |
10801 | ||
10802 | When several %lo()s match a particular %got() or %hi(), we use the | |
10803 | following rules to distinguish them: | |
10804 | ||
10805 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10806 | higher offsets. | |
10807 | ||
10808 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10809 | that already have a matching %got() or %hi(). | |
10810 | ||
10811 | (3) later %lo()s are better than earlier %lo()s. | |
10812 | ||
10813 | These rules are applied in order. | |
10814 | ||
10815 | (1) means, among other things, that %lo()s with identical offsets are | |
10816 | chosen if they exist. | |
10817 | ||
10818 | (2) means that we won't associate several high-part relocations with | |
10819 | the same low-part relocation unless there's no alternative. Having | |
10820 | several high parts for the same low part is a GNU extension; this rule | |
10821 | allows careful users to avoid it. | |
10822 | ||
10823 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10824 | with the last high-part relocation being at the front of the list. | |
10825 | It therefore makes sense to choose the last matching low-part | |
10826 | relocation, all other things being equal. It's also easier | |
10827 | to code that way. */ | |
252b5132 RH |
10828 | |
10829 | void | |
17a2f251 | 10830 | mips_frob_file (void) |
252b5132 RH |
10831 | { |
10832 | struct mips_hi_fixup *l; | |
10833 | ||
10834 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10835 | { | |
10836 | segment_info_type *seginfo; | |
3b91255e RS |
10837 | bfd_boolean matched_lo_p; |
10838 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10839 | |
5919d012 | 10840 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10841 | |
5919d012 RS |
10842 | /* If a GOT16 relocation turns out to be against a global symbol, |
10843 | there isn't supposed to be a matching LO. */ | |
10844 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10845 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10846 | continue; | |
10847 | ||
10848 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10849 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10850 | continue; |
10851 | ||
252b5132 | 10852 | seginfo = seg_info (l->seg); |
252b5132 | 10853 | |
3b91255e RS |
10854 | /* Set HI_POS to the position of this relocation in the chain. |
10855 | Set LO_POS to the position of the chosen low-part relocation. | |
10856 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10857 | relocation that matches an immediately-preceding high-part | |
10858 | relocation. */ | |
10859 | hi_pos = NULL; | |
10860 | lo_pos = NULL; | |
10861 | matched_lo_p = FALSE; | |
10862 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10863 | { | |
10864 | if (*pos == l->fixp) | |
10865 | hi_pos = pos; | |
10866 | ||
10867 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10868 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10869 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10870 | && (lo_pos == NULL | |
10871 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10872 | || (!matched_lo_p | |
10873 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10874 | lo_pos = pos; | |
10875 | ||
10876 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10877 | && fixup_has_matching_lo_p (*pos)); | |
10878 | } | |
10879 | ||
10880 | /* If we found a match, remove the high-part relocation from its | |
10881 | current position and insert it before the low-part relocation. | |
10882 | Make the offsets match so that fixup_has_matching_lo_p() | |
10883 | will return true. | |
10884 | ||
10885 | We don't warn about unmatched high-part relocations since some | |
10886 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10887 | instructions. */ | |
10888 | if (lo_pos != NULL) | |
10889 | { | |
10890 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10891 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10892 | { |
3b91255e RS |
10893 | *hi_pos = l->fixp->fx_next; |
10894 | l->fixp->fx_next = *lo_pos; | |
10895 | *lo_pos = l->fixp; | |
252b5132 | 10896 | } |
252b5132 RH |
10897 | } |
10898 | } | |
10899 | } | |
10900 | ||
3e722fb5 | 10901 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10902 | We have to prevent gas from dropping them. */ |
252b5132 | 10903 | |
252b5132 | 10904 | int |
17a2f251 | 10905 | mips_force_relocation (fixS *fixp) |
252b5132 | 10906 | { |
ae6063d4 | 10907 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10908 | return 1; |
10909 | ||
f6688943 TS |
10910 | if (HAVE_NEWABI |
10911 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10912 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10913 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10914 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10915 | return 1; | |
10916 | ||
3e722fb5 | 10917 | return 0; |
252b5132 RH |
10918 | } |
10919 | ||
45f8dfe8 AO |
10920 | /* This hook is called before a fix is simplified. We don't really |
10921 | decide whether to skip a fix here. Rather, we turn global symbols | |
10922 | used as branch targets into local symbols, such that they undergo | |
10923 | simplification. We can only do this if the symbol is defined and | |
10924 | it is in the same section as the branch. If this doesn't hold, we | |
10925 | emit a better error message than just saying the relocation is not | |
10926 | valid for the selected object format. | |
10927 | ||
10928 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10929 | segment in which the fix up occurs. The return value should be | |
10930 | non-zero to indicate the fix-up is valid for further | |
10931 | simplifications. */ | |
10932 | ||
10933 | int | |
17a2f251 | 10934 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10935 | { |
10936 | /* There's a lot of discussion on whether it should be possible to | |
10937 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10938 | seems to be that it can, but gas/bfd are very broken in creating | |
10939 | RELA relocations for this, so for now we only accept branches to | |
10940 | symbols in the same section. Anything else is of dubious value, | |
10941 | since there's no guarantee that at link time the symbol would be | |
10942 | in range. Even for branches to local symbols this is arguably | |
10943 | wrong, since it we assume the symbol is not going to be | |
10944 | overridden, which should be possible per ELF library semantics, | |
10945 | but then, there isn't a dynamic relocation that could be used to | |
10946 | this effect, and the target would likely be out of range as well. | |
10947 | ||
10948 | Unfortunately, it seems that there is too much code out there | |
10949 | that relies on branches to symbols that are global to be resolved | |
10950 | as if they were local, like the IRIX tools do, so we do it as | |
10951 | well, but with a warning so that people are reminded to fix their | |
10952 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10953 | targets, this entire block should go away (and probably the | |
10954 | whole function). */ | |
10955 | ||
10956 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10957 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10958 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10959 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10960 | && fixP->fx_addsy) | |
10961 | { | |
10962 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10963 | { | |
10964 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10965 | _("Cannot branch to undefined symbol.")); | |
10966 | /* Avoid any further errors about this fixup. */ | |
10967 | fixP->fx_done = 1; | |
10968 | } | |
10969 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10970 | { | |
10971 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10972 | _("Cannot branch to symbol in another section.")); | |
10973 | fixP->fx_done = 1; | |
10974 | } | |
10975 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10976 | { | |
10977 | symbolS *sym = fixP->fx_addsy; | |
10978 | ||
115695a8 CD |
10979 | if (mips_pic == SVR4_PIC) |
10980 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10981 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10982 | |
10983 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10984 | S_GET_SEGMENT (sym), | |
10985 | S_GET_VALUE (sym), | |
10986 | symbol_get_frag (sym)); | |
10987 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10988 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10989 | assert (symbol_resolved_p (sym)); | |
10990 | symbol_mark_resolved (fixP->fx_addsy); | |
10991 | } | |
10992 | } | |
10993 | ||
10994 | return 1; | |
10995 | } | |
10996 | ||
252b5132 RH |
10997 | /* Apply a fixup to the object file. */ |
10998 | ||
94f592af | 10999 | void |
17a2f251 | 11000 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11001 | { |
874e8986 | 11002 | bfd_byte *buf; |
98aa84af | 11003 | long insn; |
a7ebbfdf | 11004 | reloc_howto_type *howto; |
252b5132 | 11005 | |
a7ebbfdf TS |
11006 | /* We ignore generic BFD relocations we don't know about. */ |
11007 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11008 | if (! howto) | |
11009 | return; | |
65551fa4 | 11010 | |
252b5132 RH |
11011 | assert (fixP->fx_size == 4 |
11012 | || fixP->fx_r_type == BFD_RELOC_16 | |
11013 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11014 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11015 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11016 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11017 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11018 | |
a7ebbfdf | 11019 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11020 | |
3e722fb5 | 11021 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
11022 | |
11023 | /* Don't treat parts of a composite relocation as done. There are two | |
11024 | reasons for this: | |
11025 | ||
11026 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11027 | should nevertheless be emitted if the first part is. | |
11028 | ||
11029 | (2) In normal usage, composite relocations are never assembly-time | |
11030 | constants. The easiest way of dealing with the pathological | |
11031 | exceptions is to generate a relocation against STN_UNDEF and | |
11032 | leave everything up to the linker. */ | |
11033 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
11034 | fixP->fx_done = 1; |
11035 | ||
11036 | switch (fixP->fx_r_type) | |
11037 | { | |
11038 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11039 | case BFD_RELOC_MIPS_SHIFT5: |
11040 | case BFD_RELOC_MIPS_SHIFT6: | |
11041 | case BFD_RELOC_MIPS_GOT_DISP: | |
11042 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11043 | case BFD_RELOC_MIPS_GOT_OFST: | |
11044 | case BFD_RELOC_MIPS_SUB: | |
11045 | case BFD_RELOC_MIPS_INSERT_A: | |
11046 | case BFD_RELOC_MIPS_INSERT_B: | |
11047 | case BFD_RELOC_MIPS_DELETE: | |
11048 | case BFD_RELOC_MIPS_HIGHEST: | |
11049 | case BFD_RELOC_MIPS_HIGHER: | |
11050 | case BFD_RELOC_MIPS_SCN_DISP: | |
11051 | case BFD_RELOC_MIPS_REL16: | |
11052 | case BFD_RELOC_MIPS_RELGOT: | |
11053 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11054 | case BFD_RELOC_HI16: |
11055 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11056 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11057 | case BFD_RELOC_MIPS_LITERAL: |
11058 | case BFD_RELOC_MIPS_CALL16: | |
11059 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11060 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11061 | case BFD_RELOC_MIPS_GOT_HI16: |
11062 | case BFD_RELOC_MIPS_GOT_LO16: | |
11063 | case BFD_RELOC_MIPS_CALL_HI16: | |
11064 | case BFD_RELOC_MIPS_CALL_LO16: | |
11065 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11066 | case BFD_RELOC_MIPS16_HI16: |
11067 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 11068 | assert (! fixP->fx_pcrel); |
252b5132 RH |
11069 | /* Nothing needed to do. The value comes from the reloc entry */ |
11070 | break; | |
11071 | ||
11072 | case BFD_RELOC_MIPS16_JMP: | |
11073 | /* We currently always generate a reloc against a symbol, which | |
11074 | means that we don't want an addend even if the symbol is | |
11075 | defined. */ | |
a7ebbfdf | 11076 | *valP = 0; |
252b5132 RH |
11077 | break; |
11078 | ||
252b5132 RH |
11079 | case BFD_RELOC_64: |
11080 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11081 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11082 | if (fixP->fx_done) |
252b5132 RH |
11083 | { |
11084 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11085 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11086 | else |
11087 | { | |
a7ebbfdf | 11088 | valueT hiv; |
252b5132 | 11089 | |
a7ebbfdf | 11090 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11091 | hiv = 0xffffffff; |
11092 | else | |
11093 | hiv = 0; | |
a7ebbfdf TS |
11094 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11095 | *valP, 4); | |
11096 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11097 | hiv, 4); | |
252b5132 RH |
11098 | } |
11099 | } | |
11100 | break; | |
11101 | ||
056350c6 | 11102 | case BFD_RELOC_RVA: |
252b5132 RH |
11103 | case BFD_RELOC_32: |
11104 | /* If we are deleting this reloc entry, we must fill in the | |
11105 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11106 | resolved when it appears but is later defined. */ |
11107 | if (fixP->fx_done) | |
a7ebbfdf | 11108 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11109 | break; |
11110 | ||
11111 | case BFD_RELOC_16: | |
11112 | /* If we are deleting this reloc entry, we must fill in the | |
11113 | value now. */ | |
252b5132 | 11114 | if (fixP->fx_done) |
a7ebbfdf | 11115 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11116 | break; |
11117 | ||
11118 | case BFD_RELOC_LO16: | |
d6f16593 | 11119 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11120 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11121 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11122 | /* When handling an embedded PIC switch statement, we can wind |
11123 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11124 | if (fixP->fx_done) | |
11125 | { | |
a7ebbfdf | 11126 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11127 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11128 | _("relocation overflow")); | |
252b5132 RH |
11129 | if (target_big_endian) |
11130 | buf += 2; | |
17a2f251 | 11131 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11132 | } |
11133 | break; | |
11134 | ||
11135 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11136 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11137 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11138 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11139 | |
252b5132 RH |
11140 | /* |
11141 | * We need to save the bits in the instruction since fixup_segment() | |
11142 | * might be deleting the relocation entry (i.e., a branch within | |
11143 | * the current segment). | |
11144 | */ | |
a7ebbfdf | 11145 | if (! fixP->fx_done) |
bb2d6cd7 | 11146 | break; |
252b5132 RH |
11147 | |
11148 | /* update old instruction data */ | |
252b5132 RH |
11149 | if (target_big_endian) |
11150 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11151 | else | |
11152 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11153 | ||
a7ebbfdf TS |
11154 | if (*valP + 0x20000 <= 0x3ffff) |
11155 | { | |
11156 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11157 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11158 | } |
11159 | else if (mips_pic == NO_PIC | |
11160 | && fixP->fx_done | |
11161 | && fixP->fx_frag->fr_address >= text_section->vma | |
11162 | && (fixP->fx_frag->fr_address | |
587aac4e | 11163 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11164 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11165 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11166 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11167 | { |
11168 | /* The branch offset is too large. If this is an | |
11169 | unconditional branch, and we are not generating PIC code, | |
11170 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11171 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11172 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11173 | else |
a7ebbfdf TS |
11174 | insn = 0x08000000; /* j */ |
11175 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11176 | fixP->fx_done = 0; | |
11177 | fixP->fx_addsy = section_symbol (text_section); | |
11178 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11179 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11180 | } |
11181 | else | |
11182 | { | |
11183 | /* If we got here, we have branch-relaxation disabled, | |
11184 | and there's nothing we can do to fix this instruction | |
11185 | without turning it into a longer sequence. */ | |
11186 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11187 | _("Branch out of range")); | |
252b5132 | 11188 | } |
252b5132 RH |
11189 | break; |
11190 | ||
11191 | case BFD_RELOC_VTABLE_INHERIT: | |
11192 | fixP->fx_done = 0; | |
11193 | if (fixP->fx_addsy | |
11194 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11195 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11196 | S_SET_WEAK (fixP->fx_addsy); | |
11197 | break; | |
11198 | ||
11199 | case BFD_RELOC_VTABLE_ENTRY: | |
11200 | fixP->fx_done = 0; | |
11201 | break; | |
11202 | ||
11203 | default: | |
11204 | internalError (); | |
11205 | } | |
a7ebbfdf TS |
11206 | |
11207 | /* Remember value for tc_gen_reloc. */ | |
11208 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11209 | } |
11210 | ||
252b5132 | 11211 | static symbolS * |
17a2f251 | 11212 | get_symbol (void) |
252b5132 RH |
11213 | { |
11214 | int c; | |
11215 | char *name; | |
11216 | symbolS *p; | |
11217 | ||
11218 | name = input_line_pointer; | |
11219 | c = get_symbol_end (); | |
11220 | p = (symbolS *) symbol_find_or_make (name); | |
11221 | *input_line_pointer = c; | |
11222 | return p; | |
11223 | } | |
11224 | ||
11225 | /* Align the current frag to a given power of two. The MIPS assembler | |
11226 | also automatically adjusts any preceding label. */ | |
11227 | ||
11228 | static void | |
17a2f251 | 11229 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11230 | { |
b34976b6 | 11231 | mips_emit_delays (FALSE); |
252b5132 RH |
11232 | frag_align (to, fill, 0); |
11233 | record_alignment (now_seg, to); | |
11234 | if (label != NULL) | |
11235 | { | |
11236 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11237 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11238 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11239 | } | |
11240 | } | |
11241 | ||
11242 | /* Align to a given power of two. .align 0 turns off the automatic | |
11243 | alignment used by the data creating pseudo-ops. */ | |
11244 | ||
11245 | static void | |
17a2f251 | 11246 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11247 | { |
11248 | register int temp; | |
11249 | register long temp_fill; | |
11250 | long max_alignment = 15; | |
11251 | ||
11252 | /* | |
11253 | ||
67c1ffbe | 11254 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11255 | to the aligned address. |
11256 | o It's not documented but auto alignment is reinstated by | |
11257 | a .align pseudo instruction. | |
11258 | o Note also that after auto alignment is turned off the mips assembler | |
11259 | issues an error on attempt to assemble an improperly aligned data item. | |
11260 | We don't. | |
11261 | ||
11262 | */ | |
11263 | ||
11264 | temp = get_absolute_expression (); | |
11265 | if (temp > max_alignment) | |
11266 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11267 | else if (temp < 0) | |
11268 | { | |
11269 | as_warn (_("Alignment negative: 0 assumed.")); | |
11270 | temp = 0; | |
11271 | } | |
11272 | if (*input_line_pointer == ',') | |
11273 | { | |
f9419b05 | 11274 | ++input_line_pointer; |
252b5132 RH |
11275 | temp_fill = get_absolute_expression (); |
11276 | } | |
11277 | else | |
11278 | temp_fill = 0; | |
11279 | if (temp) | |
11280 | { | |
11281 | auto_align = 1; | |
11282 | mips_align (temp, (int) temp_fill, | |
11283 | insn_labels != NULL ? insn_labels->label : NULL); | |
11284 | } | |
11285 | else | |
11286 | { | |
11287 | auto_align = 0; | |
11288 | } | |
11289 | ||
11290 | demand_empty_rest_of_line (); | |
11291 | } | |
11292 | ||
11293 | void | |
17a2f251 | 11294 | mips_flush_pending_output (void) |
252b5132 | 11295 | { |
b34976b6 | 11296 | mips_emit_delays (FALSE); |
252b5132 RH |
11297 | mips_clear_insn_labels (); |
11298 | } | |
11299 | ||
11300 | static void | |
17a2f251 | 11301 | s_change_sec (int sec) |
252b5132 RH |
11302 | { |
11303 | segT seg; | |
11304 | ||
252b5132 RH |
11305 | #ifdef OBJ_ELF |
11306 | /* The ELF backend needs to know that we are changing sections, so | |
11307 | that .previous works correctly. We could do something like check | |
b6ff326e | 11308 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11309 | as it would not be appropriate to use it in the section changing |
11310 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11311 | This should be cleaner, somehow. */ | |
11312 | obj_elf_section_change_hook (); | |
11313 | #endif | |
11314 | ||
b34976b6 | 11315 | mips_emit_delays (FALSE); |
252b5132 RH |
11316 | switch (sec) |
11317 | { | |
11318 | case 't': | |
11319 | s_text (0); | |
11320 | break; | |
11321 | case 'd': | |
11322 | s_data (0); | |
11323 | break; | |
11324 | case 'b': | |
11325 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11326 | demand_empty_rest_of_line (); | |
11327 | break; | |
11328 | ||
11329 | case 'r': | |
4d0d148d TS |
11330 | seg = subseg_new (RDATA_SECTION_NAME, |
11331 | (subsegT) get_absolute_expression ()); | |
11332 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11333 | { |
4d0d148d TS |
11334 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11335 | | SEC_READONLY | SEC_RELOC | |
11336 | | SEC_DATA)); | |
11337 | if (strcmp (TARGET_OS, "elf") != 0) | |
11338 | record_alignment (seg, 4); | |
252b5132 | 11339 | } |
4d0d148d | 11340 | demand_empty_rest_of_line (); |
252b5132 RH |
11341 | break; |
11342 | ||
11343 | case 's': | |
4d0d148d TS |
11344 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11345 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11346 | { |
4d0d148d TS |
11347 | bfd_set_section_flags (stdoutput, seg, |
11348 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11349 | if (strcmp (TARGET_OS, "elf") != 0) | |
11350 | record_alignment (seg, 4); | |
252b5132 | 11351 | } |
4d0d148d TS |
11352 | demand_empty_rest_of_line (); |
11353 | break; | |
252b5132 RH |
11354 | } |
11355 | ||
11356 | auto_align = 1; | |
11357 | } | |
b34976b6 | 11358 | |
cca86cc8 | 11359 | void |
17a2f251 | 11360 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11361 | { |
7ed4a06a | 11362 | #ifdef OBJ_ELF |
cca86cc8 SC |
11363 | char *section_name; |
11364 | char c; | |
684022ea | 11365 | char next_c = 0; |
cca86cc8 SC |
11366 | int section_type; |
11367 | int section_flag; | |
11368 | int section_entry_size; | |
11369 | int section_alignment; | |
b34976b6 | 11370 | |
7ed4a06a TS |
11371 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11372 | return; | |
11373 | ||
cca86cc8 SC |
11374 | section_name = input_line_pointer; |
11375 | c = get_symbol_end (); | |
a816d1ed AO |
11376 | if (c) |
11377 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11378 | |
4cf0dd0d TS |
11379 | /* Do we have .section Name<,"flags">? */ |
11380 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11381 | { |
4cf0dd0d TS |
11382 | /* just after name is now '\0'. */ |
11383 | *input_line_pointer = c; | |
cca86cc8 SC |
11384 | input_line_pointer = section_name; |
11385 | obj_elf_section (ignore); | |
11386 | return; | |
11387 | } | |
11388 | input_line_pointer++; | |
11389 | ||
11390 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11391 | if (c == ',') | |
11392 | section_type = get_absolute_expression (); | |
11393 | else | |
11394 | section_type = 0; | |
11395 | if (*input_line_pointer++ == ',') | |
11396 | section_flag = get_absolute_expression (); | |
11397 | else | |
11398 | section_flag = 0; | |
11399 | if (*input_line_pointer++ == ',') | |
11400 | section_entry_size = get_absolute_expression (); | |
11401 | else | |
11402 | section_entry_size = 0; | |
11403 | if (*input_line_pointer++ == ',') | |
11404 | section_alignment = get_absolute_expression (); | |
11405 | else | |
11406 | section_alignment = 0; | |
11407 | ||
a816d1ed AO |
11408 | section_name = xstrdup (section_name); |
11409 | ||
8ab8a5c8 RS |
11410 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11411 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11412 | traditionally had to fall back on the more common @progbits instead. | |
11413 | ||
11414 | There's nothing really harmful in this, since bfd will correct | |
11415 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11416 | means that, for backwards compatibiltiy, the special_section entries | |
11417 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11418 | ||
11419 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11420 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11421 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11422 | generic type-checking code. */ | |
11423 | if (section_type == SHT_MIPS_DWARF) | |
11424 | section_type = SHT_PROGBITS; | |
11425 | ||
cca86cc8 SC |
11426 | obj_elf_change_section (section_name, section_type, section_flag, |
11427 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11428 | |
11429 | if (now_seg->name != section_name) | |
11430 | free (section_name); | |
7ed4a06a | 11431 | #endif /* OBJ_ELF */ |
cca86cc8 | 11432 | } |
252b5132 RH |
11433 | |
11434 | void | |
17a2f251 | 11435 | mips_enable_auto_align (void) |
252b5132 RH |
11436 | { |
11437 | auto_align = 1; | |
11438 | } | |
11439 | ||
11440 | static void | |
17a2f251 | 11441 | s_cons (int log_size) |
252b5132 RH |
11442 | { |
11443 | symbolS *label; | |
11444 | ||
11445 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11446 | mips_emit_delays (FALSE); |
252b5132 RH |
11447 | if (log_size > 0 && auto_align) |
11448 | mips_align (log_size, 0, label); | |
11449 | mips_clear_insn_labels (); | |
11450 | cons (1 << log_size); | |
11451 | } | |
11452 | ||
11453 | static void | |
17a2f251 | 11454 | s_float_cons (int type) |
252b5132 RH |
11455 | { |
11456 | symbolS *label; | |
11457 | ||
11458 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11459 | ||
b34976b6 | 11460 | mips_emit_delays (FALSE); |
252b5132 RH |
11461 | |
11462 | if (auto_align) | |
49309057 ILT |
11463 | { |
11464 | if (type == 'd') | |
11465 | mips_align (3, 0, label); | |
11466 | else | |
11467 | mips_align (2, 0, label); | |
11468 | } | |
252b5132 RH |
11469 | |
11470 | mips_clear_insn_labels (); | |
11471 | ||
11472 | float_cons (type); | |
11473 | } | |
11474 | ||
11475 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11476 | permitted to say | |
11477 | .globl foo .text | |
11478 | where foo is an undefined symbol, to mean that foo should be | |
11479 | considered to be the address of a function. */ | |
11480 | ||
11481 | static void | |
17a2f251 | 11482 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11483 | { |
11484 | char *name; | |
11485 | int c; | |
11486 | symbolS *symbolP; | |
11487 | flagword flag; | |
11488 | ||
11489 | name = input_line_pointer; | |
11490 | c = get_symbol_end (); | |
11491 | symbolP = symbol_find_or_make (name); | |
11492 | *input_line_pointer = c; | |
11493 | SKIP_WHITESPACE (); | |
11494 | ||
11495 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11496 | being a function is apparently labelled as being an object. */ | |
11497 | flag = BSF_OBJECT; | |
11498 | ||
11499 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11500 | { | |
11501 | char *secname; | |
11502 | asection *sec; | |
11503 | ||
11504 | secname = input_line_pointer; | |
11505 | c = get_symbol_end (); | |
11506 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11507 | if (sec == NULL) | |
11508 | as_bad (_("%s: no such section"), secname); | |
11509 | *input_line_pointer = c; | |
11510 | ||
11511 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11512 | flag = BSF_FUNCTION; | |
11513 | } | |
11514 | ||
49309057 | 11515 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11516 | |
11517 | S_SET_EXTERNAL (symbolP); | |
11518 | demand_empty_rest_of_line (); | |
11519 | } | |
11520 | ||
11521 | static void | |
17a2f251 | 11522 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11523 | { |
11524 | char *opt; | |
11525 | char c; | |
11526 | ||
11527 | opt = input_line_pointer; | |
11528 | c = get_symbol_end (); | |
11529 | ||
11530 | if (*opt == 'O') | |
11531 | { | |
11532 | /* FIXME: What does this mean? */ | |
11533 | } | |
11534 | else if (strncmp (opt, "pic", 3) == 0) | |
11535 | { | |
11536 | int i; | |
11537 | ||
11538 | i = atoi (opt + 3); | |
11539 | if (i == 0) | |
11540 | mips_pic = NO_PIC; | |
11541 | else if (i == 2) | |
143d77c5 | 11542 | { |
252b5132 | 11543 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11544 | mips_abicalls = TRUE; |
11545 | } | |
252b5132 RH |
11546 | else |
11547 | as_bad (_(".option pic%d not supported"), i); | |
11548 | ||
4d0d148d | 11549 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11550 | { |
11551 | if (g_switch_seen && g_switch_value != 0) | |
11552 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11553 | g_switch_value = 0; | |
11554 | bfd_set_gp_size (stdoutput, 0); | |
11555 | } | |
11556 | } | |
11557 | else | |
11558 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11559 | ||
11560 | *input_line_pointer = c; | |
11561 | demand_empty_rest_of_line (); | |
11562 | } | |
11563 | ||
11564 | /* This structure is used to hold a stack of .set values. */ | |
11565 | ||
e972090a NC |
11566 | struct mips_option_stack |
11567 | { | |
252b5132 RH |
11568 | struct mips_option_stack *next; |
11569 | struct mips_set_options options; | |
11570 | }; | |
11571 | ||
11572 | static struct mips_option_stack *mips_opts_stack; | |
11573 | ||
11574 | /* Handle the .set pseudo-op. */ | |
11575 | ||
11576 | static void | |
17a2f251 | 11577 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11578 | { |
11579 | char *name = input_line_pointer, ch; | |
11580 | ||
11581 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11582 | ++input_line_pointer; |
252b5132 RH |
11583 | ch = *input_line_pointer; |
11584 | *input_line_pointer = '\0'; | |
11585 | ||
11586 | if (strcmp (name, "reorder") == 0) | |
11587 | { | |
11588 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11589 | { | |
11590 | /* If we still have pending nops, we can discard them. The | |
11591 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11592 | needed. */ |
252b5132 RH |
11593 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11594 | * (mips_opts.mips16 ? 2 : 4)); | |
11595 | prev_nop_frag = NULL; | |
11596 | } | |
11597 | mips_opts.noreorder = 0; | |
11598 | } | |
11599 | else if (strcmp (name, "noreorder") == 0) | |
11600 | { | |
b34976b6 | 11601 | mips_emit_delays (TRUE); |
252b5132 RH |
11602 | mips_opts.noreorder = 1; |
11603 | mips_any_noreorder = 1; | |
11604 | } | |
11605 | else if (strcmp (name, "at") == 0) | |
11606 | { | |
11607 | mips_opts.noat = 0; | |
11608 | } | |
11609 | else if (strcmp (name, "noat") == 0) | |
11610 | { | |
11611 | mips_opts.noat = 1; | |
11612 | } | |
11613 | else if (strcmp (name, "macro") == 0) | |
11614 | { | |
11615 | mips_opts.warn_about_macros = 0; | |
11616 | } | |
11617 | else if (strcmp (name, "nomacro") == 0) | |
11618 | { | |
11619 | if (mips_opts.noreorder == 0) | |
11620 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11621 | mips_opts.warn_about_macros = 1; | |
11622 | } | |
11623 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11624 | { | |
11625 | mips_opts.nomove = 0; | |
11626 | } | |
11627 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11628 | { | |
11629 | mips_opts.nomove = 1; | |
11630 | } | |
11631 | else if (strcmp (name, "bopt") == 0) | |
11632 | { | |
11633 | mips_opts.nobopt = 0; | |
11634 | } | |
11635 | else if (strcmp (name, "nobopt") == 0) | |
11636 | { | |
11637 | mips_opts.nobopt = 1; | |
11638 | } | |
11639 | else if (strcmp (name, "mips16") == 0 | |
11640 | || strcmp (name, "MIPS-16") == 0) | |
11641 | mips_opts.mips16 = 1; | |
11642 | else if (strcmp (name, "nomips16") == 0 | |
11643 | || strcmp (name, "noMIPS-16") == 0) | |
11644 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11645 | else if (strcmp (name, "mips3d") == 0) |
11646 | mips_opts.ase_mips3d = 1; | |
11647 | else if (strcmp (name, "nomips3d") == 0) | |
11648 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11649 | else if (strcmp (name, "mdmx") == 0) |
11650 | mips_opts.ase_mdmx = 1; | |
11651 | else if (strcmp (name, "nomdmx") == 0) | |
11652 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11653 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11654 | { |
af7ee8bf | 11655 | int reset = 0; |
252b5132 | 11656 | |
1a2c1fad CD |
11657 | /* Permit the user to change the ISA and architecture on the fly. |
11658 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11659 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11660 | { |
11661 | reset = 1; | |
11662 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11663 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11664 | } |
11665 | else if (strncmp (name, "arch=", 5) == 0) | |
11666 | { | |
11667 | const struct mips_cpu_info *p; | |
11668 | ||
11669 | p = mips_parse_cpu("internal use", name + 5); | |
11670 | if (!p) | |
11671 | as_bad (_("unknown architecture %s"), name + 5); | |
11672 | else | |
11673 | { | |
11674 | mips_opts.arch = p->cpu; | |
11675 | mips_opts.isa = p->isa; | |
11676 | } | |
11677 | } | |
81a21e38 TS |
11678 | else if (strncmp (name, "mips", 4) == 0) |
11679 | { | |
11680 | const struct mips_cpu_info *p; | |
11681 | ||
11682 | p = mips_parse_cpu("internal use", name); | |
11683 | if (!p) | |
11684 | as_bad (_("unknown ISA level %s"), name + 4); | |
11685 | else | |
11686 | { | |
11687 | mips_opts.arch = p->cpu; | |
11688 | mips_opts.isa = p->isa; | |
11689 | } | |
11690 | } | |
af7ee8bf | 11691 | else |
81a21e38 | 11692 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11693 | |
11694 | switch (mips_opts.isa) | |
98d3f06f KH |
11695 | { |
11696 | case 0: | |
98d3f06f | 11697 | break; |
af7ee8bf CD |
11698 | case ISA_MIPS1: |
11699 | case ISA_MIPS2: | |
11700 | case ISA_MIPS32: | |
11701 | case ISA_MIPS32R2: | |
98d3f06f KH |
11702 | mips_opts.gp32 = 1; |
11703 | mips_opts.fp32 = 1; | |
11704 | break; | |
af7ee8bf CD |
11705 | case ISA_MIPS3: |
11706 | case ISA_MIPS4: | |
11707 | case ISA_MIPS5: | |
11708 | case ISA_MIPS64: | |
5f74bc13 | 11709 | case ISA_MIPS64R2: |
98d3f06f KH |
11710 | mips_opts.gp32 = 0; |
11711 | mips_opts.fp32 = 0; | |
11712 | break; | |
11713 | default: | |
11714 | as_bad (_("unknown ISA level %s"), name + 4); | |
11715 | break; | |
11716 | } | |
af7ee8bf | 11717 | if (reset) |
98d3f06f | 11718 | { |
af7ee8bf CD |
11719 | mips_opts.gp32 = file_mips_gp32; |
11720 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11721 | } |
252b5132 RH |
11722 | } |
11723 | else if (strcmp (name, "autoextend") == 0) | |
11724 | mips_opts.noautoextend = 0; | |
11725 | else if (strcmp (name, "noautoextend") == 0) | |
11726 | mips_opts.noautoextend = 1; | |
11727 | else if (strcmp (name, "push") == 0) | |
11728 | { | |
11729 | struct mips_option_stack *s; | |
11730 | ||
11731 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11732 | s->next = mips_opts_stack; | |
11733 | s->options = mips_opts; | |
11734 | mips_opts_stack = s; | |
11735 | } | |
11736 | else if (strcmp (name, "pop") == 0) | |
11737 | { | |
11738 | struct mips_option_stack *s; | |
11739 | ||
11740 | s = mips_opts_stack; | |
11741 | if (s == NULL) | |
11742 | as_bad (_(".set pop with no .set push")); | |
11743 | else | |
11744 | { | |
11745 | /* If we're changing the reorder mode we need to handle | |
11746 | delay slots correctly. */ | |
11747 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11748 | mips_emit_delays (TRUE); |
252b5132 RH |
11749 | else if (! s->options.noreorder && mips_opts.noreorder) |
11750 | { | |
11751 | if (prev_nop_frag != NULL) | |
11752 | { | |
11753 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11754 | * (mips_opts.mips16 ? 2 : 4)); | |
11755 | prev_nop_frag = NULL; | |
11756 | } | |
11757 | } | |
11758 | ||
11759 | mips_opts = s->options; | |
11760 | mips_opts_stack = s->next; | |
11761 | free (s); | |
11762 | } | |
11763 | } | |
11764 | else | |
11765 | { | |
11766 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11767 | } | |
11768 | *input_line_pointer = ch; | |
11769 | demand_empty_rest_of_line (); | |
11770 | } | |
11771 | ||
11772 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11773 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11774 | ||
11775 | static void | |
17a2f251 | 11776 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11777 | { |
11778 | mips_pic = SVR4_PIC; | |
143d77c5 | 11779 | mips_abicalls = TRUE; |
4d0d148d TS |
11780 | |
11781 | if (g_switch_seen && g_switch_value != 0) | |
11782 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11783 | g_switch_value = 0; | |
11784 | ||
252b5132 RH |
11785 | bfd_set_gp_size (stdoutput, 0); |
11786 | demand_empty_rest_of_line (); | |
11787 | } | |
11788 | ||
11789 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11790 | PIC code. It sets the $gp register for the function based on the | |
11791 | function address, which is in the register named in the argument. | |
11792 | This uses a relocation against _gp_disp, which is handled specially | |
11793 | by the linker. The result is: | |
11794 | lui $gp,%hi(_gp_disp) | |
11795 | addiu $gp,$gp,%lo(_gp_disp) | |
11796 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11797 | The .cpload argument is normally $25 == $t9. |
11798 | ||
11799 | The -mno-shared option changes this to: | |
11800 | lui $gp,%hi(_gp) | |
11801 | addiu $gp,$gp,%lo(_gp) | |
11802 | and the argument is ignored. This saves an instruction, but the | |
11803 | resulting code is not position independent; it uses an absolute | |
11804 | address for _gp. Thus code assembled with -mno-shared can go into | |
11805 | an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11806 | |
11807 | static void | |
17a2f251 | 11808 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11809 | { |
11810 | expressionS ex; | |
aa6975fb ILT |
11811 | int reg; |
11812 | int in_shared; | |
252b5132 | 11813 | |
6478892d TS |
11814 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11815 | .cpload is ignored. */ | |
11816 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11817 | { |
11818 | s_ignore (0); | |
11819 | return; | |
11820 | } | |
11821 | ||
d3ecfc59 | 11822 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11823 | if (mips_opts.noreorder == 0) |
11824 | as_warn (_(".cpload not in noreorder section")); | |
11825 | ||
aa6975fb ILT |
11826 | reg = tc_get_register (0); |
11827 | ||
11828 | /* If we need to produce a 64-bit address, we are better off using | |
11829 | the default instruction sequence. */ | |
11830 | in_shared = mips_in_shared || HAVE_64BIT_ADDRESSES; | |
11831 | ||
252b5132 | 11832 | ex.X_op = O_symbol; |
aa6975fb | 11833 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : "_gp"); |
252b5132 RH |
11834 | ex.X_op_symbol = NULL; |
11835 | ex.X_add_number = 0; | |
11836 | ||
11837 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11838 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11839 | |
584892a6 | 11840 | macro_start (); |
67c0d1eb RS |
11841 | macro_build_lui (&ex, mips_gp_register); |
11842 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11843 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11844 | if (in_shared) |
11845 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11846 | mips_gp_register, reg); | |
584892a6 | 11847 | macro_end (); |
252b5132 RH |
11848 | |
11849 | demand_empty_rest_of_line (); | |
11850 | } | |
11851 | ||
6478892d TS |
11852 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11853 | .cpsetup $reg1, offset|$reg2, label | |
11854 | ||
11855 | If offset is given, this results in: | |
11856 | sd $gp, offset($sp) | |
956cd1d6 | 11857 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11858 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11859 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11860 | |
11861 | If $reg2 is given, this results in: | |
11862 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11863 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11864 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11865 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11866 | $reg1 is normally $25 == $t9. |
11867 | ||
11868 | The -mno-shared option replaces the last three instructions with | |
11869 | lui $gp,%hi(_gp) | |
11870 | addiu $gp,$gp,%lo(_gp) | |
11871 | */ | |
11872 | ||
6478892d | 11873 | static void |
17a2f251 | 11874 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11875 | { |
11876 | expressionS ex_off; | |
11877 | expressionS ex_sym; | |
11878 | int reg1; | |
6478892d | 11879 | |
8586fc66 | 11880 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11881 | We also need NewABI support. */ |
11882 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11883 | { | |
11884 | s_ignore (0); | |
11885 | return; | |
11886 | } | |
11887 | ||
11888 | reg1 = tc_get_register (0); | |
11889 | SKIP_WHITESPACE (); | |
11890 | if (*input_line_pointer != ',') | |
11891 | { | |
11892 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11893 | return; | |
11894 | } | |
11895 | else | |
80245285 | 11896 | ++input_line_pointer; |
6478892d TS |
11897 | SKIP_WHITESPACE (); |
11898 | if (*input_line_pointer == '$') | |
80245285 TS |
11899 | { |
11900 | mips_cpreturn_register = tc_get_register (0); | |
11901 | mips_cpreturn_offset = -1; | |
11902 | } | |
6478892d | 11903 | else |
80245285 TS |
11904 | { |
11905 | mips_cpreturn_offset = get_absolute_expression (); | |
11906 | mips_cpreturn_register = -1; | |
11907 | } | |
6478892d TS |
11908 | SKIP_WHITESPACE (); |
11909 | if (*input_line_pointer != ',') | |
11910 | { | |
11911 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11912 | return; | |
11913 | } | |
11914 | else | |
f9419b05 | 11915 | ++input_line_pointer; |
6478892d | 11916 | SKIP_WHITESPACE (); |
f21f8242 | 11917 | expression (&ex_sym); |
6478892d | 11918 | |
584892a6 | 11919 | macro_start (); |
6478892d TS |
11920 | if (mips_cpreturn_register == -1) |
11921 | { | |
11922 | ex_off.X_op = O_constant; | |
11923 | ex_off.X_add_symbol = NULL; | |
11924 | ex_off.X_op_symbol = NULL; | |
11925 | ex_off.X_add_number = mips_cpreturn_offset; | |
11926 | ||
67c0d1eb | 11927 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11928 | BFD_RELOC_LO16, SP); |
6478892d TS |
11929 | } |
11930 | else | |
67c0d1eb | 11931 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11932 | mips_gp_register, 0); |
6478892d | 11933 | |
aa6975fb ILT |
11934 | if (mips_in_shared || HAVE_64BIT_ADDRESSES) |
11935 | { | |
11936 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11937 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11938 | BFD_RELOC_HI16_S); | |
11939 | ||
11940 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11941 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11942 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11943 | ||
11944 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11945 | mips_gp_register, reg1); | |
11946 | } | |
11947 | else | |
11948 | { | |
11949 | expressionS ex; | |
11950 | ||
11951 | ex.X_op = O_symbol; | |
11952 | ex.X_add_symbol = symbol_find_or_make ("_gp"); | |
11953 | ex.X_op_symbol = NULL; | |
11954 | ex.X_add_number = 0; | |
6e1304d8 | 11955 | |
aa6975fb ILT |
11956 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11957 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11958 | ||
11959 | macro_build_lui (&ex, mips_gp_register); | |
11960 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11961 | mips_gp_register, BFD_RELOC_LO16); | |
11962 | } | |
f21f8242 | 11963 | |
584892a6 | 11964 | macro_end (); |
6478892d TS |
11965 | |
11966 | demand_empty_rest_of_line (); | |
11967 | } | |
11968 | ||
11969 | static void | |
17a2f251 | 11970 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11971 | { |
11972 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11973 | .cplocal is ignored. */ | |
11974 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11975 | { | |
11976 | s_ignore (0); | |
11977 | return; | |
11978 | } | |
11979 | ||
11980 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11981 | demand_empty_rest_of_line (); |
6478892d TS |
11982 | } |
11983 | ||
252b5132 RH |
11984 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11985 | offset from $sp. The offset is remembered, and after making a PIC | |
11986 | call $gp is restored from that location. */ | |
11987 | ||
11988 | static void | |
17a2f251 | 11989 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11990 | { |
11991 | expressionS ex; | |
252b5132 | 11992 | |
6478892d | 11993 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11994 | .cprestore is ignored. */ |
6478892d | 11995 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11996 | { |
11997 | s_ignore (0); | |
11998 | return; | |
11999 | } | |
12000 | ||
12001 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12002 | mips_cprestore_valid = 1; |
252b5132 RH |
12003 | |
12004 | ex.X_op = O_constant; | |
12005 | ex.X_add_symbol = NULL; | |
12006 | ex.X_op_symbol = NULL; | |
12007 | ex.X_add_number = mips_cprestore_offset; | |
12008 | ||
584892a6 | 12009 | macro_start (); |
67c0d1eb RS |
12010 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12011 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12012 | macro_end (); |
252b5132 RH |
12013 | |
12014 | demand_empty_rest_of_line (); | |
12015 | } | |
12016 | ||
6478892d | 12017 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12018 | was given in the preceding .cpsetup, it results in: |
6478892d | 12019 | ld $gp, offset($sp) |
76b3015f | 12020 | |
6478892d | 12021 | If a register $reg2 was given there, it results in: |
609f23f4 | 12022 | daddu $gp, $reg2, $0 |
6478892d TS |
12023 | */ |
12024 | static void | |
17a2f251 | 12025 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12026 | { |
12027 | expressionS ex; | |
6478892d TS |
12028 | |
12029 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12030 | We also need NewABI support. */ | |
12031 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12032 | { | |
12033 | s_ignore (0); | |
12034 | return; | |
12035 | } | |
12036 | ||
584892a6 | 12037 | macro_start (); |
6478892d TS |
12038 | if (mips_cpreturn_register == -1) |
12039 | { | |
12040 | ex.X_op = O_constant; | |
12041 | ex.X_add_symbol = NULL; | |
12042 | ex.X_op_symbol = NULL; | |
12043 | ex.X_add_number = mips_cpreturn_offset; | |
12044 | ||
67c0d1eb | 12045 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12046 | } |
12047 | else | |
67c0d1eb | 12048 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12049 | mips_cpreturn_register, 0); |
584892a6 | 12050 | macro_end (); |
6478892d TS |
12051 | |
12052 | demand_empty_rest_of_line (); | |
12053 | } | |
12054 | ||
12055 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12056 | code. It sets the offset to use in gp_rel relocations. */ | |
12057 | ||
12058 | static void | |
17a2f251 | 12059 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12060 | { |
12061 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12062 | We also need NewABI support. */ | |
12063 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12064 | { | |
12065 | s_ignore (0); | |
12066 | return; | |
12067 | } | |
12068 | ||
def2e0dd | 12069 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12070 | |
12071 | demand_empty_rest_of_line (); | |
12072 | } | |
12073 | ||
252b5132 RH |
12074 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12075 | code. It generates a 32 bit GP relative reloc. */ | |
12076 | ||
12077 | static void | |
17a2f251 | 12078 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12079 | { |
12080 | symbolS *label; | |
12081 | expressionS ex; | |
12082 | char *p; | |
12083 | ||
12084 | /* When not generating PIC code, this is treated as .word. */ | |
12085 | if (mips_pic != SVR4_PIC) | |
12086 | { | |
12087 | s_cons (2); | |
12088 | return; | |
12089 | } | |
12090 | ||
12091 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12092 | mips_emit_delays (TRUE); |
252b5132 RH |
12093 | if (auto_align) |
12094 | mips_align (2, 0, label); | |
12095 | mips_clear_insn_labels (); | |
12096 | ||
12097 | expression (&ex); | |
12098 | ||
12099 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12100 | { | |
12101 | as_bad (_("Unsupported use of .gpword")); | |
12102 | ignore_rest_of_line (); | |
12103 | } | |
12104 | ||
12105 | p = frag_more (4); | |
17a2f251 | 12106 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12107 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12108 | BFD_RELOC_GPREL32); |
252b5132 RH |
12109 | |
12110 | demand_empty_rest_of_line (); | |
12111 | } | |
12112 | ||
10181a0d | 12113 | static void |
17a2f251 | 12114 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12115 | { |
12116 | symbolS *label; | |
12117 | expressionS ex; | |
12118 | char *p; | |
12119 | ||
12120 | /* When not generating PIC code, this is treated as .dword. */ | |
12121 | if (mips_pic != SVR4_PIC) | |
12122 | { | |
12123 | s_cons (3); | |
12124 | return; | |
12125 | } | |
12126 | ||
12127 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12128 | mips_emit_delays (TRUE); |
10181a0d AO |
12129 | if (auto_align) |
12130 | mips_align (3, 0, label); | |
12131 | mips_clear_insn_labels (); | |
12132 | ||
12133 | expression (&ex); | |
12134 | ||
12135 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12136 | { | |
12137 | as_bad (_("Unsupported use of .gpdword")); | |
12138 | ignore_rest_of_line (); | |
12139 | } | |
12140 | ||
12141 | p = frag_more (8); | |
17a2f251 | 12142 | md_number_to_chars (p, 0, 8); |
a105a300 | 12143 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12144 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12145 | |
12146 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12147 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12148 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12149 | |
12150 | demand_empty_rest_of_line (); | |
12151 | } | |
12152 | ||
252b5132 RH |
12153 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12154 | tables in SVR4 PIC code. */ | |
12155 | ||
12156 | static void | |
17a2f251 | 12157 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12158 | { |
252b5132 RH |
12159 | int reg; |
12160 | ||
10181a0d AO |
12161 | /* This is ignored when not generating SVR4 PIC code. */ |
12162 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12163 | { |
12164 | s_ignore (0); | |
12165 | return; | |
12166 | } | |
12167 | ||
12168 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12169 | macro_start (); |
252b5132 | 12170 | reg = tc_get_register (0); |
67c0d1eb | 12171 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12172 | macro_end (); |
252b5132 | 12173 | |
bdaaa2e1 | 12174 | demand_empty_rest_of_line (); |
252b5132 RH |
12175 | } |
12176 | ||
12177 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12178 | mips16 mode. This permits the linker to handle them specially, | |
12179 | such as generating jalx instructions when needed. We also make | |
12180 | them odd for the duration of the assembly, in order to generate the | |
12181 | right sort of code. We will make them even in the adjust_symtab | |
12182 | routine, while leaving them marked. This is convenient for the | |
12183 | debugger and the disassembler. The linker knows to make them odd | |
12184 | again. */ | |
12185 | ||
12186 | static void | |
17a2f251 | 12187 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12188 | { |
f9419b05 | 12189 | mips16_mark_labels (); |
252b5132 RH |
12190 | |
12191 | demand_empty_rest_of_line (); | |
12192 | } | |
12193 | ||
12194 | /* Handle a .stabn directive. We need these in order to mark a label | |
12195 | as being a mips16 text label correctly. Sometimes the compiler | |
12196 | will emit a label, followed by a .stabn, and then switch sections. | |
12197 | If the label and .stabn are in mips16 mode, then the label is | |
12198 | really a mips16 text label. */ | |
12199 | ||
12200 | static void | |
17a2f251 | 12201 | s_mips_stab (int type) |
252b5132 | 12202 | { |
f9419b05 | 12203 | if (type == 'n') |
252b5132 RH |
12204 | mips16_mark_labels (); |
12205 | ||
12206 | s_stab (type); | |
12207 | } | |
12208 | ||
12209 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12210 | */ | |
12211 | ||
12212 | static void | |
17a2f251 | 12213 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12214 | { |
12215 | char *name; | |
12216 | int c; | |
12217 | symbolS *symbolP; | |
12218 | expressionS exp; | |
12219 | ||
12220 | name = input_line_pointer; | |
12221 | c = get_symbol_end (); | |
12222 | symbolP = symbol_find_or_make (name); | |
12223 | S_SET_WEAK (symbolP); | |
12224 | *input_line_pointer = c; | |
12225 | ||
12226 | SKIP_WHITESPACE (); | |
12227 | ||
12228 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12229 | { | |
12230 | if (S_IS_DEFINED (symbolP)) | |
12231 | { | |
956cd1d6 | 12232 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12233 | S_GET_NAME (symbolP)); |
12234 | ignore_rest_of_line (); | |
12235 | return; | |
12236 | } | |
bdaaa2e1 | 12237 | |
252b5132 RH |
12238 | if (*input_line_pointer == ',') |
12239 | { | |
12240 | ++input_line_pointer; | |
12241 | SKIP_WHITESPACE (); | |
12242 | } | |
bdaaa2e1 | 12243 | |
252b5132 RH |
12244 | expression (&exp); |
12245 | if (exp.X_op != O_symbol) | |
12246 | { | |
12247 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12248 | ignore_rest_of_line (); |
252b5132 RH |
12249 | return; |
12250 | } | |
49309057 | 12251 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12252 | } |
12253 | ||
12254 | demand_empty_rest_of_line (); | |
12255 | } | |
12256 | ||
12257 | /* Parse a register string into a number. Called from the ECOFF code | |
12258 | to parse .frame. The argument is non-zero if this is the frame | |
12259 | register, so that we can record it in mips_frame_reg. */ | |
12260 | ||
12261 | int | |
17a2f251 | 12262 | tc_get_register (int frame) |
252b5132 RH |
12263 | { |
12264 | int reg; | |
12265 | ||
12266 | SKIP_WHITESPACE (); | |
12267 | if (*input_line_pointer++ != '$') | |
12268 | { | |
12269 | as_warn (_("expected `$'")); | |
85b51719 | 12270 | reg = ZERO; |
252b5132 | 12271 | } |
3882b010 | 12272 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12273 | { |
12274 | reg = get_absolute_expression (); | |
12275 | if (reg < 0 || reg >= 32) | |
12276 | { | |
12277 | as_warn (_("Bad register number")); | |
85b51719 | 12278 | reg = ZERO; |
252b5132 RH |
12279 | } |
12280 | } | |
12281 | else | |
12282 | { | |
76db943d | 12283 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12284 | { |
12285 | reg = RA; | |
12286 | input_line_pointer += 2; | |
12287 | } | |
76db943d | 12288 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12289 | { |
12290 | reg = FP; | |
12291 | input_line_pointer += 2; | |
12292 | } | |
252b5132 | 12293 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12294 | { |
12295 | reg = SP; | |
12296 | input_line_pointer += 2; | |
12297 | } | |
252b5132 | 12298 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12299 | { |
12300 | reg = GP; | |
12301 | input_line_pointer += 2; | |
12302 | } | |
252b5132 | 12303 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12304 | { |
12305 | reg = AT; | |
12306 | input_line_pointer += 2; | |
12307 | } | |
12308 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12309 | { | |
12310 | reg = KT0; | |
12311 | input_line_pointer += 3; | |
12312 | } | |
12313 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12314 | { | |
12315 | reg = KT1; | |
12316 | input_line_pointer += 3; | |
12317 | } | |
12318 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12319 | { | |
12320 | reg = ZERO; | |
12321 | input_line_pointer += 4; | |
12322 | } | |
252b5132 RH |
12323 | else |
12324 | { | |
12325 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12326 | reg = ZERO; |
12327 | while (ISALNUM(*input_line_pointer)) | |
12328 | input_line_pointer++; | |
252b5132 | 12329 | } |
252b5132 RH |
12330 | } |
12331 | if (frame) | |
7a621144 DJ |
12332 | { |
12333 | mips_frame_reg = reg != 0 ? reg : SP; | |
12334 | mips_frame_reg_valid = 1; | |
12335 | mips_cprestore_valid = 0; | |
12336 | } | |
252b5132 RH |
12337 | return reg; |
12338 | } | |
12339 | ||
12340 | valueT | |
17a2f251 | 12341 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12342 | { |
12343 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12344 | ||
12345 | #ifdef OBJ_ELF | |
12346 | /* We don't need to align ELF sections to the full alignment. | |
12347 | However, Irix 5 may prefer that we align them at least to a 16 | |
12348 | byte boundary. We don't bother to align the sections if we are | |
12349 | targeted for an embedded system. */ | |
12350 | if (strcmp (TARGET_OS, "elf") == 0) | |
12351 | return addr; | |
12352 | if (align > 4) | |
12353 | align = 4; | |
12354 | #endif | |
12355 | ||
12356 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12357 | } | |
12358 | ||
12359 | /* Utility routine, called from above as well. If called while the | |
12360 | input file is still being read, it's only an approximation. (For | |
12361 | example, a symbol may later become defined which appeared to be | |
12362 | undefined earlier.) */ | |
12363 | ||
12364 | static int | |
17a2f251 | 12365 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12366 | { |
12367 | if (sym == 0) | |
12368 | return 0; | |
12369 | ||
4d0d148d | 12370 | if (g_switch_value > 0) |
252b5132 RH |
12371 | { |
12372 | const char *symname; | |
12373 | int change; | |
12374 | ||
c9914766 | 12375 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12376 | register. It can be if it is smaller than the -G size or if |
12377 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12378 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12379 | they can. */ |
12380 | symname = S_GET_NAME (sym); | |
12381 | if (symname != (const char *) NULL | |
12382 | && (strcmp (symname, "eprol") == 0 | |
12383 | || strcmp (symname, "etext") == 0 | |
12384 | || strcmp (symname, "_gp") == 0 | |
12385 | || strcmp (symname, "edata") == 0 | |
12386 | || strcmp (symname, "_fbss") == 0 | |
12387 | || strcmp (symname, "_fdata") == 0 | |
12388 | || strcmp (symname, "_ftext") == 0 | |
12389 | || strcmp (symname, "end") == 0 | |
12390 | || strcmp (symname, "_gp_disp") == 0)) | |
12391 | change = 1; | |
12392 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12393 | && (0 | |
12394 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12395 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12396 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12397 | <= g_switch_value)) | |
252b5132 RH |
12398 | #endif |
12399 | /* We must defer this decision until after the whole | |
12400 | file has been read, since there might be a .extern | |
12401 | after the first use of this symbol. */ | |
12402 | || (before_relaxing | |
12403 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12404 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12405 | #endif |
12406 | && S_GET_VALUE (sym) == 0) | |
12407 | || (S_GET_VALUE (sym) != 0 | |
12408 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12409 | change = 0; | |
12410 | else | |
12411 | { | |
12412 | const char *segname; | |
12413 | ||
12414 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12415 | assert (strcmp (segname, ".lit8") != 0 | |
12416 | && strcmp (segname, ".lit4") != 0); | |
12417 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12418 | && strcmp (segname, ".sbss") != 0 |
12419 | && strncmp (segname, ".sdata.", 7) != 0 | |
12420 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12421 | } |
12422 | return change; | |
12423 | } | |
12424 | else | |
c9914766 | 12425 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12426 | return 1; |
12427 | } | |
12428 | ||
5919d012 RS |
12429 | |
12430 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12431 | ||
12432 | static bfd_boolean | |
17a2f251 | 12433 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12434 | { |
12435 | asection *symsec; | |
12436 | bfd_boolean linkonce; | |
12437 | ||
12438 | /* Handle the case of a symbol equated to another symbol. */ | |
12439 | while (symbol_equated_reloc_p (sym)) | |
12440 | { | |
12441 | symbolS *n; | |
12442 | ||
12443 | /* It's possible to get a loop here in a badly written | |
12444 | program. */ | |
12445 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12446 | if (n == sym) | |
12447 | break; | |
12448 | sym = n; | |
12449 | } | |
12450 | ||
12451 | symsec = S_GET_SEGMENT (sym); | |
12452 | ||
12453 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12454 | linkonce = FALSE; | |
12455 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12456 | { | |
12457 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12458 | != 0) | |
12459 | linkonce = TRUE; | |
12460 | ||
12461 | /* The GNU toolchain uses an extension for ELF: a section | |
12462 | beginning with the magic string .gnu.linkonce is a linkonce | |
12463 | section. */ | |
12464 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12465 | sizeof ".gnu.linkonce" - 1) == 0) | |
12466 | linkonce = TRUE; | |
12467 | } | |
12468 | ||
12469 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12470 | return (symsec != &bfd_und_section | |
12471 | && symsec != &bfd_abs_section | |
12472 | && ! bfd_is_com_section (symsec) | |
12473 | && !linkonce | |
12474 | #ifdef OBJ_ELF | |
12475 | /* A global or weak symbol is treated as external. */ | |
12476 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12477 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12478 | #endif |
12479 | ); | |
12480 | } | |
12481 | ||
12482 | ||
252b5132 RH |
12483 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12484 | extended opcode. SEC is the section the frag is in. */ | |
12485 | ||
12486 | static int | |
17a2f251 | 12487 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12488 | { |
12489 | int type; | |
12490 | register const struct mips16_immed_operand *op; | |
12491 | offsetT val; | |
12492 | int mintiny, maxtiny; | |
12493 | segT symsec; | |
98aa84af | 12494 | fragS *sym_frag; |
252b5132 RH |
12495 | |
12496 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12497 | return 0; | |
12498 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12499 | return 1; | |
12500 | ||
12501 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12502 | op = mips16_immed_operands; | |
12503 | while (op->type != type) | |
12504 | { | |
12505 | ++op; | |
12506 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12507 | } | |
12508 | ||
12509 | if (op->unsp) | |
12510 | { | |
12511 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12512 | { | |
12513 | mintiny = 1; | |
12514 | maxtiny = 1 << op->nbits; | |
12515 | } | |
12516 | else | |
12517 | { | |
12518 | mintiny = 0; | |
12519 | maxtiny = (1 << op->nbits) - 1; | |
12520 | } | |
12521 | } | |
12522 | else | |
12523 | { | |
12524 | mintiny = - (1 << (op->nbits - 1)); | |
12525 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12526 | } | |
12527 | ||
98aa84af | 12528 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12529 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12530 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12531 | |
12532 | if (op->pcrel) | |
12533 | { | |
12534 | addressT addr; | |
12535 | ||
12536 | /* We won't have the section when we are called from | |
12537 | mips_relax_frag. However, we will always have been called | |
12538 | from md_estimate_size_before_relax first. If this is a | |
12539 | branch to a different section, we mark it as such. If SEC is | |
12540 | NULL, and the frag is not marked, then it must be a branch to | |
12541 | the same section. */ | |
12542 | if (sec == NULL) | |
12543 | { | |
12544 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12545 | return 1; | |
12546 | } | |
12547 | else | |
12548 | { | |
98aa84af | 12549 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12550 | if (symsec != sec) |
12551 | { | |
12552 | fragp->fr_subtype = | |
12553 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12554 | ||
12555 | /* FIXME: We should support this, and let the linker | |
12556 | catch branches and loads that are out of range. */ | |
12557 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12558 | _("unsupported PC relative reference to different section")); | |
12559 | ||
12560 | return 1; | |
12561 | } | |
98aa84af AM |
12562 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12563 | /* Assume non-extended on the first relaxation pass. | |
12564 | The address we have calculated will be bogus if this is | |
12565 | a forward branch to another frag, as the forward frag | |
12566 | will have fr_address == 0. */ | |
12567 | return 0; | |
252b5132 RH |
12568 | } |
12569 | ||
12570 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12571 | the same section. If the relax_marker of the symbol fragment |
12572 | differs from the relax_marker of this fragment, we have not | |
12573 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12574 | in STRETCH in order to get a better estimate of the address. |
12575 | This particularly matters because of the shift bits. */ | |
12576 | if (stretch != 0 | |
98aa84af | 12577 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12578 | { |
12579 | fragS *f; | |
12580 | ||
12581 | /* Adjust stretch for any alignment frag. Note that if have | |
12582 | been expanding the earlier code, the symbol may be | |
12583 | defined in what appears to be an earlier frag. FIXME: | |
12584 | This doesn't handle the fr_subtype field, which specifies | |
12585 | a maximum number of bytes to skip when doing an | |
12586 | alignment. */ | |
98aa84af | 12587 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12588 | { |
12589 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12590 | { | |
12591 | if (stretch < 0) | |
12592 | stretch = - ((- stretch) | |
12593 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12594 | else | |
12595 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12596 | if (stretch == 0) | |
12597 | break; | |
12598 | } | |
12599 | } | |
12600 | if (f != NULL) | |
12601 | val += stretch; | |
12602 | } | |
12603 | ||
12604 | addr = fragp->fr_address + fragp->fr_fix; | |
12605 | ||
12606 | /* The base address rules are complicated. The base address of | |
12607 | a branch is the following instruction. The base address of a | |
12608 | PC relative load or add is the instruction itself, but if it | |
12609 | is in a delay slot (in which case it can not be extended) use | |
12610 | the address of the instruction whose delay slot it is in. */ | |
12611 | if (type == 'p' || type == 'q') | |
12612 | { | |
12613 | addr += 2; | |
12614 | ||
12615 | /* If we are currently assuming that this frag should be | |
12616 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12617 | higher. */ |
252b5132 RH |
12618 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12619 | addr += 2; | |
12620 | ||
12621 | /* Ignore the low bit in the target, since it will be set | |
12622 | for a text label. */ | |
12623 | if ((val & 1) != 0) | |
12624 | --val; | |
12625 | } | |
12626 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12627 | addr -= 4; | |
12628 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12629 | addr -= 2; | |
12630 | ||
12631 | val -= addr & ~ ((1 << op->shift) - 1); | |
12632 | ||
12633 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12634 | if (type == 'p' || type == 'q') | |
12635 | val /= 2; | |
12636 | ||
12637 | /* If any of the shifted bits are set, we must use an extended | |
12638 | opcode. If the address depends on the size of this | |
12639 | instruction, this can lead to a loop, so we arrange to always | |
12640 | use an extended opcode. We only check this when we are in | |
12641 | the main relaxation loop, when SEC is NULL. */ | |
12642 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12643 | { | |
12644 | fragp->fr_subtype = | |
12645 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12646 | return 1; | |
12647 | } | |
12648 | ||
12649 | /* If we are about to mark a frag as extended because the value | |
12650 | is precisely maxtiny + 1, then there is a chance of an | |
12651 | infinite loop as in the following code: | |
12652 | la $4,foo | |
12653 | .skip 1020 | |
12654 | .align 2 | |
12655 | foo: | |
12656 | In this case when the la is extended, foo is 0x3fc bytes | |
12657 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12658 | the la must be extended. To avoid this loop, we mark the | |
12659 | frag as extended if it was small, and is about to become | |
12660 | extended with a value of maxtiny + 1. */ | |
12661 | if (val == ((maxtiny + 1) << op->shift) | |
12662 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12663 | && sec == NULL) | |
12664 | { | |
12665 | fragp->fr_subtype = | |
12666 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12667 | return 1; | |
12668 | } | |
12669 | } | |
12670 | else if (symsec != absolute_section && sec != NULL) | |
12671 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12672 | ||
12673 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12674 | || val < (mintiny << op->shift) | |
12675 | || val > (maxtiny << op->shift)) | |
12676 | return 1; | |
12677 | else | |
12678 | return 0; | |
12679 | } | |
12680 | ||
4a6a3df4 AO |
12681 | /* Compute the length of a branch sequence, and adjust the |
12682 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12683 | worst-case length is computed, with UPDATE being used to indicate | |
12684 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12685 | branch is to be computed. */ | |
12686 | static int | |
17a2f251 | 12687 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12688 | { |
b34976b6 | 12689 | bfd_boolean toofar; |
4a6a3df4 AO |
12690 | int length; |
12691 | ||
12692 | if (fragp | |
12693 | && S_IS_DEFINED (fragp->fr_symbol) | |
12694 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12695 | { | |
12696 | addressT addr; | |
12697 | offsetT val; | |
12698 | ||
12699 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12700 | ||
12701 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12702 | ||
12703 | val -= addr; | |
12704 | ||
12705 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12706 | } | |
12707 | else if (fragp) | |
12708 | /* If the symbol is not defined or it's in a different segment, | |
12709 | assume the user knows what's going on and emit a short | |
12710 | branch. */ | |
b34976b6 | 12711 | toofar = FALSE; |
4a6a3df4 | 12712 | else |
b34976b6 | 12713 | toofar = TRUE; |
4a6a3df4 AO |
12714 | |
12715 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12716 | fragp->fr_subtype | |
af6ae2ad | 12717 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12718 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12719 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12720 | toofar); | |
12721 | ||
12722 | length = 4; | |
12723 | if (toofar) | |
12724 | { | |
12725 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12726 | length += 8; | |
12727 | ||
12728 | if (mips_pic != NO_PIC) | |
12729 | { | |
12730 | /* Additional space for PIC loading of target address. */ | |
12731 | length += 8; | |
12732 | if (mips_opts.isa == ISA_MIPS1) | |
12733 | /* Additional space for $at-stabilizing nop. */ | |
12734 | length += 4; | |
12735 | } | |
12736 | ||
12737 | /* If branch is conditional. */ | |
12738 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12739 | length += 8; | |
12740 | } | |
b34976b6 | 12741 | |
4a6a3df4 AO |
12742 | return length; |
12743 | } | |
12744 | ||
252b5132 RH |
12745 | /* Estimate the size of a frag before relaxing. Unless this is the |
12746 | mips16, we are not really relaxing here, and the final size is | |
12747 | encoded in the subtype information. For the mips16, we have to | |
12748 | decide whether we are using an extended opcode or not. */ | |
12749 | ||
252b5132 | 12750 | int |
17a2f251 | 12751 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12752 | { |
5919d012 | 12753 | int change; |
252b5132 | 12754 | |
4a6a3df4 AO |
12755 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12756 | { | |
12757 | ||
b34976b6 AM |
12758 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12759 | ||
4a6a3df4 AO |
12760 | return fragp->fr_var; |
12761 | } | |
12762 | ||
252b5132 | 12763 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12764 | /* We don't want to modify the EXTENDED bit here; it might get us |
12765 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12766 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12767 | |
12768 | if (mips_pic == NO_PIC) | |
5919d012 | 12769 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12770 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12771 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12772 | else |
12773 | abort (); | |
12774 | ||
12775 | if (change) | |
12776 | { | |
4d7206a2 | 12777 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12778 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12779 | } |
4d7206a2 RS |
12780 | else |
12781 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12782 | } |
12783 | ||
12784 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12785 | should be converted into a reloc against a section. */ |
252b5132 RH |
12786 | |
12787 | int | |
17a2f251 | 12788 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12789 | { |
de7e6852 RS |
12790 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12791 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12792 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12793 | return 0; | |
a161fe53 | 12794 | |
252b5132 RH |
12795 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12796 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12797 | return 0; | |
a161fe53 | 12798 | |
252b5132 RH |
12799 | if (fixp->fx_addsy == NULL) |
12800 | return 1; | |
a161fe53 | 12801 | |
de7e6852 RS |
12802 | /* If symbol SYM is in a mergeable section, relocations of the form |
12803 | SYM + 0 can usually be made section-relative. The mergeable data | |
12804 | is then identified by the section offset rather than by the symbol. | |
12805 | ||
12806 | However, if we're generating REL LO16 relocations, the offset is split | |
12807 | between the LO16 and parterning high part relocation. The linker will | |
12808 | need to recalculate the complete offset in order to correctly identify | |
12809 | the merge data. | |
12810 | ||
12811 | The linker has traditionally not looked for the parterning high part | |
12812 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12813 | placed anywhere. Rather than break backwards compatibility by changing | |
12814 | this, it seems better not to force the issue, and instead keep the | |
12815 | original symbol. This will work with either linker behavior. */ | |
12816 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12817 | && HAVE_IN_PLACE_ADDENDS | |
12818 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12819 | return 0; | |
12820 | ||
252b5132 | 12821 | #ifdef OBJ_ELF |
de7e6852 RS |
12822 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12823 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12824 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12825 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12826 | && fixp->fx_subsy == NULL) | |
12827 | return 0; | |
12828 | #endif | |
a161fe53 | 12829 | |
252b5132 RH |
12830 | return 1; |
12831 | } | |
12832 | ||
12833 | /* Translate internal representation of relocation info to BFD target | |
12834 | format. */ | |
12835 | ||
12836 | arelent ** | |
17a2f251 | 12837 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12838 | { |
12839 | static arelent *retval[4]; | |
12840 | arelent *reloc; | |
12841 | bfd_reloc_code_real_type code; | |
12842 | ||
4b0cff4e TS |
12843 | memset (retval, 0, sizeof(retval)); |
12844 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12845 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12846 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12847 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12848 | ||
3e722fb5 CD |
12849 | assert (! fixp->fx_pcrel); |
12850 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12851 | |
438c16b8 TS |
12852 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12853 | entry to be used in the relocation's section offset. */ | |
12854 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12855 | { |
12856 | reloc->address = reloc->addend; | |
12857 | reloc->addend = 0; | |
12858 | } | |
12859 | ||
252b5132 | 12860 | code = fixp->fx_r_type; |
252b5132 | 12861 | |
3e722fb5 CD |
12862 | /* To support a PC relative reloc, we used a Cygnus extension. |
12863 | We check for that here to make sure that we don't let such a | |
12864 | reloc escape normally. (FIXME: This was formerly used by | |
12865 | embedded-PIC support, but is now used by branch handling in | |
12866 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12867 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12868 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12869 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12870 | reloc->howto = NULL; |
12871 | else | |
12872 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12873 | ||
252b5132 RH |
12874 | if (reloc->howto == NULL) |
12875 | { | |
12876 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12877 | _("Can not represent %s relocation in this object file format"), | |
12878 | bfd_get_reloc_code_name (code)); | |
12879 | retval[0] = NULL; | |
12880 | } | |
12881 | ||
12882 | return retval; | |
12883 | } | |
12884 | ||
12885 | /* Relax a machine dependent frag. This returns the amount by which | |
12886 | the current size of the frag should change. */ | |
12887 | ||
12888 | int | |
17a2f251 | 12889 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12890 | { |
4a6a3df4 AO |
12891 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12892 | { | |
12893 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12894 | |
12895 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12896 | |
12897 | return fragp->fr_var - old_var; | |
12898 | } | |
12899 | ||
252b5132 RH |
12900 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12901 | return 0; | |
12902 | ||
c4e7957c | 12903 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12904 | { |
12905 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12906 | return 0; | |
12907 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12908 | return 2; | |
12909 | } | |
12910 | else | |
12911 | { | |
12912 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12913 | return 0; | |
12914 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12915 | return -2; | |
12916 | } | |
12917 | ||
12918 | return 0; | |
12919 | } | |
12920 | ||
12921 | /* Convert a machine dependent frag. */ | |
12922 | ||
12923 | void | |
17a2f251 | 12924 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12925 | { |
4a6a3df4 AO |
12926 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12927 | { | |
12928 | bfd_byte *buf; | |
12929 | unsigned long insn; | |
12930 | expressionS exp; | |
12931 | fixS *fixp; | |
b34976b6 | 12932 | |
4a6a3df4 AO |
12933 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12934 | ||
12935 | if (target_big_endian) | |
12936 | insn = bfd_getb32 (buf); | |
12937 | else | |
12938 | insn = bfd_getl32 (buf); | |
b34976b6 | 12939 | |
4a6a3df4 AO |
12940 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12941 | { | |
12942 | /* We generate a fixup instead of applying it right now | |
12943 | because, if there are linker relaxations, we're going to | |
12944 | need the relocations. */ | |
12945 | exp.X_op = O_symbol; | |
12946 | exp.X_add_symbol = fragp->fr_symbol; | |
12947 | exp.X_add_number = fragp->fr_offset; | |
12948 | ||
12949 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12950 | 4, &exp, 1, |
12951 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12952 | fixp->fx_file = fragp->fr_file; |
12953 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12954 | |
17a2f251 | 12955 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12956 | buf += 4; |
12957 | } | |
12958 | else | |
12959 | { | |
12960 | int i; | |
12961 | ||
12962 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12963 | _("relaxed out-of-range branch into a jump")); | |
12964 | ||
12965 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12966 | goto uncond; | |
12967 | ||
12968 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12969 | { | |
12970 | /* Reverse the branch. */ | |
12971 | switch ((insn >> 28) & 0xf) | |
12972 | { | |
12973 | case 4: | |
12974 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12975 | have the condition reversed by tweaking a single | |
12976 | bit, and their opcodes all have 0x4???????. */ | |
12977 | assert ((insn & 0xf1000000) == 0x41000000); | |
12978 | insn ^= 0x00010000; | |
12979 | break; | |
12980 | ||
12981 | case 0: | |
12982 | /* bltz 0x04000000 bgez 0x04010000 | |
12983 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12984 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12985 | insn ^= 0x00010000; | |
12986 | break; | |
b34976b6 | 12987 | |
4a6a3df4 AO |
12988 | case 1: |
12989 | /* beq 0x10000000 bne 0x14000000 | |
12990 | blez 0x18000000 bgtz 0x1c000000 */ | |
12991 | insn ^= 0x04000000; | |
12992 | break; | |
12993 | ||
12994 | default: | |
12995 | abort (); | |
12996 | } | |
12997 | } | |
12998 | ||
12999 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13000 | { | |
13001 | /* Clear the and-link bit. */ | |
13002 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13003 | ||
13004 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13005 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13006 | insn &= ~0x00100000; | |
13007 | } | |
13008 | ||
13009 | /* Branch over the branch (if the branch was likely) or the | |
13010 | full jump (not likely case). Compute the offset from the | |
13011 | current instruction to branch to. */ | |
13012 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13013 | i = 16; | |
13014 | else | |
13015 | { | |
13016 | /* How many bytes in instructions we've already emitted? */ | |
13017 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13018 | /* How many bytes in instructions from here to the end? */ | |
13019 | i = fragp->fr_var - i; | |
13020 | } | |
13021 | /* Convert to instruction count. */ | |
13022 | i >>= 2; | |
13023 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13024 | i--; |
4a6a3df4 AO |
13025 | insn |= i; |
13026 | /* Branch over the jump. */ | |
17a2f251 | 13027 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13028 | buf += 4; |
13029 | ||
13030 | /* Nop */ | |
17a2f251 | 13031 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13032 | buf += 4; |
13033 | ||
13034 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13035 | { | |
13036 | /* beql $0, $0, 2f */ | |
13037 | insn = 0x50000000; | |
13038 | /* Compute the PC offset from the current instruction to | |
13039 | the end of the variable frag. */ | |
13040 | /* How many bytes in instructions we've already emitted? */ | |
13041 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13042 | /* How many bytes in instructions from here to the end? */ | |
13043 | i = fragp->fr_var - i; | |
13044 | /* Convert to instruction count. */ | |
13045 | i >>= 2; | |
13046 | /* Don't decrement i, because we want to branch over the | |
13047 | delay slot. */ | |
13048 | ||
13049 | insn |= i; | |
17a2f251 | 13050 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13051 | buf += 4; |
13052 | ||
17a2f251 | 13053 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13054 | buf += 4; |
13055 | } | |
13056 | ||
13057 | uncond: | |
13058 | if (mips_pic == NO_PIC) | |
13059 | { | |
13060 | /* j or jal. */ | |
13061 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13062 | ? 0x0c000000 : 0x08000000); | |
13063 | exp.X_op = O_symbol; | |
13064 | exp.X_add_symbol = fragp->fr_symbol; | |
13065 | exp.X_add_number = fragp->fr_offset; | |
13066 | ||
13067 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13068 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13069 | fixp->fx_file = fragp->fr_file; | |
13070 | fixp->fx_line = fragp->fr_line; | |
13071 | ||
17a2f251 | 13072 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13073 | buf += 4; |
13074 | } | |
13075 | else | |
13076 | { | |
13077 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13078 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13079 | exp.X_op = O_symbol; | |
13080 | exp.X_add_symbol = fragp->fr_symbol; | |
13081 | exp.X_add_number = fragp->fr_offset; | |
13082 | ||
13083 | if (fragp->fr_offset) | |
13084 | { | |
13085 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13086 | exp.X_add_number = 0; | |
13087 | } | |
13088 | ||
13089 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13090 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13091 | fixp->fx_file = fragp->fr_file; | |
13092 | fixp->fx_line = fragp->fr_line; | |
13093 | ||
17a2f251 | 13094 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13095 | buf += 4; |
b34976b6 | 13096 | |
4a6a3df4 AO |
13097 | if (mips_opts.isa == ISA_MIPS1) |
13098 | { | |
13099 | /* nop */ | |
17a2f251 | 13100 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13101 | buf += 4; |
13102 | } | |
13103 | ||
13104 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13105 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13106 | ||
13107 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13108 | 4, &exp, 0, BFD_RELOC_LO16); | |
13109 | fixp->fx_file = fragp->fr_file; | |
13110 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13111 | |
17a2f251 | 13112 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13113 | buf += 4; |
13114 | ||
13115 | /* j(al)r $at. */ | |
13116 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13117 | insn = 0x0020f809; | |
13118 | else | |
13119 | insn = 0x00200008; | |
13120 | ||
17a2f251 | 13121 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13122 | buf += 4; |
13123 | } | |
13124 | } | |
13125 | ||
13126 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13127 | + fragp->fr_fix + fragp->fr_var); | |
13128 | ||
13129 | fragp->fr_fix += fragp->fr_var; | |
13130 | ||
13131 | return; | |
13132 | } | |
13133 | ||
252b5132 RH |
13134 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13135 | { | |
13136 | int type; | |
13137 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13138 | bfd_boolean small, ext; |
252b5132 RH |
13139 | offsetT val; |
13140 | bfd_byte *buf; | |
13141 | unsigned long insn; | |
b34976b6 | 13142 | bfd_boolean use_extend; |
252b5132 RH |
13143 | unsigned short extend; |
13144 | ||
13145 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13146 | op = mips16_immed_operands; | |
13147 | while (op->type != type) | |
13148 | ++op; | |
13149 | ||
13150 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13151 | { | |
b34976b6 AM |
13152 | small = FALSE; |
13153 | ext = TRUE; | |
252b5132 RH |
13154 | } |
13155 | else | |
13156 | { | |
b34976b6 AM |
13157 | small = TRUE; |
13158 | ext = FALSE; | |
252b5132 RH |
13159 | } |
13160 | ||
6386f3a7 | 13161 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13162 | val = S_GET_VALUE (fragp->fr_symbol); |
13163 | if (op->pcrel) | |
13164 | { | |
13165 | addressT addr; | |
13166 | ||
13167 | addr = fragp->fr_address + fragp->fr_fix; | |
13168 | ||
13169 | /* The rules for the base address of a PC relative reloc are | |
13170 | complicated; see mips16_extended_frag. */ | |
13171 | if (type == 'p' || type == 'q') | |
13172 | { | |
13173 | addr += 2; | |
13174 | if (ext) | |
13175 | addr += 2; | |
13176 | /* Ignore the low bit in the target, since it will be | |
13177 | set for a text label. */ | |
13178 | if ((val & 1) != 0) | |
13179 | --val; | |
13180 | } | |
13181 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13182 | addr -= 4; | |
13183 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13184 | addr -= 2; | |
13185 | ||
13186 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13187 | val -= addr; | |
13188 | ||
13189 | /* Make sure the section winds up with the alignment we have | |
13190 | assumed. */ | |
13191 | if (op->shift > 0) | |
13192 | record_alignment (asec, op->shift); | |
13193 | } | |
13194 | ||
13195 | if (ext | |
13196 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13197 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13198 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13199 | _("extended instruction in delay slot")); | |
13200 | ||
13201 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13202 | ||
13203 | if (target_big_endian) | |
13204 | insn = bfd_getb16 (buf); | |
13205 | else | |
13206 | insn = bfd_getl16 (buf); | |
13207 | ||
13208 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13209 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13210 | small, ext, &insn, &use_extend, &extend); | |
13211 | ||
13212 | if (use_extend) | |
13213 | { | |
17a2f251 | 13214 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13215 | fragp->fr_fix += 2; |
13216 | buf += 2; | |
13217 | } | |
13218 | ||
17a2f251 | 13219 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13220 | fragp->fr_fix += 2; |
13221 | buf += 2; | |
13222 | } | |
13223 | else | |
13224 | { | |
4d7206a2 RS |
13225 | int first, second; |
13226 | fixS *fixp; | |
252b5132 | 13227 | |
4d7206a2 RS |
13228 | first = RELAX_FIRST (fragp->fr_subtype); |
13229 | second = RELAX_SECOND (fragp->fr_subtype); | |
13230 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13231 | |
584892a6 RS |
13232 | /* Possibly emit a warning if we've chosen the longer option. */ |
13233 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13234 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13235 | { | |
13236 | const char *msg = macro_warning (fragp->fr_subtype); | |
13237 | if (msg != 0) | |
13238 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13239 | } | |
13240 | ||
4d7206a2 RS |
13241 | /* Go through all the fixups for the first sequence. Disable them |
13242 | (by marking them as done) if we're going to use the second | |
13243 | sequence instead. */ | |
13244 | while (fixp | |
13245 | && fixp->fx_frag == fragp | |
13246 | && fixp->fx_where < fragp->fr_fix - second) | |
13247 | { | |
13248 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13249 | fixp->fx_done = 1; | |
13250 | fixp = fixp->fx_next; | |
13251 | } | |
252b5132 | 13252 | |
4d7206a2 RS |
13253 | /* Go through the fixups for the second sequence. Disable them if |
13254 | we're going to use the first sequence, otherwise adjust their | |
13255 | addresses to account for the relaxation. */ | |
13256 | while (fixp && fixp->fx_frag == fragp) | |
13257 | { | |
13258 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13259 | fixp->fx_where -= first; | |
13260 | else | |
13261 | fixp->fx_done = 1; | |
13262 | fixp = fixp->fx_next; | |
13263 | } | |
13264 | ||
13265 | /* Now modify the frag contents. */ | |
13266 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13267 | { | |
13268 | char *start; | |
13269 | ||
13270 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13271 | memmove (start, start + first, second); | |
13272 | fragp->fr_fix -= first; | |
13273 | } | |
13274 | else | |
13275 | fragp->fr_fix -= second; | |
252b5132 RH |
13276 | } |
13277 | } | |
13278 | ||
13279 | #ifdef OBJ_ELF | |
13280 | ||
13281 | /* This function is called after the relocs have been generated. | |
13282 | We've been storing mips16 text labels as odd. Here we convert them | |
13283 | back to even for the convenience of the debugger. */ | |
13284 | ||
13285 | void | |
17a2f251 | 13286 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13287 | { |
13288 | asymbol **syms; | |
13289 | unsigned int count, i; | |
13290 | ||
13291 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13292 | return; | |
13293 | ||
13294 | syms = bfd_get_outsymbols (stdoutput); | |
13295 | count = bfd_get_symcount (stdoutput); | |
13296 | for (i = 0; i < count; i++, syms++) | |
13297 | { | |
13298 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13299 | && ((*syms)->value & 1) != 0) | |
13300 | { | |
13301 | (*syms)->value &= ~1; | |
13302 | /* If the symbol has an odd size, it was probably computed | |
13303 | incorrectly, so adjust that as well. */ | |
13304 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13305 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13306 | } | |
13307 | } | |
13308 | } | |
13309 | ||
13310 | #endif | |
13311 | ||
13312 | /* This function is called whenever a label is defined. It is used | |
13313 | when handling branch delays; if a branch has a label, we assume we | |
13314 | can not move it. */ | |
13315 | ||
13316 | void | |
17a2f251 | 13317 | mips_define_label (symbolS *sym) |
252b5132 RH |
13318 | { |
13319 | struct insn_label_list *l; | |
13320 | ||
13321 | if (free_insn_labels == NULL) | |
13322 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13323 | else | |
13324 | { | |
13325 | l = free_insn_labels; | |
13326 | free_insn_labels = l->next; | |
13327 | } | |
13328 | ||
13329 | l->label = sym; | |
13330 | l->next = insn_labels; | |
13331 | insn_labels = l; | |
13332 | } | |
13333 | \f | |
13334 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13335 | ||
13336 | /* Some special processing for a MIPS ELF file. */ | |
13337 | ||
13338 | void | |
17a2f251 | 13339 | mips_elf_final_processing (void) |
252b5132 RH |
13340 | { |
13341 | /* Write out the register information. */ | |
316f5878 | 13342 | if (mips_abi != N64_ABI) |
252b5132 RH |
13343 | { |
13344 | Elf32_RegInfo s; | |
13345 | ||
13346 | s.ri_gprmask = mips_gprmask; | |
13347 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13348 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13349 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13350 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13351 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13352 | ||
13353 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13354 | ((Elf32_External_RegInfo *) | |
13355 | mips_regmask_frag)); | |
13356 | } | |
13357 | else | |
13358 | { | |
13359 | Elf64_Internal_RegInfo s; | |
13360 | ||
13361 | s.ri_gprmask = mips_gprmask; | |
13362 | s.ri_pad = 0; | |
13363 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13364 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13365 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13366 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13367 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13368 | ||
13369 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13370 | ((Elf64_External_RegInfo *) | |
13371 | mips_regmask_frag)); | |
13372 | } | |
13373 | ||
13374 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13375 | sort of BFD interface for this. */ | |
13376 | if (mips_any_noreorder) | |
13377 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13378 | if (mips_pic != NO_PIC) | |
143d77c5 | 13379 | { |
252b5132 | 13380 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13381 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13382 | } | |
13383 | if (mips_abicalls) | |
13384 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13385 | |
98d3f06f | 13386 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13387 | if (file_ase_mips16) |
13388 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13389 | #if 0 /* XXX FIXME */ |
13390 | if (file_ase_mips3d) | |
13391 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13392 | #endif | |
deec1734 CD |
13393 | if (file_ase_mdmx) |
13394 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13395 | |
bdaaa2e1 | 13396 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13397 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13398 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13399 | else if (mips_abi == O64_ABI) |
252b5132 | 13400 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13401 | else if (mips_abi == EABI_ABI) |
252b5132 | 13402 | { |
316f5878 | 13403 | if (!file_mips_gp32) |
252b5132 RH |
13404 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13405 | else | |
13406 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13407 | } | |
316f5878 | 13408 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13409 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13410 | ||
c9914766 | 13411 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13412 | |
13413 | if (mips_32bitmode) | |
13414 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13415 | } | |
13416 | ||
13417 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13418 | \f | |
beae10d5 KH |
13419 | typedef struct proc { |
13420 | symbolS *isym; | |
13421 | unsigned long reg_mask; | |
13422 | unsigned long reg_offset; | |
13423 | unsigned long fpreg_mask; | |
13424 | unsigned long fpreg_offset; | |
13425 | unsigned long frame_offset; | |
13426 | unsigned long frame_reg; | |
13427 | unsigned long pc_reg; | |
13428 | } procS; | |
252b5132 RH |
13429 | |
13430 | static procS cur_proc; | |
13431 | static procS *cur_proc_ptr; | |
13432 | static int numprocs; | |
13433 | ||
0a9ef439 | 13434 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13435 | |
0a9ef439 | 13436 | void |
17a2f251 | 13437 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13438 | { |
0a9ef439 RH |
13439 | if (fragp->fr_type != rs_align_code) |
13440 | return; | |
13441 | ||
13442 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13443 | { |
13444 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13445 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13446 | ||
0a9ef439 RH |
13447 | int bytes; |
13448 | char *p; | |
a19d8eb0 | 13449 | |
0a9ef439 RH |
13450 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13451 | p = fragp->fr_literal + fragp->fr_fix; | |
13452 | ||
13453 | if (bytes & 1) | |
13454 | { | |
13455 | *p++ = 0; | |
f9419b05 | 13456 | fragp->fr_fix++; |
0a9ef439 RH |
13457 | } |
13458 | ||
13459 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13460 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13461 | } |
13462 | ||
0a9ef439 | 13463 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13464 | } |
13465 | ||
252b5132 | 13466 | static void |
17a2f251 | 13467 | md_obj_begin (void) |
252b5132 RH |
13468 | { |
13469 | } | |
13470 | ||
13471 | static void | |
17a2f251 | 13472 | md_obj_end (void) |
252b5132 RH |
13473 | { |
13474 | /* check for premature end, nesting errors, etc */ | |
13475 | if (cur_proc_ptr) | |
9a41af64 | 13476 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13477 | } |
13478 | ||
13479 | static long | |
17a2f251 | 13480 | get_number (void) |
252b5132 RH |
13481 | { |
13482 | int negative = 0; | |
13483 | long val = 0; | |
13484 | ||
13485 | if (*input_line_pointer == '-') | |
13486 | { | |
13487 | ++input_line_pointer; | |
13488 | negative = 1; | |
13489 | } | |
3882b010 | 13490 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13491 | as_bad (_("expected simple number")); |
252b5132 RH |
13492 | if (input_line_pointer[0] == '0') |
13493 | { | |
13494 | if (input_line_pointer[1] == 'x') | |
13495 | { | |
13496 | input_line_pointer += 2; | |
3882b010 | 13497 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13498 | { |
13499 | val <<= 4; | |
13500 | val |= hex_value (*input_line_pointer++); | |
13501 | } | |
13502 | return negative ? -val : val; | |
13503 | } | |
13504 | else | |
13505 | { | |
13506 | ++input_line_pointer; | |
3882b010 | 13507 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13508 | { |
13509 | val <<= 3; | |
13510 | val |= *input_line_pointer++ - '0'; | |
13511 | } | |
13512 | return negative ? -val : val; | |
13513 | } | |
13514 | } | |
3882b010 | 13515 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13516 | { |
13517 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13518 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13519 | as_warn (_("invalid number")); |
252b5132 RH |
13520 | return -1; |
13521 | } | |
3882b010 | 13522 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13523 | { |
13524 | val *= 10; | |
13525 | val += *input_line_pointer++ - '0'; | |
13526 | } | |
13527 | return negative ? -val : val; | |
13528 | } | |
13529 | ||
13530 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13531 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13532 | case .file implies DWARF-2. */ | |
13533 | ||
13534 | static void | |
17a2f251 | 13535 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13536 | { |
ecb4347a DJ |
13537 | static int first_file_directive = 0; |
13538 | ||
c5dd6aab DJ |
13539 | if (ECOFF_DEBUGGING) |
13540 | { | |
13541 | get_number (); | |
13542 | s_app_file (0); | |
13543 | } | |
13544 | else | |
ecb4347a DJ |
13545 | { |
13546 | char *filename; | |
13547 | ||
13548 | filename = dwarf2_directive_file (0); | |
13549 | ||
13550 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13551 | directive even for stabs output. Make sure that this | |
13552 | ".file" is handled. Note that you need a version of GCC | |
13553 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13554 | if (filename != NULL && ! first_file_directive) | |
13555 | { | |
13556 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13557 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13558 | } |
13559 | first_file_directive = 1; | |
13560 | } | |
c5dd6aab DJ |
13561 | } |
13562 | ||
13563 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13564 | |
13565 | static void | |
17a2f251 | 13566 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13567 | { |
c5dd6aab DJ |
13568 | if (!ECOFF_DEBUGGING) |
13569 | dwarf2_directive_loc (0); | |
252b5132 RH |
13570 | } |
13571 | ||
252b5132 RH |
13572 | /* The .end directive. */ |
13573 | ||
13574 | static void | |
17a2f251 | 13575 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13576 | { |
13577 | symbolS *p; | |
252b5132 | 13578 | |
7a621144 DJ |
13579 | /* Following functions need their own .frame and .cprestore directives. */ |
13580 | mips_frame_reg_valid = 0; | |
13581 | mips_cprestore_valid = 0; | |
13582 | ||
252b5132 RH |
13583 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13584 | { | |
13585 | p = get_symbol (); | |
13586 | demand_empty_rest_of_line (); | |
13587 | } | |
13588 | else | |
13589 | p = NULL; | |
13590 | ||
14949570 | 13591 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13592 | as_warn (_(".end not in text section")); |
13593 | ||
13594 | if (!cur_proc_ptr) | |
13595 | { | |
13596 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13597 | demand_empty_rest_of_line (); | |
13598 | return; | |
13599 | } | |
13600 | ||
13601 | if (p != NULL) | |
13602 | { | |
13603 | assert (S_GET_NAME (p)); | |
13604 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13605 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13606 | |
13607 | if (debug_type == DEBUG_STABS) | |
13608 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13609 | S_GET_NAME (p)); | |
252b5132 RH |
13610 | } |
13611 | else | |
13612 | as_warn (_(".end directive missing or unknown symbol")); | |
13613 | ||
ecb4347a DJ |
13614 | #ifdef OBJ_ELF |
13615 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13616 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13617 | && mips_flag_pdr) | |
ecb4347a DJ |
13618 | { |
13619 | segT saved_seg = now_seg; | |
13620 | subsegT saved_subseg = now_subseg; | |
13621 | valueT dot; | |
13622 | expressionS exp; | |
13623 | char *fragp; | |
252b5132 | 13624 | |
ecb4347a | 13625 | dot = frag_now_fix (); |
252b5132 RH |
13626 | |
13627 | #ifdef md_flush_pending_output | |
ecb4347a | 13628 | md_flush_pending_output (); |
252b5132 RH |
13629 | #endif |
13630 | ||
ecb4347a DJ |
13631 | assert (pdr_seg); |
13632 | subseg_set (pdr_seg, 0); | |
252b5132 | 13633 | |
ecb4347a DJ |
13634 | /* Write the symbol. */ |
13635 | exp.X_op = O_symbol; | |
13636 | exp.X_add_symbol = p; | |
13637 | exp.X_add_number = 0; | |
13638 | emit_expr (&exp, 4); | |
252b5132 | 13639 | |
ecb4347a | 13640 | fragp = frag_more (7 * 4); |
252b5132 | 13641 | |
17a2f251 TS |
13642 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13643 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13644 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13645 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13646 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13647 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13648 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13649 | |
ecb4347a DJ |
13650 | subseg_set (saved_seg, saved_subseg); |
13651 | } | |
13652 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13653 | |
13654 | cur_proc_ptr = NULL; | |
13655 | } | |
13656 | ||
13657 | /* The .aent and .ent directives. */ | |
13658 | ||
13659 | static void | |
17a2f251 | 13660 | s_mips_ent (int aent) |
252b5132 | 13661 | { |
252b5132 | 13662 | symbolS *symbolP; |
252b5132 RH |
13663 | |
13664 | symbolP = get_symbol (); | |
13665 | if (*input_line_pointer == ',') | |
f9419b05 | 13666 | ++input_line_pointer; |
252b5132 | 13667 | SKIP_WHITESPACE (); |
3882b010 | 13668 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13669 | || *input_line_pointer == '-') |
874e8986 | 13670 | get_number (); |
252b5132 | 13671 | |
14949570 | 13672 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13673 | as_warn (_(".ent or .aent not in text section.")); |
13674 | ||
13675 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13676 | as_warn (_("missing .end")); |
252b5132 RH |
13677 | |
13678 | if (!aent) | |
13679 | { | |
7a621144 DJ |
13680 | /* This function needs its own .frame and .cprestore directives. */ |
13681 | mips_frame_reg_valid = 0; | |
13682 | mips_cprestore_valid = 0; | |
13683 | ||
252b5132 RH |
13684 | cur_proc_ptr = &cur_proc; |
13685 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13686 | ||
13687 | cur_proc_ptr->isym = symbolP; | |
13688 | ||
49309057 | 13689 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13690 | |
f9419b05 | 13691 | ++numprocs; |
ecb4347a DJ |
13692 | |
13693 | if (debug_type == DEBUG_STABS) | |
13694 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13695 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13696 | } |
13697 | ||
13698 | demand_empty_rest_of_line (); | |
13699 | } | |
13700 | ||
13701 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13702 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13703 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13704 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13705 | symbol table (in the mdebug section). */ |
13706 | ||
13707 | static void | |
17a2f251 | 13708 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13709 | { |
ecb4347a DJ |
13710 | #ifdef OBJ_ELF |
13711 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13712 | { | |
13713 | long val; | |
252b5132 | 13714 | |
ecb4347a DJ |
13715 | if (cur_proc_ptr == (procS *) NULL) |
13716 | { | |
13717 | as_warn (_(".frame outside of .ent")); | |
13718 | demand_empty_rest_of_line (); | |
13719 | return; | |
13720 | } | |
252b5132 | 13721 | |
ecb4347a DJ |
13722 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13723 | ||
13724 | SKIP_WHITESPACE (); | |
13725 | if (*input_line_pointer++ != ',' | |
13726 | || get_absolute_expression_and_terminator (&val) != ',') | |
13727 | { | |
13728 | as_warn (_("Bad .frame directive")); | |
13729 | --input_line_pointer; | |
13730 | demand_empty_rest_of_line (); | |
13731 | return; | |
13732 | } | |
252b5132 | 13733 | |
ecb4347a DJ |
13734 | cur_proc_ptr->frame_offset = val; |
13735 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13736 | |
252b5132 | 13737 | demand_empty_rest_of_line (); |
252b5132 | 13738 | } |
ecb4347a DJ |
13739 | else |
13740 | #endif /* OBJ_ELF */ | |
13741 | s_ignore (ignore); | |
252b5132 RH |
13742 | } |
13743 | ||
bdaaa2e1 KH |
13744 | /* The .fmask and .mask directives. If the mdebug section is present |
13745 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13746 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13747 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13748 | make reference to the ecoff symbol table (in the mdebug section). */ |
13749 | ||
13750 | static void | |
17a2f251 | 13751 | s_mips_mask (int reg_type) |
252b5132 | 13752 | { |
ecb4347a DJ |
13753 | #ifdef OBJ_ELF |
13754 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13755 | { |
ecb4347a | 13756 | long mask, off; |
252b5132 | 13757 | |
ecb4347a DJ |
13758 | if (cur_proc_ptr == (procS *) NULL) |
13759 | { | |
13760 | as_warn (_(".mask/.fmask outside of .ent")); | |
13761 | demand_empty_rest_of_line (); | |
13762 | return; | |
13763 | } | |
252b5132 | 13764 | |
ecb4347a DJ |
13765 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13766 | { | |
13767 | as_warn (_("Bad .mask/.fmask directive")); | |
13768 | --input_line_pointer; | |
13769 | demand_empty_rest_of_line (); | |
13770 | return; | |
13771 | } | |
252b5132 | 13772 | |
ecb4347a DJ |
13773 | off = get_absolute_expression (); |
13774 | ||
13775 | if (reg_type == 'F') | |
13776 | { | |
13777 | cur_proc_ptr->fpreg_mask = mask; | |
13778 | cur_proc_ptr->fpreg_offset = off; | |
13779 | } | |
13780 | else | |
13781 | { | |
13782 | cur_proc_ptr->reg_mask = mask; | |
13783 | cur_proc_ptr->reg_offset = off; | |
13784 | } | |
13785 | ||
13786 | demand_empty_rest_of_line (); | |
252b5132 RH |
13787 | } |
13788 | else | |
ecb4347a DJ |
13789 | #endif /* OBJ_ELF */ |
13790 | s_ignore (reg_type); | |
252b5132 RH |
13791 | } |
13792 | ||
316f5878 RS |
13793 | /* A table describing all the processors gas knows about. Names are |
13794 | matched in the order listed. | |
e7af610e | 13795 | |
316f5878 RS |
13796 | To ease comparison, please keep this table in the same order as |
13797 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13798 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13799 | { | |
316f5878 RS |
13800 | /* Entries for generic ISAs */ |
13801 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13802 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13803 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13804 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13805 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13806 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13807 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13808 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13809 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13810 | |
13811 | /* MIPS I */ | |
13812 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13813 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13814 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13815 | ||
13816 | /* MIPS II */ | |
13817 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13818 | ||
13819 | /* MIPS III */ | |
13820 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13821 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13822 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13823 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13824 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13825 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13826 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13827 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13828 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13829 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13830 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13831 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13832 | ||
13833 | /* MIPS IV */ | |
13834 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13835 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13836 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13837 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13838 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13839 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13840 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13841 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13842 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13843 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13844 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13845 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13846 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13847 | |
13848 | /* MIPS 32 */ | |
fef14a42 | 13849 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13850 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13851 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13852 | |
316f5878 RS |
13853 | /* MIPS 64 */ |
13854 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13855 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13856 | |
c7a23324 | 13857 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13858 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13859 | |
316f5878 RS |
13860 | /* End marker */ |
13861 | { NULL, 0, 0, 0 } | |
13862 | }; | |
e7af610e | 13863 | |
84ea6cf2 | 13864 | |
316f5878 RS |
13865 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13866 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13867 | |
316f5878 | 13868 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13869 | |
b34976b6 | 13870 | static bfd_boolean |
17a2f251 | 13871 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13872 | { |
13873 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13874 | given++, canonical++; | |
13875 | ||
13876 | return ((*given == 0 && *canonical == 0) | |
13877 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13878 | } | |
13879 | ||
13880 | ||
13881 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13882 | CPU name. We've traditionally allowed a lot of variation here. | |
13883 | ||
13884 | Note: this function is shared between GCC and GAS. */ | |
13885 | ||
b34976b6 | 13886 | static bfd_boolean |
17a2f251 | 13887 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13888 | { |
13889 | /* First see if the name matches exactly, or with a final "000" | |
13890 | turned into "k". */ | |
13891 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13892 | return TRUE; |
316f5878 RS |
13893 | |
13894 | /* If not, try comparing based on numerical designation alone. | |
13895 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13896 | if (TOLOWER (*given) == 'r') | |
13897 | given++; | |
13898 | if (!ISDIGIT (*given)) | |
b34976b6 | 13899 | return FALSE; |
316f5878 RS |
13900 | |
13901 | /* Skip over some well-known prefixes in the canonical name, | |
13902 | hoping to find a number there too. */ | |
13903 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13904 | canonical += 2; | |
13905 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13906 | canonical += 2; | |
13907 | else if (TOLOWER (canonical[0]) == 'r') | |
13908 | canonical += 1; | |
13909 | ||
13910 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13911 | } | |
13912 | ||
13913 | ||
13914 | /* Parse an option that takes the name of a processor as its argument. | |
13915 | OPTION is the name of the option and CPU_STRING is the argument. | |
13916 | Return the corresponding processor enumeration if the CPU_STRING is | |
13917 | recognized, otherwise report an error and return null. | |
13918 | ||
13919 | A similar function exists in GCC. */ | |
e7af610e NC |
13920 | |
13921 | static const struct mips_cpu_info * | |
17a2f251 | 13922 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13923 | { |
316f5878 | 13924 | const struct mips_cpu_info *p; |
e7af610e | 13925 | |
316f5878 RS |
13926 | /* 'from-abi' selects the most compatible architecture for the given |
13927 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13928 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13929 | version. Look first at the -mgp options, if given, otherwise base | |
13930 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13931 | |
316f5878 RS |
13932 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13933 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13934 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13935 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13936 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13937 | { | |
13938 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13939 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13940 | ||
13941 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13942 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13943 | ||
13944 | if (file_mips_gp32 >= 0) | |
13945 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13946 | ||
13947 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13948 | ? ISA_MIPS3 | |
13949 | : ISA_MIPS1); | |
13950 | } | |
13951 | ||
13952 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13953 | if (strcasecmp (cpu_string, "default") == 0) | |
13954 | return 0; | |
13955 | ||
13956 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13957 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13958 | return p; | |
13959 | ||
13960 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13961 | return 0; | |
e7af610e NC |
13962 | } |
13963 | ||
316f5878 RS |
13964 | /* Return the canonical processor information for ISA (a member of the |
13965 | ISA_MIPS* enumeration). */ | |
13966 | ||
e7af610e | 13967 | static const struct mips_cpu_info * |
17a2f251 | 13968 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13969 | { |
13970 | int i; | |
13971 | ||
13972 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13973 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13974 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13975 | return (&mips_cpu_info_table[i]); |
13976 | ||
e972090a | 13977 | return NULL; |
e7af610e | 13978 | } |
fef14a42 TS |
13979 | |
13980 | static const struct mips_cpu_info * | |
17a2f251 | 13981 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13982 | { |
13983 | int i; | |
13984 | ||
13985 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13986 | if (arch == mips_cpu_info_table[i].cpu) | |
13987 | return (&mips_cpu_info_table[i]); | |
13988 | ||
13989 | return NULL; | |
13990 | } | |
316f5878 RS |
13991 | \f |
13992 | static void | |
17a2f251 | 13993 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13994 | { |
13995 | if (*first_p) | |
13996 | { | |
13997 | fprintf (stream, "%24s", ""); | |
13998 | *col_p = 24; | |
13999 | } | |
14000 | else | |
14001 | { | |
14002 | fprintf (stream, ", "); | |
14003 | *col_p += 2; | |
14004 | } | |
e7af610e | 14005 | |
316f5878 RS |
14006 | if (*col_p + strlen (string) > 72) |
14007 | { | |
14008 | fprintf (stream, "\n%24s", ""); | |
14009 | *col_p = 24; | |
14010 | } | |
14011 | ||
14012 | fprintf (stream, "%s", string); | |
14013 | *col_p += strlen (string); | |
14014 | ||
14015 | *first_p = 0; | |
14016 | } | |
14017 | ||
14018 | void | |
17a2f251 | 14019 | md_show_usage (FILE *stream) |
e7af610e | 14020 | { |
316f5878 RS |
14021 | int column, first; |
14022 | size_t i; | |
14023 | ||
14024 | fprintf (stream, _("\ | |
14025 | MIPS options:\n\ | |
316f5878 RS |
14026 | -EB generate big endian output\n\ |
14027 | -EL generate little endian output\n\ | |
14028 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14029 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14030 | implicitly with the gp register [default 8]\n")); | |
14031 | fprintf (stream, _("\ | |
14032 | -mips1 generate MIPS ISA I instructions\n\ | |
14033 | -mips2 generate MIPS ISA II instructions\n\ | |
14034 | -mips3 generate MIPS ISA III instructions\n\ | |
14035 | -mips4 generate MIPS ISA IV instructions\n\ | |
14036 | -mips5 generate MIPS ISA V instructions\n\ | |
14037 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14038 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14039 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14040 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14041 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14042 | ||
14043 | first = 1; | |
e7af610e NC |
14044 | |
14045 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14046 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14047 | show (stream, "from-abi", &column, &first); | |
14048 | fputc ('\n', stream); | |
e7af610e | 14049 | |
316f5878 RS |
14050 | fprintf (stream, _("\ |
14051 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14052 | -no-mCPU don't generate code specific to CPU.\n\ | |
14053 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14054 | ||
14055 | first = 1; | |
14056 | ||
14057 | show (stream, "3900", &column, &first); | |
14058 | show (stream, "4010", &column, &first); | |
14059 | show (stream, "4100", &column, &first); | |
14060 | show (stream, "4650", &column, &first); | |
14061 | fputc ('\n', stream); | |
14062 | ||
14063 | fprintf (stream, _("\ | |
14064 | -mips16 generate mips16 instructions\n\ | |
14065 | -no-mips16 do not generate mips16 instructions\n")); | |
14066 | fprintf (stream, _("\ | |
d766e8ec | 14067 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14068 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14069 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14070 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14071 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14072 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14073 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14074 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14075 | #ifdef OBJ_ELF | |
14076 | fprintf (stream, _("\ | |
14077 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14078 | -non_shared do not generate position independent code\n\ | |
14079 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14080 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14081 | -mabi=ABI create ABI conformant object file for:\n")); |
14082 | ||
14083 | first = 1; | |
14084 | ||
14085 | show (stream, "32", &column, &first); | |
14086 | show (stream, "o64", &column, &first); | |
14087 | show (stream, "n32", &column, &first); | |
14088 | show (stream, "64", &column, &first); | |
14089 | show (stream, "eabi", &column, &first); | |
14090 | ||
14091 | fputc ('\n', stream); | |
14092 | ||
14093 | fprintf (stream, _("\ | |
14094 | -32 create o32 ABI object file (default)\n\ | |
14095 | -n32 create n32 ABI object file\n\ | |
14096 | -64 create 64 ABI object file\n")); | |
14097 | #endif | |
e7af610e | 14098 | } |
14e777e0 KB |
14099 | |
14100 | enum dwarf2_format | |
17a2f251 | 14101 | mips_dwarf2_format (void) |
14e777e0 KB |
14102 | { |
14103 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14104 | { |
14105 | #ifdef TE_IRIX | |
14106 | return dwarf2_format_64bit_irix; | |
14107 | #else | |
14108 | return dwarf2_format_64bit; | |
14109 | #endif | |
14110 | } | |
14e777e0 KB |
14111 | else |
14112 | return dwarf2_format_32bit; | |
14113 | } | |
73369e65 EC |
14114 | |
14115 | int | |
14116 | mips_dwarf2_addr_size (void) | |
14117 | { | |
14118 | if (mips_abi == N64_ABI) | |
14119 | return 8; | |
73369e65 EC |
14120 | else |
14121 | return 4; | |
14122 | } |