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[deliverable/binutils-gdb.git] / gas / config / tc-msp430.c
CommitLineData
2469cfa2
NC		 1/* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
2
2571583a 3 Copyright (C) 2002-2017 Free Software Foundation, Inc.
2469cfa2
NC		 4 Contributed by Dmitry Diky <diwil@mail.ru>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
2469cfa2
NC		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
2469cfa2 22
df7b86aa 23#include "as.h"
2469cfa2 24#include <limits.h>
2469cfa2
NC		 25#include "subsegs.h"
26#include "opcode/msp430.h"
27#include "safe-ctype.h"
2a9a06c1 28#include "dwarf2dbg.h"
13761a11 29#include "elf/msp430.h"
ede77e69 30#include "libiberty.h"
2469cfa2 31
79cf5950 32/* We will disable polymorphs by default because it is dangerous.
708587a4 33 The potential problem here is the following: assume we got the
77592908
DD		 34 following code:
35
36 jump .l1
37 nop
38 jump subroutine ; external symbol
39 .l1:
40 nop
41 ret
13761a11 42
77592908
DD		 43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
45 2: nop
46 4: br subroutine
47 .l1:
48 8: nop
49 10: ret
50
79cf5950
NC		 51 If the 'subroutine' is within +-1024 bytes range then linker
52 will produce:
77592908
DD		 53 0: jmp .text +0x08
54 2: nop
55 4: jmp subroutine
56 .l1:
57 6: nop
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
59
77592908 60 The workaround is the following:
79cf5950 61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
77592908
DD		 62 2. Declare global var enable_relax which set to 1 via option -mQ.
63
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
13761a11 66
79cf5950 67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
77592908
DD		 68
69int msp430_enable_relax;
70int msp430_enable_polys;
71
f5c7edf4
AM		 72/* GCC uses the some condition codes which we'll
73 implement as new polymorph instructions.
13761a11 74
f5c7edf4
AM		 75 COND EXPL SHORT JUMP LONG JUMP
76 ===============================================
77 eq == jeq jne +4; br lab
78 ne != jne jeq +4; br lab
79
80 ltn honours no-overflow flag
81 ltn < jn jn +2; jmp +4; br lab
82
13761a11 83 lt < jl jge +4; br lab
f5c7edf4
AM		 84 ltu < jlo lhs +4; br lab
85 le <= see below
86 leu <= see below
87
88 gt > see below
89 gtu > see below
90 ge >= jge jl +4; br lab
91 geu >= jhs jlo +4; br lab
92 ===============================================
93
94 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
95 beq,bne,blt,bltn,bltu,bge,bgeu
13761a11
NC		 96 'u' means unsigned compares
97
f5c7edf4
AM		 98 Also, we add 'jump' instruction:
99 jump UNCOND -> jmp br lab
100
101 They will have fmt == 4, and insn_opnumb == number of instruction. */
102
13761a11 103struct rcodes_s
f5c7edf4 104{
e0471c16 105 const char * name;
f5c7edf4
AM		 106 int index; /* Corresponding insn_opnumb. */
107 int sop; /* Opcode if jump length is short. */
108 long lpos; /* Label position. */
109 long lop0; /* Opcode 1 _word_ (16 bits). */
110 long lop1; /* Opcode second word. */
111 long lop2; /* Opcode third word. */
112};
113
114#define MSP430_RLC(n,i,sop,o1) \
115 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
116
13761a11 117static struct rcodes_s msp430_rcodes[] =
f5c7edf4
AM		 118{
119 MSP430_RLC (beq, 0, 0x2400, 0x2000),
120 MSP430_RLC (bne, 1, 0x2000, 0x2400),
121 MSP430_RLC (blt, 2, 0x3800, 0x3400),
122 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
123 MSP430_RLC (bge, 4, 0x3400, 0x3800),
124 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
125 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
126 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
127 {0,0,0,0,0,0,0}
128};
f5c7edf4 129
13761a11
NC		 130#undef MSP430_RLC
131#define MSP430_RLC(n,i,sop,o1) \
132 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
133
134static struct rcodes_s msp430x_rcodes[] =
135{
136 MSP430_RLC (beq, 0, 0x2400, 0x2000),
137 MSP430_RLC (bne, 1, 0x2000, 0x2400),
138 MSP430_RLC (blt, 2, 0x3800, 0x3400),
139 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
140 MSP430_RLC (bge, 4, 0x3400, 0x3800),
141 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
142 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
143 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
144 {0,0,0,0,0,0,0}
145};
146#undef MSP430_RLC
f5c7edf4
AM		 147
148/* More difficult than above and they have format 5.
13761a11 149
f5c7edf4
AM		 150 COND EXPL SHORT LONG
151 =================================================================
152 gt > jeq +2; jge label jeq +6; jl +4; br label
153 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
154 leu <= jeq label; jlo label jeq +2; jhs +4; br label
155 le <= jeq label; jl label jeq +2; jge +4; br label
156 ================================================================= */
157
13761a11 158struct hcodes_s
f5c7edf4 159{
e0471c16 160 const char * name;
f5c7edf4
AM		 161 int index; /* Corresponding insn_opnumb. */
162 int tlab; /* Number of labels in short mode. */
163 int op0; /* Opcode for first word of short jump. */
164 int op1; /* Opcode for second word of short jump. */
165 int lop0; /* Opcodes for long jump mode. */
166 int lop1;
167 int lop2;
168};
169
13761a11 170static struct hcodes_s msp430_hcodes[] =
f5c7edf4
AM		 171{
172 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
173 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
174 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
175 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
176 {0,0,0,0,0,0,0,0}
177};
178
13761a11
NC		 179static struct hcodes_s msp430x_hcodes[] =
180{
181 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
182 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
183 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
184 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
185 {0,0,0,0,0,0,0,0}
186};
187
2469cfa2
NC		 188const char comment_chars[] = ";";
189const char line_comment_chars[] = "#";
870074dd 190const char line_separator_chars[] = "{";
2469cfa2
NC		 191const char EXP_CHARS[] = "eE";
192const char FLT_CHARS[] = "dD";
193
194/* Handle long expressions. */
195extern LITTLENUM_TYPE generic_bignum[];
196
197static struct hash_control *msp430_hash;
198
b18c562e
NC		 199/* Relaxations. */
200#define STATE_UNCOND_BRANCH 1 /* jump */
201#define STATE_NOOV_BRANCH 3 /* bltn */
202#define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
203#define STATE_EMUL_BRANCH 4
204
205#define CNRL 2
206#define CUBL 4
207#define CNOL 8
208#define CSBL 6
209#define CEBL 4
210
211/* Length. */
212#define STATE_BITS10 1 /* wild guess. short jump */
213#define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
214#define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
215
216#define ENCODE_RELAX(what,length) (((what) << 2) + (length))
217#define RELAX_STATE(s) ((s) & 3)
218#define RELAX_LEN(s) ((s) >> 2)
219#define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
220
221relax_typeS md_relax_table[] =
222{
223 /* Unused. */
224 {1, 1, 0, 0},
225 {1, 1, 0, 0},
226 {1, 1, 0, 0},
227 {1, 1, 0, 0},
228
229 /* Unconditional jump. */
230 {1, 1, 8, 5},
231 {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
232 {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */
233 {1, 1, CUBL, 0}, /* state undef */
234
235 /* Simple branches. */
236 {0, 0, 8, 9},
237 {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
238 {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */
239 {1, 1, CSBL, 0},
240
241 /* blt no overflow branch. */
242 {1, 1, 8, 13},
243 {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
244 {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */
245 {1, 1, CNOL, 0},
246
247 /* Emulated branches. */
248 {1, 1, 8, 17},
249 {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
250 {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */
251 {1, 1, CNOL, 0}
252};
253
2469cfa2 254
837a17b3 255#define MAX_OP_LEN 4096
2469cfa2 256
638d3803
NC		 257typedef enum msp_isa
258{
259 MSP_ISA_430,
260 MSP_ISA_430X,
261 MSP_ISA_430Xv2
262} msp_isa;
263
65d7bab5 264static enum msp_isa selected_isa = MSP_ISA_430Xv2;
638d3803
NC		 265
266static inline bfd_boolean
267target_is_430x (void)
268{
65d7bab5 269 return selected_isa >= MSP_ISA_430X;
638d3803
NC		 270}
271
272static inline bfd_boolean
273target_is_430xv2 (void)
274{
65d7bab5 275 return selected_isa == MSP_ISA_430Xv2;
638d3803 276}
13761a11 277
00b32ff2
NC		 278/* Generate an absolute 16-bit relocation.
279 For the 430X we generate a relocation without linker range checking
280 if the value is being used in an extended (ie 20-bit) instruction,
281 otherwise if have a shifted expression we use a HI reloc.
13761a11 282 For the 430 we generate a relocation without assembler range checking
00b32ff2
NC		 283 if we are handling an immediate value or a byte-width instruction. */
284
13761a11 285#undef CHECK_RELOC_MSP430
00b32ff2
NC		 286#define CHECK_RELOC_MSP430(OP) \
287 (target_is_430x () \
288 ? (extended_op \
289 ? BFD_RELOC_16 \
290 : ((OP).vshift == 1) \
291 ? BFD_RELOC_MSP430_ABS_HI16 \
292 : BFD_RELOC_MSP430X_ABS16) \
293 : ((imm_op || byte_op) \
13761a11
NC		 294 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
295
296/* Generate a 16-bit pc-relative relocation.
33eaf5de 297 For the 430X we generate a relocation without linker range checking.
13761a11
NC		 298 For the 430 we generate a relocation without assembler range checking
299 if we are handling an immediate value or a byte-width instruction. */
300#undef CHECK_RELOC_MSP430_PCREL
301#define CHECK_RELOC_MSP430_PCREL \
638d3803 302 (target_is_430x () \
13761a11
NC		 303 ? BFD_RELOC_MSP430X_PCR16 \
304 : (imm_op || byte_op) \
305 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
2469cfa2 306
b18c562e
NC		 307/* Profiling capability:
308 It is a performance hit to use gcc's profiling approach for this tiny target.
309 Even more -- jtag hardware facility does not perform any profiling functions.
310 However we've got gdb's built-in simulator where we can do anything.
311 Therefore my suggestion is:
312
313 We define new section ".profiler" which holds all profiling information.
314 We define new pseudo operation .profiler which will instruct assembler to
315 add new profile entry to the object file. Profile should take place at the
316 present address.
317
318 Pseudo-op format:
319
320 .profiler flags,function_to_profile [, cycle_corrector, extra]
321
322 where 'flags' is a combination of the following chars:
323 s - function Start
324 x - function eXit
325 i - function is in Init section
326 f - function is in Fini section
327 l - Library call
328 c - libC standard call
329 d - stack value Demand (saved at run-time in simulator)
330 I - Interrupt service routine
331 P - Prologue start
332 p - Prologue end
333 E - Epilogue start
334 e - Epilogue end
335 j - long Jump/ sjlj unwind
336 a - an Arbitrary code fragment
337 t - exTra parameter saved (constant value like frame size)
338 '""' optional: "sil" == sil
339
340 function_to_profile - function's address
341 cycle_corrector - a value which should be added to the cycle
342 counter, zero if omitted
343 extra - some extra parameter, zero if omitted.
344
345 For example:
346 ------------------------------
347 .global fxx
348 .type fxx,@function
349 fxx:
350 .LFrameOffset_fxx=0x08
351 .profiler "scdP", fxx ; function entry.
352 ; we also demand stack value to be displayed
353 push r11
354 push r10
355 push r9
356 push r8
357 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
358 ; (this is a prologue end)
79cf5950 359 ; note, that spare var filled with the frame size
b18c562e
NC		 360 mov r15,r8
361 ....
362 .profiler cdE,fxx ; check stack
363 pop r8
364 pop r9
365 pop r10
366 pop r11
367 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
368 ret ; cause 'ret' insn takes 3 cycles
369 -------------------------------
370
371 This profiling approach does not produce any overhead and
372 absolutely harmless.
373 So, even profiled code can be uploaded to the MCU. */
374#define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
375#define MSP430_PROFILER_FLAG_EXIT 2 /* x */
376#define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
377#define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
378#define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
379#define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
380#define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
381#define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
382#define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
383#define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
384#define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
385#define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
386#define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
387#define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
388#define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
389#define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
2469cfa2 390
b18c562e
NC		 391static int
392pow2value (int y)
2469cfa2 393{
b18c562e
NC		 394 int n = 0;
395 unsigned int x;
2469cfa2 396
b18c562e 397 x = y;
2469cfa2 398
b18c562e
NC		 399 if (!x)
400 return 1;
2469cfa2 401
b18c562e
NC		 402 for (; x; x = x >> 1)
403 if (x & 1)
404 n++;
405
406 return n == 1;
407}
408
409/* Parse ordinary expression. */
410
411static char *
412parse_exp (char * s, expressionS * op)
2469cfa2 413{
b18c562e
NC		 414 input_line_pointer = s;
415 expression (op);
416 if (op->X_op == O_absent)
417 as_bad (_("missing operand"));
2bfa0cdf
NC		 418 /* Our caller is likely to check that the entire expression was parsed.
419 If we have found a hex constant with an 'h' suffix, ilp will be left
420 pointing at the 'h', so skip it here. */
421 if (input_line_pointer != NULL
422 && op->X_op == O_constant
423 && (*input_line_pointer == 'h' || *input_line_pointer == 'H'))
424 ++ input_line_pointer;
b18c562e
NC		 425 return input_line_pointer;
426}
2469cfa2 427
b18c562e
NC		 428
429/* Delete spaces from s: X ( r 1 2) => X(r12). */
2469cfa2
NC		 430
431static void
b18c562e 432del_spaces (char * s)
2469cfa2 433{
b18c562e
NC		 434 while (*s)
435 {
436 if (ISSPACE (*s))
437 {
438 char *m = s + 1;
2469cfa2 439
b18c562e
NC		 440 while (ISSPACE (*m) && *m)
441 m++;
442 memmove (s, m, strlen (m) + 1);
443 }
444 else
445 s++;
446 }
447}
2469cfa2 448
b18c562e
NC		 449static inline char *
450skip_space (char * s)
451{
452 while (ISSPACE (*s))
453 ++s;
454 return s;
455}
2469cfa2 456
708587a4 457/* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
b18c562e
NC		 458
459static char *
460extract_operand (char * from, char * to, int limit)
461{
462 int size = 0;
463
464 /* Drop leading whitespace. */
465 from = skip_space (from);
466
467 while (size < limit && *from)
468 {
469 *(to + size) = *from;
470 if (*from == ',' || *from == ';' || *from == '\n')
471 break;
472 from++;
473 size++;
474 }
475
476 *(to + size) = 0;
477 del_spaces (to);
478
479 from++;
480
481 return from;
2469cfa2
NC		 482}
483
b18c562e
NC		 484static void
485msp430_profiler (int dummy ATTRIBUTE_UNUSED)
2469cfa2 486{
b18c562e
NC		 487 char buffer[1024];
488 char f[32];
489 char * str = buffer;
490 char * flags = f;
491 int p_flags = 0;
492 char * halt;
493 int ops = 0;
494 int left;
495 char * s;
496 segT seg;
497 int subseg;
498 char * end = 0;
499 expressionS exp;
500 expressionS exp1;
501
502 s = input_line_pointer;
503 end = input_line_pointer;
504
505 while (*end && *end != '\n')
506 end++;
507
508 while (*s && *s != '\n')
509 {
510 if (*s == ',')
511 ops++;
512 s++;
513 }
2469cfa2 514
b18c562e
NC		 515 left = 3 - ops;
516
517 if (ops < 1)
518 {
519 as_bad (_(".profiler pseudo requires at least two operands."));
520 input_line_pointer = end;
521 return;
522 }
523
524 input_line_pointer = extract_operand (input_line_pointer, flags, 32);
525
526 while (*flags)
527 {
528 switch (*flags)
529 {
530 case '"':
531 break;
532 case 'a':
533 p_flags |= MSP430_PROFILER_FLAG_FRAGMENT;
534 break;
535 case 'j':
536 p_flags |= MSP430_PROFILER_FLAG_JUMP;
537 break;
538 case 'P':
539 p_flags |= MSP430_PROFILER_FLAG_PROLSTART;
540 break;
541 case 'p':
542 p_flags |= MSP430_PROFILER_FLAG_PROLEND;
543 break;
544 case 'E':
545 p_flags |= MSP430_PROFILER_FLAG_EPISTART;
546 break;
547 case 'e':
548 p_flags |= MSP430_PROFILER_FLAG_EPIEND;
549 break;
550 case 's':
551 p_flags |= MSP430_PROFILER_FLAG_ENTRY;
552 break;
553 case 'x':
554 p_flags |= MSP430_PROFILER_FLAG_EXIT;
555 break;
556 case 'i':
557 p_flags |= MSP430_PROFILER_FLAG_INITSECT;
558 break;
559 case 'f':
560 p_flags |= MSP430_PROFILER_FLAG_FINISECT;
561 break;
562 case 'l':
563 p_flags |= MSP430_PROFILER_FLAG_LIBCALL;
564 break;
565 case 'c':
566 p_flags |= MSP430_PROFILER_FLAG_STDCALL;
567 break;
568 case 'd':
569 p_flags |= MSP430_PROFILER_FLAG_STACKDMD;
570 break;
571 case 'I':
572 p_flags |= MSP430_PROFILER_FLAG_ISR;
573 break;
574 case 't':
575 p_flags |= MSP430_PROFILER_FLAG_EXTRA;
576 break;
577 default:
578 as_warn (_("unknown profiling flag - ignored."));
579 break;
580 }
581 flags++;
582 }
583
584 if (p_flags
585 && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY
586 | MSP430_PROFILER_FLAG_EXIT))
587 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART
588 | MSP430_PROFILER_FLAG_PROLEND
589 | MSP430_PROFILER_FLAG_EPISTART
590 | MSP430_PROFILER_FLAG_EPIEND))
591 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT
592 | MSP430_PROFILER_FLAG_FINISECT))))
593 {
79cf5950 594 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
b18c562e
NC		 595 input_line_pointer = end;
596 return;
597 }
598
599 /* Generate temp symbol which denotes current location. */
79cf5950 600 if (now_seg == absolute_section) /* Paranoia ? */
b18c562e
NC		 601 {
602 exp1.X_op = O_constant;
603 exp1.X_add_number = abs_section_offset;
79cf5950 604 as_warn (_("profiling in absolute section?"));
b18c562e
NC		 605 }
606 else
607 {
608 exp1.X_op = O_symbol;
609 exp1.X_add_symbol = symbol_temp_new_now ();
610 exp1.X_add_number = 0;
611 }
612
613 /* Generate a symbol which holds flags value. */
614 exp.X_op = O_constant;
615 exp.X_add_number = p_flags;
616
617 /* Save current section. */
618 seg = now_seg;
619 subseg = now_subseg;
620
621 /* Now go to .profiler section. */
a91e1603 622 obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0, 0);
b18c562e
NC		 623
624 /* Save flags. */
625 emit_expr (& exp, 2);
626
627 /* Save label value. */
628 emit_expr (& exp1, 2);
629
630 while (ops--)
631 {
632 /* Now get profiling info. */
633 halt = extract_operand (input_line_pointer, str, 1024);
634 /* Process like ".word xxx" directive. */
2bfa0cdf 635 (void) parse_exp (str, & exp);
b18c562e
NC		 636 emit_expr (& exp, 2);
637 input_line_pointer = halt;
638 }
639
640 /* Fill the rest with zeros. */
641 exp.X_op = O_constant;
642 exp.X_add_number = 0;
643 while (left--)
644 emit_expr (& exp, 2);
645
646 /* Return to current section. */
647 subseg_set (seg, subseg);
2469cfa2
NC		 648}
649
650static char *
b18c562e 651extract_word (char * from, char * to, int limit)
2469cfa2 652{
2469cfa2
NC		 653 char *op_end;
654 int size = 0;
655
656 /* Drop leading whitespace. */
657 from = skip_space (from);
658 *to = 0;
659
660 /* Find the op code end. */
87975d2a 661 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
2469cfa2
NC		 662 {
663 to[size++] = *op_end++;
664 if (size + 1 >= limit)
665 break;
666 }
667
668 to[size] = 0;
669 return op_end;
670}
671
b18c562e 672#define OPTION_MMCU 'm'
77592908
DD		 673#define OPTION_RELAX 'Q'
674#define OPTION_POLYMORPHS 'P'
13761a11
NC		 675#define OPTION_LARGE 'l'
676static bfd_boolean large_model = FALSE;
677#define OPTION_NO_INTR_NOPS 'N'
65d7bab5 678#define OPTION_INTR_NOPS 'n'
a75555d1 679static bfd_boolean gen_interrupt_nops = FALSE;
69227609
NC		 680#define OPTION_WARN_INTR_NOPS 'y'
681#define OPTION_NO_WARN_INTR_NOPS 'Y'
65d7bab5 682static bfd_boolean warn_interrupt_nops = TRUE;
638d3803 683#define OPTION_MCPU 'c'
ab905915
NC		 684#define OPTION_MOVE_DATA 'd'
685static bfd_boolean move_data = FALSE;
7ef3addb
JL		 686#define OPTION_DATA_REGION 'r'
687static bfd_boolean upper_data_region_in_use = FALSE;
b18c562e 688
2213f746
NC		 689enum
690{
691 OPTION_SILICON_ERRATA = OPTION_MD_BASE,
692 OPTION_SILICON_ERRATA_WARN,
85e53f62 693};
2213f746
NC		 694
695static unsigned int silicon_errata_fix = 0;
696static unsigned int silicon_errata_warn = 0;
697#define SILICON_ERRATA_CPU4 (1 << 0)
698#define SILICON_ERRATA_CPU8 (1 << 1)
699#define SILICON_ERRATA_CPU11 (1 << 2)
700#define SILICON_ERRATA_CPU12 (1 << 3)
701#define SILICON_ERRATA_CPU13 (1 << 4)
702#define SILICON_ERRATA_CPU19 (1 << 5)
2213f746 703
2469cfa2 704static void
638d3803 705msp430_set_arch (int option)
2469cfa2 706{
e1fa0163 707 char str[32]; /* 32 for good measure. */
2469cfa2
NC		 708
709 input_line_pointer = extract_word (input_line_pointer, str, 32);
710
638d3803
NC		 711 md_parse_option (option, str);
712 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
713 target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
2469cfa2
NC		 714}
715
ede77e69
NC		 716/* This is a copy of the same data structure found in gcc/config/msp430/msp430.c
717 Keep these two structures in sync.
4eabf344
JS		 718 The data in this structure has been extracted from version 1.194 of the
719 devices.csv file released by TI in September 2016. */
ede77e69
NC		 720
721struct msp430_mcu_data
65d7bab5 722{
ede77e69
NC		 723 const char * name;
724 unsigned int revision; /* 0=> MSP430, 1=>MSP430X, 2=> MSP430Xv2. */
725 unsigned int hwmpy; /* 0=>none, 1=>16-bit, 2=>16-bit w/sign extend, 4=>32-bit, 8=> 32-bit (5xx). */
726}
727msp430_mcu_data [] =
728{
729 { "cc430f5123",2,8 },
730 { "cc430f5125",2,8 },
731 { "cc430f5133",2,8 },
732 { "cc430f5135",2,8 },
733 { "cc430f5137",2,8 },
734 { "cc430f5143",2,8 },
735 { "cc430f5145",2,8 },
736 { "cc430f5147",2,8 },
737 { "cc430f6125",2,8 },
738 { "cc430f6126",2,8 },
739 { "cc430f6127",2,8 },
740 { "cc430f6135",2,8 },
741 { "cc430f6137",2,8 },
742 { "cc430f6143",2,8 },
743 { "cc430f6145",2,8 },
744 { "cc430f6147",2,8 },
745 { "msp430afe221",0,2 },
746 { "msp430afe222",0,2 },
747 { "msp430afe223",0,2 },
748 { "msp430afe231",0,2 },
749 { "msp430afe232",0,2 },
750 { "msp430afe233",0,2 },
751 { "msp430afe251",0,2 },
752 { "msp430afe252",0,2 },
753 { "msp430afe253",0,2 },
754 { "msp430bt5190",2,8 },
755 { "msp430c091",0,0 },
756 { "msp430c092",0,0 },
757 { "msp430c111",0,0 },
758 { "msp430c1111",0,0 },
759 { "msp430c112",0,0 },
760 { "msp430c1121",0,0 },
761 { "msp430c1331",0,0 },
762 { "msp430c1351",0,0 },
763 { "msp430c311s",0,0 },
764 { "msp430c312",0,0 },
765 { "msp430c313",0,0 },
766 { "msp430c314",0,0 },
767 { "msp430c315",0,0 },
768 { "msp430c323",0,0 },
769 { "msp430c325",0,0 },
770 { "msp430c336",0,1 },
771 { "msp430c337",0,1 },
772 { "msp430c412",0,0 },
773 { "msp430c413",0,0 },
774 { "msp430cg4616",1,1 },
775 { "msp430cg4617",1,1 },
776 { "msp430cg4618",1,1 },
777 { "msp430cg4619",1,1 },
778 { "msp430e112",0,0 },
779 { "msp430e313",0,0 },
780 { "msp430e315",0,0 },
781 { "msp430e325",0,0 },
782 { "msp430e337",0,1 },
783 { "msp430f110",0,0 },
784 { "msp430f1101",0,0 },
785 { "msp430f1101a",0,0 },
786 { "msp430f1111",0,0 },
787 { "msp430f1111a",0,0 },
788 { "msp430f112",0,0 },
789 { "msp430f1121",0,0 },
790 { "msp430f1121a",0,0 },
791 { "msp430f1122",0,0 },
792 { "msp430f1132",0,0 },
793 { "msp430f122",0,0 },
794 { "msp430f1222",0,0 },
795 { "msp430f123",0,0 },
796 { "msp430f1232",0,0 },
797 { "msp430f133",0,0 },
798 { "msp430f135",0,0 },
799 { "msp430f147",0,1 },
800 { "msp430f1471",0,1 },
801 { "msp430f148",0,1 },
802 { "msp430f1481",0,1 },
803 { "msp430f149",0,1 },
804 { "msp430f1491",0,1 },
805 { "msp430f155",0,0 },
806 { "msp430f156",0,0 },
807 { "msp430f157",0,0 },
808 { "msp430f1610",0,1 },
809 { "msp430f1611",0,1 },
810 { "msp430f1612",0,1 },
811 { "msp430f167",0,1 },
812 { "msp430f168",0,1 },
813 { "msp430f169",0,1 },
814 { "msp430f2001",0,0 },
815 { "msp430f2002",0,0 },
816 { "msp430f2003",0,0 },
817 { "msp430f2011",0,0 },
818 { "msp430f2012",0,0 },
819 { "msp430f2013",0,0 },
820 { "msp430f2101",0,0 },
821 { "msp430f2111",0,0 },
822 { "msp430f2112",0,0 },
823 { "msp430f2121",0,0 },
824 { "msp430f2122",0,0 },
825 { "msp430f2131",0,0 },
826 { "msp430f2132",0,0 },
827 { "msp430f2232",0,0 },
828 { "msp430f2234",0,0 },
829 { "msp430f2252",0,0 },
830 { "msp430f2254",0,0 },
831 { "msp430f2272",0,0 },
832 { "msp430f2274",0,0 },
833 { "msp430f233",0,2 },
834 { "msp430f2330",0,2 },
835 { "msp430f235",0,2 },
836 { "msp430f2350",0,2 },
837 { "msp430f2370",0,2 },
838 { "msp430f2410",0,2 },
839 { "msp430f2416",1,2 },
840 { "msp430f2417",1,2 },
841 { "msp430f2418",1,2 },
842 { "msp430f2419",1,2 },
843 { "msp430f247",0,2 },
844 { "msp430f2471",0,2 },
845 { "msp430f248",0,2 },
846 { "msp430f2481",0,2 },
847 { "msp430f249",0,2 },
848 { "msp430f2491",0,2 },
849 { "msp430f2616",1,2 },
850 { "msp430f2617",1,2 },
851 { "msp430f2618",1,2 },
852 { "msp430f2619",1,2 },
853 { "msp430f412",0,0 },
854 { "msp430f413",0,0 },
855 { "msp430f4132",0,0 },
856 { "msp430f415",0,0 },
857 { "msp430f4152",0,0 },
858 { "msp430f417",0,0 },
859 { "msp430f423",0,1 },
860 { "msp430f423a",0,1 },
861 { "msp430f425",0,1 },
862 { "msp430f4250",0,0 },
863 { "msp430f425a",0,1 },
864 { "msp430f4260",0,0 },
865 { "msp430f427",0,1 },
866 { "msp430f4270",0,0 },
867 { "msp430f427a",0,1 },
868 { "msp430f435",0,0 },
869 { "msp430f4351",0,0 },
870 { "msp430f436",0,0 },
871 { "msp430f4361",0,0 },
872 { "msp430f437",0,0 },
873 { "msp430f4371",0,0 },
874 { "msp430f438",0,0 },
875 { "msp430f439",0,0 },
876 { "msp430f447",0,1 },
877 { "msp430f448",0,1 },
878 { "msp430f4481",0,1 },
879 { "msp430f449",0,1 },
880 { "msp430f4491",0,1 },
881 { "msp430f4616",1,1 },
882 { "msp430f46161",1,1 },
883 { "msp430f4617",1,1 },
884 { "msp430f46171",1,1 },
885 { "msp430f4618",1,1 },
886 { "msp430f46181",1,1 },
887 { "msp430f4619",1,1 },
888 { "msp430f46191",1,1 },
889 { "msp430f47126",1,4 },
890 { "msp430f47127",1,4 },
891 { "msp430f47163",1,4 },
892 { "msp430f47166",1,4 },
893 { "msp430f47167",1,4 },
894 { "msp430f47173",1,4 },
895 { "msp430f47176",1,4 },
896 { "msp430f47177",1,4 },
897 { "msp430f47183",1,4 },
898 { "msp430f47186",1,4 },
899 { "msp430f47187",1,4 },
900 { "msp430f47193",1,4 },
901 { "msp430f47196",1,4 },
902 { "msp430f47197",1,4 },
903 { "msp430f477",0,0 },
904 { "msp430f478",0,0 },
905 { "msp430f4783",0,4 },
906 { "msp430f4784",0,4 },
907 { "msp430f479",0,0 },
908 { "msp430f4793",0,4 },
909 { "msp430f4794",0,4 },
910 { "msp430f5131",2,8 },
911 { "msp430f5132",2,8 },
912 { "msp430f5151",2,8 },
913 { "msp430f5152",2,8 },
914 { "msp430f5171",2,8 },
915 { "msp430f5172",2,8 },
916 { "msp430f5212",2,8 },
917 { "msp430f5213",2,8 },
918 { "msp430f5214",2,8 },
919 { "msp430f5217",2,8 },
920 { "msp430f5218",2,8 },
921 { "msp430f5219",2,8 },
922 { "msp430f5222",2,8 },
923 { "msp430f5223",2,8 },
924 { "msp430f5224",2,8 },
925 { "msp430f5227",2,8 },
926 { "msp430f5228",2,8 },
927 { "msp430f5229",2,8 },
928 { "msp430f5232",2,8 },
929 { "msp430f5234",2,8 },
930 { "msp430f5237",2,8 },
931 { "msp430f5239",2,8 },
932 { "msp430f5242",2,8 },
933 { "msp430f5244",2,8 },
934 { "msp430f5247",2,8 },
935 { "msp430f5249",2,8 },
936 { "msp430f5252",2,8 },
937 { "msp430f5253",2,8 },
938 { "msp430f5254",2,8 },
939 { "msp430f5255",2,8 },
940 { "msp430f5256",2,8 },
941 { "msp430f5257",2,8 },
942 { "msp430f5258",2,8 },
943 { "msp430f5259",2,8 },
944 { "msp430f5304",2,8 },
945 { "msp430f5308",2,8 },
946 { "msp430f5309",2,8 },
947 { "msp430f5310",2,8 },
948 { "msp430f5324",2,8 },
949 { "msp430f5325",2,8 },
950 { "msp430f5326",2,8 },
951 { "msp430f5327",2,8 },
952 { "msp430f5328",2,8 },
953 { "msp430f5329",2,8 },
954 { "msp430f5333",2,8 },
955 { "msp430f5335",2,8 },
956 { "msp430f5336",2,8 },
957 { "msp430f5338",2,8 },
958 { "msp430f5340",2,8 },
959 { "msp430f5341",2,8 },
960 { "msp430f5342",2,8 },
961 { "msp430f5358",2,8 },
962 { "msp430f5359",2,8 },
963 { "msp430f5418",2,8 },
964 { "msp430f5418a",2,8 },
965 { "msp430f5419",2,8 },
966 { "msp430f5419a",2,8 },
967 { "msp430f5435",2,8 },
968 { "msp430f5435a",2,8 },
969 { "msp430f5436",2,8 },
970 { "msp430f5436a",2,8 },
971 { "msp430f5437",2,8 },
972 { "msp430f5437a",2,8 },
973 { "msp430f5438",2,8 },
974 { "msp430f5438a",2,8 },
975 { "msp430f5500",2,8 },
976 { "msp430f5501",2,8 },
977 { "msp430f5502",2,8 },
978 { "msp430f5503",2,8 },
979 { "msp430f5504",2,8 },
980 { "msp430f5505",2,8 },
981 { "msp430f5506",2,8 },
982 { "msp430f5507",2,8 },
983 { "msp430f5508",2,8 },
984 { "msp430f5509",2,8 },
985 { "msp430f5510",2,8 },
986 { "msp430f5513",2,8 },
987 { "msp430f5514",2,8 },
988 { "msp430f5515",2,8 },
989 { "msp430f5517",2,8 },
990 { "msp430f5519",2,8 },
991 { "msp430f5521",2,8 },
992 { "msp430f5522",2,8 },
993 { "msp430f5524",2,8 },
994 { "msp430f5525",2,8 },
995 { "msp430f5526",2,8 },
996 { "msp430f5527",2,8 },
997 { "msp430f5528",2,8 },
998 { "msp430f5529",2,8 },
999 { "msp430f5630",2,8 },
1000 { "msp430f5631",2,8 },
1001 { "msp430f5632",2,8 },
1002 { "msp430f5633",2,8 },
1003 { "msp430f5634",2,8 },
1004 { "msp430f5635",2,8 },
1005 { "msp430f5636",2,8 },
1006 { "msp430f5637",2,8 },
1007 { "msp430f5638",2,8 },
1008 { "msp430f5658",2,8 },
1009 { "msp430f5659",2,8 },
1010 { "msp430f5xx_6xxgeneric",2,8 },
1011 { "msp430f6433",2,8 },
1012 { "msp430f6435",2,8 },
1013 { "msp430f6436",2,8 },
1014 { "msp430f6438",2,8 },
1015 { "msp430f6458",2,8 },
1016 { "msp430f6459",2,8 },
1017 { "msp430f6630",2,8 },
1018 { "msp430f6631",2,8 },
1019 { "msp430f6632",2,8 },
1020 { "msp430f6633",2,8 },
1021 { "msp430f6634",2,8 },
1022 { "msp430f6635",2,8 },
1023 { "msp430f6636",2,8 },
1024 { "msp430f6637",2,8 },
1025 { "msp430f6638",2,8 },
1026 { "msp430f6658",2,8 },
1027 { "msp430f6659",2,8 },
1028 { "msp430f6720",2,8 },
1029 { "msp430f6720a",2,8 },
1030 { "msp430f6721",2,8 },
1031 { "msp430f6721a",2,8 },
1032 { "msp430f6723",2,8 },
1033 { "msp430f6723a",2,8 },
1034 { "msp430f6724",2,8 },
1035 { "msp430f6724a",2,8 },
1036 { "msp430f6725",2,8 },
1037 { "msp430f6725a",2,8 },
1038 { "msp430f6726",2,8 },
1039 { "msp430f6726a",2,8 },
1040 { "msp430f6730",2,8 },
1041 { "msp430f6730a",2,8 },
1042 { "msp430f6731",2,8 },
1043 { "msp430f6731a",2,8 },
1044 { "msp430f6733",2,8 },
1045 { "msp430f6733a",2,8 },
1046 { "msp430f6734",2,8 },
1047 { "msp430f6734a",2,8 },
1048 { "msp430f6735",2,8 },
1049 { "msp430f6735a",2,8 },
1050 { "msp430f6736",2,8 },
1051 { "msp430f6736a",2,8 },
1052 { "msp430f6745",2,8 },
1053 { "msp430f67451",2,8 },
1054 { "msp430f67451a",2,8 },
1055 { "msp430f6745a",2,8 },
1056 { "msp430f6746",2,8 },
1057 { "msp430f67461",2,8 },
1058 { "msp430f67461a",2,8 },
1059 { "msp430f6746a",2,8 },
1060 { "msp430f6747",2,8 },
1061 { "msp430f67471",2,8 },
1062 { "msp430f67471a",2,8 },
1063 { "msp430f6747a",2,8 },
1064 { "msp430f6748",2,8 },
1065 { "msp430f67481",2,8 },
1066 { "msp430f67481a",2,8 },
1067 { "msp430f6748a",2,8 },
1068 { "msp430f6749",2,8 },
1069 { "msp430f67491",2,8 },
1070 { "msp430f67491a",2,8 },
1071 { "msp430f6749a",2,8 },
1072 { "msp430f67621",2,8 },
1073 { "msp430f67621a",2,8 },
1074 { "msp430f67641",2,8 },
1075 { "msp430f67641a",2,8 },
1076 { "msp430f6765",2,8 },
1077 { "msp430f67651",2,8 },
1078 { "msp430f67651a",2,8 },
1079 { "msp430f6765a",2,8 },
1080 { "msp430f6766",2,8 },
1081 { "msp430f67661",2,8 },
1082 { "msp430f67661a",2,8 },
1083 { "msp430f6766a",2,8 },
1084 { "msp430f6767",2,8 },
1085 { "msp430f67671",2,8 },
1086 { "msp430f67671a",2,8 },
1087 { "msp430f6767a",2,8 },
1088 { "msp430f6768",2,8 },
1089 { "msp430f67681",2,8 },
1090 { "msp430f67681a",2,8 },
1091 { "msp430f6768a",2,8 },
1092 { "msp430f6769",2,8 },
1093 { "msp430f67691",2,8 },
1094 { "msp430f67691a",2,8 },
1095 { "msp430f6769a",2,8 },
1096 { "msp430f6775",2,8 },
1097 { "msp430f67751",2,8 },
1098 { "msp430f67751a",2,8 },
1099 { "msp430f6775a",2,8 },
1100 { "msp430f6776",2,8 },
1101 { "msp430f67761",2,8 },
1102 { "msp430f67761a",2,8 },
1103 { "msp430f6776a",2,8 },
1104 { "msp430f6777",2,8 },
1105 { "msp430f67771",2,8 },
1106 { "msp430f67771a",2,8 },
1107 { "msp430f6777a",2,8 },
1108 { "msp430f6778",2,8 },
1109 { "msp430f67781",2,8 },
1110 { "msp430f67781a",2,8 },
1111 { "msp430f6778a",2,8 },
1112 { "msp430f6779",2,8 },
1113 { "msp430f67791",2,8 },
1114 { "msp430f67791a",2,8 },
1115 { "msp430f6779a",2,8 },
1116 { "msp430fe423",0,0 },
1117 { "msp430fe4232",0,0 },
1118 { "msp430fe423a",0,0 },
1119 { "msp430fe4242",0,0 },
1120 { "msp430fe425",0,0 },
1121 { "msp430fe4252",0,0 },
1122 { "msp430fe425a",0,0 },
1123 { "msp430fe427",0,0 },
1124 { "msp430fe4272",0,0 },
1125 { "msp430fe427a",0,0 },
1126 { "msp430fg4250",0,0 },
1127 { "msp430fg4260",0,0 },
1128 { "msp430fg4270",0,0 },
1129 { "msp430fg437",0,0 },
1130 { "msp430fg438",0,0 },
1131 { "msp430fg439",0,0 },
1132 { "msp430fg4616",1,1 },
1133 { "msp430fg4617",1,1 },
1134 { "msp430fg4618",1,1 },
1135 { "msp430fg4619",1,1 },
1136 { "msp430fg477",0,0 },
1137 { "msp430fg478",0,0 },
1138 { "msp430fg479",0,0 },
1139 { "msp430fg6425",2,8 },
1140 { "msp430fg6426",2,8 },
1141 { "msp430fg6625",2,8 },
1142 { "msp430fg6626",2,8 },
1143 { "msp430fr2032",2,0 },
1144 { "msp430fr2033",2,0 },
4eabf344
JS		 1145 { "msp430fr2110",2,0 },
1146 { "msp430fr2111",2,0 },
b27c40ec
NC		 1147 { "msp430fr2310",2,0 },
1148 { "msp430fr2311",2,0 },
ede77e69 1149 { "msp430fr2433",2,8 },
b27c40ec
NC		 1150 { "msp430fr2532",2,8 },
1151 { "msp430fr2533",2,8 },
1152 { "msp430fr2632",2,8 },
1153 { "msp430fr2633",2,8 },
ede77e69
NC		 1154 { "msp430fr2xx_4xxgeneric",2,8 },
1155 { "msp430fr4131",2,0 },
1156 { "msp430fr4132",2,0 },
1157 { "msp430fr4133",2,0 },
1158 { "msp430fr5720",2,8 },
1159 { "msp430fr5721",2,8 },
1160 { "msp430fr5722",2,8 },
1161 { "msp430fr5723",2,8 },
1162 { "msp430fr5724",2,8 },
1163 { "msp430fr5725",2,8 },
1164 { "msp430fr5726",2,8 },
1165 { "msp430fr5727",2,8 },
1166 { "msp430fr5728",2,8 },
1167 { "msp430fr5729",2,8 },
1168 { "msp430fr5730",2,8 },
1169 { "msp430fr5731",2,8 },
1170 { "msp430fr5732",2,8 },
1171 { "msp430fr5733",2,8 },
1172 { "msp430fr5734",2,8 },
1173 { "msp430fr5735",2,8 },
1174 { "msp430fr5736",2,8 },
1175 { "msp430fr5737",2,8 },
1176 { "msp430fr5738",2,8 },
1177 { "msp430fr5739",2,8 },
1178 { "msp430fr57xxgeneric",2,8 },
1179 { "msp430fr5847",2,8 },
1180 { "msp430fr58471",2,8 },
1181 { "msp430fr5848",2,8 },
1182 { "msp430fr5849",2,8 },
1183 { "msp430fr5857",2,8 },
1184 { "msp430fr5858",2,8 },
1185 { "msp430fr5859",2,8 },
1186 { "msp430fr5867",2,8 },
1187 { "msp430fr58671",2,8 },
1188 { "msp430fr5868",2,8 },
1189 { "msp430fr5869",2,8 },
1190 { "msp430fr5870",2,8 },
1191 { "msp430fr5872",2,8 },
1192 { "msp430fr58721",2,8 },
1193 { "msp430fr5887",2,8 },
1194 { "msp430fr5888",2,8 },
1195 { "msp430fr5889",2,8 },
1196 { "msp430fr58891",2,8 },
1197 { "msp430fr5922",2,8 },
1198 { "msp430fr59221",2,8 },
1199 { "msp430fr5947",2,8 },
1200 { "msp430fr59471",2,8 },
1201 { "msp430fr5948",2,8 },
1202 { "msp430fr5949",2,8 },
1203 { "msp430fr5957",2,8 },
1204 { "msp430fr5958",2,8 },
1205 { "msp430fr5959",2,8 },
b27c40ec
NC		 1206 { "msp430fr5962",2,8 },
1207 { "msp430fr5964",2,8 },
ede77e69
NC		 1208 { "msp430fr5967",2,8 },
1209 { "msp430fr5968",2,8 },
1210 { "msp430fr5969",2,8 },
1211 { "msp430fr59691",2,8 },
1212 { "msp430fr5970",2,8 },
1213 { "msp430fr5972",2,8 },
1214 { "msp430fr59721",2,8 },
1215 { "msp430fr5986",2,8 },
1216 { "msp430fr5987",2,8 },
1217 { "msp430fr5988",2,8 },
1218 { "msp430fr5989",2,8 },
1219 { "msp430fr59891",2,8 },
b27c40ec
NC		 1220 { "msp430fr5992",2,8 },
1221 { "msp430fr5994",2,8 },
4eabf344 1222 { "msp430fr59941",2,8 },
ede77e69
NC		 1223 { "msp430fr5xx_6xxgeneric",2,8 },
1224 { "msp430fr6820",2,8 },
1225 { "msp430fr6822",2,8 },
1226 { "msp430fr68221",2,8 },
1227 { "msp430fr6870",2,8 },
1228 { "msp430fr6872",2,8 },
1229 { "msp430fr68721",2,8 },
1230 { "msp430fr6877",2,8 },
1231 { "msp430fr6879",2,8 },
1232 { "msp430fr68791",2,8 },
1233 { "msp430fr6887",2,8 },
1234 { "msp430fr6888",2,8 },
1235 { "msp430fr6889",2,8 },
1236 { "msp430fr68891",2,8 },
1237 { "msp430fr6920",2,8 },
1238 { "msp430fr6922",2,8 },
1239 { "msp430fr69221",2,8 },
1240 { "msp430fr6927",2,8 },
1241 { "msp430fr69271",2,8 },
1242 { "msp430fr6928",2,8 },
1243 { "msp430fr6970",2,8 },
1244 { "msp430fr6972",2,8 },
1245 { "msp430fr69721",2,8 },
1246 { "msp430fr6977",2,8 },
1247 { "msp430fr6979",2,8 },
1248 { "msp430fr69791",2,8 },
1249 { "msp430fr6987",2,8 },
1250 { "msp430fr6988",2,8 },
1251 { "msp430fr6989",2,8 },
1252 { "msp430fr69891",2,8 },
1253 { "msp430fw423",0,0 },
1254 { "msp430fw425",0,0 },
1255 { "msp430fw427",0,0 },
1256 { "msp430fw428",0,0 },
1257 { "msp430fw429",0,0 },
1258 { "msp430g2001",0,0 },
1259 { "msp430g2101",0,0 },
1260 { "msp430g2102",0,0 },
1261 { "msp430g2111",0,0 },
1262 { "msp430g2112",0,0 },
1263 { "msp430g2113",0,0 },
1264 { "msp430g2121",0,0 },
1265 { "msp430g2131",0,0 },
1266 { "msp430g2132",0,0 },
1267 { "msp430g2152",0,0 },
1268 { "msp430g2153",0,0 },
1269 { "msp430g2201",0,0 },
1270 { "msp430g2202",0,0 },
1271 { "msp430g2203",0,0 },
1272 { "msp430g2210",0,0 },
1273 { "msp430g2211",0,0 },
1274 { "msp430g2212",0,0 },
1275 { "msp430g2213",0,0 },
1276 { "msp430g2221",0,0 },
1277 { "msp430g2230",0,0 },
1278 { "msp430g2231",0,0 },
1279 { "msp430g2232",0,0 },
1280 { "msp430g2233",0,0 },
1281 { "msp430g2252",0,0 },
1282 { "msp430g2253",0,0 },
1283 { "msp430g2302",0,0 },
1284 { "msp430g2303",0,0 },
1285 { "msp430g2312",0,0 },
1286 { "msp430g2313",0,0 },
1287 { "msp430g2332",0,0 },
1288 { "msp430g2333",0,0 },
1289 { "msp430g2352",0,0 },
1290 { "msp430g2353",0,0 },
1291 { "msp430g2402",0,0 },
1292 { "msp430g2403",0,0 },
1293 { "msp430g2412",0,0 },
1294 { "msp430g2413",0,0 },
1295 { "msp430g2432",0,0 },
1296 { "msp430g2433",0,0 },
1297 { "msp430g2444",0,0 },
1298 { "msp430g2452",0,0 },
1299 { "msp430g2453",0,0 },
1300 { "msp430g2513",0,0 },
1301 { "msp430g2533",0,0 },
1302 { "msp430g2544",0,0 },
1303 { "msp430g2553",0,0 },
1304 { "msp430g2744",0,0 },
1305 { "msp430g2755",0,0 },
1306 { "msp430g2855",0,0 },
1307 { "msp430g2955",0,0 },
1308 { "msp430i2020",0,2 },
1309 { "msp430i2021",0,2 },
1310 { "msp430i2030",0,2 },
1311 { "msp430i2031",0,2 },
1312 { "msp430i2040",0,2 },
1313 { "msp430i2041",0,2 },
1314 { "msp430i2xxgeneric",0,2 },
1315 { "msp430l092",0,0 },
1316 { "msp430p112",0,0 },
1317 { "msp430p313",0,0 },
1318 { "msp430p315",0,0 },
1319 { "msp430p315s",0,0 },
1320 { "msp430p325",0,0 },
1321 { "msp430p337",0,1 },
1322 { "msp430sl5438a",2,8 },
1323 { "msp430tch5e",0,0 },
1324 { "msp430xgeneric",2,8 },
1325 { "rf430f5144",2,8 },
1326 { "rf430f5155",2,8 },
1327 { "rf430f5175",2,8 },
1328 { "rf430frl152h",0,0 },
1329 { "rf430frl152h_rom",0,0 },
1330 { "rf430frl153h",0,0 },
1331 { "rf430frl153h_rom",0,0 },
1332 { "rf430frl154h",0,0 },
1333 { "rf430frl154h_rom",0,0 }
1334};
65d7bab5 1335
2469cfa2 1336int
17b9d67d 1337md_parse_option (int c, const char * arg)
2469cfa2 1338{
2469cfa2
NC		 1339 switch (c)
1340 {
2213f746
NC		 1341 case OPTION_SILICON_ERRATA:
1342 case OPTION_SILICON_ERRATA_WARN:
1343 {
1344 signed int i;
1345 const struct
1346 {
e0471c16 1347 const char * name;
2213f746
NC		 1348 unsigned int length;
1349 unsigned int bitfield;
1350 } erratas[] =
1351 {
1352 { STRING_COMMA_LEN ("cpu4"), SILICON_ERRATA_CPU4 },
1353 { STRING_COMMA_LEN ("cpu8"), SILICON_ERRATA_CPU8 },
1354 { STRING_COMMA_LEN ("cpu11"), SILICON_ERRATA_CPU11 },
1355 { STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12 },
1356 { STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13 },
1357 { STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19 },
2213f746
NC		 1358 };
1359
1360 do
1361 {
1362 for (i = ARRAY_SIZE (erratas); i--;)
1363 if (strncasecmp (arg, erratas[i].name, erratas[i].length) == 0)
1364 {
1365 if (c == OPTION_SILICON_ERRATA)
1366 silicon_errata_fix |= erratas[i].bitfield;
1367 else
1368 silicon_errata_warn |= erratas[i].bitfield;
1369 arg += erratas[i].length;
1370 break;
1371 }
1372 if (i < 0)
1373 {
1374 as_warn (_("Unrecognised CPU errata name starting here: %s"), arg);
1375 break;
1376 }
1377 if (*arg == 0)
1378 break;
1379 if (*arg != ',')
1380 as_warn (_("Expecting comma after CPU errata name, not: %s"), arg);
1381 else
1382 arg ++;
1383 }
1384 while (*arg != 0);
1385 }
1386 return 1;
1387
2469cfa2 1388 case OPTION_MMCU:
638d3803
NC		 1389 if (arg == NULL)
1390 as_fatal (_("MCU option requires a name\n"));
1391
65d7bab5
NC		 1392 if (strcasecmp ("msp430", arg) == 0)
1393 selected_isa = MSP_ISA_430;
1394 else if (strcasecmp ("msp430xv2", arg) == 0)
1395 selected_isa = MSP_ISA_430Xv2;
1396 else if (strcasecmp ("msp430x", arg) == 0)
1397 selected_isa = MSP_ISA_430X;
1398 else
2469cfa2 1399 {
65d7bab5
NC		 1400 int i;
1401
ede77e69
NC		 1402 for (i = ARRAY_SIZE (msp430_mcu_data); i--;)
1403 if (strcasecmp (msp430_mcu_data[i].name, arg) == 0)
65d7bab5 1404 {
ede77e69
NC		 1405 switch (msp430_mcu_data[i].revision)
1406 {
1407 case 0: selected_isa = MSP_ISA_430; break;
1408 case 1: selected_isa = MSP_ISA_430X; break;
1409 case 2: selected_isa = MSP_ISA_430Xv2; break;
1410 }
65d7bab5
NC		 1411 break;
1412 }
2469cfa2 1413 }
8e75a78f 1414 /* It is not an error if we do not match the MCU name. */
2469cfa2 1415 return 1;
65d7bab5 1416
638d3803 1417 case OPTION_MCPU:
8e75a78f
NC		 1418 if (strcmp (arg, "430") == 0
1419 || strcasecmp (arg, "msp430") == 0)
65d7bab5 1420 selected_isa = MSP_ISA_430;
8e75a78f
NC		 1421 else if (strcasecmp (arg, "430x") == 0
1422 || strcasecmp (arg, "msp430x") == 0)
65d7bab5 1423 selected_isa = MSP_ISA_430X;
8e75a78f
NC		 1424 else if (strcasecmp (arg, "430xv2") == 0
1425 || strcasecmp (arg, "msp430xv2") == 0)
65d7bab5 1426 selected_isa = MSP_ISA_430Xv2;
638d3803
NC		 1427 else
1428 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg);
638d3803 1429 return 1;
38d77545 1430
77592908 1431 case OPTION_RELAX:
13761a11 1432 msp430_enable_relax = 1;
77592908 1433 return 1;
13761a11 1434
77592908
DD		 1435 case OPTION_POLYMORPHS:
1436 msp430_enable_polys = 1;
1437 return 1;
13761a11
NC		 1438
1439 case OPTION_LARGE:
1440 large_model = TRUE;
1441 return 1;
1442
1443 case OPTION_NO_INTR_NOPS:
1444 gen_interrupt_nops = FALSE;
1445 return 1;
a75555d1
NC		 1446 case OPTION_INTR_NOPS:
1447 gen_interrupt_nops = TRUE;
1448 return 1;
ab905915 1449
65d7bab5
NC		 1450 case OPTION_WARN_INTR_NOPS:
1451 warn_interrupt_nops = TRUE;
1452 return 1;
1453 case OPTION_NO_WARN_INTR_NOPS:
1454 warn_interrupt_nops = FALSE;
1455 return 1;
1456
ab905915
NC		 1457 case OPTION_MOVE_DATA:
1458 move_data = TRUE;
1459 return 1;
7ef3addb
JL		 1460
1461 case OPTION_DATA_REGION:
1462 if (strcmp (arg, "upper") == 0
1463 || strcmp (arg, "either") == 0)
1464 upper_data_region_in_use = TRUE;
1465 return 1;
2469cfa2
NC		 1466 }
1467
1468 return 0;
1469}
1470
34b822e3
DD		 1471/* The intention here is to have the mere presence of these sections
1472 cause the object to have a reference to a well-known symbol. This
1473 reference pulls in the bits of the runtime (crt0) that initialize
1474 these sections. Thus, for example, the startup code to call
1475 memset() to initialize .bss will only be linked in when there is a
1476 non-empty .bss section. Otherwise, the call would exist but have a
1477 zero length parameter, which is a waste of memory and cycles.
1478
1479 The code which initializes these sections should have a global
1480 label for these symbols, and should be marked with KEEP() in the
837a17b3
NC		 1481 linker script. */
1482
ab905915 1483static void
837a17b3 1484msp430_make_init_symbols (const char * name)
ab905915 1485{
ab905915
NC		 1486 if (strncmp (name, ".bss", 4) == 0
1487 || strncmp (name, ".gnu.linkonce.b.", 16) == 0)
1488 (void) symbol_find_or_make ("__crt0_init_bss");
1489
34b822e3
DD		 1490 if (strncmp (name, ".data", 5) == 0
1491 || strncmp (name, ".gnu.linkonce.d.", 16) == 0)
ab905915
NC		 1492 (void) symbol_find_or_make ("__crt0_movedata");
1493
837a17b3
NC		 1494 /* Note - data assigned to the .either.data section may end up being
1495 placed in the .upper.data section if the .lower.data section is
7ef3addb
JL		 1496 full. Hence the need to define the crt0 symbol.
1497 The linker may create upper or either data sections, even when none exist
1498 at the moment, so use the value of the data-region flag to determine if
1499 the symbol is needed. */
837a17b3 1500 if (strncmp (name, ".either.data", 12) == 0
7ef3addb
JL		 1501 || strncmp (name, ".upper.data", 11) == 0
1502 || upper_data_region_in_use)
837a17b3
NC		 1503 (void) symbol_find_or_make ("__crt0_move_highdata");
1504
1505 /* See note about .either.data above. */
1506 if (strncmp (name, ".upper.bss", 10) == 0
7ef3addb
JL		 1507 || strncmp (name, ".either.bss", 11) == 0
1508 || upper_data_region_in_use)
837a17b3
NC		 1509 (void) symbol_find_or_make ("__crt0_init_highbss");
1510}
1511
1512static void
1513msp430_section (int arg)
1514{
1515 char * saved_ilp = input_line_pointer;
b9bb4a93 1516 const char * name = obj_elf_section_name ();
837a17b3
NC		 1517
1518 msp430_make_init_symbols (name);
3739860c 1519
ab905915
NC		 1520 input_line_pointer = saved_ilp;
1521 obj_elf_section (arg);
1522}
1523
34b822e3
DD		 1524void
1525msp430_frob_section (asection *sec)
1526{
1527 const char *name = sec->name;
1528
1529 if (sec->size == 0)
1530 return;
1531
837a17b3 1532 msp430_make_init_symbols (name);
34b822e3
DD		 1533}
1534
1535static void
1536msp430_lcomm (int ignore ATTRIBUTE_UNUSED)
1537{
1538 symbolS *symbolP = s_comm_internal (0, s_lcomm_internal);
1539
1540 if (symbolP)
1541 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
1542 (void) symbol_find_or_make ("__crt0_init_bss");
1543}
1544
1545static void
1546msp430_comm (int needs_align)
1547{
1548 s_comm_internal (needs_align, elf_common_parse);
1549 (void) symbol_find_or_make ("__crt0_init_bss");
1550}
1551
96b96102
DD		 1552static void
1553msp430_refsym (int arg ATTRIBUTE_UNUSED)
1554{
1555 char sym_name[1024];
1556 input_line_pointer = extract_word (input_line_pointer, sym_name, 1024);
1557
1558 (void) symbol_find_or_make (sym_name);
1559}
1560
b18c562e 1561const pseudo_typeS md_pseudo_table[] =
2469cfa2 1562{
638d3803
NC		 1563 {"arch", msp430_set_arch, OPTION_MMCU},
1564 {"cpu", msp430_set_arch, OPTION_MCPU},
b18c562e 1565 {"profiler", msp430_profiler, 0},
ab905915
NC		 1566 {"section", msp430_section, 0},
1567 {"section.s", msp430_section, 0},
1568 {"sect", msp430_section, 0},
1569 {"sect.s", msp430_section, 0},
1570 {"pushsection", msp430_section, 1},
96b96102 1571 {"refsym", msp430_refsym, 0},
34b822e3
DD		 1572 {"comm", msp430_comm, 0},
1573 {"lcomm", msp430_lcomm, 0},
b18c562e
NC		 1574 {NULL, NULL, 0}
1575};
2469cfa2 1576
69227609 1577const char *md_shortopts = "mm:,mP,mQ,ml,mN,mn,my,mY";
2469cfa2 1578
b18c562e 1579struct option md_longopts[] =
2469cfa2 1580{
2213f746
NC		 1581 {"msilicon-errata", required_argument, NULL, OPTION_SILICON_ERRATA},
1582 {"msilicon-errata-warn", required_argument, NULL, OPTION_SILICON_ERRATA_WARN},
b18c562e 1583 {"mmcu", required_argument, NULL, OPTION_MMCU},
638d3803 1584 {"mcpu", required_argument, NULL, OPTION_MCPU},
77592908
DD		 1585 {"mP", no_argument, NULL, OPTION_POLYMORPHS},
1586 {"mQ", no_argument, NULL, OPTION_RELAX},
13761a11
NC		 1587 {"ml", no_argument, NULL, OPTION_LARGE},
1588 {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS},
a75555d1 1589 {"mn", no_argument, NULL, OPTION_INTR_NOPS},
69227609
NC		 1590 {"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS},
1591 {"my", no_argument, NULL, OPTION_WARN_INTR_NOPS},
ab905915 1592 {"md", no_argument, NULL, OPTION_MOVE_DATA},
7ef3addb 1593 {"mdata-region", required_argument, NULL, OPTION_DATA_REGION},
b18c562e
NC		 1594 {NULL, no_argument, NULL, 0}
1595};
2469cfa2 1596
b18c562e 1597size_t md_longopts_size = sizeof (md_longopts);
2469cfa2 1598
b18c562e
NC		 1599void
1600md_show_usage (FILE * stream)
2469cfa2 1601{
b18c562e
NC		 1602 fprintf (stream,
1603 _("MSP430 options:\n"
638d3803
NC		 1604 " -mmcu=<msp430-name> - select microcontroller type\n"
1605 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
2213f746
NC		 1606 fprintf (stream,
1607 _(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
1608 " -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
ff1fe6fa 1609 " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
77592908
DD		 1610 fprintf (stream,
1611 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
1612 " -mP - enable polymorph instructions\n"));
13761a11
NC		 1613 fprintf (stream,
1614 _(" -ml - enable large code model\n"));
1615 fprintf (stream,
65d7bab5 1616 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
a75555d1 1617 fprintf (stream,
65d7bab5
NC		 1618 _(" -mn - insert a NOP after changing interrupts\n"));
1619 fprintf (stream,
69227609 1620 _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
65d7bab5 1621 fprintf (stream,
69227609 1622 _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
ab905915
NC		 1623 fprintf (stream,
1624 _(" -md - Force copying of data from ROM to RAM at startup\n"));
7ef3addb
JL		 1625 fprintf (stream,
1626 _(" -mdata-region={none|lower|upper|either} - select region data will be\n"
1627 " placed in.\n"));
b18c562e 1628}
2469cfa2 1629
b18c562e
NC		 1630symbolS *
1631md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
1632{
13761a11 1633 return NULL;
2469cfa2
NC		 1634}
1635
1636static char *
b18c562e 1637extract_cmd (char * from, char * to, int limit)
2469cfa2
NC		 1638{
1639 int size = 0;
1640
1641 while (*from && ! ISSPACE (*from) && *from != '.' && limit > size)
1642 {
1643 *(to + size) = *from;
1644 from++;
1645 size++;
1646 }
1647
1648 *(to + size) = 0;
1649
1650 return from;
1651}
1652
6d4af3c2 1653const char *
b18c562e 1654md_atof (int type, char * litP, int * sizeP)
2469cfa2 1655{
499ac353 1656 return ieee_md_atof (type, litP, sizeP, FALSE);
2469cfa2
NC		 1657}
1658
1659void
b18c562e 1660md_begin (void)
2469cfa2 1661{
b18c562e 1662 struct msp430_opcode_s * opcode;
2469cfa2
NC		 1663 msp430_hash = hash_new ();
1664
1665 for (opcode = msp430_opcodes; opcode->name; opcode++)
1666 hash_insert (msp430_hash, opcode->name, (char *) opcode);
1667
638d3803
NC		 1668 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
1669 target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
9117cd3e
TS		 1670
1671 /* Set linkrelax here to avoid fixups in most sections. */
1672 linkrelax = 1;
2469cfa2
NC		 1673}
1674
13761a11
NC		 1675/* Returns the register number equivalent to the string T.
1676 Returns -1 if there is no such register.
1677 Skips a leading 'r' or 'R' character if there is one.
1678 Handles the register aliases PC and SP. */
1679
1680static signed int
b18c562e 1681check_reg (char * t)
2469cfa2 1682{
13761a11 1683 signed int val;
2469cfa2 1684
13761a11
NC		 1685 if (t == NULL)
1686 return -1;
2469cfa2 1687
13761a11
NC		 1688 if (*t == 'r' || *t == 'R')
1689 ++t;
1690
1691 if (strncasecmp (t, "pc", 2) == 0)
1692 return 0;
2469cfa2 1693
13761a11 1694 if (strncasecmp (t, "sp", 2) == 0)
b18c562e 1695 return 1;
2469cfa2 1696
13761a11
NC		 1697 if (strncasecmp (t, "sr", 2) == 0)
1698 return 2;
1699
1700 if (*t == '0')
1701 return 0;
2469cfa2 1702
13761a11
NC		 1703 val = atoi (t);
1704
1705 if (val < 1 || val > 15)
1706 return -1;
1707
1708 return val;
1709}
2469cfa2 1710
b18c562e
NC		 1711static int
1712msp430_srcoperand (struct msp430_operand_s * op,
13761a11
NC		 1713 char * l,
1714 int bin,
00b32ff2 1715 bfd_boolean * imm_op,
13761a11
NC		 1716 bfd_boolean allow_20bit_values,
1717 bfd_boolean constants_allowed)
2469cfa2 1718{
2bfa0cdf 1719 char * end;
b18c562e 1720 char *__tl = l;
2469cfa2 1721
b18c562e
NC		 1722 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1723 if (*l == '#')
2469cfa2 1724 {
b18c562e
NC		 1725 char *h = l;
1726 int vshift = -1;
1727 int rval = 0;
2469cfa2 1728
b18c562e
NC		 1729 /* Check if there is:
1730 llo(x) - least significant 16 bits, x &= 0xffff
1731 lhi(x) - x = (x >> 16) & 0xffff,
1732 hlo(x) - x = (x >> 32) & 0xffff,
1733 hhi(x) - x = (x >> 48) & 0xffff
1734 The value _MUST_ be constant expression: #hlo(1231231231). */
2469cfa2 1735
00b32ff2 1736 *imm_op = TRUE;
2469cfa2 1737
b18c562e
NC		 1738 if (strncasecmp (h, "#llo(", 5) == 0)
1739 {
1740 vshift = 0;
1741 rval = 3;
1742 }
1743 else if (strncasecmp (h, "#lhi(", 5) == 0)
1744 {
1745 vshift = 1;
1746 rval = 3;
1747 }
1748 else if (strncasecmp (h, "#hlo(", 5) == 0)
1749 {
1750 vshift = 2;
1751 rval = 3;
1752 }
1753 else if (strncasecmp (h, "#hhi(", 5) == 0)
1754 {
1755 vshift = 3;
1756 rval = 3;
1757 }
1758 else if (strncasecmp (h, "#lo(", 4) == 0)
1759 {
1760 vshift = 0;
1761 rval = 2;
1762 }
1763 else if (strncasecmp (h, "#hi(", 4) == 0)
1764 {
1765 vshift = 1;
1766 rval = 2;
1767 }
2469cfa2 1768
b18c562e
NC		 1769 op->reg = 0; /* Reg PC. */
1770 op->am = 3;
65d7bab5 1771 op->ol = 1; /* Immediate will follow an instruction. */
b18c562e
NC		 1772 __tl = h + 1 + rval;
1773 op->mode = OP_EXP;
00b32ff2 1774 op->vshift = vshift;
2469cfa2 1775
2bfa0cdf
NC		 1776 end = parse_exp (__tl, &(op->exp));
1777 if (end != NULL && *end != 0 && *end != ')' )
1778 {
1779 as_bad (_("extra characters '%s' at end of immediate expression '%s'"), end, l);
1780 return 1;
1781 }
b18c562e 1782 if (op->exp.X_op == O_constant)
2469cfa2 1783 {
b18c562e 1784 int x = op->exp.X_add_number;
2469cfa2 1785
b18c562e 1786 if (vshift == 0)
2469cfa2 1787 {
b18c562e
NC		 1788 x = x & 0xffff;
1789 op->exp.X_add_number = x;
1790 }
1791 else if (vshift == 1)
1792 {
1793 x = (x >> 16) & 0xffff;
1794 op->exp.X_add_number = x;
00b32ff2 1795 op->vshift = 0;
b18c562e
NC		 1796 }
1797 else if (vshift > 1)
1798 {
1799 if (x < 0)
1800 op->exp.X_add_number = -1;
2469cfa2 1801 else
b18c562e
NC		 1802 op->exp.X_add_number = 0; /* Nothing left. */
1803 x = op->exp.X_add_number;
00b32ff2 1804 op->vshift = 0;
2469cfa2 1805 }
2469cfa2 1806
13761a11
NC		 1807 if (allow_20bit_values)
1808 {
99b4a5a0 1809 if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < -524288)
13761a11
NC		 1810 {
1811 as_bad (_("value 0x%x out of extended range."), x);
1812 return 1;
1813 }
1814 }
1815 else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)
b18c562e
NC		 1816 {
1817 as_bad (_("value %d out of range. Use #lo() or #hi()"), x);
1818 return 1;
1819 }
2469cfa2 1820
b18c562e
NC		 1821 /* Now check constants. */
1822 /* Substitute register mode with a constant generator if applicable. */
2469cfa2 1823
13761a11
NC		 1824 if (!allow_20bit_values)
1825 x = (short) x; /* Extend sign. */
2469cfa2 1826
13761a11
NC		 1827 if (! constants_allowed)
1828 ;
1829 else if (x == 0)
2469cfa2 1830 {
b18c562e
NC		 1831 op->reg = 3;
1832 op->am = 0;
1833 op->ol = 0;
1834 op->mode = OP_REG;
1835 }
1836 else if (x == 1)
1837 {
1838 op->reg = 3;
1839 op->am = 1;
1840 op->ol = 0;
1841 op->mode = OP_REG;
1842 }
1843 else if (x == 2)
1844 {
1845 op->reg = 3;
1846 op->am = 2;
1847 op->ol = 0;
1848 op->mode = OP_REG;
1849 }
1850 else if (x == -1)
1851 {
1852 op->reg = 3;
1853 op->am = 3;
1854 op->ol = 0;
1855 op->mode = OP_REG;
1856 }
1857 else if (x == 4)
1858 {
2213f746 1859 if (bin == 0x1200 && ! target_is_430x ())
b18c562e 1860 {
2213f746
NC		 1861 /* CPU4: The shorter form of PUSH #4 is not supported on MSP430. */
1862 if (silicon_errata_warn & SILICON_ERRATA_CPU4)
1863 as_warn (_("cpu4: not converting PUSH #4 to shorter form"));
1864 /* No need to check silicon_errata_fixes - this fix is always implemented. */
b18c562e
NC		 1865 }
1866 else
b18c562e
NC		 1867 {
1868 op->reg = 2;
1869 op->am = 2;
1870 op->ol = 0;
1871 op->mode = OP_REG;
1872 }
1873 }
1874 else if (x == 8)
1875 {
2213f746 1876 if (bin == 0x1200 && ! target_is_430x ())
b18c562e 1877 {
2213f746
NC		 1878 /* CPU4: The shorter form of PUSH #8 is not supported on MSP430. */
1879 if (silicon_errata_warn & SILICON_ERRATA_CPU4)
1880 as_warn (_("cpu4: not converting PUSH #8 to shorter form"));
b18c562e
NC		 1881 }
1882 else
b18c562e
NC		 1883 {
1884 op->reg = 2;
1885 op->am = 3;
1886 op->ol = 0;
1887 op->mode = OP_REG;
1888 }
2469cfa2 1889 }
2469cfa2 1890 }
b18c562e
NC		 1891 else if (op->exp.X_op == O_symbol)
1892 {
00b32ff2
NC		 1893 if (vshift > 1)
1894 as_bad (_("error: unsupported #foo() directive used on symbol"));
b18c562e
NC		 1895 op->mode = OP_EXP;
1896 }
1897 else if (op->exp.X_op == O_big)
1898 {
1899 short x;
65d7bab5 1900
b18c562e
NC		 1901 if (vshift != -1)
1902 {
1903 op->exp.X_op = O_constant;
1904 op->exp.X_add_number = 0xffff & generic_bignum[vshift];
1905 x = op->exp.X_add_number;
00b32ff2 1906 op->vshift = 0;
b18c562e
NC		 1907 }
1908 else
1909 {
1910 as_bad (_
33eaf5de 1911 ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
b18c562e
NC		 1912 l);
1913 return 1;
1914 }
2469cfa2 1915
b18c562e
NC		 1916 if (x == 0)
1917 {
1918 op->reg = 3;
1919 op->am = 0;
1920 op->ol = 0;
1921 op->mode = OP_REG;
1922 }
1923 else if (x == 1)
1924 {
1925 op->reg = 3;
1926 op->am = 1;
1927 op->ol = 0;
1928 op->mode = OP_REG;
1929 }
1930 else if (x == 2)
1931 {
1932 op->reg = 3;
1933 op->am = 2;
1934 op->ol = 0;
1935 op->mode = OP_REG;
1936 }
1937 else if (x == -1)
1938 {
1939 op->reg = 3;
1940 op->am = 3;
1941 op->ol = 0;
1942 op->mode = OP_REG;
1943 }
1944 else if (x == 4)
1945 {
1946 op->reg = 2;
1947 op->am = 2;
1948 op->ol = 0;
1949 op->mode = OP_REG;
1950 }
1951 else if (x == 8)
1952 {
1953 op->reg = 2;
1954 op->am = 3;
1955 op->ol = 0;
1956 op->mode = OP_REG;
1957 }
1958 }
79cf5950 1959 /* Redundant (yet) check. */
b18c562e
NC		 1960 else if (op->exp.X_op == O_register)
1961 as_bad
1962 (_("Registers cannot be used within immediate expression [%s]"), l);
1963 else
1964 as_bad (_("unknown operand %s"), l);
2469cfa2 1965
b18c562e
NC		 1966 return 0;
1967 }
2469cfa2 1968
b18c562e
NC		 1969 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1970 if (*l == '&')
1971 {
1972 char *h = l;
2469cfa2 1973
b18c562e
NC		 1974 op->reg = 2; /* reg 2 in absolute addr mode. */
1975 op->am = 1; /* mode As == 01 bin. */
1976 op->ol = 1; /* Immediate value followed by instruction. */
1977 __tl = h + 1;
2bfa0cdf
NC		 1978 end = parse_exp (__tl, &(op->exp));
1979 if (end != NULL && *end != 0)
1980 {
1981 as_bad (_("extra characters '%s' at the end of absolute operand '%s'"), end, l);
1982 return 1;
1983 }
b18c562e 1984 op->mode = OP_EXP;
00b32ff2 1985 op->vshift = 0;
b18c562e 1986 if (op->exp.X_op == O_constant)
2469cfa2 1987 {
b18c562e 1988 int x = op->exp.X_add_number;
2469cfa2 1989
13761a11
NC		 1990 if (allow_20bit_values)
1991 {
1992 if (x > 0xfffff || x < -(0x7ffff))
1993 {
1994 as_bad (_("value 0x%x out of extended range."), x);
1995 return 1;
1996 }
1997 }
1998 else if (x > 65535 || x < -32768)
b18c562e 1999 {
13761a11 2000 as_bad (_("value out of range: 0x%x"), x);
b18c562e
NC		 2001 return 1;
2002 }
2469cfa2 2003 }
b18c562e
NC		 2004 else if (op->exp.X_op == O_symbol)
2005 ;
2006 else
2469cfa2 2007 {
79cf5950 2008 /* Redundant (yet) check. */
b18c562e
NC		 2009 if (op->exp.X_op == O_register)
2010 as_bad
2011 (_("Registers cannot be used within absolute expression [%s]"), l);
2469cfa2 2012 else
b18c562e
NC		 2013 as_bad (_("unknown expression in operand %s"), l);
2014 return 1;
2469cfa2 2015 }
b18c562e
NC		 2016 return 0;
2017 }
2469cfa2 2018
b18c562e
NC		 2019 /* Check if indirect register mode @Rn / postincrement @Rn+. */
2020 if (*l == '@')
2021 {
2022 char *t = l;
2023 char *m = strchr (l, '+');
2024
2025 if (t != l)
2469cfa2 2026 {
b18c562e
NC		 2027 as_bad (_("unknown addressing mode %s"), l);
2028 return 1;
2469cfa2
NC		 2029 }
2030
b18c562e 2031 t++;
2469cfa2 2032
13761a11 2033 if ((op->reg = check_reg (t)) == -1)
2469cfa2 2034 {
13761a11 2035 as_bad (_("Bad register name %s"), t);
b18c562e 2036 return 1;
2469cfa2 2037 }
2469cfa2 2038
b18c562e
NC		 2039 op->mode = OP_REG;
2040 op->am = m ? 3 : 2;
2041 op->ol = 0;
2469cfa2 2042
d1706f38
NC		 2043 /* PC cannot be used in indirect addressing. */
2044 if (target_is_430xv2 () && op->reg == 0)
2045 {
2046 as_bad (_("cannot use indirect addressing with the PC"));
2047 return 1;
2048 }
65d7bab5 2049
b18c562e
NC		 2050 return 0;
2051 }
2469cfa2 2052
b18c562e
NC		 2053 /* Check if register indexed X(Rn). */
2054 do
2055 {
2056 char *h = strrchr (l, '(');
2057 char *m = strrchr (l, ')');
2058 char *t;
2469cfa2 2059
00b32ff2 2060 *imm_op = TRUE;
2469cfa2 2061
b18c562e
NC		 2062 if (!h)
2063 break;
2064 if (!m)
2065 {
2066 as_bad (_("')' required"));
2067 return 1;
2068 }
2469cfa2 2069
b18c562e
NC		 2070 t = h;
2071 op->am = 1;
2072 op->ol = 1;
2469cfa2 2073
13761a11
NC		 2074 /* Extract a register. */
2075 if ((op->reg = check_reg (t + 1)) == -1)
b18c562e
NC		 2076 {
2077 as_bad (_
2078 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
2079 l);
2080 return 1;
2081 }
2469cfa2 2082
13761a11 2083 if (op->reg == 2)
b18c562e 2084 {
13761a11 2085 as_bad (_("r2 should not be used in indexed addressing mode"));
b18c562e
NC		 2086 return 1;
2087 }
b18c562e
NC		 2088
2089 /* Extract constant. */
2090 __tl = l;
2091 *h = 0;
2092 op->mode = OP_EXP;
00b32ff2 2093 op->vshift = 0;
2bfa0cdf
NC		 2094 end = parse_exp (__tl, &(op->exp));
2095 if (end != NULL && *end != 0)
2096 {
2097 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
2098 return 1;
2099 }
b18c562e
NC		 2100 if (op->exp.X_op == O_constant)
2101 {
2102 int x = op->exp.X_add_number;
2103
13761a11
NC		 2104 if (allow_20bit_values)
2105 {
2106 if (x > 0xfffff || x < - (0x7ffff))
2107 {
2108 as_bad (_("value 0x%x out of extended range."), x);
2109 return 1;
2110 }
2111 }
2112 else if (x > 65535 || x < -32768)
2469cfa2 2113 {
13761a11 2114 as_bad (_("value out of range: 0x%x"), x);
b18c562e 2115 return 1;
2469cfa2 2116 }
b18c562e
NC		 2117
2118 if (x == 0)
2469cfa2 2119 {
b18c562e
NC		 2120 op->mode = OP_REG;
2121 op->am = 2;
2122 op->ol = 0;
2123 return 0;
2469cfa2 2124 }
2213f746
NC		 2125
2126 if (op->reg == 1 && (x & 1))
2127 {
2128 if (silicon_errata_fix & SILICON_ERRATA_CPU8)
2129 as_bad (_("CPU8: Stack pointer accessed with an odd offset"));
2130 else if (silicon_errata_warn & SILICON_ERRATA_CPU8)
2131 as_warn (_("CPU8: Stack pointer accessed with an odd offset"));
2132 }
2469cfa2 2133 }
b18c562e
NC		 2134 else if (op->exp.X_op == O_symbol)
2135 ;
2469cfa2
NC		 2136 else
2137 {
79cf5950 2138 /* Redundant (yet) check. */
b18c562e
NC		 2139 if (op->exp.X_op == O_register)
2140 as_bad
2141 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l);
2142 else
2143 as_bad (_("unknown expression in operand %s"), l);
2144 return 1;
2469cfa2 2145 }
2469cfa2 2146
b18c562e 2147 return 0;
2469cfa2 2148 }
b18c562e 2149 while (0);
2469cfa2 2150
13761a11
NC		 2151 /* Possibly register mode 'mov r1,r2'. */
2152 if ((op->reg = check_reg (l)) != -1)
b18c562e 2153 {
13761a11
NC		 2154 op->mode = OP_REG;
2155 op->am = 0;
2156 op->ol = 0;
2157 return 0;
b18c562e 2158 }
b18c562e
NC		 2159
2160 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
2bfa0cdf
NC		 2161 op->mode = OP_EXP;
2162 op->reg = 0; /* PC relative... be careful. */
2163 /* An expression starting with a minus sign is a constant, not an address. */
2164 op->am = (*l == '-' ? 3 : 1);
2165 op->ol = 1;
2166 op->vshift = 0;
2167 __tl = l;
2168 end = parse_exp (__tl, &(op->exp));
2169 if (end != NULL && * end != 0)
b18c562e 2170 {
2bfa0cdf
NC		 2171 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
2172 return 1;
b18c562e 2173 }
2bfa0cdf 2174 return 0;
2469cfa2
NC		 2175}
2176
b18c562e 2177
2469cfa2 2178static int
13761a11
NC		 2179msp430_dstoperand (struct msp430_operand_s * op,
2180 char * l,
2181 int bin,
2182 bfd_boolean allow_20bit_values,
2183 bfd_boolean constants_allowed)
2469cfa2
NC		 2184{
2185 int dummy;
13761a11
NC		 2186 int ret = msp430_srcoperand (op, l, bin, & dummy,
2187 allow_20bit_values,
2188 constants_allowed);
b18c562e 2189
2469cfa2
NC		 2190 if (ret)
2191 return ret;
2192
2193 if (op->am == 2)
2194 {
47990a6a 2195 char *__tl = (char *) "0";
2469cfa2
NC		 2196
2197 op->mode = OP_EXP;
2198 op->am = 1;
2199 op->ol = 1;
00b32ff2 2200 op->vshift = 0;
2bfa0cdf 2201 (void) parse_exp (__tl, &(op->exp));
b18c562e 2202
2469cfa2
NC		 2203 if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
2204 {
2205 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
2206 op->reg, op->reg);
2207 return 1;
2208 }
2209 return 0;
2210 }
2211
2212 if (op->am > 1)
2213 {
2214 as_bad (_
2215 ("this addressing mode is not applicable for destination operand"));
2216 return 1;
2217 }
2218 return 0;
2219}
2220
13761a11
NC		 2221/* Attempt to encode a MOVA instruction with the given operands.
2222 Returns the length of the encoded instruction if successful
2223 or 0 upon failure. If the encoding fails, an error message
2224 will be returned if a pointer is provided. */
2225
2226static int
2227try_encode_mova (bfd_boolean imm_op,
2228 int bin,
2229 struct msp430_operand_s * op1,
2230 struct msp430_operand_s * op2,
2231 const char ** error_message_return)
2232{
2233 short ZEROS = 0;
2234 char *frag;
2235 int where;
2236
2237 /* Only a restricted subset of the normal MSP430 addressing modes
2238 are supported here, so check for the ones that are allowed. */
2239 if (imm_op)
2240 {
2241 if (op1->mode == OP_EXP)
2242 {
2243 if (op2->mode != OP_REG)
2244 {
2245 if (error_message_return != NULL)
2246 * error_message_return = _("expected register as second argument of %s");
2247 return 0;
2248 }
2249
2250 if (op1->am == 3)
2251 {
2252 /* MOVA #imm20, Rdst. */
2253 bin |= 0x80 | op2->reg;
2254 frag = frag_more (4);
2255 where = frag - frag_now->fr_literal;
2256 if (op1->exp.X_op == O_constant)
2257 {
2258 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
2259 bfd_putl16 ((bfd_vma) bin, frag);
2260 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2261 }
2262 else
2263 {
2264 bfd_putl16 ((bfd_vma) bin, frag);
2265 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
2266 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2267 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2268 }
2269
2270 return 4;
2271 }
2272 else if (op1->am == 1)
2273 {
2274 /* MOVA z16(Rsrc), Rdst. */
2275 bin |= 0x30 | (op1->reg << 8) | op2->reg;
2276 frag = frag_more (4);
2277 where = frag - frag_now->fr_literal;
2278 bfd_putl16 ((bfd_vma) bin, frag);
2279 if (op1->exp.X_op == O_constant)
2280 {
2281 if (op1->exp.X_add_number > 0xffff
2282 || op1->exp.X_add_number < -(0x7fff))
2283 {
2284 if (error_message_return != NULL)
2285 * error_message_return = _("index value too big for %s");
2286 return 0;
2287 }
2288 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2289 }
2290 else
2291 {
2292 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2293 fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
2294 op1->reg == 0 ?
2295 BFD_RELOC_MSP430X_PCR16 :
2296 BFD_RELOC_MSP430X_ABS16);
2297 }
2298 return 4;
2299 }
2300
2301 if (error_message_return != NULL)
2302 * error_message_return = _("unexpected addressing mode for %s");
2303 return 0;
2304 }
2305 else if (op1->am == 0)
2306 {
2307 /* MOVA Rsrc, ... */
2308 if (op2->mode == OP_REG)
2309 {
2310 bin |= 0xc0 | (op1->reg << 8) | op2->reg;
2311 frag = frag_more (2);
2312 where = frag - frag_now->fr_literal;
2313 bfd_putl16 ((bfd_vma) bin, frag);
2314 return 2;
2315 }
2316 else if (op2->am == 1)
2317 {
2318 if (op2->reg == 2)
2319 {
2320 /* MOVA Rsrc, &abs20. */
2321 bin |= 0x60 | (op1->reg << 8);
2322 frag = frag_more (4);
2323 where = frag - frag_now->fr_literal;
2324 if (op2->exp.X_op == O_constant)
2325 {
2326 bin |= (op2->exp.X_add_number >> 16) & 0xf;
2327 bfd_putl16 ((bfd_vma) bin, frag);
2328 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
2329 }
2330 else
2331 {
2332 bfd_putl16 ((bfd_vma) bin, frag);
2333 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2334 fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
2335 BFD_RELOC_MSP430X_ABS20_ADR_DST);
2336 }
2337 return 4;
2338 }
2339
2340 /* MOVA Rsrc, z16(Rdst). */
2341 bin |= 0x70 | (op1->reg << 8) | op2->reg;
2342 frag = frag_more (4);
2343 where = frag - frag_now->fr_literal;
2344 bfd_putl16 ((bfd_vma) bin, frag);
2345 if (op2->exp.X_op == O_constant)
2346 {
2347 if (op2->exp.X_add_number > 0xffff
2348 || op2->exp.X_add_number < -(0x7fff))
2349 {
2350 if (error_message_return != NULL)
2351 * error_message_return = _("index value too big for %s");
2352 return 0;
2353 }
2354 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
2355 }
2356 else
2357 {
2358 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2359 fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
2360 op2->reg == 0 ?
2361 BFD_RELOC_MSP430X_PCR16 :
2362 BFD_RELOC_MSP430X_ABS16);
2363 }
2364 return 4;
2365 }
2366
2367 if (error_message_return != NULL)
2368 * error_message_return = _("unexpected addressing mode for %s");
2369 return 0;
2370 }
2371 }
2372
2373 /* imm_op == FALSE. */
2374
2375 if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
2376 {
2377 /* MOVA &abs20, Rdst. */
2378 if (op2->mode != OP_REG)
2379 {
2380 if (error_message_return != NULL)
2381 * error_message_return = _("expected register as second argument of %s");
2382 return 0;
2383 }
2384
2385 if (op2->reg == 2 || op2->reg == 3)
2386 {
2387 if (error_message_return != NULL)
2388 * error_message_return = _("constant generator destination register found in %s");
2389 return 0;
2390 }
2391
2392 bin |= 0x20 | op2->reg;
2393 frag = frag_more (4);
2394 where = frag - frag_now->fr_literal;
2395 if (op1->exp.X_op == O_constant)
2396 {
2397 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
2398 bfd_putl16 ((bfd_vma) bin, frag);
2399 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2400 }
2401 else
2402 {
2403 bfd_putl16 ((bfd_vma) bin, frag);
2404 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2405 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
2406 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2407 }
2408 return 4;
2409 }
2410 else if (op1->mode == OP_REG)
2411 {
2412 if (op1->am == 3)
2413 {
2414 /* MOVA @Rsrc+, Rdst. */
2415 if (op2->mode != OP_REG)
2416 {
2417 if (error_message_return != NULL)
2418 * error_message_return = _("expected register as second argument of %s");
2419 return 0;
2420 }
2421
2422 if (op2->reg == 2 || op2->reg == 3)
2423 {
2424 if (error_message_return != NULL)
2425 * error_message_return = _("constant generator destination register found in %s");
2426 return 0;
2427 }
2428
2429 if (op1->reg == 2 || op1->reg == 3)
2430 {
2431 if (error_message_return != NULL)
2432 * error_message_return = _("constant generator source register found in %s");
2433 return 0;
2434 }
2435
2436 bin |= 0x10 | (op1->reg << 8) | op2->reg;
2437 frag = frag_more (2);
2438 where = frag - frag_now->fr_literal;
2439 bfd_putl16 ((bfd_vma) bin, frag);
2440 return 2;
2441 }
2442 else if (op1->am == 2)
2443 {
2444 /* MOVA @Rsrc,Rdst */
2445 if (op2->mode != OP_REG)
2446 {
2447 if (error_message_return != NULL)
2448 * error_message_return = _("expected register as second argument of %s");
2449 return 0;
2450 }
2451
2452 if (op2->reg == 2 || op2->reg == 3)
2453 {
2454 if (error_message_return != NULL)
2455 * error_message_return = _("constant generator destination register found in %s");
2456 return 0;
2457 }
2458
2459 if (op1->reg == 2 || op1->reg == 3)
2460 {
2461 if (error_message_return != NULL)
2462 * error_message_return = _("constant generator source register found in %s");
2463 return 0;
2464 }
2465
2466 bin |= (op1->reg << 8) | op2->reg;
2467 frag = frag_more (2);
2468 where = frag - frag_now->fr_literal;
2469 bfd_putl16 ((bfd_vma) bin, frag);
2470 return 2;
2471 }
2472 }
2473
2474 if (error_message_return != NULL)
2475 * error_message_return = _("unexpected addressing mode for %s");
2476
2477 return 0;
2478}
2479
2213f746
NC		 2480#define NOP_CHECK_INTERRUPT (1 << 0)
2481#define NOP_CHECK_CPU12 (1 << 1)
2482#define NOP_CHECK_CPU19 (1 << 2)
2483
2484static signed int check_for_nop = 0;
65d7bab5 2485
638d3803
NC		 2486#define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
2487
b18c562e
NC		 2488/* Parse instruction operands.
2489 Return binary opcode. */
2490
2491static unsigned int
2492msp430_operands (struct msp430_opcode_s * opcode, char * line)
2469cfa2 2493{
b18c562e 2494 int bin = opcode->bin_opcode; /* Opcode mask. */
13761a11 2495 int insn_length = 0;
b18c562e
NC		 2496 char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
2497 char *frag;
2bfa0cdf 2498 char *end;
b18c562e
NC		 2499 int where;
2500 struct msp430_operand_s op1, op2;
2501 int res = 0;
2502 static short ZEROS = 0;
00b32ff2 2503 bfd_boolean byte_op, imm_op;
13761a11
NC		 2504 int op_length = 0;
2505 int fmt;
2506 int extended = 0x1800;
2507 bfd_boolean extended_op = FALSE;
2508 bfd_boolean addr_op;
2509 const char * error_message;
2510 static signed int repeat_count = 0;
927f2d25 2511 static bfd_boolean prev_insn_is_nop = FALSE;
13761a11 2512 bfd_boolean fix_emitted;
2469cfa2 2513
b18c562e
NC		 2514 /* Opcode is the one from opcodes table
2515 line contains something like
2516 [.w] @r2+, 5(R1)
2517 or
2518 .b @r2+, 5(R1). */
2469cfa2 2519
00b32ff2 2520 byte_op = FALSE;
38d77545
NC		 2521 addr_op = FALSE;
2522 if (*line == '.')
2469cfa2 2523 {
38d77545
NC		 2524 bfd_boolean check = FALSE;
2525 ++ line;
2526
2527 switch (TOLOWER (* line))
2528 {
2529 case 'b':
2530 /* Byte operation. */
2531 bin |= BYTE_OPERATION;
00b32ff2 2532 byte_op = TRUE;
38d77545
NC		 2533 check = TRUE;
2534 break;
2535
2536 case 'a':
2537 /* "Address" ops work on 20-bit values. */
2538 addr_op = TRUE;
2539 bin |= BYTE_OPERATION;
2540 check = TRUE;
2541 break;
2542
2543 case 'w':
2544 /* Word operation - this is the default. */
2545 check = TRUE;
2546 break;
2547
2548 case 0:
2549 case ' ':
2550 case '\n':
2551 case '\r':
2552 as_warn (_("no size modifier after period, .w assumed"));
2553 break;
2554
2555 default:
2556 as_bad (_("unrecognised instruction size modifier .%c"),
2557 * line);
2558 return 0;
2559 }
2560
2561 if (check)
2562 {
2563 ++ line;
2564
2565 }
2469cfa2
NC		 2566 }
2567
38d77545 2568 if (*line && ! ISSPACE (*line))
13761a11 2569 {
38d77545
NC		 2570 as_bad (_("junk found after instruction: %s.%s"),
2571 opcode->name, line);
2572 return 0;
13761a11 2573 }
13761a11 2574
38d77545
NC		 2575 /* Catch the case where the programmer has used a ".a" size modifier on an
2576 instruction that does not support it. Look for an alternative extended
2577 instruction that has the same name without the period. Eg: "add.a"
2578 becomes "adda". Although this not an officially supported way of
33eaf5de 2579 specifying instruction aliases other MSP430 assemblers allow it. So we
38d77545
NC		 2580 support it for compatibility purposes. */
2581 if (addr_op && opcode->fmt >= 0)
2582 {
f86f5863 2583 const char * old_name = opcode->name;
38d77545
NC		 2584 char real_name[32];
2585
2586 sprintf (real_name, "%sa", old_name);
2587 opcode = hash_find (msp430_hash, real_name);
2588 if (opcode == NULL)
2589 {
2590 as_bad (_("instruction %s.a does not exist"), old_name);
2591 return 0;
2592 }
2593#if 0 /* Enable for debugging. */
2594 as_warn ("treating %s.a as %s", old_name, real_name);
2595#endif
2596 addr_op = FALSE;
2597 bin = opcode->bin_opcode;
2598 }
2469cfa2 2599
13761a11
NC		 2600 if (opcode->fmt != -1
2601 && opcode->insn_opnumb
2602 && (!*line || *line == '\n'))
2469cfa2 2603 {
b18c562e
NC		 2604 as_bad (_("instruction %s requires %d operand(s)"),
2605 opcode->name, opcode->insn_opnumb);
2606 return 0;
2607 }
2469cfa2 2608
b18c562e
NC		 2609 memset (l1, 0, sizeof (l1));
2610 memset (l2, 0, sizeof (l2));
2611 memset (&op1, 0, sizeof (op1));
2612 memset (&op2, 0, sizeof (op2));
2469cfa2 2613
00b32ff2 2614 imm_op = FALSE;
2469cfa2 2615
13761a11
NC		 2616 if ((fmt = opcode->fmt) < 0)
2617 {
638d3803 2618 if (! target_is_430x ())
13761a11
NC		 2619 {
2620 as_bad (_("instruction %s requires MSP430X mcu"),
2621 opcode->name);
2622 return 0;
2623 }
3739860c 2624
13761a11
NC		 2625 fmt = (-fmt) - 1;
2626 extended_op = TRUE;
2627 }
2628
2629 if (repeat_count)
2630 {
2631 /* If requested set the extended instruction repeat count. */
2632 if (extended_op)
2633 {
2634 if (repeat_count > 0)
2635 extended |= (repeat_count - 1);
2636 else
2637 extended |= (1 << 7) | (- repeat_count);
2638 }
2639 else
2640 as_bad (_("unable to repeat %s insn"), opcode->name);
2641
2642 repeat_count = 0;
2643 }
2644
2213f746 2645 if (check_for_nop)
b18c562e 2646 {
2213f746 2647 if (! is_opcode ("nop"))
2469cfa2 2648 {
2213f746
NC		 2649 bfd_boolean doit = FALSE;
2650
2651 do
65d7bab5 2652 {
2213f746 2653 switch (check_for_nop & - check_for_nop)
65d7bab5 2654 {
2213f746 2655 case NOP_CHECK_INTERRUPT:
ff1fe6fa 2656 if (warn_interrupt_nops)
65d7bab5
NC		 2657 {
2658 if (gen_interrupt_nops)
2659 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2660 else
2661 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2662 }
2663
ff1fe6fa 2664 if (gen_interrupt_nops)
2213f746
NC		 2665 /* Emit a NOP between interrupt enable/disable.
2666 See 1.3.4.1 of the MSP430x5xx User Guide. */
2667 doit = TRUE;
2668 break;
2669
2670 case NOP_CHECK_CPU12:
2671 if (silicon_errata_warn & SILICON_ERRATA_CPU12)
de194d85 2672 as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
2213f746
NC		 2673
2674 if (silicon_errata_fix & SILICON_ERRATA_CPU12)
2675 doit = TRUE;
2676 break;
2677
2678 case NOP_CHECK_CPU19:
2679 if (silicon_errata_warn & SILICON_ERRATA_CPU19)
2680 as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
65d7bab5 2681
2213f746
NC		 2682 if (silicon_errata_fix & SILICON_ERRATA_CPU19)
2683 doit = TRUE;
2684 break;
2685
2686 default:
2687 as_bad (_("internal error: unknown nop check state"));
2688 break;
2689 }
2690 check_for_nop &= ~ (check_for_nop & - check_for_nop);
2691 }
2692 while (check_for_nop);
2693
2694 if (doit)
2695 {
2696 frag = frag_more (2);
2697 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
2698 dwarf2_emit_insn (2);
65d7bab5 2699 }
2213f746
NC		 2700 }
2701
2702 check_for_nop = 0;
2703 }
2704
2705 switch (fmt)
2706 {
2707 case 0: /* Emulated. */
2708 switch (opcode->insn_opnumb)
2709 {
2710 case 0:
927f2d25
NC		 2711 if (is_opcode ("eint"))
2712 {
2713 if (! prev_insn_is_nop)
2714 {
2715 if (gen_interrupt_nops)
2716 {
2717 frag = frag_more (2);
2718 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
2719 dwarf2_emit_insn (2);
2720
2721 if (warn_interrupt_nops)
2722 as_warn (_("inserting a NOP before EINT"));
2723 }
2724 else if (warn_interrupt_nops)
2725 as_warn (_("a NOP might be needed before the EINT"));
2726 }
2727 }
2728 else if (is_opcode ("dint"))
2213f746 2729 check_for_nop |= NOP_CHECK_INTERRUPT;
65d7bab5 2730
b18c562e 2731 /* Set/clear bits instructions. */
13761a11
NC		 2732 if (extended_op)
2733 {
2734 if (!addr_op)
2735 extended |= BYTE_OPERATION;
2736
2737 /* Emit the extension word. */
2738 insn_length += 2;
65d7bab5 2739 frag = frag_more (2);
13761a11
NC		 2740 bfd_putl16 (extended, frag);
2741 }
638d3803 2742
13761a11 2743 insn_length += 2;
65d7bab5 2744 frag = frag_more (2);
b18c562e 2745 bfd_putl16 ((bfd_vma) bin, frag);
13761a11 2746 dwarf2_emit_insn (insn_length);
b18c562e 2747 break;
13761a11 2748
b18c562e
NC		 2749 case 1:
2750 /* Something which works with destination operand. */
2751 line = extract_operand (line, l1, sizeof (l1));
13761a11 2752 res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
b18c562e
NC		 2753 if (res)
2754 break;
2469cfa2 2755
65d7bab5
NC		 2756 bin |= (op1.reg | (op1.am << 7));
2757
2213f746
NC		 2758 /* If the PC is the destination... */
2759 if (op1.am == 0 && op1.reg == 0
2760 /* ... and the opcode alters the SR. */
2761 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
2762 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
65d7bab5 2763 {
2213f746 2764 if (silicon_errata_fix & SILICON_ERRATA_CPU11)
de194d85 2765 as_bad (_("CPU11: PC is destination of SR altering instruction"));
2213f746 2766 else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
de194d85 2767 as_warn (_("CPU11: PC is destination of SR altering instruction"));
65d7bab5 2768 }
2213f746
NC		 2769
2770 /* If the status register is the destination... */
2771 if (op1.am == 0 && op1.reg == 2
2772 /* ... and the opcode alters the SR. */
2773 && (is_opcode ("adc") || is_opcode ("dec") || is_opcode ("decd")
2774 || is_opcode ("inc") || is_opcode ("incd") || is_opcode ("inv")
2775 || is_opcode ("sbc") || is_opcode ("sxt")
2776 || is_opcode ("adcx") || is_opcode ("decx") || is_opcode ("decdx")
2777 || is_opcode ("incx") || is_opcode ("incdx") || is_opcode ("invx")
2778 || is_opcode ("sbcx")
2779 ))
2780 {
2781 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
de194d85 2782 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2213f746 2783 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
de194d85 2784 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2213f746
NC		 2785 }
2786
2787 if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
2788 check_for_nop |= NOP_CHECK_INTERRUPT;
65d7bab5 2789
13761a11 2790 /* Compute the entire instruction length, in bytes. */
65d7bab5
NC		 2791 op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
2792 insn_length += op_length;
2793 frag = frag_more (op_length);
b18c562e 2794 where = frag - frag_now->fr_literal;
38d77545 2795
13761a11 2796 if (extended_op)
2469cfa2 2797 {
13761a11
NC		 2798 if (!addr_op)
2799 extended |= BYTE_OPERATION;
2800
2801 if (op1.ol != 0 && ((extended & 0xf) != 0))
2802 {
2803 as_bad (_("repeat instruction used with non-register mode instruction"));
2804 extended &= ~ 0xf;
2805 }
38d77545 2806
13761a11
NC		 2807 if (op1.mode == OP_EXP)
2808 {
2809 if (op1.exp.X_op == O_constant)
2810 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2811
e66c3c25 2812 else if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11
NC		 2813 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2814 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2815 else
2816 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2817 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2818 }
38d77545 2819
13761a11
NC		 2820 /* Emit the extension word. */
2821 bfd_putl16 (extended, frag);
2822 frag += 2;
2823 where += 2;
2824 }
2825
13761a11
NC		 2826 bfd_putl16 ((bfd_vma) bin, frag);
2827 frag += 2;
2828 where += 2;
2829
2830 if (op1.mode == OP_EXP)
2831 {
2832 if (op1.exp.X_op == O_constant)
2833 {
2834 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2835 }
2469cfa2 2836 else
13761a11
NC		 2837 {
2838 bfd_putl16 ((bfd_vma) ZEROS, frag);
2839
2840 if (!extended_op)
2841 {
2842 if (op1.reg)
2843 fix_new_exp (frag_now, where, 2,
00b32ff2 2844 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
13761a11
NC		 2845 else
2846 fix_new_exp (frag_now, where, 2,
2847 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2848 }
2849 }
2850 }
2851
13761a11 2852 dwarf2_emit_insn (insn_length);
b18c562e 2853 break;
2469cfa2 2854
b18c562e 2855 case 2:
13761a11
NC		 2856 /* Shift instruction. */
2857 line = extract_operand (line, l1, sizeof (l1));
2858 strncpy (l2, l1, sizeof (l2));
2859 l2[sizeof (l2) - 1] = '\0';
2860 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
2861 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
2862
2863 if (res)
2864 break; /* An error occurred. All warnings were done before. */
2865
2866 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2) + (op2.ol * 2);
2867 frag = frag_more (insn_length);
2868 where = frag - frag_now->fr_literal;
2869
d1706f38
NC		 2870 if (target_is_430xv2 ()
2871 && op1.mode == OP_REG
38d77545 2872 && op1.reg == 0
638d3803
NC		 2873 && (is_opcode ("rlax")
2874 || is_opcode ("rlcx")
2875 || is_opcode ("rla")
2876 || is_opcode ("rlc")))
2877 {
2878 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
65d7bab5 2879 break;
638d3803 2880 }
38d77545 2881
2213f746
NC		 2882 /* If the status register is the destination... */
2883 if (op1.am == 0 && op1.reg == 2
2884 /* ... and the opcode alters the SR. */
2885 && (is_opcode ("rla") || is_opcode ("rlc")
2886 || is_opcode ("rlax") || is_opcode ("rlcx")
2887 ))
2888 {
2889 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
de194d85 2890 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2213f746 2891 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
de194d85 2892 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2213f746
NC		 2893 }
2894
13761a11
NC		 2895 if (extended_op)
2896 {
2897 if (!addr_op)
2898 extended |= BYTE_OPERATION;
2899
2900 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
2901 {
2902 as_bad (_("repeat instruction used with non-register mode instruction"));
2903 extended &= ~ 0xf;
2904 }
38d77545 2905
13761a11
NC		 2906 if (op1.mode == OP_EXP)
2907 {
2908 if (op1.exp.X_op == O_constant)
2909 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2910
e66c3c25 2911 else if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11
NC		 2912 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2913 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2914 else
2915 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2916 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2917 }
2918
2919 if (op2.mode == OP_EXP)
2920 {
2921 if (op2.exp.X_op == O_constant)
2922 extended |= (op2.exp.X_add_number >> 16) & 0xf;
2923
2924 else if (op1.mode == OP_EXP)
2925 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
2926 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2927 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
2928 else
2929 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
2930 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
2931 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
2932 }
2933
2934 /* Emit the extension word. */
2935 bfd_putl16 (extended, frag);
2936 frag += 2;
2937 where += 2;
2938 }
2939
2940 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
2941 bfd_putl16 ((bfd_vma) bin, frag);
2942 frag += 2;
2943 where += 2;
2944
2945 if (op1.mode == OP_EXP)
2946 {
2947 if (op1.exp.X_op == O_constant)
2948 {
2949 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2950 }
2951 else
2952 {
2953 bfd_putl16 ((bfd_vma) ZEROS, frag);
2954
2955 if (!extended_op)
2956 {
e66c3c25 2957 if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11 2958 fix_new_exp (frag_now, where, 2,
00b32ff2 2959 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
13761a11
NC		 2960 else
2961 fix_new_exp (frag_now, where, 2,
2962 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2963 }
2964 }
2965 frag += 2;
2966 where += 2;
2967 }
2968
2969 if (op2.mode == OP_EXP)
2970 {
2971 if (op2.exp.X_op == O_constant)
2972 {
2973 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
2974 }
2975 else
2976 {
2977 bfd_putl16 ((bfd_vma) ZEROS, frag);
2978
2979 if (!extended_op)
2980 {
2981 if (op2.reg) /* Not PC relative. */
2982 fix_new_exp (frag_now, where, 2,
00b32ff2 2983 &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
13761a11
NC		 2984 else
2985 fix_new_exp (frag_now, where, 2,
2986 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2987 }
2988 }
2989 }
2990
2991 dwarf2_emit_insn (insn_length);
2992 break;
2993
2994 case 3:
2995 /* Branch instruction => mov dst, r0. */
2996 if (extended_op)
2997 {
2998 as_bad ("Internal error: state 0/3 not coded for extended instructions");
65d7bab5 2999 break;
13761a11
NC		 3000 }
3001
3002 line = extract_operand (line, l1, sizeof (l1));
3003 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE);
3004 if (res)
3005 break;
3006
00b32ff2
NC		 3007 byte_op = FALSE;
3008 imm_op = FALSE;
13761a11
NC		 3009 bin |= ((op1.reg << 8) | (op1.am << 4));
3010 op_length = 2 + 2 * op1.ol;
3011 frag = frag_more (op_length);
3012 where = frag - frag_now->fr_literal;
3013 bfd_putl16 ((bfd_vma) bin, frag);
3014
3015 if (op1.mode == OP_EXP)
3016 {
3017 if (op1.exp.X_op == O_constant)
3018 {
3019 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag + 2);
3020 }
3021 else
3022 {
3023 where += 2;
38d77545 3024
13761a11
NC		 3025 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
3026
e66c3c25 3027 if (op1.reg || op1.am == 3)
13761a11 3028 fix_new_exp (frag_now, where, 2,
00b32ff2 3029 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
13761a11
NC		 3030 else
3031 fix_new_exp (frag_now, where, 2,
3032 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3033 }
3034 }
3035
3036 dwarf2_emit_insn (insn_length + op_length);
3037 break;
3038
3039 case 4:
3040 /* CALLA instructions. */
3041 fix_emitted = FALSE;
3042
3043 line = extract_operand (line, l1, sizeof (l1));
00b32ff2 3044 imm_op = FALSE;
13761a11
NC		 3045
3046 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op,
3047 extended_op, FALSE);
3048 if (res)
3049 break;
3050
00b32ff2 3051 byte_op = FALSE;
13761a11
NC		 3052
3053 op_length = 2 + 2 * op1.ol;
3054 frag = frag_more (op_length);
3055 where = frag - frag_now->fr_literal;
3056
3057 if (imm_op)
3058 {
3059 if (op1.am == 3)
3060 {
3061 bin |= 0xb0;
3062
3063 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3064 BFD_RELOC_MSP430X_ABS20_ADR_DST);
3065 fix_emitted = TRUE;
3066 }
3067 else if (op1.am == 1)
3068 {
3069 if (op1.reg == 0)
3070 {
3071 bin |= 0x90;
3072
3073 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3074 BFD_RELOC_MSP430X_PCR20_CALL);
3075 fix_emitted = TRUE;
3076 }
3077 else
3078 bin |= 0x50 | op1.reg;
3079 }
3080 else if (op1.am == 0)
3081 bin |= 0x40 | op1.reg;
3082 }
3083 else if (op1.am == 1)
3084 {
3085 bin |= 0x80;
3086
3087 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3088 BFD_RELOC_MSP430X_ABS20_ADR_DST);
3089 fix_emitted = TRUE;
3090 }
3091 else if (op1.am == 2)
3092 bin |= 0x60 | op1.reg;
3093 else if (op1.am == 3)
3094 bin |= 0x70 | op1.reg;
38d77545 3095
13761a11
NC		 3096 bfd_putl16 ((bfd_vma) bin, frag);
3097
3098 if (op1.mode == OP_EXP)
3099 {
3100 if (op1.ol != 1)
3101 {
3102 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol);
65d7bab5 3103 break;
13761a11
NC		 3104 }
3105
3106 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
3107
3108 if (! fix_emitted)
3109 fix_new_exp (frag_now, where + 2, 2,
3110 &(op1.exp), FALSE, BFD_RELOC_16);
3111 }
3112
3113 dwarf2_emit_insn (insn_length + op_length);
3114 break;
3115
3116 case 5:
b18c562e 3117 {
13761a11
NC		 3118 int n;
3119 int reg;
3120
3121 /* [POP|PUSH]M[.A] #N, Rd */
b18c562e 3122 line = extract_operand (line, l1, sizeof (l1));
13761a11 3123 line = extract_operand (line, l2, sizeof (l2));
2469cfa2 3124
13761a11
NC		 3125 if (*l1 != '#')
3126 {
638d3803 3127 as_bad (_("expected #n as first argument of %s"), opcode->name);
65d7bab5 3128 break;
13761a11 3129 }
2bfa0cdf
NC		 3130 end = parse_exp (l1 + 1, &(op1.exp));
3131 if (end != NULL && *end != 0)
3132 {
3133 as_bad (_("extra characters '%s' at end of constant expression '%s'"), end, l1);
3134 break;
3135 }
13761a11
NC		 3136 if (op1.exp.X_op != O_constant)
3137 {
33eaf5de 3138 as_bad (_("expected constant expression as first argument of %s"),
13761a11 3139 opcode->name);
65d7bab5 3140 break;
13761a11 3141 }
2469cfa2 3142
13761a11
NC		 3143 if ((reg = check_reg (l2)) == -1)
3144 {
3145 as_bad (_("expected register as second argument of %s"),
3146 opcode->name);
65d7bab5 3147 break;
13761a11 3148 }
2469cfa2 3149
13761a11
NC		 3150 op_length = 2;
3151 frag = frag_more (op_length);
b18c562e 3152 where = frag - frag_now->fr_literal;
13761a11
NC		 3153 bin = opcode->bin_opcode;
3154 if (! addr_op)
3155 bin |= 0x100;
3156 n = op1.exp.X_add_number;
3157 bin |= (n - 1) << 4;
638d3803 3158 if (is_opcode ("pushm"))
13761a11
NC		 3159 bin |= reg;
3160 else
3161 {
3162 if (reg - n + 1 < 0)
3163 {
3164 as_bad (_("Too many registers popped"));
65d7bab5 3165 break;
13761a11 3166 }
638d3803 3167
65d7bab5 3168 /* CPU21 errata: cannot use POPM to restore the SR register. */
d1706f38 3169 if (target_is_430xv2 ()
638d3803
NC		 3170 && (reg - n + 1 < 3)
3171 && reg >= 2
3172 && is_opcode ("popm"))
3173 {
3174 as_bad (_("Cannot use POPM to restore the SR register"));
65d7bab5 3175 break;
638d3803
NC		 3176 }
3177
13761a11
NC		 3178 bin |= (reg - n + 1);
3179 }
3180
b18c562e 3181 bfd_putl16 ((bfd_vma) bin, frag);
13761a11
NC		 3182 dwarf2_emit_insn (op_length);
3183 break;
3184 }
3185
3186 case 6:
3187 {
3188 int n;
3189 int reg;
3190
3191 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
3192 if (extended & 0xff)
3193 {
3194 as_bad (_("repeat count cannot be used with %s"), opcode->name);
65d7bab5 3195 break;
13761a11
NC		 3196 }
3197
3198 line = extract_operand (line, l1, sizeof (l1));
3199 line = extract_operand (line, l2, sizeof (l2));
3200
3201 if (*l1 != '#')
3202 {
3203 as_bad (_("expected #n as first argument of %s"), opcode->name);
65d7bab5 3204 break;
13761a11 3205 }
2bfa0cdf
NC		 3206 end = parse_exp (l1 + 1, &(op1.exp));
3207 if (end != NULL && *end != 0)
3208 {
3209 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3210 break;
3211 }
13761a11
NC		 3212 if (op1.exp.X_op != O_constant)
3213 {
33eaf5de 3214 as_bad (_("expected constant expression as first argument of %s"),
13761a11 3215 opcode->name);
65d7bab5 3216 break;
13761a11
NC		 3217 }
3218 n = op1.exp.X_add_number;
3219 if (n > 4 || n < 1)
b18c562e 3220 {
13761a11
NC		 3221 as_bad (_("expected first argument of %s to be in the range 1-4"),
3222 opcode->name);
65d7bab5 3223 break;
13761a11 3224 }
b18c562e 3225
13761a11
NC		 3226 if ((reg = check_reg (l2)) == -1)
3227 {
3228 as_bad (_("expected register as second argument of %s"),
3229 opcode->name);
65d7bab5 3230 break;
b18c562e
NC		 3231 }
3232
d1706f38 3233 if (target_is_430xv2 () && reg == 0)
638d3803
NC		 3234 {
3235 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
65d7bab5 3236 break;
638d3803
NC		 3237 }
3238
13761a11
NC		 3239 op_length = 2;
3240 frag = frag_more (op_length);
3241 where = frag - frag_now->fr_literal;
3242
3243 bin = opcode->bin_opcode;
3244 if (! addr_op)
3245 bin |= 0x10;
3246 bin |= (n - 1) << 10;
3247 bin |= reg;
3248
3249 bfd_putl16 ((bfd_vma) bin, frag);
3250 dwarf2_emit_insn (op_length);
3251 break;
3252 }
3253
13761a11
NC		 3254 case 8:
3255 {
3256 bfd_boolean need_reloc = FALSE;
3257 int n;
3258 int reg;
3259
3260 /* ADDA, CMPA and SUBA address instructions. */
3261 if (extended & 0xff)
3262 {
3263 as_bad (_("repeat count cannot be used with %s"), opcode->name);
65d7bab5 3264 break;
13761a11
NC		 3265 }
3266
3267 line = extract_operand (line, l1, sizeof (l1));
3268 line = extract_operand (line, l2, sizeof (l2));
3269
3270 bin = opcode->bin_opcode;
3271
3272 if (*l1 == '#')
3273 {
2bfa0cdf
NC		 3274 end = parse_exp (l1 + 1, &(op1.exp));
3275 if (end != NULL && *end != 0)
3276 {
3277 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3278 break;
3279 }
13761a11
NC		 3280
3281 if (op1.exp.X_op == O_constant)
3282 {
3283 n = op1.exp.X_add_number;
3284 if (n > 0xfffff || n < - (0x7ffff))
3285 {
3286 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
3287 opcode->name);
65d7bab5 3288 break;
13761a11
NC		 3289 }
3290
3291 bin |= ((n >> 16) & 0xf) << 8;
3292 }
3293 else
3294 {
3295 n = 0;
3296 need_reloc = TRUE;
3297 }
3298
3299 op_length = 4;
3300 }
3301 else
3302 {
3303 if ((n = check_reg (l1)) == -1)
3304 {
3305 as_bad (_("expected register name or constant as first argument of %s"),
3306 opcode->name);
65d7bab5 3307 break;
13761a11
NC		 3308 }
3309
3310 bin |= (n << 8) | (1 << 6);
3311 op_length = 2;
3312 }
3313
3314 if ((reg = check_reg (l2)) == -1)
3315 {
3316 as_bad (_("expected register as second argument of %s"),
3317 opcode->name);
65d7bab5 3318 break;
13761a11
NC		 3319 }
3320
3321 frag = frag_more (op_length);
3322 where = frag - frag_now->fr_literal;
3323 bin |= reg;
3324 if (need_reloc)
3325 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3326 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
3327
3328 bfd_putl16 ((bfd_vma) bin, frag);
3329 if (op_length == 4)
3330 bfd_putl16 ((bfd_vma) (n & 0xffff), frag + 2);
3331 dwarf2_emit_insn (op_length);
b18c562e 3332 break;
13761a11 3333 }
38d77545 3334
13761a11 3335 case 9: /* MOVA, BRA, RETA. */
00b32ff2 3336 imm_op = FALSE;
13761a11 3337 bin = opcode->bin_opcode;
b18c562e 3338
638d3803 3339 if (is_opcode ("reta"))
13761a11
NC		 3340 {
3341 /* The RETA instruction does not take any arguments.
3342 The implicit first argument is @SP+.
3343 The implicit second argument is PC. */
3344 op1.mode = OP_REG;
3345 op1.am = 3;
3346 op1.reg = 1;
3347
3348 op2.mode = OP_REG;
3349 op2.reg = 0;
3350 }
3351 else
3352 {
3353 line = extract_operand (line, l1, sizeof (l1));
3354 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
3355 &imm_op, extended_op, FALSE);
b18c562e 3356
638d3803 3357 if (is_opcode ("bra"))
13761a11
NC		 3358 {
3359 /* This is the BRA synthetic instruction.
3360 The second argument is always PC. */
3361 op2.mode = OP_REG;
3362 op2.reg = 0;
3363 }
3364 else
3365 {
3366 line = extract_operand (line, l2, sizeof (l2));
3367 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode,
3368 extended_op, TRUE);
3369 }
38d77545 3370
13761a11
NC		 3371 if (res)
3372 break; /* Error occurred. All warnings were done before. */
3373 }
3374
3375 /* Only a restricted subset of the normal MSP430 addressing modes
3376 are supported here, so check for the ones that are allowed. */
3377 if ((op_length = try_encode_mova (imm_op, bin, & op1, & op2,
3378 & error_message)) == 0)
2469cfa2 3379 {
13761a11 3380 as_bad (error_message, opcode->name);
65d7bab5 3381 break;
13761a11
NC		 3382 }
3383 dwarf2_emit_insn (op_length);
3384 break;
3385
3386 case 10: /* RPT */
3387 line = extract_operand (line, l1, sizeof l1);
3388 /* The RPT instruction only accepted immediates and registers. */
3389 if (*l1 == '#')
3390 {
2bfa0cdf
NC		 3391 end = parse_exp (l1 + 1, &(op1.exp));
3392 if (end != NULL && *end != 0)
3393 {
3394 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3395 break;
3396 }
13761a11
NC		 3397 if (op1.exp.X_op != O_constant)
3398 {
3399 as_bad (_("expected constant value as argument to RPT"));
65d7bab5 3400 break;
13761a11
NC		 3401 }
3402 if (op1.exp.X_add_number < 1
3403 || op1.exp.X_add_number > (1 << 4))
3404 {
3405 as_bad (_("expected constant in the range 2..16"));
65d7bab5 3406 break;
13761a11
NC		 3407 }
3408
3409 /* We silently accept and ignore a repeat count of 1. */
3410 if (op1.exp.X_add_number > 1)
3411 repeat_count = op1.exp.X_add_number;
3412 }
3413 else
3414 {
3415 int reg;
b18c562e 3416
13761a11
NC		 3417 if ((reg = check_reg (l1)) != -1)
3418 {
3419 if (reg == 0)
3420 as_warn (_("PC used as an argument to RPT"));
3421 else
3422 repeat_count = - reg;
3423 }
2469cfa2 3424 else
13761a11
NC		 3425 {
3426 as_bad (_("expected constant or register name as argument to RPT insn"));
65d7bab5 3427 break;
13761a11 3428 }
2469cfa2 3429 }
b18c562e 3430 break;
13761a11
NC		 3431
3432 default:
33eaf5de 3433 as_bad (_("Illegal emulated instruction"));
13761a11 3434 break;
2469cfa2 3435 }
b18c562e 3436 break;
2469cfa2 3437
b18c562e
NC		 3438 case 1: /* Format 1, double operand. */
3439 line = extract_operand (line, l1, sizeof (l1));
3440 line = extract_operand (line, l2, sizeof (l2));
13761a11
NC		 3441 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
3442 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
2469cfa2 3443
b18c562e
NC		 3444 if (res)
3445 break; /* Error occurred. All warnings were done before. */
2469cfa2 3446
13761a11 3447 if (extended_op
638d3803 3448 && is_opcode ("movx")
13761a11
NC		 3449 && addr_op
3450 && msp430_enable_relax)
3451 {
3452 /* This is the MOVX.A instruction. See if we can convert
3453 it into the MOVA instruction instead. This saves 2 bytes. */
3454 if ((op_length = try_encode_mova (imm_op, 0x0000, & op1, & op2,
3455 NULL)) != 0)
3456 {
3457 dwarf2_emit_insn (op_length);
3458 break;
3459 }
3460 }
3461
65d7bab5
NC		 3462 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
3463
2213f746
NC		 3464 /* If the PC is the destination... */
3465 if (op2.am == 0 && op2.reg == 0
3466 /* ... and the opcode alters the SR. */
3467 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
3468 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
3469 {
3470 if (silicon_errata_fix & SILICON_ERRATA_CPU11)
de194d85 3471 as_bad (_("CPU11: PC is destination of SR altering instruction"));
2213f746 3472 else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
de194d85 3473 as_warn (_("CPU11: PC is destination of SR altering instruction"));
2213f746
NC		 3474 }
3475
3476 /* If the status register is the destination... */
3477 if (op2.am == 0 && op2.reg == 2
3478 /* ... and the opcode alters the SR. */
3479 && (is_opcode ("add") || is_opcode ("addc") || is_opcode ("and")
3480 || is_opcode ("dadd") || is_opcode ("sub") || is_opcode ("subc")
3481 || is_opcode ("xor")
3482 || is_opcode ("addx") || is_opcode ("addcx") || is_opcode ("andx")
3483 || is_opcode ("daddx") || is_opcode ("subx") || is_opcode ("subcx")
3484 || is_opcode ("xorx")
3485 ))
3486 {
3487 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
de194d85 3488 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2213f746 3489 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
de194d85 3490 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2213f746
NC		 3491 }
3492
65d7bab5
NC		 3493 if ( (is_opcode ("bic") && bin == 0xc232)
3494 || (is_opcode ("bis") && bin == 0xd232)
3495 || (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))
3496 {
2213f746
NC		 3497 /* Avoid false checks when a constant value is being put into the SR. */
3498 if (op1.mode == OP_EXP
3499 && op1.exp.X_op == O_constant
3500 && (op1.exp.X_add_number & 0x8) != 0x8)
3501 ;
3502 else
3503 check_for_nop |= NOP_CHECK_INTERRUPT;
65d7bab5
NC		 3504 }
3505
2213f746
NC		 3506 if (((is_opcode ("bis") && bin == 0xd032)
3507 || (is_opcode ("mov") && bin == 0x4032)
3508 || (is_opcode ("xor") && bin == 0xe032))
3509 && op1.mode == OP_EXP
3510 && op1.exp.X_op == O_constant
3511 && (op1.exp.X_add_number & 0x10) == 0x10)
3512 check_for_nop |= NOP_CHECK_CPU19;
3513
13761a11 3514 /* Compute the entire length of the instruction in bytes. */
65d7bab5 3515 op_length = (extended_op ? 2 : 0) /* The extension word. */
13761a11
NC		 3516 + 2 /* The opcode */
3517 + (2 * op1.ol) /* The first operand. */
3518 + (2 * op2.ol); /* The second operand. */
b18c562e 3519
65d7bab5
NC		 3520 insn_length += op_length;
3521 frag = frag_more (op_length);
b18c562e 3522 where = frag - frag_now->fr_literal;
38d77545 3523
13761a11
NC		 3524 if (extended_op)
3525 {
3526 if (!addr_op)
3527 extended |= BYTE_OPERATION;
3528
3529 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
3530 {
3531 as_bad (_("repeat instruction used with non-register mode instruction"));
3532 extended &= ~ 0xf;
3533 }
3534
3535 /* If necessary, emit a reloc to update the extension word. */
3536 if (op1.mode == OP_EXP)
3537 {
3538 if (op1.exp.X_op == O_constant)
3539 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
3540
e66c3c25 3541 else if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11
NC		 3542 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3543 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3544 else
3545 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3546 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3547 }
38d77545 3548
13761a11
NC		 3549 if (op2.mode == OP_EXP)
3550 {
3551 if (op2.exp.X_op == O_constant)
3552 extended |= (op2.exp.X_add_number >> 16) & 0xf;
3553
3554 else if (op1.mode == OP_EXP)
3555 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
3556 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
3557 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
38d77545 3558
13761a11
NC		 3559 else
3560 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
3561 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
3562 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
3563 }
3564
3565 /* Emit the extension word. */
3566 bfd_putl16 (extended, frag);
3567 where += 2;
3568 frag += 2;
3569 }
3570
b18c562e 3571 bfd_putl16 ((bfd_vma) bin, frag);
13761a11
NC		 3572 where += 2;
3573 frag += 2;
b18c562e
NC		 3574
3575 if (op1.mode == OP_EXP)
2469cfa2 3576 {
13761a11
NC		 3577 if (op1.exp.X_op == O_constant)
3578 {
3579 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3580 }
b18c562e 3581 else
13761a11
NC		 3582 {
3583 bfd_putl16 ((bfd_vma) ZEROS, frag);
3584
3585 if (!extended_op)
3586 {
e66c3c25 3587 if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11 3588 fix_new_exp (frag_now, where, 2,
00b32ff2 3589 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
13761a11
NC		 3590 else
3591 fix_new_exp (frag_now, where, 2,
3592 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3593 }
3594 }
3595
3596 where += 2;
3597 frag += 2;
2469cfa2 3598 }
b18c562e
NC		 3599
3600 if (op2.mode == OP_EXP)
2469cfa2 3601 {
13761a11
NC		 3602 if (op2.exp.X_op == O_constant)
3603 {
3604 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
3605 }
b18c562e 3606 else
13761a11
NC		 3607 {
3608 bfd_putl16 ((bfd_vma) ZEROS, frag);
3609
3610 if (!extended_op)
3611 {
3612 if (op2.reg) /* Not PC relative. */
3613 fix_new_exp (frag_now, where, 2,
00b32ff2 3614 &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
13761a11
NC		 3615 else
3616 fix_new_exp (frag_now, where, 2,
3617 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3618 }
3619 }
3620 }
3621
13761a11 3622 dwarf2_emit_insn (insn_length);
2213f746
NC		 3623
3624 /* If the PC is the destination... */
3625 if (op2.am == 0 && op2.reg == 0
3626 /* ... but the opcode does not alter the destination. */
3627 && (is_opcode ("cmp") || is_opcode ("bit") || is_opcode ("cmpx")))
3628 check_for_nop |= NOP_CHECK_CPU12;
b18c562e
NC		 3629 break;
3630
3631 case 2: /* Single-operand mostly instr. */
3632 if (opcode->insn_opnumb == 0)
2469cfa2 3633 {
b18c562e 3634 /* reti instruction. */
13761a11 3635 insn_length += 2;
b18c562e
NC		 3636 frag = frag_more (2);
3637 bfd_putl16 ((bfd_vma) bin, frag);
13761a11 3638 dwarf2_emit_insn (insn_length);
b18c562e 3639 break;
2469cfa2 3640 }
2469cfa2 3641
b18c562e 3642 line = extract_operand (line, l1, sizeof (l1));
13761a11
NC		 3643 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
3644 &imm_op, extended_op, TRUE);
b18c562e
NC		 3645 if (res)
3646 break; /* Error in operand. */
2469cfa2 3647
d1706f38
NC		 3648 if (target_is_430xv2 ()
3649 && op1.mode == OP_REG
38d77545 3650 && op1.reg == 0
638d3803
NC		 3651 && (is_opcode ("rrax")
3652 || is_opcode ("rrcx")
3653 || is_opcode ("rra")
3654 || is_opcode ("rrc")))
3655 {
3656 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
65d7bab5 3657 break;
638d3803 3658 }
38d77545 3659
2213f746
NC		 3660 /* If the status register is the destination... */
3661 if (op1.am == 0 && op1.reg == 2
3662 /* ... and the opcode alters the SR. */
3663 && (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
3664 {
3665 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
de194d85 3666 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2213f746 3667 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
de194d85 3668 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2213f746
NC		 3669 }
3670
13761a11
NC		 3671 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
3672 frag = frag_more (insn_length);
b18c562e 3673 where = frag - frag_now->fr_literal;
38d77545 3674
13761a11
NC		 3675 if (extended_op)
3676 {
638d3803 3677 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
13761a11
NC		 3678 {
3679 /* These two instructions use a special
3680 encoding of the A/L and B/W bits. */
3681 bin &= ~ BYTE_OPERATION;
3682
3683 if (byte_op)
3684 {
3685 as_bad (_("%s instruction does not accept a .b suffix"),
3686 opcode->name);
65d7bab5 3687 break;
13761a11
NC		 3688 }
3689 else if (! addr_op)
3690 extended |= BYTE_OPERATION;
3691 }
3692 else if (! addr_op)
3693 extended |= BYTE_OPERATION;
3694
c1d9289f
NC		 3695 if (is_opcode ("rrux"))
3696 extended |= IGNORE_CARRY_BIT;
3697
13761a11
NC		 3698 if (op1.ol != 0 && ((extended & 0xf) != 0))
3699 {
3700 as_bad (_("repeat instruction used with non-register mode instruction"));
3701 extended &= ~ 0xf;
3702 }
3703
3704 if (op1.mode == OP_EXP)
3705 {
3706 if (op1.exp.X_op == O_constant)
3707 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
38d77545 3708
e66c3c25 3709 else if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11
NC		 3710 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3711 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3712 else
3713 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3714 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3715 }
38d77545 3716
13761a11
NC		 3717 /* Emit the extension word. */
3718 bfd_putl16 (extended, frag);
3719 frag += 2;
3720 where += 2;
3721 }
3722
3723 bin |= op1.reg | (op1.am << 4);
b18c562e 3724 bfd_putl16 ((bfd_vma) bin, frag);
13761a11
NC		 3725 frag += 2;
3726 where += 2;
b18c562e
NC		 3727
3728 if (op1.mode == OP_EXP)
2469cfa2 3729 {
13761a11
NC		 3730 if (op1.exp.X_op == O_constant)
3731 {
3732 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3733 }
b18c562e 3734 else
13761a11
NC		 3735 {
3736 bfd_putl16 ((bfd_vma) ZEROS, frag);
3737
3738 if (!extended_op)
3739 {
e66c3c25 3740 if (op1.reg || op1.am == 3) /* Not PC relative. */
13761a11 3741 fix_new_exp (frag_now, where, 2,
00b32ff2 3742 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
13761a11
NC		 3743 else
3744 fix_new_exp (frag_now, where, 2,
3745 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3746 }
3747 }
2469cfa2 3748 }
13761a11
NC		 3749
3750 dwarf2_emit_insn (insn_length);
b18c562e 3751 break;
2469cfa2 3752
b18c562e
NC		 3753 case 3: /* Conditional jumps instructions. */
3754 line = extract_operand (line, l1, sizeof (l1));
3755 /* l1 is a label. */
3756 if (l1[0])
2469cfa2 3757 {
b18c562e
NC		 3758 char *m = l1;
3759 expressionS exp;
2469cfa2 3760
b18c562e
NC		 3761 if (*m == '$')
3762 m++;
2469cfa2 3763
2bfa0cdf
NC		 3764 end = parse_exp (m, &exp);
3765 if (end != NULL && *end != 0)
3766 {
3767 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3768 break;
3769 }
2469cfa2 3770
b18c562e 3771 /* In order to handle something like:
2469cfa2 3772
b18c562e
NC		 3773 and #0x8000, r5
3774 tst r5
3775 jz 4 ; skip next 4 bytes
3776 inv r5
3777 inc r5
3778 nop ; will jump here if r5 positive or zero
2469cfa2 3779
b18c562e 3780 jCOND -n ;assumes jump n bytes backward:
2469cfa2 3781
b18c562e
NC		 3782 mov r5,r6
3783 jmp -2
2469cfa2 3784
b18c562e
NC		 3785 is equal to:
3786 lab:
3787 mov r5,r6
3788 jmp lab
3789
3790 jCOND $n ; jump from PC in either direction. */
2469cfa2 3791
b18c562e
NC		 3792 if (exp.X_op == O_constant)
3793 {
3794 int x = exp.X_add_number;
2469cfa2 3795
b18c562e
NC		 3796 if (x & 1)
3797 {
3798 as_warn (_("Even number required. Rounded to %d"), x + 1);
3799 x++;
3800 }
2469cfa2 3801
b18c562e
NC		 3802 if ((*l1 == '$' && x > 0) || x < 0)
3803 x -= 2;
2469cfa2 3804
b18c562e
NC		 3805 x >>= 1;
3806
3807 if (x > 512 || x < -511)
3808 {
33eaf5de 3809 as_bad (_("Wrong displacement %d"), x << 1);
b18c562e
NC		 3810 break;
3811 }
3812
13761a11
NC		 3813 insn_length += 2;
3814 frag = frag_more (2); /* Instr size is 1 word. */
3815
b18c562e
NC		 3816 bin |= x & 0x3ff;
3817 bfd_putl16 ((bfd_vma) bin, frag);
3818 }
3819 else if (exp.X_op == O_symbol && *l1 != '$')
2469cfa2 3820 {
13761a11
NC		 3821 insn_length += 2;
3822 frag = frag_more (2); /* Instr size is 1 word. */
b18c562e
NC		 3823 where = frag - frag_now->fr_literal;
3824 fix_new_exp (frag_now, where, 2,
3825 &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
3826
3827 bfd_putl16 ((bfd_vma) bin, frag);
2469cfa2 3828 }
b18c562e 3829 else if (*l1 == '$')
2469cfa2 3830 {
b18c562e 3831 as_bad (_("instruction requires label sans '$'"));
2469cfa2 3832 }
b18c562e 3833 else
13761a11
NC		 3834 as_bad (_
3835 ("instruction requires label or value in range -511:512"));
3836 dwarf2_emit_insn (insn_length);
2a9a06c1 3837 break;
2469cfa2 3838 }
b18c562e
NC		 3839 else
3840 {
3841 as_bad (_("instruction requires label"));
3842 break;
3843 }
3844 break;
2469cfa2 3845
b18c562e 3846 case 4: /* Extended jumps. */
77592908
DD		 3847 if (!msp430_enable_polys)
3848 {
20203fb9 3849 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
77592908
DD		 3850 break;
3851 }
3739860c 3852
b18c562e
NC		 3853 line = extract_operand (line, l1, sizeof (l1));
3854 if (l1[0])
2469cfa2 3855 {
b18c562e
NC		 3856 char *m = l1;
3857 expressionS exp;
2469cfa2 3858
b18c562e
NC		 3859 /* Ignore absolute addressing. make it PC relative anyway. */
3860 if (*m == '#' || *m == '$')
3861 m++;
2469cfa2 3862
2bfa0cdf
NC		 3863 end = parse_exp (m, & exp);
3864 if (end != NULL && *end != 0)
3865 {
3866 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3867 break;
3868 }
b18c562e 3869 if (exp.X_op == O_symbol)
2469cfa2 3870 {
b18c562e
NC		 3871 /* Relaxation required. */
3872 struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb];
3873
638d3803 3874 if (target_is_430x ())
13761a11
NC		 3875 rc = msp430x_rcodes[opcode->insn_opnumb];
3876
3877 /* The parameter to dwarf2_emit_insn is actually the offset to
3878 the start of the insn from the fix piece of instruction that
3879 was emitted. Since next fragments may have variable size we
3880 tie debug info to the beginning of the instruction. */
3881 insn_length += 8;
3e470ab5 3882 frag = frag_more (8);
2a9a06c1 3883 dwarf2_emit_insn (0);
3e470ab5
DD		 3884 bfd_putl16 ((bfd_vma) rc.sop, frag);
3885 frag = frag_variant (rs_machine_dependent, 8, 2,
13761a11
NC		 3886 /* Wild guess. */
3887 ENCODE_RELAX (rc.lpos, STATE_BITS10),
b18c562e
NC		 3888 exp.X_add_symbol,
3889 0, /* Offset is zero if jump dist less than 1K. */
3890 (char *) frag);
3891 break;
2469cfa2
NC		 3892 }
3893 }
b18c562e
NC		 3894
3895 as_bad (_("instruction requires label"));
3896 break;
3897
3898 case 5: /* Emulated extended branches. */
77592908
DD		 3899 if (!msp430_enable_polys)
3900 {
20203fb9 3901 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
77592908
DD		 3902 break;
3903 }
b18c562e
NC		 3904 line = extract_operand (line, l1, sizeof (l1));
3905 if (l1[0])
2469cfa2 3906 {
b18c562e
NC		 3907 char * m = l1;
3908 expressionS exp;
3909
3910 /* Ignore absolute addressing. make it PC relative anyway. */
3911 if (*m == '#' || *m == '$')
3912 m++;
3913
2bfa0cdf
NC		 3914 end = parse_exp (m, & exp);
3915 if (end != NULL && *end != 0)
3916 {
3917 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3918 break;
3919 }
b18c562e
NC		 3920 if (exp.X_op == O_symbol)
3921 {
3922 /* Relaxation required. */
3923 struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb];
3924
638d3803 3925 if (target_is_430x ())
13761a11
NC		 3926 hc = msp430x_hcodes[opcode->insn_opnumb];
3927
3928 insn_length += 8;
3e470ab5 3929 frag = frag_more (8);
2a9a06c1 3930 dwarf2_emit_insn (0);
3e470ab5
DD		 3931 bfd_putl16 ((bfd_vma) hc.op0, frag);
3932 bfd_putl16 ((bfd_vma) hc.op1, frag+2);
3933
3934 frag = frag_variant (rs_machine_dependent, 8, 2,
b18c562e
NC		 3935 ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */
3936 exp.X_add_symbol,
3937 0, /* Offset is zero if jump dist less than 1K. */
3938 (char *) frag);
3939 break;
3940 }
2469cfa2
NC		 3941 }
3942
b18c562e
NC		 3943 as_bad (_("instruction requires label"));
3944 break;
2469cfa2 3945
b18c562e 3946 default:
79cf5950 3947 as_bad (_("Illegal instruction or not implemented opcode."));
b18c562e 3948 }
2469cfa2 3949
927f2d25
NC		 3950 if (is_opcode ("nop"))
3951 prev_insn_is_nop = TRUE;
3952 else
3953 prev_insn_is_nop = FALSE;
3954
b18c562e
NC		 3955 input_line_pointer = line;
3956 return 0;
3957}
2469cfa2 3958
b18c562e
NC		 3959void
3960md_assemble (char * str)
3961{
3962 struct msp430_opcode_s * opcode;
3963 char cmd[32];
3964 unsigned int i = 0;
2469cfa2 3965
b18c562e 3966 str = skip_space (str); /* Skip leading spaces. */
64a81db0 3967 str = extract_cmd (str, cmd, sizeof (cmd) - 1);
2469cfa2 3968
64a81db0 3969 while (cmd[i])
b18c562e
NC		 3970 {
3971 char a = TOLOWER (cmd[i]);
3972 cmd[i] = a;
3973 i++;
2469cfa2 3974 }
2469cfa2 3975
b18c562e 3976 if (!cmd[0])
2469cfa2 3977 {
33eaf5de 3978 as_bad (_("can't find opcode"));
b18c562e
NC		 3979 return;
3980 }
2469cfa2 3981
b18c562e 3982 opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);
2469cfa2 3983
b18c562e
NC		 3984 if (opcode == NULL)
3985 {
3986 as_bad (_("unknown opcode `%s'"), cmd);
3987 return;
2469cfa2 3988 }
2469cfa2 3989
b18c562e
NC		 3990 {
3991 char *__t = input_line_pointer;
2469cfa2 3992
b18c562e
NC		 3993 msp430_operands (opcode, str);
3994 input_line_pointer = __t;
3995 }
3996}
2469cfa2
NC		 3997
3998/* GAS will call this function for each section at the end of the assembly,
3999 to permit the CPU backend to adjust the alignment of a section. */
4000
4001valueT
b18c562e 4002md_section_align (asection * seg, valueT addr)
2469cfa2
NC		 4003{
4004 int align = bfd_get_section_alignment (stdoutput, seg);
4005
8d3842cd 4006 return ((addr + (1 << align) - 1) & -(1 << align));
2469cfa2
NC		 4007}
4008
4009/* If you define this macro, it should return the offset between the
4010 address of a PC relative fixup and the position from which the PC
4011 relative adjustment should be made. On many processors, the base
4012 of a PC relative instruction is the next instruction, so this
4013 macro would return the length of an instruction. */
4014
4015long
b18c562e 4016md_pcrel_from_section (fixS * fixp, segT sec)
2469cfa2
NC		 4017{
4018 if (fixp->fx_addsy != (symbolS *) NULL
4019 && (!S_IS_DEFINED (fixp->fx_addsy)
4020 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
4021 return 0;
4022
4023 return fixp->fx_frag->fr_address + fixp->fx_where;
4024}
4025
91cb9803 4026/* Addition to the standard TC_FORCE_RELOCATION_LOCAL.
77592908 4027 Now it handles the situation when relocations
13761a11 4028 have to be passed to linker. */
77592908 4029int
13761a11 4030msp430_force_relocation_local (fixS *fixp)
77592908 4031{
13761a11
NC		 4032 if (fixp->fx_r_type == BFD_RELOC_MSP430_10_PCREL)
4033 return 1;
13761a11
NC		 4034 if (fixp->fx_pcrel)
4035 return 1;
77592908
DD		 4036 if (msp430_enable_polys
4037 && !msp430_enable_relax)
4038 return 1;
13761a11 4039
91cb9803 4040 return 0;
77592908
DD		 4041}
4042
4043
2469cfa2
NC		 4044/* GAS will call this for each fixup. It should store the correct
4045 value in the object file. */
2469cfa2 4046void
55cf6793 4047md_apply_fix (fixS * fixp, valueT * valuep, segT seg)
2469cfa2 4048{
b18c562e 4049 unsigned char * where;
2469cfa2
NC		 4050 unsigned long insn;
4051 long value;
4052
4053 if (fixp->fx_addsy == (symbolS *) NULL)
4054 {
4055 value = *valuep;
4056 fixp->fx_done = 1;
4057 }
4058 else if (fixp->fx_pcrel)
4059 {
4060 segT s = S_GET_SEGMENT (fixp->fx_addsy);
4061
4062 if (fixp->fx_addsy && (s == seg || s == absolute_section))
4063 {
18af0b39
NC		 4064 /* FIXME: We can appear here only in case if we perform a pc
4065 relative jump to the label which is i) global, ii) locally
4066 defined or this is a jump to an absolute symbol.
4067 If this is an absolute symbol -- everything is OK.
4068 If this is a global label, we've got a symbol value defined
4069 twice:
4070 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
4071 from this section start
4072 2. *valuep will contain the real offset from jump insn to the
4073 label
4074 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
4075 will be incorrect. Therefore remove s_get_value. */
4076 value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep;
2469cfa2
NC		 4077 fixp->fx_done = 1;
4078 }
4079 else
4080 value = *valuep;
4081 }
4082 else
4083 {
4084 value = fixp->fx_offset;
4085
4086 if (fixp->fx_subsy != (symbolS *) NULL)
4087 {
4088 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
4089 {
4090 value -= S_GET_VALUE (fixp->fx_subsy);
4091 fixp->fx_done = 1;
4092 }
2469cfa2
NC		 4093 }
4094 }
4095
77592908
DD		 4096 fixp->fx_no_overflow = 1;
4097
38d77545 4098 /* If polymorphs are enabled and relax disabled.
13761a11 4099 do not kill any relocs and pass them to linker. */
38d77545 4100 if (msp430_enable_polys
77592908 4101 && !msp430_enable_relax)
2469cfa2 4102 {
e66c3c25
NC		 4103 if (!fixp->fx_addsy
4104 || S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
79cf5950 4105 fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */
77592908
DD		 4106 else
4107 fixp->fx_done = 0;
2469cfa2
NC		 4108 }
4109
4110 if (fixp->fx_done)
4111 {
4112 /* Fetch the instruction, insert the fully resolved operand
8cd5b113 4113 value, and stuff the instruction back again. */
2132e3a3 4114 where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where;
2469cfa2
NC		 4115
4116 insn = bfd_getl16 (where);
4117
4118 switch (fixp->fx_r_type)
4119 {
4120 case BFD_RELOC_MSP430_10_PCREL:
4121 if (value & 1)
4122 as_bad_where (fixp->fx_file, fixp->fx_line,
4123 _("odd address operand: %ld"), value);
4124
4125 /* Jumps are in words. */
4126 value >>= 1;
4127 --value; /* Correct PC. */
4128
4129 if (value < -512 || value > 511)
4130 as_bad_where (fixp->fx_file, fixp->fx_line,
4131 _("operand out of range: %ld"), value);
4132
4133 value &= 0x3ff; /* get rid of extended sign */
4134 bfd_putl16 ((bfd_vma) (value | insn), where);
4135 break;
4136
13761a11 4137 case BFD_RELOC_MSP430X_PCR16:
b18c562e 4138 case BFD_RELOC_MSP430_RL_PCREL:
2469cfa2
NC		 4139 case BFD_RELOC_MSP430_16_PCREL:
4140 if (value & 1)
4141 as_bad_where (fixp->fx_file, fixp->fx_line,
4142 _("odd address operand: %ld"), value);
13761a11 4143 /* Fall through. */
2469cfa2
NC		 4144
4145 case BFD_RELOC_MSP430_16_PCREL_BYTE:
4146 /* Nothing to be corrected here. */
4147 if (value < -32768 || value > 65536)
4148 as_bad_where (fixp->fx_file, fixp->fx_line,
4149 _("operand out of range: %ld"), value);
13761a11 4150 /* Fall through. */
2469cfa2 4151
13761a11
NC		 4152 case BFD_RELOC_MSP430X_ABS16:
4153 case BFD_RELOC_MSP430_16:
4154 case BFD_RELOC_16:
4155 case BFD_RELOC_MSP430_16_BYTE:
2469cfa2
NC		 4156 value &= 0xffff; /* Get rid of extended sign. */
4157 bfd_putl16 ((bfd_vma) value, where);
4158 break;
4159
00b32ff2
NC		 4160 case BFD_RELOC_MSP430_ABS_HI16:
4161 value >>= 16;
4162 value &= 0xffff; /* Get rid of extended sign. */
4163 bfd_putl16 ((bfd_vma) value, where);
4164 break;
3739860c 4165
2469cfa2
NC		 4166 case BFD_RELOC_32:
4167 bfd_putl16 ((bfd_vma) value, where);
4168 break;
4169
13761a11
NC		 4170 case BFD_RELOC_MSP430_ABS8:
4171 case BFD_RELOC_8:
4172 bfd_put_8 (NULL, (bfd_vma) value, where);
4173 break;
4174
4175 case BFD_RELOC_MSP430X_ABS20_EXT_SRC:
4176 case BFD_RELOC_MSP430X_PCR20_EXT_SRC:
4177 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
38d77545 4178 value >>= 16;
13761a11
NC		 4179 bfd_putl16 ((bfd_vma) (((value & 0xf) << 7) | insn), where);
4180 break;
4181
4182 case BFD_RELOC_MSP430X_ABS20_ADR_SRC:
4183 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
38d77545 4184 value >>= 16;
13761a11
NC		 4185 bfd_putl16 ((bfd_vma) (((value & 0xf) << 8) | insn), where);
4186 break;
4187
4188 case BFD_RELOC_MSP430X_ABS20_EXT_ODST:
4189 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
4190 value >>= 16;
4191 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4192 break;
4193
4194 case BFD_RELOC_MSP430X_PCR20_CALL:
4195 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4196 value >>= 16;
4197 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4198 break;
4199
4200 case BFD_RELOC_MSP430X_ABS20_EXT_DST:
4201 case BFD_RELOC_MSP430X_PCR20_EXT_DST:
4202 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
4203 value >>= 16;
4204 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4205 break;
4206
4207 case BFD_RELOC_MSP430X_PCR20_EXT_ODST:
4208 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
4209 value >>= 16;
4210 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4211 break;
4212
4213 case BFD_RELOC_MSP430X_ABS20_ADR_DST:
4214 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4215 value >>= 16;
4216 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
2469cfa2 4217 break;
38d77545 4218
2469cfa2
NC		 4219 default:
4220 as_fatal (_("line %d: unknown relocation type: 0x%x"),
4221 fixp->fx_line, fixp->fx_r_type);
4222 break;
4223 }
4224 }
4225 else
4226 {
4227 fixp->fx_addnumber = value;
4228 }
2469cfa2
NC		 4229}
4230
13761a11
NC		 4231static bfd_boolean
4232S_IS_GAS_LOCAL (symbolS * s)
4233{
4234 const char * name;
4235 unsigned int len;
4236
4237 if (s == NULL)
4238 return FALSE;
4239 name = S_GET_NAME (s);
4240 len = strlen (name) - 1;
38d77545 4241
13761a11
NC		 4242 return name[len] == 1 || name[len] == 2;
4243}
4244
7be1c489
AM		 4245/* GAS will call this to generate a reloc, passing the resulting reloc
4246 to `bfd_install_relocation'. This currently works poorly, as
4247 `bfd_install_relocation' often does the wrong thing, and instances of
4248 `tc_gen_reloc' have been written to work around the problems, which
4249 in turns makes it difficult to fix `bfd_install_relocation'. */
2469cfa2
NC		 4250
4251/* If while processing a fixup, a reloc really needs to be created
4252 then it is done here. */
4253
13761a11 4254arelent **
b18c562e 4255tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
2469cfa2 4256{
13761a11
NC		 4257 static arelent * no_relocs = NULL;
4258 static arelent * relocs[MAX_RELOC_EXPANSION + 1];
4259 arelent *reloc;
2469cfa2 4260
325801bd 4261 reloc = XNEW (arelent);
2469cfa2
NC		 4262 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4263 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
13761a11 4264
2469cfa2
NC		 4265 if (reloc->howto == (reloc_howto_type *) NULL)
4266 {
4267 as_bad_where (fixp->fx_file, fixp->fx_line,
4268 _("reloc %d not supported by object file format"),
4269 (int) fixp->fx_r_type);
13761a11
NC		 4270 free (reloc);
4271 return & no_relocs;
4272 }
4273
4274 relocs[0] = reloc;
4275 relocs[1] = NULL;
4276
4277 if (fixp->fx_subsy
4278 && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
4279 {
4280 fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy);
4281 fixp->fx_subsy = NULL;
2469cfa2
NC		 4282 }
4283
13761a11
NC		 4284 if (fixp->fx_addsy && fixp->fx_subsy)
4285 {
4286 asection *asec, *ssec;
4287
4288 asec = S_GET_SEGMENT (fixp->fx_addsy);
4289 ssec = S_GET_SEGMENT (fixp->fx_subsy);
4290
4291 /* If we have a difference between two different, non-absolute symbols
4292 we must generate two relocs (one for each symbol) and allow the
4293 linker to resolve them - relaxation may change the distances between
4294 symbols, even local symbols defined in the same section.
4295
4296 Unfortunately we cannot do this with assembler generated local labels
4297 because there can be multiple incarnations of the same label, with
4298 exactly the same name, in any given section and the linker will have
4299 no way to identify the correct one. Instead we just have to hope
33eaf5de 4300 that no relaxation will occur between the local label and the other
13761a11
NC		 4301 symbol in the expression.
4302
4303 Similarly we have to compute differences between symbols in the .eh_frame
4304 section as the linker is not smart enough to apply relocations there
4305 before attempting to process it. */
4306 if ((ssec != absolute_section || asec != absolute_section)
4307 && (fixp->fx_addsy != fixp->fx_subsy)
4308 && strcmp (ssec->name, ".eh_frame") != 0
4309 && ! S_IS_GAS_LOCAL (fixp->fx_addsy)
4310 && ! S_IS_GAS_LOCAL (fixp->fx_subsy))
4311 {
325801bd 4312 arelent * reloc2 = XNEW (arelent);
2469cfa2 4313
13761a11
NC		 4314 relocs[0] = reloc2;
4315 relocs[1] = reloc;
2469cfa2 4316
13761a11
NC		 4317 reloc2->address = reloc->address;
4318 reloc2->howto = bfd_reloc_type_lookup (stdoutput,
4319 BFD_RELOC_MSP430_SYM_DIFF);
4320 reloc2->addend = - S_GET_VALUE (fixp->fx_subsy);
4321
4322 if (ssec == absolute_section)
4323 reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
4324 else
4325 {
325801bd 4326 reloc2->sym_ptr_ptr = XNEW (asymbol *);
13761a11
NC		 4327 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
4328 }
4329
38d77545 4330 reloc->addend = fixp->fx_offset;
13761a11
NC		 4331 if (asec == absolute_section)
4332 {
4333 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
4334 reloc->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
4335 }
4336 else
4337 {
325801bd 4338 reloc->sym_ptr_ptr = XNEW (asymbol *);
13761a11
NC		 4339 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4340 }
4341
4342 fixp->fx_pcrel = 0;
4343 fixp->fx_done = 1;
4344 return relocs;
4345 }
4346 else
4347 {
4348 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
4349
4350 reloc->addend = (S_GET_VALUE (fixp->fx_addsy)
4351 - S_GET_VALUE (fixp->fx_subsy) + fixp->fx_offset);
4352
4353 switch (fixp->fx_r_type)
4354 {
4355 case BFD_RELOC_8:
4356 md_number_to_chars (fixpos, reloc->addend, 1);
4357 break;
4358
4359 case BFD_RELOC_16:
4360 md_number_to_chars (fixpos, reloc->addend, 2);
4361 break;
4362
4363 case BFD_RELOC_24:
4364 md_number_to_chars (fixpos, reloc->addend, 3);
4365 break;
4366
4367 case BFD_RELOC_32:
4368 md_number_to_chars (fixpos, reloc->addend, 4);
4369 break;
4370
4371 default:
4372 reloc->sym_ptr_ptr
4373 = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
4374 return relocs;
4375 }
4376
4377 free (reloc);
4378 return & no_relocs;
4379 }
4380 }
4381 else
4382 {
4383#if 0
4384 if (fixp->fx_r_type == BFD_RELOC_MSP430X_ABS16
4385 && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
4386 {
4387 bfd_vma amount = S_GET_VALUE (fixp->fx_addsy);
4388 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
4389
4390 md_number_to_chars (fixpos, amount, 2);
4391 free (reloc);
4392 return & no_relocs;
4393 }
4394#endif
325801bd 4395 reloc->sym_ptr_ptr = XNEW (asymbol *);
13761a11
NC		 4396 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4397 reloc->addend = fixp->fx_offset;
4398
4399 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4400 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4401 reloc->address = fixp->fx_offset;
4402 }
4403
4404 return relocs;
2469cfa2
NC		 4405}
4406
b18c562e
NC		 4407int
4408md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
4409 asection * segment_type ATTRIBUTE_UNUSED)
4410{
4411 if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4412 {
4413 /* This is a jump -> pcrel mode. Nothing to do much here.
4414 Return value == 2. */
4415 fragP->fr_subtype =
4416 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10);
4417 }
4418 else if (fragP->fr_symbol)
4419 {
33eaf5de 4420 /* It's got a segment, but it's not ours. Even if fr_symbol is in
79cf5950 4421 an absolute segment, we don't know a displacement until we link
b18c562e
NC		 4422 object files. So it will always be long. This also applies to
4423 labels in a subsegment of current. Liker may relax it to short
4424 jump later. Return value == 8. */
4425 fragP->fr_subtype =
4426 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD);
4427 }
4428 else
4429 {
4430 /* We know the abs value. may be it is a jump to fixed address.
79cf5950 4431 Impossible in our case, cause all constants already handled. */
b18c562e
NC		 4432 fragP->fr_subtype =
4433 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF);
4434 }
2469cfa2 4435
b18c562e
NC		 4436 return md_relax_table[fragP->fr_subtype].rlx_length;
4437}
4438
4439void
4440md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
4441 asection * sec ATTRIBUTE_UNUSED,
4442 fragS * fragP)
2469cfa2 4443{
b18c562e
NC		 4444 char * where = 0;
4445 int rela = -1;
4446 int i;
4447 struct rcodes_s * cc = NULL;
4448 struct hcodes_s * hc = NULL;
4449
4450 switch (fragP->fr_subtype)
4451 {
4452 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10):
4453 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10):
4454 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10):
4455 /* We do not have to convert anything here.
4456 Just apply a fix. */
4457 rela = BFD_RELOC_MSP430_10_PCREL;
4458 break;
4459
4460 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD):
4461 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF):
4462 /* Convert uncond branch jmp lab -> br lab. */
638d3803 4463 if (target_is_430x ())
13761a11 4464 cc = msp430x_rcodes + 7;
638d3803
NC		 4465 else
4466 cc = msp430_rcodes + 7;
b18c562e
NC		 4467 where = fragP->fr_literal + fragP->fr_fix;
4468 bfd_putl16 (cc->lop0, where);
4469 rela = BFD_RELOC_MSP430_RL_PCREL;
4470 fragP->fr_fix += 2;
4471 break;
4472
4473 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD):
4474 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF):
4475 {
4476 /* Other simple branches. */
4477 int insn = bfd_getl16 (fragP->fr_opcode);
4478
4479 insn &= 0xffff;
4480 /* Find actual instruction. */
638d3803 4481 if (target_is_430x ())
13761a11
NC		 4482 {
4483 for (i = 0; i < 7 && !cc; i++)
4484 if (msp430x_rcodes[i].sop == insn)
4485 cc = msp430x_rcodes + i;
4486 }
4487 else
4488 {
4489 for (i = 0; i < 7 && !cc; i++)
4490 if (msp430_rcodes[i].sop == insn)
4491 cc = & msp430_rcodes[i];
4492 }
4493
b18c562e
NC		 4494 if (!cc || !cc->name)
4495 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
4496 __FUNCTION__, (long) insn);
4497 where = fragP->fr_literal + fragP->fr_fix;
4498 bfd_putl16 (cc->lop0, where);
4499 bfd_putl16 (cc->lop1, where + 2);
4500 rela = BFD_RELOC_MSP430_RL_PCREL;
4501 fragP->fr_fix += 4;
4502 }
4503 break;
4504
4505 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD):
4506 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF):
638d3803 4507 if (target_is_430x ())
13761a11 4508 cc = msp430x_rcodes + 6;
638d3803
NC		 4509 else
4510 cc = msp430_rcodes + 6;
b18c562e
NC		 4511 where = fragP->fr_literal + fragP->fr_fix;
4512 bfd_putl16 (cc->lop0, where);
4513 bfd_putl16 (cc->lop1, where + 2);
4514 bfd_putl16 (cc->lop2, where + 4);
4515 rela = BFD_RELOC_MSP430_RL_PCREL;
4516 fragP->fr_fix += 6;
4517 break;
4518
4519 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10):
4520 {
4521 int insn = bfd_getl16 (fragP->fr_opcode + 2);
4522
4523 insn &= 0xffff;
638d3803 4524 if (target_is_430x ())
13761a11
NC		 4525 {
4526 for (i = 0; i < 4 && !hc; i++)
4527 if (msp430x_hcodes[i].op1 == insn)
4528 hc = msp430x_hcodes + i;
4529 }
4530 else
4531 {
4532 for (i = 0; i < 4 && !hc; i++)
4533 if (msp430_hcodes[i].op1 == insn)
4534 hc = &msp430_hcodes[i];
4535 }
b18c562e
NC		 4536 if (!hc || !hc->name)
4537 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4538 __FUNCTION__, (long) insn);
4539 rela = BFD_RELOC_MSP430_10_PCREL;
4540 /* Apply a fix for a first label if necessary.
4541 another fix will be applied to the next word of insn anyway. */
4542 if (hc->tlab == 2)
4543 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
13761a11 4544 fragP->fr_offset, TRUE, rela);
b18c562e
NC		 4545 fragP->fr_fix += 2;
4546 }
4547
4548 break;
4549
4550 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD):
4551 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF):
4552 {
4553 int insn = bfd_getl16 (fragP->fr_opcode + 2);
4554
4555 insn &= 0xffff;
638d3803 4556 if (target_is_430x ())
13761a11
NC		 4557 {
4558 for (i = 0; i < 4 && !hc; i++)
4559 if (msp430x_hcodes[i].op1 == insn)
4560 hc = msp430x_hcodes + i;
4561 }
4562 else
4563 {
4564 for (i = 0; i < 4 && !hc; i++)
4565 if (msp430_hcodes[i].op1 == insn)
4566 hc = & msp430_hcodes[i];
4567 }
b18c562e
NC		 4568 if (!hc || !hc->name)
4569 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4570 __FUNCTION__, (long) insn);
4571 rela = BFD_RELOC_MSP430_RL_PCREL;
4572 where = fragP->fr_literal + fragP->fr_fix;
4573 bfd_putl16 (hc->lop0, where);
4574 bfd_putl16 (hc->lop1, where + 2);
4575 bfd_putl16 (hc->lop2, where + 4);
4576 fragP->fr_fix += 6;
4577 }
4578 break;
4579
4580 default:
33eaf5de 4581 as_fatal (_("internal inconsistency problem in %s: %lx"),
b18c562e
NC		 4582 __FUNCTION__, (long) fragP->fr_subtype);
4583 break;
4584 }
4585
4586 /* Now apply fix. */
4587 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4588 fragP->fr_offset, TRUE, rela);
4589 /* Just fixed 2 bytes. */
4590 fragP->fr_fix += 2;
2469cfa2
NC		 4591}
4592
b18c562e
NC		 4593/* Relax fragment. Mostly stolen from hc11 and mcore
4594 which arches I think I know. */
2469cfa2 4595
b18c562e
NC		 4596long
4597msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP,
4598 long stretch ATTRIBUTE_UNUSED)
2469cfa2 4599{
b18c562e
NC		 4600 long growth;
4601 offsetT aim = 0;
4602 symbolS *symbolP;
4603 const relax_typeS *this_type;
4604 const relax_typeS *start_type;
4605 relax_substateT next_state;
4606 relax_substateT this_state;
4607 const relax_typeS *table = md_relax_table;
4608
4609 /* Nothing to be done if the frag has already max size. */
4610 if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF
4611 || RELAX_STATE (fragP->fr_subtype) == STATE_WORD)
4612 return 0;
4613
4614 if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10)
4615 {
4616 symbolP = fragP->fr_symbol;
4617 if (symbol_resolved_p (symbolP))
4618 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
4619 __FUNCTION__);
4620 /* We know the offset. calculate a distance. */
4621 aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix;
4622 }
4623
77592908
DD		 4624 if (!msp430_enable_relax)
4625 {
4626 /* Relaxation is not enabled. So, make all jump as long ones
13761a11 4627 by setting 'aim' to quite high value. */
77592908
DD		 4628 aim = 0x7fff;
4629 }
38d77545 4630
b18c562e
NC		 4631 this_state = fragP->fr_subtype;
4632 start_type = this_type = table + this_state;
4633
4634 if (aim < 0)
4635 {
4636 /* Look backwards. */
4637 for (next_state = this_type->rlx_more; next_state;)
3e470ab5 4638 if (aim >= this_type->rlx_backward || !this_type->rlx_backward)
b18c562e
NC		 4639 next_state = 0;
4640 else
4641 {
4642 /* Grow to next state. */
4643 this_state = next_state;
4644 this_type = table + this_state;
4645 next_state = this_type->rlx_more;
4646 }
4647 }
4648 else
4649 {
4650 /* Look forwards. */
4651 for (next_state = this_type->rlx_more; next_state;)
3e470ab5 4652 if (aim <= this_type->rlx_forward || !this_type->rlx_forward)
b18c562e
NC		 4653 next_state = 0;
4654 else
4655 {
4656 /* Grow to next state. */
4657 this_state = next_state;
4658 this_type = table + this_state;
4659 next_state = this_type->rlx_more;
4660 }
4661 }
4662
4663 growth = this_type->rlx_length - start_type->rlx_length;
4664 if (growth != 0)
4665 fragP->fr_subtype = this_state;
4666 return growth;
2469cfa2 4667}
13761a11
NC		 4668
4669/* Return FALSE if the fixup in fixp should be left alone and not
4670 adjusted. We return FALSE here so that linker relaxation will
4671 work. */
4672
4673bfd_boolean
4674msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED)
4675{
4676 /* If the symbol is in a non-code section then it should be OK. */
4677 if (fixp->fx_addsy
4678 && ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0))
4679 return TRUE;
38d77545 4680
13761a11
NC		 4681 return FALSE;
4682}
4683
4684/* Set the contents of the .MSP430.attributes section. */
4685
4686void
4687msp430_md_end (void)
4688{
2213f746
NC		 4689 if (check_for_nop)
4690 as_warn ("assembly finished without a possibly needed NOP instruction");
65d7bab5 4691
13761a11 4692 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA,
638d3803 4693 target_is_430x () ? 2 : 1);
13761a11
NC		 4694
4695 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Code_Model,
4696 large_model ? 2 : 1);
4697
4698 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Data_Model,
4699 large_model ? 2 : 1);
4700}
4701
4702/* Returns FALSE if there is a msp430 specific reason why the
4703 subtraction of two same-section symbols cannot be computed by
4704 the assembler. */
4705
4706bfd_boolean
4707msp430_allow_local_subtract (expressionS * left,
4708 expressionS * right,
4709 segT section)
4710{
4711 /* If the symbols are not in a code section then they are OK. */
4712 if ((section->flags & SEC_CODE) == 0)
4713 return TRUE;
4714
4715 if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol))
4716 return TRUE;
4717
4718 if (left->X_add_symbol == right->X_add_symbol)
4719 return TRUE;
4720
4721 /* We have to assume that there may be instructions between the
4722 two symbols and that relaxation may increase the distance between
4723 them. */
4724 return FALSE;
4725}
GDB Binutils - Deliverables
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