Commit | Line | Data |
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252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
b3adc24a | 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
34 | #ifdef TE_PE | |
35 | #include "coff/pe.h" | |
36 | #endif | |
37 | ||
85645aed TG |
38 | #ifdef OBJ_XCOFF |
39 | #include "coff/xcoff.h" | |
40 | #include "libxcoff.h" | |
41 | #endif | |
42 | ||
252b5132 RH |
43 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
44 | ||
45 | /* Tell the main code what the endianness is. */ | |
46 | extern int target_big_endian; | |
47 | ||
48 | /* Whether or not, we've set target_big_endian. */ | |
49 | static int set_target_endian = 0; | |
50 | ||
51 | /* Whether to use user friendly register names. */ | |
52 | #ifndef TARGET_REG_NAMES_P | |
53 | #ifdef TE_PE | |
b34976b6 | 54 | #define TARGET_REG_NAMES_P TRUE |
252b5132 | 55 | #else |
b34976b6 | 56 | #define TARGET_REG_NAMES_P FALSE |
252b5132 RH |
57 | #endif |
58 | #endif | |
59 | ||
0baf16f2 AM |
60 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
61 | HIGHESTA. */ | |
62 | ||
63 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
64 | #define PPC_LO(v) ((v) & 0xffff) | |
65 | ||
66 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
67 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
68 | ||
69 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
70 | the indicated value, compensating for #lo() being treated as a | |
71 | signed number. */ | |
15c1449b | 72 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
73 | |
74 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 75 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
76 | |
77 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
78 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 79 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
80 | |
81 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 82 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
83 | |
84 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
85 | compensating for #lo being treated as a signed number. */ |
86 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 87 | |
f9c6b907 AM |
88 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
89 | ||
90 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
91 | applied to constants. */ | |
92 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 93 | |
b34976b6 | 94 | static bfd_boolean reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 95 | |
98027b10 AM |
96 | static void ppc_macro (char *, const struct powerpc_macro *); |
97 | static void ppc_byte (int); | |
0baf16f2 AM |
98 | |
99 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
100 | static void ppc_tc (int); |
101 | static void ppc_machine (int); | |
0baf16f2 | 102 | #endif |
252b5132 RH |
103 | |
104 | #ifdef OBJ_XCOFF | |
98027b10 AM |
105 | static void ppc_comm (int); |
106 | static void ppc_bb (int); | |
107 | static void ppc_bc (int); | |
108 | static void ppc_bf (int); | |
109 | static void ppc_biei (int); | |
110 | static void ppc_bs (int); | |
111 | static void ppc_eb (int); | |
112 | static void ppc_ec (int); | |
113 | static void ppc_ef (int); | |
114 | static void ppc_es (int); | |
115 | static void ppc_csect (int); | |
85645aed | 116 | static void ppc_dwsect (int); |
98027b10 AM |
117 | static void ppc_change_csect (symbolS *, offsetT); |
118 | static void ppc_function (int); | |
119 | static void ppc_extern (int); | |
120 | static void ppc_lglobl (int); | |
c865e45b | 121 | static void ppc_ref (int); |
98027b10 AM |
122 | static void ppc_section (int); |
123 | static void ppc_named_section (int); | |
124 | static void ppc_stabx (int); | |
125 | static void ppc_rename (int); | |
126 | static void ppc_toc (int); | |
127 | static void ppc_xcoff_cons (int); | |
128 | static void ppc_vbyte (int); | |
252b5132 RH |
129 | #endif |
130 | ||
131 | #ifdef OBJ_ELF | |
98027b10 AM |
132 | static void ppc_elf_rdata (int); |
133 | static void ppc_elf_lcomm (int); | |
6911b7dc | 134 | static void ppc_elf_localentry (int); |
ee67d69a | 135 | static void ppc_elf_abiversion (int); |
005d79fd | 136 | static void ppc_elf_gnu_attribute (int); |
252b5132 RH |
137 | #endif |
138 | ||
139 | #ifdef TE_PE | |
98027b10 AM |
140 | static void ppc_previous (int); |
141 | static void ppc_pdata (int); | |
142 | static void ppc_ydata (int); | |
143 | static void ppc_reldata (int); | |
144 | static void ppc_rdata (int); | |
145 | static void ppc_ualong (int); | |
146 | static void ppc_znop (int); | |
147 | static void ppc_pe_comm (int); | |
148 | static void ppc_pe_section (int); | |
149 | static void ppc_pe_function (int); | |
150 | static void ppc_pe_tocd (int); | |
252b5132 RH |
151 | #endif |
152 | \f | |
153 | /* Generic assembler global variables which must be defined by all | |
154 | targets. */ | |
155 | ||
156 | #ifdef OBJ_ELF | |
157 | /* This string holds the chars that always start a comment. If the | |
158 | pre-processor is disabled, these aren't very useful. The macro | |
159 | tc_comment_chars points to this. We use this, rather than the | |
160 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
161 | static const char ppc_solaris_comment_chars[] = "#!"; | |
162 | static const char ppc_eabi_comment_chars[] = "#"; | |
163 | ||
164 | #ifdef TARGET_SOLARIS_COMMENT | |
165 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
166 | #else | |
167 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
168 | #endif | |
169 | #else | |
170 | const char comment_chars[] = "#"; | |
171 | #endif | |
172 | ||
173 | /* Characters which start a comment at the beginning of a line. */ | |
174 | const char line_comment_chars[] = "#"; | |
175 | ||
176 | /* Characters which may be used to separate multiple commands on a | |
177 | single line. */ | |
178 | const char line_separator_chars[] = ";"; | |
179 | ||
180 | /* Characters which are used to indicate an exponent in a floating | |
181 | point number. */ | |
182 | const char EXP_CHARS[] = "eE"; | |
183 | ||
184 | /* Characters which mean that a number is a floating point constant, | |
185 | as in 0d1.0. */ | |
186 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 187 | |
5e02f92e | 188 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 189 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 190 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
191 | |
192 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
193 | int ppc_cie_data_alignment; | |
783de163 | 194 | |
8fbf7334 JL |
195 | /* The dwarf2 minimum instruction length. */ |
196 | int ppc_dwarf2_line_min_insn_length; | |
197 | ||
cef4f754 AM |
198 | /* More than this number of nops in an alignment op gets a branch |
199 | instead. */ | |
200 | unsigned long nop_limit = 4; | |
201 | ||
783de163 AM |
202 | /* The type of processor we are assembling for. This is one or more |
203 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 204 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 205 | ppc_cpu_t sticky = 0; |
01efc3af | 206 | |
ee67d69a AM |
207 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
208 | unsigned int ppc_abiversion = 0; | |
209 | ||
05f7541e | 210 | #ifdef OBJ_ELF |
01efc3af | 211 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 212 | static enum { |
01efc3af AM |
213 | has_large_toc_reloc = 1, |
214 | has_small_toc_reloc = 2 | |
215 | } toc_reloc_types; | |
05f7541e | 216 | #endif |
bf7279d5 AM |
217 | |
218 | /* Warn on emitting data to code sections. */ | |
219 | int warn_476; | |
0f873fd5 | 220 | uint64_t last_insn; |
bf7279d5 AM |
221 | segT last_seg; |
222 | subsegT last_subseg; | |
252b5132 RH |
223 | \f |
224 | /* The target specific pseudo-ops which we support. */ | |
225 | ||
226 | const pseudo_typeS md_pseudo_table[] = | |
227 | { | |
228 | /* Pseudo-ops which must be overridden. */ | |
229 | { "byte", ppc_byte, 0 }, | |
230 | ||
231 | #ifdef OBJ_XCOFF | |
232 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
233 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
234 | on COFF, and is only implemented for the RS/6000. We just use | |
235 | obj-coff.c, and add what we need here. */ | |
236 | { "comm", ppc_comm, 0 }, | |
237 | { "lcomm", ppc_comm, 1 }, | |
238 | { "bb", ppc_bb, 0 }, | |
239 | { "bc", ppc_bc, 0 }, | |
240 | { "bf", ppc_bf, 0 }, | |
241 | { "bi", ppc_biei, 0 }, | |
242 | { "bs", ppc_bs, 0 }, | |
243 | { "csect", ppc_csect, 0 }, | |
85645aed | 244 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
245 | { "data", ppc_section, 'd' }, |
246 | { "eb", ppc_eb, 0 }, | |
247 | { "ec", ppc_ec, 0 }, | |
248 | { "ef", ppc_ef, 0 }, | |
249 | { "ei", ppc_biei, 1 }, | |
250 | { "es", ppc_es, 0 }, | |
251 | { "extern", ppc_extern, 0 }, | |
252 | { "function", ppc_function, 0 }, | |
253 | { "lglobl", ppc_lglobl, 0 }, | |
c865e45b | 254 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
255 | { "rename", ppc_rename, 0 }, |
256 | { "section", ppc_named_section, 0 }, | |
257 | { "stabx", ppc_stabx, 0 }, | |
258 | { "text", ppc_section, 't' }, | |
259 | { "toc", ppc_toc, 0 }, | |
260 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 261 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
262 | { "word", ppc_xcoff_cons, 1 }, |
263 | { "short", ppc_xcoff_cons, 1 }, | |
264 | { "vbyte", ppc_vbyte, 0 }, | |
265 | #endif | |
266 | ||
267 | #ifdef OBJ_ELF | |
62ebcb5c | 268 | { "llong", cons, 8 }, |
252b5132 RH |
269 | { "rdata", ppc_elf_rdata, 0 }, |
270 | { "rodata", ppc_elf_rdata, 0 }, | |
271 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 272 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 273 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 274 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
275 | #endif |
276 | ||
277 | #ifdef TE_PE | |
99a814a1 | 278 | /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */ |
252b5132 RH |
279 | { "previous", ppc_previous, 0 }, |
280 | { "pdata", ppc_pdata, 0 }, | |
281 | { "ydata", ppc_ydata, 0 }, | |
282 | { "reldata", ppc_reldata, 0 }, | |
283 | { "rdata", ppc_rdata, 0 }, | |
284 | { "ualong", ppc_ualong, 0 }, | |
285 | { "znop", ppc_znop, 0 }, | |
286 | { "comm", ppc_pe_comm, 0 }, | |
287 | { "lcomm", ppc_pe_comm, 1 }, | |
288 | { "section", ppc_pe_section, 0 }, | |
289 | { "function", ppc_pe_function,0 }, | |
290 | { "tocd", ppc_pe_tocd, 0 }, | |
291 | #endif | |
292 | ||
0baf16f2 | 293 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 294 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
295 | { "machine", ppc_machine, 0 }, |
296 | #endif | |
252b5132 RH |
297 | |
298 | { NULL, NULL, 0 } | |
299 | }; | |
300 | ||
301 | \f | |
99a814a1 AM |
302 | /* Predefined register names if -mregnames (or default for Windows NT). |
303 | In general, there are lots of them, in an attempt to be compatible | |
304 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
305 | |
306 | /* Structure to hold information about predefined registers. */ | |
307 | struct pd_reg | |
308 | { | |
e0471c16 | 309 | const char *name; |
7e0de605 AM |
310 | unsigned short value; |
311 | unsigned short flags; | |
252b5132 RH |
312 | }; |
313 | ||
314 | /* List of registers that are pre-defined: | |
315 | ||
316 | Each general register has predefined names of the form: | |
317 | 1. r<reg_num> which has the value <reg_num>. | |
318 | 2. r.<reg_num> which has the value <reg_num>. | |
319 | ||
252b5132 RH |
320 | Each floating point register has predefined names of the form: |
321 | 1. f<reg_num> which has the value <reg_num>. | |
322 | 2. f.<reg_num> which has the value <reg_num>. | |
323 | ||
7a899fff C |
324 | Each vector unit register has predefined names of the form: |
325 | 1. v<reg_num> which has the value <reg_num>. | |
326 | 2. v.<reg_num> which has the value <reg_num>. | |
327 | ||
252b5132 RH |
328 | Each condition register has predefined names of the form: |
329 | 1. cr<reg_num> which has the value <reg_num>. | |
330 | 2. cr.<reg_num> which has the value <reg_num>. | |
331 | ||
332 | There are individual registers as well: | |
333 | sp or r.sp has the value 1 | |
334 | rtoc or r.toc has the value 2 | |
252b5132 RH |
335 | xer has the value 1 |
336 | lr has the value 8 | |
337 | ctr has the value 9 | |
252b5132 RH |
338 | dar has the value 19 |
339 | dsisr has the value 18 | |
340 | dec has the value 22 | |
341 | sdr1 has the value 25 | |
342 | srr0 has the value 26 | |
343 | srr1 has the value 27 | |
344 | ||
81d4177b | 345 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
346 | |
347 | static const struct pd_reg pre_defined_registers[] = | |
348 | { | |
aa3c112f AM |
349 | /* VSX accumulators. */ |
350 | { "a0", 0, PPC_OPERAND_ACC }, | |
351 | { "a1", 1, PPC_OPERAND_ACC }, | |
352 | { "a2", 2, PPC_OPERAND_ACC }, | |
353 | { "a3", 3, PPC_OPERAND_ACC }, | |
354 | { "a4", 4, PPC_OPERAND_ACC }, | |
355 | { "a5", 5, PPC_OPERAND_ACC }, | |
356 | { "a6", 6, PPC_OPERAND_ACC }, | |
357 | { "a7", 7, PPC_OPERAND_ACC }, | |
358 | ||
7e0de605 AM |
359 | /* Condition Registers */ |
360 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
361 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
362 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
363 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
364 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
365 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
366 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
367 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
368 | ||
369 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
370 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
371 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
372 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
373 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
374 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
375 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
376 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
377 | ||
378 | { "ctr", 9, PPC_OPERAND_SPR }, | |
379 | { "dar", 19, PPC_OPERAND_SPR }, | |
380 | { "dec", 22, PPC_OPERAND_SPR }, | |
381 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
382 | ||
383 | /* Floating point registers */ | |
384 | { "f.0", 0, PPC_OPERAND_FPR }, | |
385 | { "f.1", 1, PPC_OPERAND_FPR }, | |
386 | { "f.10", 10, PPC_OPERAND_FPR }, | |
387 | { "f.11", 11, PPC_OPERAND_FPR }, | |
388 | { "f.12", 12, PPC_OPERAND_FPR }, | |
389 | { "f.13", 13, PPC_OPERAND_FPR }, | |
390 | { "f.14", 14, PPC_OPERAND_FPR }, | |
391 | { "f.15", 15, PPC_OPERAND_FPR }, | |
392 | { "f.16", 16, PPC_OPERAND_FPR }, | |
393 | { "f.17", 17, PPC_OPERAND_FPR }, | |
394 | { "f.18", 18, PPC_OPERAND_FPR }, | |
395 | { "f.19", 19, PPC_OPERAND_FPR }, | |
396 | { "f.2", 2, PPC_OPERAND_FPR }, | |
397 | { "f.20", 20, PPC_OPERAND_FPR }, | |
398 | { "f.21", 21, PPC_OPERAND_FPR }, | |
399 | { "f.22", 22, PPC_OPERAND_FPR }, | |
400 | { "f.23", 23, PPC_OPERAND_FPR }, | |
401 | { "f.24", 24, PPC_OPERAND_FPR }, | |
402 | { "f.25", 25, PPC_OPERAND_FPR }, | |
403 | { "f.26", 26, PPC_OPERAND_FPR }, | |
404 | { "f.27", 27, PPC_OPERAND_FPR }, | |
405 | { "f.28", 28, PPC_OPERAND_FPR }, | |
406 | { "f.29", 29, PPC_OPERAND_FPR }, | |
407 | { "f.3", 3, PPC_OPERAND_FPR }, | |
408 | { "f.30", 30, PPC_OPERAND_FPR }, | |
409 | { "f.31", 31, PPC_OPERAND_FPR }, | |
410 | { "f.32", 32, PPC_OPERAND_VSR }, | |
411 | { "f.33", 33, PPC_OPERAND_VSR }, | |
412 | { "f.34", 34, PPC_OPERAND_VSR }, | |
413 | { "f.35", 35, PPC_OPERAND_VSR }, | |
414 | { "f.36", 36, PPC_OPERAND_VSR }, | |
415 | { "f.37", 37, PPC_OPERAND_VSR }, | |
416 | { "f.38", 38, PPC_OPERAND_VSR }, | |
417 | { "f.39", 39, PPC_OPERAND_VSR }, | |
418 | { "f.4", 4, PPC_OPERAND_FPR }, | |
419 | { "f.40", 40, PPC_OPERAND_VSR }, | |
420 | { "f.41", 41, PPC_OPERAND_VSR }, | |
421 | { "f.42", 42, PPC_OPERAND_VSR }, | |
422 | { "f.43", 43, PPC_OPERAND_VSR }, | |
423 | { "f.44", 44, PPC_OPERAND_VSR }, | |
424 | { "f.45", 45, PPC_OPERAND_VSR }, | |
425 | { "f.46", 46, PPC_OPERAND_VSR }, | |
426 | { "f.47", 47, PPC_OPERAND_VSR }, | |
427 | { "f.48", 48, PPC_OPERAND_VSR }, | |
428 | { "f.49", 49, PPC_OPERAND_VSR }, | |
429 | { "f.5", 5, PPC_OPERAND_FPR }, | |
430 | { "f.50", 50, PPC_OPERAND_VSR }, | |
431 | { "f.51", 51, PPC_OPERAND_VSR }, | |
432 | { "f.52", 52, PPC_OPERAND_VSR }, | |
433 | { "f.53", 53, PPC_OPERAND_VSR }, | |
434 | { "f.54", 54, PPC_OPERAND_VSR }, | |
435 | { "f.55", 55, PPC_OPERAND_VSR }, | |
436 | { "f.56", 56, PPC_OPERAND_VSR }, | |
437 | { "f.57", 57, PPC_OPERAND_VSR }, | |
438 | { "f.58", 58, PPC_OPERAND_VSR }, | |
439 | { "f.59", 59, PPC_OPERAND_VSR }, | |
440 | { "f.6", 6, PPC_OPERAND_FPR }, | |
441 | { "f.60", 60, PPC_OPERAND_VSR }, | |
442 | { "f.61", 61, PPC_OPERAND_VSR }, | |
443 | { "f.62", 62, PPC_OPERAND_VSR }, | |
444 | { "f.63", 63, PPC_OPERAND_VSR }, | |
445 | { "f.7", 7, PPC_OPERAND_FPR }, | |
446 | { "f.8", 8, PPC_OPERAND_FPR }, | |
447 | { "f.9", 9, PPC_OPERAND_FPR }, | |
448 | ||
449 | { "f0", 0, PPC_OPERAND_FPR }, | |
450 | { "f1", 1, PPC_OPERAND_FPR }, | |
451 | { "f10", 10, PPC_OPERAND_FPR }, | |
452 | { "f11", 11, PPC_OPERAND_FPR }, | |
453 | { "f12", 12, PPC_OPERAND_FPR }, | |
454 | { "f13", 13, PPC_OPERAND_FPR }, | |
455 | { "f14", 14, PPC_OPERAND_FPR }, | |
456 | { "f15", 15, PPC_OPERAND_FPR }, | |
457 | { "f16", 16, PPC_OPERAND_FPR }, | |
458 | { "f17", 17, PPC_OPERAND_FPR }, | |
459 | { "f18", 18, PPC_OPERAND_FPR }, | |
460 | { "f19", 19, PPC_OPERAND_FPR }, | |
461 | { "f2", 2, PPC_OPERAND_FPR }, | |
462 | { "f20", 20, PPC_OPERAND_FPR }, | |
463 | { "f21", 21, PPC_OPERAND_FPR }, | |
464 | { "f22", 22, PPC_OPERAND_FPR }, | |
465 | { "f23", 23, PPC_OPERAND_FPR }, | |
466 | { "f24", 24, PPC_OPERAND_FPR }, | |
467 | { "f25", 25, PPC_OPERAND_FPR }, | |
468 | { "f26", 26, PPC_OPERAND_FPR }, | |
469 | { "f27", 27, PPC_OPERAND_FPR }, | |
470 | { "f28", 28, PPC_OPERAND_FPR }, | |
471 | { "f29", 29, PPC_OPERAND_FPR }, | |
472 | { "f3", 3, PPC_OPERAND_FPR }, | |
473 | { "f30", 30, PPC_OPERAND_FPR }, | |
474 | { "f31", 31, PPC_OPERAND_FPR }, | |
475 | { "f32", 32, PPC_OPERAND_VSR }, | |
476 | { "f33", 33, PPC_OPERAND_VSR }, | |
477 | { "f34", 34, PPC_OPERAND_VSR }, | |
478 | { "f35", 35, PPC_OPERAND_VSR }, | |
479 | { "f36", 36, PPC_OPERAND_VSR }, | |
480 | { "f37", 37, PPC_OPERAND_VSR }, | |
481 | { "f38", 38, PPC_OPERAND_VSR }, | |
482 | { "f39", 39, PPC_OPERAND_VSR }, | |
483 | { "f4", 4, PPC_OPERAND_FPR }, | |
484 | { "f40", 40, PPC_OPERAND_VSR }, | |
485 | { "f41", 41, PPC_OPERAND_VSR }, | |
486 | { "f42", 42, PPC_OPERAND_VSR }, | |
487 | { "f43", 43, PPC_OPERAND_VSR }, | |
488 | { "f44", 44, PPC_OPERAND_VSR }, | |
489 | { "f45", 45, PPC_OPERAND_VSR }, | |
490 | { "f46", 46, PPC_OPERAND_VSR }, | |
491 | { "f47", 47, PPC_OPERAND_VSR }, | |
492 | { "f48", 48, PPC_OPERAND_VSR }, | |
493 | { "f49", 49, PPC_OPERAND_VSR }, | |
494 | { "f5", 5, PPC_OPERAND_FPR }, | |
495 | { "f50", 50, PPC_OPERAND_VSR }, | |
496 | { "f51", 51, PPC_OPERAND_VSR }, | |
497 | { "f52", 52, PPC_OPERAND_VSR }, | |
498 | { "f53", 53, PPC_OPERAND_VSR }, | |
499 | { "f54", 54, PPC_OPERAND_VSR }, | |
500 | { "f55", 55, PPC_OPERAND_VSR }, | |
501 | { "f56", 56, PPC_OPERAND_VSR }, | |
502 | { "f57", 57, PPC_OPERAND_VSR }, | |
503 | { "f58", 58, PPC_OPERAND_VSR }, | |
504 | { "f59", 59, PPC_OPERAND_VSR }, | |
505 | { "f6", 6, PPC_OPERAND_FPR }, | |
506 | { "f60", 60, PPC_OPERAND_VSR }, | |
507 | { "f61", 61, PPC_OPERAND_VSR }, | |
508 | { "f62", 62, PPC_OPERAND_VSR }, | |
509 | { "f63", 63, PPC_OPERAND_VSR }, | |
510 | { "f7", 7, PPC_OPERAND_FPR }, | |
511 | { "f8", 8, PPC_OPERAND_FPR }, | |
512 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 513 | |
c3d65c1c | 514 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
515 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
516 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
517 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
518 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
519 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
520 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
521 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
522 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
523 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
524 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
525 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
526 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
527 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
528 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
529 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
530 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
531 | ||
532 | { "lr", 8, PPC_OPERAND_SPR }, | |
533 | ||
534 | /* General Purpose Registers */ | |
535 | { "r.0", 0, PPC_OPERAND_GPR }, | |
536 | { "r.1", 1, PPC_OPERAND_GPR }, | |
537 | { "r.10", 10, PPC_OPERAND_GPR }, | |
538 | { "r.11", 11, PPC_OPERAND_GPR }, | |
539 | { "r.12", 12, PPC_OPERAND_GPR }, | |
540 | { "r.13", 13, PPC_OPERAND_GPR }, | |
541 | { "r.14", 14, PPC_OPERAND_GPR }, | |
542 | { "r.15", 15, PPC_OPERAND_GPR }, | |
543 | { "r.16", 16, PPC_OPERAND_GPR }, | |
544 | { "r.17", 17, PPC_OPERAND_GPR }, | |
545 | { "r.18", 18, PPC_OPERAND_GPR }, | |
546 | { "r.19", 19, PPC_OPERAND_GPR }, | |
547 | { "r.2", 2, PPC_OPERAND_GPR }, | |
548 | { "r.20", 20, PPC_OPERAND_GPR }, | |
549 | { "r.21", 21, PPC_OPERAND_GPR }, | |
550 | { "r.22", 22, PPC_OPERAND_GPR }, | |
551 | { "r.23", 23, PPC_OPERAND_GPR }, | |
552 | { "r.24", 24, PPC_OPERAND_GPR }, | |
553 | { "r.25", 25, PPC_OPERAND_GPR }, | |
554 | { "r.26", 26, PPC_OPERAND_GPR }, | |
555 | { "r.27", 27, PPC_OPERAND_GPR }, | |
556 | { "r.28", 28, PPC_OPERAND_GPR }, | |
557 | { "r.29", 29, PPC_OPERAND_GPR }, | |
558 | { "r.3", 3, PPC_OPERAND_GPR }, | |
559 | { "r.30", 30, PPC_OPERAND_GPR }, | |
560 | { "r.31", 31, PPC_OPERAND_GPR }, | |
561 | { "r.4", 4, PPC_OPERAND_GPR }, | |
562 | { "r.5", 5, PPC_OPERAND_GPR }, | |
563 | { "r.6", 6, PPC_OPERAND_GPR }, | |
564 | { "r.7", 7, PPC_OPERAND_GPR }, | |
565 | { "r.8", 8, PPC_OPERAND_GPR }, | |
566 | { "r.9", 9, PPC_OPERAND_GPR }, | |
567 | ||
568 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
569 | ||
570 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
571 | ||
572 | { "r0", 0, PPC_OPERAND_GPR }, | |
573 | { "r1", 1, PPC_OPERAND_GPR }, | |
574 | { "r10", 10, PPC_OPERAND_GPR }, | |
575 | { "r11", 11, PPC_OPERAND_GPR }, | |
576 | { "r12", 12, PPC_OPERAND_GPR }, | |
577 | { "r13", 13, PPC_OPERAND_GPR }, | |
578 | { "r14", 14, PPC_OPERAND_GPR }, | |
579 | { "r15", 15, PPC_OPERAND_GPR }, | |
580 | { "r16", 16, PPC_OPERAND_GPR }, | |
581 | { "r17", 17, PPC_OPERAND_GPR }, | |
582 | { "r18", 18, PPC_OPERAND_GPR }, | |
583 | { "r19", 19, PPC_OPERAND_GPR }, | |
584 | { "r2", 2, PPC_OPERAND_GPR }, | |
585 | { "r20", 20, PPC_OPERAND_GPR }, | |
586 | { "r21", 21, PPC_OPERAND_GPR }, | |
587 | { "r22", 22, PPC_OPERAND_GPR }, | |
588 | { "r23", 23, PPC_OPERAND_GPR }, | |
589 | { "r24", 24, PPC_OPERAND_GPR }, | |
590 | { "r25", 25, PPC_OPERAND_GPR }, | |
591 | { "r26", 26, PPC_OPERAND_GPR }, | |
592 | { "r27", 27, PPC_OPERAND_GPR }, | |
593 | { "r28", 28, PPC_OPERAND_GPR }, | |
594 | { "r29", 29, PPC_OPERAND_GPR }, | |
595 | { "r3", 3, PPC_OPERAND_GPR }, | |
596 | { "r30", 30, PPC_OPERAND_GPR }, | |
597 | { "r31", 31, PPC_OPERAND_GPR }, | |
598 | { "r4", 4, PPC_OPERAND_GPR }, | |
599 | { "r5", 5, PPC_OPERAND_GPR }, | |
600 | { "r6", 6, PPC_OPERAND_GPR }, | |
601 | { "r7", 7, PPC_OPERAND_GPR }, | |
602 | { "r8", 8, PPC_OPERAND_GPR }, | |
603 | { "r9", 9, PPC_OPERAND_GPR }, | |
604 | ||
605 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
606 | ||
607 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
608 | ||
609 | { "sp", 1, PPC_OPERAND_GPR }, | |
610 | ||
611 | { "srr0", 26, PPC_OPERAND_SPR }, | |
612 | { "srr1", 27, PPC_OPERAND_SPR }, | |
613 | ||
614 | /* Vector (Altivec/VMX) registers */ | |
615 | { "v.0", 0, PPC_OPERAND_VR }, | |
616 | { "v.1", 1, PPC_OPERAND_VR }, | |
617 | { "v.10", 10, PPC_OPERAND_VR }, | |
618 | { "v.11", 11, PPC_OPERAND_VR }, | |
619 | { "v.12", 12, PPC_OPERAND_VR }, | |
620 | { "v.13", 13, PPC_OPERAND_VR }, | |
621 | { "v.14", 14, PPC_OPERAND_VR }, | |
622 | { "v.15", 15, PPC_OPERAND_VR }, | |
623 | { "v.16", 16, PPC_OPERAND_VR }, | |
624 | { "v.17", 17, PPC_OPERAND_VR }, | |
625 | { "v.18", 18, PPC_OPERAND_VR }, | |
626 | { "v.19", 19, PPC_OPERAND_VR }, | |
627 | { "v.2", 2, PPC_OPERAND_VR }, | |
628 | { "v.20", 20, PPC_OPERAND_VR }, | |
629 | { "v.21", 21, PPC_OPERAND_VR }, | |
630 | { "v.22", 22, PPC_OPERAND_VR }, | |
631 | { "v.23", 23, PPC_OPERAND_VR }, | |
632 | { "v.24", 24, PPC_OPERAND_VR }, | |
633 | { "v.25", 25, PPC_OPERAND_VR }, | |
634 | { "v.26", 26, PPC_OPERAND_VR }, | |
635 | { "v.27", 27, PPC_OPERAND_VR }, | |
636 | { "v.28", 28, PPC_OPERAND_VR }, | |
637 | { "v.29", 29, PPC_OPERAND_VR }, | |
638 | { "v.3", 3, PPC_OPERAND_VR }, | |
639 | { "v.30", 30, PPC_OPERAND_VR }, | |
640 | { "v.31", 31, PPC_OPERAND_VR }, | |
641 | { "v.4", 4, PPC_OPERAND_VR }, | |
642 | { "v.5", 5, PPC_OPERAND_VR }, | |
643 | { "v.6", 6, PPC_OPERAND_VR }, | |
644 | { "v.7", 7, PPC_OPERAND_VR }, | |
645 | { "v.8", 8, PPC_OPERAND_VR }, | |
646 | { "v.9", 9, PPC_OPERAND_VR }, | |
647 | ||
648 | { "v0", 0, PPC_OPERAND_VR }, | |
649 | { "v1", 1, PPC_OPERAND_VR }, | |
650 | { "v10", 10, PPC_OPERAND_VR }, | |
651 | { "v11", 11, PPC_OPERAND_VR }, | |
652 | { "v12", 12, PPC_OPERAND_VR }, | |
653 | { "v13", 13, PPC_OPERAND_VR }, | |
654 | { "v14", 14, PPC_OPERAND_VR }, | |
655 | { "v15", 15, PPC_OPERAND_VR }, | |
656 | { "v16", 16, PPC_OPERAND_VR }, | |
657 | { "v17", 17, PPC_OPERAND_VR }, | |
658 | { "v18", 18, PPC_OPERAND_VR }, | |
659 | { "v19", 19, PPC_OPERAND_VR }, | |
660 | { "v2", 2, PPC_OPERAND_VR }, | |
661 | { "v20", 20, PPC_OPERAND_VR }, | |
662 | { "v21", 21, PPC_OPERAND_VR }, | |
663 | { "v22", 22, PPC_OPERAND_VR }, | |
664 | { "v23", 23, PPC_OPERAND_VR }, | |
665 | { "v24", 24, PPC_OPERAND_VR }, | |
666 | { "v25", 25, PPC_OPERAND_VR }, | |
667 | { "v26", 26, PPC_OPERAND_VR }, | |
668 | { "v27", 27, PPC_OPERAND_VR }, | |
669 | { "v28", 28, PPC_OPERAND_VR }, | |
670 | { "v29", 29, PPC_OPERAND_VR }, | |
671 | { "v3", 3, PPC_OPERAND_VR }, | |
672 | { "v30", 30, PPC_OPERAND_VR }, | |
673 | { "v31", 31, PPC_OPERAND_VR }, | |
674 | { "v4", 4, PPC_OPERAND_VR }, | |
675 | { "v5", 5, PPC_OPERAND_VR }, | |
676 | { "v6", 6, PPC_OPERAND_VR }, | |
677 | { "v7", 7, PPC_OPERAND_VR }, | |
678 | { "v8", 8, PPC_OPERAND_VR }, | |
679 | { "v9", 9, PPC_OPERAND_VR }, | |
680 | ||
681 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
682 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
683 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
684 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
685 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
686 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
687 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
688 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
689 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
690 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
691 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
692 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
693 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
694 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
695 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
696 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
697 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
698 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
699 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
700 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
701 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
702 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
703 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
704 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
705 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
706 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
707 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
708 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
709 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
710 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
711 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
712 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
713 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
714 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
715 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
716 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
717 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
718 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
719 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
720 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
721 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
722 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
723 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
724 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
725 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
726 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
727 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
728 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
729 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
730 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
731 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
732 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
733 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
734 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
735 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
736 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
737 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
738 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
739 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
740 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
741 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
742 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
743 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
744 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
745 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
746 | ||
747 | { "vs0", 0, PPC_OPERAND_VSR }, | |
748 | { "vs1", 1, PPC_OPERAND_VSR }, | |
749 | { "vs10", 10, PPC_OPERAND_VSR }, | |
750 | { "vs11", 11, PPC_OPERAND_VSR }, | |
751 | { "vs12", 12, PPC_OPERAND_VSR }, | |
752 | { "vs13", 13, PPC_OPERAND_VSR }, | |
753 | { "vs14", 14, PPC_OPERAND_VSR }, | |
754 | { "vs15", 15, PPC_OPERAND_VSR }, | |
755 | { "vs16", 16, PPC_OPERAND_VSR }, | |
756 | { "vs17", 17, PPC_OPERAND_VSR }, | |
757 | { "vs18", 18, PPC_OPERAND_VSR }, | |
758 | { "vs19", 19, PPC_OPERAND_VSR }, | |
759 | { "vs2", 2, PPC_OPERAND_VSR }, | |
760 | { "vs20", 20, PPC_OPERAND_VSR }, | |
761 | { "vs21", 21, PPC_OPERAND_VSR }, | |
762 | { "vs22", 22, PPC_OPERAND_VSR }, | |
763 | { "vs23", 23, PPC_OPERAND_VSR }, | |
764 | { "vs24", 24, PPC_OPERAND_VSR }, | |
765 | { "vs25", 25, PPC_OPERAND_VSR }, | |
766 | { "vs26", 26, PPC_OPERAND_VSR }, | |
767 | { "vs27", 27, PPC_OPERAND_VSR }, | |
768 | { "vs28", 28, PPC_OPERAND_VSR }, | |
769 | { "vs29", 29, PPC_OPERAND_VSR }, | |
770 | { "vs3", 3, PPC_OPERAND_VSR }, | |
771 | { "vs30", 30, PPC_OPERAND_VSR }, | |
772 | { "vs31", 31, PPC_OPERAND_VSR }, | |
773 | { "vs32", 32, PPC_OPERAND_VSR }, | |
774 | { "vs33", 33, PPC_OPERAND_VSR }, | |
775 | { "vs34", 34, PPC_OPERAND_VSR }, | |
776 | { "vs35", 35, PPC_OPERAND_VSR }, | |
777 | { "vs36", 36, PPC_OPERAND_VSR }, | |
778 | { "vs37", 37, PPC_OPERAND_VSR }, | |
779 | { "vs38", 38, PPC_OPERAND_VSR }, | |
780 | { "vs39", 39, PPC_OPERAND_VSR }, | |
781 | { "vs4", 4, PPC_OPERAND_VSR }, | |
782 | { "vs40", 40, PPC_OPERAND_VSR }, | |
783 | { "vs41", 41, PPC_OPERAND_VSR }, | |
784 | { "vs42", 42, PPC_OPERAND_VSR }, | |
785 | { "vs43", 43, PPC_OPERAND_VSR }, | |
786 | { "vs44", 44, PPC_OPERAND_VSR }, | |
787 | { "vs45", 45, PPC_OPERAND_VSR }, | |
788 | { "vs46", 46, PPC_OPERAND_VSR }, | |
789 | { "vs47", 47, PPC_OPERAND_VSR }, | |
790 | { "vs48", 48, PPC_OPERAND_VSR }, | |
791 | { "vs49", 49, PPC_OPERAND_VSR }, | |
792 | { "vs5", 5, PPC_OPERAND_VSR }, | |
793 | { "vs50", 50, PPC_OPERAND_VSR }, | |
794 | { "vs51", 51, PPC_OPERAND_VSR }, | |
795 | { "vs52", 52, PPC_OPERAND_VSR }, | |
796 | { "vs53", 53, PPC_OPERAND_VSR }, | |
797 | { "vs54", 54, PPC_OPERAND_VSR }, | |
798 | { "vs55", 55, PPC_OPERAND_VSR }, | |
799 | { "vs56", 56, PPC_OPERAND_VSR }, | |
800 | { "vs57", 57, PPC_OPERAND_VSR }, | |
801 | { "vs58", 58, PPC_OPERAND_VSR }, | |
802 | { "vs59", 59, PPC_OPERAND_VSR }, | |
803 | { "vs6", 6, PPC_OPERAND_VSR }, | |
804 | { "vs60", 60, PPC_OPERAND_VSR }, | |
805 | { "vs61", 61, PPC_OPERAND_VSR }, | |
806 | { "vs62", 62, PPC_OPERAND_VSR }, | |
807 | { "vs63", 63, PPC_OPERAND_VSR }, | |
808 | { "vs7", 7, PPC_OPERAND_VSR }, | |
809 | { "vs8", 8, PPC_OPERAND_VSR }, | |
810 | { "vs9", 9, PPC_OPERAND_VSR }, | |
811 | ||
812 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
813 | }; |
814 | ||
bc805888 | 815 | #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) |
252b5132 RH |
816 | |
817 | /* Given NAME, find the register number associated with that name, return | |
818 | the integer value associated with the given name or -1 on failure. */ | |
819 | ||
7e0de605 | 820 | static const struct pd_reg * |
98027b10 | 821 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
822 | { |
823 | int middle, low, high; | |
824 | int cmp; | |
825 | ||
826 | low = 0; | |
827 | high = regcount - 1; | |
828 | ||
829 | do | |
830 | { | |
831 | middle = (low + high) / 2; | |
832 | cmp = strcasecmp (name, regs[middle].name); | |
833 | if (cmp < 0) | |
834 | high = middle - 1; | |
835 | else if (cmp > 0) | |
836 | low = middle + 1; | |
837 | else | |
7e0de605 | 838 | return ®s[middle]; |
252b5132 RH |
839 | } |
840 | while (low <= high); | |
841 | ||
7e0de605 | 842 | return NULL; |
252b5132 RH |
843 | } |
844 | ||
845 | /* | |
99a814a1 | 846 | * Summary of register_name. |
252b5132 RH |
847 | * |
848 | * in: Input_line_pointer points to 1st char of operand. | |
849 | * | |
850 | * out: A expressionS. | |
851 | * The operand may have been a register: in this case, X_op == O_register, | |
852 | * X_add_number is set to the register number, and truth is returned. | |
853 | * Input_line_pointer->(next non-blank) char after operand, or is in its | |
854 | * original state. | |
855 | */ | |
856 | ||
b34976b6 | 857 | static bfd_boolean |
98027b10 | 858 | register_name (expressionS *expressionP) |
252b5132 | 859 | { |
7e0de605 | 860 | const struct pd_reg *reg; |
252b5132 RH |
861 | char *name; |
862 | char *start; | |
863 | char c; | |
864 | ||
99a814a1 | 865 | /* Find the spelling of the operand. */ |
252b5132 | 866 | start = name = input_line_pointer; |
3882b010 | 867 | if (name[0] == '%' && ISALPHA (name[1])) |
252b5132 RH |
868 | name = ++input_line_pointer; |
869 | ||
3882b010 | 870 | else if (!reg_names_p || !ISALPHA (name[0])) |
b34976b6 | 871 | return FALSE; |
252b5132 | 872 | |
d02603dc | 873 | c = get_symbol_name (&name); |
7e0de605 | 874 | reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); |
252b5132 | 875 | |
468cced8 AM |
876 | /* Put back the delimiting char. */ |
877 | *input_line_pointer = c; | |
878 | ||
99a814a1 | 879 | /* Look to see if it's in the register table. */ |
7e0de605 | 880 | if (reg != NULL) |
252b5132 RH |
881 | { |
882 | expressionP->X_op = O_register; | |
7e0de605 AM |
883 | expressionP->X_add_number = reg->value; |
884 | expressionP->X_md = reg->flags; | |
81d4177b | 885 | |
99a814a1 | 886 | /* Make the rest nice. */ |
252b5132 RH |
887 | expressionP->X_add_symbol = NULL; |
888 | expressionP->X_op_symbol = NULL; | |
b34976b6 | 889 | return TRUE; |
252b5132 | 890 | } |
468cced8 AM |
891 | |
892 | /* Reset the line as if we had not done anything. */ | |
893 | input_line_pointer = start; | |
b34976b6 | 894 | return FALSE; |
252b5132 RH |
895 | } |
896 | \f | |
897 | /* This function is called for each symbol seen in an expression. It | |
898 | handles the special parsing which PowerPC assemblers are supposed | |
899 | to use for condition codes. */ | |
900 | ||
901 | /* Whether to do the special parsing. */ | |
b34976b6 | 902 | static bfd_boolean cr_operand; |
252b5132 RH |
903 | |
904 | /* Names to recognize in a condition code. This table is sorted. */ | |
905 | static const struct pd_reg cr_names[] = | |
906 | { | |
7e0de605 AM |
907 | { "cr0", 0, PPC_OPERAND_CR_REG }, |
908 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
909 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
910 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
911 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
912 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
913 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
914 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
915 | { "eq", 2, PPC_OPERAND_CR_BIT }, | |
916 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
917 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
918 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
919 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
920 | }; |
921 | ||
922 | /* Parsing function. This returns non-zero if it recognized an | |
923 | expression. */ | |
924 | ||
925 | int | |
91d6fa6a | 926 | ppc_parse_name (const char *name, expressionS *exp) |
252b5132 | 927 | { |
7e0de605 | 928 | const struct pd_reg *reg; |
252b5132 RH |
929 | |
930 | if (! cr_operand) | |
931 | return 0; | |
932 | ||
13abbae3 AM |
933 | if (*name == '%') |
934 | ++name; | |
7e0de605 | 935 | reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0], |
252b5132 | 936 | name); |
7e0de605 | 937 | if (reg == NULL) |
252b5132 RH |
938 | return 0; |
939 | ||
7e0de605 AM |
940 | exp->X_op = O_register; |
941 | exp->X_add_number = reg->value; | |
942 | exp->X_md = reg->flags; | |
252b5132 RH |
943 | |
944 | return 1; | |
945 | } | |
7e0de605 AM |
946 | |
947 | /* Propagate X_md and check register expressions. This is to support | |
948 | condition codes like 4*cr5+eq. */ | |
949 | ||
950 | int | |
951 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
952 | { | |
953 | /* Accept 4*cr<n> and cr<n>*4. */ | |
954 | if (op == O_multiply | |
955 | && ((right->X_op == O_register | |
956 | && right->X_md == PPC_OPERAND_CR_REG | |
957 | && left->X_op == O_constant | |
958 | && left->X_add_number == 4) | |
959 | || (left->X_op == O_register | |
960 | && left->X_md == PPC_OPERAND_CR_REG | |
961 | && right->X_op == O_constant | |
962 | && right->X_add_number == 4))) | |
963 | { | |
964 | left->X_op = O_register; | |
965 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
966 | left->X_add_number *= right->X_add_number; | |
967 | return 1; | |
968 | } | |
969 | ||
970 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
971 | if (right->X_op == O_register | |
972 | && left->X_op == O_register | |
973 | && op == O_add | |
974 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
975 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
976 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
977 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
978 | { | |
979 | left->X_md = PPC_OPERAND_CR_BIT; | |
980 | right->X_op = O_constant; | |
981 | return 0; | |
982 | } | |
983 | ||
984 | /* Accept reg +/- constant. */ | |
985 | if (left->X_op == O_register | |
986 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 987 | as_warn (_("invalid register expression")); |
7e0de605 AM |
988 | |
989 | /* Accept constant + reg. */ | |
990 | if (right->X_op == O_register) | |
991 | { | |
992 | if (op == O_add && left->X_op == O_constant) | |
993 | left->X_md = right->X_md; | |
994 | else | |
ece5dcc1 | 995 | as_warn (_("invalid register expression")); |
7e0de605 AM |
996 | } |
997 | ||
998 | return 0; | |
999 | } | |
252b5132 RH |
1000 | \f |
1001 | /* Local variables. */ | |
1002 | ||
2b3c4602 AM |
1003 | /* Whether to target xcoff64/elf64. */ |
1004 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 1005 | |
252b5132 RH |
1006 | /* Opcode hash table. */ |
1007 | static struct hash_control *ppc_hash; | |
1008 | ||
1009 | /* Macro hash table. */ | |
1010 | static struct hash_control *ppc_macro_hash; | |
1011 | ||
1012 | #ifdef OBJ_ELF | |
99a814a1 | 1013 | /* What type of shared library support to use. */ |
5d6f4f16 | 1014 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 1015 | |
99a814a1 | 1016 | /* Flags to set in the elf header. */ |
252b5132 RH |
1017 | static flagword ppc_flags = 0; |
1018 | ||
1019 | /* Whether this is Solaris or not. */ | |
1020 | #ifdef TARGET_SOLARIS_COMMENT | |
b34976b6 | 1021 | #define SOLARIS_P TRUE |
252b5132 | 1022 | #else |
b34976b6 | 1023 | #define SOLARIS_P FALSE |
252b5132 RH |
1024 | #endif |
1025 | ||
b34976b6 | 1026 | static bfd_boolean msolaris = SOLARIS_P; |
252b5132 RH |
1027 | #endif |
1028 | ||
1029 | #ifdef OBJ_XCOFF | |
1030 | ||
1031 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
1032 | using a bunch of different sections. These assembler sections, | |
1033 | however, are all encompassed within the .text or .data sections of | |
1034 | the final output file. We handle this by using different | |
1035 | subsegments within these main segments. */ | |
1036 | ||
1037 | /* Next subsegment to allocate within the .text segment. */ | |
1038 | static subsegT ppc_text_subsegment = 2; | |
1039 | ||
1040 | /* Linked list of csects in the text section. */ | |
1041 | static symbolS *ppc_text_csects; | |
1042 | ||
1043 | /* Next subsegment to allocate within the .data segment. */ | |
1044 | static subsegT ppc_data_subsegment = 2; | |
1045 | ||
1046 | /* Linked list of csects in the data section. */ | |
1047 | static symbolS *ppc_data_csects; | |
1048 | ||
1049 | /* The current csect. */ | |
1050 | static symbolS *ppc_current_csect; | |
1051 | ||
1052 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1053 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1054 | A special relocation is used when accessing TOC entries. We handle | |
1055 | the TOC as a subsegment within the .data segment. We set it up if | |
1056 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1057 | static symbolS *ppc_toc_csect; | |
1058 | ||
1059 | /* The first frag in the TOC subsegment. */ | |
1060 | static fragS *ppc_toc_frag; | |
1061 | ||
1062 | /* The first frag in the first subsegment after the TOC in the .data | |
1063 | segment. NULL if there are no subsegments after the TOC. */ | |
1064 | static fragS *ppc_after_toc_frag; | |
1065 | ||
1066 | /* The current static block. */ | |
1067 | static symbolS *ppc_current_block; | |
1068 | ||
1069 | /* The COFF debugging section; set by md_begin. This is not the | |
1070 | .debug section, but is instead the secret BFD section which will | |
1071 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1072 | static asection *ppc_coff_debug_section; | |
1073 | ||
85645aed TG |
1074 | /* Structure to set the length field of the dwarf sections. */ |
1075 | struct dw_subsection { | |
1076 | /* Subsections are simply linked. */ | |
1077 | struct dw_subsection *link; | |
1078 | ||
1079 | /* The subsection number. */ | |
1080 | subsegT subseg; | |
1081 | ||
1082 | /* Expression to compute the length of the section. */ | |
1083 | expressionS end_exp; | |
1084 | }; | |
1085 | ||
1086 | static struct dw_section { | |
1087 | /* Corresponding section. */ | |
1088 | segT sect; | |
1089 | ||
1090 | /* Simply linked list of subsections with a label. */ | |
1091 | struct dw_subsection *list_subseg; | |
1092 | ||
1093 | /* The anonymous subsection. */ | |
1094 | struct dw_subsection *anon_subseg; | |
1095 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1096 | #endif /* OBJ_XCOFF */ |
1097 | ||
1098 | #ifdef TE_PE | |
1099 | ||
1100 | /* Various sections that we need for PE coff support. */ | |
1101 | static segT ydata_section; | |
1102 | static segT pdata_section; | |
1103 | static segT reldata_section; | |
1104 | static segT rdata_section; | |
1105 | static segT tocdata_section; | |
1106 | ||
81d4177b | 1107 | /* The current section and the previous section. See ppc_previous. */ |
252b5132 RH |
1108 | static segT ppc_previous_section; |
1109 | static segT ppc_current_section; | |
1110 | ||
1111 | #endif /* TE_PE */ | |
1112 | ||
1113 | #ifdef OBJ_ELF | |
1114 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1115 | unsigned long *ppc_apuinfo_list; |
1116 | unsigned int ppc_apuinfo_num; | |
1117 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1118 | #endif /* OBJ_ELF */ |
1119 | \f | |
1120 | #ifdef OBJ_ELF | |
15c1449b | 1121 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1122 | #else |
15c1449b | 1123 | const char *const md_shortopts = "um:"; |
252b5132 | 1124 | #endif |
cef4f754 | 1125 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1126 | const struct option md_longopts[] = { |
cef4f754 | 1127 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1128 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1129 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1130 | {NULL, no_argument, NULL, 0} |
1131 | }; | |
15c1449b | 1132 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1133 | |
1134 | int | |
17b9d67d | 1135 | md_parse_option (int c, const char *arg) |
252b5132 | 1136 | { |
69fe9ce5 AM |
1137 | ppc_cpu_t new_cpu; |
1138 | ||
252b5132 RH |
1139 | switch (c) |
1140 | { | |
1141 | case 'u': | |
1142 | /* -u means that any undefined symbols should be treated as | |
1143 | external, which is the default for gas anyhow. */ | |
1144 | break; | |
1145 | ||
1146 | #ifdef OBJ_ELF | |
1147 | case 'l': | |
1148 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1149 | sake, recognize -be also. */ |
252b5132 RH |
1150 | if (strcmp (arg, "e") == 0) |
1151 | { | |
1152 | target_big_endian = 0; | |
1153 | set_target_endian = 1; | |
b9c361e0 | 1154 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1155 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1156 | } |
1157 | else | |
1158 | return 0; | |
1159 | ||
1160 | break; | |
1161 | ||
1162 | case 'b': | |
1163 | if (strcmp (arg, "e") == 0) | |
1164 | { | |
1165 | target_big_endian = 1; | |
1166 | set_target_endian = 1; | |
1167 | } | |
1168 | else | |
1169 | return 0; | |
1170 | ||
1171 | break; | |
1172 | ||
1173 | case 'K': | |
99a814a1 | 1174 | /* Recognize -K PIC. */ |
252b5132 RH |
1175 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1176 | { | |
1177 | shlib = SHLIB_PIC; | |
1178 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1179 | } | |
1180 | else | |
1181 | return 0; | |
1182 | ||
1183 | break; | |
1184 | #endif | |
1185 | ||
7f6d05e8 CP |
1186 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1187 | case 'a': | |
1188 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1189 | { |
1190 | #ifdef BFD64 | |
1191 | ppc_obj64 = 1; | |
d6ed37ed AM |
1192 | if (ppc_cpu & PPC_OPCODE_VLE) |
1193 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1194 | #else |
1195 | as_fatal (_("%s unsupported"), "-a64"); | |
1196 | #endif | |
1197 | } | |
7f6d05e8 | 1198 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1199 | ppc_obj64 = 0; |
7f6d05e8 CP |
1200 | else |
1201 | return 0; | |
1202 | break; | |
81d4177b | 1203 | |
252b5132 | 1204 | case 'm': |
776fc418 | 1205 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1206 | /* "raw" is only valid for the disassembler. */ |
1207 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1208 | { |
1209 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1210 | if (strcmp (arg, "vle") == 0) |
1211 | { | |
1212 | if (set_target_endian && target_big_endian == 0) | |
1213 | as_bad (_("the use of -mvle requires big endian.")); | |
1214 | if (ppc_obj64) | |
1215 | as_bad (_("the use of -mvle requires -a32.")); | |
1216 | } | |
b9c361e0 | 1217 | } |
252b5132 | 1218 | |
83eef883 AFB |
1219 | else if (strcmp (arg, "no-vle") == 0) |
1220 | { | |
1221 | sticky &= ~PPC_OPCODE_VLE; | |
1222 | ||
1223 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1224 | new_cpu &= ~PPC_OPCODE_VLE; | |
1225 | ||
1226 | ppc_cpu = new_cpu; | |
1227 | } | |
1228 | ||
252b5132 | 1229 | else if (strcmp (arg, "regnames") == 0) |
b34976b6 | 1230 | reg_names_p = TRUE; |
252b5132 RH |
1231 | |
1232 | else if (strcmp (arg, "no-regnames") == 0) | |
b34976b6 | 1233 | reg_names_p = FALSE; |
252b5132 RH |
1234 | |
1235 | #ifdef OBJ_ELF | |
99a814a1 AM |
1236 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1237 | that require relocation. */ | |
252b5132 RH |
1238 | else if (strcmp (arg, "relocatable") == 0) |
1239 | { | |
5d6f4f16 | 1240 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1241 | ppc_flags |= EF_PPC_RELOCATABLE; |
1242 | } | |
1243 | ||
1244 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1245 | { | |
5d6f4f16 | 1246 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1247 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1248 | } | |
1249 | ||
99a814a1 | 1250 | /* -memb, set embedded bit. */ |
252b5132 RH |
1251 | else if (strcmp (arg, "emb") == 0) |
1252 | ppc_flags |= EF_PPC_EMB; | |
1253 | ||
cc643b88 | 1254 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1255 | else if (strcmp (arg, "little") == 0 |
1256 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1257 | { |
1258 | target_big_endian = 0; | |
1259 | set_target_endian = 1; | |
b9c361e0 | 1260 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1261 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1262 | } |
1263 | ||
1264 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1265 | { | |
1266 | target_big_endian = 1; | |
1267 | set_target_endian = 1; | |
1268 | } | |
1269 | ||
1270 | else if (strcmp (arg, "solaris") == 0) | |
1271 | { | |
b34976b6 | 1272 | msolaris = TRUE; |
252b5132 RH |
1273 | ppc_comment_chars = ppc_solaris_comment_chars; |
1274 | } | |
1275 | ||
1276 | else if (strcmp (arg, "no-solaris") == 0) | |
1277 | { | |
b34976b6 | 1278 | msolaris = FALSE; |
252b5132 RH |
1279 | ppc_comment_chars = ppc_eabi_comment_chars; |
1280 | } | |
74081948 AF |
1281 | else if (strcmp (arg, "spe2") == 0) |
1282 | { | |
1283 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1284 | } | |
252b5132 RH |
1285 | #endif |
1286 | else | |
1287 | { | |
1288 | as_bad (_("invalid switch -m%s"), arg); | |
1289 | return 0; | |
1290 | } | |
1291 | break; | |
1292 | ||
1293 | #ifdef OBJ_ELF | |
1294 | /* -V: SVR4 argument to print version ID. */ | |
1295 | case 'V': | |
1296 | print_version_id (); | |
1297 | break; | |
1298 | ||
1299 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1300 | should be emitted or not. FIXME: Not implemented. */ | |
1301 | case 'Q': | |
1302 | break; | |
1303 | ||
1304 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1305 | rather than .stabs.excl, which is ignored by the linker. | |
1306 | FIXME: Not implemented. */ | |
1307 | case 's': | |
1308 | if (arg) | |
1309 | return 0; | |
1310 | ||
1311 | break; | |
1312 | #endif | |
1313 | ||
cef4f754 AM |
1314 | case OPTION_NOPS: |
1315 | { | |
1316 | char *end; | |
1317 | nop_limit = strtoul (optarg, &end, 0); | |
1318 | if (*end) | |
1319 | as_bad (_("--nops needs a numeric argument")); | |
1320 | } | |
1321 | break; | |
85645aed | 1322 | |
bf7279d5 AM |
1323 | case 0: |
1324 | break; | |
1325 | ||
252b5132 RH |
1326 | default: |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | return 1; | |
1331 | } | |
1332 | ||
5f63875b AM |
1333 | static int |
1334 | is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED) | |
1335 | { | |
1336 | switch (targ->flavour) | |
1337 | { | |
1338 | #ifdef OBJ_ELF | |
1339 | case bfd_target_elf_flavour: | |
1340 | return strncmp (targ->name, "elf64-powerpc", 13) == 0; | |
1341 | #endif | |
1342 | #ifdef OBJ_XCOFF | |
1343 | case bfd_target_xcoff_flavour: | |
1344 | return (strcmp (targ->name, "aixcoff64-rs6000") == 0 | |
1345 | || strcmp (targ->name, "aix5coff64-rs6000") == 0); | |
1346 | #endif | |
1347 | default: | |
1348 | return 0; | |
1349 | } | |
1350 | } | |
1351 | ||
252b5132 | 1352 | void |
98027b10 | 1353 | md_show_usage (FILE *stream) |
252b5132 | 1354 | { |
bc805888 | 1355 | fprintf (stream, _("\ |
5f63875b AM |
1356 | PowerPC options:\n")); |
1357 | fprintf (stream, _("\ | |
1358 | -a32 generate ELF32/XCOFF32\n")); | |
1359 | if (bfd_iterate_over_targets (is_ppc64_target, NULL)) | |
1360 | fprintf (stream, _("\ | |
1361 | -a64 generate ELF64/XCOFF64\n")); | |
1362 | fprintf (stream, _("\ | |
1363 | -u ignored\n")); | |
1364 | fprintf (stream, _("\ | |
1365 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n")); | |
1366 | fprintf (stream, _("\ | |
1367 | -mpwr generate code for POWER (RIOS1)\n")); | |
1368 | fprintf (stream, _("\ | |
1369 | -m601 generate code for PowerPC 601\n")); | |
1370 | fprintf (stream, _("\ | |
418c1742 | 1371 | -mppc, -mppc32, -m603, -m604\n\ |
5f63875b AM |
1372 | generate code for PowerPC 603/604\n")); |
1373 | fprintf (stream, _("\ | |
1374 | -m403 generate code for PowerPC 403\n")); | |
1375 | fprintf (stream, _("\ | |
1376 | -m405 generate code for PowerPC 405\n")); | |
1377 | fprintf (stream, _("\ | |
1378 | -m440 generate code for PowerPC 440\n")); | |
1379 | fprintf (stream, _("\ | |
1380 | -m464 generate code for PowerPC 464\n")); | |
1381 | fprintf (stream, _("\ | |
1382 | -m476 generate code for PowerPC 476\n")); | |
1383 | fprintf (stream, _("\ | |
f5c120c5 | 1384 | -m7400, -m7410, -m7450, -m7455\n\ |
5f63875b AM |
1385 | generate code for PowerPC 7400/7410/7450/7455\n")); |
1386 | fprintf (stream, _("\ | |
fa758a70 | 1387 | -m750cl, -mgekko, -mbroadway\n\ |
5f63875b AM |
1388 | generate code for PowerPC 750cl/Gekko/Broadway\n")); |
1389 | fprintf (stream, _("\ | |
ef5a96d5 | 1390 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1391 | fprintf (stream, _("\ |
5f63875b AM |
1392 | -mppc64, -m620 generate code for PowerPC 620/625/630\n")); |
1393 | fprintf (stream, _("\ | |
1394 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n")); | |
1395 | fprintf (stream, _("\ | |
1396 | -mbooke generate code for 32-bit PowerPC BookE\n")); | |
1397 | fprintf (stream, _("\ | |
1398 | -ma2 generate code for A2 architecture\n")); | |
1399 | fprintf (stream, _("\ | |
1400 | -mpower4, -mpwr4 generate code for Power4 architecture\n")); | |
1401 | fprintf (stream, _("\ | |
cdc51b07 | 1402 | -mpower5, -mpwr5, -mpwr5x\n\ |
5f63875b AM |
1403 | generate code for Power5 architecture\n")); |
1404 | fprintf (stream, _("\ | |
1405 | -mpower6, -mpwr6 generate code for Power6 architecture\n")); | |
1406 | fprintf (stream, _("\ | |
1407 | -mpower7, -mpwr7 generate code for Power7 architecture\n")); | |
1408 | fprintf (stream, _("\ | |
1409 | -mpower8, -mpwr8 generate code for Power8 architecture\n")); | |
1410 | fprintf (stream, _("\ | |
1411 | -mpower9, -mpwr9 generate code for Power9 architecture\n")); | |
1412 | fprintf (stream, _("\ | |
1413 | -mcell generate code for Cell Broadband Engine architecture\n")); | |
1414 | fprintf (stream, _("\ | |
1415 | -mcom generate code for Power/PowerPC common instructions\n")); | |
1416 | fprintf (stream, _("\ | |
ce3d2015 | 1417 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1418 | fprintf (stream, _("\ |
5f63875b AM |
1419 | -maltivec generate code for AltiVec\n")); |
1420 | fprintf (stream, _("\ | |
1421 | -mvsx generate code for Vector-Scalar (VSX) instructions\n")); | |
1422 | fprintf (stream, _("\ | |
1423 | -me300 generate code for PowerPC e300 family\n")); | |
1424 | fprintf (stream, _("\ | |
1425 | -me500, -me500x2 generate code for Motorola e500 core complex\n")); | |
1426 | fprintf (stream, _("\ | |
1427 | -me500mc, generate code for Freescale e500mc core complex\n")); | |
1428 | fprintf (stream, _("\ | |
1429 | -me500mc64, generate code for Freescale e500mc64 core complex\n")); | |
1430 | fprintf (stream, _("\ | |
1431 | -me5500, generate code for Freescale e5500 core complex\n")); | |
1432 | fprintf (stream, _("\ | |
1433 | -me6500, generate code for Freescale e6500 core complex\n")); | |
1434 | fprintf (stream, _("\ | |
1435 | -mspe generate code for Motorola SPE instructions\n")); | |
1436 | fprintf (stream, _("\ | |
1437 | -mspe2 generate code for Freescale SPE2 instructions\n")); | |
1438 | fprintf (stream, _("\ | |
1439 | -mvle generate code for Freescale VLE instructions\n")); | |
1440 | fprintf (stream, _("\ | |
1441 | -mtitan generate code for AppliedMicro Titan core complex\n")); | |
1442 | fprintf (stream, _("\ | |
1443 | -mregnames Allow symbolic names for registers\n")); | |
1444 | fprintf (stream, _("\ | |
ce3d2015 | 1445 | -mno-regnames Do not allow symbolic names for registers\n")); |
252b5132 | 1446 | #ifdef OBJ_ELF |
bc805888 | 1447 | fprintf (stream, _("\ |
5f63875b AM |
1448 | -mrelocatable support for GCC's -mrelocatble option\n")); |
1449 | fprintf (stream, _("\ | |
1450 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n")); | |
1451 | fprintf (stream, _("\ | |
1452 | -memb set PPC_EMB bit in ELF flags\n")); | |
1453 | fprintf (stream, _("\ | |
b8b738ac | 1454 | -mlittle, -mlittle-endian, -le\n\ |
5f63875b AM |
1455 | generate code for a little endian machine\n")); |
1456 | fprintf (stream, _("\ | |
b8b738ac | 1457 | -mbig, -mbig-endian, -be\n\ |
5f63875b AM |
1458 | generate code for a big endian machine\n")); |
1459 | fprintf (stream, _("\ | |
1460 | -msolaris generate code for Solaris\n")); | |
1461 | fprintf (stream, _("\ | |
1462 | -mno-solaris do not generate code for Solaris\n")); | |
1463 | fprintf (stream, _("\ | |
1464 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n")); | |
1465 | fprintf (stream, _("\ | |
1466 | -V print assembler version number\n")); | |
1467 | fprintf (stream, _("\ | |
ce3d2015 | 1468 | -Qy, -Qn ignored\n")); |
252b5132 | 1469 | #endif |
cef4f754 | 1470 | fprintf (stream, _("\ |
5f63875b AM |
1471 | -nops=count when aligning, more than COUNT nops uses a branch\n")); |
1472 | fprintf (stream, _("\ | |
bf7279d5 | 1473 | -ppc476-workaround warn if emitting data to code sections\n")); |
252b5132 RH |
1474 | } |
1475 | \f | |
1476 | /* Set ppc_cpu if it is not already set. */ | |
1477 | ||
1478 | static void | |
98027b10 | 1479 | ppc_set_cpu (void) |
252b5132 RH |
1480 | { |
1481 | const char *default_os = TARGET_OS; | |
1482 | const char *default_cpu = TARGET_CPU; | |
1483 | ||
7102e95e | 1484 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1485 | { |
2a98c3a6 | 1486 | if (ppc_obj64) |
f2ab4b42 PB |
1487 | if (target_big_endian) |
1488 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1489 | else | |
1490 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1491 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
2a98c3a6 AM |
1492 | else if (strncmp (default_os, "aix", 3) == 0 |
1493 | && default_os[3] >= '4' && default_os[3] <= '9') | |
bdc70b4a | 1494 | ppc_cpu |= PPC_OPCODE_COMMON; |
252b5132 | 1495 | else if (strncmp (default_os, "aix3", 4) == 0) |
bdc70b4a | 1496 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1497 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1498 | ppc_cpu |= PPC_OPCODE_POWER; |
0baf16f2 | 1499 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
bdc70b4a | 1500 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1501 | else |
d6ed37ed | 1502 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1503 | default_cpu, default_os); |
252b5132 RH |
1504 | } |
1505 | } | |
1506 | ||
9232bbb0 AM |
1507 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1508 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1509 | |
1510 | enum bfd_architecture | |
98027b10 | 1511 | ppc_arch (void) |
252b5132 RH |
1512 | { |
1513 | const char *default_cpu = TARGET_CPU; | |
1514 | ppc_set_cpu (); | |
1515 | ||
1516 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1517 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1518 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1519 | return bfd_arch_powerpc; | |
1520 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1521 | return bfd_arch_rs6000; |
b9c361e0 | 1522 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1523 | { |
1524 | if (strcmp (default_cpu, "rs6000") == 0) | |
1525 | return bfd_arch_rs6000; | |
0baf16f2 | 1526 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
252b5132 RH |
1527 | return bfd_arch_powerpc; |
1528 | } | |
1529 | ||
d6ed37ed | 1530 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1531 | return bfd_arch_unknown; |
1532 | } | |
1533 | ||
7f6d05e8 | 1534 | unsigned long |
98027b10 | 1535 | ppc_mach (void) |
7f6d05e8 | 1536 | { |
2a98c3a6 AM |
1537 | if (ppc_obj64) |
1538 | return bfd_mach_ppc64; | |
1539 | else if (ppc_arch () == bfd_arch_rs6000) | |
1540 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1541 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1542 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1543 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1544 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1545 | else |
1546 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1547 | } |
1548 | ||
e0471c16 | 1549 | extern const char* |
98027b10 | 1550 | ppc_target_format (void) |
7f6d05e8 CP |
1551 | { |
1552 | #ifdef OBJ_COFF | |
1553 | #ifdef TE_PE | |
99a814a1 | 1554 | return target_big_endian ? "pe-powerpc" : "pe-powerpcle"; |
7f6d05e8 | 1555 | #elif TE_POWERMAC |
0baf16f2 | 1556 | return "xcoff-powermac"; |
7f6d05e8 | 1557 | #else |
eb1e0e80 | 1558 | # ifdef TE_AIX5 |
edc1d652 | 1559 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1560 | # else |
edc1d652 | 1561 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1562 | # endif |
7f6d05e8 | 1563 | #endif |
7f6d05e8 CP |
1564 | #endif |
1565 | #ifdef OBJ_ELF | |
edc1d652 AM |
1566 | # ifdef TE_FreeBSD |
1567 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1568 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1569 | return "elf32-powerpc-vxworks"; |
1570 | # else | |
0baf16f2 | 1571 | return (target_big_endian |
2b3c4602 AM |
1572 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1573 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1574 | # endif |
7f6d05e8 CP |
1575 | #endif |
1576 | } | |
1577 | ||
b9c361e0 JL |
1578 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1579 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1580 | ||
1581 | static bfd_boolean | |
1582 | insn_validate (const struct powerpc_opcode *op) | |
1583 | { | |
1584 | const unsigned char *o; | |
0f873fd5 | 1585 | uint64_t omask = op->mask; |
b9c361e0 JL |
1586 | |
1587 | /* The mask had better not trim off opcode bits. */ | |
1588 | if ((op->opcode & omask) != op->opcode) | |
1589 | { | |
1590 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
1591 | return TRUE; | |
1592 | } | |
1593 | ||
1594 | /* The operands must not overlap the opcode or each other. */ | |
1595 | for (o = op->operands; *o; ++o) | |
1596 | { | |
2eac3da1 | 1597 | bfd_boolean optional = FALSE; |
b9c361e0 JL |
1598 | if (*o >= num_powerpc_operands) |
1599 | { | |
1600 | as_bad (_("operand index error for %s"), op->name); | |
1601 | return TRUE; | |
1602 | } | |
1603 | else | |
1604 | { | |
71553718 | 1605 | uint64_t mask; |
b9c361e0 | 1606 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1607 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1608 | { |
71553718 AM |
1609 | const char *errmsg; |
1610 | int64_t val; | |
1611 | ||
1612 | errmsg = NULL; | |
1613 | val = -1; | |
1614 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1615 | val = -val; | |
1616 | else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) | |
1617 | val += 1; | |
1618 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); | |
b9c361e0 | 1619 | } |
71553718 AM |
1620 | else if (operand->shift >= 0) |
1621 | mask = operand->bitm << operand->shift; | |
1622 | else | |
1623 | mask = operand->bitm >> -operand->shift; | |
1624 | if (omask & mask) | |
1625 | { | |
1626 | as_bad (_("operand %d overlap in %s"), | |
1627 | (int) (o - op->operands), op->name); | |
1628 | return TRUE; | |
1629 | } | |
1630 | omask |= mask; | |
2eac3da1 AM |
1631 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
1632 | optional = TRUE; | |
1633 | else if (optional) | |
1634 | { | |
1635 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1636 | (int) (o - op->operands), op->name); | |
1637 | return TRUE; | |
1638 | } | |
b9c361e0 JL |
1639 | } |
1640 | } | |
1641 | return FALSE; | |
1642 | } | |
1643 | ||
69c040df | 1644 | /* Insert opcodes and macros into hash tables. Called at startup and |
1fe532cf | 1645 | for .machine pseudo. */ |
252b5132 | 1646 | |
69c040df AM |
1647 | static void |
1648 | ppc_setup_opcodes (void) | |
252b5132 | 1649 | { |
98027b10 | 1650 | const struct powerpc_opcode *op; |
252b5132 RH |
1651 | const struct powerpc_opcode *op_end; |
1652 | const struct powerpc_macro *macro; | |
1653 | const struct powerpc_macro *macro_end; | |
b84bf58a | 1654 | bfd_boolean bad_insn = FALSE; |
252b5132 | 1655 | |
69c040df AM |
1656 | if (ppc_hash != NULL) |
1657 | hash_die (ppc_hash); | |
1658 | if (ppc_macro_hash != NULL) | |
1659 | hash_die (ppc_macro_hash); | |
252b5132 RH |
1660 | |
1661 | /* Insert the opcodes into a hash table. */ | |
1662 | ppc_hash = hash_new (); | |
1663 | ||
c43a438d | 1664 | if (ENABLE_CHECKING) |
b84bf58a | 1665 | { |
c43a438d | 1666 | unsigned int i; |
b84bf58a | 1667 | |
3b8b57a9 AM |
1668 | /* An index into powerpc_operands is stored in struct fix |
1669 | fx_pcrel_adjust which is 8 bits wide. */ | |
1670 | gas_assert (num_powerpc_operands < 256); | |
1671 | ||
c43a438d AM |
1672 | /* Check operand masks. Code here and in the disassembler assumes |
1673 | all the 1's in the mask are contiguous. */ | |
1674 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1675 | { |
0f873fd5 PB |
1676 | uint64_t mask = powerpc_operands[i].bitm; |
1677 | uint64_t right_bit; | |
c43a438d AM |
1678 | unsigned int j; |
1679 | ||
1680 | right_bit = mask & -mask; | |
1681 | mask += right_bit; | |
1682 | right_bit = mask & -mask; | |
1683 | if (mask != right_bit) | |
1684 | { | |
1685 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
1686 | bad_insn = TRUE; | |
1687 | } | |
1688 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1689 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1690 | sizeof (powerpc_operands[0])) == 0) | |
1691 | { | |
1692 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1693 | j, i); | |
1694 | bad_insn = TRUE; | |
1695 | } | |
b84bf58a AM |
1696 | } |
1697 | } | |
1698 | ||
252b5132 RH |
1699 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1700 | for (op = powerpc_opcodes; op < op_end; op++) | |
1701 | { | |
c43a438d | 1702 | if (ENABLE_CHECKING) |
b84bf58a | 1703 | { |
2ceb7719 | 1704 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1705 | |
1706 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1707 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1708 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1709 | new_opcode, (unsigned long long) op->opcode, | |
1710 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1711 | #endif |
1712 | ||
2ceb7719 PB |
1713 | /* The major opcodes had better be sorted. Code in the disassembler |
1714 | assumes the insns are sorted according to major opcode. */ | |
1715 | if (op != powerpc_opcodes | |
1716 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1717 | { | |
1718 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1719 | bad_insn = TRUE; | |
8dbcd839 | 1720 | } |
2ceb7719 | 1721 | |
14b57c7c AM |
1722 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1723 | { | |
1724 | as_bad (_("%s is enabled by vle flag"), op->name); | |
1725 | bad_insn = TRUE; | |
1726 | } | |
1727 | if (PPC_OP (op->opcode) != 4 | |
1728 | && PPC_OP (op->opcode) != 31 | |
1729 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1730 | { | |
1731 | as_bad (_("%s not disabled by vle flag"), op->name); | |
1732 | bad_insn = TRUE; | |
1733 | } | |
b9c361e0 JL |
1734 | bad_insn |= insn_validate (op); |
1735 | } | |
c43a438d | 1736 | |
b9c361e0 JL |
1737 | if ((ppc_cpu & op->flags) != 0 |
1738 | && !(ppc_cpu & op->deprecated)) | |
1739 | { | |
1740 | const char *retval; | |
1741 | ||
1742 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1743 | if (retval != NULL) | |
c43a438d | 1744 | { |
b9c361e0 | 1745 | as_bad (_("duplicate instruction %s"), |
c43a438d AM |
1746 | op->name); |
1747 | bad_insn = TRUE; | |
1748 | } | |
b9c361e0 JL |
1749 | } |
1750 | } | |
c43a438d | 1751 | |
b9c361e0 JL |
1752 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1753 | for (op = powerpc_opcodes; op < op_end; op++) | |
1754 | hash_insert (ppc_hash, op->name, (void *) op); | |
1755 | ||
dd7efa79 PB |
1756 | op_end = prefix_opcodes + prefix_num_opcodes; |
1757 | for (op = prefix_opcodes; op < op_end; op++) | |
1758 | { | |
1759 | if (ENABLE_CHECKING) | |
1760 | { | |
1761 | unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); | |
1762 | ||
1763 | #ifdef PRINT_OPCODE_TABLE | |
1764 | printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", | |
1765 | op->name, (unsigned int) (op - prefix_opcodes), | |
1766 | new_opcode, (unsigned long long) op->opcode, | |
1767 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
1768 | #endif | |
1769 | ||
1770 | /* The major opcodes had better be sorted. Code in the disassembler | |
1771 | assumes the insns are sorted according to major opcode. */ | |
1772 | if (op != prefix_opcodes | |
1773 | && new_opcode < PPC_PREFIX_SEG (op[-1].opcode)) | |
1774 | { | |
1775 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1776 | bad_insn = TRUE; | |
1777 | } | |
1778 | bad_insn |= insn_validate (op); | |
1779 | } | |
1780 | ||
1781 | if ((ppc_cpu & op->flags) != 0 | |
1782 | && !(ppc_cpu & op->deprecated)) | |
1783 | { | |
1784 | const char *retval; | |
1785 | ||
1786 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1787 | if (retval != NULL) | |
1788 | { | |
1789 | as_bad (_("duplicate instruction %s"), | |
1790 | op->name); | |
1791 | bad_insn = TRUE; | |
1792 | } | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1797 | for (op = prefix_opcodes; op < op_end; op++) | |
1798 | hash_insert (ppc_hash, op->name, (void *) op); | |
1799 | ||
b9c361e0 JL |
1800 | op_end = vle_opcodes + vle_num_opcodes; |
1801 | for (op = vle_opcodes; op < op_end; op++) | |
1802 | { | |
1803 | if (ENABLE_CHECKING) | |
1804 | { | |
2ceb7719 | 1805 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1806 | |
1807 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1808 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1809 | op->name, (unsigned int) (op - vle_opcodes), | |
1810 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1811 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1812 | #endif |
2ceb7719 PB |
1813 | |
1814 | /* The major opcodes had better be sorted. Code in the disassembler | |
1815 | assumes the insns are sorted according to major opcode. */ | |
1816 | if (op != vle_opcodes | |
1817 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1818 | { | |
1819 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1820 | bad_insn = TRUE; | |
b9c361e0 JL |
1821 | } |
1822 | ||
1823 | bad_insn |= insn_validate (op); | |
c43a438d | 1824 | } |
252b5132 | 1825 | |
bdc70b4a | 1826 | if ((ppc_cpu & op->flags) != 0 |
1cb0a767 | 1827 | && !(ppc_cpu & op->deprecated)) |
252b5132 RH |
1828 | { |
1829 | const char *retval; | |
1830 | ||
98027b10 | 1831 | retval = hash_insert (ppc_hash, op->name, (void *) op); |
69c040df | 1832 | if (retval != NULL) |
252b5132 | 1833 | { |
b84bf58a | 1834 | as_bad (_("duplicate instruction %s"), |
99a814a1 | 1835 | op->name); |
b84bf58a | 1836 | bad_insn = TRUE; |
252b5132 RH |
1837 | } |
1838 | } | |
1839 | } | |
1840 | ||
74081948 AF |
1841 | /* SPE2 instructions */ |
1842 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1843 | { | |
1844 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1845 | for (op = spe2_opcodes; op < op_end; op++) | |
1846 | { | |
1847 | if (ENABLE_CHECKING) | |
1848 | { | |
1849 | if (op != spe2_opcodes) | |
1850 | { | |
1851 | unsigned old_seg, new_seg; | |
1852 | ||
1853 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1854 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1855 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1856 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1857 | ||
1858 | /* The major opcodes had better be sorted. Code in the | |
1859 | disassembler assumes the insns are sorted according to | |
1860 | major opcode. */ | |
1861 | if (new_seg < old_seg) | |
1862 | { | |
1863 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1864 | bad_insn = TRUE; | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | bad_insn |= insn_validate (op); | |
1869 | } | |
1870 | ||
1871 | if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated)) | |
1872 | { | |
1873 | const char *retval; | |
1874 | ||
1875 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1876 | if (retval != NULL) | |
1877 | { | |
1878 | as_bad (_("duplicate instruction %s"), | |
1879 | op->name); | |
1880 | bad_insn = TRUE; | |
1881 | } | |
1882 | } | |
1883 | } | |
1884 | ||
1885 | for (op = spe2_opcodes; op < op_end; op++) | |
1886 | hash_insert (ppc_hash, op->name, (void *) op); | |
1887 | } | |
1888 | ||
252b5132 RH |
1889 | /* Insert the macros into a hash table. */ |
1890 | ppc_macro_hash = hash_new (); | |
1891 | ||
1892 | macro_end = powerpc_macros + powerpc_num_macros; | |
1893 | for (macro = powerpc_macros; macro < macro_end; macro++) | |
1894 | { | |
33740db9 | 1895 | if ((macro->flags & ppc_cpu) != 0 || (ppc_cpu & PPC_OPCODE_ANY) != 0) |
252b5132 RH |
1896 | { |
1897 | const char *retval; | |
1898 | ||
98027b10 | 1899 | retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro); |
252b5132 RH |
1900 | if (retval != (const char *) NULL) |
1901 | { | |
b84bf58a AM |
1902 | as_bad (_("duplicate macro %s"), macro->name); |
1903 | bad_insn = TRUE; | |
252b5132 RH |
1904 | } |
1905 | } | |
1906 | } | |
1907 | ||
b84bf58a | 1908 | if (bad_insn) |
252b5132 | 1909 | abort (); |
69c040df AM |
1910 | } |
1911 | ||
1912 | /* This function is called when the assembler starts up. It is called | |
1913 | after the options have been parsed and the output file has been | |
1914 | opened. */ | |
1915 | ||
1916 | void | |
98027b10 | 1917 | md_begin (void) |
69c040df AM |
1918 | { |
1919 | ppc_set_cpu (); | |
1920 | ||
1921 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1922 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1923 | |
1924 | #ifdef OBJ_ELF | |
1925 | /* Set the ELF flags if desired. */ | |
1926 | if (ppc_flags && !msolaris) | |
1927 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1928 | #endif | |
1929 | ||
1930 | ppc_setup_opcodes (); | |
252b5132 | 1931 | |
67c1ffbe | 1932 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1933 | by the user. */ |
252b5132 RH |
1934 | if (!set_target_endian) |
1935 | { | |
1936 | set_target_endian = 1; | |
1937 | target_big_endian = PPC_BIG_ENDIAN; | |
1938 | } | |
1939 | ||
1940 | #ifdef OBJ_XCOFF | |
1941 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1942 | ||
1943 | /* Create dummy symbols to serve as initial csects. This forces the | |
1944 | text csects to precede the data csects. These symbols will not | |
1945 | be output. */ | |
1946 | ppc_text_csects = symbol_make ("dummy\001"); | |
809ffe0d | 1947 | symbol_get_tc (ppc_text_csects)->within = ppc_text_csects; |
252b5132 | 1948 | ppc_data_csects = symbol_make ("dummy\001"); |
809ffe0d | 1949 | symbol_get_tc (ppc_data_csects)->within = ppc_data_csects; |
252b5132 RH |
1950 | #endif |
1951 | ||
1952 | #ifdef TE_PE | |
1953 | ||
1954 | ppc_current_section = text_section; | |
81d4177b | 1955 | ppc_previous_section = 0; |
252b5132 RH |
1956 | |
1957 | #endif | |
1958 | } | |
1959 | ||
6a0c61b7 | 1960 | void |
98027b10 | 1961 | ppc_cleanup (void) |
6a0c61b7 | 1962 | { |
dc1d03fc | 1963 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1964 | if (ppc_apuinfo_list == NULL) |
1965 | return; | |
1966 | ||
1967 | /* Ok, so write the section info out. We have this layout: | |
1968 | ||
1969 | byte data what | |
1970 | ---- ---- ---- | |
1971 | 0 8 length of "APUinfo\0" | |
1972 | 4 (n*4) number of APU's (4 bytes each) | |
1973 | 8 2 note type 2 | |
1974 | 12 "APUinfo\0" name | |
1975 | 20 APU#1 first APU's info | |
1976 | 24 APU#2 second APU's info | |
1977 | ... ... | |
1978 | */ | |
1979 | { | |
1980 | char *p; | |
1981 | asection *seg = now_seg; | |
1982 | subsegT subseg = now_subseg; | |
1983 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1984 | unsigned int i; |
6a0c61b7 EZ |
1985 | |
1986 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1987 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
fd361982 | 1988 | bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1989 | |
1990 | p = frag_more (4); | |
1991 | md_number_to_chars (p, (valueT) 8, 4); | |
1992 | ||
1993 | p = frag_more (4); | |
e98d298c | 1994 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1995 | |
1996 | p = frag_more (4); | |
1997 | md_number_to_chars (p, (valueT) 2, 4); | |
1998 | ||
1999 | p = frag_more (8); | |
14b57c7c | 2000 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
2001 | |
2002 | for (i = 0; i < ppc_apuinfo_num; i++) | |
2003 | { | |
b34976b6 AM |
2004 | p = frag_more (4); |
2005 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
2006 | } |
2007 | ||
2008 | frag_align (2, 0, 0); | |
2009 | ||
2010 | /* We probably can't restore the current segment, for there likely | |
2011 | isn't one yet... */ | |
2012 | if (seg && subseg) | |
2013 | subseg_set (seg, subseg); | |
2014 | } | |
dc1d03fc | 2015 | #endif |
6a0c61b7 EZ |
2016 | } |
2017 | ||
252b5132 RH |
2018 | /* Insert an operand value into an instruction. */ |
2019 | ||
0f873fd5 PB |
2020 | static uint64_t |
2021 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 2022 | const struct powerpc_operand *operand, |
0f873fd5 | 2023 | int64_t val, |
91d6fa6a | 2024 | ppc_cpu_t cpu, |
3b4dbbbf | 2025 | const char *file, |
a1867a27 | 2026 | unsigned int line) |
252b5132 | 2027 | { |
0f873fd5 | 2028 | int64_t min, max, right; |
eb42fac1 | 2029 | |
b84bf58a AM |
2030 | max = operand->bitm; |
2031 | right = max & -max; | |
2032 | min = 0; | |
2033 | ||
a47622ac | 2034 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 2035 | { |
a255f00a AM |
2036 | /* Extend the allowed range for addis to [-32768, 65535]. |
2037 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
2038 | it would be good to disable this for signed fields since the | |
a47622ac AM |
2039 | value is sign extended into the high 32 bits of the register. |
2040 | If the value is, say, an address, then we might care about | |
2041 | the high bits. However, gcc as of 2014-06 uses unsigned | |
2042 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
2043 | lis. */ |
2044 | min = ~(max >> 1) & -right; | |
a47622ac AM |
2045 | } |
2046 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
2047 | { | |
2048 | max = (max >> 1) & -right; | |
931774a9 | 2049 | min = ~max & -right; |
b84bf58a | 2050 | } |
252b5132 | 2051 | |
b84bf58a | 2052 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 2053 | max++; |
252b5132 | 2054 | |
b84bf58a | 2055 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 2056 | { |
0f873fd5 | 2057 | int64_t tmp = min; |
a1867a27 AM |
2058 | min = -max; |
2059 | max = -tmp; | |
2060 | } | |
b84bf58a | 2061 | |
a1867a27 AM |
2062 | if (min <= max) |
2063 | { | |
2064 | /* Some people write constants with the sign extension done by | |
2065 | hand but only up to 32 bits. This shouldn't really be valid, | |
2066 | but, to permit this code to assemble on a 64-bit host, we | |
2067 | sign extend the 32-bit value to 64 bits if so doing makes the | |
8acf1435 PB |
2068 | value valid. We only do this for operands that are 32-bits or |
2069 | smaller. */ | |
a1867a27 | 2070 | if (val > max |
8acf1435 | 2071 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2072 | && (val - (1LL << 32)) >= min |
2073 | && (val - (1LL << 32)) <= max | |
2074 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
2075 | val = val - (1LL << 32); | |
a1867a27 AM |
2076 | |
2077 | /* Similarly, people write expressions like ~(1<<15), and expect | |
2078 | this to be OK for a 32-bit unsigned value. */ | |
2079 | else if (val < min | |
8acf1435 | 2080 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2081 | && (val + (1LL << 32)) >= min |
2082 | && (val + (1LL << 32)) <= max | |
2083 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
2084 | val = val + (1LL << 32); | |
a1867a27 AM |
2085 | |
2086 | else if (val < min | |
2087 | || val > max | |
2088 | || (val & (right - 1)) != 0) | |
2089 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
2090 | } | |
b84bf58a | 2091 | |
252b5132 RH |
2092 | if (operand->insert) |
2093 | { | |
2094 | const char *errmsg; | |
2095 | ||
2096 | errmsg = NULL; | |
0f873fd5 | 2097 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 2098 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 2099 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 2100 | } |
b9c361e0 | 2101 | else if (operand->shift >= 0) |
0f873fd5 | 2102 | insn |= (val & operand->bitm) << operand->shift; |
b9c361e0 | 2103 | else |
0f873fd5 | 2104 | insn |= (val & operand->bitm) >> -operand->shift; |
252b5132 RH |
2105 | |
2106 | return insn; | |
2107 | } | |
2108 | ||
2109 | \f | |
2110 | #ifdef OBJ_ELF | |
2111 | /* Parse @got, etc. and return the desired relocation. */ | |
2112 | static bfd_reloc_code_real_type | |
98027b10 | 2113 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
2114 | { |
2115 | struct map_bfd { | |
e0471c16 | 2116 | const char *string; |
b7d7dc63 AM |
2117 | unsigned int length : 8; |
2118 | unsigned int valid32 : 1; | |
2119 | unsigned int valid64 : 1; | |
2120 | unsigned int reloc; | |
252b5132 RH |
2121 | }; |
2122 | ||
2123 | char ident[20]; | |
2124 | char *str = *str_p; | |
2125 | char *str2; | |
2126 | int ch; | |
2127 | int len; | |
15c1449b | 2128 | const struct map_bfd *ptr; |
252b5132 | 2129 | |
b7d7dc63 AM |
2130 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2131 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2132 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2133 | |
15c1449b | 2134 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2135 | MAP ("l", BFD_RELOC_LO16), |
2136 | MAP ("h", BFD_RELOC_HI16), | |
2137 | MAP ("ha", BFD_RELOC_HI16_S), | |
2138 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2139 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2140 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2141 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2142 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2143 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2144 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2145 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2146 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2147 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2148 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2149 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2150 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2151 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2152 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2153 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2154 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2155 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2156 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2157 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2158 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2159 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2160 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2161 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2162 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2163 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2164 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2165 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2166 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2167 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2168 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2169 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2170 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2171 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2172 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2173 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2174 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2175 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2176 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2177 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2178 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2179 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2180 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2181 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2182 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2183 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2184 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2185 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2186 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2187 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2188 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2189 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2190 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2191 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2192 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2193 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2194 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2195 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2196 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2197 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2198 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2199 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2200 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2201 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2202 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2203 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2204 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2205 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2206 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2207 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2208 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2209 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2210 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2211 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2212 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2213 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2214 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2215 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2216 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2217 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2218 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2219 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2220 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2221 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2222 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2223 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2224 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2225 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2226 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2227 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2228 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2229 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2230 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2231 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
5663e321 AM |
2232 | MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34), |
2233 | MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34), | |
2234 | MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34), | |
c213164a AM |
2235 | MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL), |
2236 | MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD34), | |
2237 | MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD34), | |
2238 | MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL34), | |
2239 | MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL34), | |
5663e321 AM |
2240 | MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34), |
2241 | MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34), | |
2242 | MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34), | |
2243 | MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34), | |
62ebcb5c | 2244 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2245 | }; |
2246 | ||
2247 | if (*str++ != '@') | |
62ebcb5c | 2248 | return BFD_RELOC_NONE; |
252b5132 RH |
2249 | |
2250 | for (ch = *str, str2 = ident; | |
2251 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2252 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2253 | ch = *++str) |
2254 | { | |
3882b010 | 2255 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2256 | } |
2257 | ||
2258 | *str2 = '\0'; | |
2259 | len = str2 - ident; | |
2260 | ||
2261 | ch = ident[0]; | |
2262 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2263 | if (ch == ptr->string[0] | |
2264 | && len == ptr->length | |
b7d7dc63 AM |
2265 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2266 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2267 | { |
15c1449b AM |
2268 | int reloc = ptr->reloc; |
2269 | ||
727fc41e AM |
2270 | if (!ppc_obj64 && exp_p->X_add_number != 0) |
2271 | { | |
2272 | switch (reloc) | |
2273 | { | |
2274 | case BFD_RELOC_16_GOTOFF: | |
2275 | case BFD_RELOC_LO16_GOTOFF: | |
2276 | case BFD_RELOC_HI16_GOTOFF: | |
2277 | case BFD_RELOC_HI16_S_GOTOFF: | |
e47d413a AM |
2278 | as_warn (_("symbol+offset@%s means symbol@%s+offset"), |
2279 | ptr->string, ptr->string); | |
727fc41e AM |
2280 | break; |
2281 | ||
2282 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2283 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2284 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2285 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2286 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2287 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2288 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2289 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2290 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2291 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2292 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2293 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2294 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2295 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2296 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2297 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
e47d413a | 2298 | as_bad (_("symbol+offset@%s not supported"), ptr->string); |
727fc41e AM |
2299 | break; |
2300 | } | |
2301 | } | |
5f6db75a AM |
2302 | |
2303 | /* Now check for identifier@suffix+constant. */ | |
2304 | if (*str == '-' || *str == '+') | |
252b5132 | 2305 | { |
5f6db75a AM |
2306 | char *orig_line = input_line_pointer; |
2307 | expressionS new_exp; | |
2308 | ||
2309 | input_line_pointer = str; | |
2310 | expression (&new_exp); | |
2311 | if (new_exp.X_op == O_constant) | |
252b5132 | 2312 | { |
5f6db75a AM |
2313 | exp_p->X_add_number += new_exp.X_add_number; |
2314 | str = input_line_pointer; | |
252b5132 | 2315 | } |
5f6db75a AM |
2316 | |
2317 | if (&input_line_pointer != str_p) | |
2318 | input_line_pointer = orig_line; | |
252b5132 | 2319 | } |
252b5132 | 2320 | *str_p = str; |
0baf16f2 | 2321 | |
2b3c4602 | 2322 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2323 | && exp_p->X_op == O_symbol |
2324 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2325 | { |
9f2b53d7 AM |
2326 | /* Change the symbol so that the dummy .TOC. symbol can be |
2327 | omitted from the object file. */ | |
0baf16f2 AM |
2328 | exp_p->X_add_symbol = &abs_symbol; |
2329 | } | |
2330 | ||
15c1449b | 2331 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2332 | } |
2333 | ||
62ebcb5c | 2334 | return BFD_RELOC_NONE; |
252b5132 RH |
2335 | } |
2336 | ||
62ebcb5c | 2337 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2338 | |
62ebcb5c AM |
2339 | bfd_reloc_code_real_type |
2340 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2341 | { | |
2342 | expression (exp); | |
2343 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2344 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2345 | return BFD_RELOC_NONE; | |
252b5132 RH |
2346 | } |
2347 | ||
bf7279d5 AM |
2348 | /* Warn when emitting data to code sections, unless we are emitting |
2349 | a relocation that ld --ppc476-workaround uses to recognise data | |
2350 | *and* there was an unconditional branch prior to the data. */ | |
2351 | ||
2352 | void | |
2353 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2354 | unsigned int nbytes, fixS *fix) | |
2355 | { | |
2356 | if (warn_476 | |
2357 | && (now_seg->flags & SEC_CODE) != 0 | |
2358 | && (nbytes != 4 | |
2359 | || fix == NULL | |
2360 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2361 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2362 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2363 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2364 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2365 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2366 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2367 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2368 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2369 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2370 | { | |
2371 | /* Flag that we've warned. */ | |
2372 | if (fix != NULL) | |
2373 | fix->fx_tcbit = 1; | |
2374 | ||
2375 | as_warn (_("data in executable section")); | |
2376 | } | |
2377 | } | |
2378 | ||
252b5132 RH |
2379 | /* Solaris pseduo op to change to the .rodata section. */ |
2380 | static void | |
98027b10 | 2381 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2382 | { |
2383 | char *save_line = input_line_pointer; | |
2384 | static char section[] = ".rodata\n"; | |
2385 | ||
99a814a1 | 2386 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2387 | input_line_pointer = section; |
2388 | obj_elf_section (xxx); | |
2389 | ||
2390 | input_line_pointer = save_line; | |
2391 | } | |
2392 | ||
99a814a1 | 2393 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2394 | static void |
98027b10 | 2395 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2396 | { |
98027b10 AM |
2397 | char *name; |
2398 | char c; | |
2399 | char *p; | |
252b5132 | 2400 | offsetT size; |
98027b10 | 2401 | symbolS *symbolP; |
252b5132 RH |
2402 | offsetT align; |
2403 | segT old_sec; | |
2404 | int old_subsec; | |
2405 | char *pfrag; | |
2406 | int align2; | |
2407 | ||
d02603dc | 2408 | c = get_symbol_name (&name); |
252b5132 | 2409 | |
d02603dc | 2410 | /* Just after name is now '\0'. */ |
252b5132 RH |
2411 | p = input_line_pointer; |
2412 | *p = c; | |
d02603dc | 2413 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2414 | if (*input_line_pointer != ',') |
2415 | { | |
d6ed37ed | 2416 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2417 | ignore_rest_of_line (); |
2418 | return; | |
2419 | } | |
2420 | ||
2421 | input_line_pointer++; /* skip ',' */ | |
2422 | if ((size = get_absolute_expression ()) < 0) | |
2423 | { | |
2424 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2425 | ignore_rest_of_line (); | |
2426 | return; | |
2427 | } | |
2428 | ||
2429 | /* The third argument to .lcomm is the alignment. */ | |
2430 | if (*input_line_pointer != ',') | |
2431 | align = 8; | |
2432 | else | |
2433 | { | |
2434 | ++input_line_pointer; | |
2435 | align = get_absolute_expression (); | |
2436 | if (align <= 0) | |
2437 | { | |
2438 | as_warn (_("ignoring bad alignment")); | |
2439 | align = 8; | |
2440 | } | |
2441 | } | |
2442 | ||
2443 | *p = 0; | |
2444 | symbolP = symbol_find_or_make (name); | |
2445 | *p = c; | |
2446 | ||
2447 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2448 | { | |
d6ed37ed | 2449 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2450 | S_GET_NAME (symbolP)); |
2451 | ignore_rest_of_line (); | |
2452 | return; | |
2453 | } | |
2454 | ||
2455 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2456 | { | |
d6ed37ed | 2457 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2458 | S_GET_NAME (symbolP), |
2459 | (long) S_GET_VALUE (symbolP), | |
2460 | (long) size); | |
2461 | ||
2462 | ignore_rest_of_line (); | |
2463 | return; | |
2464 | } | |
2465 | ||
99a814a1 | 2466 | /* Allocate_bss. */ |
252b5132 RH |
2467 | old_sec = now_seg; |
2468 | old_subsec = now_subseg; | |
2469 | if (align) | |
2470 | { | |
99a814a1 | 2471 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2472 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2473 | if (align != 1) | |
2474 | { | |
d6ed37ed | 2475 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2476 | ignore_rest_of_line (); |
2477 | return; | |
2478 | } | |
2479 | } | |
2480 | else | |
2481 | align2 = 0; | |
2482 | ||
2483 | record_alignment (bss_section, align2); | |
cbe02d4f | 2484 | subseg_set (bss_section, 1); |
252b5132 RH |
2485 | if (align2) |
2486 | frag_align (align2, 0, 0); | |
2487 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2488 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2489 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2490 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2491 | (char *) 0); | |
2492 | *pfrag = 0; | |
2493 | S_SET_SIZE (symbolP, size); | |
2494 | S_SET_SEGMENT (symbolP, bss_section); | |
2495 | subseg_set (old_sec, old_subsec); | |
2496 | demand_empty_rest_of_line (); | |
2497 | } | |
2498 | ||
6911b7dc AM |
2499 | /* Pseudo op to set symbol local entry point. */ |
2500 | static void | |
2501 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2502 | { | |
d02603dc NC |
2503 | char *name; |
2504 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2505 | char *p; |
2506 | expressionS exp; | |
2507 | symbolS *sym; | |
2508 | asymbol *bfdsym; | |
2509 | elf_symbol_type *elfsym; | |
2510 | ||
2511 | p = input_line_pointer; | |
2512 | *p = c; | |
d02603dc | 2513 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2514 | if (*input_line_pointer != ',') |
2515 | { | |
2516 | *p = 0; | |
2517 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2518 | name); | |
2519 | *p = c; | |
2520 | ignore_rest_of_line (); | |
2521 | return; | |
2522 | } | |
2523 | input_line_pointer++; | |
2524 | expression (&exp); | |
2525 | if (exp.X_op == O_absent) | |
2526 | { | |
2527 | as_bad (_("missing expression in .localentry directive")); | |
2528 | exp.X_op = O_constant; | |
2529 | exp.X_add_number = 0; | |
2530 | } | |
2531 | *p = 0; | |
2532 | sym = symbol_find_or_make (name); | |
2533 | *p = c; | |
2534 | ||
2535 | if (resolve_expression (&exp) | |
2536 | && exp.X_op == O_constant) | |
2537 | { | |
33cb30a1 | 2538 | unsigned int encoded, ok; |
6911b7dc | 2539 | |
33cb30a1 AM |
2540 | ok = 1; |
2541 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2542 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2543 | else |
33cb30a1 AM |
2544 | { |
2545 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2546 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2547 | { | |
2548 | as_bad (_(".localentry expression for `%s' " | |
2549 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2550 | ok = 0; | |
2551 | } | |
2552 | } | |
2553 | if (ok) | |
6911b7dc AM |
2554 | { |
2555 | bfdsym = symbol_get_bfdsym (sym); | |
2556 | elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
2557 | gas_assert (elfsym); | |
2558 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2559 | elfsym->internal_elf_sym.st_other |= encoded; | |
2560 | if (ppc_abiversion == 0) | |
2561 | ppc_abiversion = 2; | |
2562 | } | |
2563 | } | |
2564 | else | |
2565 | as_bad (_(".localentry expression for `%s' " | |
2566 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2567 | ||
2568 | demand_empty_rest_of_line (); | |
2569 | } | |
2570 | ||
ee67d69a AM |
2571 | /* Pseudo op to set ABI version. */ |
2572 | static void | |
2573 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2574 | { | |
2575 | expressionS exp; | |
2576 | ||
2577 | expression (&exp); | |
2578 | if (exp.X_op == O_absent) | |
2579 | { | |
2580 | as_bad (_("missing expression in .abiversion directive")); | |
2581 | exp.X_op = O_constant; | |
2582 | exp.X_add_number = 0; | |
2583 | } | |
2584 | ||
2585 | if (resolve_expression (&exp) | |
2586 | && exp.X_op == O_constant) | |
2587 | ppc_abiversion = exp.X_add_number; | |
2588 | else | |
2589 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2590 | demand_empty_rest_of_line (); | |
2591 | } | |
2592 | ||
005d79fd AM |
2593 | /* Parse a .gnu_attribute directive. */ |
2594 | static void | |
2595 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2596 | { | |
2597 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2598 | ||
2599 | /* Check validity of defined powerpc tags. */ | |
2600 | if (tag == Tag_GNU_Power_ABI_FP | |
2601 | || tag == Tag_GNU_Power_ABI_Vector | |
2602 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2603 | { | |
2604 | unsigned int val; | |
2605 | ||
2606 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2607 | ||
2608 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2609 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2610 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2611 | as_warn (_("unknown .gnu_attribute value")); | |
2612 | } | |
2613 | } | |
2614 | ||
ee67d69a AM |
2615 | /* Set ABI version in output file. */ |
2616 | void | |
2617 | ppc_elf_end (void) | |
2618 | { | |
2619 | if (ppc_obj64 && ppc_abiversion != 0) | |
2620 | { | |
2621 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2622 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2623 | } | |
22f72c48 AM |
2624 | /* Any selection of opcodes based on ppc_cpu after gas has finished |
2625 | parsing the file is invalid. md_apply_fix and ppc_handle_align | |
2626 | must select opcodes based on the machine in force at the point | |
2627 | where the fixup or alignment frag was created, not the machine in | |
2628 | force at the end of file. */ | |
2629 | ppc_cpu = 0; | |
ee67d69a AM |
2630 | } |
2631 | ||
252b5132 RH |
2632 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2633 | fixups for word relocations in writable segments, so we can adjust | |
2634 | them at runtime. */ | |
2635 | static void | |
98027b10 | 2636 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2637 | { |
2638 | if (fixp->fx_done || fixp->fx_pcrel) | |
2639 | return; | |
2640 | ||
2641 | switch (shlib) | |
2642 | { | |
2643 | case SHLIB_NONE: | |
2644 | case SHLIB_PIC: | |
2645 | return; | |
2646 | ||
5d6f4f16 | 2647 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2648 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2649 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2650 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2651 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2652 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2653 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2654 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2655 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2656 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2657 | && strcmp (segment_name (seg), ".got2") != 0 |
2658 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2659 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2660 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2661 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2662 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2663 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2664 | { | |
2665 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2666 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2667 | { | |
2668 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2669 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2670 | } |
2671 | } | |
2672 | return; | |
2673 | } | |
2674 | } | |
0baf16f2 | 2675 | |
7e8d4ab4 AM |
2676 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2677 | function descriptor sym if the corresponding code sym is used. */ | |
2678 | ||
2679 | void | |
98027b10 | 2680 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2681 | { |
7e8d4ab4 | 2682 | symbolS *symp; |
9232bbb0 | 2683 | asection *toc; |
0baf16f2 | 2684 | |
7e8d4ab4 AM |
2685 | if (!ppc_obj64) |
2686 | return; | |
2687 | ||
2688 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2689 | { |
7e8d4ab4 AM |
2690 | const char *name; |
2691 | char *dotname; | |
2692 | symbolS *dotsym; | |
7e8d4ab4 AM |
2693 | |
2694 | name = S_GET_NAME (symp); | |
2695 | if (name[0] == '.') | |
2696 | continue; | |
2697 | ||
2698 | if (! S_IS_WEAK (symp) | |
2699 | || S_IS_DEFINED (symp)) | |
2700 | continue; | |
2701 | ||
a44e2901 | 2702 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2703 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2704 | free (dotname); |
2705 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2706 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2707 | symbol_mark_used (symp); |
2708 | ||
0baf16f2 AM |
2709 | } |
2710 | ||
9232bbb0 AM |
2711 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2712 | if (toc != NULL | |
01efc3af | 2713 | && toc_reloc_types != has_large_toc_reloc |
fd361982 | 2714 | && bfd_section_size (toc) > 0x10000) |
9232bbb0 | 2715 | as_warn (_("TOC section size exceeds 64k")); |
a38a07e0 AM |
2716 | } |
2717 | ||
2718 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2719 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2720 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2721 | |
a38a07e0 AM |
2722 | void |
2723 | ppc_elf_adjust_symtab (void) | |
2724 | { | |
2725 | if (ppc_obj64) | |
2726 | { | |
2727 | symbolS *symp; | |
2728 | symp = symbol_find (".TOC."); | |
2729 | if (symp != NULL) | |
2730 | { | |
2731 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2732 | if ((bsym->flags & BSF_KEEP) == 0) | |
2733 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2734 | } |
2735 | } | |
0baf16f2 | 2736 | } |
252b5132 RH |
2737 | #endif /* OBJ_ELF */ |
2738 | \f | |
2739 | #ifdef TE_PE | |
2740 | ||
2741 | /* | |
99a814a1 | 2742 | * Summary of parse_toc_entry. |
252b5132 RH |
2743 | * |
2744 | * in: Input_line_pointer points to the '[' in one of: | |
2745 | * | |
2746 | * [toc] [tocv] [toc32] [toc64] | |
2747 | * | |
2748 | * Anything else is an error of one kind or another. | |
2749 | * | |
81d4177b | 2750 | * out: |
252b5132 RH |
2751 | * return value: success or failure |
2752 | * toc_kind: kind of toc reference | |
2753 | * input_line_pointer: | |
2754 | * success: first char after the ']' | |
2755 | * failure: unchanged | |
2756 | * | |
2757 | * settings: | |
2758 | * | |
2759 | * [toc] - rv == success, toc_kind = default_toc | |
2760 | * [tocv] - rv == success, toc_kind = data_in_toc | |
2761 | * [toc32] - rv == success, toc_kind = must_be_32 | |
2762 | * [toc64] - rv == success, toc_kind = must_be_64 | |
2763 | * | |
2764 | */ | |
2765 | ||
81d4177b KH |
2766 | enum toc_size_qualifier |
2767 | { | |
252b5132 RH |
2768 | default_toc, /* The toc cell constructed should be the system default size */ |
2769 | data_in_toc, /* This is a direct reference to a toc cell */ | |
2770 | must_be_32, /* The toc cell constructed must be 32 bits wide */ | |
2771 | must_be_64 /* The toc cell constructed must be 64 bits wide */ | |
2772 | }; | |
2773 | ||
2774 | static int | |
98027b10 | 2775 | parse_toc_entry (enum toc_size_qualifier *toc_kind) |
252b5132 RH |
2776 | { |
2777 | char *start; | |
2778 | char *toc_spec; | |
2779 | char c; | |
2780 | enum toc_size_qualifier t; | |
2781 | ||
99a814a1 | 2782 | /* Save the input_line_pointer. */ |
252b5132 RH |
2783 | start = input_line_pointer; |
2784 | ||
99a814a1 | 2785 | /* Skip over the '[' , and whitespace. */ |
252b5132 RH |
2786 | ++input_line_pointer; |
2787 | SKIP_WHITESPACE (); | |
81d4177b | 2788 | |
99a814a1 | 2789 | /* Find the spelling of the operand. */ |
d02603dc | 2790 | c = get_symbol_name (&toc_spec); |
252b5132 | 2791 | |
99a814a1 | 2792 | if (strcmp (toc_spec, "toc") == 0) |
252b5132 RH |
2793 | { |
2794 | t = default_toc; | |
2795 | } | |
99a814a1 | 2796 | else if (strcmp (toc_spec, "tocv") == 0) |
252b5132 RH |
2797 | { |
2798 | t = data_in_toc; | |
2799 | } | |
99a814a1 | 2800 | else if (strcmp (toc_spec, "toc32") == 0) |
252b5132 RH |
2801 | { |
2802 | t = must_be_32; | |
2803 | } | |
99a814a1 | 2804 | else if (strcmp (toc_spec, "toc64") == 0) |
252b5132 RH |
2805 | { |
2806 | t = must_be_64; | |
2807 | } | |
2808 | else | |
2809 | { | |
2810 | as_bad (_("syntax error: invalid toc specifier `%s'"), toc_spec); | |
99a814a1 AM |
2811 | *input_line_pointer = c; |
2812 | input_line_pointer = start; | |
252b5132 RH |
2813 | return 0; |
2814 | } | |
2815 | ||
99a814a1 AM |
2816 | /* Now find the ']'. */ |
2817 | *input_line_pointer = c; | |
252b5132 | 2818 | |
d02603dc | 2819 | SKIP_WHITESPACE_AFTER_NAME (); /* leading whitespace could be there. */ |
81d4177b | 2820 | c = *input_line_pointer++; /* input_line_pointer->past char in c. */ |
252b5132 RH |
2821 | |
2822 | if (c != ']') | |
2823 | { | |
2824 | as_bad (_("syntax error: expected `]', found `%c'"), c); | |
99a814a1 | 2825 | input_line_pointer = start; |
252b5132 RH |
2826 | return 0; |
2827 | } | |
2828 | ||
99a814a1 | 2829 | *toc_kind = t; |
252b5132 RH |
2830 | return 1; |
2831 | } | |
2832 | #endif | |
3b8b57a9 | 2833 | |
3e60bf4d | 2834 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2835 | /* See whether a symbol is in the TOC section. */ |
2836 | ||
2837 | static int | |
2838 | ppc_is_toc_sym (symbolS *sym) | |
2839 | { | |
3e60bf4d | 2840 | #ifdef OBJ_XCOFF |
9f6e76f4 TG |
2841 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
2842 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); | |
f50c47f1 | 2843 | #endif |
3e60bf4d AM |
2844 | #ifdef OBJ_ELF |
2845 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2846 | if (ppc_obj64) | |
2847 | return strcmp (sname, ".toc") == 0; | |
2848 | else | |
2849 | return strcmp (sname, ".got") == 0; | |
2850 | #endif | |
2851 | } | |
2852 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2853 | \f |
2854 | ||
dc1d03fc | 2855 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2856 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2857 | static void | |
98027b10 | 2858 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2859 | { |
2860 | unsigned int i; | |
2861 | ||
2862 | /* Check we don't already exist. */ | |
2863 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2864 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2865 | return; |
b34976b6 | 2866 | |
6a0c61b7 EZ |
2867 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2868 | { | |
2869 | if (ppc_apuinfo_num_alloc == 0) | |
2870 | { | |
2871 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2872 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2873 | } |
2874 | else | |
2875 | { | |
2876 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2877 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2878 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2879 | } |
2880 | } | |
dc1d03fc | 2881 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2882 | } |
2883 | #undef APUID | |
dc1d03fc | 2884 | #endif |
6a0c61b7 | 2885 | \f |
dd7efa79 PB |
2886 | /* Various frobbings of labels and their addresses. */ |
2887 | ||
2888 | /* Symbols labelling the current insn. */ | |
2889 | struct insn_label_list | |
2890 | { | |
2891 | struct insn_label_list *next; | |
2892 | symbolS *label; | |
2893 | }; | |
2894 | ||
2895 | static struct insn_label_list *insn_labels; | |
2896 | static struct insn_label_list *free_insn_labels; | |
2897 | ||
2898 | static void | |
2899 | ppc_record_label (symbolS *sym) | |
2900 | { | |
2901 | struct insn_label_list *l; | |
2902 | ||
2903 | if (free_insn_labels == NULL) | |
2904 | l = XNEW (struct insn_label_list); | |
2905 | else | |
2906 | { | |
2907 | l = free_insn_labels; | |
2908 | free_insn_labels = l->next; | |
2909 | } | |
2910 | ||
2911 | l->label = sym; | |
2912 | l->next = insn_labels; | |
2913 | insn_labels = l; | |
2914 | } | |
2915 | ||
2916 | static void | |
2917 | ppc_clear_labels (void) | |
2918 | { | |
2919 | while (insn_labels != NULL) | |
2920 | { | |
2921 | struct insn_label_list *l = insn_labels; | |
2922 | insn_labels = l->next; | |
2923 | l->next = free_insn_labels; | |
2924 | free_insn_labels = l; | |
2925 | } | |
2926 | } | |
2927 | ||
2928 | void | |
2929 | ppc_start_line_hook (void) | |
2930 | { | |
2931 | ppc_clear_labels (); | |
2932 | } | |
2933 | ||
2934 | void | |
2935 | ppc_new_dot_label (symbolS *sym) | |
2936 | { | |
2937 | ppc_record_label (sym); | |
2938 | #ifdef OBJ_XCOFF | |
2939 | /* Anchor this label to the current csect for relocations. */ | |
2940 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2941 | #endif | |
2942 | } | |
2943 | ||
2944 | void | |
2945 | ppc_frob_label (symbolS *sym) | |
2946 | { | |
2947 | ppc_record_label (sym); | |
2948 | ||
2949 | #ifdef OBJ_XCOFF | |
2950 | /* Set the class of a label based on where it is defined. This handles | |
2951 | symbols without suffixes. Also, move the symbol so that it follows | |
2952 | the csect symbol. */ | |
2953 | if (ppc_current_csect != (symbolS *) NULL) | |
2954 | { | |
2955 | if (symbol_get_tc (sym)->symbol_class == -1) | |
2956 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
2957 | ||
2958 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
2959 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, | |
2960 | &symbol_rootP, &symbol_lastP); | |
2961 | symbol_get_tc (ppc_current_csect)->within = sym; | |
2962 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2963 | } | |
2964 | #endif | |
2965 | ||
2966 | #ifdef OBJ_ELF | |
2967 | dwarf2_emit_label (sym); | |
2968 | #endif | |
2969 | } | |
6a0c61b7 | 2970 | |
252b5132 RH |
2971 | /* We need to keep a list of fixups. We can't simply generate them as |
2972 | we go, because that would require us to first create the frag, and | |
2973 | that would screw up references to ``.''. */ | |
2974 | ||
2975 | struct ppc_fixup | |
2976 | { | |
2977 | expressionS exp; | |
2978 | int opindex; | |
2979 | bfd_reloc_code_real_type reloc; | |
2980 | }; | |
2981 | ||
2982 | #define MAX_INSN_FIXUPS (5) | |
2983 | ||
0e2779e9 AM |
2984 | /* Return the field size operated on by RELOC, and whether it is |
2985 | pc-relative in PC_RELATIVE. */ | |
2986 | ||
2987 | static unsigned int | |
2988 | fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative) | |
2989 | { | |
2990 | unsigned int size = 0; | |
2991 | bfd_boolean pcrel = FALSE; | |
2992 | ||
2993 | switch (reloc) | |
2994 | { | |
2995 | /* This switch statement must handle all BFD_RELOC values | |
2996 | possible in instruction fixups. As is, it handles all | |
2997 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
2998 | bfd/coff-ppc, bfd/coff-rs6000.c and bfd/coff64-rs6000.c. | |
2999 | Overkill since data and marker relocs need not be handled | |
3000 | here, but this way we can be sure a needed fixup reloc isn't | |
3001 | accidentally omitted. */ | |
3002 | case BFD_RELOC_PPC_EMB_MRKREF: | |
3003 | case BFD_RELOC_VTABLE_ENTRY: | |
3004 | case BFD_RELOC_VTABLE_INHERIT: | |
3005 | break; | |
3006 | ||
3007 | case BFD_RELOC_8: | |
3008 | size = 1; | |
3009 | break; | |
3010 | ||
3011 | case BFD_RELOC_16: | |
3012 | case BFD_RELOC_16_BASEREL: | |
3013 | case BFD_RELOC_16_GOTOFF: | |
3014 | case BFD_RELOC_GPREL16: | |
3015 | case BFD_RELOC_HI16: | |
3016 | case BFD_RELOC_HI16_BASEREL: | |
3017 | case BFD_RELOC_HI16_GOTOFF: | |
3018 | case BFD_RELOC_HI16_PLTOFF: | |
3019 | case BFD_RELOC_HI16_S: | |
3020 | case BFD_RELOC_HI16_S_BASEREL: | |
3021 | case BFD_RELOC_HI16_S_GOTOFF: | |
3022 | case BFD_RELOC_HI16_S_PLTOFF: | |
3023 | case BFD_RELOC_LO16: | |
3024 | case BFD_RELOC_LO16_BASEREL: | |
3025 | case BFD_RELOC_LO16_GOTOFF: | |
3026 | case BFD_RELOC_LO16_PLTOFF: | |
3027 | case BFD_RELOC_PPC64_ADDR16_DS: | |
3028 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3029 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
5663e321 AM |
3030 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
3031 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
3032 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
3033 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
0e2779e9 AM |
3034 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
3035 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
3036 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
3037 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3038 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
3039 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
3040 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
3041 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
3042 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
3043 | case BFD_RELOC_PPC64_GOT16_DS: | |
3044 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
3045 | case BFD_RELOC_PPC64_HIGHER: | |
3046 | case BFD_RELOC_PPC64_HIGHER_S: | |
3047 | case BFD_RELOC_PPC64_HIGHEST: | |
3048 | case BFD_RELOC_PPC64_HIGHEST_S: | |
3049 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
3050 | case BFD_RELOC_PPC64_PLTGOT16: | |
3051 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
3052 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
3053 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
3054 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
3055 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
3056 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
3057 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
3058 | case BFD_RELOC_PPC64_TOC16_DS: | |
3059 | case BFD_RELOC_PPC64_TOC16_HA: | |
3060 | case BFD_RELOC_PPC64_TOC16_HI: | |
3061 | case BFD_RELOC_PPC64_TOC16_LO: | |
3062 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
3063 | case BFD_RELOC_PPC64_TPREL16_DS: | |
3064 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
3065 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3066 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
3067 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
3068 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
3069 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
3070 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
3071 | #ifdef OBJ_XCOFF | |
3072 | case BFD_RELOC_PPC_BA16: | |
3073 | #endif | |
3074 | case BFD_RELOC_PPC_DTPREL16: | |
3075 | case BFD_RELOC_PPC_DTPREL16_HA: | |
3076 | case BFD_RELOC_PPC_DTPREL16_HI: | |
3077 | case BFD_RELOC_PPC_DTPREL16_LO: | |
3078 | case BFD_RELOC_PPC_EMB_NADDR16: | |
3079 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
3080 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
3081 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
3082 | case BFD_RELOC_PPC_EMB_RELSDA: | |
3083 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
3084 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
3085 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
3086 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
3087 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
3088 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
3089 | case BFD_RELOC_PPC_EMB_SDAI16: | |
3090 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
3091 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
3092 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
3093 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3094 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
3095 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
3096 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
3097 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
3098 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
3099 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
3100 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
3101 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
3102 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3103 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
3104 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
3105 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3106 | case BFD_RELOC_PPC_TOC16: | |
3107 | case BFD_RELOC_PPC_TPREL16: | |
3108 | case BFD_RELOC_PPC_TPREL16_HA: | |
3109 | case BFD_RELOC_PPC_TPREL16_HI: | |
3110 | case BFD_RELOC_PPC_TPREL16_LO: | |
3111 | size = 2; | |
3112 | break; | |
3113 | ||
3114 | case BFD_RELOC_16_PCREL: | |
3115 | case BFD_RELOC_HI16_PCREL: | |
3116 | case BFD_RELOC_HI16_S_PCREL: | |
3117 | case BFD_RELOC_LO16_PCREL: | |
3118 | case BFD_RELOC_PPC64_REL16_HIGH: | |
3119 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
3120 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
5663e321 | 3121 | case BFD_RELOC_PPC64_REL16_HIGHER34: |
0e2779e9 | 3122 | case BFD_RELOC_PPC64_REL16_HIGHERA: |
5663e321 | 3123 | case BFD_RELOC_PPC64_REL16_HIGHERA34: |
0e2779e9 | 3124 | case BFD_RELOC_PPC64_REL16_HIGHEST: |
5663e321 | 3125 | case BFD_RELOC_PPC64_REL16_HIGHEST34: |
0e2779e9 | 3126 | case BFD_RELOC_PPC64_REL16_HIGHESTA: |
5663e321 | 3127 | case BFD_RELOC_PPC64_REL16_HIGHESTA34: |
0e2779e9 AM |
3128 | #ifdef OBJ_XCOFF |
3129 | case BFD_RELOC_PPC_B16: | |
3130 | #endif | |
3131 | case BFD_RELOC_PPC_VLE_REL8: | |
3132 | size = 2; | |
3133 | pcrel = TRUE; | |
3134 | break; | |
3135 | ||
3136 | case BFD_RELOC_16_GOT_PCREL: /* coff reloc, bad name re size. */ | |
3137 | case BFD_RELOC_32: | |
3138 | case BFD_RELOC_32_GOTOFF: | |
3139 | case BFD_RELOC_32_PLTOFF: | |
3140 | #ifdef OBJ_XCOFF | |
3141 | case BFD_RELOC_CTOR: | |
3142 | #endif | |
3143 | case BFD_RELOC_PPC64_ENTRY: | |
3144 | case BFD_RELOC_PPC_16DX_HA: | |
3145 | #ifndef OBJ_XCOFF | |
3146 | case BFD_RELOC_PPC_BA16: | |
3147 | #endif | |
3148 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
3149 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
3150 | case BFD_RELOC_PPC_BA26: | |
3151 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
3152 | case BFD_RELOC_PPC_EMB_NADDR32: | |
3153 | case BFD_RELOC_PPC_EMB_SDA21: | |
3154 | case BFD_RELOC_PPC_TLS: | |
3155 | case BFD_RELOC_PPC_TLSGD: | |
3156 | case BFD_RELOC_PPC_TLSLD: | |
3157 | case BFD_RELOC_PPC_VLE_HA16A: | |
3158 | case BFD_RELOC_PPC_VLE_HA16D: | |
3159 | case BFD_RELOC_PPC_VLE_HI16A: | |
3160 | case BFD_RELOC_PPC_VLE_HI16D: | |
3161 | case BFD_RELOC_PPC_VLE_LO16A: | |
3162 | case BFD_RELOC_PPC_VLE_LO16D: | |
3163 | case BFD_RELOC_PPC_VLE_SDA21: | |
3164 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
3165 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3166 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
3167 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3168 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
3169 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3170 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
c213164a | 3171 | case BFD_RELOC_PPC64_TLS_PCREL: |
0e2779e9 AM |
3172 | case BFD_RELOC_RVA: |
3173 | size = 4; | |
3174 | break; | |
3175 | ||
3176 | case BFD_RELOC_24_PLT_PCREL: | |
3177 | case BFD_RELOC_32_PCREL: | |
3178 | case BFD_RELOC_32_PLT_PCREL: | |
3179 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
3180 | #ifndef OBJ_XCOFF | |
3181 | case BFD_RELOC_PPC_B16: | |
3182 | #endif | |
3183 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3184 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3185 | case BFD_RELOC_PPC_B26: | |
3186 | case BFD_RELOC_PPC_LOCAL24PC: | |
3187 | case BFD_RELOC_PPC_REL16DX_HA: | |
3188 | case BFD_RELOC_PPC_VLE_REL15: | |
3189 | case BFD_RELOC_PPC_VLE_REL24: | |
3190 | size = 4; | |
3191 | pcrel = TRUE; | |
3192 | break; | |
3193 | ||
3194 | #ifndef OBJ_XCOFF | |
3195 | case BFD_RELOC_CTOR: | |
3196 | #endif | |
3197 | case BFD_RELOC_PPC_COPY: | |
3198 | case BFD_RELOC_PPC_DTPMOD: | |
3199 | case BFD_RELOC_PPC_DTPREL: | |
3200 | case BFD_RELOC_PPC_GLOB_DAT: | |
3201 | case BFD_RELOC_PPC_TPREL: | |
3202 | size = ppc_obj64 ? 8 : 4; | |
3203 | break; | |
3204 | ||
3205 | case BFD_RELOC_64: | |
3206 | case BFD_RELOC_64_PLTOFF: | |
3207 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
5663e321 AM |
3208 | case BFD_RELOC_PPC64_D28: |
3209 | case BFD_RELOC_PPC64_D34: | |
3210 | case BFD_RELOC_PPC64_D34_LO: | |
3211 | case BFD_RELOC_PPC64_D34_HI30: | |
3212 | case BFD_RELOC_PPC64_D34_HA30: | |
c213164a AM |
3213 | case BFD_RELOC_PPC64_TPREL34: |
3214 | case BFD_RELOC_PPC64_DTPREL34: | |
0e2779e9 AM |
3215 | case BFD_RELOC_PPC64_TOC: |
3216 | size = 8; | |
3217 | break; | |
3218 | ||
3219 | case BFD_RELOC_64_PCREL: | |
3220 | case BFD_RELOC_64_PLT_PCREL: | |
5663e321 | 3221 | case BFD_RELOC_PPC64_GOT_PCREL34: |
c213164a AM |
3222 | case BFD_RELOC_PPC64_GOT_TLSGD34: |
3223 | case BFD_RELOC_PPC64_GOT_TLSLD34: | |
3224 | case BFD_RELOC_PPC64_GOT_TPREL34: | |
3225 | case BFD_RELOC_PPC64_GOT_DTPREL34: | |
5663e321 AM |
3226 | case BFD_RELOC_PPC64_PCREL28: |
3227 | case BFD_RELOC_PPC64_PCREL34: | |
3228 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
0e2779e9 AM |
3229 | size = 8; |
3230 | pcrel = TRUE; | |
3231 | break; | |
3232 | ||
3233 | default: | |
3234 | abort (); | |
3235 | } | |
3236 | ||
3237 | if (ENABLE_CHECKING) | |
3238 | { | |
3239 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3240 | if (reloc_howto != NULL | |
3241 | && (size != bfd_get_reloc_size (reloc_howto) | |
3242 | || pcrel != reloc_howto->pc_relative)) | |
3243 | { | |
3244 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
3245 | reloc_howto->name); | |
3246 | abort (); | |
3247 | } | |
3248 | } | |
3249 | *pc_relative = pcrel; | |
3250 | return size; | |
3251 | } | |
3252 | ||
a894d76a | 3253 | #ifdef OBJ_ELF |
160eba93 AM |
3254 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3255 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3256 | is successfully parsed, *STR is updated past the trailing | |
3257 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3258 | reloc and arg expression. */ | |
3259 | ||
3260 | static int | |
3261 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3262 | { | |
3263 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3264 | if (sym_name[0] == '.') | |
3265 | ++sym_name; | |
3266 | ||
3267 | tls_fix->reloc = BFD_RELOC_NONE; | |
9e7028aa AM |
3268 | if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0 |
3269 | && (sym_name[14] == 0 | |
3270 | || strcasecmp (sym_name + 14, "_desc") == 0 | |
3271 | || strcasecmp (sym_name + 14, "_opt") == 0)) | |
160eba93 AM |
3272 | { |
3273 | char *hold = input_line_pointer; | |
3274 | input_line_pointer = *str + 1; | |
3275 | expression (&tls_fix->exp); | |
3276 | if (tls_fix->exp.X_op == O_symbol) | |
3277 | { | |
3278 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3279 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3280 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3281 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3282 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3283 | { | |
3284 | input_line_pointer += 7; | |
3285 | SKIP_WHITESPACE (); | |
3286 | *str = input_line_pointer; | |
3287 | } | |
3288 | } | |
3289 | input_line_pointer = hold; | |
3290 | } | |
3291 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3292 | } | |
a894d76a | 3293 | #endif |
160eba93 | 3294 | |
252b5132 RH |
3295 | /* This routine is called for each instruction to be assembled. */ |
3296 | ||
3297 | void | |
98027b10 | 3298 | md_assemble (char *str) |
252b5132 RH |
3299 | { |
3300 | char *s; | |
3301 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3302 | uint64_t insn; |
252b5132 | 3303 | const unsigned char *opindex_ptr; |
252b5132 RH |
3304 | int need_paren; |
3305 | int next_opindex; | |
3306 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3307 | int fc; | |
3308 | char *f; | |
a9479dc0 | 3309 | int addr_mask; |
252b5132 | 3310 | int i; |
b9c361e0 | 3311 | unsigned int insn_length; |
252b5132 RH |
3312 | |
3313 | /* Get the opcode. */ | |
3882b010 | 3314 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3315 | ; |
3316 | if (*s != '\0') | |
3317 | *s++ = '\0'; | |
3318 | ||
3319 | /* Look up the opcode in the hash table. */ | |
3320 | opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, str); | |
3321 | if (opcode == (const struct powerpc_opcode *) NULL) | |
3322 | { | |
3323 | const struct powerpc_macro *macro; | |
3324 | ||
3325 | macro = (const struct powerpc_macro *) hash_find (ppc_macro_hash, str); | |
3326 | if (macro == (const struct powerpc_macro *) NULL) | |
d6ed37ed | 3327 | as_bad (_("unrecognized opcode: `%s'"), str); |
252b5132 RH |
3328 | else |
3329 | ppc_macro (s, macro); | |
3330 | ||
dd7efa79 | 3331 | ppc_clear_labels (); |
252b5132 RH |
3332 | return; |
3333 | } | |
3334 | ||
3335 | insn = opcode->opcode; | |
3336 | ||
3337 | str = s; | |
3882b010 | 3338 | while (ISSPACE (*str)) |
252b5132 RH |
3339 | ++str; |
3340 | ||
3341 | /* PowerPC operands are just expressions. The only real issue is | |
9cf7e568 AM |
3342 | that a few operand types are optional. If an instruction has |
3343 | multiple optional operands and one is omitted, then all optional | |
3344 | operands past the first omitted one must also be omitted. */ | |
3345 | int num_optional_operands = 0; | |
3346 | int num_optional_provided = 0; | |
252b5132 RH |
3347 | |
3348 | /* Gather the operands. */ | |
3349 | need_paren = 0; | |
3350 | next_opindex = 0; | |
3351 | fc = 0; | |
3352 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3353 | { | |
3354 | const struct powerpc_operand *operand; | |
3355 | const char *errmsg; | |
3356 | char *hold; | |
3357 | expressionS ex; | |
3358 | char endc; | |
3359 | ||
3360 | if (next_opindex == 0) | |
3361 | operand = &powerpc_operands[*opindex_ptr]; | |
3362 | else | |
3363 | { | |
3364 | operand = &powerpc_operands[next_opindex]; | |
3365 | next_opindex = 0; | |
3366 | } | |
252b5132 RH |
3367 | errmsg = NULL; |
3368 | ||
252b5132 | 3369 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3370 | insert the default value, usually a zero. */ |
252b5132 | 3371 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3372 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3373 | { |
9cf7e568 AM |
3374 | if (num_optional_operands == 0) |
3375 | { | |
3376 | const unsigned char *optr; | |
3377 | int total = 0; | |
3378 | int provided = 0; | |
3379 | int omitted; | |
3380 | ||
3381 | s = str; | |
3382 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3383 | { | |
3384 | const struct powerpc_operand *op; | |
3385 | op = &powerpc_operands[*optr]; | |
3386 | ||
3387 | ++total; | |
3388 | ||
3389 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3390 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3391 | && ppc_obj64)) | |
3392 | ++num_optional_operands; | |
3393 | ||
3394 | if (s != NULL && *s != '\0') | |
3395 | { | |
3396 | ++provided; | |
3397 | ||
3398 | /* Look for the start of the next operand. */ | |
3399 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3400 | s = strpbrk (s, "(,"); | |
3401 | else | |
3402 | s = strchr (s, ','); | |
3403 | ||
3404 | if (s != NULL) | |
3405 | ++s; | |
3406 | } | |
3407 | } | |
3408 | omitted = total - provided; | |
3409 | num_optional_provided = num_optional_operands - omitted; | |
3410 | } | |
3411 | if (--num_optional_provided < 0) | |
252b5132 | 3412 | { |
9cf7e568 AM |
3413 | int64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3414 | num_optional_provided); | |
3415 | if (operand->insert) | |
3416 | { | |
3417 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3418 | if (errmsg != (const char *) NULL) | |
3419 | as_bad ("%s", errmsg); | |
3420 | } | |
3421 | else if (operand->shift >= 0) | |
3422 | insn |= (val & operand->bitm) << operand->shift; | |
3423 | else | |
3424 | insn |= (val & operand->bitm) >> -operand->shift; | |
3425 | ||
3426 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3427 | next_opindex = *opindex_ptr + 1; | |
3428 | continue; | |
252b5132 | 3429 | } |
252b5132 RH |
3430 | } |
3431 | ||
3432 | /* Gather the operand. */ | |
3433 | hold = input_line_pointer; | |
3434 | input_line_pointer = str; | |
3435 | ||
3436 | #ifdef TE_PE | |
81d4177b | 3437 | if (*input_line_pointer == '[') |
252b5132 RH |
3438 | { |
3439 | /* We are expecting something like the second argument here: | |
99a814a1 AM |
3440 | * |
3441 | * lwz r4,[toc].GS.0.static_int(rtoc) | |
3442 | * ^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
3443 | * The argument following the `]' must be a symbol name, and the | |
3444 | * register must be the toc register: 'rtoc' or '2' | |
3445 | * | |
3446 | * The effect is to 0 as the displacement field | |
3447 | * in the instruction, and issue an IMAGE_REL_PPC_TOCREL16 (or | |
3448 | * the appropriate variation) reloc against it based on the symbol. | |
3449 | * The linker will build the toc, and insert the resolved toc offset. | |
3450 | * | |
3451 | * Note: | |
3452 | * o The size of the toc entry is currently assumed to be | |
3453 | * 32 bits. This should not be assumed to be a hard coded | |
3454 | * number. | |
3455 | * o In an effort to cope with a change from 32 to 64 bits, | |
3456 | * there are also toc entries that are specified to be | |
3457 | * either 32 or 64 bits: | |
3458 | * lwz r4,[toc32].GS.0.static_int(rtoc) | |
3459 | * lwz r4,[toc64].GS.0.static_int(rtoc) | |
3460 | * These demand toc entries of the specified size, and the | |
3461 | * instruction probably requires it. | |
3462 | */ | |
252b5132 RH |
3463 | |
3464 | int valid_toc; | |
3465 | enum toc_size_qualifier toc_kind; | |
3466 | bfd_reloc_code_real_type toc_reloc; | |
3467 | ||
99a814a1 AM |
3468 | /* Go parse off the [tocXX] part. */ |
3469 | valid_toc = parse_toc_entry (&toc_kind); | |
252b5132 | 3470 | |
81d4177b | 3471 | if (!valid_toc) |
252b5132 | 3472 | { |
a5840dce AM |
3473 | ignore_rest_of_line (); |
3474 | break; | |
252b5132 RH |
3475 | } |
3476 | ||
99a814a1 AM |
3477 | /* Now get the symbol following the ']'. */ |
3478 | expression (&ex); | |
252b5132 RH |
3479 | |
3480 | switch (toc_kind) | |
3481 | { | |
3482 | case default_toc: | |
99a814a1 AM |
3483 | /* In this case, we may not have seen the symbol yet, |
3484 | since it is allowed to appear on a .extern or .globl | |
3485 | or just be a label in the .data section. */ | |
252b5132 RH |
3486 | toc_reloc = BFD_RELOC_PPC_TOC16; |
3487 | break; | |
3488 | case data_in_toc: | |
99a814a1 AM |
3489 | /* 1. The symbol must be defined and either in the toc |
3490 | section, or a global. | |
3491 | 2. The reloc generated must have the TOCDEFN flag set | |
3492 | in upper bit mess of the reloc type. | |
3493 | FIXME: It's a little confusing what the tocv | |
3494 | qualifier can be used for. At the very least, I've | |
3495 | seen three uses, only one of which I'm sure I can | |
3496 | explain. */ | |
81d4177b KH |
3497 | if (ex.X_op == O_symbol) |
3498 | { | |
9c2799c2 | 3499 | gas_assert (ex.X_add_symbol != NULL); |
fed9b18a ILT |
3500 | if (symbol_get_bfdsym (ex.X_add_symbol)->section |
3501 | != tocdata_section) | |
252b5132 | 3502 | { |
99a814a1 | 3503 | as_bad (_("[tocv] symbol is not a toc symbol")); |
252b5132 RH |
3504 | } |
3505 | } | |
3506 | ||
3507 | toc_reloc = BFD_RELOC_PPC_TOC16; | |
3508 | break; | |
3509 | case must_be_32: | |
99a814a1 AM |
3510 | /* FIXME: these next two specifically specify 32/64 bit |
3511 | toc entries. We don't support them today. Is this | |
3512 | the right way to say that? */ | |
62ebcb5c | 3513 | toc_reloc = BFD_RELOC_NONE; |
d6ed37ed | 3514 | as_bad (_("unimplemented toc32 expression modifier")); |
252b5132 RH |
3515 | break; |
3516 | case must_be_64: | |
99a814a1 | 3517 | /* FIXME: see above. */ |
62ebcb5c | 3518 | toc_reloc = BFD_RELOC_NONE; |
d6ed37ed | 3519 | as_bad (_("unimplemented toc64 expression modifier")); |
252b5132 RH |
3520 | break; |
3521 | default: | |
bc805888 | 3522 | fprintf (stderr, |
99a814a1 AM |
3523 | _("Unexpected return value [%d] from parse_toc_entry!\n"), |
3524 | toc_kind); | |
bc805888 | 3525 | abort (); |
252b5132 RH |
3526 | break; |
3527 | } | |
3528 | ||
3529 | /* We need to generate a fixup for this expression. */ | |
3530 | if (fc >= MAX_INSN_FIXUPS) | |
3531 | as_fatal (_("too many fixups")); | |
3532 | ||
3533 | fixups[fc].reloc = toc_reloc; | |
3534 | fixups[fc].exp = ex; | |
3535 | fixups[fc].opindex = *opindex_ptr; | |
3536 | ++fc; | |
3537 | ||
99a814a1 AM |
3538 | /* Ok. We've set up the fixup for the instruction. Now make it |
3539 | look like the constant 0 was found here. */ | |
252b5132 RH |
3540 | ex.X_unsigned = 1; |
3541 | ex.X_op = O_constant; | |
3542 | ex.X_add_number = 0; | |
3543 | ex.X_add_symbol = NULL; | |
3544 | ex.X_op_symbol = NULL; | |
3545 | } | |
3546 | ||
3547 | else | |
3548 | #endif /* TE_PE */ | |
3549 | { | |
b9c361e0 JL |
3550 | if ((reg_names_p |
3551 | && (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
3552 | || ((operand->flags & PPC_OPERAND_CR_REG) != 0))) | |
2ad068be | 3553 | || !register_name (&ex)) |
252b5132 | 3554 | { |
13abbae3 AM |
3555 | char save_lex = lex_type['%']; |
3556 | ||
b9c361e0 JL |
3557 | if (((operand->flags & PPC_OPERAND_CR_REG) != 0) |
3558 | || (operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
13abbae3 AM |
3559 | { |
3560 | cr_operand = TRUE; | |
3561 | lex_type['%'] |= LEX_BEGIN_NAME; | |
3562 | } | |
252b5132 | 3563 | expression (&ex); |
b34976b6 | 3564 | cr_operand = FALSE; |
13abbae3 | 3565 | lex_type['%'] = save_lex; |
252b5132 RH |
3566 | } |
3567 | } | |
3568 | ||
3569 | str = input_line_pointer; | |
3570 | input_line_pointer = hold; | |
3571 | ||
3572 | if (ex.X_op == O_illegal) | |
3573 | as_bad (_("illegal operand")); | |
3574 | else if (ex.X_op == O_absent) | |
3575 | as_bad (_("missing operand")); | |
3576 | else if (ex.X_op == O_register) | |
3577 | { | |
7e0de605 AM |
3578 | if ((ex.X_md |
3579 | & ~operand->flags | |
3580 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3581 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
aa3c112f | 3582 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0 |
7e0de605 AM |
3583 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 |
3584 | && ex.X_add_number != 0 | |
3585 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3586 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3587 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3588 | ppc_cpu, (char *) NULL, 0); |
252b5132 RH |
3589 | } |
3590 | else if (ex.X_op == O_constant) | |
3591 | { | |
3592 | #ifdef OBJ_ELF | |
81d4177b | 3593 | /* Allow @HA, @L, @H on constants. */ |
3b8b57a9 | 3594 | bfd_reloc_code_real_type reloc; |
252b5132 RH |
3595 | char *orig_str = str; |
3596 | ||
62ebcb5c | 3597 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
252b5132 RH |
3598 | switch (reloc) |
3599 | { | |
3600 | default: | |
3601 | str = orig_str; | |
3602 | break; | |
3603 | ||
3604 | case BFD_RELOC_LO16: | |
f9c6b907 AM |
3605 | ex.X_add_number &= 0xffff; |
3606 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
0baf16f2 | 3607 | ex.X_add_number = SEX16 (ex.X_add_number); |
252b5132 RH |
3608 | break; |
3609 | ||
3610 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3611 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3612 | { | |
3613 | /* PowerPC64 @h is tested for overflow. */ | |
3614 | ex.X_add_number = (addressT) ex.X_add_number >> 16; | |
3615 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3616 | { | |
3617 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3618 | ex.X_add_number | |
3619 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3620 | } | |
3621 | break; | |
3622 | } | |
2b0f3761 | 3623 | /* Fallthru */ |
f9c6b907 AM |
3624 | |
3625 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3626 | ex.X_add_number = PPC_HI (ex.X_add_number); | |
3627 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3628 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 RH |
3629 | break; |
3630 | ||
3631 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3632 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3633 | { | |
3634 | /* PowerPC64 @ha is tested for overflow. */ | |
3635 | ex.X_add_number | |
3636 | = ((addressT) ex.X_add_number + 0x8000) >> 16; | |
3637 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3638 | { | |
3639 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3640 | ex.X_add_number | |
3641 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3642 | } | |
3643 | break; | |
3644 | } | |
2b0f3761 | 3645 | /* Fallthru */ |
f9c6b907 AM |
3646 | |
3647 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
3648 | ex.X_add_number = PPC_HA (ex.X_add_number); | |
3649 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3650 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3651 | break; |
3652 | ||
0baf16f2 | 3653 | case BFD_RELOC_PPC64_HIGHER: |
f9c6b907 AM |
3654 | ex.X_add_number = PPC_HIGHER (ex.X_add_number); |
3655 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3656 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3657 | break; |
3658 | ||
3659 | case BFD_RELOC_PPC64_HIGHER_S: | |
f9c6b907 AM |
3660 | ex.X_add_number = PPC_HIGHERA (ex.X_add_number); |
3661 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3662 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 | 3663 | break; |
0baf16f2 AM |
3664 | |
3665 | case BFD_RELOC_PPC64_HIGHEST: | |
f9c6b907 AM |
3666 | ex.X_add_number = PPC_HIGHEST (ex.X_add_number); |
3667 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3668 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3669 | break; |
3670 | ||
3671 | case BFD_RELOC_PPC64_HIGHEST_S: | |
f9c6b907 AM |
3672 | ex.X_add_number = PPC_HIGHESTA (ex.X_add_number); |
3673 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3674 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 | 3675 | break; |
252b5132 | 3676 | } |
0baf16f2 | 3677 | #endif /* OBJ_ELF */ |
252b5132 | 3678 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3679 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3680 | } |
727fc41e | 3681 | else |
252b5132 | 3682 | { |
62ebcb5c | 3683 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3684 | #ifdef OBJ_ELF |
160eba93 AM |
3685 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3686 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3687 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3688 | { |
160eba93 AM |
3689 | fixups[fc].opindex = *opindex_ptr; |
3690 | ++fc; | |
252b5132 RH |
3691 | } |
3692 | ||
62ebcb5c | 3693 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3694 | { |
b9c361e0 JL |
3695 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3696 | if (opcode->flags & PPC_OPCODE_VLE) | |
3697 | { | |
0f873fd5 | 3698 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3699 | |
08dc996f | 3700 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3701 | || tmp_insn == E_AND2I_DOT_INSN |
3702 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3703 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3704 | || tmp_insn == E_LIS_INSN |
3705 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3706 | ||
3707 | ||
08dc996f | 3708 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3709 | || tmp_insn == E_ADD2IS_INSN |
3710 | || tmp_insn == E_CMP16I_INSN | |
3711 | || tmp_insn == E_MULL2I_INSN | |
3712 | || tmp_insn == E_CMPL16I_INSN | |
3713 | || tmp_insn == E_CMPH16I_INSN | |
3714 | || tmp_insn == E_CMPHL16I_INSN); | |
3715 | ||
3716 | switch (reloc) | |
3717 | { | |
3718 | default: | |
3719 | break; | |
3720 | ||
3721 | case BFD_RELOC_PPC_EMB_SDA21: | |
3722 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3723 | break; | |
3724 | ||
3725 | case BFD_RELOC_LO16: | |
3726 | if (use_d_reloc) | |
3727 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3728 | else if (use_a_reloc) | |
3729 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3730 | break; | |
3731 | ||
3732 | case BFD_RELOC_HI16: | |
3733 | if (use_d_reloc) | |
3734 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3735 | else if (use_a_reloc) | |
3736 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3737 | break; | |
3739860c | 3738 | |
b9c361e0 JL |
3739 | case BFD_RELOC_HI16_S: |
3740 | if (use_d_reloc) | |
3741 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3742 | else if (use_a_reloc) | |
3743 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3744 | break; | |
3745 | ||
3746 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3747 | if (use_d_reloc) | |
3748 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3749 | break; | |
3750 | ||
3751 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3752 | if (use_d_reloc) | |
3753 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3754 | break; | |
3755 | ||
3756 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3757 | if (use_d_reloc) | |
3758 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3759 | break; | |
3760 | } | |
3761 | } | |
bb6bf75e AM |
3762 | |
3763 | /* TLS and other tweaks. */ | |
3764 | switch (reloc) | |
3765 | { | |
3766 | default: | |
3767 | break; | |
3768 | ||
3769 | case BFD_RELOC_PPC_TLS: | |
c213164a | 3770 | case BFD_RELOC_PPC64_TLS_PCREL: |
bb6bf75e AM |
3771 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) |
3772 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3773 | opcode->name); | |
3774 | else if (operand->shift != 11) | |
3775 | as_bad (_("@tls may only be used in last operand")); | |
3776 | else | |
3777 | insn = ppc_insert_operand (insn, operand, | |
3778 | ppc_obj64 ? 13 : 2, | |
3779 | ppc_cpu, (char *) NULL, 0); | |
3780 | break; | |
3781 | ||
3782 | /* We'll only use the 32 (or 64) bit form of these relocations | |
c213164a | 3783 | in constants. Instructions get the 16 or 34 bit form. */ |
bb6bf75e | 3784 | case BFD_RELOC_PPC_DTPREL: |
c213164a AM |
3785 | if (operand->bitm == 0x3ffffffffULL) |
3786 | reloc = BFD_RELOC_PPC64_DTPREL34; | |
3787 | else | |
3788 | reloc = BFD_RELOC_PPC_DTPREL16; | |
bb6bf75e AM |
3789 | break; |
3790 | ||
3791 | case BFD_RELOC_PPC_TPREL: | |
c213164a AM |
3792 | if (operand->bitm == 0x3ffffffffULL) |
3793 | reloc = BFD_RELOC_PPC64_TPREL34; | |
3794 | else | |
3795 | reloc = BFD_RELOC_PPC_TPREL16; | |
bb6bf75e AM |
3796 | break; |
3797 | ||
5663e321 AM |
3798 | case BFD_RELOC_PPC64_PCREL34: |
3799 | if (operand->bitm == 0xfffffffULL) | |
3800 | { | |
3801 | reloc = BFD_RELOC_PPC64_PCREL28; | |
3802 | break; | |
3803 | } | |
3804 | /* Fall through. */ | |
3805 | case BFD_RELOC_PPC64_GOT_PCREL34: | |
3806 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
c213164a AM |
3807 | case BFD_RELOC_PPC64_GOT_TLSGD34: |
3808 | case BFD_RELOC_PPC64_GOT_TLSLD34: | |
3809 | case BFD_RELOC_PPC64_GOT_TPREL34: | |
3810 | case BFD_RELOC_PPC64_GOT_DTPREL34: | |
5663e321 | 3811 | if (operand->bitm != 0x3ffffffffULL |
bb6bf75e | 3812 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
5663e321 AM |
3813 | as_warn (_("%s unsupported on this instruction"), "@pcrel"); |
3814 | break; | |
3815 | ||
3816 | case BFD_RELOC_LO16: | |
3817 | if (operand->bitm == 0x3ffffffffULL | |
3818 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3819 | reloc = BFD_RELOC_PPC64_D34_LO; | |
3820 | else if ((operand->bitm | 0xf) != 0xffff | |
3821 | || operand->shift != 0 | |
3822 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3823 | as_warn (_("%s unsupported on this instruction"), "@l"); |
3824 | break; | |
3825 | ||
3826 | case BFD_RELOC_HI16: | |
5663e321 AM |
3827 | if (operand->bitm == 0x3ffffffffULL |
3828 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3829 | reloc = BFD_RELOC_PPC64_D34_HI30; | |
3830 | else if (operand->bitm != 0xffff | |
3831 | || operand->shift != 0 | |
3832 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3833 | as_warn (_("%s unsupported on this instruction"), "@h"); |
3834 | break; | |
3835 | ||
3836 | case BFD_RELOC_HI16_S: | |
5663e321 AM |
3837 | if (operand->bitm == 0x3ffffffffULL |
3838 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3839 | reloc = BFD_RELOC_PPC64_D34_HA30; | |
3840 | else if (operand->bitm == 0xffff | |
3841 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3842 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
bb6bf75e AM |
3843 | /* addpcis. */ |
3844 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3845 | else if (operand->bitm != 0xffff | |
3846 | || operand->shift != 0 | |
3847 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3848 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3849 | } | |
0baf16f2 | 3850 | } |
3b8b57a9 AM |
3851 | #endif /* OBJ_ELF */ |
3852 | ||
62ebcb5c | 3853 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3854 | ; |
3855 | /* Determine a BFD reloc value based on the operand information. | |
3856 | We are only prepared to turn a few of the operands into | |
3857 | relocs. */ | |
a0593ad9 AM |
3858 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3859 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3860 | && operand->bitm == 0x3fffffc |
3861 | && operand->shift == 0) | |
3862 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3863 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3864 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3865 | && operand->bitm == 0xfffc |
3866 | && operand->shift == 0) | |
3867 | reloc = BFD_RELOC_PPC_B16; | |
3868 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3869 | && operand->bitm == 0x1fe | |
3870 | && operand->shift == -1) | |
3871 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3872 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3873 | && operand->bitm == 0xfffe | |
3874 | && operand->shift == 0) | |
3875 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3876 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3877 | && operand->bitm == 0x1fffffe | |
3878 | && operand->shift == 0) | |
3879 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3880 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3881 | && (operand->bitm & 0xfff0) == 0xfff0 |
3882 | && operand->shift == 0) | |
3883 | { | |
f50c47f1 | 3884 | reloc = BFD_RELOC_16; |
3e60bf4d | 3885 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3886 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3887 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3888 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3889 | { |
3890 | reloc = BFD_RELOC_PPC_TOC16; | |
3891 | #ifdef OBJ_ELF | |
3892 | as_warn (_("assuming %s on symbol"), | |
3893 | ppc_obj64 ? "@toc" : "@xgot"); | |
3894 | #endif | |
3895 | } | |
3b8b57a9 | 3896 | #endif |
3b8b57a9 | 3897 | } |
5663e321 AM |
3898 | else if (operand->bitm == 0x3ffffffffULL) |
3899 | reloc = BFD_RELOC_PPC64_D34; | |
3900 | else if (operand->bitm == 0xfffffffULL) | |
3901 | reloc = BFD_RELOC_PPC64_D28; | |
a0593ad9 AM |
3902 | |
3903 | /* For the absolute forms of branches, convert the PC | |
3904 | relative form back into the absolute. */ | |
3905 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3906 | { | |
3907 | switch (reloc) | |
3908 | { | |
3909 | case BFD_RELOC_PPC_B26: | |
3910 | reloc = BFD_RELOC_PPC_BA26; | |
3911 | break; | |
3912 | case BFD_RELOC_PPC_B16: | |
3913 | reloc = BFD_RELOC_PPC_BA16; | |
3914 | break; | |
3915 | #ifdef OBJ_ELF | |
3916 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3917 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3918 | break; | |
3919 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3920 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3921 | break; | |
3922 | #endif | |
3923 | default: | |
3924 | break; | |
3925 | } | |
3926 | } | |
3927 | ||
3928 | #ifdef OBJ_ELF | |
3929 | switch (reloc) | |
3930 | { | |
3931 | case BFD_RELOC_PPC_TOC16: | |
3932 | toc_reloc_types |= has_small_toc_reloc; | |
3933 | break; | |
3934 | case BFD_RELOC_PPC64_TOC16_LO: | |
3935 | case BFD_RELOC_PPC64_TOC16_HI: | |
3936 | case BFD_RELOC_PPC64_TOC16_HA: | |
3937 | toc_reloc_types |= has_large_toc_reloc; | |
3938 | break; | |
3939 | default: | |
3940 | break; | |
3941 | } | |
3942 | ||
3943 | if (ppc_obj64 | |
3944 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3945 | { | |
3946 | switch (reloc) | |
3947 | { | |
3948 | case BFD_RELOC_16: | |
3949 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3950 | break; | |
5663e321 | 3951 | |
a0593ad9 AM |
3952 | case BFD_RELOC_LO16: |
3953 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3954 | break; | |
5663e321 | 3955 | |
a0593ad9 AM |
3956 | case BFD_RELOC_16_GOTOFF: |
3957 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3958 | break; | |
5663e321 | 3959 | |
a0593ad9 AM |
3960 | case BFD_RELOC_LO16_GOTOFF: |
3961 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3962 | break; | |
5663e321 | 3963 | |
a0593ad9 AM |
3964 | case BFD_RELOC_LO16_PLTOFF: |
3965 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3966 | break; | |
5663e321 | 3967 | |
a0593ad9 AM |
3968 | case BFD_RELOC_16_BASEREL: |
3969 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3970 | break; | |
5663e321 | 3971 | |
a0593ad9 AM |
3972 | case BFD_RELOC_LO16_BASEREL: |
3973 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3974 | break; | |
5663e321 | 3975 | |
a0593ad9 AM |
3976 | case BFD_RELOC_PPC_TOC16: |
3977 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3978 | break; | |
5663e321 | 3979 | |
a0593ad9 AM |
3980 | case BFD_RELOC_PPC64_TOC16_LO: |
3981 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3982 | break; | |
5663e321 | 3983 | |
a0593ad9 AM |
3984 | case BFD_RELOC_PPC64_PLTGOT16: |
3985 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3986 | break; | |
5663e321 | 3987 | |
a0593ad9 AM |
3988 | case BFD_RELOC_PPC64_PLTGOT16_LO: |
3989 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3990 | break; | |
5663e321 | 3991 | |
a0593ad9 AM |
3992 | case BFD_RELOC_PPC_DTPREL16: |
3993 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3994 | break; | |
5663e321 | 3995 | |
a0593ad9 AM |
3996 | case BFD_RELOC_PPC_DTPREL16_LO: |
3997 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
3998 | break; | |
5663e321 | 3999 | |
a0593ad9 AM |
4000 | case BFD_RELOC_PPC_TPREL16: |
4001 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
4002 | break; | |
5663e321 | 4003 | |
a0593ad9 AM |
4004 | case BFD_RELOC_PPC_TPREL16_LO: |
4005 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
4006 | break; | |
5663e321 | 4007 | |
a0593ad9 AM |
4008 | case BFD_RELOC_PPC_GOT_DTPREL16: |
4009 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
4010 | case BFD_RELOC_PPC_GOT_TPREL16: | |
4011 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
4012 | break; | |
5663e321 | 4013 | |
a0593ad9 AM |
4014 | default: |
4015 | as_bad (_("unsupported relocation for DS offset field")); | |
4016 | break; | |
4017 | } | |
4018 | } | |
160eba93 AM |
4019 | |
4020 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
4021 | modifiers like @plt. This fixup must be emitted before | |
4022 | the usual call fixup. */ | |
4023 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
4024 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
4025 | { | |
4026 | fixups[fc].opindex = *opindex_ptr; | |
4027 | ++fc; | |
4028 | } | |
a0593ad9 | 4029 | #endif |
0baf16f2 | 4030 | |
252b5132 RH |
4031 | /* We need to generate a fixup for this expression. */ |
4032 | if (fc >= MAX_INSN_FIXUPS) | |
4033 | as_fatal (_("too many fixups")); | |
4034 | fixups[fc].exp = ex; | |
727fc41e | 4035 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
4036 | fixups[fc].reloc = reloc; |
4037 | ++fc; | |
4038 | } | |
252b5132 RH |
4039 | |
4040 | if (need_paren) | |
4041 | { | |
4042 | endc = ')'; | |
4043 | need_paren = 0; | |
c3d65c1c BE |
4044 | /* If expecting more operands, then we want to see "),". */ |
4045 | if (*str == endc && opindex_ptr[1] != 0) | |
4046 | { | |
4047 | do | |
4048 | ++str; | |
4049 | while (ISSPACE (*str)); | |
4050 | endc = ','; | |
4051 | } | |
252b5132 RH |
4052 | } |
4053 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 4054 | endc = '('; |
252b5132 RH |
4055 | else |
4056 | endc = ','; | |
4057 | ||
4058 | /* The call to expression should have advanced str past any | |
4059 | whitespace. */ | |
9cf7e568 | 4060 | if (*str == endc) |
252b5132 | 4061 | { |
9cf7e568 AM |
4062 | ++str; |
4063 | if (endc == '(') | |
4064 | need_paren = 1; | |
4065 | } | |
4066 | else if (*str != '\0') | |
4067 | { | |
4068 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
4069 | break; | |
4070 | } | |
4071 | else if (endc == ')') | |
4072 | { | |
4073 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
4074 | break; |
4075 | } | |
252b5132 RH |
4076 | } |
4077 | ||
3882b010 | 4078 | while (ISSPACE (*str)) |
252b5132 RH |
4079 | ++str; |
4080 | ||
4081 | if (*str != '\0') | |
4082 | as_bad (_("junk at end of line: `%s'"), str); | |
4083 | ||
dc1d03fc | 4084 | #ifdef OBJ_ELF |
b9c361e0 | 4085 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
4086 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
4087 | && !ppc_obj64) | |
6a0c61b7 EZ |
4088 | { |
4089 | /* These are all version "1". */ | |
4090 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 4091 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 4092 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 4093 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 4094 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 4095 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 4096 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 4097 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 4098 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 4099 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 4100 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 4101 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 4102 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 4103 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
4104 | /* Only set the VLE flag if the instruction has been pulled via |
4105 | the VLE instruction set. This way the flag is guaranteed to | |
4106 | be set for VLE-only instructions or for VLE-only processors, | |
4107 | however it'll remain clear for dual-mode instructions on | |
4108 | dual-mode and, more importantly, standard-mode processors. */ | |
4109 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
4110 | { |
4111 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
4112 | if (elf_section_data (now_seg) != NULL) | |
4113 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
4114 | } | |
6a0c61b7 | 4115 | } |
dc1d03fc | 4116 | #endif |
6a0c61b7 | 4117 | |
252b5132 | 4118 | /* Write out the instruction. */ |
a9479dc0 AM |
4119 | |
4120 | addr_mask = 3; | |
f7d69005 | 4121 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
4122 | /* All instructions can start on a 2 byte boundary for VLE. */ |
4123 | addr_mask = 1; | |
4124 | ||
4125 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 4126 | { |
a9479dc0 AM |
4127 | /* Don't emit instructions to a frag started for data, or for a |
4128 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
4129 | and it's possible to start a new frag in the middle of | |
4130 | misaligned data. */ | |
4131 | frag_wane (frag_now); | |
4132 | frag_new (0); | |
b9c361e0 | 4133 | } |
a9479dc0 AM |
4134 | |
4135 | /* Check that insns within the frag are aligned. ppc_frag_check | |
4136 | will ensure that the frag start address is aligned. */ | |
4137 | if ((frag_now_fix () & addr_mask) != 0) | |
4138 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
4139 | ||
dd7efa79 | 4140 | /* Differentiate between two, four, and eight byte insns. */ |
a9479dc0 AM |
4141 | insn_length = 4; |
4142 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
4143 | insn_length = 2; | |
7c1f4227 | 4144 | else if ((opcode->flags & PPC_OPCODE_POWER10) != 0 |
dd7efa79 PB |
4145 | && PPC_PREFIX_P (insn)) |
4146 | { | |
4147 | struct insn_label_list *l; | |
4148 | ||
4149 | insn_length = 8; | |
4150 | ||
4151 | /* 8-byte prefix instructions are not allowed to cross 64-byte | |
4152 | boundaries. */ | |
4153 | frag_align_code (6, 4); | |
4154 | record_alignment (now_seg, 6); | |
4155 | ||
4156 | /* Update "dot" in any expressions used by this instruction, and | |
4157 | a label attached to the instruction. By "attached" we mean | |
4158 | on the same source line as the instruction and without any | |
4159 | intervening semicolons. */ | |
4160 | dot_value = frag_now_fix (); | |
4161 | dot_frag = frag_now; | |
4162 | for (l = insn_labels; l != NULL; l = l->next) | |
4163 | { | |
4164 | symbol_set_frag (l->label, dot_frag); | |
4165 | S_SET_VALUE (l->label, dot_value); | |
4166 | } | |
4167 | } | |
4168 | ||
4169 | ppc_clear_labels (); | |
a9479dc0 | 4170 | |
b9c361e0 | 4171 | f = frag_more (insn_length); |
a9479dc0 | 4172 | frag_now->insn_addr = addr_mask; |
dd7efa79 PB |
4173 | |
4174 | /* The prefix part of an 8-byte instruction always occupies the lower | |
4175 | addressed word in a doubleword, regardless of endianness. */ | |
4176 | if (!target_big_endian && insn_length == 8) | |
4177 | { | |
4178 | md_number_to_chars (f, PPC_GET_PREFIX (insn), 4); | |
4179 | md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4); | |
4180 | } | |
4181 | else | |
4182 | md_number_to_chars (f, insn, insn_length); | |
4183 | ||
bf7279d5 AM |
4184 | last_insn = insn; |
4185 | last_seg = now_seg; | |
4186 | last_subseg = now_subseg; | |
252b5132 | 4187 | |
5d6f4f16 | 4188 | #ifdef OBJ_ELF |
b9c361e0 | 4189 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
4190 | #endif |
4191 | ||
3b8b57a9 | 4192 | /* Create any fixups. */ |
252b5132 RH |
4193 | for (i = 0; i < fc; i++) |
4194 | { | |
3b8b57a9 | 4195 | fixS *fixP; |
62ebcb5c | 4196 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 4197 | { |
0e2779e9 AM |
4198 | bfd_boolean pcrel; |
4199 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); | |
4200 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 4201 | |
99a814a1 AM |
4202 | fixP = fix_new_exp (frag_now, |
4203 | f - frag_now->fr_literal + offset, | |
4204 | size, | |
4205 | &fixups[i].exp, | |
0e2779e9 | 4206 | pcrel, |
252b5132 | 4207 | fixups[i].reloc); |
252b5132 RH |
4208 | } |
4209 | else | |
727fc41e AM |
4210 | { |
4211 | const struct powerpc_operand *operand; | |
4212 | ||
4213 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
4214 | fixP = fix_new_exp (frag_now, |
4215 | f - frag_now->fr_literal, | |
4216 | insn_length, | |
4217 | &fixups[i].exp, | |
4218 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 4219 | BFD_RELOC_NONE); |
727fc41e | 4220 | } |
3b8b57a9 | 4221 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
4222 | } |
4223 | } | |
4224 | ||
4225 | /* Handle a macro. Gather all the operands, transform them as | |
4226 | described by the macro, and call md_assemble recursively. All the | |
4227 | operands are separated by commas; we don't accept parentheses | |
4228 | around operands here. */ | |
4229 | ||
4230 | static void | |
98027b10 | 4231 | ppc_macro (char *str, const struct powerpc_macro *macro) |
252b5132 RH |
4232 | { |
4233 | char *operands[10]; | |
4234 | unsigned int count; | |
4235 | char *s; | |
4236 | unsigned int len; | |
4237 | const char *format; | |
db557034 | 4238 | unsigned int arg; |
252b5132 RH |
4239 | char *send; |
4240 | char *complete; | |
4241 | ||
4242 | /* Gather the users operands into the operands array. */ | |
4243 | count = 0; | |
4244 | s = str; | |
4245 | while (1) | |
4246 | { | |
4247 | if (count >= sizeof operands / sizeof operands[0]) | |
4248 | break; | |
4249 | operands[count++] = s; | |
4250 | s = strchr (s, ','); | |
4251 | if (s == (char *) NULL) | |
4252 | break; | |
4253 | *s++ = '\0'; | |
81d4177b | 4254 | } |
252b5132 RH |
4255 | |
4256 | if (count != macro->operands) | |
4257 | { | |
4258 | as_bad (_("wrong number of operands")); | |
4259 | return; | |
4260 | } | |
4261 | ||
4262 | /* Work out how large the string must be (the size is unbounded | |
4263 | because it includes user input). */ | |
4264 | len = 0; | |
4265 | format = macro->format; | |
4266 | while (*format != '\0') | |
4267 | { | |
4268 | if (*format != '%') | |
4269 | { | |
4270 | ++len; | |
4271 | ++format; | |
4272 | } | |
4273 | else | |
4274 | { | |
4275 | arg = strtol (format + 1, &send, 10); | |
db557034 | 4276 | know (send != format && arg < count); |
252b5132 RH |
4277 | len += strlen (operands[arg]); |
4278 | format = send; | |
4279 | } | |
4280 | } | |
4281 | ||
4282 | /* Put the string together. */ | |
325801bd | 4283 | complete = s = XNEWVEC (char, len + 1); |
252b5132 RH |
4284 | format = macro->format; |
4285 | while (*format != '\0') | |
4286 | { | |
4287 | if (*format != '%') | |
4288 | *s++ = *format++; | |
4289 | else | |
4290 | { | |
4291 | arg = strtol (format + 1, &send, 10); | |
4292 | strcpy (s, operands[arg]); | |
4293 | s += strlen (s); | |
4294 | format = send; | |
4295 | } | |
4296 | } | |
4297 | *s = '\0'; | |
4298 | ||
4299 | /* Assemble the constructed instruction. */ | |
4300 | md_assemble (complete); | |
e1fa0163 | 4301 | free (complete); |
81d4177b | 4302 | } |
252b5132 RH |
4303 | \f |
4304 | #ifdef OBJ_ELF | |
18ae9cc1 | 4305 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
4306 | |
4307 | int | |
98027b10 | 4308 | ppc_section_type (char *str, size_t len) |
252b5132 | 4309 | { |
9de8d8f1 RH |
4310 | if (len == 7 && strncmp (str, "ordered", 7) == 0) |
4311 | return SHT_ORDERED; | |
252b5132 | 4312 | |
9de8d8f1 | 4313 | return -1; |
252b5132 RH |
4314 | } |
4315 | ||
4316 | int | |
1239de13 | 4317 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
4318 | { |
4319 | if (type == SHT_ORDERED) | |
4320 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
4321 | ||
252b5132 RH |
4322 | return flags; |
4323 | } | |
83eef883 AFB |
4324 | |
4325 | bfd_vma | |
4326 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
4327 | { | |
4328 | if (letter == 'v') | |
4329 | return SHF_PPC_VLE; | |
4330 | ||
4331 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
4332 | return -1; | |
4333 | } | |
252b5132 RH |
4334 | #endif /* OBJ_ELF */ |
4335 | ||
4336 | \f | |
4337 | /* Pseudo-op handling. */ | |
4338 | ||
4339 | /* The .byte pseudo-op. This is similar to the normal .byte | |
4340 | pseudo-op, but it can also take a single ASCII string. */ | |
4341 | ||
4342 | static void | |
98027b10 | 4343 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 4344 | { |
bf7279d5 AM |
4345 | int count = 0; |
4346 | ||
252b5132 RH |
4347 | if (*input_line_pointer != '\"') |
4348 | { | |
4349 | cons (1); | |
4350 | return; | |
4351 | } | |
4352 | ||
4353 | /* Gather characters. A real double quote is doubled. Unusual | |
4354 | characters are not permitted. */ | |
4355 | ++input_line_pointer; | |
4356 | while (1) | |
4357 | { | |
4358 | char c; | |
4359 | ||
4360 | c = *input_line_pointer++; | |
4361 | ||
4362 | if (c == '\"') | |
4363 | { | |
4364 | if (*input_line_pointer != '\"') | |
4365 | break; | |
4366 | ++input_line_pointer; | |
4367 | } | |
4368 | ||
4369 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4370 | ++count; |
252b5132 RH |
4371 | } |
4372 | ||
bf7279d5 AM |
4373 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4374 | as_warn (_("data in executable section")); | |
252b5132 RH |
4375 | demand_empty_rest_of_line (); |
4376 | } | |
4377 | \f | |
4378 | #ifdef OBJ_XCOFF | |
4379 | ||
4380 | /* XCOFF specific pseudo-op handling. */ | |
4381 | ||
4382 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4383 | to handle symbol suffixes for such symbols. */ | |
b34976b6 | 4384 | static bfd_boolean ppc_stab_symbol; |
252b5132 RH |
4385 | |
4386 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common | |
4387 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4388 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1ad63b2f | 4389 | aligns .comm and .lcomm to 4 bytes. */ |
252b5132 RH |
4390 | |
4391 | static void | |
98027b10 | 4392 | ppc_comm (int lcomm) |
252b5132 RH |
4393 | { |
4394 | asection *current_seg = now_seg; | |
4395 | subsegT current_subseg = now_subseg; | |
4396 | char *name; | |
4397 | char endc; | |
4398 | char *end_name; | |
4399 | offsetT size; | |
4400 | offsetT align; | |
4401 | symbolS *lcomm_sym = NULL; | |
4402 | symbolS *sym; | |
4403 | char *pfrag; | |
4404 | ||
d02603dc | 4405 | endc = get_symbol_name (&name); |
252b5132 | 4406 | end_name = input_line_pointer; |
d02603dc | 4407 | (void) restore_line_pointer (endc); |
252b5132 RH |
4408 | |
4409 | if (*input_line_pointer != ',') | |
4410 | { | |
4411 | as_bad (_("missing size")); | |
4412 | ignore_rest_of_line (); | |
4413 | return; | |
4414 | } | |
4415 | ++input_line_pointer; | |
4416 | ||
4417 | size = get_absolute_expression (); | |
4418 | if (size < 0) | |
4419 | { | |
4420 | as_bad (_("negative size")); | |
4421 | ignore_rest_of_line (); | |
4422 | return; | |
4423 | } | |
4424 | ||
4425 | if (! lcomm) | |
4426 | { | |
4427 | /* The third argument to .comm is the alignment. */ | |
4428 | if (*input_line_pointer != ',') | |
1ad63b2f | 4429 | align = 2; |
252b5132 RH |
4430 | else |
4431 | { | |
4432 | ++input_line_pointer; | |
4433 | align = get_absolute_expression (); | |
4434 | if (align <= 0) | |
4435 | { | |
4436 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4437 | align = 2; |
252b5132 RH |
4438 | } |
4439 | } | |
4440 | } | |
4441 | else | |
4442 | { | |
4443 | char *lcomm_name; | |
4444 | char lcomm_endc; | |
4445 | ||
252b5132 RH |
4446 | /* The third argument to .lcomm appears to be the real local |
4447 | common symbol to create. References to the symbol named in | |
4448 | the first argument are turned into references to the third | |
4449 | argument. */ | |
4450 | if (*input_line_pointer != ',') | |
4451 | { | |
4452 | as_bad (_("missing real symbol name")); | |
4453 | ignore_rest_of_line (); | |
4454 | return; | |
4455 | } | |
4456 | ++input_line_pointer; | |
4457 | ||
d02603dc | 4458 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4459 | |
252b5132 RH |
4460 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4461 | ||
d02603dc | 4462 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4463 | |
4464 | /* The fourth argument to .lcomm is the alignment. */ | |
4465 | if (*input_line_pointer != ',') | |
4466 | { | |
4467 | if (size <= 4) | |
4468 | align = 2; | |
4469 | else | |
4470 | align = 3; | |
4471 | } | |
4472 | else | |
4473 | { | |
4474 | ++input_line_pointer; | |
4475 | align = get_absolute_expression (); | |
4476 | if (align <= 0) | |
4477 | { | |
4478 | as_warn (_("ignoring bad alignment")); | |
4479 | align = 2; | |
4480 | } | |
4481 | } | |
252b5132 RH |
4482 | } |
4483 | ||
4484 | *end_name = '\0'; | |
4485 | sym = symbol_find_or_make (name); | |
4486 | *end_name = endc; | |
4487 | ||
4488 | if (S_IS_DEFINED (sym) | |
4489 | || S_GET_VALUE (sym) != 0) | |
4490 | { | |
4491 | as_bad (_("attempt to redefine symbol")); | |
4492 | ignore_rest_of_line (); | |
4493 | return; | |
4494 | } | |
81d4177b | 4495 | |
252b5132 | 4496 | record_alignment (bss_section, align); |
81d4177b | 4497 | |
252b5132 RH |
4498 | if (! lcomm |
4499 | || ! S_IS_DEFINED (lcomm_sym)) | |
4500 | { | |
4501 | symbolS *def_sym; | |
4502 | offsetT def_size; | |
4503 | ||
4504 | if (! lcomm) | |
4505 | { | |
4506 | def_sym = sym; | |
4507 | def_size = size; | |
4508 | S_SET_EXTERNAL (sym); | |
4509 | } | |
4510 | else | |
4511 | { | |
809ffe0d | 4512 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4513 | def_sym = lcomm_sym; |
4514 | def_size = 0; | |
4515 | } | |
4516 | ||
4517 | subseg_set (bss_section, 1); | |
4518 | frag_align (align, 0, 0); | |
81d4177b | 4519 | |
809ffe0d | 4520 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4521 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4522 | def_size, (char *) NULL); | |
4523 | *pfrag = 0; | |
4524 | S_SET_SEGMENT (def_sym, bss_section); | |
809ffe0d | 4525 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4526 | } |
4527 | else if (lcomm) | |
4528 | { | |
4529 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4530 | symbol_get_frag (lcomm_sym)->fr_offset = |
4531 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4532 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4533 | if (align > symbol_get_tc (lcomm_sym)->align) |
4534 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4535 | } |
4536 | ||
4537 | if (lcomm) | |
4538 | { | |
4539 | /* Make sym an offset from lcomm_sym. */ | |
4540 | S_SET_SEGMENT (sym, bss_section); | |
809ffe0d ILT |
4541 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4542 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4543 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4544 | } |
4545 | ||
4546 | subseg_set (current_seg, current_subseg); | |
4547 | ||
4548 | demand_empty_rest_of_line (); | |
4549 | } | |
4550 | ||
4551 | /* The .csect pseudo-op. This switches us into a different | |
4552 | subsegment. The first argument is a symbol whose value is the | |
4553 | start of the .csect. In COFF, csect symbols get special aux | |
4554 | entries defined by the x_csect field of union internal_auxent. The | |
4555 | optional second argument is the alignment (the default is 2). */ | |
4556 | ||
4557 | static void | |
98027b10 | 4558 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4559 | { |
4560 | char *name; | |
4561 | char endc; | |
4562 | symbolS *sym; | |
931e13a6 | 4563 | offsetT align; |
252b5132 | 4564 | |
d02603dc | 4565 | endc = get_symbol_name (&name); |
81d4177b | 4566 | |
252b5132 RH |
4567 | sym = symbol_find_or_make (name); |
4568 | ||
d02603dc | 4569 | (void) restore_line_pointer (endc); |
252b5132 RH |
4570 | |
4571 | if (S_GET_NAME (sym)[0] == '\0') | |
4572 | { | |
4573 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4574 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4575 | } |
4576 | ||
931e13a6 | 4577 | align = 2; |
252b5132 RH |
4578 | if (*input_line_pointer == ',') |
4579 | { | |
4580 | ++input_line_pointer; | |
931e13a6 | 4581 | align = get_absolute_expression (); |
252b5132 RH |
4582 | } |
4583 | ||
931e13a6 AM |
4584 | ppc_change_csect (sym, align); |
4585 | ||
252b5132 RH |
4586 | demand_empty_rest_of_line (); |
4587 | } | |
4588 | ||
4589 | /* Change to a different csect. */ | |
4590 | ||
4591 | static void | |
98027b10 | 4592 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4593 | { |
4594 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4595 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4596 | else |
4597 | { | |
4598 | symbolS **list_ptr; | |
4599 | int after_toc; | |
4600 | int hold_chunksize; | |
4601 | symbolS *list; | |
931e13a6 AM |
4602 | int is_code; |
4603 | segT sec; | |
252b5132 RH |
4604 | |
4605 | /* This is a new csect. We need to look at the symbol class to | |
4606 | figure out whether it should go in the text section or the | |
4607 | data section. */ | |
4608 | after_toc = 0; | |
931e13a6 | 4609 | is_code = 0; |
96d56e9f | 4610 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4611 | { |
4612 | case XMC_PR: | |
4613 | case XMC_RO: | |
4614 | case XMC_DB: | |
4615 | case XMC_GL: | |
4616 | case XMC_XO: | |
4617 | case XMC_SV: | |
4618 | case XMC_TI: | |
4619 | case XMC_TB: | |
4620 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4621 | symbol_get_tc (sym)->subseg = ppc_text_subsegment; |
252b5132 RH |
4622 | ++ppc_text_subsegment; |
4623 | list_ptr = &ppc_text_csects; | |
931e13a6 | 4624 | is_code = 1; |
252b5132 RH |
4625 | break; |
4626 | case XMC_RW: | |
4627 | case XMC_TC0: | |
4628 | case XMC_TC: | |
4629 | case XMC_DS: | |
4630 | case XMC_UA: | |
4631 | case XMC_BS: | |
4632 | case XMC_UC: | |
4633 | if (ppc_toc_csect != NULL | |
809ffe0d ILT |
4634 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
4635 | == ppc_data_subsegment)) | |
252b5132 RH |
4636 | after_toc = 1; |
4637 | S_SET_SEGMENT (sym, data_section); | |
809ffe0d | 4638 | symbol_get_tc (sym)->subseg = ppc_data_subsegment; |
252b5132 RH |
4639 | ++ppc_data_subsegment; |
4640 | list_ptr = &ppc_data_csects; | |
4641 | break; | |
4642 | default: | |
4643 | abort (); | |
4644 | } | |
4645 | ||
4646 | /* We set the obstack chunk size to a small value before | |
99a814a1 AM |
4647 | changing subsegments, so that we don't use a lot of memory |
4648 | space for what may be a small section. */ | |
252b5132 RH |
4649 | hold_chunksize = chunksize; |
4650 | chunksize = 64; | |
4651 | ||
931e13a6 AM |
4652 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4653 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4654 | |
4655 | chunksize = hold_chunksize; | |
4656 | ||
4657 | if (after_toc) | |
4658 | ppc_after_toc_frag = frag_now; | |
4659 | ||
931e13a6 AM |
4660 | record_alignment (sec, align); |
4661 | if (is_code) | |
4662 | frag_align_code (align, 0); | |
4663 | else | |
4664 | frag_align (align, 0, 0); | |
4665 | ||
809ffe0d | 4666 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4667 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4668 | ||
931e13a6 | 4669 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4670 | symbol_get_tc (sym)->output = 1; |
4671 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4672 | |
252b5132 | 4673 | for (list = *list_ptr; |
809ffe0d ILT |
4674 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4675 | list = symbol_get_tc (list)->next) | |
252b5132 | 4676 | ; |
809ffe0d | 4677 | symbol_get_tc (list)->next = sym; |
81d4177b | 4678 | |
252b5132 | 4679 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4680 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4681 | &symbol_lastP); | |
252b5132 RH |
4682 | } |
4683 | ||
4684 | ppc_current_csect = sym; | |
4685 | } | |
4686 | ||
85645aed TG |
4687 | static void |
4688 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4689 | { | |
4690 | segT sec; | |
4691 | flagword oldflags; | |
4692 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4693 | ||
4694 | sec = subseg_new (dw->name, subseg); | |
fd361982 | 4695 | oldflags = bfd_section_flags (sec); |
85645aed TG |
4696 | if (oldflags == SEC_NO_FLAGS) |
4697 | { | |
4698 | /* Just created section. */ | |
4699 | gas_assert (dw_sections[idx].sect == NULL); | |
4700 | ||
fd361982 AM |
4701 | bfd_set_section_flags (sec, SEC_DEBUGGING); |
4702 | bfd_set_section_alignment (sec, 0); | |
85645aed TG |
4703 | dw_sections[idx].sect = sec; |
4704 | } | |
4705 | ||
4706 | /* Not anymore in a csect. */ | |
4707 | ppc_current_csect = NULL; | |
4708 | } | |
4709 | ||
4710 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4711 | .dwsect flag [, opt-label ] | |
4712 | */ | |
4713 | ||
4714 | static void | |
4715 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4716 | { | |
16de26a6 | 4717 | valueT flag; |
85645aed TG |
4718 | symbolS *opt_label; |
4719 | const struct xcoff_dwsect_name *dw; | |
4720 | struct dw_subsection *subseg; | |
4721 | struct dw_section *dws; | |
4722 | int i; | |
4723 | ||
4724 | /* Find section. */ | |
4725 | flag = get_absolute_expression (); | |
4726 | dw = NULL; | |
4727 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4728 | if (xcoff_dwsect_names[i].flag == flag) | |
4729 | { | |
4730 | dw = &xcoff_dwsect_names[i]; | |
4731 | break; | |
4732 | } | |
4733 | ||
4734 | /* Parse opt-label. */ | |
4735 | if (*input_line_pointer == ',') | |
4736 | { | |
d02603dc | 4737 | char *label; |
85645aed TG |
4738 | char c; |
4739 | ||
4740 | ++input_line_pointer; | |
4741 | ||
d02603dc | 4742 | c = get_symbol_name (&label); |
85645aed | 4743 | opt_label = symbol_find_or_make (label); |
d02603dc | 4744 | (void) restore_line_pointer (c); |
85645aed TG |
4745 | } |
4746 | else | |
4747 | opt_label = NULL; | |
4748 | ||
4749 | demand_empty_rest_of_line (); | |
4750 | ||
4751 | /* Return now in case of unknown subsection. */ | |
4752 | if (dw == NULL) | |
4753 | { | |
d6ed37ed | 4754 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4755 | (unsigned)flag); |
4756 | return; | |
4757 | } | |
4758 | ||
4759 | /* Find the subsection. */ | |
4760 | dws = &dw_sections[i]; | |
4761 | subseg = NULL; | |
4762 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4763 | { | |
4764 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4765 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4766 | { | |
4767 | as_bad (_("label %s was not defined in this dwarf section"), | |
4768 | S_GET_NAME (opt_label)); | |
4769 | subseg = dws->anon_subseg; | |
4770 | opt_label = NULL; | |
4771 | } | |
4772 | else | |
4773 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4774 | } | |
4775 | ||
4776 | if (subseg != NULL) | |
4777 | { | |
4778 | /* Switch to the subsection. */ | |
4779 | ppc_change_debug_section (i, subseg->subseg); | |
4780 | } | |
4781 | else | |
4782 | { | |
4783 | /* Create a new dw subsection. */ | |
325801bd | 4784 | subseg = XNEW (struct dw_subsection); |
85645aed TG |
4785 | |
4786 | if (opt_label == NULL) | |
4787 | { | |
4788 | /* The anonymous one. */ | |
4789 | subseg->subseg = 0; | |
4790 | subseg->link = NULL; | |
4791 | dws->anon_subseg = subseg; | |
4792 | } | |
4793 | else | |
4794 | { | |
4795 | /* A named one. */ | |
4796 | if (dws->list_subseg != NULL) | |
4797 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4798 | else | |
4799 | subseg->subseg = 1; | |
4800 | ||
4801 | subseg->link = dws->list_subseg; | |
4802 | dws->list_subseg = subseg; | |
4803 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4804 | } | |
4805 | ||
4806 | ppc_change_debug_section (i, subseg->subseg); | |
4807 | ||
4808 | if (dw->def_size) | |
4809 | { | |
4810 | /* Add the length field. */ | |
4811 | expressionS *exp = &subseg->end_exp; | |
4812 | int sz; | |
4813 | ||
4814 | if (opt_label != NULL) | |
4815 | symbol_set_value_now (opt_label); | |
4816 | ||
4817 | /* Add the length field. Note that according to the AIX assembler | |
4818 | manual, the size of the length field is 4 for powerpc32 but | |
4819 | 12 for powerpc64. */ | |
4820 | if (ppc_obj64) | |
4821 | { | |
4822 | /* Write the 64bit marker. */ | |
4823 | md_number_to_chars (frag_more (4), -1, 4); | |
4824 | } | |
4825 | ||
4826 | exp->X_op = O_subtract; | |
4827 | exp->X_op_symbol = symbol_temp_new_now (); | |
4828 | exp->X_add_symbol = symbol_temp_make (); | |
4829 | ||
4830 | sz = ppc_obj64 ? 8 : 4; | |
4831 | exp->X_add_number = -sz; | |
4832 | emit_expr (exp, sz); | |
4833 | } | |
4834 | } | |
4835 | } | |
4836 | ||
252b5132 RH |
4837 | /* This function handles the .text and .data pseudo-ops. These |
4838 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4839 | convenience of people who aren't used to XCOFF. */ | |
4840 | ||
4841 | static void | |
98027b10 | 4842 | ppc_section (int type) |
252b5132 RH |
4843 | { |
4844 | const char *name; | |
4845 | symbolS *sym; | |
4846 | ||
4847 | if (type == 't') | |
4848 | name = ".text[PR]"; | |
4849 | else if (type == 'd') | |
4850 | name = ".data[RW]"; | |
4851 | else | |
4852 | abort (); | |
4853 | ||
4854 | sym = symbol_find_or_make (name); | |
4855 | ||
931e13a6 | 4856 | ppc_change_csect (sym, 2); |
252b5132 RH |
4857 | |
4858 | demand_empty_rest_of_line (); | |
4859 | } | |
4860 | ||
4861 | /* This function handles the .section pseudo-op. This is mostly to | |
4862 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4863 | we do permit the user to name the text or data section. */ | |
4864 | ||
4865 | static void | |
98027b10 | 4866 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4867 | { |
4868 | char *user_name; | |
4869 | const char *real_name; | |
4870 | char c; | |
4871 | symbolS *sym; | |
4872 | ||
d02603dc | 4873 | c = get_symbol_name (&user_name); |
252b5132 RH |
4874 | |
4875 | if (strcmp (user_name, ".text") == 0) | |
4876 | real_name = ".text[PR]"; | |
4877 | else if (strcmp (user_name, ".data") == 0) | |
4878 | real_name = ".data[RW]"; | |
4879 | else | |
4880 | { | |
d6ed37ed | 4881 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4882 | (void) restore_line_pointer (c); |
252b5132 RH |
4883 | ignore_rest_of_line (); |
4884 | return; | |
4885 | } | |
4886 | ||
d02603dc | 4887 | (void) restore_line_pointer (c); |
252b5132 RH |
4888 | |
4889 | sym = symbol_find_or_make (real_name); | |
4890 | ||
931e13a6 | 4891 | ppc_change_csect (sym, 2); |
252b5132 RH |
4892 | |
4893 | demand_empty_rest_of_line (); | |
4894 | } | |
4895 | ||
4896 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4897 | ||
4898 | static void | |
98027b10 | 4899 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4900 | { |
4901 | char *name; | |
4902 | char endc; | |
4903 | ||
d02603dc | 4904 | endc = get_symbol_name (&name); |
252b5132 RH |
4905 | |
4906 | (void) symbol_find_or_make (name); | |
4907 | ||
d02603dc | 4908 | (void) restore_line_pointer (endc); |
252b5132 RH |
4909 | |
4910 | demand_empty_rest_of_line (); | |
4911 | } | |
4912 | ||
4913 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4914 | ||
4915 | static void | |
98027b10 | 4916 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4917 | { |
4918 | char *name; | |
4919 | char endc; | |
4920 | symbolS *sym; | |
4921 | ||
d02603dc | 4922 | endc = get_symbol_name (&name); |
252b5132 RH |
4923 | |
4924 | sym = symbol_find_or_make (name); | |
4925 | ||
d02603dc | 4926 | (void) restore_line_pointer (endc); |
252b5132 | 4927 | |
809ffe0d | 4928 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4929 | |
4930 | demand_empty_rest_of_line (); | |
4931 | } | |
4932 | ||
c865e45b RS |
4933 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4934 | relocations at the beginning of the current csect. | |
4935 | ||
4936 | (In principle, there's no reason why the relocations _have_ to be at | |
4937 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4938 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4939 | deal with cases where the .ref statements follow the section contents.) |
4940 | ||
4941 | ??? .refs don't work for empty .csects. However, the native assembler | |
4942 | doesn't report an error in this case, and neither yet do we. */ | |
4943 | ||
4944 | static void | |
4945 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4946 | { | |
4947 | char *name; | |
4948 | char c; | |
4949 | ||
4950 | if (ppc_current_csect == NULL) | |
4951 | { | |
4952 | as_bad (_(".ref outside .csect")); | |
4953 | ignore_rest_of_line (); | |
4954 | return; | |
4955 | } | |
4956 | ||
4957 | do | |
4958 | { | |
d02603dc | 4959 | c = get_symbol_name (&name); |
c865e45b RS |
4960 | |
4961 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
4962 | symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE); | |
4963 | ||
4964 | *input_line_pointer = c; | |
d02603dc | 4965 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
4966 | c = *input_line_pointer; |
4967 | if (c == ',') | |
4968 | { | |
4969 | input_line_pointer++; | |
4970 | SKIP_WHITESPACE (); | |
4971 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
4972 | { | |
4973 | as_bad (_("missing symbol name")); | |
4974 | ignore_rest_of_line (); | |
4975 | return; | |
4976 | } | |
4977 | } | |
4978 | } | |
4979 | while (c == ','); | |
4980 | ||
4981 | demand_empty_rest_of_line (); | |
4982 | } | |
4983 | ||
252b5132 RH |
4984 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
4985 | although I don't know why it bothers. */ | |
4986 | ||
4987 | static void | |
98027b10 | 4988 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4989 | { |
4990 | char *name; | |
4991 | char endc; | |
4992 | symbolS *sym; | |
4993 | int len; | |
4994 | ||
d02603dc | 4995 | endc = get_symbol_name (&name); |
252b5132 RH |
4996 | |
4997 | sym = symbol_find_or_make (name); | |
4998 | ||
d02603dc | 4999 | (void) restore_line_pointer (endc); |
252b5132 RH |
5000 | |
5001 | if (*input_line_pointer != ',') | |
5002 | { | |
5003 | as_bad (_("missing rename string")); | |
5004 | ignore_rest_of_line (); | |
5005 | return; | |
5006 | } | |
5007 | ++input_line_pointer; | |
5008 | ||
809ffe0d | 5009 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
5010 | |
5011 | demand_empty_rest_of_line (); | |
5012 | } | |
5013 | ||
5014 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
5015 | pseudo-op, but slightly different. A sample is | |
5016 | .stabx "main:F-1",.main,142,0 | |
5017 | The first argument is the symbol name to create. The second is the | |
5018 | value, and the third is the storage class. The fourth seems to be | |
5019 | always zero, and I am assuming it is the type. */ | |
5020 | ||
5021 | static void | |
98027b10 | 5022 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5023 | { |
5024 | char *name; | |
5025 | int len; | |
5026 | symbolS *sym; | |
5027 | expressionS exp; | |
5028 | ||
5029 | name = demand_copy_C_string (&len); | |
5030 | ||
5031 | if (*input_line_pointer != ',') | |
5032 | { | |
5033 | as_bad (_("missing value")); | |
5034 | return; | |
5035 | } | |
5036 | ++input_line_pointer; | |
5037 | ||
b34976b6 | 5038 | ppc_stab_symbol = TRUE; |
252b5132 | 5039 | sym = symbol_make (name); |
b34976b6 | 5040 | ppc_stab_symbol = FALSE; |
252b5132 | 5041 | |
809ffe0d | 5042 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
5043 | |
5044 | (void) expression (&exp); | |
5045 | ||
5046 | switch (exp.X_op) | |
5047 | { | |
5048 | case O_illegal: | |
5049 | case O_absent: | |
5050 | case O_big: | |
5051 | as_bad (_("illegal .stabx expression; zero assumed")); | |
5052 | exp.X_add_number = 0; | |
5053 | /* Fall through. */ | |
5054 | case O_constant: | |
5055 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 5056 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
5057 | break; |
5058 | ||
5059 | case O_symbol: | |
5060 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 5061 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5062 | else |
5063 | { | |
5064 | S_SET_VALUE (sym, | |
5065 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 5066 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
5067 | } |
5068 | break; | |
5069 | ||
5070 | default: | |
5071 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
5072 | fail at some later point, but this is probably the right |
5073 | thing to do here. */ | |
809ffe0d | 5074 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5075 | break; |
5076 | } | |
5077 | ||
5078 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5079 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5080 | |
5081 | if (*input_line_pointer != ',') | |
5082 | { | |
5083 | as_bad (_("missing class")); | |
5084 | return; | |
5085 | } | |
5086 | ++input_line_pointer; | |
5087 | ||
5088 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
5089 | ||
5090 | if (*input_line_pointer != ',') | |
5091 | { | |
5092 | as_bad (_("missing type")); | |
5093 | return; | |
5094 | } | |
5095 | ++input_line_pointer; | |
5096 | ||
5097 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
5098 | ||
809ffe0d | 5099 | symbol_get_tc (sym)->output = 1; |
252b5132 | 5100 | |
c734e7e3 TG |
5101 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
5102 | { | |
5103 | /* In this case : | |
252b5132 | 5104 | |
c734e7e3 TG |
5105 | .bs name |
5106 | .stabx "z",arrays_,133,0 | |
5107 | .es | |
99a814a1 | 5108 | |
c734e7e3 | 5109 | .comm arrays_,13768,3 |
99a814a1 | 5110 | |
c734e7e3 TG |
5111 | resolve_symbol_value will copy the exp's "within" into sym's when the |
5112 | offset is 0. Since this seems to be corner case problem, | |
5113 | only do the correction for storage class C_STSYM. A better solution | |
5114 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 5115 | |
c734e7e3 TG |
5116 | if (exp.X_op == O_symbol) |
5117 | { | |
5118 | if (ppc_current_block == NULL) | |
5119 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 5120 | |
c734e7e3 TG |
5121 | symbol_get_tc (sym)->within = ppc_current_block; |
5122 | symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block; | |
5123 | } | |
5124 | } | |
99a814a1 | 5125 | |
252b5132 RH |
5126 | if (exp.X_op != O_symbol |
5127 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
5128 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
5129 | ppc_frob_label (sym); | |
5130 | else | |
5131 | { | |
5132 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5133 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5134 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
5135 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
5136 | } |
5137 | ||
5138 | demand_empty_rest_of_line (); | |
5139 | } | |
5140 | ||
5141 | /* The .function pseudo-op. This takes several arguments. The first | |
5142 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 5143 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
5144 | uses the same name for both. I have no idea what the third and |
5145 | fourth arguments are meant to be. The optional fifth argument is | |
5146 | an expression for the size of the function. In COFF this symbol | |
5147 | gets an aux entry like that used for a csect. */ | |
5148 | ||
5149 | static void | |
98027b10 | 5150 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5151 | { |
5152 | char *name; | |
5153 | char endc; | |
5154 | char *s; | |
5155 | symbolS *ext_sym; | |
5156 | symbolS *lab_sym; | |
5157 | ||
d02603dc | 5158 | endc = get_symbol_name (&name); |
252b5132 RH |
5159 | |
5160 | /* Ignore any [PR] suffix. */ | |
5161 | name = ppc_canonicalize_symbol_name (name); | |
5162 | s = strchr (name, '['); | |
5163 | if (s != (char *) NULL | |
5164 | && strcmp (s + 1, "PR]") == 0) | |
5165 | *s = '\0'; | |
5166 | ||
5167 | ext_sym = symbol_find_or_make (name); | |
5168 | ||
d02603dc | 5169 | (void) restore_line_pointer (endc); |
252b5132 RH |
5170 | |
5171 | if (*input_line_pointer != ',') | |
5172 | { | |
5173 | as_bad (_("missing symbol name")); | |
5174 | ignore_rest_of_line (); | |
5175 | return; | |
5176 | } | |
5177 | ++input_line_pointer; | |
5178 | ||
d02603dc | 5179 | endc = get_symbol_name (&name); |
252b5132 RH |
5180 | |
5181 | lab_sym = symbol_find_or_make (name); | |
5182 | ||
d02603dc | 5183 | (void) restore_line_pointer (endc); |
252b5132 RH |
5184 | |
5185 | if (ext_sym != lab_sym) | |
5186 | { | |
809ffe0d ILT |
5187 | expressionS exp; |
5188 | ||
5189 | exp.X_op = O_symbol; | |
5190 | exp.X_add_symbol = lab_sym; | |
5191 | exp.X_op_symbol = NULL; | |
5192 | exp.X_add_number = 0; | |
5193 | exp.X_unsigned = 0; | |
5194 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
5195 | } |
5196 | ||
96d56e9f NC |
5197 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
5198 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 5199 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
5200 | |
5201 | if (*input_line_pointer == ',') | |
5202 | { | |
91d6fa6a | 5203 | expressionS exp; |
252b5132 RH |
5204 | |
5205 | /* Ignore the third argument. */ | |
5206 | ++input_line_pointer; | |
91d6fa6a | 5207 | expression (& exp); |
252b5132 RH |
5208 | if (*input_line_pointer == ',') |
5209 | { | |
5210 | /* Ignore the fourth argument. */ | |
5211 | ++input_line_pointer; | |
91d6fa6a | 5212 | expression (& exp); |
252b5132 RH |
5213 | if (*input_line_pointer == ',') |
5214 | { | |
5215 | /* The fifth argument is the function size. */ | |
5216 | ++input_line_pointer; | |
85645aed TG |
5217 | symbol_get_tc (ext_sym)->u.size = symbol_new |
5218 | ("L0\001", absolute_section,(valueT) 0, &zero_address_frag); | |
5219 | pseudo_set (symbol_get_tc (ext_sym)->u.size); | |
252b5132 RH |
5220 | } |
5221 | } | |
5222 | } | |
5223 | ||
5224 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
5225 | SF_SET_FUNCTION (ext_sym); | |
5226 | SF_SET_PROCESS (ext_sym); | |
5227 | coff_add_linesym (ext_sym); | |
5228 | ||
5229 | demand_empty_rest_of_line (); | |
5230 | } | |
5231 | ||
5232 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
5233 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
5234 | with the correct line number */ | |
5d6255fe | 5235 | |
8642cce8 | 5236 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
5237 | |
5238 | static void | |
98027b10 | 5239 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5240 | { |
5241 | symbolS *sym; | |
5242 | ||
5243 | sym = symbol_make (".bf"); | |
5244 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5245 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5246 | S_SET_VALUE (sym, frag_now_fix ()); |
5247 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5248 | ||
5249 | coff_line_base = get_absolute_expression (); | |
5250 | ||
5251 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5252 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
5253 | ||
8642cce8 | 5254 | /* Line number for bi. */ |
5d6255fe | 5255 | if (saved_bi_sym) |
8642cce8 TR |
5256 | { |
5257 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
5258 | saved_bi_sym = 0; | |
5259 | } | |
5d6255fe | 5260 | |
8642cce8 | 5261 | |
809ffe0d | 5262 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5263 | |
5264 | ppc_frob_label (sym); | |
5265 | ||
5266 | demand_empty_rest_of_line (); | |
5267 | } | |
5268 | ||
5269 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
5270 | ".ef", except that the line number is absolute, not relative to the | |
5271 | most recent ".bf" symbol. */ | |
5272 | ||
5273 | static void | |
98027b10 | 5274 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5275 | { |
5276 | symbolS *sym; | |
5277 | ||
5278 | sym = symbol_make (".ef"); | |
5279 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5280 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5281 | S_SET_VALUE (sym, frag_now_fix ()); |
5282 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5283 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5284 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5285 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5286 | |
5287 | ppc_frob_label (sym); | |
5288 | ||
5289 | demand_empty_rest_of_line (); | |
5290 | } | |
5291 | ||
5292 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
5293 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
5294 | the symbol list. The value of .bi will be know when the next .bf |
5295 | is encountered. */ | |
252b5132 RH |
5296 | |
5297 | static void | |
98027b10 | 5298 | ppc_biei (int ei) |
252b5132 RH |
5299 | { |
5300 | static symbolS *last_biei; | |
5301 | ||
5302 | char *name; | |
5303 | int len; | |
5304 | symbolS *sym; | |
5305 | symbolS *look; | |
5306 | ||
5307 | name = demand_copy_C_string (&len); | |
5308 | ||
5309 | /* The value of these symbols is actually file offset. Here we set | |
5310 | the value to the index into the line number entries. In | |
5311 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
5312 | to do the right thing. */ | |
5313 | ||
5314 | sym = symbol_make (name); | |
5315 | /* obj-coff.c currently only handles line numbers correctly in the | |
5316 | .text section. */ | |
5317 | S_SET_SEGMENT (sym, text_section); | |
5318 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 5319 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5320 | |
5321 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 5322 | symbol_get_tc (sym)->output = 1; |
81d4177b | 5323 | |
8642cce8 | 5324 | /* Save bi. */ |
5d6255fe | 5325 | if (ei) |
8642cce8 TR |
5326 | saved_bi_sym = 0; |
5327 | else | |
5328 | saved_bi_sym = sym; | |
5329 | ||
252b5132 RH |
5330 | for (look = last_biei ? last_biei : symbol_rootP; |
5331 | (look != (symbolS *) NULL | |
5332 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
5333 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
5334 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
5335 | look = symbol_next (look)) | |
5336 | ; | |
5337 | if (look != (symbolS *) NULL) | |
5338 | { | |
5339 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5340 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
5341 | last_biei = sym; | |
5342 | } | |
5343 | ||
5344 | demand_empty_rest_of_line (); | |
5345 | } | |
5346 | ||
5347 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5348 | There is one argument, which is a csect symbol. The value of the | |
5349 | .bs symbol is the index of this csect symbol. */ | |
5350 | ||
5351 | static void | |
98027b10 | 5352 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5353 | { |
5354 | char *name; | |
5355 | char endc; | |
5356 | symbolS *csect; | |
5357 | symbolS *sym; | |
5358 | ||
5359 | if (ppc_current_block != NULL) | |
5360 | as_bad (_("nested .bs blocks")); | |
5361 | ||
d02603dc | 5362 | endc = get_symbol_name (&name); |
252b5132 RH |
5363 | |
5364 | csect = symbol_find_or_make (name); | |
5365 | ||
d02603dc | 5366 | (void) restore_line_pointer (endc); |
252b5132 RH |
5367 | |
5368 | sym = symbol_make (".bs"); | |
5369 | S_SET_SEGMENT (sym, now_seg); | |
5370 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5371 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5372 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5373 | |
809ffe0d | 5374 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5375 | |
5376 | ppc_frob_label (sym); | |
5377 | ||
5378 | ppc_current_block = sym; | |
5379 | ||
5380 | demand_empty_rest_of_line (); | |
5381 | } | |
5382 | ||
5383 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5384 | ||
5385 | static void | |
98027b10 | 5386 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5387 | { |
5388 | symbolS *sym; | |
5389 | ||
5390 | if (ppc_current_block == NULL) | |
5391 | as_bad (_(".es without preceding .bs")); | |
5392 | ||
5393 | sym = symbol_make (".es"); | |
5394 | S_SET_SEGMENT (sym, now_seg); | |
5395 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5396 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5397 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5398 | |
5399 | ppc_frob_label (sym); | |
5400 | ||
5401 | ppc_current_block = NULL; | |
5402 | ||
5403 | demand_empty_rest_of_line (); | |
5404 | } | |
5405 | ||
5406 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5407 | line number. */ | |
5408 | ||
5409 | static void | |
98027b10 | 5410 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5411 | { |
5412 | symbolS *sym; | |
5413 | ||
5414 | sym = symbol_make (".bb"); | |
5415 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5416 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5417 | S_SET_VALUE (sym, frag_now_fix ()); |
5418 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5419 | ||
5420 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5421 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5422 | ||
809ffe0d | 5423 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5424 | |
5425 | SF_SET_PROCESS (sym); | |
5426 | ||
5427 | ppc_frob_label (sym); | |
5428 | ||
5429 | demand_empty_rest_of_line (); | |
5430 | } | |
5431 | ||
5432 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5433 | line number. */ | |
5434 | ||
5435 | static void | |
98027b10 | 5436 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5437 | { |
5438 | symbolS *sym; | |
5439 | ||
5440 | sym = symbol_make (".eb"); | |
5441 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5442 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5443 | S_SET_VALUE (sym, frag_now_fix ()); |
5444 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5445 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5446 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5447 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5448 | |
5449 | SF_SET_PROCESS (sym); | |
5450 | ||
5451 | ppc_frob_label (sym); | |
5452 | ||
5453 | demand_empty_rest_of_line (); | |
5454 | } | |
5455 | ||
5456 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5457 | specified name. */ | |
5458 | ||
5459 | static void | |
98027b10 | 5460 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5461 | { |
5462 | char *name; | |
5463 | int len; | |
5464 | symbolS *sym; | |
5465 | ||
5466 | name = demand_copy_C_string (&len); | |
5467 | sym = symbol_make (name); | |
5468 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5469 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5470 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5471 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5472 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5473 | |
5474 | ppc_frob_label (sym); | |
5475 | ||
5476 | demand_empty_rest_of_line (); | |
5477 | } | |
5478 | ||
5479 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5480 | ||
5481 | static void | |
98027b10 | 5482 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5483 | { |
5484 | symbolS *sym; | |
5485 | ||
5486 | sym = symbol_make (".ec"); | |
5487 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5488 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5489 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5490 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5491 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5492 | |
5493 | ppc_frob_label (sym); | |
5494 | ||
5495 | demand_empty_rest_of_line (); | |
5496 | } | |
5497 | ||
5498 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5499 | ||
5500 | static void | |
98027b10 | 5501 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5502 | { |
5503 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5504 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5505 | else |
5506 | { | |
5507 | subsegT subseg; | |
5508 | symbolS *sym; | |
5509 | symbolS *list; | |
81d4177b | 5510 | |
252b5132 RH |
5511 | subseg = ppc_data_subsegment; |
5512 | ++ppc_data_subsegment; | |
5513 | ||
5514 | subseg_new (segment_name (data_section), subseg); | |
5515 | ppc_toc_frag = frag_now; | |
5516 | ||
5517 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5518 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5519 | S_SET_SEGMENT (sym, data_section); |
5520 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5521 | symbol_get_tc (sym)->subseg = subseg; |
5522 | symbol_get_tc (sym)->output = 1; | |
5523 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5524 | |
5525 | ppc_toc_csect = sym; | |
81d4177b | 5526 | |
252b5132 | 5527 | for (list = ppc_data_csects; |
809ffe0d ILT |
5528 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5529 | list = symbol_get_tc (list)->next) | |
252b5132 | 5530 | ; |
809ffe0d | 5531 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5532 | |
5533 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5534 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5535 | &symbol_lastP); | |
252b5132 RH |
5536 | } |
5537 | ||
5538 | ppc_current_csect = ppc_toc_csect; | |
5539 | ||
5540 | demand_empty_rest_of_line (); | |
5541 | } | |
5542 | ||
5543 | /* The AIX assembler automatically aligns the operands of a .long or | |
5544 | .short pseudo-op, and we want to be compatible. */ | |
5545 | ||
5546 | static void | |
98027b10 | 5547 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5548 | { |
5549 | frag_align (log_size, 0, 0); | |
5550 | record_alignment (now_seg, log_size); | |
5551 | cons (1 << log_size); | |
5552 | } | |
5553 | ||
5554 | static void | |
98027b10 | 5555 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5556 | { |
5557 | expressionS exp; | |
5558 | int byte_count; | |
5559 | ||
5560 | (void) expression (&exp); | |
5561 | ||
5562 | if (exp.X_op != O_constant) | |
5563 | { | |
5564 | as_bad (_("non-constant byte count")); | |
5565 | return; | |
5566 | } | |
5567 | ||
5568 | byte_count = exp.X_add_number; | |
5569 | ||
5570 | if (*input_line_pointer != ',') | |
5571 | { | |
5572 | as_bad (_("missing value")); | |
5573 | return; | |
5574 | } | |
5575 | ||
5576 | ++input_line_pointer; | |
5577 | cons (byte_count); | |
5578 | } | |
5579 | ||
85645aed TG |
5580 | void |
5581 | ppc_xcoff_end (void) | |
5582 | { | |
5583 | int i; | |
5584 | ||
5585 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5586 | { | |
5587 | struct dw_section *dws = &dw_sections[i]; | |
5588 | struct dw_subsection *dwss; | |
5589 | ||
5590 | if (dws->anon_subseg) | |
5591 | { | |
5592 | dwss = dws->anon_subseg; | |
5593 | dwss->link = dws->list_subseg; | |
5594 | } | |
5595 | else | |
5596 | dwss = dws->list_subseg; | |
5597 | ||
5598 | for (; dwss != NULL; dwss = dwss->link) | |
5599 | if (dwss->end_exp.X_add_symbol != NULL) | |
5600 | { | |
5601 | subseg_set (dws->sect, dwss->subseg); | |
5602 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5603 | } | |
5604 | } | |
22f72c48 | 5605 | ppc_cpu = 0; |
85645aed TG |
5606 | } |
5607 | ||
252b5132 | 5608 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5609 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5610 | \f |
5611 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5612 | ELF. This takes two or more arguments. | |
5613 | ||
5614 | When generating XCOFF output, the first argument is the name to | |
5615 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5616 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5617 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5618 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5619 | depends on target word size. A 32-bit target uses 4-byte values, a |
5620 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5621 | |
5622 | When not generating XCOFF output, the arguments are the same, but | |
5623 | the first argument is simply ignored. */ | |
5624 | ||
5625 | static void | |
98027b10 | 5626 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5627 | { |
5628 | #ifdef OBJ_XCOFF | |
5629 | ||
5630 | /* Define the TOC symbol name. */ | |
5631 | { | |
5632 | char *name; | |
5633 | char endc; | |
5634 | symbolS *sym; | |
5635 | ||
5636 | if (ppc_toc_csect == (symbolS *) NULL | |
5637 | || ppc_toc_csect != ppc_current_csect) | |
5638 | { | |
5639 | as_bad (_(".tc not in .toc section")); | |
5640 | ignore_rest_of_line (); | |
5641 | return; | |
5642 | } | |
5643 | ||
d02603dc | 5644 | endc = get_symbol_name (&name); |
252b5132 RH |
5645 | |
5646 | sym = symbol_find_or_make (name); | |
5647 | ||
d02603dc | 5648 | (void) restore_line_pointer (endc); |
252b5132 RH |
5649 | |
5650 | if (S_IS_DEFINED (sym)) | |
5651 | { | |
5652 | symbolS *label; | |
5653 | ||
809ffe0d | 5654 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5655 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5656 | { |
5657 | as_bad (_(".tc with no label")); | |
5658 | ignore_rest_of_line (); | |
5659 | return; | |
5660 | } | |
5661 | ||
5662 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5663 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5664 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5665 | ||
5666 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5667 | ++input_line_pointer; | |
5668 | ||
5669 | return; | |
5670 | } | |
5671 | ||
5672 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5673 | symbol_set_frag (sym, frag_now); |
252b5132 | 5674 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
96d56e9f | 5675 | symbol_get_tc (sym)->symbol_class = XMC_TC; |
809ffe0d | 5676 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5677 | |
5678 | ppc_frob_label (sym); | |
5679 | } | |
5680 | ||
0baf16f2 AM |
5681 | #endif /* OBJ_XCOFF */ |
5682 | #ifdef OBJ_ELF | |
9c7977b3 | 5683 | int align; |
252b5132 RH |
5684 | |
5685 | /* Skip the TOC symbol name. */ | |
5686 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5687 | || *input_line_pointer == ' ' |
252b5132 RH |
5688 | || *input_line_pointer == '[' |
5689 | || *input_line_pointer == ']' | |
5690 | || *input_line_pointer == '{' | |
5691 | || *input_line_pointer == '}') | |
5692 | ++input_line_pointer; | |
5693 | ||
0baf16f2 | 5694 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5695 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5696 | frag_align (align, 0, 0); |
5697 | record_alignment (now_seg, align); | |
0baf16f2 | 5698 | #endif /* OBJ_ELF */ |
252b5132 RH |
5699 | |
5700 | if (*input_line_pointer != ',') | |
5701 | demand_empty_rest_of_line (); | |
5702 | else | |
5703 | { | |
5704 | ++input_line_pointer; | |
2b3c4602 | 5705 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5706 | } |
5707 | } | |
0baf16f2 AM |
5708 | |
5709 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5710 | |
5711 | static void | |
98027b10 | 5712 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5713 | { |
d02603dc | 5714 | char c; |
69c040df AM |
5715 | char *cpu_string; |
5716 | #define MAX_HISTORY 100 | |
fa452fa6 | 5717 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5718 | static int curr_hist; |
5719 | ||
5720 | SKIP_WHITESPACE (); | |
5721 | ||
d02603dc NC |
5722 | c = get_symbol_name (&cpu_string); |
5723 | cpu_string = xstrdup (cpu_string); | |
5724 | (void) restore_line_pointer (c); | |
69c040df AM |
5725 | |
5726 | if (cpu_string != NULL) | |
5727 | { | |
fa452fa6 | 5728 | ppc_cpu_t old_cpu = ppc_cpu; |
69fe9ce5 | 5729 | ppc_cpu_t new_cpu; |
69c040df AM |
5730 | char *p; |
5731 | ||
5732 | for (p = cpu_string; *p != 0; p++) | |
5733 | *p = TOLOWER (*p); | |
5734 | ||
5735 | if (strcmp (cpu_string, "push") == 0) | |
5736 | { | |
5737 | if (cpu_history == NULL) | |
325801bd | 5738 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5739 | |
5740 | if (curr_hist >= MAX_HISTORY) | |
5741 | as_bad (_(".machine stack overflow")); | |
5742 | else | |
5743 | cpu_history[curr_hist++] = ppc_cpu; | |
5744 | } | |
5745 | else if (strcmp (cpu_string, "pop") == 0) | |
5746 | { | |
5747 | if (curr_hist <= 0) | |
5748 | as_bad (_(".machine stack underflow")); | |
5749 | else | |
5750 | ppc_cpu = cpu_history[--curr_hist]; | |
5751 | } | |
776fc418 | 5752 | else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0) |
69fe9ce5 | 5753 | ppc_cpu = new_cpu; |
69c040df AM |
5754 | else |
5755 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5756 | ||
5757 | if (ppc_cpu != old_cpu) | |
5758 | ppc_setup_opcodes (); | |
5759 | } | |
5760 | ||
5761 | demand_empty_rest_of_line (); | |
0baf16f2 | 5762 | } |
0baf16f2 | 5763 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 RH |
5764 | \f |
5765 | #ifdef TE_PE | |
5766 | ||
99a814a1 | 5767 | /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */ |
252b5132 RH |
5768 | |
5769 | /* Set the current section. */ | |
5770 | static void | |
98027b10 | 5771 | ppc_set_current_section (segT new) |
252b5132 RH |
5772 | { |
5773 | ppc_previous_section = ppc_current_section; | |
5774 | ppc_current_section = new; | |
5775 | } | |
5776 | ||
5777 | /* pseudo-op: .previous | |
5778 | behaviour: toggles the current section with the previous section. | |
5779 | errors: None | |
99a814a1 AM |
5780 | warnings: "No previous section" */ |
5781 | ||
252b5132 | 5782 | static void |
98027b10 | 5783 | ppc_previous (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5784 | { |
81d4177b | 5785 | if (ppc_previous_section == NULL) |
252b5132 | 5786 | { |
d6ed37ed | 5787 | as_warn (_("no previous section to return to, ignored.")); |
252b5132 RH |
5788 | return; |
5789 | } | |
5790 | ||
99a814a1 | 5791 | subseg_set (ppc_previous_section, 0); |
252b5132 | 5792 | |
99a814a1 | 5793 | ppc_set_current_section (ppc_previous_section); |
252b5132 RH |
5794 | } |
5795 | ||
5796 | /* pseudo-op: .pdata | |
5797 | behaviour: predefined read only data section | |
b34976b6 | 5798 | double word aligned |
252b5132 RH |
5799 | errors: None |
5800 | warnings: None | |
5801 | initial: .section .pdata "adr3" | |
b34976b6 | 5802 | a - don't know -- maybe a misprint |
252b5132 RH |
5803 | d - initialized data |
5804 | r - readable | |
5805 | 3 - double word aligned (that would be 4 byte boundary) | |
5806 | ||
5807 | commentary: | |
5808 | Tag index tables (also known as the function table) for exception | |
99a814a1 | 5809 | handling, debugging, etc. */ |
252b5132 | 5810 | |
252b5132 | 5811 | static void |
98027b10 | 5812 | ppc_pdata (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5813 | { |
81d4177b | 5814 | if (pdata_section == 0) |
252b5132 RH |
5815 | { |
5816 | pdata_section = subseg_new (".pdata", 0); | |
81d4177b | 5817 | |
fd361982 AM |
5818 | bfd_set_section_flags (pdata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5819 | | SEC_READONLY | SEC_DATA)); | |
81d4177b | 5820 | |
fd361982 | 5821 | bfd_set_section_alignment (pdata_section, 2); |
252b5132 RH |
5822 | } |
5823 | else | |
5824 | { | |
99a814a1 | 5825 | pdata_section = subseg_new (".pdata", 0); |
252b5132 | 5826 | } |
99a814a1 | 5827 | ppc_set_current_section (pdata_section); |
252b5132 RH |
5828 | } |
5829 | ||
5830 | /* pseudo-op: .ydata | |
5831 | behaviour: predefined read only data section | |
b34976b6 | 5832 | double word aligned |
252b5132 RH |
5833 | errors: None |
5834 | warnings: None | |
5835 | initial: .section .ydata "drw3" | |
b34976b6 | 5836 | a - don't know -- maybe a misprint |
252b5132 RH |
5837 | d - initialized data |
5838 | r - readable | |
5839 | 3 - double word aligned (that would be 4 byte boundary) | |
5840 | commentary: | |
5841 | Tag tables (also known as the scope table) for exception handling, | |
99a814a1 AM |
5842 | debugging, etc. */ |
5843 | ||
252b5132 | 5844 | static void |
98027b10 | 5845 | ppc_ydata (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5846 | { |
81d4177b | 5847 | if (ydata_section == 0) |
252b5132 RH |
5848 | { |
5849 | ydata_section = subseg_new (".ydata", 0); | |
fd361982 AM |
5850 | bfd_set_section_flags (ydata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5851 | | SEC_READONLY | SEC_DATA )); | |
252b5132 | 5852 | |
fd361982 | 5853 | bfd_set_section_alignment (ydata_section, 3); |
252b5132 RH |
5854 | } |
5855 | else | |
5856 | { | |
5857 | ydata_section = subseg_new (".ydata", 0); | |
5858 | } | |
99a814a1 | 5859 | ppc_set_current_section (ydata_section); |
252b5132 RH |
5860 | } |
5861 | ||
5862 | /* pseudo-op: .reldata | |
5863 | behaviour: predefined read write data section | |
b34976b6 | 5864 | double word aligned (4-byte) |
252b5132 RH |
5865 | FIXME: relocation is applied to it |
5866 | FIXME: what's the difference between this and .data? | |
5867 | errors: None | |
5868 | warnings: None | |
5869 | initial: .section .reldata "drw3" | |
5870 | d - initialized data | |
5871 | r - readable | |
33eaf5de | 5872 | w - writable |
252b5132 RH |
5873 | 3 - double word aligned (that would be 8 byte boundary) |
5874 | ||
5875 | commentary: | |
5876 | Like .data, but intended to hold data subject to relocation, such as | |
99a814a1 AM |
5877 | function descriptors, etc. */ |
5878 | ||
252b5132 | 5879 | static void |
98027b10 | 5880 | ppc_reldata (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5881 | { |
5882 | if (reldata_section == 0) | |
5883 | { | |
5884 | reldata_section = subseg_new (".reldata", 0); | |
5885 | ||
fd361982 AM |
5886 | bfd_set_section_flags (reldata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5887 | | SEC_DATA)); | |
252b5132 | 5888 | |
fd361982 | 5889 | bfd_set_section_alignment (reldata_section, 2); |
252b5132 RH |
5890 | } |
5891 | else | |
5892 | { | |
5893 | reldata_section = subseg_new (".reldata", 0); | |
5894 | } | |
99a814a1 | 5895 | ppc_set_current_section (reldata_section); |
252b5132 RH |
5896 | } |
5897 | ||
5898 | /* pseudo-op: .rdata | |
5899 | behaviour: predefined read only data section | |
b34976b6 | 5900 | double word aligned |
252b5132 RH |
5901 | errors: None |
5902 | warnings: None | |
5903 | initial: .section .rdata "dr3" | |
5904 | d - initialized data | |
5905 | r - readable | |
99a814a1 AM |
5906 | 3 - double word aligned (that would be 4 byte boundary) */ |
5907 | ||
252b5132 | 5908 | static void |
98027b10 | 5909 | ppc_rdata (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5910 | { |
5911 | if (rdata_section == 0) | |
5912 | { | |
5913 | rdata_section = subseg_new (".rdata", 0); | |
fd361982 AM |
5914 | bfd_set_section_flags (rdata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5915 | | SEC_READONLY | SEC_DATA )); | |
252b5132 | 5916 | |
fd361982 | 5917 | bfd_set_section_alignment (rdata_section, 2); |
252b5132 RH |
5918 | } |
5919 | else | |
5920 | { | |
5921 | rdata_section = subseg_new (".rdata", 0); | |
5922 | } | |
99a814a1 | 5923 | ppc_set_current_section (rdata_section); |
252b5132 RH |
5924 | } |
5925 | ||
5926 | /* pseudo-op: .ualong | |
81d4177b | 5927 | behaviour: much like .int, with the exception that no alignment is |
b34976b6 | 5928 | performed. |
252b5132 RH |
5929 | FIXME: test the alignment statement |
5930 | errors: None | |
99a814a1 AM |
5931 | warnings: None */ |
5932 | ||
252b5132 | 5933 | static void |
98027b10 | 5934 | ppc_ualong (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5935 | { |
99a814a1 AM |
5936 | /* Try for long. */ |
5937 | cons (4); | |
252b5132 RH |
5938 | } |
5939 | ||
5940 | /* pseudo-op: .znop <symbol name> | |
5941 | behaviour: Issue a nop instruction | |
b34976b6 | 5942 | Issue a IMAGE_REL_PPC_IFGLUE relocation against it, using |
252b5132 RH |
5943 | the supplied symbol name. |
5944 | errors: None | |
99a814a1 AM |
5945 | warnings: Missing symbol name */ |
5946 | ||
252b5132 | 5947 | static void |
98027b10 | 5948 | ppc_znop (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5949 | { |
5950 | unsigned long insn; | |
5951 | const struct powerpc_opcode *opcode; | |
252b5132 | 5952 | char *f; |
252b5132 | 5953 | symbolS *sym; |
252b5132 RH |
5954 | char *symbol_name; |
5955 | char c; | |
5956 | char *name; | |
252b5132 | 5957 | |
99a814a1 | 5958 | /* Strip out the symbol name. */ |
d02603dc | 5959 | c = get_symbol_name (&symbol_name); |
252b5132 | 5960 | |
a44e2901 | 5961 | name = xstrdup (symbol_name); |
252b5132 RH |
5962 | |
5963 | sym = symbol_find_or_make (name); | |
5964 | ||
5965 | *input_line_pointer = c; | |
5966 | ||
d02603dc | 5967 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
5968 | |
5969 | /* Look up the opcode in the hash table. */ | |
5970 | opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, "nop"); | |
5971 | ||
99a814a1 | 5972 | /* Stick in the nop. */ |
252b5132 RH |
5973 | insn = opcode->opcode; |
5974 | ||
5975 | /* Write out the instruction. */ | |
5976 | f = frag_more (4); | |
5977 | md_number_to_chars (f, insn, 4); | |
5978 | fix_new (frag_now, | |
5979 | f - frag_now->fr_literal, | |
5980 | 4, | |
5981 | sym, | |
5982 | 0, | |
5983 | 0, | |
5984 | BFD_RELOC_16_GOT_PCREL); | |
5985 | ||
5986 | } | |
5987 | ||
81d4177b KH |
5988 | /* pseudo-op: |
5989 | behaviour: | |
5990 | errors: | |
99a814a1 AM |
5991 | warnings: */ |
5992 | ||
252b5132 | 5993 | static void |
98027b10 | 5994 | ppc_pe_comm (int lcomm) |
252b5132 | 5995 | { |
98027b10 AM |
5996 | char *name; |
5997 | char c; | |
5998 | char *p; | |
252b5132 | 5999 | offsetT temp; |
98027b10 | 6000 | symbolS *symbolP; |
252b5132 RH |
6001 | offsetT align; |
6002 | ||
d02603dc | 6003 | c = get_symbol_name (&name); |
252b5132 | 6004 | |
99a814a1 | 6005 | /* just after name is now '\0'. */ |
252b5132 RH |
6006 | p = input_line_pointer; |
6007 | *p = c; | |
d02603dc | 6008 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
6009 | if (*input_line_pointer != ',') |
6010 | { | |
d6ed37ed | 6011 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
6012 | ignore_rest_of_line (); |
6013 | return; | |
6014 | } | |
6015 | ||
6016 | input_line_pointer++; /* skip ',' */ | |
6017 | if ((temp = get_absolute_expression ()) < 0) | |
6018 | { | |
6019 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) temp); | |
6020 | ignore_rest_of_line (); | |
6021 | return; | |
6022 | } | |
6023 | ||
6024 | if (! lcomm) | |
6025 | { | |
6026 | /* The third argument to .comm is the alignment. */ | |
6027 | if (*input_line_pointer != ',') | |
6028 | align = 3; | |
6029 | else | |
6030 | { | |
6031 | ++input_line_pointer; | |
6032 | align = get_absolute_expression (); | |
6033 | if (align <= 0) | |
6034 | { | |
6035 | as_warn (_("ignoring bad alignment")); | |
6036 | align = 3; | |
6037 | } | |
6038 | } | |
6039 | } | |
6040 | ||
6041 | *p = 0; | |
6042 | symbolP = symbol_find_or_make (name); | |
6043 | ||
6044 | *p = c; | |
6045 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
6046 | { | |
d6ed37ed | 6047 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
6048 | S_GET_NAME (symbolP)); |
6049 | ignore_rest_of_line (); | |
6050 | return; | |
6051 | } | |
6052 | ||
6053 | if (S_GET_VALUE (symbolP)) | |
6054 | { | |
6055 | if (S_GET_VALUE (symbolP) != (valueT) temp) | |
d6ed37ed | 6056 | as_bad (_("length of .comm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
6057 | S_GET_NAME (symbolP), |
6058 | (long) S_GET_VALUE (symbolP), | |
6059 | (long) temp); | |
6060 | } | |
6061 | else | |
6062 | { | |
6063 | S_SET_VALUE (symbolP, (valueT) temp); | |
6064 | S_SET_EXTERNAL (symbolP); | |
86ebace2 | 6065 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); |
252b5132 RH |
6066 | } |
6067 | ||
6068 | demand_empty_rest_of_line (); | |
6069 | } | |
6070 | ||
6071 | /* | |
6072 | * implement the .section pseudo op: | |
6073 | * .section name {, "flags"} | |
6074 | * ^ ^ | |
6075 | * | +--- optional flags: 'b' for bss | |
6076 | * | 'i' for info | |
6077 | * +-- section name 'l' for lib | |
6078 | * 'n' for noload | |
6079 | * 'o' for over | |
6080 | * 'w' for data | |
6081 | * 'd' (apparently m88k for data) | |
6082 | * 'x' for text | |
6083 | * But if the argument is not a quoted string, treat it as a | |
6084 | * subsegment number. | |
6085 | * | |
6086 | * FIXME: this is a copy of the section processing from obj-coff.c, with | |
6087 | * additions/changes for the moto-pas assembler support. There are three | |
6088 | * categories: | |
6089 | * | |
81d4177b | 6090 | * FIXME: I just noticed this. This doesn't work at all really. It it |
252b5132 RH |
6091 | * setting bits that bfd probably neither understands or uses. The |
6092 | * correct approach (?) will have to incorporate extra fields attached | |
6093 | * to the section to hold the system specific stuff. (krk) | |
6094 | * | |
6095 | * Section Contents: | |
6096 | * 'a' - unknown - referred to in documentation, but no definition supplied | |
6097 | * 'c' - section has code | |
6098 | * 'd' - section has initialized data | |
6099 | * 'u' - section has uninitialized data | |
6100 | * 'i' - section contains directives (info) | |
6101 | * 'n' - section can be discarded | |
6102 | * 'R' - remove section at link time | |
6103 | * | |
6104 | * Section Protection: | |
6105 | * 'r' - section is readable | |
33eaf5de | 6106 | * 'w' - section is writable |
252b5132 RH |
6107 | * 'x' - section is executable |
6108 | * 's' - section is sharable | |
6109 | * | |
6110 | * Section Alignment: | |
6111 | * '0' - align to byte boundary | |
33eaf5de | 6112 | * '1' - align to halfword boundary |
252b5132 RH |
6113 | * '2' - align to word boundary |
6114 | * '3' - align to doubleword boundary | |
6115 | * '4' - align to quadword boundary | |
6116 | * '5' - align to 32 byte boundary | |
6117 | * '6' - align to 64 byte boundary | |
6118 | * | |
6119 | */ | |
6120 | ||
6121 | void | |
98027b10 | 6122 | ppc_pe_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 6123 | { |
99a814a1 | 6124 | /* Strip out the section name. */ |
252b5132 RH |
6125 | char *section_name; |
6126 | char c; | |
6127 | char *name; | |
6128 | unsigned int exp; | |
6129 | flagword flags; | |
6130 | segT sec; | |
6131 | int align; | |
6132 | ||
d02603dc | 6133 | c = get_symbol_name (§ion_name); |
252b5132 | 6134 | |
a44e2901 | 6135 | name = xstrdup (section_name); |
252b5132 RH |
6136 | |
6137 | *input_line_pointer = c; | |
6138 | ||
d02603dc | 6139 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
6140 | |
6141 | exp = 0; | |
6142 | flags = SEC_NO_FLAGS; | |
6143 | ||
6144 | if (strcmp (name, ".idata$2") == 0) | |
6145 | { | |
6146 | align = 0; | |
6147 | } | |
6148 | else if (strcmp (name, ".idata$3") == 0) | |
6149 | { | |
6150 | align = 0; | |
6151 | } | |
6152 | else if (strcmp (name, ".idata$4") == 0) | |
6153 | { | |
6154 | align = 2; | |
6155 | } | |
6156 | else if (strcmp (name, ".idata$5") == 0) | |
6157 | { | |
6158 | align = 2; | |
6159 | } | |
6160 | else if (strcmp (name, ".idata$6") == 0) | |
6161 | { | |
6162 | align = 1; | |
6163 | } | |
6164 | else | |
99a814a1 AM |
6165 | /* Default alignment to 16 byte boundary. */ |
6166 | align = 4; | |
252b5132 RH |
6167 | |
6168 | if (*input_line_pointer == ',') | |
6169 | { | |
6170 | ++input_line_pointer; | |
6171 | SKIP_WHITESPACE (); | |
6172 | if (*input_line_pointer != '"') | |
6173 | exp = get_absolute_expression (); | |
6174 | else | |
6175 | { | |
6176 | ++input_line_pointer; | |
6177 | while (*input_line_pointer != '"' | |
6178 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6179 | { | |
6180 | switch (*input_line_pointer) | |
6181 | { | |
6182 | /* Section Contents */ | |
6183 | case 'a': /* unknown */ | |
d6ed37ed | 6184 | as_bad (_("unsupported section attribute -- 'a'")); |
252b5132 RH |
6185 | break; |
6186 | case 'c': /* code section */ | |
81d4177b | 6187 | flags |= SEC_CODE; |
252b5132 RH |
6188 | break; |
6189 | case 'd': /* section has initialized data */ | |
6190 | flags |= SEC_DATA; | |
6191 | break; | |
6192 | case 'u': /* section has uninitialized data */ | |
6193 | /* FIXME: This is IMAGE_SCN_CNT_UNINITIALIZED_DATA | |
6194 | in winnt.h */ | |
6195 | flags |= SEC_ROM; | |
6196 | break; | |
6197 | case 'i': /* section contains directives (info) */ | |
6198 | /* FIXME: This is IMAGE_SCN_LNK_INFO | |
6199 | in winnt.h */ | |
6200 | flags |= SEC_HAS_CONTENTS; | |
6201 | break; | |
6202 | case 'n': /* section can be discarded */ | |
81d4177b | 6203 | flags &=~ SEC_LOAD; |
252b5132 RH |
6204 | break; |
6205 | case 'R': /* Remove section at link time */ | |
6206 | flags |= SEC_NEVER_LOAD; | |
6207 | break; | |
8d452c78 | 6208 | #if IFLICT_BRAIN_DAMAGE |
252b5132 RH |
6209 | /* Section Protection */ |
6210 | case 'r': /* section is readable */ | |
6211 | flags |= IMAGE_SCN_MEM_READ; | |
6212 | break; | |
33eaf5de | 6213 | case 'w': /* section is writable */ |
252b5132 RH |
6214 | flags |= IMAGE_SCN_MEM_WRITE; |
6215 | break; | |
6216 | case 'x': /* section is executable */ | |
6217 | flags |= IMAGE_SCN_MEM_EXECUTE; | |
6218 | break; | |
6219 | case 's': /* section is sharable */ | |
6220 | flags |= IMAGE_SCN_MEM_SHARED; | |
6221 | break; | |
6222 | ||
6223 | /* Section Alignment */ | |
6224 | case '0': /* align to byte boundary */ | |
6225 | flags |= IMAGE_SCN_ALIGN_1BYTES; | |
6226 | align = 0; | |
6227 | break; | |
6228 | case '1': /* align to halfword boundary */ | |
6229 | flags |= IMAGE_SCN_ALIGN_2BYTES; | |
6230 | align = 1; | |
6231 | break; | |
6232 | case '2': /* align to word boundary */ | |
6233 | flags |= IMAGE_SCN_ALIGN_4BYTES; | |
6234 | align = 2; | |
6235 | break; | |
6236 | case '3': /* align to doubleword boundary */ | |
6237 | flags |= IMAGE_SCN_ALIGN_8BYTES; | |
6238 | align = 3; | |
6239 | break; | |
6240 | case '4': /* align to quadword boundary */ | |
6241 | flags |= IMAGE_SCN_ALIGN_16BYTES; | |
6242 | align = 4; | |
6243 | break; | |
6244 | case '5': /* align to 32 byte boundary */ | |
6245 | flags |= IMAGE_SCN_ALIGN_32BYTES; | |
6246 | align = 5; | |
6247 | break; | |
6248 | case '6': /* align to 64 byte boundary */ | |
6249 | flags |= IMAGE_SCN_ALIGN_64BYTES; | |
6250 | align = 6; | |
6251 | break; | |
8d452c78 | 6252 | #endif |
252b5132 | 6253 | default: |
99a814a1 AM |
6254 | as_bad (_("unknown section attribute '%c'"), |
6255 | *input_line_pointer); | |
252b5132 RH |
6256 | break; |
6257 | } | |
6258 | ++input_line_pointer; | |
6259 | } | |
6260 | if (*input_line_pointer == '"') | |
6261 | ++input_line_pointer; | |
6262 | } | |
6263 | } | |
6264 | ||
6265 | sec = subseg_new (name, (subsegT) exp); | |
6266 | ||
99a814a1 | 6267 | ppc_set_current_section (sec); |
252b5132 RH |
6268 | |
6269 | if (flags != SEC_NO_FLAGS) | |
6270 | { | |
fd361982 | 6271 | if (!bfd_set_section_flags (sec, flags)) |
252b5132 | 6272 | as_bad (_("error setting flags for \"%s\": %s"), |
fd361982 | 6273 | bfd_section_name (sec), |
252b5132 RH |
6274 | bfd_errmsg (bfd_get_error ())); |
6275 | } | |
6276 | ||
fd361982 | 6277 | bfd_set_section_alignment (sec, align); |
252b5132 RH |
6278 | } |
6279 | ||
6280 | static void | |
98027b10 | 6281 | ppc_pe_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6282 | { |
6283 | char *name; | |
6284 | char endc; | |
6285 | symbolS *ext_sym; | |
6286 | ||
d02603dc | 6287 | endc = get_symbol_name (&name); |
252b5132 RH |
6288 | |
6289 | ext_sym = symbol_find_or_make (name); | |
6290 | ||
d02603dc | 6291 | (void) restore_line_pointer (endc); |
252b5132 RH |
6292 | |
6293 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
6294 | SF_SET_FUNCTION (ext_sym); | |
6295 | SF_SET_PROCESS (ext_sym); | |
6296 | coff_add_linesym (ext_sym); | |
6297 | ||
6298 | demand_empty_rest_of_line (); | |
6299 | } | |
6300 | ||
6301 | static void | |
98027b10 | 6302 | ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6303 | { |
6304 | if (tocdata_section == 0) | |
6305 | { | |
6306 | tocdata_section = subseg_new (".tocd", 0); | |
99a814a1 | 6307 | /* FIXME: section flags won't work. */ |
fd361982 AM |
6308 | bfd_set_section_flags (tocdata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
6309 | | SEC_READONLY | SEC_DATA)); | |
252b5132 | 6310 | |
fd361982 | 6311 | bfd_set_section_alignment (tocdata_section, 2); |
252b5132 RH |
6312 | } |
6313 | else | |
6314 | { | |
6315 | rdata_section = subseg_new (".tocd", 0); | |
6316 | } | |
6317 | ||
99a814a1 | 6318 | ppc_set_current_section (tocdata_section); |
252b5132 RH |
6319 | |
6320 | demand_empty_rest_of_line (); | |
6321 | } | |
6322 | ||
6323 | /* Don't adjust TOC relocs to use the section symbol. */ | |
6324 | ||
6325 | int | |
98027b10 | 6326 | ppc_pe_fix_adjustable (fixS *fix) |
252b5132 RH |
6327 | { |
6328 | return fix->fx_r_type != BFD_RELOC_PPC_TOC16; | |
6329 | } | |
6330 | ||
6331 | #endif | |
6332 | \f | |
6333 | #ifdef OBJ_XCOFF | |
6334 | ||
6335 | /* XCOFF specific symbol and file handling. */ | |
6336 | ||
6337 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
6338 | any, to use square brackets, and to be in upper case. */ | |
6339 | ||
6340 | char * | |
98027b10 | 6341 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
6342 | { |
6343 | char *s; | |
6344 | ||
6345 | if (ppc_stab_symbol) | |
6346 | return name; | |
6347 | ||
6348 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
6349 | ; | |
6350 | if (*s != '\0') | |
6351 | { | |
6352 | char brac; | |
6353 | ||
6354 | if (*s == '[') | |
6355 | brac = ']'; | |
6356 | else | |
6357 | { | |
6358 | *s = '['; | |
6359 | brac = '}'; | |
6360 | } | |
6361 | ||
6362 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 6363 | *s = TOUPPER (*s); |
252b5132 RH |
6364 | |
6365 | if (*s == '\0' || s[1] != '\0') | |
6366 | as_bad (_("bad symbol suffix")); | |
6367 | ||
6368 | *s = ']'; | |
6369 | } | |
6370 | ||
6371 | return name; | |
6372 | } | |
6373 | ||
6374 | /* Set the class of a symbol based on the suffix, if any. This is | |
6375 | called whenever a new symbol is created. */ | |
6376 | ||
6377 | void | |
98027b10 | 6378 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 6379 | { |
809ffe0d | 6380 | struct ppc_tc_sy *tc; |
252b5132 RH |
6381 | const char *s; |
6382 | ||
809ffe0d ILT |
6383 | tc = symbol_get_tc (sym); |
6384 | tc->next = NULL; | |
6385 | tc->output = 0; | |
96d56e9f | 6386 | tc->symbol_class = -1; |
809ffe0d ILT |
6387 | tc->real_name = NULL; |
6388 | tc->subseg = 0; | |
6389 | tc->align = 0; | |
85645aed TG |
6390 | tc->u.size = NULL; |
6391 | tc->u.dw = NULL; | |
809ffe0d | 6392 | tc->within = NULL; |
252b5132 RH |
6393 | |
6394 | if (ppc_stab_symbol) | |
6395 | return; | |
6396 | ||
6397 | s = strchr (S_GET_NAME (sym), '['); | |
6398 | if (s == (const char *) NULL) | |
6399 | { | |
6400 | /* There is no suffix. */ | |
6401 | return; | |
6402 | } | |
6403 | ||
6404 | ++s; | |
6405 | ||
6406 | switch (s[0]) | |
6407 | { | |
6408 | case 'B': | |
6409 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 6410 | tc->symbol_class = XMC_BS; |
252b5132 RH |
6411 | break; |
6412 | case 'D': | |
6413 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 6414 | tc->symbol_class = XMC_DB; |
252b5132 | 6415 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 6416 | tc->symbol_class = XMC_DS; |
252b5132 RH |
6417 | break; |
6418 | case 'G': | |
6419 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 6420 | tc->symbol_class = XMC_GL; |
252b5132 RH |
6421 | break; |
6422 | case 'P': | |
6423 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 6424 | tc->symbol_class = XMC_PR; |
252b5132 RH |
6425 | break; |
6426 | case 'R': | |
6427 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 6428 | tc->symbol_class = XMC_RO; |
252b5132 | 6429 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 6430 | tc->symbol_class = XMC_RW; |
252b5132 RH |
6431 | break; |
6432 | case 'S': | |
6433 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 6434 | tc->symbol_class = XMC_SV; |
252b5132 RH |
6435 | break; |
6436 | case 'T': | |
6437 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 6438 | tc->symbol_class = XMC_TC; |
252b5132 | 6439 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 6440 | tc->symbol_class = XMC_TI; |
252b5132 | 6441 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 6442 | tc->symbol_class = XMC_TB; |
252b5132 | 6443 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 6444 | tc->symbol_class = XMC_TC0; |
252b5132 RH |
6445 | break; |
6446 | case 'U': | |
6447 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 6448 | tc->symbol_class = XMC_UA; |
252b5132 | 6449 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 6450 | tc->symbol_class = XMC_UC; |
252b5132 RH |
6451 | break; |
6452 | case 'X': | |
6453 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 6454 | tc->symbol_class = XMC_XO; |
252b5132 RH |
6455 | break; |
6456 | } | |
6457 | ||
96d56e9f | 6458 | if (tc->symbol_class == -1) |
d6ed37ed | 6459 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
6460 | } |
6461 | ||
252b5132 RH |
6462 | /* This variable is set by ppc_frob_symbol if any absolute symbols are |
6463 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
6464 | the symbols. */ | |
6465 | ||
b34976b6 | 6466 | static bfd_boolean ppc_saw_abs; |
252b5132 RH |
6467 | |
6468 | /* Change the name of a symbol just before writing it out. Set the | |
6469 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
6470 | class suffix. Return 1 if the symbol should not be included in the | |
6471 | symbol table. */ | |
6472 | ||
6473 | int | |
98027b10 | 6474 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
6475 | { |
6476 | static symbolS *ppc_last_function; | |
6477 | static symbolS *set_end; | |
6478 | ||
6479 | /* Discard symbols that should not be included in the output symbol | |
6480 | table. */ | |
809ffe0d ILT |
6481 | if (! symbol_used_in_reloc_p (sym) |
6482 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 | |
670ec21d | 6483 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6484 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
6485 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
6486 | return 1; | |
6487 | ||
a161fe53 AM |
6488 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
6489 | if (sym == abs_section_sym) | |
6490 | return 1; | |
6491 | ||
809ffe0d ILT |
6492 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
6493 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
6494 | else |
6495 | { | |
6496 | const char *name; | |
6497 | const char *s; | |
6498 | ||
6499 | name = S_GET_NAME (sym); | |
6500 | s = strchr (name, '['); | |
6501 | if (s != (char *) NULL) | |
6502 | { | |
6503 | unsigned int len; | |
6504 | char *snew; | |
6505 | ||
6506 | len = s - name; | |
a44e2901 | 6507 | snew = xstrndup (name, len); |
252b5132 RH |
6508 | |
6509 | S_SET_NAME (sym, snew); | |
6510 | } | |
6511 | } | |
6512 | ||
6513 | if (set_end != (symbolS *) NULL) | |
6514 | { | |
6515 | SA_SET_SYM_ENDNDX (set_end, sym); | |
6516 | set_end = NULL; | |
6517 | } | |
6518 | ||
6519 | if (SF_GET_FUNCTION (sym)) | |
6520 | { | |
6521 | if (ppc_last_function != (symbolS *) NULL) | |
6522 | as_bad (_("two .function pseudo-ops with no intervening .ef")); | |
6523 | ppc_last_function = sym; | |
85645aed | 6524 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 6525 | { |
85645aed | 6526 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 6527 | SA_SET_SYM_FSIZE (sym, |
85645aed | 6528 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 RH |
6529 | } |
6530 | } | |
6531 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
6532 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
6533 | { | |
6534 | if (ppc_last_function == (symbolS *) NULL) | |
6535 | as_bad (_(".ef with no preceding .function")); | |
6536 | else | |
6537 | { | |
6538 | set_end = ppc_last_function; | |
6539 | ppc_last_function = NULL; | |
6540 | ||
6541 | /* We don't have a C_EFCN symbol, but we need to force the | |
6542 | COFF backend to believe that it has seen one. */ | |
6543 | coff_last_function = NULL; | |
6544 | } | |
6545 | } | |
6546 | ||
670ec21d | 6547 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6548 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
6549 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
6550 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
6551 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
6552 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
6553 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
6554 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
6555 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
6556 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
6557 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
6558 | ||
6559 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 6560 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
6561 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
6562 | { | |
6563 | int i; | |
6564 | union internal_auxent *a; | |
6565 | ||
6566 | /* Create a csect aux. */ | |
6567 | i = S_GET_NUMBER_AUXILIARY (sym); | |
6568 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 6569 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 6570 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
6571 | { |
6572 | /* This is the TOC table. */ | |
6573 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
6574 | a->x_csect.x_scnlen.l = 0; | |
6575 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6576 | } | |
809ffe0d | 6577 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
6578 | { |
6579 | /* This is a csect symbol. x_scnlen is the size of the | |
6580 | csect. */ | |
809ffe0d | 6581 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
fd361982 | 6582 | a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym)) |
252b5132 RH |
6583 | - S_GET_VALUE (sym)); |
6584 | else | |
6585 | { | |
6386f3a7 | 6586 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 6587 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
6588 | - S_GET_VALUE (sym)); |
6589 | } | |
809ffe0d | 6590 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; |
252b5132 RH |
6591 | } |
6592 | else if (S_GET_SEGMENT (sym) == bss_section) | |
6593 | { | |
6594 | /* This is a common symbol. */ | |
809ffe0d ILT |
6595 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
6596 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
252b5132 | 6597 | if (S_IS_EXTERNAL (sym)) |
96d56e9f | 6598 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 6599 | else |
96d56e9f | 6600 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
6601 | } |
6602 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
6603 | { | |
6604 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 6605 | ppc_adjust_symtab. */ |
b34976b6 | 6606 | ppc_saw_abs = TRUE; |
252b5132 | 6607 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
6608 | if (symbol_get_tc (sym)->symbol_class == -1) |
6609 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
6610 | } |
6611 | else if (! S_IS_DEFINED (sym)) | |
6612 | { | |
6613 | /* This is an external symbol. */ | |
6614 | a->x_csect.x_scnlen.l = 0; | |
6615 | a->x_csect.x_smtyp = XTY_ER; | |
6616 | } | |
96d56e9f | 6617 | else if (symbol_get_tc (sym)->symbol_class == XMC_TC) |
252b5132 RH |
6618 | { |
6619 | symbolS *next; | |
6620 | ||
6621 | /* This is a TOC definition. x_scnlen is the size of the | |
6622 | TOC entry. */ | |
6623 | next = symbol_next (sym); | |
96d56e9f | 6624 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
6625 | next = symbol_next (next); |
6626 | if (next == (symbolS *) NULL | |
96d56e9f | 6627 | || symbol_get_tc (next)->symbol_class != XMC_TC) |
252b5132 RH |
6628 | { |
6629 | if (ppc_after_toc_frag == (fragS *) NULL) | |
fd361982 | 6630 | a->x_csect.x_scnlen.l = (bfd_section_size (data_section) |
252b5132 RH |
6631 | - S_GET_VALUE (sym)); |
6632 | else | |
6633 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
6634 | - S_GET_VALUE (sym)); | |
6635 | } | |
6636 | else | |
6637 | { | |
6386f3a7 | 6638 | resolve_symbol_value (next); |
252b5132 RH |
6639 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
6640 | - S_GET_VALUE (sym)); | |
6641 | } | |
6642 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6643 | } | |
6644 | else | |
6645 | { | |
6646 | symbolS *csect; | |
6647 | ||
6648 | /* This is a normal symbol definition. x_scnlen is the | |
6649 | symbol index of the containing csect. */ | |
6650 | if (S_GET_SEGMENT (sym) == text_section) | |
6651 | csect = ppc_text_csects; | |
6652 | else if (S_GET_SEGMENT (sym) == data_section) | |
6653 | csect = ppc_data_csects; | |
6654 | else | |
6655 | abort (); | |
6656 | ||
6657 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 6658 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6659 | |
6660 | if (csect == (symbolS *) NULL) | |
6661 | { | |
6662 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
6663 | a->x_csect.x_scnlen.l = 0; | |
6664 | } | |
6665 | else | |
6666 | { | |
809ffe0d | 6667 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 6668 | { |
6386f3a7 | 6669 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
6670 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
6671 | > S_GET_VALUE (sym)) | |
252b5132 | 6672 | break; |
809ffe0d | 6673 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6674 | } |
6675 | ||
809ffe0d ILT |
6676 | a->x_csect.x_scnlen.p = |
6677 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
6678 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
6679 | 1; | |
252b5132 RH |
6680 | } |
6681 | a->x_csect.x_smtyp = XTY_LD; | |
6682 | } | |
81d4177b | 6683 | |
252b5132 RH |
6684 | a->x_csect.x_parmhash = 0; |
6685 | a->x_csect.x_snhash = 0; | |
96d56e9f | 6686 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
6687 | a->x_csect.x_smclas = XMC_PR; |
6688 | else | |
96d56e9f | 6689 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
6690 | a->x_csect.x_stab = 0; |
6691 | a->x_csect.x_snstab = 0; | |
6692 | ||
6693 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 6694 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
6695 | } |
6696 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
6697 | { | |
6698 | /* We want the value to be the symbol index of the referenced | |
6699 | csect symbol. BFD will do that for us if we set the right | |
6700 | flags. */ | |
b782de16 AM |
6701 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
6702 | combined_entry_type *c = coffsymbol (bsym)->native; | |
6703 | ||
6704 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 6705 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
6706 | } |
6707 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
6708 | { | |
6709 | symbolS *block; | |
c734e7e3 | 6710 | valueT base; |
252b5132 | 6711 | |
809ffe0d | 6712 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
6713 | if (block) |
6714 | { | |
6715 | /* The value is the offset from the enclosing csect. */ | |
6716 | symbolS *csect; | |
6717 | ||
6718 | csect = symbol_get_tc (block)->within; | |
6719 | resolve_symbol_value (csect); | |
6720 | base = S_GET_VALUE (csect); | |
6721 | } | |
6722 | else | |
6723 | base = 0; | |
6724 | ||
6725 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
6726 | } |
6727 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
6728 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
6729 | { | |
6730 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
6731 | BFD will do that for us if we set the right flags. We have |
6732 | already set the value correctly. */ | |
809ffe0d | 6733 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
6734 | } |
6735 | ||
6736 | return 0; | |
6737 | } | |
6738 | ||
6739 | /* Adjust the symbol table. This creates csect symbols for all | |
6740 | absolute symbols. */ | |
6741 | ||
6742 | void | |
98027b10 | 6743 | ppc_adjust_symtab (void) |
252b5132 RH |
6744 | { |
6745 | symbolS *sym; | |
6746 | ||
6747 | if (! ppc_saw_abs) | |
6748 | return; | |
6749 | ||
6750 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
6751 | { | |
6752 | symbolS *csect; | |
6753 | int i; | |
6754 | union internal_auxent *a; | |
6755 | ||
6756 | if (S_GET_SEGMENT (sym) != absolute_section) | |
6757 | continue; | |
6758 | ||
6759 | csect = symbol_create (".abs[XO]", absolute_section, | |
6760 | S_GET_VALUE (sym), &zero_address_frag); | |
809ffe0d | 6761 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
6762 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
6763 | i = S_GET_NUMBER_AUXILIARY (csect); | |
6764 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 6765 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
6766 | a->x_csect.x_scnlen.l = 0; |
6767 | a->x_csect.x_smtyp = XTY_SD; | |
6768 | a->x_csect.x_parmhash = 0; | |
6769 | a->x_csect.x_snhash = 0; | |
6770 | a->x_csect.x_smclas = XMC_XO; | |
6771 | a->x_csect.x_stab = 0; | |
6772 | a->x_csect.x_snstab = 0; | |
6773 | ||
6774 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
6775 | ||
6776 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
6777 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
6778 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
6779 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
6780 | } |
6781 | ||
b34976b6 | 6782 | ppc_saw_abs = FALSE; |
252b5132 RH |
6783 | } |
6784 | ||
6785 | /* Set the VMA for a section. This is called on all the sections in | |
6786 | turn. */ | |
6787 | ||
6788 | void | |
98027b10 | 6789 | ppc_frob_section (asection *sec) |
252b5132 | 6790 | { |
931e13a6 | 6791 | static bfd_vma vma = 0; |
252b5132 | 6792 | |
85645aed | 6793 | /* Dwarf sections start at 0. */ |
fd361982 | 6794 | if (bfd_section_flags (sec) & SEC_DEBUGGING) |
85645aed TG |
6795 | return; |
6796 | ||
931e13a6 | 6797 | vma = md_section_align (sec, vma); |
fd361982 AM |
6798 | bfd_set_section_vma (sec, vma); |
6799 | vma += bfd_section_size (sec); | |
252b5132 RH |
6800 | } |
6801 | ||
6802 | #endif /* OBJ_XCOFF */ | |
6803 | \f | |
6d4af3c2 | 6804 | const char * |
98027b10 | 6805 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 6806 | { |
499ac353 | 6807 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
6808 | } |
6809 | ||
6810 | /* Write a value out to the object file, using the appropriate | |
6811 | endianness. */ | |
6812 | ||
6813 | void | |
98027b10 | 6814 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
6815 | { |
6816 | if (target_big_endian) | |
6817 | number_to_chars_bigendian (buf, val, n); | |
6818 | else | |
6819 | number_to_chars_littleendian (buf, val, n); | |
6820 | } | |
6821 | ||
6822 | /* Align a section (I don't know why this is machine dependent). */ | |
6823 | ||
6824 | valueT | |
3aeeedbb | 6825 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 6826 | { |
3aeeedbb AM |
6827 | #ifdef OBJ_ELF |
6828 | return addr; | |
6829 | #else | |
fd361982 | 6830 | int align = bfd_section_alignment (seg); |
252b5132 | 6831 | |
8d3842cd | 6832 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 6833 | #endif |
252b5132 RH |
6834 | } |
6835 | ||
6836 | /* We don't have any form of relaxing. */ | |
6837 | ||
6838 | int | |
98027b10 AM |
6839 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
6840 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
6841 | { |
6842 | abort (); | |
6843 | return 0; | |
6844 | } | |
6845 | ||
6846 | /* Convert a machine dependent frag. We never generate these. */ | |
6847 | ||
6848 | void | |
98027b10 AM |
6849 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
6850 | asection *sec ATTRIBUTE_UNUSED, | |
6851 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
6852 | { |
6853 | abort (); | |
6854 | } | |
6855 | ||
6856 | /* We have no need to default values of symbols. */ | |
6857 | ||
252b5132 | 6858 | symbolS * |
98027b10 | 6859 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6860 | { |
6861 | return 0; | |
6862 | } | |
6863 | \f | |
6864 | /* Functions concerning relocs. */ | |
6865 | ||
6866 | /* The location from which a PC relative jump should be calculated, | |
6867 | given a PC relative reloc. */ | |
6868 | ||
6869 | long | |
98027b10 | 6870 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6871 | { |
6872 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6873 | } | |
6874 | ||
6875 | #ifdef OBJ_XCOFF | |
6876 | ||
6877 | /* This is called to see whether a fixup should be adjusted to use a | |
6878 | section symbol. We take the opportunity to change a fixup against | |
6879 | a symbol in the TOC subsegment into a reloc against the | |
6880 | corresponding .tc symbol. */ | |
6881 | ||
6882 | int | |
98027b10 | 6883 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6884 | { |
b782de16 AM |
6885 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6886 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
6887 | TC_SYMFIELD_TYPE *tc; | |
6888 | ||
6889 | if (symseg == absolute_section) | |
6890 | return 0; | |
252b5132 | 6891 | |
85645aed | 6892 | /* Always adjust symbols in debugging sections. */ |
fd361982 | 6893 | if (bfd_section_flags (symseg) & SEC_DEBUGGING) |
85645aed TG |
6894 | return 1; |
6895 | ||
252b5132 | 6896 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6897 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6898 | && symseg == data_section |
252b5132 RH |
6899 | && val >= ppc_toc_frag->fr_address |
6900 | && (ppc_after_toc_frag == (fragS *) NULL | |
6901 | || val < ppc_after_toc_frag->fr_address)) | |
6902 | { | |
6903 | symbolS *sy; | |
6904 | ||
6905 | for (sy = symbol_next (ppc_toc_csect); | |
6906 | sy != (symbolS *) NULL; | |
6907 | sy = symbol_next (sy)) | |
6908 | { | |
b782de16 AM |
6909 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6910 | ||
96d56e9f | 6911 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6912 | continue; |
96d56e9f | 6913 | if (sy_tc->symbol_class != XMC_TC) |
252b5132 | 6914 | break; |
b782de16 | 6915 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6916 | { |
6917 | fix->fx_addsy = sy; | |
6918 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6919 | return 0; | |
6920 | } | |
6921 | } | |
6922 | ||
6923 | as_bad_where (fix->fx_file, fix->fx_line, | |
6924 | _("symbol in .toc does not match any .tc")); | |
6925 | } | |
6926 | ||
6927 | /* Possibly adjust the reloc to be against the csect. */ | |
b782de16 AM |
6928 | tc = symbol_get_tc (fix->fx_addsy); |
6929 | if (tc->subseg == 0 | |
96d56e9f NC |
6930 | && tc->symbol_class != XMC_TC0 |
6931 | && tc->symbol_class != XMC_TC | |
b782de16 | 6932 | && symseg != bss_section |
252b5132 | 6933 | /* Don't adjust if this is a reloc in the toc section. */ |
b782de16 | 6934 | && (symseg != data_section |
252b5132 RH |
6935 | || ppc_toc_csect == NULL |
6936 | || val < ppc_toc_frag->fr_address | |
6937 | || (ppc_after_toc_frag != NULL | |
6938 | && val >= ppc_after_toc_frag->fr_address))) | |
6939 | { | |
2fb4b302 | 6940 | symbolS *csect = tc->within; |
252b5132 | 6941 | |
2fb4b302 TG |
6942 | /* If the symbol was not declared by a label (eg: a section symbol), |
6943 | use the section instead of the csect. This doesn't happen in | |
6944 | normal AIX assembly code. */ | |
6945 | if (csect == NULL) | |
6946 | csect = seg_info (symseg)->sym; | |
252b5132 | 6947 | |
2fb4b302 TG |
6948 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6949 | fix->fx_addsy = csect; | |
252b5132 | 6950 | |
b782de16 | 6951 | return 0; |
252b5132 RH |
6952 | } |
6953 | ||
6954 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6955 | .lcomm. */ | |
b782de16 | 6956 | if (symseg == bss_section |
252b5132 RH |
6957 | && ! S_IS_EXTERNAL (fix->fx_addsy)) |
6958 | { | |
b782de16 AM |
6959 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6960 | ||
6961 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6962 | fix->fx_addsy = sy; | |
252b5132 RH |
6963 | } |
6964 | ||
6965 | return 0; | |
6966 | } | |
6967 | ||
6968 | /* A reloc from one csect to another must be kept. The assembler | |
6969 | will, of course, keep relocs between sections, and it will keep | |
6970 | absolute relocs, but we need to force it to keep PC relative relocs | |
6971 | between two csects in the same section. */ | |
6972 | ||
6973 | int | |
98027b10 | 6974 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6975 | { |
6976 | /* At this point fix->fx_addsy should already have been converted to | |
6977 | a csect symbol. If the csect does not include the fragment, then | |
6978 | we need to force the relocation. */ | |
6979 | if (fix->fx_pcrel | |
6980 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6981 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6982 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6983 | > fix->fx_frag->fr_address) | |
6984 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6985 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6986 | <= fix->fx_frag->fr_address)))) |
6987 | return 1; | |
6988 | ||
ae6063d4 | 6989 | return generic_force_reloc (fix); |
252b5132 | 6990 | } |
252b5132 RH |
6991 | #endif /* OBJ_XCOFF */ |
6992 | ||
0baf16f2 | 6993 | #ifdef OBJ_ELF |
a161fe53 AM |
6994 | /* If this function returns non-zero, it guarantees that a relocation |
6995 | will be emitted for a fixup. */ | |
6996 | ||
6997 | int | |
98027b10 | 6998 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
6999 | { |
7000 | /* Branch prediction relocations must force a relocation, as must | |
7001 | the vtable description relocs. */ | |
7002 | switch (fix->fx_r_type) | |
7003 | { | |
7004 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7005 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7006 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
7007 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 7008 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 7009 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 7010 | return 1; |
6911b7dc AM |
7011 | case BFD_RELOC_PPC_B26: |
7012 | case BFD_RELOC_PPC_BA26: | |
7013 | case BFD_RELOC_PPC_B16: | |
7014 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 7015 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
7016 | /* All branch fixups targeting a localentry symbol must |
7017 | force a relocation. */ | |
7018 | if (fix->fx_addsy) | |
7019 | { | |
7020 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
7021 | elf_symbol_type *elfsym | |
7022 | = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
7023 | gas_assert (elfsym); | |
7024 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
7025 | return 1; | |
7026 | } | |
7027 | break; | |
a161fe53 AM |
7028 | default: |
7029 | break; | |
7030 | } | |
7031 | ||
cdba85ec | 7032 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 7033 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL) |
cdba85ec AM |
7034 | return 1; |
7035 | ||
ae6063d4 | 7036 | return generic_force_reloc (fix); |
a161fe53 AM |
7037 | } |
7038 | ||
0baf16f2 | 7039 | int |
98027b10 | 7040 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 7041 | { |
6911b7dc AM |
7042 | switch (fix->fx_r_type) |
7043 | { | |
7044 | /* All branch fixups targeting a localentry symbol must | |
7045 | continue using the symbol. */ | |
7046 | case BFD_RELOC_PPC_B26: | |
7047 | case BFD_RELOC_PPC_BA26: | |
7048 | case BFD_RELOC_PPC_B16: | |
7049 | case BFD_RELOC_PPC_BA16: | |
7050 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7051 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7052 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
7053 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 7054 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
7055 | if (fix->fx_addsy) |
7056 | { | |
7057 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
7058 | elf_symbol_type *elfsym | |
7059 | = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
7060 | gas_assert (elfsym); | |
7061 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
7062 | return 0; | |
7063 | } | |
7064 | break; | |
7065 | default: | |
7066 | break; | |
7067 | } | |
7068 | ||
0baf16f2 AM |
7069 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
7070 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
7071 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
7072 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
7073 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
7074 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
334d91b9 AM |
7075 | && fix->fx_r_type != BFD_RELOC_16_GOT_PCREL |
7076 | && fix->fx_r_type != BFD_RELOC_32_GOTOFF | |
5663e321 | 7077 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34 |
334d91b9 AM |
7078 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL |
7079 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
7080 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
7081 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
7082 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
7083 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
7084 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
7085 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
7086 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
5663e321 | 7087 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34 |
334d91b9 AM |
7088 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 |
7089 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
7090 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
7091 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
7092 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
7093 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 7094 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
7095 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
7096 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
7097 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
7098 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
7099 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 7100 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 7101 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)); |
252b5132 | 7102 | } |
0baf16f2 | 7103 | #endif |
252b5132 | 7104 | |
b9c361e0 JL |
7105 | void |
7106 | ppc_frag_check (struct frag *fragP) | |
7107 | { | |
a9479dc0 AM |
7108 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
7109 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7110 | _("instruction address is not a multiple of %d"), | |
7111 | fragP->insn_addr + 1); | |
b9c361e0 JL |
7112 | } |
7113 | ||
22f72c48 AM |
7114 | /* rs_align_code frag handling. */ |
7115 | ||
7116 | enum ppc_nop_encoding_for_rs_align_code | |
7117 | { | |
7118 | PPC_NOP_VANILLA, | |
7119 | PPC_NOP_VLE, | |
7120 | PPC_NOP_GROUP_P6, | |
7121 | PPC_NOP_GROUP_P7 | |
7122 | }; | |
7123 | ||
7124 | unsigned int | |
7125 | ppc_nop_select (void) | |
7126 | { | |
7127 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) | |
7128 | return PPC_NOP_VLE; | |
7129 | if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0) | |
7130 | { | |
7131 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) | |
7132 | return PPC_NOP_GROUP_P7; | |
7133 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0) | |
7134 | return PPC_NOP_GROUP_P6; | |
7135 | } | |
7136 | return PPC_NOP_VANILLA; | |
7137 | } | |
3aeeedbb AM |
7138 | |
7139 | void | |
7140 | ppc_handle_align (struct frag *fragP) | |
7141 | { | |
7142 | valueT count = (fragP->fr_next->fr_address | |
7143 | - (fragP->fr_address + fragP->fr_fix)); | |
22f72c48 AM |
7144 | char *dest = fragP->fr_literal + fragP->fr_fix; |
7145 | enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff; | |
7146 | ||
7147 | /* Pad with zeros if not inserting a whole number of instructions. | |
7148 | We could pad with zeros up to an instruction boundary then follow | |
7149 | with nops but odd counts indicate data in an executable section | |
7150 | so padding with zeros is most appropriate. */ | |
7151 | if (count == 0 | |
de626965 | 7152 | || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0)) |
22f72c48 AM |
7153 | { |
7154 | *dest = 0; | |
7155 | return; | |
7156 | } | |
3aeeedbb | 7157 | |
22f72c48 | 7158 | if (nop_select == PPC_NOP_VLE) |
b9c361e0 | 7159 | { |
b9c361e0 JL |
7160 | |
7161 | fragP->fr_var = 2; | |
7162 | md_number_to_chars (dest, 0x4400, 2); | |
7163 | } | |
22f72c48 | 7164 | else |
3aeeedbb | 7165 | { |
3aeeedbb | 7166 | fragP->fr_var = 4; |
cef4f754 AM |
7167 | |
7168 | if (count > 4 * nop_limit && count < 0x2000000) | |
7169 | { | |
7170 | struct frag *rest; | |
7171 | ||
7172 | /* Make a branch, then follow with nops. Insert another | |
7173 | frag to handle the nops. */ | |
7174 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
7175 | count -= 4; | |
7176 | if (count == 0) | |
7177 | return; | |
7178 | ||
7179 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
7180 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
7181 | fragP->fr_next = rest; | |
7182 | fragP = rest; | |
7183 | rest->fr_address += rest->fr_fix + 4; | |
7184 | rest->fr_fix = 0; | |
7185 | /* If we leave the next frag as rs_align_code we'll come here | |
7186 | again, resulting in a bunch of branches rather than a | |
7187 | branch followed by nops. */ | |
7188 | rest->fr_type = rs_align; | |
7189 | dest = rest->fr_literal; | |
7190 | } | |
7191 | ||
3aeeedbb AM |
7192 | md_number_to_chars (dest, 0x60000000, 4); |
7193 | ||
22f72c48 | 7194 | if (nop_select >= PPC_NOP_GROUP_P6) |
3aeeedbb | 7195 | { |
3fea0c3b AM |
7196 | /* For power6, power7, and power8, we want the last nop to |
7197 | be a group terminating one. Do this by inserting an | |
7198 | rs_fill frag immediately after this one, with its address | |
7199 | set to the last nop location. This will automatically | |
7200 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
7201 | if (count > 4) |
7202 | { | |
7203 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
7204 | ||
7205 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
7206 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
7207 | group_nop->fr_fix = 0; | |
7208 | group_nop->fr_offset = 1; | |
7209 | group_nop->fr_type = rs_fill; | |
7210 | fragP->fr_next = group_nop; | |
7211 | dest = group_nop->fr_literal; | |
7212 | } | |
7213 | ||
22f72c48 | 7214 | if (nop_select == PPC_NOP_GROUP_P6) |
42240548 PB |
7215 | /* power6 group terminating nop: "ori 1,1,0". */ |
7216 | md_number_to_chars (dest, 0x60210000, 4); | |
22f72c48 AM |
7217 | else |
7218 | /* power7/power8 group terminating nop: "ori 2,2,0". */ | |
7219 | md_number_to_chars (dest, 0x60420000, 4); | |
3aeeedbb AM |
7220 | } |
7221 | } | |
7222 | } | |
7223 | ||
252b5132 | 7224 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 7225 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 7226 | |
94f592af | 7227 | void |
62ebcb5c | 7228 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 7229 | { |
94f592af | 7230 | valueT value = * valP; |
5656a981 AM |
7231 | offsetT fieldval; |
7232 | const struct powerpc_operand *operand; | |
252b5132 RH |
7233 | |
7234 | #ifdef OBJ_ELF | |
94f592af | 7235 | if (fixP->fx_addsy != NULL) |
252b5132 | 7236 | { |
a161fe53 | 7237 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
7238 | if (fixP->fx_pcrel) |
7239 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
7240 | |
7241 | if (fixP->fx_addsy == abs_section_sym) | |
7242 | fixP->fx_done = 1; | |
252b5132 RH |
7243 | } |
7244 | else | |
94f592af | 7245 | fixP->fx_done = 1; |
252b5132 | 7246 | #else |
a161fe53 | 7247 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
7248 | the symbol values. If we are doing this relocation the code in |
7249 | write.c is going to call bfd_install_relocation, which is also | |
7250 | going to use the symbol value. That means that if the reloc is | |
7251 | fully resolved we want to use *valP since bfd_install_relocation is | |
7252 | not being used. | |
9f0eb232 RS |
7253 | However, if the reloc is not fully resolved we do not want to |
7254 | use *valP, and must use fx_offset instead. If the relocation | |
7255 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
7256 | to this new relocation value. */ | |
94f592af NC |
7257 | if (fixP->fx_addsy == (symbolS *) NULL) |
7258 | fixP->fx_done = 1; | |
7259 | ||
252b5132 | 7260 | else |
9f0eb232 RS |
7261 | { |
7262 | value = fixP->fx_offset; | |
7263 | if (fixP->fx_pcrel) | |
7264 | value -= md_pcrel_from_section (fixP, seg); | |
7265 | } | |
a161fe53 AM |
7266 | #endif |
7267 | ||
7ba71655 AM |
7268 | /* We are only able to convert some relocs to pc-relative. */ |
7269 | if (fixP->fx_pcrel) | |
7270 | { | |
7271 | switch (fixP->fx_r_type) | |
7272 | { | |
4a969973 AM |
7273 | case BFD_RELOC_64: |
7274 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7275 | break; | |
7276 | ||
7277 | case BFD_RELOC_32: | |
7278 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
7279 | break; | |
7280 | ||
7281 | case BFD_RELOC_16: | |
7282 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7283 | break; | |
7284 | ||
7ba71655 AM |
7285 | case BFD_RELOC_LO16: |
7286 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
7287 | break; | |
7288 | ||
7289 | case BFD_RELOC_HI16: | |
7290 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
7291 | break; | |
7292 | ||
7293 | case BFD_RELOC_HI16_S: | |
7294 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
7295 | break; | |
7296 | ||
4a969973 AM |
7297 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7298 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
7299 | break; |
7300 | ||
4a969973 AM |
7301 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
7302 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
7303 | break; |
7304 | ||
4a969973 AM |
7305 | case BFD_RELOC_PPC64_HIGHER: |
7306 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
7307 | break; | |
7308 | ||
7309 | case BFD_RELOC_PPC64_HIGHER_S: | |
7310 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
7311 | break; | |
7312 | ||
7313 | case BFD_RELOC_PPC64_HIGHEST: | |
7314 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
7315 | break; | |
7316 | ||
7317 | case BFD_RELOC_PPC64_HIGHEST_S: | |
7318 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
7319 | break; |
7320 | ||
5663e321 AM |
7321 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
7322 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34; | |
7323 | break; | |
7324 | ||
7325 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
7326 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34; | |
7327 | break; | |
7328 | ||
7329 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
7330 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34; | |
7331 | break; | |
7332 | ||
7333 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
7334 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34; | |
7335 | break; | |
7336 | ||
7ba71655 AM |
7337 | case BFD_RELOC_PPC_16DX_HA: |
7338 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7339 | break; | |
7340 | ||
5663e321 AM |
7341 | case BFD_RELOC_PPC64_D34: |
7342 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34; | |
7343 | break; | |
7344 | ||
7345 | case BFD_RELOC_PPC64_D28: | |
7346 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28; | |
7347 | break; | |
7348 | ||
7ba71655 AM |
7349 | default: |
7350 | break; | |
7351 | } | |
7352 | } | |
7353 | else if (!fixP->fx_done | |
7354 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 7355 | { |
7ba71655 AM |
7356 | /* addpcis is relative to next insn address. */ |
7357 | value -= 4; | |
7358 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7359 | fixP->fx_pcrel = 1; | |
252b5132 | 7360 | } |
252b5132 | 7361 | |
5656a981 | 7362 | operand = NULL; |
3b8b57a9 | 7363 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 7364 | { |
5656a981 | 7365 | /* This is a fixup on an instruction. */ |
3b8b57a9 | 7366 | int opindex = fixP->fx_pcrel_adjust & 0xff; |
252b5132 | 7367 | |
5656a981 | 7368 | operand = &powerpc_operands[opindex]; |
252b5132 | 7369 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
7370 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
7371 | does not generate a reloc. It uses the offset of `sym' within its | |
7372 | csect. Other usages, such as `.long sym', generate relocs. This | |
7373 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 7374 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 7375 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 7376 | && operand->shift == 0 |
2b3c4602 | 7377 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
7378 | && fixP->fx_addsy != NULL |
7379 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
96d56e9f NC |
7380 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC |
7381 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC0 | |
94f592af | 7382 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 7383 | { |
94f592af NC |
7384 | value = fixP->fx_offset; |
7385 | fixP->fx_done = 1; | |
252b5132 | 7386 | } |
ac21e7da TG |
7387 | |
7388 | /* During parsing of instructions, a TOC16 reloc is generated for | |
7389 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
7390 | in the toc. But at parse time, SYM may be not yet defined, so | |
7391 | check again here. */ | |
7392 | if (fixP->fx_r_type == BFD_RELOC_16 | |
7393 | && fixP->fx_addsy != NULL | |
7394 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
7395 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; | |
252b5132 | 7396 | #endif |
5656a981 AM |
7397 | } |
7398 | ||
7399 | /* Calculate value to be stored in field. */ | |
7400 | fieldval = value; | |
7401 | switch (fixP->fx_r_type) | |
7402 | { | |
1ec2d25e | 7403 | #ifdef OBJ_ELF |
5656a981 AM |
7404 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
7405 | case BFD_RELOC_PPC_VLE_LO16A: | |
7406 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 7407 | #endif |
5656a981 AM |
7408 | case BFD_RELOC_LO16: |
7409 | case BFD_RELOC_LO16_PCREL: | |
7410 | fieldval = value & 0xffff; | |
7411 | sign_extend_16: | |
7412 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 7413 | fieldval = SEX16 (fieldval); |
5656a981 AM |
7414 | fixP->fx_no_overflow = 1; |
7415 | break; | |
3c9d25f4 | 7416 | |
f9c6b907 AM |
7417 | case BFD_RELOC_HI16: |
7418 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 7419 | #ifdef OBJ_ELF |
f9c6b907 AM |
7420 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7421 | { | |
7422 | fieldval = value >> 16; | |
7423 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7424 | { | |
7425 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7426 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7427 | } | |
7428 | break; | |
7429 | } | |
2b0f3761 | 7430 | /* Fallthru */ |
f9c6b907 | 7431 | |
5656a981 AM |
7432 | case BFD_RELOC_PPC_VLE_HI16A: |
7433 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 7434 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 7435 | #endif |
5656a981 AM |
7436 | fieldval = PPC_HI (value); |
7437 | goto sign_extend_16; | |
0baf16f2 | 7438 | |
f9c6b907 AM |
7439 | case BFD_RELOC_HI16_S: |
7440 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 7441 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 7442 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 7443 | #ifdef OBJ_ELF |
f9c6b907 AM |
7444 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7445 | { | |
7446 | fieldval = (value + 0x8000) >> 16; | |
7447 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7448 | { | |
7449 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7450 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7451 | } | |
7452 | break; | |
7453 | } | |
2b0f3761 | 7454 | /* Fallthru */ |
f9c6b907 | 7455 | |
5656a981 AM |
7456 | case BFD_RELOC_PPC_VLE_HA16A: |
7457 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 7458 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 7459 | #endif |
5656a981 AM |
7460 | fieldval = PPC_HA (value); |
7461 | goto sign_extend_16; | |
0baf16f2 | 7462 | |
3b8b57a9 | 7463 | #ifdef OBJ_ELF |
5656a981 AM |
7464 | case BFD_RELOC_PPC64_HIGHER: |
7465 | fieldval = PPC_HIGHER (value); | |
7466 | goto sign_extend_16; | |
252b5132 | 7467 | |
5656a981 AM |
7468 | case BFD_RELOC_PPC64_HIGHER_S: |
7469 | fieldval = PPC_HIGHERA (value); | |
7470 | goto sign_extend_16; | |
0baf16f2 | 7471 | |
5656a981 AM |
7472 | case BFD_RELOC_PPC64_HIGHEST: |
7473 | fieldval = PPC_HIGHEST (value); | |
7474 | goto sign_extend_16; | |
0baf16f2 | 7475 | |
5656a981 AM |
7476 | case BFD_RELOC_PPC64_HIGHEST_S: |
7477 | fieldval = PPC_HIGHESTA (value); | |
7478 | goto sign_extend_16; | |
7479 | #endif | |
7480 | ||
7481 | default: | |
7482 | break; | |
7483 | } | |
7484 | ||
7485 | if (operand != NULL) | |
7486 | { | |
7487 | /* Handle relocs in an insn. */ | |
5656a981 AM |
7488 | switch (fixP->fx_r_type) |
7489 | { | |
7fa9fcb6 | 7490 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7491 | /* The following relocs can't be calculated by the assembler. |
7492 | Leave the field zero. */ | |
cdba85ec AM |
7493 | case BFD_RELOC_PPC_TPREL16: |
7494 | case BFD_RELOC_PPC_TPREL16_LO: | |
7495 | case BFD_RELOC_PPC_TPREL16_HI: | |
7496 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
7497 | case BFD_RELOC_PPC_DTPREL16: |
7498 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7499 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7500 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
7501 | case BFD_RELOC_PPC_GOT_TLSGD16: |
7502 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7503 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7504 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7505 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7506 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7507 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7508 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7509 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7510 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7511 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7512 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7513 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7514 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7515 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7516 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7517 | case BFD_RELOC_PPC64_TPREL16_DS: | |
7518 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
7519 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7520 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
7521 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7522 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7523 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7524 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
7525 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7526 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
7527 | case BFD_RELOC_PPC64_DTPREL16_DS: |
7528 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
7529 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
7530 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7531 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7532 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
c213164a AM |
7533 | case BFD_RELOC_PPC64_TPREL34: |
7534 | case BFD_RELOC_PPC64_DTPREL34: | |
7535 | case BFD_RELOC_PPC64_GOT_TLSGD34: | |
7536 | case BFD_RELOC_PPC64_GOT_TLSLD34: | |
7537 | case BFD_RELOC_PPC64_GOT_TPREL34: | |
7538 | case BFD_RELOC_PPC64_GOT_DTPREL34: | |
3b8b57a9 | 7539 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 7540 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 7541 | fieldval = 0; |
cdba85ec | 7542 | break; |
3b8b57a9 AM |
7543 | |
7544 | /* These also should leave the field zero for the same | |
7545 | reason. Note that older versions of gas wrote values | |
7546 | here. If we want to go back to the old behaviour, then | |
7547 | all _LO and _LO_DS cases will need to be treated like | |
7548 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
7549 | case BFD_RELOC_16_GOTOFF: | |
7550 | case BFD_RELOC_LO16_GOTOFF: | |
7551 | case BFD_RELOC_HI16_GOTOFF: | |
7552 | case BFD_RELOC_HI16_S_GOTOFF: | |
7553 | case BFD_RELOC_LO16_PLTOFF: | |
7554 | case BFD_RELOC_HI16_PLTOFF: | |
7555 | case BFD_RELOC_HI16_S_PLTOFF: | |
7556 | case BFD_RELOC_GPREL16: | |
7557 | case BFD_RELOC_16_BASEREL: | |
7558 | case BFD_RELOC_LO16_BASEREL: | |
7559 | case BFD_RELOC_HI16_BASEREL: | |
7560 | case BFD_RELOC_HI16_S_BASEREL: | |
7561 | case BFD_RELOC_PPC_TOC16: | |
7562 | case BFD_RELOC_PPC64_TOC16_LO: | |
7563 | case BFD_RELOC_PPC64_TOC16_HI: | |
7564 | case BFD_RELOC_PPC64_TOC16_HA: | |
7565 | case BFD_RELOC_PPC64_PLTGOT16: | |
7566 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
7567 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
7568 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
7569 | case BFD_RELOC_PPC64_GOT16_DS: | |
7570 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
7571 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
7572 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
7573 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
7574 | case BFD_RELOC_PPC64_TOC16_DS: | |
7575 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
7576 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
7577 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
7578 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7579 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7580 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7581 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7582 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7583 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7584 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 7585 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
7586 | case BFD_RELOC_PPC_EMB_MRKREF: |
7587 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7588 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7589 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7590 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7591 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7592 | case BFD_RELOC_PPC_EMB_RELSDA: | |
7593 | case BFD_RELOC_PPC_VLE_SDA21: | |
7594 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7595 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7596 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
7597 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7598 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
7599 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7600 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
5663e321 AM |
7601 | case BFD_RELOC_PPC64_GOT_PCREL34: |
7602 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
3b8b57a9 | 7603 | gas_assert (fixP->fx_addsy != NULL); |
2b0f3761 | 7604 | /* Fallthru */ |
3b8b57a9 AM |
7605 | |
7606 | case BFD_RELOC_PPC_TLS: | |
7607 | case BFD_RELOC_PPC_TLSGD: | |
7608 | case BFD_RELOC_PPC_TLSLD: | |
c213164a | 7609 | case BFD_RELOC_PPC64_TLS_PCREL: |
3b8b57a9 | 7610 | fieldval = 0; |
3b8b57a9 | 7611 | break; |
7fa9fcb6 TG |
7612 | #endif |
7613 | ||
7614 | #ifdef OBJ_XCOFF | |
7615 | case BFD_RELOC_PPC_B16: | |
7616 | /* Adjust the offset to the instruction boundary. */ | |
7617 | fieldval += 2; | |
7618 | break; | |
7619 | #endif | |
252b5132 | 7620 | |
f728387b AM |
7621 | case BFD_RELOC_VTABLE_INHERIT: |
7622 | case BFD_RELOC_VTABLE_ENTRY: | |
7623 | case BFD_RELOC_PPC_DTPMOD: | |
7624 | case BFD_RELOC_PPC_TPREL: | |
7625 | case BFD_RELOC_PPC_DTPREL: | |
7626 | case BFD_RELOC_PPC_COPY: | |
7627 | case BFD_RELOC_PPC_GLOB_DAT: | |
7628 | case BFD_RELOC_32_PLT_PCREL: | |
7629 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7630 | case BFD_RELOC_PPC64_TOC: | |
7631 | case BFD_RELOC_CTOR: | |
7632 | case BFD_RELOC_32: | |
7633 | case BFD_RELOC_32_PCREL: | |
7634 | case BFD_RELOC_RVA: | |
7635 | case BFD_RELOC_64: | |
7636 | case BFD_RELOC_64_PCREL: | |
7637 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
7638 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7639 | _("%s unsupported as instruction fixup"), | |
7640 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7641 | fixP->fx_done = 1; | |
7642 | return; | |
7643 | ||
3b8b57a9 | 7644 | default: |
252b5132 | 7645 | break; |
3b8b57a9 | 7646 | } |
252b5132 | 7647 | |
3b8b57a9 AM |
7648 | #ifdef OBJ_ELF |
7649 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
7650 | contents can stay at zero. */ | |
7651 | #define APPLY_RELOC fixP->fx_done | |
7652 | #else | |
7653 | #define APPLY_RELOC 1 | |
7654 | #endif | |
5663e321 AM |
7655 | /* We need to call the insert function even when fieldval is |
7656 | zero if the insert function would translate that zero to a | |
7657 | bit pattern other than all zeros. */ | |
3b8b57a9 AM |
7658 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) |
7659 | { | |
5663e321 | 7660 | uint64_t insn; |
487b24d8 AM |
7661 | unsigned char *where; |
7662 | ||
3b8b57a9 AM |
7663 | /* Fetch the instruction, insert the fully resolved operand |
7664 | value, and stuff the instruction back again. */ | |
487b24d8 | 7665 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 7666 | if (target_big_endian) |
31a91399 | 7667 | { |
5663e321 | 7668 | if (fixP->fx_size < 4) |
487b24d8 | 7669 | insn = bfd_getb16 (where); |
5663e321 AM |
7670 | else |
7671 | { | |
7672 | insn = bfd_getb32 (where); | |
7673 | if (fixP->fx_size > 4) | |
7674 | insn = insn << 32 | bfd_getb32 (where + 4); | |
7675 | } | |
31a91399 NC |
7676 | } |
7677 | else | |
3b8b57a9 | 7678 | { |
5663e321 | 7679 | if (fixP->fx_size < 4) |
487b24d8 | 7680 | insn = bfd_getl16 (where); |
5663e321 AM |
7681 | else |
7682 | { | |
7683 | insn = bfd_getl32 (where); | |
7684 | if (fixP->fx_size > 4) | |
7685 | insn = insn << 32 | bfd_getl32 (where + 4); | |
7686 | } | |
3b8b57a9 AM |
7687 | } |
7688 | insn = ppc_insert_operand (insn, operand, fieldval, | |
7689 | fixP->tc_fix_data.ppc_cpu, | |
7690 | fixP->fx_file, fixP->fx_line); | |
7691 | if (target_big_endian) | |
7692 | { | |
5663e321 | 7693 | if (fixP->fx_size < 4) |
487b24d8 | 7694 | bfd_putb16 (insn, where); |
5663e321 AM |
7695 | else |
7696 | { | |
7697 | if (fixP->fx_size > 4) | |
7698 | { | |
7699 | bfd_putb32 (insn, where + 4); | |
7700 | insn >>= 32; | |
7701 | } | |
7702 | bfd_putb32 (insn, where); | |
7703 | } | |
3b8b57a9 AM |
7704 | } |
7705 | else | |
7706 | { | |
5663e321 | 7707 | if (fixP->fx_size < 4) |
487b24d8 | 7708 | bfd_putl16 (insn, where); |
5663e321 AM |
7709 | else |
7710 | { | |
7711 | if (fixP->fx_size > 4) | |
7712 | { | |
7713 | bfd_putl32 (insn, where + 4); | |
7714 | insn >>= 32; | |
7715 | } | |
7716 | bfd_putl32 (insn, where); | |
7717 | } | |
3b8b57a9 AM |
7718 | } |
7719 | } | |
7720 | ||
7721 | if (fixP->fx_done) | |
7722 | /* Nothing else to do here. */ | |
7723 | return; | |
7724 | ||
7725 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 7726 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 7727 | { |
3b4dbbbf | 7728 | const char *sfile; |
3b8b57a9 AM |
7729 | unsigned int sline; |
7730 | ||
7731 | /* Use expr_symbol_where to see if this is an expression | |
7732 | symbol. */ | |
7733 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
7734 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7735 | _("unresolved expression that must be resolved")); | |
7736 | else | |
7737 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7738 | _("unsupported relocation against %s"), | |
7739 | S_GET_NAME (fixP->fx_addsy)); | |
7740 | fixP->fx_done = 1; | |
7741 | return; | |
7742 | } | |
7743 | } | |
7744 | else | |
7745 | { | |
7746 | /* Handle relocs in data. */ | |
7747 | switch (fixP->fx_r_type) | |
7748 | { | |
252b5132 | 7749 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
7750 | if (fixP->fx_addsy |
7751 | && !S_IS_DEFINED (fixP->fx_addsy) | |
7752 | && !S_IS_WEAK (fixP->fx_addsy)) | |
7753 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 7754 | /* Fallthru */ |
252b5132 RH |
7755 | |
7756 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 7757 | fixP->fx_done = 0; |
252b5132 RH |
7758 | break; |
7759 | ||
0baf16f2 | 7760 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7761 | /* These can appear with @l etc. in data. */ |
7762 | case BFD_RELOC_LO16: | |
3b8b57a9 | 7763 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 7764 | case BFD_RELOC_HI16: |
3b8b57a9 | 7765 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 7766 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 7767 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 7768 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 7769 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 7770 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 7771 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
7772 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7773 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 7774 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
7775 | break; |
7776 | ||
7777 | case BFD_RELOC_PPC_DTPMOD: | |
7778 | case BFD_RELOC_PPC_TPREL: | |
7779 | case BFD_RELOC_PPC_DTPREL: | |
7780 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7781 | break; | |
7782 | ||
7783 | /* Just punt all of these to the linker. */ | |
7784 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7785 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7786 | case BFD_RELOC_16_GOTOFF: | |
7787 | case BFD_RELOC_LO16_GOTOFF: | |
7788 | case BFD_RELOC_HI16_GOTOFF: | |
7789 | case BFD_RELOC_HI16_S_GOTOFF: | |
7790 | case BFD_RELOC_LO16_PLTOFF: | |
7791 | case BFD_RELOC_HI16_PLTOFF: | |
7792 | case BFD_RELOC_HI16_S_PLTOFF: | |
7793 | case BFD_RELOC_PPC_COPY: | |
7794 | case BFD_RELOC_PPC_GLOB_DAT: | |
7795 | case BFD_RELOC_16_BASEREL: | |
7796 | case BFD_RELOC_LO16_BASEREL: | |
7797 | case BFD_RELOC_HI16_BASEREL: | |
7798 | case BFD_RELOC_HI16_S_BASEREL: | |
7799 | case BFD_RELOC_PPC_TLS: | |
7800 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7801 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7802 | case BFD_RELOC_PPC_DTPREL16_HA: | |
7803 | case BFD_RELOC_PPC_TPREL16_LO: | |
7804 | case BFD_RELOC_PPC_TPREL16_HI: | |
7805 | case BFD_RELOC_PPC_TPREL16_HA: | |
7806 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
7807 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7808 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7809 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7810 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7811 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7812 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7813 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7814 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7815 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7816 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7817 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7818 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7819 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7820 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7821 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7822 | case BFD_RELOC_24_PLT_PCREL: | |
7823 | case BFD_RELOC_PPC_LOCAL24PC: | |
7824 | case BFD_RELOC_32_PLT_PCREL: | |
7825 | case BFD_RELOC_GPREL16: | |
7826 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7827 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7828 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7829 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7830 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7831 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7832 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7833 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7834 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7835 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
7836 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7837 | case BFD_RELOC_PPC_EMB_SDA21: | |
7838 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7839 | case BFD_RELOC_PPC_EMB_MRKREF: | |
7840 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7841 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7842 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7843 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7844 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7845 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 7846 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 AM |
7847 | case BFD_RELOC_PPC_TOC16: |
7848 | case BFD_RELOC_PPC64_TOC16_LO: | |
7849 | case BFD_RELOC_PPC64_TOC16_HI: | |
7850 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
7851 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7852 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
7853 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
7854 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7855 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7856 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
7857 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7858 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
7859 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7860 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7861 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7862 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
c213164a | 7863 | case BFD_RELOC_PPC64_TLS_PCREL: |
94f592af | 7864 | fixP->fx_done = 0; |
0baf16f2 | 7865 | break; |
0baf16f2 | 7866 | #endif |
3b8b57a9 AM |
7867 | |
7868 | #ifdef OBJ_XCOFF | |
7869 | case BFD_RELOC_NONE: | |
3b8b57a9 | 7870 | #endif |
5656a981 AM |
7871 | case BFD_RELOC_CTOR: |
7872 | case BFD_RELOC_32: | |
7873 | case BFD_RELOC_32_PCREL: | |
7874 | case BFD_RELOC_RVA: | |
7875 | case BFD_RELOC_64: | |
7876 | case BFD_RELOC_64_PCREL: | |
7877 | case BFD_RELOC_16: | |
7878 | case BFD_RELOC_16_PCREL: | |
7879 | case BFD_RELOC_8: | |
7880 | break; | |
3b8b57a9 | 7881 | |
252b5132 | 7882 | default: |
bc805888 | 7883 | fprintf (stderr, |
94f592af | 7884 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7885 | fflush (stderr); |
252b5132 RH |
7886 | abort (); |
7887 | } | |
46b596ff | 7888 | |
5656a981 | 7889 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7890 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7891 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7892 | if (warn_476 |
7893 | && (seg->flags & SEC_CODE) != 0 | |
7894 | && fixP->fx_size == 4 | |
7895 | && fixP->fx_done | |
7896 | && !fixP->fx_tcbit | |
7897 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7898 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7899 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7900 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7901 | _("data in executable section")); | |
5656a981 AM |
7902 | } |
7903 | ||
252b5132 | 7904 | #ifdef OBJ_ELF |
3b8b57a9 | 7905 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7906 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7907 | |
7908 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7909 | from the section contents. If we are going to be emitting a reloc | |
7910 | then the section contents are immaterial, so don't warn if they | |
7911 | happen to overflow. Leave such warnings to ld. */ | |
7912 | if (!fixP->fx_done) | |
a38a07e0 AM |
7913 | { |
7914 | fixP->fx_no_overflow = 1; | |
7915 | ||
7916 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7917 | but .TOC.@tocbase. */ | |
7918 | if (ppc_obj64 | |
7919 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7920 | && fixP->fx_addsy != NULL | |
7921 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7922 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7923 | } | |
252b5132 | 7924 | #else |
94f592af NC |
7925 | if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16) |
7926 | fixP->fx_addnumber = 0; | |
252b5132 RH |
7927 | else |
7928 | { | |
7929 | #ifdef TE_PE | |
94f592af | 7930 | fixP->fx_addnumber = 0; |
252b5132 | 7931 | #else |
8edcbfcd TG |
7932 | /* We want to use the offset within the toc, not the actual VMA |
7933 | of the symbol. */ | |
fd361982 AM |
7934 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) |
7935 | - S_GET_VALUE (ppc_toc_csect)); | |
ac21e7da TG |
7936 | /* Set *valP to avoid errors. */ |
7937 | *valP = value; | |
252b5132 RH |
7938 | #endif |
7939 | } | |
7940 | #endif | |
252b5132 RH |
7941 | } |
7942 | ||
7943 | /* Generate a reloc for a fixup. */ | |
7944 | ||
7945 | arelent * | |
98027b10 | 7946 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
7947 | { |
7948 | arelent *reloc; | |
7949 | ||
325801bd | 7950 | reloc = XNEW (arelent); |
252b5132 | 7951 | |
325801bd | 7952 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7953 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 | 7954 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
c213164a AM |
7955 | /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */ |
7956 | if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL) | |
7957 | reloc->address++; | |
252b5132 RH |
7958 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
7959 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7960 | { | |
7961 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7962 | _("reloc %d not supported by object file format"), |
7963 | (int) fixp->fx_r_type); | |
252b5132 RH |
7964 | return NULL; |
7965 | } | |
7966 | reloc->addend = fixp->fx_addnumber; | |
7967 | ||
7968 | return reloc; | |
7969 | } | |
75e21f08 JJ |
7970 | |
7971 | void | |
98027b10 | 7972 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7973 | { |
7974 | cfi_add_CFA_def_cfa (1, 0); | |
7975 | } | |
7976 | ||
7977 | int | |
1df69f4f | 7978 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7979 | { |
7980 | unsigned int regnum = -1; | |
7981 | unsigned int i; | |
7982 | const char *p; | |
7983 | char *q; | |
e0471c16 | 7984 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7985 | { |
7986 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7987 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7988 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7989 | { "spe_acc", 111 }, { "spefscr", 112 } |
7990 | }; | |
7991 | ||
7992 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7993 | if (strcmp (regnames[i].name, regname) == 0) | |
7994 | return regnames[i].dw2regnum; | |
7995 | ||
7996 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7997 | { | |
7998 | p = regname + 1 + (regname[1] == '.'); | |
7999 | regnum = strtoul (p, &q, 10); | |
8000 | if (p == q || *q || regnum >= 32) | |
8001 | return -1; | |
8002 | if (regname[0] == 'f') | |
b7d7dc63 | 8003 | regnum += 32; |
75e21f08 | 8004 | else if (regname[0] == 'v') |
b7d7dc63 | 8005 | regnum += 77; |
75e21f08 JJ |
8006 | } |
8007 | else if (regname[0] == 'c' && regname[1] == 'r') | |
8008 | { | |
8009 | p = regname + 2 + (regname[2] == '.'); | |
8010 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 8011 | return -1; |
75e21f08 JJ |
8012 | regnum = p[0] - '0' + 68; |
8013 | } | |
8014 | return regnum; | |
8015 | } |