Commit | Line | Data |
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252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
82704155 | 2 | Copyright (C) 1994-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
34 | #ifdef TE_PE | |
35 | #include "coff/pe.h" | |
36 | #endif | |
37 | ||
85645aed TG |
38 | #ifdef OBJ_XCOFF |
39 | #include "coff/xcoff.h" | |
40 | #include "libxcoff.h" | |
41 | #endif | |
42 | ||
252b5132 RH |
43 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
44 | ||
45 | /* Tell the main code what the endianness is. */ | |
46 | extern int target_big_endian; | |
47 | ||
48 | /* Whether or not, we've set target_big_endian. */ | |
49 | static int set_target_endian = 0; | |
50 | ||
51 | /* Whether to use user friendly register names. */ | |
52 | #ifndef TARGET_REG_NAMES_P | |
53 | #ifdef TE_PE | |
b34976b6 | 54 | #define TARGET_REG_NAMES_P TRUE |
252b5132 | 55 | #else |
b34976b6 | 56 | #define TARGET_REG_NAMES_P FALSE |
252b5132 RH |
57 | #endif |
58 | #endif | |
59 | ||
0baf16f2 AM |
60 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
61 | HIGHESTA. */ | |
62 | ||
63 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
64 | #define PPC_LO(v) ((v) & 0xffff) | |
65 | ||
66 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
67 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
68 | ||
69 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
70 | the indicated value, compensating for #lo() being treated as a | |
71 | signed number. */ | |
15c1449b | 72 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
73 | |
74 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 75 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
76 | |
77 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
78 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 79 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
80 | |
81 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 82 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
83 | |
84 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
85 | compensating for #lo being treated as a signed number. */ |
86 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 87 | |
f9c6b907 AM |
88 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
89 | ||
90 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
91 | applied to constants. */ | |
92 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 93 | |
b34976b6 | 94 | static bfd_boolean reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 95 | |
98027b10 AM |
96 | static void ppc_macro (char *, const struct powerpc_macro *); |
97 | static void ppc_byte (int); | |
0baf16f2 AM |
98 | |
99 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
100 | static void ppc_tc (int); |
101 | static void ppc_machine (int); | |
0baf16f2 | 102 | #endif |
252b5132 RH |
103 | |
104 | #ifdef OBJ_XCOFF | |
98027b10 AM |
105 | static void ppc_comm (int); |
106 | static void ppc_bb (int); | |
107 | static void ppc_bc (int); | |
108 | static void ppc_bf (int); | |
109 | static void ppc_biei (int); | |
110 | static void ppc_bs (int); | |
111 | static void ppc_eb (int); | |
112 | static void ppc_ec (int); | |
113 | static void ppc_ef (int); | |
114 | static void ppc_es (int); | |
115 | static void ppc_csect (int); | |
85645aed | 116 | static void ppc_dwsect (int); |
98027b10 AM |
117 | static void ppc_change_csect (symbolS *, offsetT); |
118 | static void ppc_function (int); | |
119 | static void ppc_extern (int); | |
120 | static void ppc_lglobl (int); | |
c865e45b | 121 | static void ppc_ref (int); |
98027b10 AM |
122 | static void ppc_section (int); |
123 | static void ppc_named_section (int); | |
124 | static void ppc_stabx (int); | |
125 | static void ppc_rename (int); | |
126 | static void ppc_toc (int); | |
127 | static void ppc_xcoff_cons (int); | |
128 | static void ppc_vbyte (int); | |
252b5132 RH |
129 | #endif |
130 | ||
131 | #ifdef OBJ_ELF | |
98027b10 AM |
132 | static void ppc_elf_rdata (int); |
133 | static void ppc_elf_lcomm (int); | |
6911b7dc | 134 | static void ppc_elf_localentry (int); |
ee67d69a | 135 | static void ppc_elf_abiversion (int); |
005d79fd | 136 | static void ppc_elf_gnu_attribute (int); |
252b5132 RH |
137 | #endif |
138 | ||
139 | #ifdef TE_PE | |
98027b10 AM |
140 | static void ppc_previous (int); |
141 | static void ppc_pdata (int); | |
142 | static void ppc_ydata (int); | |
143 | static void ppc_reldata (int); | |
144 | static void ppc_rdata (int); | |
145 | static void ppc_ualong (int); | |
146 | static void ppc_znop (int); | |
147 | static void ppc_pe_comm (int); | |
148 | static void ppc_pe_section (int); | |
149 | static void ppc_pe_function (int); | |
150 | static void ppc_pe_tocd (int); | |
252b5132 RH |
151 | #endif |
152 | \f | |
153 | /* Generic assembler global variables which must be defined by all | |
154 | targets. */ | |
155 | ||
156 | #ifdef OBJ_ELF | |
157 | /* This string holds the chars that always start a comment. If the | |
158 | pre-processor is disabled, these aren't very useful. The macro | |
159 | tc_comment_chars points to this. We use this, rather than the | |
160 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
161 | static const char ppc_solaris_comment_chars[] = "#!"; | |
162 | static const char ppc_eabi_comment_chars[] = "#"; | |
163 | ||
164 | #ifdef TARGET_SOLARIS_COMMENT | |
165 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
166 | #else | |
167 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
168 | #endif | |
169 | #else | |
170 | const char comment_chars[] = "#"; | |
171 | #endif | |
172 | ||
173 | /* Characters which start a comment at the beginning of a line. */ | |
174 | const char line_comment_chars[] = "#"; | |
175 | ||
176 | /* Characters which may be used to separate multiple commands on a | |
177 | single line. */ | |
178 | const char line_separator_chars[] = ";"; | |
179 | ||
180 | /* Characters which are used to indicate an exponent in a floating | |
181 | point number. */ | |
182 | const char EXP_CHARS[] = "eE"; | |
183 | ||
184 | /* Characters which mean that a number is a floating point constant, | |
185 | as in 0d1.0. */ | |
186 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 187 | |
5e02f92e | 188 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 189 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 190 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
191 | |
192 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
193 | int ppc_cie_data_alignment; | |
783de163 | 194 | |
8fbf7334 JL |
195 | /* The dwarf2 minimum instruction length. */ |
196 | int ppc_dwarf2_line_min_insn_length; | |
197 | ||
cef4f754 AM |
198 | /* More than this number of nops in an alignment op gets a branch |
199 | instead. */ | |
200 | unsigned long nop_limit = 4; | |
201 | ||
783de163 AM |
202 | /* The type of processor we are assembling for. This is one or more |
203 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 204 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 205 | ppc_cpu_t sticky = 0; |
01efc3af | 206 | |
ee67d69a AM |
207 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
208 | unsigned int ppc_abiversion = 0; | |
209 | ||
05f7541e | 210 | #ifdef OBJ_ELF |
01efc3af | 211 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 212 | static enum { |
01efc3af AM |
213 | has_large_toc_reloc = 1, |
214 | has_small_toc_reloc = 2 | |
215 | } toc_reloc_types; | |
05f7541e | 216 | #endif |
bf7279d5 AM |
217 | |
218 | /* Warn on emitting data to code sections. */ | |
219 | int warn_476; | |
0f873fd5 | 220 | uint64_t last_insn; |
bf7279d5 AM |
221 | segT last_seg; |
222 | subsegT last_subseg; | |
252b5132 RH |
223 | \f |
224 | /* The target specific pseudo-ops which we support. */ | |
225 | ||
226 | const pseudo_typeS md_pseudo_table[] = | |
227 | { | |
228 | /* Pseudo-ops which must be overridden. */ | |
229 | { "byte", ppc_byte, 0 }, | |
230 | ||
231 | #ifdef OBJ_XCOFF | |
232 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
233 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
234 | on COFF, and is only implemented for the RS/6000. We just use | |
235 | obj-coff.c, and add what we need here. */ | |
236 | { "comm", ppc_comm, 0 }, | |
237 | { "lcomm", ppc_comm, 1 }, | |
238 | { "bb", ppc_bb, 0 }, | |
239 | { "bc", ppc_bc, 0 }, | |
240 | { "bf", ppc_bf, 0 }, | |
241 | { "bi", ppc_biei, 0 }, | |
242 | { "bs", ppc_bs, 0 }, | |
243 | { "csect", ppc_csect, 0 }, | |
85645aed | 244 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
245 | { "data", ppc_section, 'd' }, |
246 | { "eb", ppc_eb, 0 }, | |
247 | { "ec", ppc_ec, 0 }, | |
248 | { "ef", ppc_ef, 0 }, | |
249 | { "ei", ppc_biei, 1 }, | |
250 | { "es", ppc_es, 0 }, | |
251 | { "extern", ppc_extern, 0 }, | |
252 | { "function", ppc_function, 0 }, | |
253 | { "lglobl", ppc_lglobl, 0 }, | |
c865e45b | 254 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
255 | { "rename", ppc_rename, 0 }, |
256 | { "section", ppc_named_section, 0 }, | |
257 | { "stabx", ppc_stabx, 0 }, | |
258 | { "text", ppc_section, 't' }, | |
259 | { "toc", ppc_toc, 0 }, | |
260 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 261 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
262 | { "word", ppc_xcoff_cons, 1 }, |
263 | { "short", ppc_xcoff_cons, 1 }, | |
264 | { "vbyte", ppc_vbyte, 0 }, | |
265 | #endif | |
266 | ||
267 | #ifdef OBJ_ELF | |
62ebcb5c | 268 | { "llong", cons, 8 }, |
252b5132 RH |
269 | { "rdata", ppc_elf_rdata, 0 }, |
270 | { "rodata", ppc_elf_rdata, 0 }, | |
271 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 272 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 273 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 274 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
275 | #endif |
276 | ||
277 | #ifdef TE_PE | |
99a814a1 | 278 | /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */ |
252b5132 RH |
279 | { "previous", ppc_previous, 0 }, |
280 | { "pdata", ppc_pdata, 0 }, | |
281 | { "ydata", ppc_ydata, 0 }, | |
282 | { "reldata", ppc_reldata, 0 }, | |
283 | { "rdata", ppc_rdata, 0 }, | |
284 | { "ualong", ppc_ualong, 0 }, | |
285 | { "znop", ppc_znop, 0 }, | |
286 | { "comm", ppc_pe_comm, 0 }, | |
287 | { "lcomm", ppc_pe_comm, 1 }, | |
288 | { "section", ppc_pe_section, 0 }, | |
289 | { "function", ppc_pe_function,0 }, | |
290 | { "tocd", ppc_pe_tocd, 0 }, | |
291 | #endif | |
292 | ||
0baf16f2 | 293 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 294 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
295 | { "machine", ppc_machine, 0 }, |
296 | #endif | |
252b5132 RH |
297 | |
298 | { NULL, NULL, 0 } | |
299 | }; | |
300 | ||
301 | \f | |
99a814a1 AM |
302 | /* Predefined register names if -mregnames (or default for Windows NT). |
303 | In general, there are lots of them, in an attempt to be compatible | |
304 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
305 | |
306 | /* Structure to hold information about predefined registers. */ | |
307 | struct pd_reg | |
308 | { | |
e0471c16 | 309 | const char *name; |
7e0de605 AM |
310 | unsigned short value; |
311 | unsigned short flags; | |
252b5132 RH |
312 | }; |
313 | ||
314 | /* List of registers that are pre-defined: | |
315 | ||
316 | Each general register has predefined names of the form: | |
317 | 1. r<reg_num> which has the value <reg_num>. | |
318 | 2. r.<reg_num> which has the value <reg_num>. | |
319 | ||
252b5132 RH |
320 | Each floating point register has predefined names of the form: |
321 | 1. f<reg_num> which has the value <reg_num>. | |
322 | 2. f.<reg_num> which has the value <reg_num>. | |
323 | ||
7a899fff C |
324 | Each vector unit register has predefined names of the form: |
325 | 1. v<reg_num> which has the value <reg_num>. | |
326 | 2. v.<reg_num> which has the value <reg_num>. | |
327 | ||
252b5132 RH |
328 | Each condition register has predefined names of the form: |
329 | 1. cr<reg_num> which has the value <reg_num>. | |
330 | 2. cr.<reg_num> which has the value <reg_num>. | |
331 | ||
332 | There are individual registers as well: | |
333 | sp or r.sp has the value 1 | |
334 | rtoc or r.toc has the value 2 | |
252b5132 RH |
335 | xer has the value 1 |
336 | lr has the value 8 | |
337 | ctr has the value 9 | |
252b5132 RH |
338 | dar has the value 19 |
339 | dsisr has the value 18 | |
340 | dec has the value 22 | |
341 | sdr1 has the value 25 | |
342 | srr0 has the value 26 | |
343 | srr1 has the value 27 | |
344 | ||
81d4177b | 345 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
346 | |
347 | static const struct pd_reg pre_defined_registers[] = | |
348 | { | |
7e0de605 AM |
349 | /* Condition Registers */ |
350 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
351 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
352 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
353 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
354 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
355 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
356 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
357 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
358 | ||
359 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
360 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
361 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
362 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
363 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
364 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
365 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
366 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
367 | ||
368 | { "ctr", 9, PPC_OPERAND_SPR }, | |
369 | { "dar", 19, PPC_OPERAND_SPR }, | |
370 | { "dec", 22, PPC_OPERAND_SPR }, | |
371 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
372 | ||
373 | /* Floating point registers */ | |
374 | { "f.0", 0, PPC_OPERAND_FPR }, | |
375 | { "f.1", 1, PPC_OPERAND_FPR }, | |
376 | { "f.10", 10, PPC_OPERAND_FPR }, | |
377 | { "f.11", 11, PPC_OPERAND_FPR }, | |
378 | { "f.12", 12, PPC_OPERAND_FPR }, | |
379 | { "f.13", 13, PPC_OPERAND_FPR }, | |
380 | { "f.14", 14, PPC_OPERAND_FPR }, | |
381 | { "f.15", 15, PPC_OPERAND_FPR }, | |
382 | { "f.16", 16, PPC_OPERAND_FPR }, | |
383 | { "f.17", 17, PPC_OPERAND_FPR }, | |
384 | { "f.18", 18, PPC_OPERAND_FPR }, | |
385 | { "f.19", 19, PPC_OPERAND_FPR }, | |
386 | { "f.2", 2, PPC_OPERAND_FPR }, | |
387 | { "f.20", 20, PPC_OPERAND_FPR }, | |
388 | { "f.21", 21, PPC_OPERAND_FPR }, | |
389 | { "f.22", 22, PPC_OPERAND_FPR }, | |
390 | { "f.23", 23, PPC_OPERAND_FPR }, | |
391 | { "f.24", 24, PPC_OPERAND_FPR }, | |
392 | { "f.25", 25, PPC_OPERAND_FPR }, | |
393 | { "f.26", 26, PPC_OPERAND_FPR }, | |
394 | { "f.27", 27, PPC_OPERAND_FPR }, | |
395 | { "f.28", 28, PPC_OPERAND_FPR }, | |
396 | { "f.29", 29, PPC_OPERAND_FPR }, | |
397 | { "f.3", 3, PPC_OPERAND_FPR }, | |
398 | { "f.30", 30, PPC_OPERAND_FPR }, | |
399 | { "f.31", 31, PPC_OPERAND_FPR }, | |
400 | { "f.32", 32, PPC_OPERAND_VSR }, | |
401 | { "f.33", 33, PPC_OPERAND_VSR }, | |
402 | { "f.34", 34, PPC_OPERAND_VSR }, | |
403 | { "f.35", 35, PPC_OPERAND_VSR }, | |
404 | { "f.36", 36, PPC_OPERAND_VSR }, | |
405 | { "f.37", 37, PPC_OPERAND_VSR }, | |
406 | { "f.38", 38, PPC_OPERAND_VSR }, | |
407 | { "f.39", 39, PPC_OPERAND_VSR }, | |
408 | { "f.4", 4, PPC_OPERAND_FPR }, | |
409 | { "f.40", 40, PPC_OPERAND_VSR }, | |
410 | { "f.41", 41, PPC_OPERAND_VSR }, | |
411 | { "f.42", 42, PPC_OPERAND_VSR }, | |
412 | { "f.43", 43, PPC_OPERAND_VSR }, | |
413 | { "f.44", 44, PPC_OPERAND_VSR }, | |
414 | { "f.45", 45, PPC_OPERAND_VSR }, | |
415 | { "f.46", 46, PPC_OPERAND_VSR }, | |
416 | { "f.47", 47, PPC_OPERAND_VSR }, | |
417 | { "f.48", 48, PPC_OPERAND_VSR }, | |
418 | { "f.49", 49, PPC_OPERAND_VSR }, | |
419 | { "f.5", 5, PPC_OPERAND_FPR }, | |
420 | { "f.50", 50, PPC_OPERAND_VSR }, | |
421 | { "f.51", 51, PPC_OPERAND_VSR }, | |
422 | { "f.52", 52, PPC_OPERAND_VSR }, | |
423 | { "f.53", 53, PPC_OPERAND_VSR }, | |
424 | { "f.54", 54, PPC_OPERAND_VSR }, | |
425 | { "f.55", 55, PPC_OPERAND_VSR }, | |
426 | { "f.56", 56, PPC_OPERAND_VSR }, | |
427 | { "f.57", 57, PPC_OPERAND_VSR }, | |
428 | { "f.58", 58, PPC_OPERAND_VSR }, | |
429 | { "f.59", 59, PPC_OPERAND_VSR }, | |
430 | { "f.6", 6, PPC_OPERAND_FPR }, | |
431 | { "f.60", 60, PPC_OPERAND_VSR }, | |
432 | { "f.61", 61, PPC_OPERAND_VSR }, | |
433 | { "f.62", 62, PPC_OPERAND_VSR }, | |
434 | { "f.63", 63, PPC_OPERAND_VSR }, | |
435 | { "f.7", 7, PPC_OPERAND_FPR }, | |
436 | { "f.8", 8, PPC_OPERAND_FPR }, | |
437 | { "f.9", 9, PPC_OPERAND_FPR }, | |
438 | ||
439 | { "f0", 0, PPC_OPERAND_FPR }, | |
440 | { "f1", 1, PPC_OPERAND_FPR }, | |
441 | { "f10", 10, PPC_OPERAND_FPR }, | |
442 | { "f11", 11, PPC_OPERAND_FPR }, | |
443 | { "f12", 12, PPC_OPERAND_FPR }, | |
444 | { "f13", 13, PPC_OPERAND_FPR }, | |
445 | { "f14", 14, PPC_OPERAND_FPR }, | |
446 | { "f15", 15, PPC_OPERAND_FPR }, | |
447 | { "f16", 16, PPC_OPERAND_FPR }, | |
448 | { "f17", 17, PPC_OPERAND_FPR }, | |
449 | { "f18", 18, PPC_OPERAND_FPR }, | |
450 | { "f19", 19, PPC_OPERAND_FPR }, | |
451 | { "f2", 2, PPC_OPERAND_FPR }, | |
452 | { "f20", 20, PPC_OPERAND_FPR }, | |
453 | { "f21", 21, PPC_OPERAND_FPR }, | |
454 | { "f22", 22, PPC_OPERAND_FPR }, | |
455 | { "f23", 23, PPC_OPERAND_FPR }, | |
456 | { "f24", 24, PPC_OPERAND_FPR }, | |
457 | { "f25", 25, PPC_OPERAND_FPR }, | |
458 | { "f26", 26, PPC_OPERAND_FPR }, | |
459 | { "f27", 27, PPC_OPERAND_FPR }, | |
460 | { "f28", 28, PPC_OPERAND_FPR }, | |
461 | { "f29", 29, PPC_OPERAND_FPR }, | |
462 | { "f3", 3, PPC_OPERAND_FPR }, | |
463 | { "f30", 30, PPC_OPERAND_FPR }, | |
464 | { "f31", 31, PPC_OPERAND_FPR }, | |
465 | { "f32", 32, PPC_OPERAND_VSR }, | |
466 | { "f33", 33, PPC_OPERAND_VSR }, | |
467 | { "f34", 34, PPC_OPERAND_VSR }, | |
468 | { "f35", 35, PPC_OPERAND_VSR }, | |
469 | { "f36", 36, PPC_OPERAND_VSR }, | |
470 | { "f37", 37, PPC_OPERAND_VSR }, | |
471 | { "f38", 38, PPC_OPERAND_VSR }, | |
472 | { "f39", 39, PPC_OPERAND_VSR }, | |
473 | { "f4", 4, PPC_OPERAND_FPR }, | |
474 | { "f40", 40, PPC_OPERAND_VSR }, | |
475 | { "f41", 41, PPC_OPERAND_VSR }, | |
476 | { "f42", 42, PPC_OPERAND_VSR }, | |
477 | { "f43", 43, PPC_OPERAND_VSR }, | |
478 | { "f44", 44, PPC_OPERAND_VSR }, | |
479 | { "f45", 45, PPC_OPERAND_VSR }, | |
480 | { "f46", 46, PPC_OPERAND_VSR }, | |
481 | { "f47", 47, PPC_OPERAND_VSR }, | |
482 | { "f48", 48, PPC_OPERAND_VSR }, | |
483 | { "f49", 49, PPC_OPERAND_VSR }, | |
484 | { "f5", 5, PPC_OPERAND_FPR }, | |
485 | { "f50", 50, PPC_OPERAND_VSR }, | |
486 | { "f51", 51, PPC_OPERAND_VSR }, | |
487 | { "f52", 52, PPC_OPERAND_VSR }, | |
488 | { "f53", 53, PPC_OPERAND_VSR }, | |
489 | { "f54", 54, PPC_OPERAND_VSR }, | |
490 | { "f55", 55, PPC_OPERAND_VSR }, | |
491 | { "f56", 56, PPC_OPERAND_VSR }, | |
492 | { "f57", 57, PPC_OPERAND_VSR }, | |
493 | { "f58", 58, PPC_OPERAND_VSR }, | |
494 | { "f59", 59, PPC_OPERAND_VSR }, | |
495 | { "f6", 6, PPC_OPERAND_FPR }, | |
496 | { "f60", 60, PPC_OPERAND_VSR }, | |
497 | { "f61", 61, PPC_OPERAND_VSR }, | |
498 | { "f62", 62, PPC_OPERAND_VSR }, | |
499 | { "f63", 63, PPC_OPERAND_VSR }, | |
500 | { "f7", 7, PPC_OPERAND_FPR }, | |
501 | { "f8", 8, PPC_OPERAND_FPR }, | |
502 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 503 | |
c3d65c1c | 504 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
505 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
506 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
507 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
508 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
509 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
510 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
511 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
512 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
513 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
514 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
515 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
516 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
517 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
518 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
519 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
520 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
521 | ||
522 | { "lr", 8, PPC_OPERAND_SPR }, | |
523 | ||
524 | /* General Purpose Registers */ | |
525 | { "r.0", 0, PPC_OPERAND_GPR }, | |
526 | { "r.1", 1, PPC_OPERAND_GPR }, | |
527 | { "r.10", 10, PPC_OPERAND_GPR }, | |
528 | { "r.11", 11, PPC_OPERAND_GPR }, | |
529 | { "r.12", 12, PPC_OPERAND_GPR }, | |
530 | { "r.13", 13, PPC_OPERAND_GPR }, | |
531 | { "r.14", 14, PPC_OPERAND_GPR }, | |
532 | { "r.15", 15, PPC_OPERAND_GPR }, | |
533 | { "r.16", 16, PPC_OPERAND_GPR }, | |
534 | { "r.17", 17, PPC_OPERAND_GPR }, | |
535 | { "r.18", 18, PPC_OPERAND_GPR }, | |
536 | { "r.19", 19, PPC_OPERAND_GPR }, | |
537 | { "r.2", 2, PPC_OPERAND_GPR }, | |
538 | { "r.20", 20, PPC_OPERAND_GPR }, | |
539 | { "r.21", 21, PPC_OPERAND_GPR }, | |
540 | { "r.22", 22, PPC_OPERAND_GPR }, | |
541 | { "r.23", 23, PPC_OPERAND_GPR }, | |
542 | { "r.24", 24, PPC_OPERAND_GPR }, | |
543 | { "r.25", 25, PPC_OPERAND_GPR }, | |
544 | { "r.26", 26, PPC_OPERAND_GPR }, | |
545 | { "r.27", 27, PPC_OPERAND_GPR }, | |
546 | { "r.28", 28, PPC_OPERAND_GPR }, | |
547 | { "r.29", 29, PPC_OPERAND_GPR }, | |
548 | { "r.3", 3, PPC_OPERAND_GPR }, | |
549 | { "r.30", 30, PPC_OPERAND_GPR }, | |
550 | { "r.31", 31, PPC_OPERAND_GPR }, | |
551 | { "r.4", 4, PPC_OPERAND_GPR }, | |
552 | { "r.5", 5, PPC_OPERAND_GPR }, | |
553 | { "r.6", 6, PPC_OPERAND_GPR }, | |
554 | { "r.7", 7, PPC_OPERAND_GPR }, | |
555 | { "r.8", 8, PPC_OPERAND_GPR }, | |
556 | { "r.9", 9, PPC_OPERAND_GPR }, | |
557 | ||
558 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
559 | ||
560 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
561 | ||
562 | { "r0", 0, PPC_OPERAND_GPR }, | |
563 | { "r1", 1, PPC_OPERAND_GPR }, | |
564 | { "r10", 10, PPC_OPERAND_GPR }, | |
565 | { "r11", 11, PPC_OPERAND_GPR }, | |
566 | { "r12", 12, PPC_OPERAND_GPR }, | |
567 | { "r13", 13, PPC_OPERAND_GPR }, | |
568 | { "r14", 14, PPC_OPERAND_GPR }, | |
569 | { "r15", 15, PPC_OPERAND_GPR }, | |
570 | { "r16", 16, PPC_OPERAND_GPR }, | |
571 | { "r17", 17, PPC_OPERAND_GPR }, | |
572 | { "r18", 18, PPC_OPERAND_GPR }, | |
573 | { "r19", 19, PPC_OPERAND_GPR }, | |
574 | { "r2", 2, PPC_OPERAND_GPR }, | |
575 | { "r20", 20, PPC_OPERAND_GPR }, | |
576 | { "r21", 21, PPC_OPERAND_GPR }, | |
577 | { "r22", 22, PPC_OPERAND_GPR }, | |
578 | { "r23", 23, PPC_OPERAND_GPR }, | |
579 | { "r24", 24, PPC_OPERAND_GPR }, | |
580 | { "r25", 25, PPC_OPERAND_GPR }, | |
581 | { "r26", 26, PPC_OPERAND_GPR }, | |
582 | { "r27", 27, PPC_OPERAND_GPR }, | |
583 | { "r28", 28, PPC_OPERAND_GPR }, | |
584 | { "r29", 29, PPC_OPERAND_GPR }, | |
585 | { "r3", 3, PPC_OPERAND_GPR }, | |
586 | { "r30", 30, PPC_OPERAND_GPR }, | |
587 | { "r31", 31, PPC_OPERAND_GPR }, | |
588 | { "r4", 4, PPC_OPERAND_GPR }, | |
589 | { "r5", 5, PPC_OPERAND_GPR }, | |
590 | { "r6", 6, PPC_OPERAND_GPR }, | |
591 | { "r7", 7, PPC_OPERAND_GPR }, | |
592 | { "r8", 8, PPC_OPERAND_GPR }, | |
593 | { "r9", 9, PPC_OPERAND_GPR }, | |
594 | ||
595 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
596 | ||
597 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
598 | ||
599 | { "sp", 1, PPC_OPERAND_GPR }, | |
600 | ||
601 | { "srr0", 26, PPC_OPERAND_SPR }, | |
602 | { "srr1", 27, PPC_OPERAND_SPR }, | |
603 | ||
604 | /* Vector (Altivec/VMX) registers */ | |
605 | { "v.0", 0, PPC_OPERAND_VR }, | |
606 | { "v.1", 1, PPC_OPERAND_VR }, | |
607 | { "v.10", 10, PPC_OPERAND_VR }, | |
608 | { "v.11", 11, PPC_OPERAND_VR }, | |
609 | { "v.12", 12, PPC_OPERAND_VR }, | |
610 | { "v.13", 13, PPC_OPERAND_VR }, | |
611 | { "v.14", 14, PPC_OPERAND_VR }, | |
612 | { "v.15", 15, PPC_OPERAND_VR }, | |
613 | { "v.16", 16, PPC_OPERAND_VR }, | |
614 | { "v.17", 17, PPC_OPERAND_VR }, | |
615 | { "v.18", 18, PPC_OPERAND_VR }, | |
616 | { "v.19", 19, PPC_OPERAND_VR }, | |
617 | { "v.2", 2, PPC_OPERAND_VR }, | |
618 | { "v.20", 20, PPC_OPERAND_VR }, | |
619 | { "v.21", 21, PPC_OPERAND_VR }, | |
620 | { "v.22", 22, PPC_OPERAND_VR }, | |
621 | { "v.23", 23, PPC_OPERAND_VR }, | |
622 | { "v.24", 24, PPC_OPERAND_VR }, | |
623 | { "v.25", 25, PPC_OPERAND_VR }, | |
624 | { "v.26", 26, PPC_OPERAND_VR }, | |
625 | { "v.27", 27, PPC_OPERAND_VR }, | |
626 | { "v.28", 28, PPC_OPERAND_VR }, | |
627 | { "v.29", 29, PPC_OPERAND_VR }, | |
628 | { "v.3", 3, PPC_OPERAND_VR }, | |
629 | { "v.30", 30, PPC_OPERAND_VR }, | |
630 | { "v.31", 31, PPC_OPERAND_VR }, | |
631 | { "v.4", 4, PPC_OPERAND_VR }, | |
632 | { "v.5", 5, PPC_OPERAND_VR }, | |
633 | { "v.6", 6, PPC_OPERAND_VR }, | |
634 | { "v.7", 7, PPC_OPERAND_VR }, | |
635 | { "v.8", 8, PPC_OPERAND_VR }, | |
636 | { "v.9", 9, PPC_OPERAND_VR }, | |
637 | ||
638 | { "v0", 0, PPC_OPERAND_VR }, | |
639 | { "v1", 1, PPC_OPERAND_VR }, | |
640 | { "v10", 10, PPC_OPERAND_VR }, | |
641 | { "v11", 11, PPC_OPERAND_VR }, | |
642 | { "v12", 12, PPC_OPERAND_VR }, | |
643 | { "v13", 13, PPC_OPERAND_VR }, | |
644 | { "v14", 14, PPC_OPERAND_VR }, | |
645 | { "v15", 15, PPC_OPERAND_VR }, | |
646 | { "v16", 16, PPC_OPERAND_VR }, | |
647 | { "v17", 17, PPC_OPERAND_VR }, | |
648 | { "v18", 18, PPC_OPERAND_VR }, | |
649 | { "v19", 19, PPC_OPERAND_VR }, | |
650 | { "v2", 2, PPC_OPERAND_VR }, | |
651 | { "v20", 20, PPC_OPERAND_VR }, | |
652 | { "v21", 21, PPC_OPERAND_VR }, | |
653 | { "v22", 22, PPC_OPERAND_VR }, | |
654 | { "v23", 23, PPC_OPERAND_VR }, | |
655 | { "v24", 24, PPC_OPERAND_VR }, | |
656 | { "v25", 25, PPC_OPERAND_VR }, | |
657 | { "v26", 26, PPC_OPERAND_VR }, | |
658 | { "v27", 27, PPC_OPERAND_VR }, | |
659 | { "v28", 28, PPC_OPERAND_VR }, | |
660 | { "v29", 29, PPC_OPERAND_VR }, | |
661 | { "v3", 3, PPC_OPERAND_VR }, | |
662 | { "v30", 30, PPC_OPERAND_VR }, | |
663 | { "v31", 31, PPC_OPERAND_VR }, | |
664 | { "v4", 4, PPC_OPERAND_VR }, | |
665 | { "v5", 5, PPC_OPERAND_VR }, | |
666 | { "v6", 6, PPC_OPERAND_VR }, | |
667 | { "v7", 7, PPC_OPERAND_VR }, | |
668 | { "v8", 8, PPC_OPERAND_VR }, | |
669 | { "v9", 9, PPC_OPERAND_VR }, | |
670 | ||
671 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
672 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
673 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
674 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
675 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
676 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
677 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
678 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
679 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
680 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
681 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
682 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
683 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
684 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
685 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
686 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
687 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
688 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
689 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
690 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
691 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
692 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
693 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
694 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
695 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
696 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
697 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
698 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
699 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
700 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
701 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
702 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
703 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
704 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
705 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
706 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
707 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
708 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
709 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
710 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
711 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
712 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
713 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
714 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
715 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
716 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
717 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
718 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
719 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
720 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
721 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
722 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
723 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
724 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
725 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
726 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
727 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
728 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
729 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
730 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
731 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
732 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
733 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
734 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
735 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
736 | ||
737 | { "vs0", 0, PPC_OPERAND_VSR }, | |
738 | { "vs1", 1, PPC_OPERAND_VSR }, | |
739 | { "vs10", 10, PPC_OPERAND_VSR }, | |
740 | { "vs11", 11, PPC_OPERAND_VSR }, | |
741 | { "vs12", 12, PPC_OPERAND_VSR }, | |
742 | { "vs13", 13, PPC_OPERAND_VSR }, | |
743 | { "vs14", 14, PPC_OPERAND_VSR }, | |
744 | { "vs15", 15, PPC_OPERAND_VSR }, | |
745 | { "vs16", 16, PPC_OPERAND_VSR }, | |
746 | { "vs17", 17, PPC_OPERAND_VSR }, | |
747 | { "vs18", 18, PPC_OPERAND_VSR }, | |
748 | { "vs19", 19, PPC_OPERAND_VSR }, | |
749 | { "vs2", 2, PPC_OPERAND_VSR }, | |
750 | { "vs20", 20, PPC_OPERAND_VSR }, | |
751 | { "vs21", 21, PPC_OPERAND_VSR }, | |
752 | { "vs22", 22, PPC_OPERAND_VSR }, | |
753 | { "vs23", 23, PPC_OPERAND_VSR }, | |
754 | { "vs24", 24, PPC_OPERAND_VSR }, | |
755 | { "vs25", 25, PPC_OPERAND_VSR }, | |
756 | { "vs26", 26, PPC_OPERAND_VSR }, | |
757 | { "vs27", 27, PPC_OPERAND_VSR }, | |
758 | { "vs28", 28, PPC_OPERAND_VSR }, | |
759 | { "vs29", 29, PPC_OPERAND_VSR }, | |
760 | { "vs3", 3, PPC_OPERAND_VSR }, | |
761 | { "vs30", 30, PPC_OPERAND_VSR }, | |
762 | { "vs31", 31, PPC_OPERAND_VSR }, | |
763 | { "vs32", 32, PPC_OPERAND_VSR }, | |
764 | { "vs33", 33, PPC_OPERAND_VSR }, | |
765 | { "vs34", 34, PPC_OPERAND_VSR }, | |
766 | { "vs35", 35, PPC_OPERAND_VSR }, | |
767 | { "vs36", 36, PPC_OPERAND_VSR }, | |
768 | { "vs37", 37, PPC_OPERAND_VSR }, | |
769 | { "vs38", 38, PPC_OPERAND_VSR }, | |
770 | { "vs39", 39, PPC_OPERAND_VSR }, | |
771 | { "vs4", 4, PPC_OPERAND_VSR }, | |
772 | { "vs40", 40, PPC_OPERAND_VSR }, | |
773 | { "vs41", 41, PPC_OPERAND_VSR }, | |
774 | { "vs42", 42, PPC_OPERAND_VSR }, | |
775 | { "vs43", 43, PPC_OPERAND_VSR }, | |
776 | { "vs44", 44, PPC_OPERAND_VSR }, | |
777 | { "vs45", 45, PPC_OPERAND_VSR }, | |
778 | { "vs46", 46, PPC_OPERAND_VSR }, | |
779 | { "vs47", 47, PPC_OPERAND_VSR }, | |
780 | { "vs48", 48, PPC_OPERAND_VSR }, | |
781 | { "vs49", 49, PPC_OPERAND_VSR }, | |
782 | { "vs5", 5, PPC_OPERAND_VSR }, | |
783 | { "vs50", 50, PPC_OPERAND_VSR }, | |
784 | { "vs51", 51, PPC_OPERAND_VSR }, | |
785 | { "vs52", 52, PPC_OPERAND_VSR }, | |
786 | { "vs53", 53, PPC_OPERAND_VSR }, | |
787 | { "vs54", 54, PPC_OPERAND_VSR }, | |
788 | { "vs55", 55, PPC_OPERAND_VSR }, | |
789 | { "vs56", 56, PPC_OPERAND_VSR }, | |
790 | { "vs57", 57, PPC_OPERAND_VSR }, | |
791 | { "vs58", 58, PPC_OPERAND_VSR }, | |
792 | { "vs59", 59, PPC_OPERAND_VSR }, | |
793 | { "vs6", 6, PPC_OPERAND_VSR }, | |
794 | { "vs60", 60, PPC_OPERAND_VSR }, | |
795 | { "vs61", 61, PPC_OPERAND_VSR }, | |
796 | { "vs62", 62, PPC_OPERAND_VSR }, | |
797 | { "vs63", 63, PPC_OPERAND_VSR }, | |
798 | { "vs7", 7, PPC_OPERAND_VSR }, | |
799 | { "vs8", 8, PPC_OPERAND_VSR }, | |
800 | { "vs9", 9, PPC_OPERAND_VSR }, | |
801 | ||
802 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
803 | }; |
804 | ||
bc805888 | 805 | #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) |
252b5132 RH |
806 | |
807 | /* Given NAME, find the register number associated with that name, return | |
808 | the integer value associated with the given name or -1 on failure. */ | |
809 | ||
7e0de605 | 810 | static const struct pd_reg * |
98027b10 | 811 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
812 | { |
813 | int middle, low, high; | |
814 | int cmp; | |
815 | ||
816 | low = 0; | |
817 | high = regcount - 1; | |
818 | ||
819 | do | |
820 | { | |
821 | middle = (low + high) / 2; | |
822 | cmp = strcasecmp (name, regs[middle].name); | |
823 | if (cmp < 0) | |
824 | high = middle - 1; | |
825 | else if (cmp > 0) | |
826 | low = middle + 1; | |
827 | else | |
7e0de605 | 828 | return ®s[middle]; |
252b5132 RH |
829 | } |
830 | while (low <= high); | |
831 | ||
7e0de605 | 832 | return NULL; |
252b5132 RH |
833 | } |
834 | ||
835 | /* | |
99a814a1 | 836 | * Summary of register_name. |
252b5132 RH |
837 | * |
838 | * in: Input_line_pointer points to 1st char of operand. | |
839 | * | |
840 | * out: A expressionS. | |
841 | * The operand may have been a register: in this case, X_op == O_register, | |
842 | * X_add_number is set to the register number, and truth is returned. | |
843 | * Input_line_pointer->(next non-blank) char after operand, or is in its | |
844 | * original state. | |
845 | */ | |
846 | ||
b34976b6 | 847 | static bfd_boolean |
98027b10 | 848 | register_name (expressionS *expressionP) |
252b5132 | 849 | { |
7e0de605 | 850 | const struct pd_reg *reg; |
252b5132 RH |
851 | char *name; |
852 | char *start; | |
853 | char c; | |
854 | ||
99a814a1 | 855 | /* Find the spelling of the operand. */ |
252b5132 | 856 | start = name = input_line_pointer; |
3882b010 | 857 | if (name[0] == '%' && ISALPHA (name[1])) |
252b5132 RH |
858 | name = ++input_line_pointer; |
859 | ||
3882b010 | 860 | else if (!reg_names_p || !ISALPHA (name[0])) |
b34976b6 | 861 | return FALSE; |
252b5132 | 862 | |
d02603dc | 863 | c = get_symbol_name (&name); |
7e0de605 | 864 | reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); |
252b5132 | 865 | |
468cced8 AM |
866 | /* Put back the delimiting char. */ |
867 | *input_line_pointer = c; | |
868 | ||
99a814a1 | 869 | /* Look to see if it's in the register table. */ |
7e0de605 | 870 | if (reg != NULL) |
252b5132 RH |
871 | { |
872 | expressionP->X_op = O_register; | |
7e0de605 AM |
873 | expressionP->X_add_number = reg->value; |
874 | expressionP->X_md = reg->flags; | |
81d4177b | 875 | |
99a814a1 | 876 | /* Make the rest nice. */ |
252b5132 RH |
877 | expressionP->X_add_symbol = NULL; |
878 | expressionP->X_op_symbol = NULL; | |
b34976b6 | 879 | return TRUE; |
252b5132 | 880 | } |
468cced8 AM |
881 | |
882 | /* Reset the line as if we had not done anything. */ | |
883 | input_line_pointer = start; | |
b34976b6 | 884 | return FALSE; |
252b5132 RH |
885 | } |
886 | \f | |
887 | /* This function is called for each symbol seen in an expression. It | |
888 | handles the special parsing which PowerPC assemblers are supposed | |
889 | to use for condition codes. */ | |
890 | ||
891 | /* Whether to do the special parsing. */ | |
b34976b6 | 892 | static bfd_boolean cr_operand; |
252b5132 RH |
893 | |
894 | /* Names to recognize in a condition code. This table is sorted. */ | |
895 | static const struct pd_reg cr_names[] = | |
896 | { | |
7e0de605 AM |
897 | { "cr0", 0, PPC_OPERAND_CR_REG }, |
898 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
899 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
900 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
901 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
902 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
903 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
904 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
905 | { "eq", 2, PPC_OPERAND_CR_BIT }, | |
906 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
907 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
908 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
909 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
910 | }; |
911 | ||
912 | /* Parsing function. This returns non-zero if it recognized an | |
913 | expression. */ | |
914 | ||
915 | int | |
91d6fa6a | 916 | ppc_parse_name (const char *name, expressionS *exp) |
252b5132 | 917 | { |
7e0de605 | 918 | const struct pd_reg *reg; |
252b5132 RH |
919 | |
920 | if (! cr_operand) | |
921 | return 0; | |
922 | ||
13abbae3 AM |
923 | if (*name == '%') |
924 | ++name; | |
7e0de605 | 925 | reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0], |
252b5132 | 926 | name); |
7e0de605 | 927 | if (reg == NULL) |
252b5132 RH |
928 | return 0; |
929 | ||
7e0de605 AM |
930 | exp->X_op = O_register; |
931 | exp->X_add_number = reg->value; | |
932 | exp->X_md = reg->flags; | |
252b5132 RH |
933 | |
934 | return 1; | |
935 | } | |
7e0de605 AM |
936 | |
937 | /* Propagate X_md and check register expressions. This is to support | |
938 | condition codes like 4*cr5+eq. */ | |
939 | ||
940 | int | |
941 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
942 | { | |
943 | /* Accept 4*cr<n> and cr<n>*4. */ | |
944 | if (op == O_multiply | |
945 | && ((right->X_op == O_register | |
946 | && right->X_md == PPC_OPERAND_CR_REG | |
947 | && left->X_op == O_constant | |
948 | && left->X_add_number == 4) | |
949 | || (left->X_op == O_register | |
950 | && left->X_md == PPC_OPERAND_CR_REG | |
951 | && right->X_op == O_constant | |
952 | && right->X_add_number == 4))) | |
953 | { | |
954 | left->X_op = O_register; | |
955 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
956 | left->X_add_number *= right->X_add_number; | |
957 | return 1; | |
958 | } | |
959 | ||
960 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
961 | if (right->X_op == O_register | |
962 | && left->X_op == O_register | |
963 | && op == O_add | |
964 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
965 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
966 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
967 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
968 | { | |
969 | left->X_md = PPC_OPERAND_CR_BIT; | |
970 | right->X_op = O_constant; | |
971 | return 0; | |
972 | } | |
973 | ||
974 | /* Accept reg +/- constant. */ | |
975 | if (left->X_op == O_register | |
976 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 977 | as_warn (_("invalid register expression")); |
7e0de605 AM |
978 | |
979 | /* Accept constant + reg. */ | |
980 | if (right->X_op == O_register) | |
981 | { | |
982 | if (op == O_add && left->X_op == O_constant) | |
983 | left->X_md = right->X_md; | |
984 | else | |
ece5dcc1 | 985 | as_warn (_("invalid register expression")); |
7e0de605 AM |
986 | } |
987 | ||
988 | return 0; | |
989 | } | |
252b5132 RH |
990 | \f |
991 | /* Local variables. */ | |
992 | ||
2b3c4602 AM |
993 | /* Whether to target xcoff64/elf64. */ |
994 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 995 | |
252b5132 RH |
996 | /* Opcode hash table. */ |
997 | static struct hash_control *ppc_hash; | |
998 | ||
999 | /* Macro hash table. */ | |
1000 | static struct hash_control *ppc_macro_hash; | |
1001 | ||
1002 | #ifdef OBJ_ELF | |
99a814a1 | 1003 | /* What type of shared library support to use. */ |
5d6f4f16 | 1004 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 1005 | |
99a814a1 | 1006 | /* Flags to set in the elf header. */ |
252b5132 RH |
1007 | static flagword ppc_flags = 0; |
1008 | ||
1009 | /* Whether this is Solaris or not. */ | |
1010 | #ifdef TARGET_SOLARIS_COMMENT | |
b34976b6 | 1011 | #define SOLARIS_P TRUE |
252b5132 | 1012 | #else |
b34976b6 | 1013 | #define SOLARIS_P FALSE |
252b5132 RH |
1014 | #endif |
1015 | ||
b34976b6 | 1016 | static bfd_boolean msolaris = SOLARIS_P; |
252b5132 RH |
1017 | #endif |
1018 | ||
1019 | #ifdef OBJ_XCOFF | |
1020 | ||
1021 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
1022 | using a bunch of different sections. These assembler sections, | |
1023 | however, are all encompassed within the .text or .data sections of | |
1024 | the final output file. We handle this by using different | |
1025 | subsegments within these main segments. */ | |
1026 | ||
1027 | /* Next subsegment to allocate within the .text segment. */ | |
1028 | static subsegT ppc_text_subsegment = 2; | |
1029 | ||
1030 | /* Linked list of csects in the text section. */ | |
1031 | static symbolS *ppc_text_csects; | |
1032 | ||
1033 | /* Next subsegment to allocate within the .data segment. */ | |
1034 | static subsegT ppc_data_subsegment = 2; | |
1035 | ||
1036 | /* Linked list of csects in the data section. */ | |
1037 | static symbolS *ppc_data_csects; | |
1038 | ||
1039 | /* The current csect. */ | |
1040 | static symbolS *ppc_current_csect; | |
1041 | ||
1042 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1043 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1044 | A special relocation is used when accessing TOC entries. We handle | |
1045 | the TOC as a subsegment within the .data segment. We set it up if | |
1046 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1047 | static symbolS *ppc_toc_csect; | |
1048 | ||
1049 | /* The first frag in the TOC subsegment. */ | |
1050 | static fragS *ppc_toc_frag; | |
1051 | ||
1052 | /* The first frag in the first subsegment after the TOC in the .data | |
1053 | segment. NULL if there are no subsegments after the TOC. */ | |
1054 | static fragS *ppc_after_toc_frag; | |
1055 | ||
1056 | /* The current static block. */ | |
1057 | static symbolS *ppc_current_block; | |
1058 | ||
1059 | /* The COFF debugging section; set by md_begin. This is not the | |
1060 | .debug section, but is instead the secret BFD section which will | |
1061 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1062 | static asection *ppc_coff_debug_section; | |
1063 | ||
85645aed TG |
1064 | /* Structure to set the length field of the dwarf sections. */ |
1065 | struct dw_subsection { | |
1066 | /* Subsections are simply linked. */ | |
1067 | struct dw_subsection *link; | |
1068 | ||
1069 | /* The subsection number. */ | |
1070 | subsegT subseg; | |
1071 | ||
1072 | /* Expression to compute the length of the section. */ | |
1073 | expressionS end_exp; | |
1074 | }; | |
1075 | ||
1076 | static struct dw_section { | |
1077 | /* Corresponding section. */ | |
1078 | segT sect; | |
1079 | ||
1080 | /* Simply linked list of subsections with a label. */ | |
1081 | struct dw_subsection *list_subseg; | |
1082 | ||
1083 | /* The anonymous subsection. */ | |
1084 | struct dw_subsection *anon_subseg; | |
1085 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1086 | #endif /* OBJ_XCOFF */ |
1087 | ||
1088 | #ifdef TE_PE | |
1089 | ||
1090 | /* Various sections that we need for PE coff support. */ | |
1091 | static segT ydata_section; | |
1092 | static segT pdata_section; | |
1093 | static segT reldata_section; | |
1094 | static segT rdata_section; | |
1095 | static segT tocdata_section; | |
1096 | ||
81d4177b | 1097 | /* The current section and the previous section. See ppc_previous. */ |
252b5132 RH |
1098 | static segT ppc_previous_section; |
1099 | static segT ppc_current_section; | |
1100 | ||
1101 | #endif /* TE_PE */ | |
1102 | ||
1103 | #ifdef OBJ_ELF | |
1104 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1105 | unsigned long *ppc_apuinfo_list; |
1106 | unsigned int ppc_apuinfo_num; | |
1107 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1108 | #endif /* OBJ_ELF */ |
1109 | \f | |
1110 | #ifdef OBJ_ELF | |
15c1449b | 1111 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1112 | #else |
15c1449b | 1113 | const char *const md_shortopts = "um:"; |
252b5132 | 1114 | #endif |
cef4f754 | 1115 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1116 | const struct option md_longopts[] = { |
cef4f754 | 1117 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1118 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1119 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1120 | {NULL, no_argument, NULL, 0} |
1121 | }; | |
15c1449b | 1122 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1123 | |
1124 | int | |
17b9d67d | 1125 | md_parse_option (int c, const char *arg) |
252b5132 | 1126 | { |
69fe9ce5 AM |
1127 | ppc_cpu_t new_cpu; |
1128 | ||
252b5132 RH |
1129 | switch (c) |
1130 | { | |
1131 | case 'u': | |
1132 | /* -u means that any undefined symbols should be treated as | |
1133 | external, which is the default for gas anyhow. */ | |
1134 | break; | |
1135 | ||
1136 | #ifdef OBJ_ELF | |
1137 | case 'l': | |
1138 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1139 | sake, recognize -be also. */ |
252b5132 RH |
1140 | if (strcmp (arg, "e") == 0) |
1141 | { | |
1142 | target_big_endian = 0; | |
1143 | set_target_endian = 1; | |
b9c361e0 | 1144 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1145 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1146 | } |
1147 | else | |
1148 | return 0; | |
1149 | ||
1150 | break; | |
1151 | ||
1152 | case 'b': | |
1153 | if (strcmp (arg, "e") == 0) | |
1154 | { | |
1155 | target_big_endian = 1; | |
1156 | set_target_endian = 1; | |
1157 | } | |
1158 | else | |
1159 | return 0; | |
1160 | ||
1161 | break; | |
1162 | ||
1163 | case 'K': | |
99a814a1 | 1164 | /* Recognize -K PIC. */ |
252b5132 RH |
1165 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1166 | { | |
1167 | shlib = SHLIB_PIC; | |
1168 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1169 | } | |
1170 | else | |
1171 | return 0; | |
1172 | ||
1173 | break; | |
1174 | #endif | |
1175 | ||
7f6d05e8 CP |
1176 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1177 | case 'a': | |
1178 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1179 | { |
1180 | #ifdef BFD64 | |
1181 | ppc_obj64 = 1; | |
d6ed37ed AM |
1182 | if (ppc_cpu & PPC_OPCODE_VLE) |
1183 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1184 | #else |
1185 | as_fatal (_("%s unsupported"), "-a64"); | |
1186 | #endif | |
1187 | } | |
7f6d05e8 | 1188 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1189 | ppc_obj64 = 0; |
7f6d05e8 CP |
1190 | else |
1191 | return 0; | |
1192 | break; | |
81d4177b | 1193 | |
252b5132 | 1194 | case 'm': |
776fc418 | 1195 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1196 | /* "raw" is only valid for the disassembler. */ |
1197 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1198 | { |
1199 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1200 | if (strcmp (arg, "vle") == 0) |
1201 | { | |
1202 | if (set_target_endian && target_big_endian == 0) | |
1203 | as_bad (_("the use of -mvle requires big endian.")); | |
1204 | if (ppc_obj64) | |
1205 | as_bad (_("the use of -mvle requires -a32.")); | |
1206 | } | |
b9c361e0 | 1207 | } |
252b5132 | 1208 | |
83eef883 AFB |
1209 | else if (strcmp (arg, "no-vle") == 0) |
1210 | { | |
1211 | sticky &= ~PPC_OPCODE_VLE; | |
1212 | ||
1213 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1214 | new_cpu &= ~PPC_OPCODE_VLE; | |
1215 | ||
1216 | ppc_cpu = new_cpu; | |
1217 | } | |
1218 | ||
252b5132 | 1219 | else if (strcmp (arg, "regnames") == 0) |
b34976b6 | 1220 | reg_names_p = TRUE; |
252b5132 RH |
1221 | |
1222 | else if (strcmp (arg, "no-regnames") == 0) | |
b34976b6 | 1223 | reg_names_p = FALSE; |
252b5132 RH |
1224 | |
1225 | #ifdef OBJ_ELF | |
99a814a1 AM |
1226 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1227 | that require relocation. */ | |
252b5132 RH |
1228 | else if (strcmp (arg, "relocatable") == 0) |
1229 | { | |
5d6f4f16 | 1230 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1231 | ppc_flags |= EF_PPC_RELOCATABLE; |
1232 | } | |
1233 | ||
1234 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1235 | { | |
5d6f4f16 | 1236 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1237 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1238 | } | |
1239 | ||
99a814a1 | 1240 | /* -memb, set embedded bit. */ |
252b5132 RH |
1241 | else if (strcmp (arg, "emb") == 0) |
1242 | ppc_flags |= EF_PPC_EMB; | |
1243 | ||
cc643b88 | 1244 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1245 | else if (strcmp (arg, "little") == 0 |
1246 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1247 | { |
1248 | target_big_endian = 0; | |
1249 | set_target_endian = 1; | |
b9c361e0 | 1250 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1251 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1252 | } |
1253 | ||
1254 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1255 | { | |
1256 | target_big_endian = 1; | |
1257 | set_target_endian = 1; | |
1258 | } | |
1259 | ||
1260 | else if (strcmp (arg, "solaris") == 0) | |
1261 | { | |
b34976b6 | 1262 | msolaris = TRUE; |
252b5132 RH |
1263 | ppc_comment_chars = ppc_solaris_comment_chars; |
1264 | } | |
1265 | ||
1266 | else if (strcmp (arg, "no-solaris") == 0) | |
1267 | { | |
b34976b6 | 1268 | msolaris = FALSE; |
252b5132 RH |
1269 | ppc_comment_chars = ppc_eabi_comment_chars; |
1270 | } | |
74081948 AF |
1271 | else if (strcmp (arg, "spe2") == 0) |
1272 | { | |
1273 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1274 | } | |
252b5132 RH |
1275 | #endif |
1276 | else | |
1277 | { | |
1278 | as_bad (_("invalid switch -m%s"), arg); | |
1279 | return 0; | |
1280 | } | |
1281 | break; | |
1282 | ||
1283 | #ifdef OBJ_ELF | |
1284 | /* -V: SVR4 argument to print version ID. */ | |
1285 | case 'V': | |
1286 | print_version_id (); | |
1287 | break; | |
1288 | ||
1289 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1290 | should be emitted or not. FIXME: Not implemented. */ | |
1291 | case 'Q': | |
1292 | break; | |
1293 | ||
1294 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1295 | rather than .stabs.excl, which is ignored by the linker. | |
1296 | FIXME: Not implemented. */ | |
1297 | case 's': | |
1298 | if (arg) | |
1299 | return 0; | |
1300 | ||
1301 | break; | |
1302 | #endif | |
1303 | ||
cef4f754 AM |
1304 | case OPTION_NOPS: |
1305 | { | |
1306 | char *end; | |
1307 | nop_limit = strtoul (optarg, &end, 0); | |
1308 | if (*end) | |
1309 | as_bad (_("--nops needs a numeric argument")); | |
1310 | } | |
1311 | break; | |
85645aed | 1312 | |
bf7279d5 AM |
1313 | case 0: |
1314 | break; | |
1315 | ||
252b5132 RH |
1316 | default: |
1317 | return 0; | |
1318 | } | |
1319 | ||
1320 | return 1; | |
1321 | } | |
1322 | ||
1323 | void | |
98027b10 | 1324 | md_show_usage (FILE *stream) |
252b5132 | 1325 | { |
bc805888 | 1326 | fprintf (stream, _("\ |
252b5132 | 1327 | PowerPC options:\n\ |
ce3d2015 AM |
1328 | -a32 generate ELF32/XCOFF32\n\ |
1329 | -a64 generate ELF64/XCOFF64\n\ | |
1330 | -u ignored\n\ | |
1331 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n\ | |
1332 | -mpwr generate code for POWER (RIOS1)\n\ | |
1333 | -m601 generate code for PowerPC 601\n\ | |
418c1742 | 1334 | -mppc, -mppc32, -m603, -m604\n\ |
ce3d2015 AM |
1335 | generate code for PowerPC 603/604\n\ |
1336 | -m403 generate code for PowerPC 403\n\ | |
1337 | -m405 generate code for PowerPC 405\n\ | |
1338 | -m440 generate code for PowerPC 440\n\ | |
1339 | -m464 generate code for PowerPC 464\n\ | |
1340 | -m476 generate code for PowerPC 476\n\ | |
f5c120c5 | 1341 | -m7400, -m7410, -m7450, -m7455\n\ |
ce3d2015 | 1342 | generate code for PowerPC 7400/7410/7450/7455\n\ |
fa758a70 AC |
1343 | -m750cl, -mgekko, -mbroadway\n\ |
1344 | generate code for PowerPC 750cl/Gekko/Broadway\n\ | |
ef5a96d5 | 1345 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1346 | fprintf (stream, _("\ |
ce3d2015 AM |
1347 | -mppc64, -m620 generate code for PowerPC 620/625/630\n\ |
1348 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n\ | |
1349 | -mbooke generate code for 32-bit PowerPC BookE\n\ | |
1350 | -ma2 generate code for A2 architecture\n\ | |
cdc51b07 RS |
1351 | -mpower4, -mpwr4 generate code for Power4 architecture\n\ |
1352 | -mpower5, -mpwr5, -mpwr5x\n\ | |
1353 | generate code for Power5 architecture\n\ | |
1354 | -mpower6, -mpwr6 generate code for Power6 architecture\n\ | |
1355 | -mpower7, -mpwr7 generate code for Power7 architecture\n\ | |
5817ffd1 | 1356 | -mpower8, -mpwr8 generate code for Power8 architecture\n\ |
a680de9a | 1357 | -mpower9, -mpwr9 generate code for Power9 architecture\n\ |
ce3d2015 | 1358 | -mcell generate code for Cell Broadband Engine architecture\n\ |
33eaf5de | 1359 | -mcom generate code for Power/PowerPC common instructions\n\ |
ce3d2015 | 1360 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1361 | fprintf (stream, _("\ |
ce3d2015 AM |
1362 | -maltivec generate code for AltiVec\n\ |
1363 | -mvsx generate code for Vector-Scalar (VSX) instructions\n\ | |
1364 | -me300 generate code for PowerPC e300 family\n\ | |
1365 | -me500, -me500x2 generate code for Motorola e500 core complex\n\ | |
1366 | -me500mc, generate code for Freescale e500mc core complex\n\ | |
1367 | -me500mc64, generate code for Freescale e500mc64 core complex\n\ | |
aea77599 AM |
1368 | -me5500, generate code for Freescale e5500 core complex\n\ |
1369 | -me6500, generate code for Freescale e6500 core complex\n\ | |
ce3d2015 | 1370 | -mspe generate code for Motorola SPE instructions\n\ |
74081948 | 1371 | -mspe2 generate code for Freescale SPE2 instructions\n\ |
b9c361e0 | 1372 | -mvle generate code for Freescale VLE instructions\n\ |
ce3d2015 AM |
1373 | -mtitan generate code for AppliedMicro Titan core complex\n\ |
1374 | -mregnames Allow symbolic names for registers\n\ | |
1375 | -mno-regnames Do not allow symbolic names for registers\n")); | |
252b5132 | 1376 | #ifdef OBJ_ELF |
bc805888 | 1377 | fprintf (stream, _("\ |
ce3d2015 AM |
1378 | -mrelocatable support for GCC's -mrelocatble option\n\ |
1379 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n\ | |
1380 | -memb set PPC_EMB bit in ELF flags\n\ | |
b8b738ac | 1381 | -mlittle, -mlittle-endian, -le\n\ |
ce3d2015 | 1382 | generate code for a little endian machine\n\ |
b8b738ac | 1383 | -mbig, -mbig-endian, -be\n\ |
ce3d2015 AM |
1384 | generate code for a big endian machine\n\ |
1385 | -msolaris generate code for Solaris\n\ | |
1386 | -mno-solaris do not generate code for Solaris\n\ | |
b8b738ac | 1387 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n\ |
ce3d2015 AM |
1388 | -V print assembler version number\n\ |
1389 | -Qy, -Qn ignored\n")); | |
252b5132 | 1390 | #endif |
cef4f754 | 1391 | fprintf (stream, _("\ |
bf7279d5 AM |
1392 | -nops=count when aligning, more than COUNT nops uses a branch\n\ |
1393 | -ppc476-workaround warn if emitting data to code sections\n")); | |
252b5132 RH |
1394 | } |
1395 | \f | |
1396 | /* Set ppc_cpu if it is not already set. */ | |
1397 | ||
1398 | static void | |
98027b10 | 1399 | ppc_set_cpu (void) |
252b5132 RH |
1400 | { |
1401 | const char *default_os = TARGET_OS; | |
1402 | const char *default_cpu = TARGET_CPU; | |
1403 | ||
7102e95e | 1404 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1405 | { |
2a98c3a6 | 1406 | if (ppc_obj64) |
f2ab4b42 PB |
1407 | if (target_big_endian) |
1408 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1409 | else | |
1410 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1411 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
2a98c3a6 AM |
1412 | else if (strncmp (default_os, "aix", 3) == 0 |
1413 | && default_os[3] >= '4' && default_os[3] <= '9') | |
bdc70b4a | 1414 | ppc_cpu |= PPC_OPCODE_COMMON; |
252b5132 | 1415 | else if (strncmp (default_os, "aix3", 4) == 0) |
bdc70b4a | 1416 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1417 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1418 | ppc_cpu |= PPC_OPCODE_POWER; |
0baf16f2 | 1419 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
bdc70b4a | 1420 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1421 | else |
d6ed37ed | 1422 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1423 | default_cpu, default_os); |
252b5132 RH |
1424 | } |
1425 | } | |
1426 | ||
9232bbb0 AM |
1427 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1428 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1429 | |
1430 | enum bfd_architecture | |
98027b10 | 1431 | ppc_arch (void) |
252b5132 RH |
1432 | { |
1433 | const char *default_cpu = TARGET_CPU; | |
1434 | ppc_set_cpu (); | |
1435 | ||
1436 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1437 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1438 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1439 | return bfd_arch_powerpc; | |
1440 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1441 | return bfd_arch_rs6000; |
b9c361e0 | 1442 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1443 | { |
1444 | if (strcmp (default_cpu, "rs6000") == 0) | |
1445 | return bfd_arch_rs6000; | |
0baf16f2 | 1446 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
252b5132 RH |
1447 | return bfd_arch_powerpc; |
1448 | } | |
1449 | ||
d6ed37ed | 1450 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1451 | return bfd_arch_unknown; |
1452 | } | |
1453 | ||
7f6d05e8 | 1454 | unsigned long |
98027b10 | 1455 | ppc_mach (void) |
7f6d05e8 | 1456 | { |
2a98c3a6 AM |
1457 | if (ppc_obj64) |
1458 | return bfd_mach_ppc64; | |
1459 | else if (ppc_arch () == bfd_arch_rs6000) | |
1460 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1461 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1462 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1463 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1464 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1465 | else |
1466 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1467 | } |
1468 | ||
e0471c16 | 1469 | extern const char* |
98027b10 | 1470 | ppc_target_format (void) |
7f6d05e8 CP |
1471 | { |
1472 | #ifdef OBJ_COFF | |
1473 | #ifdef TE_PE | |
99a814a1 | 1474 | return target_big_endian ? "pe-powerpc" : "pe-powerpcle"; |
7f6d05e8 | 1475 | #elif TE_POWERMAC |
0baf16f2 | 1476 | return "xcoff-powermac"; |
7f6d05e8 | 1477 | #else |
eb1e0e80 | 1478 | # ifdef TE_AIX5 |
edc1d652 | 1479 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1480 | # else |
edc1d652 | 1481 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1482 | # endif |
7f6d05e8 | 1483 | #endif |
7f6d05e8 CP |
1484 | #endif |
1485 | #ifdef OBJ_ELF | |
edc1d652 AM |
1486 | # ifdef TE_FreeBSD |
1487 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1488 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1489 | return "elf32-powerpc-vxworks"; |
1490 | # else | |
0baf16f2 | 1491 | return (target_big_endian |
2b3c4602 AM |
1492 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1493 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1494 | # endif |
7f6d05e8 CP |
1495 | #endif |
1496 | } | |
1497 | ||
b9c361e0 JL |
1498 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1499 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1500 | ||
1501 | static bfd_boolean | |
1502 | insn_validate (const struct powerpc_opcode *op) | |
1503 | { | |
1504 | const unsigned char *o; | |
0f873fd5 | 1505 | uint64_t omask = op->mask; |
b9c361e0 JL |
1506 | |
1507 | /* The mask had better not trim off opcode bits. */ | |
1508 | if ((op->opcode & omask) != op->opcode) | |
1509 | { | |
1510 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
1511 | return TRUE; | |
1512 | } | |
1513 | ||
1514 | /* The operands must not overlap the opcode or each other. */ | |
1515 | for (o = op->operands; *o; ++o) | |
1516 | { | |
2eac3da1 | 1517 | bfd_boolean optional = FALSE; |
b9c361e0 JL |
1518 | if (*o >= num_powerpc_operands) |
1519 | { | |
1520 | as_bad (_("operand index error for %s"), op->name); | |
1521 | return TRUE; | |
1522 | } | |
1523 | else | |
1524 | { | |
71553718 | 1525 | uint64_t mask; |
b9c361e0 | 1526 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1527 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1528 | { |
71553718 AM |
1529 | const char *errmsg; |
1530 | int64_t val; | |
1531 | ||
1532 | errmsg = NULL; | |
1533 | val = -1; | |
1534 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1535 | val = -val; | |
1536 | else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) | |
1537 | val += 1; | |
1538 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); | |
b9c361e0 | 1539 | } |
71553718 AM |
1540 | else if (operand->shift >= 0) |
1541 | mask = operand->bitm << operand->shift; | |
1542 | else | |
1543 | mask = operand->bitm >> -operand->shift; | |
1544 | if (omask & mask) | |
1545 | { | |
1546 | as_bad (_("operand %d overlap in %s"), | |
1547 | (int) (o - op->operands), op->name); | |
1548 | return TRUE; | |
1549 | } | |
1550 | omask |= mask; | |
2eac3da1 AM |
1551 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
1552 | optional = TRUE; | |
1553 | else if (optional) | |
1554 | { | |
1555 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1556 | (int) (o - op->operands), op->name); | |
1557 | return TRUE; | |
1558 | } | |
b9c361e0 JL |
1559 | } |
1560 | } | |
1561 | return FALSE; | |
1562 | } | |
1563 | ||
69c040df | 1564 | /* Insert opcodes and macros into hash tables. Called at startup and |
1fe532cf | 1565 | for .machine pseudo. */ |
252b5132 | 1566 | |
69c040df AM |
1567 | static void |
1568 | ppc_setup_opcodes (void) | |
252b5132 | 1569 | { |
98027b10 | 1570 | const struct powerpc_opcode *op; |
252b5132 RH |
1571 | const struct powerpc_opcode *op_end; |
1572 | const struct powerpc_macro *macro; | |
1573 | const struct powerpc_macro *macro_end; | |
b84bf58a | 1574 | bfd_boolean bad_insn = FALSE; |
252b5132 | 1575 | |
69c040df AM |
1576 | if (ppc_hash != NULL) |
1577 | hash_die (ppc_hash); | |
1578 | if (ppc_macro_hash != NULL) | |
1579 | hash_die (ppc_macro_hash); | |
252b5132 RH |
1580 | |
1581 | /* Insert the opcodes into a hash table. */ | |
1582 | ppc_hash = hash_new (); | |
1583 | ||
c43a438d | 1584 | if (ENABLE_CHECKING) |
b84bf58a | 1585 | { |
c43a438d | 1586 | unsigned int i; |
b84bf58a | 1587 | |
3b8b57a9 AM |
1588 | /* An index into powerpc_operands is stored in struct fix |
1589 | fx_pcrel_adjust which is 8 bits wide. */ | |
1590 | gas_assert (num_powerpc_operands < 256); | |
1591 | ||
c43a438d AM |
1592 | /* Check operand masks. Code here and in the disassembler assumes |
1593 | all the 1's in the mask are contiguous. */ | |
1594 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1595 | { |
0f873fd5 PB |
1596 | uint64_t mask = powerpc_operands[i].bitm; |
1597 | uint64_t right_bit; | |
c43a438d AM |
1598 | unsigned int j; |
1599 | ||
1600 | right_bit = mask & -mask; | |
1601 | mask += right_bit; | |
1602 | right_bit = mask & -mask; | |
1603 | if (mask != right_bit) | |
1604 | { | |
1605 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
1606 | bad_insn = TRUE; | |
1607 | } | |
1608 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1609 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1610 | sizeof (powerpc_operands[0])) == 0) | |
1611 | { | |
1612 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1613 | j, i); | |
1614 | bad_insn = TRUE; | |
1615 | } | |
b84bf58a AM |
1616 | } |
1617 | } | |
1618 | ||
252b5132 RH |
1619 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1620 | for (op = powerpc_opcodes; op < op_end; op++) | |
1621 | { | |
c43a438d | 1622 | if (ENABLE_CHECKING) |
b84bf58a | 1623 | { |
2ceb7719 | 1624 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1625 | |
1626 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1627 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1628 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1629 | new_opcode, (unsigned long long) op->opcode, | |
1630 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1631 | #endif |
1632 | ||
2ceb7719 PB |
1633 | /* The major opcodes had better be sorted. Code in the disassembler |
1634 | assumes the insns are sorted according to major opcode. */ | |
1635 | if (op != powerpc_opcodes | |
1636 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1637 | { | |
1638 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1639 | bad_insn = TRUE; | |
8dbcd839 | 1640 | } |
2ceb7719 | 1641 | |
14b57c7c AM |
1642 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1643 | { | |
1644 | as_bad (_("%s is enabled by vle flag"), op->name); | |
1645 | bad_insn = TRUE; | |
1646 | } | |
1647 | if (PPC_OP (op->opcode) != 4 | |
1648 | && PPC_OP (op->opcode) != 31 | |
1649 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1650 | { | |
1651 | as_bad (_("%s not disabled by vle flag"), op->name); | |
1652 | bad_insn = TRUE; | |
1653 | } | |
b9c361e0 JL |
1654 | bad_insn |= insn_validate (op); |
1655 | } | |
c43a438d | 1656 | |
b9c361e0 JL |
1657 | if ((ppc_cpu & op->flags) != 0 |
1658 | && !(ppc_cpu & op->deprecated)) | |
1659 | { | |
1660 | const char *retval; | |
1661 | ||
1662 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1663 | if (retval != NULL) | |
c43a438d | 1664 | { |
b9c361e0 | 1665 | as_bad (_("duplicate instruction %s"), |
c43a438d AM |
1666 | op->name); |
1667 | bad_insn = TRUE; | |
1668 | } | |
b9c361e0 JL |
1669 | } |
1670 | } | |
c43a438d | 1671 | |
b9c361e0 JL |
1672 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1673 | for (op = powerpc_opcodes; op < op_end; op++) | |
1674 | hash_insert (ppc_hash, op->name, (void *) op); | |
1675 | ||
1676 | op_end = vle_opcodes + vle_num_opcodes; | |
1677 | for (op = vle_opcodes; op < op_end; op++) | |
1678 | { | |
1679 | if (ENABLE_CHECKING) | |
1680 | { | |
2ceb7719 | 1681 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1682 | |
1683 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1684 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1685 | op->name, (unsigned int) (op - vle_opcodes), | |
1686 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1687 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1688 | #endif |
2ceb7719 PB |
1689 | |
1690 | /* The major opcodes had better be sorted. Code in the disassembler | |
1691 | assumes the insns are sorted according to major opcode. */ | |
1692 | if (op != vle_opcodes | |
1693 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1694 | { | |
1695 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1696 | bad_insn = TRUE; | |
b9c361e0 JL |
1697 | } |
1698 | ||
1699 | bad_insn |= insn_validate (op); | |
c43a438d | 1700 | } |
252b5132 | 1701 | |
bdc70b4a | 1702 | if ((ppc_cpu & op->flags) != 0 |
1cb0a767 | 1703 | && !(ppc_cpu & op->deprecated)) |
252b5132 RH |
1704 | { |
1705 | const char *retval; | |
1706 | ||
98027b10 | 1707 | retval = hash_insert (ppc_hash, op->name, (void *) op); |
69c040df | 1708 | if (retval != NULL) |
252b5132 | 1709 | { |
b84bf58a | 1710 | as_bad (_("duplicate instruction %s"), |
99a814a1 | 1711 | op->name); |
b84bf58a | 1712 | bad_insn = TRUE; |
252b5132 RH |
1713 | } |
1714 | } | |
1715 | } | |
1716 | ||
74081948 AF |
1717 | /* SPE2 instructions */ |
1718 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1719 | { | |
1720 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1721 | for (op = spe2_opcodes; op < op_end; op++) | |
1722 | { | |
1723 | if (ENABLE_CHECKING) | |
1724 | { | |
1725 | if (op != spe2_opcodes) | |
1726 | { | |
1727 | unsigned old_seg, new_seg; | |
1728 | ||
1729 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1730 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1731 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1732 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1733 | ||
1734 | /* The major opcodes had better be sorted. Code in the | |
1735 | disassembler assumes the insns are sorted according to | |
1736 | major opcode. */ | |
1737 | if (new_seg < old_seg) | |
1738 | { | |
1739 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1740 | bad_insn = TRUE; | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | bad_insn |= insn_validate (op); | |
1745 | } | |
1746 | ||
1747 | if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated)) | |
1748 | { | |
1749 | const char *retval; | |
1750 | ||
1751 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1752 | if (retval != NULL) | |
1753 | { | |
1754 | as_bad (_("duplicate instruction %s"), | |
1755 | op->name); | |
1756 | bad_insn = TRUE; | |
1757 | } | |
1758 | } | |
1759 | } | |
1760 | ||
1761 | for (op = spe2_opcodes; op < op_end; op++) | |
1762 | hash_insert (ppc_hash, op->name, (void *) op); | |
1763 | } | |
1764 | ||
252b5132 RH |
1765 | /* Insert the macros into a hash table. */ |
1766 | ppc_macro_hash = hash_new (); | |
1767 | ||
1768 | macro_end = powerpc_macros + powerpc_num_macros; | |
1769 | for (macro = powerpc_macros; macro < macro_end; macro++) | |
1770 | { | |
33740db9 | 1771 | if ((macro->flags & ppc_cpu) != 0 || (ppc_cpu & PPC_OPCODE_ANY) != 0) |
252b5132 RH |
1772 | { |
1773 | const char *retval; | |
1774 | ||
98027b10 | 1775 | retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro); |
252b5132 RH |
1776 | if (retval != (const char *) NULL) |
1777 | { | |
b84bf58a AM |
1778 | as_bad (_("duplicate macro %s"), macro->name); |
1779 | bad_insn = TRUE; | |
252b5132 RH |
1780 | } |
1781 | } | |
1782 | } | |
1783 | ||
b84bf58a | 1784 | if (bad_insn) |
252b5132 | 1785 | abort (); |
69c040df AM |
1786 | } |
1787 | ||
1788 | /* This function is called when the assembler starts up. It is called | |
1789 | after the options have been parsed and the output file has been | |
1790 | opened. */ | |
1791 | ||
1792 | void | |
98027b10 | 1793 | md_begin (void) |
69c040df AM |
1794 | { |
1795 | ppc_set_cpu (); | |
1796 | ||
1797 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1798 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1799 | |
1800 | #ifdef OBJ_ELF | |
1801 | /* Set the ELF flags if desired. */ | |
1802 | if (ppc_flags && !msolaris) | |
1803 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1804 | #endif | |
1805 | ||
1806 | ppc_setup_opcodes (); | |
252b5132 | 1807 | |
67c1ffbe | 1808 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1809 | by the user. */ |
252b5132 RH |
1810 | if (!set_target_endian) |
1811 | { | |
1812 | set_target_endian = 1; | |
1813 | target_big_endian = PPC_BIG_ENDIAN; | |
1814 | } | |
1815 | ||
1816 | #ifdef OBJ_XCOFF | |
1817 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1818 | ||
1819 | /* Create dummy symbols to serve as initial csects. This forces the | |
1820 | text csects to precede the data csects. These symbols will not | |
1821 | be output. */ | |
1822 | ppc_text_csects = symbol_make ("dummy\001"); | |
809ffe0d | 1823 | symbol_get_tc (ppc_text_csects)->within = ppc_text_csects; |
252b5132 | 1824 | ppc_data_csects = symbol_make ("dummy\001"); |
809ffe0d | 1825 | symbol_get_tc (ppc_data_csects)->within = ppc_data_csects; |
252b5132 RH |
1826 | #endif |
1827 | ||
1828 | #ifdef TE_PE | |
1829 | ||
1830 | ppc_current_section = text_section; | |
81d4177b | 1831 | ppc_previous_section = 0; |
252b5132 RH |
1832 | |
1833 | #endif | |
1834 | } | |
1835 | ||
6a0c61b7 | 1836 | void |
98027b10 | 1837 | ppc_cleanup (void) |
6a0c61b7 | 1838 | { |
dc1d03fc | 1839 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1840 | if (ppc_apuinfo_list == NULL) |
1841 | return; | |
1842 | ||
1843 | /* Ok, so write the section info out. We have this layout: | |
1844 | ||
1845 | byte data what | |
1846 | ---- ---- ---- | |
1847 | 0 8 length of "APUinfo\0" | |
1848 | 4 (n*4) number of APU's (4 bytes each) | |
1849 | 8 2 note type 2 | |
1850 | 12 "APUinfo\0" name | |
1851 | 20 APU#1 first APU's info | |
1852 | 24 APU#2 second APU's info | |
1853 | ... ... | |
1854 | */ | |
1855 | { | |
1856 | char *p; | |
1857 | asection *seg = now_seg; | |
1858 | subsegT subseg = now_subseg; | |
1859 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1860 | unsigned int i; |
6a0c61b7 EZ |
1861 | |
1862 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1863 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
6a0c61b7 EZ |
1864 | bfd_set_section_flags (stdoutput, |
1865 | apuinfo_secp, | |
e1a9cb8e | 1866 | SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1867 | |
1868 | p = frag_more (4); | |
1869 | md_number_to_chars (p, (valueT) 8, 4); | |
1870 | ||
1871 | p = frag_more (4); | |
e98d298c | 1872 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1873 | |
1874 | p = frag_more (4); | |
1875 | md_number_to_chars (p, (valueT) 2, 4); | |
1876 | ||
1877 | p = frag_more (8); | |
14b57c7c | 1878 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
1879 | |
1880 | for (i = 0; i < ppc_apuinfo_num; i++) | |
1881 | { | |
b34976b6 AM |
1882 | p = frag_more (4); |
1883 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
1884 | } |
1885 | ||
1886 | frag_align (2, 0, 0); | |
1887 | ||
1888 | /* We probably can't restore the current segment, for there likely | |
1889 | isn't one yet... */ | |
1890 | if (seg && subseg) | |
1891 | subseg_set (seg, subseg); | |
1892 | } | |
dc1d03fc | 1893 | #endif |
6a0c61b7 EZ |
1894 | } |
1895 | ||
252b5132 RH |
1896 | /* Insert an operand value into an instruction. */ |
1897 | ||
0f873fd5 PB |
1898 | static uint64_t |
1899 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 1900 | const struct powerpc_operand *operand, |
0f873fd5 | 1901 | int64_t val, |
91d6fa6a | 1902 | ppc_cpu_t cpu, |
3b4dbbbf | 1903 | const char *file, |
a1867a27 | 1904 | unsigned int line) |
252b5132 | 1905 | { |
0f873fd5 | 1906 | int64_t min, max, right; |
eb42fac1 | 1907 | |
b84bf58a AM |
1908 | max = operand->bitm; |
1909 | right = max & -max; | |
1910 | min = 0; | |
1911 | ||
a47622ac | 1912 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 1913 | { |
a255f00a AM |
1914 | /* Extend the allowed range for addis to [-32768, 65535]. |
1915 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
1916 | it would be good to disable this for signed fields since the | |
a47622ac AM |
1917 | value is sign extended into the high 32 bits of the register. |
1918 | If the value is, say, an address, then we might care about | |
1919 | the high bits. However, gcc as of 2014-06 uses unsigned | |
1920 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
1921 | lis. */ |
1922 | min = ~(max >> 1) & -right; | |
a47622ac AM |
1923 | } |
1924 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
1925 | { | |
1926 | max = (max >> 1) & -right; | |
931774a9 | 1927 | min = ~max & -right; |
b84bf58a | 1928 | } |
252b5132 | 1929 | |
b84bf58a | 1930 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 1931 | max++; |
252b5132 | 1932 | |
b84bf58a | 1933 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 1934 | { |
0f873fd5 | 1935 | int64_t tmp = min; |
a1867a27 AM |
1936 | min = -max; |
1937 | max = -tmp; | |
1938 | } | |
b84bf58a | 1939 | |
a1867a27 AM |
1940 | if (min <= max) |
1941 | { | |
1942 | /* Some people write constants with the sign extension done by | |
1943 | hand but only up to 32 bits. This shouldn't really be valid, | |
1944 | but, to permit this code to assemble on a 64-bit host, we | |
1945 | sign extend the 32-bit value to 64 bits if so doing makes the | |
1946 | value valid. */ | |
1947 | if (val > max | |
0f873fd5 PB |
1948 | && (val - (1LL << 32)) >= min |
1949 | && (val - (1LL << 32)) <= max | |
1950 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
1951 | val = val - (1LL << 32); | |
a1867a27 AM |
1952 | |
1953 | /* Similarly, people write expressions like ~(1<<15), and expect | |
1954 | this to be OK for a 32-bit unsigned value. */ | |
1955 | else if (val < min | |
0f873fd5 PB |
1956 | && (val + (1LL << 32)) >= min |
1957 | && (val + (1LL << 32)) <= max | |
1958 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
1959 | val = val + (1LL << 32); | |
a1867a27 AM |
1960 | |
1961 | else if (val < min | |
1962 | || val > max | |
1963 | || (val & (right - 1)) != 0) | |
1964 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
1965 | } | |
b84bf58a | 1966 | |
252b5132 RH |
1967 | if (operand->insert) |
1968 | { | |
1969 | const char *errmsg; | |
1970 | ||
1971 | errmsg = NULL; | |
0f873fd5 | 1972 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 1973 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 1974 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 1975 | } |
b9c361e0 | 1976 | else if (operand->shift >= 0) |
0f873fd5 | 1977 | insn |= (val & operand->bitm) << operand->shift; |
b9c361e0 | 1978 | else |
0f873fd5 | 1979 | insn |= (val & operand->bitm) >> -operand->shift; |
252b5132 RH |
1980 | |
1981 | return insn; | |
1982 | } | |
1983 | ||
1984 | \f | |
1985 | #ifdef OBJ_ELF | |
1986 | /* Parse @got, etc. and return the desired relocation. */ | |
1987 | static bfd_reloc_code_real_type | |
98027b10 | 1988 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
1989 | { |
1990 | struct map_bfd { | |
e0471c16 | 1991 | const char *string; |
b7d7dc63 AM |
1992 | unsigned int length : 8; |
1993 | unsigned int valid32 : 1; | |
1994 | unsigned int valid64 : 1; | |
1995 | unsigned int reloc; | |
252b5132 RH |
1996 | }; |
1997 | ||
1998 | char ident[20]; | |
1999 | char *str = *str_p; | |
2000 | char *str2; | |
2001 | int ch; | |
2002 | int len; | |
15c1449b | 2003 | const struct map_bfd *ptr; |
252b5132 | 2004 | |
b7d7dc63 AM |
2005 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2006 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2007 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2008 | |
15c1449b | 2009 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2010 | MAP ("l", BFD_RELOC_LO16), |
2011 | MAP ("h", BFD_RELOC_HI16), | |
2012 | MAP ("ha", BFD_RELOC_HI16_S), | |
2013 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2014 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2015 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2016 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2017 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2018 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2019 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2020 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2021 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2022 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2023 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2024 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2025 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2026 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2027 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2028 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2029 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2030 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2031 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2032 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2033 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2034 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2035 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2036 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2037 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2038 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2039 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2040 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2041 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2042 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2043 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2044 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2045 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2046 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2047 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2048 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2049 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2050 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2051 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2052 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2053 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2054 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2055 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2056 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2057 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2058 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2059 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2060 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2061 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2062 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2063 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2064 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2065 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2066 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2067 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2068 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2069 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2070 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2071 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2072 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2073 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2074 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2075 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2076 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2077 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2078 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2079 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2080 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2081 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2082 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2083 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2084 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2085 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2086 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2087 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2088 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2089 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2090 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2091 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2092 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2093 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2094 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2095 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2096 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2097 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2098 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2099 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2100 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2101 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2102 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2103 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2104 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2105 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2106 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
62ebcb5c | 2107 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2108 | }; |
2109 | ||
2110 | if (*str++ != '@') | |
62ebcb5c | 2111 | return BFD_RELOC_NONE; |
252b5132 RH |
2112 | |
2113 | for (ch = *str, str2 = ident; | |
2114 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2115 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2116 | ch = *++str) |
2117 | { | |
3882b010 | 2118 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2119 | } |
2120 | ||
2121 | *str2 = '\0'; | |
2122 | len = str2 - ident; | |
2123 | ||
2124 | ch = ident[0]; | |
2125 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2126 | if (ch == ptr->string[0] | |
2127 | && len == ptr->length | |
b7d7dc63 AM |
2128 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2129 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2130 | { |
15c1449b AM |
2131 | int reloc = ptr->reloc; |
2132 | ||
727fc41e AM |
2133 | if (!ppc_obj64 && exp_p->X_add_number != 0) |
2134 | { | |
2135 | switch (reloc) | |
2136 | { | |
2137 | case BFD_RELOC_16_GOTOFF: | |
2138 | case BFD_RELOC_LO16_GOTOFF: | |
2139 | case BFD_RELOC_HI16_GOTOFF: | |
2140 | case BFD_RELOC_HI16_S_GOTOFF: | |
2141 | as_warn (_("identifier+constant@got means " | |
2142 | "identifier@got+constant")); | |
2143 | break; | |
2144 | ||
2145 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2146 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2147 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2148 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2149 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2150 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2151 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2152 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2153 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2154 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2155 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2156 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2157 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2158 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2159 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2160 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
2161 | as_bad (_("symbol+offset not supported for got tls")); | |
2162 | break; | |
2163 | } | |
2164 | } | |
5f6db75a AM |
2165 | |
2166 | /* Now check for identifier@suffix+constant. */ | |
2167 | if (*str == '-' || *str == '+') | |
252b5132 | 2168 | { |
5f6db75a AM |
2169 | char *orig_line = input_line_pointer; |
2170 | expressionS new_exp; | |
2171 | ||
2172 | input_line_pointer = str; | |
2173 | expression (&new_exp); | |
2174 | if (new_exp.X_op == O_constant) | |
252b5132 | 2175 | { |
5f6db75a AM |
2176 | exp_p->X_add_number += new_exp.X_add_number; |
2177 | str = input_line_pointer; | |
252b5132 | 2178 | } |
5f6db75a AM |
2179 | |
2180 | if (&input_line_pointer != str_p) | |
2181 | input_line_pointer = orig_line; | |
252b5132 | 2182 | } |
252b5132 | 2183 | *str_p = str; |
0baf16f2 | 2184 | |
2b3c4602 | 2185 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2186 | && exp_p->X_op == O_symbol |
2187 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2188 | { |
9f2b53d7 AM |
2189 | /* Change the symbol so that the dummy .TOC. symbol can be |
2190 | omitted from the object file. */ | |
0baf16f2 AM |
2191 | exp_p->X_add_symbol = &abs_symbol; |
2192 | } | |
2193 | ||
15c1449b | 2194 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2195 | } |
2196 | ||
62ebcb5c | 2197 | return BFD_RELOC_NONE; |
252b5132 RH |
2198 | } |
2199 | ||
62ebcb5c | 2200 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2201 | |
62ebcb5c AM |
2202 | bfd_reloc_code_real_type |
2203 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2204 | { | |
2205 | expression (exp); | |
2206 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2207 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2208 | return BFD_RELOC_NONE; | |
252b5132 RH |
2209 | } |
2210 | ||
bf7279d5 AM |
2211 | /* Warn when emitting data to code sections, unless we are emitting |
2212 | a relocation that ld --ppc476-workaround uses to recognise data | |
2213 | *and* there was an unconditional branch prior to the data. */ | |
2214 | ||
2215 | void | |
2216 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2217 | unsigned int nbytes, fixS *fix) | |
2218 | { | |
2219 | if (warn_476 | |
2220 | && (now_seg->flags & SEC_CODE) != 0 | |
2221 | && (nbytes != 4 | |
2222 | || fix == NULL | |
2223 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2224 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2225 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2226 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2227 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2228 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2229 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2230 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2231 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2232 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2233 | { | |
2234 | /* Flag that we've warned. */ | |
2235 | if (fix != NULL) | |
2236 | fix->fx_tcbit = 1; | |
2237 | ||
2238 | as_warn (_("data in executable section")); | |
2239 | } | |
2240 | } | |
2241 | ||
252b5132 RH |
2242 | /* Solaris pseduo op to change to the .rodata section. */ |
2243 | static void | |
98027b10 | 2244 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2245 | { |
2246 | char *save_line = input_line_pointer; | |
2247 | static char section[] = ".rodata\n"; | |
2248 | ||
99a814a1 | 2249 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2250 | input_line_pointer = section; |
2251 | obj_elf_section (xxx); | |
2252 | ||
2253 | input_line_pointer = save_line; | |
2254 | } | |
2255 | ||
99a814a1 | 2256 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2257 | static void |
98027b10 | 2258 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2259 | { |
98027b10 AM |
2260 | char *name; |
2261 | char c; | |
2262 | char *p; | |
252b5132 | 2263 | offsetT size; |
98027b10 | 2264 | symbolS *symbolP; |
252b5132 RH |
2265 | offsetT align; |
2266 | segT old_sec; | |
2267 | int old_subsec; | |
2268 | char *pfrag; | |
2269 | int align2; | |
2270 | ||
d02603dc | 2271 | c = get_symbol_name (&name); |
252b5132 | 2272 | |
d02603dc | 2273 | /* Just after name is now '\0'. */ |
252b5132 RH |
2274 | p = input_line_pointer; |
2275 | *p = c; | |
d02603dc | 2276 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2277 | if (*input_line_pointer != ',') |
2278 | { | |
d6ed37ed | 2279 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2280 | ignore_rest_of_line (); |
2281 | return; | |
2282 | } | |
2283 | ||
2284 | input_line_pointer++; /* skip ',' */ | |
2285 | if ((size = get_absolute_expression ()) < 0) | |
2286 | { | |
2287 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2288 | ignore_rest_of_line (); | |
2289 | return; | |
2290 | } | |
2291 | ||
2292 | /* The third argument to .lcomm is the alignment. */ | |
2293 | if (*input_line_pointer != ',') | |
2294 | align = 8; | |
2295 | else | |
2296 | { | |
2297 | ++input_line_pointer; | |
2298 | align = get_absolute_expression (); | |
2299 | if (align <= 0) | |
2300 | { | |
2301 | as_warn (_("ignoring bad alignment")); | |
2302 | align = 8; | |
2303 | } | |
2304 | } | |
2305 | ||
2306 | *p = 0; | |
2307 | symbolP = symbol_find_or_make (name); | |
2308 | *p = c; | |
2309 | ||
2310 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2311 | { | |
d6ed37ed | 2312 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2313 | S_GET_NAME (symbolP)); |
2314 | ignore_rest_of_line (); | |
2315 | return; | |
2316 | } | |
2317 | ||
2318 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2319 | { | |
d6ed37ed | 2320 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2321 | S_GET_NAME (symbolP), |
2322 | (long) S_GET_VALUE (symbolP), | |
2323 | (long) size); | |
2324 | ||
2325 | ignore_rest_of_line (); | |
2326 | return; | |
2327 | } | |
2328 | ||
99a814a1 | 2329 | /* Allocate_bss. */ |
252b5132 RH |
2330 | old_sec = now_seg; |
2331 | old_subsec = now_subseg; | |
2332 | if (align) | |
2333 | { | |
99a814a1 | 2334 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2335 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2336 | if (align != 1) | |
2337 | { | |
d6ed37ed | 2338 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2339 | ignore_rest_of_line (); |
2340 | return; | |
2341 | } | |
2342 | } | |
2343 | else | |
2344 | align2 = 0; | |
2345 | ||
2346 | record_alignment (bss_section, align2); | |
cbe02d4f | 2347 | subseg_set (bss_section, 1); |
252b5132 RH |
2348 | if (align2) |
2349 | frag_align (align2, 0, 0); | |
2350 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2351 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2352 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2353 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2354 | (char *) 0); | |
2355 | *pfrag = 0; | |
2356 | S_SET_SIZE (symbolP, size); | |
2357 | S_SET_SEGMENT (symbolP, bss_section); | |
2358 | subseg_set (old_sec, old_subsec); | |
2359 | demand_empty_rest_of_line (); | |
2360 | } | |
2361 | ||
6911b7dc AM |
2362 | /* Pseudo op to set symbol local entry point. */ |
2363 | static void | |
2364 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2365 | { | |
d02603dc NC |
2366 | char *name; |
2367 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2368 | char *p; |
2369 | expressionS exp; | |
2370 | symbolS *sym; | |
2371 | asymbol *bfdsym; | |
2372 | elf_symbol_type *elfsym; | |
2373 | ||
2374 | p = input_line_pointer; | |
2375 | *p = c; | |
d02603dc | 2376 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2377 | if (*input_line_pointer != ',') |
2378 | { | |
2379 | *p = 0; | |
2380 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2381 | name); | |
2382 | *p = c; | |
2383 | ignore_rest_of_line (); | |
2384 | return; | |
2385 | } | |
2386 | input_line_pointer++; | |
2387 | expression (&exp); | |
2388 | if (exp.X_op == O_absent) | |
2389 | { | |
2390 | as_bad (_("missing expression in .localentry directive")); | |
2391 | exp.X_op = O_constant; | |
2392 | exp.X_add_number = 0; | |
2393 | } | |
2394 | *p = 0; | |
2395 | sym = symbol_find_or_make (name); | |
2396 | *p = c; | |
2397 | ||
2398 | if (resolve_expression (&exp) | |
2399 | && exp.X_op == O_constant) | |
2400 | { | |
33cb30a1 | 2401 | unsigned int encoded, ok; |
6911b7dc | 2402 | |
33cb30a1 AM |
2403 | ok = 1; |
2404 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2405 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2406 | else |
33cb30a1 AM |
2407 | { |
2408 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2409 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2410 | { | |
2411 | as_bad (_(".localentry expression for `%s' " | |
2412 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2413 | ok = 0; | |
2414 | } | |
2415 | } | |
2416 | if (ok) | |
6911b7dc AM |
2417 | { |
2418 | bfdsym = symbol_get_bfdsym (sym); | |
2419 | elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
2420 | gas_assert (elfsym); | |
2421 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2422 | elfsym->internal_elf_sym.st_other |= encoded; | |
2423 | if (ppc_abiversion == 0) | |
2424 | ppc_abiversion = 2; | |
2425 | } | |
2426 | } | |
2427 | else | |
2428 | as_bad (_(".localentry expression for `%s' " | |
2429 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2430 | ||
2431 | demand_empty_rest_of_line (); | |
2432 | } | |
2433 | ||
ee67d69a AM |
2434 | /* Pseudo op to set ABI version. */ |
2435 | static void | |
2436 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2437 | { | |
2438 | expressionS exp; | |
2439 | ||
2440 | expression (&exp); | |
2441 | if (exp.X_op == O_absent) | |
2442 | { | |
2443 | as_bad (_("missing expression in .abiversion directive")); | |
2444 | exp.X_op = O_constant; | |
2445 | exp.X_add_number = 0; | |
2446 | } | |
2447 | ||
2448 | if (resolve_expression (&exp) | |
2449 | && exp.X_op == O_constant) | |
2450 | ppc_abiversion = exp.X_add_number; | |
2451 | else | |
2452 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2453 | demand_empty_rest_of_line (); | |
2454 | } | |
2455 | ||
005d79fd AM |
2456 | /* Parse a .gnu_attribute directive. */ |
2457 | static void | |
2458 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2459 | { | |
2460 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2461 | ||
2462 | /* Check validity of defined powerpc tags. */ | |
2463 | if (tag == Tag_GNU_Power_ABI_FP | |
2464 | || tag == Tag_GNU_Power_ABI_Vector | |
2465 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2466 | { | |
2467 | unsigned int val; | |
2468 | ||
2469 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2470 | ||
2471 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2472 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2473 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2474 | as_warn (_("unknown .gnu_attribute value")); | |
2475 | } | |
2476 | } | |
2477 | ||
ee67d69a AM |
2478 | /* Set ABI version in output file. */ |
2479 | void | |
2480 | ppc_elf_end (void) | |
2481 | { | |
2482 | if (ppc_obj64 && ppc_abiversion != 0) | |
2483 | { | |
2484 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2485 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2486 | } | |
2487 | } | |
2488 | ||
252b5132 RH |
2489 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2490 | fixups for word relocations in writable segments, so we can adjust | |
2491 | them at runtime. */ | |
2492 | static void | |
98027b10 | 2493 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2494 | { |
2495 | if (fixp->fx_done || fixp->fx_pcrel) | |
2496 | return; | |
2497 | ||
2498 | switch (shlib) | |
2499 | { | |
2500 | case SHLIB_NONE: | |
2501 | case SHLIB_PIC: | |
2502 | return; | |
2503 | ||
5d6f4f16 | 2504 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2505 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2506 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2507 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2508 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2509 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2510 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2511 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2512 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2513 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2514 | && strcmp (segment_name (seg), ".got2") != 0 |
2515 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2516 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2517 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2518 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2519 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2520 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2521 | { | |
2522 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2523 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2524 | { | |
2525 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2526 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2527 | } |
2528 | } | |
2529 | return; | |
2530 | } | |
2531 | } | |
0baf16f2 | 2532 | |
7e8d4ab4 AM |
2533 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2534 | function descriptor sym if the corresponding code sym is used. */ | |
2535 | ||
2536 | void | |
98027b10 | 2537 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2538 | { |
7e8d4ab4 | 2539 | symbolS *symp; |
9232bbb0 | 2540 | asection *toc; |
0baf16f2 | 2541 | |
7e8d4ab4 AM |
2542 | if (!ppc_obj64) |
2543 | return; | |
2544 | ||
2545 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2546 | { |
7e8d4ab4 AM |
2547 | const char *name; |
2548 | char *dotname; | |
2549 | symbolS *dotsym; | |
7e8d4ab4 AM |
2550 | |
2551 | name = S_GET_NAME (symp); | |
2552 | if (name[0] == '.') | |
2553 | continue; | |
2554 | ||
2555 | if (! S_IS_WEAK (symp) | |
2556 | || S_IS_DEFINED (symp)) | |
2557 | continue; | |
2558 | ||
a44e2901 | 2559 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2560 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2561 | free (dotname); |
2562 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2563 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2564 | symbol_mark_used (symp); |
2565 | ||
0baf16f2 AM |
2566 | } |
2567 | ||
9232bbb0 AM |
2568 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2569 | if (toc != NULL | |
01efc3af | 2570 | && toc_reloc_types != has_large_toc_reloc |
9232bbb0 AM |
2571 | && bfd_section_size (stdoutput, toc) > 0x10000) |
2572 | as_warn (_("TOC section size exceeds 64k")); | |
a38a07e0 AM |
2573 | } |
2574 | ||
2575 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2576 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2577 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2578 | |
a38a07e0 AM |
2579 | void |
2580 | ppc_elf_adjust_symtab (void) | |
2581 | { | |
2582 | if (ppc_obj64) | |
2583 | { | |
2584 | symbolS *symp; | |
2585 | symp = symbol_find (".TOC."); | |
2586 | if (symp != NULL) | |
2587 | { | |
2588 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2589 | if ((bsym->flags & BSF_KEEP) == 0) | |
2590 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2591 | } |
2592 | } | |
0baf16f2 | 2593 | } |
252b5132 RH |
2594 | #endif /* OBJ_ELF */ |
2595 | \f | |
2596 | #ifdef TE_PE | |
2597 | ||
2598 | /* | |
99a814a1 | 2599 | * Summary of parse_toc_entry. |
252b5132 RH |
2600 | * |
2601 | * in: Input_line_pointer points to the '[' in one of: | |
2602 | * | |
2603 | * [toc] [tocv] [toc32] [toc64] | |
2604 | * | |
2605 | * Anything else is an error of one kind or another. | |
2606 | * | |
81d4177b | 2607 | * out: |
252b5132 RH |
2608 | * return value: success or failure |
2609 | * toc_kind: kind of toc reference | |
2610 | * input_line_pointer: | |
2611 | * success: first char after the ']' | |
2612 | * failure: unchanged | |
2613 | * | |
2614 | * settings: | |
2615 | * | |
2616 | * [toc] - rv == success, toc_kind = default_toc | |
2617 | * [tocv] - rv == success, toc_kind = data_in_toc | |
2618 | * [toc32] - rv == success, toc_kind = must_be_32 | |
2619 | * [toc64] - rv == success, toc_kind = must_be_64 | |
2620 | * | |
2621 | */ | |
2622 | ||
81d4177b KH |
2623 | enum toc_size_qualifier |
2624 | { | |
252b5132 RH |
2625 | default_toc, /* The toc cell constructed should be the system default size */ |
2626 | data_in_toc, /* This is a direct reference to a toc cell */ | |
2627 | must_be_32, /* The toc cell constructed must be 32 bits wide */ | |
2628 | must_be_64 /* The toc cell constructed must be 64 bits wide */ | |
2629 | }; | |
2630 | ||
2631 | static int | |
98027b10 | 2632 | parse_toc_entry (enum toc_size_qualifier *toc_kind) |
252b5132 RH |
2633 | { |
2634 | char *start; | |
2635 | char *toc_spec; | |
2636 | char c; | |
2637 | enum toc_size_qualifier t; | |
2638 | ||
99a814a1 | 2639 | /* Save the input_line_pointer. */ |
252b5132 RH |
2640 | start = input_line_pointer; |
2641 | ||
99a814a1 | 2642 | /* Skip over the '[' , and whitespace. */ |
252b5132 RH |
2643 | ++input_line_pointer; |
2644 | SKIP_WHITESPACE (); | |
81d4177b | 2645 | |
99a814a1 | 2646 | /* Find the spelling of the operand. */ |
d02603dc | 2647 | c = get_symbol_name (&toc_spec); |
252b5132 | 2648 | |
99a814a1 | 2649 | if (strcmp (toc_spec, "toc") == 0) |
252b5132 RH |
2650 | { |
2651 | t = default_toc; | |
2652 | } | |
99a814a1 | 2653 | else if (strcmp (toc_spec, "tocv") == 0) |
252b5132 RH |
2654 | { |
2655 | t = data_in_toc; | |
2656 | } | |
99a814a1 | 2657 | else if (strcmp (toc_spec, "toc32") == 0) |
252b5132 RH |
2658 | { |
2659 | t = must_be_32; | |
2660 | } | |
99a814a1 | 2661 | else if (strcmp (toc_spec, "toc64") == 0) |
252b5132 RH |
2662 | { |
2663 | t = must_be_64; | |
2664 | } | |
2665 | else | |
2666 | { | |
2667 | as_bad (_("syntax error: invalid toc specifier `%s'"), toc_spec); | |
99a814a1 AM |
2668 | *input_line_pointer = c; |
2669 | input_line_pointer = start; | |
252b5132 RH |
2670 | return 0; |
2671 | } | |
2672 | ||
99a814a1 AM |
2673 | /* Now find the ']'. */ |
2674 | *input_line_pointer = c; | |
252b5132 | 2675 | |
d02603dc | 2676 | SKIP_WHITESPACE_AFTER_NAME (); /* leading whitespace could be there. */ |
81d4177b | 2677 | c = *input_line_pointer++; /* input_line_pointer->past char in c. */ |
252b5132 RH |
2678 | |
2679 | if (c != ']') | |
2680 | { | |
2681 | as_bad (_("syntax error: expected `]', found `%c'"), c); | |
99a814a1 | 2682 | input_line_pointer = start; |
252b5132 RH |
2683 | return 0; |
2684 | } | |
2685 | ||
99a814a1 | 2686 | *toc_kind = t; |
252b5132 RH |
2687 | return 1; |
2688 | } | |
2689 | #endif | |
3b8b57a9 | 2690 | |
3e60bf4d | 2691 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2692 | /* See whether a symbol is in the TOC section. */ |
2693 | ||
2694 | static int | |
2695 | ppc_is_toc_sym (symbolS *sym) | |
2696 | { | |
3e60bf4d | 2697 | #ifdef OBJ_XCOFF |
9f6e76f4 TG |
2698 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
2699 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); | |
f50c47f1 | 2700 | #endif |
3e60bf4d AM |
2701 | #ifdef OBJ_ELF |
2702 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2703 | if (ppc_obj64) | |
2704 | return strcmp (sname, ".toc") == 0; | |
2705 | else | |
2706 | return strcmp (sname, ".got") == 0; | |
2707 | #endif | |
2708 | } | |
2709 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2710 | \f |
2711 | ||
dc1d03fc | 2712 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2713 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2714 | static void | |
98027b10 | 2715 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2716 | { |
2717 | unsigned int i; | |
2718 | ||
2719 | /* Check we don't already exist. */ | |
2720 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2721 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2722 | return; |
b34976b6 | 2723 | |
6a0c61b7 EZ |
2724 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2725 | { | |
2726 | if (ppc_apuinfo_num_alloc == 0) | |
2727 | { | |
2728 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2729 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2730 | } |
2731 | else | |
2732 | { | |
2733 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2734 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2735 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2736 | } |
2737 | } | |
dc1d03fc | 2738 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2739 | } |
2740 | #undef APUID | |
dc1d03fc | 2741 | #endif |
6a0c61b7 EZ |
2742 | \f |
2743 | ||
252b5132 RH |
2744 | /* We need to keep a list of fixups. We can't simply generate them as |
2745 | we go, because that would require us to first create the frag, and | |
2746 | that would screw up references to ``.''. */ | |
2747 | ||
2748 | struct ppc_fixup | |
2749 | { | |
2750 | expressionS exp; | |
2751 | int opindex; | |
2752 | bfd_reloc_code_real_type reloc; | |
2753 | }; | |
2754 | ||
2755 | #define MAX_INSN_FIXUPS (5) | |
2756 | ||
0e2779e9 AM |
2757 | /* Return the field size operated on by RELOC, and whether it is |
2758 | pc-relative in PC_RELATIVE. */ | |
2759 | ||
2760 | static unsigned int | |
2761 | fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative) | |
2762 | { | |
2763 | unsigned int size = 0; | |
2764 | bfd_boolean pcrel = FALSE; | |
2765 | ||
2766 | switch (reloc) | |
2767 | { | |
2768 | /* This switch statement must handle all BFD_RELOC values | |
2769 | possible in instruction fixups. As is, it handles all | |
2770 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
2771 | bfd/coff-ppc, bfd/coff-rs6000.c and bfd/coff64-rs6000.c. | |
2772 | Overkill since data and marker relocs need not be handled | |
2773 | here, but this way we can be sure a needed fixup reloc isn't | |
2774 | accidentally omitted. */ | |
2775 | case BFD_RELOC_PPC_EMB_MRKREF: | |
2776 | case BFD_RELOC_VTABLE_ENTRY: | |
2777 | case BFD_RELOC_VTABLE_INHERIT: | |
2778 | break; | |
2779 | ||
2780 | case BFD_RELOC_8: | |
2781 | size = 1; | |
2782 | break; | |
2783 | ||
2784 | case BFD_RELOC_16: | |
2785 | case BFD_RELOC_16_BASEREL: | |
2786 | case BFD_RELOC_16_GOTOFF: | |
2787 | case BFD_RELOC_GPREL16: | |
2788 | case BFD_RELOC_HI16: | |
2789 | case BFD_RELOC_HI16_BASEREL: | |
2790 | case BFD_RELOC_HI16_GOTOFF: | |
2791 | case BFD_RELOC_HI16_PLTOFF: | |
2792 | case BFD_RELOC_HI16_S: | |
2793 | case BFD_RELOC_HI16_S_BASEREL: | |
2794 | case BFD_RELOC_HI16_S_GOTOFF: | |
2795 | case BFD_RELOC_HI16_S_PLTOFF: | |
2796 | case BFD_RELOC_LO16: | |
2797 | case BFD_RELOC_LO16_BASEREL: | |
2798 | case BFD_RELOC_LO16_GOTOFF: | |
2799 | case BFD_RELOC_LO16_PLTOFF: | |
2800 | case BFD_RELOC_PPC64_ADDR16_DS: | |
2801 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
2802 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
2803 | case BFD_RELOC_PPC64_ADDR16_LO_DS: | |
2804 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
2805 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
2806 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
2807 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
2808 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
2809 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
2810 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
2811 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
2812 | case BFD_RELOC_PPC64_GOT16_DS: | |
2813 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
2814 | case BFD_RELOC_PPC64_HIGHER: | |
2815 | case BFD_RELOC_PPC64_HIGHER_S: | |
2816 | case BFD_RELOC_PPC64_HIGHEST: | |
2817 | case BFD_RELOC_PPC64_HIGHEST_S: | |
2818 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
2819 | case BFD_RELOC_PPC64_PLTGOT16: | |
2820 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
2821 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
2822 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
2823 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
2824 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
2825 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
2826 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
2827 | case BFD_RELOC_PPC64_TOC16_DS: | |
2828 | case BFD_RELOC_PPC64_TOC16_HA: | |
2829 | case BFD_RELOC_PPC64_TOC16_HI: | |
2830 | case BFD_RELOC_PPC64_TOC16_LO: | |
2831 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
2832 | case BFD_RELOC_PPC64_TPREL16_DS: | |
2833 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
2834 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
2835 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
2836 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
2837 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
2838 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
2839 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
2840 | #ifdef OBJ_XCOFF | |
2841 | case BFD_RELOC_PPC_BA16: | |
2842 | #endif | |
2843 | case BFD_RELOC_PPC_DTPREL16: | |
2844 | case BFD_RELOC_PPC_DTPREL16_HA: | |
2845 | case BFD_RELOC_PPC_DTPREL16_HI: | |
2846 | case BFD_RELOC_PPC_DTPREL16_LO: | |
2847 | case BFD_RELOC_PPC_EMB_NADDR16: | |
2848 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
2849 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
2850 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
2851 | case BFD_RELOC_PPC_EMB_RELSDA: | |
2852 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
2853 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
2854 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
2855 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
2856 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
2857 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
2858 | case BFD_RELOC_PPC_EMB_SDAI16: | |
2859 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2860 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2861 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2862 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2863 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2864 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2865 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2866 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2867 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2868 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2869 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2870 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2871 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2872 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
2873 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2874 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2875 | case BFD_RELOC_PPC_TOC16: | |
2876 | case BFD_RELOC_PPC_TPREL16: | |
2877 | case BFD_RELOC_PPC_TPREL16_HA: | |
2878 | case BFD_RELOC_PPC_TPREL16_HI: | |
2879 | case BFD_RELOC_PPC_TPREL16_LO: | |
2880 | size = 2; | |
2881 | break; | |
2882 | ||
2883 | case BFD_RELOC_16_PCREL: | |
2884 | case BFD_RELOC_HI16_PCREL: | |
2885 | case BFD_RELOC_HI16_S_PCREL: | |
2886 | case BFD_RELOC_LO16_PCREL: | |
2887 | case BFD_RELOC_PPC64_REL16_HIGH: | |
2888 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
2889 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
2890 | case BFD_RELOC_PPC64_REL16_HIGHERA: | |
2891 | case BFD_RELOC_PPC64_REL16_HIGHEST: | |
2892 | case BFD_RELOC_PPC64_REL16_HIGHESTA: | |
2893 | #ifdef OBJ_XCOFF | |
2894 | case BFD_RELOC_PPC_B16: | |
2895 | #endif | |
2896 | case BFD_RELOC_PPC_VLE_REL8: | |
2897 | size = 2; | |
2898 | pcrel = TRUE; | |
2899 | break; | |
2900 | ||
2901 | case BFD_RELOC_16_GOT_PCREL: /* coff reloc, bad name re size. */ | |
2902 | case BFD_RELOC_32: | |
2903 | case BFD_RELOC_32_GOTOFF: | |
2904 | case BFD_RELOC_32_PLTOFF: | |
2905 | #ifdef OBJ_XCOFF | |
2906 | case BFD_RELOC_CTOR: | |
2907 | #endif | |
2908 | case BFD_RELOC_PPC64_ENTRY: | |
2909 | case BFD_RELOC_PPC_16DX_HA: | |
2910 | #ifndef OBJ_XCOFF | |
2911 | case BFD_RELOC_PPC_BA16: | |
2912 | #endif | |
2913 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
2914 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
2915 | case BFD_RELOC_PPC_BA26: | |
2916 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
2917 | case BFD_RELOC_PPC_EMB_NADDR32: | |
2918 | case BFD_RELOC_PPC_EMB_SDA21: | |
2919 | case BFD_RELOC_PPC_TLS: | |
2920 | case BFD_RELOC_PPC_TLSGD: | |
2921 | case BFD_RELOC_PPC_TLSLD: | |
2922 | case BFD_RELOC_PPC_VLE_HA16A: | |
2923 | case BFD_RELOC_PPC_VLE_HA16D: | |
2924 | case BFD_RELOC_PPC_VLE_HI16A: | |
2925 | case BFD_RELOC_PPC_VLE_HI16D: | |
2926 | case BFD_RELOC_PPC_VLE_LO16A: | |
2927 | case BFD_RELOC_PPC_VLE_LO16D: | |
2928 | case BFD_RELOC_PPC_VLE_SDA21: | |
2929 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
2930 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
2931 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
2932 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
2933 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
2934 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
2935 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
2936 | case BFD_RELOC_RVA: | |
2937 | size = 4; | |
2938 | break; | |
2939 | ||
2940 | case BFD_RELOC_24_PLT_PCREL: | |
2941 | case BFD_RELOC_32_PCREL: | |
2942 | case BFD_RELOC_32_PLT_PCREL: | |
2943 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
2944 | #ifndef OBJ_XCOFF | |
2945 | case BFD_RELOC_PPC_B16: | |
2946 | #endif | |
2947 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
2948 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
2949 | case BFD_RELOC_PPC_B26: | |
2950 | case BFD_RELOC_PPC_LOCAL24PC: | |
2951 | case BFD_RELOC_PPC_REL16DX_HA: | |
2952 | case BFD_RELOC_PPC_VLE_REL15: | |
2953 | case BFD_RELOC_PPC_VLE_REL24: | |
2954 | size = 4; | |
2955 | pcrel = TRUE; | |
2956 | break; | |
2957 | ||
2958 | #ifndef OBJ_XCOFF | |
2959 | case BFD_RELOC_CTOR: | |
2960 | #endif | |
2961 | case BFD_RELOC_PPC_COPY: | |
2962 | case BFD_RELOC_PPC_DTPMOD: | |
2963 | case BFD_RELOC_PPC_DTPREL: | |
2964 | case BFD_RELOC_PPC_GLOB_DAT: | |
2965 | case BFD_RELOC_PPC_TPREL: | |
2966 | size = ppc_obj64 ? 8 : 4; | |
2967 | break; | |
2968 | ||
2969 | case BFD_RELOC_64: | |
2970 | case BFD_RELOC_64_PLTOFF: | |
2971 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
2972 | case BFD_RELOC_PPC64_TOC: | |
2973 | size = 8; | |
2974 | break; | |
2975 | ||
2976 | case BFD_RELOC_64_PCREL: | |
2977 | case BFD_RELOC_64_PLT_PCREL: | |
2978 | size = 8; | |
2979 | pcrel = TRUE; | |
2980 | break; | |
2981 | ||
2982 | default: | |
2983 | abort (); | |
2984 | } | |
2985 | ||
2986 | if (ENABLE_CHECKING) | |
2987 | { | |
2988 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
2989 | if (reloc_howto != NULL | |
2990 | && (size != bfd_get_reloc_size (reloc_howto) | |
2991 | || pcrel != reloc_howto->pc_relative)) | |
2992 | { | |
2993 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
2994 | reloc_howto->name); | |
2995 | abort (); | |
2996 | } | |
2997 | } | |
2998 | *pc_relative = pcrel; | |
2999 | return size; | |
3000 | } | |
3001 | ||
a894d76a | 3002 | #ifdef OBJ_ELF |
160eba93 AM |
3003 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3004 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3005 | is successfully parsed, *STR is updated past the trailing | |
3006 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3007 | reloc and arg expression. */ | |
3008 | ||
3009 | static int | |
3010 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3011 | { | |
3012 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3013 | if (sym_name[0] == '.') | |
3014 | ++sym_name; | |
3015 | ||
3016 | tls_fix->reloc = BFD_RELOC_NONE; | |
3017 | if (strcasecmp (sym_name, "__tls_get_addr") == 0) | |
3018 | { | |
3019 | char *hold = input_line_pointer; | |
3020 | input_line_pointer = *str + 1; | |
3021 | expression (&tls_fix->exp); | |
3022 | if (tls_fix->exp.X_op == O_symbol) | |
3023 | { | |
3024 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3025 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3026 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3027 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3028 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3029 | { | |
3030 | input_line_pointer += 7; | |
3031 | SKIP_WHITESPACE (); | |
3032 | *str = input_line_pointer; | |
3033 | } | |
3034 | } | |
3035 | input_line_pointer = hold; | |
3036 | } | |
3037 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3038 | } | |
a894d76a | 3039 | #endif |
160eba93 | 3040 | |
252b5132 RH |
3041 | /* This routine is called for each instruction to be assembled. */ |
3042 | ||
3043 | void | |
98027b10 | 3044 | md_assemble (char *str) |
252b5132 RH |
3045 | { |
3046 | char *s; | |
3047 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3048 | uint64_t insn; |
252b5132 | 3049 | const unsigned char *opindex_ptr; |
252b5132 RH |
3050 | int need_paren; |
3051 | int next_opindex; | |
3052 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3053 | int fc; | |
3054 | char *f; | |
a9479dc0 | 3055 | int addr_mask; |
252b5132 | 3056 | int i; |
b9c361e0 | 3057 | unsigned int insn_length; |
252b5132 RH |
3058 | |
3059 | /* Get the opcode. */ | |
3882b010 | 3060 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3061 | ; |
3062 | if (*s != '\0') | |
3063 | *s++ = '\0'; | |
3064 | ||
3065 | /* Look up the opcode in the hash table. */ | |
3066 | opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, str); | |
3067 | if (opcode == (const struct powerpc_opcode *) NULL) | |
3068 | { | |
3069 | const struct powerpc_macro *macro; | |
3070 | ||
3071 | macro = (const struct powerpc_macro *) hash_find (ppc_macro_hash, str); | |
3072 | if (macro == (const struct powerpc_macro *) NULL) | |
d6ed37ed | 3073 | as_bad (_("unrecognized opcode: `%s'"), str); |
252b5132 RH |
3074 | else |
3075 | ppc_macro (s, macro); | |
3076 | ||
3077 | return; | |
3078 | } | |
3079 | ||
3080 | insn = opcode->opcode; | |
3081 | ||
3082 | str = s; | |
3882b010 | 3083 | while (ISSPACE (*str)) |
252b5132 RH |
3084 | ++str; |
3085 | ||
3086 | /* PowerPC operands are just expressions. The only real issue is | |
9cf7e568 AM |
3087 | that a few operand types are optional. If an instruction has |
3088 | multiple optional operands and one is omitted, then all optional | |
3089 | operands past the first omitted one must also be omitted. */ | |
3090 | int num_optional_operands = 0; | |
3091 | int num_optional_provided = 0; | |
252b5132 RH |
3092 | |
3093 | /* Gather the operands. */ | |
3094 | need_paren = 0; | |
3095 | next_opindex = 0; | |
3096 | fc = 0; | |
3097 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3098 | { | |
3099 | const struct powerpc_operand *operand; | |
3100 | const char *errmsg; | |
3101 | char *hold; | |
3102 | expressionS ex; | |
3103 | char endc; | |
3104 | ||
3105 | if (next_opindex == 0) | |
3106 | operand = &powerpc_operands[*opindex_ptr]; | |
3107 | else | |
3108 | { | |
3109 | operand = &powerpc_operands[next_opindex]; | |
3110 | next_opindex = 0; | |
3111 | } | |
252b5132 RH |
3112 | errmsg = NULL; |
3113 | ||
252b5132 | 3114 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3115 | insert the default value, usually a zero. */ |
252b5132 | 3116 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3117 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3118 | { |
9cf7e568 AM |
3119 | if (num_optional_operands == 0) |
3120 | { | |
3121 | const unsigned char *optr; | |
3122 | int total = 0; | |
3123 | int provided = 0; | |
3124 | int omitted; | |
3125 | ||
3126 | s = str; | |
3127 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3128 | { | |
3129 | const struct powerpc_operand *op; | |
3130 | op = &powerpc_operands[*optr]; | |
3131 | ||
3132 | ++total; | |
3133 | ||
3134 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3135 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3136 | && ppc_obj64)) | |
3137 | ++num_optional_operands; | |
3138 | ||
3139 | if (s != NULL && *s != '\0') | |
3140 | { | |
3141 | ++provided; | |
3142 | ||
3143 | /* Look for the start of the next operand. */ | |
3144 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3145 | s = strpbrk (s, "(,"); | |
3146 | else | |
3147 | s = strchr (s, ','); | |
3148 | ||
3149 | if (s != NULL) | |
3150 | ++s; | |
3151 | } | |
3152 | } | |
3153 | omitted = total - provided; | |
3154 | num_optional_provided = num_optional_operands - omitted; | |
3155 | } | |
3156 | if (--num_optional_provided < 0) | |
252b5132 | 3157 | { |
9cf7e568 AM |
3158 | int64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3159 | num_optional_provided); | |
3160 | if (operand->insert) | |
3161 | { | |
3162 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3163 | if (errmsg != (const char *) NULL) | |
3164 | as_bad ("%s", errmsg); | |
3165 | } | |
3166 | else if (operand->shift >= 0) | |
3167 | insn |= (val & operand->bitm) << operand->shift; | |
3168 | else | |
3169 | insn |= (val & operand->bitm) >> -operand->shift; | |
3170 | ||
3171 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3172 | next_opindex = *opindex_ptr + 1; | |
3173 | continue; | |
252b5132 | 3174 | } |
252b5132 RH |
3175 | } |
3176 | ||
3177 | /* Gather the operand. */ | |
3178 | hold = input_line_pointer; | |
3179 | input_line_pointer = str; | |
3180 | ||
3181 | #ifdef TE_PE | |
81d4177b | 3182 | if (*input_line_pointer == '[') |
252b5132 RH |
3183 | { |
3184 | /* We are expecting something like the second argument here: | |
99a814a1 AM |
3185 | * |
3186 | * lwz r4,[toc].GS.0.static_int(rtoc) | |
3187 | * ^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
3188 | * The argument following the `]' must be a symbol name, and the | |
3189 | * register must be the toc register: 'rtoc' or '2' | |
3190 | * | |
3191 | * The effect is to 0 as the displacement field | |
3192 | * in the instruction, and issue an IMAGE_REL_PPC_TOCREL16 (or | |
3193 | * the appropriate variation) reloc against it based on the symbol. | |
3194 | * The linker will build the toc, and insert the resolved toc offset. | |
3195 | * | |
3196 | * Note: | |
3197 | * o The size of the toc entry is currently assumed to be | |
3198 | * 32 bits. This should not be assumed to be a hard coded | |
3199 | * number. | |
3200 | * o In an effort to cope with a change from 32 to 64 bits, | |
3201 | * there are also toc entries that are specified to be | |
3202 | * either 32 or 64 bits: | |
3203 | * lwz r4,[toc32].GS.0.static_int(rtoc) | |
3204 | * lwz r4,[toc64].GS.0.static_int(rtoc) | |
3205 | * These demand toc entries of the specified size, and the | |
3206 | * instruction probably requires it. | |
3207 | */ | |
252b5132 RH |
3208 | |
3209 | int valid_toc; | |
3210 | enum toc_size_qualifier toc_kind; | |
3211 | bfd_reloc_code_real_type toc_reloc; | |
3212 | ||
99a814a1 AM |
3213 | /* Go parse off the [tocXX] part. */ |
3214 | valid_toc = parse_toc_entry (&toc_kind); | |
252b5132 | 3215 | |
81d4177b | 3216 | if (!valid_toc) |
252b5132 | 3217 | { |
a5840dce AM |
3218 | ignore_rest_of_line (); |
3219 | break; | |
252b5132 RH |
3220 | } |
3221 | ||
99a814a1 AM |
3222 | /* Now get the symbol following the ']'. */ |
3223 | expression (&ex); | |
252b5132 RH |
3224 | |
3225 | switch (toc_kind) | |
3226 | { | |
3227 | case default_toc: | |
99a814a1 AM |
3228 | /* In this case, we may not have seen the symbol yet, |
3229 | since it is allowed to appear on a .extern or .globl | |
3230 | or just be a label in the .data section. */ | |
252b5132 RH |
3231 | toc_reloc = BFD_RELOC_PPC_TOC16; |
3232 | break; | |
3233 | case data_in_toc: | |
99a814a1 AM |
3234 | /* 1. The symbol must be defined and either in the toc |
3235 | section, or a global. | |
3236 | 2. The reloc generated must have the TOCDEFN flag set | |
3237 | in upper bit mess of the reloc type. | |
3238 | FIXME: It's a little confusing what the tocv | |
3239 | qualifier can be used for. At the very least, I've | |
3240 | seen three uses, only one of which I'm sure I can | |
3241 | explain. */ | |
81d4177b KH |
3242 | if (ex.X_op == O_symbol) |
3243 | { | |
9c2799c2 | 3244 | gas_assert (ex.X_add_symbol != NULL); |
fed9b18a ILT |
3245 | if (symbol_get_bfdsym (ex.X_add_symbol)->section |
3246 | != tocdata_section) | |
252b5132 | 3247 | { |
99a814a1 | 3248 | as_bad (_("[tocv] symbol is not a toc symbol")); |
252b5132 RH |
3249 | } |
3250 | } | |
3251 | ||
3252 | toc_reloc = BFD_RELOC_PPC_TOC16; | |
3253 | break; | |
3254 | case must_be_32: | |
99a814a1 AM |
3255 | /* FIXME: these next two specifically specify 32/64 bit |
3256 | toc entries. We don't support them today. Is this | |
3257 | the right way to say that? */ | |
62ebcb5c | 3258 | toc_reloc = BFD_RELOC_NONE; |
d6ed37ed | 3259 | as_bad (_("unimplemented toc32 expression modifier")); |
252b5132 RH |
3260 | break; |
3261 | case must_be_64: | |
99a814a1 | 3262 | /* FIXME: see above. */ |
62ebcb5c | 3263 | toc_reloc = BFD_RELOC_NONE; |
d6ed37ed | 3264 | as_bad (_("unimplemented toc64 expression modifier")); |
252b5132 RH |
3265 | break; |
3266 | default: | |
bc805888 | 3267 | fprintf (stderr, |
99a814a1 AM |
3268 | _("Unexpected return value [%d] from parse_toc_entry!\n"), |
3269 | toc_kind); | |
bc805888 | 3270 | abort (); |
252b5132 RH |
3271 | break; |
3272 | } | |
3273 | ||
3274 | /* We need to generate a fixup for this expression. */ | |
3275 | if (fc >= MAX_INSN_FIXUPS) | |
3276 | as_fatal (_("too many fixups")); | |
3277 | ||
3278 | fixups[fc].reloc = toc_reloc; | |
3279 | fixups[fc].exp = ex; | |
3280 | fixups[fc].opindex = *opindex_ptr; | |
3281 | ++fc; | |
3282 | ||
99a814a1 AM |
3283 | /* Ok. We've set up the fixup for the instruction. Now make it |
3284 | look like the constant 0 was found here. */ | |
252b5132 RH |
3285 | ex.X_unsigned = 1; |
3286 | ex.X_op = O_constant; | |
3287 | ex.X_add_number = 0; | |
3288 | ex.X_add_symbol = NULL; | |
3289 | ex.X_op_symbol = NULL; | |
3290 | } | |
3291 | ||
3292 | else | |
3293 | #endif /* TE_PE */ | |
3294 | { | |
b9c361e0 JL |
3295 | if ((reg_names_p |
3296 | && (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
3297 | || ((operand->flags & PPC_OPERAND_CR_REG) != 0))) | |
2ad068be | 3298 | || !register_name (&ex)) |
252b5132 | 3299 | { |
13abbae3 AM |
3300 | char save_lex = lex_type['%']; |
3301 | ||
b9c361e0 JL |
3302 | if (((operand->flags & PPC_OPERAND_CR_REG) != 0) |
3303 | || (operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
13abbae3 AM |
3304 | { |
3305 | cr_operand = TRUE; | |
3306 | lex_type['%'] |= LEX_BEGIN_NAME; | |
3307 | } | |
252b5132 | 3308 | expression (&ex); |
b34976b6 | 3309 | cr_operand = FALSE; |
13abbae3 | 3310 | lex_type['%'] = save_lex; |
252b5132 RH |
3311 | } |
3312 | } | |
3313 | ||
3314 | str = input_line_pointer; | |
3315 | input_line_pointer = hold; | |
3316 | ||
3317 | if (ex.X_op == O_illegal) | |
3318 | as_bad (_("illegal operand")); | |
3319 | else if (ex.X_op == O_absent) | |
3320 | as_bad (_("missing operand")); | |
3321 | else if (ex.X_op == O_register) | |
3322 | { | |
7e0de605 AM |
3323 | if ((ex.X_md |
3324 | & ~operand->flags | |
3325 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3326 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
3327 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR)) != 0 | |
3328 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 | |
3329 | && ex.X_add_number != 0 | |
3330 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3331 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3332 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3333 | ppc_cpu, (char *) NULL, 0); |
252b5132 RH |
3334 | } |
3335 | else if (ex.X_op == O_constant) | |
3336 | { | |
3337 | #ifdef OBJ_ELF | |
81d4177b | 3338 | /* Allow @HA, @L, @H on constants. */ |
3b8b57a9 | 3339 | bfd_reloc_code_real_type reloc; |
252b5132 RH |
3340 | char *orig_str = str; |
3341 | ||
62ebcb5c | 3342 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
252b5132 RH |
3343 | switch (reloc) |
3344 | { | |
3345 | default: | |
3346 | str = orig_str; | |
3347 | break; | |
3348 | ||
3349 | case BFD_RELOC_LO16: | |
f9c6b907 AM |
3350 | ex.X_add_number &= 0xffff; |
3351 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
0baf16f2 | 3352 | ex.X_add_number = SEX16 (ex.X_add_number); |
252b5132 RH |
3353 | break; |
3354 | ||
3355 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3356 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3357 | { | |
3358 | /* PowerPC64 @h is tested for overflow. */ | |
3359 | ex.X_add_number = (addressT) ex.X_add_number >> 16; | |
3360 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3361 | { | |
3362 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3363 | ex.X_add_number | |
3364 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3365 | } | |
3366 | break; | |
3367 | } | |
2b0f3761 | 3368 | /* Fallthru */ |
f9c6b907 AM |
3369 | |
3370 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3371 | ex.X_add_number = PPC_HI (ex.X_add_number); | |
3372 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3373 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 RH |
3374 | break; |
3375 | ||
3376 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3377 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3378 | { | |
3379 | /* PowerPC64 @ha is tested for overflow. */ | |
3380 | ex.X_add_number | |
3381 | = ((addressT) ex.X_add_number + 0x8000) >> 16; | |
3382 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3383 | { | |
3384 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3385 | ex.X_add_number | |
3386 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3387 | } | |
3388 | break; | |
3389 | } | |
2b0f3761 | 3390 | /* Fallthru */ |
f9c6b907 AM |
3391 | |
3392 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
3393 | ex.X_add_number = PPC_HA (ex.X_add_number); | |
3394 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3395 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3396 | break; |
3397 | ||
0baf16f2 | 3398 | case BFD_RELOC_PPC64_HIGHER: |
f9c6b907 AM |
3399 | ex.X_add_number = PPC_HIGHER (ex.X_add_number); |
3400 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3401 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3402 | break; |
3403 | ||
3404 | case BFD_RELOC_PPC64_HIGHER_S: | |
f9c6b907 AM |
3405 | ex.X_add_number = PPC_HIGHERA (ex.X_add_number); |
3406 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3407 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 | 3408 | break; |
0baf16f2 AM |
3409 | |
3410 | case BFD_RELOC_PPC64_HIGHEST: | |
f9c6b907 AM |
3411 | ex.X_add_number = PPC_HIGHEST (ex.X_add_number); |
3412 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3413 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3414 | break; |
3415 | ||
3416 | case BFD_RELOC_PPC64_HIGHEST_S: | |
f9c6b907 AM |
3417 | ex.X_add_number = PPC_HIGHESTA (ex.X_add_number); |
3418 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3419 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 | 3420 | break; |
252b5132 | 3421 | } |
0baf16f2 | 3422 | #endif /* OBJ_ELF */ |
252b5132 | 3423 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3424 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3425 | } |
727fc41e | 3426 | else |
252b5132 | 3427 | { |
62ebcb5c | 3428 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3429 | #ifdef OBJ_ELF |
160eba93 AM |
3430 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3431 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3432 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3433 | { |
160eba93 AM |
3434 | fixups[fc].opindex = *opindex_ptr; |
3435 | ++fc; | |
252b5132 RH |
3436 | } |
3437 | ||
62ebcb5c | 3438 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3439 | { |
b9c361e0 JL |
3440 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3441 | if (opcode->flags & PPC_OPCODE_VLE) | |
3442 | { | |
0f873fd5 | 3443 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3444 | |
08dc996f | 3445 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3446 | || tmp_insn == E_AND2I_DOT_INSN |
3447 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3448 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3449 | || tmp_insn == E_LIS_INSN |
3450 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3451 | ||
3452 | ||
08dc996f | 3453 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3454 | || tmp_insn == E_ADD2IS_INSN |
3455 | || tmp_insn == E_CMP16I_INSN | |
3456 | || tmp_insn == E_MULL2I_INSN | |
3457 | || tmp_insn == E_CMPL16I_INSN | |
3458 | || tmp_insn == E_CMPH16I_INSN | |
3459 | || tmp_insn == E_CMPHL16I_INSN); | |
3460 | ||
3461 | switch (reloc) | |
3462 | { | |
3463 | default: | |
3464 | break; | |
3465 | ||
3466 | case BFD_RELOC_PPC_EMB_SDA21: | |
3467 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3468 | break; | |
3469 | ||
3470 | case BFD_RELOC_LO16: | |
3471 | if (use_d_reloc) | |
3472 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3473 | else if (use_a_reloc) | |
3474 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3475 | break; | |
3476 | ||
3477 | case BFD_RELOC_HI16: | |
3478 | if (use_d_reloc) | |
3479 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3480 | else if (use_a_reloc) | |
3481 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3482 | break; | |
3739860c | 3483 | |
b9c361e0 JL |
3484 | case BFD_RELOC_HI16_S: |
3485 | if (use_d_reloc) | |
3486 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3487 | else if (use_a_reloc) | |
3488 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3489 | break; | |
3490 | ||
3491 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3492 | if (use_d_reloc) | |
3493 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3494 | break; | |
3495 | ||
3496 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3497 | if (use_d_reloc) | |
3498 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3499 | break; | |
3500 | ||
3501 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3502 | if (use_d_reloc) | |
3503 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3504 | break; | |
3505 | } | |
3506 | } | |
bb6bf75e AM |
3507 | |
3508 | /* TLS and other tweaks. */ | |
3509 | switch (reloc) | |
3510 | { | |
3511 | default: | |
3512 | break; | |
3513 | ||
3514 | case BFD_RELOC_PPC_TLS: | |
3515 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) | |
3516 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3517 | opcode->name); | |
3518 | else if (operand->shift != 11) | |
3519 | as_bad (_("@tls may only be used in last operand")); | |
3520 | else | |
3521 | insn = ppc_insert_operand (insn, operand, | |
3522 | ppc_obj64 ? 13 : 2, | |
3523 | ppc_cpu, (char *) NULL, 0); | |
3524 | break; | |
3525 | ||
3526 | /* We'll only use the 32 (or 64) bit form of these relocations | |
3527 | in constants. Instructions get the 16 bit form. */ | |
3528 | case BFD_RELOC_PPC_DTPREL: | |
3529 | reloc = BFD_RELOC_PPC_DTPREL16; | |
3530 | break; | |
3531 | ||
3532 | case BFD_RELOC_PPC_TPREL: | |
3533 | reloc = BFD_RELOC_PPC_TPREL16; | |
3534 | break; | |
3535 | ||
3536 | case BFD_RELOC_LO16: | |
3537 | if ((operand->bitm | 0xf) != 0xffff | |
3538 | || operand->shift != 0 | |
3539 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3540 | as_warn (_("%s unsupported on this instruction"), "@l"); | |
3541 | break; | |
3542 | ||
3543 | case BFD_RELOC_HI16: | |
3544 | if (operand->bitm != 0xffff | |
3545 | || operand->shift != 0 | |
3546 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3547 | as_warn (_("%s unsupported on this instruction"), "@h"); | |
3548 | break; | |
3549 | ||
3550 | case BFD_RELOC_HI16_S: | |
3551 | if (operand->bitm == 0xffff | |
3552 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3553 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
3554 | /* addpcis. */ | |
3555 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3556 | else if (operand->bitm != 0xffff | |
3557 | || operand->shift != 0 | |
3558 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3559 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3560 | } | |
0baf16f2 | 3561 | } |
3b8b57a9 AM |
3562 | #endif /* OBJ_ELF */ |
3563 | ||
62ebcb5c | 3564 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3565 | ; |
3566 | /* Determine a BFD reloc value based on the operand information. | |
3567 | We are only prepared to turn a few of the operands into | |
3568 | relocs. */ | |
a0593ad9 AM |
3569 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3570 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3571 | && operand->bitm == 0x3fffffc |
3572 | && operand->shift == 0) | |
3573 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3574 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3575 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3576 | && operand->bitm == 0xfffc |
3577 | && operand->shift == 0) | |
3578 | reloc = BFD_RELOC_PPC_B16; | |
3579 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3580 | && operand->bitm == 0x1fe | |
3581 | && operand->shift == -1) | |
3582 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3583 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3584 | && operand->bitm == 0xfffe | |
3585 | && operand->shift == 0) | |
3586 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3587 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3588 | && operand->bitm == 0x1fffffe | |
3589 | && operand->shift == 0) | |
3590 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3591 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3592 | && (operand->bitm & 0xfff0) == 0xfff0 |
3593 | && operand->shift == 0) | |
3594 | { | |
f50c47f1 | 3595 | reloc = BFD_RELOC_16; |
3e60bf4d | 3596 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3597 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3598 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3599 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3600 | { |
3601 | reloc = BFD_RELOC_PPC_TOC16; | |
3602 | #ifdef OBJ_ELF | |
3603 | as_warn (_("assuming %s on symbol"), | |
3604 | ppc_obj64 ? "@toc" : "@xgot"); | |
3605 | #endif | |
3606 | } | |
3b8b57a9 | 3607 | #endif |
3b8b57a9 | 3608 | } |
a0593ad9 AM |
3609 | |
3610 | /* For the absolute forms of branches, convert the PC | |
3611 | relative form back into the absolute. */ | |
3612 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3613 | { | |
3614 | switch (reloc) | |
3615 | { | |
3616 | case BFD_RELOC_PPC_B26: | |
3617 | reloc = BFD_RELOC_PPC_BA26; | |
3618 | break; | |
3619 | case BFD_RELOC_PPC_B16: | |
3620 | reloc = BFD_RELOC_PPC_BA16; | |
3621 | break; | |
3622 | #ifdef OBJ_ELF | |
3623 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3624 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3625 | break; | |
3626 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3627 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3628 | break; | |
3629 | #endif | |
3630 | default: | |
3631 | break; | |
3632 | } | |
3633 | } | |
3634 | ||
3635 | #ifdef OBJ_ELF | |
3636 | switch (reloc) | |
3637 | { | |
3638 | case BFD_RELOC_PPC_TOC16: | |
3639 | toc_reloc_types |= has_small_toc_reloc; | |
3640 | break; | |
3641 | case BFD_RELOC_PPC64_TOC16_LO: | |
3642 | case BFD_RELOC_PPC64_TOC16_HI: | |
3643 | case BFD_RELOC_PPC64_TOC16_HA: | |
3644 | toc_reloc_types |= has_large_toc_reloc; | |
3645 | break; | |
3646 | default: | |
3647 | break; | |
3648 | } | |
3649 | ||
3650 | if (ppc_obj64 | |
3651 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3652 | { | |
3653 | switch (reloc) | |
3654 | { | |
3655 | case BFD_RELOC_16: | |
3656 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3657 | break; | |
3658 | case BFD_RELOC_LO16: | |
3659 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3660 | break; | |
3661 | case BFD_RELOC_16_GOTOFF: | |
3662 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3663 | break; | |
3664 | case BFD_RELOC_LO16_GOTOFF: | |
3665 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3666 | break; | |
3667 | case BFD_RELOC_LO16_PLTOFF: | |
3668 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3669 | break; | |
3670 | case BFD_RELOC_16_BASEREL: | |
3671 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3672 | break; | |
3673 | case BFD_RELOC_LO16_BASEREL: | |
3674 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3675 | break; | |
3676 | case BFD_RELOC_PPC_TOC16: | |
3677 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3678 | break; | |
3679 | case BFD_RELOC_PPC64_TOC16_LO: | |
3680 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3681 | break; | |
3682 | case BFD_RELOC_PPC64_PLTGOT16: | |
3683 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3684 | break; | |
3685 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
3686 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3687 | break; | |
3688 | case BFD_RELOC_PPC_DTPREL16: | |
3689 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3690 | break; | |
3691 | case BFD_RELOC_PPC_DTPREL16_LO: | |
3692 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
3693 | break; | |
3694 | case BFD_RELOC_PPC_TPREL16: | |
3695 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
3696 | break; | |
3697 | case BFD_RELOC_PPC_TPREL16_LO: | |
3698 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
3699 | break; | |
3700 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
3701 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3702 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3703 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3704 | break; | |
3705 | default: | |
3706 | as_bad (_("unsupported relocation for DS offset field")); | |
3707 | break; | |
3708 | } | |
3709 | } | |
160eba93 AM |
3710 | |
3711 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
3712 | modifiers like @plt. This fixup must be emitted before | |
3713 | the usual call fixup. */ | |
3714 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3715 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
3716 | { | |
3717 | fixups[fc].opindex = *opindex_ptr; | |
3718 | ++fc; | |
3719 | } | |
a0593ad9 | 3720 | #endif |
0baf16f2 | 3721 | |
252b5132 RH |
3722 | /* We need to generate a fixup for this expression. */ |
3723 | if (fc >= MAX_INSN_FIXUPS) | |
3724 | as_fatal (_("too many fixups")); | |
3725 | fixups[fc].exp = ex; | |
727fc41e | 3726 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
3727 | fixups[fc].reloc = reloc; |
3728 | ++fc; | |
3729 | } | |
252b5132 RH |
3730 | |
3731 | if (need_paren) | |
3732 | { | |
3733 | endc = ')'; | |
3734 | need_paren = 0; | |
c3d65c1c BE |
3735 | /* If expecting more operands, then we want to see "),". */ |
3736 | if (*str == endc && opindex_ptr[1] != 0) | |
3737 | { | |
3738 | do | |
3739 | ++str; | |
3740 | while (ISSPACE (*str)); | |
3741 | endc = ','; | |
3742 | } | |
252b5132 RH |
3743 | } |
3744 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 3745 | endc = '('; |
252b5132 RH |
3746 | else |
3747 | endc = ','; | |
3748 | ||
3749 | /* The call to expression should have advanced str past any | |
3750 | whitespace. */ | |
9cf7e568 | 3751 | if (*str == endc) |
252b5132 | 3752 | { |
9cf7e568 AM |
3753 | ++str; |
3754 | if (endc == '(') | |
3755 | need_paren = 1; | |
3756 | } | |
3757 | else if (*str != '\0') | |
3758 | { | |
3759 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
3760 | break; | |
3761 | } | |
3762 | else if (endc == ')') | |
3763 | { | |
3764 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
3765 | break; |
3766 | } | |
252b5132 RH |
3767 | } |
3768 | ||
3882b010 | 3769 | while (ISSPACE (*str)) |
252b5132 RH |
3770 | ++str; |
3771 | ||
3772 | if (*str != '\0') | |
3773 | as_bad (_("junk at end of line: `%s'"), str); | |
3774 | ||
dc1d03fc | 3775 | #ifdef OBJ_ELF |
b9c361e0 | 3776 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
3777 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
3778 | && !ppc_obj64) | |
6a0c61b7 EZ |
3779 | { |
3780 | /* These are all version "1". */ | |
3781 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 3782 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 3783 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 3784 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 3785 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 3786 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 3787 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 3788 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 3789 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 3790 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 3791 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 3792 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 3793 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 3794 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
3795 | /* Only set the VLE flag if the instruction has been pulled via |
3796 | the VLE instruction set. This way the flag is guaranteed to | |
3797 | be set for VLE-only instructions or for VLE-only processors, | |
3798 | however it'll remain clear for dual-mode instructions on | |
3799 | dual-mode and, more importantly, standard-mode processors. */ | |
3800 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
3801 | { |
3802 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
3803 | if (elf_section_data (now_seg) != NULL) | |
3804 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
3805 | } | |
6a0c61b7 | 3806 | } |
dc1d03fc | 3807 | #endif |
6a0c61b7 | 3808 | |
252b5132 | 3809 | /* Write out the instruction. */ |
a9479dc0 AM |
3810 | |
3811 | addr_mask = 3; | |
f7d69005 | 3812 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
3813 | /* All instructions can start on a 2 byte boundary for VLE. */ |
3814 | addr_mask = 1; | |
3815 | ||
3816 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 3817 | { |
a9479dc0 AM |
3818 | /* Don't emit instructions to a frag started for data, or for a |
3819 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
3820 | and it's possible to start a new frag in the middle of | |
3821 | misaligned data. */ | |
3822 | frag_wane (frag_now); | |
3823 | frag_new (0); | |
b9c361e0 | 3824 | } |
a9479dc0 AM |
3825 | |
3826 | /* Check that insns within the frag are aligned. ppc_frag_check | |
3827 | will ensure that the frag start address is aligned. */ | |
3828 | if ((frag_now_fix () & addr_mask) != 0) | |
3829 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
3830 | ||
3831 | /* Differentiate between two and four byte insns. */ | |
3832 | insn_length = 4; | |
3833 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
3834 | insn_length = 2; | |
3835 | ||
b9c361e0 | 3836 | f = frag_more (insn_length); |
a9479dc0 | 3837 | frag_now->insn_addr = addr_mask; |
b9c361e0 | 3838 | md_number_to_chars (f, insn, insn_length); |
bf7279d5 AM |
3839 | last_insn = insn; |
3840 | last_seg = now_seg; | |
3841 | last_subseg = now_subseg; | |
252b5132 | 3842 | |
5d6f4f16 | 3843 | #ifdef OBJ_ELF |
b9c361e0 | 3844 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
3845 | #endif |
3846 | ||
3b8b57a9 | 3847 | /* Create any fixups. */ |
252b5132 RH |
3848 | for (i = 0; i < fc; i++) |
3849 | { | |
3b8b57a9 | 3850 | fixS *fixP; |
62ebcb5c | 3851 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 3852 | { |
0e2779e9 AM |
3853 | bfd_boolean pcrel; |
3854 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); | |
3855 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 3856 | |
99a814a1 AM |
3857 | fixP = fix_new_exp (frag_now, |
3858 | f - frag_now->fr_literal + offset, | |
3859 | size, | |
3860 | &fixups[i].exp, | |
0e2779e9 | 3861 | pcrel, |
252b5132 | 3862 | fixups[i].reloc); |
252b5132 RH |
3863 | } |
3864 | else | |
727fc41e AM |
3865 | { |
3866 | const struct powerpc_operand *operand; | |
3867 | ||
3868 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
3869 | fixP = fix_new_exp (frag_now, |
3870 | f - frag_now->fr_literal, | |
3871 | insn_length, | |
3872 | &fixups[i].exp, | |
3873 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 3874 | BFD_RELOC_NONE); |
727fc41e | 3875 | } |
3b8b57a9 | 3876 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
3877 | } |
3878 | } | |
3879 | ||
3880 | /* Handle a macro. Gather all the operands, transform them as | |
3881 | described by the macro, and call md_assemble recursively. All the | |
3882 | operands are separated by commas; we don't accept parentheses | |
3883 | around operands here. */ | |
3884 | ||
3885 | static void | |
98027b10 | 3886 | ppc_macro (char *str, const struct powerpc_macro *macro) |
252b5132 RH |
3887 | { |
3888 | char *operands[10]; | |
3889 | unsigned int count; | |
3890 | char *s; | |
3891 | unsigned int len; | |
3892 | const char *format; | |
db557034 | 3893 | unsigned int arg; |
252b5132 RH |
3894 | char *send; |
3895 | char *complete; | |
3896 | ||
3897 | /* Gather the users operands into the operands array. */ | |
3898 | count = 0; | |
3899 | s = str; | |
3900 | while (1) | |
3901 | { | |
3902 | if (count >= sizeof operands / sizeof operands[0]) | |
3903 | break; | |
3904 | operands[count++] = s; | |
3905 | s = strchr (s, ','); | |
3906 | if (s == (char *) NULL) | |
3907 | break; | |
3908 | *s++ = '\0'; | |
81d4177b | 3909 | } |
252b5132 RH |
3910 | |
3911 | if (count != macro->operands) | |
3912 | { | |
3913 | as_bad (_("wrong number of operands")); | |
3914 | return; | |
3915 | } | |
3916 | ||
3917 | /* Work out how large the string must be (the size is unbounded | |
3918 | because it includes user input). */ | |
3919 | len = 0; | |
3920 | format = macro->format; | |
3921 | while (*format != '\0') | |
3922 | { | |
3923 | if (*format != '%') | |
3924 | { | |
3925 | ++len; | |
3926 | ++format; | |
3927 | } | |
3928 | else | |
3929 | { | |
3930 | arg = strtol (format + 1, &send, 10); | |
db557034 | 3931 | know (send != format && arg < count); |
252b5132 RH |
3932 | len += strlen (operands[arg]); |
3933 | format = send; | |
3934 | } | |
3935 | } | |
3936 | ||
3937 | /* Put the string together. */ | |
325801bd | 3938 | complete = s = XNEWVEC (char, len + 1); |
252b5132 RH |
3939 | format = macro->format; |
3940 | while (*format != '\0') | |
3941 | { | |
3942 | if (*format != '%') | |
3943 | *s++ = *format++; | |
3944 | else | |
3945 | { | |
3946 | arg = strtol (format + 1, &send, 10); | |
3947 | strcpy (s, operands[arg]); | |
3948 | s += strlen (s); | |
3949 | format = send; | |
3950 | } | |
3951 | } | |
3952 | *s = '\0'; | |
3953 | ||
3954 | /* Assemble the constructed instruction. */ | |
3955 | md_assemble (complete); | |
e1fa0163 | 3956 | free (complete); |
81d4177b | 3957 | } |
252b5132 RH |
3958 | \f |
3959 | #ifdef OBJ_ELF | |
18ae9cc1 | 3960 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
3961 | |
3962 | int | |
98027b10 | 3963 | ppc_section_type (char *str, size_t len) |
252b5132 | 3964 | { |
9de8d8f1 RH |
3965 | if (len == 7 && strncmp (str, "ordered", 7) == 0) |
3966 | return SHT_ORDERED; | |
252b5132 | 3967 | |
9de8d8f1 | 3968 | return -1; |
252b5132 RH |
3969 | } |
3970 | ||
3971 | int | |
1239de13 | 3972 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
3973 | { |
3974 | if (type == SHT_ORDERED) | |
3975 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
3976 | ||
252b5132 RH |
3977 | return flags; |
3978 | } | |
83eef883 AFB |
3979 | |
3980 | bfd_vma | |
3981 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
3982 | { | |
3983 | if (letter == 'v') | |
3984 | return SHF_PPC_VLE; | |
3985 | ||
3986 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
3987 | return -1; | |
3988 | } | |
252b5132 RH |
3989 | #endif /* OBJ_ELF */ |
3990 | ||
3991 | \f | |
3992 | /* Pseudo-op handling. */ | |
3993 | ||
3994 | /* The .byte pseudo-op. This is similar to the normal .byte | |
3995 | pseudo-op, but it can also take a single ASCII string. */ | |
3996 | ||
3997 | static void | |
98027b10 | 3998 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 3999 | { |
bf7279d5 AM |
4000 | int count = 0; |
4001 | ||
252b5132 RH |
4002 | if (*input_line_pointer != '\"') |
4003 | { | |
4004 | cons (1); | |
4005 | return; | |
4006 | } | |
4007 | ||
4008 | /* Gather characters. A real double quote is doubled. Unusual | |
4009 | characters are not permitted. */ | |
4010 | ++input_line_pointer; | |
4011 | while (1) | |
4012 | { | |
4013 | char c; | |
4014 | ||
4015 | c = *input_line_pointer++; | |
4016 | ||
4017 | if (c == '\"') | |
4018 | { | |
4019 | if (*input_line_pointer != '\"') | |
4020 | break; | |
4021 | ++input_line_pointer; | |
4022 | } | |
4023 | ||
4024 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4025 | ++count; |
252b5132 RH |
4026 | } |
4027 | ||
bf7279d5 AM |
4028 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4029 | as_warn (_("data in executable section")); | |
252b5132 RH |
4030 | demand_empty_rest_of_line (); |
4031 | } | |
4032 | \f | |
4033 | #ifdef OBJ_XCOFF | |
4034 | ||
4035 | /* XCOFF specific pseudo-op handling. */ | |
4036 | ||
4037 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4038 | to handle symbol suffixes for such symbols. */ | |
b34976b6 | 4039 | static bfd_boolean ppc_stab_symbol; |
252b5132 RH |
4040 | |
4041 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common | |
4042 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4043 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1ad63b2f | 4044 | aligns .comm and .lcomm to 4 bytes. */ |
252b5132 RH |
4045 | |
4046 | static void | |
98027b10 | 4047 | ppc_comm (int lcomm) |
252b5132 RH |
4048 | { |
4049 | asection *current_seg = now_seg; | |
4050 | subsegT current_subseg = now_subseg; | |
4051 | char *name; | |
4052 | char endc; | |
4053 | char *end_name; | |
4054 | offsetT size; | |
4055 | offsetT align; | |
4056 | symbolS *lcomm_sym = NULL; | |
4057 | symbolS *sym; | |
4058 | char *pfrag; | |
4059 | ||
d02603dc | 4060 | endc = get_symbol_name (&name); |
252b5132 | 4061 | end_name = input_line_pointer; |
d02603dc | 4062 | (void) restore_line_pointer (endc); |
252b5132 RH |
4063 | |
4064 | if (*input_line_pointer != ',') | |
4065 | { | |
4066 | as_bad (_("missing size")); | |
4067 | ignore_rest_of_line (); | |
4068 | return; | |
4069 | } | |
4070 | ++input_line_pointer; | |
4071 | ||
4072 | size = get_absolute_expression (); | |
4073 | if (size < 0) | |
4074 | { | |
4075 | as_bad (_("negative size")); | |
4076 | ignore_rest_of_line (); | |
4077 | return; | |
4078 | } | |
4079 | ||
4080 | if (! lcomm) | |
4081 | { | |
4082 | /* The third argument to .comm is the alignment. */ | |
4083 | if (*input_line_pointer != ',') | |
1ad63b2f | 4084 | align = 2; |
252b5132 RH |
4085 | else |
4086 | { | |
4087 | ++input_line_pointer; | |
4088 | align = get_absolute_expression (); | |
4089 | if (align <= 0) | |
4090 | { | |
4091 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4092 | align = 2; |
252b5132 RH |
4093 | } |
4094 | } | |
4095 | } | |
4096 | else | |
4097 | { | |
4098 | char *lcomm_name; | |
4099 | char lcomm_endc; | |
4100 | ||
252b5132 RH |
4101 | /* The third argument to .lcomm appears to be the real local |
4102 | common symbol to create. References to the symbol named in | |
4103 | the first argument are turned into references to the third | |
4104 | argument. */ | |
4105 | if (*input_line_pointer != ',') | |
4106 | { | |
4107 | as_bad (_("missing real symbol name")); | |
4108 | ignore_rest_of_line (); | |
4109 | return; | |
4110 | } | |
4111 | ++input_line_pointer; | |
4112 | ||
d02603dc | 4113 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4114 | |
252b5132 RH |
4115 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4116 | ||
d02603dc | 4117 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4118 | |
4119 | /* The fourth argument to .lcomm is the alignment. */ | |
4120 | if (*input_line_pointer != ',') | |
4121 | { | |
4122 | if (size <= 4) | |
4123 | align = 2; | |
4124 | else | |
4125 | align = 3; | |
4126 | } | |
4127 | else | |
4128 | { | |
4129 | ++input_line_pointer; | |
4130 | align = get_absolute_expression (); | |
4131 | if (align <= 0) | |
4132 | { | |
4133 | as_warn (_("ignoring bad alignment")); | |
4134 | align = 2; | |
4135 | } | |
4136 | } | |
252b5132 RH |
4137 | } |
4138 | ||
4139 | *end_name = '\0'; | |
4140 | sym = symbol_find_or_make (name); | |
4141 | *end_name = endc; | |
4142 | ||
4143 | if (S_IS_DEFINED (sym) | |
4144 | || S_GET_VALUE (sym) != 0) | |
4145 | { | |
4146 | as_bad (_("attempt to redefine symbol")); | |
4147 | ignore_rest_of_line (); | |
4148 | return; | |
4149 | } | |
81d4177b | 4150 | |
252b5132 | 4151 | record_alignment (bss_section, align); |
81d4177b | 4152 | |
252b5132 RH |
4153 | if (! lcomm |
4154 | || ! S_IS_DEFINED (lcomm_sym)) | |
4155 | { | |
4156 | symbolS *def_sym; | |
4157 | offsetT def_size; | |
4158 | ||
4159 | if (! lcomm) | |
4160 | { | |
4161 | def_sym = sym; | |
4162 | def_size = size; | |
4163 | S_SET_EXTERNAL (sym); | |
4164 | } | |
4165 | else | |
4166 | { | |
809ffe0d | 4167 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4168 | def_sym = lcomm_sym; |
4169 | def_size = 0; | |
4170 | } | |
4171 | ||
4172 | subseg_set (bss_section, 1); | |
4173 | frag_align (align, 0, 0); | |
81d4177b | 4174 | |
809ffe0d | 4175 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4176 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4177 | def_size, (char *) NULL); | |
4178 | *pfrag = 0; | |
4179 | S_SET_SEGMENT (def_sym, bss_section); | |
809ffe0d | 4180 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4181 | } |
4182 | else if (lcomm) | |
4183 | { | |
4184 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4185 | symbol_get_frag (lcomm_sym)->fr_offset = |
4186 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4187 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4188 | if (align > symbol_get_tc (lcomm_sym)->align) |
4189 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4190 | } |
4191 | ||
4192 | if (lcomm) | |
4193 | { | |
4194 | /* Make sym an offset from lcomm_sym. */ | |
4195 | S_SET_SEGMENT (sym, bss_section); | |
809ffe0d ILT |
4196 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4197 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4198 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4199 | } |
4200 | ||
4201 | subseg_set (current_seg, current_subseg); | |
4202 | ||
4203 | demand_empty_rest_of_line (); | |
4204 | } | |
4205 | ||
4206 | /* The .csect pseudo-op. This switches us into a different | |
4207 | subsegment. The first argument is a symbol whose value is the | |
4208 | start of the .csect. In COFF, csect symbols get special aux | |
4209 | entries defined by the x_csect field of union internal_auxent. The | |
4210 | optional second argument is the alignment (the default is 2). */ | |
4211 | ||
4212 | static void | |
98027b10 | 4213 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4214 | { |
4215 | char *name; | |
4216 | char endc; | |
4217 | symbolS *sym; | |
931e13a6 | 4218 | offsetT align; |
252b5132 | 4219 | |
d02603dc | 4220 | endc = get_symbol_name (&name); |
81d4177b | 4221 | |
252b5132 RH |
4222 | sym = symbol_find_or_make (name); |
4223 | ||
d02603dc | 4224 | (void) restore_line_pointer (endc); |
252b5132 RH |
4225 | |
4226 | if (S_GET_NAME (sym)[0] == '\0') | |
4227 | { | |
4228 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4229 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4230 | } |
4231 | ||
931e13a6 | 4232 | align = 2; |
252b5132 RH |
4233 | if (*input_line_pointer == ',') |
4234 | { | |
4235 | ++input_line_pointer; | |
931e13a6 | 4236 | align = get_absolute_expression (); |
252b5132 RH |
4237 | } |
4238 | ||
931e13a6 AM |
4239 | ppc_change_csect (sym, align); |
4240 | ||
252b5132 RH |
4241 | demand_empty_rest_of_line (); |
4242 | } | |
4243 | ||
4244 | /* Change to a different csect. */ | |
4245 | ||
4246 | static void | |
98027b10 | 4247 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4248 | { |
4249 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4250 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4251 | else |
4252 | { | |
4253 | symbolS **list_ptr; | |
4254 | int after_toc; | |
4255 | int hold_chunksize; | |
4256 | symbolS *list; | |
931e13a6 AM |
4257 | int is_code; |
4258 | segT sec; | |
252b5132 RH |
4259 | |
4260 | /* This is a new csect. We need to look at the symbol class to | |
4261 | figure out whether it should go in the text section or the | |
4262 | data section. */ | |
4263 | after_toc = 0; | |
931e13a6 | 4264 | is_code = 0; |
96d56e9f | 4265 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4266 | { |
4267 | case XMC_PR: | |
4268 | case XMC_RO: | |
4269 | case XMC_DB: | |
4270 | case XMC_GL: | |
4271 | case XMC_XO: | |
4272 | case XMC_SV: | |
4273 | case XMC_TI: | |
4274 | case XMC_TB: | |
4275 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4276 | symbol_get_tc (sym)->subseg = ppc_text_subsegment; |
252b5132 RH |
4277 | ++ppc_text_subsegment; |
4278 | list_ptr = &ppc_text_csects; | |
931e13a6 | 4279 | is_code = 1; |
252b5132 RH |
4280 | break; |
4281 | case XMC_RW: | |
4282 | case XMC_TC0: | |
4283 | case XMC_TC: | |
4284 | case XMC_DS: | |
4285 | case XMC_UA: | |
4286 | case XMC_BS: | |
4287 | case XMC_UC: | |
4288 | if (ppc_toc_csect != NULL | |
809ffe0d ILT |
4289 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
4290 | == ppc_data_subsegment)) | |
252b5132 RH |
4291 | after_toc = 1; |
4292 | S_SET_SEGMENT (sym, data_section); | |
809ffe0d | 4293 | symbol_get_tc (sym)->subseg = ppc_data_subsegment; |
252b5132 RH |
4294 | ++ppc_data_subsegment; |
4295 | list_ptr = &ppc_data_csects; | |
4296 | break; | |
4297 | default: | |
4298 | abort (); | |
4299 | } | |
4300 | ||
4301 | /* We set the obstack chunk size to a small value before | |
99a814a1 AM |
4302 | changing subsegments, so that we don't use a lot of memory |
4303 | space for what may be a small section. */ | |
252b5132 RH |
4304 | hold_chunksize = chunksize; |
4305 | chunksize = 64; | |
4306 | ||
931e13a6 AM |
4307 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4308 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4309 | |
4310 | chunksize = hold_chunksize; | |
4311 | ||
4312 | if (after_toc) | |
4313 | ppc_after_toc_frag = frag_now; | |
4314 | ||
931e13a6 AM |
4315 | record_alignment (sec, align); |
4316 | if (is_code) | |
4317 | frag_align_code (align, 0); | |
4318 | else | |
4319 | frag_align (align, 0, 0); | |
4320 | ||
809ffe0d | 4321 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4322 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4323 | ||
931e13a6 | 4324 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4325 | symbol_get_tc (sym)->output = 1; |
4326 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4327 | |
252b5132 | 4328 | for (list = *list_ptr; |
809ffe0d ILT |
4329 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4330 | list = symbol_get_tc (list)->next) | |
252b5132 | 4331 | ; |
809ffe0d | 4332 | symbol_get_tc (list)->next = sym; |
81d4177b | 4333 | |
252b5132 | 4334 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4335 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4336 | &symbol_lastP); | |
252b5132 RH |
4337 | } |
4338 | ||
4339 | ppc_current_csect = sym; | |
4340 | } | |
4341 | ||
85645aed TG |
4342 | static void |
4343 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4344 | { | |
4345 | segT sec; | |
4346 | flagword oldflags; | |
4347 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4348 | ||
4349 | sec = subseg_new (dw->name, subseg); | |
4350 | oldflags = bfd_get_section_flags (stdoutput, sec); | |
4351 | if (oldflags == SEC_NO_FLAGS) | |
4352 | { | |
4353 | /* Just created section. */ | |
4354 | gas_assert (dw_sections[idx].sect == NULL); | |
4355 | ||
4356 | bfd_set_section_flags (stdoutput, sec, SEC_DEBUGGING); | |
4357 | bfd_set_section_alignment (stdoutput, sec, 0); | |
4358 | dw_sections[idx].sect = sec; | |
4359 | } | |
4360 | ||
4361 | /* Not anymore in a csect. */ | |
4362 | ppc_current_csect = NULL; | |
4363 | } | |
4364 | ||
4365 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4366 | .dwsect flag [, opt-label ] | |
4367 | */ | |
4368 | ||
4369 | static void | |
4370 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4371 | { | |
16de26a6 | 4372 | valueT flag; |
85645aed TG |
4373 | symbolS *opt_label; |
4374 | const struct xcoff_dwsect_name *dw; | |
4375 | struct dw_subsection *subseg; | |
4376 | struct dw_section *dws; | |
4377 | int i; | |
4378 | ||
4379 | /* Find section. */ | |
4380 | flag = get_absolute_expression (); | |
4381 | dw = NULL; | |
4382 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4383 | if (xcoff_dwsect_names[i].flag == flag) | |
4384 | { | |
4385 | dw = &xcoff_dwsect_names[i]; | |
4386 | break; | |
4387 | } | |
4388 | ||
4389 | /* Parse opt-label. */ | |
4390 | if (*input_line_pointer == ',') | |
4391 | { | |
d02603dc | 4392 | char *label; |
85645aed TG |
4393 | char c; |
4394 | ||
4395 | ++input_line_pointer; | |
4396 | ||
d02603dc | 4397 | c = get_symbol_name (&label); |
85645aed | 4398 | opt_label = symbol_find_or_make (label); |
d02603dc | 4399 | (void) restore_line_pointer (c); |
85645aed TG |
4400 | } |
4401 | else | |
4402 | opt_label = NULL; | |
4403 | ||
4404 | demand_empty_rest_of_line (); | |
4405 | ||
4406 | /* Return now in case of unknown subsection. */ | |
4407 | if (dw == NULL) | |
4408 | { | |
d6ed37ed | 4409 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4410 | (unsigned)flag); |
4411 | return; | |
4412 | } | |
4413 | ||
4414 | /* Find the subsection. */ | |
4415 | dws = &dw_sections[i]; | |
4416 | subseg = NULL; | |
4417 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4418 | { | |
4419 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4420 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4421 | { | |
4422 | as_bad (_("label %s was not defined in this dwarf section"), | |
4423 | S_GET_NAME (opt_label)); | |
4424 | subseg = dws->anon_subseg; | |
4425 | opt_label = NULL; | |
4426 | } | |
4427 | else | |
4428 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4429 | } | |
4430 | ||
4431 | if (subseg != NULL) | |
4432 | { | |
4433 | /* Switch to the subsection. */ | |
4434 | ppc_change_debug_section (i, subseg->subseg); | |
4435 | } | |
4436 | else | |
4437 | { | |
4438 | /* Create a new dw subsection. */ | |
325801bd | 4439 | subseg = XNEW (struct dw_subsection); |
85645aed TG |
4440 | |
4441 | if (opt_label == NULL) | |
4442 | { | |
4443 | /* The anonymous one. */ | |
4444 | subseg->subseg = 0; | |
4445 | subseg->link = NULL; | |
4446 | dws->anon_subseg = subseg; | |
4447 | } | |
4448 | else | |
4449 | { | |
4450 | /* A named one. */ | |
4451 | if (dws->list_subseg != NULL) | |
4452 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4453 | else | |
4454 | subseg->subseg = 1; | |
4455 | ||
4456 | subseg->link = dws->list_subseg; | |
4457 | dws->list_subseg = subseg; | |
4458 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4459 | } | |
4460 | ||
4461 | ppc_change_debug_section (i, subseg->subseg); | |
4462 | ||
4463 | if (dw->def_size) | |
4464 | { | |
4465 | /* Add the length field. */ | |
4466 | expressionS *exp = &subseg->end_exp; | |
4467 | int sz; | |
4468 | ||
4469 | if (opt_label != NULL) | |
4470 | symbol_set_value_now (opt_label); | |
4471 | ||
4472 | /* Add the length field. Note that according to the AIX assembler | |
4473 | manual, the size of the length field is 4 for powerpc32 but | |
4474 | 12 for powerpc64. */ | |
4475 | if (ppc_obj64) | |
4476 | { | |
4477 | /* Write the 64bit marker. */ | |
4478 | md_number_to_chars (frag_more (4), -1, 4); | |
4479 | } | |
4480 | ||
4481 | exp->X_op = O_subtract; | |
4482 | exp->X_op_symbol = symbol_temp_new_now (); | |
4483 | exp->X_add_symbol = symbol_temp_make (); | |
4484 | ||
4485 | sz = ppc_obj64 ? 8 : 4; | |
4486 | exp->X_add_number = -sz; | |
4487 | emit_expr (exp, sz); | |
4488 | } | |
4489 | } | |
4490 | } | |
4491 | ||
252b5132 RH |
4492 | /* This function handles the .text and .data pseudo-ops. These |
4493 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4494 | convenience of people who aren't used to XCOFF. */ | |
4495 | ||
4496 | static void | |
98027b10 | 4497 | ppc_section (int type) |
252b5132 RH |
4498 | { |
4499 | const char *name; | |
4500 | symbolS *sym; | |
4501 | ||
4502 | if (type == 't') | |
4503 | name = ".text[PR]"; | |
4504 | else if (type == 'd') | |
4505 | name = ".data[RW]"; | |
4506 | else | |
4507 | abort (); | |
4508 | ||
4509 | sym = symbol_find_or_make (name); | |
4510 | ||
931e13a6 | 4511 | ppc_change_csect (sym, 2); |
252b5132 RH |
4512 | |
4513 | demand_empty_rest_of_line (); | |
4514 | } | |
4515 | ||
4516 | /* This function handles the .section pseudo-op. This is mostly to | |
4517 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4518 | we do permit the user to name the text or data section. */ | |
4519 | ||
4520 | static void | |
98027b10 | 4521 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4522 | { |
4523 | char *user_name; | |
4524 | const char *real_name; | |
4525 | char c; | |
4526 | symbolS *sym; | |
4527 | ||
d02603dc | 4528 | c = get_symbol_name (&user_name); |
252b5132 RH |
4529 | |
4530 | if (strcmp (user_name, ".text") == 0) | |
4531 | real_name = ".text[PR]"; | |
4532 | else if (strcmp (user_name, ".data") == 0) | |
4533 | real_name = ".data[RW]"; | |
4534 | else | |
4535 | { | |
d6ed37ed | 4536 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4537 | (void) restore_line_pointer (c); |
252b5132 RH |
4538 | ignore_rest_of_line (); |
4539 | return; | |
4540 | } | |
4541 | ||
d02603dc | 4542 | (void) restore_line_pointer (c); |
252b5132 RH |
4543 | |
4544 | sym = symbol_find_or_make (real_name); | |
4545 | ||
931e13a6 | 4546 | ppc_change_csect (sym, 2); |
252b5132 RH |
4547 | |
4548 | demand_empty_rest_of_line (); | |
4549 | } | |
4550 | ||
4551 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4552 | ||
4553 | static void | |
98027b10 | 4554 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4555 | { |
4556 | char *name; | |
4557 | char endc; | |
4558 | ||
d02603dc | 4559 | endc = get_symbol_name (&name); |
252b5132 RH |
4560 | |
4561 | (void) symbol_find_or_make (name); | |
4562 | ||
d02603dc | 4563 | (void) restore_line_pointer (endc); |
252b5132 RH |
4564 | |
4565 | demand_empty_rest_of_line (); | |
4566 | } | |
4567 | ||
4568 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4569 | ||
4570 | static void | |
98027b10 | 4571 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4572 | { |
4573 | char *name; | |
4574 | char endc; | |
4575 | symbolS *sym; | |
4576 | ||
d02603dc | 4577 | endc = get_symbol_name (&name); |
252b5132 RH |
4578 | |
4579 | sym = symbol_find_or_make (name); | |
4580 | ||
d02603dc | 4581 | (void) restore_line_pointer (endc); |
252b5132 | 4582 | |
809ffe0d | 4583 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4584 | |
4585 | demand_empty_rest_of_line (); | |
4586 | } | |
4587 | ||
c865e45b RS |
4588 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4589 | relocations at the beginning of the current csect. | |
4590 | ||
4591 | (In principle, there's no reason why the relocations _have_ to be at | |
4592 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4593 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4594 | deal with cases where the .ref statements follow the section contents.) |
4595 | ||
4596 | ??? .refs don't work for empty .csects. However, the native assembler | |
4597 | doesn't report an error in this case, and neither yet do we. */ | |
4598 | ||
4599 | static void | |
4600 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4601 | { | |
4602 | char *name; | |
4603 | char c; | |
4604 | ||
4605 | if (ppc_current_csect == NULL) | |
4606 | { | |
4607 | as_bad (_(".ref outside .csect")); | |
4608 | ignore_rest_of_line (); | |
4609 | return; | |
4610 | } | |
4611 | ||
4612 | do | |
4613 | { | |
d02603dc | 4614 | c = get_symbol_name (&name); |
c865e45b RS |
4615 | |
4616 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
4617 | symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE); | |
4618 | ||
4619 | *input_line_pointer = c; | |
d02603dc | 4620 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
4621 | c = *input_line_pointer; |
4622 | if (c == ',') | |
4623 | { | |
4624 | input_line_pointer++; | |
4625 | SKIP_WHITESPACE (); | |
4626 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
4627 | { | |
4628 | as_bad (_("missing symbol name")); | |
4629 | ignore_rest_of_line (); | |
4630 | return; | |
4631 | } | |
4632 | } | |
4633 | } | |
4634 | while (c == ','); | |
4635 | ||
4636 | demand_empty_rest_of_line (); | |
4637 | } | |
4638 | ||
252b5132 RH |
4639 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
4640 | although I don't know why it bothers. */ | |
4641 | ||
4642 | static void | |
98027b10 | 4643 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4644 | { |
4645 | char *name; | |
4646 | char endc; | |
4647 | symbolS *sym; | |
4648 | int len; | |
4649 | ||
d02603dc | 4650 | endc = get_symbol_name (&name); |
252b5132 RH |
4651 | |
4652 | sym = symbol_find_or_make (name); | |
4653 | ||
d02603dc | 4654 | (void) restore_line_pointer (endc); |
252b5132 RH |
4655 | |
4656 | if (*input_line_pointer != ',') | |
4657 | { | |
4658 | as_bad (_("missing rename string")); | |
4659 | ignore_rest_of_line (); | |
4660 | return; | |
4661 | } | |
4662 | ++input_line_pointer; | |
4663 | ||
809ffe0d | 4664 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
4665 | |
4666 | demand_empty_rest_of_line (); | |
4667 | } | |
4668 | ||
4669 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
4670 | pseudo-op, but slightly different. A sample is | |
4671 | .stabx "main:F-1",.main,142,0 | |
4672 | The first argument is the symbol name to create. The second is the | |
4673 | value, and the third is the storage class. The fourth seems to be | |
4674 | always zero, and I am assuming it is the type. */ | |
4675 | ||
4676 | static void | |
98027b10 | 4677 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4678 | { |
4679 | char *name; | |
4680 | int len; | |
4681 | symbolS *sym; | |
4682 | expressionS exp; | |
4683 | ||
4684 | name = demand_copy_C_string (&len); | |
4685 | ||
4686 | if (*input_line_pointer != ',') | |
4687 | { | |
4688 | as_bad (_("missing value")); | |
4689 | return; | |
4690 | } | |
4691 | ++input_line_pointer; | |
4692 | ||
b34976b6 | 4693 | ppc_stab_symbol = TRUE; |
252b5132 | 4694 | sym = symbol_make (name); |
b34976b6 | 4695 | ppc_stab_symbol = FALSE; |
252b5132 | 4696 | |
809ffe0d | 4697 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
4698 | |
4699 | (void) expression (&exp); | |
4700 | ||
4701 | switch (exp.X_op) | |
4702 | { | |
4703 | case O_illegal: | |
4704 | case O_absent: | |
4705 | case O_big: | |
4706 | as_bad (_("illegal .stabx expression; zero assumed")); | |
4707 | exp.X_add_number = 0; | |
4708 | /* Fall through. */ | |
4709 | case O_constant: | |
4710 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 4711 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
4712 | break; |
4713 | ||
4714 | case O_symbol: | |
4715 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 4716 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
4717 | else |
4718 | { | |
4719 | S_SET_VALUE (sym, | |
4720 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 4721 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
4722 | } |
4723 | break; | |
4724 | ||
4725 | default: | |
4726 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
4727 | fail at some later point, but this is probably the right |
4728 | thing to do here. */ | |
809ffe0d | 4729 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
4730 | break; |
4731 | } | |
4732 | ||
4733 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 4734 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
4735 | |
4736 | if (*input_line_pointer != ',') | |
4737 | { | |
4738 | as_bad (_("missing class")); | |
4739 | return; | |
4740 | } | |
4741 | ++input_line_pointer; | |
4742 | ||
4743 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
4744 | ||
4745 | if (*input_line_pointer != ',') | |
4746 | { | |
4747 | as_bad (_("missing type")); | |
4748 | return; | |
4749 | } | |
4750 | ++input_line_pointer; | |
4751 | ||
4752 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
4753 | ||
809ffe0d | 4754 | symbol_get_tc (sym)->output = 1; |
252b5132 | 4755 | |
c734e7e3 TG |
4756 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
4757 | { | |
4758 | /* In this case : | |
252b5132 | 4759 | |
c734e7e3 TG |
4760 | .bs name |
4761 | .stabx "z",arrays_,133,0 | |
4762 | .es | |
99a814a1 | 4763 | |
c734e7e3 | 4764 | .comm arrays_,13768,3 |
99a814a1 | 4765 | |
c734e7e3 TG |
4766 | resolve_symbol_value will copy the exp's "within" into sym's when the |
4767 | offset is 0. Since this seems to be corner case problem, | |
4768 | only do the correction for storage class C_STSYM. A better solution | |
4769 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 4770 | |
c734e7e3 TG |
4771 | if (exp.X_op == O_symbol) |
4772 | { | |
4773 | if (ppc_current_block == NULL) | |
4774 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 4775 | |
c734e7e3 TG |
4776 | symbol_get_tc (sym)->within = ppc_current_block; |
4777 | symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block; | |
4778 | } | |
4779 | } | |
99a814a1 | 4780 | |
252b5132 RH |
4781 | if (exp.X_op != O_symbol |
4782 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
4783 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
4784 | ppc_frob_label (sym); | |
4785 | else | |
4786 | { | |
4787 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
4788 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
4789 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
4790 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
4791 | } |
4792 | ||
4793 | demand_empty_rest_of_line (); | |
4794 | } | |
4795 | ||
4796 | /* The .function pseudo-op. This takes several arguments. The first | |
4797 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 4798 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
4799 | uses the same name for both. I have no idea what the third and |
4800 | fourth arguments are meant to be. The optional fifth argument is | |
4801 | an expression for the size of the function. In COFF this symbol | |
4802 | gets an aux entry like that used for a csect. */ | |
4803 | ||
4804 | static void | |
98027b10 | 4805 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4806 | { |
4807 | char *name; | |
4808 | char endc; | |
4809 | char *s; | |
4810 | symbolS *ext_sym; | |
4811 | symbolS *lab_sym; | |
4812 | ||
d02603dc | 4813 | endc = get_symbol_name (&name); |
252b5132 RH |
4814 | |
4815 | /* Ignore any [PR] suffix. */ | |
4816 | name = ppc_canonicalize_symbol_name (name); | |
4817 | s = strchr (name, '['); | |
4818 | if (s != (char *) NULL | |
4819 | && strcmp (s + 1, "PR]") == 0) | |
4820 | *s = '\0'; | |
4821 | ||
4822 | ext_sym = symbol_find_or_make (name); | |
4823 | ||
d02603dc | 4824 | (void) restore_line_pointer (endc); |
252b5132 RH |
4825 | |
4826 | if (*input_line_pointer != ',') | |
4827 | { | |
4828 | as_bad (_("missing symbol name")); | |
4829 | ignore_rest_of_line (); | |
4830 | return; | |
4831 | } | |
4832 | ++input_line_pointer; | |
4833 | ||
d02603dc | 4834 | endc = get_symbol_name (&name); |
252b5132 RH |
4835 | |
4836 | lab_sym = symbol_find_or_make (name); | |
4837 | ||
d02603dc | 4838 | (void) restore_line_pointer (endc); |
252b5132 RH |
4839 | |
4840 | if (ext_sym != lab_sym) | |
4841 | { | |
809ffe0d ILT |
4842 | expressionS exp; |
4843 | ||
4844 | exp.X_op = O_symbol; | |
4845 | exp.X_add_symbol = lab_sym; | |
4846 | exp.X_op_symbol = NULL; | |
4847 | exp.X_add_number = 0; | |
4848 | exp.X_unsigned = 0; | |
4849 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
4850 | } |
4851 | ||
96d56e9f NC |
4852 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
4853 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 4854 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
4855 | |
4856 | if (*input_line_pointer == ',') | |
4857 | { | |
91d6fa6a | 4858 | expressionS exp; |
252b5132 RH |
4859 | |
4860 | /* Ignore the third argument. */ | |
4861 | ++input_line_pointer; | |
91d6fa6a | 4862 | expression (& exp); |
252b5132 RH |
4863 | if (*input_line_pointer == ',') |
4864 | { | |
4865 | /* Ignore the fourth argument. */ | |
4866 | ++input_line_pointer; | |
91d6fa6a | 4867 | expression (& exp); |
252b5132 RH |
4868 | if (*input_line_pointer == ',') |
4869 | { | |
4870 | /* The fifth argument is the function size. */ | |
4871 | ++input_line_pointer; | |
85645aed TG |
4872 | symbol_get_tc (ext_sym)->u.size = symbol_new |
4873 | ("L0\001", absolute_section,(valueT) 0, &zero_address_frag); | |
4874 | pseudo_set (symbol_get_tc (ext_sym)->u.size); | |
252b5132 RH |
4875 | } |
4876 | } | |
4877 | } | |
4878 | ||
4879 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
4880 | SF_SET_FUNCTION (ext_sym); | |
4881 | SF_SET_PROCESS (ext_sym); | |
4882 | coff_add_linesym (ext_sym); | |
4883 | ||
4884 | demand_empty_rest_of_line (); | |
4885 | } | |
4886 | ||
4887 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
4888 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
4889 | with the correct line number */ | |
5d6255fe | 4890 | |
8642cce8 | 4891 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
4892 | |
4893 | static void | |
98027b10 | 4894 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4895 | { |
4896 | symbolS *sym; | |
4897 | ||
4898 | sym = symbol_make (".bf"); | |
4899 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4900 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4901 | S_SET_VALUE (sym, frag_now_fix ()); |
4902 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
4903 | ||
4904 | coff_line_base = get_absolute_expression (); | |
4905 | ||
4906 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
4907 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
4908 | ||
8642cce8 | 4909 | /* Line number for bi. */ |
5d6255fe | 4910 | if (saved_bi_sym) |
8642cce8 TR |
4911 | { |
4912 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
4913 | saved_bi_sym = 0; | |
4914 | } | |
5d6255fe | 4915 | |
8642cce8 | 4916 | |
809ffe0d | 4917 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4918 | |
4919 | ppc_frob_label (sym); | |
4920 | ||
4921 | demand_empty_rest_of_line (); | |
4922 | } | |
4923 | ||
4924 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
4925 | ".ef", except that the line number is absolute, not relative to the | |
4926 | most recent ".bf" symbol. */ | |
4927 | ||
4928 | static void | |
98027b10 | 4929 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4930 | { |
4931 | symbolS *sym; | |
4932 | ||
4933 | sym = symbol_make (".ef"); | |
4934 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4935 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4936 | S_SET_VALUE (sym, frag_now_fix ()); |
4937 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
4938 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
4939 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 4940 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4941 | |
4942 | ppc_frob_label (sym); | |
4943 | ||
4944 | demand_empty_rest_of_line (); | |
4945 | } | |
4946 | ||
4947 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
4948 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
4949 | the symbol list. The value of .bi will be know when the next .bf |
4950 | is encountered. */ | |
252b5132 RH |
4951 | |
4952 | static void | |
98027b10 | 4953 | ppc_biei (int ei) |
252b5132 RH |
4954 | { |
4955 | static symbolS *last_biei; | |
4956 | ||
4957 | char *name; | |
4958 | int len; | |
4959 | symbolS *sym; | |
4960 | symbolS *look; | |
4961 | ||
4962 | name = demand_copy_C_string (&len); | |
4963 | ||
4964 | /* The value of these symbols is actually file offset. Here we set | |
4965 | the value to the index into the line number entries. In | |
4966 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
4967 | to do the right thing. */ | |
4968 | ||
4969 | sym = symbol_make (name); | |
4970 | /* obj-coff.c currently only handles line numbers correctly in the | |
4971 | .text section. */ | |
4972 | S_SET_SEGMENT (sym, text_section); | |
4973 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 4974 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
4975 | |
4976 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 4977 | symbol_get_tc (sym)->output = 1; |
81d4177b | 4978 | |
8642cce8 | 4979 | /* Save bi. */ |
5d6255fe | 4980 | if (ei) |
8642cce8 TR |
4981 | saved_bi_sym = 0; |
4982 | else | |
4983 | saved_bi_sym = sym; | |
4984 | ||
252b5132 RH |
4985 | for (look = last_biei ? last_biei : symbol_rootP; |
4986 | (look != (symbolS *) NULL | |
4987 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
4988 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
4989 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
4990 | look = symbol_next (look)) | |
4991 | ; | |
4992 | if (look != (symbolS *) NULL) | |
4993 | { | |
4994 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
4995 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
4996 | last_biei = sym; | |
4997 | } | |
4998 | ||
4999 | demand_empty_rest_of_line (); | |
5000 | } | |
5001 | ||
5002 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5003 | There is one argument, which is a csect symbol. The value of the | |
5004 | .bs symbol is the index of this csect symbol. */ | |
5005 | ||
5006 | static void | |
98027b10 | 5007 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5008 | { |
5009 | char *name; | |
5010 | char endc; | |
5011 | symbolS *csect; | |
5012 | symbolS *sym; | |
5013 | ||
5014 | if (ppc_current_block != NULL) | |
5015 | as_bad (_("nested .bs blocks")); | |
5016 | ||
d02603dc | 5017 | endc = get_symbol_name (&name); |
252b5132 RH |
5018 | |
5019 | csect = symbol_find_or_make (name); | |
5020 | ||
d02603dc | 5021 | (void) restore_line_pointer (endc); |
252b5132 RH |
5022 | |
5023 | sym = symbol_make (".bs"); | |
5024 | S_SET_SEGMENT (sym, now_seg); | |
5025 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5026 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5027 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5028 | |
809ffe0d | 5029 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5030 | |
5031 | ppc_frob_label (sym); | |
5032 | ||
5033 | ppc_current_block = sym; | |
5034 | ||
5035 | demand_empty_rest_of_line (); | |
5036 | } | |
5037 | ||
5038 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5039 | ||
5040 | static void | |
98027b10 | 5041 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5042 | { |
5043 | symbolS *sym; | |
5044 | ||
5045 | if (ppc_current_block == NULL) | |
5046 | as_bad (_(".es without preceding .bs")); | |
5047 | ||
5048 | sym = symbol_make (".es"); | |
5049 | S_SET_SEGMENT (sym, now_seg); | |
5050 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5051 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5052 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5053 | |
5054 | ppc_frob_label (sym); | |
5055 | ||
5056 | ppc_current_block = NULL; | |
5057 | ||
5058 | demand_empty_rest_of_line (); | |
5059 | } | |
5060 | ||
5061 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5062 | line number. */ | |
5063 | ||
5064 | static void | |
98027b10 | 5065 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5066 | { |
5067 | symbolS *sym; | |
5068 | ||
5069 | sym = symbol_make (".bb"); | |
5070 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5071 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5072 | S_SET_VALUE (sym, frag_now_fix ()); |
5073 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5074 | ||
5075 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5076 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5077 | ||
809ffe0d | 5078 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5079 | |
5080 | SF_SET_PROCESS (sym); | |
5081 | ||
5082 | ppc_frob_label (sym); | |
5083 | ||
5084 | demand_empty_rest_of_line (); | |
5085 | } | |
5086 | ||
5087 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5088 | line number. */ | |
5089 | ||
5090 | static void | |
98027b10 | 5091 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5092 | { |
5093 | symbolS *sym; | |
5094 | ||
5095 | sym = symbol_make (".eb"); | |
5096 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5097 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5098 | S_SET_VALUE (sym, frag_now_fix ()); |
5099 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5100 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5101 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5102 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5103 | |
5104 | SF_SET_PROCESS (sym); | |
5105 | ||
5106 | ppc_frob_label (sym); | |
5107 | ||
5108 | demand_empty_rest_of_line (); | |
5109 | } | |
5110 | ||
5111 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5112 | specified name. */ | |
5113 | ||
5114 | static void | |
98027b10 | 5115 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5116 | { |
5117 | char *name; | |
5118 | int len; | |
5119 | symbolS *sym; | |
5120 | ||
5121 | name = demand_copy_C_string (&len); | |
5122 | sym = symbol_make (name); | |
5123 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5124 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5125 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5126 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5127 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5128 | |
5129 | ppc_frob_label (sym); | |
5130 | ||
5131 | demand_empty_rest_of_line (); | |
5132 | } | |
5133 | ||
5134 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5135 | ||
5136 | static void | |
98027b10 | 5137 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5138 | { |
5139 | symbolS *sym; | |
5140 | ||
5141 | sym = symbol_make (".ec"); | |
5142 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5143 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5144 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5145 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5146 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5147 | |
5148 | ppc_frob_label (sym); | |
5149 | ||
5150 | demand_empty_rest_of_line (); | |
5151 | } | |
5152 | ||
5153 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5154 | ||
5155 | static void | |
98027b10 | 5156 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5157 | { |
5158 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5159 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5160 | else |
5161 | { | |
5162 | subsegT subseg; | |
5163 | symbolS *sym; | |
5164 | symbolS *list; | |
81d4177b | 5165 | |
252b5132 RH |
5166 | subseg = ppc_data_subsegment; |
5167 | ++ppc_data_subsegment; | |
5168 | ||
5169 | subseg_new (segment_name (data_section), subseg); | |
5170 | ppc_toc_frag = frag_now; | |
5171 | ||
5172 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5173 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5174 | S_SET_SEGMENT (sym, data_section); |
5175 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5176 | symbol_get_tc (sym)->subseg = subseg; |
5177 | symbol_get_tc (sym)->output = 1; | |
5178 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5179 | |
5180 | ppc_toc_csect = sym; | |
81d4177b | 5181 | |
252b5132 | 5182 | for (list = ppc_data_csects; |
809ffe0d ILT |
5183 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5184 | list = symbol_get_tc (list)->next) | |
252b5132 | 5185 | ; |
809ffe0d | 5186 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5187 | |
5188 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5189 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5190 | &symbol_lastP); | |
252b5132 RH |
5191 | } |
5192 | ||
5193 | ppc_current_csect = ppc_toc_csect; | |
5194 | ||
5195 | demand_empty_rest_of_line (); | |
5196 | } | |
5197 | ||
5198 | /* The AIX assembler automatically aligns the operands of a .long or | |
5199 | .short pseudo-op, and we want to be compatible. */ | |
5200 | ||
5201 | static void | |
98027b10 | 5202 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5203 | { |
5204 | frag_align (log_size, 0, 0); | |
5205 | record_alignment (now_seg, log_size); | |
5206 | cons (1 << log_size); | |
5207 | } | |
5208 | ||
5209 | static void | |
98027b10 | 5210 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5211 | { |
5212 | expressionS exp; | |
5213 | int byte_count; | |
5214 | ||
5215 | (void) expression (&exp); | |
5216 | ||
5217 | if (exp.X_op != O_constant) | |
5218 | { | |
5219 | as_bad (_("non-constant byte count")); | |
5220 | return; | |
5221 | } | |
5222 | ||
5223 | byte_count = exp.X_add_number; | |
5224 | ||
5225 | if (*input_line_pointer != ',') | |
5226 | { | |
5227 | as_bad (_("missing value")); | |
5228 | return; | |
5229 | } | |
5230 | ||
5231 | ++input_line_pointer; | |
5232 | cons (byte_count); | |
5233 | } | |
5234 | ||
85645aed TG |
5235 | void |
5236 | ppc_xcoff_end (void) | |
5237 | { | |
5238 | int i; | |
5239 | ||
5240 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5241 | { | |
5242 | struct dw_section *dws = &dw_sections[i]; | |
5243 | struct dw_subsection *dwss; | |
5244 | ||
5245 | if (dws->anon_subseg) | |
5246 | { | |
5247 | dwss = dws->anon_subseg; | |
5248 | dwss->link = dws->list_subseg; | |
5249 | } | |
5250 | else | |
5251 | dwss = dws->list_subseg; | |
5252 | ||
5253 | for (; dwss != NULL; dwss = dwss->link) | |
5254 | if (dwss->end_exp.X_add_symbol != NULL) | |
5255 | { | |
5256 | subseg_set (dws->sect, dwss->subseg); | |
5257 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5258 | } | |
5259 | } | |
5260 | } | |
5261 | ||
252b5132 | 5262 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5263 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5264 | \f |
5265 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5266 | ELF. This takes two or more arguments. | |
5267 | ||
5268 | When generating XCOFF output, the first argument is the name to | |
5269 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5270 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5271 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5272 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5273 | depends on target word size. A 32-bit target uses 4-byte values, a |
5274 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5275 | |
5276 | When not generating XCOFF output, the arguments are the same, but | |
5277 | the first argument is simply ignored. */ | |
5278 | ||
5279 | static void | |
98027b10 | 5280 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5281 | { |
5282 | #ifdef OBJ_XCOFF | |
5283 | ||
5284 | /* Define the TOC symbol name. */ | |
5285 | { | |
5286 | char *name; | |
5287 | char endc; | |
5288 | symbolS *sym; | |
5289 | ||
5290 | if (ppc_toc_csect == (symbolS *) NULL | |
5291 | || ppc_toc_csect != ppc_current_csect) | |
5292 | { | |
5293 | as_bad (_(".tc not in .toc section")); | |
5294 | ignore_rest_of_line (); | |
5295 | return; | |
5296 | } | |
5297 | ||
d02603dc | 5298 | endc = get_symbol_name (&name); |
252b5132 RH |
5299 | |
5300 | sym = symbol_find_or_make (name); | |
5301 | ||
d02603dc | 5302 | (void) restore_line_pointer (endc); |
252b5132 RH |
5303 | |
5304 | if (S_IS_DEFINED (sym)) | |
5305 | { | |
5306 | symbolS *label; | |
5307 | ||
809ffe0d | 5308 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5309 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5310 | { |
5311 | as_bad (_(".tc with no label")); | |
5312 | ignore_rest_of_line (); | |
5313 | return; | |
5314 | } | |
5315 | ||
5316 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5317 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5318 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5319 | ||
5320 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5321 | ++input_line_pointer; | |
5322 | ||
5323 | return; | |
5324 | } | |
5325 | ||
5326 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5327 | symbol_set_frag (sym, frag_now); |
252b5132 | 5328 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
96d56e9f | 5329 | symbol_get_tc (sym)->symbol_class = XMC_TC; |
809ffe0d | 5330 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5331 | |
5332 | ppc_frob_label (sym); | |
5333 | } | |
5334 | ||
0baf16f2 AM |
5335 | #endif /* OBJ_XCOFF */ |
5336 | #ifdef OBJ_ELF | |
9c7977b3 | 5337 | int align; |
252b5132 RH |
5338 | |
5339 | /* Skip the TOC symbol name. */ | |
5340 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5341 | || *input_line_pointer == ' ' |
252b5132 RH |
5342 | || *input_line_pointer == '[' |
5343 | || *input_line_pointer == ']' | |
5344 | || *input_line_pointer == '{' | |
5345 | || *input_line_pointer == '}') | |
5346 | ++input_line_pointer; | |
5347 | ||
0baf16f2 | 5348 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5349 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5350 | frag_align (align, 0, 0); |
5351 | record_alignment (now_seg, align); | |
0baf16f2 | 5352 | #endif /* OBJ_ELF */ |
252b5132 RH |
5353 | |
5354 | if (*input_line_pointer != ',') | |
5355 | demand_empty_rest_of_line (); | |
5356 | else | |
5357 | { | |
5358 | ++input_line_pointer; | |
2b3c4602 | 5359 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5360 | } |
5361 | } | |
0baf16f2 AM |
5362 | |
5363 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5364 | |
5365 | static void | |
98027b10 | 5366 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5367 | { |
d02603dc | 5368 | char c; |
69c040df AM |
5369 | char *cpu_string; |
5370 | #define MAX_HISTORY 100 | |
fa452fa6 | 5371 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5372 | static int curr_hist; |
5373 | ||
5374 | SKIP_WHITESPACE (); | |
5375 | ||
d02603dc NC |
5376 | c = get_symbol_name (&cpu_string); |
5377 | cpu_string = xstrdup (cpu_string); | |
5378 | (void) restore_line_pointer (c); | |
69c040df AM |
5379 | |
5380 | if (cpu_string != NULL) | |
5381 | { | |
fa452fa6 | 5382 | ppc_cpu_t old_cpu = ppc_cpu; |
69fe9ce5 | 5383 | ppc_cpu_t new_cpu; |
69c040df AM |
5384 | char *p; |
5385 | ||
5386 | for (p = cpu_string; *p != 0; p++) | |
5387 | *p = TOLOWER (*p); | |
5388 | ||
5389 | if (strcmp (cpu_string, "push") == 0) | |
5390 | { | |
5391 | if (cpu_history == NULL) | |
325801bd | 5392 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5393 | |
5394 | if (curr_hist >= MAX_HISTORY) | |
5395 | as_bad (_(".machine stack overflow")); | |
5396 | else | |
5397 | cpu_history[curr_hist++] = ppc_cpu; | |
5398 | } | |
5399 | else if (strcmp (cpu_string, "pop") == 0) | |
5400 | { | |
5401 | if (curr_hist <= 0) | |
5402 | as_bad (_(".machine stack underflow")); | |
5403 | else | |
5404 | ppc_cpu = cpu_history[--curr_hist]; | |
5405 | } | |
776fc418 | 5406 | else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0) |
69fe9ce5 | 5407 | ppc_cpu = new_cpu; |
69c040df AM |
5408 | else |
5409 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5410 | ||
5411 | if (ppc_cpu != old_cpu) | |
5412 | ppc_setup_opcodes (); | |
5413 | } | |
5414 | ||
5415 | demand_empty_rest_of_line (); | |
0baf16f2 | 5416 | } |
0baf16f2 | 5417 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 RH |
5418 | \f |
5419 | #ifdef TE_PE | |
5420 | ||
99a814a1 | 5421 | /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */ |
252b5132 RH |
5422 | |
5423 | /* Set the current section. */ | |
5424 | static void | |
98027b10 | 5425 | ppc_set_current_section (segT new) |
252b5132 RH |
5426 | { |
5427 | ppc_previous_section = ppc_current_section; | |
5428 | ppc_current_section = new; | |
5429 | } | |
5430 | ||
5431 | /* pseudo-op: .previous | |
5432 | behaviour: toggles the current section with the previous section. | |
5433 | errors: None | |
99a814a1 AM |
5434 | warnings: "No previous section" */ |
5435 | ||
252b5132 | 5436 | static void |
98027b10 | 5437 | ppc_previous (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5438 | { |
81d4177b | 5439 | if (ppc_previous_section == NULL) |
252b5132 | 5440 | { |
d6ed37ed | 5441 | as_warn (_("no previous section to return to, ignored.")); |
252b5132 RH |
5442 | return; |
5443 | } | |
5444 | ||
99a814a1 | 5445 | subseg_set (ppc_previous_section, 0); |
252b5132 | 5446 | |
99a814a1 | 5447 | ppc_set_current_section (ppc_previous_section); |
252b5132 RH |
5448 | } |
5449 | ||
5450 | /* pseudo-op: .pdata | |
5451 | behaviour: predefined read only data section | |
b34976b6 | 5452 | double word aligned |
252b5132 RH |
5453 | errors: None |
5454 | warnings: None | |
5455 | initial: .section .pdata "adr3" | |
b34976b6 | 5456 | a - don't know -- maybe a misprint |
252b5132 RH |
5457 | d - initialized data |
5458 | r - readable | |
5459 | 3 - double word aligned (that would be 4 byte boundary) | |
5460 | ||
5461 | commentary: | |
5462 | Tag index tables (also known as the function table) for exception | |
99a814a1 | 5463 | handling, debugging, etc. */ |
252b5132 | 5464 | |
252b5132 | 5465 | static void |
98027b10 | 5466 | ppc_pdata (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5467 | { |
81d4177b | 5468 | if (pdata_section == 0) |
252b5132 RH |
5469 | { |
5470 | pdata_section = subseg_new (".pdata", 0); | |
81d4177b | 5471 | |
252b5132 RH |
5472 | bfd_set_section_flags (stdoutput, pdata_section, |
5473 | (SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
5474 | | SEC_READONLY | SEC_DATA )); | |
81d4177b | 5475 | |
252b5132 RH |
5476 | bfd_set_section_alignment (stdoutput, pdata_section, 2); |
5477 | } | |
5478 | else | |
5479 | { | |
99a814a1 | 5480 | pdata_section = subseg_new (".pdata", 0); |
252b5132 | 5481 | } |
99a814a1 | 5482 | ppc_set_current_section (pdata_section); |
252b5132 RH |
5483 | } |
5484 | ||
5485 | /* pseudo-op: .ydata | |
5486 | behaviour: predefined read only data section | |
b34976b6 | 5487 | double word aligned |
252b5132 RH |
5488 | errors: None |
5489 | warnings: None | |
5490 | initial: .section .ydata "drw3" | |
b34976b6 | 5491 | a - don't know -- maybe a misprint |
252b5132 RH |
5492 | d - initialized data |
5493 | r - readable | |
5494 | 3 - double word aligned (that would be 4 byte boundary) | |
5495 | commentary: | |
5496 | Tag tables (also known as the scope table) for exception handling, | |
99a814a1 AM |
5497 | debugging, etc. */ |
5498 | ||
252b5132 | 5499 | static void |
98027b10 | 5500 | ppc_ydata (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5501 | { |
81d4177b | 5502 | if (ydata_section == 0) |
252b5132 RH |
5503 | { |
5504 | ydata_section = subseg_new (".ydata", 0); | |
5505 | bfd_set_section_flags (stdoutput, ydata_section, | |
99a814a1 AM |
5506 | (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5507 | | SEC_READONLY | SEC_DATA )); | |
252b5132 RH |
5508 | |
5509 | bfd_set_section_alignment (stdoutput, ydata_section, 3); | |
5510 | } | |
5511 | else | |
5512 | { | |
5513 | ydata_section = subseg_new (".ydata", 0); | |
5514 | } | |
99a814a1 | 5515 | ppc_set_current_section (ydata_section); |
252b5132 RH |
5516 | } |
5517 | ||
5518 | /* pseudo-op: .reldata | |
5519 | behaviour: predefined read write data section | |
b34976b6 | 5520 | double word aligned (4-byte) |
252b5132 RH |
5521 | FIXME: relocation is applied to it |
5522 | FIXME: what's the difference between this and .data? | |
5523 | errors: None | |
5524 | warnings: None | |
5525 | initial: .section .reldata "drw3" | |
5526 | d - initialized data | |
5527 | r - readable | |
33eaf5de | 5528 | w - writable |
252b5132 RH |
5529 | 3 - double word aligned (that would be 8 byte boundary) |
5530 | ||
5531 | commentary: | |
5532 | Like .data, but intended to hold data subject to relocation, such as | |
99a814a1 AM |
5533 | function descriptors, etc. */ |
5534 | ||
252b5132 | 5535 | static void |
98027b10 | 5536 | ppc_reldata (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5537 | { |
5538 | if (reldata_section == 0) | |
5539 | { | |
5540 | reldata_section = subseg_new (".reldata", 0); | |
5541 | ||
5542 | bfd_set_section_flags (stdoutput, reldata_section, | |
99a814a1 AM |
5543 | (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5544 | | SEC_DATA)); | |
252b5132 RH |
5545 | |
5546 | bfd_set_section_alignment (stdoutput, reldata_section, 2); | |
5547 | } | |
5548 | else | |
5549 | { | |
5550 | reldata_section = subseg_new (".reldata", 0); | |
5551 | } | |
99a814a1 | 5552 | ppc_set_current_section (reldata_section); |
252b5132 RH |
5553 | } |
5554 | ||
5555 | /* pseudo-op: .rdata | |
5556 | behaviour: predefined read only data section | |
b34976b6 | 5557 | double word aligned |
252b5132 RH |
5558 | errors: None |
5559 | warnings: None | |
5560 | initial: .section .rdata "dr3" | |
5561 | d - initialized data | |
5562 | r - readable | |
99a814a1 AM |
5563 | 3 - double word aligned (that would be 4 byte boundary) */ |
5564 | ||
252b5132 | 5565 | static void |
98027b10 | 5566 | ppc_rdata (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5567 | { |
5568 | if (rdata_section == 0) | |
5569 | { | |
5570 | rdata_section = subseg_new (".rdata", 0); | |
5571 | bfd_set_section_flags (stdoutput, rdata_section, | |
5572 | (SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
5573 | | SEC_READONLY | SEC_DATA )); | |
5574 | ||
5575 | bfd_set_section_alignment (stdoutput, rdata_section, 2); | |
5576 | } | |
5577 | else | |
5578 | { | |
5579 | rdata_section = subseg_new (".rdata", 0); | |
5580 | } | |
99a814a1 | 5581 | ppc_set_current_section (rdata_section); |
252b5132 RH |
5582 | } |
5583 | ||
5584 | /* pseudo-op: .ualong | |
81d4177b | 5585 | behaviour: much like .int, with the exception that no alignment is |
b34976b6 | 5586 | performed. |
252b5132 RH |
5587 | FIXME: test the alignment statement |
5588 | errors: None | |
99a814a1 AM |
5589 | warnings: None */ |
5590 | ||
252b5132 | 5591 | static void |
98027b10 | 5592 | ppc_ualong (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5593 | { |
99a814a1 AM |
5594 | /* Try for long. */ |
5595 | cons (4); | |
252b5132 RH |
5596 | } |
5597 | ||
5598 | /* pseudo-op: .znop <symbol name> | |
5599 | behaviour: Issue a nop instruction | |
b34976b6 | 5600 | Issue a IMAGE_REL_PPC_IFGLUE relocation against it, using |
252b5132 RH |
5601 | the supplied symbol name. |
5602 | errors: None | |
99a814a1 AM |
5603 | warnings: Missing symbol name */ |
5604 | ||
252b5132 | 5605 | static void |
98027b10 | 5606 | ppc_znop (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5607 | { |
5608 | unsigned long insn; | |
5609 | const struct powerpc_opcode *opcode; | |
252b5132 | 5610 | char *f; |
252b5132 | 5611 | symbolS *sym; |
252b5132 RH |
5612 | char *symbol_name; |
5613 | char c; | |
5614 | char *name; | |
252b5132 | 5615 | |
99a814a1 | 5616 | /* Strip out the symbol name. */ |
d02603dc | 5617 | c = get_symbol_name (&symbol_name); |
252b5132 | 5618 | |
a44e2901 | 5619 | name = xstrdup (symbol_name); |
252b5132 RH |
5620 | |
5621 | sym = symbol_find_or_make (name); | |
5622 | ||
5623 | *input_line_pointer = c; | |
5624 | ||
d02603dc | 5625 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
5626 | |
5627 | /* Look up the opcode in the hash table. */ | |
5628 | opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, "nop"); | |
5629 | ||
99a814a1 | 5630 | /* Stick in the nop. */ |
252b5132 RH |
5631 | insn = opcode->opcode; |
5632 | ||
5633 | /* Write out the instruction. */ | |
5634 | f = frag_more (4); | |
5635 | md_number_to_chars (f, insn, 4); | |
5636 | fix_new (frag_now, | |
5637 | f - frag_now->fr_literal, | |
5638 | 4, | |
5639 | sym, | |
5640 | 0, | |
5641 | 0, | |
5642 | BFD_RELOC_16_GOT_PCREL); | |
5643 | ||
5644 | } | |
5645 | ||
81d4177b KH |
5646 | /* pseudo-op: |
5647 | behaviour: | |
5648 | errors: | |
99a814a1 AM |
5649 | warnings: */ |
5650 | ||
252b5132 | 5651 | static void |
98027b10 | 5652 | ppc_pe_comm (int lcomm) |
252b5132 | 5653 | { |
98027b10 AM |
5654 | char *name; |
5655 | char c; | |
5656 | char *p; | |
252b5132 | 5657 | offsetT temp; |
98027b10 | 5658 | symbolS *symbolP; |
252b5132 RH |
5659 | offsetT align; |
5660 | ||
d02603dc | 5661 | c = get_symbol_name (&name); |
252b5132 | 5662 | |
99a814a1 | 5663 | /* just after name is now '\0'. */ |
252b5132 RH |
5664 | p = input_line_pointer; |
5665 | *p = c; | |
d02603dc | 5666 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
5667 | if (*input_line_pointer != ',') |
5668 | { | |
d6ed37ed | 5669 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
5670 | ignore_rest_of_line (); |
5671 | return; | |
5672 | } | |
5673 | ||
5674 | input_line_pointer++; /* skip ',' */ | |
5675 | if ((temp = get_absolute_expression ()) < 0) | |
5676 | { | |
5677 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) temp); | |
5678 | ignore_rest_of_line (); | |
5679 | return; | |
5680 | } | |
5681 | ||
5682 | if (! lcomm) | |
5683 | { | |
5684 | /* The third argument to .comm is the alignment. */ | |
5685 | if (*input_line_pointer != ',') | |
5686 | align = 3; | |
5687 | else | |
5688 | { | |
5689 | ++input_line_pointer; | |
5690 | align = get_absolute_expression (); | |
5691 | if (align <= 0) | |
5692 | { | |
5693 | as_warn (_("ignoring bad alignment")); | |
5694 | align = 3; | |
5695 | } | |
5696 | } | |
5697 | } | |
5698 | ||
5699 | *p = 0; | |
5700 | symbolP = symbol_find_or_make (name); | |
5701 | ||
5702 | *p = c; | |
5703 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
5704 | { | |
d6ed37ed | 5705 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
5706 | S_GET_NAME (symbolP)); |
5707 | ignore_rest_of_line (); | |
5708 | return; | |
5709 | } | |
5710 | ||
5711 | if (S_GET_VALUE (symbolP)) | |
5712 | { | |
5713 | if (S_GET_VALUE (symbolP) != (valueT) temp) | |
d6ed37ed | 5714 | as_bad (_("length of .comm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
5715 | S_GET_NAME (symbolP), |
5716 | (long) S_GET_VALUE (symbolP), | |
5717 | (long) temp); | |
5718 | } | |
5719 | else | |
5720 | { | |
5721 | S_SET_VALUE (symbolP, (valueT) temp); | |
5722 | S_SET_EXTERNAL (symbolP); | |
86ebace2 | 5723 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); |
252b5132 RH |
5724 | } |
5725 | ||
5726 | demand_empty_rest_of_line (); | |
5727 | } | |
5728 | ||
5729 | /* | |
5730 | * implement the .section pseudo op: | |
5731 | * .section name {, "flags"} | |
5732 | * ^ ^ | |
5733 | * | +--- optional flags: 'b' for bss | |
5734 | * | 'i' for info | |
5735 | * +-- section name 'l' for lib | |
5736 | * 'n' for noload | |
5737 | * 'o' for over | |
5738 | * 'w' for data | |
5739 | * 'd' (apparently m88k for data) | |
5740 | * 'x' for text | |
5741 | * But if the argument is not a quoted string, treat it as a | |
5742 | * subsegment number. | |
5743 | * | |
5744 | * FIXME: this is a copy of the section processing from obj-coff.c, with | |
5745 | * additions/changes for the moto-pas assembler support. There are three | |
5746 | * categories: | |
5747 | * | |
81d4177b | 5748 | * FIXME: I just noticed this. This doesn't work at all really. It it |
252b5132 RH |
5749 | * setting bits that bfd probably neither understands or uses. The |
5750 | * correct approach (?) will have to incorporate extra fields attached | |
5751 | * to the section to hold the system specific stuff. (krk) | |
5752 | * | |
5753 | * Section Contents: | |
5754 | * 'a' - unknown - referred to in documentation, but no definition supplied | |
5755 | * 'c' - section has code | |
5756 | * 'd' - section has initialized data | |
5757 | * 'u' - section has uninitialized data | |
5758 | * 'i' - section contains directives (info) | |
5759 | * 'n' - section can be discarded | |
5760 | * 'R' - remove section at link time | |
5761 | * | |
5762 | * Section Protection: | |
5763 | * 'r' - section is readable | |
33eaf5de | 5764 | * 'w' - section is writable |
252b5132 RH |
5765 | * 'x' - section is executable |
5766 | * 's' - section is sharable | |
5767 | * | |
5768 | * Section Alignment: | |
5769 | * '0' - align to byte boundary | |
33eaf5de | 5770 | * '1' - align to halfword boundary |
252b5132 RH |
5771 | * '2' - align to word boundary |
5772 | * '3' - align to doubleword boundary | |
5773 | * '4' - align to quadword boundary | |
5774 | * '5' - align to 32 byte boundary | |
5775 | * '6' - align to 64 byte boundary | |
5776 | * | |
5777 | */ | |
5778 | ||
5779 | void | |
98027b10 | 5780 | ppc_pe_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5781 | { |
99a814a1 | 5782 | /* Strip out the section name. */ |
252b5132 RH |
5783 | char *section_name; |
5784 | char c; | |
5785 | char *name; | |
5786 | unsigned int exp; | |
5787 | flagword flags; | |
5788 | segT sec; | |
5789 | int align; | |
5790 | ||
d02603dc | 5791 | c = get_symbol_name (§ion_name); |
252b5132 | 5792 | |
a44e2901 | 5793 | name = xstrdup (section_name); |
252b5132 RH |
5794 | |
5795 | *input_line_pointer = c; | |
5796 | ||
d02603dc | 5797 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
5798 | |
5799 | exp = 0; | |
5800 | flags = SEC_NO_FLAGS; | |
5801 | ||
5802 | if (strcmp (name, ".idata$2") == 0) | |
5803 | { | |
5804 | align = 0; | |
5805 | } | |
5806 | else if (strcmp (name, ".idata$3") == 0) | |
5807 | { | |
5808 | align = 0; | |
5809 | } | |
5810 | else if (strcmp (name, ".idata$4") == 0) | |
5811 | { | |
5812 | align = 2; | |
5813 | } | |
5814 | else if (strcmp (name, ".idata$5") == 0) | |
5815 | { | |
5816 | align = 2; | |
5817 | } | |
5818 | else if (strcmp (name, ".idata$6") == 0) | |
5819 | { | |
5820 | align = 1; | |
5821 | } | |
5822 | else | |
99a814a1 AM |
5823 | /* Default alignment to 16 byte boundary. */ |
5824 | align = 4; | |
252b5132 RH |
5825 | |
5826 | if (*input_line_pointer == ',') | |
5827 | { | |
5828 | ++input_line_pointer; | |
5829 | SKIP_WHITESPACE (); | |
5830 | if (*input_line_pointer != '"') | |
5831 | exp = get_absolute_expression (); | |
5832 | else | |
5833 | { | |
5834 | ++input_line_pointer; | |
5835 | while (*input_line_pointer != '"' | |
5836 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5837 | { | |
5838 | switch (*input_line_pointer) | |
5839 | { | |
5840 | /* Section Contents */ | |
5841 | case 'a': /* unknown */ | |
d6ed37ed | 5842 | as_bad (_("unsupported section attribute -- 'a'")); |
252b5132 RH |
5843 | break; |
5844 | case 'c': /* code section */ | |
81d4177b | 5845 | flags |= SEC_CODE; |
252b5132 RH |
5846 | break; |
5847 | case 'd': /* section has initialized data */ | |
5848 | flags |= SEC_DATA; | |
5849 | break; | |
5850 | case 'u': /* section has uninitialized data */ | |
5851 | /* FIXME: This is IMAGE_SCN_CNT_UNINITIALIZED_DATA | |
5852 | in winnt.h */ | |
5853 | flags |= SEC_ROM; | |
5854 | break; | |
5855 | case 'i': /* section contains directives (info) */ | |
5856 | /* FIXME: This is IMAGE_SCN_LNK_INFO | |
5857 | in winnt.h */ | |
5858 | flags |= SEC_HAS_CONTENTS; | |
5859 | break; | |
5860 | case 'n': /* section can be discarded */ | |
81d4177b | 5861 | flags &=~ SEC_LOAD; |
252b5132 RH |
5862 | break; |
5863 | case 'R': /* Remove section at link time */ | |
5864 | flags |= SEC_NEVER_LOAD; | |
5865 | break; | |
8d452c78 | 5866 | #if IFLICT_BRAIN_DAMAGE |
252b5132 RH |
5867 | /* Section Protection */ |
5868 | case 'r': /* section is readable */ | |
5869 | flags |= IMAGE_SCN_MEM_READ; | |
5870 | break; | |
33eaf5de | 5871 | case 'w': /* section is writable */ |
252b5132 RH |
5872 | flags |= IMAGE_SCN_MEM_WRITE; |
5873 | break; | |
5874 | case 'x': /* section is executable */ | |
5875 | flags |= IMAGE_SCN_MEM_EXECUTE; | |
5876 | break; | |
5877 | case 's': /* section is sharable */ | |
5878 | flags |= IMAGE_SCN_MEM_SHARED; | |
5879 | break; | |
5880 | ||
5881 | /* Section Alignment */ | |
5882 | case '0': /* align to byte boundary */ | |
5883 | flags |= IMAGE_SCN_ALIGN_1BYTES; | |
5884 | align = 0; | |
5885 | break; | |
5886 | case '1': /* align to halfword boundary */ | |
5887 | flags |= IMAGE_SCN_ALIGN_2BYTES; | |
5888 | align = 1; | |
5889 | break; | |
5890 | case '2': /* align to word boundary */ | |
5891 | flags |= IMAGE_SCN_ALIGN_4BYTES; | |
5892 | align = 2; | |
5893 | break; | |
5894 | case '3': /* align to doubleword boundary */ | |
5895 | flags |= IMAGE_SCN_ALIGN_8BYTES; | |
5896 | align = 3; | |
5897 | break; | |
5898 | case '4': /* align to quadword boundary */ | |
5899 | flags |= IMAGE_SCN_ALIGN_16BYTES; | |
5900 | align = 4; | |
5901 | break; | |
5902 | case '5': /* align to 32 byte boundary */ | |
5903 | flags |= IMAGE_SCN_ALIGN_32BYTES; | |
5904 | align = 5; | |
5905 | break; | |
5906 | case '6': /* align to 64 byte boundary */ | |
5907 | flags |= IMAGE_SCN_ALIGN_64BYTES; | |
5908 | align = 6; | |
5909 | break; | |
8d452c78 | 5910 | #endif |
252b5132 | 5911 | default: |
99a814a1 AM |
5912 | as_bad (_("unknown section attribute '%c'"), |
5913 | *input_line_pointer); | |
252b5132 RH |
5914 | break; |
5915 | } | |
5916 | ++input_line_pointer; | |
5917 | } | |
5918 | if (*input_line_pointer == '"') | |
5919 | ++input_line_pointer; | |
5920 | } | |
5921 | } | |
5922 | ||
5923 | sec = subseg_new (name, (subsegT) exp); | |
5924 | ||
99a814a1 | 5925 | ppc_set_current_section (sec); |
252b5132 RH |
5926 | |
5927 | if (flags != SEC_NO_FLAGS) | |
5928 | { | |
5929 | if (! bfd_set_section_flags (stdoutput, sec, flags)) | |
5930 | as_bad (_("error setting flags for \"%s\": %s"), | |
5931 | bfd_section_name (stdoutput, sec), | |
5932 | bfd_errmsg (bfd_get_error ())); | |
5933 | } | |
5934 | ||
99a814a1 | 5935 | bfd_set_section_alignment (stdoutput, sec, align); |
252b5132 RH |
5936 | } |
5937 | ||
5938 | static void | |
98027b10 | 5939 | ppc_pe_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5940 | { |
5941 | char *name; | |
5942 | char endc; | |
5943 | symbolS *ext_sym; | |
5944 | ||
d02603dc | 5945 | endc = get_symbol_name (&name); |
252b5132 RH |
5946 | |
5947 | ext_sym = symbol_find_or_make (name); | |
5948 | ||
d02603dc | 5949 | (void) restore_line_pointer (endc); |
252b5132 RH |
5950 | |
5951 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
5952 | SF_SET_FUNCTION (ext_sym); | |
5953 | SF_SET_PROCESS (ext_sym); | |
5954 | coff_add_linesym (ext_sym); | |
5955 | ||
5956 | demand_empty_rest_of_line (); | |
5957 | } | |
5958 | ||
5959 | static void | |
98027b10 | 5960 | ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5961 | { |
5962 | if (tocdata_section == 0) | |
5963 | { | |
5964 | tocdata_section = subseg_new (".tocd", 0); | |
99a814a1 | 5965 | /* FIXME: section flags won't work. */ |
252b5132 RH |
5966 | bfd_set_section_flags (stdoutput, tocdata_section, |
5967 | (SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
99a814a1 | 5968 | | SEC_READONLY | SEC_DATA)); |
252b5132 RH |
5969 | |
5970 | bfd_set_section_alignment (stdoutput, tocdata_section, 2); | |
5971 | } | |
5972 | else | |
5973 | { | |
5974 | rdata_section = subseg_new (".tocd", 0); | |
5975 | } | |
5976 | ||
99a814a1 | 5977 | ppc_set_current_section (tocdata_section); |
252b5132 RH |
5978 | |
5979 | demand_empty_rest_of_line (); | |
5980 | } | |
5981 | ||
5982 | /* Don't adjust TOC relocs to use the section symbol. */ | |
5983 | ||
5984 | int | |
98027b10 | 5985 | ppc_pe_fix_adjustable (fixS *fix) |
252b5132 RH |
5986 | { |
5987 | return fix->fx_r_type != BFD_RELOC_PPC_TOC16; | |
5988 | } | |
5989 | ||
5990 | #endif | |
5991 | \f | |
5992 | #ifdef OBJ_XCOFF | |
5993 | ||
5994 | /* XCOFF specific symbol and file handling. */ | |
5995 | ||
5996 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
5997 | any, to use square brackets, and to be in upper case. */ | |
5998 | ||
5999 | char * | |
98027b10 | 6000 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
6001 | { |
6002 | char *s; | |
6003 | ||
6004 | if (ppc_stab_symbol) | |
6005 | return name; | |
6006 | ||
6007 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
6008 | ; | |
6009 | if (*s != '\0') | |
6010 | { | |
6011 | char brac; | |
6012 | ||
6013 | if (*s == '[') | |
6014 | brac = ']'; | |
6015 | else | |
6016 | { | |
6017 | *s = '['; | |
6018 | brac = '}'; | |
6019 | } | |
6020 | ||
6021 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 6022 | *s = TOUPPER (*s); |
252b5132 RH |
6023 | |
6024 | if (*s == '\0' || s[1] != '\0') | |
6025 | as_bad (_("bad symbol suffix")); | |
6026 | ||
6027 | *s = ']'; | |
6028 | } | |
6029 | ||
6030 | return name; | |
6031 | } | |
6032 | ||
6033 | /* Set the class of a symbol based on the suffix, if any. This is | |
6034 | called whenever a new symbol is created. */ | |
6035 | ||
6036 | void | |
98027b10 | 6037 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 6038 | { |
809ffe0d | 6039 | struct ppc_tc_sy *tc; |
252b5132 RH |
6040 | const char *s; |
6041 | ||
809ffe0d ILT |
6042 | tc = symbol_get_tc (sym); |
6043 | tc->next = NULL; | |
6044 | tc->output = 0; | |
96d56e9f | 6045 | tc->symbol_class = -1; |
809ffe0d ILT |
6046 | tc->real_name = NULL; |
6047 | tc->subseg = 0; | |
6048 | tc->align = 0; | |
85645aed TG |
6049 | tc->u.size = NULL; |
6050 | tc->u.dw = NULL; | |
809ffe0d | 6051 | tc->within = NULL; |
252b5132 RH |
6052 | |
6053 | if (ppc_stab_symbol) | |
6054 | return; | |
6055 | ||
6056 | s = strchr (S_GET_NAME (sym), '['); | |
6057 | if (s == (const char *) NULL) | |
6058 | { | |
6059 | /* There is no suffix. */ | |
6060 | return; | |
6061 | } | |
6062 | ||
6063 | ++s; | |
6064 | ||
6065 | switch (s[0]) | |
6066 | { | |
6067 | case 'B': | |
6068 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 6069 | tc->symbol_class = XMC_BS; |
252b5132 RH |
6070 | break; |
6071 | case 'D': | |
6072 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 6073 | tc->symbol_class = XMC_DB; |
252b5132 | 6074 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 6075 | tc->symbol_class = XMC_DS; |
252b5132 RH |
6076 | break; |
6077 | case 'G': | |
6078 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 6079 | tc->symbol_class = XMC_GL; |
252b5132 RH |
6080 | break; |
6081 | case 'P': | |
6082 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 6083 | tc->symbol_class = XMC_PR; |
252b5132 RH |
6084 | break; |
6085 | case 'R': | |
6086 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 6087 | tc->symbol_class = XMC_RO; |
252b5132 | 6088 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 6089 | tc->symbol_class = XMC_RW; |
252b5132 RH |
6090 | break; |
6091 | case 'S': | |
6092 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 6093 | tc->symbol_class = XMC_SV; |
252b5132 RH |
6094 | break; |
6095 | case 'T': | |
6096 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 6097 | tc->symbol_class = XMC_TC; |
252b5132 | 6098 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 6099 | tc->symbol_class = XMC_TI; |
252b5132 | 6100 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 6101 | tc->symbol_class = XMC_TB; |
252b5132 | 6102 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 6103 | tc->symbol_class = XMC_TC0; |
252b5132 RH |
6104 | break; |
6105 | case 'U': | |
6106 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 6107 | tc->symbol_class = XMC_UA; |
252b5132 | 6108 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 6109 | tc->symbol_class = XMC_UC; |
252b5132 RH |
6110 | break; |
6111 | case 'X': | |
6112 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 6113 | tc->symbol_class = XMC_XO; |
252b5132 RH |
6114 | break; |
6115 | } | |
6116 | ||
96d56e9f | 6117 | if (tc->symbol_class == -1) |
d6ed37ed | 6118 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
6119 | } |
6120 | ||
6121 | /* Set the class of a label based on where it is defined. This | |
6122 | handles symbols without suffixes. Also, move the symbol so that it | |
6123 | follows the csect symbol. */ | |
6124 | ||
6125 | void | |
98027b10 | 6126 | ppc_frob_label (symbolS *sym) |
252b5132 RH |
6127 | { |
6128 | if (ppc_current_csect != (symbolS *) NULL) | |
6129 | { | |
96d56e9f NC |
6130 | if (symbol_get_tc (sym)->symbol_class == -1) |
6131 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
252b5132 RH |
6132 | |
6133 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
6134 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, |
6135 | &symbol_rootP, &symbol_lastP); | |
6136 | symbol_get_tc (ppc_current_csect)->within = sym; | |
2fb4b302 | 6137 | symbol_get_tc (sym)->within = ppc_current_csect; |
252b5132 | 6138 | } |
07a53e5c RH |
6139 | |
6140 | #ifdef OBJ_ELF | |
6141 | dwarf2_emit_label (sym); | |
6142 | #endif | |
252b5132 RH |
6143 | } |
6144 | ||
6145 | /* This variable is set by ppc_frob_symbol if any absolute symbols are | |
6146 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
6147 | the symbols. */ | |
6148 | ||
b34976b6 | 6149 | static bfd_boolean ppc_saw_abs; |
252b5132 RH |
6150 | |
6151 | /* Change the name of a symbol just before writing it out. Set the | |
6152 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
6153 | class suffix. Return 1 if the symbol should not be included in the | |
6154 | symbol table. */ | |
6155 | ||
6156 | int | |
98027b10 | 6157 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
6158 | { |
6159 | static symbolS *ppc_last_function; | |
6160 | static symbolS *set_end; | |
6161 | ||
6162 | /* Discard symbols that should not be included in the output symbol | |
6163 | table. */ | |
809ffe0d ILT |
6164 | if (! symbol_used_in_reloc_p (sym) |
6165 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 | |
670ec21d | 6166 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6167 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
6168 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
6169 | return 1; | |
6170 | ||
a161fe53 AM |
6171 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
6172 | if (sym == abs_section_sym) | |
6173 | return 1; | |
6174 | ||
809ffe0d ILT |
6175 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
6176 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
6177 | else |
6178 | { | |
6179 | const char *name; | |
6180 | const char *s; | |
6181 | ||
6182 | name = S_GET_NAME (sym); | |
6183 | s = strchr (name, '['); | |
6184 | if (s != (char *) NULL) | |
6185 | { | |
6186 | unsigned int len; | |
6187 | char *snew; | |
6188 | ||
6189 | len = s - name; | |
a44e2901 | 6190 | snew = xstrndup (name, len); |
252b5132 RH |
6191 | |
6192 | S_SET_NAME (sym, snew); | |
6193 | } | |
6194 | } | |
6195 | ||
6196 | if (set_end != (symbolS *) NULL) | |
6197 | { | |
6198 | SA_SET_SYM_ENDNDX (set_end, sym); | |
6199 | set_end = NULL; | |
6200 | } | |
6201 | ||
6202 | if (SF_GET_FUNCTION (sym)) | |
6203 | { | |
6204 | if (ppc_last_function != (symbolS *) NULL) | |
6205 | as_bad (_("two .function pseudo-ops with no intervening .ef")); | |
6206 | ppc_last_function = sym; | |
85645aed | 6207 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 6208 | { |
85645aed | 6209 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 6210 | SA_SET_SYM_FSIZE (sym, |
85645aed | 6211 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 RH |
6212 | } |
6213 | } | |
6214 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
6215 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
6216 | { | |
6217 | if (ppc_last_function == (symbolS *) NULL) | |
6218 | as_bad (_(".ef with no preceding .function")); | |
6219 | else | |
6220 | { | |
6221 | set_end = ppc_last_function; | |
6222 | ppc_last_function = NULL; | |
6223 | ||
6224 | /* We don't have a C_EFCN symbol, but we need to force the | |
6225 | COFF backend to believe that it has seen one. */ | |
6226 | coff_last_function = NULL; | |
6227 | } | |
6228 | } | |
6229 | ||
670ec21d | 6230 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6231 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
6232 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
6233 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
6234 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
6235 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
6236 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
6237 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
6238 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
6239 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
6240 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
6241 | ||
6242 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 6243 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
6244 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
6245 | { | |
6246 | int i; | |
6247 | union internal_auxent *a; | |
6248 | ||
6249 | /* Create a csect aux. */ | |
6250 | i = S_GET_NUMBER_AUXILIARY (sym); | |
6251 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 6252 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 6253 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
6254 | { |
6255 | /* This is the TOC table. */ | |
6256 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
6257 | a->x_csect.x_scnlen.l = 0; | |
6258 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6259 | } | |
809ffe0d | 6260 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
6261 | { |
6262 | /* This is a csect symbol. x_scnlen is the size of the | |
6263 | csect. */ | |
809ffe0d | 6264 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
252b5132 RH |
6265 | a->x_csect.x_scnlen.l = (bfd_section_size (stdoutput, |
6266 | S_GET_SEGMENT (sym)) | |
6267 | - S_GET_VALUE (sym)); | |
6268 | else | |
6269 | { | |
6386f3a7 | 6270 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 6271 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
6272 | - S_GET_VALUE (sym)); |
6273 | } | |
809ffe0d | 6274 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; |
252b5132 RH |
6275 | } |
6276 | else if (S_GET_SEGMENT (sym) == bss_section) | |
6277 | { | |
6278 | /* This is a common symbol. */ | |
809ffe0d ILT |
6279 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
6280 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
252b5132 | 6281 | if (S_IS_EXTERNAL (sym)) |
96d56e9f | 6282 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 6283 | else |
96d56e9f | 6284 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
6285 | } |
6286 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
6287 | { | |
6288 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 6289 | ppc_adjust_symtab. */ |
b34976b6 | 6290 | ppc_saw_abs = TRUE; |
252b5132 | 6291 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
6292 | if (symbol_get_tc (sym)->symbol_class == -1) |
6293 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
6294 | } |
6295 | else if (! S_IS_DEFINED (sym)) | |
6296 | { | |
6297 | /* This is an external symbol. */ | |
6298 | a->x_csect.x_scnlen.l = 0; | |
6299 | a->x_csect.x_smtyp = XTY_ER; | |
6300 | } | |
96d56e9f | 6301 | else if (symbol_get_tc (sym)->symbol_class == XMC_TC) |
252b5132 RH |
6302 | { |
6303 | symbolS *next; | |
6304 | ||
6305 | /* This is a TOC definition. x_scnlen is the size of the | |
6306 | TOC entry. */ | |
6307 | next = symbol_next (sym); | |
96d56e9f | 6308 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
6309 | next = symbol_next (next); |
6310 | if (next == (symbolS *) NULL | |
96d56e9f | 6311 | || symbol_get_tc (next)->symbol_class != XMC_TC) |
252b5132 RH |
6312 | { |
6313 | if (ppc_after_toc_frag == (fragS *) NULL) | |
6314 | a->x_csect.x_scnlen.l = (bfd_section_size (stdoutput, | |
6315 | data_section) | |
6316 | - S_GET_VALUE (sym)); | |
6317 | else | |
6318 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
6319 | - S_GET_VALUE (sym)); | |
6320 | } | |
6321 | else | |
6322 | { | |
6386f3a7 | 6323 | resolve_symbol_value (next); |
252b5132 RH |
6324 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
6325 | - S_GET_VALUE (sym)); | |
6326 | } | |
6327 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6328 | } | |
6329 | else | |
6330 | { | |
6331 | symbolS *csect; | |
6332 | ||
6333 | /* This is a normal symbol definition. x_scnlen is the | |
6334 | symbol index of the containing csect. */ | |
6335 | if (S_GET_SEGMENT (sym) == text_section) | |
6336 | csect = ppc_text_csects; | |
6337 | else if (S_GET_SEGMENT (sym) == data_section) | |
6338 | csect = ppc_data_csects; | |
6339 | else | |
6340 | abort (); | |
6341 | ||
6342 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 6343 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6344 | |
6345 | if (csect == (symbolS *) NULL) | |
6346 | { | |
6347 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
6348 | a->x_csect.x_scnlen.l = 0; | |
6349 | } | |
6350 | else | |
6351 | { | |
809ffe0d | 6352 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 6353 | { |
6386f3a7 | 6354 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
6355 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
6356 | > S_GET_VALUE (sym)) | |
252b5132 | 6357 | break; |
809ffe0d | 6358 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6359 | } |
6360 | ||
809ffe0d ILT |
6361 | a->x_csect.x_scnlen.p = |
6362 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
6363 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
6364 | 1; | |
252b5132 RH |
6365 | } |
6366 | a->x_csect.x_smtyp = XTY_LD; | |
6367 | } | |
81d4177b | 6368 | |
252b5132 RH |
6369 | a->x_csect.x_parmhash = 0; |
6370 | a->x_csect.x_snhash = 0; | |
96d56e9f | 6371 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
6372 | a->x_csect.x_smclas = XMC_PR; |
6373 | else | |
96d56e9f | 6374 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
6375 | a->x_csect.x_stab = 0; |
6376 | a->x_csect.x_snstab = 0; | |
6377 | ||
6378 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 6379 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
6380 | } |
6381 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
6382 | { | |
6383 | /* We want the value to be the symbol index of the referenced | |
6384 | csect symbol. BFD will do that for us if we set the right | |
6385 | flags. */ | |
b782de16 AM |
6386 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
6387 | combined_entry_type *c = coffsymbol (bsym)->native; | |
6388 | ||
6389 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 6390 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
6391 | } |
6392 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
6393 | { | |
6394 | symbolS *block; | |
c734e7e3 | 6395 | valueT base; |
252b5132 | 6396 | |
809ffe0d | 6397 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
6398 | if (block) |
6399 | { | |
6400 | /* The value is the offset from the enclosing csect. */ | |
6401 | symbolS *csect; | |
6402 | ||
6403 | csect = symbol_get_tc (block)->within; | |
6404 | resolve_symbol_value (csect); | |
6405 | base = S_GET_VALUE (csect); | |
6406 | } | |
6407 | else | |
6408 | base = 0; | |
6409 | ||
6410 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
6411 | } |
6412 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
6413 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
6414 | { | |
6415 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
6416 | BFD will do that for us if we set the right flags. We have |
6417 | already set the value correctly. */ | |
809ffe0d | 6418 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
6419 | } |
6420 | ||
6421 | return 0; | |
6422 | } | |
6423 | ||
6424 | /* Adjust the symbol table. This creates csect symbols for all | |
6425 | absolute symbols. */ | |
6426 | ||
6427 | void | |
98027b10 | 6428 | ppc_adjust_symtab (void) |
252b5132 RH |
6429 | { |
6430 | symbolS *sym; | |
6431 | ||
6432 | if (! ppc_saw_abs) | |
6433 | return; | |
6434 | ||
6435 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
6436 | { | |
6437 | symbolS *csect; | |
6438 | int i; | |
6439 | union internal_auxent *a; | |
6440 | ||
6441 | if (S_GET_SEGMENT (sym) != absolute_section) | |
6442 | continue; | |
6443 | ||
6444 | csect = symbol_create (".abs[XO]", absolute_section, | |
6445 | S_GET_VALUE (sym), &zero_address_frag); | |
809ffe0d | 6446 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
6447 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
6448 | i = S_GET_NUMBER_AUXILIARY (csect); | |
6449 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 6450 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
6451 | a->x_csect.x_scnlen.l = 0; |
6452 | a->x_csect.x_smtyp = XTY_SD; | |
6453 | a->x_csect.x_parmhash = 0; | |
6454 | a->x_csect.x_snhash = 0; | |
6455 | a->x_csect.x_smclas = XMC_XO; | |
6456 | a->x_csect.x_stab = 0; | |
6457 | a->x_csect.x_snstab = 0; | |
6458 | ||
6459 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
6460 | ||
6461 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
6462 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
6463 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
6464 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
6465 | } |
6466 | ||
b34976b6 | 6467 | ppc_saw_abs = FALSE; |
252b5132 RH |
6468 | } |
6469 | ||
6470 | /* Set the VMA for a section. This is called on all the sections in | |
6471 | turn. */ | |
6472 | ||
6473 | void | |
98027b10 | 6474 | ppc_frob_section (asection *sec) |
252b5132 | 6475 | { |
931e13a6 | 6476 | static bfd_vma vma = 0; |
252b5132 | 6477 | |
85645aed TG |
6478 | /* Dwarf sections start at 0. */ |
6479 | if (bfd_get_section_flags (NULL, sec) & SEC_DEBUGGING) | |
6480 | return; | |
6481 | ||
931e13a6 | 6482 | vma = md_section_align (sec, vma); |
252b5132 RH |
6483 | bfd_set_section_vma (stdoutput, sec, vma); |
6484 | vma += bfd_section_size (stdoutput, sec); | |
6485 | } | |
6486 | ||
6487 | #endif /* OBJ_XCOFF */ | |
6488 | \f | |
6d4af3c2 | 6489 | const char * |
98027b10 | 6490 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 6491 | { |
499ac353 | 6492 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
6493 | } |
6494 | ||
6495 | /* Write a value out to the object file, using the appropriate | |
6496 | endianness. */ | |
6497 | ||
6498 | void | |
98027b10 | 6499 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
6500 | { |
6501 | if (target_big_endian) | |
6502 | number_to_chars_bigendian (buf, val, n); | |
6503 | else | |
6504 | number_to_chars_littleendian (buf, val, n); | |
6505 | } | |
6506 | ||
6507 | /* Align a section (I don't know why this is machine dependent). */ | |
6508 | ||
6509 | valueT | |
3aeeedbb | 6510 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 6511 | { |
3aeeedbb AM |
6512 | #ifdef OBJ_ELF |
6513 | return addr; | |
6514 | #else | |
252b5132 RH |
6515 | int align = bfd_get_section_alignment (stdoutput, seg); |
6516 | ||
8d3842cd | 6517 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 6518 | #endif |
252b5132 RH |
6519 | } |
6520 | ||
6521 | /* We don't have any form of relaxing. */ | |
6522 | ||
6523 | int | |
98027b10 AM |
6524 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
6525 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
6526 | { |
6527 | abort (); | |
6528 | return 0; | |
6529 | } | |
6530 | ||
6531 | /* Convert a machine dependent frag. We never generate these. */ | |
6532 | ||
6533 | void | |
98027b10 AM |
6534 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
6535 | asection *sec ATTRIBUTE_UNUSED, | |
6536 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
6537 | { |
6538 | abort (); | |
6539 | } | |
6540 | ||
6541 | /* We have no need to default values of symbols. */ | |
6542 | ||
252b5132 | 6543 | symbolS * |
98027b10 | 6544 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6545 | { |
6546 | return 0; | |
6547 | } | |
6548 | \f | |
6549 | /* Functions concerning relocs. */ | |
6550 | ||
6551 | /* The location from which a PC relative jump should be calculated, | |
6552 | given a PC relative reloc. */ | |
6553 | ||
6554 | long | |
98027b10 | 6555 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6556 | { |
6557 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6558 | } | |
6559 | ||
6560 | #ifdef OBJ_XCOFF | |
6561 | ||
6562 | /* This is called to see whether a fixup should be adjusted to use a | |
6563 | section symbol. We take the opportunity to change a fixup against | |
6564 | a symbol in the TOC subsegment into a reloc against the | |
6565 | corresponding .tc symbol. */ | |
6566 | ||
6567 | int | |
98027b10 | 6568 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6569 | { |
b782de16 AM |
6570 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6571 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
6572 | TC_SYMFIELD_TYPE *tc; | |
6573 | ||
6574 | if (symseg == absolute_section) | |
6575 | return 0; | |
252b5132 | 6576 | |
85645aed TG |
6577 | /* Always adjust symbols in debugging sections. */ |
6578 | if (bfd_get_section_flags (stdoutput, symseg) & SEC_DEBUGGING) | |
6579 | return 1; | |
6580 | ||
252b5132 | 6581 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6582 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6583 | && symseg == data_section |
252b5132 RH |
6584 | && val >= ppc_toc_frag->fr_address |
6585 | && (ppc_after_toc_frag == (fragS *) NULL | |
6586 | || val < ppc_after_toc_frag->fr_address)) | |
6587 | { | |
6588 | symbolS *sy; | |
6589 | ||
6590 | for (sy = symbol_next (ppc_toc_csect); | |
6591 | sy != (symbolS *) NULL; | |
6592 | sy = symbol_next (sy)) | |
6593 | { | |
b782de16 AM |
6594 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6595 | ||
96d56e9f | 6596 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6597 | continue; |
96d56e9f | 6598 | if (sy_tc->symbol_class != XMC_TC) |
252b5132 | 6599 | break; |
b782de16 | 6600 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6601 | { |
6602 | fix->fx_addsy = sy; | |
6603 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6604 | return 0; | |
6605 | } | |
6606 | } | |
6607 | ||
6608 | as_bad_where (fix->fx_file, fix->fx_line, | |
6609 | _("symbol in .toc does not match any .tc")); | |
6610 | } | |
6611 | ||
6612 | /* Possibly adjust the reloc to be against the csect. */ | |
b782de16 AM |
6613 | tc = symbol_get_tc (fix->fx_addsy); |
6614 | if (tc->subseg == 0 | |
96d56e9f NC |
6615 | && tc->symbol_class != XMC_TC0 |
6616 | && tc->symbol_class != XMC_TC | |
b782de16 | 6617 | && symseg != bss_section |
252b5132 | 6618 | /* Don't adjust if this is a reloc in the toc section. */ |
b782de16 | 6619 | && (symseg != data_section |
252b5132 RH |
6620 | || ppc_toc_csect == NULL |
6621 | || val < ppc_toc_frag->fr_address | |
6622 | || (ppc_after_toc_frag != NULL | |
6623 | && val >= ppc_after_toc_frag->fr_address))) | |
6624 | { | |
2fb4b302 | 6625 | symbolS *csect = tc->within; |
252b5132 | 6626 | |
2fb4b302 TG |
6627 | /* If the symbol was not declared by a label (eg: a section symbol), |
6628 | use the section instead of the csect. This doesn't happen in | |
6629 | normal AIX assembly code. */ | |
6630 | if (csect == NULL) | |
6631 | csect = seg_info (symseg)->sym; | |
252b5132 | 6632 | |
2fb4b302 TG |
6633 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6634 | fix->fx_addsy = csect; | |
252b5132 | 6635 | |
b782de16 | 6636 | return 0; |
252b5132 RH |
6637 | } |
6638 | ||
6639 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6640 | .lcomm. */ | |
b782de16 | 6641 | if (symseg == bss_section |
252b5132 RH |
6642 | && ! S_IS_EXTERNAL (fix->fx_addsy)) |
6643 | { | |
b782de16 AM |
6644 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6645 | ||
6646 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6647 | fix->fx_addsy = sy; | |
252b5132 RH |
6648 | } |
6649 | ||
6650 | return 0; | |
6651 | } | |
6652 | ||
6653 | /* A reloc from one csect to another must be kept. The assembler | |
6654 | will, of course, keep relocs between sections, and it will keep | |
6655 | absolute relocs, but we need to force it to keep PC relative relocs | |
6656 | between two csects in the same section. */ | |
6657 | ||
6658 | int | |
98027b10 | 6659 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6660 | { |
6661 | /* At this point fix->fx_addsy should already have been converted to | |
6662 | a csect symbol. If the csect does not include the fragment, then | |
6663 | we need to force the relocation. */ | |
6664 | if (fix->fx_pcrel | |
6665 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6666 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6667 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6668 | > fix->fx_frag->fr_address) | |
6669 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6670 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6671 | <= fix->fx_frag->fr_address)))) |
6672 | return 1; | |
6673 | ||
ae6063d4 | 6674 | return generic_force_reloc (fix); |
252b5132 RH |
6675 | } |
6676 | ||
2fb4b302 TG |
6677 | void |
6678 | ppc_new_dot_label (symbolS *sym) | |
6679 | { | |
6680 | /* Anchor this label to the current csect for relocations. */ | |
6681 | symbol_get_tc (sym)->within = ppc_current_csect; | |
6682 | } | |
6683 | ||
252b5132 RH |
6684 | #endif /* OBJ_XCOFF */ |
6685 | ||
0baf16f2 | 6686 | #ifdef OBJ_ELF |
a161fe53 AM |
6687 | /* If this function returns non-zero, it guarantees that a relocation |
6688 | will be emitted for a fixup. */ | |
6689 | ||
6690 | int | |
98027b10 | 6691 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
6692 | { |
6693 | /* Branch prediction relocations must force a relocation, as must | |
6694 | the vtable description relocs. */ | |
6695 | switch (fix->fx_r_type) | |
6696 | { | |
6697 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6698 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6699 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6700 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 6701 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 6702 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 6703 | return 1; |
6911b7dc AM |
6704 | case BFD_RELOC_PPC_B26: |
6705 | case BFD_RELOC_PPC_BA26: | |
6706 | case BFD_RELOC_PPC_B16: | |
6707 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 6708 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
6709 | /* All branch fixups targeting a localentry symbol must |
6710 | force a relocation. */ | |
6711 | if (fix->fx_addsy) | |
6712 | { | |
6713 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
6714 | elf_symbol_type *elfsym | |
6715 | = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
6716 | gas_assert (elfsym); | |
6717 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6718 | return 1; | |
6719 | } | |
6720 | break; | |
a161fe53 AM |
6721 | default: |
6722 | break; | |
6723 | } | |
6724 | ||
cdba85ec AM |
6725 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
6726 | && fix->fx_r_type <= BFD_RELOC_PPC64_DTPREL16_HIGHESTA) | |
6727 | return 1; | |
6728 | ||
ae6063d4 | 6729 | return generic_force_reloc (fix); |
a161fe53 AM |
6730 | } |
6731 | ||
0baf16f2 | 6732 | int |
98027b10 | 6733 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6734 | { |
6911b7dc AM |
6735 | switch (fix->fx_r_type) |
6736 | { | |
6737 | /* All branch fixups targeting a localentry symbol must | |
6738 | continue using the symbol. */ | |
6739 | case BFD_RELOC_PPC_B26: | |
6740 | case BFD_RELOC_PPC_BA26: | |
6741 | case BFD_RELOC_PPC_B16: | |
6742 | case BFD_RELOC_PPC_BA16: | |
6743 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6744 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6745 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6746 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 6747 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
6748 | if (fix->fx_addsy) |
6749 | { | |
6750 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
6751 | elf_symbol_type *elfsym | |
6752 | = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
6753 | gas_assert (elfsym); | |
6754 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6755 | return 0; | |
6756 | } | |
6757 | break; | |
6758 | default: | |
6759 | break; | |
6760 | } | |
6761 | ||
0baf16f2 AM |
6762 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
6763 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
6764 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
6765 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
6766 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
6767 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
334d91b9 AM |
6768 | && fix->fx_r_type != BFD_RELOC_16_GOT_PCREL |
6769 | && fix->fx_r_type != BFD_RELOC_32_GOTOFF | |
6770 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL | |
6771 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
6772 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
6773 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
6774 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
6775 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
6776 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
6777 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
6778 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
6779 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 | |
6780 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
6781 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
6782 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
6783 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
6784 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 6785 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
6786 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
6787 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
6788 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
6789 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
6790 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 6791 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
ab1e9ef7 | 6792 | && fix->fx_r_type <= BFD_RELOC_PPC64_DTPREL16_HIGHESTA)); |
252b5132 | 6793 | } |
0baf16f2 | 6794 | #endif |
252b5132 | 6795 | |
b9c361e0 JL |
6796 | void |
6797 | ppc_frag_check (struct frag *fragP) | |
6798 | { | |
a9479dc0 AM |
6799 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
6800 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6801 | _("instruction address is not a multiple of %d"), | |
6802 | fragP->insn_addr + 1); | |
b9c361e0 JL |
6803 | } |
6804 | ||
3aeeedbb AM |
6805 | /* Implement HANDLE_ALIGN. This writes the NOP pattern into an |
6806 | rs_align_code frag. */ | |
6807 | ||
6808 | void | |
6809 | ppc_handle_align (struct frag *fragP) | |
6810 | { | |
6811 | valueT count = (fragP->fr_next->fr_address | |
6812 | - (fragP->fr_address + fragP->fr_fix)); | |
6813 | ||
f7d69005 | 6814 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && count != 0 && (count & 1) == 0) |
b9c361e0 JL |
6815 | { |
6816 | char *dest = fragP->fr_literal + fragP->fr_fix; | |
6817 | ||
6818 | fragP->fr_var = 2; | |
6819 | md_number_to_chars (dest, 0x4400, 2); | |
6820 | } | |
6821 | else if (count != 0 && (count & 3) == 0) | |
3aeeedbb AM |
6822 | { |
6823 | char *dest = fragP->fr_literal + fragP->fr_fix; | |
6824 | ||
6825 | fragP->fr_var = 4; | |
cef4f754 AM |
6826 | |
6827 | if (count > 4 * nop_limit && count < 0x2000000) | |
6828 | { | |
6829 | struct frag *rest; | |
6830 | ||
6831 | /* Make a branch, then follow with nops. Insert another | |
6832 | frag to handle the nops. */ | |
6833 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
6834 | count -= 4; | |
6835 | if (count == 0) | |
6836 | return; | |
6837 | ||
6838 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6839 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
6840 | fragP->fr_next = rest; | |
6841 | fragP = rest; | |
6842 | rest->fr_address += rest->fr_fix + 4; | |
6843 | rest->fr_fix = 0; | |
6844 | /* If we leave the next frag as rs_align_code we'll come here | |
6845 | again, resulting in a bunch of branches rather than a | |
6846 | branch followed by nops. */ | |
6847 | rest->fr_type = rs_align; | |
6848 | dest = rest->fr_literal; | |
6849 | } | |
6850 | ||
3aeeedbb AM |
6851 | md_number_to_chars (dest, 0x60000000, 4); |
6852 | ||
42240548 | 6853 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0 |
6a7524c6 | 6854 | && (ppc_cpu & PPC_OPCODE_POWER9) == 0) |
3aeeedbb | 6855 | { |
3fea0c3b AM |
6856 | /* For power6, power7, and power8, we want the last nop to |
6857 | be a group terminating one. Do this by inserting an | |
6858 | rs_fill frag immediately after this one, with its address | |
6859 | set to the last nop location. This will automatically | |
6860 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
6861 | if (count > 4) |
6862 | { | |
6863 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6864 | ||
6865 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
6866 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
6867 | group_nop->fr_fix = 0; | |
6868 | group_nop->fr_offset = 1; | |
6869 | group_nop->fr_type = rs_fill; | |
6870 | fragP->fr_next = group_nop; | |
6871 | dest = group_nop->fr_literal; | |
6872 | } | |
6873 | ||
6a7524c6 | 6874 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) |
aea77599 AM |
6875 | { |
6876 | if (ppc_cpu & PPC_OPCODE_E500MC) | |
6877 | /* e500mc group terminating nop: "ori 0,0,0". */ | |
6878 | md_number_to_chars (dest, 0x60000000, 4); | |
6879 | else | |
3fea0c3b | 6880 | /* power7/power8 group terminating nop: "ori 2,2,0". */ |
aea77599 AM |
6881 | md_number_to_chars (dest, 0x60420000, 4); |
6882 | } | |
42240548 PB |
6883 | else |
6884 | /* power6 group terminating nop: "ori 1,1,0". */ | |
6885 | md_number_to_chars (dest, 0x60210000, 4); | |
3aeeedbb AM |
6886 | } |
6887 | } | |
6888 | } | |
6889 | ||
252b5132 | 6890 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 6891 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 6892 | |
94f592af | 6893 | void |
62ebcb5c | 6894 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 6895 | { |
94f592af | 6896 | valueT value = * valP; |
5656a981 AM |
6897 | offsetT fieldval; |
6898 | const struct powerpc_operand *operand; | |
252b5132 RH |
6899 | |
6900 | #ifdef OBJ_ELF | |
94f592af | 6901 | if (fixP->fx_addsy != NULL) |
252b5132 | 6902 | { |
a161fe53 | 6903 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
6904 | if (fixP->fx_pcrel) |
6905 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
6906 | |
6907 | if (fixP->fx_addsy == abs_section_sym) | |
6908 | fixP->fx_done = 1; | |
252b5132 RH |
6909 | } |
6910 | else | |
94f592af | 6911 | fixP->fx_done = 1; |
252b5132 | 6912 | #else |
a161fe53 | 6913 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
6914 | the symbol values. If we are doing this relocation the code in |
6915 | write.c is going to call bfd_install_relocation, which is also | |
6916 | going to use the symbol value. That means that if the reloc is | |
6917 | fully resolved we want to use *valP since bfd_install_relocation is | |
6918 | not being used. | |
9f0eb232 RS |
6919 | However, if the reloc is not fully resolved we do not want to |
6920 | use *valP, and must use fx_offset instead. If the relocation | |
6921 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
6922 | to this new relocation value. */ | |
94f592af NC |
6923 | if (fixP->fx_addsy == (symbolS *) NULL) |
6924 | fixP->fx_done = 1; | |
6925 | ||
252b5132 | 6926 | else |
9f0eb232 RS |
6927 | { |
6928 | value = fixP->fx_offset; | |
6929 | if (fixP->fx_pcrel) | |
6930 | value -= md_pcrel_from_section (fixP, seg); | |
6931 | } | |
a161fe53 AM |
6932 | #endif |
6933 | ||
7ba71655 AM |
6934 | /* We are only able to convert some relocs to pc-relative. */ |
6935 | if (fixP->fx_pcrel) | |
6936 | { | |
6937 | switch (fixP->fx_r_type) | |
6938 | { | |
4a969973 AM |
6939 | case BFD_RELOC_64: |
6940 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6941 | break; | |
6942 | ||
6943 | case BFD_RELOC_32: | |
6944 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
6945 | break; | |
6946 | ||
6947 | case BFD_RELOC_16: | |
6948 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6949 | break; | |
6950 | ||
7ba71655 AM |
6951 | case BFD_RELOC_LO16: |
6952 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
6953 | break; | |
6954 | ||
6955 | case BFD_RELOC_HI16: | |
6956 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
6957 | break; | |
6958 | ||
6959 | case BFD_RELOC_HI16_S: | |
6960 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
6961 | break; | |
6962 | ||
4a969973 AM |
6963 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
6964 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
6965 | break; |
6966 | ||
4a969973 AM |
6967 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
6968 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
6969 | break; |
6970 | ||
4a969973 AM |
6971 | case BFD_RELOC_PPC64_HIGHER: |
6972 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
6973 | break; | |
6974 | ||
6975 | case BFD_RELOC_PPC64_HIGHER_S: | |
6976 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
6977 | break; | |
6978 | ||
6979 | case BFD_RELOC_PPC64_HIGHEST: | |
6980 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
6981 | break; | |
6982 | ||
6983 | case BFD_RELOC_PPC64_HIGHEST_S: | |
6984 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
6985 | break; |
6986 | ||
6987 | case BFD_RELOC_PPC_16DX_HA: | |
6988 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6989 | break; | |
6990 | ||
6991 | default: | |
6992 | break; | |
6993 | } | |
6994 | } | |
6995 | else if (!fixP->fx_done | |
6996 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 6997 | { |
7ba71655 AM |
6998 | /* addpcis is relative to next insn address. */ |
6999 | value -= 4; | |
7000 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7001 | fixP->fx_pcrel = 1; | |
252b5132 | 7002 | } |
252b5132 | 7003 | |
5656a981 | 7004 | operand = NULL; |
3b8b57a9 | 7005 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 7006 | { |
5656a981 | 7007 | /* This is a fixup on an instruction. */ |
3b8b57a9 | 7008 | int opindex = fixP->fx_pcrel_adjust & 0xff; |
252b5132 | 7009 | |
5656a981 | 7010 | operand = &powerpc_operands[opindex]; |
252b5132 | 7011 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
7012 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
7013 | does not generate a reloc. It uses the offset of `sym' within its | |
7014 | csect. Other usages, such as `.long sym', generate relocs. This | |
7015 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 7016 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 7017 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 7018 | && operand->shift == 0 |
2b3c4602 | 7019 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
7020 | && fixP->fx_addsy != NULL |
7021 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
96d56e9f NC |
7022 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC |
7023 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC0 | |
94f592af | 7024 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 7025 | { |
94f592af NC |
7026 | value = fixP->fx_offset; |
7027 | fixP->fx_done = 1; | |
252b5132 | 7028 | } |
ac21e7da TG |
7029 | |
7030 | /* During parsing of instructions, a TOC16 reloc is generated for | |
7031 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
7032 | in the toc. But at parse time, SYM may be not yet defined, so | |
7033 | check again here. */ | |
7034 | if (fixP->fx_r_type == BFD_RELOC_16 | |
7035 | && fixP->fx_addsy != NULL | |
7036 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
7037 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; | |
252b5132 | 7038 | #endif |
5656a981 AM |
7039 | } |
7040 | ||
7041 | /* Calculate value to be stored in field. */ | |
7042 | fieldval = value; | |
7043 | switch (fixP->fx_r_type) | |
7044 | { | |
1ec2d25e | 7045 | #ifdef OBJ_ELF |
5656a981 AM |
7046 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
7047 | case BFD_RELOC_PPC_VLE_LO16A: | |
7048 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 7049 | #endif |
5656a981 AM |
7050 | case BFD_RELOC_LO16: |
7051 | case BFD_RELOC_LO16_PCREL: | |
7052 | fieldval = value & 0xffff; | |
7053 | sign_extend_16: | |
7054 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 7055 | fieldval = SEX16 (fieldval); |
5656a981 AM |
7056 | fixP->fx_no_overflow = 1; |
7057 | break; | |
3c9d25f4 | 7058 | |
f9c6b907 AM |
7059 | case BFD_RELOC_HI16: |
7060 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 7061 | #ifdef OBJ_ELF |
f9c6b907 AM |
7062 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7063 | { | |
7064 | fieldval = value >> 16; | |
7065 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7066 | { | |
7067 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7068 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7069 | } | |
7070 | break; | |
7071 | } | |
2b0f3761 | 7072 | /* Fallthru */ |
f9c6b907 | 7073 | |
5656a981 AM |
7074 | case BFD_RELOC_PPC_VLE_HI16A: |
7075 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 7076 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 7077 | #endif |
5656a981 AM |
7078 | fieldval = PPC_HI (value); |
7079 | goto sign_extend_16; | |
0baf16f2 | 7080 | |
f9c6b907 AM |
7081 | case BFD_RELOC_HI16_S: |
7082 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 7083 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 7084 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 7085 | #ifdef OBJ_ELF |
f9c6b907 AM |
7086 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7087 | { | |
7088 | fieldval = (value + 0x8000) >> 16; | |
7089 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7090 | { | |
7091 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7092 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7093 | } | |
7094 | break; | |
7095 | } | |
2b0f3761 | 7096 | /* Fallthru */ |
f9c6b907 | 7097 | |
5656a981 AM |
7098 | case BFD_RELOC_PPC_VLE_HA16A: |
7099 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 7100 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 7101 | #endif |
5656a981 AM |
7102 | fieldval = PPC_HA (value); |
7103 | goto sign_extend_16; | |
0baf16f2 | 7104 | |
3b8b57a9 | 7105 | #ifdef OBJ_ELF |
5656a981 AM |
7106 | case BFD_RELOC_PPC64_HIGHER: |
7107 | fieldval = PPC_HIGHER (value); | |
7108 | goto sign_extend_16; | |
252b5132 | 7109 | |
5656a981 AM |
7110 | case BFD_RELOC_PPC64_HIGHER_S: |
7111 | fieldval = PPC_HIGHERA (value); | |
7112 | goto sign_extend_16; | |
0baf16f2 | 7113 | |
5656a981 AM |
7114 | case BFD_RELOC_PPC64_HIGHEST: |
7115 | fieldval = PPC_HIGHEST (value); | |
7116 | goto sign_extend_16; | |
0baf16f2 | 7117 | |
5656a981 AM |
7118 | case BFD_RELOC_PPC64_HIGHEST_S: |
7119 | fieldval = PPC_HIGHESTA (value); | |
7120 | goto sign_extend_16; | |
7121 | #endif | |
7122 | ||
7123 | default: | |
7124 | break; | |
7125 | } | |
7126 | ||
7127 | if (operand != NULL) | |
7128 | { | |
7129 | /* Handle relocs in an insn. */ | |
5656a981 AM |
7130 | switch (fixP->fx_r_type) |
7131 | { | |
7fa9fcb6 | 7132 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7133 | /* The following relocs can't be calculated by the assembler. |
7134 | Leave the field zero. */ | |
cdba85ec AM |
7135 | case BFD_RELOC_PPC_TPREL16: |
7136 | case BFD_RELOC_PPC_TPREL16_LO: | |
7137 | case BFD_RELOC_PPC_TPREL16_HI: | |
7138 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
7139 | case BFD_RELOC_PPC_DTPREL16: |
7140 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7141 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7142 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
7143 | case BFD_RELOC_PPC_GOT_TLSGD16: |
7144 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7145 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7146 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7147 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7148 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7149 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7150 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7151 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7152 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7153 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7154 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7155 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7156 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7157 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7158 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7159 | case BFD_RELOC_PPC64_TPREL16_DS: | |
7160 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
7161 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7162 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
7163 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7164 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7165 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7166 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
7167 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7168 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
7169 | case BFD_RELOC_PPC64_DTPREL16_DS: |
7170 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
7171 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
7172 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7173 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7174 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
3b8b57a9 | 7175 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 7176 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 7177 | fieldval = 0; |
cdba85ec | 7178 | break; |
3b8b57a9 AM |
7179 | |
7180 | /* These also should leave the field zero for the same | |
7181 | reason. Note that older versions of gas wrote values | |
7182 | here. If we want to go back to the old behaviour, then | |
7183 | all _LO and _LO_DS cases will need to be treated like | |
7184 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
7185 | case BFD_RELOC_16_GOTOFF: | |
7186 | case BFD_RELOC_LO16_GOTOFF: | |
7187 | case BFD_RELOC_HI16_GOTOFF: | |
7188 | case BFD_RELOC_HI16_S_GOTOFF: | |
7189 | case BFD_RELOC_LO16_PLTOFF: | |
7190 | case BFD_RELOC_HI16_PLTOFF: | |
7191 | case BFD_RELOC_HI16_S_PLTOFF: | |
7192 | case BFD_RELOC_GPREL16: | |
7193 | case BFD_RELOC_16_BASEREL: | |
7194 | case BFD_RELOC_LO16_BASEREL: | |
7195 | case BFD_RELOC_HI16_BASEREL: | |
7196 | case BFD_RELOC_HI16_S_BASEREL: | |
7197 | case BFD_RELOC_PPC_TOC16: | |
7198 | case BFD_RELOC_PPC64_TOC16_LO: | |
7199 | case BFD_RELOC_PPC64_TOC16_HI: | |
7200 | case BFD_RELOC_PPC64_TOC16_HA: | |
7201 | case BFD_RELOC_PPC64_PLTGOT16: | |
7202 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
7203 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
7204 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
7205 | case BFD_RELOC_PPC64_GOT16_DS: | |
7206 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
7207 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
7208 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
7209 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
7210 | case BFD_RELOC_PPC64_TOC16_DS: | |
7211 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
7212 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
7213 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
7214 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7215 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7216 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7217 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7218 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7219 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7220 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 7221 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
7222 | case BFD_RELOC_PPC_EMB_MRKREF: |
7223 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7224 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7225 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7226 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7227 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7228 | case BFD_RELOC_PPC_EMB_RELSDA: | |
7229 | case BFD_RELOC_PPC_VLE_SDA21: | |
7230 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7231 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7232 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
7233 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7234 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
7235 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7236 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
7237 | gas_assert (fixP->fx_addsy != NULL); | |
2b0f3761 | 7238 | /* Fallthru */ |
3b8b57a9 AM |
7239 | |
7240 | case BFD_RELOC_PPC_TLS: | |
7241 | case BFD_RELOC_PPC_TLSGD: | |
7242 | case BFD_RELOC_PPC_TLSLD: | |
7243 | fieldval = 0; | |
3b8b57a9 | 7244 | break; |
7fa9fcb6 TG |
7245 | #endif |
7246 | ||
7247 | #ifdef OBJ_XCOFF | |
7248 | case BFD_RELOC_PPC_B16: | |
7249 | /* Adjust the offset to the instruction boundary. */ | |
7250 | fieldval += 2; | |
7251 | break; | |
7252 | #endif | |
252b5132 | 7253 | |
f728387b AM |
7254 | case BFD_RELOC_VTABLE_INHERIT: |
7255 | case BFD_RELOC_VTABLE_ENTRY: | |
7256 | case BFD_RELOC_PPC_DTPMOD: | |
7257 | case BFD_RELOC_PPC_TPREL: | |
7258 | case BFD_RELOC_PPC_DTPREL: | |
7259 | case BFD_RELOC_PPC_COPY: | |
7260 | case BFD_RELOC_PPC_GLOB_DAT: | |
7261 | case BFD_RELOC_32_PLT_PCREL: | |
7262 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7263 | case BFD_RELOC_PPC64_TOC: | |
7264 | case BFD_RELOC_CTOR: | |
7265 | case BFD_RELOC_32: | |
7266 | case BFD_RELOC_32_PCREL: | |
7267 | case BFD_RELOC_RVA: | |
7268 | case BFD_RELOC_64: | |
7269 | case BFD_RELOC_64_PCREL: | |
7270 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
7271 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7272 | _("%s unsupported as instruction fixup"), | |
7273 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7274 | fixP->fx_done = 1; | |
7275 | return; | |
7276 | ||
3b8b57a9 | 7277 | default: |
252b5132 | 7278 | break; |
3b8b57a9 | 7279 | } |
252b5132 | 7280 | |
3b8b57a9 AM |
7281 | #ifdef OBJ_ELF |
7282 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
7283 | contents can stay at zero. */ | |
7284 | #define APPLY_RELOC fixP->fx_done | |
7285 | #else | |
7286 | #define APPLY_RELOC 1 | |
7287 | #endif | |
7288 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) | |
7289 | { | |
487b24d8 AM |
7290 | unsigned long insn; |
7291 | unsigned char *where; | |
7292 | ||
3b8b57a9 AM |
7293 | /* Fetch the instruction, insert the fully resolved operand |
7294 | value, and stuff the instruction back again. */ | |
487b24d8 | 7295 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 7296 | if (target_big_endian) |
31a91399 | 7297 | { |
3b8b57a9 | 7298 | if (fixP->fx_size == 4) |
487b24d8 | 7299 | insn = bfd_getb32 (where); |
31a91399 | 7300 | else |
487b24d8 | 7301 | insn = bfd_getb16 (where); |
31a91399 NC |
7302 | } |
7303 | else | |
3b8b57a9 AM |
7304 | { |
7305 | if (fixP->fx_size == 4) | |
487b24d8 | 7306 | insn = bfd_getl32 (where); |
3b8b57a9 | 7307 | else |
487b24d8 | 7308 | insn = bfd_getl16 (where); |
3b8b57a9 AM |
7309 | } |
7310 | insn = ppc_insert_operand (insn, operand, fieldval, | |
7311 | fixP->tc_fix_data.ppc_cpu, | |
7312 | fixP->fx_file, fixP->fx_line); | |
7313 | if (target_big_endian) | |
7314 | { | |
7315 | if (fixP->fx_size == 4) | |
487b24d8 | 7316 | bfd_putb32 (insn, where); |
3b8b57a9 | 7317 | else |
487b24d8 | 7318 | bfd_putb16 (insn, where); |
3b8b57a9 AM |
7319 | } |
7320 | else | |
7321 | { | |
7322 | if (fixP->fx_size == 4) | |
487b24d8 | 7323 | bfd_putl32 (insn, where); |
3b8b57a9 | 7324 | else |
487b24d8 | 7325 | bfd_putl16 (insn, where); |
3b8b57a9 AM |
7326 | } |
7327 | } | |
7328 | ||
7329 | if (fixP->fx_done) | |
7330 | /* Nothing else to do here. */ | |
7331 | return; | |
7332 | ||
7333 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 7334 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 7335 | { |
3b4dbbbf | 7336 | const char *sfile; |
3b8b57a9 AM |
7337 | unsigned int sline; |
7338 | ||
7339 | /* Use expr_symbol_where to see if this is an expression | |
7340 | symbol. */ | |
7341 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
7342 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7343 | _("unresolved expression that must be resolved")); | |
7344 | else | |
7345 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7346 | _("unsupported relocation against %s"), | |
7347 | S_GET_NAME (fixP->fx_addsy)); | |
7348 | fixP->fx_done = 1; | |
7349 | return; | |
7350 | } | |
7351 | } | |
7352 | else | |
7353 | { | |
7354 | /* Handle relocs in data. */ | |
7355 | switch (fixP->fx_r_type) | |
7356 | { | |
252b5132 | 7357 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
7358 | if (fixP->fx_addsy |
7359 | && !S_IS_DEFINED (fixP->fx_addsy) | |
7360 | && !S_IS_WEAK (fixP->fx_addsy)) | |
7361 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 7362 | /* Fallthru */ |
252b5132 RH |
7363 | |
7364 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 7365 | fixP->fx_done = 0; |
252b5132 RH |
7366 | break; |
7367 | ||
0baf16f2 | 7368 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7369 | /* These can appear with @l etc. in data. */ |
7370 | case BFD_RELOC_LO16: | |
3b8b57a9 | 7371 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 7372 | case BFD_RELOC_HI16: |
3b8b57a9 | 7373 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 7374 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 7375 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 7376 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 7377 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 7378 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 7379 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
7380 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7381 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 7382 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
7383 | break; |
7384 | ||
7385 | case BFD_RELOC_PPC_DTPMOD: | |
7386 | case BFD_RELOC_PPC_TPREL: | |
7387 | case BFD_RELOC_PPC_DTPREL: | |
7388 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7389 | break; | |
7390 | ||
7391 | /* Just punt all of these to the linker. */ | |
7392 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7393 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7394 | case BFD_RELOC_16_GOTOFF: | |
7395 | case BFD_RELOC_LO16_GOTOFF: | |
7396 | case BFD_RELOC_HI16_GOTOFF: | |
7397 | case BFD_RELOC_HI16_S_GOTOFF: | |
7398 | case BFD_RELOC_LO16_PLTOFF: | |
7399 | case BFD_RELOC_HI16_PLTOFF: | |
7400 | case BFD_RELOC_HI16_S_PLTOFF: | |
7401 | case BFD_RELOC_PPC_COPY: | |
7402 | case BFD_RELOC_PPC_GLOB_DAT: | |
7403 | case BFD_RELOC_16_BASEREL: | |
7404 | case BFD_RELOC_LO16_BASEREL: | |
7405 | case BFD_RELOC_HI16_BASEREL: | |
7406 | case BFD_RELOC_HI16_S_BASEREL: | |
7407 | case BFD_RELOC_PPC_TLS: | |
7408 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7409 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7410 | case BFD_RELOC_PPC_DTPREL16_HA: | |
7411 | case BFD_RELOC_PPC_TPREL16_LO: | |
7412 | case BFD_RELOC_PPC_TPREL16_HI: | |
7413 | case BFD_RELOC_PPC_TPREL16_HA: | |
7414 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
7415 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7416 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7417 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7418 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7419 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7420 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7421 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7422 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7423 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7424 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7425 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7426 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7427 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7428 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7429 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7430 | case BFD_RELOC_24_PLT_PCREL: | |
7431 | case BFD_RELOC_PPC_LOCAL24PC: | |
7432 | case BFD_RELOC_32_PLT_PCREL: | |
7433 | case BFD_RELOC_GPREL16: | |
7434 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7435 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7436 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7437 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7438 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7439 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7440 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7441 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7442 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7443 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
7444 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7445 | case BFD_RELOC_PPC_EMB_SDA21: | |
7446 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7447 | case BFD_RELOC_PPC_EMB_MRKREF: | |
7448 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7449 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7450 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7451 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7452 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7453 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 7454 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 AM |
7455 | case BFD_RELOC_PPC_TOC16: |
7456 | case BFD_RELOC_PPC64_TOC16_LO: | |
7457 | case BFD_RELOC_PPC64_TOC16_HI: | |
7458 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
7459 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7460 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
7461 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
7462 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7463 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7464 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
7465 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7466 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
7467 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7468 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7469 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7470 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
94f592af | 7471 | fixP->fx_done = 0; |
0baf16f2 | 7472 | break; |
0baf16f2 | 7473 | #endif |
3b8b57a9 AM |
7474 | |
7475 | #ifdef OBJ_XCOFF | |
7476 | case BFD_RELOC_NONE: | |
3b8b57a9 | 7477 | #endif |
5656a981 AM |
7478 | case BFD_RELOC_CTOR: |
7479 | case BFD_RELOC_32: | |
7480 | case BFD_RELOC_32_PCREL: | |
7481 | case BFD_RELOC_RVA: | |
7482 | case BFD_RELOC_64: | |
7483 | case BFD_RELOC_64_PCREL: | |
7484 | case BFD_RELOC_16: | |
7485 | case BFD_RELOC_16_PCREL: | |
7486 | case BFD_RELOC_8: | |
7487 | break; | |
3b8b57a9 | 7488 | |
252b5132 | 7489 | default: |
bc805888 | 7490 | fprintf (stderr, |
94f592af | 7491 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7492 | fflush (stderr); |
252b5132 RH |
7493 | abort (); |
7494 | } | |
46b596ff | 7495 | |
5656a981 | 7496 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7497 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7498 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7499 | if (warn_476 |
7500 | && (seg->flags & SEC_CODE) != 0 | |
7501 | && fixP->fx_size == 4 | |
7502 | && fixP->fx_done | |
7503 | && !fixP->fx_tcbit | |
7504 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7505 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7506 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7507 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7508 | _("data in executable section")); | |
5656a981 AM |
7509 | } |
7510 | ||
252b5132 | 7511 | #ifdef OBJ_ELF |
3b8b57a9 | 7512 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7513 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7514 | |
7515 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7516 | from the section contents. If we are going to be emitting a reloc | |
7517 | then the section contents are immaterial, so don't warn if they | |
7518 | happen to overflow. Leave such warnings to ld. */ | |
7519 | if (!fixP->fx_done) | |
a38a07e0 AM |
7520 | { |
7521 | fixP->fx_no_overflow = 1; | |
7522 | ||
7523 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7524 | but .TOC.@tocbase. */ | |
7525 | if (ppc_obj64 | |
7526 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7527 | && fixP->fx_addsy != NULL | |
7528 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7529 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7530 | } | |
252b5132 | 7531 | #else |
94f592af NC |
7532 | if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16) |
7533 | fixP->fx_addnumber = 0; | |
252b5132 RH |
7534 | else |
7535 | { | |
7536 | #ifdef TE_PE | |
94f592af | 7537 | fixP->fx_addnumber = 0; |
252b5132 | 7538 | #else |
8edcbfcd TG |
7539 | /* We want to use the offset within the toc, not the actual VMA |
7540 | of the symbol. */ | |
94f592af | 7541 | fixP->fx_addnumber = |
8edcbfcd TG |
7542 | - bfd_get_section_vma (stdoutput, S_GET_SEGMENT (fixP->fx_addsy)) |
7543 | - S_GET_VALUE (ppc_toc_csect); | |
ac21e7da TG |
7544 | /* Set *valP to avoid errors. */ |
7545 | *valP = value; | |
252b5132 RH |
7546 | #endif |
7547 | } | |
7548 | #endif | |
252b5132 RH |
7549 | } |
7550 | ||
7551 | /* Generate a reloc for a fixup. */ | |
7552 | ||
7553 | arelent * | |
98027b10 | 7554 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
7555 | { |
7556 | arelent *reloc; | |
7557 | ||
325801bd | 7558 | reloc = XNEW (arelent); |
252b5132 | 7559 | |
325801bd | 7560 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7561 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
7562 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
7563 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
7564 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7565 | { | |
7566 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7567 | _("reloc %d not supported by object file format"), |
7568 | (int) fixp->fx_r_type); | |
252b5132 RH |
7569 | return NULL; |
7570 | } | |
7571 | reloc->addend = fixp->fx_addnumber; | |
7572 | ||
7573 | return reloc; | |
7574 | } | |
75e21f08 JJ |
7575 | |
7576 | void | |
98027b10 | 7577 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7578 | { |
7579 | cfi_add_CFA_def_cfa (1, 0); | |
7580 | } | |
7581 | ||
7582 | int | |
1df69f4f | 7583 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7584 | { |
7585 | unsigned int regnum = -1; | |
7586 | unsigned int i; | |
7587 | const char *p; | |
7588 | char *q; | |
e0471c16 | 7589 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7590 | { |
7591 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7592 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7593 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7594 | { "spe_acc", 111 }, { "spefscr", 112 } |
7595 | }; | |
7596 | ||
7597 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7598 | if (strcmp (regnames[i].name, regname) == 0) | |
7599 | return regnames[i].dw2regnum; | |
7600 | ||
7601 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7602 | { | |
7603 | p = regname + 1 + (regname[1] == '.'); | |
7604 | regnum = strtoul (p, &q, 10); | |
7605 | if (p == q || *q || regnum >= 32) | |
7606 | return -1; | |
7607 | if (regname[0] == 'f') | |
b7d7dc63 | 7608 | regnum += 32; |
75e21f08 | 7609 | else if (regname[0] == 'v') |
b7d7dc63 | 7610 | regnum += 77; |
75e21f08 JJ |
7611 | } |
7612 | else if (regname[0] == 'c' && regname[1] == 'r') | |
7613 | { | |
7614 | p = regname + 2 + (regname[2] == '.'); | |
7615 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 7616 | return -1; |
75e21f08 JJ |
7617 | regnum = p[0] - '0' + 68; |
7618 | } | |
7619 | return regnum; | |
7620 | } |