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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
b3adc24a | 2 | Copyright (C) 2011-2020 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
1080bf78 | 32 | #include "bfd/elfxx-riscv.h" |
e23eba97 NC |
33 | #include "elf/riscv.h" |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
45 | /* The encoded instruction bits. */ | |
46 | insn_t insn_opcode; | |
47 | ||
48 | /* The frag that contains the instruction. */ | |
49 | struct frag *frag; | |
50 | ||
51 | /* The offset into FRAG of the first instruction byte. */ | |
52 | long where; | |
53 | ||
54 | /* The relocs associated with the instruction, if any. */ | |
55 | fixS *fixp; | |
56 | }; | |
57 | ||
58 | #ifndef DEFAULT_ARCH | |
59 | #define DEFAULT_ARCH "riscv64" | |
60 | #endif | |
61 | ||
2dc8dd17 JW |
62 | #ifndef DEFAULT_RISCV_ATTR |
63 | #define DEFAULT_RISCV_ATTR 0 | |
64 | #endif | |
65 | ||
e23eba97 NC |
66 | static const char default_arch[] = DEFAULT_ARCH; |
67 | ||
2922d21d AW |
68 | static unsigned xlen = 0; /* width of an x-register */ |
69 | static unsigned abi_xlen = 0; /* width of a pointer in the ABI */ | |
7f999549 | 70 | static bfd_boolean rve_abi = FALSE; |
e23eba97 | 71 | |
2922d21d | 72 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
73 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
74 | ||
75 | static unsigned elf_flags = 0; | |
76 | ||
77 | /* This is the set of options which the .option pseudo-op may modify. */ | |
78 | ||
79 | struct riscv_set_options | |
80 | { | |
81 | int pic; /* Generate position-independent code. */ | |
82 | int rvc; /* Generate RVC code. */ | |
7f999549 | 83 | int rve; /* Generate RVE code. */ |
45f76423 | 84 | int relax; /* Emit relocs the linker is allowed to relax. */ |
2dc8dd17 | 85 | int arch_attr; /* Emit arch attribute. */ |
2ca89224 | 86 | int csr_check; /* Enable the CSR checking. */ |
e23eba97 NC |
87 | }; |
88 | ||
89 | static struct riscv_set_options riscv_opts = | |
90 | { | |
91 | 0, /* pic */ | |
92 | 0, /* rvc */ | |
7f999549 | 93 | 0, /* rve */ |
45f76423 | 94 | 1, /* relax */ |
2dc8dd17 | 95 | DEFAULT_RISCV_ATTR, /* arch_attr */ |
2ca89224 | 96 | 0. /* csr_check */ |
e23eba97 NC |
97 | }; |
98 | ||
99 | static void | |
100 | riscv_set_rvc (bfd_boolean rvc_value) | |
101 | { | |
102 | if (rvc_value) | |
103 | elf_flags |= EF_RISCV_RVC; | |
104 | ||
105 | riscv_opts.rvc = rvc_value; | |
106 | } | |
107 | ||
7f999549 JW |
108 | static void |
109 | riscv_set_rve (bfd_boolean rve_value) | |
110 | { | |
111 | riscv_opts.rve = rve_value; | |
112 | } | |
113 | ||
1080bf78 | 114 | static riscv_subset_list_t riscv_subsets; |
e23eba97 NC |
115 | |
116 | static bfd_boolean | |
1080bf78 | 117 | riscv_subset_supports (const char *feature) |
e23eba97 | 118 | { |
1080bf78 JW |
119 | if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0)) |
120 | return TRUE; | |
e23eba97 | 121 | |
1080bf78 | 122 | return riscv_lookup_subset (&riscv_subsets, feature) != NULL; |
e23eba97 NC |
123 | } |
124 | ||
43135d3b | 125 | static bfd_boolean |
7e9ad3a3 | 126 | riscv_multi_subset_supports (enum riscv_insn_class insn_class) |
43135d3b | 127 | { |
7e9ad3a3 JW |
128 | switch (insn_class) |
129 | { | |
130 | case INSN_CLASS_I: return riscv_subset_supports ("i"); | |
131 | case INSN_CLASS_C: return riscv_subset_supports ("c"); | |
132 | case INSN_CLASS_A: return riscv_subset_supports ("a"); | |
133 | case INSN_CLASS_M: return riscv_subset_supports ("m"); | |
134 | case INSN_CLASS_F: return riscv_subset_supports ("f"); | |
135 | case INSN_CLASS_D: return riscv_subset_supports ("d"); | |
136 | case INSN_CLASS_D_AND_C: | |
137 | return riscv_subset_supports ("d") && riscv_subset_supports ("c"); | |
138 | ||
139 | case INSN_CLASS_F_AND_C: | |
140 | return riscv_subset_supports ("f") && riscv_subset_supports ("c"); | |
43135d3b | 141 | |
7e9ad3a3 | 142 | case INSN_CLASS_Q: return riscv_subset_supports ("q"); |
43135d3b | 143 | |
7e9ad3a3 JW |
144 | default: |
145 | as_fatal ("Unreachable"); | |
146 | return FALSE; | |
147 | } | |
43135d3b JW |
148 | } |
149 | ||
2922d21d | 150 | /* Set which ISA and extensions are available. */ |
e23eba97 | 151 | |
e23eba97 | 152 | static void |
2922d21d | 153 | riscv_set_arch (const char *s) |
e23eba97 | 154 | { |
1080bf78 JW |
155 | riscv_parse_subset_t rps; |
156 | rps.subset_list = &riscv_subsets; | |
157 | rps.error_handler = as_fatal; | |
158 | rps.xlen = &xlen; | |
7f999549 | 159 | |
1080bf78 JW |
160 | riscv_release_subset_list (&riscv_subsets); |
161 | riscv_parse_subset (&rps, s); | |
e23eba97 NC |
162 | } |
163 | ||
164 | /* Handle of the OPCODE hash table. */ | |
165 | static struct hash_control *op_hash = NULL; | |
166 | ||
0e35537d JW |
167 | /* Handle of the type of .insn hash table. */ |
168 | static struct hash_control *insn_type_hash = NULL; | |
169 | ||
e23eba97 NC |
170 | /* This array holds the chars that always start a comment. If the |
171 | pre-processor is disabled, these aren't very useful */ | |
172 | const char comment_chars[] = "#"; | |
173 | ||
174 | /* This array holds the chars that only start a comment at the beginning of | |
175 | a line. If the line seems to have the form '# 123 filename' | |
176 | .line and .file directives will appear in the pre-processed output */ | |
177 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
178 | first line of the input file. This is because the compiler outputs | |
179 | #NO_APP at the beginning of its output. */ | |
180 | /* Also note that C style comments are always supported. */ | |
181 | const char line_comment_chars[] = "#"; | |
182 | ||
183 | /* This array holds machine specific line separator characters. */ | |
184 | const char line_separator_chars[] = ";"; | |
185 | ||
186 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
187 | const char EXP_CHARS[] = "eE"; | |
188 | ||
189 | /* Chars that mean this number is a floating point constant */ | |
190 | /* As in 0f12.456 */ | |
191 | /* or 0d1.2345e12 */ | |
192 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
193 | ||
2dc8dd17 JW |
194 | /* Indicate we are already assemble any instructions or not. */ |
195 | static bfd_boolean start_assemble = FALSE; | |
196 | ||
197 | /* Indicate arch attribute is explictly set. */ | |
198 | static bfd_boolean explicit_arch_attr = FALSE; | |
199 | ||
e23eba97 NC |
200 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ |
201 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
202 | ((relax_substateT) \ | |
203 | (0xc0000000 \ | |
204 | | ((uncond) ? 1 : 0) \ | |
205 | | ((rvc) ? 2 : 0) \ | |
206 | | ((length) << 2))) | |
207 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
208 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
209 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
210 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
211 | ||
212 | /* Is the given value a sign-extended 32-bit value? */ | |
213 | #define IS_SEXT_32BIT_NUM(x) \ | |
214 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
215 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
216 | ||
217 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
218 | #define IS_ZEXT_32BIT_NUM(x) \ | |
219 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
220 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
221 | ||
222 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
223 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
224 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
225 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
226 | ||
227 | /* Determine if an instruction matches an opcode. */ | |
228 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
229 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
230 | ||
231 | static char *expr_end; | |
232 | ||
233 | /* The default target format to use. */ | |
234 | ||
235 | const char * | |
236 | riscv_target_format (void) | |
237 | { | |
238 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
239 | } | |
240 | ||
241 | /* Return the length of instruction INSN. */ | |
242 | ||
243 | static inline unsigned int | |
244 | insn_length (const struct riscv_cl_insn *insn) | |
245 | { | |
246 | return riscv_insn_length (insn->insn_opcode); | |
247 | } | |
248 | ||
249 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
250 | ||
251 | static void | |
252 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
253 | { | |
254 | insn->insn_mo = mo; | |
255 | insn->insn_opcode = mo->match; | |
256 | insn->frag = NULL; | |
257 | insn->where = 0; | |
258 | insn->fixp = NULL; | |
259 | } | |
260 | ||
261 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
262 | ||
263 | static void | |
264 | install_insn (const struct riscv_cl_insn *insn) | |
265 | { | |
266 | char *f = insn->frag->fr_literal + insn->where; | |
267 | md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); | |
268 | } | |
269 | ||
270 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
271 | and install the opcode in the new location. */ | |
272 | ||
273 | static void | |
274 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
275 | { | |
276 | insn->frag = frag; | |
277 | insn->where = where; | |
278 | if (insn->fixp != NULL) | |
279 | { | |
280 | insn->fixp->fx_frag = frag; | |
281 | insn->fixp->fx_where = where; | |
282 | } | |
283 | install_insn (insn); | |
284 | } | |
285 | ||
286 | /* Add INSN to the end of the output. */ | |
287 | ||
288 | static void | |
289 | add_fixed_insn (struct riscv_cl_insn *insn) | |
290 | { | |
291 | char *f = frag_more (insn_length (insn)); | |
292 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
293 | } | |
294 | ||
295 | static void | |
296 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
297 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
298 | { | |
299 | frag_grow (max_chars); | |
300 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
301 | frag_var (rs_machine_dependent, max_chars, var, | |
302 | subtype, symbol, offset, NULL); | |
303 | } | |
304 | ||
305 | /* Compute the length of a branch sequence, and adjust the stored length | |
306 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
307 | ||
308 | static unsigned | |
309 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
310 | { | |
311 | int jump, rvc, length = 8; | |
312 | ||
313 | if (!fragp) | |
314 | return length; | |
315 | ||
316 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
317 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
318 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
319 | ||
320 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
321 | length = jump ? 4 : 8; | |
322 | ||
323 | if (fragp->fr_symbol != NULL | |
324 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 325 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
326 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
327 | { | |
328 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
329 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
330 | val -= fragp->fr_address + fragp->fr_fix; | |
331 | ||
332 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
333 | length = 2; | |
334 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
335 | length = 4; | |
336 | else if (!jump && rvc) | |
337 | length = 6; | |
338 | } | |
339 | ||
340 | if (update) | |
341 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
342 | ||
343 | return length; | |
344 | } | |
345 | ||
0e35537d JW |
346 | /* Information about an opcode name, mnemonics and its value. */ |
347 | struct opcode_name_t | |
348 | { | |
349 | const char *name; | |
350 | unsigned int val; | |
351 | }; | |
352 | ||
353 | /* List for all supported opcode name. */ | |
354 | static const struct opcode_name_t opcode_name_list[] = | |
355 | { | |
356 | {"C0", 0x0}, | |
357 | {"C1", 0x1}, | |
358 | {"C2", 0x2}, | |
359 | ||
360 | {"LOAD", 0x03}, | |
361 | {"LOAD_FP", 0x07}, | |
362 | {"CUSTOM_0", 0x0b}, | |
363 | {"MISC_MEM", 0x0f}, | |
364 | {"OP_IMM", 0x13}, | |
365 | {"AUIPC", 0x17}, | |
366 | {"OP_IMM_32", 0x1b}, | |
367 | /* 48b 0x1f. */ | |
368 | ||
369 | {"STORE", 0x23}, | |
370 | {"STORE_FP", 0x27}, | |
371 | {"CUSTOM_1", 0x2b}, | |
372 | {"AMO", 0x2f}, | |
373 | {"OP", 0x33}, | |
374 | {"LUI", 0x37}, | |
375 | {"OP_32", 0x3b}, | |
376 | /* 64b 0x3f. */ | |
377 | ||
378 | {"MADD", 0x43}, | |
379 | {"MSUB", 0x47}, | |
380 | {"NMADD", 0x4f}, | |
381 | {"NMSUB", 0x4b}, | |
382 | {"OP_FP", 0x53}, | |
383 | /*reserved 0x57. */ | |
384 | {"CUSTOM_2", 0x5b}, | |
385 | /* 48b 0x5f. */ | |
386 | ||
387 | {"BRANCH", 0x63}, | |
388 | {"JALR", 0x67}, | |
389 | /*reserved 0x5b. */ | |
390 | {"JAL", 0x6f}, | |
391 | {"SYSTEM", 0x73}, | |
392 | /*reserved 0x77. */ | |
393 | {"CUSTOM_3", 0x7b}, | |
394 | /* >80b 0x7f. */ | |
395 | ||
396 | {NULL, 0} | |
397 | }; | |
398 | ||
399 | /* Hash table for lookup opcode name. */ | |
400 | static struct hash_control *opcode_names_hash = NULL; | |
401 | ||
402 | /* Initialization for hash table of opcode name. */ | |
403 | static void | |
404 | init_opcode_names_hash (void) | |
405 | { | |
406 | const char *retval; | |
407 | const struct opcode_name_t *opcode; | |
408 | ||
409 | for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) | |
410 | { | |
411 | retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode); | |
412 | ||
413 | if (retval != NULL) | |
414 | as_fatal (_("internal error: can't hash `%s': %s"), | |
415 | opcode->name, retval); | |
416 | } | |
417 | } | |
418 | ||
419 | /* Find `s` is a valid opcode name or not, | |
420 | return the opcode name info if found. */ | |
421 | static const struct opcode_name_t * | |
422 | opcode_name_lookup (char **s) | |
423 | { | |
424 | char *e; | |
425 | char save_c; | |
426 | struct opcode_name_t *o; | |
427 | ||
428 | /* Find end of name. */ | |
429 | e = *s; | |
430 | if (is_name_beginner (*e)) | |
431 | ++e; | |
432 | while (is_part_of_name (*e)) | |
433 | ++e; | |
434 | ||
435 | /* Terminate name. */ | |
436 | save_c = *e; | |
437 | *e = '\0'; | |
438 | ||
439 | o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s); | |
440 | ||
441 | /* Advance to next token if one was recognized. */ | |
442 | if (o) | |
443 | *s = e; | |
444 | ||
445 | *e = save_c; | |
446 | expr_end = e; | |
447 | ||
448 | return o; | |
449 | } | |
450 | ||
e23eba97 NC |
451 | enum reg_class |
452 | { | |
453 | RCLASS_GPR, | |
454 | RCLASS_FPR, | |
455 | RCLASS_CSR, | |
456 | RCLASS_MAX | |
457 | }; | |
458 | ||
459 | static struct hash_control *reg_names_hash = NULL; | |
bd0cf5a6 | 460 | static struct hash_control *csr_extra_hash = NULL; |
e23eba97 NC |
461 | |
462 | #define ENCODE_REG_HASH(cls, n) \ | |
463 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
464 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
465 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
466 | ||
467 | static void | |
468 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
469 | { | |
470 | void *hash = ENCODE_REG_HASH (class, n); | |
471 | const char *retval = hash_insert (reg_names_hash, name, hash); | |
472 | ||
473 | if (retval != NULL) | |
474 | as_fatal (_("internal error: can't hash `%s': %s"), name, retval); | |
475 | } | |
476 | ||
477 | static void | |
478 | hash_reg_names (enum reg_class class, const char * const names[], unsigned n) | |
479 | { | |
480 | unsigned i; | |
481 | ||
482 | for (i = 0; i < n; i++) | |
483 | hash_reg_name (class, names[i], i); | |
484 | } | |
485 | ||
bd0cf5a6 NC |
486 | /* All RISC-V CSRs belong to one of these classes. */ |
487 | ||
488 | enum riscv_csr_class | |
489 | { | |
490 | CSR_CLASS_NONE, | |
491 | ||
492 | CSR_CLASS_I, | |
493 | CSR_CLASS_I_32, /* rv32 only */ | |
494 | CSR_CLASS_F, /* f-ext only */ | |
495 | }; | |
496 | ||
497 | /* This structure holds all restricted conditions for a CSR. */ | |
498 | ||
499 | struct riscv_csr_extra | |
500 | { | |
501 | /* Class to which this CSR belongs. Used to decide whether or | |
502 | not this CSR is legal in the current -march context. */ | |
503 | enum riscv_csr_class csr_class; | |
504 | }; | |
505 | ||
506 | /* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */ | |
507 | ||
508 | static void | |
509 | riscv_init_csr_hashes (const char *name, | |
510 | unsigned address, | |
511 | enum riscv_csr_class class) | |
512 | { | |
513 | struct riscv_csr_extra *entry = XNEW (struct riscv_csr_extra); | |
514 | entry->csr_class = class; | |
515 | ||
516 | const char *hash_error = | |
517 | hash_insert (csr_extra_hash, name, (void *) entry); | |
518 | if (hash_error != NULL) | |
519 | { | |
520 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
521 | name, hash_error); | |
522 | /* Probably a memory allocation problem? Give up now. */ | |
523 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
524 | } | |
525 | ||
526 | hash_reg_name (RCLASS_CSR, name, address); | |
527 | } | |
528 | ||
529 | /* Check wether the CSR is valid according to the ISA. */ | |
530 | ||
531 | static bfd_boolean | |
532 | riscv_csr_class_check (enum riscv_csr_class csr_class) | |
533 | { | |
534 | switch (csr_class) | |
535 | { | |
536 | case CSR_CLASS_I: return riscv_subset_supports ("i"); | |
537 | case CSR_CLASS_F: return riscv_subset_supports ("f"); | |
538 | case CSR_CLASS_I_32: | |
539 | return (xlen == 32 && riscv_subset_supports ("i")); | |
540 | ||
541 | default: | |
542 | return FALSE; | |
543 | } | |
544 | } | |
545 | ||
546 | /* If the CSR is defined, then we call `riscv_csr_class_check` to do the | |
547 | further checking. Return FALSE if the CSR is not defined. Otherwise, | |
548 | return TRUE. */ | |
549 | ||
550 | static bfd_boolean | |
551 | reg_csr_lookup_internal (const char *s) | |
552 | { | |
553 | struct riscv_csr_extra *r = | |
554 | (struct riscv_csr_extra *) hash_find (csr_extra_hash, s); | |
555 | ||
556 | if (r == NULL) | |
557 | return FALSE; | |
558 | ||
559 | /* We just report the warning when the CSR is invalid. */ | |
560 | if (!riscv_csr_class_check (r->csr_class)) | |
561 | as_warn (_("Invalid CSR `%s' for the current ISA"), s); | |
562 | ||
563 | return TRUE; | |
564 | } | |
565 | ||
e23eba97 NC |
566 | static unsigned int |
567 | reg_lookup_internal (const char *s, enum reg_class class) | |
568 | { | |
b7379ead | 569 | void *r = hash_find (reg_names_hash, s); |
e23eba97 NC |
570 | |
571 | if (r == NULL || DECODE_REG_CLASS (r) != class) | |
572 | return -1; | |
7f999549 JW |
573 | |
574 | if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15) | |
575 | return -1; | |
576 | ||
2ca89224 NC |
577 | if (class == RCLASS_CSR |
578 | && riscv_opts.csr_check | |
579 | && !reg_csr_lookup_internal (s)) | |
bd0cf5a6 NC |
580 | return -1; |
581 | ||
e23eba97 NC |
582 | return DECODE_REG_NUM (r); |
583 | } | |
584 | ||
585 | static bfd_boolean | |
586 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) | |
587 | { | |
588 | char *e; | |
589 | char save_c; | |
590 | int reg = -1; | |
591 | ||
592 | /* Find end of name. */ | |
593 | e = *s; | |
594 | if (is_name_beginner (*e)) | |
595 | ++e; | |
596 | while (is_part_of_name (*e)) | |
597 | ++e; | |
598 | ||
599 | /* Terminate name. */ | |
600 | save_c = *e; | |
601 | *e = '\0'; | |
602 | ||
603 | /* Look for the register. Advance to next token if one was recognized. */ | |
604 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
605 | *s = e; | |
606 | ||
607 | *e = save_c; | |
608 | if (regnop) | |
609 | *regnop = reg; | |
610 | return reg >= 0; | |
611 | } | |
612 | ||
613 | static bfd_boolean | |
614 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) | |
615 | { | |
616 | const char *p = strchr (*s, ','); | |
617 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
618 | ||
bfb218e3 JW |
619 | if (len == 0) |
620 | return FALSE; | |
621 | ||
e23eba97 NC |
622 | for (i = 0; i < size; i++) |
623 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0) | |
624 | { | |
625 | *regnop = i; | |
626 | *s += len; | |
627 | return TRUE; | |
628 | } | |
629 | ||
630 | return FALSE; | |
631 | } | |
632 | ||
633 | /* For consistency checking, verify that all bits are specified either | |
634 | by the match/mask part of the instruction definition, or by the | |
0e35537d JW |
635 | operand list. |
636 | ||
637 | `length` could be 0, 4 or 8, 0 for auto detection. */ | |
e23eba97 | 638 | static bfd_boolean |
0e35537d | 639 | validate_riscv_insn (const struct riscv_opcode *opc, int length) |
e23eba97 NC |
640 | { |
641 | const char *p = opc->args; | |
642 | char c; | |
643 | insn_t used_bits = opc->mask; | |
0e35537d JW |
644 | int insn_width; |
645 | insn_t required_bits; | |
646 | ||
647 | if (length == 0) | |
648 | insn_width = 8 * riscv_insn_length (opc->match); | |
649 | else | |
650 | insn_width = 8 * length; | |
651 | ||
652 | required_bits = ~0ULL >> (64 - insn_width); | |
e23eba97 NC |
653 | |
654 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
655 | { | |
656 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
657 | opc->name, opc->args); | |
658 | return FALSE; | |
659 | } | |
660 | ||
661 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) | |
662 | while (*p) | |
663 | switch (c = *p++) | |
664 | { | |
665 | case 'C': /* RVC */ | |
666 | switch (c = *p++) | |
667 | { | |
1d65abb5 | 668 | case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break; |
e23eba97 NC |
669 | case 'c': break; /* RS1, constrained to equal sp */ |
670 | case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; | |
1d65abb5 | 671 | case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; |
b416fe87 | 672 | case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; |
1d65abb5 AW |
673 | case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; |
674 | case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; | |
675 | case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; | |
676 | case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break; | |
677 | case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break; | |
e23eba97 NC |
678 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; |
679 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1d65abb5 AW |
680 | case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break; |
681 | case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
e23eba97 NC |
682 | case 'w': break; /* RS1S, constrained to equal RD */ |
683 | case 'x': break; /* RS2S, constrained to equal RD */ | |
ca0bc150 | 684 | case 'z': break; /* RS2S, contrained to be x0 */ |
1d65abb5 AW |
685 | case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break; |
686 | case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break; | |
687 | case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break; | |
688 | case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break; | |
e23eba97 NC |
689 | case 'U': break; /* RS1, constrained to equal RD */ |
690 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1d65abb5 AW |
691 | case '<': used_bits |= ENCODE_RVC_IMM (-1U); break; |
692 | case '>': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
0e35537d JW |
693 | case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break; |
694 | case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; | |
e23eba97 NC |
695 | case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; |
696 | case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
0e35537d JW |
697 | case 'F': /* funct */ |
698 | switch (c = *p++) | |
699 | { | |
4765cd61 | 700 | case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; |
0e35537d JW |
701 | case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; |
702 | case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; | |
4765cd61 | 703 | case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; |
0e35537d JW |
704 | default: |
705 | as_bad (_("internal: bad RISC-V opcode" | |
706 | " (unknown operand type `CF%c'): %s %s"), | |
707 | c, opc->name, opc->args); | |
708 | return FALSE; | |
709 | } | |
710 | break; | |
e23eba97 NC |
711 | default: |
712 | as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), | |
713 | c, opc->name, opc->args); | |
714 | return FALSE; | |
715 | } | |
716 | break; | |
717 | case ',': break; | |
718 | case '(': break; | |
719 | case ')': break; | |
720 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
721 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
722 | case 'A': break; | |
723 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
724 | case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
725 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
726 | case 'I': break; | |
727 | case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
728 | case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
729 | case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ | |
730 | case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
731 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
732 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
733 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
734 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
0e35537d | 735 | case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; |
e23eba97 NC |
736 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; |
737 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
738 | case 'o': | |
1d65abb5 AW |
739 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; |
740 | case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break; | |
741 | case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; | |
742 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
743 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
e925c834 | 744 | case 'z': break; |
e23eba97 NC |
745 | case '[': break; |
746 | case ']': break; | |
747 | case '0': break; | |
f50fabe4 | 748 | case '1': break; |
0e35537d JW |
749 | case 'F': /* funct */ |
750 | switch (c = *p++) | |
751 | { | |
752 | case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; | |
753 | case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; | |
754 | case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; | |
755 | default: | |
756 | as_bad (_("internal: bad RISC-V opcode" | |
757 | " (unknown operand type `F%c'): %s %s"), | |
758 | c, opc->name, opc->args); | |
759 | return FALSE; | |
760 | } | |
761 | break; | |
762 | case 'O': /* opcode */ | |
763 | switch (c = *p++) | |
764 | { | |
765 | case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; | |
766 | case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; | |
767 | default: | |
768 | as_bad (_("internal: bad RISC-V opcode" | |
769 | " (unknown operand type `F%c'): %s %s"), | |
770 | c, opc->name, opc->args); | |
771 | return FALSE; | |
772 | } | |
773 | break; | |
e23eba97 NC |
774 | default: |
775 | as_bad (_("internal: bad RISC-V opcode " | |
776 | "(unknown operand type `%c'): %s %s"), | |
777 | c, opc->name, opc->args); | |
778 | return FALSE; | |
779 | } | |
780 | #undef USE_BITS | |
781 | if (used_bits != required_bits) | |
782 | { | |
783 | as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), | |
784 | ~(unsigned long)(used_bits & required_bits), | |
785 | opc->name, opc->args); | |
786 | return FALSE; | |
787 | } | |
788 | return TRUE; | |
789 | } | |
790 | ||
791 | struct percent_op_match | |
792 | { | |
793 | const char *str; | |
794 | bfd_reloc_code_real_type reloc; | |
795 | }; | |
796 | ||
0e35537d JW |
797 | /* Common hash table initialization function for |
798 | instruction and .insn directive. */ | |
799 | static struct hash_control * | |
800 | init_opcode_hash (const struct riscv_opcode *opcodes, | |
801 | bfd_boolean insn_directive_p) | |
e23eba97 NC |
802 | { |
803 | int i = 0; | |
0e35537d JW |
804 | int length; |
805 | struct hash_control *hash = hash_new (); | |
806 | while (opcodes[i].name) | |
e23eba97 | 807 | { |
0e35537d | 808 | const char *name = opcodes[i].name; |
e23eba97 | 809 | const char *hash_error = |
0e35537d | 810 | hash_insert (hash, name, (void *) &opcodes[i]); |
e23eba97 | 811 | |
bd0cf5a6 | 812 | if (hash_error != NULL) |
e23eba97 NC |
813 | { |
814 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
0e35537d | 815 | opcodes[i].name, hash_error); |
e23eba97 NC |
816 | /* Probably a memory allocation problem? Give up now. */ |
817 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
818 | } | |
819 | ||
820 | do | |
821 | { | |
0e35537d | 822 | if (opcodes[i].pinfo != INSN_MACRO) |
e23eba97 | 823 | { |
0e35537d JW |
824 | if (insn_directive_p) |
825 | length = ((name[0] == 'c') ? 2 : 4); | |
826 | else | |
827 | length = 0; /* Let assembler determine the length. */ | |
828 | if (!validate_riscv_insn (&opcodes[i], length)) | |
e23eba97 NC |
829 | as_fatal (_("Broken assembler. No assembly attempted.")); |
830 | } | |
0e35537d JW |
831 | else |
832 | gas_assert (!insn_directive_p); | |
e23eba97 NC |
833 | ++i; |
834 | } | |
0e35537d | 835 | while (opcodes[i].name && !strcmp (opcodes[i].name, name)); |
e23eba97 NC |
836 | } |
837 | ||
0e35537d JW |
838 | return hash; |
839 | } | |
840 | ||
841 | /* This function is called once, at assembler startup time. It should set up | |
842 | all the tables, etc. that the MD part of the assembler will need. */ | |
843 | ||
844 | void | |
845 | md_begin (void) | |
846 | { | |
847 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
848 | ||
849 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
850 | as_warn (_("Could not set architecture and machine")); | |
851 | ||
852 | op_hash = init_opcode_hash (riscv_opcodes, FALSE); | |
853 | insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE); | |
854 | ||
e23eba97 NC |
855 | reg_names_hash = hash_new (); |
856 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); | |
857 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
858 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
859 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
b9c04e5a JW |
860 | /* Add "fp" as an alias for "s0". */ |
861 | hash_reg_name (RCLASS_GPR, "fp", 8); | |
862 | ||
bd0cf5a6 NC |
863 | /* Create and insert CSR hash tables. */ |
864 | csr_extra_hash = hash_new (); | |
865 | #define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class); | |
866 | #define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class); | |
e23eba97 NC |
867 | #include "opcode/riscv-opc.h" |
868 | #undef DECLARE_CSR | |
869 | ||
bd0cf5a6 NC |
870 | opcode_names_hash = hash_new (); |
871 | init_opcode_names_hash (); | |
872 | ||
e23eba97 NC |
873 | /* Set the default alignment for the text section. */ |
874 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
875 | } | |
876 | ||
45f76423 AW |
877 | static insn_t |
878 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
879 | { | |
880 | switch (reloc_type) | |
881 | { | |
882 | case BFD_RELOC_32: | |
883 | return value; | |
884 | ||
885 | case BFD_RELOC_RISCV_HI20: | |
886 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
887 | ||
888 | case BFD_RELOC_RISCV_LO12_S: | |
889 | return ENCODE_STYPE_IMM (value); | |
890 | ||
891 | case BFD_RELOC_RISCV_LO12_I: | |
892 | return ENCODE_ITYPE_IMM (value); | |
893 | ||
894 | default: | |
895 | abort (); | |
896 | } | |
897 | } | |
898 | ||
e23eba97 NC |
899 | /* Output an instruction. IP is the instruction information. |
900 | ADDRESS_EXPR is an operand of the instruction to be used with | |
901 | RELOC_TYPE. */ | |
902 | ||
903 | static void | |
904 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
905 | bfd_reloc_code_real_type reloc_type) | |
906 | { | |
907 | dwarf2_emit_insn (0); | |
908 | ||
909 | if (reloc_type != BFD_RELOC_UNUSED) | |
910 | { | |
911 | reloc_howto_type *howto; | |
912 | ||
1d65abb5 | 913 | gas_assert (address_expr); |
e23eba97 NC |
914 | if (reloc_type == BFD_RELOC_12_PCREL |
915 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
916 | { | |
917 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
918 | int best_case = riscv_insn_length (ip->insn_opcode); | |
919 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); | |
920 | add_relaxed_insn (ip, worst_case, best_case, | |
921 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
922 | address_expr->X_add_symbol, | |
923 | address_expr->X_add_number); | |
924 | return; | |
925 | } | |
45f76423 | 926 | else |
e23eba97 | 927 | { |
45f76423 AW |
928 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
929 | if (howto == NULL) | |
930 | as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); | |
e23eba97 | 931 | |
45f76423 AW |
932 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
933 | bfd_get_reloc_size (howto), | |
934 | address_expr, FALSE, reloc_type); | |
e23eba97 | 935 | |
45f76423 | 936 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 937 | } |
e23eba97 NC |
938 | } |
939 | ||
e23eba97 NC |
940 | add_fixed_insn (ip); |
941 | install_insn (ip); | |
f77bb6c5 JW |
942 | |
943 | /* We need to start a new frag after any instruction that can be | |
944 | optimized away or compressed by the linker during relaxation, to prevent | |
945 | the assembler from computing static offsets across such an instruction. | |
946 | This is necessary to get correct EH info. */ | |
947 | if (reloc_type == BFD_RELOC_RISCV_CALL | |
948 | || reloc_type == BFD_RELOC_RISCV_CALL_PLT | |
949 | || reloc_type == BFD_RELOC_RISCV_HI20 | |
950 | || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 | |
951 | || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 | |
952 | || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) | |
953 | { | |
954 | frag_wane (frag_now); | |
955 | frag_new (0); | |
956 | } | |
e23eba97 NC |
957 | } |
958 | ||
959 | /* Build an instruction created by a macro expansion. This is passed | |
960 | a pointer to the count of instructions created so far, an | |
961 | expression, the name of the instruction to build, an operand format | |
962 | string, and corresponding arguments. */ | |
963 | ||
964 | static void | |
965 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
966 | { | |
967 | const struct riscv_opcode *mo; | |
968 | struct riscv_cl_insn insn; | |
969 | bfd_reloc_code_real_type r; | |
970 | va_list args; | |
971 | ||
972 | va_start (args, fmt); | |
973 | ||
974 | r = BFD_RELOC_UNUSED; | |
975 | mo = (struct riscv_opcode *) hash_find (op_hash, name); | |
976 | gas_assert (mo); | |
977 | ||
978 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
979 | it if possible. */ | |
980 | while (riscv_insn_length (mo->match) < 4) | |
981 | mo++; | |
982 | gas_assert (strcmp (name, mo->name) == 0); | |
983 | ||
984 | create_insn (&insn, mo); | |
985 | for (;;) | |
986 | { | |
987 | switch (*fmt++) | |
988 | { | |
989 | case 'd': | |
990 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
991 | continue; | |
992 | ||
993 | case 's': | |
994 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
995 | continue; | |
996 | ||
997 | case 't': | |
998 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
999 | continue; | |
1000 | ||
1001 | case '>': | |
1002 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); | |
1003 | continue; | |
1004 | ||
1005 | case 'j': | |
1006 | case 'u': | |
1007 | case 'q': | |
1008 | gas_assert (ep != NULL); | |
1009 | r = va_arg (args, int); | |
1010 | continue; | |
1011 | ||
1012 | case '\0': | |
1013 | break; | |
1014 | case ',': | |
1015 | continue; | |
1016 | default: | |
1017 | as_fatal (_("internal error: invalid macro")); | |
1018 | } | |
1019 | break; | |
1020 | } | |
1021 | va_end (args); | |
1022 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1023 | ||
1024 | append_insn (&insn, ep, r); | |
1025 | } | |
1026 | ||
db3b6ecc KC |
1027 | /* Build an instruction created by a macro expansion. Like md_assemble but |
1028 | accept a printf-style format string and arguments. */ | |
1029 | ||
1030 | static void | |
1031 | md_assemblef (const char *format, ...) | |
1032 | { | |
1033 | char *buf = NULL; | |
1034 | va_list ap; | |
1035 | int r; | |
1036 | ||
1037 | va_start (ap, format); | |
1038 | ||
1039 | r = vasprintf (&buf, format, ap); | |
1040 | ||
1041 | if (r < 0) | |
1042 | as_fatal (_("internal error: vasprintf failed")); | |
1043 | ||
1044 | md_assemble (buf); | |
1045 | free(buf); | |
1046 | ||
1047 | va_end (ap); | |
1048 | } | |
1049 | ||
e23eba97 NC |
1050 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits |
1051 | unset. */ | |
1052 | static void | |
1053 | normalize_constant_expr (expressionS *ex) | |
1054 | { | |
1055 | if (xlen > 32) | |
1056 | return; | |
1057 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
1058 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
1059 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
1060 | - 0x80000000); | |
1061 | } | |
1062 | ||
ca2fd32c JW |
1063 | /* Fail if an expression EX is not a constant. IP is the instruction using EX. |
1064 | MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ | |
e23eba97 NC |
1065 | |
1066 | static void | |
ca2fd32c JW |
1067 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, |
1068 | bfd_boolean maybe_csr) | |
e23eba97 NC |
1069 | { |
1070 | if (ex->X_op == O_big) | |
1071 | as_bad (_("unsupported large constant")); | |
ca2fd32c JW |
1072 | else if (maybe_csr && ex->X_op == O_symbol) |
1073 | as_bad (_("unknown CSR `%s'"), | |
1074 | S_GET_NAME (ex->X_add_symbol)); | |
e23eba97 NC |
1075 | else if (ex->X_op != O_constant) |
1076 | as_bad (_("Instruction %s requires absolute expression"), | |
1077 | ip->insn_mo->name); | |
1078 | normalize_constant_expr (ex); | |
1079 | } | |
1080 | ||
1081 | static symbolS * | |
1082 | make_internal_label (void) | |
1083 | { | |
1084 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, | |
1d65abb5 | 1085 | (valueT) frag_now_fix (), frag_now); |
e23eba97 NC |
1086 | } |
1087 | ||
1088 | /* Load an entry from the GOT. */ | |
1089 | static void | |
1090 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
1091 | const char *lo_insn, const char *lo_pattern, | |
1092 | bfd_reloc_code_real_type hi_reloc, | |
1093 | bfd_reloc_code_real_type lo_reloc) | |
1094 | { | |
1095 | expressionS ep2; | |
1096 | ep2.X_op = O_symbol; | |
1097 | ep2.X_add_symbol = make_internal_label (); | |
1098 | ep2.X_add_number = 0; | |
1099 | ||
1100 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
1101 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
1102 | } | |
1103 | ||
1104 | static void | |
1105 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1106 | bfd_reloc_code_real_type hi_reloc, | |
1107 | bfd_reloc_code_real_type lo_reloc) | |
1108 | { | |
1109 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
1110 | } | |
1111 | ||
1112 | static void | |
1113 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1114 | bfd_reloc_code_real_type hi_reloc, | |
1115 | bfd_reloc_code_real_type lo_reloc) | |
1116 | { | |
1117 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
1118 | } | |
1119 | ||
1120 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
1121 | static void | |
1122 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
1123 | bfd_reloc_code_real_type reloc) | |
1124 | { | |
1125 | macro_build (ep, "auipc", "d,u", tempreg, reloc); | |
1126 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
1127 | } | |
1128 | ||
1129 | /* Load an integer constant into a register. */ | |
1130 | ||
1131 | static void | |
1132 | load_const (int reg, expressionS *ep) | |
1133 | { | |
1134 | int shift = RISCV_IMM_BITS; | |
4f7cc141 | 1135 | bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1); |
e23eba97 | 1136 | expressionS upper = *ep, lower = *ep; |
4f7cc141 | 1137 | lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign; |
e23eba97 NC |
1138 | upper.X_add_number -= lower.X_add_number; |
1139 | ||
1140 | if (ep->X_op != O_constant) | |
1141 | { | |
1142 | as_bad (_("unsupported large constant")); | |
1143 | return; | |
1144 | } | |
1145 | ||
1d65abb5 | 1146 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
1147 | { |
1148 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
1149 | while (((upper.X_add_number >> shift) & 1) == 0) | |
1150 | shift++; | |
1151 | ||
1152 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 1153 | load_const (reg, &upper); |
e23eba97 | 1154 | |
db3b6ecc | 1155 | md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift); |
e23eba97 | 1156 | if (lower.X_add_number != 0) |
db3b6ecc KC |
1157 | md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg, |
1158 | lower.X_add_number); | |
e23eba97 NC |
1159 | } |
1160 | else | |
1161 | { | |
1162 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
1163 | int hi_reg = 0; | |
1164 | ||
1165 | if (upper.X_add_number != 0) | |
1166 | { | |
db3b6ecc KC |
1167 | /* Discard low part and zero-extend upper immediate. */ |
1168 | upper_imm = ((uint32_t)upper.X_add_number >> shift); | |
1169 | ||
1170 | md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm); | |
e23eba97 NC |
1171 | hi_reg = reg; |
1172 | } | |
1173 | ||
1174 | if (lower.X_add_number != 0 || hi_reg == 0) | |
db3b6ecc KC |
1175 | md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg, |
1176 | lower.X_add_number); | |
e23eba97 NC |
1177 | } |
1178 | } | |
1179 | ||
1180 | /* Expand RISC-V assembly macros into one or more instructions. */ | |
1181 | static void | |
1182 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
1183 | bfd_reloc_code_real_type *imm_reloc) | |
1184 | { | |
1185 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
1186 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
1187 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
1188 | int mask = ip->insn_mo->mask; | |
1189 | ||
1190 | switch (mask) | |
1191 | { | |
1192 | case M_LI: | |
1193 | load_const (rd, imm_expr); | |
1194 | break; | |
1195 | ||
1196 | case M_LA: | |
1197 | case M_LLA: | |
1198 | /* Load the address of a symbol into a register. */ | |
1199 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
1200 | as_bad (_("offset too large")); | |
1201 | ||
1202 | if (imm_expr->X_op == O_constant) | |
1203 | load_const (rd, imm_expr); | |
1204 | else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ | |
1205 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
1206 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1207 | else /* Local PIC symbol, or any non-PIC symbol */ | |
1208 | pcrel_load (rd, rd, imm_expr, "addi", | |
1209 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1210 | break; | |
1211 | ||
1212 | case M_LA_TLS_GD: | |
1213 | pcrel_load (rd, rd, imm_expr, "addi", | |
1214 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1215 | break; | |
1216 | ||
1217 | case M_LA_TLS_IE: | |
1218 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
1219 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1220 | break; | |
1221 | ||
1222 | case M_LB: | |
1223 | pcrel_load (rd, rd, imm_expr, "lb", | |
1224 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1225 | break; | |
1226 | ||
1227 | case M_LBU: | |
1228 | pcrel_load (rd, rd, imm_expr, "lbu", | |
1229 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1230 | break; | |
1231 | ||
1232 | case M_LH: | |
1233 | pcrel_load (rd, rd, imm_expr, "lh", | |
1234 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1235 | break; | |
1236 | ||
1237 | case M_LHU: | |
1238 | pcrel_load (rd, rd, imm_expr, "lhu", | |
1239 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1240 | break; | |
1241 | ||
1242 | case M_LW: | |
1243 | pcrel_load (rd, rd, imm_expr, "lw", | |
1244 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1245 | break; | |
1246 | ||
1247 | case M_LWU: | |
1248 | pcrel_load (rd, rd, imm_expr, "lwu", | |
1249 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1250 | break; | |
1251 | ||
1252 | case M_LD: | |
1253 | pcrel_load (rd, rd, imm_expr, "ld", | |
1254 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1255 | break; | |
1256 | ||
1257 | case M_FLW: | |
1258 | pcrel_load (rd, rs1, imm_expr, "flw", | |
1259 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1260 | break; | |
1261 | ||
1262 | case M_FLD: | |
1263 | pcrel_load (rd, rs1, imm_expr, "fld", | |
1264 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1265 | break; | |
1266 | ||
1267 | case M_SB: | |
1268 | pcrel_store (rs2, rs1, imm_expr, "sb", | |
1269 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1270 | break; | |
1271 | ||
1272 | case M_SH: | |
1273 | pcrel_store (rs2, rs1, imm_expr, "sh", | |
1274 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1275 | break; | |
1276 | ||
1277 | case M_SW: | |
1278 | pcrel_store (rs2, rs1, imm_expr, "sw", | |
1279 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1280 | break; | |
1281 | ||
1282 | case M_SD: | |
1283 | pcrel_store (rs2, rs1, imm_expr, "sd", | |
1284 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1285 | break; | |
1286 | ||
1287 | case M_FSW: | |
1288 | pcrel_store (rs2, rs1, imm_expr, "fsw", | |
1289 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1290 | break; | |
1291 | ||
1292 | case M_FSD: | |
1293 | pcrel_store (rs2, rs1, imm_expr, "fsd", | |
1294 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1295 | break; | |
1296 | ||
1297 | case M_CALL: | |
1298 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
1299 | break; | |
1300 | ||
1301 | default: | |
1302 | as_bad (_("Macro %s not implemented"), ip->insn_mo->name); | |
1303 | break; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | static const struct percent_op_match percent_op_utype[] = | |
1308 | { | |
1309 | {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, | |
1310 | {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
dee35d02 | 1311 | {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, |
e23eba97 NC |
1312 | {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, |
1313 | {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
1314 | {"%hi", BFD_RELOC_RISCV_HI20}, | |
1315 | {0, 0} | |
1316 | }; | |
1317 | ||
1318 | static const struct percent_op_match percent_op_itype[] = | |
1319 | { | |
1320 | {"%lo", BFD_RELOC_RISCV_LO12_I}, | |
1321 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
1322 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
1323 | {0, 0} | |
1324 | }; | |
1325 | ||
1326 | static const struct percent_op_match percent_op_stype[] = | |
1327 | { | |
1328 | {"%lo", BFD_RELOC_RISCV_LO12_S}, | |
1329 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
1330 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
1331 | {0, 0} | |
1332 | }; | |
1333 | ||
1334 | static const struct percent_op_match percent_op_rtype[] = | |
1335 | { | |
1336 | {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, | |
1337 | {0, 0} | |
1338 | }; | |
1339 | ||
f50fabe4 JW |
1340 | static const struct percent_op_match percent_op_null[] = |
1341 | { | |
1342 | {0, 0} | |
1343 | }; | |
1344 | ||
e23eba97 NC |
1345 | /* Return true if *STR points to a relocation operator. When returning true, |
1346 | move *STR over the operator and store its relocation code in *RELOC. | |
1347 | Leave both *STR and *RELOC alone when returning false. */ | |
1348 | ||
1349 | static bfd_boolean | |
1350 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, | |
1351 | const struct percent_op_match *percent_op) | |
1352 | { | |
1353 | for ( ; percent_op->str; percent_op++) | |
1354 | if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) | |
1355 | { | |
1356 | int len = strlen (percent_op->str); | |
1357 | ||
1358 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
1359 | continue; | |
1360 | ||
1361 | *str += strlen (percent_op->str); | |
1362 | *reloc = percent_op->reloc; | |
1363 | ||
1364 | /* Check whether the output BFD supports this relocation. | |
1365 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
1366 | if (*reloc != BFD_RELOC_UNUSED |
1367 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 NC |
1368 | { |
1369 | as_bad ("relocation %s isn't supported by the current ABI", | |
1370 | percent_op->str); | |
1371 | *reloc = BFD_RELOC_UNUSED; | |
1372 | } | |
1373 | return TRUE; | |
1374 | } | |
1375 | return FALSE; | |
1376 | } | |
1377 | ||
1378 | static void | |
1379 | my_getExpression (expressionS *ep, char *str) | |
1380 | { | |
1381 | char *save_in; | |
1382 | ||
1383 | save_in = input_line_pointer; | |
1384 | input_line_pointer = str; | |
1385 | expression (ep); | |
1386 | expr_end = input_line_pointer; | |
1387 | input_line_pointer = save_in; | |
1388 | } | |
1389 | ||
1390 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
1391 | expression in *EP and the relocation, if any, in RELOC. | |
1392 | Return the number of relocation operators used (0 or 1). | |
1393 | ||
1394 | On exit, EXPR_END points to the first character after the expression. */ | |
1395 | ||
1396 | static size_t | |
1397 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1398 | char *str, const struct percent_op_match *percent_op) | |
1399 | { | |
1400 | size_t reloc_index; | |
1401 | unsigned crux_depth, str_depth, regno; | |
1402 | char *crux; | |
1403 | ||
8970c022 JW |
1404 | /* First, check for integer registers. No callers can accept a reg, but |
1405 | we need to avoid accidentally creating a useless undefined symbol below, | |
1406 | if this is an instruction pattern that can't match. A glibc build fails | |
1407 | if this is removed. */ | |
e23eba97 NC |
1408 | if (reg_lookup (&str, RCLASS_GPR, ®no)) |
1409 | { | |
1410 | ep->X_op = O_register; | |
1411 | ep->X_add_number = regno; | |
8970c022 | 1412 | expr_end = str; |
e23eba97 NC |
1413 | return 0; |
1414 | } | |
1415 | ||
1416 | /* Search for the start of the main expression. | |
1417 | End the loop with CRUX pointing to the start | |
1418 | of the main expression and with CRUX_DEPTH containing the number | |
1419 | of open brackets at that point. */ | |
1420 | reloc_index = -1; | |
1421 | str_depth = 0; | |
1422 | do | |
1423 | { | |
1424 | reloc_index++; | |
1425 | crux = str; | |
1426 | crux_depth = str_depth; | |
1427 | ||
1428 | /* Skip over whitespace and brackets, keeping count of the number | |
1429 | of brackets. */ | |
1430 | while (*str == ' ' || *str == '\t' || *str == '(') | |
1431 | if (*str++ == '(') | |
1432 | str_depth++; | |
1433 | } | |
1434 | while (*str == '%' | |
1435 | && reloc_index < 1 | |
1436 | && parse_relocation (&str, reloc, percent_op)); | |
1437 | ||
1438 | my_getExpression (ep, crux); | |
1439 | str = expr_end; | |
1440 | ||
1441 | /* Match every open bracket. */ | |
1442 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
1443 | if (*str++ == ')') | |
1444 | crux_depth--; | |
1445 | ||
1446 | if (crux_depth > 0) | |
1447 | as_bad ("unclosed '('"); | |
1448 | ||
1449 | expr_end = str; | |
1450 | ||
1451 | return reloc_index; | |
1452 | } | |
1453 | ||
0e35537d JW |
1454 | /* Parse opcode name, could be an mnemonics or number. */ |
1455 | static size_t | |
1456 | my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1457 | char *str, const struct percent_op_match *percent_op) | |
1458 | { | |
1459 | const struct opcode_name_t *o = opcode_name_lookup (&str); | |
1460 | ||
1461 | if (o != NULL) | |
1462 | { | |
1463 | ep->X_op = O_constant; | |
1464 | ep->X_add_number = o->val; | |
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | return my_getSmallExpression (ep, reloc, str, percent_op); | |
1469 | } | |
1470 | ||
f0531ed6 JW |
1471 | /* Detect and handle implicitly zero load-store offsets. For example, |
1472 | "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such | |
1473 | an implicit offset was detected. */ | |
1474 | ||
1475 | static bfd_boolean | |
89424b1d | 1476 | riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) |
f0531ed6 JW |
1477 | { |
1478 | /* Check whether there is only a single bracketed expression left. | |
1479 | If so, it must be the base register and the constant must be zero. */ | |
1480 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
1481 | { | |
89424b1d MR |
1482 | ep->X_op = O_constant; |
1483 | ep->X_add_number = 0; | |
f0531ed6 JW |
1484 | return TRUE; |
1485 | } | |
1486 | ||
1487 | return FALSE; | |
1488 | } | |
1489 | ||
54b2aec1 NC |
1490 | /* All RISC-V CSR instructions belong to one of these classes. */ |
1491 | ||
1492 | enum csr_insn_type | |
1493 | { | |
1494 | INSN_NOT_CSR, | |
1495 | INSN_CSRRW, | |
1496 | INSN_CSRRS, | |
1497 | INSN_CSRRC | |
1498 | }; | |
1499 | ||
1500 | /* Return which CSR instruction is checking. */ | |
1501 | ||
1502 | static enum csr_insn_type | |
1503 | riscv_csr_insn_type (insn_t insn) | |
1504 | { | |
1505 | if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0 | |
1506 | || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0) | |
1507 | return INSN_CSRRW; | |
1508 | else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0 | |
1509 | || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0) | |
1510 | return INSN_CSRRS; | |
1511 | else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0 | |
1512 | || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0) | |
1513 | return INSN_CSRRC; | |
1514 | else | |
1515 | return INSN_NOT_CSR; | |
1516 | } | |
1517 | ||
1518 | /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write | |
1519 | CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of | |
1520 | CSR address is 0x3. */ | |
1521 | ||
1522 | static bfd_boolean | |
1523 | riscv_csr_read_only_check (insn_t insn) | |
1524 | { | |
1525 | int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR; | |
1526 | int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1; | |
1527 | int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3); | |
1528 | enum csr_insn_type csr_insn = riscv_csr_insn_type (insn); | |
1529 | ||
1530 | if (readonly | |
1531 | && (((csr_insn == INSN_CSRRS | |
1532 | || csr_insn == INSN_CSRRC) | |
1533 | && rs1 != 0) | |
1534 | || csr_insn == INSN_CSRRW)) | |
1535 | return FALSE; | |
1536 | ||
1537 | return TRUE; | |
1538 | } | |
1539 | ||
e23eba97 NC |
1540 | /* This routine assembles an instruction into its binary format. As a |
1541 | side effect, it sets the global variable imm_reloc to the type of | |
1542 | relocation to do if one of the operands is an address expression. */ | |
1543 | ||
1544 | static const char * | |
1545 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, | |
0e35537d | 1546 | bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash) |
e23eba97 NC |
1547 | { |
1548 | char *s; | |
1549 | const char *args; | |
1550 | char c = 0; | |
1551 | struct riscv_opcode *insn; | |
1552 | char *argsStart; | |
1553 | unsigned int regno; | |
1554 | char save_c = 0; | |
1555 | int argnum; | |
1556 | const struct percent_op_match *p; | |
1557 | const char *error = "unrecognized opcode"; | |
54b2aec1 NC |
1558 | /* Indicate we are assembling instruction with CSR. */ |
1559 | bfd_boolean insn_with_csr = FALSE; | |
e23eba97 NC |
1560 | |
1561 | /* Parse the name of the instruction. Terminate the string if whitespace | |
1562 | is found so that hash_find only sees the name part of the string. */ | |
1563 | for (s = str; *s != '\0'; ++s) | |
1564 | if (ISSPACE (*s)) | |
1565 | { | |
1566 | save_c = *s; | |
1567 | *s++ = '\0'; | |
1568 | break; | |
1569 | } | |
1570 | ||
0e35537d | 1571 | insn = (struct riscv_opcode *) hash_find (hash, str); |
e23eba97 NC |
1572 | |
1573 | argsStart = s; | |
1574 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) | |
1575 | { | |
1080bf78 JW |
1576 | if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement)) |
1577 | continue; | |
1578 | ||
7e9ad3a3 | 1579 | if (!riscv_multi_subset_supports (insn->insn_class)) |
e23eba97 NC |
1580 | continue; |
1581 | ||
1582 | create_insn (ip, insn); | |
1583 | argnum = 1; | |
1584 | ||
1585 | imm_expr->X_op = O_absent; | |
1586 | *imm_reloc = BFD_RELOC_UNUSED; | |
1587 | p = percent_op_itype; | |
1588 | ||
1589 | for (args = insn->args;; ++args) | |
1590 | { | |
1591 | s += strspn (s, " \t"); | |
1592 | switch (*args) | |
1593 | { | |
1594 | case '\0': /* End of args. */ | |
1595 | if (insn->pinfo != INSN_MACRO) | |
1596 | { | |
1597 | if (!insn->match_func (insn, ip->insn_opcode)) | |
1598 | break; | |
0e35537d JW |
1599 | |
1600 | /* For .insn, insn->match and insn->mask are 0. */ | |
1601 | if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) | |
1602 | ? ip->insn_opcode | |
1603 | : insn->match) == 2 | |
1604 | && !riscv_opts.rvc) | |
e23eba97 | 1605 | break; |
54b2aec1 NC |
1606 | |
1607 | /* Check if we write a read-only CSR by the CSR | |
1608 | instruction. */ | |
1609 | if (insn_with_csr | |
1610 | && riscv_opts.csr_check | |
1611 | && !riscv_csr_read_only_check (ip->insn_opcode)) | |
1612 | { | |
1613 | /* Restore the character in advance, since we want to | |
1614 | report the detailed warning message here. */ | |
1615 | if (save_c) | |
1616 | *(argsStart - 1) = save_c; | |
1617 | as_warn (_("Read-only CSR is written `%s'"), str); | |
1618 | insn_with_csr = FALSE; | |
1619 | } | |
e23eba97 NC |
1620 | } |
1621 | if (*s != '\0') | |
1622 | break; | |
1623 | /* Successful assembly. */ | |
1624 | error = NULL; | |
54b2aec1 | 1625 | insn_with_csr = FALSE; |
e23eba97 NC |
1626 | goto out; |
1627 | ||
1628 | case 'C': /* RVC */ | |
1629 | switch (*++args) | |
1630 | { | |
1631 | case 's': /* RS1 x8-x15 */ | |
1632 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1633 | || !(regno >= 8 && regno <= 15)) | |
1634 | break; | |
1635 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1636 | continue; | |
1637 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
1638 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1639 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) | |
1640 | break; | |
1641 | continue; | |
1642 | case 't': /* RS2 x8-x15 */ | |
1643 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1644 | || !(regno >= 8 && regno <= 15)) | |
1645 | break; | |
1646 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1647 | continue; | |
1648 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
1649 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1650 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) | |
1651 | break; | |
1652 | continue; | |
1653 | case 'U': /* RS1, constrained to equal RD. */ | |
1654 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1655 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) | |
1656 | break; | |
1657 | continue; | |
1658 | case 'V': /* RS2 */ | |
1659 | if (!reg_lookup (&s, RCLASS_GPR, ®no)) | |
1660 | break; | |
1661 | INSERT_OPERAND (CRS2, *ip, regno); | |
1662 | continue; | |
1663 | case 'c': /* RS1, constrained to equal sp. */ | |
1664 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1665 | || regno != X_SP) | |
1666 | break; | |
1667 | continue; | |
ca0bc150 JW |
1668 | case 'z': /* RS2, contrained to equal x0. */ |
1669 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1670 | || regno != 0) | |
1671 | break; | |
1672 | continue; | |
e23eba97 NC |
1673 | case '>': |
1674 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1675 | || imm_expr->X_op != O_constant | |
1676 | || imm_expr->X_add_number <= 0 | |
1677 | || imm_expr->X_add_number >= 64) | |
1678 | break; | |
1679 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
dc1e8a47 | 1680 | rvc_imm_done: |
e23eba97 NC |
1681 | s = expr_end; |
1682 | imm_expr->X_op = O_absent; | |
1683 | continue; | |
1684 | case '<': | |
1685 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1686 | || imm_expr->X_op != O_constant | |
1687 | || !VALID_RVC_IMM (imm_expr->X_add_number) | |
1688 | || imm_expr->X_add_number <= 0 | |
1689 | || imm_expr->X_add_number >= 32) | |
1690 | break; | |
1691 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1692 | goto rvc_imm_done; | |
0e35537d JW |
1693 | case '8': |
1694 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1695 | || imm_expr->X_op != O_constant | |
1696 | || !VALID_RVC_UIMM8 (imm_expr->X_add_number) | |
1697 | || imm_expr->X_add_number < 0 | |
1698 | || imm_expr->X_add_number >= 256) | |
1699 | break; | |
1700 | ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number); | |
1701 | goto rvc_imm_done; | |
e23eba97 NC |
1702 | case 'i': |
1703 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1704 | || imm_expr->X_op != O_constant | |
1705 | || imm_expr->X_add_number == 0 | |
1706 | || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) | |
1707 | break; | |
1708 | ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); | |
1709 | goto rvc_imm_done; | |
1710 | case 'j': | |
1711 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1712 | || imm_expr->X_op != O_constant | |
1713 | || imm_expr->X_add_number == 0 | |
1714 | || !VALID_RVC_IMM (imm_expr->X_add_number)) | |
1715 | break; | |
1716 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1717 | goto rvc_imm_done; | |
1718 | case 'k': | |
f0531ed6 JW |
1719 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1720 | continue; | |
e23eba97 NC |
1721 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1722 | || imm_expr->X_op != O_constant | |
1723 | || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) | |
1724 | break; | |
1725 | ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); | |
1726 | goto rvc_imm_done; | |
1727 | case 'l': | |
f0531ed6 JW |
1728 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1729 | continue; | |
e23eba97 NC |
1730 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1731 | || imm_expr->X_op != O_constant | |
1732 | || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) | |
1733 | break; | |
1734 | ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); | |
1735 | goto rvc_imm_done; | |
1736 | case 'm': | |
f0531ed6 JW |
1737 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1738 | continue; | |
e23eba97 NC |
1739 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1740 | || imm_expr->X_op != O_constant | |
1741 | || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) | |
1742 | break; | |
1743 | ip->insn_opcode |= | |
1744 | ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); | |
1745 | goto rvc_imm_done; | |
1746 | case 'n': | |
f0531ed6 JW |
1747 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1748 | continue; | |
e23eba97 NC |
1749 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1750 | || imm_expr->X_op != O_constant | |
1751 | || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) | |
1752 | break; | |
1753 | ip->insn_opcode |= | |
1754 | ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); | |
1755 | goto rvc_imm_done; | |
b416fe87 KC |
1756 | case 'o': |
1757 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1758 | || imm_expr->X_op != O_constant | |
21a186f2 JW |
1759 | /* C.addiw, c.li, and c.andi allow zero immediate. |
1760 | C.addi allows zero immediate as hint. Otherwise this | |
1761 | is same as 'j'. */ | |
b416fe87 KC |
1762 | || !VALID_RVC_IMM (imm_expr->X_add_number)) |
1763 | break; | |
1764 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1765 | goto rvc_imm_done; | |
e23eba97 NC |
1766 | case 'K': |
1767 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1768 | || imm_expr->X_op != O_constant | |
1769 | || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) | |
1770 | || imm_expr->X_add_number == 0) | |
1771 | break; | |
1772 | ip->insn_opcode |= | |
1773 | ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); | |
1774 | goto rvc_imm_done; | |
1775 | case 'L': | |
1776 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1777 | || imm_expr->X_op != O_constant | |
1778 | || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) | |
1779 | || imm_expr->X_add_number == 0) | |
1780 | break; | |
1781 | ip->insn_opcode |= | |
1782 | ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); | |
1783 | goto rvc_imm_done; | |
1784 | case 'M': | |
f0531ed6 JW |
1785 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1786 | continue; | |
e23eba97 NC |
1787 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1788 | || imm_expr->X_op != O_constant | |
1789 | || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) | |
1790 | break; | |
1791 | ip->insn_opcode |= | |
1792 | ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); | |
1793 | goto rvc_imm_done; | |
1794 | case 'N': | |
f0531ed6 JW |
1795 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1796 | continue; | |
e23eba97 NC |
1797 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1798 | || imm_expr->X_op != O_constant | |
1799 | || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) | |
1800 | break; | |
1801 | ip->insn_opcode |= | |
1802 | ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); | |
1803 | goto rvc_imm_done; | |
1804 | case 'u': | |
1805 | p = percent_op_utype; | |
1806 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1807 | break; | |
dc1e8a47 | 1808 | rvc_lui: |
e23eba97 NC |
1809 | if (imm_expr->X_op != O_constant |
1810 | || imm_expr->X_add_number <= 0 | |
1811 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
1812 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
1813 | && (imm_expr->X_add_number < | |
1814 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
1815 | break; | |
1816 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1817 | goto rvc_imm_done; | |
1818 | case 'v': | |
1819 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1820 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) | |
1821 | || ((int32_t)imm_expr->X_add_number | |
1822 | != imm_expr->X_add_number)) | |
1823 | break; | |
1824 | imm_expr->X_add_number = | |
1825 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
1826 | goto rvc_lui; | |
1827 | case 'p': | |
1828 | goto branch; | |
1829 | case 'a': | |
1830 | goto jump; | |
0e35537d JW |
1831 | case 'S': /* Floating-point RS1 x8-x15. */ |
1832 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1833 | || !(regno >= 8 && regno <= 15)) | |
1834 | break; | |
1835 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1836 | continue; | |
e23eba97 NC |
1837 | case 'D': /* Floating-point RS2 x8-x15. */ |
1838 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1839 | || !(regno >= 8 && regno <= 15)) | |
1840 | break; | |
1841 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1842 | continue; | |
1843 | case 'T': /* Floating-point RS2. */ | |
1844 | if (!reg_lookup (&s, RCLASS_FPR, ®no)) | |
1845 | break; | |
1846 | INSERT_OPERAND (CRS2, *ip, regno); | |
1847 | continue; | |
0e35537d JW |
1848 | case 'F': |
1849 | switch (*++args) | |
1850 | { | |
4765cd61 JW |
1851 | case '6': |
1852 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1853 | || imm_expr->X_op != O_constant | |
1854 | || imm_expr->X_add_number < 0 | |
1855 | || imm_expr->X_add_number >= 64) | |
1856 | { | |
1857 | as_bad (_("bad value for funct6 field, " | |
1858 | "value must be 0...64")); | |
1859 | break; | |
1860 | } | |
1861 | ||
1862 | INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number); | |
1863 | imm_expr->X_op = O_absent; | |
1864 | s = expr_end; | |
1865 | continue; | |
0e35537d JW |
1866 | case '4': |
1867 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1868 | || imm_expr->X_op != O_constant | |
1869 | || imm_expr->X_add_number < 0 | |
1870 | || imm_expr->X_add_number >= 16) | |
1871 | { | |
1872 | as_bad (_("bad value for funct4 field, " | |
1873 | "value must be 0...15")); | |
1874 | break; | |
1875 | } | |
1876 | ||
1877 | INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); | |
1878 | imm_expr->X_op = O_absent; | |
1879 | s = expr_end; | |
1880 | continue; | |
1881 | case '3': | |
1882 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1883 | || imm_expr->X_op != O_constant | |
1884 | || imm_expr->X_add_number < 0 | |
1885 | || imm_expr->X_add_number >= 8) | |
1886 | { | |
1887 | as_bad (_("bad value for funct3 field, " | |
1888 | "value must be 0...7")); | |
1889 | break; | |
1890 | } | |
1891 | INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); | |
1892 | imm_expr->X_op = O_absent; | |
1893 | s = expr_end; | |
1894 | continue; | |
4765cd61 JW |
1895 | case '2': |
1896 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1897 | || imm_expr->X_op != O_constant | |
1898 | || imm_expr->X_add_number < 0 | |
1899 | || imm_expr->X_add_number >= 4) | |
1900 | { | |
1901 | as_bad (_("bad value for funct2 field, " | |
1902 | "value must be 0...3")); | |
1903 | break; | |
1904 | } | |
1905 | INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number); | |
1906 | imm_expr->X_op = O_absent; | |
1907 | s = expr_end; | |
1908 | continue; | |
0e35537d JW |
1909 | default: |
1910 | as_bad (_("bad compressed FUNCT field" | |
1911 | " specifier 'CF%c'\n"), | |
1912 | *args); | |
1913 | } | |
1914 | break; | |
1915 | ||
e23eba97 NC |
1916 | default: |
1917 | as_bad (_("bad RVC field specifier 'C%c'\n"), *args); | |
1918 | } | |
1919 | break; | |
1920 | ||
1921 | case ',': | |
1922 | ++argnum; | |
1923 | if (*s++ == *args) | |
1924 | continue; | |
1925 | s--; | |
1926 | break; | |
1927 | ||
1928 | case '(': | |
1929 | case ')': | |
1930 | case '[': | |
1931 | case ']': | |
1932 | if (*s++ == *args) | |
1933 | continue; | |
1934 | break; | |
1935 | ||
1936 | case '<': /* Shift amount, 0 - 31. */ | |
1937 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1938 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1939 | if ((unsigned long) imm_expr->X_add_number > 31) |
94f78a77 AW |
1940 | as_bad (_("Improper shift amount (%lu)"), |
1941 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1942 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); |
1943 | imm_expr->X_op = O_absent; | |
1944 | s = expr_end; | |
1945 | continue; | |
1946 | ||
1947 | case '>': /* Shift amount, 0 - (XLEN-1). */ | |
1948 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1949 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1950 | if ((unsigned long) imm_expr->X_add_number >= xlen) |
94f78a77 AW |
1951 | as_bad (_("Improper shift amount (%lu)"), |
1952 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1953 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); |
1954 | imm_expr->X_op = O_absent; | |
1955 | s = expr_end; | |
1956 | continue; | |
1957 | ||
1958 | case 'Z': /* CSRRxI immediate. */ | |
1959 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1960 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1961 | if ((unsigned long) imm_expr->X_add_number > 31) |
94f78a77 AW |
1962 | as_bad (_("Improper CSRxI immediate (%lu)"), |
1963 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1964 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); |
1965 | imm_expr->X_op = O_absent; | |
1966 | s = expr_end; | |
1967 | continue; | |
1968 | ||
1969 | case 'E': /* Control register. */ | |
54b2aec1 | 1970 | insn_with_csr = TRUE; |
e23eba97 NC |
1971 | if (reg_lookup (&s, RCLASS_CSR, ®no)) |
1972 | INSERT_OPERAND (CSR, *ip, regno); | |
1973 | else | |
1974 | { | |
1975 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1976 | check_absolute_expr (ip, imm_expr, TRUE); |
e23eba97 | 1977 | if ((unsigned long) imm_expr->X_add_number > 0xfff) |
94f78a77 AW |
1978 | as_bad (_("Improper CSR address (%lu)"), |
1979 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1980 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
1981 | imm_expr->X_op = O_absent; | |
1982 | s = expr_end; | |
1983 | } | |
1984 | continue; | |
1985 | ||
1986 | case 'm': /* Rounding mode. */ | |
1987 | if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) | |
1988 | { | |
1989 | INSERT_OPERAND (RM, *ip, regno); | |
1990 | continue; | |
1991 | } | |
1992 | break; | |
1993 | ||
1994 | case 'P': | |
1995 | case 'Q': /* Fence predecessor/successor. */ | |
1996 | if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), | |
1997 | ®no)) | |
1998 | { | |
1999 | if (*args == 'P') | |
2000 | INSERT_OPERAND (PRED, *ip, regno); | |
2001 | else | |
2002 | INSERT_OPERAND (SUCC, *ip, regno); | |
2003 | continue; | |
2004 | } | |
2005 | break; | |
2006 | ||
2007 | case 'd': /* Destination register. */ | |
2008 | case 's': /* Source register. */ | |
2009 | case 't': /* Target register. */ | |
0e35537d | 2010 | case 'r': /* rs3. */ |
e23eba97 NC |
2011 | if (reg_lookup (&s, RCLASS_GPR, ®no)) |
2012 | { | |
2013 | c = *args; | |
2014 | if (*s == ' ') | |
2015 | ++s; | |
2016 | ||
2017 | /* Now that we have assembled one operand, we use the args | |
2018 | string to figure out where it goes in the instruction. */ | |
2019 | switch (c) | |
2020 | { | |
2021 | case 's': | |
2022 | INSERT_OPERAND (RS1, *ip, regno); | |
2023 | break; | |
2024 | case 'd': | |
2025 | INSERT_OPERAND (RD, *ip, regno); | |
2026 | break; | |
2027 | case 't': | |
2028 | INSERT_OPERAND (RS2, *ip, regno); | |
2029 | break; | |
0e35537d JW |
2030 | case 'r': |
2031 | INSERT_OPERAND (RS3, *ip, regno); | |
2032 | break; | |
e23eba97 NC |
2033 | } |
2034 | continue; | |
2035 | } | |
2036 | break; | |
2037 | ||
2038 | case 'D': /* Floating point rd. */ | |
2039 | case 'S': /* Floating point rs1. */ | |
2040 | case 'T': /* Floating point rs2. */ | |
2041 | case 'U': /* Floating point rs1 and rs2. */ | |
2042 | case 'R': /* Floating point rs3. */ | |
2043 | if (reg_lookup (&s, RCLASS_FPR, ®no)) | |
2044 | { | |
2045 | c = *args; | |
2046 | if (*s == ' ') | |
2047 | ++s; | |
2048 | switch (c) | |
2049 | { | |
2050 | case 'D': | |
2051 | INSERT_OPERAND (RD, *ip, regno); | |
2052 | break; | |
2053 | case 'S': | |
2054 | INSERT_OPERAND (RS1, *ip, regno); | |
2055 | break; | |
2056 | case 'U': | |
2057 | INSERT_OPERAND (RS1, *ip, regno); | |
2058 | /* fallthru */ | |
2059 | case 'T': | |
2060 | INSERT_OPERAND (RS2, *ip, regno); | |
2061 | break; | |
2062 | case 'R': | |
2063 | INSERT_OPERAND (RS3, *ip, regno); | |
2064 | break; | |
2065 | } | |
2066 | continue; | |
2067 | } | |
2068 | ||
2069 | break; | |
2070 | ||
2071 | case 'I': | |
2072 | my_getExpression (imm_expr, s); | |
2073 | if (imm_expr->X_op != O_big | |
2074 | && imm_expr->X_op != O_constant) | |
2075 | break; | |
2076 | normalize_constant_expr (imm_expr); | |
2077 | s = expr_end; | |
2078 | continue; | |
2079 | ||
2080 | case 'A': | |
2081 | my_getExpression (imm_expr, s); | |
2082 | normalize_constant_expr (imm_expr); | |
2083 | /* The 'A' format specifier must be a symbol. */ | |
2084 | if (imm_expr->X_op != O_symbol) | |
2085 | break; | |
2086 | *imm_reloc = BFD_RELOC_32; | |
2087 | s = expr_end; | |
2088 | continue; | |
2089 | ||
160d1b3d SH |
2090 | case 'B': |
2091 | my_getExpression (imm_expr, s); | |
2092 | normalize_constant_expr (imm_expr); | |
2093 | /* The 'B' format specifier must be a symbol or a constant. */ | |
2094 | if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) | |
2095 | break; | |
2096 | if (imm_expr->X_op == O_symbol) | |
2097 | *imm_reloc = BFD_RELOC_32; | |
2098 | s = expr_end; | |
2099 | continue; | |
2100 | ||
e23eba97 | 2101 | case 'j': /* Sign-extended immediate. */ |
e23eba97 | 2102 | p = percent_op_itype; |
f50fabe4 | 2103 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; |
e23eba97 NC |
2104 | goto alu_op; |
2105 | case 'q': /* Store displacement. */ | |
2106 | p = percent_op_stype; | |
2107 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
2108 | goto load_store; | |
2109 | case 'o': /* Load displacement. */ | |
2110 | p = percent_op_itype; | |
2111 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
2112 | goto load_store; | |
f50fabe4 | 2113 | case '1': /* 4-operand add, must be %tprel_add. */ |
e23eba97 | 2114 | p = percent_op_rtype; |
f50fabe4 JW |
2115 | goto alu_op; |
2116 | case '0': /* AMO "displacement," which must be zero. */ | |
2117 | p = percent_op_null; | |
dc1e8a47 | 2118 | load_store: |
f0531ed6 | 2119 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
e23eba97 | 2120 | continue; |
dc1e8a47 | 2121 | alu_op: |
e23eba97 NC |
2122 | /* If this value won't fit into a 16 bit offset, then go |
2123 | find a macro that will generate the 32 bit offset | |
2124 | code pattern. */ | |
2125 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
2126 | { | |
2127 | normalize_constant_expr (imm_expr); | |
2128 | if (imm_expr->X_op != O_constant | |
2129 | || (*args == '0' && imm_expr->X_add_number != 0) | |
f50fabe4 | 2130 | || (*args == '1') |
e23eba97 NC |
2131 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 |
2132 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
2133 | break; | |
2134 | } | |
2135 | ||
2136 | s = expr_end; | |
2137 | continue; | |
2138 | ||
2139 | case 'p': /* PC-relative offset. */ | |
dc1e8a47 | 2140 | branch: |
e23eba97 NC |
2141 | *imm_reloc = BFD_RELOC_12_PCREL; |
2142 | my_getExpression (imm_expr, s); | |
2143 | s = expr_end; | |
2144 | continue; | |
2145 | ||
2146 | case 'u': /* Upper 20 bits. */ | |
2147 | p = percent_op_utype; | |
4288405d | 2148 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) |
e23eba97 | 2149 | { |
4288405d JW |
2150 | if (imm_expr->X_op != O_constant) |
2151 | break; | |
2152 | ||
e23eba97 NC |
2153 | if (imm_expr->X_add_number < 0 |
2154 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
2155 | as_bad (_("lui expression not in range 0..1048575")); | |
2156 | ||
2157 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
2158 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
2159 | } | |
2160 | s = expr_end; | |
2161 | continue; | |
2162 | ||
2163 | case 'a': /* 20-bit PC-relative offset. */ | |
dc1e8a47 | 2164 | jump: |
e23eba97 NC |
2165 | my_getExpression (imm_expr, s); |
2166 | s = expr_end; | |
2167 | *imm_reloc = BFD_RELOC_RISCV_JMP; | |
2168 | continue; | |
2169 | ||
2170 | case 'c': | |
2171 | my_getExpression (imm_expr, s); | |
2172 | s = expr_end; | |
2173 | if (strcmp (s, "@plt") == 0) | |
2174 | { | |
2175 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
2176 | s += 4; | |
2177 | } | |
2178 | else | |
2179 | *imm_reloc = BFD_RELOC_RISCV_CALL; | |
2180 | continue; | |
0e35537d JW |
2181 | case 'O': |
2182 | switch (*++args) | |
2183 | { | |
2184 | case '4': | |
2185 | if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) | |
2186 | || imm_expr->X_op != O_constant | |
2187 | || imm_expr->X_add_number < 0 | |
2188 | || imm_expr->X_add_number >= 128 | |
2189 | || (imm_expr->X_add_number & 0x3) != 3) | |
2190 | { | |
2191 | as_bad (_("bad value for opcode field, " | |
2192 | "value must be 0...127 and " | |
2193 | "lower 2 bits must be 0x3")); | |
2194 | break; | |
2195 | } | |
2196 | ||
2197 | INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); | |
2198 | imm_expr->X_op = O_absent; | |
2199 | s = expr_end; | |
2200 | continue; | |
2201 | case '2': | |
2202 | if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) | |
2203 | || imm_expr->X_op != O_constant | |
2204 | || imm_expr->X_add_number < 0 | |
2205 | || imm_expr->X_add_number >= 3) | |
2206 | { | |
2207 | as_bad (_("bad value for opcode field, " | |
2208 | "value must be 0...2")); | |
2209 | break; | |
2210 | } | |
2211 | ||
2212 | INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); | |
2213 | imm_expr->X_op = O_absent; | |
2214 | s = expr_end; | |
2215 | continue; | |
2216 | default: | |
2217 | as_bad (_("bad Opcode field specifier 'O%c'\n"), *args); | |
2218 | } | |
2219 | break; | |
2220 | ||
2221 | case 'F': | |
2222 | switch (*++args) | |
2223 | { | |
2224 | case '7': | |
2225 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2226 | || imm_expr->X_op != O_constant | |
2227 | || imm_expr->X_add_number < 0 | |
2228 | || imm_expr->X_add_number >= 128) | |
2229 | { | |
2230 | as_bad (_("bad value for funct7 field, " | |
2231 | "value must be 0...127")); | |
2232 | break; | |
2233 | } | |
2234 | ||
2235 | INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); | |
2236 | imm_expr->X_op = O_absent; | |
2237 | s = expr_end; | |
2238 | continue; | |
2239 | case '3': | |
2240 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2241 | || imm_expr->X_op != O_constant | |
2242 | || imm_expr->X_add_number < 0 | |
2243 | || imm_expr->X_add_number >= 8) | |
2244 | { | |
2245 | as_bad (_("bad value for funct3 field, " | |
2246 | "value must be 0...7")); | |
2247 | break; | |
2248 | } | |
2249 | ||
2250 | INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); | |
2251 | imm_expr->X_op = O_absent; | |
2252 | s = expr_end; | |
2253 | continue; | |
2254 | case '2': | |
2255 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2256 | || imm_expr->X_op != O_constant | |
2257 | || imm_expr->X_add_number < 0 | |
2258 | || imm_expr->X_add_number >= 4) | |
2259 | { | |
2260 | as_bad (_("bad value for funct2 field, " | |
2261 | "value must be 0...3")); | |
2262 | break; | |
2263 | } | |
2264 | ||
2265 | INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); | |
2266 | imm_expr->X_op = O_absent; | |
2267 | s = expr_end; | |
2268 | continue; | |
2269 | ||
2270 | default: | |
2271 | as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args); | |
2272 | } | |
2273 | break; | |
e23eba97 | 2274 | |
e925c834 JW |
2275 | case 'z': |
2276 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2277 | || imm_expr->X_op != O_constant | |
2278 | || imm_expr->X_add_number != 0) | |
2279 | break; | |
2280 | s = expr_end; | |
2281 | imm_expr->X_op = O_absent; | |
2282 | continue; | |
2283 | ||
e23eba97 NC |
2284 | default: |
2285 | as_fatal (_("internal error: bad argument type %c"), *args); | |
2286 | } | |
2287 | break; | |
2288 | } | |
2289 | s = argsStart; | |
2290 | error = _("illegal operands"); | |
54b2aec1 | 2291 | insn_with_csr = FALSE; |
e23eba97 NC |
2292 | } |
2293 | ||
dc1e8a47 | 2294 | out: |
e23eba97 NC |
2295 | /* Restore the character we might have clobbered above. */ |
2296 | if (save_c) | |
2297 | *(argsStart - 1) = save_c; | |
2298 | ||
2299 | return error; | |
2300 | } | |
2301 | ||
2302 | void | |
2303 | md_assemble (char *str) | |
2304 | { | |
2305 | struct riscv_cl_insn insn; | |
2306 | expressionS imm_expr; | |
2307 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
2308 | ||
0e35537d | 2309 | const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); |
e23eba97 | 2310 | |
2dc8dd17 JW |
2311 | start_assemble = TRUE; |
2312 | ||
e23eba97 NC |
2313 | if (error) |
2314 | { | |
2315 | as_bad ("%s `%s'", error, str); | |
2316 | return; | |
2317 | } | |
2318 | ||
2319 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2320 | macro (&insn, &imm_expr, &imm_reloc); | |
2321 | else | |
2322 | append_insn (&insn, &imm_expr, imm_reloc); | |
2323 | } | |
2324 | ||
2325 | const char * | |
2326 | md_atof (int type, char *litP, int *sizeP) | |
2327 | { | |
2328 | return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); | |
2329 | } | |
2330 | ||
2331 | void | |
2332 | md_number_to_chars (char *buf, valueT val, int n) | |
2333 | { | |
2334 | number_to_chars_littleendian (buf, val, n); | |
2335 | } | |
2336 | ||
2337 | const char *md_shortopts = "O::g::G:"; | |
2338 | ||
2339 | enum options | |
2340 | { | |
2922d21d | 2341 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
2342 | OPTION_PIC, |
2343 | OPTION_NO_PIC, | |
2922d21d | 2344 | OPTION_MABI, |
71060565 JW |
2345 | OPTION_RELAX, |
2346 | OPTION_NO_RELAX, | |
2dc8dd17 JW |
2347 | OPTION_ARCH_ATTR, |
2348 | OPTION_NO_ARCH_ATTR, | |
2ca89224 NC |
2349 | OPTION_CSR_CHECK, |
2350 | OPTION_NO_CSR_CHECK, | |
e23eba97 NC |
2351 | OPTION_END_OF_ENUM |
2352 | }; | |
2353 | ||
2354 | struct option md_longopts[] = | |
2355 | { | |
e23eba97 NC |
2356 | {"march", required_argument, NULL, OPTION_MARCH}, |
2357 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
2358 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
2359 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 2360 | {"mabi", required_argument, NULL, OPTION_MABI}, |
71060565 JW |
2361 | {"mrelax", no_argument, NULL, OPTION_RELAX}, |
2362 | {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
2dc8dd17 JW |
2363 | {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR}, |
2364 | {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR}, | |
2ca89224 NC |
2365 | {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK}, |
2366 | {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK}, | |
e23eba97 NC |
2367 | |
2368 | {NULL, no_argument, NULL, 0} | |
2369 | }; | |
2370 | size_t md_longopts_size = sizeof (md_longopts); | |
2371 | ||
2922d21d AW |
2372 | enum float_abi { |
2373 | FLOAT_ABI_DEFAULT = -1, | |
2374 | FLOAT_ABI_SOFT, | |
2375 | FLOAT_ABI_SINGLE, | |
2376 | FLOAT_ABI_DOUBLE, | |
2377 | FLOAT_ABI_QUAD | |
e23eba97 | 2378 | }; |
2922d21d AW |
2379 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; |
2380 | ||
2381 | static void | |
7f999549 | 2382 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve) |
2922d21d AW |
2383 | { |
2384 | abi_xlen = new_xlen; | |
2385 | float_abi = new_float_abi; | |
7f999549 | 2386 | rve_abi = rve; |
2922d21d | 2387 | } |
e23eba97 NC |
2388 | |
2389 | int | |
2390 | md_parse_option (int c, const char *arg) | |
2391 | { | |
2392 | switch (c) | |
2393 | { | |
e23eba97 NC |
2394 | case OPTION_MARCH: |
2395 | riscv_set_arch (arg); | |
2396 | break; | |
2397 | ||
2398 | case OPTION_NO_PIC: | |
2399 | riscv_opts.pic = FALSE; | |
2400 | break; | |
2401 | ||
2402 | case OPTION_PIC: | |
2403 | riscv_opts.pic = TRUE; | |
2404 | break; | |
2405 | ||
2922d21d AW |
2406 | case OPTION_MABI: |
2407 | if (strcmp (arg, "ilp32") == 0) | |
7f999549 JW |
2408 | riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE); |
2409 | else if (strcmp (arg, "ilp32e") == 0) | |
2410 | riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE); | |
2922d21d | 2411 | else if (strcmp (arg, "ilp32f") == 0) |
7f999549 | 2412 | riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE); |
2922d21d | 2413 | else if (strcmp (arg, "ilp32d") == 0) |
7f999549 | 2414 | riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE); |
2922d21d | 2415 | else if (strcmp (arg, "ilp32q") == 0) |
7f999549 | 2416 | riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE); |
2922d21d | 2417 | else if (strcmp (arg, "lp64") == 0) |
7f999549 | 2418 | riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE); |
2922d21d | 2419 | else if (strcmp (arg, "lp64f") == 0) |
7f999549 | 2420 | riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE); |
2922d21d | 2421 | else if (strcmp (arg, "lp64d") == 0) |
7f999549 | 2422 | riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE); |
2922d21d | 2423 | else if (strcmp (arg, "lp64q") == 0) |
7f999549 | 2424 | riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE); |
2922d21d AW |
2425 | else |
2426 | return 0; | |
2427 | break; | |
2428 | ||
71060565 JW |
2429 | case OPTION_RELAX: |
2430 | riscv_opts.relax = TRUE; | |
2431 | break; | |
2432 | ||
2433 | case OPTION_NO_RELAX: | |
2434 | riscv_opts.relax = FALSE; | |
2435 | break; | |
2436 | ||
2dc8dd17 JW |
2437 | case OPTION_ARCH_ATTR: |
2438 | riscv_opts.arch_attr = TRUE; | |
2439 | break; | |
2440 | ||
2441 | case OPTION_NO_ARCH_ATTR: | |
2442 | riscv_opts.arch_attr = FALSE; | |
2443 | break; | |
2444 | ||
2ca89224 NC |
2445 | case OPTION_CSR_CHECK: |
2446 | riscv_opts.csr_check = TRUE; | |
2447 | break; | |
2448 | ||
2449 | case OPTION_NO_CSR_CHECK: | |
2450 | riscv_opts.csr_check = FALSE; | |
2451 | break; | |
2452 | ||
e23eba97 NC |
2453 | default: |
2454 | return 0; | |
2455 | } | |
2456 | ||
2457 | return 1; | |
2458 | } | |
2459 | ||
2460 | void | |
2461 | riscv_after_parse_args (void) | |
2462 | { | |
e23eba97 NC |
2463 | if (xlen == 0) |
2464 | { | |
2465 | if (strcmp (default_arch, "riscv32") == 0) | |
2466 | xlen = 32; | |
2467 | else if (strcmp (default_arch, "riscv64") == 0) | |
2468 | xlen = 64; | |
2469 | else | |
2470 | as_bad ("unknown default architecture `%s'", default_arch); | |
2471 | } | |
2922d21d | 2472 | |
1080bf78 | 2473 | if (riscv_subsets.head == NULL) |
2922d21d AW |
2474 | riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g"); |
2475 | ||
2476 | /* Add the RVC extension, regardless of -march, to support .option rvc. */ | |
fecb9c46 | 2477 | riscv_set_rvc (FALSE); |
1080bf78 | 2478 | if (riscv_subset_supports ("c")) |
2922d21d | 2479 | riscv_set_rvc (TRUE); |
2922d21d | 2480 | |
7f999549 JW |
2481 | /* Enable RVE if specified by the -march option. */ |
2482 | riscv_set_rve (FALSE); | |
1080bf78 | 2483 | if (riscv_subset_supports ("e")) |
7f999549 JW |
2484 | riscv_set_rve (TRUE); |
2485 | ||
2922d21d AW |
2486 | /* Infer ABI from ISA if not specified on command line. */ |
2487 | if (abi_xlen == 0) | |
2488 | abi_xlen = xlen; | |
2489 | else if (abi_xlen > xlen) | |
2490 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
2491 | else if (abi_xlen < xlen) | |
2492 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
2493 | ||
2494 | if (float_abi == FLOAT_ABI_DEFAULT) | |
2495 | { | |
1080bf78 | 2496 | riscv_subset_t *subset; |
2922d21d AW |
2497 | |
2498 | /* Assume soft-float unless D extension is present. */ | |
2499 | float_abi = FLOAT_ABI_SOFT; | |
2500 | ||
1080bf78 | 2501 | for (subset = riscv_subsets.head; subset != NULL; subset = subset->next) |
cc917fd9 KC |
2502 | { |
2503 | if (strcasecmp (subset->name, "D") == 0) | |
2504 | float_abi = FLOAT_ABI_DOUBLE; | |
2505 | if (strcasecmp (subset->name, "Q") == 0) | |
2506 | float_abi = FLOAT_ABI_QUAD; | |
2507 | } | |
2922d21d AW |
2508 | } |
2509 | ||
7f999549 JW |
2510 | if (rve_abi) |
2511 | elf_flags |= EF_RISCV_RVE; | |
2512 | ||
2922d21d AW |
2513 | /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */ |
2514 | elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1)); | |
0ac2b354 AB |
2515 | |
2516 | /* If the CIE to be produced has not been overridden on the command line, | |
2517 | then produce version 3 by default. This allows us to use the full | |
2518 | range of registers in a .cfi_return_column directive. */ | |
2519 | if (flag_dwarf_cie_version == -1) | |
2520 | flag_dwarf_cie_version = 3; | |
e23eba97 NC |
2521 | } |
2522 | ||
2523 | long | |
2524 | md_pcrel_from (fixS *fixP) | |
2525 | { | |
2526 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
2527 | } | |
2528 | ||
2529 | /* Apply a fixup to the object file. */ | |
2530 | ||
2531 | void | |
2532 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
2533 | { | |
45f76423 | 2534 | unsigned int subtype; |
e23eba97 | 2535 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
45f76423 | 2536 | bfd_boolean relaxable = FALSE; |
c1b465c9 | 2537 | offsetT loc; |
a6cbf936 | 2538 | segT sub_segment; |
e23eba97 NC |
2539 | |
2540 | /* Remember value for tc_gen_reloc. */ | |
2541 | fixP->fx_addnumber = *valP; | |
2542 | ||
2543 | switch (fixP->fx_r_type) | |
2544 | { | |
e23eba97 NC |
2545 | case BFD_RELOC_RISCV_HI20: |
2546 | case BFD_RELOC_RISCV_LO12_I: | |
2547 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
2548 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
2549 | | bfd_getl32 (buf), buf); | |
a5ec5e3f AW |
2550 | if (fixP->fx_addsy == NULL) |
2551 | fixP->fx_done = TRUE; | |
45f76423 AW |
2552 | relaxable = TRUE; |
2553 | break; | |
2554 | ||
2555 | case BFD_RELOC_RISCV_GOT_HI20: | |
e23eba97 NC |
2556 | case BFD_RELOC_RISCV_ADD8: |
2557 | case BFD_RELOC_RISCV_ADD16: | |
2558 | case BFD_RELOC_RISCV_ADD32: | |
2559 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 2560 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
2561 | case BFD_RELOC_RISCV_SUB8: |
2562 | case BFD_RELOC_RISCV_SUB16: | |
2563 | case BFD_RELOC_RISCV_SUB32: | |
2564 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 AW |
2565 | case BFD_RELOC_RISCV_RELAX: |
2566 | break; | |
2567 | ||
2568 | case BFD_RELOC_RISCV_TPREL_HI20: | |
2569 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
2570 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
2571 | case BFD_RELOC_RISCV_TPREL_ADD: | |
2572 | relaxable = TRUE; | |
2573 | /* Fall through. */ | |
2574 | ||
2575 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
2576 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
2577 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
2578 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
2579 | if (fixP->fx_addsy != NULL) |
2580 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2581 | else | |
2582 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2583 | _("TLS relocation against a constant")); | |
e23eba97 NC |
2584 | break; |
2585 | ||
e23eba97 | 2586 | case BFD_RELOC_32: |
a6cbf936 KLC |
2587 | /* Use pc-relative relocation for FDE initial location. |
2588 | The symbol address in .eh_frame may be adjusted in | |
2589 | _bfd_elf_discard_section_eh_frame, and the content of | |
2590 | .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. | |
2591 | Therefore, we cannot insert a relocation whose addend symbol is | |
2592 | in .eh_frame. Othrewise, the value may be adjusted twice.*/ | |
2593 | if (fixP->fx_addsy && fixP->fx_subsy | |
2594 | && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) | |
2595 | && strcmp (sub_segment->name, ".eh_frame") == 0 | |
2596 | && S_GET_VALUE (fixP->fx_subsy) | |
2597 | == fixP->fx_frag->fr_address + fixP->fx_where) | |
2598 | { | |
2599 | fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; | |
2600 | fixP->fx_subsy = NULL; | |
2601 | break; | |
2602 | } | |
2603 | /* Fall through. */ | |
2604 | case BFD_RELOC_64: | |
e23eba97 NC |
2605 | case BFD_RELOC_16: |
2606 | case BFD_RELOC_8: | |
45f76423 | 2607 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
2608 | if (fixP->fx_addsy && fixP->fx_subsy) |
2609 | { | |
2610 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2611 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
2612 | fixP->fx_next->fx_subsy = NULL; | |
2613 | fixP->fx_next->fx_offset = 0; | |
2614 | fixP->fx_subsy = NULL; | |
2615 | ||
2616 | switch (fixP->fx_r_type) | |
2617 | { | |
2618 | case BFD_RELOC_64: | |
2619 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
2620 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
2621 | break; | |
2622 | ||
2623 | case BFD_RELOC_32: | |
2624 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
2625 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
2626 | break; | |
2627 | ||
2628 | case BFD_RELOC_16: | |
2629 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
2630 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
2631 | break; | |
2632 | ||
2633 | case BFD_RELOC_8: | |
2634 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
2635 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 2636 | break; |
e23eba97 | 2637 | |
45f76423 AW |
2638 | case BFD_RELOC_RISCV_CFA: |
2639 | /* Load the byte to get the subtype. */ | |
c1b465c9 KLC |
2640 | subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); |
2641 | loc = fixP->fx_frag->fr_fix - (subtype & 7); | |
45f76423 AW |
2642 | switch (subtype) |
2643 | { | |
2644 | case DW_CFA_advance_loc1: | |
c1b465c9 KLC |
2645 | fixP->fx_where = loc + 1; |
2646 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
2647 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; |
2648 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
2649 | break; | |
2650 | ||
2651 | case DW_CFA_advance_loc2: | |
2652 | fixP->fx_size = 2; | |
45f76423 | 2653 | fixP->fx_next->fx_size = 2; |
c1b465c9 KLC |
2654 | fixP->fx_where = loc + 1; |
2655 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
2656 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; |
2657 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
2658 | break; | |
2659 | ||
2660 | case DW_CFA_advance_loc4: | |
2661 | fixP->fx_size = 4; | |
45f76423 | 2662 | fixP->fx_next->fx_size = 4; |
c1b465c9 KLC |
2663 | fixP->fx_where = loc; |
2664 | fixP->fx_next->fx_where = loc; | |
45f76423 AW |
2665 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; |
2666 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
2667 | break; | |
2668 | ||
2669 | default: | |
2670 | if (subtype < 0x80 && (subtype & 0x40)) | |
2671 | { | |
2672 | /* DW_CFA_advance_loc */ | |
2aece2ba KLC |
2673 | fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; |
2674 | fixP->fx_next->fx_frag = fixP->fx_frag; | |
45f76423 AW |
2675 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; |
2676 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
2677 | } | |
2678 | else | |
2679 | as_fatal (_("internal error: bad CFA value #%d"), subtype); | |
2680 | break; | |
2681 | } | |
2682 | break; | |
2683 | ||
e23eba97 NC |
2684 | default: |
2685 | /* This case is unreachable. */ | |
2686 | abort (); | |
2687 | } | |
2688 | } | |
2689 | /* Fall through. */ | |
2690 | ||
2691 | case BFD_RELOC_RVA: | |
2692 | /* If we are deleting this reloc entry, we must fill in the | |
2693 | value now. This can happen if we have a .word which is not | |
2694 | resolved when it appears but is later defined. */ | |
2695 | if (fixP->fx_addsy == NULL) | |
2696 | { | |
2697 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
2698 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
2699 | fixP->fx_done = 1; | |
2700 | } | |
2701 | break; | |
2702 | ||
2703 | case BFD_RELOC_RISCV_JMP: | |
2704 | if (fixP->fx_addsy) | |
2705 | { | |
2706 | /* Fill in a tentative value to improve objdump readability. */ | |
2707 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2708 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2709 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); | |
2710 | } | |
2711 | break; | |
2712 | ||
2713 | case BFD_RELOC_12_PCREL: | |
2714 | if (fixP->fx_addsy) | |
2715 | { | |
2716 | /* Fill in a tentative value to improve objdump readability. */ | |
2717 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2718 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2719 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); | |
2720 | } | |
2721 | break; | |
2722 | ||
2723 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
2724 | if (fixP->fx_addsy) | |
2725 | { | |
2726 | /* Fill in a tentative value to improve objdump readability. */ | |
2727 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2728 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2729 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); | |
2730 | } | |
2731 | break; | |
2732 | ||
2733 | case BFD_RELOC_RISCV_RVC_JUMP: | |
2734 | if (fixP->fx_addsy) | |
2735 | { | |
2736 | /* Fill in a tentative value to improve objdump readability. */ | |
2737 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2738 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2739 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); | |
2740 | } | |
2741 | break; | |
2742 | ||
e23eba97 NC |
2743 | case BFD_RELOC_RISCV_CALL: |
2744 | case BFD_RELOC_RISCV_CALL_PLT: | |
45f76423 AW |
2745 | relaxable = TRUE; |
2746 | break; | |
2747 | ||
9d06997a | 2748 | case BFD_RELOC_RISCV_PCREL_HI20: |
45f76423 AW |
2749 | case BFD_RELOC_RISCV_PCREL_LO12_S: |
2750 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
9d06997a PD |
2751 | relaxable = riscv_opts.relax; |
2752 | break; | |
2753 | ||
e23eba97 NC |
2754 | case BFD_RELOC_RISCV_ALIGN: |
2755 | break; | |
2756 | ||
2757 | default: | |
2758 | /* We ignore generic BFD relocations we don't know about. */ | |
2759 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
2760 | as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); | |
2761 | } | |
45f76423 | 2762 | |
e294484e AW |
2763 | if (fixP->fx_subsy != NULL) |
2764 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2765 | _("unsupported symbol subtraction")); | |
2766 | ||
45f76423 AW |
2767 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
2768 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
2769 | { | |
2770 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2771 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
2772 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
2773 | } | |
2774 | } | |
2775 | ||
2776 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
2777 | we insert a fix to relocate it again in link-time. */ | |
2778 | ||
2779 | void | |
2780 | riscv_pre_output_hook (void) | |
2781 | { | |
2782 | const frchainS *frch; | |
2783 | const asection *s; | |
2784 | ||
2785 | for (s = stdoutput->sections; s; s = s->next) | |
2786 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
2787 | { | |
7cb7b948 | 2788 | fragS *frag; |
45f76423 AW |
2789 | |
2790 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
2791 | { | |
2792 | if (frag->fr_type == rs_cfa) | |
2793 | { | |
45f76423 | 2794 | expressionS exp; |
8d1015a8 | 2795 | expressionS *symval; |
45f76423 | 2796 | |
8d1015a8 | 2797 | symval = symbol_get_value_expression (frag->fr_symbol); |
45f76423 | 2798 | exp.X_op = O_subtract; |
8d1015a8 | 2799 | exp.X_add_symbol = symval->X_add_symbol; |
45f76423 | 2800 | exp.X_add_number = 0; |
8d1015a8 | 2801 | exp.X_op_symbol = symval->X_op_symbol; |
45f76423 | 2802 | |
c1b465c9 | 2803 | fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, |
45f76423 AW |
2804 | BFD_RELOC_RISCV_CFA); |
2805 | } | |
2806 | } | |
2807 | } | |
e23eba97 NC |
2808 | } |
2809 | ||
45f76423 | 2810 | |
e23eba97 NC |
2811 | /* This structure is used to hold a stack of .option values. */ |
2812 | ||
2813 | struct riscv_option_stack | |
2814 | { | |
2815 | struct riscv_option_stack *next; | |
2816 | struct riscv_set_options options; | |
2817 | }; | |
2818 | ||
2819 | static struct riscv_option_stack *riscv_opts_stack; | |
2820 | ||
2821 | /* Handle the .option pseudo-op. */ | |
2822 | ||
2823 | static void | |
2824 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
2825 | { | |
2826 | char *name = input_line_pointer, ch; | |
2827 | ||
2828 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2829 | ++input_line_pointer; | |
2830 | ch = *input_line_pointer; | |
2831 | *input_line_pointer = '\0'; | |
2832 | ||
2833 | if (strcmp (name, "rvc") == 0) | |
2834 | riscv_set_rvc (TRUE); | |
2835 | else if (strcmp (name, "norvc") == 0) | |
2836 | riscv_set_rvc (FALSE); | |
2837 | else if (strcmp (name, "pic") == 0) | |
2838 | riscv_opts.pic = TRUE; | |
2839 | else if (strcmp (name, "nopic") == 0) | |
2840 | riscv_opts.pic = FALSE; | |
45f76423 AW |
2841 | else if (strcmp (name, "relax") == 0) |
2842 | riscv_opts.relax = TRUE; | |
2843 | else if (strcmp (name, "norelax") == 0) | |
2844 | riscv_opts.relax = FALSE; | |
2ca89224 NC |
2845 | else if (strcmp (name, "csr-check") == 0) |
2846 | riscv_opts.csr_check = TRUE; | |
2847 | else if (strcmp (name, "no-csr-check") == 0) | |
2848 | riscv_opts.csr_check = FALSE; | |
e23eba97 NC |
2849 | else if (strcmp (name, "push") == 0) |
2850 | { | |
2851 | struct riscv_option_stack *s; | |
2852 | ||
2853 | s = (struct riscv_option_stack *) xmalloc (sizeof *s); | |
2854 | s->next = riscv_opts_stack; | |
2855 | s->options = riscv_opts; | |
2856 | riscv_opts_stack = s; | |
2857 | } | |
2858 | else if (strcmp (name, "pop") == 0) | |
2859 | { | |
2860 | struct riscv_option_stack *s; | |
2861 | ||
2862 | s = riscv_opts_stack; | |
2863 | if (s == NULL) | |
2864 | as_bad (_(".option pop with no .option push")); | |
2865 | else | |
2866 | { | |
2867 | riscv_opts = s->options; | |
2868 | riscv_opts_stack = s->next; | |
2869 | free (s); | |
2870 | } | |
2871 | } | |
2872 | else | |
2873 | { | |
2874 | as_warn (_("Unrecognized .option directive: %s\n"), name); | |
2875 | } | |
2876 | *input_line_pointer = ch; | |
2877 | demand_empty_rest_of_line (); | |
2878 | } | |
2879 | ||
2880 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
2881 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
2882 | use in DWARF debug information. */ | |
2883 | ||
2884 | static void | |
2885 | s_dtprel (int bytes) | |
2886 | { | |
2887 | expressionS ex; | |
2888 | char *p; | |
2889 | ||
2890 | expression (&ex); | |
2891 | ||
2892 | if (ex.X_op != O_symbol) | |
2893 | { | |
2894 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
2895 | ? ".dtpreldword" | |
2896 | : ".dtprelword")); | |
2897 | ignore_rest_of_line (); | |
2898 | } | |
2899 | ||
2900 | p = frag_more (bytes); | |
2901 | md_number_to_chars (p, 0, bytes); | |
2902 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
2903 | (bytes == 8 | |
2904 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
2905 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
2906 | ||
2907 | demand_empty_rest_of_line (); | |
2908 | } | |
2909 | ||
2910 | /* Handle the .bss pseudo-op. */ | |
2911 | ||
2912 | static void | |
2913 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
2914 | { | |
2915 | subseg_set (bss_section, 0); | |
2916 | demand_empty_rest_of_line (); | |
2917 | } | |
2918 | ||
e23eba97 | 2919 | static void |
d115ab8e | 2920 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 2921 | { |
d115ab8e | 2922 | bfd_vma i = 0; |
e23eba97 | 2923 | |
e5b737de AW |
2924 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
2925 | means we are not within a valid instruction sequence. It is thus safe | |
2926 | to use a zero byte, even though that is not a valid instruction. */ | |
2927 | if (bytes % 2 == 1) | |
2928 | buf[i++] = 0; | |
2929 | ||
2930 | /* Use at most one 2-byte NOP. */ | |
2931 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 2932 | { |
e5b737de | 2933 | md_number_to_chars (buf + i, RVC_NOP, 2); |
d115ab8e | 2934 | i += 2; |
e23eba97 NC |
2935 | } |
2936 | ||
e5b737de | 2937 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e AW |
2938 | for ( ; i < bytes; i += 4) |
2939 | md_number_to_chars (buf + i, RISCV_NOP, 4); | |
2940 | } | |
e23eba97 | 2941 | |
d115ab8e AW |
2942 | /* Called from md_do_align. Used to create an alignment frag in a |
2943 | code section by emitting a worst-case NOP sequence that the linker | |
2944 | will later relax to the correct number of NOPs. We can't compute | |
2945 | the correct alignment now because of other linker relaxations. */ | |
2946 | ||
2947 | bfd_boolean | |
2948 | riscv_frag_align_code (int n) | |
2949 | { | |
e5b737de | 2950 | bfd_vma bytes = (bfd_vma) 1 << n; |
36877bfb JW |
2951 | bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; |
2952 | bfd_vma worst_case_bytes = bytes - insn_alignment; | |
2953 | char *nops; | |
ed0816bd | 2954 | expressionS ex; |
d115ab8e | 2955 | |
36877bfb JW |
2956 | /* If we are moving to a smaller alignment than the instruction size, then no |
2957 | alignment is required. */ | |
2958 | if (bytes <= insn_alignment) | |
2959 | return TRUE; | |
2960 | ||
d115ab8e AW |
2961 | /* When not relaxing, riscv_handle_align handles code alignment. */ |
2962 | if (!riscv_opts.relax) | |
2963 | return FALSE; | |
e23eba97 | 2964 | |
e80ae190 JW |
2965 | nops = frag_more (worst_case_bytes); |
2966 | ||
ed0816bd PD |
2967 | ex.X_op = O_constant; |
2968 | ex.X_add_number = worst_case_bytes; | |
d115ab8e | 2969 | |
ed0816bd | 2970 | riscv_make_nops (nops, worst_case_bytes); |
e23eba97 | 2971 | |
ed0816bd PD |
2972 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
2973 | &ex, FALSE, BFD_RELOC_RISCV_ALIGN); | |
e23eba97 | 2974 | |
d115ab8e AW |
2975 | return TRUE; |
2976 | } | |
e23eba97 | 2977 | |
d115ab8e AW |
2978 | /* Implement HANDLE_ALIGN. */ |
2979 | ||
2980 | void | |
2981 | riscv_handle_align (fragS *fragP) | |
2982 | { | |
2983 | switch (fragP->fr_type) | |
2984 | { | |
2985 | case rs_align_code: | |
2986 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
2987 | if (!riscv_opts.relax) | |
2988 | { | |
e80ae190 JW |
2989 | bfd_signed_vma bytes = (fragP->fr_next->fr_address |
2990 | - fragP->fr_address - fragP->fr_fix); | |
2991 | /* We have 4 byte uncompressed nops. */ | |
2992 | bfd_signed_vma size = 4; | |
2993 | bfd_signed_vma excess = bytes % size; | |
2994 | char *p = fragP->fr_literal + fragP->fr_fix; | |
2995 | ||
2996 | if (bytes <= 0) | |
d115ab8e AW |
2997 | break; |
2998 | ||
e80ae190 JW |
2999 | /* Insert zeros or compressed nops to get 4 byte alignment. */ |
3000 | if (excess) | |
3001 | { | |
3002 | riscv_make_nops (p, excess); | |
3003 | fragP->fr_fix += excess; | |
3004 | p += excess; | |
3005 | } | |
3006 | ||
3007 | /* Insert variable number of 4 byte uncompressed nops. */ | |
3008 | riscv_make_nops (p, size); | |
3009 | fragP->fr_var = size; | |
d115ab8e AW |
3010 | } |
3011 | break; | |
3012 | ||
3013 | default: | |
3014 | break; | |
3015 | } | |
e23eba97 NC |
3016 | } |
3017 | ||
3018 | int | |
3019 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
3020 | { | |
3021 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); | |
3022 | } | |
3023 | ||
3024 | /* Translate internal representation of relocation info to BFD target | |
3025 | format. */ | |
3026 | ||
3027 | arelent * | |
3028 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
3029 | { | |
3030 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3031 | ||
3032 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
3033 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
3034 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3035 | reloc->addend = fixp->fx_addnumber; | |
3036 | ||
3037 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
3038 | if (reloc->howto == NULL) | |
3039 | { | |
3040 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
3041 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
3042 | { | |
3043 | /* We don't have R_RISCV_8/16, but for this special case, | |
3044 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
3045 | return reloc; | |
3046 | } | |
3047 | ||
3048 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3049 | _("cannot represent %s relocation in object file"), | |
3050 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
3051 | return NULL; | |
3052 | } | |
3053 | ||
3054 | return reloc; | |
3055 | } | |
3056 | ||
3057 | int | |
3058 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
3059 | { | |
3060 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
3061 | { | |
3062 | offsetT old_var = fragp->fr_var; | |
3063 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
3064 | return fragp->fr_var - old_var; | |
3065 | } | |
3066 | ||
3067 | return 0; | |
3068 | } | |
3069 | ||
3070 | /* Expand far branches to multi-instruction sequences. */ | |
3071 | ||
3072 | static void | |
3073 | md_convert_frag_branch (fragS *fragp) | |
3074 | { | |
3075 | bfd_byte *buf; | |
3076 | expressionS exp; | |
3077 | fixS *fixp; | |
3078 | insn_t insn; | |
3079 | int rs1, reloc; | |
3080 | ||
3081 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
3082 | ||
3083 | exp.X_op = O_symbol; | |
3084 | exp.X_add_symbol = fragp->fr_symbol; | |
3085 | exp.X_add_number = fragp->fr_offset; | |
3086 | ||
3087 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
3088 | ||
3089 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
3090 | { | |
3091 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
3092 | { | |
3093 | case 8: | |
3094 | case 4: | |
3095 | /* Expand the RVC branch into a RISC-V one. */ | |
3096 | insn = bfd_getl16 (buf); | |
3097 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
3098 | if ((insn & MASK_C_J) == MATCH_C_J) | |
3099 | insn = MATCH_JAL; | |
3100 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
3101 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
3102 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
3103 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
3104 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
3105 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
3106 | else | |
3107 | abort (); | |
3108 | bfd_putl32 (insn, buf); | |
3109 | break; | |
3110 | ||
3111 | case 6: | |
3112 | /* Invert the branch condition. Branch over the jump. */ | |
3113 | insn = bfd_getl16 (buf); | |
3114 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
3115 | insn |= ENCODE_RVC_B_IMM (6); | |
3116 | bfd_putl16 (insn, buf); | |
3117 | buf += 2; | |
3118 | goto jump; | |
3119 | ||
3120 | case 2: | |
3121 | /* Just keep the RVC branch. */ | |
3122 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
3123 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
3124 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3125 | 2, &exp, FALSE, reloc); | |
3126 | buf += 2; | |
3127 | goto done; | |
3128 | ||
3129 | default: | |
1d65abb5 | 3130 | abort (); |
e23eba97 NC |
3131 | } |
3132 | } | |
3133 | ||
3134 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
3135 | { | |
3136 | case 8: | |
3137 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
3138 | ||
3139 | /* Invert the branch condition. Branch over the jump. */ | |
3140 | insn = bfd_getl32 (buf); | |
3141 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
3142 | insn |= ENCODE_SBTYPE_IMM (8); | |
3143 | md_number_to_chars ((char *) buf, insn, 4); | |
3144 | buf += 4; | |
3145 | ||
dc1e8a47 | 3146 | jump: |
e23eba97 NC |
3147 | /* Jump to the target. */ |
3148 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3149 | 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); | |
3150 | md_number_to_chars ((char *) buf, MATCH_JAL, 4); | |
3151 | buf += 4; | |
3152 | break; | |
3153 | ||
3154 | case 4: | |
3155 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
3156 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
3157 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3158 | 4, &exp, FALSE, reloc); | |
3159 | buf += 4; | |
3160 | break; | |
3161 | ||
3162 | default: | |
3163 | abort (); | |
3164 | } | |
3165 | ||
dc1e8a47 | 3166 | done: |
e23eba97 NC |
3167 | fixp->fx_file = fragp->fr_file; |
3168 | fixp->fx_line = fragp->fr_line; | |
3169 | ||
3170 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
3171 | + fragp->fr_fix + fragp->fr_var); | |
3172 | ||
3173 | fragp->fr_fix += fragp->fr_var; | |
3174 | } | |
3175 | ||
3176 | /* Relax a machine dependent frag. This returns the amount by which | |
3177 | the current size of the frag should change. */ | |
3178 | ||
3179 | void | |
3180 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
3181 | fragS *fragp) | |
3182 | { | |
3183 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
3184 | md_convert_frag_branch (fragp); | |
3185 | } | |
3186 | ||
3187 | void | |
3188 | md_show_usage (FILE *stream) | |
3189 | { | |
3190 | fprintf (stream, _("\ | |
3191 | RISC-V options:\n\ | |
e23eba97 NC |
3192 | -fpic generate position-independent code\n\ |
3193 | -fno-pic don't generate position-independent code (default)\n\ | |
19683c04 PD |
3194 | -march=ISA set the RISC-V architecture\n\ |
3195 | -mabi=ABI set the RISC-V ABI\n\ | |
71060565 JW |
3196 | -mrelax enable relax (default)\n\ |
3197 | -mno-relax disable relax\n\ | |
2dc8dd17 JW |
3198 | -march-attr generate RISC-V arch attribute\n\ |
3199 | -mno-arch-attr don't generate RISC-V arch attribute\n\ | |
e23eba97 NC |
3200 | ")); |
3201 | } | |
3202 | ||
3203 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
3204 | void | |
3205 | riscv_cfi_frame_initial_instructions (void) | |
3206 | { | |
3207 | cfi_add_CFA_def_cfa_register (X_SP); | |
3208 | } | |
3209 | ||
3210 | int | |
3211 | tc_riscv_regname_to_dw2regnum (char *regname) | |
3212 | { | |
3213 | int reg; | |
3214 | ||
3215 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
3216 | return reg; | |
3217 | ||
3218 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
3219 | return reg + 32; | |
3220 | ||
4762fe62 AB |
3221 | /* CSRs are numbered 4096 -> 8191. */ |
3222 | if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) | |
3223 | return reg + 4096; | |
3224 | ||
e23eba97 NC |
3225 | as_bad (_("unknown register `%s'"), regname); |
3226 | return -1; | |
3227 | } | |
3228 | ||
3229 | void | |
3230 | riscv_elf_final_processing (void) | |
3231 | { | |
e23eba97 | 3232 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
3233 | } |
3234 | ||
3235 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
3236 | since these directives break relaxation when used with symbol deltas. */ | |
3237 | ||
3238 | static void | |
3239 | s_riscv_leb128 (int sign) | |
3240 | { | |
3241 | expressionS exp; | |
3242 | char *save_in = input_line_pointer; | |
3243 | ||
3244 | expression (&exp); | |
3245 | if (exp.X_op != O_constant) | |
3246 | as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); | |
3247 | demand_empty_rest_of_line (); | |
3248 | ||
3249 | input_line_pointer = save_in; | |
3250 | return s_leb128 (sign); | |
3251 | } | |
3252 | ||
0e35537d JW |
3253 | /* Parse the .insn directive. */ |
3254 | ||
3255 | static void | |
3256 | s_riscv_insn (int x ATTRIBUTE_UNUSED) | |
3257 | { | |
3258 | char *str = input_line_pointer; | |
3259 | struct riscv_cl_insn insn; | |
3260 | expressionS imm_expr; | |
3261 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
3262 | char save_c; | |
3263 | ||
3264 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
3265 | ++input_line_pointer; | |
3266 | ||
3267 | save_c = *input_line_pointer; | |
3268 | *input_line_pointer = '\0'; | |
3269 | ||
3270 | const char *error = riscv_ip (str, &insn, &imm_expr, | |
3271 | &imm_reloc, insn_type_hash); | |
3272 | ||
3273 | if (error) | |
3274 | { | |
3275 | as_bad ("%s `%s'", error, str); | |
3276 | } | |
3277 | else | |
3278 | { | |
3279 | gas_assert (insn.insn_mo->pinfo != INSN_MACRO); | |
3280 | append_insn (&insn, &imm_expr, imm_reloc); | |
3281 | } | |
3282 | ||
3283 | *input_line_pointer = save_c; | |
3284 | demand_empty_rest_of_line (); | |
3285 | } | |
3286 | ||
2dc8dd17 JW |
3287 | /* Update arch attributes. */ |
3288 | ||
3289 | static void | |
3290 | riscv_write_out_arch_attr (void) | |
3291 | { | |
3292 | const char *arch_str = riscv_arch_str (xlen, &riscv_subsets); | |
3293 | ||
3294 | bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str); | |
3295 | ||
3296 | xfree ((void *)arch_str); | |
3297 | } | |
3298 | ||
3299 | /* Add the default contents for the .riscv.attributes section. */ | |
3300 | ||
3301 | static void | |
3302 | riscv_set_public_attributes (void) | |
3303 | { | |
3304 | if (riscv_opts.arch_attr || explicit_arch_attr) | |
3305 | /* Re-write arch attribute to normalize the arch string. */ | |
3306 | riscv_write_out_arch_attr (); | |
3307 | } | |
3308 | ||
3309 | /* Called after all assembly has been done. */ | |
3310 | ||
3311 | void | |
3312 | riscv_md_end (void) | |
3313 | { | |
3314 | riscv_set_public_attributes (); | |
3315 | } | |
3316 | ||
3317 | /* Given a symbolic attribute NAME, return the proper integer value. | |
3318 | Returns -1 if the attribute is not known. */ | |
3319 | ||
3320 | int | |
3321 | riscv_convert_symbolic_attribute (const char *name) | |
3322 | { | |
3323 | static const struct | |
3324 | { | |
3325 | const char * name; | |
3326 | const int tag; | |
3327 | } | |
3328 | attribute_table[] = | |
3329 | { | |
3330 | /* When you modify this table you should | |
3331 | also modify the list in doc/c-riscv.texi. */ | |
3332 | #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag} | |
3333 | T(arch), | |
3334 | T(priv_spec), | |
3335 | T(priv_spec_minor), | |
3336 | T(priv_spec_revision), | |
3337 | T(unaligned_access), | |
3338 | T(stack_align), | |
3339 | #undef T | |
3340 | }; | |
3341 | ||
3342 | unsigned int i; | |
3343 | ||
3344 | if (name == NULL) | |
3345 | return -1; | |
3346 | ||
3347 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
3348 | if (strcmp (name, attribute_table[i].name) == 0) | |
3349 | return attribute_table[i].tag; | |
3350 | ||
3351 | return -1; | |
3352 | } | |
3353 | ||
3354 | /* Parse a .attribute directive. */ | |
3355 | ||
3356 | static void | |
3357 | s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) | |
3358 | { | |
3359 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); | |
3360 | ||
3361 | if (tag == Tag_RISCV_arch) | |
3362 | { | |
3363 | unsigned old_xlen = xlen; | |
3364 | ||
3365 | explicit_arch_attr = TRUE; | |
3366 | obj_attribute *attr; | |
3367 | attr = elf_known_obj_attributes_proc (stdoutput); | |
3368 | if (!start_assemble) | |
3369 | riscv_set_arch (attr[Tag_RISCV_arch].s); | |
3370 | else | |
3371 | as_fatal (_(".attribute arch must set before any instructions")); | |
3372 | ||
3373 | if (old_xlen != xlen) | |
3374 | { | |
3375 | /* We must re-init bfd again if xlen is changed. */ | |
3376 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
3377 | bfd_find_target (riscv_target_format (), stdoutput); | |
3378 | ||
3379 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
3380 | as_warn (_("Could not set architecture and machine")); | |
3381 | } | |
3382 | } | |
3383 | } | |
3384 | ||
e23eba97 NC |
3385 | /* Pseudo-op table. */ |
3386 | ||
3387 | static const pseudo_typeS riscv_pseudo_table[] = | |
3388 | { | |
3389 | /* RISC-V-specific pseudo-ops. */ | |
3390 | {"option", s_riscv_option, 0}, | |
3391 | {"half", cons, 2}, | |
3392 | {"word", cons, 4}, | |
3393 | {"dword", cons, 8}, | |
3394 | {"dtprelword", s_dtprel, 4}, | |
3395 | {"dtpreldword", s_dtprel, 8}, | |
3396 | {"bss", s_bss, 0}, | |
e23eba97 NC |
3397 | {"uleb128", s_riscv_leb128, 0}, |
3398 | {"sleb128", s_riscv_leb128, 1}, | |
0e35537d | 3399 | {"insn", s_riscv_insn, 0}, |
2dc8dd17 | 3400 | {"attribute", s_riscv_attribute, 0}, |
e23eba97 NC |
3401 | |
3402 | { NULL, NULL, 0 }, | |
3403 | }; | |
3404 | ||
3405 | void | |
3406 | riscv_pop_insert (void) | |
3407 | { | |
3408 | extern void pop_insert (const pseudo_typeS *); | |
3409 | ||
3410 | pop_insert (riscv_pseudo_table); | |
3411 | } |