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RISC-V: Improve the version parsing for arch string.
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
b3adc24a 2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
6e1605e4
NC		 94enum float_abi {
95 FLOAT_ABI_DEFAULT = -1,
96 FLOAT_ABI_SOFT,
97 FLOAT_ABI_SINGLE,
98 FLOAT_ABI_DOUBLE,
99 FLOAT_ABI_QUAD
100};
101static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 102
2922d21d 103#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 104#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
105
106static unsigned elf_flags = 0;
107
8f595e9b
NC		 108/* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
110
111static int
112riscv_set_default_isa_spec (const char *s)
113{
114 enum riscv_isa_spec_class class;
115 if (!riscv_get_isa_spec_class (s, &class))
116 {
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s);
119 return 0;
120 }
121 else
122 default_isa_spec = class;
123 return 1;
124}
125
126/* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
130
131static int
132riscv_set_default_priv_spec (const char *s)
133{
134 enum riscv_priv_spec_class class;
135 unsigned major, minor, revision;
136 obj_attribute *attr;
8f595e9b
NC		 137
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s, &class))
140 {
141 default_priv_spec = class;
142 return 1;
143 }
144
145 if (s != NULL)
146 {
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s);
149 return 0;
150 }
151
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr = elf_known_obj_attributes_proc (stdoutput);
154 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
155 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
156 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
157
39ff0b81
NC		 158 if (riscv_get_priv_spec_class_from_numbers (major,
159 minor,
160 revision,
161 &class))
8f595e9b 162 {
39ff0b81
NC		 163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE)
167 return 1;
8f595e9b 168
8f595e9b 169 default_priv_spec = class;
8f595e9b
NC		 170 return 1;
171 }
172
173 /* Still can not find the priv spec class. */
ddc73fa9 174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
8f595e9b 175 "privilege attributes"), major, minor, revision);
8f595e9b
NC		 176 return 0;
177}
178
e23eba97
NC		 179/* This is the set of options which the .option pseudo-op may modify. */
180
181struct riscv_set_options
182{
183 int pic; /* Generate position-independent code. */
184 int rvc; /* Generate RVC code. */
7f999549 185 int rve; /* Generate RVE code. */
45f76423 186 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 187 int arch_attr; /* Emit arch attribute. */
2ca89224 188 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 189};
190
191static struct riscv_set_options riscv_opts =
192{
193 0, /* pic */
194 0, /* rvc */
7f999549 195 0, /* rve */
45f76423 196 1, /* relax */
2dc8dd17 197 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 198 0. /* csr_check */
e23eba97
NC		 199};
200
201static void
202riscv_set_rvc (bfd_boolean rvc_value)
203{
204 if (rvc_value)
205 elf_flags |= EF_RISCV_RVC;
206
207 riscv_opts.rvc = rvc_value;
208}
209
7f999549
JW		 210static void
211riscv_set_rve (bfd_boolean rve_value)
212{
213 riscv_opts.rve = rve_value;
214}
215
1080bf78 216static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 217
218static bfd_boolean
1080bf78 219riscv_subset_supports (const char *feature)
e23eba97 220{
1080bf78
JW		 221 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
222 return TRUE;
e23eba97 223
1080bf78 224 return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
e23eba97
NC		 225}
226
43135d3b 227static bfd_boolean
7e9ad3a3 228riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 229{
7e9ad3a3
JW		 230 switch (insn_class)
231 {
232 case INSN_CLASS_I: return riscv_subset_supports ("i");
233 case INSN_CLASS_C: return riscv_subset_supports ("c");
234 case INSN_CLASS_A: return riscv_subset_supports ("a");
235 case INSN_CLASS_M: return riscv_subset_supports ("m");
236 case INSN_CLASS_F: return riscv_subset_supports ("f");
237 case INSN_CLASS_D: return riscv_subset_supports ("d");
238 case INSN_CLASS_D_AND_C:
239 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
240
241 case INSN_CLASS_F_AND_C:
242 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
43135d3b 243
7e9ad3a3 244 case INSN_CLASS_Q: return riscv_subset_supports ("q");
43135d3b 245
7e9ad3a3
JW		 246 default:
247 as_fatal ("Unreachable");
248 return FALSE;
249 }
43135d3b
JW		 250}
251
8f595e9b 252/* Handle of the extension with version hash table. */
629310ab 253static htab_t ext_version_hash = NULL;
8f595e9b 254
629310ab 255static htab_t
8f595e9b
NC		 256init_ext_version_hash (const struct riscv_ext_version *table)
257{
258 int i = 0;
629310ab 259 htab_t hash = str_htab_create ();
8f595e9b
NC		 260
261 while (table[i].name)
262 {
263 const char *name = table[i].name;
fe0e921f
AM		 264 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
265 as_fatal (_("duplicate %s"), name);
8f595e9b
NC		 266
267 i++;
268 while (table[i].name
269 && strcmp (table[i].name, name) == 0)
270 i++;
271 }
272
273 return hash;
274}
275
276static void
277riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 278 int *major_version,
279 int *minor_version)
8f595e9b
NC		 280{
281 struct riscv_ext_version *ext;
282
8f595e9b
NC		 283 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
284 return;
285
629310ab 286 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 287 while (ext
7ef19aa6
NC		 288 && ext->name
289 && strcmp (ext->name, name) == 0)
8f595e9b
NC		 290 {
291 if (ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 292 {
293 *major_version = ext->major_version;
294 *minor_version = ext->minor_version;
295 return;
296 }
8f595e9b
NC		 297 ext++;
298 }
299}
300
2922d21d 301/* Set which ISA and extensions are available. */
e23eba97 302
e23eba97 303static void
2922d21d 304riscv_set_arch (const char *s)
e23eba97 305{
1080bf78
JW		 306 riscv_parse_subset_t rps;
307 rps.subset_list = &riscv_subsets;
7ef19aa6 308 rps.error_handler = as_bad;
1080bf78 309 rps.xlen = &xlen;
8f595e9b
NC		 310 rps.get_default_version = riscv_get_default_ext_version;
311
312 if (s == NULL)
313 return;
7f999549 314
1080bf78
JW		 315 riscv_release_subset_list (&riscv_subsets);
316 riscv_parse_subset (&rps, s);
e23eba97
NC		 317}
318
6e1605e4
NC		 319/* Indicate -mabi= option is explictly set. */
320static bfd_boolean explicit_mabi = FALSE;
321
322static void
323riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
324{
325 abi_xlen = new_xlen;
326 float_abi = new_float_abi;
327 rve_abi = rve;
328}
329
330/* If the -mabi option isn't set, then we set the abi according to the arch
331 string. Otherwise, check if there are conflicts between architecture
332 and abi setting. */
333
334static void
335riscv_set_abi_by_arch (void)
336{
337 if (!explicit_mabi)
338 {
339 if (riscv_subset_supports ("q"))
340 riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
341 else if (riscv_subset_supports ("d"))
342 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
343 else
344 riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
345 }
346 else
347 {
348 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
349 if (abi_xlen > xlen)
350 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
351 else if (abi_xlen < xlen)
352 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
353 }
354
355 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
356 elf_flags &= ~EF_RISCV_FLOAT_ABI;
357 elf_flags |= float_abi << 1;
358
359 if (rve_abi)
360 elf_flags |= EF_RISCV_RVE;
361}
362
e23eba97 363/* Handle of the OPCODE hash table. */
629310ab 364static htab_t op_hash = NULL;
e23eba97 365
0e35537d 366/* Handle of the type of .insn hash table. */
629310ab 367static htab_t insn_type_hash = NULL;
0e35537d 368
e23eba97
NC		 369/* This array holds the chars that always start a comment. If the
370 pre-processor is disabled, these aren't very useful */
371const char comment_chars[] = "#";
372
373/* This array holds the chars that only start a comment at the beginning of
374 a line. If the line seems to have the form '# 123 filename'
375 .line and .file directives will appear in the pre-processed output */
376/* Note that input_file.c hand checks for '#' at the beginning of the
377 first line of the input file. This is because the compiler outputs
378 #NO_APP at the beginning of its output. */
379/* Also note that C style comments are always supported. */
380const char line_comment_chars[] = "#";
381
382/* This array holds machine specific line separator characters. */
383const char line_separator_chars[] = ";";
384
385/* Chars that can be used to separate mant from exp in floating point nums */
386const char EXP_CHARS[] = "eE";
387
388/* Chars that mean this number is a floating point constant */
389/* As in 0f12.456 */
390/* or 0d1.2345e12 */
391const char FLT_CHARS[] = "rRsSfFdDxXpP";
392
2dc8dd17
JW		 393/* Indicate we are already assemble any instructions or not. */
394static bfd_boolean start_assemble = FALSE;
395
8f595e9b
NC		 396/* Indicate ELF attributes are explictly set. */
397static bfd_boolean explicit_attr = FALSE;
2dc8dd17 398
1a79004f
NC		 399/* Indicate CSR or priv instructions are explictly used. */
400static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 401
e23eba97
NC		 402/* Macros for encoding relaxation state for RVC branches and far jumps. */
403#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
404 ((relax_substateT) \
405 (0xc0000000 \
406 | ((uncond) ? 1 : 0) \
407 | ((rvc) ? 2 : 0) \
408 | ((length) << 2)))
409#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
410#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
411#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
412#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
413
414/* Is the given value a sign-extended 32-bit value? */
415#define IS_SEXT_32BIT_NUM(x) \
416 (((x) &~ (offsetT) 0x7fffffff) == 0 \
417 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
418
419/* Is the given value a zero-extended 32-bit value? Or a negated one? */
420#define IS_ZEXT_32BIT_NUM(x) \
421 (((x) &~ (offsetT) 0xffffffff) == 0 \
422 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
423
424/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
425 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
426#define INSERT_OPERAND(FIELD, INSN, VALUE) \
427 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
428
429/* Determine if an instruction matches an opcode. */
430#define OPCODE_MATCHES(OPCODE, OP) \
431 (((OPCODE) & MASK_##OP) == MATCH_##OP)
432
433static char *expr_end;
434
435/* The default target format to use. */
436
437const char *
438riscv_target_format (void)
439{
440 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
441}
442
443/* Return the length of instruction INSN. */
444
445static inline unsigned int
446insn_length (const struct riscv_cl_insn *insn)
447{
448 return riscv_insn_length (insn->insn_opcode);
449}
450
451/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
452
453static void
454create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
455{
456 insn->insn_mo = mo;
457 insn->insn_opcode = mo->match;
458 insn->frag = NULL;
459 insn->where = 0;
460 insn->fixp = NULL;
461}
462
463/* Install INSN at the location specified by its "frag" and "where" fields. */
464
465static void
466install_insn (const struct riscv_cl_insn *insn)
467{
468 char *f = insn->frag->fr_literal + insn->where;
469 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
470}
471
472/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
473 and install the opcode in the new location. */
474
475static void
476move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
477{
478 insn->frag = frag;
479 insn->where = where;
480 if (insn->fixp != NULL)
481 {
482 insn->fixp->fx_frag = frag;
483 insn->fixp->fx_where = where;
484 }
485 install_insn (insn);
486}
487
488/* Add INSN to the end of the output. */
489
490static void
491add_fixed_insn (struct riscv_cl_insn *insn)
492{
493 char *f = frag_more (insn_length (insn));
494 move_insn (insn, frag_now, f - frag_now->fr_literal);
495}
496
497static void
498add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
499 relax_substateT subtype, symbolS *symbol, offsetT offset)
500{
501 frag_grow (max_chars);
502 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
503 frag_var (rs_machine_dependent, max_chars, var,
504 subtype, symbol, offset, NULL);
505}
506
507/* Compute the length of a branch sequence, and adjust the stored length
508 accordingly. If FRAGP is NULL, the worst-case length is returned. */
509
510static unsigned
511relaxed_branch_length (fragS *fragp, asection *sec, int update)
512{
513 int jump, rvc, length = 8;
514
515 if (!fragp)
516 return length;
517
518 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
519 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
520 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
521
522 /* Assume jumps are in range; the linker will catch any that aren't. */
523 length = jump ? 4 : 8;
524
525 if (fragp->fr_symbol != NULL
526 && S_IS_DEFINED (fragp->fr_symbol)
01156111 527 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 528 && sec == S_GET_SEGMENT (fragp->fr_symbol))
529 {
530 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
531 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
532 val -= fragp->fr_address + fragp->fr_fix;
533
534 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
535 length = 2;
536 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
537 length = 4;
538 else if (!jump && rvc)
539 length = 6;
540 }
541
542 if (update)
543 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
544
545 return length;
546}
547
0e35537d
JW		 548/* Information about an opcode name, mnemonics and its value. */
549struct opcode_name_t
550{
551 const char *name;
552 unsigned int val;
553};
554
555/* List for all supported opcode name. */
556static const struct opcode_name_t opcode_name_list[] =
557{
558 {"C0", 0x0},
559 {"C1", 0x1},
560 {"C2", 0x2},
561
562 {"LOAD", 0x03},
563 {"LOAD_FP", 0x07},
564 {"CUSTOM_0", 0x0b},
565 {"MISC_MEM", 0x0f},
566 {"OP_IMM", 0x13},
567 {"AUIPC", 0x17},
568 {"OP_IMM_32", 0x1b},
569 /* 48b 0x1f. */
570
571 {"STORE", 0x23},
572 {"STORE_FP", 0x27},
573 {"CUSTOM_1", 0x2b},
574 {"AMO", 0x2f},
575 {"OP", 0x33},
576 {"LUI", 0x37},
577 {"OP_32", 0x3b},
578 /* 64b 0x3f. */
579
580 {"MADD", 0x43},
581 {"MSUB", 0x47},
582 {"NMADD", 0x4f},
583 {"NMSUB", 0x4b},
584 {"OP_FP", 0x53},
585 /*reserved 0x57. */
586 {"CUSTOM_2", 0x5b},
587 /* 48b 0x5f. */
588
589 {"BRANCH", 0x63},
590 {"JALR", 0x67},
591 /*reserved 0x5b. */
592 {"JAL", 0x6f},
593 {"SYSTEM", 0x73},
594 /*reserved 0x77. */
595 {"CUSTOM_3", 0x7b},
596 /* >80b 0x7f. */
597
598 {NULL, 0}
599};
600
601/* Hash table for lookup opcode name. */
629310ab 602static htab_t opcode_names_hash = NULL;
0e35537d
JW		 603
604/* Initialization for hash table of opcode name. */
605static void
606init_opcode_names_hash (void)
607{
0e35537d
JW		 608 const struct opcode_name_t *opcode;
609
610 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f
AM		 611 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
612 as_fatal (_("duplicate %s"), opcode->name);
0e35537d
JW		 613}
614
615/* Find `s` is a valid opcode name or not,
616 return the opcode name info if found. */
617static const struct opcode_name_t *
618opcode_name_lookup (char **s)
619{
620 char *e;
621 char save_c;
622 struct opcode_name_t *o;
623
624 /* Find end of name. */
625 e = *s;
626 if (is_name_beginner (*e))
627 ++e;
628 while (is_part_of_name (*e))
629 ++e;
630
631 /* Terminate name. */
632 save_c = *e;
633 *e = '\0';
634
629310ab 635 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 636
637 /* Advance to next token if one was recognized. */
638 if (o)
639 *s = e;
640
641 *e = save_c;
642 expr_end = e;
643
644 return o;
645}
646
e23eba97
NC		 647enum reg_class
648{
649 RCLASS_GPR,
650 RCLASS_FPR,
8f595e9b
NC		 651 RCLASS_MAX,
652
653 RCLASS_CSR
e23eba97
NC		 654};
655
629310ab
ML		 656static htab_t reg_names_hash = NULL;
657static htab_t csr_extra_hash = NULL;
e23eba97
NC		 658
659#define ENCODE_REG_HASH(cls, n) \
660 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
661#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
662#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
663
664static void
665hash_reg_name (enum reg_class class, const char *name, unsigned n)
666{
667 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f
AM		 668 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
669 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 670}
671
672static void
673hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
674{
675 unsigned i;
676
677 for (i = 0; i < n; i++)
678 hash_reg_name (class, names[i], i);
679}
680
8f595e9b
NC		 681/* Init hash table csr_extra_hash to handle CSR. */
682static void
683riscv_init_csr_hash (const char *name,
684 unsigned address,
685 enum riscv_csr_class class,
686 enum riscv_priv_spec_class define_version,
687 enum riscv_priv_spec_class abort_version)
688{
689 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 690 bfd_boolean need_enrty = TRUE;
691
692 pre_entry = NULL;
629310ab 693 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 694 while (need_enrty && entry != NULL)
695 {
696 if (entry->csr_class == class
697 && entry->address == address
698 && entry->define_version == define_version
699 && entry->abort_version == abort_version)
700 need_enrty = FALSE;
701 pre_entry = entry;
702 entry = entry->next;
703 }
704
705 /* Duplicate setting for the CSR, just return and do nothing. */
706 if (!need_enrty)
707 return;
bd0cf5a6 708
8f595e9b
NC		 709 entry = XNEW (struct riscv_csr_extra);
710 entry->csr_class = class;
711 entry->address = address;
712 entry->define_version = define_version;
713 entry->abort_version = abort_version;
5c505568 714 entry->next = NULL;
8f595e9b
NC		 715
716 /* If the CSR hasn't been inserted in the hash table, then insert it.
717 Otherwise, attach the extra information to the entry which is already
718 in the hash table. */
719 if (pre_entry == NULL)
fe0e921f 720 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 721 else
722 pre_entry->next = entry;
723}
bd0cf5a6 724
08ccfccf
NC		 725/* Return the suitable CSR address after checking the ISA dependency and
726 priv spec versions. */
bd0cf5a6 727
08ccfccf
NC		 728static unsigned int
729riscv_csr_address (const char *csr_name,
730 struct riscv_csr_extra *entry)
bd0cf5a6 731{
08ccfccf
NC		 732 struct riscv_csr_extra *saved_entry = entry;
733 enum riscv_csr_class csr_class = entry->csr_class;
734 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 735 bfd_boolean result = TRUE;
736
8f595e9b 737 switch (csr_class)
bd0cf5a6 738 {
8f595e9b
NC		 739 case CSR_CLASS_I:
740 result = riscv_subset_supports ("i");
741 break;
08ccfccf
NC		 742 case CSR_CLASS_I_32:
743 result = (xlen == 32 && riscv_subset_supports ("i"));
744 break;
8f595e9b
NC		 745 case CSR_CLASS_F:
746 result = riscv_subset_supports ("f");
08ccfccf 747 need_check_version = FALSE;
8f595e9b 748 break;
08ccfccf
NC		 749 case CSR_CLASS_DEBUG:
750 need_check_version = FALSE;
8f595e9b
NC		 751 break;
752 default:
753 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 754 }
755
08ccfccf
NC		 756 /* Don't report the ISA conflict when -mcsr-check isn't set. */
757 if (riscv_opts.csr_check && !result)
758 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 759
760 while (entry != NULL)
bd0cf5a6 761 {
08ccfccf
NC		 762 if (!need_check_version
763 || (default_priv_spec >= entry->define_version
764 && default_priv_spec < entry->abort_version))
8f595e9b
NC		 765 {
766 /* Find the suitable CSR according to the specific version. */
08ccfccf 767 return entry->address;
8f595e9b
NC		 768 }
769 entry = entry->next;
770 }
bd0cf5a6 771
8f595e9b
NC		 772 /* We can not find the suitable CSR address according to the privilege
773 version. Therefore, we use the last defined value. Report the warning
774 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
775 otherwise, you may get the unexpected CSR address. */
776 if (riscv_opts.csr_check)
777 {
778 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
779
780 if (priv_name != NULL)
781 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
782 csr_name, priv_name);
bd0cf5a6 783 }
08ccfccf
NC		 784
785 return saved_entry->address;
bd0cf5a6
NC		 786}
787
8f595e9b
NC		 788/* Once the CSR is defined, including the old privilege spec, then we call
789 riscv_csr_class_check and riscv_csr_version_check to do the further checking
790 and get the corresponding address. Return -1 if the CSR is never been
791 defined. Otherwise, return the address. */
bd0cf5a6 792
8f595e9b 793static unsigned int
bd0cf5a6
NC		 794reg_csr_lookup_internal (const char *s)
795{
796 struct riscv_csr_extra *r =
629310ab 797 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 798
799 if (r == NULL)
8f595e9b 800 return -1U;
bd0cf5a6 801
8f595e9b
NC		 802 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
803 the CSR was defined, but isn't allowed for the current ISA setting or
804 the privilege spec. If the CSR is never been defined, then assembler
805 will regard it as a "Unknown CSR" and report error. If user use number
806 to set the CSR, but over the range (> 0xfff), then assembler will report
807 "Improper CSR" error for it. */
08ccfccf 808 return riscv_csr_address (s, r);
bd0cf5a6
NC		 809}
810
e23eba97
NC		 811static unsigned int
812reg_lookup_internal (const char *s, enum reg_class class)
813{
8f595e9b
NC		 814 void *r;
815
816 if (class == RCLASS_CSR)
817 return reg_csr_lookup_internal (s);
e23eba97 818
629310ab 819 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 820 if (r == NULL || DECODE_REG_CLASS (r) != class)
821 return -1;
7f999549
JW		 822
823 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
824 return -1;
825
e23eba97
NC		 826 return DECODE_REG_NUM (r);
827}
828
829static bfd_boolean
830reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
831{
832 char *e;
833 char save_c;
834 int reg = -1;
835
836 /* Find end of name. */
837 e = *s;
838 if (is_name_beginner (*e))
839 ++e;
840 while (is_part_of_name (*e))
841 ++e;
842
843 /* Terminate name. */
844 save_c = *e;
845 *e = '\0';
846
847 /* Look for the register. Advance to next token if one was recognized. */
848 if ((reg = reg_lookup_internal (*s, class)) >= 0)
849 *s = e;
850
851 *e = save_c;
852 if (regnop)
853 *regnop = reg;
854 return reg >= 0;
855}
856
857static bfd_boolean
858arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
859{
860 const char *p = strchr (*s, ',');
861 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
862
bfb218e3
JW		 863 if (len == 0)
864 return FALSE;
865
e23eba97
NC		 866 for (i = 0; i < size; i++)
867 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
868 {
869 *regnop = i;
870 *s += len;
871 return TRUE;
872 }
873
874 return FALSE;
875}
876
877/* For consistency checking, verify that all bits are specified either
878 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 879 operand list.
880
881 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 882static bfd_boolean
0e35537d 883validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 884{
885 const char *p = opc->args;
886 char c;
887 insn_t used_bits = opc->mask;
0e35537d
JW		 888 int insn_width;
889 insn_t required_bits;
890
891 if (length == 0)
892 insn_width = 8 * riscv_insn_length (opc->match);
893 else
894 insn_width = 8 * length;
895
896 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 897
898 if ((used_bits & opc->match) != (opc->match & required_bits))
899 {
900 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
901 opc->name, opc->args);
902 return FALSE;
903 }
904
905#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
906 while (*p)
907 switch (c = *p++)
908 {
909 case 'C': /* RVC */
910 switch (c = *p++)
911 {
1d65abb5 912 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 913 case 'c': break; /* RS1, constrained to equal sp */
914 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 915 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 916 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 917 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
918 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
919 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
920 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
921 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 922 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
923 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 924 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
925 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 926 case 'w': break; /* RS1S, constrained to equal RD */
927 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 928 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 929 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
930 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
931 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
932 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 933 case 'U': break; /* RS1, constrained to equal RD */
934 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 935 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
936 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 937 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
938 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 939 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
940 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 941 case 'F': /* funct */
942 switch (c = *p++)
943 {
4765cd61 944 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 945 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
946 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 947 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 948 default:
949 as_bad (_("internal: bad RISC-V opcode"
950 " (unknown operand type `CF%c'): %s %s"),
951 c, opc->name, opc->args);
952 return FALSE;
953 }
954 break;
e23eba97
NC		 955 default:
956 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
957 c, opc->name, opc->args);
958 return FALSE;
959 }
960 break;
961 case ',': break;
962 case '(': break;
963 case ')': break;
964 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
965 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
966 case 'A': break;
967 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
968 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
969 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
970 case 'I': break;
971 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
972 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
973 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
974 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
975 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
976 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
977 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
978 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 979 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 980 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
981 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
982 case 'o':
1d65abb5
AW		 983 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
984 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
985 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
986 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
987 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 988 case 'z': break;
e23eba97
NC		 989 case '[': break;
990 case ']': break;
991 case '0': break;
f50fabe4 992 case '1': break;
0e35537d
JW		 993 case 'F': /* funct */
994 switch (c = *p++)
995 {
996 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
997 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
998 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
999 default:
1000 as_bad (_("internal: bad RISC-V opcode"
1001 " (unknown operand type `F%c'): %s %s"),
1002 c, opc->name, opc->args);
1003 return FALSE;
1004 }
1005 break;
1006 case 'O': /* opcode */
1007 switch (c = *p++)
1008 {
1009 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1010 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1011 default:
1012 as_bad (_("internal: bad RISC-V opcode"
1013 " (unknown operand type `F%c'): %s %s"),
1014 c, opc->name, opc->args);
1015 return FALSE;
1016 }
1017 break;
e23eba97
NC		 1018 default:
1019 as_bad (_("internal: bad RISC-V opcode "
1020 "(unknown operand type `%c'): %s %s"),
1021 c, opc->name, opc->args);
1022 return FALSE;
1023 }
1024#undef USE_BITS
1025 if (used_bits != required_bits)
1026 {
1027 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1028 ~(unsigned long)(used_bits & required_bits),
1029 opc->name, opc->args);
1030 return FALSE;
1031 }
1032 return TRUE;
1033}
1034
1035struct percent_op_match
1036{
1037 const char *str;
1038 bfd_reloc_code_real_type reloc;
1039};
1040
0e35537d
JW		 1041/* Common hash table initialization function for
1042 instruction and .insn directive. */
629310ab 1043static htab_t
0e35537d
JW		 1044init_opcode_hash (const struct riscv_opcode *opcodes,
1045 bfd_boolean insn_directive_p)
e23eba97
NC		 1046{
1047 int i = 0;
0e35537d 1048 int length;
629310ab 1049 htab_t hash = str_htab_create ();
0e35537d 1050 while (opcodes[i].name)
e23eba97 1051 {
0e35537d 1052 const char *name = opcodes[i].name;
fe0e921f
AM		 1053 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
1054 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 1055
1056 do
1057 {
0e35537d 1058 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1059 {
0e35537d
JW		 1060 if (insn_directive_p)
1061 length = ((name[0] == 'c') ? 2 : 4);
1062 else
1063 length = 0; /* Let assembler determine the length. */
1064 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1065 as_fatal (_("Broken assembler. No assembly attempted."));
1066 }
0e35537d
JW		 1067 else
1068 gas_assert (!insn_directive_p);
e23eba97
NC		 1069 ++i;
1070 }
0e35537d 1071 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1072 }
1073
0e35537d
JW		 1074 return hash;
1075}
1076
1077/* This function is called once, at assembler startup time. It should set up
1078 all the tables, etc. that the MD part of the assembler will need. */
1079
1080void
1081md_begin (void)
1082{
1083 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1084
1085 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1086 as_warn (_("Could not set architecture and machine"));
1087
1088 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1089 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1090
629310ab 1091 reg_names_hash = str_htab_create ();
e23eba97
NC		 1092 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1093 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1094 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1095 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1096 /* Add "fp" as an alias for "s0". */
1097 hash_reg_name (RCLASS_GPR, "fp", 8);
1098
bd0cf5a6 1099 /* Create and insert CSR hash tables. */
629310ab 1100 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1101#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1102 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1103#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1104 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1105#include "opcode/riscv-opc.h"
1106#undef DECLARE_CSR
1107
629310ab 1108 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1109 init_opcode_names_hash ();
1110
e23eba97
NC		 1111 /* Set the default alignment for the text section. */
1112 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1113}
1114
45f76423
AW		 1115static insn_t
1116riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1117{
1118 switch (reloc_type)
1119 {
1120 case BFD_RELOC_32:
1121 return value;
1122
1123 case BFD_RELOC_RISCV_HI20:
1124 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1125
1126 case BFD_RELOC_RISCV_LO12_S:
1127 return ENCODE_STYPE_IMM (value);
1128
1129 case BFD_RELOC_RISCV_LO12_I:
1130 return ENCODE_ITYPE_IMM (value);
1131
1132 default:
1133 abort ();
1134 }
1135}
1136
e23eba97
NC		 1137/* Output an instruction. IP is the instruction information.
1138 ADDRESS_EXPR is an operand of the instruction to be used with
1139 RELOC_TYPE. */
1140
1141static void
1142append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1143 bfd_reloc_code_real_type reloc_type)
1144{
1145 dwarf2_emit_insn (0);
1146
1147 if (reloc_type != BFD_RELOC_UNUSED)
1148 {
1149 reloc_howto_type *howto;
1150
1d65abb5 1151 gas_assert (address_expr);
e23eba97
NC		 1152 if (reloc_type == BFD_RELOC_12_PCREL
1153 || reloc_type == BFD_RELOC_RISCV_JMP)
1154 {
1155 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1156 int best_case = riscv_insn_length (ip->insn_opcode);
1157 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1158
1159 if (now_seg == absolute_section)
1160 {
1161 as_bad (_("relaxable branches not supported in absolute section"));
1162 return;
1163 }
1164
e23eba97
NC		 1165 add_relaxed_insn (ip, worst_case, best_case,
1166 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1167 address_expr->X_add_symbol,
1168 address_expr->X_add_number);
1169 return;
1170 }
45f76423 1171 else
e23eba97 1172 {
45f76423
AW		 1173 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1174 if (howto == NULL)
1175 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1176
45f76423
AW		 1177 ip->fixp = fix_new_exp (ip->frag, ip->where,
1178 bfd_get_reloc_size (howto),
1179 address_expr, FALSE, reloc_type);
e23eba97 1180
45f76423 1181 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1182 }
e23eba97
NC		 1183 }
1184
e23eba97
NC		 1185 add_fixed_insn (ip);
1186 install_insn (ip);
f77bb6c5
JW		 1187
1188 /* We need to start a new frag after any instruction that can be
1189 optimized away or compressed by the linker during relaxation, to prevent
1190 the assembler from computing static offsets across such an instruction.
1191 This is necessary to get correct EH info. */
b1b11e92 1192 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1193 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1194 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1195 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1196 {
1197 frag_wane (frag_now);
1198 frag_new (0);
1199 }
e23eba97
NC		 1200}
1201
1202/* Build an instruction created by a macro expansion. This is passed
1203 a pointer to the count of instructions created so far, an
1204 expression, the name of the instruction to build, an operand format
1205 string, and corresponding arguments. */
1206
1207static void
1208macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1209{
1210 const struct riscv_opcode *mo;
1211 struct riscv_cl_insn insn;
1212 bfd_reloc_code_real_type r;
1213 va_list args;
1214
1215 va_start (args, fmt);
1216
1217 r = BFD_RELOC_UNUSED;
629310ab 1218 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1219 gas_assert (mo);
1220
1221 /* Find a non-RVC variant of the instruction. append_insn will compress
1222 it if possible. */
1223 while (riscv_insn_length (mo->match) < 4)
1224 mo++;
1225 gas_assert (strcmp (name, mo->name) == 0);
1226
1227 create_insn (&insn, mo);
1228 for (;;)
1229 {
1230 switch (*fmt++)
1231 {
1232 case 'd':
1233 INSERT_OPERAND (RD, insn, va_arg (args, int));
1234 continue;
1235
1236 case 's':
1237 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1238 continue;
1239
1240 case 't':
1241 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1242 continue;
1243
1244 case '>':
1245 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1246 continue;
1247
1248 case 'j':
1249 case 'u':
1250 case 'q':
1251 gas_assert (ep != NULL);
1252 r = va_arg (args, int);
1253 continue;
1254
1255 case '\0':
1256 break;
1257 case ',':
1258 continue;
1259 default:
1260 as_fatal (_("internal error: invalid macro"));
1261 }
1262 break;
1263 }
1264 va_end (args);
1265 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1266
1267 append_insn (&insn, ep, r);
1268}
1269
db3b6ecc
KC		 1270/* Build an instruction created by a macro expansion. Like md_assemble but
1271 accept a printf-style format string and arguments. */
1272
1273static void
1274md_assemblef (const char *format, ...)
1275{
1276 char *buf = NULL;
1277 va_list ap;
1278 int r;
1279
1280 va_start (ap, format);
1281
1282 r = vasprintf (&buf, format, ap);
1283
1284 if (r < 0)
1285 as_fatal (_("internal error: vasprintf failed"));
1286
1287 md_assemble (buf);
1288 free(buf);
1289
1290 va_end (ap);
1291}
1292
e23eba97
NC		 1293/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1294 unset. */
1295static void
1296normalize_constant_expr (expressionS *ex)
1297{
1298 if (xlen > 32)
1299 return;
1300 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1301 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1302 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1303 - 0x80000000);
1304}
1305
ca2fd32c
JW		 1306/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1307 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1308
1309static void
ca2fd32c
JW		 1310check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1311 bfd_boolean maybe_csr)
e23eba97
NC		 1312{
1313 if (ex->X_op == O_big)
1314 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1315 else if (maybe_csr && ex->X_op == O_symbol)
1316 as_bad (_("unknown CSR `%s'"),
1317 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1318 else if (ex->X_op != O_constant)
1319 as_bad (_("Instruction %s requires absolute expression"),
1320 ip->insn_mo->name);
1321 normalize_constant_expr (ex);
1322}
1323
1324static symbolS *
1325make_internal_label (void)
1326{
e01e1cee
AM		 1327 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1328 frag_now_fix ());
e23eba97
NC		 1329}
1330
1331/* Load an entry from the GOT. */
1332static void
1333pcrel_access (int destreg, int tempreg, expressionS *ep,
1334 const char *lo_insn, const char *lo_pattern,
1335 bfd_reloc_code_real_type hi_reloc,
1336 bfd_reloc_code_real_type lo_reloc)
1337{
1338 expressionS ep2;
1339 ep2.X_op = O_symbol;
1340 ep2.X_add_symbol = make_internal_label ();
1341 ep2.X_add_number = 0;
1342
1343 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1344 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1345}
1346
1347static void
1348pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1349 bfd_reloc_code_real_type hi_reloc,
1350 bfd_reloc_code_real_type lo_reloc)
1351{
1352 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1353}
1354
1355static void
1356pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1357 bfd_reloc_code_real_type hi_reloc,
1358 bfd_reloc_code_real_type lo_reloc)
1359{
1360 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1361}
1362
1363/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1364static void
1365riscv_call (int destreg, int tempreg, expressionS *ep,
1366 bfd_reloc_code_real_type reloc)
1367{
b1b11e92
AM		 1368 /* Ensure the jalr is emitted to the same frag as the auipc. */
1369 frag_grow (8);
e23eba97
NC		 1370 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1371 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1372 /* See comment at end of append_insn. */
1373 frag_wane (frag_now);
1374 frag_new (0);
e23eba97
NC		 1375}
1376
1377/* Load an integer constant into a register. */
1378
1379static void
1380load_const (int reg, expressionS *ep)
1381{
1382 int shift = RISCV_IMM_BITS;
4f7cc141 1383 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1384 expressionS upper = *ep, lower = *ep;
4f7cc141 1385 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1386 upper.X_add_number -= lower.X_add_number;
1387
1388 if (ep->X_op != O_constant)
1389 {
1390 as_bad (_("unsupported large constant"));
1391 return;
1392 }
1393
1d65abb5 1394 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1395 {
1396 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1397 while (((upper.X_add_number >> shift) & 1) == 0)
1398 shift++;
1399
1400 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1401 load_const (reg, &upper);
e23eba97 1402
db3b6ecc 1403 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1404 if (lower.X_add_number != 0)
db3b6ecc
KC		 1405 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1406 lower.X_add_number);
e23eba97
NC		 1407 }
1408 else
1409 {
1410 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1411 int hi_reg = 0;
1412
1413 if (upper.X_add_number != 0)
1414 {
db3b6ecc
KC		 1415 /* Discard low part and zero-extend upper immediate. */
1416 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1417
1418 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1419 hi_reg = reg;
1420 }
1421
1422 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1423 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1424 lower.X_add_number);
e23eba97
NC		 1425 }
1426}
1427
1428/* Expand RISC-V assembly macros into one or more instructions. */
1429static void
1430macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1431 bfd_reloc_code_real_type *imm_reloc)
1432{
1433 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1434 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1435 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1436 int mask = ip->insn_mo->mask;
1437
1438 switch (mask)
1439 {
1440 case M_LI:
1441 load_const (rd, imm_expr);
1442 break;
1443
1444 case M_LA:
1445 case M_LLA:
1446 /* Load the address of a symbol into a register. */
1447 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1448 as_bad (_("offset too large"));
1449
1450 if (imm_expr->X_op == O_constant)
1451 load_const (rd, imm_expr);
1452 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1453 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1454 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1455 else /* Local PIC symbol, or any non-PIC symbol */
1456 pcrel_load (rd, rd, imm_expr, "addi",
1457 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1458 break;
1459
1460 case M_LA_TLS_GD:
1461 pcrel_load (rd, rd, imm_expr, "addi",
1462 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1463 break;
1464
1465 case M_LA_TLS_IE:
1466 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1467 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1468 break;
1469
1470 case M_LB:
1471 pcrel_load (rd, rd, imm_expr, "lb",
1472 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1473 break;
1474
1475 case M_LBU:
1476 pcrel_load (rd, rd, imm_expr, "lbu",
1477 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1478 break;
1479
1480 case M_LH:
1481 pcrel_load (rd, rd, imm_expr, "lh",
1482 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1483 break;
1484
1485 case M_LHU:
1486 pcrel_load (rd, rd, imm_expr, "lhu",
1487 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1488 break;
1489
1490 case M_LW:
1491 pcrel_load (rd, rd, imm_expr, "lw",
1492 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1493 break;
1494
1495 case M_LWU:
1496 pcrel_load (rd, rd, imm_expr, "lwu",
1497 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1498 break;
1499
1500 case M_LD:
1501 pcrel_load (rd, rd, imm_expr, "ld",
1502 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1503 break;
1504
1505 case M_FLW:
1506 pcrel_load (rd, rs1, imm_expr, "flw",
1507 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1508 break;
1509
1510 case M_FLD:
1511 pcrel_load (rd, rs1, imm_expr, "fld",
1512 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1513 break;
1514
1515 case M_SB:
1516 pcrel_store (rs2, rs1, imm_expr, "sb",
1517 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1518 break;
1519
1520 case M_SH:
1521 pcrel_store (rs2, rs1, imm_expr, "sh",
1522 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1523 break;
1524
1525 case M_SW:
1526 pcrel_store (rs2, rs1, imm_expr, "sw",
1527 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1528 break;
1529
1530 case M_SD:
1531 pcrel_store (rs2, rs1, imm_expr, "sd",
1532 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1533 break;
1534
1535 case M_FSW:
1536 pcrel_store (rs2, rs1, imm_expr, "fsw",
1537 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1538 break;
1539
1540 case M_FSD:
1541 pcrel_store (rs2, rs1, imm_expr, "fsd",
1542 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1543 break;
1544
1545 case M_CALL:
1546 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1547 break;
1548
1549 default:
1550 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1551 break;
1552 }
1553}
1554
1555static const struct percent_op_match percent_op_utype[] =
1556{
1557 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1558 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1559 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1560 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1561 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1562 {"%hi", BFD_RELOC_RISCV_HI20},
1563 {0, 0}
1564};
1565
1566static const struct percent_op_match percent_op_itype[] =
1567{
1568 {"%lo", BFD_RELOC_RISCV_LO12_I},
1569 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1570 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1571 {0, 0}
1572};
1573
1574static const struct percent_op_match percent_op_stype[] =
1575{
1576 {"%lo", BFD_RELOC_RISCV_LO12_S},
1577 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1578 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1579 {0, 0}
1580};
1581
1582static const struct percent_op_match percent_op_rtype[] =
1583{
1584 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1585 {0, 0}
1586};
1587
f50fabe4
JW		 1588static const struct percent_op_match percent_op_null[] =
1589{
1590 {0, 0}
1591};
1592
e23eba97
NC		 1593/* Return true if *STR points to a relocation operator. When returning true,
1594 move *STR over the operator and store its relocation code in *RELOC.
1595 Leave both *STR and *RELOC alone when returning false. */
1596
1597static bfd_boolean
1598parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1599 const struct percent_op_match *percent_op)
1600{
1601 for ( ; percent_op->str; percent_op++)
1602 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1603 {
1604 int len = strlen (percent_op->str);
1605
1606 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1607 continue;
1608
1609 *str += strlen (percent_op->str);
1610 *reloc = percent_op->reloc;
1611
1612 /* Check whether the output BFD supports this relocation.
1613 If not, issue an error and fall back on something safe. */
45f76423
AW		 1614 if (*reloc != BFD_RELOC_UNUSED
1615 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1616 {
1617 as_bad ("relocation %s isn't supported by the current ABI",
1618 percent_op->str);
1619 *reloc = BFD_RELOC_UNUSED;
1620 }
1621 return TRUE;
1622 }
1623 return FALSE;
1624}
1625
1626static void
1627my_getExpression (expressionS *ep, char *str)
1628{
1629 char *save_in;
1630
1631 save_in = input_line_pointer;
1632 input_line_pointer = str;
1633 expression (ep);
1634 expr_end = input_line_pointer;
1635 input_line_pointer = save_in;
1636}
1637
1638/* Parse string STR as a 16-bit relocatable operand. Store the
1639 expression in *EP and the relocation, if any, in RELOC.
1640 Return the number of relocation operators used (0 or 1).
1641
1642 On exit, EXPR_END points to the first character after the expression. */
1643
1644static size_t
1645my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1646 char *str, const struct percent_op_match *percent_op)
1647{
1648 size_t reloc_index;
1649 unsigned crux_depth, str_depth, regno;
1650 char *crux;
1651
8970c022
JW		 1652 /* First, check for integer registers. No callers can accept a reg, but
1653 we need to avoid accidentally creating a useless undefined symbol below,
1654 if this is an instruction pattern that can't match. A glibc build fails
1655 if this is removed. */
e23eba97
NC		 1656 if (reg_lookup (&str, RCLASS_GPR, &regno))
1657 {
1658 ep->X_op = O_register;
1659 ep->X_add_number = regno;
8970c022 1660 expr_end = str;
e23eba97
NC		 1661 return 0;
1662 }
1663
1664 /* Search for the start of the main expression.
1665 End the loop with CRUX pointing to the start
1666 of the main expression and with CRUX_DEPTH containing the number
1667 of open brackets at that point. */
1668 reloc_index = -1;
1669 str_depth = 0;
1670 do
1671 {
1672 reloc_index++;
1673 crux = str;
1674 crux_depth = str_depth;
1675
1676 /* Skip over whitespace and brackets, keeping count of the number
1677 of brackets. */
1678 while (*str == ' ' || *str == '\t' || *str == '(')
1679 if (*str++ == '(')
1680 str_depth++;
1681 }
1682 while (*str == '%'
1683 && reloc_index < 1
1684 && parse_relocation (&str, reloc, percent_op));
1685
1686 my_getExpression (ep, crux);
1687 str = expr_end;
1688
1689 /* Match every open bracket. */
1690 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1691 if (*str++ == ')')
1692 crux_depth--;
1693
1694 if (crux_depth > 0)
1695 as_bad ("unclosed '('");
1696
1697 expr_end = str;
1698
1699 return reloc_index;
1700}
1701
0e35537d
JW		 1702/* Parse opcode name, could be an mnemonics or number. */
1703static size_t
1704my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1705 char *str, const struct percent_op_match *percent_op)
1706{
1707 const struct opcode_name_t *o = opcode_name_lookup (&str);
1708
1709 if (o != NULL)
1710 {
1711 ep->X_op = O_constant;
1712 ep->X_add_number = o->val;
1713 return 0;
1714 }
1715
1716 return my_getSmallExpression (ep, reloc, str, percent_op);
1717}
1718
f0531ed6
JW		 1719/* Detect and handle implicitly zero load-store offsets. For example,
1720 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1721 an implicit offset was detected. */
1722
1723static bfd_boolean
89424b1d 1724riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1725{
1726 /* Check whether there is only a single bracketed expression left.
1727 If so, it must be the base register and the constant must be zero. */
1728 if (*s == '(' && strchr (s + 1, '(') == 0)
1729 {
89424b1d
MR		 1730 ep->X_op = O_constant;
1731 ep->X_add_number = 0;
f0531ed6
JW		 1732 return TRUE;
1733 }
1734
1735 return FALSE;
1736}
1737
54b2aec1
NC		 1738/* All RISC-V CSR instructions belong to one of these classes. */
1739
1740enum csr_insn_type
1741{
1742 INSN_NOT_CSR,
1743 INSN_CSRRW,
1744 INSN_CSRRS,
1745 INSN_CSRRC
1746};
1747
1748/* Return which CSR instruction is checking. */
1749
1750static enum csr_insn_type
1751riscv_csr_insn_type (insn_t insn)
1752{
1753 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1754 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1755 return INSN_CSRRW;
1756 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1757 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1758 return INSN_CSRRS;
1759 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1760 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1761 return INSN_CSRRC;
1762 else
1763 return INSN_NOT_CSR;
1764}
1765
1766/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1767 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1768 CSR address is 0x3. */
1769
1770static bfd_boolean
1771riscv_csr_read_only_check (insn_t insn)
1772{
1773 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1774 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1775 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1776 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1777
1778 if (readonly
1779 && (((csr_insn == INSN_CSRRS
1780 || csr_insn == INSN_CSRRC)
1781 && rs1 != 0)
1782 || csr_insn == INSN_CSRRW))
1783 return FALSE;
1784
1785 return TRUE;
1786}
1787
1a79004f
NC		 1788/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1789
1790 uret is actually a N-ext instruction. So it is better to regard it as
1791 an user instruction rather than the priv instruction.
1792
1793 hret is used to return from traps in H-mode. H-mode is removed since
1794 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1795 Therefore, hret should be controlled by the hypervisor spec rather than
1796 priv spec in the future.
1797
1798 dret is defined in the debug spec, so it should be checked in the future,
1799 too. */
1800
1801static bfd_boolean
1802riscv_is_priv_insn (insn_t insn)
1803{
1804 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1805 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1806 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1807 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1808 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1809 check it here to keep the compatible. Maybe we should issue warning
1810 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1811 We already have a similar check for CSR, but not yet for instructions.
1812 It would be good if we could check the spec versions both for CSR and
1813 instructions, but not here. */
1814 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1815}
1816
e23eba97
NC		 1817/* This routine assembles an instruction into its binary format. As a
1818 side effect, it sets the global variable imm_reloc to the type of
1819 relocation to do if one of the operands is an address expression. */
1820
1821static const char *
1822riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1823 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1824{
1825 char *s;
1826 const char *args;
1827 char c = 0;
1828 struct riscv_opcode *insn;
1829 char *argsStart;
1830 unsigned int regno;
1831 char save_c = 0;
1832 int argnum;
1833 const struct percent_op_match *p;
1834 const char *error = "unrecognized opcode";
54b2aec1
NC		 1835 /* Indicate we are assembling instruction with CSR. */
1836 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1837
1838 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1839 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1840 for (s = str; *s != '\0'; ++s)
1841 if (ISSPACE (*s))
1842 {
1843 save_c = *s;
1844 *s++ = '\0';
1845 break;
1846 }
1847
629310ab 1848 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1849
1850 argsStart = s;
1851 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1852 {
1080bf78
JW		 1853 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1854 continue;
1855
7e9ad3a3 1856 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1857 continue;
1858
1859 create_insn (ip, insn);
1860 argnum = 1;
1861
1862 imm_expr->X_op = O_absent;
1863 *imm_reloc = BFD_RELOC_UNUSED;
1864 p = percent_op_itype;
1865
1866 for (args = insn->args;; ++args)
1867 {
1868 s += strspn (s, " \t");
1869 switch (*args)
1870 {
1871 case '\0': /* End of args. */
1872 if (insn->pinfo != INSN_MACRO)
1873 {
1874 if (!insn->match_func (insn, ip->insn_opcode))
1875 break;
0e35537d
JW		 1876
1877 /* For .insn, insn->match and insn->mask are 0. */
1878 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1879 ? ip->insn_opcode
1880 : insn->match) == 2
1881 && !riscv_opts.rvc)
e23eba97 1882 break;
54b2aec1 1883
1a79004f
NC		 1884 if (riscv_is_priv_insn (ip->insn_opcode))
1885 explicit_priv_attr = TRUE;
1886
54b2aec1
NC		 1887 /* Check if we write a read-only CSR by the CSR
1888 instruction. */
1889 if (insn_with_csr
1890 && riscv_opts.csr_check
1891 && !riscv_csr_read_only_check (ip->insn_opcode))
1892 {
1893 /* Restore the character in advance, since we want to
1894 report the detailed warning message here. */
1895 if (save_c)
1896 *(argsStart - 1) = save_c;
1897 as_warn (_("Read-only CSR is written `%s'"), str);
1898 insn_with_csr = FALSE;
1899 }
e23eba97
NC		 1900 }
1901 if (*s != '\0')
1902 break;
1903 /* Successful assembly. */
1904 error = NULL;
54b2aec1 1905 insn_with_csr = FALSE;
e23eba97
NC		 1906 goto out;
1907
1908 case 'C': /* RVC */
1909 switch (*++args)
1910 {
1911 case 's': /* RS1 x8-x15 */
1912 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1913 || !(regno >= 8 && regno <= 15))
1914 break;
1915 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1916 continue;
1917 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1918 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1919 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1920 break;
1921 continue;
1922 case 't': /* RS2 x8-x15 */
1923 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1924 || !(regno >= 8 && regno <= 15))
1925 break;
1926 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1927 continue;
1928 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1929 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1930 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1931 break;
1932 continue;
1933 case 'U': /* RS1, constrained to equal RD. */
1934 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1935 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1936 break;
1937 continue;
1938 case 'V': /* RS2 */
1939 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1940 break;
1941 INSERT_OPERAND (CRS2, *ip, regno);
1942 continue;
1943 case 'c': /* RS1, constrained to equal sp. */
1944 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1945 || regno != X_SP)
1946 break;
1947 continue;
ca0bc150
JW		 1948 case 'z': /* RS2, contrained to equal x0. */
1949 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1950 || regno != 0)
1951 break;
1952 continue;
e23eba97
NC		 1953 case '>':
1954 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1955 || imm_expr->X_op != O_constant
1956 || imm_expr->X_add_number <= 0
1957 || imm_expr->X_add_number >= 64)
1958 break;
1959 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 1960 rvc_imm_done:
e23eba97
NC		 1961 s = expr_end;
1962 imm_expr->X_op = O_absent;
1963 continue;
1964 case '<':
1965 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1966 || imm_expr->X_op != O_constant
e23eba97 1967 || imm_expr->X_add_number <= 0
169ec512
AM		 1968 || imm_expr->X_add_number >= 32
1969 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1970 break;
1971 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1972 goto rvc_imm_done;
0e35537d
JW		 1973 case '8':
1974 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1975 || imm_expr->X_op != O_constant
0e35537d 1976 || imm_expr->X_add_number < 0
169ec512
AM		 1977 || imm_expr->X_add_number >= 256
1978 || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
0e35537d
JW		 1979 break;
1980 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1981 goto rvc_imm_done;
e23eba97
NC		 1982 case 'i':
1983 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1984 || imm_expr->X_op != O_constant
1985 || imm_expr->X_add_number == 0
169ec512 1986 || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1987 break;
1988 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1989 goto rvc_imm_done;
1990 case 'j':
1991 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1992 || imm_expr->X_op != O_constant
1993 || imm_expr->X_add_number == 0
169ec512 1994 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1995 break;
1996 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1997 goto rvc_imm_done;
1998 case 'k':
f0531ed6
JW		 1999 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2000 continue;
e23eba97
NC		 2001 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2002 || imm_expr->X_op != O_constant
169ec512 2003 || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2004 break;
2005 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
2006 goto rvc_imm_done;
2007 case 'l':
f0531ed6
JW		 2008 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2009 continue;
e23eba97
NC		 2010 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2011 || imm_expr->X_op != O_constant
169ec512 2012 || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2013 break;
2014 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
2015 goto rvc_imm_done;
2016 case 'm':
f0531ed6
JW		 2017 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2018 continue;
e23eba97
NC		 2019 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2020 || imm_expr->X_op != O_constant
169ec512 2021 || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2022 break;
2023 ip->insn_opcode |=
2024 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
2025 goto rvc_imm_done;
2026 case 'n':
f0531ed6
JW		 2027 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2028 continue;
e23eba97
NC		 2029 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2030 || imm_expr->X_op != O_constant
169ec512 2031 || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2032 break;
2033 ip->insn_opcode |=
2034 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
2035 goto rvc_imm_done;
b416fe87
KC		 2036 case 'o':
2037 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2038 || imm_expr->X_op != O_constant
21a186f2
JW		 2039 /* C.addiw, c.li, and c.andi allow zero immediate.
2040 C.addi allows zero immediate as hint. Otherwise this
2041 is same as 'j'. */
169ec512 2042 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
b416fe87
KC		 2043 break;
2044 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2045 goto rvc_imm_done;
e23eba97
NC		 2046 case 'K':
2047 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2048 || imm_expr->X_op != O_constant
169ec512
AM		 2049 || imm_expr->X_add_number == 0
2050 || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2051 break;
2052 ip->insn_opcode |=
2053 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
2054 goto rvc_imm_done;
2055 case 'L':
2056 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2057 || imm_expr->X_op != O_constant
169ec512
AM		 2058 || imm_expr->X_add_number == 0
2059 || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2060 break;
2061 ip->insn_opcode |=
2062 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2063 goto rvc_imm_done;
2064 case 'M':
f0531ed6
JW		 2065 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2066 continue;
e23eba97
NC		 2067 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2068 || imm_expr->X_op != O_constant
169ec512 2069 || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2070 break;
2071 ip->insn_opcode |=
2072 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2073 goto rvc_imm_done;
2074 case 'N':
f0531ed6
JW		 2075 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2076 continue;
e23eba97
NC		 2077 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2078 || imm_expr->X_op != O_constant
169ec512 2079 || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2080 break;
2081 ip->insn_opcode |=
2082 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2083 goto rvc_imm_done;
2084 case 'u':
2085 p = percent_op_utype;
2086 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2087 break;
dc1e8a47 2088 rvc_lui:
e23eba97
NC		 2089 if (imm_expr->X_op != O_constant
2090 || imm_expr->X_add_number <= 0
2091 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2092 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2093 && (imm_expr->X_add_number <
2094 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2095 break;
2096 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2097 goto rvc_imm_done;
2098 case 'v':
2099 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2100 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2101 || ((int32_t)imm_expr->X_add_number
2102 != imm_expr->X_add_number))
2103 break;
2104 imm_expr->X_add_number =
2105 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2106 goto rvc_lui;
2107 case 'p':
2108 goto branch;
2109 case 'a':
2110 goto jump;
0e35537d
JW		 2111 case 'S': /* Floating-point RS1 x8-x15. */
2112 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2113 || !(regno >= 8 && regno <= 15))
2114 break;
2115 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2116 continue;
e23eba97
NC		 2117 case 'D': /* Floating-point RS2 x8-x15. */
2118 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2119 || !(regno >= 8 && regno <= 15))
2120 break;
2121 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2122 continue;
2123 case 'T': /* Floating-point RS2. */
2124 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2125 break;
2126 INSERT_OPERAND (CRS2, *ip, regno);
2127 continue;
0e35537d
JW		 2128 case 'F':
2129 switch (*++args)
2130 {
4765cd61
JW		 2131 case '6':
2132 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2133 || imm_expr->X_op != O_constant
2134 || imm_expr->X_add_number < 0
2135 || imm_expr->X_add_number >= 64)
2136 {
2137 as_bad (_("bad value for funct6 field, "
2138 "value must be 0...64"));
2139 break;
2140 }
2141
2142 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2143 imm_expr->X_op = O_absent;
2144 s = expr_end;
2145 continue;
0e35537d
JW		 2146 case '4':
2147 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2148 || imm_expr->X_op != O_constant
2149 || imm_expr->X_add_number < 0
2150 || imm_expr->X_add_number >= 16)
2151 {
2152 as_bad (_("bad value for funct4 field, "
2153 "value must be 0...15"));
2154 break;
2155 }
2156
2157 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2158 imm_expr->X_op = O_absent;
2159 s = expr_end;
2160 continue;
2161 case '3':
2162 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2163 || imm_expr->X_op != O_constant
2164 || imm_expr->X_add_number < 0
2165 || imm_expr->X_add_number >= 8)
2166 {
2167 as_bad (_("bad value for funct3 field, "
2168 "value must be 0...7"));
2169 break;
2170 }
2171 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2172 imm_expr->X_op = O_absent;
2173 s = expr_end;
2174 continue;
4765cd61
JW		 2175 case '2':
2176 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2177 || imm_expr->X_op != O_constant
2178 || imm_expr->X_add_number < 0
2179 || imm_expr->X_add_number >= 4)
2180 {
2181 as_bad (_("bad value for funct2 field, "
2182 "value must be 0...3"));
2183 break;
2184 }
2185 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2186 imm_expr->X_op = O_absent;
2187 s = expr_end;
2188 continue;
0e35537d
JW		 2189 default:
2190 as_bad (_("bad compressed FUNCT field"
2191 " specifier 'CF%c'\n"),
2192 *args);
2193 }
2194 break;
2195
e23eba97
NC		 2196 default:
2197 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2198 }
2199 break;
2200
2201 case ',':
2202 ++argnum;
2203 if (*s++ == *args)
2204 continue;
2205 s--;
2206 break;
2207
2208 case '(':
2209 case ')':
2210 case '[':
2211 case ']':
2212 if (*s++ == *args)
2213 continue;
2214 break;
2215
2216 case '<': /* Shift amount, 0 - 31. */
2217 my_getExpression (imm_expr, s);
ca2fd32c 2218 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2219 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2220 as_bad (_("Improper shift amount (%lu)"),
2221 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2222 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2223 imm_expr->X_op = O_absent;
2224 s = expr_end;
2225 continue;
2226
2227 case '>': /* Shift amount, 0 - (XLEN-1). */
2228 my_getExpression (imm_expr, s);
ca2fd32c 2229 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2230 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2231 as_bad (_("Improper shift amount (%lu)"),
2232 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2233 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2234 imm_expr->X_op = O_absent;
2235 s = expr_end;
2236 continue;
2237
2238 case 'Z': /* CSRRxI immediate. */
2239 my_getExpression (imm_expr, s);
ca2fd32c 2240 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2241 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2242 as_bad (_("Improper CSRxI immediate (%lu)"),
2243 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2244 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2245 imm_expr->X_op = O_absent;
2246 s = expr_end;
2247 continue;
2248
2249 case 'E': /* Control register. */
54b2aec1 2250 insn_with_csr = TRUE;
1a79004f 2251 explicit_priv_attr = TRUE;
e23eba97
NC		 2252 if (reg_lookup (&s, RCLASS_CSR, &regno))
2253 INSERT_OPERAND (CSR, *ip, regno);
2254 else
2255 {
2256 my_getExpression (imm_expr, s);
ca2fd32c 2257 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2258 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2259 as_bad (_("Improper CSR address (%lu)"),
2260 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2261 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2262 imm_expr->X_op = O_absent;
2263 s = expr_end;
2264 }
2265 continue;
2266
2267 case 'm': /* Rounding mode. */
2268 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2269 {
2270 INSERT_OPERAND (RM, *ip, regno);
2271 continue;
2272 }
2273 break;
2274
2275 case 'P':
2276 case 'Q': /* Fence predecessor/successor. */
2277 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2278 &regno))
2279 {
2280 if (*args == 'P')
2281 INSERT_OPERAND (PRED, *ip, regno);
2282 else
2283 INSERT_OPERAND (SUCC, *ip, regno);
2284 continue;
2285 }
2286 break;
2287
2288 case 'd': /* Destination register. */
2289 case 's': /* Source register. */
2290 case 't': /* Target register. */
0e35537d 2291 case 'r': /* rs3. */
e23eba97
NC		 2292 if (reg_lookup (&s, RCLASS_GPR, &regno))
2293 {
2294 c = *args;
2295 if (*s == ' ')
2296 ++s;
2297
2298 /* Now that we have assembled one operand, we use the args
2299 string to figure out where it goes in the instruction. */
2300 switch (c)
2301 {
2302 case 's':
2303 INSERT_OPERAND (RS1, *ip, regno);
2304 break;
2305 case 'd':
2306 INSERT_OPERAND (RD, *ip, regno);
2307 break;
2308 case 't':
2309 INSERT_OPERAND (RS2, *ip, regno);
2310 break;
0e35537d
JW		 2311 case 'r':
2312 INSERT_OPERAND (RS3, *ip, regno);
2313 break;
e23eba97
NC		 2314 }
2315 continue;
2316 }
2317 break;
2318
2319 case 'D': /* Floating point rd. */
2320 case 'S': /* Floating point rs1. */
2321 case 'T': /* Floating point rs2. */
2322 case 'U': /* Floating point rs1 and rs2. */
2323 case 'R': /* Floating point rs3. */
2324 if (reg_lookup (&s, RCLASS_FPR, &regno))
2325 {
2326 c = *args;
2327 if (*s == ' ')
2328 ++s;
2329 switch (c)
2330 {
2331 case 'D':
2332 INSERT_OPERAND (RD, *ip, regno);
2333 break;
2334 case 'S':
2335 INSERT_OPERAND (RS1, *ip, regno);
2336 break;
2337 case 'U':
2338 INSERT_OPERAND (RS1, *ip, regno);
2339 /* fallthru */
2340 case 'T':
2341 INSERT_OPERAND (RS2, *ip, regno);
2342 break;
2343 case 'R':
2344 INSERT_OPERAND (RS3, *ip, regno);
2345 break;
2346 }
2347 continue;
2348 }
2349
2350 break;
2351
2352 case 'I':
2353 my_getExpression (imm_expr, s);
2354 if (imm_expr->X_op != O_big
2355 && imm_expr->X_op != O_constant)
2356 break;
2357 normalize_constant_expr (imm_expr);
2358 s = expr_end;
2359 continue;
2360
2361 case 'A':
2362 my_getExpression (imm_expr, s);
2363 normalize_constant_expr (imm_expr);
2364 /* The 'A' format specifier must be a symbol. */
2365 if (imm_expr->X_op != O_symbol)
2366 break;
2367 *imm_reloc = BFD_RELOC_32;
2368 s = expr_end;
2369 continue;
2370
160d1b3d
SH		 2371 case 'B':
2372 my_getExpression (imm_expr, s);
2373 normalize_constant_expr (imm_expr);
2374 /* The 'B' format specifier must be a symbol or a constant. */
2375 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2376 break;
2377 if (imm_expr->X_op == O_symbol)
2378 *imm_reloc = BFD_RELOC_32;
2379 s = expr_end;
2380 continue;
2381
e23eba97 2382 case 'j': /* Sign-extended immediate. */
e23eba97 2383 p = percent_op_itype;
f50fabe4 2384 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2385 goto alu_op;
2386 case 'q': /* Store displacement. */
2387 p = percent_op_stype;
2388 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2389 goto load_store;
2390 case 'o': /* Load displacement. */
2391 p = percent_op_itype;
2392 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2393 goto load_store;
f50fabe4 2394 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2395 p = percent_op_rtype;
f50fabe4
JW		 2396 goto alu_op;
2397 case '0': /* AMO "displacement," which must be zero. */
2398 p = percent_op_null;
dc1e8a47 2399 load_store:
f0531ed6 2400 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2401 continue;
dc1e8a47 2402 alu_op:
e23eba97
NC		 2403 /* If this value won't fit into a 16 bit offset, then go
2404 find a macro that will generate the 32 bit offset
2405 code pattern. */
2406 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2407 {
2408 normalize_constant_expr (imm_expr);
2409 if (imm_expr->X_op != O_constant
2410 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2411 || (*args == '1')
e23eba97
NC		 2412 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2413 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2414 break;
2415 }
2416
2417 s = expr_end;
2418 continue;
2419
2420 case 'p': /* PC-relative offset. */
dc1e8a47 2421 branch:
e23eba97
NC		 2422 *imm_reloc = BFD_RELOC_12_PCREL;
2423 my_getExpression (imm_expr, s);
2424 s = expr_end;
2425 continue;
2426
2427 case 'u': /* Upper 20 bits. */
2428 p = percent_op_utype;
4288405d 2429 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2430 {
4288405d
JW		 2431 if (imm_expr->X_op != O_constant)
2432 break;
2433
e23eba97
NC		 2434 if (imm_expr->X_add_number < 0
2435 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2436 as_bad (_("lui expression not in range 0..1048575"));
2437
2438 *imm_reloc = BFD_RELOC_RISCV_HI20;
2439 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2440 }
2441 s = expr_end;
2442 continue;
2443
2444 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2445 jump:
e23eba97
NC		 2446 my_getExpression (imm_expr, s);
2447 s = expr_end;
2448 *imm_reloc = BFD_RELOC_RISCV_JMP;
2449 continue;
2450
2451 case 'c':
2452 my_getExpression (imm_expr, s);
2453 s = expr_end;
2454 if (strcmp (s, "@plt") == 0)
2455 {
2456 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2457 s += 4;
2458 }
2459 else
2460 *imm_reloc = BFD_RELOC_RISCV_CALL;
2461 continue;
0e35537d
JW		 2462 case 'O':
2463 switch (*++args)
2464 {
2465 case '4':
2466 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2467 || imm_expr->X_op != O_constant
2468 || imm_expr->X_add_number < 0
2469 || imm_expr->X_add_number >= 128
2470 || (imm_expr->X_add_number & 0x3) != 3)
2471 {
2472 as_bad (_("bad value for opcode field, "
2473 "value must be 0...127 and "
2474 "lower 2 bits must be 0x3"));
2475 break;
2476 }
2477
2478 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2479 imm_expr->X_op = O_absent;
2480 s = expr_end;
2481 continue;
2482 case '2':
2483 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2484 || imm_expr->X_op != O_constant
2485 || imm_expr->X_add_number < 0
2486 || imm_expr->X_add_number >= 3)
2487 {
2488 as_bad (_("bad value for opcode field, "
2489 "value must be 0...2"));
2490 break;
2491 }
2492
2493 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2494 imm_expr->X_op = O_absent;
2495 s = expr_end;
2496 continue;
2497 default:
2498 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2499 }
2500 break;
2501
2502 case 'F':
2503 switch (*++args)
2504 {
2505 case '7':
2506 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2507 || imm_expr->X_op != O_constant
2508 || imm_expr->X_add_number < 0
2509 || imm_expr->X_add_number >= 128)
2510 {
2511 as_bad (_("bad value for funct7 field, "
2512 "value must be 0...127"));
2513 break;
2514 }
2515
2516 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2517 imm_expr->X_op = O_absent;
2518 s = expr_end;
2519 continue;
2520 case '3':
2521 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2522 || imm_expr->X_op != O_constant
2523 || imm_expr->X_add_number < 0
2524 || imm_expr->X_add_number >= 8)
2525 {
2526 as_bad (_("bad value for funct3 field, "
2527 "value must be 0...7"));
2528 break;
2529 }
2530
2531 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2532 imm_expr->X_op = O_absent;
2533 s = expr_end;
2534 continue;
2535 case '2':
2536 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2537 || imm_expr->X_op != O_constant
2538 || imm_expr->X_add_number < 0
2539 || imm_expr->X_add_number >= 4)
2540 {
2541 as_bad (_("bad value for funct2 field, "
2542 "value must be 0...3"));
2543 break;
2544 }
2545
2546 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2547 imm_expr->X_op = O_absent;
2548 s = expr_end;
2549 continue;
2550
2551 default:
2552 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2553 }
2554 break;
e23eba97 2555
e925c834
JW		 2556 case 'z':
2557 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2558 || imm_expr->X_op != O_constant
2559 || imm_expr->X_add_number != 0)
2560 break;
2561 s = expr_end;
2562 imm_expr->X_op = O_absent;
2563 continue;
2564
e23eba97
NC		 2565 default:
2566 as_fatal (_("internal error: bad argument type %c"), *args);
2567 }
2568 break;
2569 }
2570 s = argsStart;
2571 error = _("illegal operands");
54b2aec1 2572 insn_with_csr = FALSE;
e23eba97
NC		 2573 }
2574
dc1e8a47 2575 out:
e23eba97
NC		 2576 /* Restore the character we might have clobbered above. */
2577 if (save_c)
2578 *(argsStart - 1) = save_c;
2579
2580 return error;
2581}
2582
2583void
2584md_assemble (char *str)
2585{
2586 struct riscv_cl_insn insn;
2587 expressionS imm_expr;
2588 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2589
8f595e9b
NC		 2590 /* The arch and priv attributes should be set before assembling. */
2591 if (!start_assemble)
2592 {
2593 start_assemble = TRUE;
6e1605e4 2594 riscv_set_abi_by_arch ();
e23eba97 2595
8f595e9b
NC		 2596 /* Set the default_priv_spec according to the priv attributes. */
2597 if (!riscv_set_default_priv_spec (NULL))
2598 return;
2599 }
2600
2601 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2602
e23eba97
NC		 2603 if (error)
2604 {
2605 as_bad ("%s `%s'", error, str);
2606 return;
2607 }
2608
2609 if (insn.insn_mo->pinfo == INSN_MACRO)
2610 macro (&insn, &imm_expr, &imm_reloc);
2611 else
2612 append_insn (&insn, &imm_expr, imm_reloc);
2613}
2614
2615const char *
2616md_atof (int type, char *litP, int *sizeP)
2617{
2618 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2619}
2620
2621void
2622md_number_to_chars (char *buf, valueT val, int n)
2623{
2624 number_to_chars_littleendian (buf, val, n);
2625}
2626
2627const char *md_shortopts = "O::g::G:";
2628
2629enum options
2630{
2922d21d 2631 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2632 OPTION_PIC,
2633 OPTION_NO_PIC,
2922d21d 2634 OPTION_MABI,
71060565
JW		 2635 OPTION_RELAX,
2636 OPTION_NO_RELAX,
2dc8dd17
JW		 2637 OPTION_ARCH_ATTR,
2638 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2639 OPTION_CSR_CHECK,
2640 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2641 OPTION_MISA_SPEC,
2642 OPTION_MPRIV_SPEC,
e23eba97
NC		 2643 OPTION_END_OF_ENUM
2644};
2645
2646struct option md_longopts[] =
2647{
e23eba97
NC		 2648 {"march", required_argument, NULL, OPTION_MARCH},
2649 {"fPIC", no_argument, NULL, OPTION_PIC},
2650 {"fpic", no_argument, NULL, OPTION_PIC},
2651 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2652 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2653 {"mrelax", no_argument, NULL, OPTION_RELAX},
2654 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2655 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2656 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2657 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2658 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2659 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2660 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
e23eba97
NC		 2661
2662 {NULL, no_argument, NULL, 0}
2663};
2664size_t md_longopts_size = sizeof (md_longopts);
2665
e23eba97
NC		 2666int
2667md_parse_option (int c, const char *arg)
2668{
2669 switch (c)
2670 {
e23eba97 2671 case OPTION_MARCH:
8f595e9b
NC		 2672 /* riscv_after_parse_args will call riscv_set_arch to parse
2673 the architecture. */
2674 default_arch_with_ext = arg;
e23eba97
NC		 2675 break;
2676
2677 case OPTION_NO_PIC:
2678 riscv_opts.pic = FALSE;
2679 break;
2680
2681 case OPTION_PIC:
2682 riscv_opts.pic = TRUE;
2683 break;
2684
2922d21d
AW		 2685 case OPTION_MABI:
2686 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2687 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2688 else if (strcmp (arg, "ilp32e") == 0)
2689 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2690 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2691 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2692 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2693 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2694 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2695 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2696 else if (strcmp (arg, "lp64") == 0)
7f999549 2697 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2698 else if (strcmp (arg, "lp64f") == 0)
7f999549 2699 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2700 else if (strcmp (arg, "lp64d") == 0)
7f999549 2701 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2702 else if (strcmp (arg, "lp64q") == 0)
7f999549 2703 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2704 else
2705 return 0;
6e1605e4 2706 explicit_mabi = TRUE;
2922d21d
AW		 2707 break;
2708
71060565
JW		 2709 case OPTION_RELAX:
2710 riscv_opts.relax = TRUE;
2711 break;
2712
2713 case OPTION_NO_RELAX:
2714 riscv_opts.relax = FALSE;
2715 break;
2716
2dc8dd17
JW		 2717 case OPTION_ARCH_ATTR:
2718 riscv_opts.arch_attr = TRUE;
2719 break;
2720
2721 case OPTION_NO_ARCH_ATTR:
2722 riscv_opts.arch_attr = FALSE;
2723 break;
2724
2ca89224
NC		 2725 case OPTION_CSR_CHECK:
2726 riscv_opts.csr_check = TRUE;
2727 break;
2728
2729 case OPTION_NO_CSR_CHECK:
2730 riscv_opts.csr_check = FALSE;
2731 break;
2732
8f595e9b
NC		 2733 case OPTION_MISA_SPEC:
2734 return riscv_set_default_isa_spec (arg);
2735
2736 case OPTION_MPRIV_SPEC:
2737 return riscv_set_default_priv_spec (arg);
2738
e23eba97
NC		 2739 default:
2740 return 0;
2741 }
2742
2743 return 1;
2744}
2745
2746void
2747riscv_after_parse_args (void)
2748{
8f595e9b
NC		 2749 /* The --with-arch is optional for now, so we have to set the xlen
2750 according to the default_arch, which is set by the --targte, first.
2751 Then, we use the xlen to set the default_arch_with_ext if the
2752 -march and --with-arch are not set. */
e23eba97
NC		 2753 if (xlen == 0)
2754 {
2755 if (strcmp (default_arch, "riscv32") == 0)
2756 xlen = 32;
2757 else if (strcmp (default_arch, "riscv64") == 0)
2758 xlen = 64;
2759 else
2760 as_bad ("unknown default architecture `%s'", default_arch);
2761 }
8f595e9b
NC		 2762 if (default_arch_with_ext == NULL)
2763 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2764
2765 /* Initialize the hash table for extensions with default version. */
2766 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2767
2768 /* If the -misa-spec isn't set, then we set the default ISA spec according
2769 to DEFAULT_RISCV_ISA_SPEC. */
2770 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2771 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2772
8f595e9b
NC		 2773 /* Set the architecture according to -march or or --with-arch. */
2774 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2775
2776 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2777 riscv_set_rvc (FALSE);
1080bf78 2778 if (riscv_subset_supports ("c"))
2922d21d 2779 riscv_set_rvc (TRUE);
2922d21d 2780
7f999549
JW		 2781 /* Enable RVE if specified by the -march option. */
2782 riscv_set_rve (FALSE);
1080bf78 2783 if (riscv_subset_supports ("e"))
7f999549
JW		 2784 riscv_set_rve (TRUE);
2785
8f595e9b
NC		 2786 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2787 according to DEFAULT_PRIV_SPEC. */
2788 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2789 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2790
0ac2b354
AB		 2791 /* If the CIE to be produced has not been overridden on the command line,
2792 then produce version 3 by default. This allows us to use the full
2793 range of registers in a .cfi_return_column directive. */
2794 if (flag_dwarf_cie_version == -1)
2795 flag_dwarf_cie_version = 3;
e23eba97
NC		 2796}
2797
2798long
2799md_pcrel_from (fixS *fixP)
2800{
2801 return fixP->fx_where + fixP->fx_frag->fr_address;
2802}
2803
2804/* Apply a fixup to the object file. */
2805
2806void
2807md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2808{
45f76423 2809 unsigned int subtype;
e23eba97 2810 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2811 bfd_boolean relaxable = FALSE;
c1b465c9 2812 offsetT loc;
a6cbf936 2813 segT sub_segment;
e23eba97
NC		 2814
2815 /* Remember value for tc_gen_reloc. */
2816 fixP->fx_addnumber = *valP;
2817
2818 switch (fixP->fx_r_type)
2819 {
e23eba97
NC		 2820 case BFD_RELOC_RISCV_HI20:
2821 case BFD_RELOC_RISCV_LO12_I:
2822 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2823 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2824 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2825 if (fixP->fx_addsy == NULL)
2826 fixP->fx_done = TRUE;
45f76423
AW		 2827 relaxable = TRUE;
2828 break;
2829
2830 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2831 case BFD_RELOC_RISCV_ADD8:
2832 case BFD_RELOC_RISCV_ADD16:
2833 case BFD_RELOC_RISCV_ADD32:
2834 case BFD_RELOC_RISCV_ADD64:
45f76423 2835 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2836 case BFD_RELOC_RISCV_SUB8:
2837 case BFD_RELOC_RISCV_SUB16:
2838 case BFD_RELOC_RISCV_SUB32:
2839 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2840 case BFD_RELOC_RISCV_RELAX:
2841 break;
2842
2843 case BFD_RELOC_RISCV_TPREL_HI20:
2844 case BFD_RELOC_RISCV_TPREL_LO12_I:
2845 case BFD_RELOC_RISCV_TPREL_LO12_S:
2846 case BFD_RELOC_RISCV_TPREL_ADD:
2847 relaxable = TRUE;
2848 /* Fall through. */
2849
2850 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2851 case BFD_RELOC_RISCV_TLS_GD_HI20:
2852 case BFD_RELOC_RISCV_TLS_DTPREL32:
2853 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2854 if (fixP->fx_addsy != NULL)
2855 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2856 else
2857 as_bad_where (fixP->fx_file, fixP->fx_line,
2858 _("TLS relocation against a constant"));
e23eba97
NC		 2859 break;
2860
e23eba97 2861 case BFD_RELOC_32:
a6cbf936
KLC		 2862 /* Use pc-relative relocation for FDE initial location.
2863 The symbol address in .eh_frame may be adjusted in
2864 _bfd_elf_discard_section_eh_frame, and the content of
2865 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2866 Therefore, we cannot insert a relocation whose addend symbol is
2867 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2868 if (fixP->fx_addsy && fixP->fx_subsy
2869 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2870 && strcmp (sub_segment->name, ".eh_frame") == 0
2871 && S_GET_VALUE (fixP->fx_subsy)
2872 == fixP->fx_frag->fr_address + fixP->fx_where)
2873 {
2874 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2875 fixP->fx_subsy = NULL;
2876 break;
2877 }
2878 /* Fall through. */
2879 case BFD_RELOC_64:
e23eba97
NC		 2880 case BFD_RELOC_16:
2881 case BFD_RELOC_8:
45f76423 2882 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2883 if (fixP->fx_addsy && fixP->fx_subsy)
2884 {
2885 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2886 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2887 fixP->fx_next->fx_subsy = NULL;
2888 fixP->fx_next->fx_offset = 0;
2889 fixP->fx_subsy = NULL;
2890
2891 switch (fixP->fx_r_type)
2892 {
2893 case BFD_RELOC_64:
2894 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2895 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2896 break;
2897
2898 case BFD_RELOC_32:
2899 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2900 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2901 break;
2902
2903 case BFD_RELOC_16:
2904 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2905 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2906 break;
2907
2908 case BFD_RELOC_8:
2909 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2910 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2911 break;
e23eba97 2912
45f76423
AW		 2913 case BFD_RELOC_RISCV_CFA:
2914 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2915 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2916 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2917 switch (subtype)
2918 {
2919 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2920 fixP->fx_where = loc + 1;
2921 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2922 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2923 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2924 break;
2925
2926 case DW_CFA_advance_loc2:
2927 fixP->fx_size = 2;
45f76423 2928 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2929 fixP->fx_where = loc + 1;
2930 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2931 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2932 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2933 break;
2934
2935 case DW_CFA_advance_loc4:
2936 fixP->fx_size = 4;
45f76423 2937 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2938 fixP->fx_where = loc;
2939 fixP->fx_next->fx_where = loc;
45f76423
AW		 2940 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2941 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2942 break;
2943
2944 default:
2945 if (subtype < 0x80 && (subtype & 0x40))
2946 {
2947 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2948 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2949 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2950 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2951 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2952 }
2953 else
2954 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2955 break;
2956 }
2957 break;
2958
e23eba97
NC		 2959 default:
2960 /* This case is unreachable. */
2961 abort ();
2962 }
2963 }
2964 /* Fall through. */
2965
2966 case BFD_RELOC_RVA:
2967 /* If we are deleting this reloc entry, we must fill in the
2968 value now. This can happen if we have a .word which is not
2969 resolved when it appears but is later defined. */
2970 if (fixP->fx_addsy == NULL)
2971 {
2972 gas_assert (fixP->fx_size <= sizeof (valueT));
2973 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2974 fixP->fx_done = 1;
2975 }
2976 break;
2977
2978 case BFD_RELOC_RISCV_JMP:
2979 if (fixP->fx_addsy)
2980 {
2981 /* Fill in a tentative value to improve objdump readability. */
2982 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2983 bfd_vma delta = target - md_pcrel_from (fixP);
2984 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2985 }
2986 break;
2987
2988 case BFD_RELOC_12_PCREL:
2989 if (fixP->fx_addsy)
2990 {
2991 /* Fill in a tentative value to improve objdump readability. */
2992 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2993 bfd_vma delta = target - md_pcrel_from (fixP);
2994 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2995 }
2996 break;
2997
2998 case BFD_RELOC_RISCV_RVC_BRANCH:
2999 if (fixP->fx_addsy)
3000 {
3001 /* Fill in a tentative value to improve objdump readability. */
3002 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3003 bfd_vma delta = target - md_pcrel_from (fixP);
3004 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
3005 }
3006 break;
3007
3008 case BFD_RELOC_RISCV_RVC_JUMP:
3009 if (fixP->fx_addsy)
3010 {
3011 /* Fill in a tentative value to improve objdump readability. */
3012 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3013 bfd_vma delta = target - md_pcrel_from (fixP);
3014 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3015 }
3016 break;
3017
e23eba97
NC		 3018 case BFD_RELOC_RISCV_CALL:
3019 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3020 relaxable = TRUE;
3021 break;
3022
9d06997a 3023 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3024 case BFD_RELOC_RISCV_PCREL_LO12_S:
3025 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3026 relaxable = riscv_opts.relax;
3027 break;
3028
e23eba97
NC		 3029 case BFD_RELOC_RISCV_ALIGN:
3030 break;
3031
3032 default:
3033 /* We ignore generic BFD relocations we don't know about. */
3034 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3035 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3036 }
45f76423 3037
e294484e
AW		 3038 if (fixP->fx_subsy != NULL)
3039 as_bad_where (fixP->fx_file, fixP->fx_line,
3040 _("unsupported symbol subtraction"));
3041
45f76423
AW		 3042 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3043 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3044 {
3045 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3046 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3047 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3048 fixP->fx_next->fx_size = 0;
45f76423
AW		 3049 }
3050}
3051
3052/* Because the value of .cfi_remember_state may changed after relaxation,
3053 we insert a fix to relocate it again in link-time. */
3054
3055void
3056riscv_pre_output_hook (void)
3057{
3058 const frchainS *frch;
72393fd1
JW		 3059 segT s;
3060
3061 /* Save the current segment info. */
3062 segT seg = now_seg;
3063 subsegT subseg = now_subseg;
45f76423
AW		 3064
3065 for (s = stdoutput->sections; s; s = s->next)
3066 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3067 {
7cb7b948 3068 fragS *frag;
45f76423
AW		 3069
3070 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3071 {
3072 if (frag->fr_type == rs_cfa)
3073 {
45f76423 3074 expressionS exp;
8d1015a8 3075 expressionS *symval;
45f76423 3076
8d1015a8 3077 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3078 exp.X_op = O_subtract;
8d1015a8 3079 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3080 exp.X_add_number = 0;
8d1015a8 3081 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3082
72393fd1
JW		 3083 /* We must set the segment before creating a frag after all
3084 frag chains have been chained together. */
3085 subseg_set (s, frch->frch_subseg);
3086
c1b465c9 3087 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3088 BFD_RELOC_RISCV_CFA);
3089 }
3090 }
3091 }
72393fd1
JW		 3092
3093 /* Restore the original segment info. */
3094 subseg_set (seg, subseg);
e23eba97
NC		 3095}
3096
45f76423 3097
e23eba97
NC		 3098/* This structure is used to hold a stack of .option values. */
3099
3100struct riscv_option_stack
3101{
3102 struct riscv_option_stack *next;
3103 struct riscv_set_options options;
3104};
3105
3106static struct riscv_option_stack *riscv_opts_stack;
3107
3108/* Handle the .option pseudo-op. */
3109
3110static void
3111s_riscv_option (int x ATTRIBUTE_UNUSED)
3112{
3113 char *name = input_line_pointer, ch;
3114
3115 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3116 ++input_line_pointer;
3117 ch = *input_line_pointer;
3118 *input_line_pointer = '\0';
3119
3120 if (strcmp (name, "rvc") == 0)
3121 riscv_set_rvc (TRUE);
3122 else if (strcmp (name, "norvc") == 0)
3123 riscv_set_rvc (FALSE);
3124 else if (strcmp (name, "pic") == 0)
3125 riscv_opts.pic = TRUE;
3126 else if (strcmp (name, "nopic") == 0)
3127 riscv_opts.pic = FALSE;
45f76423
AW		 3128 else if (strcmp (name, "relax") == 0)
3129 riscv_opts.relax = TRUE;
3130 else if (strcmp (name, "norelax") == 0)
3131 riscv_opts.relax = FALSE;
2ca89224
NC		 3132 else if (strcmp (name, "csr-check") == 0)
3133 riscv_opts.csr_check = TRUE;
3134 else if (strcmp (name, "no-csr-check") == 0)
3135 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3136 else if (strcmp (name, "push") == 0)
3137 {
3138 struct riscv_option_stack *s;
3139
3140 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3141 s->next = riscv_opts_stack;
3142 s->options = riscv_opts;
3143 riscv_opts_stack = s;
3144 }
3145 else if (strcmp (name, "pop") == 0)
3146 {
3147 struct riscv_option_stack *s;
3148
3149 s = riscv_opts_stack;
3150 if (s == NULL)
3151 as_bad (_(".option pop with no .option push"));
3152 else
3153 {
3154 riscv_opts = s->options;
3155 riscv_opts_stack = s->next;
3156 free (s);
3157 }
3158 }
3159 else
3160 {
3161 as_warn (_("Unrecognized .option directive: %s\n"), name);
3162 }
3163 *input_line_pointer = ch;
3164 demand_empty_rest_of_line ();
3165}
3166
3167/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3168 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3169 use in DWARF debug information. */
3170
3171static void
3172s_dtprel (int bytes)
3173{
3174 expressionS ex;
3175 char *p;
3176
3177 expression (&ex);
3178
3179 if (ex.X_op != O_symbol)
3180 {
3181 as_bad (_("Unsupported use of %s"), (bytes == 8
3182 ? ".dtpreldword"
3183 : ".dtprelword"));
3184 ignore_rest_of_line ();
3185 }
3186
3187 p = frag_more (bytes);
3188 md_number_to_chars (p, 0, bytes);
3189 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3190 (bytes == 8
3191 ? BFD_RELOC_RISCV_TLS_DTPREL64
3192 : BFD_RELOC_RISCV_TLS_DTPREL32));
3193
3194 demand_empty_rest_of_line ();
3195}
3196
3197/* Handle the .bss pseudo-op. */
3198
3199static void
3200s_bss (int ignore ATTRIBUTE_UNUSED)
3201{
3202 subseg_set (bss_section, 0);
3203 demand_empty_rest_of_line ();
3204}
3205
e23eba97 3206static void
d115ab8e 3207riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3208{
d115ab8e 3209 bfd_vma i = 0;
e23eba97 3210
e5b737de
AW		 3211 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3212 means we are not within a valid instruction sequence. It is thus safe
3213 to use a zero byte, even though that is not a valid instruction. */
3214 if (bytes % 2 == 1)
3215 buf[i++] = 0;
3216
3217 /* Use at most one 2-byte NOP. */
3218 if ((bytes - i) % 4 == 2)
e23eba97 3219 {
e5b737de 3220 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 3221 i += 2;
e23eba97
NC		 3222 }
3223
e5b737de 3224 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 3225 for ( ; i < bytes; i += 4)
3226 md_number_to_chars (buf + i, RISCV_NOP, 4);
3227}
e23eba97 3228
d115ab8e
AW		 3229/* Called from md_do_align. Used to create an alignment frag in a
3230 code section by emitting a worst-case NOP sequence that the linker
3231 will later relax to the correct number of NOPs. We can't compute
3232 the correct alignment now because of other linker relaxations. */
3233
3234bfd_boolean
3235riscv_frag_align_code (int n)
3236{
e5b737de 3237 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3238 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3239 bfd_vma worst_case_bytes = bytes - insn_alignment;
3240 char *nops;
ed0816bd 3241 expressionS ex;
d115ab8e 3242
36877bfb
JW		 3243 /* If we are moving to a smaller alignment than the instruction size, then no
3244 alignment is required. */
3245 if (bytes <= insn_alignment)
3246 return TRUE;
3247
d115ab8e
AW		 3248 /* When not relaxing, riscv_handle_align handles code alignment. */
3249 if (!riscv_opts.relax)
3250 return FALSE;
e23eba97 3251
e80ae190
JW		 3252 nops = frag_more (worst_case_bytes);
3253
ed0816bd
PD		 3254 ex.X_op = O_constant;
3255 ex.X_add_number = worst_case_bytes;
d115ab8e 3256
ed0816bd 3257 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3258
ed0816bd
PD		 3259 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3260 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3261
d115ab8e
AW		 3262 return TRUE;
3263}
e23eba97 3264
d115ab8e
AW		 3265/* Implement HANDLE_ALIGN. */
3266
3267void
3268riscv_handle_align (fragS *fragP)
3269{
3270 switch (fragP->fr_type)
3271 {
3272 case rs_align_code:
3273 /* When relaxing, riscv_frag_align_code handles code alignment. */
3274 if (!riscv_opts.relax)
3275 {
e80ae190
JW		 3276 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3277 - fragP->fr_address - fragP->fr_fix);
3278 /* We have 4 byte uncompressed nops. */
3279 bfd_signed_vma size = 4;
3280 bfd_signed_vma excess = bytes % size;
3281 char *p = fragP->fr_literal + fragP->fr_fix;
3282
3283 if (bytes <= 0)
d115ab8e
AW		 3284 break;
3285
e80ae190
JW		 3286 /* Insert zeros or compressed nops to get 4 byte alignment. */
3287 if (excess)
3288 {
3289 riscv_make_nops (p, excess);
3290 fragP->fr_fix += excess;
3291 p += excess;
3292 }
3293
3294 /* Insert variable number of 4 byte uncompressed nops. */
3295 riscv_make_nops (p, size);
3296 fragP->fr_var = size;
d115ab8e
AW		 3297 }
3298 break;
3299
3300 default:
3301 break;
3302 }
e23eba97
NC		 3303}
3304
3305int
3306md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3307{
3308 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3309}
3310
3311/* Translate internal representation of relocation info to BFD target
3312 format. */
3313
3314arelent *
3315tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3316{
3317 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3318
3319 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3320 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3321 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3322 reloc->addend = fixp->fx_addnumber;
3323
3324 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3325 if (reloc->howto == NULL)
3326 {
3327 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3328 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3329 {
3330 /* We don't have R_RISCV_8/16, but for this special case,
3331 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3332 return reloc;
3333 }
3334
3335 as_bad_where (fixp->fx_file, fixp->fx_line,
3336 _("cannot represent %s relocation in object file"),
3337 bfd_get_reloc_code_name (fixp->fx_r_type));
3338 return NULL;
3339 }
3340
3341 return reloc;
3342}
3343
3344int
3345riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3346{
3347 if (RELAX_BRANCH_P (fragp->fr_subtype))
3348 {
3349 offsetT old_var = fragp->fr_var;
3350 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3351 return fragp->fr_var - old_var;
3352 }
3353
3354 return 0;
3355}
3356
3357/* Expand far branches to multi-instruction sequences. */
3358
3359static void
3360md_convert_frag_branch (fragS *fragp)
3361{
3362 bfd_byte *buf;
3363 expressionS exp;
3364 fixS *fixp;
3365 insn_t insn;
3366 int rs1, reloc;
3367
3368 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3369
3370 exp.X_op = O_symbol;
3371 exp.X_add_symbol = fragp->fr_symbol;
3372 exp.X_add_number = fragp->fr_offset;
3373
3374 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3375
3376 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3377 {
3378 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3379 {
3380 case 8:
3381 case 4:
3382 /* Expand the RVC branch into a RISC-V one. */
3383 insn = bfd_getl16 (buf);
3384 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3385 if ((insn & MASK_C_J) == MATCH_C_J)
3386 insn = MATCH_JAL;
3387 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3388 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3389 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3390 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3391 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3392 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3393 else
3394 abort ();
3395 bfd_putl32 (insn, buf);
3396 break;
3397
3398 case 6:
3399 /* Invert the branch condition. Branch over the jump. */
3400 insn = bfd_getl16 (buf);
3401 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3402 insn |= ENCODE_RVC_B_IMM (6);
3403 bfd_putl16 (insn, buf);
3404 buf += 2;
3405 goto jump;
3406
3407 case 2:
3408 /* Just keep the RVC branch. */
3409 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3410 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3411 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3412 2, &exp, FALSE, reloc);
3413 buf += 2;
3414 goto done;
3415
3416 default:
1d65abb5 3417 abort ();
e23eba97
NC		 3418 }
3419 }
3420
3421 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3422 {
3423 case 8:
3424 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3425
3426 /* Invert the branch condition. Branch over the jump. */
3427 insn = bfd_getl32 (buf);
3428 insn ^= MATCH_BEQ ^ MATCH_BNE;
3429 insn |= ENCODE_SBTYPE_IMM (8);
3430 md_number_to_chars ((char *) buf, insn, 4);
3431 buf += 4;
3432
dc1e8a47 3433 jump:
e23eba97
NC		 3434 /* Jump to the target. */
3435 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3436 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
3437 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
3438 buf += 4;
3439 break;
3440
3441 case 4:
3442 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3443 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3444 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3445 4, &exp, FALSE, reloc);
3446 buf += 4;
3447 break;
3448
3449 default:
3450 abort ();
3451 }
3452
dc1e8a47 3453 done:
e23eba97
NC		 3454 fixp->fx_file = fragp->fr_file;
3455 fixp->fx_line = fragp->fr_line;
3456
3457 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3458 + fragp->fr_fix + fragp->fr_var);
3459
3460 fragp->fr_fix += fragp->fr_var;
3461}
3462
3463/* Relax a machine dependent frag. This returns the amount by which
3464 the current size of the frag should change. */
3465
3466void
3467md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3468 fragS *fragp)
3469{
3470 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3471 md_convert_frag_branch (fragp);
3472}
3473
3474void
3475md_show_usage (FILE *stream)
3476{
3477 fprintf (stream, _("\
3478RISC-V options:\n\
8f595e9b
NC		 3479 -fpic generate position-independent code\n\
3480 -fno-pic don't generate position-independent code (default)\n\
3481 -march=ISA set the RISC-V architecture\n\
3482 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3483 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3484 -mabi=ABI set the RISC-V ABI\n\
3485 -mrelax enable relax (default)\n\
3486 -mno-relax disable relax\n\
3487 -march-attr generate RISC-V arch attribute\n\
3488 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3489"));
3490}
3491
3492/* Standard calling conventions leave the CFA at SP on entry. */
3493void
3494riscv_cfi_frame_initial_instructions (void)
3495{
3496 cfi_add_CFA_def_cfa_register (X_SP);
3497}
3498
3499int
3500tc_riscv_regname_to_dw2regnum (char *regname)
3501{
3502 int reg;
3503
3504 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3505 return reg;
3506
3507 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3508 return reg + 32;
3509
4762fe62
AB		 3510 /* CSRs are numbered 4096 -> 8191. */
3511 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3512 return reg + 4096;
3513
e23eba97
NC		 3514 as_bad (_("unknown register `%s'"), regname);
3515 return -1;
3516}
3517
3518void
3519riscv_elf_final_processing (void)
3520{
6e1605e4 3521 riscv_set_abi_by_arch ();
e23eba97 3522 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3523}
3524
3525/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3526 since these directives break relaxation when used with symbol deltas. */
3527
3528static void
3529s_riscv_leb128 (int sign)
3530{
3531 expressionS exp;
3532 char *save_in = input_line_pointer;
3533
3534 expression (&exp);
3535 if (exp.X_op != O_constant)
3536 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3537 demand_empty_rest_of_line ();
3538
3539 input_line_pointer = save_in;
3540 return s_leb128 (sign);
3541}
3542
0e35537d
JW		 3543/* Parse the .insn directive. */
3544
3545static void
3546s_riscv_insn (int x ATTRIBUTE_UNUSED)
3547{
3548 char *str = input_line_pointer;
3549 struct riscv_cl_insn insn;
3550 expressionS imm_expr;
3551 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3552 char save_c;
3553
3554 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3555 ++input_line_pointer;
3556
3557 save_c = *input_line_pointer;
3558 *input_line_pointer = '\0';
3559
3560 const char *error = riscv_ip (str, &insn, &imm_expr,
3561 &imm_reloc, insn_type_hash);
3562
3563 if (error)
3564 {
3565 as_bad ("%s `%s'", error, str);
3566 }
3567 else
3568 {
3569 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3570 append_insn (&insn, &imm_expr, imm_reloc);
3571 }
3572
3573 *input_line_pointer = save_c;
3574 demand_empty_rest_of_line ();
3575}
3576
8f595e9b
NC		 3577/* Update arch and priv attributes. If we don't set the corresponding ELF
3578 attributes, then try to output the default ones. */
2dc8dd17
JW		 3579
3580static void
8f595e9b 3581riscv_write_out_attrs (void)
2dc8dd17 3582{
8f595e9b
NC		 3583 const char *arch_str, *priv_str, *p;
3584 /* versions[0] is major, versions[1] is minor,
3585 and versions[3] is revision. */
3586 unsigned versions[3] = {0}, number = 0;
3587 unsigned int i;
2dc8dd17 3588
8f595e9b
NC		 3589 /* Re-write arch attribute to normalize the arch string. */
3590 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3591 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3592 xfree ((void *)arch_str);
8f595e9b
NC		 3593
3594 /* For the file without any instruction, we don't set the default_priv_spec
3595 according to the priv attributes since the md_assemble isn't called.
3596 Call riscv_set_default_priv_spec here for the above case, although
3597 it seems strange. */
3598 if (!start_assemble
3599 && !riscv_set_default_priv_spec (NULL))
3600 return;
3601
1a79004f
NC		 3602 /* If we already have set elf priv attributes, then no need to do anything,
3603 assembler will generate them according to what you set. Otherwise, don't
3604 generate or update them when no CSR and priv instructions are used.
3605 Generate the priv attributes according to default_priv_spec, which can be
3606 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3607 priv attribute sets. */
3608 if (!explicit_priv_attr)
3fc6c3dc
NC		 3609 return;
3610
8f595e9b
NC		 3611 /* Re-write priv attributes by default_priv_spec. */
3612 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3613 p = priv_str;
3614 for (i = 0; *p; ++p)
3615 {
3616 if (*p == '.' && i < 3)
3617 {
3618 versions[i++] = number;
3619 number = 0;
3620 }
3621 else if (ISDIGIT (*p))
3622 number = (number * 10) + (*p - '0');
3623 else
3624 {
3625 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3626 return;
3627 }
3628 }
3629 versions[i] = number;
3630
3631 /* Set the priv attributes. */
3632 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3633 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3634 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3635}
3636
8f595e9b
NC		 3637/* Add the default contents for the .riscv.attributes section. If any
3638 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3639 to update the arch and priv attributes. */
2dc8dd17
JW		 3640
3641static void
3642riscv_set_public_attributes (void)
3643{
8f595e9b
NC		 3644 if (riscv_opts.arch_attr || explicit_attr)
3645 riscv_write_out_attrs ();
2dc8dd17
JW		 3646}
3647
3648/* Called after all assembly has been done. */
3649
3650void
3651riscv_md_end (void)
3652{
3653 riscv_set_public_attributes ();
3654}
3655
3656/* Given a symbolic attribute NAME, return the proper integer value.
3657 Returns -1 if the attribute is not known. */
3658
3659int
3660riscv_convert_symbolic_attribute (const char *name)
3661{
3662 static const struct
3663 {
3664 const char * name;
3665 const int tag;
3666 }
3667 attribute_table[] =
3668 {
3669 /* When you modify this table you should
3670 also modify the list in doc/c-riscv.texi. */
3671#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3672 T(arch),
3673 T(priv_spec),
3674 T(priv_spec_minor),
3675 T(priv_spec_revision),
3676 T(unaligned_access),
3677 T(stack_align),
3678#undef T
3679 };
3680
3681 unsigned int i;
3682
3683 if (name == NULL)
3684 return -1;
3685
3686 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3687 if (strcmp (name, attribute_table[i].name) == 0)
3688 return attribute_table[i].tag;
3689
3690 return -1;
3691}
3692
3693/* Parse a .attribute directive. */
3694
3695static void
3696s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3697{
3698 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3699 unsigned old_xlen;
3700 obj_attribute *attr;
2dc8dd17 3701
8f595e9b
NC		 3702 explicit_attr = TRUE;
3703 switch (tag)
2dc8dd17 3704 {
8f595e9b
NC		 3705 case Tag_RISCV_arch:
3706 old_xlen = xlen;
2dc8dd17
JW		 3707 attr = elf_known_obj_attributes_proc (stdoutput);
3708 if (!start_assemble)
3709 riscv_set_arch (attr[Tag_RISCV_arch].s);
3710 else
3711 as_fatal (_(".attribute arch must set before any instructions"));
3712
3713 if (old_xlen != xlen)
3714 {
3715 /* We must re-init bfd again if xlen is changed. */
3716 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3717 bfd_find_target (riscv_target_format (), stdoutput);
3718
3719 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3720 as_warn (_("Could not set architecture and machine"));
3721 }
8f595e9b
NC		 3722 break;
3723
3724 case Tag_RISCV_priv_spec:
3725 case Tag_RISCV_priv_spec_minor:
3726 case Tag_RISCV_priv_spec_revision:
3727 if (start_assemble)
3728 as_fatal (_(".attribute priv spec must set before any instructions"));
3729 break;
3730
3731 default:
3732 break;
2dc8dd17
JW		 3733 }
3734}
3735
e23eba97
NC		 3736/* Pseudo-op table. */
3737
3738static const pseudo_typeS riscv_pseudo_table[] =
3739{
3740 /* RISC-V-specific pseudo-ops. */
3741 {"option", s_riscv_option, 0},
3742 {"half", cons, 2},
3743 {"word", cons, 4},
3744 {"dword", cons, 8},
3745 {"dtprelword", s_dtprel, 4},
3746 {"dtpreldword", s_dtprel, 8},
3747 {"bss", s_bss, 0},
e23eba97
NC		 3748 {"uleb128", s_riscv_leb128, 0},
3749 {"sleb128", s_riscv_leb128, 1},
0e35537d 3750 {"insn", s_riscv_insn, 0},
2dc8dd17 3751 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3752
3753 { NULL, NULL, 0 },
3754};
3755
3756void
3757riscv_pop_insert (void)
3758{
3759 extern void pop_insert (const pseudo_typeS *);
3760
3761 pop_insert (riscv_pseudo_table);
3762}
GDB Binutils - Deliverables
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