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gas: Silence GCC 10 warning tc-vax.c
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
b3adc24a 2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
e23eba97 94
2922d21d 95#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 96#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
97
98static unsigned elf_flags = 0;
99
8f595e9b
NC		 100/* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
102
103static int
104riscv_set_default_isa_spec (const char *s)
105{
106 enum riscv_isa_spec_class class;
107 if (!riscv_get_isa_spec_class (s, &class))
108 {
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s);
111 return 0;
112 }
113 else
114 default_isa_spec = class;
115 return 1;
116}
117
118/* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
122
123static int
124riscv_set_default_priv_spec (const char *s)
125{
126 enum riscv_priv_spec_class class;
127 unsigned major, minor, revision;
128 obj_attribute *attr;
129 size_t buf_size;
130 char *buf;
131
132 /* Find the corresponding priv spec class. */
133 if (riscv_get_priv_spec_class (s, &class))
134 {
135 default_priv_spec = class;
136 return 1;
137 }
138
139 if (s != NULL)
140 {
141 as_bad (_("Unknown default privilege spec `%s' set by "
142 "-mpriv-spec or --with-priv-spec"), s);
143 return 0;
144 }
145
146 /* Try to set the default_priv_spec according to the priv attributes. */
147 attr = elf_known_obj_attributes_proc (stdoutput);
148 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
149 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
150 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
151
152 /* The priv attributes setting 0.0.0 is meaningless. We should have set
153 the default_priv_spec by md_parse_option and riscv_after_parse_args,
154 so just skip the following setting. */
155 if (major == 0 && minor == 0 && revision == 0)
156 return 1;
157
158 buf_size = riscv_estimate_digit (major)
159 + 1 /* '.' */
160 + riscv_estimate_digit (minor)
161 + 1; /* string terminator */
162 if (revision != 0)
163 {
164 buf_size += 1 /* '.' */
165 + riscv_estimate_digit (revision);
166 buf = xmalloc (buf_size);
167 snprintf (buf, buf_size, "%d.%d.%d", major, minor, revision);
168 }
169 else
170 {
171 buf = xmalloc (buf_size);
172 snprintf (buf, buf_size, "%d.%d", major, minor);
173 }
174
175 if (riscv_get_priv_spec_class (buf, &class))
176 {
177 default_priv_spec = class;
178 free (buf);
179 return 1;
180 }
181
182 /* Still can not find the priv spec class. */
183 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
184 "privilege attributes"), major, minor, revision);
185 free (buf);
186 return 0;
187}
188
e23eba97
NC		 189/* This is the set of options which the .option pseudo-op may modify. */
190
191struct riscv_set_options
192{
193 int pic; /* Generate position-independent code. */
194 int rvc; /* Generate RVC code. */
7f999549 195 int rve; /* Generate RVE code. */
45f76423 196 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 197 int arch_attr; /* Emit arch attribute. */
2ca89224 198 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 199};
200
201static struct riscv_set_options riscv_opts =
202{
203 0, /* pic */
204 0, /* rvc */
7f999549 205 0, /* rve */
45f76423 206 1, /* relax */
2dc8dd17 207 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 208 0. /* csr_check */
e23eba97
NC		 209};
210
211static void
212riscv_set_rvc (bfd_boolean rvc_value)
213{
214 if (rvc_value)
215 elf_flags |= EF_RISCV_RVC;
216
217 riscv_opts.rvc = rvc_value;
218}
219
7f999549
JW		 220static void
221riscv_set_rve (bfd_boolean rve_value)
222{
223 riscv_opts.rve = rve_value;
224}
225
1080bf78 226static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 227
228static bfd_boolean
1080bf78 229riscv_subset_supports (const char *feature)
e23eba97 230{
1080bf78
JW		 231 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
232 return TRUE;
e23eba97 233
1080bf78 234 return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
e23eba97
NC		 235}
236
43135d3b 237static bfd_boolean
7e9ad3a3 238riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 239{
7e9ad3a3
JW		 240 switch (insn_class)
241 {
242 case INSN_CLASS_I: return riscv_subset_supports ("i");
243 case INSN_CLASS_C: return riscv_subset_supports ("c");
244 case INSN_CLASS_A: return riscv_subset_supports ("a");
245 case INSN_CLASS_M: return riscv_subset_supports ("m");
246 case INSN_CLASS_F: return riscv_subset_supports ("f");
247 case INSN_CLASS_D: return riscv_subset_supports ("d");
248 case INSN_CLASS_D_AND_C:
249 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
250
251 case INSN_CLASS_F_AND_C:
252 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
43135d3b 253
7e9ad3a3 254 case INSN_CLASS_Q: return riscv_subset_supports ("q");
43135d3b 255
7e9ad3a3
JW		 256 default:
257 as_fatal ("Unreachable");
258 return FALSE;
259 }
43135d3b
JW		 260}
261
8f595e9b
NC		 262/* Handle of the extension with version hash table. */
263static struct hash_control *ext_version_hash = NULL;
264
265static struct hash_control *
266init_ext_version_hash (const struct riscv_ext_version *table)
267{
268 int i = 0;
269 struct hash_control *hash = hash_new ();
270
271 while (table[i].name)
272 {
273 const char *name = table[i].name;
274 const char *hash_error =
275 hash_insert (hash, name, (void *) &table[i]);
276
277 if (hash_error != NULL)
278 {
279 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
280 table[i].name, hash_error);
281 /* Probably a memory allocation problem? Give up now. */
282 as_fatal (_("Broken assembler. No assembly attempted."));
283 return NULL;
284 }
285
286 i++;
287 while (table[i].name
288 && strcmp (table[i].name, name) == 0)
289 i++;
290 }
291
292 return hash;
293}
294
295static void
296riscv_get_default_ext_version (const char *name,
297 unsigned int *major_version,
298 unsigned int *minor_version)
299{
300 struct riscv_ext_version *ext;
301
302 *major_version = 0;
303 *minor_version = 0;
304
305 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
306 return;
307
308 ext = (struct riscv_ext_version *) hash_find (ext_version_hash, name);
309 while (ext
310 && ext->name
311 && strcmp (ext->name, name) == 0)
312 {
313 if (ext->isa_spec_class == default_isa_spec)
314 {
315 *major_version = ext->major_version;
316 *minor_version = ext->minor_version;
317 return;
318 }
319 ext++;
320 }
321}
322
2922d21d 323/* Set which ISA and extensions are available. */
e23eba97 324
e23eba97 325static void
2922d21d 326riscv_set_arch (const char *s)
e23eba97 327{
1080bf78
JW		 328 riscv_parse_subset_t rps;
329 rps.subset_list = &riscv_subsets;
330 rps.error_handler = as_fatal;
331 rps.xlen = &xlen;
8f595e9b
NC		 332 rps.get_default_version = riscv_get_default_ext_version;
333
334 if (s == NULL)
335 return;
7f999549 336
1080bf78
JW		 337 riscv_release_subset_list (&riscv_subsets);
338 riscv_parse_subset (&rps, s);
e23eba97
NC		 339}
340
341/* Handle of the OPCODE hash table. */
342static struct hash_control *op_hash = NULL;
343
0e35537d
JW		 344/* Handle of the type of .insn hash table. */
345static struct hash_control *insn_type_hash = NULL;
346
e23eba97
NC		 347/* This array holds the chars that always start a comment. If the
348 pre-processor is disabled, these aren't very useful */
349const char comment_chars[] = "#";
350
351/* This array holds the chars that only start a comment at the beginning of
352 a line. If the line seems to have the form '# 123 filename'
353 .line and .file directives will appear in the pre-processed output */
354/* Note that input_file.c hand checks for '#' at the beginning of the
355 first line of the input file. This is because the compiler outputs
356 #NO_APP at the beginning of its output. */
357/* Also note that C style comments are always supported. */
358const char line_comment_chars[] = "#";
359
360/* This array holds machine specific line separator characters. */
361const char line_separator_chars[] = ";";
362
363/* Chars that can be used to separate mant from exp in floating point nums */
364const char EXP_CHARS[] = "eE";
365
366/* Chars that mean this number is a floating point constant */
367/* As in 0f12.456 */
368/* or 0d1.2345e12 */
369const char FLT_CHARS[] = "rRsSfFdDxXpP";
370
2dc8dd17
JW		 371/* Indicate we are already assemble any instructions or not. */
372static bfd_boolean start_assemble = FALSE;
373
8f595e9b
NC		 374/* Indicate ELF attributes are explictly set. */
375static bfd_boolean explicit_attr = FALSE;
2dc8dd17 376
e23eba97
NC		 377/* Macros for encoding relaxation state for RVC branches and far jumps. */
378#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
379 ((relax_substateT) \
380 (0xc0000000 \
381 | ((uncond) ? 1 : 0) \
382 | ((rvc) ? 2 : 0) \
383 | ((length) << 2)))
384#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
385#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
386#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
387#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
388
389/* Is the given value a sign-extended 32-bit value? */
390#define IS_SEXT_32BIT_NUM(x) \
391 (((x) &~ (offsetT) 0x7fffffff) == 0 \
392 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
393
394/* Is the given value a zero-extended 32-bit value? Or a negated one? */
395#define IS_ZEXT_32BIT_NUM(x) \
396 (((x) &~ (offsetT) 0xffffffff) == 0 \
397 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
398
399/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
400 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
401#define INSERT_OPERAND(FIELD, INSN, VALUE) \
402 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
403
404/* Determine if an instruction matches an opcode. */
405#define OPCODE_MATCHES(OPCODE, OP) \
406 (((OPCODE) & MASK_##OP) == MATCH_##OP)
407
408static char *expr_end;
409
410/* The default target format to use. */
411
412const char *
413riscv_target_format (void)
414{
415 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
416}
417
418/* Return the length of instruction INSN. */
419
420static inline unsigned int
421insn_length (const struct riscv_cl_insn *insn)
422{
423 return riscv_insn_length (insn->insn_opcode);
424}
425
426/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
427
428static void
429create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
430{
431 insn->insn_mo = mo;
432 insn->insn_opcode = mo->match;
433 insn->frag = NULL;
434 insn->where = 0;
435 insn->fixp = NULL;
436}
437
438/* Install INSN at the location specified by its "frag" and "where" fields. */
439
440static void
441install_insn (const struct riscv_cl_insn *insn)
442{
443 char *f = insn->frag->fr_literal + insn->where;
444 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
445}
446
447/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
448 and install the opcode in the new location. */
449
450static void
451move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
452{
453 insn->frag = frag;
454 insn->where = where;
455 if (insn->fixp != NULL)
456 {
457 insn->fixp->fx_frag = frag;
458 insn->fixp->fx_where = where;
459 }
460 install_insn (insn);
461}
462
463/* Add INSN to the end of the output. */
464
465static void
466add_fixed_insn (struct riscv_cl_insn *insn)
467{
468 char *f = frag_more (insn_length (insn));
469 move_insn (insn, frag_now, f - frag_now->fr_literal);
470}
471
472static void
473add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
474 relax_substateT subtype, symbolS *symbol, offsetT offset)
475{
476 frag_grow (max_chars);
477 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
478 frag_var (rs_machine_dependent, max_chars, var,
479 subtype, symbol, offset, NULL);
480}
481
482/* Compute the length of a branch sequence, and adjust the stored length
483 accordingly. If FRAGP is NULL, the worst-case length is returned. */
484
485static unsigned
486relaxed_branch_length (fragS *fragp, asection *sec, int update)
487{
488 int jump, rvc, length = 8;
489
490 if (!fragp)
491 return length;
492
493 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
494 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
495 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
496
497 /* Assume jumps are in range; the linker will catch any that aren't. */
498 length = jump ? 4 : 8;
499
500 if (fragp->fr_symbol != NULL
501 && S_IS_DEFINED (fragp->fr_symbol)
01156111 502 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 503 && sec == S_GET_SEGMENT (fragp->fr_symbol))
504 {
505 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
506 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
507 val -= fragp->fr_address + fragp->fr_fix;
508
509 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
510 length = 2;
511 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
512 length = 4;
513 else if (!jump && rvc)
514 length = 6;
515 }
516
517 if (update)
518 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
519
520 return length;
521}
522
0e35537d
JW		 523/* Information about an opcode name, mnemonics and its value. */
524struct opcode_name_t
525{
526 const char *name;
527 unsigned int val;
528};
529
530/* List for all supported opcode name. */
531static const struct opcode_name_t opcode_name_list[] =
532{
533 {"C0", 0x0},
534 {"C1", 0x1},
535 {"C2", 0x2},
536
537 {"LOAD", 0x03},
538 {"LOAD_FP", 0x07},
539 {"CUSTOM_0", 0x0b},
540 {"MISC_MEM", 0x0f},
541 {"OP_IMM", 0x13},
542 {"AUIPC", 0x17},
543 {"OP_IMM_32", 0x1b},
544 /* 48b 0x1f. */
545
546 {"STORE", 0x23},
547 {"STORE_FP", 0x27},
548 {"CUSTOM_1", 0x2b},
549 {"AMO", 0x2f},
550 {"OP", 0x33},
551 {"LUI", 0x37},
552 {"OP_32", 0x3b},
553 /* 64b 0x3f. */
554
555 {"MADD", 0x43},
556 {"MSUB", 0x47},
557 {"NMADD", 0x4f},
558 {"NMSUB", 0x4b},
559 {"OP_FP", 0x53},
560 /*reserved 0x57. */
561 {"CUSTOM_2", 0x5b},
562 /* 48b 0x5f. */
563
564 {"BRANCH", 0x63},
565 {"JALR", 0x67},
566 /*reserved 0x5b. */
567 {"JAL", 0x6f},
568 {"SYSTEM", 0x73},
569 /*reserved 0x77. */
570 {"CUSTOM_3", 0x7b},
571 /* >80b 0x7f. */
572
573 {NULL, 0}
574};
575
576/* Hash table for lookup opcode name. */
577static struct hash_control *opcode_names_hash = NULL;
578
579/* Initialization for hash table of opcode name. */
580static void
581init_opcode_names_hash (void)
582{
583 const char *retval;
584 const struct opcode_name_t *opcode;
585
586 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
587 {
588 retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
589
590 if (retval != NULL)
591 as_fatal (_("internal error: can't hash `%s': %s"),
592 opcode->name, retval);
593 }
594}
595
596/* Find `s` is a valid opcode name or not,
597 return the opcode name info if found. */
598static const struct opcode_name_t *
599opcode_name_lookup (char **s)
600{
601 char *e;
602 char save_c;
603 struct opcode_name_t *o;
604
605 /* Find end of name. */
606 e = *s;
607 if (is_name_beginner (*e))
608 ++e;
609 while (is_part_of_name (*e))
610 ++e;
611
612 /* Terminate name. */
613 save_c = *e;
614 *e = '\0';
615
616 o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s);
617
618 /* Advance to next token if one was recognized. */
619 if (o)
620 *s = e;
621
622 *e = save_c;
623 expr_end = e;
624
625 return o;
626}
627
e23eba97
NC		 628enum reg_class
629{
630 RCLASS_GPR,
631 RCLASS_FPR,
8f595e9b
NC		 632 RCLASS_MAX,
633
634 RCLASS_CSR
e23eba97
NC		 635};
636
637static struct hash_control *reg_names_hash = NULL;
bd0cf5a6 638static struct hash_control *csr_extra_hash = NULL;
e23eba97
NC		 639
640#define ENCODE_REG_HASH(cls, n) \
641 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
642#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
643#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
644
645static void
646hash_reg_name (enum reg_class class, const char *name, unsigned n)
647{
648 void *hash = ENCODE_REG_HASH (class, n);
649 const char *retval = hash_insert (reg_names_hash, name, hash);
650
651 if (retval != NULL)
652 as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
653}
654
655static void
656hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
657{
658 unsigned i;
659
660 for (i = 0; i < n; i++)
661 hash_reg_name (class, names[i], i);
662}
663
8f595e9b
NC		 664/* Init hash table csr_extra_hash to handle CSR. */
665static void
666riscv_init_csr_hash (const char *name,
667 unsigned address,
668 enum riscv_csr_class class,
669 enum riscv_priv_spec_class define_version,
670 enum riscv_priv_spec_class abort_version)
671{
672 struct riscv_csr_extra *entry, *pre_entry;
673 const char *hash_error = NULL;
674 bfd_boolean need_enrty = TRUE;
675
676 pre_entry = NULL;
677 entry = (struct riscv_csr_extra *) hash_find (csr_extra_hash, name);
678 while (need_enrty && entry != NULL)
679 {
680 if (entry->csr_class == class
681 && entry->address == address
682 && entry->define_version == define_version
683 && entry->abort_version == abort_version)
684 need_enrty = FALSE;
685 pre_entry = entry;
686 entry = entry->next;
687 }
688
689 /* Duplicate setting for the CSR, just return and do nothing. */
690 if (!need_enrty)
691 return;
bd0cf5a6 692
8f595e9b
NC		 693 entry = XNEW (struct riscv_csr_extra);
694 entry->csr_class = class;
695 entry->address = address;
696 entry->define_version = define_version;
697 entry->abort_version = abort_version;
698
699 /* If the CSR hasn't been inserted in the hash table, then insert it.
700 Otherwise, attach the extra information to the entry which is already
701 in the hash table. */
702 if (pre_entry == NULL)
703 {
704 hash_error = hash_insert (csr_extra_hash, name, (void *) entry);
705 if (hash_error != NULL)
706 {
707 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
708 name, hash_error);
709 /* Probably a memory allocation problem? Give up now. */
710 as_fatal (_("Broken assembler. No assembly attempted."));
711 }
712 }
713 else
714 pre_entry->next = entry;
715}
bd0cf5a6 716
8f595e9b 717/* Check wether the CSR is valid according to the ISA. */
bd0cf5a6
NC		 718
719static void
8f595e9b
NC		 720riscv_csr_class_check (const char *s,
721 enum riscv_csr_class csr_class)
bd0cf5a6 722{
8f595e9b
NC		 723 bfd_boolean result = TRUE;
724
725 /* Don't check the ISA dependency when -mcsr-check isn't set. */
726 if (!riscv_opts.csr_check)
727 return;
bd0cf5a6 728
8f595e9b 729 switch (csr_class)
bd0cf5a6 730 {
8f595e9b
NC		 731 case CSR_CLASS_I:
732 result = riscv_subset_supports ("i");
733 break;
734 case CSR_CLASS_F:
735 result = riscv_subset_supports ("f");
736 break;
737 case CSR_CLASS_I_32:
738 result = (xlen == 32 && riscv_subset_supports ("i"));
739 break;
740 default:
741 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 742 }
743
8f595e9b
NC		 744 if (!result)
745 as_warn (_("Invalid CSR `%s' for the current ISA"), s);
bd0cf5a6
NC		 746}
747
8f595e9b 748/* Check and find the CSR address according to the privilege spec version. */
bd0cf5a6 749
8f595e9b
NC		 750static void
751riscv_csr_version_check (const char *csr_name,
752 struct riscv_csr_extra **entryP)
bd0cf5a6 753{
8f595e9b
NC		 754 struct riscv_csr_extra *entry = *entryP;
755
756 while (entry != NULL)
bd0cf5a6 757 {
8f595e9b
NC		 758 if (default_priv_spec >= entry->define_version
759 && default_priv_spec < entry->abort_version)
760 {
761 /* Find the suitable CSR according to the specific version. */
762 *entryP = entry;
763 return;
764 }
765 entry = entry->next;
766 }
bd0cf5a6 767
8f595e9b
NC		 768 /* We can not find the suitable CSR address according to the privilege
769 version. Therefore, we use the last defined value. Report the warning
770 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
771 otherwise, you may get the unexpected CSR address. */
772 if (riscv_opts.csr_check)
773 {
774 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
775
776 if (priv_name != NULL)
777 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
778 csr_name, priv_name);
bd0cf5a6
NC		 779 }
780}
781
8f595e9b
NC		 782/* Once the CSR is defined, including the old privilege spec, then we call
783 riscv_csr_class_check and riscv_csr_version_check to do the further checking
784 and get the corresponding address. Return -1 if the CSR is never been
785 defined. Otherwise, return the address. */
bd0cf5a6 786
8f595e9b 787static unsigned int
bd0cf5a6
NC		 788reg_csr_lookup_internal (const char *s)
789{
790 struct riscv_csr_extra *r =
791 (struct riscv_csr_extra *) hash_find (csr_extra_hash, s);
792
793 if (r == NULL)
8f595e9b 794 return -1U;
bd0cf5a6 795
8f595e9b
NC		 796 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
797 the CSR was defined, but isn't allowed for the current ISA setting or
798 the privilege spec. If the CSR is never been defined, then assembler
799 will regard it as a "Unknown CSR" and report error. If user use number
800 to set the CSR, but over the range (> 0xfff), then assembler will report
801 "Improper CSR" error for it. */
802 riscv_csr_class_check (s, r->csr_class);
803 riscv_csr_version_check (s, &r);
bd0cf5a6 804
8f595e9b 805 return r->address;
bd0cf5a6
NC		 806}
807
e23eba97
NC		 808static unsigned int
809reg_lookup_internal (const char *s, enum reg_class class)
810{
8f595e9b
NC		 811 void *r;
812
813 if (class == RCLASS_CSR)
814 return reg_csr_lookup_internal (s);
e23eba97 815
8f595e9b 816 r = hash_find (reg_names_hash, s);
e23eba97
NC		 817 if (r == NULL || DECODE_REG_CLASS (r) != class)
818 return -1;
7f999549
JW		 819
820 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
821 return -1;
822
e23eba97
NC		 823 return DECODE_REG_NUM (r);
824}
825
826static bfd_boolean
827reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
828{
829 char *e;
830 char save_c;
831 int reg = -1;
832
833 /* Find end of name. */
834 e = *s;
835 if (is_name_beginner (*e))
836 ++e;
837 while (is_part_of_name (*e))
838 ++e;
839
840 /* Terminate name. */
841 save_c = *e;
842 *e = '\0';
843
844 /* Look for the register. Advance to next token if one was recognized. */
845 if ((reg = reg_lookup_internal (*s, class)) >= 0)
846 *s = e;
847
848 *e = save_c;
849 if (regnop)
850 *regnop = reg;
851 return reg >= 0;
852}
853
854static bfd_boolean
855arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
856{
857 const char *p = strchr (*s, ',');
858 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
859
bfb218e3
JW		 860 if (len == 0)
861 return FALSE;
862
e23eba97
NC		 863 for (i = 0; i < size; i++)
864 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
865 {
866 *regnop = i;
867 *s += len;
868 return TRUE;
869 }
870
871 return FALSE;
872}
873
874/* For consistency checking, verify that all bits are specified either
875 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 876 operand list.
877
878 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 879static bfd_boolean
0e35537d 880validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 881{
882 const char *p = opc->args;
883 char c;
884 insn_t used_bits = opc->mask;
0e35537d
JW		 885 int insn_width;
886 insn_t required_bits;
887
888 if (length == 0)
889 insn_width = 8 * riscv_insn_length (opc->match);
890 else
891 insn_width = 8 * length;
892
893 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 894
895 if ((used_bits & opc->match) != (opc->match & required_bits))
896 {
897 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
898 opc->name, opc->args);
899 return FALSE;
900 }
901
902#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
903 while (*p)
904 switch (c = *p++)
905 {
906 case 'C': /* RVC */
907 switch (c = *p++)
908 {
1d65abb5 909 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 910 case 'c': break; /* RS1, constrained to equal sp */
911 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 912 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 913 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 914 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
915 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
916 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
917 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
918 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 919 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
920 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 921 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
922 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 923 case 'w': break; /* RS1S, constrained to equal RD */
924 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 925 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 926 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
927 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
928 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
929 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 930 case 'U': break; /* RS1, constrained to equal RD */
931 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 932 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
933 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 934 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
935 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 936 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
937 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 938 case 'F': /* funct */
939 switch (c = *p++)
940 {
4765cd61 941 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 942 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
943 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 944 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 945 default:
946 as_bad (_("internal: bad RISC-V opcode"
947 " (unknown operand type `CF%c'): %s %s"),
948 c, opc->name, opc->args);
949 return FALSE;
950 }
951 break;
e23eba97
NC		 952 default:
953 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
954 c, opc->name, opc->args);
955 return FALSE;
956 }
957 break;
958 case ',': break;
959 case '(': break;
960 case ')': break;
961 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
962 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
963 case 'A': break;
964 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
965 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
966 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
967 case 'I': break;
968 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
969 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
970 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
971 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
972 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
973 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
974 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
975 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 976 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 977 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
978 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
979 case 'o':
1d65abb5
AW		 980 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
981 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
982 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
983 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
984 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 985 case 'z': break;
e23eba97
NC		 986 case '[': break;
987 case ']': break;
988 case '0': break;
f50fabe4 989 case '1': break;
0e35537d
JW		 990 case 'F': /* funct */
991 switch (c = *p++)
992 {
993 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
994 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
995 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
996 default:
997 as_bad (_("internal: bad RISC-V opcode"
998 " (unknown operand type `F%c'): %s %s"),
999 c, opc->name, opc->args);
1000 return FALSE;
1001 }
1002 break;
1003 case 'O': /* opcode */
1004 switch (c = *p++)
1005 {
1006 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1007 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1008 default:
1009 as_bad (_("internal: bad RISC-V opcode"
1010 " (unknown operand type `F%c'): %s %s"),
1011 c, opc->name, opc->args);
1012 return FALSE;
1013 }
1014 break;
e23eba97
NC		 1015 default:
1016 as_bad (_("internal: bad RISC-V opcode "
1017 "(unknown operand type `%c'): %s %s"),
1018 c, opc->name, opc->args);
1019 return FALSE;
1020 }
1021#undef USE_BITS
1022 if (used_bits != required_bits)
1023 {
1024 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1025 ~(unsigned long)(used_bits & required_bits),
1026 opc->name, opc->args);
1027 return FALSE;
1028 }
1029 return TRUE;
1030}
1031
1032struct percent_op_match
1033{
1034 const char *str;
1035 bfd_reloc_code_real_type reloc;
1036};
1037
0e35537d
JW		 1038/* Common hash table initialization function for
1039 instruction and .insn directive. */
1040static struct hash_control *
1041init_opcode_hash (const struct riscv_opcode *opcodes,
1042 bfd_boolean insn_directive_p)
e23eba97
NC		 1043{
1044 int i = 0;
0e35537d
JW		 1045 int length;
1046 struct hash_control *hash = hash_new ();
1047 while (opcodes[i].name)
e23eba97 1048 {
0e35537d 1049 const char *name = opcodes[i].name;
e23eba97 1050 const char *hash_error =
0e35537d 1051 hash_insert (hash, name, (void *) &opcodes[i]);
e23eba97 1052
bd0cf5a6 1053 if (hash_error != NULL)
e23eba97
NC		 1054 {
1055 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
0e35537d 1056 opcodes[i].name, hash_error);
e23eba97
NC		 1057 /* Probably a memory allocation problem? Give up now. */
1058 as_fatal (_("Broken assembler. No assembly attempted."));
1059 }
1060
1061 do
1062 {
0e35537d 1063 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1064 {
0e35537d
JW		 1065 if (insn_directive_p)
1066 length = ((name[0] == 'c') ? 2 : 4);
1067 else
1068 length = 0; /* Let assembler determine the length. */
1069 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1070 as_fatal (_("Broken assembler. No assembly attempted."));
1071 }
0e35537d
JW		 1072 else
1073 gas_assert (!insn_directive_p);
e23eba97
NC		 1074 ++i;
1075 }
0e35537d 1076 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1077 }
1078
0e35537d
JW		 1079 return hash;
1080}
1081
1082/* This function is called once, at assembler startup time. It should set up
1083 all the tables, etc. that the MD part of the assembler will need. */
1084
1085void
1086md_begin (void)
1087{
1088 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1089
1090 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1091 as_warn (_("Could not set architecture and machine"));
1092
1093 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1094 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1095
e23eba97
NC		 1096 reg_names_hash = hash_new ();
1097 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1098 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1099 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1100 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1101 /* Add "fp" as an alias for "s0". */
1102 hash_reg_name (RCLASS_GPR, "fp", 8);
1103
bd0cf5a6
NC		 1104 /* Create and insert CSR hash tables. */
1105 csr_extra_hash = hash_new ();
8f595e9b
NC		 1106#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1107 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1108#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1109 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1110#include "opcode/riscv-opc.h"
1111#undef DECLARE_CSR
1112
bd0cf5a6
NC		 1113 opcode_names_hash = hash_new ();
1114 init_opcode_names_hash ();
1115
e23eba97
NC		 1116 /* Set the default alignment for the text section. */
1117 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1118}
1119
45f76423
AW		 1120static insn_t
1121riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1122{
1123 switch (reloc_type)
1124 {
1125 case BFD_RELOC_32:
1126 return value;
1127
1128 case BFD_RELOC_RISCV_HI20:
1129 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1130
1131 case BFD_RELOC_RISCV_LO12_S:
1132 return ENCODE_STYPE_IMM (value);
1133
1134 case BFD_RELOC_RISCV_LO12_I:
1135 return ENCODE_ITYPE_IMM (value);
1136
1137 default:
1138 abort ();
1139 }
1140}
1141
e23eba97
NC		 1142/* Output an instruction. IP is the instruction information.
1143 ADDRESS_EXPR is an operand of the instruction to be used with
1144 RELOC_TYPE. */
1145
1146static void
1147append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1148 bfd_reloc_code_real_type reloc_type)
1149{
1150 dwarf2_emit_insn (0);
1151
1152 if (reloc_type != BFD_RELOC_UNUSED)
1153 {
1154 reloc_howto_type *howto;
1155
1d65abb5 1156 gas_assert (address_expr);
e23eba97
NC		 1157 if (reloc_type == BFD_RELOC_12_PCREL
1158 || reloc_type == BFD_RELOC_RISCV_JMP)
1159 {
1160 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1161 int best_case = riscv_insn_length (ip->insn_opcode);
1162 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
1163 add_relaxed_insn (ip, worst_case, best_case,
1164 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1165 address_expr->X_add_symbol,
1166 address_expr->X_add_number);
1167 return;
1168 }
45f76423 1169 else
e23eba97 1170 {
45f76423
AW		 1171 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1172 if (howto == NULL)
1173 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1174
45f76423
AW		 1175 ip->fixp = fix_new_exp (ip->frag, ip->where,
1176 bfd_get_reloc_size (howto),
1177 address_expr, FALSE, reloc_type);
e23eba97 1178
45f76423 1179 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1180 }
e23eba97
NC		 1181 }
1182
e23eba97
NC		 1183 add_fixed_insn (ip);
1184 install_insn (ip);
f77bb6c5
JW		 1185
1186 /* We need to start a new frag after any instruction that can be
1187 optimized away or compressed by the linker during relaxation, to prevent
1188 the assembler from computing static offsets across such an instruction.
1189 This is necessary to get correct EH info. */
1190 if (reloc_type == BFD_RELOC_RISCV_CALL
1191 || reloc_type == BFD_RELOC_RISCV_CALL_PLT
1192 || reloc_type == BFD_RELOC_RISCV_HI20
1193 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1194 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1195 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1196 {
1197 frag_wane (frag_now);
1198 frag_new (0);
1199 }
e23eba97
NC		 1200}
1201
1202/* Build an instruction created by a macro expansion. This is passed
1203 a pointer to the count of instructions created so far, an
1204 expression, the name of the instruction to build, an operand format
1205 string, and corresponding arguments. */
1206
1207static void
1208macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1209{
1210 const struct riscv_opcode *mo;
1211 struct riscv_cl_insn insn;
1212 bfd_reloc_code_real_type r;
1213 va_list args;
1214
1215 va_start (args, fmt);
1216
1217 r = BFD_RELOC_UNUSED;
1218 mo = (struct riscv_opcode *) hash_find (op_hash, name);
1219 gas_assert (mo);
1220
1221 /* Find a non-RVC variant of the instruction. append_insn will compress
1222 it if possible. */
1223 while (riscv_insn_length (mo->match) < 4)
1224 mo++;
1225 gas_assert (strcmp (name, mo->name) == 0);
1226
1227 create_insn (&insn, mo);
1228 for (;;)
1229 {
1230 switch (*fmt++)
1231 {
1232 case 'd':
1233 INSERT_OPERAND (RD, insn, va_arg (args, int));
1234 continue;
1235
1236 case 's':
1237 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1238 continue;
1239
1240 case 't':
1241 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1242 continue;
1243
1244 case '>':
1245 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1246 continue;
1247
1248 case 'j':
1249 case 'u':
1250 case 'q':
1251 gas_assert (ep != NULL);
1252 r = va_arg (args, int);
1253 continue;
1254
1255 case '\0':
1256 break;
1257 case ',':
1258 continue;
1259 default:
1260 as_fatal (_("internal error: invalid macro"));
1261 }
1262 break;
1263 }
1264 va_end (args);
1265 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1266
1267 append_insn (&insn, ep, r);
1268}
1269
db3b6ecc
KC		 1270/* Build an instruction created by a macro expansion. Like md_assemble but
1271 accept a printf-style format string and arguments. */
1272
1273static void
1274md_assemblef (const char *format, ...)
1275{
1276 char *buf = NULL;
1277 va_list ap;
1278 int r;
1279
1280 va_start (ap, format);
1281
1282 r = vasprintf (&buf, format, ap);
1283
1284 if (r < 0)
1285 as_fatal (_("internal error: vasprintf failed"));
1286
1287 md_assemble (buf);
1288 free(buf);
1289
1290 va_end (ap);
1291}
1292
e23eba97
NC		 1293/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1294 unset. */
1295static void
1296normalize_constant_expr (expressionS *ex)
1297{
1298 if (xlen > 32)
1299 return;
1300 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1301 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1302 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1303 - 0x80000000);
1304}
1305
ca2fd32c
JW		 1306/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1307 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1308
1309static void
ca2fd32c
JW		 1310check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1311 bfd_boolean maybe_csr)
e23eba97
NC		 1312{
1313 if (ex->X_op == O_big)
1314 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1315 else if (maybe_csr && ex->X_op == O_symbol)
1316 as_bad (_("unknown CSR `%s'"),
1317 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1318 else if (ex->X_op != O_constant)
1319 as_bad (_("Instruction %s requires absolute expression"),
1320 ip->insn_mo->name);
1321 normalize_constant_expr (ex);
1322}
1323
1324static symbolS *
1325make_internal_label (void)
1326{
1327 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
1d65abb5 1328 (valueT) frag_now_fix (), frag_now);
e23eba97
NC		 1329}
1330
1331/* Load an entry from the GOT. */
1332static void
1333pcrel_access (int destreg, int tempreg, expressionS *ep,
1334 const char *lo_insn, const char *lo_pattern,
1335 bfd_reloc_code_real_type hi_reloc,
1336 bfd_reloc_code_real_type lo_reloc)
1337{
1338 expressionS ep2;
1339 ep2.X_op = O_symbol;
1340 ep2.X_add_symbol = make_internal_label ();
1341 ep2.X_add_number = 0;
1342
1343 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1344 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1345}
1346
1347static void
1348pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1349 bfd_reloc_code_real_type hi_reloc,
1350 bfd_reloc_code_real_type lo_reloc)
1351{
1352 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1353}
1354
1355static void
1356pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1357 bfd_reloc_code_real_type hi_reloc,
1358 bfd_reloc_code_real_type lo_reloc)
1359{
1360 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1361}
1362
1363/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1364static void
1365riscv_call (int destreg, int tempreg, expressionS *ep,
1366 bfd_reloc_code_real_type reloc)
1367{
1368 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1369 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
1370}
1371
1372/* Load an integer constant into a register. */
1373
1374static void
1375load_const (int reg, expressionS *ep)
1376{
1377 int shift = RISCV_IMM_BITS;
4f7cc141 1378 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1379 expressionS upper = *ep, lower = *ep;
4f7cc141 1380 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1381 upper.X_add_number -= lower.X_add_number;
1382
1383 if (ep->X_op != O_constant)
1384 {
1385 as_bad (_("unsupported large constant"));
1386 return;
1387 }
1388
1d65abb5 1389 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1390 {
1391 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1392 while (((upper.X_add_number >> shift) & 1) == 0)
1393 shift++;
1394
1395 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1396 load_const (reg, &upper);
e23eba97 1397
db3b6ecc 1398 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1399 if (lower.X_add_number != 0)
db3b6ecc
KC		 1400 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1401 lower.X_add_number);
e23eba97
NC		 1402 }
1403 else
1404 {
1405 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1406 int hi_reg = 0;
1407
1408 if (upper.X_add_number != 0)
1409 {
db3b6ecc
KC		 1410 /* Discard low part and zero-extend upper immediate. */
1411 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1412
1413 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1414 hi_reg = reg;
1415 }
1416
1417 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1418 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1419 lower.X_add_number);
e23eba97
NC		 1420 }
1421}
1422
1423/* Expand RISC-V assembly macros into one or more instructions. */
1424static void
1425macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1426 bfd_reloc_code_real_type *imm_reloc)
1427{
1428 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1429 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1430 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1431 int mask = ip->insn_mo->mask;
1432
1433 switch (mask)
1434 {
1435 case M_LI:
1436 load_const (rd, imm_expr);
1437 break;
1438
1439 case M_LA:
1440 case M_LLA:
1441 /* Load the address of a symbol into a register. */
1442 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1443 as_bad (_("offset too large"));
1444
1445 if (imm_expr->X_op == O_constant)
1446 load_const (rd, imm_expr);
1447 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1448 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1449 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1450 else /* Local PIC symbol, or any non-PIC symbol */
1451 pcrel_load (rd, rd, imm_expr, "addi",
1452 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1453 break;
1454
1455 case M_LA_TLS_GD:
1456 pcrel_load (rd, rd, imm_expr, "addi",
1457 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1458 break;
1459
1460 case M_LA_TLS_IE:
1461 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1462 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1463 break;
1464
1465 case M_LB:
1466 pcrel_load (rd, rd, imm_expr, "lb",
1467 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1468 break;
1469
1470 case M_LBU:
1471 pcrel_load (rd, rd, imm_expr, "lbu",
1472 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1473 break;
1474
1475 case M_LH:
1476 pcrel_load (rd, rd, imm_expr, "lh",
1477 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1478 break;
1479
1480 case M_LHU:
1481 pcrel_load (rd, rd, imm_expr, "lhu",
1482 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1483 break;
1484
1485 case M_LW:
1486 pcrel_load (rd, rd, imm_expr, "lw",
1487 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1488 break;
1489
1490 case M_LWU:
1491 pcrel_load (rd, rd, imm_expr, "lwu",
1492 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1493 break;
1494
1495 case M_LD:
1496 pcrel_load (rd, rd, imm_expr, "ld",
1497 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1498 break;
1499
1500 case M_FLW:
1501 pcrel_load (rd, rs1, imm_expr, "flw",
1502 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1503 break;
1504
1505 case M_FLD:
1506 pcrel_load (rd, rs1, imm_expr, "fld",
1507 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1508 break;
1509
1510 case M_SB:
1511 pcrel_store (rs2, rs1, imm_expr, "sb",
1512 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1513 break;
1514
1515 case M_SH:
1516 pcrel_store (rs2, rs1, imm_expr, "sh",
1517 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1518 break;
1519
1520 case M_SW:
1521 pcrel_store (rs2, rs1, imm_expr, "sw",
1522 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1523 break;
1524
1525 case M_SD:
1526 pcrel_store (rs2, rs1, imm_expr, "sd",
1527 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1528 break;
1529
1530 case M_FSW:
1531 pcrel_store (rs2, rs1, imm_expr, "fsw",
1532 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1533 break;
1534
1535 case M_FSD:
1536 pcrel_store (rs2, rs1, imm_expr, "fsd",
1537 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1538 break;
1539
1540 case M_CALL:
1541 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1542 break;
1543
1544 default:
1545 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1546 break;
1547 }
1548}
1549
1550static const struct percent_op_match percent_op_utype[] =
1551{
1552 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1553 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1554 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1555 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1556 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1557 {"%hi", BFD_RELOC_RISCV_HI20},
1558 {0, 0}
1559};
1560
1561static const struct percent_op_match percent_op_itype[] =
1562{
1563 {"%lo", BFD_RELOC_RISCV_LO12_I},
1564 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1565 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1566 {0, 0}
1567};
1568
1569static const struct percent_op_match percent_op_stype[] =
1570{
1571 {"%lo", BFD_RELOC_RISCV_LO12_S},
1572 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1573 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1574 {0, 0}
1575};
1576
1577static const struct percent_op_match percent_op_rtype[] =
1578{
1579 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1580 {0, 0}
1581};
1582
f50fabe4
JW		 1583static const struct percent_op_match percent_op_null[] =
1584{
1585 {0, 0}
1586};
1587
e23eba97
NC		 1588/* Return true if *STR points to a relocation operator. When returning true,
1589 move *STR over the operator and store its relocation code in *RELOC.
1590 Leave both *STR and *RELOC alone when returning false. */
1591
1592static bfd_boolean
1593parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1594 const struct percent_op_match *percent_op)
1595{
1596 for ( ; percent_op->str; percent_op++)
1597 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1598 {
1599 int len = strlen (percent_op->str);
1600
1601 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1602 continue;
1603
1604 *str += strlen (percent_op->str);
1605 *reloc = percent_op->reloc;
1606
1607 /* Check whether the output BFD supports this relocation.
1608 If not, issue an error and fall back on something safe. */
45f76423
AW		 1609 if (*reloc != BFD_RELOC_UNUSED
1610 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1611 {
1612 as_bad ("relocation %s isn't supported by the current ABI",
1613 percent_op->str);
1614 *reloc = BFD_RELOC_UNUSED;
1615 }
1616 return TRUE;
1617 }
1618 return FALSE;
1619}
1620
1621static void
1622my_getExpression (expressionS *ep, char *str)
1623{
1624 char *save_in;
1625
1626 save_in = input_line_pointer;
1627 input_line_pointer = str;
1628 expression (ep);
1629 expr_end = input_line_pointer;
1630 input_line_pointer = save_in;
1631}
1632
1633/* Parse string STR as a 16-bit relocatable operand. Store the
1634 expression in *EP and the relocation, if any, in RELOC.
1635 Return the number of relocation operators used (0 or 1).
1636
1637 On exit, EXPR_END points to the first character after the expression. */
1638
1639static size_t
1640my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1641 char *str, const struct percent_op_match *percent_op)
1642{
1643 size_t reloc_index;
1644 unsigned crux_depth, str_depth, regno;
1645 char *crux;
1646
8970c022
JW		 1647 /* First, check for integer registers. No callers can accept a reg, but
1648 we need to avoid accidentally creating a useless undefined symbol below,
1649 if this is an instruction pattern that can't match. A glibc build fails
1650 if this is removed. */
e23eba97
NC		 1651 if (reg_lookup (&str, RCLASS_GPR, &regno))
1652 {
1653 ep->X_op = O_register;
1654 ep->X_add_number = regno;
8970c022 1655 expr_end = str;
e23eba97
NC		 1656 return 0;
1657 }
1658
1659 /* Search for the start of the main expression.
1660 End the loop with CRUX pointing to the start
1661 of the main expression and with CRUX_DEPTH containing the number
1662 of open brackets at that point. */
1663 reloc_index = -1;
1664 str_depth = 0;
1665 do
1666 {
1667 reloc_index++;
1668 crux = str;
1669 crux_depth = str_depth;
1670
1671 /* Skip over whitespace and brackets, keeping count of the number
1672 of brackets. */
1673 while (*str == ' ' || *str == '\t' || *str == '(')
1674 if (*str++ == '(')
1675 str_depth++;
1676 }
1677 while (*str == '%'
1678 && reloc_index < 1
1679 && parse_relocation (&str, reloc, percent_op));
1680
1681 my_getExpression (ep, crux);
1682 str = expr_end;
1683
1684 /* Match every open bracket. */
1685 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1686 if (*str++ == ')')
1687 crux_depth--;
1688
1689 if (crux_depth > 0)
1690 as_bad ("unclosed '('");
1691
1692 expr_end = str;
1693
1694 return reloc_index;
1695}
1696
0e35537d
JW		 1697/* Parse opcode name, could be an mnemonics or number. */
1698static size_t
1699my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1700 char *str, const struct percent_op_match *percent_op)
1701{
1702 const struct opcode_name_t *o = opcode_name_lookup (&str);
1703
1704 if (o != NULL)
1705 {
1706 ep->X_op = O_constant;
1707 ep->X_add_number = o->val;
1708 return 0;
1709 }
1710
1711 return my_getSmallExpression (ep, reloc, str, percent_op);
1712}
1713
f0531ed6
JW		 1714/* Detect and handle implicitly zero load-store offsets. For example,
1715 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1716 an implicit offset was detected. */
1717
1718static bfd_boolean
89424b1d 1719riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1720{
1721 /* Check whether there is only a single bracketed expression left.
1722 If so, it must be the base register and the constant must be zero. */
1723 if (*s == '(' && strchr (s + 1, '(') == 0)
1724 {
89424b1d
MR		 1725 ep->X_op = O_constant;
1726 ep->X_add_number = 0;
f0531ed6
JW		 1727 return TRUE;
1728 }
1729
1730 return FALSE;
1731}
1732
54b2aec1
NC		 1733/* All RISC-V CSR instructions belong to one of these classes. */
1734
1735enum csr_insn_type
1736{
1737 INSN_NOT_CSR,
1738 INSN_CSRRW,
1739 INSN_CSRRS,
1740 INSN_CSRRC
1741};
1742
1743/* Return which CSR instruction is checking. */
1744
1745static enum csr_insn_type
1746riscv_csr_insn_type (insn_t insn)
1747{
1748 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1749 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1750 return INSN_CSRRW;
1751 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1752 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1753 return INSN_CSRRS;
1754 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1755 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1756 return INSN_CSRRC;
1757 else
1758 return INSN_NOT_CSR;
1759}
1760
1761/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1762 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1763 CSR address is 0x3. */
1764
1765static bfd_boolean
1766riscv_csr_read_only_check (insn_t insn)
1767{
1768 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1769 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1770 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1771 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1772
1773 if (readonly
1774 && (((csr_insn == INSN_CSRRS
1775 || csr_insn == INSN_CSRRC)
1776 && rs1 != 0)
1777 || csr_insn == INSN_CSRRW))
1778 return FALSE;
1779
1780 return TRUE;
1781}
1782
e23eba97
NC		 1783/* This routine assembles an instruction into its binary format. As a
1784 side effect, it sets the global variable imm_reloc to the type of
1785 relocation to do if one of the operands is an address expression. */
1786
1787static const char *
1788riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
0e35537d 1789 bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash)
e23eba97
NC		 1790{
1791 char *s;
1792 const char *args;
1793 char c = 0;
1794 struct riscv_opcode *insn;
1795 char *argsStart;
1796 unsigned int regno;
1797 char save_c = 0;
1798 int argnum;
1799 const struct percent_op_match *p;
1800 const char *error = "unrecognized opcode";
54b2aec1
NC		 1801 /* Indicate we are assembling instruction with CSR. */
1802 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1803
1804 /* Parse the name of the instruction. Terminate the string if whitespace
1805 is found so that hash_find only sees the name part of the string. */
1806 for (s = str; *s != '\0'; ++s)
1807 if (ISSPACE (*s))
1808 {
1809 save_c = *s;
1810 *s++ = '\0';
1811 break;
1812 }
1813
0e35537d 1814 insn = (struct riscv_opcode *) hash_find (hash, str);
e23eba97
NC		 1815
1816 argsStart = s;
1817 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1818 {
1080bf78
JW		 1819 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1820 continue;
1821
7e9ad3a3 1822 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1823 continue;
1824
1825 create_insn (ip, insn);
1826 argnum = 1;
1827
1828 imm_expr->X_op = O_absent;
1829 *imm_reloc = BFD_RELOC_UNUSED;
1830 p = percent_op_itype;
1831
1832 for (args = insn->args;; ++args)
1833 {
1834 s += strspn (s, " \t");
1835 switch (*args)
1836 {
1837 case '\0': /* End of args. */
1838 if (insn->pinfo != INSN_MACRO)
1839 {
1840 if (!insn->match_func (insn, ip->insn_opcode))
1841 break;
0e35537d
JW		 1842
1843 /* For .insn, insn->match and insn->mask are 0. */
1844 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1845 ? ip->insn_opcode
1846 : insn->match) == 2
1847 && !riscv_opts.rvc)
e23eba97 1848 break;
54b2aec1
NC		 1849
1850 /* Check if we write a read-only CSR by the CSR
1851 instruction. */
1852 if (insn_with_csr
1853 && riscv_opts.csr_check
1854 && !riscv_csr_read_only_check (ip->insn_opcode))
1855 {
1856 /* Restore the character in advance, since we want to
1857 report the detailed warning message here. */
1858 if (save_c)
1859 *(argsStart - 1) = save_c;
1860 as_warn (_("Read-only CSR is written `%s'"), str);
1861 insn_with_csr = FALSE;
1862 }
e23eba97
NC		 1863 }
1864 if (*s != '\0')
1865 break;
1866 /* Successful assembly. */
1867 error = NULL;
54b2aec1 1868 insn_with_csr = FALSE;
e23eba97
NC		 1869 goto out;
1870
1871 case 'C': /* RVC */
1872 switch (*++args)
1873 {
1874 case 's': /* RS1 x8-x15 */
1875 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1876 || !(regno >= 8 && regno <= 15))
1877 break;
1878 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1879 continue;
1880 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1881 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1882 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1883 break;
1884 continue;
1885 case 't': /* RS2 x8-x15 */
1886 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1887 || !(regno >= 8 && regno <= 15))
1888 break;
1889 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1890 continue;
1891 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1892 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1893 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1894 break;
1895 continue;
1896 case 'U': /* RS1, constrained to equal RD. */
1897 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1898 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1899 break;
1900 continue;
1901 case 'V': /* RS2 */
1902 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1903 break;
1904 INSERT_OPERAND (CRS2, *ip, regno);
1905 continue;
1906 case 'c': /* RS1, constrained to equal sp. */
1907 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1908 || regno != X_SP)
1909 break;
1910 continue;
ca0bc150
JW		 1911 case 'z': /* RS2, contrained to equal x0. */
1912 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1913 || regno != 0)
1914 break;
1915 continue;
e23eba97
NC		 1916 case '>':
1917 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1918 || imm_expr->X_op != O_constant
1919 || imm_expr->X_add_number <= 0
1920 || imm_expr->X_add_number >= 64)
1921 break;
1922 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 1923 rvc_imm_done:
e23eba97
NC		 1924 s = expr_end;
1925 imm_expr->X_op = O_absent;
1926 continue;
1927 case '<':
1928 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1929 || imm_expr->X_op != O_constant
1930 || !VALID_RVC_IMM (imm_expr->X_add_number)
1931 || imm_expr->X_add_number <= 0
1932 || imm_expr->X_add_number >= 32)
1933 break;
1934 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1935 goto rvc_imm_done;
0e35537d
JW		 1936 case '8':
1937 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1938 || imm_expr->X_op != O_constant
1939 || !VALID_RVC_UIMM8 (imm_expr->X_add_number)
1940 || imm_expr->X_add_number < 0
1941 || imm_expr->X_add_number >= 256)
1942 break;
1943 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1944 goto rvc_imm_done;
e23eba97
NC		 1945 case 'i':
1946 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1947 || imm_expr->X_op != O_constant
1948 || imm_expr->X_add_number == 0
1949 || !VALID_RVC_SIMM3 (imm_expr->X_add_number))
1950 break;
1951 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1952 goto rvc_imm_done;
1953 case 'j':
1954 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1955 || imm_expr->X_op != O_constant
1956 || imm_expr->X_add_number == 0
1957 || !VALID_RVC_IMM (imm_expr->X_add_number))
1958 break;
1959 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1960 goto rvc_imm_done;
1961 case 'k':
f0531ed6
JW		 1962 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1963 continue;
e23eba97
NC		 1964 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1965 || imm_expr->X_op != O_constant
1966 || !VALID_RVC_LW_IMM (imm_expr->X_add_number))
1967 break;
1968 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
1969 goto rvc_imm_done;
1970 case 'l':
f0531ed6
JW		 1971 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1972 continue;
e23eba97
NC		 1973 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1974 || imm_expr->X_op != O_constant
1975 || !VALID_RVC_LD_IMM (imm_expr->X_add_number))
1976 break;
1977 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
1978 goto rvc_imm_done;
1979 case 'm':
f0531ed6
JW		 1980 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1981 continue;
e23eba97
NC		 1982 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1983 || imm_expr->X_op != O_constant
1984 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
1985 break;
1986 ip->insn_opcode |=
1987 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
1988 goto rvc_imm_done;
1989 case 'n':
f0531ed6
JW		 1990 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1991 continue;
e23eba97
NC		 1992 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1993 || imm_expr->X_op != O_constant
1994 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
1995 break;
1996 ip->insn_opcode |=
1997 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
1998 goto rvc_imm_done;
b416fe87
KC		 1999 case 'o':
2000 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2001 || imm_expr->X_op != O_constant
21a186f2
JW		 2002 /* C.addiw, c.li, and c.andi allow zero immediate.
2003 C.addi allows zero immediate as hint. Otherwise this
2004 is same as 'j'. */
b416fe87
KC		 2005 || !VALID_RVC_IMM (imm_expr->X_add_number))
2006 break;
2007 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2008 goto rvc_imm_done;
e23eba97
NC		 2009 case 'K':
2010 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2011 || imm_expr->X_op != O_constant
2012 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
2013 || imm_expr->X_add_number == 0)
2014 break;
2015 ip->insn_opcode |=
2016 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
2017 goto rvc_imm_done;
2018 case 'L':
2019 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2020 || imm_expr->X_op != O_constant
2021 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
2022 || imm_expr->X_add_number == 0)
2023 break;
2024 ip->insn_opcode |=
2025 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2026 goto rvc_imm_done;
2027 case 'M':
f0531ed6
JW		 2028 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2029 continue;
e23eba97
NC		 2030 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2031 || imm_expr->X_op != O_constant
2032 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
2033 break;
2034 ip->insn_opcode |=
2035 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2036 goto rvc_imm_done;
2037 case 'N':
f0531ed6
JW		 2038 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2039 continue;
e23eba97
NC		 2040 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2041 || imm_expr->X_op != O_constant
2042 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
2043 break;
2044 ip->insn_opcode |=
2045 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2046 goto rvc_imm_done;
2047 case 'u':
2048 p = percent_op_utype;
2049 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2050 break;
dc1e8a47 2051 rvc_lui:
e23eba97
NC		 2052 if (imm_expr->X_op != O_constant
2053 || imm_expr->X_add_number <= 0
2054 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2055 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2056 && (imm_expr->X_add_number <
2057 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2058 break;
2059 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2060 goto rvc_imm_done;
2061 case 'v':
2062 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2063 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2064 || ((int32_t)imm_expr->X_add_number
2065 != imm_expr->X_add_number))
2066 break;
2067 imm_expr->X_add_number =
2068 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2069 goto rvc_lui;
2070 case 'p':
2071 goto branch;
2072 case 'a':
2073 goto jump;
0e35537d
JW		 2074 case 'S': /* Floating-point RS1 x8-x15. */
2075 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2076 || !(regno >= 8 && regno <= 15))
2077 break;
2078 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2079 continue;
e23eba97
NC		 2080 case 'D': /* Floating-point RS2 x8-x15. */
2081 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2082 || !(regno >= 8 && regno <= 15))
2083 break;
2084 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2085 continue;
2086 case 'T': /* Floating-point RS2. */
2087 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2088 break;
2089 INSERT_OPERAND (CRS2, *ip, regno);
2090 continue;
0e35537d
JW		 2091 case 'F':
2092 switch (*++args)
2093 {
4765cd61
JW		 2094 case '6':
2095 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2096 || imm_expr->X_op != O_constant
2097 || imm_expr->X_add_number < 0
2098 || imm_expr->X_add_number >= 64)
2099 {
2100 as_bad (_("bad value for funct6 field, "
2101 "value must be 0...64"));
2102 break;
2103 }
2104
2105 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2106 imm_expr->X_op = O_absent;
2107 s = expr_end;
2108 continue;
0e35537d
JW		 2109 case '4':
2110 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2111 || imm_expr->X_op != O_constant
2112 || imm_expr->X_add_number < 0
2113 || imm_expr->X_add_number >= 16)
2114 {
2115 as_bad (_("bad value for funct4 field, "
2116 "value must be 0...15"));
2117 break;
2118 }
2119
2120 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2121 imm_expr->X_op = O_absent;
2122 s = expr_end;
2123 continue;
2124 case '3':
2125 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2126 || imm_expr->X_op != O_constant
2127 || imm_expr->X_add_number < 0
2128 || imm_expr->X_add_number >= 8)
2129 {
2130 as_bad (_("bad value for funct3 field, "
2131 "value must be 0...7"));
2132 break;
2133 }
2134 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2135 imm_expr->X_op = O_absent;
2136 s = expr_end;
2137 continue;
4765cd61
JW		 2138 case '2':
2139 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2140 || imm_expr->X_op != O_constant
2141 || imm_expr->X_add_number < 0
2142 || imm_expr->X_add_number >= 4)
2143 {
2144 as_bad (_("bad value for funct2 field, "
2145 "value must be 0...3"));
2146 break;
2147 }
2148 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2149 imm_expr->X_op = O_absent;
2150 s = expr_end;
2151 continue;
0e35537d
JW		 2152 default:
2153 as_bad (_("bad compressed FUNCT field"
2154 " specifier 'CF%c'\n"),
2155 *args);
2156 }
2157 break;
2158
e23eba97
NC		 2159 default:
2160 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2161 }
2162 break;
2163
2164 case ',':
2165 ++argnum;
2166 if (*s++ == *args)
2167 continue;
2168 s--;
2169 break;
2170
2171 case '(':
2172 case ')':
2173 case '[':
2174 case ']':
2175 if (*s++ == *args)
2176 continue;
2177 break;
2178
2179 case '<': /* Shift amount, 0 - 31. */
2180 my_getExpression (imm_expr, s);
ca2fd32c 2181 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2182 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2183 as_bad (_("Improper shift amount (%lu)"),
2184 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2185 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2186 imm_expr->X_op = O_absent;
2187 s = expr_end;
2188 continue;
2189
2190 case '>': /* Shift amount, 0 - (XLEN-1). */
2191 my_getExpression (imm_expr, s);
ca2fd32c 2192 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2193 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2194 as_bad (_("Improper shift amount (%lu)"),
2195 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2196 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2197 imm_expr->X_op = O_absent;
2198 s = expr_end;
2199 continue;
2200
2201 case 'Z': /* CSRRxI immediate. */
2202 my_getExpression (imm_expr, s);
ca2fd32c 2203 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2204 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2205 as_bad (_("Improper CSRxI immediate (%lu)"),
2206 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2207 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2208 imm_expr->X_op = O_absent;
2209 s = expr_end;
2210 continue;
2211
2212 case 'E': /* Control register. */
54b2aec1 2213 insn_with_csr = TRUE;
e23eba97
NC		 2214 if (reg_lookup (&s, RCLASS_CSR, &regno))
2215 INSERT_OPERAND (CSR, *ip, regno);
2216 else
2217 {
2218 my_getExpression (imm_expr, s);
ca2fd32c 2219 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2220 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2221 as_bad (_("Improper CSR address (%lu)"),
2222 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2223 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2224 imm_expr->X_op = O_absent;
2225 s = expr_end;
2226 }
2227 continue;
2228
2229 case 'm': /* Rounding mode. */
2230 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2231 {
2232 INSERT_OPERAND (RM, *ip, regno);
2233 continue;
2234 }
2235 break;
2236
2237 case 'P':
2238 case 'Q': /* Fence predecessor/successor. */
2239 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2240 &regno))
2241 {
2242 if (*args == 'P')
2243 INSERT_OPERAND (PRED, *ip, regno);
2244 else
2245 INSERT_OPERAND (SUCC, *ip, regno);
2246 continue;
2247 }
2248 break;
2249
2250 case 'd': /* Destination register. */
2251 case 's': /* Source register. */
2252 case 't': /* Target register. */
0e35537d 2253 case 'r': /* rs3. */
e23eba97
NC		 2254 if (reg_lookup (&s, RCLASS_GPR, &regno))
2255 {
2256 c = *args;
2257 if (*s == ' ')
2258 ++s;
2259
2260 /* Now that we have assembled one operand, we use the args
2261 string to figure out where it goes in the instruction. */
2262 switch (c)
2263 {
2264 case 's':
2265 INSERT_OPERAND (RS1, *ip, regno);
2266 break;
2267 case 'd':
2268 INSERT_OPERAND (RD, *ip, regno);
2269 break;
2270 case 't':
2271 INSERT_OPERAND (RS2, *ip, regno);
2272 break;
0e35537d
JW		 2273 case 'r':
2274 INSERT_OPERAND (RS3, *ip, regno);
2275 break;
e23eba97
NC		 2276 }
2277 continue;
2278 }
2279 break;
2280
2281 case 'D': /* Floating point rd. */
2282 case 'S': /* Floating point rs1. */
2283 case 'T': /* Floating point rs2. */
2284 case 'U': /* Floating point rs1 and rs2. */
2285 case 'R': /* Floating point rs3. */
2286 if (reg_lookup (&s, RCLASS_FPR, &regno))
2287 {
2288 c = *args;
2289 if (*s == ' ')
2290 ++s;
2291 switch (c)
2292 {
2293 case 'D':
2294 INSERT_OPERAND (RD, *ip, regno);
2295 break;
2296 case 'S':
2297 INSERT_OPERAND (RS1, *ip, regno);
2298 break;
2299 case 'U':
2300 INSERT_OPERAND (RS1, *ip, regno);
2301 /* fallthru */
2302 case 'T':
2303 INSERT_OPERAND (RS2, *ip, regno);
2304 break;
2305 case 'R':
2306 INSERT_OPERAND (RS3, *ip, regno);
2307 break;
2308 }
2309 continue;
2310 }
2311
2312 break;
2313
2314 case 'I':
2315 my_getExpression (imm_expr, s);
2316 if (imm_expr->X_op != O_big
2317 && imm_expr->X_op != O_constant)
2318 break;
2319 normalize_constant_expr (imm_expr);
2320 s = expr_end;
2321 continue;
2322
2323 case 'A':
2324 my_getExpression (imm_expr, s);
2325 normalize_constant_expr (imm_expr);
2326 /* The 'A' format specifier must be a symbol. */
2327 if (imm_expr->X_op != O_symbol)
2328 break;
2329 *imm_reloc = BFD_RELOC_32;
2330 s = expr_end;
2331 continue;
2332
160d1b3d
SH		 2333 case 'B':
2334 my_getExpression (imm_expr, s);
2335 normalize_constant_expr (imm_expr);
2336 /* The 'B' format specifier must be a symbol or a constant. */
2337 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2338 break;
2339 if (imm_expr->X_op == O_symbol)
2340 *imm_reloc = BFD_RELOC_32;
2341 s = expr_end;
2342 continue;
2343
e23eba97 2344 case 'j': /* Sign-extended immediate. */
e23eba97 2345 p = percent_op_itype;
f50fabe4 2346 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2347 goto alu_op;
2348 case 'q': /* Store displacement. */
2349 p = percent_op_stype;
2350 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2351 goto load_store;
2352 case 'o': /* Load displacement. */
2353 p = percent_op_itype;
2354 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2355 goto load_store;
f50fabe4 2356 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2357 p = percent_op_rtype;
f50fabe4
JW		 2358 goto alu_op;
2359 case '0': /* AMO "displacement," which must be zero. */
2360 p = percent_op_null;
dc1e8a47 2361 load_store:
f0531ed6 2362 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2363 continue;
dc1e8a47 2364 alu_op:
e23eba97
NC		 2365 /* If this value won't fit into a 16 bit offset, then go
2366 find a macro that will generate the 32 bit offset
2367 code pattern. */
2368 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2369 {
2370 normalize_constant_expr (imm_expr);
2371 if (imm_expr->X_op != O_constant
2372 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2373 || (*args == '1')
e23eba97
NC		 2374 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2375 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2376 break;
2377 }
2378
2379 s = expr_end;
2380 continue;
2381
2382 case 'p': /* PC-relative offset. */
dc1e8a47 2383 branch:
e23eba97
NC		 2384 *imm_reloc = BFD_RELOC_12_PCREL;
2385 my_getExpression (imm_expr, s);
2386 s = expr_end;
2387 continue;
2388
2389 case 'u': /* Upper 20 bits. */
2390 p = percent_op_utype;
4288405d 2391 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2392 {
4288405d
JW		 2393 if (imm_expr->X_op != O_constant)
2394 break;
2395
e23eba97
NC		 2396 if (imm_expr->X_add_number < 0
2397 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2398 as_bad (_("lui expression not in range 0..1048575"));
2399
2400 *imm_reloc = BFD_RELOC_RISCV_HI20;
2401 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2402 }
2403 s = expr_end;
2404 continue;
2405
2406 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2407 jump:
e23eba97
NC		 2408 my_getExpression (imm_expr, s);
2409 s = expr_end;
2410 *imm_reloc = BFD_RELOC_RISCV_JMP;
2411 continue;
2412
2413 case 'c':
2414 my_getExpression (imm_expr, s);
2415 s = expr_end;
2416 if (strcmp (s, "@plt") == 0)
2417 {
2418 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2419 s += 4;
2420 }
2421 else
2422 *imm_reloc = BFD_RELOC_RISCV_CALL;
2423 continue;
0e35537d
JW		 2424 case 'O':
2425 switch (*++args)
2426 {
2427 case '4':
2428 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2429 || imm_expr->X_op != O_constant
2430 || imm_expr->X_add_number < 0
2431 || imm_expr->X_add_number >= 128
2432 || (imm_expr->X_add_number & 0x3) != 3)
2433 {
2434 as_bad (_("bad value for opcode field, "
2435 "value must be 0...127 and "
2436 "lower 2 bits must be 0x3"));
2437 break;
2438 }
2439
2440 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2441 imm_expr->X_op = O_absent;
2442 s = expr_end;
2443 continue;
2444 case '2':
2445 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2446 || imm_expr->X_op != O_constant
2447 || imm_expr->X_add_number < 0
2448 || imm_expr->X_add_number >= 3)
2449 {
2450 as_bad (_("bad value for opcode field, "
2451 "value must be 0...2"));
2452 break;
2453 }
2454
2455 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2456 imm_expr->X_op = O_absent;
2457 s = expr_end;
2458 continue;
2459 default:
2460 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2461 }
2462 break;
2463
2464 case 'F':
2465 switch (*++args)
2466 {
2467 case '7':
2468 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2469 || imm_expr->X_op != O_constant
2470 || imm_expr->X_add_number < 0
2471 || imm_expr->X_add_number >= 128)
2472 {
2473 as_bad (_("bad value for funct7 field, "
2474 "value must be 0...127"));
2475 break;
2476 }
2477
2478 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2479 imm_expr->X_op = O_absent;
2480 s = expr_end;
2481 continue;
2482 case '3':
2483 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2484 || imm_expr->X_op != O_constant
2485 || imm_expr->X_add_number < 0
2486 || imm_expr->X_add_number >= 8)
2487 {
2488 as_bad (_("bad value for funct3 field, "
2489 "value must be 0...7"));
2490 break;
2491 }
2492
2493 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2494 imm_expr->X_op = O_absent;
2495 s = expr_end;
2496 continue;
2497 case '2':
2498 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2499 || imm_expr->X_op != O_constant
2500 || imm_expr->X_add_number < 0
2501 || imm_expr->X_add_number >= 4)
2502 {
2503 as_bad (_("bad value for funct2 field, "
2504 "value must be 0...3"));
2505 break;
2506 }
2507
2508 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2509 imm_expr->X_op = O_absent;
2510 s = expr_end;
2511 continue;
2512
2513 default:
2514 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2515 }
2516 break;
e23eba97 2517
e925c834
JW		 2518 case 'z':
2519 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2520 || imm_expr->X_op != O_constant
2521 || imm_expr->X_add_number != 0)
2522 break;
2523 s = expr_end;
2524 imm_expr->X_op = O_absent;
2525 continue;
2526
e23eba97
NC		 2527 default:
2528 as_fatal (_("internal error: bad argument type %c"), *args);
2529 }
2530 break;
2531 }
2532 s = argsStart;
2533 error = _("illegal operands");
54b2aec1 2534 insn_with_csr = FALSE;
e23eba97
NC		 2535 }
2536
dc1e8a47 2537 out:
e23eba97
NC		 2538 /* Restore the character we might have clobbered above. */
2539 if (save_c)
2540 *(argsStart - 1) = save_c;
2541
2542 return error;
2543}
2544
2545void
2546md_assemble (char *str)
2547{
2548 struct riscv_cl_insn insn;
2549 expressionS imm_expr;
2550 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2551
8f595e9b
NC		 2552 /* The arch and priv attributes should be set before assembling. */
2553 if (!start_assemble)
2554 {
2555 start_assemble = TRUE;
e23eba97 2556
8f595e9b
NC		 2557 /* Set the default_priv_spec according to the priv attributes. */
2558 if (!riscv_set_default_priv_spec (NULL))
2559 return;
2560 }
2561
2562 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2563
e23eba97
NC		 2564 if (error)
2565 {
2566 as_bad ("%s `%s'", error, str);
2567 return;
2568 }
2569
2570 if (insn.insn_mo->pinfo == INSN_MACRO)
2571 macro (&insn, &imm_expr, &imm_reloc);
2572 else
2573 append_insn (&insn, &imm_expr, imm_reloc);
2574}
2575
2576const char *
2577md_atof (int type, char *litP, int *sizeP)
2578{
2579 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2580}
2581
2582void
2583md_number_to_chars (char *buf, valueT val, int n)
2584{
2585 number_to_chars_littleendian (buf, val, n);
2586}
2587
2588const char *md_shortopts = "O::g::G:";
2589
2590enum options
2591{
2922d21d 2592 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2593 OPTION_PIC,
2594 OPTION_NO_PIC,
2922d21d 2595 OPTION_MABI,
71060565
JW		 2596 OPTION_RELAX,
2597 OPTION_NO_RELAX,
2dc8dd17
JW		 2598 OPTION_ARCH_ATTR,
2599 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2600 OPTION_CSR_CHECK,
2601 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2602 OPTION_MISA_SPEC,
2603 OPTION_MPRIV_SPEC,
e23eba97
NC		 2604 OPTION_END_OF_ENUM
2605};
2606
2607struct option md_longopts[] =
2608{
e23eba97
NC		 2609 {"march", required_argument, NULL, OPTION_MARCH},
2610 {"fPIC", no_argument, NULL, OPTION_PIC},
2611 {"fpic", no_argument, NULL, OPTION_PIC},
2612 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2613 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2614 {"mrelax", no_argument, NULL, OPTION_RELAX},
2615 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2616 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2617 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2618 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2619 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2620 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2621 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
e23eba97
NC		 2622
2623 {NULL, no_argument, NULL, 0}
2624};
2625size_t md_longopts_size = sizeof (md_longopts);
2626
2922d21d
AW		 2627enum float_abi {
2628 FLOAT_ABI_DEFAULT = -1,
2629 FLOAT_ABI_SOFT,
2630 FLOAT_ABI_SINGLE,
2631 FLOAT_ABI_DOUBLE,
2632 FLOAT_ABI_QUAD
e23eba97 2633};
2922d21d
AW		 2634static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
2635
2636static void
7f999549 2637riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
2922d21d
AW		 2638{
2639 abi_xlen = new_xlen;
2640 float_abi = new_float_abi;
7f999549 2641 rve_abi = rve;
2922d21d 2642}
e23eba97
NC		 2643
2644int
2645md_parse_option (int c, const char *arg)
2646{
2647 switch (c)
2648 {
e23eba97 2649 case OPTION_MARCH:
8f595e9b
NC		 2650 /* riscv_after_parse_args will call riscv_set_arch to parse
2651 the architecture. */
2652 default_arch_with_ext = arg;
e23eba97
NC		 2653 break;
2654
2655 case OPTION_NO_PIC:
2656 riscv_opts.pic = FALSE;
2657 break;
2658
2659 case OPTION_PIC:
2660 riscv_opts.pic = TRUE;
2661 break;
2662
2922d21d
AW		 2663 case OPTION_MABI:
2664 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2665 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2666 else if (strcmp (arg, "ilp32e") == 0)
2667 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2668 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2669 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2670 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2671 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2672 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2673 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2674 else if (strcmp (arg, "lp64") == 0)
7f999549 2675 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2676 else if (strcmp (arg, "lp64f") == 0)
7f999549 2677 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2678 else if (strcmp (arg, "lp64d") == 0)
7f999549 2679 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2680 else if (strcmp (arg, "lp64q") == 0)
7f999549 2681 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2682 else
2683 return 0;
2684 break;
2685
71060565
JW		 2686 case OPTION_RELAX:
2687 riscv_opts.relax = TRUE;
2688 break;
2689
2690 case OPTION_NO_RELAX:
2691 riscv_opts.relax = FALSE;
2692 break;
2693
2dc8dd17
JW		 2694 case OPTION_ARCH_ATTR:
2695 riscv_opts.arch_attr = TRUE;
2696 break;
2697
2698 case OPTION_NO_ARCH_ATTR:
2699 riscv_opts.arch_attr = FALSE;
2700 break;
2701
2ca89224
NC		 2702 case OPTION_CSR_CHECK:
2703 riscv_opts.csr_check = TRUE;
2704 break;
2705
2706 case OPTION_NO_CSR_CHECK:
2707 riscv_opts.csr_check = FALSE;
2708 break;
2709
8f595e9b
NC		 2710 case OPTION_MISA_SPEC:
2711 return riscv_set_default_isa_spec (arg);
2712
2713 case OPTION_MPRIV_SPEC:
2714 return riscv_set_default_priv_spec (arg);
2715
e23eba97
NC		 2716 default:
2717 return 0;
2718 }
2719
2720 return 1;
2721}
2722
2723void
2724riscv_after_parse_args (void)
2725{
8f595e9b
NC		 2726 /* The --with-arch is optional for now, so we have to set the xlen
2727 according to the default_arch, which is set by the --targte, first.
2728 Then, we use the xlen to set the default_arch_with_ext if the
2729 -march and --with-arch are not set. */
e23eba97
NC		 2730 if (xlen == 0)
2731 {
2732 if (strcmp (default_arch, "riscv32") == 0)
2733 xlen = 32;
2734 else if (strcmp (default_arch, "riscv64") == 0)
2735 xlen = 64;
2736 else
2737 as_bad ("unknown default architecture `%s'", default_arch);
2738 }
8f595e9b
NC		 2739 if (default_arch_with_ext == NULL)
2740 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2741
2742 /* Initialize the hash table for extensions with default version. */
2743 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2744
2745 /* If the -misa-spec isn't set, then we set the default ISA spec according
2746 to DEFAULT_RISCV_ISA_SPEC. */
2747 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2748 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2749
8f595e9b
NC		 2750 /* Set the architecture according to -march or or --with-arch. */
2751 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2752
2753 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2754 riscv_set_rvc (FALSE);
1080bf78 2755 if (riscv_subset_supports ("c"))
2922d21d 2756 riscv_set_rvc (TRUE);
2922d21d 2757
7f999549
JW		 2758 /* Enable RVE if specified by the -march option. */
2759 riscv_set_rve (FALSE);
1080bf78 2760 if (riscv_subset_supports ("e"))
7f999549
JW		 2761 riscv_set_rve (TRUE);
2762
8f595e9b
NC		 2763 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2764 according to DEFAULT_PRIV_SPEC. */
2765 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2766 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2767
2922d21d
AW		 2768 /* Infer ABI from ISA if not specified on command line. */
2769 if (abi_xlen == 0)
2770 abi_xlen = xlen;
2771 else if (abi_xlen > xlen)
2772 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
2773 else if (abi_xlen < xlen)
2774 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
2775
2776 if (float_abi == FLOAT_ABI_DEFAULT)
2777 {
1080bf78 2778 riscv_subset_t *subset;
2922d21d
AW		 2779
2780 /* Assume soft-float unless D extension is present. */
2781 float_abi = FLOAT_ABI_SOFT;
2782
1080bf78 2783 for (subset = riscv_subsets.head; subset != NULL; subset = subset->next)
cc917fd9
KC		 2784 {
2785 if (strcasecmp (subset->name, "D") == 0)
2786 float_abi = FLOAT_ABI_DOUBLE;
2787 if (strcasecmp (subset->name, "Q") == 0)
2788 float_abi = FLOAT_ABI_QUAD;
2789 }
2922d21d
AW		 2790 }
2791
7f999549
JW		 2792 if (rve_abi)
2793 elf_flags |= EF_RISCV_RVE;
2794
2922d21d
AW		 2795 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2796 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
0ac2b354
AB		 2797
2798 /* If the CIE to be produced has not been overridden on the command line,
2799 then produce version 3 by default. This allows us to use the full
2800 range of registers in a .cfi_return_column directive. */
2801 if (flag_dwarf_cie_version == -1)
2802 flag_dwarf_cie_version = 3;
e23eba97
NC		 2803}
2804
2805long
2806md_pcrel_from (fixS *fixP)
2807{
2808 return fixP->fx_where + fixP->fx_frag->fr_address;
2809}
2810
2811/* Apply a fixup to the object file. */
2812
2813void
2814md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2815{
45f76423 2816 unsigned int subtype;
e23eba97 2817 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2818 bfd_boolean relaxable = FALSE;
c1b465c9 2819 offsetT loc;
a6cbf936 2820 segT sub_segment;
e23eba97
NC		 2821
2822 /* Remember value for tc_gen_reloc. */
2823 fixP->fx_addnumber = *valP;
2824
2825 switch (fixP->fx_r_type)
2826 {
e23eba97
NC		 2827 case BFD_RELOC_RISCV_HI20:
2828 case BFD_RELOC_RISCV_LO12_I:
2829 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2830 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2831 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2832 if (fixP->fx_addsy == NULL)
2833 fixP->fx_done = TRUE;
45f76423
AW		 2834 relaxable = TRUE;
2835 break;
2836
2837 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2838 case BFD_RELOC_RISCV_ADD8:
2839 case BFD_RELOC_RISCV_ADD16:
2840 case BFD_RELOC_RISCV_ADD32:
2841 case BFD_RELOC_RISCV_ADD64:
45f76423 2842 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2843 case BFD_RELOC_RISCV_SUB8:
2844 case BFD_RELOC_RISCV_SUB16:
2845 case BFD_RELOC_RISCV_SUB32:
2846 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2847 case BFD_RELOC_RISCV_RELAX:
2848 break;
2849
2850 case BFD_RELOC_RISCV_TPREL_HI20:
2851 case BFD_RELOC_RISCV_TPREL_LO12_I:
2852 case BFD_RELOC_RISCV_TPREL_LO12_S:
2853 case BFD_RELOC_RISCV_TPREL_ADD:
2854 relaxable = TRUE;
2855 /* Fall through. */
2856
2857 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2858 case BFD_RELOC_RISCV_TLS_GD_HI20:
2859 case BFD_RELOC_RISCV_TLS_DTPREL32:
2860 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2861 if (fixP->fx_addsy != NULL)
2862 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2863 else
2864 as_bad_where (fixP->fx_file, fixP->fx_line,
2865 _("TLS relocation against a constant"));
e23eba97
NC		 2866 break;
2867
e23eba97 2868 case BFD_RELOC_32:
a6cbf936
KLC		 2869 /* Use pc-relative relocation for FDE initial location.
2870 The symbol address in .eh_frame may be adjusted in
2871 _bfd_elf_discard_section_eh_frame, and the content of
2872 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2873 Therefore, we cannot insert a relocation whose addend symbol is
2874 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2875 if (fixP->fx_addsy && fixP->fx_subsy
2876 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2877 && strcmp (sub_segment->name, ".eh_frame") == 0
2878 && S_GET_VALUE (fixP->fx_subsy)
2879 == fixP->fx_frag->fr_address + fixP->fx_where)
2880 {
2881 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2882 fixP->fx_subsy = NULL;
2883 break;
2884 }
2885 /* Fall through. */
2886 case BFD_RELOC_64:
e23eba97
NC		 2887 case BFD_RELOC_16:
2888 case BFD_RELOC_8:
45f76423 2889 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2890 if (fixP->fx_addsy && fixP->fx_subsy)
2891 {
2892 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2893 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2894 fixP->fx_next->fx_subsy = NULL;
2895 fixP->fx_next->fx_offset = 0;
2896 fixP->fx_subsy = NULL;
2897
2898 switch (fixP->fx_r_type)
2899 {
2900 case BFD_RELOC_64:
2901 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2902 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2903 break;
2904
2905 case BFD_RELOC_32:
2906 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2907 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2908 break;
2909
2910 case BFD_RELOC_16:
2911 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2912 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2913 break;
2914
2915 case BFD_RELOC_8:
2916 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2917 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2918 break;
e23eba97 2919
45f76423
AW		 2920 case BFD_RELOC_RISCV_CFA:
2921 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2922 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2923 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2924 switch (subtype)
2925 {
2926 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2927 fixP->fx_where = loc + 1;
2928 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2929 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2930 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2931 break;
2932
2933 case DW_CFA_advance_loc2:
2934 fixP->fx_size = 2;
45f76423 2935 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2936 fixP->fx_where = loc + 1;
2937 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2938 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2939 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2940 break;
2941
2942 case DW_CFA_advance_loc4:
2943 fixP->fx_size = 4;
45f76423 2944 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2945 fixP->fx_where = loc;
2946 fixP->fx_next->fx_where = loc;
45f76423
AW		 2947 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2948 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2949 break;
2950
2951 default:
2952 if (subtype < 0x80 && (subtype & 0x40))
2953 {
2954 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2955 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2956 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2957 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2958 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2959 }
2960 else
2961 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2962 break;
2963 }
2964 break;
2965
e23eba97
NC		 2966 default:
2967 /* This case is unreachable. */
2968 abort ();
2969 }
2970 }
2971 /* Fall through. */
2972
2973 case BFD_RELOC_RVA:
2974 /* If we are deleting this reloc entry, we must fill in the
2975 value now. This can happen if we have a .word which is not
2976 resolved when it appears but is later defined. */
2977 if (fixP->fx_addsy == NULL)
2978 {
2979 gas_assert (fixP->fx_size <= sizeof (valueT));
2980 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2981 fixP->fx_done = 1;
2982 }
2983 break;
2984
2985 case BFD_RELOC_RISCV_JMP:
2986 if (fixP->fx_addsy)
2987 {
2988 /* Fill in a tentative value to improve objdump readability. */
2989 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2990 bfd_vma delta = target - md_pcrel_from (fixP);
2991 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2992 }
2993 break;
2994
2995 case BFD_RELOC_12_PCREL:
2996 if (fixP->fx_addsy)
2997 {
2998 /* Fill in a tentative value to improve objdump readability. */
2999 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3000 bfd_vma delta = target - md_pcrel_from (fixP);
3001 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
3002 }
3003 break;
3004
3005 case BFD_RELOC_RISCV_RVC_BRANCH:
3006 if (fixP->fx_addsy)
3007 {
3008 /* Fill in a tentative value to improve objdump readability. */
3009 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3010 bfd_vma delta = target - md_pcrel_from (fixP);
3011 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
3012 }
3013 break;
3014
3015 case BFD_RELOC_RISCV_RVC_JUMP:
3016 if (fixP->fx_addsy)
3017 {
3018 /* Fill in a tentative value to improve objdump readability. */
3019 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3020 bfd_vma delta = target - md_pcrel_from (fixP);
3021 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3022 }
3023 break;
3024
e23eba97
NC		 3025 case BFD_RELOC_RISCV_CALL:
3026 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3027 relaxable = TRUE;
3028 break;
3029
9d06997a 3030 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3031 case BFD_RELOC_RISCV_PCREL_LO12_S:
3032 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3033 relaxable = riscv_opts.relax;
3034 break;
3035
e23eba97
NC		 3036 case BFD_RELOC_RISCV_ALIGN:
3037 break;
3038
3039 default:
3040 /* We ignore generic BFD relocations we don't know about. */
3041 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3042 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3043 }
45f76423 3044
e294484e
AW		 3045 if (fixP->fx_subsy != NULL)
3046 as_bad_where (fixP->fx_file, fixP->fx_line,
3047 _("unsupported symbol subtraction"));
3048
45f76423
AW		 3049 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3050 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3051 {
3052 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3053 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3054 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
3055 }
3056}
3057
3058/* Because the value of .cfi_remember_state may changed after relaxation,
3059 we insert a fix to relocate it again in link-time. */
3060
3061void
3062riscv_pre_output_hook (void)
3063{
3064 const frchainS *frch;
72393fd1
JW		 3065 segT s;
3066
3067 /* Save the current segment info. */
3068 segT seg = now_seg;
3069 subsegT subseg = now_subseg;
45f76423
AW		 3070
3071 for (s = stdoutput->sections; s; s = s->next)
3072 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3073 {
7cb7b948 3074 fragS *frag;
45f76423
AW		 3075
3076 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3077 {
3078 if (frag->fr_type == rs_cfa)
3079 {
45f76423 3080 expressionS exp;
8d1015a8 3081 expressionS *symval;
45f76423 3082
8d1015a8 3083 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3084 exp.X_op = O_subtract;
8d1015a8 3085 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3086 exp.X_add_number = 0;
8d1015a8 3087 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3088
72393fd1
JW		 3089 /* We must set the segment before creating a frag after all
3090 frag chains have been chained together. */
3091 subseg_set (s, frch->frch_subseg);
3092
c1b465c9 3093 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3094 BFD_RELOC_RISCV_CFA);
3095 }
3096 }
3097 }
72393fd1
JW		 3098
3099 /* Restore the original segment info. */
3100 subseg_set (seg, subseg);
e23eba97
NC		 3101}
3102
45f76423 3103
e23eba97
NC		 3104/* This structure is used to hold a stack of .option values. */
3105
3106struct riscv_option_stack
3107{
3108 struct riscv_option_stack *next;
3109 struct riscv_set_options options;
3110};
3111
3112static struct riscv_option_stack *riscv_opts_stack;
3113
3114/* Handle the .option pseudo-op. */
3115
3116static void
3117s_riscv_option (int x ATTRIBUTE_UNUSED)
3118{
3119 char *name = input_line_pointer, ch;
3120
3121 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3122 ++input_line_pointer;
3123 ch = *input_line_pointer;
3124 *input_line_pointer = '\0';
3125
3126 if (strcmp (name, "rvc") == 0)
3127 riscv_set_rvc (TRUE);
3128 else if (strcmp (name, "norvc") == 0)
3129 riscv_set_rvc (FALSE);
3130 else if (strcmp (name, "pic") == 0)
3131 riscv_opts.pic = TRUE;
3132 else if (strcmp (name, "nopic") == 0)
3133 riscv_opts.pic = FALSE;
45f76423
AW		 3134 else if (strcmp (name, "relax") == 0)
3135 riscv_opts.relax = TRUE;
3136 else if (strcmp (name, "norelax") == 0)
3137 riscv_opts.relax = FALSE;
2ca89224
NC		 3138 else if (strcmp (name, "csr-check") == 0)
3139 riscv_opts.csr_check = TRUE;
3140 else if (strcmp (name, "no-csr-check") == 0)
3141 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3142 else if (strcmp (name, "push") == 0)
3143 {
3144 struct riscv_option_stack *s;
3145
3146 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3147 s->next = riscv_opts_stack;
3148 s->options = riscv_opts;
3149 riscv_opts_stack = s;
3150 }
3151 else if (strcmp (name, "pop") == 0)
3152 {
3153 struct riscv_option_stack *s;
3154
3155 s = riscv_opts_stack;
3156 if (s == NULL)
3157 as_bad (_(".option pop with no .option push"));
3158 else
3159 {
3160 riscv_opts = s->options;
3161 riscv_opts_stack = s->next;
3162 free (s);
3163 }
3164 }
3165 else
3166 {
3167 as_warn (_("Unrecognized .option directive: %s\n"), name);
3168 }
3169 *input_line_pointer = ch;
3170 demand_empty_rest_of_line ();
3171}
3172
3173/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3174 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3175 use in DWARF debug information. */
3176
3177static void
3178s_dtprel (int bytes)
3179{
3180 expressionS ex;
3181 char *p;
3182
3183 expression (&ex);
3184
3185 if (ex.X_op != O_symbol)
3186 {
3187 as_bad (_("Unsupported use of %s"), (bytes == 8
3188 ? ".dtpreldword"
3189 : ".dtprelword"));
3190 ignore_rest_of_line ();
3191 }
3192
3193 p = frag_more (bytes);
3194 md_number_to_chars (p, 0, bytes);
3195 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3196 (bytes == 8
3197 ? BFD_RELOC_RISCV_TLS_DTPREL64
3198 : BFD_RELOC_RISCV_TLS_DTPREL32));
3199
3200 demand_empty_rest_of_line ();
3201}
3202
3203/* Handle the .bss pseudo-op. */
3204
3205static void
3206s_bss (int ignore ATTRIBUTE_UNUSED)
3207{
3208 subseg_set (bss_section, 0);
3209 demand_empty_rest_of_line ();
3210}
3211
e23eba97 3212static void
d115ab8e 3213riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3214{
d115ab8e 3215 bfd_vma i = 0;
e23eba97 3216
e5b737de
AW		 3217 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3218 means we are not within a valid instruction sequence. It is thus safe
3219 to use a zero byte, even though that is not a valid instruction. */
3220 if (bytes % 2 == 1)
3221 buf[i++] = 0;
3222
3223 /* Use at most one 2-byte NOP. */
3224 if ((bytes - i) % 4 == 2)
e23eba97 3225 {
e5b737de 3226 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 3227 i += 2;
e23eba97
NC		 3228 }
3229
e5b737de 3230 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 3231 for ( ; i < bytes; i += 4)
3232 md_number_to_chars (buf + i, RISCV_NOP, 4);
3233}
e23eba97 3234
d115ab8e
AW		 3235/* Called from md_do_align. Used to create an alignment frag in a
3236 code section by emitting a worst-case NOP sequence that the linker
3237 will later relax to the correct number of NOPs. We can't compute
3238 the correct alignment now because of other linker relaxations. */
3239
3240bfd_boolean
3241riscv_frag_align_code (int n)
3242{
e5b737de 3243 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3244 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3245 bfd_vma worst_case_bytes = bytes - insn_alignment;
3246 char *nops;
ed0816bd 3247 expressionS ex;
d115ab8e 3248
36877bfb
JW		 3249 /* If we are moving to a smaller alignment than the instruction size, then no
3250 alignment is required. */
3251 if (bytes <= insn_alignment)
3252 return TRUE;
3253
d115ab8e
AW		 3254 /* When not relaxing, riscv_handle_align handles code alignment. */
3255 if (!riscv_opts.relax)
3256 return FALSE;
e23eba97 3257
e80ae190
JW		 3258 nops = frag_more (worst_case_bytes);
3259
ed0816bd
PD		 3260 ex.X_op = O_constant;
3261 ex.X_add_number = worst_case_bytes;
d115ab8e 3262
ed0816bd 3263 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3264
ed0816bd
PD		 3265 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3266 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3267
d115ab8e
AW		 3268 return TRUE;
3269}
e23eba97 3270
d115ab8e
AW		 3271/* Implement HANDLE_ALIGN. */
3272
3273void
3274riscv_handle_align (fragS *fragP)
3275{
3276 switch (fragP->fr_type)
3277 {
3278 case rs_align_code:
3279 /* When relaxing, riscv_frag_align_code handles code alignment. */
3280 if (!riscv_opts.relax)
3281 {
e80ae190
JW		 3282 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3283 - fragP->fr_address - fragP->fr_fix);
3284 /* We have 4 byte uncompressed nops. */
3285 bfd_signed_vma size = 4;
3286 bfd_signed_vma excess = bytes % size;
3287 char *p = fragP->fr_literal + fragP->fr_fix;
3288
3289 if (bytes <= 0)
d115ab8e
AW		 3290 break;
3291
e80ae190
JW		 3292 /* Insert zeros or compressed nops to get 4 byte alignment. */
3293 if (excess)
3294 {
3295 riscv_make_nops (p, excess);
3296 fragP->fr_fix += excess;
3297 p += excess;
3298 }
3299
3300 /* Insert variable number of 4 byte uncompressed nops. */
3301 riscv_make_nops (p, size);
3302 fragP->fr_var = size;
d115ab8e
AW		 3303 }
3304 break;
3305
3306 default:
3307 break;
3308 }
e23eba97
NC		 3309}
3310
3311int
3312md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3313{
3314 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3315}
3316
3317/* Translate internal representation of relocation info to BFD target
3318 format. */
3319
3320arelent *
3321tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3322{
3323 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3324
3325 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3326 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3327 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3328 reloc->addend = fixp->fx_addnumber;
3329
3330 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3331 if (reloc->howto == NULL)
3332 {
3333 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3334 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3335 {
3336 /* We don't have R_RISCV_8/16, but for this special case,
3337 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3338 return reloc;
3339 }
3340
3341 as_bad_where (fixp->fx_file, fixp->fx_line,
3342 _("cannot represent %s relocation in object file"),
3343 bfd_get_reloc_code_name (fixp->fx_r_type));
3344 return NULL;
3345 }
3346
3347 return reloc;
3348}
3349
3350int
3351riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3352{
3353 if (RELAX_BRANCH_P (fragp->fr_subtype))
3354 {
3355 offsetT old_var = fragp->fr_var;
3356 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3357 return fragp->fr_var - old_var;
3358 }
3359
3360 return 0;
3361}
3362
3363/* Expand far branches to multi-instruction sequences. */
3364
3365static void
3366md_convert_frag_branch (fragS *fragp)
3367{
3368 bfd_byte *buf;
3369 expressionS exp;
3370 fixS *fixp;
3371 insn_t insn;
3372 int rs1, reloc;
3373
3374 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3375
3376 exp.X_op = O_symbol;
3377 exp.X_add_symbol = fragp->fr_symbol;
3378 exp.X_add_number = fragp->fr_offset;
3379
3380 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3381
3382 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3383 {
3384 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3385 {
3386 case 8:
3387 case 4:
3388 /* Expand the RVC branch into a RISC-V one. */
3389 insn = bfd_getl16 (buf);
3390 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3391 if ((insn & MASK_C_J) == MATCH_C_J)
3392 insn = MATCH_JAL;
3393 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3394 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3395 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3396 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3397 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3398 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3399 else
3400 abort ();
3401 bfd_putl32 (insn, buf);
3402 break;
3403
3404 case 6:
3405 /* Invert the branch condition. Branch over the jump. */
3406 insn = bfd_getl16 (buf);
3407 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3408 insn |= ENCODE_RVC_B_IMM (6);
3409 bfd_putl16 (insn, buf);
3410 buf += 2;
3411 goto jump;
3412
3413 case 2:
3414 /* Just keep the RVC branch. */
3415 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3416 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3417 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3418 2, &exp, FALSE, reloc);
3419 buf += 2;
3420 goto done;
3421
3422 default:
1d65abb5 3423 abort ();
e23eba97
NC		 3424 }
3425 }
3426
3427 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3428 {
3429 case 8:
3430 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3431
3432 /* Invert the branch condition. Branch over the jump. */
3433 insn = bfd_getl32 (buf);
3434 insn ^= MATCH_BEQ ^ MATCH_BNE;
3435 insn |= ENCODE_SBTYPE_IMM (8);
3436 md_number_to_chars ((char *) buf, insn, 4);
3437 buf += 4;
3438
dc1e8a47 3439 jump:
e23eba97
NC		 3440 /* Jump to the target. */
3441 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3442 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
3443 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
3444 buf += 4;
3445 break;
3446
3447 case 4:
3448 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3449 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3450 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3451 4, &exp, FALSE, reloc);
3452 buf += 4;
3453 break;
3454
3455 default:
3456 abort ();
3457 }
3458
dc1e8a47 3459 done:
e23eba97
NC		 3460 fixp->fx_file = fragp->fr_file;
3461 fixp->fx_line = fragp->fr_line;
3462
3463 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3464 + fragp->fr_fix + fragp->fr_var);
3465
3466 fragp->fr_fix += fragp->fr_var;
3467}
3468
3469/* Relax a machine dependent frag. This returns the amount by which
3470 the current size of the frag should change. */
3471
3472void
3473md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3474 fragS *fragp)
3475{
3476 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3477 md_convert_frag_branch (fragp);
3478}
3479
3480void
3481md_show_usage (FILE *stream)
3482{
3483 fprintf (stream, _("\
3484RISC-V options:\n\
8f595e9b
NC		 3485 -fpic generate position-independent code\n\
3486 -fno-pic don't generate position-independent code (default)\n\
3487 -march=ISA set the RISC-V architecture\n\
3488 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3489 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3490 -mabi=ABI set the RISC-V ABI\n\
3491 -mrelax enable relax (default)\n\
3492 -mno-relax disable relax\n\
3493 -march-attr generate RISC-V arch attribute\n\
3494 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3495"));
3496}
3497
3498/* Standard calling conventions leave the CFA at SP on entry. */
3499void
3500riscv_cfi_frame_initial_instructions (void)
3501{
3502 cfi_add_CFA_def_cfa_register (X_SP);
3503}
3504
3505int
3506tc_riscv_regname_to_dw2regnum (char *regname)
3507{
3508 int reg;
3509
3510 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3511 return reg;
3512
3513 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3514 return reg + 32;
3515
4762fe62
AB		 3516 /* CSRs are numbered 4096 -> 8191. */
3517 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3518 return reg + 4096;
3519
e23eba97
NC		 3520 as_bad (_("unknown register `%s'"), regname);
3521 return -1;
3522}
3523
3524void
3525riscv_elf_final_processing (void)
3526{
e23eba97 3527 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3528}
3529
3530/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3531 since these directives break relaxation when used with symbol deltas. */
3532
3533static void
3534s_riscv_leb128 (int sign)
3535{
3536 expressionS exp;
3537 char *save_in = input_line_pointer;
3538
3539 expression (&exp);
3540 if (exp.X_op != O_constant)
3541 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3542 demand_empty_rest_of_line ();
3543
3544 input_line_pointer = save_in;
3545 return s_leb128 (sign);
3546}
3547
0e35537d
JW		 3548/* Parse the .insn directive. */
3549
3550static void
3551s_riscv_insn (int x ATTRIBUTE_UNUSED)
3552{
3553 char *str = input_line_pointer;
3554 struct riscv_cl_insn insn;
3555 expressionS imm_expr;
3556 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3557 char save_c;
3558
3559 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3560 ++input_line_pointer;
3561
3562 save_c = *input_line_pointer;
3563 *input_line_pointer = '\0';
3564
3565 const char *error = riscv_ip (str, &insn, &imm_expr,
3566 &imm_reloc, insn_type_hash);
3567
3568 if (error)
3569 {
3570 as_bad ("%s `%s'", error, str);
3571 }
3572 else
3573 {
3574 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3575 append_insn (&insn, &imm_expr, imm_reloc);
3576 }
3577
3578 *input_line_pointer = save_c;
3579 demand_empty_rest_of_line ();
3580}
3581
8f595e9b
NC		 3582/* Update arch and priv attributes. If we don't set the corresponding ELF
3583 attributes, then try to output the default ones. */
2dc8dd17
JW		 3584
3585static void
8f595e9b 3586riscv_write_out_attrs (void)
2dc8dd17 3587{
8f595e9b
NC		 3588 const char *arch_str, *priv_str, *p;
3589 /* versions[0] is major, versions[1] is minor,
3590 and versions[3] is revision. */
3591 unsigned versions[3] = {0}, number = 0;
3592 unsigned int i;
2dc8dd17 3593
8f595e9b
NC		 3594 /* Re-write arch attribute to normalize the arch string. */
3595 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3596 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3597 xfree ((void *)arch_str);
8f595e9b
NC		 3598
3599 /* For the file without any instruction, we don't set the default_priv_spec
3600 according to the priv attributes since the md_assemble isn't called.
3601 Call riscv_set_default_priv_spec here for the above case, although
3602 it seems strange. */
3603 if (!start_assemble
3604 && !riscv_set_default_priv_spec (NULL))
3605 return;
3606
3607 /* Re-write priv attributes by default_priv_spec. */
3608 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3609 p = priv_str;
3610 for (i = 0; *p; ++p)
3611 {
3612 if (*p == '.' && i < 3)
3613 {
3614 versions[i++] = number;
3615 number = 0;
3616 }
3617 else if (ISDIGIT (*p))
3618 number = (number * 10) + (*p - '0');
3619 else
3620 {
3621 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3622 return;
3623 }
3624 }
3625 versions[i] = number;
3626
3627 /* Set the priv attributes. */
3628 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3629 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3630 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3631}
3632
8f595e9b
NC		 3633/* Add the default contents for the .riscv.attributes section. If any
3634 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3635 to update the arch and priv attributes. */
2dc8dd17
JW		 3636
3637static void
3638riscv_set_public_attributes (void)
3639{
8f595e9b
NC		 3640 if (riscv_opts.arch_attr || explicit_attr)
3641 riscv_write_out_attrs ();
2dc8dd17
JW		 3642}
3643
3644/* Called after all assembly has been done. */
3645
3646void
3647riscv_md_end (void)
3648{
3649 riscv_set_public_attributes ();
3650}
3651
3652/* Given a symbolic attribute NAME, return the proper integer value.
3653 Returns -1 if the attribute is not known. */
3654
3655int
3656riscv_convert_symbolic_attribute (const char *name)
3657{
3658 static const struct
3659 {
3660 const char * name;
3661 const int tag;
3662 }
3663 attribute_table[] =
3664 {
3665 /* When you modify this table you should
3666 also modify the list in doc/c-riscv.texi. */
3667#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3668 T(arch),
3669 T(priv_spec),
3670 T(priv_spec_minor),
3671 T(priv_spec_revision),
3672 T(unaligned_access),
3673 T(stack_align),
3674#undef T
3675 };
3676
3677 unsigned int i;
3678
3679 if (name == NULL)
3680 return -1;
3681
3682 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3683 if (strcmp (name, attribute_table[i].name) == 0)
3684 return attribute_table[i].tag;
3685
3686 return -1;
3687}
3688
3689/* Parse a .attribute directive. */
3690
3691static void
3692s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3693{
3694 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3695 unsigned old_xlen;
3696 obj_attribute *attr;
2dc8dd17 3697
8f595e9b
NC		 3698 explicit_attr = TRUE;
3699 switch (tag)
2dc8dd17 3700 {
8f595e9b
NC		 3701 case Tag_RISCV_arch:
3702 old_xlen = xlen;
2dc8dd17
JW		 3703 attr = elf_known_obj_attributes_proc (stdoutput);
3704 if (!start_assemble)
3705 riscv_set_arch (attr[Tag_RISCV_arch].s);
3706 else
3707 as_fatal (_(".attribute arch must set before any instructions"));
3708
3709 if (old_xlen != xlen)
3710 {
3711 /* We must re-init bfd again if xlen is changed. */
3712 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3713 bfd_find_target (riscv_target_format (), stdoutput);
3714
3715 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3716 as_warn (_("Could not set architecture and machine"));
3717 }
8f595e9b
NC		 3718 break;
3719
3720 case Tag_RISCV_priv_spec:
3721 case Tag_RISCV_priv_spec_minor:
3722 case Tag_RISCV_priv_spec_revision:
3723 if (start_assemble)
3724 as_fatal (_(".attribute priv spec must set before any instructions"));
3725 break;
3726
3727 default:
3728 break;
2dc8dd17
JW		 3729 }
3730}
3731
e23eba97
NC		 3732/* Pseudo-op table. */
3733
3734static const pseudo_typeS riscv_pseudo_table[] =
3735{
3736 /* RISC-V-specific pseudo-ops. */
3737 {"option", s_riscv_option, 0},
3738 {"half", cons, 2},
3739 {"word", cons, 4},
3740 {"dword", cons, 8},
3741 {"dtprelword", s_dtprel, 4},
3742 {"dtpreldword", s_dtprel, 8},
3743 {"bss", s_bss, 0},
e23eba97
NC		 3744 {"uleb128", s_riscv_leb128, 0},
3745 {"sleb128", s_riscv_leb128, 1},
0e35537d 3746 {"insn", s_riscv_insn, 0},
2dc8dd17 3747 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3748
3749 { NULL, NULL, 0 },
3750};
3751
3752void
3753riscv_pop_insert (void)
3754{
3755 extern void pop_insert (const pseudo_typeS *);
3756
3757 pop_insert (riscv_pseudo_table);
3758}
GDB Binutils - Deliverables
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