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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
219d1afa | 2 | Copyright (C) 2011-2018 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
1d65abb5 | 31 | #include "struc-symbol.h" |
e23eba97 NC |
32 | |
33 | #include "elf/riscv.h" | |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
45 | /* The encoded instruction bits. */ | |
46 | insn_t insn_opcode; | |
47 | ||
48 | /* The frag that contains the instruction. */ | |
49 | struct frag *frag; | |
50 | ||
51 | /* The offset into FRAG of the first instruction byte. */ | |
52 | long where; | |
53 | ||
54 | /* The relocs associated with the instruction, if any. */ | |
55 | fixS *fixp; | |
56 | }; | |
57 | ||
58 | #ifndef DEFAULT_ARCH | |
59 | #define DEFAULT_ARCH "riscv64" | |
60 | #endif | |
61 | ||
62 | static const char default_arch[] = DEFAULT_ARCH; | |
63 | ||
2922d21d AW |
64 | static unsigned xlen = 0; /* width of an x-register */ |
65 | static unsigned abi_xlen = 0; /* width of a pointer in the ABI */ | |
7f999549 | 66 | static bfd_boolean rve_abi = FALSE; |
e23eba97 | 67 | |
2922d21d | 68 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
69 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
70 | ||
71 | static unsigned elf_flags = 0; | |
72 | ||
73 | /* This is the set of options which the .option pseudo-op may modify. */ | |
74 | ||
75 | struct riscv_set_options | |
76 | { | |
77 | int pic; /* Generate position-independent code. */ | |
78 | int rvc; /* Generate RVC code. */ | |
7f999549 | 79 | int rve; /* Generate RVE code. */ |
45f76423 | 80 | int relax; /* Emit relocs the linker is allowed to relax. */ |
e23eba97 NC |
81 | }; |
82 | ||
83 | static struct riscv_set_options riscv_opts = | |
84 | { | |
85 | 0, /* pic */ | |
86 | 0, /* rvc */ | |
7f999549 | 87 | 0, /* rve */ |
45f76423 | 88 | 1, /* relax */ |
e23eba97 NC |
89 | }; |
90 | ||
91 | static void | |
92 | riscv_set_rvc (bfd_boolean rvc_value) | |
93 | { | |
94 | if (rvc_value) | |
95 | elf_flags |= EF_RISCV_RVC; | |
96 | ||
97 | riscv_opts.rvc = rvc_value; | |
98 | } | |
99 | ||
7f999549 JW |
100 | static void |
101 | riscv_set_rve (bfd_boolean rve_value) | |
102 | { | |
103 | riscv_opts.rve = rve_value; | |
104 | } | |
105 | ||
e23eba97 NC |
106 | struct riscv_subset |
107 | { | |
108 | const char *name; | |
109 | ||
110 | struct riscv_subset *next; | |
111 | }; | |
112 | ||
113 | static struct riscv_subset *riscv_subsets; | |
114 | ||
115 | static bfd_boolean | |
43135d3b | 116 | riscv_subset_supports (unsigned xlen_required, const char *feature) |
e23eba97 NC |
117 | { |
118 | struct riscv_subset *s; | |
e23eba97 NC |
119 | |
120 | if (xlen_required && xlen != xlen_required) | |
121 | return FALSE; | |
122 | ||
123 | for (s = riscv_subsets; s != NULL; s = s->next) | |
43135d3b | 124 | if (strcasecmp (s->name, feature) == 0) |
e23eba97 NC |
125 | return TRUE; |
126 | ||
127 | return FALSE; | |
128 | } | |
129 | ||
43135d3b JW |
130 | static bfd_boolean |
131 | riscv_multi_subset_supports (unsigned xlen_required, const char *features[]) | |
132 | { | |
133 | unsigned i = 0; | |
134 | bfd_boolean supported = TRUE; | |
135 | ||
136 | for (;features[i]; ++i) | |
137 | supported = supported && riscv_subset_supports (xlen_required, features[i]); | |
138 | ||
139 | return supported; | |
140 | } | |
141 | ||
fecb9c46 PD |
142 | static void |
143 | riscv_clear_subsets (void) | |
144 | { | |
145 | while (riscv_subsets != NULL) | |
146 | { | |
147 | struct riscv_subset *next = riscv_subsets->next; | |
c41cf6fd | 148 | free ((void *) riscv_subsets->name); |
fecb9c46 PD |
149 | free (riscv_subsets); |
150 | riscv_subsets = next; | |
151 | } | |
152 | } | |
153 | ||
e23eba97 NC |
154 | static void |
155 | riscv_add_subset (const char *subset) | |
156 | { | |
157 | struct riscv_subset *s = xmalloc (sizeof *s); | |
158 | ||
159 | s->name = xstrdup (subset); | |
160 | s->next = riscv_subsets; | |
161 | riscv_subsets = s; | |
162 | } | |
163 | ||
2922d21d | 164 | /* Set which ISA and extensions are available. */ |
e23eba97 | 165 | |
e23eba97 | 166 | static void |
2922d21d | 167 | riscv_set_arch (const char *s) |
e23eba97 | 168 | { |
a8086704 AW |
169 | const char *all_subsets = "imafdqc"; |
170 | char *extension = NULL; | |
2922d21d | 171 | const char *p = s; |
e23eba97 | 172 | |
fecb9c46 PD |
173 | riscv_clear_subsets(); |
174 | ||
2922d21d | 175 | if (strncmp (p, "rv32", 4) == 0) |
e23eba97 NC |
176 | { |
177 | xlen = 32; | |
178 | p += 4; | |
179 | } | |
2922d21d | 180 | else if (strncmp (p, "rv64", 4) == 0) |
e23eba97 NC |
181 | { |
182 | xlen = 64; | |
183 | p += 4; | |
184 | } | |
2922d21d AW |
185 | else |
186 | as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s); | |
e23eba97 | 187 | |
2922d21d | 188 | switch (*p) |
e23eba97 | 189 | { |
2922d21d | 190 | case 'i': |
e23eba97 NC |
191 | break; |
192 | ||
7f999549 JW |
193 | case 'e': |
194 | p++; | |
195 | riscv_add_subset ("e"); | |
196 | riscv_add_subset ("i"); | |
197 | ||
198 | if (xlen > 32) | |
199 | as_fatal ("-march=%s: rv%de is not a valid base ISA", s, xlen); | |
200 | ||
201 | break; | |
202 | ||
2922d21d | 203 | case 'g': |
e23eba97 | 204 | p++; |
a8086704 | 205 | for ( ; *all_subsets != 'q'; all_subsets++) |
e23eba97 | 206 | { |
2922d21d | 207 | const char subset[] = {*all_subsets, '\0'}; |
e23eba97 NC |
208 | riscv_add_subset (subset); |
209 | } | |
210 | break; | |
211 | ||
212 | default: | |
7f999549 | 213 | as_fatal ("-march=%s: first ISA subset must be `e', `i' or `g'", s); |
e23eba97 NC |
214 | } |
215 | ||
216 | while (*p) | |
217 | { | |
2922d21d | 218 | if (*p == 'x') |
e23eba97 | 219 | { |
a8086704 AW |
220 | char *subset = xstrdup (p); |
221 | char *q = subset; | |
e23eba97 NC |
222 | |
223 | while (*++q != '\0' && *q != '_') | |
224 | ; | |
225 | *q = '\0'; | |
226 | ||
227 | if (extension) | |
2922d21d AW |
228 | as_fatal ("-march=%s: only one non-standard extension is supported" |
229 | " (found `%s' and `%s')", s, extension, subset); | |
e23eba97 NC |
230 | extension = subset; |
231 | riscv_add_subset (subset); | |
232 | p += strlen (subset); | |
e23eba97 NC |
233 | } |
234 | else if (*p == '_') | |
235 | p++; | |
236 | else if ((all_subsets = strchr (all_subsets, *p)) != NULL) | |
237 | { | |
238 | const char subset[] = {*p, 0}; | |
239 | riscv_add_subset (subset); | |
e23eba97 NC |
240 | all_subsets++; |
241 | p++; | |
242 | } | |
243 | else | |
2922d21d | 244 | as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p); |
e23eba97 | 245 | } |
a8086704 | 246 | |
43135d3b | 247 | if (riscv_subset_supports (0, "e") && riscv_subset_supports (0, "f")) |
7f999549 JW |
248 | as_fatal ("-march=%s: rv32e does not support the `f' extension", s); |
249 | ||
43135d3b | 250 | if (riscv_subset_supports (0, "d") && !riscv_subset_supports (0, "f")) |
7f999549 JW |
251 | as_fatal ("-march=%s: `d' extension requires `f' extension", s); |
252 | ||
43135d3b | 253 | if (riscv_subset_supports (0, "q") && !riscv_subset_supports (0, "d")) |
7f999549 JW |
254 | as_fatal ("-march=%s: `q' extension requires `d' extension", s); |
255 | ||
43135d3b | 256 | if (riscv_subset_supports (0, "q") && xlen < 64) |
7f999549 JW |
257 | as_fatal ("-march=%s: rv32 does not support the `q' extension", s); |
258 | ||
a8086704 | 259 | free (extension); |
e23eba97 NC |
260 | } |
261 | ||
262 | /* Handle of the OPCODE hash table. */ | |
263 | static struct hash_control *op_hash = NULL; | |
264 | ||
0e35537d JW |
265 | /* Handle of the type of .insn hash table. */ |
266 | static struct hash_control *insn_type_hash = NULL; | |
267 | ||
e23eba97 NC |
268 | /* This array holds the chars that always start a comment. If the |
269 | pre-processor is disabled, these aren't very useful */ | |
270 | const char comment_chars[] = "#"; | |
271 | ||
272 | /* This array holds the chars that only start a comment at the beginning of | |
273 | a line. If the line seems to have the form '# 123 filename' | |
274 | .line and .file directives will appear in the pre-processed output */ | |
275 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
276 | first line of the input file. This is because the compiler outputs | |
277 | #NO_APP at the beginning of its output. */ | |
278 | /* Also note that C style comments are always supported. */ | |
279 | const char line_comment_chars[] = "#"; | |
280 | ||
281 | /* This array holds machine specific line separator characters. */ | |
282 | const char line_separator_chars[] = ";"; | |
283 | ||
284 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
285 | const char EXP_CHARS[] = "eE"; | |
286 | ||
287 | /* Chars that mean this number is a floating point constant */ | |
288 | /* As in 0f12.456 */ | |
289 | /* or 0d1.2345e12 */ | |
290 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
291 | ||
292 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ | |
293 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
294 | ((relax_substateT) \ | |
295 | (0xc0000000 \ | |
296 | | ((uncond) ? 1 : 0) \ | |
297 | | ((rvc) ? 2 : 0) \ | |
298 | | ((length) << 2))) | |
299 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
300 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
301 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
302 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
303 | ||
304 | /* Is the given value a sign-extended 32-bit value? */ | |
305 | #define IS_SEXT_32BIT_NUM(x) \ | |
306 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
307 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
308 | ||
309 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
310 | #define IS_ZEXT_32BIT_NUM(x) \ | |
311 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
312 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
313 | ||
314 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
315 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
316 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
317 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
318 | ||
319 | /* Determine if an instruction matches an opcode. */ | |
320 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
321 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
322 | ||
323 | static char *expr_end; | |
324 | ||
325 | /* The default target format to use. */ | |
326 | ||
327 | const char * | |
328 | riscv_target_format (void) | |
329 | { | |
330 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
331 | } | |
332 | ||
333 | /* Return the length of instruction INSN. */ | |
334 | ||
335 | static inline unsigned int | |
336 | insn_length (const struct riscv_cl_insn *insn) | |
337 | { | |
338 | return riscv_insn_length (insn->insn_opcode); | |
339 | } | |
340 | ||
341 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
342 | ||
343 | static void | |
344 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
345 | { | |
346 | insn->insn_mo = mo; | |
347 | insn->insn_opcode = mo->match; | |
348 | insn->frag = NULL; | |
349 | insn->where = 0; | |
350 | insn->fixp = NULL; | |
351 | } | |
352 | ||
353 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
354 | ||
355 | static void | |
356 | install_insn (const struct riscv_cl_insn *insn) | |
357 | { | |
358 | char *f = insn->frag->fr_literal + insn->where; | |
359 | md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); | |
360 | } | |
361 | ||
362 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
363 | and install the opcode in the new location. */ | |
364 | ||
365 | static void | |
366 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
367 | { | |
368 | insn->frag = frag; | |
369 | insn->where = where; | |
370 | if (insn->fixp != NULL) | |
371 | { | |
372 | insn->fixp->fx_frag = frag; | |
373 | insn->fixp->fx_where = where; | |
374 | } | |
375 | install_insn (insn); | |
376 | } | |
377 | ||
378 | /* Add INSN to the end of the output. */ | |
379 | ||
380 | static void | |
381 | add_fixed_insn (struct riscv_cl_insn *insn) | |
382 | { | |
383 | char *f = frag_more (insn_length (insn)); | |
384 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
385 | } | |
386 | ||
387 | static void | |
388 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
389 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
390 | { | |
391 | frag_grow (max_chars); | |
392 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
393 | frag_var (rs_machine_dependent, max_chars, var, | |
394 | subtype, symbol, offset, NULL); | |
395 | } | |
396 | ||
397 | /* Compute the length of a branch sequence, and adjust the stored length | |
398 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
399 | ||
400 | static unsigned | |
401 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
402 | { | |
403 | int jump, rvc, length = 8; | |
404 | ||
405 | if (!fragp) | |
406 | return length; | |
407 | ||
408 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
409 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
410 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
411 | ||
412 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
413 | length = jump ? 4 : 8; | |
414 | ||
415 | if (fragp->fr_symbol != NULL | |
416 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 417 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
418 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
419 | { | |
420 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
421 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
422 | val -= fragp->fr_address + fragp->fr_fix; | |
423 | ||
424 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
425 | length = 2; | |
426 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
427 | length = 4; | |
428 | else if (!jump && rvc) | |
429 | length = 6; | |
430 | } | |
431 | ||
432 | if (update) | |
433 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
434 | ||
435 | return length; | |
436 | } | |
437 | ||
0e35537d JW |
438 | /* Information about an opcode name, mnemonics and its value. */ |
439 | struct opcode_name_t | |
440 | { | |
441 | const char *name; | |
442 | unsigned int val; | |
443 | }; | |
444 | ||
445 | /* List for all supported opcode name. */ | |
446 | static const struct opcode_name_t opcode_name_list[] = | |
447 | { | |
448 | {"C0", 0x0}, | |
449 | {"C1", 0x1}, | |
450 | {"C2", 0x2}, | |
451 | ||
452 | {"LOAD", 0x03}, | |
453 | {"LOAD_FP", 0x07}, | |
454 | {"CUSTOM_0", 0x0b}, | |
455 | {"MISC_MEM", 0x0f}, | |
456 | {"OP_IMM", 0x13}, | |
457 | {"AUIPC", 0x17}, | |
458 | {"OP_IMM_32", 0x1b}, | |
459 | /* 48b 0x1f. */ | |
460 | ||
461 | {"STORE", 0x23}, | |
462 | {"STORE_FP", 0x27}, | |
463 | {"CUSTOM_1", 0x2b}, | |
464 | {"AMO", 0x2f}, | |
465 | {"OP", 0x33}, | |
466 | {"LUI", 0x37}, | |
467 | {"OP_32", 0x3b}, | |
468 | /* 64b 0x3f. */ | |
469 | ||
470 | {"MADD", 0x43}, | |
471 | {"MSUB", 0x47}, | |
472 | {"NMADD", 0x4f}, | |
473 | {"NMSUB", 0x4b}, | |
474 | {"OP_FP", 0x53}, | |
475 | /*reserved 0x57. */ | |
476 | {"CUSTOM_2", 0x5b}, | |
477 | /* 48b 0x5f. */ | |
478 | ||
479 | {"BRANCH", 0x63}, | |
480 | {"JALR", 0x67}, | |
481 | /*reserved 0x5b. */ | |
482 | {"JAL", 0x6f}, | |
483 | {"SYSTEM", 0x73}, | |
484 | /*reserved 0x77. */ | |
485 | {"CUSTOM_3", 0x7b}, | |
486 | /* >80b 0x7f. */ | |
487 | ||
488 | {NULL, 0} | |
489 | }; | |
490 | ||
491 | /* Hash table for lookup opcode name. */ | |
492 | static struct hash_control *opcode_names_hash = NULL; | |
493 | ||
494 | /* Initialization for hash table of opcode name. */ | |
495 | static void | |
496 | init_opcode_names_hash (void) | |
497 | { | |
498 | const char *retval; | |
499 | const struct opcode_name_t *opcode; | |
500 | ||
501 | for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) | |
502 | { | |
503 | retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode); | |
504 | ||
505 | if (retval != NULL) | |
506 | as_fatal (_("internal error: can't hash `%s': %s"), | |
507 | opcode->name, retval); | |
508 | } | |
509 | } | |
510 | ||
511 | /* Find `s` is a valid opcode name or not, | |
512 | return the opcode name info if found. */ | |
513 | static const struct opcode_name_t * | |
514 | opcode_name_lookup (char **s) | |
515 | { | |
516 | char *e; | |
517 | char save_c; | |
518 | struct opcode_name_t *o; | |
519 | ||
520 | /* Find end of name. */ | |
521 | e = *s; | |
522 | if (is_name_beginner (*e)) | |
523 | ++e; | |
524 | while (is_part_of_name (*e)) | |
525 | ++e; | |
526 | ||
527 | /* Terminate name. */ | |
528 | save_c = *e; | |
529 | *e = '\0'; | |
530 | ||
531 | o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s); | |
532 | ||
533 | /* Advance to next token if one was recognized. */ | |
534 | if (o) | |
535 | *s = e; | |
536 | ||
537 | *e = save_c; | |
538 | expr_end = e; | |
539 | ||
540 | return o; | |
541 | } | |
542 | ||
e23eba97 NC |
543 | struct regname |
544 | { | |
545 | const char *name; | |
546 | unsigned int num; | |
547 | }; | |
548 | ||
549 | enum reg_class | |
550 | { | |
551 | RCLASS_GPR, | |
552 | RCLASS_FPR, | |
553 | RCLASS_CSR, | |
554 | RCLASS_MAX | |
555 | }; | |
556 | ||
557 | static struct hash_control *reg_names_hash = NULL; | |
558 | ||
559 | #define ENCODE_REG_HASH(cls, n) \ | |
560 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
561 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
562 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
563 | ||
564 | static void | |
565 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
566 | { | |
567 | void *hash = ENCODE_REG_HASH (class, n); | |
568 | const char *retval = hash_insert (reg_names_hash, name, hash); | |
569 | ||
570 | if (retval != NULL) | |
571 | as_fatal (_("internal error: can't hash `%s': %s"), name, retval); | |
572 | } | |
573 | ||
574 | static void | |
575 | hash_reg_names (enum reg_class class, const char * const names[], unsigned n) | |
576 | { | |
577 | unsigned i; | |
578 | ||
579 | for (i = 0; i < n; i++) | |
580 | hash_reg_name (class, names[i], i); | |
581 | } | |
582 | ||
583 | static unsigned int | |
584 | reg_lookup_internal (const char *s, enum reg_class class) | |
585 | { | |
586 | struct regname *r = (struct regname *) hash_find (reg_names_hash, s); | |
587 | ||
588 | if (r == NULL || DECODE_REG_CLASS (r) != class) | |
589 | return -1; | |
7f999549 JW |
590 | |
591 | if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15) | |
592 | return -1; | |
593 | ||
e23eba97 NC |
594 | return DECODE_REG_NUM (r); |
595 | } | |
596 | ||
597 | static bfd_boolean | |
598 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) | |
599 | { | |
600 | char *e; | |
601 | char save_c; | |
602 | int reg = -1; | |
603 | ||
604 | /* Find end of name. */ | |
605 | e = *s; | |
606 | if (is_name_beginner (*e)) | |
607 | ++e; | |
608 | while (is_part_of_name (*e)) | |
609 | ++e; | |
610 | ||
611 | /* Terminate name. */ | |
612 | save_c = *e; | |
613 | *e = '\0'; | |
614 | ||
615 | /* Look for the register. Advance to next token if one was recognized. */ | |
616 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
617 | *s = e; | |
618 | ||
619 | *e = save_c; | |
620 | if (regnop) | |
621 | *regnop = reg; | |
622 | return reg >= 0; | |
623 | } | |
624 | ||
625 | static bfd_boolean | |
626 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) | |
627 | { | |
628 | const char *p = strchr (*s, ','); | |
629 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
630 | ||
bfb218e3 JW |
631 | if (len == 0) |
632 | return FALSE; | |
633 | ||
e23eba97 NC |
634 | for (i = 0; i < size; i++) |
635 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0) | |
636 | { | |
637 | *regnop = i; | |
638 | *s += len; | |
639 | return TRUE; | |
640 | } | |
641 | ||
642 | return FALSE; | |
643 | } | |
644 | ||
645 | /* For consistency checking, verify that all bits are specified either | |
646 | by the match/mask part of the instruction definition, or by the | |
0e35537d JW |
647 | operand list. |
648 | ||
649 | `length` could be 0, 4 or 8, 0 for auto detection. */ | |
e23eba97 | 650 | static bfd_boolean |
0e35537d | 651 | validate_riscv_insn (const struct riscv_opcode *opc, int length) |
e23eba97 NC |
652 | { |
653 | const char *p = opc->args; | |
654 | char c; | |
655 | insn_t used_bits = opc->mask; | |
0e35537d JW |
656 | int insn_width; |
657 | insn_t required_bits; | |
658 | ||
659 | if (length == 0) | |
660 | insn_width = 8 * riscv_insn_length (opc->match); | |
661 | else | |
662 | insn_width = 8 * length; | |
663 | ||
664 | required_bits = ~0ULL >> (64 - insn_width); | |
e23eba97 NC |
665 | |
666 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
667 | { | |
668 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
669 | opc->name, opc->args); | |
670 | return FALSE; | |
671 | } | |
672 | ||
673 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) | |
674 | while (*p) | |
675 | switch (c = *p++) | |
676 | { | |
677 | case 'C': /* RVC */ | |
678 | switch (c = *p++) | |
679 | { | |
1d65abb5 | 680 | case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break; |
e23eba97 NC |
681 | case 'c': break; /* RS1, constrained to equal sp */ |
682 | case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; | |
1d65abb5 | 683 | case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; |
b416fe87 | 684 | case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; |
1d65abb5 AW |
685 | case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; |
686 | case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; | |
687 | case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; | |
688 | case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break; | |
689 | case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break; | |
e23eba97 NC |
690 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; |
691 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1d65abb5 AW |
692 | case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break; |
693 | case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
e23eba97 NC |
694 | case 'w': break; /* RS1S, constrained to equal RD */ |
695 | case 'x': break; /* RS2S, constrained to equal RD */ | |
1d65abb5 AW |
696 | case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break; |
697 | case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break; | |
698 | case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break; | |
699 | case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break; | |
e23eba97 NC |
700 | case 'U': break; /* RS1, constrained to equal RD */ |
701 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1d65abb5 AW |
702 | case '<': used_bits |= ENCODE_RVC_IMM (-1U); break; |
703 | case '>': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
0e35537d JW |
704 | case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break; |
705 | case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; | |
e23eba97 NC |
706 | case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; |
707 | case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
0e35537d JW |
708 | case 'F': /* funct */ |
709 | switch (c = *p++) | |
710 | { | |
711 | case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; | |
712 | case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; | |
713 | default: | |
714 | as_bad (_("internal: bad RISC-V opcode" | |
715 | " (unknown operand type `CF%c'): %s %s"), | |
716 | c, opc->name, opc->args); | |
717 | return FALSE; | |
718 | } | |
719 | break; | |
e23eba97 NC |
720 | default: |
721 | as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), | |
722 | c, opc->name, opc->args); | |
723 | return FALSE; | |
724 | } | |
725 | break; | |
726 | case ',': break; | |
727 | case '(': break; | |
728 | case ')': break; | |
729 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
730 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
731 | case 'A': break; | |
732 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
733 | case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
734 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
735 | case 'I': break; | |
736 | case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
737 | case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
738 | case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ | |
739 | case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
740 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
741 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
742 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
743 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
0e35537d | 744 | case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; |
e23eba97 NC |
745 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; |
746 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
747 | case 'o': | |
1d65abb5 AW |
748 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; |
749 | case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break; | |
750 | case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; | |
751 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
752 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
e925c834 | 753 | case 'z': break; |
e23eba97 NC |
754 | case '[': break; |
755 | case ']': break; | |
756 | case '0': break; | |
0e35537d JW |
757 | case 'F': /* funct */ |
758 | switch (c = *p++) | |
759 | { | |
760 | case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; | |
761 | case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; | |
762 | case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; | |
763 | default: | |
764 | as_bad (_("internal: bad RISC-V opcode" | |
765 | " (unknown operand type `F%c'): %s %s"), | |
766 | c, opc->name, opc->args); | |
767 | return FALSE; | |
768 | } | |
769 | break; | |
770 | case 'O': /* opcode */ | |
771 | switch (c = *p++) | |
772 | { | |
773 | case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; | |
774 | case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; | |
775 | default: | |
776 | as_bad (_("internal: bad RISC-V opcode" | |
777 | " (unknown operand type `F%c'): %s %s"), | |
778 | c, opc->name, opc->args); | |
779 | return FALSE; | |
780 | } | |
781 | break; | |
e23eba97 NC |
782 | default: |
783 | as_bad (_("internal: bad RISC-V opcode " | |
784 | "(unknown operand type `%c'): %s %s"), | |
785 | c, opc->name, opc->args); | |
786 | return FALSE; | |
787 | } | |
788 | #undef USE_BITS | |
789 | if (used_bits != required_bits) | |
790 | { | |
791 | as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), | |
792 | ~(unsigned long)(used_bits & required_bits), | |
793 | opc->name, opc->args); | |
794 | return FALSE; | |
795 | } | |
796 | return TRUE; | |
797 | } | |
798 | ||
799 | struct percent_op_match | |
800 | { | |
801 | const char *str; | |
802 | bfd_reloc_code_real_type reloc; | |
803 | }; | |
804 | ||
0e35537d JW |
805 | /* Common hash table initialization function for |
806 | instruction and .insn directive. */ | |
807 | static struct hash_control * | |
808 | init_opcode_hash (const struct riscv_opcode *opcodes, | |
809 | bfd_boolean insn_directive_p) | |
e23eba97 NC |
810 | { |
811 | int i = 0; | |
0e35537d JW |
812 | int length; |
813 | struct hash_control *hash = hash_new (); | |
814 | while (opcodes[i].name) | |
e23eba97 | 815 | { |
0e35537d | 816 | const char *name = opcodes[i].name; |
e23eba97 | 817 | const char *hash_error = |
0e35537d | 818 | hash_insert (hash, name, (void *) &opcodes[i]); |
e23eba97 NC |
819 | |
820 | if (hash_error) | |
821 | { | |
822 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
0e35537d | 823 | opcodes[i].name, hash_error); |
e23eba97 NC |
824 | /* Probably a memory allocation problem? Give up now. */ |
825 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
826 | } | |
827 | ||
828 | do | |
829 | { | |
0e35537d | 830 | if (opcodes[i].pinfo != INSN_MACRO) |
e23eba97 | 831 | { |
0e35537d JW |
832 | if (insn_directive_p) |
833 | length = ((name[0] == 'c') ? 2 : 4); | |
834 | else | |
835 | length = 0; /* Let assembler determine the length. */ | |
836 | if (!validate_riscv_insn (&opcodes[i], length)) | |
e23eba97 NC |
837 | as_fatal (_("Broken assembler. No assembly attempted.")); |
838 | } | |
0e35537d JW |
839 | else |
840 | gas_assert (!insn_directive_p); | |
e23eba97 NC |
841 | ++i; |
842 | } | |
0e35537d | 843 | while (opcodes[i].name && !strcmp (opcodes[i].name, name)); |
e23eba97 NC |
844 | } |
845 | ||
0e35537d JW |
846 | return hash; |
847 | } | |
848 | ||
849 | /* This function is called once, at assembler startup time. It should set up | |
850 | all the tables, etc. that the MD part of the assembler will need. */ | |
851 | ||
852 | void | |
853 | md_begin (void) | |
854 | { | |
855 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
856 | ||
857 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
858 | as_warn (_("Could not set architecture and machine")); | |
859 | ||
860 | op_hash = init_opcode_hash (riscv_opcodes, FALSE); | |
861 | insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE); | |
862 | ||
e23eba97 NC |
863 | reg_names_hash = hash_new (); |
864 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); | |
865 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
866 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
867 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
868 | ||
b9c04e5a JW |
869 | /* Add "fp" as an alias for "s0". */ |
870 | hash_reg_name (RCLASS_GPR, "fp", 8); | |
871 | ||
0e35537d JW |
872 | opcode_names_hash = hash_new (); |
873 | init_opcode_names_hash (); | |
874 | ||
e23eba97 | 875 | #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); |
1270b047 | 876 | #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num); |
e23eba97 NC |
877 | #include "opcode/riscv-opc.h" |
878 | #undef DECLARE_CSR | |
879 | ||
880 | /* Set the default alignment for the text section. */ | |
881 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
882 | } | |
883 | ||
45f76423 AW |
884 | static insn_t |
885 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
886 | { | |
887 | switch (reloc_type) | |
888 | { | |
889 | case BFD_RELOC_32: | |
890 | return value; | |
891 | ||
892 | case BFD_RELOC_RISCV_HI20: | |
893 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
894 | ||
895 | case BFD_RELOC_RISCV_LO12_S: | |
896 | return ENCODE_STYPE_IMM (value); | |
897 | ||
898 | case BFD_RELOC_RISCV_LO12_I: | |
899 | return ENCODE_ITYPE_IMM (value); | |
900 | ||
901 | default: | |
902 | abort (); | |
903 | } | |
904 | } | |
905 | ||
e23eba97 NC |
906 | /* Output an instruction. IP is the instruction information. |
907 | ADDRESS_EXPR is an operand of the instruction to be used with | |
908 | RELOC_TYPE. */ | |
909 | ||
910 | static void | |
911 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
912 | bfd_reloc_code_real_type reloc_type) | |
913 | { | |
914 | dwarf2_emit_insn (0); | |
915 | ||
916 | if (reloc_type != BFD_RELOC_UNUSED) | |
917 | { | |
918 | reloc_howto_type *howto; | |
919 | ||
1d65abb5 | 920 | gas_assert (address_expr); |
e23eba97 NC |
921 | if (reloc_type == BFD_RELOC_12_PCREL |
922 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
923 | { | |
924 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
925 | int best_case = riscv_insn_length (ip->insn_opcode); | |
926 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); | |
927 | add_relaxed_insn (ip, worst_case, best_case, | |
928 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
929 | address_expr->X_add_symbol, | |
930 | address_expr->X_add_number); | |
931 | return; | |
932 | } | |
45f76423 | 933 | else |
e23eba97 | 934 | { |
45f76423 AW |
935 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
936 | if (howto == NULL) | |
937 | as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); | |
e23eba97 | 938 | |
45f76423 AW |
939 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
940 | bfd_get_reloc_size (howto), | |
941 | address_expr, FALSE, reloc_type); | |
e23eba97 | 942 | |
45f76423 | 943 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 944 | } |
e23eba97 NC |
945 | } |
946 | ||
e23eba97 NC |
947 | add_fixed_insn (ip); |
948 | install_insn (ip); | |
f77bb6c5 JW |
949 | |
950 | /* We need to start a new frag after any instruction that can be | |
951 | optimized away or compressed by the linker during relaxation, to prevent | |
952 | the assembler from computing static offsets across such an instruction. | |
953 | This is necessary to get correct EH info. */ | |
954 | if (reloc_type == BFD_RELOC_RISCV_CALL | |
955 | || reloc_type == BFD_RELOC_RISCV_CALL_PLT | |
956 | || reloc_type == BFD_RELOC_RISCV_HI20 | |
957 | || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 | |
958 | || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 | |
959 | || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) | |
960 | { | |
961 | frag_wane (frag_now); | |
962 | frag_new (0); | |
963 | } | |
e23eba97 NC |
964 | } |
965 | ||
966 | /* Build an instruction created by a macro expansion. This is passed | |
967 | a pointer to the count of instructions created so far, an | |
968 | expression, the name of the instruction to build, an operand format | |
969 | string, and corresponding arguments. */ | |
970 | ||
971 | static void | |
972 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
973 | { | |
974 | const struct riscv_opcode *mo; | |
975 | struct riscv_cl_insn insn; | |
976 | bfd_reloc_code_real_type r; | |
977 | va_list args; | |
978 | ||
979 | va_start (args, fmt); | |
980 | ||
981 | r = BFD_RELOC_UNUSED; | |
982 | mo = (struct riscv_opcode *) hash_find (op_hash, name); | |
983 | gas_assert (mo); | |
984 | ||
985 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
986 | it if possible. */ | |
987 | while (riscv_insn_length (mo->match) < 4) | |
988 | mo++; | |
989 | gas_assert (strcmp (name, mo->name) == 0); | |
990 | ||
991 | create_insn (&insn, mo); | |
992 | for (;;) | |
993 | { | |
994 | switch (*fmt++) | |
995 | { | |
996 | case 'd': | |
997 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
998 | continue; | |
999 | ||
1000 | case 's': | |
1001 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
1002 | continue; | |
1003 | ||
1004 | case 't': | |
1005 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
1006 | continue; | |
1007 | ||
1008 | case '>': | |
1009 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); | |
1010 | continue; | |
1011 | ||
1012 | case 'j': | |
1013 | case 'u': | |
1014 | case 'q': | |
1015 | gas_assert (ep != NULL); | |
1016 | r = va_arg (args, int); | |
1017 | continue; | |
1018 | ||
1019 | case '\0': | |
1020 | break; | |
1021 | case ',': | |
1022 | continue; | |
1023 | default: | |
1024 | as_fatal (_("internal error: invalid macro")); | |
1025 | } | |
1026 | break; | |
1027 | } | |
1028 | va_end (args); | |
1029 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1030 | ||
1031 | append_insn (&insn, ep, r); | |
1032 | } | |
1033 | ||
1034 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits | |
1035 | unset. */ | |
1036 | static void | |
1037 | normalize_constant_expr (expressionS *ex) | |
1038 | { | |
1039 | if (xlen > 32) | |
1040 | return; | |
1041 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
1042 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
1043 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
1044 | - 0x80000000); | |
1045 | } | |
1046 | ||
ca2fd32c JW |
1047 | /* Fail if an expression EX is not a constant. IP is the instruction using EX. |
1048 | MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ | |
e23eba97 NC |
1049 | |
1050 | static void | |
ca2fd32c JW |
1051 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, |
1052 | bfd_boolean maybe_csr) | |
e23eba97 NC |
1053 | { |
1054 | if (ex->X_op == O_big) | |
1055 | as_bad (_("unsupported large constant")); | |
ca2fd32c JW |
1056 | else if (maybe_csr && ex->X_op == O_symbol) |
1057 | as_bad (_("unknown CSR `%s'"), | |
1058 | S_GET_NAME (ex->X_add_symbol)); | |
e23eba97 NC |
1059 | else if (ex->X_op != O_constant) |
1060 | as_bad (_("Instruction %s requires absolute expression"), | |
1061 | ip->insn_mo->name); | |
1062 | normalize_constant_expr (ex); | |
1063 | } | |
1064 | ||
1065 | static symbolS * | |
1066 | make_internal_label (void) | |
1067 | { | |
1068 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, | |
1d65abb5 | 1069 | (valueT) frag_now_fix (), frag_now); |
e23eba97 NC |
1070 | } |
1071 | ||
1072 | /* Load an entry from the GOT. */ | |
1073 | static void | |
1074 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
1075 | const char *lo_insn, const char *lo_pattern, | |
1076 | bfd_reloc_code_real_type hi_reloc, | |
1077 | bfd_reloc_code_real_type lo_reloc) | |
1078 | { | |
1079 | expressionS ep2; | |
1080 | ep2.X_op = O_symbol; | |
1081 | ep2.X_add_symbol = make_internal_label (); | |
1082 | ep2.X_add_number = 0; | |
1083 | ||
1084 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
1085 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
1086 | } | |
1087 | ||
1088 | static void | |
1089 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1090 | bfd_reloc_code_real_type hi_reloc, | |
1091 | bfd_reloc_code_real_type lo_reloc) | |
1092 | { | |
1093 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
1094 | } | |
1095 | ||
1096 | static void | |
1097 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1098 | bfd_reloc_code_real_type hi_reloc, | |
1099 | bfd_reloc_code_real_type lo_reloc) | |
1100 | { | |
1101 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
1102 | } | |
1103 | ||
1104 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
1105 | static void | |
1106 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
1107 | bfd_reloc_code_real_type reloc) | |
1108 | { | |
1109 | macro_build (ep, "auipc", "d,u", tempreg, reloc); | |
1110 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
1111 | } | |
1112 | ||
1113 | /* Load an integer constant into a register. */ | |
1114 | ||
1115 | static void | |
1116 | load_const (int reg, expressionS *ep) | |
1117 | { | |
1118 | int shift = RISCV_IMM_BITS; | |
1119 | expressionS upper = *ep, lower = *ep; | |
1120 | lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift); | |
1121 | upper.X_add_number -= lower.X_add_number; | |
1122 | ||
1123 | if (ep->X_op != O_constant) | |
1124 | { | |
1125 | as_bad (_("unsupported large constant")); | |
1126 | return; | |
1127 | } | |
1128 | ||
1d65abb5 | 1129 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
1130 | { |
1131 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
1132 | while (((upper.X_add_number >> shift) & 1) == 0) | |
1133 | shift++; | |
1134 | ||
1135 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 1136 | load_const (reg, &upper); |
e23eba97 NC |
1137 | |
1138 | macro_build (NULL, "slli", "d,s,>", reg, reg, shift); | |
1139 | if (lower.X_add_number != 0) | |
1140 | macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); | |
1141 | } | |
1142 | else | |
1143 | { | |
1144 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
1145 | int hi_reg = 0; | |
1146 | ||
1147 | if (upper.X_add_number != 0) | |
1148 | { | |
1149 | macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); | |
1150 | hi_reg = reg; | |
1151 | } | |
1152 | ||
1153 | if (lower.X_add_number != 0 || hi_reg == 0) | |
1154 | macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, | |
1155 | BFD_RELOC_RISCV_LO12_I); | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | /* Expand RISC-V assembly macros into one or more instructions. */ | |
1160 | static void | |
1161 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
1162 | bfd_reloc_code_real_type *imm_reloc) | |
1163 | { | |
1164 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
1165 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
1166 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
1167 | int mask = ip->insn_mo->mask; | |
1168 | ||
1169 | switch (mask) | |
1170 | { | |
1171 | case M_LI: | |
1172 | load_const (rd, imm_expr); | |
1173 | break; | |
1174 | ||
1175 | case M_LA: | |
1176 | case M_LLA: | |
1177 | /* Load the address of a symbol into a register. */ | |
1178 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
1179 | as_bad (_("offset too large")); | |
1180 | ||
1181 | if (imm_expr->X_op == O_constant) | |
1182 | load_const (rd, imm_expr); | |
1183 | else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ | |
1184 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
1185 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1186 | else /* Local PIC symbol, or any non-PIC symbol */ | |
1187 | pcrel_load (rd, rd, imm_expr, "addi", | |
1188 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1189 | break; | |
1190 | ||
1191 | case M_LA_TLS_GD: | |
1192 | pcrel_load (rd, rd, imm_expr, "addi", | |
1193 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1194 | break; | |
1195 | ||
1196 | case M_LA_TLS_IE: | |
1197 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
1198 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1199 | break; | |
1200 | ||
1201 | case M_LB: | |
1202 | pcrel_load (rd, rd, imm_expr, "lb", | |
1203 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1204 | break; | |
1205 | ||
1206 | case M_LBU: | |
1207 | pcrel_load (rd, rd, imm_expr, "lbu", | |
1208 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1209 | break; | |
1210 | ||
1211 | case M_LH: | |
1212 | pcrel_load (rd, rd, imm_expr, "lh", | |
1213 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1214 | break; | |
1215 | ||
1216 | case M_LHU: | |
1217 | pcrel_load (rd, rd, imm_expr, "lhu", | |
1218 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1219 | break; | |
1220 | ||
1221 | case M_LW: | |
1222 | pcrel_load (rd, rd, imm_expr, "lw", | |
1223 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1224 | break; | |
1225 | ||
1226 | case M_LWU: | |
1227 | pcrel_load (rd, rd, imm_expr, "lwu", | |
1228 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1229 | break; | |
1230 | ||
1231 | case M_LD: | |
1232 | pcrel_load (rd, rd, imm_expr, "ld", | |
1233 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1234 | break; | |
1235 | ||
1236 | case M_FLW: | |
1237 | pcrel_load (rd, rs1, imm_expr, "flw", | |
1238 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1239 | break; | |
1240 | ||
1241 | case M_FLD: | |
1242 | pcrel_load (rd, rs1, imm_expr, "fld", | |
1243 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1244 | break; | |
1245 | ||
1246 | case M_SB: | |
1247 | pcrel_store (rs2, rs1, imm_expr, "sb", | |
1248 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1249 | break; | |
1250 | ||
1251 | case M_SH: | |
1252 | pcrel_store (rs2, rs1, imm_expr, "sh", | |
1253 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1254 | break; | |
1255 | ||
1256 | case M_SW: | |
1257 | pcrel_store (rs2, rs1, imm_expr, "sw", | |
1258 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1259 | break; | |
1260 | ||
1261 | case M_SD: | |
1262 | pcrel_store (rs2, rs1, imm_expr, "sd", | |
1263 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1264 | break; | |
1265 | ||
1266 | case M_FSW: | |
1267 | pcrel_store (rs2, rs1, imm_expr, "fsw", | |
1268 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1269 | break; | |
1270 | ||
1271 | case M_FSD: | |
1272 | pcrel_store (rs2, rs1, imm_expr, "fsd", | |
1273 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1274 | break; | |
1275 | ||
1276 | case M_CALL: | |
1277 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
1278 | break; | |
1279 | ||
1280 | default: | |
1281 | as_bad (_("Macro %s not implemented"), ip->insn_mo->name); | |
1282 | break; | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | static const struct percent_op_match percent_op_utype[] = | |
1287 | { | |
1288 | {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, | |
1289 | {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
1290 | {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, | |
1291 | {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
1292 | {"%hi", BFD_RELOC_RISCV_HI20}, | |
1293 | {0, 0} | |
1294 | }; | |
1295 | ||
1296 | static const struct percent_op_match percent_op_itype[] = | |
1297 | { | |
1298 | {"%lo", BFD_RELOC_RISCV_LO12_I}, | |
1299 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
1300 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
1301 | {0, 0} | |
1302 | }; | |
1303 | ||
1304 | static const struct percent_op_match percent_op_stype[] = | |
1305 | { | |
1306 | {"%lo", BFD_RELOC_RISCV_LO12_S}, | |
1307 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
1308 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
1309 | {0, 0} | |
1310 | }; | |
1311 | ||
1312 | static const struct percent_op_match percent_op_rtype[] = | |
1313 | { | |
1314 | {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, | |
1315 | {0, 0} | |
1316 | }; | |
1317 | ||
1318 | /* Return true if *STR points to a relocation operator. When returning true, | |
1319 | move *STR over the operator and store its relocation code in *RELOC. | |
1320 | Leave both *STR and *RELOC alone when returning false. */ | |
1321 | ||
1322 | static bfd_boolean | |
1323 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, | |
1324 | const struct percent_op_match *percent_op) | |
1325 | { | |
1326 | for ( ; percent_op->str; percent_op++) | |
1327 | if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) | |
1328 | { | |
1329 | int len = strlen (percent_op->str); | |
1330 | ||
1331 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
1332 | continue; | |
1333 | ||
1334 | *str += strlen (percent_op->str); | |
1335 | *reloc = percent_op->reloc; | |
1336 | ||
1337 | /* Check whether the output BFD supports this relocation. | |
1338 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
1339 | if (*reloc != BFD_RELOC_UNUSED |
1340 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 NC |
1341 | { |
1342 | as_bad ("relocation %s isn't supported by the current ABI", | |
1343 | percent_op->str); | |
1344 | *reloc = BFD_RELOC_UNUSED; | |
1345 | } | |
1346 | return TRUE; | |
1347 | } | |
1348 | return FALSE; | |
1349 | } | |
1350 | ||
1351 | static void | |
1352 | my_getExpression (expressionS *ep, char *str) | |
1353 | { | |
1354 | char *save_in; | |
1355 | ||
1356 | save_in = input_line_pointer; | |
1357 | input_line_pointer = str; | |
1358 | expression (ep); | |
1359 | expr_end = input_line_pointer; | |
1360 | input_line_pointer = save_in; | |
1361 | } | |
1362 | ||
1363 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
1364 | expression in *EP and the relocation, if any, in RELOC. | |
1365 | Return the number of relocation operators used (0 or 1). | |
1366 | ||
1367 | On exit, EXPR_END points to the first character after the expression. */ | |
1368 | ||
1369 | static size_t | |
1370 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1371 | char *str, const struct percent_op_match *percent_op) | |
1372 | { | |
1373 | size_t reloc_index; | |
1374 | unsigned crux_depth, str_depth, regno; | |
1375 | char *crux; | |
1376 | ||
1377 | /* First, check for integer registers. */ | |
1378 | if (reg_lookup (&str, RCLASS_GPR, ®no)) | |
1379 | { | |
1380 | ep->X_op = O_register; | |
1381 | ep->X_add_number = regno; | |
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | /* Search for the start of the main expression. | |
1386 | End the loop with CRUX pointing to the start | |
1387 | of the main expression and with CRUX_DEPTH containing the number | |
1388 | of open brackets at that point. */ | |
1389 | reloc_index = -1; | |
1390 | str_depth = 0; | |
1391 | do | |
1392 | { | |
1393 | reloc_index++; | |
1394 | crux = str; | |
1395 | crux_depth = str_depth; | |
1396 | ||
1397 | /* Skip over whitespace and brackets, keeping count of the number | |
1398 | of brackets. */ | |
1399 | while (*str == ' ' || *str == '\t' || *str == '(') | |
1400 | if (*str++ == '(') | |
1401 | str_depth++; | |
1402 | } | |
1403 | while (*str == '%' | |
1404 | && reloc_index < 1 | |
1405 | && parse_relocation (&str, reloc, percent_op)); | |
1406 | ||
1407 | my_getExpression (ep, crux); | |
1408 | str = expr_end; | |
1409 | ||
1410 | /* Match every open bracket. */ | |
1411 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
1412 | if (*str++ == ')') | |
1413 | crux_depth--; | |
1414 | ||
1415 | if (crux_depth > 0) | |
1416 | as_bad ("unclosed '('"); | |
1417 | ||
1418 | expr_end = str; | |
1419 | ||
1420 | return reloc_index; | |
1421 | } | |
1422 | ||
0e35537d JW |
1423 | /* Parse opcode name, could be an mnemonics or number. */ |
1424 | static size_t | |
1425 | my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1426 | char *str, const struct percent_op_match *percent_op) | |
1427 | { | |
1428 | const struct opcode_name_t *o = opcode_name_lookup (&str); | |
1429 | ||
1430 | if (o != NULL) | |
1431 | { | |
1432 | ep->X_op = O_constant; | |
1433 | ep->X_add_number = o->val; | |
1434 | return 0; | |
1435 | } | |
1436 | ||
1437 | return my_getSmallExpression (ep, reloc, str, percent_op); | |
1438 | } | |
1439 | ||
f0531ed6 JW |
1440 | /* Detect and handle implicitly zero load-store offsets. For example, |
1441 | "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such | |
1442 | an implicit offset was detected. */ | |
1443 | ||
1444 | static bfd_boolean | |
89424b1d | 1445 | riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) |
f0531ed6 JW |
1446 | { |
1447 | /* Check whether there is only a single bracketed expression left. | |
1448 | If so, it must be the base register and the constant must be zero. */ | |
1449 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
1450 | { | |
89424b1d MR |
1451 | ep->X_op = O_constant; |
1452 | ep->X_add_number = 0; | |
f0531ed6 JW |
1453 | return TRUE; |
1454 | } | |
1455 | ||
1456 | return FALSE; | |
1457 | } | |
1458 | ||
e23eba97 NC |
1459 | /* This routine assembles an instruction into its binary format. As a |
1460 | side effect, it sets the global variable imm_reloc to the type of | |
1461 | relocation to do if one of the operands is an address expression. */ | |
1462 | ||
1463 | static const char * | |
1464 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, | |
0e35537d | 1465 | bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash) |
e23eba97 NC |
1466 | { |
1467 | char *s; | |
1468 | const char *args; | |
1469 | char c = 0; | |
1470 | struct riscv_opcode *insn; | |
1471 | char *argsStart; | |
1472 | unsigned int regno; | |
1473 | char save_c = 0; | |
1474 | int argnum; | |
1475 | const struct percent_op_match *p; | |
1476 | const char *error = "unrecognized opcode"; | |
1477 | ||
1478 | /* Parse the name of the instruction. Terminate the string if whitespace | |
1479 | is found so that hash_find only sees the name part of the string. */ | |
1480 | for (s = str; *s != '\0'; ++s) | |
1481 | if (ISSPACE (*s)) | |
1482 | { | |
1483 | save_c = *s; | |
1484 | *s++ = '\0'; | |
1485 | break; | |
1486 | } | |
1487 | ||
0e35537d | 1488 | insn = (struct riscv_opcode *) hash_find (hash, str); |
e23eba97 NC |
1489 | |
1490 | argsStart = s; | |
1491 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) | |
1492 | { | |
43135d3b | 1493 | if (!riscv_multi_subset_supports (insn->xlen_requirement, insn->subset)) |
e23eba97 NC |
1494 | continue; |
1495 | ||
1496 | create_insn (ip, insn); | |
1497 | argnum = 1; | |
1498 | ||
1499 | imm_expr->X_op = O_absent; | |
1500 | *imm_reloc = BFD_RELOC_UNUSED; | |
1501 | p = percent_op_itype; | |
1502 | ||
1503 | for (args = insn->args;; ++args) | |
1504 | { | |
1505 | s += strspn (s, " \t"); | |
1506 | switch (*args) | |
1507 | { | |
1508 | case '\0': /* End of args. */ | |
1509 | if (insn->pinfo != INSN_MACRO) | |
1510 | { | |
1511 | if (!insn->match_func (insn, ip->insn_opcode)) | |
1512 | break; | |
0e35537d JW |
1513 | |
1514 | /* For .insn, insn->match and insn->mask are 0. */ | |
1515 | if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) | |
1516 | ? ip->insn_opcode | |
1517 | : insn->match) == 2 | |
1518 | && !riscv_opts.rvc) | |
e23eba97 NC |
1519 | break; |
1520 | } | |
1521 | if (*s != '\0') | |
1522 | break; | |
1523 | /* Successful assembly. */ | |
1524 | error = NULL; | |
1525 | goto out; | |
1526 | ||
1527 | case 'C': /* RVC */ | |
1528 | switch (*++args) | |
1529 | { | |
1530 | case 's': /* RS1 x8-x15 */ | |
1531 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1532 | || !(regno >= 8 && regno <= 15)) | |
1533 | break; | |
1534 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1535 | continue; | |
1536 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
1537 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1538 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) | |
1539 | break; | |
1540 | continue; | |
1541 | case 't': /* RS2 x8-x15 */ | |
1542 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1543 | || !(regno >= 8 && regno <= 15)) | |
1544 | break; | |
1545 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1546 | continue; | |
1547 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
1548 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1549 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) | |
1550 | break; | |
1551 | continue; | |
1552 | case 'U': /* RS1, constrained to equal RD. */ | |
1553 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1554 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) | |
1555 | break; | |
1556 | continue; | |
1557 | case 'V': /* RS2 */ | |
1558 | if (!reg_lookup (&s, RCLASS_GPR, ®no)) | |
1559 | break; | |
1560 | INSERT_OPERAND (CRS2, *ip, regno); | |
1561 | continue; | |
1562 | case 'c': /* RS1, constrained to equal sp. */ | |
1563 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1564 | || regno != X_SP) | |
1565 | break; | |
1566 | continue; | |
1567 | case '>': | |
1568 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1569 | || imm_expr->X_op != O_constant | |
1570 | || imm_expr->X_add_number <= 0 | |
1571 | || imm_expr->X_add_number >= 64) | |
1572 | break; | |
1573 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1574 | rvc_imm_done: | |
1575 | s = expr_end; | |
1576 | imm_expr->X_op = O_absent; | |
1577 | continue; | |
1578 | case '<': | |
1579 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1580 | || imm_expr->X_op != O_constant | |
1581 | || !VALID_RVC_IMM (imm_expr->X_add_number) | |
1582 | || imm_expr->X_add_number <= 0 | |
1583 | || imm_expr->X_add_number >= 32) | |
1584 | break; | |
1585 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1586 | goto rvc_imm_done; | |
0e35537d JW |
1587 | case '8': |
1588 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1589 | || imm_expr->X_op != O_constant | |
1590 | || !VALID_RVC_UIMM8 (imm_expr->X_add_number) | |
1591 | || imm_expr->X_add_number < 0 | |
1592 | || imm_expr->X_add_number >= 256) | |
1593 | break; | |
1594 | ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number); | |
1595 | goto rvc_imm_done; | |
e23eba97 NC |
1596 | case 'i': |
1597 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1598 | || imm_expr->X_op != O_constant | |
1599 | || imm_expr->X_add_number == 0 | |
1600 | || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) | |
1601 | break; | |
1602 | ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); | |
1603 | goto rvc_imm_done; | |
1604 | case 'j': | |
1605 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1606 | || imm_expr->X_op != O_constant | |
1607 | || imm_expr->X_add_number == 0 | |
1608 | || !VALID_RVC_IMM (imm_expr->X_add_number)) | |
1609 | break; | |
1610 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1611 | goto rvc_imm_done; | |
1612 | case 'k': | |
f0531ed6 JW |
1613 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1614 | continue; | |
e23eba97 NC |
1615 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1616 | || imm_expr->X_op != O_constant | |
1617 | || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) | |
1618 | break; | |
1619 | ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); | |
1620 | goto rvc_imm_done; | |
1621 | case 'l': | |
f0531ed6 JW |
1622 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1623 | continue; | |
e23eba97 NC |
1624 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1625 | || imm_expr->X_op != O_constant | |
1626 | || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) | |
1627 | break; | |
1628 | ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); | |
1629 | goto rvc_imm_done; | |
1630 | case 'm': | |
f0531ed6 JW |
1631 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1632 | continue; | |
e23eba97 NC |
1633 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1634 | || imm_expr->X_op != O_constant | |
1635 | || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) | |
1636 | break; | |
1637 | ip->insn_opcode |= | |
1638 | ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); | |
1639 | goto rvc_imm_done; | |
1640 | case 'n': | |
f0531ed6 JW |
1641 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1642 | continue; | |
e23eba97 NC |
1643 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1644 | || imm_expr->X_op != O_constant | |
1645 | || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) | |
1646 | break; | |
1647 | ip->insn_opcode |= | |
1648 | ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); | |
1649 | goto rvc_imm_done; | |
b416fe87 KC |
1650 | case 'o': |
1651 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1652 | || imm_expr->X_op != O_constant | |
21a186f2 JW |
1653 | /* C.addiw, c.li, and c.andi allow zero immediate. |
1654 | C.addi allows zero immediate as hint. Otherwise this | |
1655 | is same as 'j'. */ | |
b416fe87 KC |
1656 | || !VALID_RVC_IMM (imm_expr->X_add_number)) |
1657 | break; | |
1658 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1659 | goto rvc_imm_done; | |
e23eba97 NC |
1660 | case 'K': |
1661 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1662 | || imm_expr->X_op != O_constant | |
1663 | || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) | |
1664 | || imm_expr->X_add_number == 0) | |
1665 | break; | |
1666 | ip->insn_opcode |= | |
1667 | ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); | |
1668 | goto rvc_imm_done; | |
1669 | case 'L': | |
1670 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1671 | || imm_expr->X_op != O_constant | |
1672 | || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) | |
1673 | || imm_expr->X_add_number == 0) | |
1674 | break; | |
1675 | ip->insn_opcode |= | |
1676 | ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); | |
1677 | goto rvc_imm_done; | |
1678 | case 'M': | |
f0531ed6 JW |
1679 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1680 | continue; | |
e23eba97 NC |
1681 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1682 | || imm_expr->X_op != O_constant | |
1683 | || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) | |
1684 | break; | |
1685 | ip->insn_opcode |= | |
1686 | ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); | |
1687 | goto rvc_imm_done; | |
1688 | case 'N': | |
f0531ed6 JW |
1689 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1690 | continue; | |
e23eba97 NC |
1691 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1692 | || imm_expr->X_op != O_constant | |
1693 | || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) | |
1694 | break; | |
1695 | ip->insn_opcode |= | |
1696 | ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); | |
1697 | goto rvc_imm_done; | |
1698 | case 'u': | |
1699 | p = percent_op_utype; | |
1700 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1701 | break; | |
1702 | rvc_lui: | |
1703 | if (imm_expr->X_op != O_constant | |
1704 | || imm_expr->X_add_number <= 0 | |
1705 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
1706 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
1707 | && (imm_expr->X_add_number < | |
1708 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
1709 | break; | |
1710 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1711 | goto rvc_imm_done; | |
1712 | case 'v': | |
1713 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1714 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) | |
1715 | || ((int32_t)imm_expr->X_add_number | |
1716 | != imm_expr->X_add_number)) | |
1717 | break; | |
1718 | imm_expr->X_add_number = | |
1719 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
1720 | goto rvc_lui; | |
1721 | case 'p': | |
1722 | goto branch; | |
1723 | case 'a': | |
1724 | goto jump; | |
0e35537d JW |
1725 | case 'S': /* Floating-point RS1 x8-x15. */ |
1726 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1727 | || !(regno >= 8 && regno <= 15)) | |
1728 | break; | |
1729 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1730 | continue; | |
e23eba97 NC |
1731 | case 'D': /* Floating-point RS2 x8-x15. */ |
1732 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1733 | || !(regno >= 8 && regno <= 15)) | |
1734 | break; | |
1735 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1736 | continue; | |
1737 | case 'T': /* Floating-point RS2. */ | |
1738 | if (!reg_lookup (&s, RCLASS_FPR, ®no)) | |
1739 | break; | |
1740 | INSERT_OPERAND (CRS2, *ip, regno); | |
1741 | continue; | |
0e35537d JW |
1742 | case 'F': |
1743 | switch (*++args) | |
1744 | { | |
1745 | case '4': | |
1746 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1747 | || imm_expr->X_op != O_constant | |
1748 | || imm_expr->X_add_number < 0 | |
1749 | || imm_expr->X_add_number >= 16) | |
1750 | { | |
1751 | as_bad (_("bad value for funct4 field, " | |
1752 | "value must be 0...15")); | |
1753 | break; | |
1754 | } | |
1755 | ||
1756 | INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); | |
1757 | imm_expr->X_op = O_absent; | |
1758 | s = expr_end; | |
1759 | continue; | |
1760 | case '3': | |
1761 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1762 | || imm_expr->X_op != O_constant | |
1763 | || imm_expr->X_add_number < 0 | |
1764 | || imm_expr->X_add_number >= 8) | |
1765 | { | |
1766 | as_bad (_("bad value for funct3 field, " | |
1767 | "value must be 0...7")); | |
1768 | break; | |
1769 | } | |
1770 | INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); | |
1771 | imm_expr->X_op = O_absent; | |
1772 | s = expr_end; | |
1773 | continue; | |
1774 | default: | |
1775 | as_bad (_("bad compressed FUNCT field" | |
1776 | " specifier 'CF%c'\n"), | |
1777 | *args); | |
1778 | } | |
1779 | break; | |
1780 | ||
e23eba97 NC |
1781 | default: |
1782 | as_bad (_("bad RVC field specifier 'C%c'\n"), *args); | |
1783 | } | |
1784 | break; | |
1785 | ||
1786 | case ',': | |
1787 | ++argnum; | |
1788 | if (*s++ == *args) | |
1789 | continue; | |
1790 | s--; | |
1791 | break; | |
1792 | ||
1793 | case '(': | |
1794 | case ')': | |
1795 | case '[': | |
1796 | case ']': | |
1797 | if (*s++ == *args) | |
1798 | continue; | |
1799 | break; | |
1800 | ||
1801 | case '<': /* Shift amount, 0 - 31. */ | |
1802 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1803 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1804 | if ((unsigned long) imm_expr->X_add_number > 31) |
94f78a77 AW |
1805 | as_bad (_("Improper shift amount (%lu)"), |
1806 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1807 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); |
1808 | imm_expr->X_op = O_absent; | |
1809 | s = expr_end; | |
1810 | continue; | |
1811 | ||
1812 | case '>': /* Shift amount, 0 - (XLEN-1). */ | |
1813 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1814 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1815 | if ((unsigned long) imm_expr->X_add_number >= xlen) |
94f78a77 AW |
1816 | as_bad (_("Improper shift amount (%lu)"), |
1817 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1818 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); |
1819 | imm_expr->X_op = O_absent; | |
1820 | s = expr_end; | |
1821 | continue; | |
1822 | ||
1823 | case 'Z': /* CSRRxI immediate. */ | |
1824 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1825 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1826 | if ((unsigned long) imm_expr->X_add_number > 31) |
94f78a77 AW |
1827 | as_bad (_("Improper CSRxI immediate (%lu)"), |
1828 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1829 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); |
1830 | imm_expr->X_op = O_absent; | |
1831 | s = expr_end; | |
1832 | continue; | |
1833 | ||
1834 | case 'E': /* Control register. */ | |
1835 | if (reg_lookup (&s, RCLASS_CSR, ®no)) | |
1836 | INSERT_OPERAND (CSR, *ip, regno); | |
1837 | else | |
1838 | { | |
1839 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1840 | check_absolute_expr (ip, imm_expr, TRUE); |
e23eba97 | 1841 | if ((unsigned long) imm_expr->X_add_number > 0xfff) |
94f78a77 AW |
1842 | as_bad (_("Improper CSR address (%lu)"), |
1843 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1844 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
1845 | imm_expr->X_op = O_absent; | |
1846 | s = expr_end; | |
1847 | } | |
1848 | continue; | |
1849 | ||
1850 | case 'm': /* Rounding mode. */ | |
1851 | if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) | |
1852 | { | |
1853 | INSERT_OPERAND (RM, *ip, regno); | |
1854 | continue; | |
1855 | } | |
1856 | break; | |
1857 | ||
1858 | case 'P': | |
1859 | case 'Q': /* Fence predecessor/successor. */ | |
1860 | if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), | |
1861 | ®no)) | |
1862 | { | |
1863 | if (*args == 'P') | |
1864 | INSERT_OPERAND (PRED, *ip, regno); | |
1865 | else | |
1866 | INSERT_OPERAND (SUCC, *ip, regno); | |
1867 | continue; | |
1868 | } | |
1869 | break; | |
1870 | ||
1871 | case 'd': /* Destination register. */ | |
1872 | case 's': /* Source register. */ | |
1873 | case 't': /* Target register. */ | |
0e35537d | 1874 | case 'r': /* rs3. */ |
e23eba97 NC |
1875 | if (reg_lookup (&s, RCLASS_GPR, ®no)) |
1876 | { | |
1877 | c = *args; | |
1878 | if (*s == ' ') | |
1879 | ++s; | |
1880 | ||
1881 | /* Now that we have assembled one operand, we use the args | |
1882 | string to figure out where it goes in the instruction. */ | |
1883 | switch (c) | |
1884 | { | |
1885 | case 's': | |
1886 | INSERT_OPERAND (RS1, *ip, regno); | |
1887 | break; | |
1888 | case 'd': | |
1889 | INSERT_OPERAND (RD, *ip, regno); | |
1890 | break; | |
1891 | case 't': | |
1892 | INSERT_OPERAND (RS2, *ip, regno); | |
1893 | break; | |
0e35537d JW |
1894 | case 'r': |
1895 | INSERT_OPERAND (RS3, *ip, regno); | |
1896 | break; | |
e23eba97 NC |
1897 | } |
1898 | continue; | |
1899 | } | |
1900 | break; | |
1901 | ||
1902 | case 'D': /* Floating point rd. */ | |
1903 | case 'S': /* Floating point rs1. */ | |
1904 | case 'T': /* Floating point rs2. */ | |
1905 | case 'U': /* Floating point rs1 and rs2. */ | |
1906 | case 'R': /* Floating point rs3. */ | |
1907 | if (reg_lookup (&s, RCLASS_FPR, ®no)) | |
1908 | { | |
1909 | c = *args; | |
1910 | if (*s == ' ') | |
1911 | ++s; | |
1912 | switch (c) | |
1913 | { | |
1914 | case 'D': | |
1915 | INSERT_OPERAND (RD, *ip, regno); | |
1916 | break; | |
1917 | case 'S': | |
1918 | INSERT_OPERAND (RS1, *ip, regno); | |
1919 | break; | |
1920 | case 'U': | |
1921 | INSERT_OPERAND (RS1, *ip, regno); | |
1922 | /* fallthru */ | |
1923 | case 'T': | |
1924 | INSERT_OPERAND (RS2, *ip, regno); | |
1925 | break; | |
1926 | case 'R': | |
1927 | INSERT_OPERAND (RS3, *ip, regno); | |
1928 | break; | |
1929 | } | |
1930 | continue; | |
1931 | } | |
1932 | ||
1933 | break; | |
1934 | ||
1935 | case 'I': | |
1936 | my_getExpression (imm_expr, s); | |
1937 | if (imm_expr->X_op != O_big | |
1938 | && imm_expr->X_op != O_constant) | |
1939 | break; | |
1940 | normalize_constant_expr (imm_expr); | |
1941 | s = expr_end; | |
1942 | continue; | |
1943 | ||
1944 | case 'A': | |
1945 | my_getExpression (imm_expr, s); | |
1946 | normalize_constant_expr (imm_expr); | |
1947 | /* The 'A' format specifier must be a symbol. */ | |
1948 | if (imm_expr->X_op != O_symbol) | |
1949 | break; | |
1950 | *imm_reloc = BFD_RELOC_32; | |
1951 | s = expr_end; | |
1952 | continue; | |
1953 | ||
160d1b3d SH |
1954 | case 'B': |
1955 | my_getExpression (imm_expr, s); | |
1956 | normalize_constant_expr (imm_expr); | |
1957 | /* The 'B' format specifier must be a symbol or a constant. */ | |
1958 | if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) | |
1959 | break; | |
1960 | if (imm_expr->X_op == O_symbol) | |
1961 | *imm_reloc = BFD_RELOC_32; | |
1962 | s = expr_end; | |
1963 | continue; | |
1964 | ||
e23eba97 NC |
1965 | case 'j': /* Sign-extended immediate. */ |
1966 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
1967 | p = percent_op_itype; | |
1968 | goto alu_op; | |
1969 | case 'q': /* Store displacement. */ | |
1970 | p = percent_op_stype; | |
1971 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
1972 | goto load_store; | |
1973 | case 'o': /* Load displacement. */ | |
1974 | p = percent_op_itype; | |
1975 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
1976 | goto load_store; | |
1977 | case '0': /* AMO "displacement," which must be zero. */ | |
1978 | p = percent_op_rtype; | |
1979 | *imm_reloc = BFD_RELOC_UNUSED; | |
1980 | load_store: | |
f0531ed6 | 1981 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
e23eba97 NC |
1982 | continue; |
1983 | alu_op: | |
1984 | /* If this value won't fit into a 16 bit offset, then go | |
1985 | find a macro that will generate the 32 bit offset | |
1986 | code pattern. */ | |
1987 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1988 | { | |
1989 | normalize_constant_expr (imm_expr); | |
1990 | if (imm_expr->X_op != O_constant | |
1991 | || (*args == '0' && imm_expr->X_add_number != 0) | |
1992 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 | |
1993 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
1994 | break; | |
1995 | } | |
1996 | ||
1997 | s = expr_end; | |
1998 | continue; | |
1999 | ||
2000 | case 'p': /* PC-relative offset. */ | |
2001 | branch: | |
2002 | *imm_reloc = BFD_RELOC_12_PCREL; | |
2003 | my_getExpression (imm_expr, s); | |
2004 | s = expr_end; | |
2005 | continue; | |
2006 | ||
2007 | case 'u': /* Upper 20 bits. */ | |
2008 | p = percent_op_utype; | |
2009 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2010 | && imm_expr->X_op == O_constant) | |
2011 | { | |
2012 | if (imm_expr->X_add_number < 0 | |
2013 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
2014 | as_bad (_("lui expression not in range 0..1048575")); | |
2015 | ||
2016 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
2017 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
2018 | } | |
2019 | s = expr_end; | |
2020 | continue; | |
2021 | ||
2022 | case 'a': /* 20-bit PC-relative offset. */ | |
2023 | jump: | |
2024 | my_getExpression (imm_expr, s); | |
2025 | s = expr_end; | |
2026 | *imm_reloc = BFD_RELOC_RISCV_JMP; | |
2027 | continue; | |
2028 | ||
2029 | case 'c': | |
2030 | my_getExpression (imm_expr, s); | |
2031 | s = expr_end; | |
2032 | if (strcmp (s, "@plt") == 0) | |
2033 | { | |
2034 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
2035 | s += 4; | |
2036 | } | |
2037 | else | |
2038 | *imm_reloc = BFD_RELOC_RISCV_CALL; | |
2039 | continue; | |
0e35537d JW |
2040 | case 'O': |
2041 | switch (*++args) | |
2042 | { | |
2043 | case '4': | |
2044 | if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) | |
2045 | || imm_expr->X_op != O_constant | |
2046 | || imm_expr->X_add_number < 0 | |
2047 | || imm_expr->X_add_number >= 128 | |
2048 | || (imm_expr->X_add_number & 0x3) != 3) | |
2049 | { | |
2050 | as_bad (_("bad value for opcode field, " | |
2051 | "value must be 0...127 and " | |
2052 | "lower 2 bits must be 0x3")); | |
2053 | break; | |
2054 | } | |
2055 | ||
2056 | INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); | |
2057 | imm_expr->X_op = O_absent; | |
2058 | s = expr_end; | |
2059 | continue; | |
2060 | case '2': | |
2061 | if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) | |
2062 | || imm_expr->X_op != O_constant | |
2063 | || imm_expr->X_add_number < 0 | |
2064 | || imm_expr->X_add_number >= 3) | |
2065 | { | |
2066 | as_bad (_("bad value for opcode field, " | |
2067 | "value must be 0...2")); | |
2068 | break; | |
2069 | } | |
2070 | ||
2071 | INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); | |
2072 | imm_expr->X_op = O_absent; | |
2073 | s = expr_end; | |
2074 | continue; | |
2075 | default: | |
2076 | as_bad (_("bad Opcode field specifier 'O%c'\n"), *args); | |
2077 | } | |
2078 | break; | |
2079 | ||
2080 | case 'F': | |
2081 | switch (*++args) | |
2082 | { | |
2083 | case '7': | |
2084 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2085 | || imm_expr->X_op != O_constant | |
2086 | || imm_expr->X_add_number < 0 | |
2087 | || imm_expr->X_add_number >= 128) | |
2088 | { | |
2089 | as_bad (_("bad value for funct7 field, " | |
2090 | "value must be 0...127")); | |
2091 | break; | |
2092 | } | |
2093 | ||
2094 | INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); | |
2095 | imm_expr->X_op = O_absent; | |
2096 | s = expr_end; | |
2097 | continue; | |
2098 | case '3': | |
2099 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2100 | || imm_expr->X_op != O_constant | |
2101 | || imm_expr->X_add_number < 0 | |
2102 | || imm_expr->X_add_number >= 8) | |
2103 | { | |
2104 | as_bad (_("bad value for funct3 field, " | |
2105 | "value must be 0...7")); | |
2106 | break; | |
2107 | } | |
2108 | ||
2109 | INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); | |
2110 | imm_expr->X_op = O_absent; | |
2111 | s = expr_end; | |
2112 | continue; | |
2113 | case '2': | |
2114 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2115 | || imm_expr->X_op != O_constant | |
2116 | || imm_expr->X_add_number < 0 | |
2117 | || imm_expr->X_add_number >= 4) | |
2118 | { | |
2119 | as_bad (_("bad value for funct2 field, " | |
2120 | "value must be 0...3")); | |
2121 | break; | |
2122 | } | |
2123 | ||
2124 | INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); | |
2125 | imm_expr->X_op = O_absent; | |
2126 | s = expr_end; | |
2127 | continue; | |
2128 | ||
2129 | default: | |
2130 | as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args); | |
2131 | } | |
2132 | break; | |
e23eba97 | 2133 | |
e925c834 JW |
2134 | case 'z': |
2135 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2136 | || imm_expr->X_op != O_constant | |
2137 | || imm_expr->X_add_number != 0) | |
2138 | break; | |
2139 | s = expr_end; | |
2140 | imm_expr->X_op = O_absent; | |
2141 | continue; | |
2142 | ||
e23eba97 NC |
2143 | default: |
2144 | as_fatal (_("internal error: bad argument type %c"), *args); | |
2145 | } | |
2146 | break; | |
2147 | } | |
2148 | s = argsStart; | |
2149 | error = _("illegal operands"); | |
2150 | } | |
2151 | ||
2152 | out: | |
2153 | /* Restore the character we might have clobbered above. */ | |
2154 | if (save_c) | |
2155 | *(argsStart - 1) = save_c; | |
2156 | ||
2157 | return error; | |
2158 | } | |
2159 | ||
2160 | void | |
2161 | md_assemble (char *str) | |
2162 | { | |
2163 | struct riscv_cl_insn insn; | |
2164 | expressionS imm_expr; | |
2165 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
2166 | ||
0e35537d | 2167 | const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); |
e23eba97 NC |
2168 | |
2169 | if (error) | |
2170 | { | |
2171 | as_bad ("%s `%s'", error, str); | |
2172 | return; | |
2173 | } | |
2174 | ||
2175 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2176 | macro (&insn, &imm_expr, &imm_reloc); | |
2177 | else | |
2178 | append_insn (&insn, &imm_expr, imm_reloc); | |
2179 | } | |
2180 | ||
2181 | const char * | |
2182 | md_atof (int type, char *litP, int *sizeP) | |
2183 | { | |
2184 | return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); | |
2185 | } | |
2186 | ||
2187 | void | |
2188 | md_number_to_chars (char *buf, valueT val, int n) | |
2189 | { | |
2190 | number_to_chars_littleendian (buf, val, n); | |
2191 | } | |
2192 | ||
2193 | const char *md_shortopts = "O::g::G:"; | |
2194 | ||
2195 | enum options | |
2196 | { | |
2922d21d | 2197 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
2198 | OPTION_PIC, |
2199 | OPTION_NO_PIC, | |
2922d21d | 2200 | OPTION_MABI, |
71060565 JW |
2201 | OPTION_RELAX, |
2202 | OPTION_NO_RELAX, | |
e23eba97 NC |
2203 | OPTION_END_OF_ENUM |
2204 | }; | |
2205 | ||
2206 | struct option md_longopts[] = | |
2207 | { | |
e23eba97 NC |
2208 | {"march", required_argument, NULL, OPTION_MARCH}, |
2209 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
2210 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
2211 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 2212 | {"mabi", required_argument, NULL, OPTION_MABI}, |
71060565 JW |
2213 | {"mrelax", no_argument, NULL, OPTION_RELAX}, |
2214 | {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
e23eba97 NC |
2215 | |
2216 | {NULL, no_argument, NULL, 0} | |
2217 | }; | |
2218 | size_t md_longopts_size = sizeof (md_longopts); | |
2219 | ||
2922d21d AW |
2220 | enum float_abi { |
2221 | FLOAT_ABI_DEFAULT = -1, | |
2222 | FLOAT_ABI_SOFT, | |
2223 | FLOAT_ABI_SINGLE, | |
2224 | FLOAT_ABI_DOUBLE, | |
2225 | FLOAT_ABI_QUAD | |
e23eba97 | 2226 | }; |
2922d21d AW |
2227 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; |
2228 | ||
2229 | static void | |
7f999549 | 2230 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve) |
2922d21d AW |
2231 | { |
2232 | abi_xlen = new_xlen; | |
2233 | float_abi = new_float_abi; | |
7f999549 | 2234 | rve_abi = rve; |
2922d21d | 2235 | } |
e23eba97 NC |
2236 | |
2237 | int | |
2238 | md_parse_option (int c, const char *arg) | |
2239 | { | |
2240 | switch (c) | |
2241 | { | |
e23eba97 NC |
2242 | case OPTION_MARCH: |
2243 | riscv_set_arch (arg); | |
2244 | break; | |
2245 | ||
2246 | case OPTION_NO_PIC: | |
2247 | riscv_opts.pic = FALSE; | |
2248 | break; | |
2249 | ||
2250 | case OPTION_PIC: | |
2251 | riscv_opts.pic = TRUE; | |
2252 | break; | |
2253 | ||
2922d21d AW |
2254 | case OPTION_MABI: |
2255 | if (strcmp (arg, "ilp32") == 0) | |
7f999549 JW |
2256 | riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE); |
2257 | else if (strcmp (arg, "ilp32e") == 0) | |
2258 | riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE); | |
2922d21d | 2259 | else if (strcmp (arg, "ilp32f") == 0) |
7f999549 | 2260 | riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE); |
2922d21d | 2261 | else if (strcmp (arg, "ilp32d") == 0) |
7f999549 | 2262 | riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE); |
2922d21d | 2263 | else if (strcmp (arg, "ilp32q") == 0) |
7f999549 | 2264 | riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE); |
2922d21d | 2265 | else if (strcmp (arg, "lp64") == 0) |
7f999549 | 2266 | riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE); |
2922d21d | 2267 | else if (strcmp (arg, "lp64f") == 0) |
7f999549 | 2268 | riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE); |
2922d21d | 2269 | else if (strcmp (arg, "lp64d") == 0) |
7f999549 | 2270 | riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE); |
2922d21d | 2271 | else if (strcmp (arg, "lp64q") == 0) |
7f999549 | 2272 | riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE); |
2922d21d AW |
2273 | else |
2274 | return 0; | |
2275 | break; | |
2276 | ||
71060565 JW |
2277 | case OPTION_RELAX: |
2278 | riscv_opts.relax = TRUE; | |
2279 | break; | |
2280 | ||
2281 | case OPTION_NO_RELAX: | |
2282 | riscv_opts.relax = FALSE; | |
2283 | break; | |
2284 | ||
e23eba97 NC |
2285 | default: |
2286 | return 0; | |
2287 | } | |
2288 | ||
2289 | return 1; | |
2290 | } | |
2291 | ||
2292 | void | |
2293 | riscv_after_parse_args (void) | |
2294 | { | |
e23eba97 NC |
2295 | if (xlen == 0) |
2296 | { | |
2297 | if (strcmp (default_arch, "riscv32") == 0) | |
2298 | xlen = 32; | |
2299 | else if (strcmp (default_arch, "riscv64") == 0) | |
2300 | xlen = 64; | |
2301 | else | |
2302 | as_bad ("unknown default architecture `%s'", default_arch); | |
2303 | } | |
2922d21d AW |
2304 | |
2305 | if (riscv_subsets == NULL) | |
2306 | riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g"); | |
2307 | ||
2308 | /* Add the RVC extension, regardless of -march, to support .option rvc. */ | |
fecb9c46 | 2309 | riscv_set_rvc (FALSE); |
43135d3b | 2310 | if (riscv_subset_supports (0, "c")) |
2922d21d AW |
2311 | riscv_set_rvc (TRUE); |
2312 | else | |
2313 | riscv_add_subset ("c"); | |
2314 | ||
7f999549 JW |
2315 | /* Enable RVE if specified by the -march option. */ |
2316 | riscv_set_rve (FALSE); | |
43135d3b | 2317 | if (riscv_subset_supports (0, "e")) |
7f999549 JW |
2318 | riscv_set_rve (TRUE); |
2319 | ||
2922d21d AW |
2320 | /* Infer ABI from ISA if not specified on command line. */ |
2321 | if (abi_xlen == 0) | |
2322 | abi_xlen = xlen; | |
2323 | else if (abi_xlen > xlen) | |
2324 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
2325 | else if (abi_xlen < xlen) | |
2326 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
2327 | ||
2328 | if (float_abi == FLOAT_ABI_DEFAULT) | |
2329 | { | |
2330 | struct riscv_subset *subset; | |
2331 | ||
2332 | /* Assume soft-float unless D extension is present. */ | |
2333 | float_abi = FLOAT_ABI_SOFT; | |
2334 | ||
2335 | for (subset = riscv_subsets; subset != NULL; subset = subset->next) | |
cc917fd9 KC |
2336 | { |
2337 | if (strcasecmp (subset->name, "D") == 0) | |
2338 | float_abi = FLOAT_ABI_DOUBLE; | |
2339 | if (strcasecmp (subset->name, "Q") == 0) | |
2340 | float_abi = FLOAT_ABI_QUAD; | |
2341 | } | |
2922d21d AW |
2342 | } |
2343 | ||
7f999549 JW |
2344 | if (rve_abi) |
2345 | elf_flags |= EF_RISCV_RVE; | |
2346 | ||
2922d21d AW |
2347 | /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */ |
2348 | elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1)); | |
e23eba97 NC |
2349 | } |
2350 | ||
2351 | long | |
2352 | md_pcrel_from (fixS *fixP) | |
2353 | { | |
2354 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
2355 | } | |
2356 | ||
2357 | /* Apply a fixup to the object file. */ | |
2358 | ||
2359 | void | |
2360 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
2361 | { | |
45f76423 | 2362 | unsigned int subtype; |
e23eba97 | 2363 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
45f76423 | 2364 | bfd_boolean relaxable = FALSE; |
c1b465c9 | 2365 | offsetT loc; |
a6cbf936 | 2366 | segT sub_segment; |
e23eba97 NC |
2367 | |
2368 | /* Remember value for tc_gen_reloc. */ | |
2369 | fixP->fx_addnumber = *valP; | |
2370 | ||
2371 | switch (fixP->fx_r_type) | |
2372 | { | |
e23eba97 NC |
2373 | case BFD_RELOC_RISCV_HI20: |
2374 | case BFD_RELOC_RISCV_LO12_I: | |
2375 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
2376 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
2377 | | bfd_getl32 (buf), buf); | |
a5ec5e3f AW |
2378 | if (fixP->fx_addsy == NULL) |
2379 | fixP->fx_done = TRUE; | |
45f76423 AW |
2380 | relaxable = TRUE; |
2381 | break; | |
2382 | ||
2383 | case BFD_RELOC_RISCV_GOT_HI20: | |
e23eba97 NC |
2384 | case BFD_RELOC_RISCV_ADD8: |
2385 | case BFD_RELOC_RISCV_ADD16: | |
2386 | case BFD_RELOC_RISCV_ADD32: | |
2387 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 2388 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
2389 | case BFD_RELOC_RISCV_SUB8: |
2390 | case BFD_RELOC_RISCV_SUB16: | |
2391 | case BFD_RELOC_RISCV_SUB32: | |
2392 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 AW |
2393 | case BFD_RELOC_RISCV_RELAX: |
2394 | break; | |
2395 | ||
2396 | case BFD_RELOC_RISCV_TPREL_HI20: | |
2397 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
2398 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
2399 | case BFD_RELOC_RISCV_TPREL_ADD: | |
2400 | relaxable = TRUE; | |
2401 | /* Fall through. */ | |
2402 | ||
2403 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
2404 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
2405 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
2406 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
2407 | if (fixP->fx_addsy != NULL) |
2408 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2409 | else | |
2410 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2411 | _("TLS relocation against a constant")); | |
e23eba97 NC |
2412 | break; |
2413 | ||
e23eba97 | 2414 | case BFD_RELOC_32: |
a6cbf936 KLC |
2415 | /* Use pc-relative relocation for FDE initial location. |
2416 | The symbol address in .eh_frame may be adjusted in | |
2417 | _bfd_elf_discard_section_eh_frame, and the content of | |
2418 | .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. | |
2419 | Therefore, we cannot insert a relocation whose addend symbol is | |
2420 | in .eh_frame. Othrewise, the value may be adjusted twice.*/ | |
2421 | if (fixP->fx_addsy && fixP->fx_subsy | |
2422 | && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) | |
2423 | && strcmp (sub_segment->name, ".eh_frame") == 0 | |
2424 | && S_GET_VALUE (fixP->fx_subsy) | |
2425 | == fixP->fx_frag->fr_address + fixP->fx_where) | |
2426 | { | |
2427 | fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; | |
2428 | fixP->fx_subsy = NULL; | |
2429 | break; | |
2430 | } | |
2431 | /* Fall through. */ | |
2432 | case BFD_RELOC_64: | |
e23eba97 NC |
2433 | case BFD_RELOC_16: |
2434 | case BFD_RELOC_8: | |
45f76423 | 2435 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
2436 | if (fixP->fx_addsy && fixP->fx_subsy) |
2437 | { | |
2438 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2439 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
2440 | fixP->fx_next->fx_subsy = NULL; | |
2441 | fixP->fx_next->fx_offset = 0; | |
2442 | fixP->fx_subsy = NULL; | |
2443 | ||
2444 | switch (fixP->fx_r_type) | |
2445 | { | |
2446 | case BFD_RELOC_64: | |
2447 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
2448 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
2449 | break; | |
2450 | ||
2451 | case BFD_RELOC_32: | |
2452 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
2453 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
2454 | break; | |
2455 | ||
2456 | case BFD_RELOC_16: | |
2457 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
2458 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
2459 | break; | |
2460 | ||
2461 | case BFD_RELOC_8: | |
2462 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
2463 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 2464 | break; |
e23eba97 | 2465 | |
45f76423 AW |
2466 | case BFD_RELOC_RISCV_CFA: |
2467 | /* Load the byte to get the subtype. */ | |
c1b465c9 KLC |
2468 | subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); |
2469 | loc = fixP->fx_frag->fr_fix - (subtype & 7); | |
45f76423 AW |
2470 | switch (subtype) |
2471 | { | |
2472 | case DW_CFA_advance_loc1: | |
c1b465c9 KLC |
2473 | fixP->fx_where = loc + 1; |
2474 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
2475 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; |
2476 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
2477 | break; | |
2478 | ||
2479 | case DW_CFA_advance_loc2: | |
2480 | fixP->fx_size = 2; | |
45f76423 | 2481 | fixP->fx_next->fx_size = 2; |
c1b465c9 KLC |
2482 | fixP->fx_where = loc + 1; |
2483 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
2484 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; |
2485 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
2486 | break; | |
2487 | ||
2488 | case DW_CFA_advance_loc4: | |
2489 | fixP->fx_size = 4; | |
45f76423 | 2490 | fixP->fx_next->fx_size = 4; |
c1b465c9 KLC |
2491 | fixP->fx_where = loc; |
2492 | fixP->fx_next->fx_where = loc; | |
45f76423 AW |
2493 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; |
2494 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
2495 | break; | |
2496 | ||
2497 | default: | |
2498 | if (subtype < 0x80 && (subtype & 0x40)) | |
2499 | { | |
2500 | /* DW_CFA_advance_loc */ | |
2aece2ba KLC |
2501 | fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; |
2502 | fixP->fx_next->fx_frag = fixP->fx_frag; | |
45f76423 AW |
2503 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; |
2504 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
2505 | } | |
2506 | else | |
2507 | as_fatal (_("internal error: bad CFA value #%d"), subtype); | |
2508 | break; | |
2509 | } | |
2510 | break; | |
2511 | ||
e23eba97 NC |
2512 | default: |
2513 | /* This case is unreachable. */ | |
2514 | abort (); | |
2515 | } | |
2516 | } | |
2517 | /* Fall through. */ | |
2518 | ||
2519 | case BFD_RELOC_RVA: | |
2520 | /* If we are deleting this reloc entry, we must fill in the | |
2521 | value now. This can happen if we have a .word which is not | |
2522 | resolved when it appears but is later defined. */ | |
2523 | if (fixP->fx_addsy == NULL) | |
2524 | { | |
2525 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
2526 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
2527 | fixP->fx_done = 1; | |
2528 | } | |
2529 | break; | |
2530 | ||
2531 | case BFD_RELOC_RISCV_JMP: | |
2532 | if (fixP->fx_addsy) | |
2533 | { | |
2534 | /* Fill in a tentative value to improve objdump readability. */ | |
2535 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2536 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2537 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); | |
2538 | } | |
2539 | break; | |
2540 | ||
2541 | case BFD_RELOC_12_PCREL: | |
2542 | if (fixP->fx_addsy) | |
2543 | { | |
2544 | /* Fill in a tentative value to improve objdump readability. */ | |
2545 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2546 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2547 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); | |
2548 | } | |
2549 | break; | |
2550 | ||
2551 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
2552 | if (fixP->fx_addsy) | |
2553 | { | |
2554 | /* Fill in a tentative value to improve objdump readability. */ | |
2555 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2556 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2557 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); | |
2558 | } | |
2559 | break; | |
2560 | ||
2561 | case BFD_RELOC_RISCV_RVC_JUMP: | |
2562 | if (fixP->fx_addsy) | |
2563 | { | |
2564 | /* Fill in a tentative value to improve objdump readability. */ | |
2565 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2566 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2567 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); | |
2568 | } | |
2569 | break; | |
2570 | ||
e23eba97 NC |
2571 | case BFD_RELOC_RISCV_CALL: |
2572 | case BFD_RELOC_RISCV_CALL_PLT: | |
45f76423 AW |
2573 | relaxable = TRUE; |
2574 | break; | |
2575 | ||
9d06997a | 2576 | case BFD_RELOC_RISCV_PCREL_HI20: |
45f76423 AW |
2577 | case BFD_RELOC_RISCV_PCREL_LO12_S: |
2578 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
9d06997a PD |
2579 | relaxable = riscv_opts.relax; |
2580 | break; | |
2581 | ||
e23eba97 NC |
2582 | case BFD_RELOC_RISCV_ALIGN: |
2583 | break; | |
2584 | ||
2585 | default: | |
2586 | /* We ignore generic BFD relocations we don't know about. */ | |
2587 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
2588 | as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); | |
2589 | } | |
45f76423 | 2590 | |
e294484e AW |
2591 | if (fixP->fx_subsy != NULL) |
2592 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2593 | _("unsupported symbol subtraction")); | |
2594 | ||
45f76423 AW |
2595 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
2596 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
2597 | { | |
2598 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2599 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
2600 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
2601 | } | |
2602 | } | |
2603 | ||
2604 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
2605 | we insert a fix to relocate it again in link-time. */ | |
2606 | ||
2607 | void | |
2608 | riscv_pre_output_hook (void) | |
2609 | { | |
2610 | const frchainS *frch; | |
2611 | const asection *s; | |
2612 | ||
2613 | for (s = stdoutput->sections; s; s = s->next) | |
2614 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
2615 | { | |
7cb7b948 | 2616 | fragS *frag; |
45f76423 AW |
2617 | |
2618 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
2619 | { | |
2620 | if (frag->fr_type == rs_cfa) | |
2621 | { | |
45f76423 AW |
2622 | expressionS exp; |
2623 | ||
2624 | symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol; | |
2625 | symbolS *op_symbol = frag->fr_symbol->sy_value.X_op_symbol; | |
2626 | ||
2627 | exp.X_op = O_subtract; | |
2628 | exp.X_add_symbol = add_symbol; | |
2629 | exp.X_add_number = 0; | |
2630 | exp.X_op_symbol = op_symbol; | |
2631 | ||
c1b465c9 | 2632 | fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, |
45f76423 AW |
2633 | BFD_RELOC_RISCV_CFA); |
2634 | } | |
2635 | } | |
2636 | } | |
e23eba97 NC |
2637 | } |
2638 | ||
45f76423 | 2639 | |
e23eba97 NC |
2640 | /* This structure is used to hold a stack of .option values. */ |
2641 | ||
2642 | struct riscv_option_stack | |
2643 | { | |
2644 | struct riscv_option_stack *next; | |
2645 | struct riscv_set_options options; | |
2646 | }; | |
2647 | ||
2648 | static struct riscv_option_stack *riscv_opts_stack; | |
2649 | ||
2650 | /* Handle the .option pseudo-op. */ | |
2651 | ||
2652 | static void | |
2653 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
2654 | { | |
2655 | char *name = input_line_pointer, ch; | |
2656 | ||
2657 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2658 | ++input_line_pointer; | |
2659 | ch = *input_line_pointer; | |
2660 | *input_line_pointer = '\0'; | |
2661 | ||
2662 | if (strcmp (name, "rvc") == 0) | |
2663 | riscv_set_rvc (TRUE); | |
2664 | else if (strcmp (name, "norvc") == 0) | |
2665 | riscv_set_rvc (FALSE); | |
2666 | else if (strcmp (name, "pic") == 0) | |
2667 | riscv_opts.pic = TRUE; | |
2668 | else if (strcmp (name, "nopic") == 0) | |
2669 | riscv_opts.pic = FALSE; | |
45f76423 AW |
2670 | else if (strcmp (name, "relax") == 0) |
2671 | riscv_opts.relax = TRUE; | |
2672 | else if (strcmp (name, "norelax") == 0) | |
2673 | riscv_opts.relax = FALSE; | |
e23eba97 NC |
2674 | else if (strcmp (name, "push") == 0) |
2675 | { | |
2676 | struct riscv_option_stack *s; | |
2677 | ||
2678 | s = (struct riscv_option_stack *) xmalloc (sizeof *s); | |
2679 | s->next = riscv_opts_stack; | |
2680 | s->options = riscv_opts; | |
2681 | riscv_opts_stack = s; | |
2682 | } | |
2683 | else if (strcmp (name, "pop") == 0) | |
2684 | { | |
2685 | struct riscv_option_stack *s; | |
2686 | ||
2687 | s = riscv_opts_stack; | |
2688 | if (s == NULL) | |
2689 | as_bad (_(".option pop with no .option push")); | |
2690 | else | |
2691 | { | |
2692 | riscv_opts = s->options; | |
2693 | riscv_opts_stack = s->next; | |
2694 | free (s); | |
2695 | } | |
2696 | } | |
2697 | else | |
2698 | { | |
2699 | as_warn (_("Unrecognized .option directive: %s\n"), name); | |
2700 | } | |
2701 | *input_line_pointer = ch; | |
2702 | demand_empty_rest_of_line (); | |
2703 | } | |
2704 | ||
2705 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
2706 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
2707 | use in DWARF debug information. */ | |
2708 | ||
2709 | static void | |
2710 | s_dtprel (int bytes) | |
2711 | { | |
2712 | expressionS ex; | |
2713 | char *p; | |
2714 | ||
2715 | expression (&ex); | |
2716 | ||
2717 | if (ex.X_op != O_symbol) | |
2718 | { | |
2719 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
2720 | ? ".dtpreldword" | |
2721 | : ".dtprelword")); | |
2722 | ignore_rest_of_line (); | |
2723 | } | |
2724 | ||
2725 | p = frag_more (bytes); | |
2726 | md_number_to_chars (p, 0, bytes); | |
2727 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
2728 | (bytes == 8 | |
2729 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
2730 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
2731 | ||
2732 | demand_empty_rest_of_line (); | |
2733 | } | |
2734 | ||
2735 | /* Handle the .bss pseudo-op. */ | |
2736 | ||
2737 | static void | |
2738 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
2739 | { | |
2740 | subseg_set (bss_section, 0); | |
2741 | demand_empty_rest_of_line (); | |
2742 | } | |
2743 | ||
e23eba97 | 2744 | static void |
d115ab8e | 2745 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 2746 | { |
d115ab8e | 2747 | bfd_vma i = 0; |
e23eba97 | 2748 | |
e5b737de AW |
2749 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
2750 | means we are not within a valid instruction sequence. It is thus safe | |
2751 | to use a zero byte, even though that is not a valid instruction. */ | |
2752 | if (bytes % 2 == 1) | |
2753 | buf[i++] = 0; | |
2754 | ||
2755 | /* Use at most one 2-byte NOP. */ | |
2756 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 2757 | { |
e5b737de | 2758 | md_number_to_chars (buf + i, RVC_NOP, 2); |
d115ab8e | 2759 | i += 2; |
e23eba97 NC |
2760 | } |
2761 | ||
e5b737de | 2762 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e AW |
2763 | for ( ; i < bytes; i += 4) |
2764 | md_number_to_chars (buf + i, RISCV_NOP, 4); | |
2765 | } | |
e23eba97 | 2766 | |
d115ab8e AW |
2767 | /* Called from md_do_align. Used to create an alignment frag in a |
2768 | code section by emitting a worst-case NOP sequence that the linker | |
2769 | will later relax to the correct number of NOPs. We can't compute | |
2770 | the correct alignment now because of other linker relaxations. */ | |
2771 | ||
2772 | bfd_boolean | |
2773 | riscv_frag_align_code (int n) | |
2774 | { | |
e5b737de | 2775 | bfd_vma bytes = (bfd_vma) 1 << n; |
36877bfb JW |
2776 | bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; |
2777 | bfd_vma worst_case_bytes = bytes - insn_alignment; | |
2778 | char *nops; | |
ed0816bd | 2779 | expressionS ex; |
d115ab8e | 2780 | |
36877bfb JW |
2781 | /* If we are moving to a smaller alignment than the instruction size, then no |
2782 | alignment is required. */ | |
2783 | if (bytes <= insn_alignment) | |
2784 | return TRUE; | |
2785 | ||
d115ab8e AW |
2786 | /* When not relaxing, riscv_handle_align handles code alignment. */ |
2787 | if (!riscv_opts.relax) | |
2788 | return FALSE; | |
e23eba97 | 2789 | |
e80ae190 JW |
2790 | nops = frag_more (worst_case_bytes); |
2791 | ||
ed0816bd PD |
2792 | ex.X_op = O_constant; |
2793 | ex.X_add_number = worst_case_bytes; | |
d115ab8e | 2794 | |
ed0816bd | 2795 | riscv_make_nops (nops, worst_case_bytes); |
e23eba97 | 2796 | |
ed0816bd PD |
2797 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
2798 | &ex, FALSE, BFD_RELOC_RISCV_ALIGN); | |
e23eba97 | 2799 | |
d115ab8e AW |
2800 | return TRUE; |
2801 | } | |
e23eba97 | 2802 | |
d115ab8e AW |
2803 | /* Implement HANDLE_ALIGN. */ |
2804 | ||
2805 | void | |
2806 | riscv_handle_align (fragS *fragP) | |
2807 | { | |
2808 | switch (fragP->fr_type) | |
2809 | { | |
2810 | case rs_align_code: | |
2811 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
2812 | if (!riscv_opts.relax) | |
2813 | { | |
e80ae190 JW |
2814 | bfd_signed_vma bytes = (fragP->fr_next->fr_address |
2815 | - fragP->fr_address - fragP->fr_fix); | |
2816 | /* We have 4 byte uncompressed nops. */ | |
2817 | bfd_signed_vma size = 4; | |
2818 | bfd_signed_vma excess = bytes % size; | |
2819 | char *p = fragP->fr_literal + fragP->fr_fix; | |
2820 | ||
2821 | if (bytes <= 0) | |
d115ab8e AW |
2822 | break; |
2823 | ||
e80ae190 JW |
2824 | /* Insert zeros or compressed nops to get 4 byte alignment. */ |
2825 | if (excess) | |
2826 | { | |
2827 | riscv_make_nops (p, excess); | |
2828 | fragP->fr_fix += excess; | |
2829 | p += excess; | |
2830 | } | |
2831 | ||
2832 | /* Insert variable number of 4 byte uncompressed nops. */ | |
2833 | riscv_make_nops (p, size); | |
2834 | fragP->fr_var = size; | |
d115ab8e AW |
2835 | } |
2836 | break; | |
2837 | ||
2838 | default: | |
2839 | break; | |
2840 | } | |
e23eba97 NC |
2841 | } |
2842 | ||
2843 | int | |
2844 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
2845 | { | |
2846 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); | |
2847 | } | |
2848 | ||
2849 | /* Translate internal representation of relocation info to BFD target | |
2850 | format. */ | |
2851 | ||
2852 | arelent * | |
2853 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
2854 | { | |
2855 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
2856 | ||
2857 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2858 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
2859 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2860 | reloc->addend = fixp->fx_addnumber; | |
2861 | ||
2862 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
2863 | if (reloc->howto == NULL) | |
2864 | { | |
2865 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
2866 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
2867 | { | |
2868 | /* We don't have R_RISCV_8/16, but for this special case, | |
2869 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
2870 | return reloc; | |
2871 | } | |
2872 | ||
2873 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2874 | _("cannot represent %s relocation in object file"), | |
2875 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
2876 | return NULL; | |
2877 | } | |
2878 | ||
2879 | return reloc; | |
2880 | } | |
2881 | ||
2882 | int | |
2883 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
2884 | { | |
2885 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
2886 | { | |
2887 | offsetT old_var = fragp->fr_var; | |
2888 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
2889 | return fragp->fr_var - old_var; | |
2890 | } | |
2891 | ||
2892 | return 0; | |
2893 | } | |
2894 | ||
2895 | /* Expand far branches to multi-instruction sequences. */ | |
2896 | ||
2897 | static void | |
2898 | md_convert_frag_branch (fragS *fragp) | |
2899 | { | |
2900 | bfd_byte *buf; | |
2901 | expressionS exp; | |
2902 | fixS *fixp; | |
2903 | insn_t insn; | |
2904 | int rs1, reloc; | |
2905 | ||
2906 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
2907 | ||
2908 | exp.X_op = O_symbol; | |
2909 | exp.X_add_symbol = fragp->fr_symbol; | |
2910 | exp.X_add_number = fragp->fr_offset; | |
2911 | ||
2912 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
2913 | ||
2914 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
2915 | { | |
2916 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
2917 | { | |
2918 | case 8: | |
2919 | case 4: | |
2920 | /* Expand the RVC branch into a RISC-V one. */ | |
2921 | insn = bfd_getl16 (buf); | |
2922 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
2923 | if ((insn & MASK_C_J) == MATCH_C_J) | |
2924 | insn = MATCH_JAL; | |
2925 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
2926 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
2927 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
2928 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
2929 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
2930 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
2931 | else | |
2932 | abort (); | |
2933 | bfd_putl32 (insn, buf); | |
2934 | break; | |
2935 | ||
2936 | case 6: | |
2937 | /* Invert the branch condition. Branch over the jump. */ | |
2938 | insn = bfd_getl16 (buf); | |
2939 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
2940 | insn |= ENCODE_RVC_B_IMM (6); | |
2941 | bfd_putl16 (insn, buf); | |
2942 | buf += 2; | |
2943 | goto jump; | |
2944 | ||
2945 | case 2: | |
2946 | /* Just keep the RVC branch. */ | |
2947 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
2948 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
2949 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2950 | 2, &exp, FALSE, reloc); | |
2951 | buf += 2; | |
2952 | goto done; | |
2953 | ||
2954 | default: | |
1d65abb5 | 2955 | abort (); |
e23eba97 NC |
2956 | } |
2957 | } | |
2958 | ||
2959 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
2960 | { | |
2961 | case 8: | |
2962 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
2963 | ||
2964 | /* Invert the branch condition. Branch over the jump. */ | |
2965 | insn = bfd_getl32 (buf); | |
2966 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
2967 | insn |= ENCODE_SBTYPE_IMM (8); | |
2968 | md_number_to_chars ((char *) buf, insn, 4); | |
2969 | buf += 4; | |
2970 | ||
2971 | jump: | |
2972 | /* Jump to the target. */ | |
2973 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2974 | 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); | |
2975 | md_number_to_chars ((char *) buf, MATCH_JAL, 4); | |
2976 | buf += 4; | |
2977 | break; | |
2978 | ||
2979 | case 4: | |
2980 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
2981 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
2982 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2983 | 4, &exp, FALSE, reloc); | |
2984 | buf += 4; | |
2985 | break; | |
2986 | ||
2987 | default: | |
2988 | abort (); | |
2989 | } | |
2990 | ||
2991 | done: | |
2992 | fixp->fx_file = fragp->fr_file; | |
2993 | fixp->fx_line = fragp->fr_line; | |
2994 | ||
2995 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
2996 | + fragp->fr_fix + fragp->fr_var); | |
2997 | ||
2998 | fragp->fr_fix += fragp->fr_var; | |
2999 | } | |
3000 | ||
3001 | /* Relax a machine dependent frag. This returns the amount by which | |
3002 | the current size of the frag should change. */ | |
3003 | ||
3004 | void | |
3005 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
3006 | fragS *fragp) | |
3007 | { | |
3008 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
3009 | md_convert_frag_branch (fragp); | |
3010 | } | |
3011 | ||
3012 | void | |
3013 | md_show_usage (FILE *stream) | |
3014 | { | |
3015 | fprintf (stream, _("\ | |
3016 | RISC-V options:\n\ | |
e23eba97 NC |
3017 | -fpic generate position-independent code\n\ |
3018 | -fno-pic don't generate position-independent code (default)\n\ | |
19683c04 PD |
3019 | -march=ISA set the RISC-V architecture\n\ |
3020 | -mabi=ABI set the RISC-V ABI\n\ | |
71060565 JW |
3021 | -mrelax enable relax (default)\n\ |
3022 | -mno-relax disable relax\n\ | |
e23eba97 NC |
3023 | ")); |
3024 | } | |
3025 | ||
3026 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
3027 | void | |
3028 | riscv_cfi_frame_initial_instructions (void) | |
3029 | { | |
3030 | cfi_add_CFA_def_cfa_register (X_SP); | |
3031 | } | |
3032 | ||
3033 | int | |
3034 | tc_riscv_regname_to_dw2regnum (char *regname) | |
3035 | { | |
3036 | int reg; | |
3037 | ||
3038 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
3039 | return reg; | |
3040 | ||
3041 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
3042 | return reg + 32; | |
3043 | ||
3044 | as_bad (_("unknown register `%s'"), regname); | |
3045 | return -1; | |
3046 | } | |
3047 | ||
3048 | void | |
3049 | riscv_elf_final_processing (void) | |
3050 | { | |
e23eba97 | 3051 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
3052 | } |
3053 | ||
3054 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
3055 | since these directives break relaxation when used with symbol deltas. */ | |
3056 | ||
3057 | static void | |
3058 | s_riscv_leb128 (int sign) | |
3059 | { | |
3060 | expressionS exp; | |
3061 | char *save_in = input_line_pointer; | |
3062 | ||
3063 | expression (&exp); | |
3064 | if (exp.X_op != O_constant) | |
3065 | as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); | |
3066 | demand_empty_rest_of_line (); | |
3067 | ||
3068 | input_line_pointer = save_in; | |
3069 | return s_leb128 (sign); | |
3070 | } | |
3071 | ||
0e35537d JW |
3072 | /* Parse the .insn directive. */ |
3073 | ||
3074 | static void | |
3075 | s_riscv_insn (int x ATTRIBUTE_UNUSED) | |
3076 | { | |
3077 | char *str = input_line_pointer; | |
3078 | struct riscv_cl_insn insn; | |
3079 | expressionS imm_expr; | |
3080 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
3081 | char save_c; | |
3082 | ||
3083 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
3084 | ++input_line_pointer; | |
3085 | ||
3086 | save_c = *input_line_pointer; | |
3087 | *input_line_pointer = '\0'; | |
3088 | ||
3089 | const char *error = riscv_ip (str, &insn, &imm_expr, | |
3090 | &imm_reloc, insn_type_hash); | |
3091 | ||
3092 | if (error) | |
3093 | { | |
3094 | as_bad ("%s `%s'", error, str); | |
3095 | } | |
3096 | else | |
3097 | { | |
3098 | gas_assert (insn.insn_mo->pinfo != INSN_MACRO); | |
3099 | append_insn (&insn, &imm_expr, imm_reloc); | |
3100 | } | |
3101 | ||
3102 | *input_line_pointer = save_c; | |
3103 | demand_empty_rest_of_line (); | |
3104 | } | |
3105 | ||
e23eba97 NC |
3106 | /* Pseudo-op table. */ |
3107 | ||
3108 | static const pseudo_typeS riscv_pseudo_table[] = | |
3109 | { | |
3110 | /* RISC-V-specific pseudo-ops. */ | |
3111 | {"option", s_riscv_option, 0}, | |
3112 | {"half", cons, 2}, | |
3113 | {"word", cons, 4}, | |
3114 | {"dword", cons, 8}, | |
3115 | {"dtprelword", s_dtprel, 4}, | |
3116 | {"dtpreldword", s_dtprel, 8}, | |
3117 | {"bss", s_bss, 0}, | |
e23eba97 NC |
3118 | {"uleb128", s_riscv_leb128, 0}, |
3119 | {"sleb128", s_riscv_leb128, 1}, | |
0e35537d | 3120 | {"insn", s_riscv_insn, 0}, |
e23eba97 NC |
3121 | |
3122 | { NULL, NULL, 0 }, | |
3123 | }; | |
3124 | ||
3125 | void | |
3126 | riscv_pop_insert (void) | |
3127 | { | |
3128 | extern void pop_insert (const pseudo_typeS *); | |
3129 | ||
3130 | pop_insert (riscv_pseudo_table); | |
3131 | } |