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Remove sh5 and sh64 support
[deliverable/binutils-gdb.git] / gas / config / tc-sh.c
CommitLineData
ef230218 1/* tc-sh.c -- Assemble code for the Renesas / SuperH SH
219d1afa 2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
252b5132 20
6b31947e 21/* Written By Steve Chamberlain <sac@cygnus.com> */
252b5132 22
252b5132 23#include "as.h"
252b5132
RH		 24#include "subsegs.h"
25#define DEFINE_TABLE
26#include "opcodes/sh-opc.h"
3882b010 27#include "safe-ctype.h"
43841e91 28#include "struc-symbol.h"
d4845d57
JR		 29
30#ifdef OBJ_ELF
31#include "elf/sh.h"
32#endif
33
0d10e182 34#include "dwarf2dbg.h"
2ce4cc60 35#include "dw2gencfi.h"
0d10e182 36
e08ae979
HPN		 37typedef struct
38 {
39 sh_arg_type type;
40 int reg;
41 expressionS immediate;
42 }
43sh_operand_info;
44
252b5132
RH		 45const char comment_chars[] = "!";
46const char line_separator_chars[] = ";";
47const char line_comment_chars[] = "!#";
48
8edc77b9
KK		 49static void s_uses (int);
50static void s_uacons (int);
252b5132 51
a1cc9221 52#ifdef OBJ_ELF
8edc77b9 53static void sh_elf_cons (int);
538cd60f 54
a1cc9221
AO		 55symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
56#endif
57
05982cac 58static void
8edc77b9 59big (int ignore ATTRIBUTE_UNUSED)
05982cac
HPN		 60{
61 if (! target_big_endian)
62 as_bad (_("directive .big encountered when option -big required"));
63
64 /* Stop further messages. */
65 target_big_endian = 1;
66}
252b5132
RH		 67
68static void
8edc77b9 69little (int ignore ATTRIBUTE_UNUSED)
252b5132 70{
05982cac
HPN		 71 if (target_big_endian)
72 as_bad (_("directive .little encountered when option -little required"));
73
74 /* Stop further messages. */
252b5132
RH		 75 target_big_endian = 0;
76}
77
d4845d57
JR		 78/* This table describes all the machine specific pseudo-ops the assembler
79 has to support. The fields are:
80 pseudo-op name without dot
81 function to call to execute this pseudo-op
6b31947e 82 Integer arg to pass to the function. */
d4845d57 83
252b5132
RH		 84const pseudo_typeS md_pseudo_table[] =
85{
a1cc9221
AO		 86#ifdef OBJ_ELF
87 {"long", sh_elf_cons, 4},
88 {"int", sh_elf_cons, 4},
89 {"word", sh_elf_cons, 2},
90 {"short", sh_elf_cons, 2},
91#else
252b5132
RH		 92 {"int", cons, 4},
93 {"word", cons, 2},
a1cc9221 94#endif /* OBJ_ELF */
05982cac 95 {"big", big, 0},
252b5132
RH		 96 {"form", listing_psize, 0},
97 {"little", little, 0},
98 {"heading", listing_title, 0},
99 {"import", s_ignore, 0},
100 {"page", listing_eject, 0},
101 {"program", s_ignore, 0},
102 {"uses", s_uses, 0},
103 {"uaword", s_uacons, 2},
104 {"ualong", s_uacons, 4},
de68de20
AO		 105 {"uaquad", s_uacons, 8},
106 {"2byte", s_uacons, 2},
107 {"4byte", s_uacons, 4},
108 {"8byte", s_uacons, 8},
252b5132
RH		 109 {0, 0, 0}
110};
111
252b5132
RH		 112int sh_relax; /* set if -relax seen */
113
114/* Whether -small was seen. */
115
116int sh_small;
117
f55629b8
KK		 118/* Flag to generate relocations against symbol values for local symbols. */
119
120static int dont_adjust_reloc_32;
121
37dedf66
NC		 122/* Flag to indicate that '$' is allowed as a register prefix. */
123
124static int allow_dollar_register_prefix;
125
126/* Preset architecture set, if given; zero otherwise. */
d4845d57 127
f6f9408f 128static unsigned int preset_target_arch;
d4845d57
JR		 129
130/* The bit mask of architectures that could
67c1ffbe 131 accommodate the insns seen so far. */
f6f9408f 132static unsigned int valid_arch;
d4845d57 133
87975d2a 134#ifdef OBJ_ELF
8e45593f
NC		 135/* Whether --fdpic was given. */
136static int sh_fdpic;
87975d2a 137#endif
8e45593f 138
252b5132
RH		 139const char EXP_CHARS[] = "eE";
140
6b31947e 141/* Chars that mean this number is a floating point constant. */
252b5132
RH		 142/* As in 0f12.456 */
143/* or 0d1.2345e12 */
144const char FLT_CHARS[] = "rRsSfFdDxXpP";
145
146#define C(a,b) ENCODE_RELAX(a,b)
147
252b5132
RH		 148#define ENCODE_RELAX(what,length) (((what) << 4) + (length))
149#define GET_WHAT(x) ((x>>4))
150
67c1ffbe 151/* These are the three types of relaxable instruction. */
324bfcf3
AO		 152/* These are the types of relaxable instructions; except for END which is
153 a marker. */
252b5132
RH		 154#define COND_JUMP 1
155#define COND_JUMP_DELAY 2
156#define UNCOND_JUMP 3
324bfcf3 157
252b5132
RH		 158#define END 4
159
160#define UNDEF_DISP 0
161#define COND8 1
162#define COND12 2
163#define COND32 3
252b5132
RH		 164#define UNDEF_WORD_DISP 4
165
166#define UNCOND12 1
167#define UNCOND32 2
168
169/* Branch displacements are from the address of the branch plus
170 four, thus all minimum and maximum values have 4 added to them. */
171#define COND8_F 258
172#define COND8_M -252
173#define COND8_LENGTH 2
174
175/* There is one extra instruction before the branch, so we must add
176 two more bytes to account for it. */
177#define COND12_F 4100
178#define COND12_M -4090
179#define COND12_LENGTH 6
180
181#define COND12_DELAY_LENGTH 4
182
183/* ??? The minimum and maximum values are wrong, but this does not matter
184 since this relocation type is not supported yet. */
185#define COND32_F (1<<30)
186#define COND32_M -(1<<30)
187#define COND32_LENGTH 14
188
189#define UNCOND12_F 4098
190#define UNCOND12_M -4092
191#define UNCOND12_LENGTH 2
192
193/* ??? The minimum and maximum values are wrong, but this does not matter
194 since this relocation type is not supported yet. */
195#define UNCOND32_F (1<<30)
196#define UNCOND32_M -(1<<30)
197#define UNCOND32_LENGTH 14
198
43841e91
NC		 199#define EMPTY { 0, 0, 0, 0 }
200
252b5132 201const relax_typeS md_relax_table[C (END, 0)] = {
43841e91
NC		 202 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
203 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 204
43841e91 205 EMPTY,
252b5132
RH		 206 /* C (COND_JUMP, COND8) */
207 { COND8_F, COND8_M, COND8_LENGTH, C (COND_JUMP, COND12) },
208 /* C (COND_JUMP, COND12) */
209 { COND12_F, COND12_M, COND12_LENGTH, C (COND_JUMP, COND32), },
210 /* C (COND_JUMP, COND32) */
211 { COND32_F, COND32_M, COND32_LENGTH, 0, },
e66457fb
AM		 212 /* C (COND_JUMP, UNDEF_WORD_DISP) */
213 { 0, 0, COND32_LENGTH, 0, },
214 EMPTY, EMPTY, EMPTY,
43841e91 215 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 216
43841e91 217 EMPTY,
252b5132
RH		 218 /* C (COND_JUMP_DELAY, COND8) */
219 { COND8_F, COND8_M, COND8_LENGTH, C (COND_JUMP_DELAY, COND12) },
220 /* C (COND_JUMP_DELAY, COND12) */
221 { COND12_F, COND12_M, COND12_DELAY_LENGTH, C (COND_JUMP_DELAY, COND32), },
222 /* C (COND_JUMP_DELAY, COND32) */
223 { COND32_F, COND32_M, COND32_LENGTH, 0, },
e66457fb
AM		 224 /* C (COND_JUMP_DELAY, UNDEF_WORD_DISP) */
225 { 0, 0, COND32_LENGTH, 0, },
226 EMPTY, EMPTY, EMPTY,
43841e91 227 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 228
43841e91 229 EMPTY,
252b5132
RH		 230 /* C (UNCOND_JUMP, UNCOND12) */
231 { UNCOND12_F, UNCOND12_M, UNCOND12_LENGTH, C (UNCOND_JUMP, UNCOND32), },
232 /* C (UNCOND_JUMP, UNCOND32) */
233 { UNCOND32_F, UNCOND32_M, UNCOND32_LENGTH, 0, },
e66457fb
AM		 234 EMPTY,
235 /* C (UNCOND_JUMP, UNDEF_WORD_DISP) */
236 { 0, 0, UNCOND32_LENGTH, 0, },
237 EMPTY, EMPTY, EMPTY,
43841e91 238 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
324bfcf3 239
252b5132
RH		 240};
241
43841e91
NC		 242#undef EMPTY
243
252b5132
RH		 244static struct hash_control *opcode_hash_control; /* Opcode mnemonics */
245
a1cc9221
AO		 246\f
247#ifdef OBJ_ELF
33eaf5de 248/* Determine whether the symbol needs any kind of PIC relocation. */
538cd60f
AO		 249
250inline static int
8edc77b9 251sh_PIC_related_p (symbolS *sym)
a1cc9221 252{
538cd60f 253 expressionS *exp;
a1cc9221 254
538cd60f
AO		 255 if (! sym)
256 return 0;
257
258 if (sym == GOT_symbol)
259 return 1;
260
261 exp = symbol_get_value_expression (sym);
262
263 return (exp->X_op == O_PIC_reloc
264 || sh_PIC_related_p (exp->X_add_symbol)
265 || sh_PIC_related_p (exp->X_op_symbol));
266}
267
268/* Determine the relocation type to be used to represent the
269 expression, that may be rearranged. */
270
271static int
8edc77b9 272sh_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
538cd60f
AO		 273{
274 expressionS *exp = main_exp;
275
276 /* This is here for backward-compatibility only. GCC used to generated:
277
278 f@PLT + . - (.LPCS# + 2)
279
280 but we'd rather be able to handle this as a PIC-related reference
281 plus/minus a symbol. However, gas' parser gives us:
282
283 O_subtract (O_add (f@PLT, .), .LPCS#+2)
5d6255fe 284
538cd60f
AO		 285 so we attempt to transform this into:
286
287 O_subtract (f@PLT, O_subtract (.LPCS#+2, .))
288
5d6255fe 289 which we can handle simply below. */
538cd60f
AO		 290 if (exp->X_op == O_subtract)
291 {
292 if (sh_PIC_related_p (exp->X_op_symbol))
293 return 1;
294
295 exp = symbol_get_value_expression (exp->X_add_symbol);
296
297 if (exp && sh_PIC_related_p (exp->X_op_symbol))
298 return 1;
299
300 if (exp && exp->X_op == O_add
301 && sh_PIC_related_p (exp->X_add_symbol))
302 {
303 symbolS *sym = exp->X_add_symbol;
304
305 exp->X_op = O_subtract;
306 exp->X_add_symbol = main_exp->X_op_symbol;
307
308 main_exp->X_op_symbol = main_exp->X_add_symbol;
309 main_exp->X_add_symbol = sym;
310
311 main_exp->X_add_number += exp->X_add_number;
312 exp->X_add_number = 0;
313 }
314
315 exp = main_exp;
316 }
317 else if (exp->X_op == O_add && sh_PIC_related_p (exp->X_op_symbol))
318 return 1;
319
320 if (exp->X_op == O_symbol || exp->X_op == O_add || exp->X_op == O_subtract)
321 {
322 if (exp->X_add_symbol && exp->X_add_symbol == GOT_symbol)
323 {
324 *r_type_p = BFD_RELOC_SH_GOTPC;
325 return 0;
326 }
327 exp = symbol_get_value_expression (exp->X_add_symbol);
328 if (! exp)
329 return 0;
330 }
331
332 if (exp->X_op == O_PIC_reloc)
333 {
324bfcf3
AO		 334 switch (*r_type_p)
335 {
336 case BFD_RELOC_NONE:
337 case BFD_RELOC_UNUSED:
338 *r_type_p = exp->X_md;
339 break;
340
8e45593f
NC		 341 case BFD_RELOC_SH_DISP20:
342 switch (exp->X_md)
343 {
344 case BFD_RELOC_32_GOT_PCREL:
345 *r_type_p = BFD_RELOC_SH_GOT20;
346 break;
347
348 case BFD_RELOC_32_GOTOFF:
349 *r_type_p = BFD_RELOC_SH_GOTOFF20;
350 break;
351
352 case BFD_RELOC_SH_GOTFUNCDESC:
353 *r_type_p = BFD_RELOC_SH_GOTFUNCDESC20;
354 break;
355
356 case BFD_RELOC_SH_GOTOFFFUNCDESC:
357 *r_type_p = BFD_RELOC_SH_GOTOFFFUNCDESC20;
358 break;
359
360 default:
361 abort ();
362 }
363 break;
364
324bfcf3
AO		 365 default:
366 abort ();
367 }
538cd60f
AO		 368 if (exp == main_exp)
369 exp->X_op = O_symbol;
370 else
371 {
372 main_exp->X_add_symbol = exp->X_add_symbol;
373 main_exp->X_add_number += exp->X_add_number;
374 }
375 }
376 else
377 return (sh_PIC_related_p (exp->X_add_symbol)
378 || sh_PIC_related_p (exp->X_op_symbol));
379
380 return 0;
381}
382
383/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
384
385void
62ebcb5c
AM		 386sh_cons_fix_new (fragS *frag, int off, int size, expressionS *exp,
387 bfd_reloc_code_real_type r_type)
538cd60f 388{
62ebcb5c 389 r_type = BFD_RELOC_UNUSED;
538cd60f
AO		 390
391 if (sh_check_fixup (exp, &r_type))
392 as_bad (_("Invalid PIC expression."));
393
394 if (r_type == BFD_RELOC_UNUSED)
395 switch (size)
a1cc9221 396 {
538cd60f
AO		 397 case 1:
398 r_type = BFD_RELOC_8;
399 break;
a1cc9221 400
538cd60f
AO		 401 case 2:
402 r_type = BFD_RELOC_16;
403 break;
404
405 case 4:
406 r_type = BFD_RELOC_32;
407 break;
a1cc9221 408
324bfcf3
AO		 409 case 8:
410 r_type = BFD_RELOC_64;
411 break;
324bfcf3 412
538cd60f
AO		 413 default:
414 goto error;
415 }
416 else if (size != 4)
417 {
418 error:
419 as_bad (_("unsupported BFD relocation size %u"), size);
420 r_type = BFD_RELOC_UNUSED;
421 }
5d6255fe 422
538cd60f 423 fix_new_exp (frag, off, size, exp, 0, r_type);
a1cc9221
AO		 424}
425
426/* The regular cons() function, that reads constants, doesn't support
427 suffixes such as @GOT, @GOTOFF and @PLT, that generate
428 machine-specific relocation types. So we must define it here. */
429/* Clobbers input_line_pointer, checks end-of-line. */
8edc77b9 430/* NBYTES 1=.byte, 2=.word, 4=.long */
a1cc9221 431static void
ed9e98c2 432sh_elf_cons (int nbytes)
a1cc9221 433{
538cd60f 434 expressionS exp;
a1cc9221
AO		 435
436 if (is_it_end_of_statement ())
437 {
438 demand_empty_rest_of_line ();
439 return;
440 }
441
028f09bd
NC		 442#ifdef md_cons_align
443 md_cons_align (nbytes);
444#endif
445
a1cc9221
AO		 446 do
447 {
448 expression (&exp);
538cd60f 449 emit_expr (&exp, (unsigned int) nbytes);
a1cc9221
AO		 450 }
451 while (*input_line_pointer++ == ',');
452
81d4177b 453 input_line_pointer--; /* Put terminator back into stream. */
a1cc9221
AO		 454 if (*input_line_pointer == '#' || *input_line_pointer == '!')
455 {
dda5ecfc 456 while (! is_end_of_line[(unsigned char) *input_line_pointer++]);
a1cc9221
AO		 457 }
458 else
459 demand_empty_rest_of_line ();
460}
0cc34095
KK		 461
462/* The regular frag_offset_fixed_p doesn't work for rs_align_test
463 frags. */
464
465static bfd_boolean
466align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
467 bfd_vma *offset)
468{
469 const fragS *frag;
470 bfd_vma off;
471
472 /* Start with offset initialised to difference between the two frags.
473 Prior to assigning frag addresses this will be zero. */
474 off = frag1->fr_address - frag2->fr_address;
475 if (frag1 == frag2)
476 {
477 *offset = off;
478 return TRUE;
479 }
480
481 /* Maybe frag2 is after frag1. */
482 frag = frag1;
0838d2ac
KK		 483 while (frag->fr_type == rs_fill
484 || frag->fr_type == rs_align_test)
0cc34095 485 {
0838d2ac
KK		 486 if (frag->fr_type == rs_fill)
487 off += frag->fr_fix + frag->fr_offset * frag->fr_var;
488 else
489 off += frag->fr_fix;
0cc34095
KK		 490 frag = frag->fr_next;
491 if (frag == NULL)
492 break;
493 if (frag == frag2)
494 {
495 *offset = off;
496 return TRUE;
497 }
498 }
499
500 /* Maybe frag1 is after frag2. */
501 off = frag1->fr_address - frag2->fr_address;
502 frag = frag2;
0838d2ac
KK		 503 while (frag->fr_type == rs_fill
504 || frag->fr_type == rs_align_test)
0cc34095 505 {
0838d2ac
KK		 506 if (frag->fr_type == rs_fill)
507 off -= frag->fr_fix + frag->fr_offset * frag->fr_var;
508 else
509 off -= frag->fr_fix;
0cc34095
KK		 510 frag = frag->fr_next;
511 if (frag == NULL)
512 break;
513 if (frag == frag1)
514 {
515 *offset = off;
516 return TRUE;
517 }
518 }
519
520 return FALSE;
521}
a1cc9221 522
0cc34095
KK		 523/* Optimize a difference of symbols which have rs_align_test frag if
524 possible. */
525
526int
527sh_optimize_expr (expressionS *l, operatorT op, expressionS *r)
528{
0cc34095
KK		 529 bfd_vma frag_off;
530
531 if (op == O_subtract
532 && l->X_op == O_symbol
533 && r->X_op == O_symbol
534 && S_GET_SEGMENT (l->X_add_symbol) == S_GET_SEGMENT (r->X_add_symbol)
535 && (SEG_NORMAL (S_GET_SEGMENT (l->X_add_symbol))
536 || r->X_add_symbol == l->X_add_symbol)
537 && align_test_frag_offset_fixed_p (symbol_get_frag (l->X_add_symbol),
538 symbol_get_frag (r->X_add_symbol),
539 &frag_off))
540 {
4455e9ad
JB		 541 offsetT symval_diff = S_GET_VALUE (l->X_add_symbol)
542 - S_GET_VALUE (r->X_add_symbol);
543 subtract_from_result (l, r->X_add_number, r->X_extrabit);
544 subtract_from_result (l, frag_off / OCTETS_PER_BYTE, 0);
545 add_to_result (l, symval_diff, symval_diff < 0);
0cc34095
KK		 546 l->X_op = O_constant;
547 l->X_add_symbol = 0;
548 return 1;
549 }
0cc34095
KK		 550 return 0;
551}
541d2ffd 552#endif /* OBJ_ELF */
a1cc9221 553\f
6b31947e
NC		 554/* This function is called once, at assembler startup time. This should
555 set up all the tables, etc that the MD part of the assembler needs. */
252b5132
RH		 556
557void
8edc77b9 558md_begin (void)
252b5132 559{
5ff37431 560 const sh_opcode_info *opcode;
e0471c16 561 const char *prev_name = "";
f6f9408f 562 unsigned int target_arch;
252b5132 563
bdfaef52 564 target_arch
e38bc3b5 565 = preset_target_arch ? preset_target_arch : arch_sh_up & ~arch_sh_has_dsp;
d4845d57
JR		 566 valid_arch = target_arch;
567
252b5132
RH		 568 opcode_hash_control = hash_new ();
569
6b31947e 570 /* Insert unique names into hash table. */
252b5132
RH		 571 for (opcode = sh_table; opcode->name; opcode++)
572 {
5ff37431 573 if (strcmp (prev_name, opcode->name) != 0)
252b5132 574 {
f6f9408f 575 if (!SH_MERGE_ARCH_SET_VALID (opcode->arch, target_arch))
a37c8f88 576 continue;
252b5132
RH		 577 prev_name = opcode->name;
578 hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
579 }
252b5132
RH		 580 }
581}
582
583static int reg_m;
584static int reg_n;
d4845d57
JR		 585static int reg_x, reg_y;
586static int reg_efg;
252b5132
RH		 587static int reg_b;
588
3882b010 589#define IDENT_CHAR(c) (ISALNUM (c) || (c) == '_')
dead1419 590
6b31947e
NC		 591/* Try to parse a reg name. Return the number of chars consumed. */
592
37dedf66 593static unsigned int
c4212e11 594parse_reg_without_prefix (char *src, sh_arg_type *mode, int *reg)
252b5132 595{
3882b010
L		 596 char l0 = TOLOWER (src[0]);
597 char l1 = l0 ? TOLOWER (src[1]) : 0;
e46fee70 598
dead1419 599 /* We use ! IDENT_CHAR for the next character after the register name, to
252b5132 600 make sure that we won't accidentally recognize a symbol name such as
dead1419 601 'sram' or sr_ram as being a reference to the register 'sr'. */
252b5132 602
e46fee70 603 if (l0 == 'r')
252b5132 604 {
e46fee70 605 if (l1 == '1')
d4845d57
JR		 606 {
607 if (src[2] >= '0' && src[2] <= '5'
dead1419 608 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 609 {
610 *mode = A_REG_N;
611 *reg = 10 + src[2] - '0';
612 return 3;
613 }
614 }
e46fee70 615 if (l1 >= '0' && l1 <= '9'
dead1419 616 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 617 {
618 *mode = A_REG_N;
e46fee70 619 *reg = (l1 - '0');
d4845d57
JR		 620 return 2;
621 }
e46fee70 622 if (l1 >= '0' && l1 <= '7' && strncasecmp (&src[2], "_bank", 5) == 0
dead1419
JR		 623 && ! IDENT_CHAR ((unsigned char) src[7]))
624 {
625 *mode = A_REG_B;
e46fee70 626 *reg = (l1 - '0');
dead1419
JR		 627 return 7;
628 }
d4845d57 629
e46fee70 630 if (l1 == 'e' && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 631 {
632 *mode = A_RE;
633 return 2;
634 }
e46fee70 635 if (l1 == 's' && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 636 {
637 *mode = A_RS;
638 return 2;
639 }
252b5132
RH		 640 }
641
e46fee70 642 if (l0 == 'a')
252b5132 643 {
e46fee70 644 if (l1 == '0')
d4845d57 645 {
dead1419 646 if (! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 647 {
648 *mode = DSP_REG_N;
649 *reg = A_A0_NUM;
650 return 2;
651 }
3882b010 652 if (TOLOWER (src[2]) == 'g' && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 653 {
654 *mode = DSP_REG_N;
655 *reg = A_A0G_NUM;
656 return 3;
657 }
658 }
e46fee70 659 if (l1 == '1')
252b5132 660 {
dead1419 661 if (! IDENT_CHAR ((unsigned char) src[2]))
252b5132 662 {
d4845d57
JR		 663 *mode = DSP_REG_N;
664 *reg = A_A1_NUM;
665 return 2;
666 }
3882b010 667 if (TOLOWER (src[2]) == 'g' && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 668 {
669 *mode = DSP_REG_N;
670 *reg = A_A1G_NUM;
252b5132
RH		 671 return 3;
672 }
673 }
d4845d57 674
e46fee70 675 if (l1 == 'x' && src[2] >= '0' && src[2] <= '1'
dead1419 676 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 677 {
678 *mode = A_REG_N;
e46fee70 679 *reg = 4 + (l1 - '0');
d4845d57
JR		 680 return 3;
681 }
e46fee70 682 if (l1 == 'y' && src[2] >= '0' && src[2] <= '1'
dead1419 683 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 684 {
685 *mode = A_REG_N;
e46fee70 686 *reg = 6 + (l1 - '0');
d4845d57
JR		 687 return 3;
688 }
e46fee70 689 if (l1 == 's' && src[2] >= '0' && src[2] <= '3'
dead1419 690 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57 691 {
e46fee70 692 int n = l1 - '0';
d4845d57
JR		 693
694 *mode = A_REG_N;
695 *reg = n | ((~n & 2) << 1);
696 return 3;
697 }
698 }
699
912a07db 700 if (l0 == 'i' && l1 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57 701 {
e46fee70 702 if (l1 == 's')
d4845d57
JR		 703 {
704 *mode = A_REG_N;
705 *reg = 8;
252b5132
RH		 706 return 2;
707 }
e46fee70 708 if (l1 == 'x')
d4845d57
JR		 709 {
710 *mode = A_REG_N;
711 *reg = 8;
712 return 2;
713 }
e46fee70 714 if (l1 == 'y')
d4845d57
JR		 715 {
716 *mode = A_REG_N;
717 *reg = 9;
718 return 2;
719 }
720 }
721
e46fee70 722 if (l0 == 'x' && l1 >= '0' && l1 <= '1'
dead1419 723 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 724 {
725 *mode = DSP_REG_N;
e46fee70 726 *reg = A_X0_NUM + l1 - '0';
d4845d57
JR		 727 return 2;
728 }
729
e46fee70 730 if (l0 == 'y' && l1 >= '0' && l1 <= '1'
dead1419 731 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 732 {
733 *mode = DSP_REG_N;
e46fee70 734 *reg = A_Y0_NUM + l1 - '0';
d4845d57
JR		 735 return 2;
736 }
737
e46fee70 738 if (l0 == 'm' && l1 >= '0' && l1 <= '1'
dead1419 739 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 740 {
741 *mode = DSP_REG_N;
e46fee70 742 *reg = l1 == '0' ? A_M0_NUM : A_M1_NUM;
d4845d57 743 return 2;
252b5132
RH		 744 }
745
e46fee70
HPN		 746 if (l0 == 's'
747 && l1 == 's'
3882b010 748 && TOLOWER (src[2]) == 'r' && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 749 {
750 *mode = A_SSR;
751 return 3;
752 }
753
3882b010 754 if (l0 == 's' && l1 == 'p' && TOLOWER (src[2]) == 'c'
dead1419 755 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 756 {
757 *mode = A_SPC;
758 return 3;
759 }
760
3882b010 761 if (l0 == 's' && l1 == 'g' && TOLOWER (src[2]) == 'r'
dead1419 762 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 763 {
764 *mode = A_SGR;
765 return 3;
766 }
767
3882b010 768 if (l0 == 'd' && l1 == 's' && TOLOWER (src[2]) == 'r'
dead1419 769 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 770 {
771 *mode = A_DSR;
772 return 3;
773 }
774
3882b010 775 if (l0 == 'd' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 776 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 777 {
778 *mode = A_DBR;
779 return 3;
780 }
781
e46fee70 782 if (l0 == 's' && l1 == 'r' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 783 {
784 *mode = A_SR;
785 return 2;
786 }
787
e46fee70 788 if (l0 == 's' && l1 == 'p' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 789 {
790 *mode = A_REG_N;
791 *reg = 15;
792 return 2;
793 }
794
e46fee70 795 if (l0 == 'p' && l1 == 'r' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 796 {
797 *mode = A_PR;
798 return 2;
799 }
e46fee70 800 if (l0 == 'p' && l1 == 'c' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132 801 {
015551fc
JR		 802 /* Don't use A_DISP_PC here - that would accept stuff like 'mova pc,r0'
803 and use an uninitialized immediate. */
804 *mode = A_PC;
252b5132
RH		 805 return 2;
806 }
3882b010 807 if (l0 == 'g' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 808 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 809 {
810 *mode = A_GBR;
811 return 3;
812 }
3882b010 813 if (l0 == 'v' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 814 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 815 {
816 *mode = A_VBR;
817 return 3;
818 }
819
1d70c7fb
AO		 820 if (l0 == 't' && l1 == 'b' && TOLOWER (src[2]) == 'r'
821 && ! IDENT_CHAR ((unsigned char) src[3]))
822 {
823 *mode = A_TBR;
824 return 3;
825 }
3882b010 826 if (l0 == 'm' && l1 == 'a' && TOLOWER (src[2]) == 'c'
dead1419 827 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132 828 {
3882b010 829 if (TOLOWER (src[3]) == 'l')
252b5132
RH		 830 {
831 *mode = A_MACL;
832 return 4;
833 }
3882b010 834 if (TOLOWER (src[3]) == 'h')
252b5132
RH		 835 {
836 *mode = A_MACH;
837 return 4;
838 }
839 }
3882b010 840 if (l0 == 'm' && l1 == 'o' && TOLOWER (src[2]) == 'd'
912a07db 841 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 842 {
843 *mode = A_MOD;
844 return 3;
845 }
e46fee70 846 if (l0 == 'f' && l1 == 'r')
252b5132
RH		 847 {
848 if (src[2] == '1')
849 {
850 if (src[3] >= '0' && src[3] <= '5'
dead1419 851 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 852 {
853 *mode = F_REG_N;
854 *reg = 10 + src[3] - '0';
855 return 4;
856 }
857 }
858 if (src[2] >= '0' && src[2] <= '9'
dead1419 859 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 860 {
861 *mode = F_REG_N;
862 *reg = (src[2] - '0');
863 return 3;
864 }
865 }
e46fee70 866 if (l0 == 'd' && l1 == 'r')
252b5132
RH		 867 {
868 if (src[2] == '1')
869 {
870 if (src[3] >= '0' && src[3] <= '4' && ! ((src[3] - '0') & 1)
dead1419 871 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 872 {
873 *mode = D_REG_N;
874 *reg = 10 + src[3] - '0';
875 return 4;
876 }
877 }
878 if (src[2] >= '0' && src[2] <= '8' && ! ((src[2] - '0') & 1)
dead1419 879 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 880 {
881 *mode = D_REG_N;
882 *reg = (src[2] - '0');
883 return 3;
884 }
885 }
e46fee70 886 if (l0 == 'x' && l1 == 'd')
252b5132
RH		 887 {
888 if (src[2] == '1')
889 {
890 if (src[3] >= '0' && src[3] <= '4' && ! ((src[3] - '0') & 1)
dead1419 891 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 892 {
893 *mode = X_REG_N;
894 *reg = 11 + src[3] - '0';
895 return 4;
896 }
897 }
898 if (src[2] >= '0' && src[2] <= '8' && ! ((src[2] - '0') & 1)
dead1419 899 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 900 {
901 *mode = X_REG_N;
902 *reg = (src[2] - '0') + 1;
903 return 3;
904 }
905 }
e46fee70 906 if (l0 == 'f' && l1 == 'v')
252b5132 907 {
dead1419 908 if (src[2] == '1'&& src[3] == '2' && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 909 {
910 *mode = V_REG_N;
911 *reg = 12;
912 return 4;
913 }
914 if ((src[2] == '0' || src[2] == '4' || src[2] == '8')
dead1419 915 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 916 {
917 *mode = V_REG_N;
918 *reg = (src[2] - '0');
919 return 3;
920 }
921 }
3882b010
L		 922 if (l0 == 'f' && l1 == 'p' && TOLOWER (src[2]) == 'u'
923 && TOLOWER (src[3]) == 'l'
dead1419 924 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 925 {
926 *mode = FPUL_N;
927 return 4;
928 }
929
3882b010
L		 930 if (l0 == 'f' && l1 == 'p' && TOLOWER (src[2]) == 's'
931 && TOLOWER (src[3]) == 'c'
932 && TOLOWER (src[4]) == 'r' && ! IDENT_CHAR ((unsigned char) src[5]))
252b5132
RH		 933 {
934 *mode = FPSCR_N;
935 return 5;
936 }
937
3882b010
L		 938 if (l0 == 'x' && l1 == 'm' && TOLOWER (src[2]) == 't'
939 && TOLOWER (src[3]) == 'r'
940 && TOLOWER (src[4]) == 'x' && ! IDENT_CHAR ((unsigned char) src[5]))
252b5132
RH		 941 {
942 *mode = XMTRX_M4;
943 return 5;
944 }
945
946 return 0;
947}
948
37dedf66
NC		 949/* Like parse_reg_without_prefix, but this version supports
950 $-prefixed register names if enabled by the user. */
951
952static unsigned int
c4212e11 953parse_reg (char *src, sh_arg_type *mode, int *reg)
37dedf66
NC		 954{
955 unsigned int prefix;
956 unsigned int consumed;
957
958 if (src[0] == '$')
959 {
960 if (allow_dollar_register_prefix)
961 {
962 src ++;
963 prefix = 1;
964 }
965 else
966 return 0;
967 }
968 else
969 prefix = 0;
3739860c 970
37dedf66
NC		 971 consumed = parse_reg_without_prefix (src, mode, reg);
972
973 if (consumed == 0)
974 return 0;
975
976 return consumed + prefix;
977}
978
c4aa876b 979static char *
8edc77b9 980parse_exp (char *s, sh_operand_info *op)
252b5132
RH		 981{
982 char *save;
d3ce72d0 983 char *new_pointer;
252b5132
RH		 984
985 save = input_line_pointer;
986 input_line_pointer = s;
015551fc
JR		 987 expression (&op->immediate);
988 if (op->immediate.X_op == O_absent)
252b5132 989 as_bad (_("missing operand"));
d3ce72d0 990 new_pointer = input_line_pointer;
252b5132 991 input_line_pointer = save;
d3ce72d0 992 return new_pointer;
252b5132
RH		 993}
994
252b5132
RH		 995/* The many forms of operand:
996
997 Rn Register direct
998 @Rn Register indirect
999 @Rn+ Autoincrement
1000 @-Rn Autodecrement
1001 @(disp:4,Rn)
1002 @(disp:8,GBR)
1003 @(disp:8,PC)
1004
1005 @(R0,Rn)
1006 @(R0,GBR)
1007
1008 disp:8
1009 disp:12
1010 #imm8
1011 pr, gbr, vbr, macl, mach
252b5132
RH		 1012 */
1013
c4aa876b 1014static char *
8edc77b9 1015parse_at (char *src, sh_operand_info *op)
252b5132
RH		 1016{
1017 int len;
c4212e11 1018 sh_arg_type mode;
252b5132 1019 src++;
1d70c7fb
AO		 1020 if (src[0] == '@')
1021 {
1022 src = parse_at (src, op);
1023 if (op->type == A_DISP_TBR)
1024 op->type = A_DISP2_TBR;
1025 else
1026 as_bad (_("illegal double indirection"));
1027 }
1028 else if (src[0] == '-')
252b5132 1029 {
6b31947e 1030 /* Must be predecrement. */
252b5132
RH		 1031 src++;
1032
1033 len = parse_reg (src, &mode, &(op->reg));
1034 if (mode != A_REG_N)
1035 as_bad (_("illegal register after @-"));
1036
1037 op->type = A_DEC_N;
1038 src += len;
1039 }
1040 else if (src[0] == '(')
1041 {
1042 /* Could be @(disp, rn), @(disp, gbr), @(disp, pc), @(r0, gbr) or
8d4d84c2 1043 @(r0, rn). */
252b5132
RH		 1044 src++;
1045 len = parse_reg (src, &mode, &(op->reg));
1046 if (len && mode == A_REG_N)
1047 {
1048 src += len;
1049 if (op->reg != 0)
1050 {
1051 as_bad (_("must be @(r0,...)"));
1052 }
1053 if (src[0] == ',')
252b5132 1054 {
8d4d84c2
AO		 1055 src++;
1056 /* Now can be rn or gbr. */
1057 len = parse_reg (src, &mode, &(op->reg));
1058 }
1059 else
1060 {
1061 len = 0;
252b5132 1062 }
8d4d84c2 1063 if (len)
252b5132 1064 {
8d4d84c2
AO		 1065 if (mode == A_GBR)
1066 {
1067 op->type = A_R0_GBR;
1068 }
1069 else if (mode == A_REG_N)
1070 {
1071 op->type = A_IND_R0_REG_N;
1072 }
1073 else
1074 {
1075 as_bad (_("syntax error in @(r0,...)"));
1076 }
252b5132
RH		 1077 }
1078 else
1079 {
8d4d84c2 1080 as_bad (_("syntax error in @(r0...)"));
252b5132
RH		 1081 }
1082 }
1083 else
1084 {
8d4d84c2 1085 /* Must be an @(disp,.. thing). */
015551fc 1086 src = parse_exp (src, op);
252b5132
RH		 1087 if (src[0] == ',')
1088 src++;
8d4d84c2 1089 /* Now can be rn, gbr or pc. */
252b5132
RH		 1090 len = parse_reg (src, &mode, &op->reg);
1091 if (len)
1092 {
1093 if (mode == A_REG_N)
1094 {
1095 op->type = A_DISP_REG_N;
1096 }
1097 else if (mode == A_GBR)
1098 {
1099 op->type = A_DISP_GBR;
1100 }
1d70c7fb
AO		 1101 else if (mode == A_TBR)
1102 {
1103 op->type = A_DISP_TBR;
1104 }
015551fc 1105 else if (mode == A_PC)
252b5132 1106 {
dbb4348d
JR		 1107 /* We want @(expr, pc) to uniformly address . + expr,
1108 no matter if expr is a constant, or a more complex
1109 expression, e.g. sym-. or sym1-sym2.
1110 However, we also used to accept @(sym,pc)
67c1ffbe 1111 as addressing sym, i.e. meaning the same as plain sym.
dbb4348d
JR		 1112 Some existing code does use the @(sym,pc) syntax, so
1113 we give it the old semantics for now, but warn about
1114 its use, so that users have some time to fix their code.
1115
1116 Note that due to this backward compatibility hack,
1117 we'll get unexpected results when @(offset, pc) is used,
1118 and offset is a symbol that is set later to an an address
1119 difference, or an external symbol that is set to an
1120 address difference in another source file, so we want to
1121 eventually remove it. */
9691d64f
JR		 1122 if (op->immediate.X_op == O_symbol)
1123 {
1124 op->type = A_DISP_PC;
1125 as_warn (_("Deprecated syntax."));
1126 }
1127 else
1128 {
1129 op->type = A_DISP_PC_ABS;
1130 /* Such operands don't get corrected for PC==.+4, so
1131 make the correction here. */
1132 op->immediate.X_add_number -= 4;
1133 }
252b5132
RH		 1134 }
1135 else
1136 {
1137 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
1138 }
1139 }
1140 else
1141 {
1142 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
1143 }
1144 }
1145 src += len;
1146 if (src[0] != ')')
1147 as_bad (_("expecting )"));
1148 else
1149 src++;
1150 }
1151 else
1152 {
1153 src += parse_reg (src, &mode, &(op->reg));
1154 if (mode != A_REG_N)
006299d3
NC		 1155 as_bad (_("illegal register after @"));
1156
252b5132
RH		 1157 if (src[0] == '+')
1158 {
1000a02a
NC		 1159 char l0, l1;
1160
252b5132 1161 src++;
1000a02a
NC		 1162 l0 = TOLOWER (src[0]);
1163 l1 = TOLOWER (src[1]);
1164
1165 if ((l0 == 'r' && l1 == '8')
1166 || (l0 == 'i' && (l1 == 'x' || l1 == 's')))
d4845d57
JR		 1167 {
1168 src += 2;
88da98f3 1169 op->type = AX_PMOD_N;
d4845d57 1170 }
006299d3
NC		 1171 else if ( (l0 == 'r' && l1 == '9')
1172 || (l0 == 'i' && l1 == 'y'))
d4845d57
JR		 1173 {
1174 src += 2;
88da98f3 1175 op->type = AY_PMOD_N;
d4845d57
JR		 1176 }
1177 else
1178 op->type = A_INC_N;
252b5132
RH		 1179 }
1180 else
006299d3 1181 op->type = A_IND_N;
252b5132
RH		 1182 }
1183 return src;
1184}
1185
1186static void
8edc77b9 1187get_operand (char **ptr, sh_operand_info *op)
252b5132
RH		 1188{
1189 char *src = *ptr;
c4212e11 1190 sh_arg_type mode = (sh_arg_type) -1;
252b5132
RH		 1191 unsigned int len;
1192
1193 if (src[0] == '#')
1194 {
1195 src++;
015551fc 1196 *ptr = parse_exp (src, op);
252b5132
RH		 1197 op->type = A_IMM;
1198 return;
1199 }
1200
1201 else if (src[0] == '@')
1202 {
1203 *ptr = parse_at (src, op);
1204 return;
1205 }
1206 len = parse_reg (src, &mode, &(op->reg));
1207 if (len)
1208 {
1209 *ptr = src + len;
1210 op->type = mode;
1211 return;
1212 }
1213 else
1214 {
6b31947e 1215 /* Not a reg, the only thing left is a displacement. */
015551fc 1216 *ptr = parse_exp (src, op);
252b5132
RH		 1217 op->type = A_DISP_PC;
1218 return;
1219 }
1220}
1221
c4aa876b 1222static char *
8edc77b9 1223get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
252b5132
RH		 1224{
1225 char *ptr = args;
1226 if (info->arg[0])
1227 {
d4845d57
JR		 1228 /* The pre-processor will eliminate whitespace in front of '@'
1229 after the first argument; we may be called multiple times
1230 from assemble_ppi, so don't insist on finding whitespace here. */
1231 if (*ptr == ' ')
1232 ptr++;
252b5132
RH		 1233
1234 get_operand (&ptr, operand + 0);
1235 if (info->arg[1])
1236 {
1237 if (*ptr == ',')
1238 {
1239 ptr++;
1240 }
1241 get_operand (&ptr, operand + 1);
52ccafd0
JR		 1242 /* ??? Hack: psha/pshl have a varying operand number depending on
1243 the type of the first operand. We handle this by having the
1244 three-operand version first and reducing the number of operands
1245 parsed to two if we see that the first operand is an immediate.
1246 This works because no insn with three operands has an immediate
1247 as first operand. */
1248 if (info->arg[2] && operand[0].type != A_IMM)
252b5132
RH		 1249 {
1250 if (*ptr == ',')
1251 {
1252 ptr++;
1253 }
1254 get_operand (&ptr, operand + 2);
1255 }
1256 else
1257 {
1258 operand[2].type = 0;
1259 }
1260 }
1261 else
1262 {
1263 operand[1].type = 0;
1264 operand[2].type = 0;
1265 }
1266 }
1267 else
1268 {
1269 operand[0].type = 0;
1270 operand[1].type = 0;
1271 operand[2].type = 0;
1272 }
1273 return ptr;
1274}
1275
1276/* Passed a pointer to a list of opcodes which use different
1277 addressing modes, return the opcode which matches the opcodes
6b31947e 1278 provided. */
252b5132 1279
c4aa876b 1280static sh_opcode_info *
8edc77b9 1281get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
252b5132
RH		 1282{
1283 sh_opcode_info *this_try = opcode;
f86f5863 1284 const char *name = opcode->name;
252b5132 1285 int n = 0;
c4aa876b 1286
252b5132
RH		 1287 while (opcode->name)
1288 {
1289 this_try = opcode++;
5ff37431 1290 if ((this_try->name != name) && (strcmp (this_try->name, name) != 0))
252b5132
RH		 1291 {
1292 /* We've looked so far down the table that we've run out of
6b31947e 1293 opcodes with the same name. */
252b5132
RH		 1294 return 0;
1295 }
c4aa876b 1296
6b31947e 1297 /* Look at both operands needed by the opcodes and provided by
252b5132
RH		 1298 the user - since an arg test will often fail on the same arg
1299 again and again, we'll try and test the last failing arg the
6b31947e 1300 first on each opcode try. */
252b5132
RH		 1301 for (n = 0; this_try->arg[n]; n++)
1302 {
1303 sh_operand_info *user = operands + n;
1304 sh_arg_type arg = this_try->arg[n];
c4aa876b 1305
252b5132
RH		 1306 switch (arg)
1307 {
7679ead9
AO		 1308 case A_DISP_PC:
1309 if (user->type == A_DISP_PC_ABS)
1310 break;
1311 /* Fall through. */
252b5132
RH		 1312 case A_IMM:
1313 case A_BDISP12:
1314 case A_BDISP8:
1315 case A_DISP_GBR:
1d70c7fb 1316 case A_DISP2_TBR:
252b5132
RH		 1317 case A_MACH:
1318 case A_PR:
1319 case A_MACL:
1320 if (user->type != arg)
1321 goto fail;
1322 break;
1323 case A_R0:
1324 /* opcode needs r0 */
1325 if (user->type != A_REG_N || user->reg != 0)
1326 goto fail;
1327 break;
1328 case A_R0_GBR:
1329 if (user->type != A_R0_GBR || user->reg != 0)
1330 goto fail;
1331 break;
1332 case F_FR0:
1333 if (user->type != F_REG_N || user->reg != 0)
1334 goto fail;
1335 break;
1336
1337 case A_REG_N:
1338 case A_INC_N:
1339 case A_DEC_N:
1340 case A_IND_N:
1341 case A_IND_R0_REG_N:
1342 case A_DISP_REG_N:
1343 case F_REG_N:
1344 case D_REG_N:
1345 case X_REG_N:
1346 case V_REG_N:
1347 case FPUL_N:
1348 case FPSCR_N:
d4845d57 1349 case DSP_REG_N:
252b5132
RH		 1350 /* Opcode needs rn */
1351 if (user->type != arg)
1352 goto fail;
1353 reg_n = user->reg;
1354 break;
252b5132
RH		 1355 case DX_REG_N:
1356 if (user->type != D_REG_N && user->type != X_REG_N)
1357 goto fail;
1358 reg_n = user->reg;
1359 break;
1360 case A_GBR:
1d70c7fb 1361 case A_TBR:
252b5132
RH		 1362 case A_SR:
1363 case A_VBR:
d4845d57
JR		 1364 case A_DSR:
1365 case A_MOD:
1366 case A_RE:
1367 case A_RS:
252b5132
RH		 1368 case A_SSR:
1369 case A_SPC:
1370 case A_SGR:
1371 case A_DBR:
1372 if (user->type != arg)
1373 goto fail;
1374 break;
1375
c4aa876b 1376 case A_REG_B:
252b5132
RH		 1377 if (user->type != arg)
1378 goto fail;
1379 reg_b = user->reg;
1380 break;
1381
1d70c7fb
AO		 1382 case A_INC_R15:
1383 if (user->type != A_INC_N)
1384 goto fail;
1385 if (user->reg != 15)
1386 goto fail;
1387 reg_n = user->reg;
1388 break;
1389
1390 case A_DEC_R15:
1391 if (user->type != A_DEC_N)
1392 goto fail;
1393 if (user->reg != 15)
1394 goto fail;
1395 reg_n = user->reg;
1396 break;
1397
252b5132
RH		 1398 case A_REG_M:
1399 case A_INC_M:
1400 case A_DEC_M:
1401 case A_IND_M:
1402 case A_IND_R0_REG_M:
1403 case A_DISP_REG_M:
d4845d57 1404 case DSP_REG_M:
252b5132
RH		 1405 /* Opcode needs rn */
1406 if (user->type != arg - A_REG_M + A_REG_N)
1407 goto fail;
1408 reg_m = user->reg;
1409 break;
1410
88da98f3
MS		 1411 case AS_DEC_N:
1412 if (user->type != A_DEC_N)
1413 goto fail;
1414 if (user->reg < 2 || user->reg > 5)
1415 goto fail;
1416 reg_n = user->reg;
1417 break;
13ef8878 1418
88da98f3
MS		 1419 case AS_INC_N:
1420 if (user->type != A_INC_N)
1421 goto fail;
1422 if (user->reg < 2 || user->reg > 5)
1423 goto fail;
1424 reg_n = user->reg;
1425 break;
13ef8878 1426
88da98f3
MS		 1427 case AS_IND_N:
1428 if (user->type != A_IND_N)
1429 goto fail;
1430 if (user->reg < 2 || user->reg > 5)
1431 goto fail;
1432 reg_n = user->reg;
1433 break;
13ef8878 1434
88da98f3
MS		 1435 case AS_PMOD_N:
1436 if (user->type != AX_PMOD_N)
1437 goto fail;
1438 if (user->reg < 2 || user->reg > 5)
1439 goto fail;
1440 reg_n = user->reg;
1441 break;
13ef8878 1442
88da98f3
MS		 1443 case AX_INC_N:
1444 if (user->type != A_INC_N)
1445 goto fail;
1446 if (user->reg < 4 || user->reg > 5)
1447 goto fail;
1448 reg_n = user->reg;
1449 break;
13ef8878 1450
88da98f3
MS		 1451 case AX_IND_N:
1452 if (user->type != A_IND_N)
1453 goto fail;
1454 if (user->reg < 4 || user->reg > 5)
1455 goto fail;
1456 reg_n = user->reg;
1457 break;
13ef8878 1458
88da98f3
MS		 1459 case AX_PMOD_N:
1460 if (user->type != AX_PMOD_N)
1461 goto fail;
1462 if (user->reg < 4 || user->reg > 5)
1463 goto fail;
1464 reg_n = user->reg;
1465 break;
13ef8878 1466
88da98f3
MS		 1467 case AXY_INC_N:
1468 if (user->type != A_INC_N)
1469 goto fail;
1470 if ((user->reg < 4 || user->reg > 5)
1471 && (user->reg < 0 || user->reg > 1))
1472 goto fail;
1473 reg_n = user->reg;
1474 break;
13ef8878 1475
88da98f3
MS		 1476 case AXY_IND_N:
1477 if (user->type != A_IND_N)
1478 goto fail;
1479 if ((user->reg < 4 || user->reg > 5)
1480 && (user->reg < 0 || user->reg > 1))
1481 goto fail;
1482 reg_n = user->reg;
1483 break;
13ef8878 1484
88da98f3
MS		 1485 case AXY_PMOD_N:
1486 if (user->type != AX_PMOD_N)
1487 goto fail;
1488 if ((user->reg < 4 || user->reg > 5)
1489 && (user->reg < 0 || user->reg > 1))
1490 goto fail;
1491 reg_n = user->reg;
1492 break;
13ef8878 1493
88da98f3
MS		 1494 case AY_INC_N:
1495 if (user->type != A_INC_N)
1496 goto fail;
1497 if (user->reg < 6 || user->reg > 7)
1498 goto fail;
1499 reg_n = user->reg;
1500 break;
13ef8878 1501
88da98f3
MS		 1502 case AY_IND_N:
1503 if (user->type != A_IND_N)
1504 goto fail;
1505 if (user->reg < 6 || user->reg > 7)
1506 goto fail;
1507 reg_n = user->reg;
1508 break;
13ef8878 1509
88da98f3
MS		 1510 case AY_PMOD_N:
1511 if (user->type != AY_PMOD_N)
1512 goto fail;
1513 if (user->reg < 6 || user->reg > 7)
1514 goto fail;
1515 reg_n = user->reg;
1516 break;
1517
1518 case AYX_INC_N:
1519 if (user->type != A_INC_N)
1520 goto fail;
1521 if ((user->reg < 6 || user->reg > 7)
1522 && (user->reg < 2 || user->reg > 3))
1523 goto fail;
1524 reg_n = user->reg;
1525 break;
13ef8878 1526
88da98f3
MS		 1527 case AYX_IND_N:
1528 if (user->type != A_IND_N)
1529 goto fail;
1530 if ((user->reg < 6 || user->reg > 7)
1531 && (user->reg < 2 || user->reg > 3))
1532 goto fail;
1533 reg_n = user->reg;
1534 break;
13ef8878 1535
88da98f3
MS		 1536 case AYX_PMOD_N:
1537 if (user->type != AY_PMOD_N)
1538 goto fail;
1539 if ((user->reg < 6 || user->reg > 7)
1540 && (user->reg < 2 || user->reg > 3))
1541 goto fail;
1542 reg_n = user->reg;
1543 break;
1544
1545 case DSP_REG_A_M:
1546 if (user->type != DSP_REG_N)
1547 goto fail;
1548 if (user->reg != A_A0_NUM
1549 && user->reg != A_A1_NUM)
1550 goto fail;
1551 reg_m = user->reg;
1552 break;
1553
1554 case DSP_REG_AX:
1555 if (user->type != DSP_REG_N)
1556 goto fail;
1557 switch (user->reg)
1558 {
1559 case A_A0_NUM:
1560 reg_x = 0;
1561 break;
1562 case A_A1_NUM:
1563 reg_x = 2;
1564 break;
1565 case A_X0_NUM:
1566 reg_x = 1;
1567 break;
1568 case A_X1_NUM:
1569 reg_x = 3;
1570 break;
1571 default:
1572 goto fail;
1573 }
1574 break;
1575
1576 case DSP_REG_XY:
1577 if (user->type != DSP_REG_N)
1578 goto fail;
1579 switch (user->reg)
1580 {
1581 case A_X0_NUM:
1582 reg_x = 0;
1583 break;
1584 case A_X1_NUM:
1585 reg_x = 2;
1586 break;
1587 case A_Y0_NUM:
1588 reg_x = 1;
1589 break;
1590 case A_Y1_NUM:
1591 reg_x = 3;
1592 break;
1593 default:
1594 goto fail;
1595 }
1596 break;
1597
1598 case DSP_REG_AY:
1599 if (user->type != DSP_REG_N)
1600 goto fail;
1601 switch (user->reg)
1602 {
1603 case A_A0_NUM:
1604 reg_y = 0;
1605 break;
1606 case A_A1_NUM:
1607 reg_y = 1;
1608 break;
1609 case A_Y0_NUM:
1610 reg_y = 2;
1611 break;
1612 case A_Y1_NUM:
1613 reg_y = 3;
1614 break;
1615 default:
1616 goto fail;
1617 }
1618 break;
1619
1620 case DSP_REG_YX:
1621 if (user->type != DSP_REG_N)
1622 goto fail;
1623 switch (user->reg)
1624 {
1625 case A_Y0_NUM:
1626 reg_y = 0;
1627 break;
1628 case A_Y1_NUM:
1629 reg_y = 1;
1630 break;
1631 case A_X0_NUM:
1632 reg_y = 2;
1633 break;
1634 case A_X1_NUM:
1635 reg_y = 3;
1636 break;
1637 default:
1638 goto fail;
1639 }
1640 break;
1641
d4845d57
JR		 1642 case DSP_REG_X:
1643 if (user->type != DSP_REG_N)
1644 goto fail;
1645 switch (user->reg)
1646 {
1647 case A_X0_NUM:
1648 reg_x = 0;
1649 break;
1650 case A_X1_NUM:
1651 reg_x = 1;
1652 break;
1653 case A_A0_NUM:
1654 reg_x = 2;
1655 break;
1656 case A_A1_NUM:
1657 reg_x = 3;
1658 break;
1659 default:
1660 goto fail;
1661 }
1662 break;
1663
1664 case DSP_REG_Y:
1665 if (user->type != DSP_REG_N)
1666 goto fail;
1667 switch (user->reg)
1668 {
1669 case A_Y0_NUM:
1670 reg_y = 0;
1671 break;
1672 case A_Y1_NUM:
1673 reg_y = 1;
1674 break;
1675 case A_M0_NUM:
1676 reg_y = 2;
1677 break;
1678 case A_M1_NUM:
1679 reg_y = 3;
1680 break;
1681 default:
1682 goto fail;
1683 }
1684 break;
1685
1686 case DSP_REG_E:
1687 if (user->type != DSP_REG_N)
1688 goto fail;
1689 switch (user->reg)
1690 {
1691 case A_X0_NUM:
1692 reg_efg = 0 << 10;
1693 break;
1694 case A_X1_NUM:
1695 reg_efg = 1 << 10;
1696 break;
1697 case A_Y0_NUM:
1698 reg_efg = 2 << 10;
1699 break;
1700 case A_A1_NUM:
1701 reg_efg = 3 << 10;
1702 break;
1703 default:
1704 goto fail;
1705 }
1706 break;
1707
1708 case DSP_REG_F:
1709 if (user->type != DSP_REG_N)
1710 goto fail;
1711 switch (user->reg)
1712 {
1713 case A_Y0_NUM:
1714 reg_efg |= 0 << 8;
1715 break;
1716 case A_Y1_NUM:
1717 reg_efg |= 1 << 8;
1718 break;
1719 case A_X0_NUM:
1720 reg_efg |= 2 << 8;
1721 break;
1722 case A_A1_NUM:
1723 reg_efg |= 3 << 8;
1724 break;
1725 default:
1726 goto fail;
1727 }
1728 break;
1729
1730 case DSP_REG_G:
1731 if (user->type != DSP_REG_N)
1732 goto fail;
1733 switch (user->reg)
1734 {
1735 case A_M0_NUM:
1736 reg_efg |= 0 << 2;
1737 break;
1738 case A_M1_NUM:
1739 reg_efg |= 1 << 2;
1740 break;
1741 case A_A0_NUM:
1742 reg_efg |= 2 << 2;
1743 break;
1744 case A_A1_NUM:
1745 reg_efg |= 3 << 2;
1746 break;
1747 default:
1748 goto fail;
1749 }
1750 break;
1751
1752 case A_A0:
1753 if (user->type != DSP_REG_N || user->reg != A_A0_NUM)
1754 goto fail;
1755 break;
1756 case A_X0:
1757 if (user->type != DSP_REG_N || user->reg != A_X0_NUM)
1758 goto fail;
1759 break;
1760 case A_X1:
1761 if (user->type != DSP_REG_N || user->reg != A_X1_NUM)
1762 goto fail;
1763 break;
1764 case A_Y0:
1765 if (user->type != DSP_REG_N || user->reg != A_Y0_NUM)
1766 goto fail;
1767 break;
1768 case A_Y1:
1769 if (user->type != DSP_REG_N || user->reg != A_Y1_NUM)
1770 goto fail;
1771 break;
1772
252b5132
RH		 1773 case F_REG_M:
1774 case D_REG_M:
1775 case X_REG_M:
1776 case V_REG_M:
1777 case FPUL_M:
1778 case FPSCR_M:
1779 /* Opcode needs rn */
1780 if (user->type != arg - F_REG_M + F_REG_N)
1781 goto fail;
1782 reg_m = user->reg;
1783 break;
1784 case DX_REG_M:
1785 if (user->type != D_REG_N && user->type != X_REG_N)
1786 goto fail;
1787 reg_m = user->reg;
1788 break;
1789 case XMTRX_M4:
1790 if (user->type != XMTRX_M4)
1791 goto fail;
1792 reg_m = 4;
1793 break;
c4aa876b 1794
252b5132
RH		 1795 default:
1796 printf (_("unhandled %d\n"), arg);
1797 goto fail;
1798 }
772657e9
AS		 1799 if (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh2a_nofpu_up)
1800 && ( arg == A_DISP_REG_M
1801 || arg == A_DISP_REG_N))
1802 {
1803 /* Check a few key IMM* fields for overflow. */
1804 int opf;
1805 long val = user->immediate.X_add_number;
1806
1807 for (opf = 0; opf < 4; opf ++)
1808 switch (this_try->nibbles[opf])
1809 {
1810 case IMM0_4:
1811 case IMM1_4:
1812 if (val < 0 || val > 15)
1813 goto fail;
1814 break;
1815 case IMM0_4BY2:
1816 case IMM1_4BY2:
1817 if (val < 0 || val > 15 * 2)
1818 goto fail;
1819 break;
1820 case IMM0_4BY4:
1821 case IMM1_4BY4:
1822 if (val < 0 || val > 15 * 4)
1823 goto fail;
1824 break;
1825 default:
1826 break;
1827 }
1828 }
252b5132 1829 }
f6f9408f 1830 if ( !SH_MERGE_ARCH_SET_VALID (valid_arch, this_try->arch))
a37c8f88 1831 goto fail;
f6f9408f 1832 valid_arch = SH_MERGE_ARCH_SET (valid_arch, this_try->arch);
252b5132 1833 return this_try;
c4aa876b
NC		 1834 fail:
1835 ;
252b5132
RH		 1836 }
1837
1838 return 0;
1839}
1840
252b5132 1841static void
c4212e11
TS		 1842insert (char *where, bfd_reloc_code_real_type how, int pcrel,
1843 sh_operand_info *op)
252b5132
RH		 1844{
1845 fix_new_exp (frag_now,
1846 where - frag_now->fr_literal,
1847 2,
015551fc 1848 &op->immediate,
252b5132
RH		 1849 pcrel,
1850 how);
1851}
1852
1d70c7fb 1853static void
c4212e11
TS		 1854insert4 (char * where, bfd_reloc_code_real_type how, int pcrel,
1855 sh_operand_info * op)
1d70c7fb
AO		 1856{
1857 fix_new_exp (frag_now,
1858 where - frag_now->fr_literal,
1859 4,
1860 & op->immediate,
1861 pcrel,
1862 how);
1863}
252b5132 1864static void
8edc77b9 1865build_relax (sh_opcode_info *opcode, sh_operand_info *op)
252b5132
RH		 1866{
1867 int high_byte = target_big_endian ? 0 : 1;
1868 char *p;
1869
1870 if (opcode->arg[0] == A_BDISP8)
1871 {
1872 int what = (opcode->nibbles[1] & 4) ? COND_JUMP_DELAY : COND_JUMP;
1873 p = frag_var (rs_machine_dependent,
1874 md_relax_table[C (what, COND32)].rlx_length,
1875 md_relax_table[C (what, COND8)].rlx_length,
1876 C (what, 0),
015551fc
JR		 1877 op->immediate.X_add_symbol,
1878 op->immediate.X_add_number,
252b5132
RH		 1879 0);
1880 p[high_byte] = (opcode->nibbles[0] << 4) | (opcode->nibbles[1]);
1881 }
1882 else if (opcode->arg[0] == A_BDISP12)
1883 {
1884 p = frag_var (rs_machine_dependent,
1885 md_relax_table[C (UNCOND_JUMP, UNCOND32)].rlx_length,
1886 md_relax_table[C (UNCOND_JUMP, UNCOND12)].rlx_length,
1887 C (UNCOND_JUMP, 0),
015551fc
JR		 1888 op->immediate.X_add_symbol,
1889 op->immediate.X_add_number,
252b5132
RH		 1890 0);
1891 p[high_byte] = (opcode->nibbles[0] << 4);
1892 }
1893
1894}
1895
6b31947e 1896/* Insert ldrs & ldre with fancy relocations that relaxation can recognize. */
d67b5d6d 1897
015551fc 1898static char *
8edc77b9 1899insert_loop_bounds (char *output, sh_operand_info *operand)
015551fc 1900{
015551fc
JR		 1901 symbolS *end_sym;
1902
1903 /* Since the low byte of the opcode will be overwritten by the reloc, we
1904 can just stash the high byte into both bytes and ignore endianness. */
1905 output[0] = 0x8c;
1906 output[1] = 0x8c;
1907 insert (output, BFD_RELOC_SH_LOOP_START, 1, operand);
1908 insert (output, BFD_RELOC_SH_LOOP_END, 1, operand + 1);
1909
1910 if (sh_relax)
1911 {
1912 static int count = 0;
e1fa0163 1913 char name[11];
015551fc
JR		 1914
1915 /* If the last loop insn is a two-byte-insn, it is in danger of being
1916 swapped with the insn after it. To prevent this, create a new
1917 symbol - complete with SH_LABEL reloc - after the last loop insn.
1918 If the last loop insn is four bytes long, the symbol will be
1919 right in the middle, but four byte insns are not swapped anyways. */
1920 /* A REPEAT takes 6 bytes. The SH has a 32 bit address space.
1921 Hence a 9 digit number should be enough to count all REPEATs. */
015551fc 1922 sprintf (name, "_R%x", count++ & 0x3fffffff);
c4aa876b 1923 end_sym = symbol_new (name, undefined_section, 0, &zero_address_frag);
015551fc
JR		 1924 /* Make this a local symbol. */
1925#ifdef OBJ_COFF
1926 SF_SET_LOCAL (end_sym);
1927#endif /* OBJ_COFF */
1928 symbol_table_insert (end_sym);
1929 end_sym->sy_value = operand[1].immediate;
1930 end_sym->sy_value.X_add_number += 2;
1931 fix_new (frag_now, frag_now_fix (), 2, end_sym, 0, 1, BFD_RELOC_SH_LABEL);
1932 }
1933
1934 output = frag_more (2);
1935 output[0] = 0x8e;
1936 output[1] = 0x8e;
1937 insert (output, BFD_RELOC_SH_LOOP_START, 1, operand);
1938 insert (output, BFD_RELOC_SH_LOOP_END, 1, operand + 1);
1939
1940 return frag_more (2);
1941}
1942
d67b5d6d 1943/* Now we know what sort of opcodes it is, let's build the bytes. */
6b31947e 1944
0d10e182 1945static unsigned int
8edc77b9 1946build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
252b5132 1947{
91d6fa6a 1948 int indx;
1d70c7fb
AO		 1949 char nbuf[8];
1950 char *output;
0d10e182 1951 unsigned int size = 2;
252b5132 1952 int low_byte = target_big_endian ? 1 : 0;
1d70c7fb 1953 int max_index = 4;
8e45593f 1954 bfd_reloc_code_real_type r_type;
87975d2a 1955#ifdef OBJ_ELF
8e45593f 1956 int unhandled_pic = 0;
87975d2a 1957#endif
1d70c7fb 1958
252b5132
RH		 1959 nbuf[0] = 0;
1960 nbuf[1] = 0;
1961 nbuf[2] = 0;
1962 nbuf[3] = 0;
1d70c7fb
AO		 1963 nbuf[4] = 0;
1964 nbuf[5] = 0;
1965 nbuf[6] = 0;
1966 nbuf[7] = 0;
1967
87975d2a 1968#ifdef OBJ_ELF
8e45593f
NC		 1969 for (indx = 0; indx < 3; indx++)
1970 if (opcode->arg[indx] == A_IMM
1971 && operand[indx].type == A_IMM
1972 && (operand[indx].immediate.X_op == O_PIC_reloc
1973 || sh_PIC_related_p (operand[indx].immediate.X_add_symbol)
1974 || sh_PIC_related_p (operand[indx].immediate.X_op_symbol)))
1975 unhandled_pic = 1;
87975d2a 1976#endif
8e45593f 1977
1d70c7fb
AO		 1978 if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
1979 {
1980 output = frag_more (4);
1981 size = 4;
1982 max_index = 8;
1983 }
1984 else
1985 output = frag_more (2);
252b5132 1986
91d6fa6a 1987 for (indx = 0; indx < max_index; indx++)
252b5132 1988 {
91d6fa6a 1989 sh_nibble_type i = opcode->nibbles[indx];
252b5132
RH		 1990 if (i < 16)
1991 {
91d6fa6a 1992 nbuf[indx] = i;
252b5132
RH		 1993 }
1994 else
1995 {
1996 switch (i)
1997 {
1998 case REG_N:
6a5709a5 1999 case REG_N_D:
91d6fa6a 2000 nbuf[indx] = reg_n;
252b5132
RH		 2001 break;
2002 case REG_M:
91d6fa6a 2003 nbuf[indx] = reg_m;
252b5132 2004 break;
d4845d57
JR		 2005 case SDT_REG_N:
2006 if (reg_n < 2 || reg_n > 5)
2007 as_bad (_("Invalid register: 'r%d'"), reg_n);
91d6fa6a 2008 nbuf[indx] = (reg_n & 3) | 4;
d4845d57 2009 break;
252b5132 2010 case REG_NM:
91d6fa6a 2011 nbuf[indx] = reg_n | (reg_m >> 2);
252b5132 2012 break;
c4aa876b 2013 case REG_B:
91d6fa6a 2014 nbuf[indx] = reg_b | 0x08;
252b5132 2015 break;
6a5709a5 2016 case REG_N_B01:
91d6fa6a 2017 nbuf[indx] = reg_n | 0x01;
6a5709a5 2018 break;
1d70c7fb 2019 case IMM0_3s:
91d6fa6a 2020 nbuf[indx] |= 0x08;
1a0670f3 2021 /* Fall through. */
1d70c7fb
AO		 2022 case IMM0_3c:
2023 insert (output + low_byte, BFD_RELOC_SH_IMM3, 0, operand);
2024 break;
2025 case IMM0_3Us:
91d6fa6a 2026 nbuf[indx] |= 0x80;
1a0670f3 2027 /* Fall through. */
1d70c7fb
AO		 2028 case IMM0_3Uc:
2029 insert (output + low_byte, BFD_RELOC_SH_IMM3U, 0, operand);
2030 break;
2031 case DISP0_12:
2032 insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand);
2033 break;
2034 case DISP0_12BY2:
2035 insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand);
2036 break;
2037 case DISP0_12BY4:
2038 insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand);
2039 break;
2040 case DISP0_12BY8:
2041 insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand);
2042 break;
2043 case DISP1_12:
2044 insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand+1);
2045 break;
2046 case DISP1_12BY2:
2047 insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand+1);
2048 break;
2049 case DISP1_12BY4:
2050 insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand+1);
2051 break;
2052 case DISP1_12BY8:
2053 insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand+1);
2054 break;
2055 case IMM0_20_4:
2056 break;
2057 case IMM0_20:
8e45593f 2058 r_type = BFD_RELOC_SH_DISP20;
87975d2a 2059#ifdef OBJ_ELF
8e45593f
NC		 2060 if (sh_check_fixup (&operand->immediate, &r_type))
2061 as_bad (_("Invalid PIC expression."));
2062 unhandled_pic = 0;
87975d2a 2063#endif
8e45593f 2064 insert4 (output, r_type, 0, operand);
1d70c7fb
AO		 2065 break;
2066 case IMM0_20BY8:
2067 insert4 (output, BFD_RELOC_SH_DISP20BY8, 0, operand);
2068 break;
015551fc
JR		 2069 case IMM0_4BY4:
2070 insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand);
2071 break;
2072 case IMM0_4BY2:
2073 insert (output + low_byte, BFD_RELOC_SH_IMM4BY2, 0, operand);
2074 break;
2075 case IMM0_4:
2076 insert (output + low_byte, BFD_RELOC_SH_IMM4, 0, operand);
2077 break;
2078 case IMM1_4BY4:
2079 insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand + 1);
2080 break;
2081 case IMM1_4BY2:
2082 insert (output + low_byte, BFD_RELOC_SH_IMM4BY2, 0, operand + 1);
252b5132 2083 break;
015551fc
JR		 2084 case IMM1_4:
2085 insert (output + low_byte, BFD_RELOC_SH_IMM4, 0, operand + 1);
252b5132 2086 break;
015551fc
JR		 2087 case IMM0_8BY4:
2088 insert (output + low_byte, BFD_RELOC_SH_IMM8BY4, 0, operand);
252b5132 2089 break;
015551fc
JR		 2090 case IMM0_8BY2:
2091 insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand);
252b5132 2092 break;
015551fc
JR		 2093 case IMM0_8:
2094 insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand);
252b5132 2095 break;
015551fc
JR		 2096 case IMM1_8BY4:
2097 insert (output + low_byte, BFD_RELOC_SH_IMM8BY4, 0, operand + 1);
252b5132 2098 break;
015551fc
JR		 2099 case IMM1_8BY2:
2100 insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand + 1);
2101 break;
2102 case IMM1_8:
2103 insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand + 1);
252b5132
RH		 2104 break;
2105 case PCRELIMM_8BY4:
7679ead9
AO		 2106 insert (output, BFD_RELOC_SH_PCRELIMM8BY4,
2107 operand->type != A_DISP_PC_ABS, operand);
252b5132
RH		 2108 break;
2109 case PCRELIMM_8BY2:
7679ead9
AO		 2110 insert (output, BFD_RELOC_SH_PCRELIMM8BY2,
2111 operand->type != A_DISP_PC_ABS, operand);
015551fc
JR		 2112 break;
2113 case REPEAT:
2114 output = insert_loop_bounds (output, operand);
91d6fa6a 2115 nbuf[indx] = opcode->nibbles[3];
015551fc 2116 operand += 2;
252b5132
RH		 2117 break;
2118 default:
2119 printf (_("failed for %d\n"), i);
2120 }
2121 }
2122 }
87975d2a 2123#ifdef OBJ_ELF
8e45593f
NC		 2124 if (unhandled_pic)
2125 as_bad (_("misplaced PIC operand"));
87975d2a 2126#endif
c4aa876b
NC		 2127 if (!target_big_endian)
2128 {
2129 output[1] = (nbuf[0] << 4) | (nbuf[1]);
2130 output[0] = (nbuf[2] << 4) | (nbuf[3]);
2131 }
2132 else
2133 {
2134 output[0] = (nbuf[0] << 4) | (nbuf[1]);
2135 output[1] = (nbuf[2] << 4) | (nbuf[3]);
2136 }
1d70c7fb
AO		 2137 if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
2138 {
2139 if (!target_big_endian)
2140 {
2141 output[3] = (nbuf[4] << 4) | (nbuf[5]);
2142 output[2] = (nbuf[6] << 4) | (nbuf[7]);
2143 }
2144 else
2145 {
2146 output[2] = (nbuf[4] << 4) | (nbuf[5]);
2147 output[3] = (nbuf[6] << 4) | (nbuf[7]);
2148 }
2149 }
0d10e182 2150 return size;
252b5132
RH		 2151}
2152
d4845d57
JR		 2153/* Find an opcode at the start of *STR_P in the hash table, and set
2154 *STR_P to the first character after the last one read. */
252b5132 2155
d4845d57 2156static sh_opcode_info *
8edc77b9 2157find_cooked_opcode (char **str_p)
252b5132 2158{
d4845d57 2159 char *str = *str_p;
252b5132
RH		 2160 unsigned char *op_start;
2161 unsigned char *op_end;
252b5132 2162 char name[20];
6d0cb78c 2163 unsigned int nlen = 0;
c4aa876b 2164
6b31947e 2165 /* Drop leading whitespace. */
252b5132
RH		 2166 while (*str == ' ')
2167 str++;
2168
d4845d57
JR		 2169 /* Find the op code end.
2170 The pre-processor will eliminate whitespace in front of
2171 any '@' after the first argument; we may be called from
2172 assemble_ppi, so the opcode might be terminated by an '@'. */
2132e3a3 2173 for (op_start = op_end = (unsigned char *) str;
252b5132 2174 *op_end
6d0cb78c 2175 && nlen < sizeof (name) - 1
d4845d57 2176 && !is_end_of_line[*op_end] && *op_end != ' ' && *op_end != '@';
252b5132
RH		 2177 op_end++)
2178 {
2179 unsigned char c = op_start[nlen];
2180
2181 /* The machine independent code will convert CMP/EQ into cmp/EQ
d4845d57
JR		 2182 because it thinks the '/' is the end of the symbol. Moreover,
2183 all but the first sub-insn is a parallel processing insn won't
3882b010 2184 be capitalized. Instead of hacking up the machine independent
d4845d57 2185 code, we just deal with it here. */
3882b010 2186 c = TOLOWER (c);
252b5132
RH		 2187 name[nlen] = c;
2188 nlen++;
2189 }
c4aa876b 2190
252b5132 2191 name[nlen] = 0;
2132e3a3 2192 *str_p = (char *) op_end;
252b5132
RH		 2193
2194 if (nlen == 0)
6b31947e 2195 as_bad (_("can't find opcode "));
252b5132 2196
d4845d57
JR		 2197 return (sh_opcode_info *) hash_find (opcode_hash_control, name);
2198}
2199
2200/* Assemble a parallel processing insn. */
2201#define DDT_BASE 0xf000 /* Base value for double data transfer insns */
6b31947e 2202
0d10e182 2203static unsigned int
8edc77b9 2204assemble_ppi (char *op_end, sh_opcode_info *opcode)
d4845d57
JR		 2205{
2206 int movx = 0;
2207 int movy = 0;
2208 int cond = 0;
2209 int field_b = 0;
2210 char *output;
2211 int move_code;
0d10e182 2212 unsigned int size;
d4845d57 2213
d4845d57
JR		 2214 for (;;)
2215 {
2216 sh_operand_info operand[3];
2217
ac62e7a3
JR		 2218 /* Some insn ignore one or more register fields, e.g. psts machl,a0.
2219 Make sure we encode a defined insn pattern. */
2220 reg_x = 0;
2221 reg_y = 0;
2222 reg_n = 0;
2223
d4845d57
JR		 2224 if (opcode->arg[0] != A_END)
2225 op_end = get_operands (opcode, op_end, operand);
88da98f3 2226 try_another_opcode:
d4845d57
JR		 2227 opcode = get_specific (opcode, operand);
2228 if (opcode == 0)
2229 {
6b31947e 2230 /* Couldn't find an opcode which matched the operands. */
d4845d57 2231 char *where = frag_more (2);
0d10e182 2232 size = 2;
d4845d57
JR		 2233
2234 where[0] = 0x0;
2235 where[1] = 0x0;
2236 as_bad (_("invalid operands for opcode"));
0d10e182 2237 return size;
d4845d57 2238 }
c4aa876b 2239
d4845d57
JR		 2240 if (opcode->nibbles[0] != PPI)
2241 as_bad (_("insn can't be combined with parallel processing insn"));
2242
2243 switch (opcode->nibbles[1])
2244 {
2245
2246 case NOPX:
2247 if (movx)
2248 as_bad (_("multiple movx specifications"));
2249 movx = DDT_BASE;
2250 break;
2251 case NOPY:
2252 if (movy)
2253 as_bad (_("multiple movy specifications"));
2254 movy = DDT_BASE;
2255 break;
2256
88da98f3
MS		 2257 case MOVX_NOPY:
2258 if (movx)
2259 as_bad (_("multiple movx specifications"));
2260 if ((reg_n < 4 || reg_n > 5)
2261 && (reg_n < 0 || reg_n > 1))
2262 as_bad (_("invalid movx address register"));
2263 if (movy && movy != DDT_BASE)
2264 as_bad (_("insn cannot be combined with non-nopy"));
2265 movx = ((((reg_n & 1) != 0) << 9)
2266 + (((reg_n & 4) == 0) << 8)
2267 + (reg_x << 6)
2268 + (opcode->nibbles[2] << 4)
2269 + opcode->nibbles[3]
2270 + DDT_BASE);
2271 break;
2272
2273 case MOVY_NOPX:
2274 if (movy)
2275 as_bad (_("multiple movy specifications"));
2276 if ((reg_n < 6 || reg_n > 7)
2277 && (reg_n < 2 || reg_n > 3))
2278 as_bad (_("invalid movy address register"));
2279 if (movx && movx != DDT_BASE)
2280 as_bad (_("insn cannot be combined with non-nopx"));
2281 movy = ((((reg_n & 1) != 0) << 8)
2282 + (((reg_n & 4) == 0) << 9)
2283 + (reg_y << 6)
2284 + (opcode->nibbles[2] << 4)
2285 + opcode->nibbles[3]
2286 + DDT_BASE);
2287 break;
2288
d4845d57
JR		 2289 case MOVX:
2290 if (movx)
2291 as_bad (_("multiple movx specifications"));
88da98f3
MS		 2292 if (movy & 0x2ac)
2293 as_bad (_("previous movy requires nopx"));
d4845d57
JR		 2294 if (reg_n < 4 || reg_n > 5)
2295 as_bad (_("invalid movx address register"));
2296 if (opcode->nibbles[2] & 8)
2297 {
2298 if (reg_m == A_A1_NUM)
2299 movx = 1 << 7;
2300 else if (reg_m != A_A0_NUM)
2301 as_bad (_("invalid movx dsp register"));
2302 }
2303 else
2304 {
2305 if (reg_x > 1)
2306 as_bad (_("invalid movx dsp register"));
2307 movx = reg_x << 7;
2308 }
2309 movx += ((reg_n - 4) << 9) + (opcode->nibbles[2] << 2) + DDT_BASE;
2310 break;
2311
2312 case MOVY:
2313 if (movy)
2314 as_bad (_("multiple movy specifications"));
88da98f3
MS		 2315 if (movx & 0x153)
2316 as_bad (_("previous movx requires nopy"));
d4845d57
JR		 2317 if (opcode->nibbles[2] & 8)
2318 {
2319 /* Bit 3 in nibbles[2] is intended for bit 4 of the opcode,
2320 so add 8 more. */
2321 movy = 8;
2322 if (reg_m == A_A1_NUM)
2323 movy += 1 << 6;
2324 else if (reg_m != A_A0_NUM)
2325 as_bad (_("invalid movy dsp register"));
2326 }
2327 else
2328 {
2329 if (reg_y > 1)
2330 as_bad (_("invalid movy dsp register"));
2331 movy = reg_y << 6;
2332 }
2333 if (reg_n < 6 || reg_n > 7)
2334 as_bad (_("invalid movy address register"));
2335 movy += ((reg_n - 6) << 8) + opcode->nibbles[2] + DDT_BASE;
2336 break;
2337
2338 case PSH:
015551fc 2339 if (operand[0].immediate.X_op != O_constant)
d4845d57
JR		 2340 as_bad (_("dsp immediate shift value not constant"));
2341 field_b = ((opcode->nibbles[2] << 12)
015551fc 2342 | (operand[0].immediate.X_add_number & 127) << 4
d4845d57
JR		 2343 | reg_n);
2344 break;
88da98f3
MS		 2345 case PPI3NC:
2346 if (cond)
2347 {
2348 opcode++;
2349 goto try_another_opcode;
2350 }
2351 /* Fall through. */
d4845d57
JR		 2352 case PPI3:
2353 if (field_b)
2354 as_bad (_("multiple parallel processing specifications"));
2355 field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8)
2356 + (reg_x << 6) + (reg_y << 4) + reg_n);
88da98f3
MS		 2357 switch (opcode->nibbles[4])
2358 {
2359 case HEX_0:
2360 case HEX_XX00:
2361 case HEX_00YY:
2362 break;
2363 case HEX_1:
2364 case HEX_4:
2365 field_b += opcode->nibbles[4] << 4;
2366 break;
2367 default:
2368 abort ();
2369 }
d4845d57
JR		 2370 break;
2371 case PDC:
2372 if (cond)
2373 as_bad (_("multiple condition specifications"));
2374 cond = opcode->nibbles[2] << 8;
2375 if (*op_end)
2376 goto skip_cond_check;
2377 break;
2378 case PPIC:
2379 if (field_b)
2380 as_bad (_("multiple parallel processing specifications"));
2381 field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8)
2382 + cond + (reg_x << 6) + (reg_y << 4) + reg_n);
2383 cond = 0;
88da98f3
MS		 2384 switch (opcode->nibbles[4])
2385 {
2386 case HEX_0:
2387 case HEX_XX00:
2388 case HEX_00YY:
2389 break;
2390 case HEX_1:
2391 case HEX_4:
2392 field_b += opcode->nibbles[4] << 4;
2393 break;
2394 default:
2395 abort ();
2396 }
d4845d57
JR		 2397 break;
2398 case PMUL:
2399 if (field_b)
2400 {
88da98f3
MS		 2401 if ((field_b & 0xef00) == 0xa100)
2402 field_b -= 0x8100;
2403 /* pclr Dz pmuls Se,Sf,Dg */
2404 else if ((field_b & 0xff00) == 0x8d00
f6f9408f 2405 && (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh4al_dsp_up)))
88da98f3 2406 {
f6f9408f 2407 valid_arch = SH_MERGE_ARCH_SET (valid_arch, arch_sh4al_dsp_up);
88da98f3
MS		 2408 field_b -= 0x8cf0;
2409 }
2410 else
d4845d57 2411 as_bad (_("insn cannot be combined with pmuls"));
d4845d57
JR		 2412 switch (field_b & 0xf)
2413 {
2414 case A_X0_NUM:
2415 field_b += 0 - A_X0_NUM;
2416 break;
2417 case A_Y0_NUM:
2418 field_b += 1 - A_Y0_NUM;
2419 break;
2420 case A_A0_NUM:
2421 field_b += 2 - A_A0_NUM;
2422 break;
2423 case A_A1_NUM:
2424 field_b += 3 - A_A1_NUM;
2425 break;
2426 default:
88da98f3 2427 as_bad (_("bad combined pmuls output operand"));
d4845d57 2428 }
7dd04abd
JR		 2429 /* Generate warning if the destination register for padd / psub
2430 and pmuls is the same ( only for A0 or A1 ).
2431 If the last nibble is 1010 then A0 is used in both
2432 padd / psub and pmuls. If it is 1111 then A1 is used
2433 as destination register in both padd / psub and pmuls. */
5db33d76
JR		 2434
2435 if ((((field_b | reg_efg) & 0x000F) == 0x000A)
2436 || (((field_b | reg_efg) & 0x000F) == 0x000F))
2437 as_warn (_("destination register is same for parallel insns"));
d4845d57
JR		 2438 }
2439 field_b += 0x4000 + reg_efg;
2440 break;
2441 default:
2442 abort ();
2443 }
2444 if (cond)
2445 {
2446 as_bad (_("condition not followed by conditionalizable insn"));
2447 cond = 0;
2448 }
2449 if (! *op_end)
2450 break;
2451 skip_cond_check:
2452 opcode = find_cooked_opcode (&op_end);
2453 if (opcode == NULL)
2454 {
2455 (as_bad
2456 (_("unrecognized characters at end of parallel processing insn")));
2457 break;
2458 }
2459 }
2460
2461 move_code = movx | movy;
2462 if (field_b)
2463 {
2464 /* Parallel processing insn. */
2465 unsigned long ppi_code = (movx | movy | 0xf800) << 16 | field_b;
2466
2467 output = frag_more (4);
0d10e182 2468 size = 4;
d4845d57
JR		 2469 if (! target_big_endian)
2470 {
2471 output[3] = ppi_code >> 8;
2472 output[2] = ppi_code;
2473 }
2474 else
2475 {
2476 output[2] = ppi_code >> 8;
2477 output[3] = ppi_code;
2478 }
2479 move_code |= 0xf800;
2480 }
2481 else
0d10e182
JL		 2482 {
2483 /* Just a double data transfer. */
2484 output = frag_more (2);
2485 size = 2;
2486 }
d4845d57
JR		 2487 if (! target_big_endian)
2488 {
2489 output[1] = move_code >> 8;
2490 output[0] = move_code;
2491 }
2492 else
2493 {
2494 output[0] = move_code >> 8;
2495 output[1] = move_code;
2496 }
0d10e182 2497 return size;
d4845d57
JR		 2498}
2499
2500/* This is the guts of the machine-dependent assembler. STR points to a
2501 machine dependent instruction. This function is supposed to emit
6b31947e 2502 the frags/bytes it assembles to. */
d4845d57
JR		 2503
2504void
8edc77b9 2505md_assemble (char *str)
d4845d57 2506{
2132e3a3 2507 char *op_end;
d4845d57
JR		 2508 sh_operand_info operand[3];
2509 sh_opcode_info *opcode;
dda5ecfc 2510 unsigned int size = 0;
ae51a426 2511 char *initial_str = str;
d4845d57
JR		 2512
2513 opcode = find_cooked_opcode (&str);
2514 op_end = str;
252b5132
RH		 2515
2516 if (opcode == NULL)
2517 {
ae51a426 2518 /* The opcode is not in the hash table.
708587a4 2519 This means we definitely have an assembly failure,
ae51a426
JR		 2520 but the instruction may be valid in another CPU variant.
2521 In this case emit something better than 'unknown opcode'.
2522 Search the full table in sh-opc.h to check. */
2523
2524 char *name = initial_str;
2525 int name_length = 0;
2526 const sh_opcode_info *op;
2527 int found = 0;
2528
2529 /* identify opcode in string */
871ec896 2530 while (ISSPACE (*name))
ae51a426
JR		 2531 {
2532 name++;
2533 }
871ec896 2534 while (!ISSPACE (name[name_length]))
ae51a426
JR		 2535 {
2536 name_length++;
2537 }
2538
2539 /* search for opcode in full list */
2540 for (op = sh_table; op->name; op++)
2541 {
f6f9408f
JR		 2542 if (strncasecmp (op->name, name, name_length) == 0
2543 && op->name[name_length] == '\0')
ae51a426
JR		 2544 {
2545 found = 1;
2546 break;
2547 }
2548 }
2549
2550 if ( found )
2551 {
2552 as_bad (_("opcode not valid for this cpu variant"));
2553 }
2554 else
2555 {
2556 as_bad (_("unknown opcode"));
2557 }
252b5132
RH		 2558 return;
2559 }
2560
2561 if (sh_relax
2562 && ! seg_info (now_seg)->tc_segment_info_data.in_code)
2563 {
2564 /* Output a CODE reloc to tell the linker that the following
2565 bytes are instructions, not data. */
2566 fix_new (frag_now, frag_now_fix (), 2, &abs_symbol, 0, 0,
2567 BFD_RELOC_SH_CODE);
2568 seg_info (now_seg)->tc_segment_info_data.in_code = 1;
2569 }
2570
d4845d57
JR		 2571 if (opcode->nibbles[0] == PPI)
2572 {
0d10e182 2573 size = assemble_ppi (op_end, opcode);
252b5132
RH		 2574 }
2575 else
2576 {
0d10e182
JL		 2577 if (opcode->arg[0] == A_BDISP12
2578 || opcode->arg[0] == A_BDISP8)
252b5132 2579 {
26c9b704
JR		 2580 /* Since we skip get_specific here, we have to check & update
2581 valid_arch now. */
f6f9408f
JR		 2582 if (SH_MERGE_ARCH_SET_VALID (valid_arch, opcode->arch))
2583 valid_arch = SH_MERGE_ARCH_SET (valid_arch, opcode->arch);
26c9b704
JR		 2584 else
2585 as_bad (_("Delayed branches not available on SH1"));
0d10e182
JL		 2586 parse_exp (op_end + 1, &operand[0]);
2587 build_relax (opcode, &operand[0]);
86157c20
AS		 2588
2589 /* All branches are currently 16 bit. */
2590 size = 2;
5fc44b2d
JR		 2591 }
2592 else
2593 {
0d10e182
JL		 2594 if (opcode->arg[0] == A_END)
2595 {
2596 /* Ignore trailing whitespace. If there is any, it has already
2597 been compressed to a single space. */
2598 if (*op_end == ' ')
2599 op_end++;
2600 }
2601 else
2602 {
2603 op_end = get_operands (opcode, op_end, operand);
2604 }
2605 opcode = get_specific (opcode, operand);
252b5132 2606
0d10e182
JL		 2607 if (opcode == 0)
2608 {
2609 /* Couldn't find an opcode which matched the operands. */
2610 char *where = frag_more (2);
2611 size = 2;
252b5132 2612
0d10e182
JL		 2613 where[0] = 0x0;
2614 where[1] = 0x0;
2615 as_bad (_("invalid operands for opcode"));
2616 }
2617 else
2618 {
2619 if (*op_end)
2620 as_bad (_("excess operands: '%s'"), op_end);
2621
2622 size = build_Mytes (opcode, operand);
2623 }
252b5132 2624 }
0d10e182 2625 }
252b5132 2626
4dc7ead9 2627 dwarf2_emit_insn (size);
252b5132
RH		 2628}
2629
2630/* This routine is called each time a label definition is seen. It
2631 emits a BFD_RELOC_SH_LABEL reloc if necessary. */
2632
2633void
07a53e5c 2634sh_frob_label (symbolS *sym)
252b5132
RH		 2635{
2636 static fragS *last_label_frag;
2637 static int last_label_offset;
2638
2639 if (sh_relax
2640 && seg_info (now_seg)->tc_segment_info_data.in_code)
2641 {
2642 int offset;
2643
2644 offset = frag_now_fix ();
2645 if (frag_now != last_label_frag
2646 || offset != last_label_offset)
c4aa876b 2647 {
252b5132
RH		 2648 fix_new (frag_now, offset, 2, &abs_symbol, 0, 0, BFD_RELOC_SH_LABEL);
2649 last_label_frag = frag_now;
2650 last_label_offset = offset;
2651 }
2652 }
07a53e5c
RH		 2653
2654 dwarf2_emit_label (sym);
252b5132
RH		 2655}
2656
2657/* This routine is called when the assembler is about to output some
2658 data. It emits a BFD_RELOC_SH_DATA reloc if necessary. */
2659
2660void
8edc77b9 2661sh_flush_pending_output (void)
252b5132
RH		 2662{
2663 if (sh_relax
2664 && seg_info (now_seg)->tc_segment_info_data.in_code)
2665 {
2666 fix_new (frag_now, frag_now_fix (), 2, &abs_symbol, 0, 0,
2667 BFD_RELOC_SH_DATA);
2668 seg_info (now_seg)->tc_segment_info_data.in_code = 0;
2669 }
2670}
2671
2672symbolS *
8edc77b9 2673md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 2674{
2675 return 0;
2676}
2677
6b31947e 2678/* Various routines to kill one day. */
6b31947e 2679
6d4af3c2 2680const char *
8edc77b9 2681md_atof (int type, char *litP, int *sizeP)
252b5132 2682{
499ac353 2683 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH		 2684}
2685
2686/* Handle the .uses pseudo-op. This pseudo-op is used just before a
2687 call instruction. It refers to a label of the instruction which
2688 loads the register which the call uses. We use it to generate a
2689 special reloc for the linker. */
2690
2691static void
8edc77b9 2692s_uses (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 2693{
2694 expressionS ex;
2695
2696 if (! sh_relax)
2697 as_warn (_(".uses pseudo-op seen when not relaxing"));
2698
2699 expression (&ex);
2700
2701 if (ex.X_op != O_symbol || ex.X_add_number != 0)
2702 {
2703 as_bad (_("bad .uses format"));
2704 ignore_rest_of_line ();
2705 return;
2706 }
2707
2708 fix_new_exp (frag_now, frag_now_fix (), 2, &ex, 1, BFD_RELOC_SH_USES);
2709
2710 demand_empty_rest_of_line ();
2711}
2712\f
37dedf66
NC		 2713enum options
2714{
2715 OPTION_RELAX = OPTION_MD_BASE,
2716 OPTION_BIG,
2717 OPTION_LITTLE,
2718 OPTION_SMALL,
2719 OPTION_DSP,
2720 OPTION_ISA,
2721 OPTION_RENESAS,
2722 OPTION_ALLOW_REG_PREFIX,
6fd4f6cc 2723 OPTION_H_TICK_HEX,
8e45593f
NC		 2724#ifdef OBJ_ELF
2725 OPTION_FDPIC,
2726#endif
37dedf66
NC		 2727 OPTION_DUMMY /* Not used. This is just here to make it easy to add and subtract options from this enum. */
2728};
2729
5a38dc70 2730const char *md_shortopts = "";
6b31947e
NC		 2731struct option md_longopts[] =
2732{
252b5132 2733 {"relax", no_argument, NULL, OPTION_RELAX},
05982cac 2734 {"big", no_argument, NULL, OPTION_BIG},
252b5132 2735 {"little", no_argument, NULL, OPTION_LITTLE},
784906c5
NC		 2736 /* The next two switches are here because the
2737 generic parts of the linker testsuite uses them. */
2738 {"EB", no_argument, NULL, OPTION_BIG},
2739 {"EL", no_argument, NULL, OPTION_LITTLE},
252b5132 2740 {"small", no_argument, NULL, OPTION_SMALL},
d4845d57 2741 {"dsp", no_argument, NULL, OPTION_DSP},
37dedf66 2742 {"isa", required_argument, NULL, OPTION_ISA},
f55629b8 2743 {"renesas", no_argument, NULL, OPTION_RENESAS},
37dedf66 2744 {"allow-reg-prefix", no_argument, NULL, OPTION_ALLOW_REG_PREFIX},
f55629b8 2745
6fd4f6cc 2746 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX },
324bfcf3 2747
8e45593f
NC		 2748#ifdef OBJ_ELF
2749 {"fdpic", no_argument, NULL, OPTION_FDPIC},
2750#endif
2751
252b5132
RH		 2752 {NULL, no_argument, NULL, 0}
2753};
c4aa876b 2754size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 2755
2756int
17b9d67d 2757md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
252b5132
RH		 2758{
2759 switch (c)
2760 {
2761 case OPTION_RELAX:
2762 sh_relax = 1;
2763 break;
2764
05982cac
HPN		 2765 case OPTION_BIG:
2766 target_big_endian = 1;
2767 break;
2768
252b5132 2769 case OPTION_LITTLE:
252b5132
RH		 2770 target_big_endian = 0;
2771 break;
2772
2773 case OPTION_SMALL:
2774 sh_small = 1;
2775 break;
2776
d4845d57 2777 case OPTION_DSP:
e38bc3b5 2778 preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
d4845d57
JR		 2779 break;
2780
f55629b8
KK		 2781 case OPTION_RENESAS:
2782 dont_adjust_reloc_32 = 1;
2783 break;
2784
37dedf66
NC		 2785 case OPTION_ALLOW_REG_PREFIX:
2786 allow_dollar_register_prefix = 1;
2787 break;
2788
324bfcf3 2789 case OPTION_ISA:
871ec896 2790 if (strcasecmp (arg, "dsp") == 0)
e38bc3b5 2791 preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
88da98f3 2792 else if (strcasecmp (arg, "fp") == 0)
e38bc3b5 2793 preset_target_arch = arch_sh_up & ~arch_sh_has_dsp;
bdfaef52 2794 else if (strcasecmp (arg, "any") == 0)
e38bc3b5 2795 preset_target_arch = arch_sh_up;
324bfcf3 2796 else
f6f9408f
JR		 2797 {
2798 extern const bfd_arch_info_type bfd_sh_arch;
871ec896 2799 bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
37dedf66 2800
f6f9408f
JR		 2801 preset_target_arch = 0;
2802 for (; bfd_arch; bfd_arch=bfd_arch->next)
2803 {
2804 int len = strlen(bfd_arch->printable_name);
3739860c 2805
f6f9408f
JR		 2806 if (strncasecmp (bfd_arch->printable_name, arg, len) != 0)
2807 continue;
2808
2809 if (arg[len] == '\0')
2810 preset_target_arch =
2811 sh_get_arch_from_bfd_mach (bfd_arch->mach);
2812 else if (strcasecmp(&arg[len], "-up") == 0)
2813 preset_target_arch =
2814 sh_get_arch_up_from_bfd_mach (bfd_arch->mach);
2815 else
2816 continue;
2817 break;
2818 }
3739860c 2819
f6f9408f 2820 if (!preset_target_arch)
20203fb9 2821 as_bad (_("Invalid argument to --isa option: %s"), arg);
f6f9408f 2822 }
324bfcf3
AO		 2823 break;
2824
6fd4f6cc
DD		 2825 case OPTION_H_TICK_HEX:
2826 enable_h_tick_hex = 1;
2827 break;
2828
8e45593f
NC		 2829#ifdef OBJ_ELF
2830 case OPTION_FDPIC:
2831 sh_fdpic = TRUE;
2832 break;
2833#endif /* OBJ_ELF */
2834
252b5132
RH		 2835 default:
2836 return 0;
2837 }
2838
2839 return 1;
2840}
2841
2842void
8edc77b9 2843md_show_usage (FILE *stream)
252b5132 2844{
c4aa876b 2845 fprintf (stream, _("\
252b5132 2846SH options:\n\
37dedf66
NC		 2847--little generate little endian code\n\
2848--big generate big endian code\n\
2849--relax alter jump instructions for long displacements\n\
2850--renesas disable optimization with section symbol for\n\
f55629b8 2851 compatibility with Renesas assembler.\n\
37dedf66
NC		 2852--small align sections to 4 byte boundaries, not 16\n\
2853--dsp enable sh-dsp insns, and disable floating-point ISAs.\n\
2854--allow-reg-prefix allow '$' as a register name prefix.\n\
2855--isa=[any use most appropriate isa\n\
ae51a426 2856 | dsp same as '-dsp'\n\
f6f9408f
JR		 2857 | fp"));
2858 {
2859 extern const bfd_arch_info_type bfd_sh_arch;
871ec896 2860 bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
37dedf66 2861
f6f9408f 2862 for (; bfd_arch; bfd_arch=bfd_arch->next)
211dc24b
AM		 2863 {
2864 fprintf (stream, "\n | %s", bfd_arch->printable_name);
2865 fprintf (stream, "\n | %s-up", bfd_arch->printable_name);
2866 }
f6f9408f
JR		 2867 }
2868 fprintf (stream, "]\n");
8e45593f
NC		 2869#ifdef OBJ_ELF
2870 fprintf (stream, _("\
2871--fdpic generate an FDPIC object file\n"));
2872#endif /* OBJ_ELF */
252b5132
RH		 2873}
2874\f
252b5132
RH		 2875/* This struct is used to pass arguments to sh_count_relocs through
2876 bfd_map_over_sections. */
2877
2878struct sh_count_relocs
2879{
2880 /* Symbol we are looking for. */
2881 symbolS *sym;
2882 /* Count of relocs found. */
2883 int count;
2884};
2885
2886/* Count the number of fixups in a section which refer to a particular
7be1c489 2887 symbol. This is called via bfd_map_over_sections. */
252b5132 2888
252b5132 2889static void
8edc77b9 2890sh_count_relocs (bfd *abfd ATTRIBUTE_UNUSED, segT sec, void *data)
252b5132
RH		 2891{
2892 struct sh_count_relocs *info = (struct sh_count_relocs *) data;
2893 segment_info_type *seginfo;
2894 symbolS *sym;
2895 fixS *fix;
2896
2897 seginfo = seg_info (sec);
2898 if (seginfo == NULL)
2899 return;
2900
2901 sym = info->sym;
2902 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
2903 {
2904 if (fix->fx_addsy == sym)
2905 {
2906 ++info->count;
2907 fix->fx_tcbit = 1;
2908 }
2909 }
2910}
2911
7be1c489
AM		 2912/* Handle the count relocs for a particular section.
2913 This is called via bfd_map_over_sections. */
252b5132 2914
252b5132 2915static void
8edc77b9
KK		 2916sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
2917 void *ignore ATTRIBUTE_UNUSED)
252b5132
RH		 2918{
2919 segment_info_type *seginfo;
2920 fixS *fix;
2921
2922 seginfo = seg_info (sec);
2923 if (seginfo == NULL)
2924 return;
2925
e14e52f8
DD		 2926 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
2927 {
2928 symbolS *sym;
2929
2930 sym = fix->fx_addsy;
2931 /* Check for a local_symbol. */
2932 if (sym && sym->bsym == NULL)
2933 {
2934 struct local_symbol *ls = (struct local_symbol *)sym;
2935 /* See if it's been converted. If so, canonicalize. */
2936 if (local_symbol_converted_p (ls))
2937 fix->fx_addsy = local_symbol_get_real_symbol (ls);
2938 }
2939 }
2940
252b5132
RH		 2941 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
2942 {
2943 symbolS *sym;
2944 bfd_vma val;
2945 fixS *fscan;
2946 struct sh_count_relocs info;
2947
2948 if (fix->fx_r_type != BFD_RELOC_SH_USES)
2949 continue;
2950
2951 /* The BFD_RELOC_SH_USES reloc should refer to a defined local
2952 symbol in the same section. */
2953 sym = fix->fx_addsy;
2954 if (sym == NULL
2955 || fix->fx_subsy != NULL
2956 || fix->fx_addnumber != 0
2957 || S_GET_SEGMENT (sym) != sec
252b5132
RH		 2958 || S_IS_EXTERNAL (sym))
2959 {
2960 as_warn_where (fix->fx_file, fix->fx_line,
2961 _(".uses does not refer to a local symbol in the same section"));
2962 continue;
2963 }
2964
2965 /* Look through the fixups again, this time looking for one
2966 at the same location as sym. */
2967 val = S_GET_VALUE (sym);
2968 for (fscan = seginfo->fix_root;
2969 fscan != NULL;
2970 fscan = fscan->fx_next)
2971 if (val == fscan->fx_frag->fr_address + fscan->fx_where
2972 && fscan->fx_r_type != BFD_RELOC_SH_ALIGN
2973 && fscan->fx_r_type != BFD_RELOC_SH_CODE
2974 && fscan->fx_r_type != BFD_RELOC_SH_DATA
2975 && fscan->fx_r_type != BFD_RELOC_SH_LABEL)
2976 break;
2977 if (fscan == NULL)
2978 {
2979 as_warn_where (fix->fx_file, fix->fx_line,
2980 _("can't find fixup pointed to by .uses"));
2981 continue;
2982 }
2983
2984 if (fscan->fx_tcbit)
2985 {
2986 /* We've already done this one. */
2987 continue;
2988 }
2989
6b31947e
NC		 2990 /* The variable fscan should also be a fixup to a local symbol
2991 in the same section. */
252b5132
RH		 2992 sym = fscan->fx_addsy;
2993 if (sym == NULL
2994 || fscan->fx_subsy != NULL
2995 || fscan->fx_addnumber != 0
2996 || S_GET_SEGMENT (sym) != sec
252b5132
RH		 2997 || S_IS_EXTERNAL (sym))
2998 {
2999 as_warn_where (fix->fx_file, fix->fx_line,
3000 _(".uses target does not refer to a local symbol in the same section"));
3001 continue;
3002 }
3003
3004 /* Now we look through all the fixups of all the sections,
3005 counting the number of times we find a reference to sym. */
3006 info.sym = sym;
3007 info.count = 0;
8edc77b9 3008 bfd_map_over_sections (stdoutput, sh_count_relocs, &info);
252b5132
RH		 3009
3010 if (info.count < 1)
3011 abort ();
3012
3013 /* Generate a BFD_RELOC_SH_COUNT fixup at the location of sym.
3014 We have already adjusted the value of sym to include the
3015 fragment address, so we undo that adjustment here. */
3016 subseg_change (sec, 0);
7bcad3e5
NC		 3017 fix_new (fscan->fx_frag,
3018 S_GET_VALUE (sym) - fscan->fx_frag->fr_address,
252b5132
RH		 3019 4, &abs_symbol, info.count, 0, BFD_RELOC_SH_COUNT);
3020 }
3021}
3022
3023/* This function is called after the symbol table has been completed,
3024 but before the relocs or section contents have been written out.
3025 If we have seen any .uses pseudo-ops, they point to an instruction
3026 which loads a register with the address of a function. We look
3027 through the fixups to find where the function address is being
3028 loaded from. We then generate a COUNT reloc giving the number of
3029 times that function address is referred to. The linker uses this
3030 information when doing relaxing, to decide when it can eliminate
3031 the stored function address entirely. */
3032
3033void
8edc77b9 3034sh_frob_file (void)
252b5132
RH		 3035{
3036 if (! sh_relax)
3037 return;
3038
8edc77b9 3039 bfd_map_over_sections (stdoutput, sh_frob_section, NULL);
252b5132
RH		 3040}
3041
3042/* Called after relaxing. Set the correct sizes of the fragments, and
55cf6793 3043 create relocs so that md_apply_fix will fill in the correct values. */
252b5132
RH		 3044
3045void
8edc77b9 3046md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT seg, fragS *fragP)
252b5132
RH		 3047{
3048 int donerelax = 0;
3049
3050 switch (fragP->fr_subtype)
3051 {
3052 case C (COND_JUMP, COND8):
3053 case C (COND_JUMP_DELAY, COND8):
3054 subseg_change (seg, 0);
3055 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
3056 1, BFD_RELOC_SH_PCDISP8BY2);
3057 fragP->fr_fix += 2;
3058 fragP->fr_var = 0;
3059 break;
3060
3061 case C (UNCOND_JUMP, UNCOND12):
3062 subseg_change (seg, 0);
3063 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
3064 1, BFD_RELOC_SH_PCDISP12BY2);
3065 fragP->fr_fix += 2;
3066 fragP->fr_var = 0;
3067 break;
3068
3069 case C (UNCOND_JUMP, UNCOND32):
3070 case C (UNCOND_JUMP, UNDEF_WORD_DISP):
3071 if (fragP->fr_symbol == NULL)
99b222b4
HPN		 3072 as_bad_where (fragP->fr_file, fragP->fr_line,
3073 _("displacement overflows 12-bit field"));
252b5132 3074 else if (S_IS_DEFINED (fragP->fr_symbol))
99b222b4
HPN		 3075 as_bad_where (fragP->fr_file, fragP->fr_line,
3076 _("displacement to defined symbol %s overflows 12-bit field"),
3077 S_GET_NAME (fragP->fr_symbol));
252b5132 3078 else
99b222b4
HPN		 3079 as_bad_where (fragP->fr_file, fragP->fr_line,
3080 _("displacement to undefined symbol %s overflows 12-bit field"),
3081 S_GET_NAME (fragP->fr_symbol));
3082 /* Stabilize this frag, so we don't trip an assert. */
3083 fragP->fr_fix += fragP->fr_var;
3084 fragP->fr_var = 0;
252b5132
RH		 3085 break;
3086
3087 case C (COND_JUMP, COND12):
3088 case C (COND_JUMP_DELAY, COND12):
6b31947e 3089 /* A bcond won't fit, so turn it into a b!cond; bra disp; nop. */
252b5132
RH		 3090 /* I found that a relax failure for gcc.c-torture/execute/930628-1.c
3091 was due to gas incorrectly relaxing an out-of-range conditional
3092 branch with delay slot. It turned:
3093 bf.s L6 (slot mov.l r12,@(44,r0))
3094 into:
c4aa876b 3095
252b5132
RH		 30962c: 8f 01 a0 8b bf.s 32 <_main+32> (slot bra L6)
309730: 00 09 nop
309832: 10 cb mov.l r12,@(44,r0)
3099 Therefore, branches with delay slots have to be handled
3100 differently from ones without delay slots. */
3101 {
3102 unsigned char *buffer =
3103 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
3104 int highbyte = target_big_endian ? 0 : 1;
3105 int lowbyte = target_big_endian ? 1 : 0;
3106 int delay = fragP->fr_subtype == C (COND_JUMP_DELAY, COND12);
3107
3108 /* Toggle the true/false bit of the bcond. */
3109 buffer[highbyte] ^= 0x2;
3110
d3ecfc59 3111 /* If this is a delayed branch, we may not put the bra in the
252b5132
RH		 3112 slot. So we change it to a non-delayed branch, like that:
3113 b! cond slot_label; bra disp; slot_label: slot_insn
3114 ??? We should try if swapping the conditional branch and
3115 its delay-slot insn already makes the branch reach. */
3116
3117 /* Build a relocation to six / four bytes farther on. */
3118 subseg_change (seg, 0);
7be1c489 3119 fix_new (fragP, fragP->fr_fix, 2, section_symbol (seg),
252b5132
RH		 3120 fragP->fr_address + fragP->fr_fix + (delay ? 4 : 6),
3121 1, BFD_RELOC_SH_PCDISP8BY2);
3122
3123 /* Set up a jump instruction. */
3124 buffer[highbyte + 2] = 0xa0;
3125 buffer[lowbyte + 2] = 0;
3126 fix_new (fragP, fragP->fr_fix + 2, 2, fragP->fr_symbol,
3127 fragP->fr_offset, 1, BFD_RELOC_SH_PCDISP12BY2);
3128
3129 if (delay)
3130 {
3131 buffer[highbyte] &= ~0x4; /* Removes delay slot from branch. */
3132 fragP->fr_fix += 4;
3133 }
3134 else
3135 {
3136 /* Fill in a NOP instruction. */
3137 buffer[highbyte + 4] = 0x0;
3138 buffer[lowbyte + 4] = 0x9;
3139
3140 fragP->fr_fix += 6;
3141 }
3142 fragP->fr_var = 0;
3143 donerelax = 1;
3144 }
3145 break;
3146
3147 case C (COND_JUMP, COND32):
3148 case C (COND_JUMP_DELAY, COND32):
3149 case C (COND_JUMP, UNDEF_WORD_DISP):
3150 case C (COND_JUMP_DELAY, UNDEF_WORD_DISP):
3151 if (fragP->fr_symbol == NULL)
99b222b4
HPN		 3152 as_bad_where (fragP->fr_file, fragP->fr_line,
3153 _("displacement overflows 8-bit field"));
252b5132 3154 else if (S_IS_DEFINED (fragP->fr_symbol))
99b222b4
HPN		 3155 as_bad_where (fragP->fr_file, fragP->fr_line,
3156 _("displacement to defined symbol %s overflows 8-bit field"),
3157 S_GET_NAME (fragP->fr_symbol));
252b5132 3158 else
99b222b4
HPN		 3159 as_bad_where (fragP->fr_file, fragP->fr_line,
3160 _("displacement to undefined symbol %s overflows 8-bit field "),
3161 S_GET_NAME (fragP->fr_symbol));
3162 /* Stabilize this frag, so we don't trip an assert. */
3163 fragP->fr_fix += fragP->fr_var;
3164 fragP->fr_var = 0;
252b5132
RH		 3165 break;
3166
3167 default:
3168 abort ();
3169 }
3170
3171 if (donerelax && !sh_relax)
3172 as_warn_where (fragP->fr_file, fragP->fr_line,
3173 _("overflow in branch to %s; converted into longer instruction sequence"),
3174 (fragP->fr_symbol != NULL
3175 ? S_GET_NAME (fragP->fr_symbol)
3176 : ""));
3177}
3178
3179valueT
8edc77b9 3180md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size)
252b5132 3181{
252b5132
RH		 3182#ifdef OBJ_ELF
3183 return size;
3184#else /* ! OBJ_ELF */
3185 return ((size + (1 << bfd_get_section_alignment (stdoutput, seg)) - 1)
8d3842cd 3186 & -(1 << bfd_get_section_alignment (stdoutput, seg)));
252b5132 3187#endif /* ! OBJ_ELF */
252b5132
RH		 3188}
3189
3190/* This static variable is set by s_uacons to tell sh_cons_align that
67c1ffbe 3191 the expression does not need to be aligned. */
252b5132
RH		 3192
3193static int sh_no_align_cons = 0;
3194
3195/* This handles the unaligned space allocation pseudo-ops, such as
3196 .uaword. .uaword is just like .word, but the value does not need
3197 to be aligned. */
3198
3199static void
8edc77b9 3200s_uacons (int bytes)
252b5132
RH		 3201{
3202 /* Tell sh_cons_align not to align this value. */
3203 sh_no_align_cons = 1;
3204 cons (bytes);
3205}
3206
3207/* If a .word, et. al., pseud-op is seen, warn if the value is not
3208 aligned correctly. Note that this can cause warnings to be issued
3209 when assembling initialized structured which were declared with the
3210 packed attribute. FIXME: Perhaps we should require an option to
3211 enable this warning? */
3212
3213void
8edc77b9 3214sh_cons_align (int nbytes)
252b5132
RH		 3215{
3216 int nalign;
252b5132
RH		 3217
3218 if (sh_no_align_cons)
3219 {
3220 /* This is an unaligned pseudo-op. */
3221 sh_no_align_cons = 0;
3222 return;
3223 }
3224
3225 nalign = 0;
3226 while ((nbytes & 1) == 0)
3227 {
3228 ++nalign;
3229 nbytes >>= 1;
3230 }
3231
3232 if (nalign == 0)
3233 return;
3234
3235 if (now_seg == absolute_section)
3236 {
3237 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3238 as_warn (_("misaligned data"));
3239 return;
3240 }
3241
87975d2a
AM		 3242 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
3243 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
252b5132
RH		 3244
3245 record_alignment (now_seg, nalign);
3246}
3247
3248/* When relaxing, we need to output a reloc for any .align directive
3249 that requests alignment to a four byte boundary or larger. This is
3250 also where we check for misaligned data. */
3251
3252void
8edc77b9 3253sh_handle_align (fragS *frag)
252b5132 3254{
0a9ef439
RH		 3255 int bytes = frag->fr_next->fr_address - frag->fr_address - frag->fr_fix;
3256
3257 if (frag->fr_type == rs_align_code)
3258 {
3259 static const unsigned char big_nop_pattern[] = { 0x00, 0x09 };
3260 static const unsigned char little_nop_pattern[] = { 0x09, 0x00 };
3261
3262 char *p = frag->fr_literal + frag->fr_fix;
3263
3264 if (bytes & 1)
3265 {
3266 *p++ = 0;
3267 bytes--;
3268 frag->fr_fix += 1;
3269 }
3270
3271 if (target_big_endian)
3272 {
3273 memcpy (p, big_nop_pattern, sizeof big_nop_pattern);
3274 frag->fr_var = sizeof big_nop_pattern;
3275 }
3276 else
3277 {
3278 memcpy (p, little_nop_pattern, sizeof little_nop_pattern);
3279 frag->fr_var = sizeof little_nop_pattern;
3280 }
3281 }
3282 else if (frag->fr_type == rs_align_test)
3283 {
3284 if (bytes != 0)
91382b56 3285 as_bad_where (frag->fr_file, frag->fr_line, _("misaligned data"));
0a9ef439
RH		 3286 }
3287
252b5132 3288 if (sh_relax
0a9ef439
RH		 3289 && (frag->fr_type == rs_align
3290 || frag->fr_type == rs_align_code)
252b5132
RH		 3291 && frag->fr_address + frag->fr_fix > 0
3292 && frag->fr_offset > 1
3293 && now_seg != bss_section)
3294 fix_new (frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset, 0,
3295 BFD_RELOC_SH_ALIGN);
252b5132
RH		 3296}
3297
28602ebf
KK		 3298/* See whether the relocation should be resolved locally. */
3299
b34976b6 3300static bfd_boolean
8edc77b9 3301sh_local_pcrel (fixS *fix)
28602ebf 3302{
b34976b6
AM		 3303 return (! sh_relax
3304 && (fix->fx_r_type == BFD_RELOC_SH_PCDISP8BY2
3305 || fix->fx_r_type == BFD_RELOC_SH_PCDISP12BY2
3306 || fix->fx_r_type == BFD_RELOC_SH_PCRELIMM8BY2
3307 || fix->fx_r_type == BFD_RELOC_SH_PCRELIMM8BY4
3308 || fix->fx_r_type == BFD_RELOC_8_PCREL
3309 || fix->fx_r_type == BFD_RELOC_SH_SWITCH16
3310 || fix->fx_r_type == BFD_RELOC_SH_SWITCH32));
28602ebf
KK		 3311}
3312
252b5132
RH		 3313/* See whether we need to force a relocation into the output file.
3314 This is used to force out switch and PC relative relocations when
3315 relaxing. */
3316
3317int
8edc77b9 3318sh_force_relocation (fixS *fix)
252b5132 3319{
8ba4dac0
DJ		 3320 /* These relocations can't make it into a DSO, so no use forcing
3321 them for global symbols. */
28602ebf 3322 if (sh_local_pcrel (fix))
8ba4dac0
DJ		 3323 return 0;
3324
9efb3b7b 3325 /* Make sure some relocations get emitted. */
ae6063d4 3326 if (fix->fx_r_type == BFD_RELOC_SH_LOOP_START
a161fe53 3327 || fix->fx_r_type == BFD_RELOC_SH_LOOP_END
9efb3b7b
KK		 3328 || fix->fx_r_type == BFD_RELOC_SH_TLS_GD_32
3329 || fix->fx_r_type == BFD_RELOC_SH_TLS_LD_32
3330 || fix->fx_r_type == BFD_RELOC_SH_TLS_IE_32
3331 || fix->fx_r_type == BFD_RELOC_SH_TLS_LDO_32
3332 || fix->fx_r_type == BFD_RELOC_SH_TLS_LE_32
ae6063d4 3333 || generic_force_reloc (fix))
252b5132
RH		 3334 return 1;
3335
3336 if (! sh_relax)
3337 return 0;
3338
3339 return (fix->fx_pcrel
3340 || SWITCH_TABLE (fix)
3341 || fix->fx_r_type == BFD_RELOC_SH_COUNT
3342 || fix->fx_r_type == BFD_RELOC_SH_ALIGN
3343 || fix->fx_r_type == BFD_RELOC_SH_CODE
3344 || fix->fx_r_type == BFD_RELOC_SH_DATA
3345 || fix->fx_r_type == BFD_RELOC_SH_LABEL);
3346}
3347
3348#ifdef OBJ_ELF
b34976b6 3349bfd_boolean
8edc77b9 3350sh_fix_adjustable (fixS *fixP)
252b5132 3351{
a161fe53
AM		 3352 if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
3353 || fixP->fx_r_type == BFD_RELOC_32_GOT_PCREL
8e45593f 3354 || fixP->fx_r_type == BFD_RELOC_SH_GOT20
a161fe53 3355 || fixP->fx_r_type == BFD_RELOC_SH_GOTPC
8e45593f
NC		 3356 || fixP->fx_r_type == BFD_RELOC_SH_GOTFUNCDESC
3357 || fixP->fx_r_type == BFD_RELOC_SH_GOTFUNCDESC20
3358 || fixP->fx_r_type == BFD_RELOC_SH_GOTOFFFUNCDESC
3359 || fixP->fx_r_type == BFD_RELOC_SH_GOTOFFFUNCDESC20
3360 || fixP->fx_r_type == BFD_RELOC_SH_FUNCDESC
f55629b8 3361 || ((fixP->fx_r_type == BFD_RELOC_32) && dont_adjust_reloc_32)
a1cc9221
AO		 3362 || fixP->fx_r_type == BFD_RELOC_RVA)
3363 return 0;
3364
252b5132
RH		 3365 /* We need the symbol name for the VTABLE entries */
3366 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3367 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3368 return 0;
3369
3370 return 1;
3371}
d4845d57 3372
6b31947e 3373void
8edc77b9 3374sh_elf_final_processing (void)
d4845d57
JR		 3375{
3376 int val;
3377
3378 /* Set file-specific flags to indicate if this code needs
88da98f3 3379 a processor with the sh-dsp / sh2e ISA to execute. */
211dc24b 3380 val = sh_find_elf_flags (valid_arch);
d4845d57
JR		 3381
3382 elf_elfheader (stdoutput)->e_flags &= ~EF_SH_MACH_MASK;
3383 elf_elfheader (stdoutput)->e_flags |= val;
8e45593f
NC		 3384
3385 if (sh_fdpic)
3386 elf_elfheader (stdoutput)->e_flags |= EF_SH_FDPIC;
3387}
3388#endif
3389
3390#ifdef TE_UCLINUX
3391/* Return the target format for uClinux. */
3392
3393const char *
3394sh_uclinux_target_format (void)
3395{
3396 if (sh_fdpic)
3397 return (!target_big_endian ? "elf32-sh-fdpic" : "elf32-shbig-fdpic");
3398 else
3399 return (!target_big_endian ? "elf32-shl" : "elf32-sh");
d4845d57 3400}
252b5132
RH		 3401#endif
3402
55e6e397
RS		 3403/* Apply fixup FIXP to SIZE-byte field BUF given that VAL is its
3404 assembly-time value. If we're generating a reloc for FIXP,
3405 see whether the addend should be stored in-place or whether
3406 it should be in an ELF r_addend field. */
3407
3408static void
3409apply_full_field_fix (fixS *fixP, char *buf, bfd_vma val, int size)
3410{
3411 reloc_howto_type *howto;
3412
3413 if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
3414 {
3415 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
3416 if (howto && !howto->partial_inplace)
3417 {
3418 fixP->fx_addnumber = val;
3419 return;
3420 }
3421 }
3422 md_number_to_chars (buf, val, size);
3423}
3424
252b5132
RH		 3425/* Apply a fixup to the object file. */
3426
252b5132 3427void
55cf6793 3428md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132
RH		 3429{
3430 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3431 int lowbyte = target_big_endian ? 1 : 0;
3432 int highbyte = target_big_endian ? 0 : 1;
2ed5f585 3433 long val = (long) *valP;
252b5132
RH		 3434 long max, min;
3435 int shift;
3436
a1cc9221
AO		 3437 /* A difference between two symbols, the second of which is in the
3438 current section, is transformed in a PC-relative relocation to
3439 the other symbol. We have to adjust the relocation type here. */
3440 if (fixP->fx_pcrel)
3441 {
3442 switch (fixP->fx_r_type)
3443 {
3444 default:
3445 break;
3446
3447 case BFD_RELOC_32:
3448 fixP->fx_r_type = BFD_RELOC_32_PCREL;
3449 break;
3450
3451 /* Currently, we only support 32-bit PCREL relocations.
3452 We'd need a new reloc type to handle 16_PCREL, and
3453 8_PCREL is already taken for R_SH_SWITCH8, which
3454 apparently does something completely different than what
3455 we need. FIXME. */
3456 case BFD_RELOC_16:
3457 bfd_set_error (bfd_error_bad_value);
94f592af 3458 return;
81d4177b 3459
a1cc9221
AO		 3460 case BFD_RELOC_8:
3461 bfd_set_error (bfd_error_bad_value);
94f592af 3462 return;
a1cc9221
AO		 3463 }
3464 }
3465
6b31947e
NC		 3466 /* The function adjust_reloc_syms won't convert a reloc against a weak
3467 symbol into a reloc against a section, but bfd_install_relocation
3468 will screw up if the symbol is defined, so we have to adjust val here
1308f14c
HPN		 3469 to avoid the screw up later.
3470
3471 For ordinary relocs, this does not happen for ELF, since for ELF,
3472 bfd_install_relocation uses the "special function" field of the
3473 howto, and does not execute the code that needs to be undone, as long
3474 as the special function does not return bfd_reloc_continue.
3475 It can happen for GOT- and PLT-type relocs the way they are
3476 described in elf32-sh.c as they use bfd_elf_generic_reloc, but it
3477 doesn't matter here since those relocs don't use VAL; see below. */
3478 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
3479 && fixP->fx_addsy != NULL
252b5132
RH		 3480 && S_IS_WEAK (fixP->fx_addsy))
3481 val -= S_GET_VALUE (fixP->fx_addsy);
252b5132 3482
bdfaef52
JR		 3483 if (SWITCH_TABLE (fixP))
3484 val -= S_GET_VALUE (fixP->fx_subsy);
252b5132
RH		 3485
3486 max = min = 0;
3487 shift = 0;
3488 switch (fixP->fx_r_type)
3489 {
1d70c7fb
AO		 3490 case BFD_RELOC_SH_IMM3:
3491 max = 0x7;
3492 * buf = (* buf & 0xf8) | (val & 0x7);
3493 break;
3494 case BFD_RELOC_SH_IMM3U:
3495 max = 0x7;
3496 * buf = (* buf & 0x8f) | ((val & 0x7) << 4);
3497 break;
3498 case BFD_RELOC_SH_DISP12:
3499 max = 0xfff;
3500 buf[lowbyte] = val & 0xff;
3501 buf[highbyte] |= (val >> 8) & 0x0f;
3502 break;
3503 case BFD_RELOC_SH_DISP12BY2:
3504 max = 0xfff;
3505 shift = 1;
3506 buf[lowbyte] = (val >> 1) & 0xff;
3507 buf[highbyte] |= (val >> 9) & 0x0f;
3508 break;
3509 case BFD_RELOC_SH_DISP12BY4:
3510 max = 0xfff;
3511 shift = 2;
3512 buf[lowbyte] = (val >> 2) & 0xff;
3513 buf[highbyte] |= (val >> 10) & 0x0f;
3514 break;
3515 case BFD_RELOC_SH_DISP12BY8:
3516 max = 0xfff;
3517 shift = 3;
3518 buf[lowbyte] = (val >> 3) & 0xff;
3519 buf[highbyte] |= (val >> 11) & 0x0f;
3520 break;
3521 case BFD_RELOC_SH_DISP20:
3522 if (! target_big_endian)
3523 abort();
3524 max = 0x7ffff;
3525 min = -0x80000;
28013b5c 3526 buf[1] = (buf[1] & 0x0f) | ((val >> 12) & 0xf0);
1d70c7fb
AO		 3527 buf[2] = (val >> 8) & 0xff;
3528 buf[3] = val & 0xff;
3529 break;
3530 case BFD_RELOC_SH_DISP20BY8:
3531 if (!target_big_endian)
3532 abort();
3533 max = 0x7ffff;
3534 min = -0x80000;
3535 shift = 8;
28013b5c 3536 buf[1] = (buf[1] & 0x0f) | ((val >> 20) & 0xf0);
1d70c7fb
AO		 3537 buf[2] = (val >> 16) & 0xff;
3538 buf[3] = (val >> 8) & 0xff;
3539 break;
3540
252b5132
RH		 3541 case BFD_RELOC_SH_IMM4:
3542 max = 0xf;
3543 *buf = (*buf & 0xf0) | (val & 0xf);
3544 break;
3545
3546 case BFD_RELOC_SH_IMM4BY2:
3547 max = 0xf;
3548 shift = 1;
3549 *buf = (*buf & 0xf0) | ((val >> 1) & 0xf);
3550 break;
3551
3552 case BFD_RELOC_SH_IMM4BY4:
3553 max = 0xf;
3554 shift = 2;
3555 *buf = (*buf & 0xf0) | ((val >> 2) & 0xf);
3556 break;
3557
3558 case BFD_RELOC_SH_IMM8BY2:
3559 max = 0xff;
3560 shift = 1;
3561 *buf = val >> 1;
3562 break;
3563
3564 case BFD_RELOC_SH_IMM8BY4:
3565 max = 0xff;
3566 shift = 2;
3567 *buf = val >> 2;
3568 break;
3569
3570 case BFD_RELOC_8:
3571 case BFD_RELOC_SH_IMM8:
3572 /* Sometimes the 8 bit value is sign extended (e.g., add) and
3573 sometimes it is not (e.g., and). We permit any 8 bit value.
3574 Note that adding further restrictions may invalidate
3575 reasonable looking assembly code, such as ``and -0x1,r0''. */
3576 max = 0xff;
c4aa876b 3577 min = -0xff;
252b5132
RH		 3578 *buf++ = val;
3579 break;
3580
3581 case BFD_RELOC_SH_PCRELIMM8BY4:
52b5ca5b
AS		 3582 /* If we are dealing with a known destination ... */
3583 if ((fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
3584 && (fixP->fx_subsy == NULL || S_IS_DEFINED (fixP->fx_addsy)))
3585 {
3586 /* Don't silently move the destination due to misalignment.
3587 The absolute address is the fragment base plus the offset into
3588 the fragment plus the pc relative offset to the label. */
3589 if ((fixP->fx_frag->fr_address + fixP->fx_where + val) & 3)
3590 as_bad_where (fixP->fx_file, fixP->fx_line,
3591 _("offset to unaligned destination"));
3592
3593 /* The displacement cannot be zero or backward even if aligned.
3594 Allow -2 because val has already been adjusted somewhere. */
3595 if (val < -2)
3596 as_bad_where (fixP->fx_file, fixP->fx_line, _("negative offset"));
3597 }
3598
252b5132
RH		 3599 /* The lower two bits of the PC are cleared before the
3600 displacement is added in. We can assume that the destination
67c1ffbe 3601 is on a 4 byte boundary. If this instruction is also on a 4
252b5132
RH		 3602 byte boundary, then we want
3603 (target - here) / 4
3604 and target - here is a multiple of 4.
3605 Otherwise, we are on a 2 byte boundary, and we want
3606 (target - (here - 2)) / 4
3607 and target - here is not a multiple of 4. Computing
3608 (target - (here - 2)) / 4 == (target - here + 2) / 4
3609 works for both cases, since in the first case the addition of
3610 2 will be removed by the division. target - here is in the
3611 variable val. */
3612 val = (val + 2) / 4;
3613 if (val & ~0xff)
3614 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3615 buf[lowbyte] = val;
3616 break;
3617
3618 case BFD_RELOC_SH_PCRELIMM8BY2:
3619 val /= 2;
3620 if (val & ~0xff)
3621 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3622 buf[lowbyte] = val;
3623 break;
3624
3625 case BFD_RELOC_SH_PCDISP8BY2:
3626 val /= 2;
3627 if (val < -0x80 || val > 0x7f)
3628 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3629 buf[lowbyte] = val;
3630 break;
3631
3632 case BFD_RELOC_SH_PCDISP12BY2:
3633 val /= 2;
8637c045 3634 if (val < -0x800 || val > 0x7ff)
252b5132
RH		 3635 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3636 buf[lowbyte] = val & 0xff;
3637 buf[highbyte] |= (val >> 8) & 0xf;
3638 break;
3639
3640 case BFD_RELOC_32:
a1cc9221 3641 case BFD_RELOC_32_PCREL:
55e6e397 3642 apply_full_field_fix (fixP, buf, val, 4);
252b5132
RH		 3643 break;
3644
3645 case BFD_RELOC_16:
55e6e397 3646 apply_full_field_fix (fixP, buf, val, 2);
252b5132
RH		 3647 break;
3648
3649 case BFD_RELOC_SH_USES:
fefaa1aa 3650 /* Pass the value into sh_reloc(). */
252b5132
RH		 3651 fixP->fx_addnumber = val;
3652 break;
3653
3654 case BFD_RELOC_SH_COUNT:
3655 case BFD_RELOC_SH_ALIGN:
3656 case BFD_RELOC_SH_CODE:
3657 case BFD_RELOC_SH_DATA:
3658 case BFD_RELOC_SH_LABEL:
3659 /* Nothing to do here. */
3660 break;
3661
015551fc
JR		 3662 case BFD_RELOC_SH_LOOP_START:
3663 case BFD_RELOC_SH_LOOP_END:
3664
252b5132
RH		 3665 case BFD_RELOC_VTABLE_INHERIT:
3666 case BFD_RELOC_VTABLE_ENTRY:
3667 fixP->fx_done = 0;
3668 return;
3669
a1cc9221
AO		 3670#ifdef OBJ_ELF
3671 case BFD_RELOC_32_PLT_PCREL:
3672 /* Make the jump instruction point to the address of the operand. At
81d4177b 3673 runtime we merely add the offset to the actual PLT entry. */
94f592af 3674 * valP = 0xfffffffc;
0174e383 3675 val = fixP->fx_offset;
ac3f04d7
AO		 3676 if (fixP->fx_subsy)
3677 val -= S_GET_VALUE (fixP->fx_subsy);
55e6e397 3678 apply_full_field_fix (fixP, buf, val, 4);
a1cc9221
AO		 3679 break;
3680
3681 case BFD_RELOC_SH_GOTPC:
3682 /* This is tough to explain. We end up with this one if we have
3683 operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]".
3684 The goal here is to obtain the absolute address of the GOT,
3685 and it is strongly preferable from a performance point of
3686 view to avoid using a runtime relocation for this. There are
3687 cases where you have something like:
81d4177b 3688
a1cc9221 3689 .long _GLOBAL_OFFSET_TABLE_+[.-.L66]
81d4177b 3690
a1cc9221
AO		 3691 and here no correction would be required. Internally in the
3692 assembler we treat operands of this form as not being pcrel
3693 since the '.' is explicitly mentioned, and I wonder whether
3694 it would simplify matters to do it this way. Who knows. In
3695 earlier versions of the PIC patches, the pcrel_adjust field
3696 was used to store the correction, but since the expression is
3697 not pcrel, I felt it would be confusing to do it this way. */
94f592af 3698 * valP -= 1;
55e6e397 3699 apply_full_field_fix (fixP, buf, val, 4);
a1cc9221
AO		 3700 break;
3701
9efb3b7b
KK		 3702 case BFD_RELOC_SH_TLS_GD_32:
3703 case BFD_RELOC_SH_TLS_LD_32:
3704 case BFD_RELOC_SH_TLS_IE_32:
2bba4140
KK		 3705 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3706 /* Fallthrough */
3707 case BFD_RELOC_32_GOT_PCREL:
8e45593f 3708 case BFD_RELOC_SH_GOT20:
2bba4140 3709 case BFD_RELOC_SH_GOTPLT32:
8e45593f
NC		 3710 case BFD_RELOC_SH_GOTFUNCDESC:
3711 case BFD_RELOC_SH_GOTFUNCDESC20:
3712 case BFD_RELOC_SH_GOTOFFFUNCDESC:
3713 case BFD_RELOC_SH_GOTOFFFUNCDESC20:
3714 case BFD_RELOC_SH_FUNCDESC:
94f592af 3715 * valP = 0; /* Fully resolved at runtime. No addend. */
55e6e397 3716 apply_full_field_fix (fixP, buf, 0, 4);
a1cc9221
AO		 3717 break;
3718
9efb3b7b
KK		 3719 case BFD_RELOC_SH_TLS_LDO_32:
3720 case BFD_RELOC_SH_TLS_LE_32:
2bba4140
KK		 3721 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3722 /* Fallthrough */
3723 case BFD_RELOC_32_GOTOFF:
8e45593f 3724 case BFD_RELOC_SH_GOTOFF20:
55e6e397 3725 apply_full_field_fix (fixP, buf, val, 4);
a1cc9221
AO		 3726 break;
3727#endif
3728
252b5132
RH		 3729 default:
3730 abort ();
3731 }
3732
3733 if (shift != 0)
3734 {
3735 if ((val & ((1 << shift) - 1)) != 0)
3736 as_bad_where (fixP->fx_file, fixP->fx_line, _("misaligned offset"));
3737 if (val >= 0)
3738 val >>= shift;
3739 else
3740 val = ((val >> shift)
3741 | ((long) -1 & ~ ((long) -1 >> shift)));
3742 }
0c9b4fd7
KK		 3743
3744 /* Extend sign for 64-bit host. */
3745 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132
RH		 3746 if (max != 0 && (val < min || val > max))
3747 as_bad_where (fixP->fx_file, fixP->fx_line, _("offset out of range"));
01eaea5a 3748 else if (max != 0)
33eaf5de 3749 /* Stop the generic code from trying to overflow check the value as well.
01eaea5a
NC		 3750 It may not have the correct value anyway, as we do not store val back
3751 into *valP. */
3752 fixP->fx_no_overflow = 1;
252b5132 3753
94f592af
NC		 3754 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
3755 fixP->fx_done = 1;
252b5132
RH		 3756}
3757
3758/* Called just before address relaxation. Return the length
3759 by which a fragment must grow to reach it's destination. */
3760
3761int
8edc77b9 3762md_estimate_size_before_relax (fragS *fragP, segT segment_type)
252b5132 3763{
e66457fb
AM		 3764 int what;
3765
252b5132
RH		 3766 switch (fragP->fr_subtype)
3767 {
93c2a809
AM		 3768 default:
3769 abort ();
3770
252b5132 3771 case C (UNCOND_JUMP, UNDEF_DISP):
6b31947e 3772 /* Used to be a branch to somewhere which was unknown. */
252b5132
RH		 3773 if (!fragP->fr_symbol)
3774 {
3775 fragP->fr_subtype = C (UNCOND_JUMP, UNCOND12);
252b5132
RH		 3776 }
3777 else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
3778 {
3779 fragP->fr_subtype = C (UNCOND_JUMP, UNCOND12);
252b5132
RH		 3780 }
3781 else
3782 {
3783 fragP->fr_subtype = C (UNCOND_JUMP, UNDEF_WORD_DISP);
252b5132
RH		 3784 }
3785 break;
3786
252b5132
RH		 3787 case C (COND_JUMP, UNDEF_DISP):
3788 case C (COND_JUMP_DELAY, UNDEF_DISP):
e66457fb 3789 what = GET_WHAT (fragP->fr_subtype);
6b31947e 3790 /* Used to be a branch to somewhere which was unknown. */
252b5132
RH		 3791 if (fragP->fr_symbol
3792 && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
3793 {
252b5132 3794 /* Got a symbol and it's defined in this segment, become byte
6b31947e 3795 sized - maybe it will fix up. */
252b5132 3796 fragP->fr_subtype = C (what, COND8);
252b5132
RH		 3797 }
3798 else if (fragP->fr_symbol)
3799 {
33eaf5de 3800 /* It's got a segment, but it's not ours, so it will always be long. */
252b5132 3801 fragP->fr_subtype = C (what, UNDEF_WORD_DISP);
252b5132
RH		 3802 }
3803 else
3804 {
6b31947e 3805 /* We know the abs value. */
252b5132 3806 fragP->fr_subtype = C (what, COND8);
252b5132 3807 }
93c2a809 3808 break;
252b5132 3809
93c2a809 3810 case C (UNCOND_JUMP, UNCOND12):
e66457fb 3811 case C (UNCOND_JUMP, UNCOND32):
93c2a809
AM		 3812 case C (UNCOND_JUMP, UNDEF_WORD_DISP):
3813 case C (COND_JUMP, COND8):
e66457fb
AM		 3814 case C (COND_JUMP, COND12):
3815 case C (COND_JUMP, COND32):
93c2a809
AM		 3816 case C (COND_JUMP, UNDEF_WORD_DISP):
3817 case C (COND_JUMP_DELAY, COND8):
e66457fb
AM		 3818 case C (COND_JUMP_DELAY, COND12):
3819 case C (COND_JUMP_DELAY, COND32):
93c2a809
AM		 3820 case C (COND_JUMP_DELAY, UNDEF_WORD_DISP):
3821 /* When relaxing a section for the second time, we don't need to
e66457fb 3822 do anything besides return the current size. */
252b5132
RH		 3823 break;
3824 }
e66457fb
AM		 3825
3826 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 3827 return fragP->fr_var;
3828}
3829
6b31947e 3830/* Put number into target byte order. */
252b5132
RH		 3831
3832void
8edc77b9 3833md_number_to_chars (char *ptr, valueT use, int nbytes)
252b5132
RH		 3834{
3835 if (! target_big_endian)
3836 number_to_chars_littleendian (ptr, use, nbytes);
3837 else
3838 number_to_chars_bigendian (ptr, use, nbytes);
3839}
3840
7be1c489 3841/* This version is used in obj-coff.c eg. for the sh-hms target. */
cce5a618
NC		 3842
3843long
8edc77b9 3844md_pcrel_from (fixS *fixP)
cce5a618
NC		 3845{
3846 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address + 2;
3847}
3848
252b5132 3849long
8edc77b9 3850md_pcrel_from_section (fixS *fixP, segT sec)
252b5132 3851{
28602ebf
KK		 3852 if (! sh_local_pcrel (fixP)
3853 && fixP->fx_addsy != (symbolS *) NULL
ae6063d4 3854 && (generic_force_reloc (fixP)
ef17112f
HPN		 3855 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
3856 {
3857 /* The symbol is undefined (or is defined but not in this section,
3858 or we're not sure about it being the final definition). Let the
3859 linker figure it out. We need to adjust the subtraction of a
3860 symbol to the position of the relocated data, though. */
3861 return fixP->fx_subsy ? fixP->fx_where + fixP->fx_frag->fr_address : 0;
3862 }
3863
cce5a618 3864 return md_pcrel_from (fixP);
252b5132
RH		 3865}
3866
252b5132
RH		 3867/* Create a reloc. */
3868
3869arelent *
8edc77b9 3870tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 3871{
3872 arelent *rel;
3873 bfd_reloc_code_real_type r_type;
3874
add39d23
TS		 3875 rel = XNEW (arelent);
3876 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 3877 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3878 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3879
3880 r_type = fixp->fx_r_type;
3881
3882 if (SWITCH_TABLE (fixp))
3883 {
bdfaef52 3884 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
b131d1fc 3885 rel->addend = rel->address - S_GET_VALUE(fixp->fx_subsy);
252b5132
RH		 3886 if (r_type == BFD_RELOC_16)
3887 r_type = BFD_RELOC_SH_SWITCH16;
3888 else if (r_type == BFD_RELOC_8)
3889 r_type = BFD_RELOC_8_PCREL;
3890 else if (r_type == BFD_RELOC_32)
3891 r_type = BFD_RELOC_SH_SWITCH32;
3892 else
3893 abort ();
3894 }
3895 else if (r_type == BFD_RELOC_SH_USES)
3896 rel->addend = fixp->fx_addnumber;
3897 else if (r_type == BFD_RELOC_SH_COUNT)
3898 rel->addend = fixp->fx_offset;
3899 else if (r_type == BFD_RELOC_SH_ALIGN)
3900 rel->addend = fixp->fx_offset;
3901 else if (r_type == BFD_RELOC_VTABLE_INHERIT
3902 || r_type == BFD_RELOC_VTABLE_ENTRY)
3903 rel->addend = fixp->fx_offset;
015551fc
JR		 3904 else if (r_type == BFD_RELOC_SH_LOOP_START
3905 || r_type == BFD_RELOC_SH_LOOP_END)
3906 rel->addend = fixp->fx_offset;
3907 else if (r_type == BFD_RELOC_SH_LABEL && fixp->fx_pcrel)
3908 {
3909 rel->addend = 0;
3910 rel->address = rel->addend = fixp->fx_offset;
3911 }
252b5132 3912 else
55e6e397 3913 rel->addend = fixp->fx_addnumber;
252b5132
RH		 3914
3915 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
78878175 3916
a161fe53 3917 if (rel->howto == NULL)
252b5132
RH		 3918 {
3919 as_bad_where (fixp->fx_file, fixp->fx_line,
3920 _("Cannot represent relocation type %s"),
3921 bfd_get_reloc_code_name (r_type));
3922 /* Set howto to a garbage value so that we can keep going. */
3923 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 3924 gas_assert (rel->howto != NULL);
252b5132 3925 }
78878175
NC		 3926#ifdef OBJ_ELF
3927 else if (rel->howto->type == R_SH_IND12W)
3928 rel->addend += fixp->fx_offset - 4;
3929#endif
252b5132
RH		 3930
3931 return rel;
3932}
3933
538cd60f
AO		 3934#ifdef OBJ_ELF
3935inline static char *
e0471c16 3936sh_end_of_match (char *cont, const char *what)
538cd60f
AO		 3937{
3938 int len = strlen (what);
3939
3940 if (strncasecmp (cont, what, strlen (what)) == 0
3941 && ! is_part_of_name (cont[len]))
3942 return cont + len;
3943
3944 return NULL;
5d6255fe 3945}
538cd60f
AO		 3946
3947int
9497f5ac
NC		 3948sh_parse_name (char const *name,
3949 expressionS *exprP,
3950 enum expr_mode mode,
3951 char *nextcharP)
538cd60f
AO		 3952{
3953 char *next = input_line_pointer;
3954 char *next_end;
3955 int reloc_type;
3956 segT segment;
3957
3958 exprP->X_op_symbol = NULL;
3959
3960 if (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
3961 {
3962 if (! GOT_symbol)
3963 GOT_symbol = symbol_find_or_make (name);
3964
3965 exprP->X_add_symbol = GOT_symbol;
3966 no_suffix:
3967 /* If we have an absolute symbol or a reg, then we know its
37dedf66 3968 value now. */
538cd60f 3969 segment = S_GET_SEGMENT (exprP->X_add_symbol);
9497f5ac 3970 if (mode != expr_defer && segment == absolute_section)
538cd60f
AO		 3971 {
3972 exprP->X_op = O_constant;
3973 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
3974 exprP->X_add_symbol = NULL;
3975 }
9497f5ac 3976 else if (mode != expr_defer && segment == reg_section)
538cd60f
AO		 3977 {
3978 exprP->X_op = O_register;
3979 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
3980 exprP->X_add_symbol = NULL;
3981 }
3982 else
3983 {
3984 exprP->X_op = O_symbol;
3985 exprP->X_add_number = 0;
3986 }
3987
3988 return 1;
3989 }
3990
3991 exprP->X_add_symbol = symbol_find_or_make (name);
5d6255fe 3992
538cd60f
AO		 3993 if (*nextcharP != '@')
3994 goto no_suffix;
3995 else if ((next_end = sh_end_of_match (next + 1, "GOTOFF")))
3996 reloc_type = BFD_RELOC_32_GOTOFF;
324bfcf3
AO		 3997 else if ((next_end = sh_end_of_match (next + 1, "GOTPLT")))
3998 reloc_type = BFD_RELOC_SH_GOTPLT32;
538cd60f
AO		 3999 else if ((next_end = sh_end_of_match (next + 1, "GOT")))
4000 reloc_type = BFD_RELOC_32_GOT_PCREL;
4001 else if ((next_end = sh_end_of_match (next + 1, "PLT")))
4002 reloc_type = BFD_RELOC_32_PLT_PCREL;
9efb3b7b
KK		 4003 else if ((next_end = sh_end_of_match (next + 1, "TLSGD")))
4004 reloc_type = BFD_RELOC_SH_TLS_GD_32;
4005 else if ((next_end = sh_end_of_match (next + 1, "TLSLDM")))
4006 reloc_type = BFD_RELOC_SH_TLS_LD_32;
4007 else if ((next_end = sh_end_of_match (next + 1, "GOTTPOFF")))
4008 reloc_type = BFD_RELOC_SH_TLS_IE_32;
4009 else if ((next_end = sh_end_of_match (next + 1, "TPOFF")))
4010 reloc_type = BFD_RELOC_SH_TLS_LE_32;
4011 else if ((next_end = sh_end_of_match (next + 1, "DTPOFF")))
4012 reloc_type = BFD_RELOC_SH_TLS_LDO_32;
8e45593f
NC		 4013 else if ((next_end = sh_end_of_match (next + 1, "PCREL")))
4014 reloc_type = BFD_RELOC_32_PCREL;
4015 else if ((next_end = sh_end_of_match (next + 1, "GOTFUNCDESC")))
4016 reloc_type = BFD_RELOC_SH_GOTFUNCDESC;
4017 else if ((next_end = sh_end_of_match (next + 1, "GOTOFFFUNCDESC")))
4018 reloc_type = BFD_RELOC_SH_GOTOFFFUNCDESC;
4019 else if ((next_end = sh_end_of_match (next + 1, "FUNCDESC")))
4020 reloc_type = BFD_RELOC_SH_FUNCDESC;
538cd60f
AO		 4021 else
4022 goto no_suffix;
4023
4024 *input_line_pointer = *nextcharP;
4025 input_line_pointer = next_end;
4026 *nextcharP = *input_line_pointer;
4027 *input_line_pointer = '\0';
4028
4029 exprP->X_op = O_PIC_reloc;
4030 exprP->X_add_number = 0;
4031 exprP->X_md = reloc_type;
4032
4033 return 1;
4034}
2ce4cc60
KK		 4035
4036void
4037sh_cfi_frame_initial_instructions (void)
4038{
4039 cfi_add_CFA_def_cfa (15, 0);
4040}
4041
4042int
1df69f4f 4043sh_regname_to_dw2regnum (char *regname)
2ce4cc60
KK		 4044{
4045 unsigned int regnum = -1;
4046 unsigned int i;
4047 const char *p;
4048 char *q;
e0471c16 4049 static struct { const char *name; int dw2regnum; } regnames[] =
2ce4cc60
KK		 4050 {
4051 { "pr", 17 }, { "t", 18 }, { "gbr", 19 }, { "mach", 20 },
4052 { "macl", 21 }, { "fpul", 23 }
4053 };
4054
4055 for (i = 0; i < ARRAY_SIZE (regnames); ++i)
4056 if (strcmp (regnames[i].name, regname) == 0)
4057 return regnames[i].dw2regnum;
4058
4059 if (regname[0] == 'r')
4060 {
4061 p = regname + 1;
4062 regnum = strtoul (p, &q, 10);
4063 if (p == q || *q || regnum >= 16)
4064 return -1;
4065 }
4066 else if (regname[0] == 'f' && regname[1] == 'r')
4067 {
4068 p = regname + 2;
4069 regnum = strtoul (p, &q, 10);
4070 if (p == q || *q || regnum >= 16)
4071 return -1;
4072 regnum += 25;
4073 }
4074 else if (regname[0] == 'x' && regname[1] == 'd')
4075 {
4076 p = regname + 2;
4077 regnum = strtoul (p, &q, 10);
4078 if (p == q || *q || regnum >= 8)
4079 return -1;
4080 regnum += 87;
4081 }
4082 return regnum;
4083}
f17c130b 4084#endif /* OBJ_ELF */
GDB Binutils - Deliverables
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