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PR 1659
[deliverable/binutils-gdb.git] / gas / config / tc-sh.c
CommitLineData
ef230218 1/* tc-sh.c -- Assemble code for the Renesas / SuperH SH
4aa3e325 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
e38bc3b5 3 2003, 2004, 2005 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
252b5132 21
6b31947e 22/* Written By Steve Chamberlain <sac@cygnus.com> */
252b5132
RH		 23
24#include <stdio.h>
25#include "as.h"
26#include "bfd.h"
27#include "subsegs.h"
28#define DEFINE_TABLE
29#include "opcodes/sh-opc.h"
3882b010 30#include "safe-ctype.h"
43841e91 31#include "struc-symbol.h"
d4845d57
JR		 32
33#ifdef OBJ_ELF
34#include "elf/sh.h"
35#endif
36
0d10e182 37#include "dwarf2dbg.h"
2ce4cc60 38#include "dw2gencfi.h"
0d10e182 39
e08ae979
HPN		 40typedef struct
41 {
42 sh_arg_type type;
43 int reg;
44 expressionS immediate;
45 }
46sh_operand_info;
47
252b5132
RH		 48const char comment_chars[] = "!";
49const char line_separator_chars[] = ";";
50const char line_comment_chars[] = "!#";
51
8edc77b9
KK		 52static void s_uses (int);
53static void s_uacons (int);
252b5132 54
a1cc9221 55#ifdef OBJ_ELF
8edc77b9 56static void sh_elf_cons (int);
538cd60f 57
a1cc9221
AO		 58symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
59#endif
60
05982cac 61static void
8edc77b9 62big (int ignore ATTRIBUTE_UNUSED)
05982cac
HPN		 63{
64 if (! target_big_endian)
65 as_bad (_("directive .big encountered when option -big required"));
66
67 /* Stop further messages. */
68 target_big_endian = 1;
69}
252b5132
RH		 70
71static void
8edc77b9 72little (int ignore ATTRIBUTE_UNUSED)
252b5132 73{
05982cac
HPN		 74 if (target_big_endian)
75 as_bad (_("directive .little encountered when option -little required"));
76
77 /* Stop further messages. */
252b5132
RH		 78 target_big_endian = 0;
79}
80
d4845d57
JR		 81/* This table describes all the machine specific pseudo-ops the assembler
82 has to support. The fields are:
83 pseudo-op name without dot
84 function to call to execute this pseudo-op
6b31947e 85 Integer arg to pass to the function. */
d4845d57 86
252b5132
RH		 87const pseudo_typeS md_pseudo_table[] =
88{
a1cc9221
AO		 89#ifdef OBJ_ELF
90 {"long", sh_elf_cons, 4},
91 {"int", sh_elf_cons, 4},
92 {"word", sh_elf_cons, 2},
93 {"short", sh_elf_cons, 2},
94#else
252b5132
RH		 95 {"int", cons, 4},
96 {"word", cons, 2},
a1cc9221 97#endif /* OBJ_ELF */
05982cac 98 {"big", big, 0},
252b5132
RH		 99 {"form", listing_psize, 0},
100 {"little", little, 0},
101 {"heading", listing_title, 0},
102 {"import", s_ignore, 0},
103 {"page", listing_eject, 0},
104 {"program", s_ignore, 0},
105 {"uses", s_uses, 0},
106 {"uaword", s_uacons, 2},
107 {"ualong", s_uacons, 4},
de68de20
AO		 108 {"uaquad", s_uacons, 8},
109 {"2byte", s_uacons, 2},
110 {"4byte", s_uacons, 4},
111 {"8byte", s_uacons, 8},
324bfcf3
AO		 112#ifdef HAVE_SH64
113 {"mode", s_sh64_mode, 0 },
114
115 /* Have the old name too. */
116 {"isa", s_sh64_mode, 0 },
117
118 /* Assert that the right ABI is used. */
119 {"abi", s_sh64_abi, 0 },
120
121 { "vtable_inherit", sh64_vtable_inherit, 0 },
122 { "vtable_entry", sh64_vtable_entry, 0 },
123#endif /* HAVE_SH64 */
252b5132
RH		 124 {0, 0, 0}
125};
126
252b5132
RH		 127int sh_relax; /* set if -relax seen */
128
129/* Whether -small was seen. */
130
131int sh_small;
132
f55629b8
KK		 133/* Flag to generate relocations against symbol values for local symbols. */
134
135static int dont_adjust_reloc_32;
136
bdfaef52 137/* preset architecture set, if given; zero otherwise. */
d4845d57 138
f6f9408f 139static unsigned int preset_target_arch;
d4845d57
JR		 140
141/* The bit mask of architectures that could
67c1ffbe 142 accommodate the insns seen so far. */
f6f9408f 143static unsigned int valid_arch;
d4845d57 144
252b5132
RH		 145const char EXP_CHARS[] = "eE";
146
6b31947e 147/* Chars that mean this number is a floating point constant. */
252b5132
RH		 148/* As in 0f12.456 */
149/* or 0d1.2345e12 */
150const char FLT_CHARS[] = "rRsSfFdDxXpP";
151
152#define C(a,b) ENCODE_RELAX(a,b)
153
252b5132
RH		 154#define ENCODE_RELAX(what,length) (((what) << 4) + (length))
155#define GET_WHAT(x) ((x>>4))
156
67c1ffbe 157/* These are the three types of relaxable instruction. */
324bfcf3
AO		 158/* These are the types of relaxable instructions; except for END which is
159 a marker. */
252b5132
RH		 160#define COND_JUMP 1
161#define COND_JUMP_DELAY 2
162#define UNCOND_JUMP 3
324bfcf3
AO		 163
164#ifdef HAVE_SH64
165
166/* A 16-bit (times four) pc-relative operand, at most expanded to 32 bits. */
167#define SH64PCREL16_32 4
168/* A 16-bit (times four) pc-relative operand, at most expanded to 64 bits. */
169#define SH64PCREL16_64 5
170
171/* Variants of the above for adjusting the insn to PTA or PTB according to
172 the label. */
173#define SH64PCREL16PT_32 6
174#define SH64PCREL16PT_64 7
175
176/* A MOVI expansion, expanding to at most 32 or 64 bits. */
177#define MOVI_IMM_32 8
178#define MOVI_IMM_32_PCREL 9
179#define MOVI_IMM_64 10
180#define MOVI_IMM_64_PCREL 11
181#define END 12
182
183#else /* HAVE_SH64 */
184
252b5132
RH		 185#define END 4
186
324bfcf3
AO		 187#endif /* HAVE_SH64 */
188
252b5132
RH		 189#define UNDEF_DISP 0
190#define COND8 1
191#define COND12 2
192#define COND32 3
252b5132
RH		 193#define UNDEF_WORD_DISP 4
194
195#define UNCOND12 1
196#define UNCOND32 2
197
324bfcf3
AO		 198#ifdef HAVE_SH64
199#define UNDEF_SH64PCREL 0
200#define SH64PCREL16 1
201#define SH64PCREL32 2
202#define SH64PCREL48 3
203#define SH64PCREL64 4
204#define SH64PCRELPLT 5
205
206#define UNDEF_MOVI 0
207#define MOVI_16 1
208#define MOVI_32 2
209#define MOVI_48 3
210#define MOVI_64 4
211#define MOVI_PLT 5
212#define MOVI_GOTOFF 6
213#define MOVI_GOTPC 7
214#endif /* HAVE_SH64 */
215
252b5132
RH		 216/* Branch displacements are from the address of the branch plus
217 four, thus all minimum and maximum values have 4 added to them. */
218#define COND8_F 258
219#define COND8_M -252
220#define COND8_LENGTH 2
221
222/* There is one extra instruction before the branch, so we must add
223 two more bytes to account for it. */
224#define COND12_F 4100
225#define COND12_M -4090
226#define COND12_LENGTH 6
227
228#define COND12_DELAY_LENGTH 4
229
230/* ??? The minimum and maximum values are wrong, but this does not matter
231 since this relocation type is not supported yet. */
232#define COND32_F (1<<30)
233#define COND32_M -(1<<30)
234#define COND32_LENGTH 14
235
236#define UNCOND12_F 4098
237#define UNCOND12_M -4092
238#define UNCOND12_LENGTH 2
239
240/* ??? The minimum and maximum values are wrong, but this does not matter
241 since this relocation type is not supported yet. */
242#define UNCOND32_F (1<<30)
243#define UNCOND32_M -(1<<30)
244#define UNCOND32_LENGTH 14
245
324bfcf3
AO		 246#ifdef HAVE_SH64
247/* The trivial expansion of a SH64PCREL16 relaxation is just a "PT label,
248 TRd" as is the current insn, so no extra length. Note that the "reach"
249 is calculated from the address *after* that insn, but the offset in the
250 insn is calculated from the beginning of the insn. We also need to
251 take into account the implicit 1 coded as the "A" in PTA when counting
252 forward. If PTB reaches an odd address, we trap that as an error
253 elsewhere, so we don't have to have different relaxation entries. We
254 don't add a one to the negative range, since PTB would then have the
255 farthest backward-reaching value skipped, not generated at relaxation. */
256#define SH64PCREL16_F (32767 * 4 - 4 + 1)
257#define SH64PCREL16_M (-32768 * 4 - 4)
258#define SH64PCREL16_LENGTH 0
259
260/* The next step is to change that PT insn into
261 MOVI ((label - datalabel Ln) >> 16) & 65535, R25
262 SHORI (label - datalabel Ln) & 65535, R25
263 Ln:
264 PTREL R25,TRd
265 which means two extra insns, 8 extra bytes. This is the limit for the
266 32-bit ABI.
267
268 The expressions look a bit bad since we have to adjust this to avoid overflow on a
269 32-bit host. */
270#define SH64PCREL32_F ((((long) 1 << 30) - 1) * 2 + 1 - 4)
271#define SH64PCREL32_LENGTH (2 * 4)
272
273/* Similarly, we just change the MOVI and add a SHORI for the 48-bit
274 expansion. */
275#if BFD_HOST_64BIT_LONG
276/* The "reach" type is long, so we can only do this for a 64-bit-long
277 host. */
278#define SH64PCREL32_M (((long) -1 << 30) * 2 - 4)
279#define SH64PCREL48_F ((((long) 1 << 47) - 1) - 4)
280#define SH64PCREL48_M (((long) -1 << 47) - 4)
281#define SH64PCREL48_LENGTH (3 * 4)
282#else
283/* If the host does not have 64-bit longs, just make this state identical
284 in reach to the 32-bit state. Note that we have a slightly incorrect
285 reach, but the correct one above will overflow a 32-bit number. */
286#define SH64PCREL32_M (((long) -1 << 30) * 2)
287#define SH64PCREL48_F SH64PCREL32_F
288#define SH64PCREL48_M SH64PCREL32_M
289#define SH64PCREL48_LENGTH (3 * 4)
290#endif /* BFD_HOST_64BIT_LONG */
291
292/* And similarly for the 64-bit expansion; a MOVI + SHORI + SHORI + SHORI
293 + PTREL sequence. */
294#define SH64PCREL64_LENGTH (4 * 4)
295
296/* For MOVI, we make the MOVI + SHORI... expansion you can see in the
297 SH64PCREL expansions. The PCREL one is similar, but the other has no
298 pc-relative reach; it must be fully expanded in
299 shmedia_md_estimate_size_before_relax. */
300#define MOVI_16_LENGTH 0
301#define MOVI_16_F (32767 - 4)
302#define MOVI_16_M (-32768 - 4)
303#define MOVI_32_LENGTH 4
304#define MOVI_32_F ((((long) 1 << 30) - 1) * 2 + 1 - 4)
305#define MOVI_48_LENGTH 8
306
307#if BFD_HOST_64BIT_LONG
308/* The "reach" type is long, so we can only do this for a 64-bit-long
309 host. */
310#define MOVI_32_M (((long) -1 << 30) * 2 - 4)
311#define MOVI_48_F ((((long) 1 << 47) - 1) - 4)
312#define MOVI_48_M (((long) -1 << 47) - 4)
313#else
314/* If the host does not have 64-bit longs, just make this state identical
315 in reach to the 32-bit state. Note that we have a slightly incorrect
316 reach, but the correct one above will overflow a 32-bit number. */
317#define MOVI_32_M (((long) -1 << 30) * 2)
318#define MOVI_48_F MOVI_32_F
319#define MOVI_48_M MOVI_32_M
320#endif /* BFD_HOST_64BIT_LONG */
321
322#define MOVI_64_LENGTH 12
323#endif /* HAVE_SH64 */
324
43841e91
NC		 325#define EMPTY { 0, 0, 0, 0 }
326
252b5132 327const relax_typeS md_relax_table[C (END, 0)] = {
43841e91
NC		 328 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
329 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 330
43841e91 331 EMPTY,
252b5132
RH		 332 /* C (COND_JUMP, COND8) */
333 { COND8_F, COND8_M, COND8_LENGTH, C (COND_JUMP, COND12) },
334 /* C (COND_JUMP, COND12) */
335 { COND12_F, COND12_M, COND12_LENGTH, C (COND_JUMP, COND32), },
336 /* C (COND_JUMP, COND32) */
337 { COND32_F, COND32_M, COND32_LENGTH, 0, },
e66457fb
AM		 338 /* C (COND_JUMP, UNDEF_WORD_DISP) */
339 { 0, 0, COND32_LENGTH, 0, },
340 EMPTY, EMPTY, EMPTY,
43841e91 341 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 342
43841e91 343 EMPTY,
252b5132
RH		 344 /* C (COND_JUMP_DELAY, COND8) */
345 { COND8_F, COND8_M, COND8_LENGTH, C (COND_JUMP_DELAY, COND12) },
346 /* C (COND_JUMP_DELAY, COND12) */
347 { COND12_F, COND12_M, COND12_DELAY_LENGTH, C (COND_JUMP_DELAY, COND32), },
348 /* C (COND_JUMP_DELAY, COND32) */
349 { COND32_F, COND32_M, COND32_LENGTH, 0, },
e66457fb
AM		 350 /* C (COND_JUMP_DELAY, UNDEF_WORD_DISP) */
351 { 0, 0, COND32_LENGTH, 0, },
352 EMPTY, EMPTY, EMPTY,
43841e91 353 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 354
43841e91 355 EMPTY,
252b5132
RH		 356 /* C (UNCOND_JUMP, UNCOND12) */
357 { UNCOND12_F, UNCOND12_M, UNCOND12_LENGTH, C (UNCOND_JUMP, UNCOND32), },
358 /* C (UNCOND_JUMP, UNCOND32) */
359 { UNCOND32_F, UNCOND32_M, UNCOND32_LENGTH, 0, },
e66457fb
AM		 360 EMPTY,
361 /* C (UNCOND_JUMP, UNDEF_WORD_DISP) */
362 { 0, 0, UNCOND32_LENGTH, 0, },
363 EMPTY, EMPTY, EMPTY,
43841e91 364 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
324bfcf3
AO		 365
366#ifdef HAVE_SH64
367 /* C (SH64PCREL16_32, SH64PCREL16) */
368 EMPTY,
369 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16_32, SH64PCREL32) },
370 /* C (SH64PCREL16_32, SH64PCREL32) */
371 { 0, 0, SH64PCREL32_LENGTH, 0 },
372 EMPTY, EMPTY,
373 /* C (SH64PCREL16_32, SH64PCRELPLT) */
374 { 0, 0, SH64PCREL32_LENGTH, 0 },
375 EMPTY, EMPTY,
376 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
377
378 /* C (SH64PCREL16_64, SH64PCREL16) */
379 EMPTY,
380 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16_64, SH64PCREL32) },
381 /* C (SH64PCREL16_64, SH64PCREL32) */
382 { SH64PCREL32_F, SH64PCREL32_M, SH64PCREL32_LENGTH, C (SH64PCREL16_64, SH64PCREL48) },
383 /* C (SH64PCREL16_64, SH64PCREL48) */
384 { SH64PCREL48_F, SH64PCREL48_M, SH64PCREL48_LENGTH, C (SH64PCREL16_64, SH64PCREL64) },
385 /* C (SH64PCREL16_64, SH64PCREL64) */
386 { 0, 0, SH64PCREL64_LENGTH, 0 },
387 /* C (SH64PCREL16_64, SH64PCRELPLT) */
388 { 0, 0, SH64PCREL64_LENGTH, 0 },
389 EMPTY, EMPTY,
390 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
391
392 /* C (SH64PCREL16PT_32, SH64PCREL16) */
393 EMPTY,
394 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16PT_32, SH64PCREL32) },
395 /* C (SH64PCREL16PT_32, SH64PCREL32) */
396 { 0, 0, SH64PCREL32_LENGTH, 0 },
397 EMPTY, EMPTY,
398 /* C (SH64PCREL16PT_32, SH64PCRELPLT) */
399 { 0, 0, SH64PCREL32_LENGTH, 0 },
400 EMPTY, EMPTY,
401 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
402
403 /* C (SH64PCREL16PT_64, SH64PCREL16) */
404 EMPTY,
405 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16PT_64, SH64PCREL32) },
406 /* C (SH64PCREL16PT_64, SH64PCREL32) */
407 { SH64PCREL32_F,
5d6255fe 408 SH64PCREL32_M,
324bfcf3
AO		 409 SH64PCREL32_LENGTH,
410 C (SH64PCREL16PT_64, SH64PCREL48) },
411 /* C (SH64PCREL16PT_64, SH64PCREL48) */
412 { SH64PCREL48_F, SH64PCREL48_M, SH64PCREL48_LENGTH, C (SH64PCREL16PT_64, SH64PCREL64) },
413 /* C (SH64PCREL16PT_64, SH64PCREL64) */
414 { 0, 0, SH64PCREL64_LENGTH, 0 },
415 /* C (SH64PCREL16PT_64, SH64PCRELPLT) */
416 { 0, 0, SH64PCREL64_LENGTH, 0},
417 EMPTY, EMPTY,
418 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
419
420 /* C (MOVI_IMM_32, UNDEF_MOVI) */
421 { 0, 0, MOVI_32_LENGTH, 0 },
422 /* C (MOVI_IMM_32, MOVI_16) */
423 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_32, MOVI_32) },
424 /* C (MOVI_IMM_32, MOVI_32) */
425 { MOVI_32_F, MOVI_32_M, MOVI_32_LENGTH, 0 },
426 EMPTY, EMPTY, EMPTY,
427 /* C (MOVI_IMM_32, MOVI_GOTOFF) */
428 { 0, 0, MOVI_32_LENGTH, 0 },
429 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
430
431 /* C (MOVI_IMM_32_PCREL, MOVI_16) */
432 EMPTY,
433 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_32_PCREL, MOVI_32) },
434 /* C (MOVI_IMM_32_PCREL, MOVI_32) */
435 { 0, 0, MOVI_32_LENGTH, 0 },
436 EMPTY, EMPTY,
437 /* C (MOVI_IMM_32_PCREL, MOVI_PLT) */
438 { 0, 0, MOVI_32_LENGTH, 0 },
439 EMPTY,
440 /* C (MOVI_IMM_32_PCREL, MOVI_GOTPC) */
441 { 0, 0, MOVI_32_LENGTH, 0 },
442 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
443
444 /* C (MOVI_IMM_64, UNDEF_MOVI) */
445 { 0, 0, MOVI_64_LENGTH, 0 },
446 /* C (MOVI_IMM_64, MOVI_16) */
447 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_64, MOVI_32) },
448 /* C (MOVI_IMM_64, MOVI_32) */
449 { MOVI_32_F, MOVI_32_M, MOVI_32_LENGTH, C (MOVI_IMM_64, MOVI_48) },
450 /* C (MOVI_IMM_64, MOVI_48) */
451 { MOVI_48_F, MOVI_48_M, MOVI_48_LENGTH, C (MOVI_IMM_64, MOVI_64) },
452 /* C (MOVI_IMM_64, MOVI_64) */
453 { 0, 0, MOVI_64_LENGTH, 0 },
454 EMPTY,
455 /* C (MOVI_IMM_64, MOVI_GOTOFF) */
456 { 0, 0, MOVI_64_LENGTH, 0 },
457 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
458
459 /* C (MOVI_IMM_64_PCREL, MOVI_16) */
460 EMPTY,
461 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_64_PCREL, MOVI_32) },
462 /* C (MOVI_IMM_64_PCREL, MOVI_32) */
463 { MOVI_32_F, MOVI_32_M, MOVI_32_LENGTH, C (MOVI_IMM_64_PCREL, MOVI_48) },
464 /* C (MOVI_IMM_64_PCREL, MOVI_48) */
465 { MOVI_48_F, MOVI_48_M, MOVI_48_LENGTH, C (MOVI_IMM_64_PCREL, MOVI_64) },
466 /* C (MOVI_IMM_64_PCREL, MOVI_64) */
467 { 0, 0, MOVI_64_LENGTH, 0 },
468 /* C (MOVI_IMM_64_PCREL, MOVI_PLT) */
469 { 0, 0, MOVI_64_LENGTH, 0 },
470 EMPTY,
471 /* C (MOVI_IMM_64_PCREL, MOVI_GOTPC) */
472 { 0, 0, MOVI_64_LENGTH, 0 },
473 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
474
475#endif /* HAVE_SH64 */
476
252b5132
RH		 477};
478
43841e91
NC		 479#undef EMPTY
480
252b5132
RH		 481static struct hash_control *opcode_hash_control; /* Opcode mnemonics */
482
a1cc9221
AO		 483\f
484#ifdef OBJ_ELF
538cd60f
AO		 485/* Determinet whether the symbol needs any kind of PIC relocation. */
486
487inline static int
8edc77b9 488sh_PIC_related_p (symbolS *sym)
a1cc9221 489{
538cd60f 490 expressionS *exp;
a1cc9221 491
538cd60f
AO		 492 if (! sym)
493 return 0;
494
495 if (sym == GOT_symbol)
496 return 1;
497
324bfcf3
AO		 498#ifdef HAVE_SH64
499 if (sh_PIC_related_p (*symbol_get_tc (sym)))
500 return 1;
501#endif
502
538cd60f
AO		 503 exp = symbol_get_value_expression (sym);
504
505 return (exp->X_op == O_PIC_reloc
506 || sh_PIC_related_p (exp->X_add_symbol)
507 || sh_PIC_related_p (exp->X_op_symbol));
508}
509
510/* Determine the relocation type to be used to represent the
511 expression, that may be rearranged. */
512
513static int
8edc77b9 514sh_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
538cd60f
AO		 515{
516 expressionS *exp = main_exp;
517
518 /* This is here for backward-compatibility only. GCC used to generated:
519
520 f@PLT + . - (.LPCS# + 2)
521
522 but we'd rather be able to handle this as a PIC-related reference
523 plus/minus a symbol. However, gas' parser gives us:
524
525 O_subtract (O_add (f@PLT, .), .LPCS#+2)
5d6255fe 526
538cd60f
AO		 527 so we attempt to transform this into:
528
529 O_subtract (f@PLT, O_subtract (.LPCS#+2, .))
530
5d6255fe 531 which we can handle simply below. */
538cd60f
AO		 532 if (exp->X_op == O_subtract)
533 {
534 if (sh_PIC_related_p (exp->X_op_symbol))
535 return 1;
536
537 exp = symbol_get_value_expression (exp->X_add_symbol);
538
539 if (exp && sh_PIC_related_p (exp->X_op_symbol))
540 return 1;
541
542 if (exp && exp->X_op == O_add
543 && sh_PIC_related_p (exp->X_add_symbol))
544 {
545 symbolS *sym = exp->X_add_symbol;
546
547 exp->X_op = O_subtract;
548 exp->X_add_symbol = main_exp->X_op_symbol;
549
550 main_exp->X_op_symbol = main_exp->X_add_symbol;
551 main_exp->X_add_symbol = sym;
552
553 main_exp->X_add_number += exp->X_add_number;
554 exp->X_add_number = 0;
555 }
556
557 exp = main_exp;
558 }
559 else if (exp->X_op == O_add && sh_PIC_related_p (exp->X_op_symbol))
560 return 1;
561
562 if (exp->X_op == O_symbol || exp->X_op == O_add || exp->X_op == O_subtract)
563 {
324bfcf3
AO		 564#ifdef HAVE_SH64
565 if (exp->X_add_symbol
566 && (exp->X_add_symbol == GOT_symbol
567 || (GOT_symbol
568 && *symbol_get_tc (exp->X_add_symbol) == GOT_symbol)))
569 {
570 switch (*r_type_p)
571 {
572 case BFD_RELOC_SH_IMM_LOW16:
573 *r_type_p = BFD_RELOC_SH_GOTPC_LOW16;
574 break;
575
576 case BFD_RELOC_SH_IMM_MEDLOW16:
577 *r_type_p = BFD_RELOC_SH_GOTPC_MEDLOW16;
578 break;
579
580 case BFD_RELOC_SH_IMM_MEDHI16:
581 *r_type_p = BFD_RELOC_SH_GOTPC_MEDHI16;
582 break;
583
584 case BFD_RELOC_SH_IMM_HI16:
585 *r_type_p = BFD_RELOC_SH_GOTPC_HI16;
586 break;
587
588 case BFD_RELOC_NONE:
589 case BFD_RELOC_UNUSED:
590 *r_type_p = BFD_RELOC_SH_GOTPC;
591 break;
5d6255fe 592
324bfcf3
AO		 593 default:
594 abort ();
595 }
596 return 0;
597 }
598#else
538cd60f
AO		 599 if (exp->X_add_symbol && exp->X_add_symbol == GOT_symbol)
600 {
601 *r_type_p = BFD_RELOC_SH_GOTPC;
602 return 0;
603 }
324bfcf3 604#endif
538cd60f
AO		 605 exp = symbol_get_value_expression (exp->X_add_symbol);
606 if (! exp)
607 return 0;
608 }
609
610 if (exp->X_op == O_PIC_reloc)
611 {
324bfcf3
AO		 612#ifdef HAVE_SH64
613 switch (*r_type_p)
614 {
615 case BFD_RELOC_NONE:
616 case BFD_RELOC_UNUSED:
617 *r_type_p = exp->X_md;
618 break;
619
620 case BFD_RELOC_SH_IMM_LOW16:
621 switch (exp->X_md)
622 {
623 case BFD_RELOC_32_GOTOFF:
624 *r_type_p = BFD_RELOC_SH_GOTOFF_LOW16;
625 break;
5d6255fe 626
324bfcf3
AO		 627 case BFD_RELOC_SH_GOTPLT32:
628 *r_type_p = BFD_RELOC_SH_GOTPLT_LOW16;
629 break;
5d6255fe 630
324bfcf3
AO		 631 case BFD_RELOC_32_GOT_PCREL:
632 *r_type_p = BFD_RELOC_SH_GOT_LOW16;
633 break;
5d6255fe 634
324bfcf3
AO		 635 case BFD_RELOC_32_PLT_PCREL:
636 *r_type_p = BFD_RELOC_SH_PLT_LOW16;
637 break;
638
639 default:
640 abort ();
641 }
642 break;
643
644 case BFD_RELOC_SH_IMM_MEDLOW16:
645 switch (exp->X_md)
646 {
647 case BFD_RELOC_32_GOTOFF:
648 *r_type_p = BFD_RELOC_SH_GOTOFF_MEDLOW16;
649 break;
5d6255fe 650
324bfcf3
AO		 651 case BFD_RELOC_SH_GOTPLT32:
652 *r_type_p = BFD_RELOC_SH_GOTPLT_MEDLOW16;
653 break;
5d6255fe 654
324bfcf3
AO		 655 case BFD_RELOC_32_GOT_PCREL:
656 *r_type_p = BFD_RELOC_SH_GOT_MEDLOW16;
657 break;
5d6255fe 658
324bfcf3
AO		 659 case BFD_RELOC_32_PLT_PCREL:
660 *r_type_p = BFD_RELOC_SH_PLT_MEDLOW16;
661 break;
662
663 default:
664 abort ();
665 }
666 break;
667
668 case BFD_RELOC_SH_IMM_MEDHI16:
669 switch (exp->X_md)
670 {
671 case BFD_RELOC_32_GOTOFF:
672 *r_type_p = BFD_RELOC_SH_GOTOFF_MEDHI16;
673 break;
5d6255fe 674
324bfcf3
AO		 675 case BFD_RELOC_SH_GOTPLT32:
676 *r_type_p = BFD_RELOC_SH_GOTPLT_MEDHI16;
677 break;
5d6255fe 678
324bfcf3
AO		 679 case BFD_RELOC_32_GOT_PCREL:
680 *r_type_p = BFD_RELOC_SH_GOT_MEDHI16;
681 break;
5d6255fe 682
324bfcf3
AO		 683 case BFD_RELOC_32_PLT_PCREL:
684 *r_type_p = BFD_RELOC_SH_PLT_MEDHI16;
685 break;
686
687 default:
688 abort ();
689 }
690 break;
691
692 case BFD_RELOC_SH_IMM_HI16:
693 switch (exp->X_md)
694 {
695 case BFD_RELOC_32_GOTOFF:
696 *r_type_p = BFD_RELOC_SH_GOTOFF_HI16;
697 break;
5d6255fe 698
324bfcf3
AO		 699 case BFD_RELOC_SH_GOTPLT32:
700 *r_type_p = BFD_RELOC_SH_GOTPLT_HI16;
701 break;
5d6255fe 702
324bfcf3
AO		 703 case BFD_RELOC_32_GOT_PCREL:
704 *r_type_p = BFD_RELOC_SH_GOT_HI16;
705 break;
5d6255fe 706
324bfcf3
AO		 707 case BFD_RELOC_32_PLT_PCREL:
708 *r_type_p = BFD_RELOC_SH_PLT_HI16;
709 break;
710
711 default:
712 abort ();
713 }
714 break;
715
716 default:
717 abort ();
718 }
719#else
538cd60f 720 *r_type_p = exp->X_md;
324bfcf3 721#endif
538cd60f
AO		 722 if (exp == main_exp)
723 exp->X_op = O_symbol;
724 else
725 {
726 main_exp->X_add_symbol = exp->X_add_symbol;
727 main_exp->X_add_number += exp->X_add_number;
728 }
729 }
730 else
731 return (sh_PIC_related_p (exp->X_add_symbol)
732 || sh_PIC_related_p (exp->X_op_symbol));
733
734 return 0;
735}
736
737/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
738
739void
8edc77b9 740sh_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
538cd60f
AO		 741{
742 bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
743
744 if (sh_check_fixup (exp, &r_type))
745 as_bad (_("Invalid PIC expression."));
746
747 if (r_type == BFD_RELOC_UNUSED)
748 switch (size)
a1cc9221 749 {
538cd60f
AO		 750 case 1:
751 r_type = BFD_RELOC_8;
752 break;
a1cc9221 753
538cd60f
AO		 754 case 2:
755 r_type = BFD_RELOC_16;
756 break;
757
758 case 4:
759 r_type = BFD_RELOC_32;
760 break;
a1cc9221 761
324bfcf3
AO		 762#ifdef HAVE_SH64
763 case 8:
764 r_type = BFD_RELOC_64;
765 break;
766#endif
767
538cd60f
AO		 768 default:
769 goto error;
770 }
771 else if (size != 4)
772 {
773 error:
774 as_bad (_("unsupported BFD relocation size %u"), size);
775 r_type = BFD_RELOC_UNUSED;
776 }
5d6255fe 777
538cd60f 778 fix_new_exp (frag, off, size, exp, 0, r_type);
a1cc9221
AO		 779}
780
781/* The regular cons() function, that reads constants, doesn't support
782 suffixes such as @GOT, @GOTOFF and @PLT, that generate
783 machine-specific relocation types. So we must define it here. */
784/* Clobbers input_line_pointer, checks end-of-line. */
8edc77b9 785/* NBYTES 1=.byte, 2=.word, 4=.long */
a1cc9221 786static void
8edc77b9 787sh_elf_cons (register int nbytes)
a1cc9221 788{
538cd60f 789 expressionS exp;
a1cc9221 790
324bfcf3
AO		 791#ifdef HAVE_SH64
792
793 /* Update existing range to include a previous insn, if there was one. */
b34976b6 794 sh64_update_contents_mark (TRUE);
324bfcf3
AO		 795
796 /* We need to make sure the contents type is set to data. */
797 sh64_flag_output ();
798
799#endif /* HAVE_SH64 */
800
a1cc9221
AO		 801 if (is_it_end_of_statement ())
802 {
803 demand_empty_rest_of_line ();
804 return;
805 }
806
028f09bd
NC		 807#ifdef md_cons_align
808 md_cons_align (nbytes);
809#endif
810
a1cc9221
AO		 811 do
812 {
813 expression (&exp);
538cd60f 814 emit_expr (&exp, (unsigned int) nbytes);
a1cc9221
AO		 815 }
816 while (*input_line_pointer++ == ',');
817
81d4177b 818 input_line_pointer--; /* Put terminator back into stream. */
a1cc9221
AO		 819 if (*input_line_pointer == '#' || *input_line_pointer == '!')
820 {
dda5ecfc 821 while (! is_end_of_line[(unsigned char) *input_line_pointer++]);
a1cc9221
AO		 822 }
823 else
824 demand_empty_rest_of_line ();
825}
826#endif /* OBJ_ELF */
827
828\f
6b31947e
NC		 829/* This function is called once, at assembler startup time. This should
830 set up all the tables, etc that the MD part of the assembler needs. */
252b5132
RH		 831
832void
8edc77b9 833md_begin (void)
252b5132 834{
5ff37431 835 const sh_opcode_info *opcode;
252b5132 836 char *prev_name = "";
f6f9408f 837 unsigned int target_arch;
252b5132 838
bdfaef52 839 target_arch
e38bc3b5 840 = preset_target_arch ? preset_target_arch : arch_sh_up & ~arch_sh_has_dsp;
d4845d57
JR		 841 valid_arch = target_arch;
842
324bfcf3
AO		 843#ifdef HAVE_SH64
844 shmedia_md_begin ();
845#endif
846
252b5132
RH		 847 opcode_hash_control = hash_new ();
848
6b31947e 849 /* Insert unique names into hash table. */
252b5132
RH		 850 for (opcode = sh_table; opcode->name; opcode++)
851 {
5ff37431 852 if (strcmp (prev_name, opcode->name) != 0)
252b5132 853 {
f6f9408f 854 if (!SH_MERGE_ARCH_SET_VALID (opcode->arch, target_arch))
a37c8f88 855 continue;
252b5132
RH		 856 prev_name = opcode->name;
857 hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
858 }
252b5132
RH		 859 }
860}
861
862static int reg_m;
863static int reg_n;
d4845d57
JR		 864static int reg_x, reg_y;
865static int reg_efg;
252b5132
RH		 866static int reg_b;
867
3882b010 868#define IDENT_CHAR(c) (ISALNUM (c) || (c) == '_')
dead1419 869
6b31947e
NC		 870/* Try to parse a reg name. Return the number of chars consumed. */
871
252b5132 872static int
8edc77b9 873parse_reg (char *src, int *mode, int *reg)
252b5132 874{
3882b010
L		 875 char l0 = TOLOWER (src[0]);
876 char l1 = l0 ? TOLOWER (src[1]) : 0;
e46fee70 877
dead1419 878 /* We use ! IDENT_CHAR for the next character after the register name, to
252b5132 879 make sure that we won't accidentally recognize a symbol name such as
dead1419 880 'sram' or sr_ram as being a reference to the register 'sr'. */
252b5132 881
e46fee70 882 if (l0 == 'r')
252b5132 883 {
e46fee70 884 if (l1 == '1')
d4845d57
JR		 885 {
886 if (src[2] >= '0' && src[2] <= '5'
dead1419 887 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 888 {
889 *mode = A_REG_N;
890 *reg = 10 + src[2] - '0';
891 return 3;
892 }
893 }
e46fee70 894 if (l1 >= '0' && l1 <= '9'
dead1419 895 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 896 {
897 *mode = A_REG_N;
e46fee70 898 *reg = (l1 - '0');
d4845d57
JR		 899 return 2;
900 }
e46fee70 901 if (l1 >= '0' && l1 <= '7' && strncasecmp (&src[2], "_bank", 5) == 0
dead1419
JR		 902 && ! IDENT_CHAR ((unsigned char) src[7]))
903 {
904 *mode = A_REG_B;
e46fee70 905 *reg = (l1 - '0');
dead1419
JR		 906 return 7;
907 }
d4845d57 908
e46fee70 909 if (l1 == 'e' && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 910 {
911 *mode = A_RE;
912 return 2;
913 }
e46fee70 914 if (l1 == 's' && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 915 {
916 *mode = A_RS;
917 return 2;
918 }
252b5132
RH		 919 }
920
e46fee70 921 if (l0 == 'a')
252b5132 922 {
e46fee70 923 if (l1 == '0')
d4845d57 924 {
dead1419 925 if (! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 926 {
927 *mode = DSP_REG_N;
928 *reg = A_A0_NUM;
929 return 2;
930 }
3882b010 931 if (TOLOWER (src[2]) == 'g' && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 932 {
933 *mode = DSP_REG_N;
934 *reg = A_A0G_NUM;
935 return 3;
936 }
937 }
e46fee70 938 if (l1 == '1')
252b5132 939 {
dead1419 940 if (! IDENT_CHAR ((unsigned char) src[2]))
252b5132 941 {
d4845d57
JR		 942 *mode = DSP_REG_N;
943 *reg = A_A1_NUM;
944 return 2;
945 }
3882b010 946 if (TOLOWER (src[2]) == 'g' && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 947 {
948 *mode = DSP_REG_N;
949 *reg = A_A1G_NUM;
252b5132
RH		 950 return 3;
951 }
952 }
d4845d57 953
e46fee70 954 if (l1 == 'x' && src[2] >= '0' && src[2] <= '1'
dead1419 955 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 956 {
957 *mode = A_REG_N;
e46fee70 958 *reg = 4 + (l1 - '0');
d4845d57
JR		 959 return 3;
960 }
e46fee70 961 if (l1 == 'y' && src[2] >= '0' && src[2] <= '1'
dead1419 962 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 963 {
964 *mode = A_REG_N;
e46fee70 965 *reg = 6 + (l1 - '0');
d4845d57
JR		 966 return 3;
967 }
e46fee70 968 if (l1 == 's' && src[2] >= '0' && src[2] <= '3'
dead1419 969 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57 970 {
e46fee70 971 int n = l1 - '0';
d4845d57
JR		 972
973 *mode = A_REG_N;
974 *reg = n | ((~n & 2) << 1);
975 return 3;
976 }
977 }
978
912a07db 979 if (l0 == 'i' && l1 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57 980 {
e46fee70 981 if (l1 == 's')
d4845d57
JR		 982 {
983 *mode = A_REG_N;
984 *reg = 8;
252b5132
RH		 985 return 2;
986 }
e46fee70 987 if (l1 == 'x')
d4845d57
JR		 988 {
989 *mode = A_REG_N;
990 *reg = 8;
991 return 2;
992 }
e46fee70 993 if (l1 == 'y')
d4845d57
JR		 994 {
995 *mode = A_REG_N;
996 *reg = 9;
997 return 2;
998 }
999 }
1000
e46fee70 1001 if (l0 == 'x' && l1 >= '0' && l1 <= '1'
dead1419 1002 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1003 {
1004 *mode = DSP_REG_N;
e46fee70 1005 *reg = A_X0_NUM + l1 - '0';
d4845d57
JR		 1006 return 2;
1007 }
1008
e46fee70 1009 if (l0 == 'y' && l1 >= '0' && l1 <= '1'
dead1419 1010 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1011 {
1012 *mode = DSP_REG_N;
e46fee70 1013 *reg = A_Y0_NUM + l1 - '0';
d4845d57
JR		 1014 return 2;
1015 }
1016
e46fee70 1017 if (l0 == 'm' && l1 >= '0' && l1 <= '1'
dead1419 1018 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1019 {
1020 *mode = DSP_REG_N;
e46fee70 1021 *reg = l1 == '0' ? A_M0_NUM : A_M1_NUM;
d4845d57 1022 return 2;
252b5132
RH		 1023 }
1024
e46fee70
HPN		 1025 if (l0 == 's'
1026 && l1 == 's'
3882b010 1027 && TOLOWER (src[2]) == 'r' && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1028 {
1029 *mode = A_SSR;
1030 return 3;
1031 }
1032
3882b010 1033 if (l0 == 's' && l1 == 'p' && TOLOWER (src[2]) == 'c'
dead1419 1034 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1035 {
1036 *mode = A_SPC;
1037 return 3;
1038 }
1039
3882b010 1040 if (l0 == 's' && l1 == 'g' && TOLOWER (src[2]) == 'r'
dead1419 1041 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1042 {
1043 *mode = A_SGR;
1044 return 3;
1045 }
1046
3882b010 1047 if (l0 == 'd' && l1 == 's' && TOLOWER (src[2]) == 'r'
dead1419 1048 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1049 {
1050 *mode = A_DSR;
1051 return 3;
1052 }
1053
3882b010 1054 if (l0 == 'd' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 1055 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1056 {
1057 *mode = A_DBR;
1058 return 3;
1059 }
1060
e46fee70 1061 if (l0 == 's' && l1 == 'r' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 1062 {
1063 *mode = A_SR;
1064 return 2;
1065 }
1066
e46fee70 1067 if (l0 == 's' && l1 == 'p' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 1068 {
1069 *mode = A_REG_N;
1070 *reg = 15;
1071 return 2;
1072 }
1073
e46fee70 1074 if (l0 == 'p' && l1 == 'r' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 1075 {
1076 *mode = A_PR;
1077 return 2;
1078 }
e46fee70 1079 if (l0 == 'p' && l1 == 'c' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132 1080 {
015551fc
JR		 1081 /* Don't use A_DISP_PC here - that would accept stuff like 'mova pc,r0'
1082 and use an uninitialized immediate. */
1083 *mode = A_PC;
252b5132
RH		 1084 return 2;
1085 }
3882b010 1086 if (l0 == 'g' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 1087 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1088 {
1089 *mode = A_GBR;
1090 return 3;
1091 }
3882b010 1092 if (l0 == 'v' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 1093 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1094 {
1095 *mode = A_VBR;
1096 return 3;
1097 }
1098
1d70c7fb
AO		 1099 if (l0 == 't' && l1 == 'b' && TOLOWER (src[2]) == 'r'
1100 && ! IDENT_CHAR ((unsigned char) src[3]))
1101 {
1102 *mode = A_TBR;
1103 return 3;
1104 }
3882b010 1105 if (l0 == 'm' && l1 == 'a' && TOLOWER (src[2]) == 'c'
dead1419 1106 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132 1107 {
3882b010 1108 if (TOLOWER (src[3]) == 'l')
252b5132
RH		 1109 {
1110 *mode = A_MACL;
1111 return 4;
1112 }
3882b010 1113 if (TOLOWER (src[3]) == 'h')
252b5132
RH		 1114 {
1115 *mode = A_MACH;
1116 return 4;
1117 }
1118 }
3882b010 1119 if (l0 == 'm' && l1 == 'o' && TOLOWER (src[2]) == 'd'
912a07db 1120 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1121 {
1122 *mode = A_MOD;
1123 return 3;
1124 }
e46fee70 1125 if (l0 == 'f' && l1 == 'r')
252b5132
RH		 1126 {
1127 if (src[2] == '1')
1128 {
1129 if (src[3] >= '0' && src[3] <= '5'
dead1419 1130 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1131 {
1132 *mode = F_REG_N;
1133 *reg = 10 + src[3] - '0';
1134 return 4;
1135 }
1136 }
1137 if (src[2] >= '0' && src[2] <= '9'
dead1419 1138 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1139 {
1140 *mode = F_REG_N;
1141 *reg = (src[2] - '0');
1142 return 3;
1143 }
1144 }
e46fee70 1145 if (l0 == 'd' && l1 == 'r')
252b5132
RH		 1146 {
1147 if (src[2] == '1')
1148 {
1149 if (src[3] >= '0' && src[3] <= '4' && ! ((src[3] - '0') & 1)
dead1419 1150 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1151 {
1152 *mode = D_REG_N;
1153 *reg = 10 + src[3] - '0';
1154 return 4;
1155 }
1156 }
1157 if (src[2] >= '0' && src[2] <= '8' && ! ((src[2] - '0') & 1)
dead1419 1158 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1159 {
1160 *mode = D_REG_N;
1161 *reg = (src[2] - '0');
1162 return 3;
1163 }
1164 }
e46fee70 1165 if (l0 == 'x' && l1 == 'd')
252b5132
RH		 1166 {
1167 if (src[2] == '1')
1168 {
1169 if (src[3] >= '0' && src[3] <= '4' && ! ((src[3] - '0') & 1)
dead1419 1170 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1171 {
1172 *mode = X_REG_N;
1173 *reg = 11 + src[3] - '0';
1174 return 4;
1175 }
1176 }
1177 if (src[2] >= '0' && src[2] <= '8' && ! ((src[2] - '0') & 1)
dead1419 1178 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1179 {
1180 *mode = X_REG_N;
1181 *reg = (src[2] - '0') + 1;
1182 return 3;
1183 }
1184 }
e46fee70 1185 if (l0 == 'f' && l1 == 'v')
252b5132 1186 {
dead1419 1187 if (src[2] == '1'&& src[3] == '2' && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1188 {
1189 *mode = V_REG_N;
1190 *reg = 12;
1191 return 4;
1192 }
1193 if ((src[2] == '0' || src[2] == '4' || src[2] == '8')
dead1419 1194 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1195 {
1196 *mode = V_REG_N;
1197 *reg = (src[2] - '0');
1198 return 3;
1199 }
1200 }
3882b010
L		 1201 if (l0 == 'f' && l1 == 'p' && TOLOWER (src[2]) == 'u'
1202 && TOLOWER (src[3]) == 'l'
dead1419 1203 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1204 {
1205 *mode = FPUL_N;
1206 return 4;
1207 }
1208
3882b010
L		 1209 if (l0 == 'f' && l1 == 'p' && TOLOWER (src[2]) == 's'
1210 && TOLOWER (src[3]) == 'c'
1211 && TOLOWER (src[4]) == 'r' && ! IDENT_CHAR ((unsigned char) src[5]))
252b5132
RH		 1212 {
1213 *mode = FPSCR_N;
1214 return 5;
1215 }
1216
3882b010
L		 1217 if (l0 == 'x' && l1 == 'm' && TOLOWER (src[2]) == 't'
1218 && TOLOWER (src[3]) == 'r'
1219 && TOLOWER (src[4]) == 'x' && ! IDENT_CHAR ((unsigned char) src[5]))
252b5132
RH		 1220 {
1221 *mode = XMTRX_M4;
1222 return 5;
1223 }
1224
1225 return 0;
1226}
1227
c4aa876b 1228static char *
8edc77b9 1229parse_exp (char *s, sh_operand_info *op)
252b5132
RH		 1230{
1231 char *save;
1232 char *new;
1233
1234 save = input_line_pointer;
1235 input_line_pointer = s;
015551fc
JR		 1236 expression (&op->immediate);
1237 if (op->immediate.X_op == O_absent)
252b5132 1238 as_bad (_("missing operand"));
538cd60f
AO		 1239#ifdef OBJ_ELF
1240 else if (op->immediate.X_op == O_PIC_reloc
1241 || sh_PIC_related_p (op->immediate.X_add_symbol)
1242 || sh_PIC_related_p (op->immediate.X_op_symbol))
1243 as_bad (_("misplaced PIC operand"));
1244#endif
252b5132
RH		 1245 new = input_line_pointer;
1246 input_line_pointer = save;
1247 return new;
1248}
1249
252b5132
RH		 1250/* The many forms of operand:
1251
1252 Rn Register direct
1253 @Rn Register indirect
1254 @Rn+ Autoincrement
1255 @-Rn Autodecrement
1256 @(disp:4,Rn)
1257 @(disp:8,GBR)
1258 @(disp:8,PC)
1259
1260 @(R0,Rn)
1261 @(R0,GBR)
1262
1263 disp:8
1264 disp:12
1265 #imm8
1266 pr, gbr, vbr, macl, mach
252b5132
RH		 1267 */
1268
c4aa876b 1269static char *
8edc77b9 1270parse_at (char *src, sh_operand_info *op)
252b5132
RH		 1271{
1272 int len;
1273 int mode;
1274 src++;
1d70c7fb
AO		 1275 if (src[0] == '@')
1276 {
1277 src = parse_at (src, op);
1278 if (op->type == A_DISP_TBR)
1279 op->type = A_DISP2_TBR;
1280 else
1281 as_bad (_("illegal double indirection"));
1282 }
1283 else if (src[0] == '-')
252b5132 1284 {
6b31947e 1285 /* Must be predecrement. */
252b5132
RH		 1286 src++;
1287
1288 len = parse_reg (src, &mode, &(op->reg));
1289 if (mode != A_REG_N)
1290 as_bad (_("illegal register after @-"));
1291
1292 op->type = A_DEC_N;
1293 src += len;
1294 }
1295 else if (src[0] == '(')
1296 {
1297 /* Could be @(disp, rn), @(disp, gbr), @(disp, pc), @(r0, gbr) or
8d4d84c2 1298 @(r0, rn). */
252b5132
RH		 1299 src++;
1300 len = parse_reg (src, &mode, &(op->reg));
1301 if (len && mode == A_REG_N)
1302 {
1303 src += len;
1304 if (op->reg != 0)
1305 {
1306 as_bad (_("must be @(r0,...)"));
1307 }
1308 if (src[0] == ',')
252b5132 1309 {
8d4d84c2
AO		 1310 src++;
1311 /* Now can be rn or gbr. */
1312 len = parse_reg (src, &mode, &(op->reg));
1313 }
1314 else
1315 {
1316 len = 0;
252b5132 1317 }
8d4d84c2 1318 if (len)
252b5132 1319 {
8d4d84c2
AO		 1320 if (mode == A_GBR)
1321 {
1322 op->type = A_R0_GBR;
1323 }
1324 else if (mode == A_REG_N)
1325 {
1326 op->type = A_IND_R0_REG_N;
1327 }
1328 else
1329 {
1330 as_bad (_("syntax error in @(r0,...)"));
1331 }
252b5132
RH		 1332 }
1333 else
1334 {
8d4d84c2 1335 as_bad (_("syntax error in @(r0...)"));
252b5132
RH		 1336 }
1337 }
1338 else
1339 {
8d4d84c2 1340 /* Must be an @(disp,.. thing). */
015551fc 1341 src = parse_exp (src, op);
252b5132
RH		 1342 if (src[0] == ',')
1343 src++;
8d4d84c2 1344 /* Now can be rn, gbr or pc. */
252b5132
RH		 1345 len = parse_reg (src, &mode, &op->reg);
1346 if (len)
1347 {
1348 if (mode == A_REG_N)
1349 {
1350 op->type = A_DISP_REG_N;
1351 }
1352 else if (mode == A_GBR)
1353 {
1354 op->type = A_DISP_GBR;
1355 }
1d70c7fb
AO		 1356 else if (mode == A_TBR)
1357 {
1358 op->type = A_DISP_TBR;
1359 }
015551fc 1360 else if (mode == A_PC)
252b5132 1361 {
dbb4348d
JR		 1362 /* We want @(expr, pc) to uniformly address . + expr,
1363 no matter if expr is a constant, or a more complex
1364 expression, e.g. sym-. or sym1-sym2.
1365 However, we also used to accept @(sym,pc)
67c1ffbe 1366 as addressing sym, i.e. meaning the same as plain sym.
dbb4348d
JR		 1367 Some existing code does use the @(sym,pc) syntax, so
1368 we give it the old semantics for now, but warn about
1369 its use, so that users have some time to fix their code.
1370
1371 Note that due to this backward compatibility hack,
1372 we'll get unexpected results when @(offset, pc) is used,
1373 and offset is a symbol that is set later to an an address
1374 difference, or an external symbol that is set to an
1375 address difference in another source file, so we want to
1376 eventually remove it. */
9691d64f
JR		 1377 if (op->immediate.X_op == O_symbol)
1378 {
1379 op->type = A_DISP_PC;
1380 as_warn (_("Deprecated syntax."));
1381 }
1382 else
1383 {
1384 op->type = A_DISP_PC_ABS;
1385 /* Such operands don't get corrected for PC==.+4, so
1386 make the correction here. */
1387 op->immediate.X_add_number -= 4;
1388 }
252b5132
RH		 1389 }
1390 else
1391 {
1392 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
1393 }
1394 }
1395 else
1396 {
1397 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
1398 }
1399 }
1400 src += len;
1401 if (src[0] != ')')
1402 as_bad (_("expecting )"));
1403 else
1404 src++;
1405 }
1406 else
1407 {
1408 src += parse_reg (src, &mode, &(op->reg));
1409 if (mode != A_REG_N)
006299d3
NC		 1410 as_bad (_("illegal register after @"));
1411
252b5132
RH		 1412 if (src[0] == '+')
1413 {
1000a02a
NC		 1414 char l0, l1;
1415
252b5132 1416 src++;
1000a02a
NC		 1417 l0 = TOLOWER (src[0]);
1418 l1 = TOLOWER (src[1]);
1419
1420 if ((l0 == 'r' && l1 == '8')
1421 || (l0 == 'i' && (l1 == 'x' || l1 == 's')))
d4845d57
JR		 1422 {
1423 src += 2;
88da98f3 1424 op->type = AX_PMOD_N;
d4845d57 1425 }
006299d3
NC		 1426 else if ( (l0 == 'r' && l1 == '9')
1427 || (l0 == 'i' && l1 == 'y'))
d4845d57
JR		 1428 {
1429 src += 2;
88da98f3 1430 op->type = AY_PMOD_N;
d4845d57
JR		 1431 }
1432 else
1433 op->type = A_INC_N;
252b5132
RH		 1434 }
1435 else
006299d3 1436 op->type = A_IND_N;
252b5132
RH		 1437 }
1438 return src;
1439}
1440
1441static void
8edc77b9 1442get_operand (char **ptr, sh_operand_info *op)
252b5132
RH		 1443{
1444 char *src = *ptr;
1445 int mode = -1;
1446 unsigned int len;
1447
1448 if (src[0] == '#')
1449 {
1450 src++;
015551fc 1451 *ptr = parse_exp (src, op);
252b5132
RH		 1452 op->type = A_IMM;
1453 return;
1454 }
1455
1456 else if (src[0] == '@')
1457 {
1458 *ptr = parse_at (src, op);
1459 return;
1460 }
1461 len = parse_reg (src, &mode, &(op->reg));
1462 if (len)
1463 {
1464 *ptr = src + len;
1465 op->type = mode;
1466 return;
1467 }
1468 else
1469 {
6b31947e 1470 /* Not a reg, the only thing left is a displacement. */
015551fc 1471 *ptr = parse_exp (src, op);
252b5132
RH		 1472 op->type = A_DISP_PC;
1473 return;
1474 }
1475}
1476
c4aa876b 1477static char *
8edc77b9 1478get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
252b5132
RH		 1479{
1480 char *ptr = args;
1481 if (info->arg[0])
1482 {
d4845d57
JR		 1483 /* The pre-processor will eliminate whitespace in front of '@'
1484 after the first argument; we may be called multiple times
1485 from assemble_ppi, so don't insist on finding whitespace here. */
1486 if (*ptr == ' ')
1487 ptr++;
252b5132
RH		 1488
1489 get_operand (&ptr, operand + 0);
1490 if (info->arg[1])
1491 {
1492 if (*ptr == ',')
1493 {
1494 ptr++;
1495 }
1496 get_operand (&ptr, operand + 1);
52ccafd0
JR		 1497 /* ??? Hack: psha/pshl have a varying operand number depending on
1498 the type of the first operand. We handle this by having the
1499 three-operand version first and reducing the number of operands
1500 parsed to two if we see that the first operand is an immediate.
1501 This works because no insn with three operands has an immediate
1502 as first operand. */
1503 if (info->arg[2] && operand[0].type != A_IMM)
252b5132
RH		 1504 {
1505 if (*ptr == ',')
1506 {
1507 ptr++;
1508 }
1509 get_operand (&ptr, operand + 2);
1510 }
1511 else
1512 {
1513 operand[2].type = 0;
1514 }
1515 }
1516 else
1517 {
1518 operand[1].type = 0;
1519 operand[2].type = 0;
1520 }
1521 }
1522 else
1523 {
1524 operand[0].type = 0;
1525 operand[1].type = 0;
1526 operand[2].type = 0;
1527 }
1528 return ptr;
1529}
1530
1531/* Passed a pointer to a list of opcodes which use different
1532 addressing modes, return the opcode which matches the opcodes
6b31947e 1533 provided. */
252b5132 1534
c4aa876b 1535static sh_opcode_info *
8edc77b9 1536get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
252b5132
RH		 1537{
1538 sh_opcode_info *this_try = opcode;
1539 char *name = opcode->name;
1540 int n = 0;
c4aa876b 1541
252b5132
RH		 1542 while (opcode->name)
1543 {
1544 this_try = opcode++;
5ff37431 1545 if ((this_try->name != name) && (strcmp (this_try->name, name) != 0))
252b5132
RH		 1546 {
1547 /* We've looked so far down the table that we've run out of
6b31947e 1548 opcodes with the same name. */
252b5132
RH		 1549 return 0;
1550 }
c4aa876b 1551
6b31947e 1552 /* Look at both operands needed by the opcodes and provided by
252b5132
RH		 1553 the user - since an arg test will often fail on the same arg
1554 again and again, we'll try and test the last failing arg the
6b31947e 1555 first on each opcode try. */
252b5132
RH		 1556 for (n = 0; this_try->arg[n]; n++)
1557 {
1558 sh_operand_info *user = operands + n;
1559 sh_arg_type arg = this_try->arg[n];
c4aa876b 1560
1d70c7fb
AO		 1561 if (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh2a_nofpu_up)
1562 && ( arg == A_DISP_REG_M
1563 || arg == A_DISP_REG_N))
1564 {
1565 /* Check a few key IMM* fields for overflow. */
1566 int opf;
1567 long val = user->immediate.X_add_number;
1568
1569 for (opf = 0; opf < 4; opf ++)
1570 switch (this_try->nibbles[opf])
1571 {
1572 case IMM0_4:
1573 case IMM1_4:
1574 if (val < 0 || val > 15)
1575 goto fail;
1576 break;
1577 case IMM0_4BY2:
1578 case IMM1_4BY2:
1579 if (val < 0 || val > 15 * 2)
1580 goto fail;
1581 break;
1582 case IMM0_4BY4:
1583 case IMM1_4BY4:
1584 if (val < 0 || val > 15 * 4)
1585 goto fail;
1586 break;
1587 default:
1588 break;
1589 }
1590 }
252b5132
RH		 1591 switch (arg)
1592 {
7679ead9
AO		 1593 case A_DISP_PC:
1594 if (user->type == A_DISP_PC_ABS)
1595 break;
1596 /* Fall through. */
252b5132
RH		 1597 case A_IMM:
1598 case A_BDISP12:
1599 case A_BDISP8:
1600 case A_DISP_GBR:
1d70c7fb 1601 case A_DISP2_TBR:
252b5132
RH		 1602 case A_MACH:
1603 case A_PR:
1604 case A_MACL:
1605 if (user->type != arg)
1606 goto fail;
1607 break;
1608 case A_R0:
1609 /* opcode needs r0 */
1610 if (user->type != A_REG_N || user->reg != 0)
1611 goto fail;
1612 break;
1613 case A_R0_GBR:
1614 if (user->type != A_R0_GBR || user->reg != 0)
1615 goto fail;
1616 break;
1617 case F_FR0:
1618 if (user->type != F_REG_N || user->reg != 0)
1619 goto fail;
1620 break;
1621
1622 case A_REG_N:
1623 case A_INC_N:
1624 case A_DEC_N:
1625 case A_IND_N:
1626 case A_IND_R0_REG_N:
1627 case A_DISP_REG_N:
1628 case F_REG_N:
1629 case D_REG_N:
1630 case X_REG_N:
1631 case V_REG_N:
1632 case FPUL_N:
1633 case FPSCR_N:
d4845d57 1634 case DSP_REG_N:
252b5132
RH		 1635 /* Opcode needs rn */
1636 if (user->type != arg)
1637 goto fail;
1638 reg_n = user->reg;
1639 break;
252b5132
RH		 1640 case DX_REG_N:
1641 if (user->type != D_REG_N && user->type != X_REG_N)
1642 goto fail;
1643 reg_n = user->reg;
1644 break;
1645 case A_GBR:
1d70c7fb 1646 case A_TBR:
252b5132
RH		 1647 case A_SR:
1648 case A_VBR:
d4845d57
JR		 1649 case A_DSR:
1650 case A_MOD:
1651 case A_RE:
1652 case A_RS:
252b5132
RH		 1653 case A_SSR:
1654 case A_SPC:
1655 case A_SGR:
1656 case A_DBR:
1657 if (user->type != arg)
1658 goto fail;
1659 break;
1660
c4aa876b 1661 case A_REG_B:
252b5132
RH		 1662 if (user->type != arg)
1663 goto fail;
1664 reg_b = user->reg;
1665 break;
1666
1d70c7fb
AO		 1667 case A_INC_R15:
1668 if (user->type != A_INC_N)
1669 goto fail;
1670 if (user->reg != 15)
1671 goto fail;
1672 reg_n = user->reg;
1673 break;
1674
1675 case A_DEC_R15:
1676 if (user->type != A_DEC_N)
1677 goto fail;
1678 if (user->reg != 15)
1679 goto fail;
1680 reg_n = user->reg;
1681 break;
1682
252b5132
RH		 1683 case A_REG_M:
1684 case A_INC_M:
1685 case A_DEC_M:
1686 case A_IND_M:
1687 case A_IND_R0_REG_M:
1688 case A_DISP_REG_M:
d4845d57 1689 case DSP_REG_M:
252b5132
RH		 1690 /* Opcode needs rn */
1691 if (user->type != arg - A_REG_M + A_REG_N)
1692 goto fail;
1693 reg_m = user->reg;
1694 break;
1695
88da98f3
MS		 1696 case AS_DEC_N:
1697 if (user->type != A_DEC_N)
1698 goto fail;
1699 if (user->reg < 2 || user->reg > 5)
1700 goto fail;
1701 reg_n = user->reg;
1702 break;
13ef8878 1703
88da98f3
MS		 1704 case AS_INC_N:
1705 if (user->type != A_INC_N)
1706 goto fail;
1707 if (user->reg < 2 || user->reg > 5)
1708 goto fail;
1709 reg_n = user->reg;
1710 break;
13ef8878 1711
88da98f3
MS		 1712 case AS_IND_N:
1713 if (user->type != A_IND_N)
1714 goto fail;
1715 if (user->reg < 2 || user->reg > 5)
1716 goto fail;
1717 reg_n = user->reg;
1718 break;
13ef8878 1719
88da98f3
MS		 1720 case AS_PMOD_N:
1721 if (user->type != AX_PMOD_N)
1722 goto fail;
1723 if (user->reg < 2 || user->reg > 5)
1724 goto fail;
1725 reg_n = user->reg;
1726 break;
13ef8878 1727
88da98f3
MS		 1728 case AX_INC_N:
1729 if (user->type != A_INC_N)
1730 goto fail;
1731 if (user->reg < 4 || user->reg > 5)
1732 goto fail;
1733 reg_n = user->reg;
1734 break;
13ef8878 1735
88da98f3
MS		 1736 case AX_IND_N:
1737 if (user->type != A_IND_N)
1738 goto fail;
1739 if (user->reg < 4 || user->reg > 5)
1740 goto fail;
1741 reg_n = user->reg;
1742 break;
13ef8878 1743
88da98f3
MS		 1744 case AX_PMOD_N:
1745 if (user->type != AX_PMOD_N)
1746 goto fail;
1747 if (user->reg < 4 || user->reg > 5)
1748 goto fail;
1749 reg_n = user->reg;
1750 break;
13ef8878 1751
88da98f3
MS		 1752 case AXY_INC_N:
1753 if (user->type != A_INC_N)
1754 goto fail;
1755 if ((user->reg < 4 || user->reg > 5)
1756 && (user->reg < 0 || user->reg > 1))
1757 goto fail;
1758 reg_n = user->reg;
1759 break;
13ef8878 1760
88da98f3
MS		 1761 case AXY_IND_N:
1762 if (user->type != A_IND_N)
1763 goto fail;
1764 if ((user->reg < 4 || user->reg > 5)
1765 && (user->reg < 0 || user->reg > 1))
1766 goto fail;
1767 reg_n = user->reg;
1768 break;
13ef8878 1769
88da98f3
MS		 1770 case AXY_PMOD_N:
1771 if (user->type != AX_PMOD_N)
1772 goto fail;
1773 if ((user->reg < 4 || user->reg > 5)
1774 && (user->reg < 0 || user->reg > 1))
1775 goto fail;
1776 reg_n = user->reg;
1777 break;
13ef8878 1778
88da98f3
MS		 1779 case AY_INC_N:
1780 if (user->type != A_INC_N)
1781 goto fail;
1782 if (user->reg < 6 || user->reg > 7)
1783 goto fail;
1784 reg_n = user->reg;
1785 break;
13ef8878 1786
88da98f3
MS		 1787 case AY_IND_N:
1788 if (user->type != A_IND_N)
1789 goto fail;
1790 if (user->reg < 6 || user->reg > 7)
1791 goto fail;
1792 reg_n = user->reg;
1793 break;
13ef8878 1794
88da98f3
MS		 1795 case AY_PMOD_N:
1796 if (user->type != AY_PMOD_N)
1797 goto fail;
1798 if (user->reg < 6 || user->reg > 7)
1799 goto fail;
1800 reg_n = user->reg;
1801 break;
1802
1803 case AYX_INC_N:
1804 if (user->type != A_INC_N)
1805 goto fail;
1806 if ((user->reg < 6 || user->reg > 7)
1807 && (user->reg < 2 || user->reg > 3))
1808 goto fail;
1809 reg_n = user->reg;
1810 break;
13ef8878 1811
88da98f3
MS		 1812 case AYX_IND_N:
1813 if (user->type != A_IND_N)
1814 goto fail;
1815 if ((user->reg < 6 || user->reg > 7)
1816 && (user->reg < 2 || user->reg > 3))
1817 goto fail;
1818 reg_n = user->reg;
1819 break;
13ef8878 1820
88da98f3
MS		 1821 case AYX_PMOD_N:
1822 if (user->type != AY_PMOD_N)
1823 goto fail;
1824 if ((user->reg < 6 || user->reg > 7)
1825 && (user->reg < 2 || user->reg > 3))
1826 goto fail;
1827 reg_n = user->reg;
1828 break;
1829
1830 case DSP_REG_A_M:
1831 if (user->type != DSP_REG_N)
1832 goto fail;
1833 if (user->reg != A_A0_NUM
1834 && user->reg != A_A1_NUM)
1835 goto fail;
1836 reg_m = user->reg;
1837 break;
1838
1839 case DSP_REG_AX:
1840 if (user->type != DSP_REG_N)
1841 goto fail;
1842 switch (user->reg)
1843 {
1844 case A_A0_NUM:
1845 reg_x = 0;
1846 break;
1847 case A_A1_NUM:
1848 reg_x = 2;
1849 break;
1850 case A_X0_NUM:
1851 reg_x = 1;
1852 break;
1853 case A_X1_NUM:
1854 reg_x = 3;
1855 break;
1856 default:
1857 goto fail;
1858 }
1859 break;
1860
1861 case DSP_REG_XY:
1862 if (user->type != DSP_REG_N)
1863 goto fail;
1864 switch (user->reg)
1865 {
1866 case A_X0_NUM:
1867 reg_x = 0;
1868 break;
1869 case A_X1_NUM:
1870 reg_x = 2;
1871 break;
1872 case A_Y0_NUM:
1873 reg_x = 1;
1874 break;
1875 case A_Y1_NUM:
1876 reg_x = 3;
1877 break;
1878 default:
1879 goto fail;
1880 }
1881 break;
1882
1883 case DSP_REG_AY:
1884 if (user->type != DSP_REG_N)
1885 goto fail;
1886 switch (user->reg)
1887 {
1888 case A_A0_NUM:
1889 reg_y = 0;
1890 break;
1891 case A_A1_NUM:
1892 reg_y = 1;
1893 break;
1894 case A_Y0_NUM:
1895 reg_y = 2;
1896 break;
1897 case A_Y1_NUM:
1898 reg_y = 3;
1899 break;
1900 default:
1901 goto fail;
1902 }
1903 break;
1904
1905 case DSP_REG_YX:
1906 if (user->type != DSP_REG_N)
1907 goto fail;
1908 switch (user->reg)
1909 {
1910 case A_Y0_NUM:
1911 reg_y = 0;
1912 break;
1913 case A_Y1_NUM:
1914 reg_y = 1;
1915 break;
1916 case A_X0_NUM:
1917 reg_y = 2;
1918 break;
1919 case A_X1_NUM:
1920 reg_y = 3;
1921 break;
1922 default:
1923 goto fail;
1924 }
1925 break;
1926
d4845d57
JR		 1927 case DSP_REG_X:
1928 if (user->type != DSP_REG_N)
1929 goto fail;
1930 switch (user->reg)
1931 {
1932 case A_X0_NUM:
1933 reg_x = 0;
1934 break;
1935 case A_X1_NUM:
1936 reg_x = 1;
1937 break;
1938 case A_A0_NUM:
1939 reg_x = 2;
1940 break;
1941 case A_A1_NUM:
1942 reg_x = 3;
1943 break;
1944 default:
1945 goto fail;
1946 }
1947 break;
1948
1949 case DSP_REG_Y:
1950 if (user->type != DSP_REG_N)
1951 goto fail;
1952 switch (user->reg)
1953 {
1954 case A_Y0_NUM:
1955 reg_y = 0;
1956 break;
1957 case A_Y1_NUM:
1958 reg_y = 1;
1959 break;
1960 case A_M0_NUM:
1961 reg_y = 2;
1962 break;
1963 case A_M1_NUM:
1964 reg_y = 3;
1965 break;
1966 default:
1967 goto fail;
1968 }
1969 break;
1970
1971 case DSP_REG_E:
1972 if (user->type != DSP_REG_N)
1973 goto fail;
1974 switch (user->reg)
1975 {
1976 case A_X0_NUM:
1977 reg_efg = 0 << 10;
1978 break;
1979 case A_X1_NUM:
1980 reg_efg = 1 << 10;
1981 break;
1982 case A_Y0_NUM:
1983 reg_efg = 2 << 10;
1984 break;
1985 case A_A1_NUM:
1986 reg_efg = 3 << 10;
1987 break;
1988 default:
1989 goto fail;
1990 }
1991 break;
1992
1993 case DSP_REG_F:
1994 if (user->type != DSP_REG_N)
1995 goto fail;
1996 switch (user->reg)
1997 {
1998 case A_Y0_NUM:
1999 reg_efg |= 0 << 8;
2000 break;
2001 case A_Y1_NUM:
2002 reg_efg |= 1 << 8;
2003 break;
2004 case A_X0_NUM:
2005 reg_efg |= 2 << 8;
2006 break;
2007 case A_A1_NUM:
2008 reg_efg |= 3 << 8;
2009 break;
2010 default:
2011 goto fail;
2012 }
2013 break;
2014
2015 case DSP_REG_G:
2016 if (user->type != DSP_REG_N)
2017 goto fail;
2018 switch (user->reg)
2019 {
2020 case A_M0_NUM:
2021 reg_efg |= 0 << 2;
2022 break;
2023 case A_M1_NUM:
2024 reg_efg |= 1 << 2;
2025 break;
2026 case A_A0_NUM:
2027 reg_efg |= 2 << 2;
2028 break;
2029 case A_A1_NUM:
2030 reg_efg |= 3 << 2;
2031 break;
2032 default:
2033 goto fail;
2034 }
2035 break;
2036
2037 case A_A0:
2038 if (user->type != DSP_REG_N || user->reg != A_A0_NUM)
2039 goto fail;
2040 break;
2041 case A_X0:
2042 if (user->type != DSP_REG_N || user->reg != A_X0_NUM)
2043 goto fail;
2044 break;
2045 case A_X1:
2046 if (user->type != DSP_REG_N || user->reg != A_X1_NUM)
2047 goto fail;
2048 break;
2049 case A_Y0:
2050 if (user->type != DSP_REG_N || user->reg != A_Y0_NUM)
2051 goto fail;
2052 break;
2053 case A_Y1:
2054 if (user->type != DSP_REG_N || user->reg != A_Y1_NUM)
2055 goto fail;
2056 break;
2057
252b5132
RH		 2058 case F_REG_M:
2059 case D_REG_M:
2060 case X_REG_M:
2061 case V_REG_M:
2062 case FPUL_M:
2063 case FPSCR_M:
2064 /* Opcode needs rn */
2065 if (user->type != arg - F_REG_M + F_REG_N)
2066 goto fail;
2067 reg_m = user->reg;
2068 break;
2069 case DX_REG_M:
2070 if (user->type != D_REG_N && user->type != X_REG_N)
2071 goto fail;
2072 reg_m = user->reg;
2073 break;
2074 case XMTRX_M4:
2075 if (user->type != XMTRX_M4)
2076 goto fail;
2077 reg_m = 4;
2078 break;
c4aa876b 2079
252b5132
RH		 2080 default:
2081 printf (_("unhandled %d\n"), arg);
2082 goto fail;
2083 }
2084 }
f6f9408f 2085 if ( !SH_MERGE_ARCH_SET_VALID (valid_arch, this_try->arch))
a37c8f88 2086 goto fail;
f6f9408f 2087 valid_arch = SH_MERGE_ARCH_SET (valid_arch, this_try->arch);
252b5132 2088 return this_try;
c4aa876b
NC		 2089 fail:
2090 ;
252b5132
RH		 2091 }
2092
2093 return 0;
2094}
2095
252b5132 2096static void
8edc77b9 2097insert (char *where, int how, int pcrel, sh_operand_info *op)
252b5132
RH		 2098{
2099 fix_new_exp (frag_now,
2100 where - frag_now->fr_literal,
2101 2,
015551fc 2102 &op->immediate,
252b5132
RH		 2103 pcrel,
2104 how);
2105}
2106
1d70c7fb
AO		 2107static void
2108insert4 (char * where, int how, int pcrel, sh_operand_info * op)
2109{
2110 fix_new_exp (frag_now,
2111 where - frag_now->fr_literal,
2112 4,
2113 & op->immediate,
2114 pcrel,
2115 how);
2116}
252b5132 2117static void
8edc77b9 2118build_relax (sh_opcode_info *opcode, sh_operand_info *op)
252b5132
RH		 2119{
2120 int high_byte = target_big_endian ? 0 : 1;
2121 char *p;
2122
2123 if (opcode->arg[0] == A_BDISP8)
2124 {
2125 int what = (opcode->nibbles[1] & 4) ? COND_JUMP_DELAY : COND_JUMP;
2126 p = frag_var (rs_machine_dependent,
2127 md_relax_table[C (what, COND32)].rlx_length,
2128 md_relax_table[C (what, COND8)].rlx_length,
2129 C (what, 0),
015551fc
JR		 2130 op->immediate.X_add_symbol,
2131 op->immediate.X_add_number,
252b5132
RH		 2132 0);
2133 p[high_byte] = (opcode->nibbles[0] << 4) | (opcode->nibbles[1]);
2134 }
2135 else if (opcode->arg[0] == A_BDISP12)
2136 {
2137 p = frag_var (rs_machine_dependent,
2138 md_relax_table[C (UNCOND_JUMP, UNCOND32)].rlx_length,
2139 md_relax_table[C (UNCOND_JUMP, UNCOND12)].rlx_length,
2140 C (UNCOND_JUMP, 0),
015551fc
JR		 2141 op->immediate.X_add_symbol,
2142 op->immediate.X_add_number,
252b5132
RH		 2143 0);
2144 p[high_byte] = (opcode->nibbles[0] << 4);
2145 }
2146
2147}
2148
6b31947e 2149/* Insert ldrs & ldre with fancy relocations that relaxation can recognize. */
d67b5d6d 2150
015551fc 2151static char *
8edc77b9 2152insert_loop_bounds (char *output, sh_operand_info *operand)
015551fc
JR		 2153{
2154 char *name;
2155 symbolS *end_sym;
2156
2157 /* Since the low byte of the opcode will be overwritten by the reloc, we
2158 can just stash the high byte into both bytes and ignore endianness. */
2159 output[0] = 0x8c;
2160 output[1] = 0x8c;
2161 insert (output, BFD_RELOC_SH_LOOP_START, 1, operand);
2162 insert (output, BFD_RELOC_SH_LOOP_END, 1, operand + 1);
2163
2164 if (sh_relax)
2165 {
2166 static int count = 0;
2167
2168 /* If the last loop insn is a two-byte-insn, it is in danger of being
2169 swapped with the insn after it. To prevent this, create a new
2170 symbol - complete with SH_LABEL reloc - after the last loop insn.
2171 If the last loop insn is four bytes long, the symbol will be
2172 right in the middle, but four byte insns are not swapped anyways. */
2173 /* A REPEAT takes 6 bytes. The SH has a 32 bit address space.
2174 Hence a 9 digit number should be enough to count all REPEATs. */
2175 name = alloca (11);
2176 sprintf (name, "_R%x", count++ & 0x3fffffff);
c4aa876b 2177 end_sym = symbol_new (name, undefined_section, 0, &zero_address_frag);
015551fc
JR		 2178 /* Make this a local symbol. */
2179#ifdef OBJ_COFF
2180 SF_SET_LOCAL (end_sym);
2181#endif /* OBJ_COFF */
2182 symbol_table_insert (end_sym);
2183 end_sym->sy_value = operand[1].immediate;
2184 end_sym->sy_value.X_add_number += 2;
2185 fix_new (frag_now, frag_now_fix (), 2, end_sym, 0, 1, BFD_RELOC_SH_LABEL);
2186 }
2187
2188 output = frag_more (2);
2189 output[0] = 0x8e;
2190 output[1] = 0x8e;
2191 insert (output, BFD_RELOC_SH_LOOP_START, 1, operand);
2192 insert (output, BFD_RELOC_SH_LOOP_END, 1, operand + 1);
2193
2194 return frag_more (2);
2195}
2196
d67b5d6d 2197/* Now we know what sort of opcodes it is, let's build the bytes. */
6b31947e 2198
0d10e182 2199static unsigned int
8edc77b9 2200build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
252b5132
RH		 2201{
2202 int index;
1d70c7fb
AO		 2203 char nbuf[8];
2204 char *output;
0d10e182 2205 unsigned int size = 2;
252b5132 2206 int low_byte = target_big_endian ? 1 : 0;
1d70c7fb
AO		 2207 int max_index = 4;
2208
252b5132
RH		 2209 nbuf[0] = 0;
2210 nbuf[1] = 0;
2211 nbuf[2] = 0;
2212 nbuf[3] = 0;
1d70c7fb
AO		 2213 nbuf[4] = 0;
2214 nbuf[5] = 0;
2215 nbuf[6] = 0;
2216 nbuf[7] = 0;
2217
2218 if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
2219 {
2220 output = frag_more (4);
2221 size = 4;
2222 max_index = 8;
2223 }
2224 else
2225 output = frag_more (2);
252b5132 2226
1d70c7fb 2227 for (index = 0; index < max_index; index++)
252b5132
RH		 2228 {
2229 sh_nibble_type i = opcode->nibbles[index];
2230 if (i < 16)
2231 {
2232 nbuf[index] = i;
2233 }
2234 else
2235 {
2236 switch (i)
2237 {
2238 case REG_N:
6a5709a5 2239 case REG_N_D:
252b5132
RH		 2240 nbuf[index] = reg_n;
2241 break;
2242 case REG_M:
2243 nbuf[index] = reg_m;
2244 break;
d4845d57
JR		 2245 case SDT_REG_N:
2246 if (reg_n < 2 || reg_n > 5)
2247 as_bad (_("Invalid register: 'r%d'"), reg_n);
2248 nbuf[index] = (reg_n & 3) | 4;
2249 break;
252b5132
RH		 2250 case REG_NM:
2251 nbuf[index] = reg_n | (reg_m >> 2);
2252 break;
c4aa876b 2253 case REG_B:
252b5132
RH		 2254 nbuf[index] = reg_b | 0x08;
2255 break;
6a5709a5
JR		 2256 case REG_N_B01:
2257 nbuf[index] = reg_n | 0x01;
2258 break;
1d70c7fb
AO		 2259 case IMM0_3s:
2260 nbuf[index] |= 0x08;
2261 case IMM0_3c:
2262 insert (output + low_byte, BFD_RELOC_SH_IMM3, 0, operand);
2263 break;
2264 case IMM0_3Us:
2265 nbuf[index] |= 0x80;
2266 case IMM0_3Uc:
2267 insert (output + low_byte, BFD_RELOC_SH_IMM3U, 0, operand);
2268 break;
2269 case DISP0_12:
2270 insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand);
2271 break;
2272 case DISP0_12BY2:
2273 insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand);
2274 break;
2275 case DISP0_12BY4:
2276 insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand);
2277 break;
2278 case DISP0_12BY8:
2279 insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand);
2280 break;
2281 case DISP1_12:
2282 insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand+1);
2283 break;
2284 case DISP1_12BY2:
2285 insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand+1);
2286 break;
2287 case DISP1_12BY4:
2288 insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand+1);
2289 break;
2290 case DISP1_12BY8:
2291 insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand+1);
2292 break;
2293 case IMM0_20_4:
2294 break;
2295 case IMM0_20:
2296 insert4 (output, BFD_RELOC_SH_DISP20, 0, operand);
2297 break;
2298 case IMM0_20BY8:
2299 insert4 (output, BFD_RELOC_SH_DISP20BY8, 0, operand);
2300 break;
015551fc
JR		 2301 case IMM0_4BY4:
2302 insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand);
2303 break;
2304 case IMM0_4BY2:
2305 insert (output + low_byte, BFD_RELOC_SH_IMM4BY2, 0, operand);
2306 break;
2307 case IMM0_4:
2308 insert (output + low_byte, BFD_RELOC_SH_IMM4, 0, operand);
2309 break;
2310 case IMM1_4BY4:
2311 insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand + 1);
2312 break;
2313 case IMM1_4BY2:
2314 insert (output + low_byte, BFD_RELOC_SH_IMM4BY2, 0, operand + 1);
252b5132 2315 break;
015551fc
JR		 2316 case IMM1_4:
2317 insert (output + low_byte, BFD_RELOC_SH_IMM4, 0, operand + 1);
252b5132 2318 break;
015551fc
JR		 2319 case IMM0_8BY4:
2320 insert (output + low_byte, BFD_RELOC_SH_IMM8BY4, 0, operand);
252b5132 2321 break;
015551fc
JR		 2322 case IMM0_8BY2:
2323 insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand);
252b5132 2324 break;
015551fc
JR		 2325 case IMM0_8:
2326 insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand);
252b5132 2327 break;
015551fc
JR		 2328 case IMM1_8BY4:
2329 insert (output + low_byte, BFD_RELOC_SH_IMM8BY4, 0, operand + 1);
252b5132 2330 break;
015551fc
JR		 2331 case IMM1_8BY2:
2332 insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand + 1);
2333 break;
2334 case IMM1_8:
2335 insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand + 1);
252b5132
RH		 2336 break;
2337 case PCRELIMM_8BY4:
7679ead9
AO		 2338 insert (output, BFD_RELOC_SH_PCRELIMM8BY4,
2339 operand->type != A_DISP_PC_ABS, operand);
252b5132
RH		 2340 break;
2341 case PCRELIMM_8BY2:
7679ead9
AO		 2342 insert (output, BFD_RELOC_SH_PCRELIMM8BY2,
2343 operand->type != A_DISP_PC_ABS, operand);
015551fc
JR		 2344 break;
2345 case REPEAT:
2346 output = insert_loop_bounds (output, operand);
2347 nbuf[index] = opcode->nibbles[3];
2348 operand += 2;
252b5132
RH		 2349 break;
2350 default:
2351 printf (_("failed for %d\n"), i);
2352 }
2353 }
2354 }
c4aa876b
NC		 2355 if (!target_big_endian)
2356 {
2357 output[1] = (nbuf[0] << 4) | (nbuf[1]);
2358 output[0] = (nbuf[2] << 4) | (nbuf[3]);
2359 }
2360 else
2361 {
2362 output[0] = (nbuf[0] << 4) | (nbuf[1]);
2363 output[1] = (nbuf[2] << 4) | (nbuf[3]);
2364 }
1d70c7fb
AO		 2365 if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
2366 {
2367 if (!target_big_endian)
2368 {
2369 output[3] = (nbuf[4] << 4) | (nbuf[5]);
2370 output[2] = (nbuf[6] << 4) | (nbuf[7]);
2371 }
2372 else
2373 {
2374 output[2] = (nbuf[4] << 4) | (nbuf[5]);
2375 output[3] = (nbuf[6] << 4) | (nbuf[7]);
2376 }
2377 }
0d10e182 2378 return size;
252b5132
RH		 2379}
2380
d4845d57
JR		 2381/* Find an opcode at the start of *STR_P in the hash table, and set
2382 *STR_P to the first character after the last one read. */
252b5132 2383
d4845d57 2384static sh_opcode_info *
8edc77b9 2385find_cooked_opcode (char **str_p)
252b5132 2386{
d4845d57 2387 char *str = *str_p;
252b5132
RH		 2388 unsigned char *op_start;
2389 unsigned char *op_end;
252b5132
RH		 2390 char name[20];
2391 int nlen = 0;
c4aa876b 2392
6b31947e 2393 /* Drop leading whitespace. */
252b5132
RH		 2394 while (*str == ' ')
2395 str++;
2396
d4845d57
JR		 2397 /* Find the op code end.
2398 The pre-processor will eliminate whitespace in front of
2399 any '@' after the first argument; we may be called from
2400 assemble_ppi, so the opcode might be terminated by an '@'. */
2132e3a3 2401 for (op_start = op_end = (unsigned char *) str;
252b5132
RH		 2402 *op_end
2403 && nlen < 20
d4845d57 2404 && !is_end_of_line[*op_end] && *op_end != ' ' && *op_end != '@';
252b5132
RH		 2405 op_end++)
2406 {
2407 unsigned char c = op_start[nlen];
2408
2409 /* The machine independent code will convert CMP/EQ into cmp/EQ
d4845d57
JR		 2410 because it thinks the '/' is the end of the symbol. Moreover,
2411 all but the first sub-insn is a parallel processing insn won't
3882b010 2412 be capitalized. Instead of hacking up the machine independent
d4845d57 2413 code, we just deal with it here. */
3882b010 2414 c = TOLOWER (c);
252b5132
RH		 2415 name[nlen] = c;
2416 nlen++;
2417 }
c4aa876b 2418
252b5132 2419 name[nlen] = 0;
2132e3a3 2420 *str_p = (char *) op_end;
252b5132
RH		 2421
2422 if (nlen == 0)
6b31947e 2423 as_bad (_("can't find opcode "));
252b5132 2424
d4845d57
JR		 2425 return (sh_opcode_info *) hash_find (opcode_hash_control, name);
2426}
2427
2428/* Assemble a parallel processing insn. */
2429#define DDT_BASE 0xf000 /* Base value for double data transfer insns */
6b31947e 2430
0d10e182 2431static unsigned int
8edc77b9 2432assemble_ppi (char *op_end, sh_opcode_info *opcode)
d4845d57
JR		 2433{
2434 int movx = 0;
2435 int movy = 0;
2436 int cond = 0;
2437 int field_b = 0;
2438 char *output;
2439 int move_code;
0d10e182 2440 unsigned int size;
d4845d57 2441
d4845d57
JR		 2442 for (;;)
2443 {
2444 sh_operand_info operand[3];
2445
ac62e7a3
JR		 2446 /* Some insn ignore one or more register fields, e.g. psts machl,a0.
2447 Make sure we encode a defined insn pattern. */
2448 reg_x = 0;
2449 reg_y = 0;
2450 reg_n = 0;
2451
d4845d57
JR		 2452 if (opcode->arg[0] != A_END)
2453 op_end = get_operands (opcode, op_end, operand);
88da98f3 2454 try_another_opcode:
d4845d57
JR		 2455 opcode = get_specific (opcode, operand);
2456 if (opcode == 0)
2457 {
6b31947e 2458 /* Couldn't find an opcode which matched the operands. */
d4845d57 2459 char *where = frag_more (2);
0d10e182 2460 size = 2;
d4845d57
JR		 2461
2462 where[0] = 0x0;
2463 where[1] = 0x0;
2464 as_bad (_("invalid operands for opcode"));
0d10e182 2465 return size;
d4845d57 2466 }
c4aa876b 2467
d4845d57
JR		 2468 if (opcode->nibbles[0] != PPI)
2469 as_bad (_("insn can't be combined with parallel processing insn"));
2470
2471 switch (opcode->nibbles[1])
2472 {
2473
2474 case NOPX:
2475 if (movx)
2476 as_bad (_("multiple movx specifications"));
2477 movx = DDT_BASE;
2478 break;
2479 case NOPY:
2480 if (movy)
2481 as_bad (_("multiple movy specifications"));
2482 movy = DDT_BASE;
2483 break;
2484
88da98f3
MS		 2485 case MOVX_NOPY:
2486 if (movx)
2487 as_bad (_("multiple movx specifications"));
2488 if ((reg_n < 4 || reg_n > 5)
2489 && (reg_n < 0 || reg_n > 1))
2490 as_bad (_("invalid movx address register"));
2491 if (movy && movy != DDT_BASE)
2492 as_bad (_("insn cannot be combined with non-nopy"));
2493 movx = ((((reg_n & 1) != 0) << 9)
2494 + (((reg_n & 4) == 0) << 8)
2495 + (reg_x << 6)
2496 + (opcode->nibbles[2] << 4)
2497 + opcode->nibbles[3]
2498 + DDT_BASE);
2499 break;
2500
2501 case MOVY_NOPX:
2502 if (movy)
2503 as_bad (_("multiple movy specifications"));
2504 if ((reg_n < 6 || reg_n > 7)
2505 && (reg_n < 2 || reg_n > 3))
2506 as_bad (_("invalid movy address register"));
2507 if (movx && movx != DDT_BASE)
2508 as_bad (_("insn cannot be combined with non-nopx"));
2509 movy = ((((reg_n & 1) != 0) << 8)
2510 + (((reg_n & 4) == 0) << 9)
2511 + (reg_y << 6)
2512 + (opcode->nibbles[2] << 4)
2513 + opcode->nibbles[3]
2514 + DDT_BASE);
2515 break;
2516
d4845d57
JR		 2517 case MOVX:
2518 if (movx)
2519 as_bad (_("multiple movx specifications"));
88da98f3
MS		 2520 if (movy & 0x2ac)
2521 as_bad (_("previous movy requires nopx"));
d4845d57
JR		 2522 if (reg_n < 4 || reg_n > 5)
2523 as_bad (_("invalid movx address register"));
2524 if (opcode->nibbles[2] & 8)
2525 {
2526 if (reg_m == A_A1_NUM)
2527 movx = 1 << 7;
2528 else if (reg_m != A_A0_NUM)
2529 as_bad (_("invalid movx dsp register"));
2530 }
2531 else
2532 {
2533 if (reg_x > 1)
2534 as_bad (_("invalid movx dsp register"));
2535 movx = reg_x << 7;
2536 }
2537 movx += ((reg_n - 4) << 9) + (opcode->nibbles[2] << 2) + DDT_BASE;
2538 break;
2539
2540 case MOVY:
2541 if (movy)
2542 as_bad (_("multiple movy specifications"));
88da98f3
MS		 2543 if (movx & 0x153)
2544 as_bad (_("previous movx requires nopy"));
d4845d57
JR		 2545 if (opcode->nibbles[2] & 8)
2546 {
2547 /* Bit 3 in nibbles[2] is intended for bit 4 of the opcode,
2548 so add 8 more. */
2549 movy = 8;
2550 if (reg_m == A_A1_NUM)
2551 movy += 1 << 6;
2552 else if (reg_m != A_A0_NUM)
2553 as_bad (_("invalid movy dsp register"));
2554 }
2555 else
2556 {
2557 if (reg_y > 1)
2558 as_bad (_("invalid movy dsp register"));
2559 movy = reg_y << 6;
2560 }
2561 if (reg_n < 6 || reg_n > 7)
2562 as_bad (_("invalid movy address register"));
2563 movy += ((reg_n - 6) << 8) + opcode->nibbles[2] + DDT_BASE;
2564 break;
2565
2566 case PSH:
015551fc 2567 if (operand[0].immediate.X_op != O_constant)
d4845d57
JR		 2568 as_bad (_("dsp immediate shift value not constant"));
2569 field_b = ((opcode->nibbles[2] << 12)
015551fc 2570 | (operand[0].immediate.X_add_number & 127) << 4
d4845d57
JR		 2571 | reg_n);
2572 break;
88da98f3
MS		 2573 case PPI3NC:
2574 if (cond)
2575 {
2576 opcode++;
2577 goto try_another_opcode;
2578 }
2579 /* Fall through. */
d4845d57
JR		 2580 case PPI3:
2581 if (field_b)
2582 as_bad (_("multiple parallel processing specifications"));
2583 field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8)
2584 + (reg_x << 6) + (reg_y << 4) + reg_n);
88da98f3
MS		 2585 switch (opcode->nibbles[4])
2586 {
2587 case HEX_0:
2588 case HEX_XX00:
2589 case HEX_00YY:
2590 break;
2591 case HEX_1:
2592 case HEX_4:
2593 field_b += opcode->nibbles[4] << 4;
2594 break;
2595 default:
2596 abort ();
2597 }
d4845d57
JR		 2598 break;
2599 case PDC:
2600 if (cond)
2601 as_bad (_("multiple condition specifications"));
2602 cond = opcode->nibbles[2] << 8;
2603 if (*op_end)
2604 goto skip_cond_check;
2605 break;
2606 case PPIC:
2607 if (field_b)
2608 as_bad (_("multiple parallel processing specifications"));
2609 field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8)
2610 + cond + (reg_x << 6) + (reg_y << 4) + reg_n);
2611 cond = 0;
88da98f3
MS		 2612 switch (opcode->nibbles[4])
2613 {
2614 case HEX_0:
2615 case HEX_XX00:
2616 case HEX_00YY:
2617 break;
2618 case HEX_1:
2619 case HEX_4:
2620 field_b += opcode->nibbles[4] << 4;
2621 break;
2622 default:
2623 abort ();
2624 }
d4845d57
JR		 2625 break;
2626 case PMUL:
2627 if (field_b)
2628 {
88da98f3
MS		 2629 if ((field_b & 0xef00) == 0xa100)
2630 field_b -= 0x8100;
2631 /* pclr Dz pmuls Se,Sf,Dg */
2632 else if ((field_b & 0xff00) == 0x8d00
f6f9408f 2633 && (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh4al_dsp_up)))
88da98f3 2634 {
f6f9408f 2635 valid_arch = SH_MERGE_ARCH_SET (valid_arch, arch_sh4al_dsp_up);
88da98f3
MS		 2636 field_b -= 0x8cf0;
2637 }
2638 else
d4845d57 2639 as_bad (_("insn cannot be combined with pmuls"));
d4845d57
JR		 2640 switch (field_b & 0xf)
2641 {
2642 case A_X0_NUM:
2643 field_b += 0 - A_X0_NUM;
2644 break;
2645 case A_Y0_NUM:
2646 field_b += 1 - A_Y0_NUM;
2647 break;
2648 case A_A0_NUM:
2649 field_b += 2 - A_A0_NUM;
2650 break;
2651 case A_A1_NUM:
2652 field_b += 3 - A_A1_NUM;
2653 break;
2654 default:
88da98f3 2655 as_bad (_("bad combined pmuls output operand"));
d4845d57 2656 }
7dd04abd
JR		 2657 /* Generate warning if the destination register for padd / psub
2658 and pmuls is the same ( only for A0 or A1 ).
2659 If the last nibble is 1010 then A0 is used in both
2660 padd / psub and pmuls. If it is 1111 then A1 is used
2661 as destination register in both padd / psub and pmuls. */
5db33d76
JR		 2662
2663 if ((((field_b | reg_efg) & 0x000F) == 0x000A)
2664 || (((field_b | reg_efg) & 0x000F) == 0x000F))
2665 as_warn (_("destination register is same for parallel insns"));
d4845d57
JR		 2666 }
2667 field_b += 0x4000 + reg_efg;
2668 break;
2669 default:
2670 abort ();
2671 }
2672 if (cond)
2673 {
2674 as_bad (_("condition not followed by conditionalizable insn"));
2675 cond = 0;
2676 }
2677 if (! *op_end)
2678 break;
2679 skip_cond_check:
2680 opcode = find_cooked_opcode (&op_end);
2681 if (opcode == NULL)
2682 {
2683 (as_bad
2684 (_("unrecognized characters at end of parallel processing insn")));
2685 break;
2686 }
2687 }
2688
2689 move_code = movx | movy;
2690 if (field_b)
2691 {
2692 /* Parallel processing insn. */
2693 unsigned long ppi_code = (movx | movy | 0xf800) << 16 | field_b;
2694
2695 output = frag_more (4);
0d10e182 2696 size = 4;
d4845d57
JR		 2697 if (! target_big_endian)
2698 {
2699 output[3] = ppi_code >> 8;
2700 output[2] = ppi_code;
2701 }
2702 else
2703 {
2704 output[2] = ppi_code >> 8;
2705 output[3] = ppi_code;
2706 }
2707 move_code |= 0xf800;
2708 }
2709 else
0d10e182
JL		 2710 {
2711 /* Just a double data transfer. */
2712 output = frag_more (2);
2713 size = 2;
2714 }
d4845d57
JR		 2715 if (! target_big_endian)
2716 {
2717 output[1] = move_code >> 8;
2718 output[0] = move_code;
2719 }
2720 else
2721 {
2722 output[0] = move_code >> 8;
2723 output[1] = move_code;
2724 }
0d10e182 2725 return size;
d4845d57
JR		 2726}
2727
2728/* This is the guts of the machine-dependent assembler. STR points to a
2729 machine dependent instruction. This function is supposed to emit
6b31947e 2730 the frags/bytes it assembles to. */
d4845d57
JR		 2731
2732void
8edc77b9 2733md_assemble (char *str)
d4845d57 2734{
2132e3a3 2735 char *op_end;
d4845d57
JR		 2736 sh_operand_info operand[3];
2737 sh_opcode_info *opcode;
dda5ecfc 2738 unsigned int size = 0;
ae51a426 2739 char *initial_str = str;
d4845d57 2740
324bfcf3
AO		 2741#ifdef HAVE_SH64
2742 if (sh64_isa_mode == sh64_isa_shmedia)
2743 {
2744 shmedia_md_assemble (str);
2745 return;
2746 }
2747 else
2748 {
2749 /* If we've seen pseudo-directives, make sure any emitted data or
2750 frags are marked as data. */
b34976b6 2751 if (!seen_insn)
324bfcf3 2752 {
b34976b6 2753 sh64_update_contents_mark (TRUE);
324bfcf3
AO		 2754 sh64_set_contents_type (CRT_SH5_ISA16);
2755 }
2756
b34976b6 2757 seen_insn = TRUE;
324bfcf3
AO		 2758 }
2759#endif /* HAVE_SH64 */
2760
d4845d57
JR		 2761 opcode = find_cooked_opcode (&str);
2762 op_end = str;
252b5132
RH		 2763
2764 if (opcode == NULL)
2765 {
ae51a426
JR		 2766 /* The opcode is not in the hash table.
2767 This means we definately have an assembly failure,
2768 but the instruction may be valid in another CPU variant.
2769 In this case emit something better than 'unknown opcode'.
2770 Search the full table in sh-opc.h to check. */
2771
2772 char *name = initial_str;
2773 int name_length = 0;
2774 const sh_opcode_info *op;
2775 int found = 0;
2776
2777 /* identify opcode in string */
871ec896 2778 while (ISSPACE (*name))
ae51a426
JR		 2779 {
2780 name++;
2781 }
871ec896 2782 while (!ISSPACE (name[name_length]))
ae51a426
JR		 2783 {
2784 name_length++;
2785 }
2786
2787 /* search for opcode in full list */
2788 for (op = sh_table; op->name; op++)
2789 {
f6f9408f
JR		 2790 if (strncasecmp (op->name, name, name_length) == 0
2791 && op->name[name_length] == '\0')
ae51a426
JR		 2792 {
2793 found = 1;
2794 break;
2795 }
2796 }
2797
2798 if ( found )
2799 {
2800 as_bad (_("opcode not valid for this cpu variant"));
2801 }
2802 else
2803 {
2804 as_bad (_("unknown opcode"));
2805 }
252b5132
RH		 2806 return;
2807 }
2808
2809 if (sh_relax
2810 && ! seg_info (now_seg)->tc_segment_info_data.in_code)
2811 {
2812 /* Output a CODE reloc to tell the linker that the following
2813 bytes are instructions, not data. */
2814 fix_new (frag_now, frag_now_fix (), 2, &abs_symbol, 0, 0,
2815 BFD_RELOC_SH_CODE);
2816 seg_info (now_seg)->tc_segment_info_data.in_code = 1;
2817 }
2818
d4845d57
JR		 2819 if (opcode->nibbles[0] == PPI)
2820 {
0d10e182 2821 size = assemble_ppi (op_end, opcode);
252b5132
RH		 2822 }
2823 else
2824 {
0d10e182
JL		 2825 if (opcode->arg[0] == A_BDISP12
2826 || opcode->arg[0] == A_BDISP8)
252b5132 2827 {
26c9b704
JR		 2828 /* Since we skip get_specific here, we have to check & update
2829 valid_arch now. */
f6f9408f
JR		 2830 if (SH_MERGE_ARCH_SET_VALID (valid_arch, opcode->arch))
2831 valid_arch = SH_MERGE_ARCH_SET (valid_arch, opcode->arch);
26c9b704
JR		 2832 else
2833 as_bad (_("Delayed branches not available on SH1"));
0d10e182
JL		 2834 parse_exp (op_end + 1, &operand[0]);
2835 build_relax (opcode, &operand[0]);
5fc44b2d
JR		 2836 }
2837 else
2838 {
0d10e182
JL		 2839 if (opcode->arg[0] == A_END)
2840 {
2841 /* Ignore trailing whitespace. If there is any, it has already
2842 been compressed to a single space. */
2843 if (*op_end == ' ')
2844 op_end++;
2845 }
2846 else
2847 {
2848 op_end = get_operands (opcode, op_end, operand);
2849 }
2850 opcode = get_specific (opcode, operand);
252b5132 2851
0d10e182
JL		 2852 if (opcode == 0)
2853 {
2854 /* Couldn't find an opcode which matched the operands. */
2855 char *where = frag_more (2);
2856 size = 2;
252b5132 2857
0d10e182
JL		 2858 where[0] = 0x0;
2859 where[1] = 0x0;
2860 as_bad (_("invalid operands for opcode"));
2861 }
2862 else
2863 {
2864 if (*op_end)
2865 as_bad (_("excess operands: '%s'"), op_end);
2866
2867 size = build_Mytes (opcode, operand);
2868 }
252b5132 2869 }
0d10e182 2870 }
252b5132 2871
4dc7ead9 2872 dwarf2_emit_insn (size);
252b5132
RH		 2873}
2874
2875/* This routine is called each time a label definition is seen. It
2876 emits a BFD_RELOC_SH_LABEL reloc if necessary. */
2877
2878void
07a53e5c 2879sh_frob_label (symbolS *sym)
252b5132
RH		 2880{
2881 static fragS *last_label_frag;
2882 static int last_label_offset;
2883
2884 if (sh_relax
2885 && seg_info (now_seg)->tc_segment_info_data.in_code)
2886 {
2887 int offset;
2888
2889 offset = frag_now_fix ();
2890 if (frag_now != last_label_frag
2891 || offset != last_label_offset)
c4aa876b 2892 {
252b5132
RH		 2893 fix_new (frag_now, offset, 2, &abs_symbol, 0, 0, BFD_RELOC_SH_LABEL);
2894 last_label_frag = frag_now;
2895 last_label_offset = offset;
2896 }
2897 }
07a53e5c
RH		 2898
2899 dwarf2_emit_label (sym);
252b5132
RH		 2900}
2901
2902/* This routine is called when the assembler is about to output some
2903 data. It emits a BFD_RELOC_SH_DATA reloc if necessary. */
2904
2905void
8edc77b9 2906sh_flush_pending_output (void)
252b5132
RH		 2907{
2908 if (sh_relax
2909 && seg_info (now_seg)->tc_segment_info_data.in_code)
2910 {
2911 fix_new (frag_now, frag_now_fix (), 2, &abs_symbol, 0, 0,
2912 BFD_RELOC_SH_DATA);
2913 seg_info (now_seg)->tc_segment_info_data.in_code = 0;
2914 }
2915}
2916
2917symbolS *
8edc77b9 2918md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 2919{
2920 return 0;
2921}
2922
6b31947e
NC		 2923/* Various routines to kill one day. */
2924/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 2925#define MAX_LITTLENUMS 6
2926
6b31947e
NC		 2927/* Turn a string in input_line_pointer into a floating point constant
2928 of type TYPE, and store the appropriate bytes in *LITP. The number
2929 of LITTLENUMS emitted is stored in *SIZEP . An error message is
2930 returned, or NULL on OK. */
2931
252b5132 2932char *
8edc77b9 2933md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 2934{
2935 int prec;
2936 LITTLENUM_TYPE words[4];
2937 char *t;
2938 int i;
2939
2940 switch (type)
2941 {
2942 case 'f':
2943 prec = 2;
2944 break;
2945
2946 case 'd':
2947 prec = 4;
2948 break;
2949
2950 default:
2951 *sizeP = 0;
2952 return _("bad call to md_atof");
2953 }
2954
2955 t = atof_ieee (input_line_pointer, type, words);
2956 if (t)
2957 input_line_pointer = t;
2958
2959 *sizeP = prec * 2;
2960
2961 if (! target_big_endian)
2962 {
2963 for (i = prec - 1; i >= 0; i--)
2964 {
2965 md_number_to_chars (litP, (valueT) words[i], 2);
2966 litP += 2;
2967 }
2968 }
2969 else
2970 {
2971 for (i = 0; i < prec; i++)
2972 {
2973 md_number_to_chars (litP, (valueT) words[i], 2);
2974 litP += 2;
2975 }
2976 }
c4aa876b 2977
252b5132
RH		 2978 return NULL;
2979}
2980
2981/* Handle the .uses pseudo-op. This pseudo-op is used just before a
2982 call instruction. It refers to a label of the instruction which
2983 loads the register which the call uses. We use it to generate a
2984 special reloc for the linker. */
2985
2986static void
8edc77b9 2987s_uses (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 2988{
2989 expressionS ex;
2990
2991 if (! sh_relax)
2992 as_warn (_(".uses pseudo-op seen when not relaxing"));
2993
2994 expression (&ex);
2995
2996 if (ex.X_op != O_symbol || ex.X_add_number != 0)
2997 {
2998 as_bad (_("bad .uses format"));
2999 ignore_rest_of_line ();
3000 return;
3001 }
3002
3003 fix_new_exp (frag_now, frag_now_fix (), 2, &ex, 1, BFD_RELOC_SH_USES);
3004
3005 demand_empty_rest_of_line ();
3006}
3007\f
5a38dc70 3008const char *md_shortopts = "";
6b31947e
NC		 3009struct option md_longopts[] =
3010{
252b5132 3011#define OPTION_RELAX (OPTION_MD_BASE)
05982cac
HPN		 3012#define OPTION_BIG (OPTION_MD_BASE + 1)
3013#define OPTION_LITTLE (OPTION_BIG + 1)
252b5132 3014#define OPTION_SMALL (OPTION_LITTLE + 1)
d4845d57 3015#define OPTION_DSP (OPTION_SMALL + 1)
bdfaef52 3016#define OPTION_ISA (OPTION_DSP + 1)
f55629b8 3017#define OPTION_RENESAS (OPTION_ISA + 1)
252b5132
RH		 3018
3019 {"relax", no_argument, NULL, OPTION_RELAX},
05982cac 3020 {"big", no_argument, NULL, OPTION_BIG},
252b5132
RH		 3021 {"little", no_argument, NULL, OPTION_LITTLE},
3022 {"small", no_argument, NULL, OPTION_SMALL},
d4845d57 3023 {"dsp", no_argument, NULL, OPTION_DSP},
bdfaef52 3024 {"isa", required_argument, NULL, OPTION_ISA},
f55629b8
KK		 3025 {"renesas", no_argument, NULL, OPTION_RENESAS},
3026
324bfcf3 3027#ifdef HAVE_SH64
f55629b8 3028#define OPTION_ABI (OPTION_RENESAS + 1)
324bfcf3
AO		 3029#define OPTION_NO_MIX (OPTION_ABI + 1)
3030#define OPTION_SHCOMPACT_CONST_CRANGE (OPTION_NO_MIX + 1)
3031#define OPTION_NO_EXPAND (OPTION_SHCOMPACT_CONST_CRANGE + 1)
3032#define OPTION_PT32 (OPTION_NO_EXPAND + 1)
324bfcf3
AO		 3033 {"abi", required_argument, NULL, OPTION_ABI},
3034 {"no-mix", no_argument, NULL, OPTION_NO_MIX},
3035 {"shcompact-const-crange", no_argument, NULL, OPTION_SHCOMPACT_CONST_CRANGE},
3036 {"no-expand", no_argument, NULL, OPTION_NO_EXPAND},
3037 {"expand-pt32", no_argument, NULL, OPTION_PT32},
3038#endif /* HAVE_SH64 */
3039
252b5132
RH		 3040 {NULL, no_argument, NULL, 0}
3041};
c4aa876b 3042size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 3043
3044int
8edc77b9 3045md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
252b5132
RH		 3046{
3047 switch (c)
3048 {
3049 case OPTION_RELAX:
3050 sh_relax = 1;
3051 break;
3052
05982cac
HPN		 3053 case OPTION_BIG:
3054 target_big_endian = 1;
3055 break;
3056
252b5132 3057 case OPTION_LITTLE:
252b5132
RH		 3058 target_big_endian = 0;
3059 break;
3060
3061 case OPTION_SMALL:
3062 sh_small = 1;
3063 break;
3064
d4845d57 3065 case OPTION_DSP:
e38bc3b5 3066 preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
d4845d57
JR		 3067 break;
3068
f55629b8
KK		 3069 case OPTION_RENESAS:
3070 dont_adjust_reloc_32 = 1;
3071 break;
3072
324bfcf3 3073 case OPTION_ISA:
871ec896 3074 if (strcasecmp (arg, "dsp") == 0)
e38bc3b5 3075 preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
88da98f3 3076 else if (strcasecmp (arg, "fp") == 0)
e38bc3b5 3077 preset_target_arch = arch_sh_up & ~arch_sh_has_dsp;
bdfaef52 3078 else if (strcasecmp (arg, "any") == 0)
e38bc3b5 3079 preset_target_arch = arch_sh_up;
bdfaef52
JR		 3080#ifdef HAVE_SH64
3081 else if (strcasecmp (arg, "shmedia") == 0)
324bfcf3
AO		 3082 {
3083 if (sh64_isa_mode == sh64_isa_shcompact)
3084 as_bad (_("Invalid combination: --isa=SHcompact with --isa=SHmedia"));
3085 sh64_isa_mode = sh64_isa_shmedia;
3086 }
3087 else if (strcasecmp (arg, "shcompact") == 0)
3088 {
3089 if (sh64_isa_mode == sh64_isa_shmedia)
3090 as_bad (_("Invalid combination: --isa=SHmedia with --isa=SHcompact"));
3091 if (sh64_abi == sh64_abi_64)
3092 as_bad (_("Invalid combination: --abi=64 with --isa=SHcompact"));
3093 sh64_isa_mode = sh64_isa_shcompact;
3094 }
bdfaef52 3095#endif /* HAVE_SH64 */
324bfcf3 3096 else
f6f9408f
JR		 3097 {
3098 extern const bfd_arch_info_type bfd_sh_arch;
871ec896 3099 bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
f6f9408f
JR		 3100 preset_target_arch = 0;
3101 for (; bfd_arch; bfd_arch=bfd_arch->next)
3102 {
3103 int len = strlen(bfd_arch->printable_name);
3104
3105 if (bfd_arch->mach == bfd_mach_sh5)
3106 continue;
3107
3108 if (strncasecmp (bfd_arch->printable_name, arg, len) != 0)
3109 continue;
3110
3111 if (arg[len] == '\0')
3112 preset_target_arch =
3113 sh_get_arch_from_bfd_mach (bfd_arch->mach);
3114 else if (strcasecmp(&arg[len], "-up") == 0)
3115 preset_target_arch =
3116 sh_get_arch_up_from_bfd_mach (bfd_arch->mach);
3117 else
3118 continue;
3119 break;
3120 }
3121
3122 if (!preset_target_arch)
3123 as_bad ("Invalid argument to --isa option: %s", arg);
3124 }
324bfcf3
AO		 3125 break;
3126
bdfaef52 3127#ifdef HAVE_SH64
324bfcf3
AO		 3128 case OPTION_ABI:
3129 if (strcmp (arg, "32") == 0)
3130 {
3131 if (sh64_abi == sh64_abi_64)
3132 as_bad (_("Invalid combination: --abi=32 with --abi=64"));
3133 sh64_abi = sh64_abi_32;
3134 }
3135 else if (strcmp (arg, "64") == 0)
3136 {
3137 if (sh64_abi == sh64_abi_32)
3138 as_bad (_("Invalid combination: --abi=64 with --abi=32"));
3139 if (sh64_isa_mode == sh64_isa_shcompact)
3140 as_bad (_("Invalid combination: --isa=SHcompact with --abi=64"));
3141 sh64_abi = sh64_abi_64;
3142 }
3143 else
3144 as_bad ("Invalid argument to --abi option: %s", arg);
3145 break;
3146
3147 case OPTION_NO_MIX:
b34976b6 3148 sh64_mix = FALSE;
324bfcf3
AO		 3149 break;
3150
3151 case OPTION_SHCOMPACT_CONST_CRANGE:
b34976b6 3152 sh64_shcompact_const_crange = TRUE;
324bfcf3
AO		 3153 break;
3154
3155 case OPTION_NO_EXPAND:
b34976b6 3156 sh64_expand = FALSE;
324bfcf3
AO		 3157 break;
3158
3159 case OPTION_PT32:
b34976b6 3160 sh64_pt32 = TRUE;
324bfcf3
AO		 3161 break;
3162#endif /* HAVE_SH64 */
3163
252b5132
RH		 3164 default:
3165 return 0;
3166 }
3167
3168 return 1;
3169}
3170
3171void
8edc77b9 3172md_show_usage (FILE *stream)
252b5132 3173{
c4aa876b 3174 fprintf (stream, _("\
252b5132
RH		 3175SH options:\n\
3176-little generate little endian code\n\
05982cac 3177-big generate big endian code\n\
252b5132 3178-relax alter jump instructions for long displacements\n\
f55629b8
KK		 3179-renesas disable optimization with section symbol for\n\
3180 compatibility with Renesas assembler.\n\
5b8274e3 3181-small align sections to 4 byte boundaries, not 16\n\
ae51a426 3182-dsp enable sh-dsp insns, and disable floating-point ISAs.\n\
f6f9408f 3183-isa=[any use most appropriate isa\n\
ae51a426 3184 | dsp same as '-dsp'\n\
f6f9408f
JR		 3185 | fp"));
3186 {
3187 extern const bfd_arch_info_type bfd_sh_arch;
871ec896 3188 bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
f6f9408f
JR		 3189 for (; bfd_arch; bfd_arch=bfd_arch->next)
3190 if (bfd_arch->mach != bfd_mach_sh5)
3191 {
3192 fprintf (stream, "\n | %s", bfd_arch->printable_name);
3193 fprintf (stream, "\n | %s-up", bfd_arch->printable_name);
3194 }
3195 }
3196 fprintf (stream, "]\n");
ae51a426
JR		 3197#ifdef HAVE_SH64
3198 fprintf (stream, _("\
3199-isa=[shmedia set as the default instruction set for SH64\n\
88da98f3
MS		 3200 | SHmedia\n\
3201 | shcompact\n\
ae51a426 3202 | SHcompact]\n"));
324bfcf3 3203 fprintf (stream, _("\
324bfcf3
AO		 3204-abi=[32|64] set size of expanded SHmedia operands and object\n\
3205 file type\n\
3206-shcompact-const-crange emit code-range descriptors for constants in\n\
3207 SHcompact code sections\n\
3208-no-mix disallow SHmedia code in the same section as\n\
3209 constants and SHcompact code\n\
3210-no-expand do not expand MOVI, PT, PTA or PTB instructions\n\
3211-expand-pt32 with -abi=64, expand PT, PTA and PTB instructions\n\
2acb89ed 3212 to 32 bits only\n"));
324bfcf3 3213#endif /* HAVE_SH64 */
252b5132
RH		 3214}
3215\f
252b5132
RH		 3216/* This struct is used to pass arguments to sh_count_relocs through
3217 bfd_map_over_sections. */
3218
3219struct sh_count_relocs
3220{
3221 /* Symbol we are looking for. */
3222 symbolS *sym;
3223 /* Count of relocs found. */
3224 int count;
3225};
3226
3227/* Count the number of fixups in a section which refer to a particular
7be1c489 3228 symbol. This is called via bfd_map_over_sections. */
252b5132 3229
252b5132 3230static void
8edc77b9 3231sh_count_relocs (bfd *abfd ATTRIBUTE_UNUSED, segT sec, void *data)
252b5132
RH		 3232{
3233 struct sh_count_relocs *info = (struct sh_count_relocs *) data;
3234 segment_info_type *seginfo;
3235 symbolS *sym;
3236 fixS *fix;
3237
3238 seginfo = seg_info (sec);
3239 if (seginfo == NULL)
3240 return;
3241
3242 sym = info->sym;
3243 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
3244 {
3245 if (fix->fx_addsy == sym)
3246 {
3247 ++info->count;
3248 fix->fx_tcbit = 1;
3249 }
3250 }
3251}
3252
7be1c489
AM		 3253/* Handle the count relocs for a particular section.
3254 This is called via bfd_map_over_sections. */
252b5132 3255
252b5132 3256static void
8edc77b9
KK		 3257sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
3258 void *ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3259{
3260 segment_info_type *seginfo;
3261 fixS *fix;
3262
3263 seginfo = seg_info (sec);
3264 if (seginfo == NULL)
3265 return;
3266
3267 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
3268 {
3269 symbolS *sym;
3270 bfd_vma val;
3271 fixS *fscan;
3272 struct sh_count_relocs info;
3273
3274 if (fix->fx_r_type != BFD_RELOC_SH_USES)
3275 continue;
3276
3277 /* The BFD_RELOC_SH_USES reloc should refer to a defined local
3278 symbol in the same section. */
3279 sym = fix->fx_addsy;
3280 if (sym == NULL
3281 || fix->fx_subsy != NULL
3282 || fix->fx_addnumber != 0
3283 || S_GET_SEGMENT (sym) != sec
252b5132
RH		 3284 || S_IS_EXTERNAL (sym))
3285 {
3286 as_warn_where (fix->fx_file, fix->fx_line,
3287 _(".uses does not refer to a local symbol in the same section"));
3288 continue;
3289 }
3290
3291 /* Look through the fixups again, this time looking for one
3292 at the same location as sym. */
3293 val = S_GET_VALUE (sym);
3294 for (fscan = seginfo->fix_root;
3295 fscan != NULL;
3296 fscan = fscan->fx_next)
3297 if (val == fscan->fx_frag->fr_address + fscan->fx_where
3298 && fscan->fx_r_type != BFD_RELOC_SH_ALIGN
3299 && fscan->fx_r_type != BFD_RELOC_SH_CODE
3300 && fscan->fx_r_type != BFD_RELOC_SH_DATA
3301 && fscan->fx_r_type != BFD_RELOC_SH_LABEL)
3302 break;
3303 if (fscan == NULL)
3304 {
3305 as_warn_where (fix->fx_file, fix->fx_line,
3306 _("can't find fixup pointed to by .uses"));
3307 continue;
3308 }
3309
3310 if (fscan->fx_tcbit)
3311 {
3312 /* We've already done this one. */
3313 continue;
3314 }
3315
6b31947e
NC		 3316 /* The variable fscan should also be a fixup to a local symbol
3317 in the same section. */
252b5132
RH		 3318 sym = fscan->fx_addsy;
3319 if (sym == NULL
3320 || fscan->fx_subsy != NULL
3321 || fscan->fx_addnumber != 0
3322 || S_GET_SEGMENT (sym) != sec
252b5132
RH		 3323 || S_IS_EXTERNAL (sym))
3324 {
3325 as_warn_where (fix->fx_file, fix->fx_line,
3326 _(".uses target does not refer to a local symbol in the same section"));
3327 continue;
3328 }
3329
3330 /* Now we look through all the fixups of all the sections,
3331 counting the number of times we find a reference to sym. */
3332 info.sym = sym;
3333 info.count = 0;
8edc77b9 3334 bfd_map_over_sections (stdoutput, sh_count_relocs, &info);
252b5132
RH		 3335
3336 if (info.count < 1)
3337 abort ();
3338
3339 /* Generate a BFD_RELOC_SH_COUNT fixup at the location of sym.
3340 We have already adjusted the value of sym to include the
3341 fragment address, so we undo that adjustment here. */
3342 subseg_change (sec, 0);
7bcad3e5
NC		 3343 fix_new (fscan->fx_frag,
3344 S_GET_VALUE (sym) - fscan->fx_frag->fr_address,
252b5132
RH		 3345 4, &abs_symbol, info.count, 0, BFD_RELOC_SH_COUNT);
3346 }
3347}
3348
3349/* This function is called after the symbol table has been completed,
3350 but before the relocs or section contents have been written out.
3351 If we have seen any .uses pseudo-ops, they point to an instruction
3352 which loads a register with the address of a function. We look
3353 through the fixups to find where the function address is being
3354 loaded from. We then generate a COUNT reloc giving the number of
3355 times that function address is referred to. The linker uses this
3356 information when doing relaxing, to decide when it can eliminate
3357 the stored function address entirely. */
3358
3359void
8edc77b9 3360sh_frob_file (void)
252b5132 3361{
324bfcf3
AO		 3362#ifdef HAVE_SH64
3363 shmedia_frob_file_before_adjust ();
3364#endif
3365
252b5132
RH		 3366 if (! sh_relax)
3367 return;
3368
8edc77b9 3369 bfd_map_over_sections (stdoutput, sh_frob_section, NULL);
252b5132
RH		 3370}
3371
3372/* Called after relaxing. Set the correct sizes of the fragments, and
55cf6793 3373 create relocs so that md_apply_fix will fill in the correct values. */
252b5132
RH		 3374
3375void
8edc77b9 3376md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT seg, fragS *fragP)
252b5132
RH		 3377{
3378 int donerelax = 0;
3379
3380 switch (fragP->fr_subtype)
3381 {
3382 case C (COND_JUMP, COND8):
3383 case C (COND_JUMP_DELAY, COND8):
3384 subseg_change (seg, 0);
3385 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
3386 1, BFD_RELOC_SH_PCDISP8BY2);
3387 fragP->fr_fix += 2;
3388 fragP->fr_var = 0;
3389 break;
3390
3391 case C (UNCOND_JUMP, UNCOND12):
3392 subseg_change (seg, 0);
3393 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
3394 1, BFD_RELOC_SH_PCDISP12BY2);
3395 fragP->fr_fix += 2;
3396 fragP->fr_var = 0;
3397 break;
3398
3399 case C (UNCOND_JUMP, UNCOND32):
3400 case C (UNCOND_JUMP, UNDEF_WORD_DISP):
3401 if (fragP->fr_symbol == NULL)
99b222b4
HPN		 3402 as_bad_where (fragP->fr_file, fragP->fr_line,
3403 _("displacement overflows 12-bit field"));
252b5132 3404 else if (S_IS_DEFINED (fragP->fr_symbol))
99b222b4
HPN		 3405 as_bad_where (fragP->fr_file, fragP->fr_line,
3406 _("displacement to defined symbol %s overflows 12-bit field"),
3407 S_GET_NAME (fragP->fr_symbol));
252b5132 3408 else
99b222b4
HPN		 3409 as_bad_where (fragP->fr_file, fragP->fr_line,
3410 _("displacement to undefined symbol %s overflows 12-bit field"),
3411 S_GET_NAME (fragP->fr_symbol));
3412 /* Stabilize this frag, so we don't trip an assert. */
3413 fragP->fr_fix += fragP->fr_var;
3414 fragP->fr_var = 0;
252b5132
RH		 3415 break;
3416
3417 case C (COND_JUMP, COND12):
3418 case C (COND_JUMP_DELAY, COND12):
6b31947e 3419 /* A bcond won't fit, so turn it into a b!cond; bra disp; nop. */
252b5132
RH		 3420 /* I found that a relax failure for gcc.c-torture/execute/930628-1.c
3421 was due to gas incorrectly relaxing an out-of-range conditional
3422 branch with delay slot. It turned:
3423 bf.s L6 (slot mov.l r12,@(44,r0))
3424 into:
c4aa876b 3425
252b5132
RH		 34262c: 8f 01 a0 8b bf.s 32 <_main+32> (slot bra L6)
342730: 00 09 nop
342832: 10 cb mov.l r12,@(44,r0)
3429 Therefore, branches with delay slots have to be handled
3430 differently from ones without delay slots. */
3431 {
3432 unsigned char *buffer =
3433 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
3434 int highbyte = target_big_endian ? 0 : 1;
3435 int lowbyte = target_big_endian ? 1 : 0;
3436 int delay = fragP->fr_subtype == C (COND_JUMP_DELAY, COND12);
3437
3438 /* Toggle the true/false bit of the bcond. */
3439 buffer[highbyte] ^= 0x2;
3440
d3ecfc59 3441 /* If this is a delayed branch, we may not put the bra in the
252b5132
RH		 3442 slot. So we change it to a non-delayed branch, like that:
3443 b! cond slot_label; bra disp; slot_label: slot_insn
3444 ??? We should try if swapping the conditional branch and
3445 its delay-slot insn already makes the branch reach. */
3446
3447 /* Build a relocation to six / four bytes farther on. */
3448 subseg_change (seg, 0);
7be1c489 3449 fix_new (fragP, fragP->fr_fix, 2, section_symbol (seg),
252b5132
RH		 3450 fragP->fr_address + fragP->fr_fix + (delay ? 4 : 6),
3451 1, BFD_RELOC_SH_PCDISP8BY2);
3452
3453 /* Set up a jump instruction. */
3454 buffer[highbyte + 2] = 0xa0;
3455 buffer[lowbyte + 2] = 0;
3456 fix_new (fragP, fragP->fr_fix + 2, 2, fragP->fr_symbol,
3457 fragP->fr_offset, 1, BFD_RELOC_SH_PCDISP12BY2);
3458
3459 if (delay)
3460 {
3461 buffer[highbyte] &= ~0x4; /* Removes delay slot from branch. */
3462 fragP->fr_fix += 4;
3463 }
3464 else
3465 {
3466 /* Fill in a NOP instruction. */
3467 buffer[highbyte + 4] = 0x0;
3468 buffer[lowbyte + 4] = 0x9;
3469
3470 fragP->fr_fix += 6;
3471 }
3472 fragP->fr_var = 0;
3473 donerelax = 1;
3474 }
3475 break;
3476
3477 case C (COND_JUMP, COND32):
3478 case C (COND_JUMP_DELAY, COND32):
3479 case C (COND_JUMP, UNDEF_WORD_DISP):
3480 case C (COND_JUMP_DELAY, UNDEF_WORD_DISP):
3481 if (fragP->fr_symbol == NULL)
99b222b4
HPN		 3482 as_bad_where (fragP->fr_file, fragP->fr_line,
3483 _("displacement overflows 8-bit field"));
252b5132 3484 else if (S_IS_DEFINED (fragP->fr_symbol))
99b222b4
HPN		 3485 as_bad_where (fragP->fr_file, fragP->fr_line,
3486 _("displacement to defined symbol %s overflows 8-bit field"),
3487 S_GET_NAME (fragP->fr_symbol));
252b5132 3488 else
99b222b4
HPN		 3489 as_bad_where (fragP->fr_file, fragP->fr_line,
3490 _("displacement to undefined symbol %s overflows 8-bit field "),
3491 S_GET_NAME (fragP->fr_symbol));
3492 /* Stabilize this frag, so we don't trip an assert. */
3493 fragP->fr_fix += fragP->fr_var;
3494 fragP->fr_var = 0;
252b5132
RH		 3495 break;
3496
3497 default:
324bfcf3 3498#ifdef HAVE_SH64
b34976b6 3499 shmedia_md_convert_frag (headers, seg, fragP, TRUE);
324bfcf3 3500#else
252b5132 3501 abort ();
324bfcf3 3502#endif
252b5132
RH		 3503 }
3504
3505 if (donerelax && !sh_relax)
3506 as_warn_where (fragP->fr_file, fragP->fr_line,
3507 _("overflow in branch to %s; converted into longer instruction sequence"),
3508 (fragP->fr_symbol != NULL
3509 ? S_GET_NAME (fragP->fr_symbol)
3510 : ""));
3511}
3512
3513valueT
8edc77b9 3514md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size)
252b5132 3515{
252b5132
RH		 3516#ifdef OBJ_ELF
3517 return size;
3518#else /* ! OBJ_ELF */
3519 return ((size + (1 << bfd_get_section_alignment (stdoutput, seg)) - 1)
3520 & (-1 << bfd_get_section_alignment (stdoutput, seg)));
3521#endif /* ! OBJ_ELF */
252b5132
RH		 3522}
3523
3524/* This static variable is set by s_uacons to tell sh_cons_align that
67c1ffbe 3525 the expression does not need to be aligned. */
252b5132
RH		 3526
3527static int sh_no_align_cons = 0;
3528
3529/* This handles the unaligned space allocation pseudo-ops, such as
3530 .uaword. .uaword is just like .word, but the value does not need
3531 to be aligned. */
3532
3533static void
8edc77b9 3534s_uacons (int bytes)
252b5132
RH		 3535{
3536 /* Tell sh_cons_align not to align this value. */
3537 sh_no_align_cons = 1;
3538 cons (bytes);
3539}
3540
3541/* If a .word, et. al., pseud-op is seen, warn if the value is not
3542 aligned correctly. Note that this can cause warnings to be issued
3543 when assembling initialized structured which were declared with the
3544 packed attribute. FIXME: Perhaps we should require an option to
3545 enable this warning? */
3546
3547void
8edc77b9 3548sh_cons_align (int nbytes)
252b5132
RH		 3549{
3550 int nalign;
3551 char *p;
3552
3553 if (sh_no_align_cons)
3554 {
3555 /* This is an unaligned pseudo-op. */
3556 sh_no_align_cons = 0;
3557 return;
3558 }
3559
3560 nalign = 0;
3561 while ((nbytes & 1) == 0)
3562 {
3563 ++nalign;
3564 nbytes >>= 1;
3565 }
3566
3567 if (nalign == 0)
3568 return;
3569
3570 if (now_seg == absolute_section)
3571 {
3572 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3573 as_warn (_("misaligned data"));
3574 return;
3575 }
3576
0a9ef439 3577 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
252b5132
RH		 3578 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3579
3580 record_alignment (now_seg, nalign);
3581}
3582
3583/* When relaxing, we need to output a reloc for any .align directive
3584 that requests alignment to a four byte boundary or larger. This is
3585 also where we check for misaligned data. */
3586
3587void
8edc77b9 3588sh_handle_align (fragS *frag)
252b5132 3589{
0a9ef439
RH		 3590 int bytes = frag->fr_next->fr_address - frag->fr_address - frag->fr_fix;
3591
3592 if (frag->fr_type == rs_align_code)
3593 {
3594 static const unsigned char big_nop_pattern[] = { 0x00, 0x09 };
3595 static const unsigned char little_nop_pattern[] = { 0x09, 0x00 };
3596
3597 char *p = frag->fr_literal + frag->fr_fix;
3598
3599 if (bytes & 1)
3600 {
3601 *p++ = 0;
3602 bytes--;
3603 frag->fr_fix += 1;
3604 }
3605
3606 if (target_big_endian)
3607 {
3608 memcpy (p, big_nop_pattern, sizeof big_nop_pattern);
3609 frag->fr_var = sizeof big_nop_pattern;
3610 }
3611 else
3612 {
3613 memcpy (p, little_nop_pattern, sizeof little_nop_pattern);
3614 frag->fr_var = sizeof little_nop_pattern;
3615 }
3616 }
3617 else if (frag->fr_type == rs_align_test)
3618 {
3619 if (bytes != 0)
3620 as_warn_where (frag->fr_file, frag->fr_line, _("misaligned data"));
3621 }
3622
252b5132 3623 if (sh_relax
0a9ef439
RH		 3624 && (frag->fr_type == rs_align
3625 || frag->fr_type == rs_align_code)
252b5132
RH		 3626 && frag->fr_address + frag->fr_fix > 0
3627 && frag->fr_offset > 1
3628 && now_seg != bss_section)
3629 fix_new (frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset, 0,
3630 BFD_RELOC_SH_ALIGN);
252b5132
RH		 3631}
3632
28602ebf
KK		 3633/* See whether the relocation should be resolved locally. */
3634
b34976b6 3635static bfd_boolean
8edc77b9 3636sh_local_pcrel (fixS *fix)
28602ebf 3637{
b34976b6
AM		 3638 return (! sh_relax
3639 && (fix->fx_r_type == BFD_RELOC_SH_PCDISP8BY2
3640 || fix->fx_r_type == BFD_RELOC_SH_PCDISP12BY2
3641 || fix->fx_r_type == BFD_RELOC_SH_PCRELIMM8BY2
3642 || fix->fx_r_type == BFD_RELOC_SH_PCRELIMM8BY4
3643 || fix->fx_r_type == BFD_RELOC_8_PCREL
3644 || fix->fx_r_type == BFD_RELOC_SH_SWITCH16
3645 || fix->fx_r_type == BFD_RELOC_SH_SWITCH32));
28602ebf
KK		 3646}
3647
252b5132
RH		 3648/* See whether we need to force a relocation into the output file.
3649 This is used to force out switch and PC relative relocations when
3650 relaxing. */
3651
3652int
8edc77b9 3653sh_force_relocation (fixS *fix)
252b5132 3654{
8ba4dac0
DJ		 3655 /* These relocations can't make it into a DSO, so no use forcing
3656 them for global symbols. */
28602ebf 3657 if (sh_local_pcrel (fix))
8ba4dac0
DJ		 3658 return 0;
3659
9efb3b7b 3660 /* Make sure some relocations get emitted. */
ae6063d4 3661 if (fix->fx_r_type == BFD_RELOC_SH_LOOP_START
a161fe53 3662 || fix->fx_r_type == BFD_RELOC_SH_LOOP_END
9efb3b7b
KK		 3663 || fix->fx_r_type == BFD_RELOC_SH_TLS_GD_32
3664 || fix->fx_r_type == BFD_RELOC_SH_TLS_LD_32
3665 || fix->fx_r_type == BFD_RELOC_SH_TLS_IE_32
3666 || fix->fx_r_type == BFD_RELOC_SH_TLS_LDO_32
3667 || fix->fx_r_type == BFD_RELOC_SH_TLS_LE_32
ae6063d4 3668 || generic_force_reloc (fix))
252b5132
RH		 3669 return 1;
3670
3671 if (! sh_relax)
3672 return 0;
3673
3674 return (fix->fx_pcrel
3675 || SWITCH_TABLE (fix)
3676 || fix->fx_r_type == BFD_RELOC_SH_COUNT
3677 || fix->fx_r_type == BFD_RELOC_SH_ALIGN
3678 || fix->fx_r_type == BFD_RELOC_SH_CODE
3679 || fix->fx_r_type == BFD_RELOC_SH_DATA
324bfcf3
AO		 3680#ifdef HAVE_SH64
3681 || fix->fx_r_type == BFD_RELOC_SH_SHMEDIA_CODE
3682#endif
252b5132
RH		 3683 || fix->fx_r_type == BFD_RELOC_SH_LABEL);
3684}
3685
3686#ifdef OBJ_ELF
b34976b6 3687bfd_boolean
8edc77b9 3688sh_fix_adjustable (fixS *fixP)
252b5132 3689{
a161fe53
AM		 3690 if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
3691 || fixP->fx_r_type == BFD_RELOC_32_GOT_PCREL
3692 || fixP->fx_r_type == BFD_RELOC_SH_GOTPC
f55629b8 3693 || ((fixP->fx_r_type == BFD_RELOC_32) && dont_adjust_reloc_32)
a1cc9221
AO		 3694 || fixP->fx_r_type == BFD_RELOC_RVA)
3695 return 0;
3696
252b5132
RH		 3697 /* We need the symbol name for the VTABLE entries */
3698 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3699 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3700 return 0;
3701
3702 return 1;
3703}
d4845d57 3704
6b31947e 3705void
8edc77b9 3706sh_elf_final_processing (void)
d4845d57
JR		 3707{
3708 int val;
3709
3710 /* Set file-specific flags to indicate if this code needs
88da98f3 3711 a processor with the sh-dsp / sh2e ISA to execute. */
324bfcf3
AO		 3712#ifdef HAVE_SH64
3713 /* SH5 and above don't know about the valid_arch arch_sh* bits defined
3714 in sh-opc.h, so check SH64 mode before checking valid_arch. */
3715 if (sh64_isa_mode != sh64_isa_unspecified)
3716 val = EF_SH5;
3717 else
1a320fbb
NC		 3718#elif defined TARGET_SYMBIAN
3719 if (1)
1a66a017
NC		 3720 {
3721 extern int sh_symbian_find_elf_flags (unsigned int);
3722
3723 val = sh_symbian_find_elf_flags (valid_arch);
3724 }
1a320fbb 3725 else
324bfcf3 3726#endif /* HAVE_SH64 */
f6f9408f 3727 val = sh_find_elf_flags (valid_arch);
d4845d57
JR		 3728
3729 elf_elfheader (stdoutput)->e_flags &= ~EF_SH_MACH_MASK;
3730 elf_elfheader (stdoutput)->e_flags |= val;
3731}
252b5132
RH		 3732#endif
3733
3734/* Apply a fixup to the object file. */
3735
252b5132 3736void
55cf6793 3737md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132
RH		 3738{
3739 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3740 int lowbyte = target_big_endian ? 1 : 0;
3741 int highbyte = target_big_endian ? 0 : 1;
2ed5f585 3742 long val = (long) *valP;
252b5132
RH		 3743 long max, min;
3744 int shift;
3745
a1cc9221
AO		 3746 /* A difference between two symbols, the second of which is in the
3747 current section, is transformed in a PC-relative relocation to
3748 the other symbol. We have to adjust the relocation type here. */
3749 if (fixP->fx_pcrel)
3750 {
3751 switch (fixP->fx_r_type)
3752 {
3753 default:
3754 break;
3755
3756 case BFD_RELOC_32:
3757 fixP->fx_r_type = BFD_RELOC_32_PCREL;
3758 break;
3759
3760 /* Currently, we only support 32-bit PCREL relocations.
3761 We'd need a new reloc type to handle 16_PCREL, and
3762 8_PCREL is already taken for R_SH_SWITCH8, which
3763 apparently does something completely different than what
3764 we need. FIXME. */
3765 case BFD_RELOC_16:
3766 bfd_set_error (bfd_error_bad_value);
94f592af 3767 return;
81d4177b 3768
a1cc9221
AO		 3769 case BFD_RELOC_8:
3770 bfd_set_error (bfd_error_bad_value);
94f592af 3771 return;
a1cc9221
AO		 3772 }
3773 }
3774
6b31947e
NC		 3775 /* The function adjust_reloc_syms won't convert a reloc against a weak
3776 symbol into a reloc against a section, but bfd_install_relocation
3777 will screw up if the symbol is defined, so we have to adjust val here
1308f14c
HPN		 3778 to avoid the screw up later.
3779
3780 For ordinary relocs, this does not happen for ELF, since for ELF,
3781 bfd_install_relocation uses the "special function" field of the
3782 howto, and does not execute the code that needs to be undone, as long
3783 as the special function does not return bfd_reloc_continue.
3784 It can happen for GOT- and PLT-type relocs the way they are
3785 described in elf32-sh.c as they use bfd_elf_generic_reloc, but it
3786 doesn't matter here since those relocs don't use VAL; see below. */
3787 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
3788 && fixP->fx_addsy != NULL
252b5132
RH		 3789 && S_IS_WEAK (fixP->fx_addsy))
3790 val -= S_GET_VALUE (fixP->fx_addsy);
252b5132 3791
bdfaef52
JR		 3792 if (SWITCH_TABLE (fixP))
3793 val -= S_GET_VALUE (fixP->fx_subsy);
252b5132
RH		 3794
3795 max = min = 0;
3796 shift = 0;
3797 switch (fixP->fx_r_type)
3798 {
1d70c7fb
AO		 3799 case BFD_RELOC_SH_IMM3:
3800 max = 0x7;
3801 * buf = (* buf & 0xf8) | (val & 0x7);
3802 break;
3803 case BFD_RELOC_SH_IMM3U:
3804 max = 0x7;
3805 * buf = (* buf & 0x8f) | ((val & 0x7) << 4);
3806 break;
3807 case BFD_RELOC_SH_DISP12:
3808 max = 0xfff;
3809 buf[lowbyte] = val & 0xff;
3810 buf[highbyte] |= (val >> 8) & 0x0f;
3811 break;
3812 case BFD_RELOC_SH_DISP12BY2:
3813 max = 0xfff;
3814 shift = 1;
3815 buf[lowbyte] = (val >> 1) & 0xff;
3816 buf[highbyte] |= (val >> 9) & 0x0f;
3817 break;
3818 case BFD_RELOC_SH_DISP12BY4:
3819 max = 0xfff;
3820 shift = 2;
3821 buf[lowbyte] = (val >> 2) & 0xff;
3822 buf[highbyte] |= (val >> 10) & 0x0f;
3823 break;
3824 case BFD_RELOC_SH_DISP12BY8:
3825 max = 0xfff;
3826 shift = 3;
3827 buf[lowbyte] = (val >> 3) & 0xff;
3828 buf[highbyte] |= (val >> 11) & 0x0f;
3829 break;
3830 case BFD_RELOC_SH_DISP20:
3831 if (! target_big_endian)
3832 abort();
3833 max = 0x7ffff;
3834 min = -0x80000;
28013b5c 3835 buf[1] = (buf[1] & 0x0f) | ((val >> 12) & 0xf0);
1d70c7fb
AO		 3836 buf[2] = (val >> 8) & 0xff;
3837 buf[3] = val & 0xff;
3838 break;
3839 case BFD_RELOC_SH_DISP20BY8:
3840 if (!target_big_endian)
3841 abort();
3842 max = 0x7ffff;
3843 min = -0x80000;
3844 shift = 8;
28013b5c 3845 buf[1] = (buf[1] & 0x0f) | ((val >> 20) & 0xf0);
1d70c7fb
AO		 3846 buf[2] = (val >> 16) & 0xff;
3847 buf[3] = (val >> 8) & 0xff;
3848 break;
3849
252b5132
RH		 3850 case BFD_RELOC_SH_IMM4:
3851 max = 0xf;
3852 *buf = (*buf & 0xf0) | (val & 0xf);
3853 break;
3854
3855 case BFD_RELOC_SH_IMM4BY2:
3856 max = 0xf;
3857 shift = 1;
3858 *buf = (*buf & 0xf0) | ((val >> 1) & 0xf);
3859 break;
3860
3861 case BFD_RELOC_SH_IMM4BY4:
3862 max = 0xf;
3863 shift = 2;
3864 *buf = (*buf & 0xf0) | ((val >> 2) & 0xf);
3865 break;
3866
3867 case BFD_RELOC_SH_IMM8BY2:
3868 max = 0xff;
3869 shift = 1;
3870 *buf = val >> 1;
3871 break;
3872
3873 case BFD_RELOC_SH_IMM8BY4:
3874 max = 0xff;
3875 shift = 2;
3876 *buf = val >> 2;
3877 break;
3878
3879 case BFD_RELOC_8:
3880 case BFD_RELOC_SH_IMM8:
3881 /* Sometimes the 8 bit value is sign extended (e.g., add) and
3882 sometimes it is not (e.g., and). We permit any 8 bit value.
3883 Note that adding further restrictions may invalidate
3884 reasonable looking assembly code, such as ``and -0x1,r0''. */
3885 max = 0xff;
c4aa876b 3886 min = -0xff;
252b5132
RH		 3887 *buf++ = val;
3888 break;
3889
3890 case BFD_RELOC_SH_PCRELIMM8BY4:
3891 /* The lower two bits of the PC are cleared before the
3892 displacement is added in. We can assume that the destination
67c1ffbe 3893 is on a 4 byte boundary. If this instruction is also on a 4
252b5132
RH		 3894 byte boundary, then we want
3895 (target - here) / 4
3896 and target - here is a multiple of 4.
3897 Otherwise, we are on a 2 byte boundary, and we want
3898 (target - (here - 2)) / 4
3899 and target - here is not a multiple of 4. Computing
3900 (target - (here - 2)) / 4 == (target - here + 2) / 4
3901 works for both cases, since in the first case the addition of
3902 2 will be removed by the division. target - here is in the
3903 variable val. */
3904 val = (val + 2) / 4;
3905 if (val & ~0xff)
3906 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3907 buf[lowbyte] = val;
3908 break;
3909
3910 case BFD_RELOC_SH_PCRELIMM8BY2:
3911 val /= 2;
3912 if (val & ~0xff)
3913 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3914 buf[lowbyte] = val;
3915 break;
3916
3917 case BFD_RELOC_SH_PCDISP8BY2:
3918 val /= 2;
3919 if (val < -0x80 || val > 0x7f)
3920 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3921 buf[lowbyte] = val;
3922 break;
3923
3924 case BFD_RELOC_SH_PCDISP12BY2:
3925 val /= 2;
8637c045 3926 if (val < -0x800 || val > 0x7ff)
252b5132
RH		 3927 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
3928 buf[lowbyte] = val & 0xff;
3929 buf[highbyte] |= (val >> 8) & 0xf;
3930 break;
3931
3932 case BFD_RELOC_32:
a1cc9221 3933 case BFD_RELOC_32_PCREL:
1db77c8e 3934 md_number_to_chars (buf, val, 4);
252b5132
RH		 3935 break;
3936
3937 case BFD_RELOC_16:
1db77c8e 3938 md_number_to_chars (buf, val, 2);
252b5132
RH		 3939 break;
3940
3941 case BFD_RELOC_SH_USES:
fefaa1aa 3942 /* Pass the value into sh_reloc(). */
252b5132
RH		 3943 fixP->fx_addnumber = val;
3944 break;
3945
3946 case BFD_RELOC_SH_COUNT:
3947 case BFD_RELOC_SH_ALIGN:
3948 case BFD_RELOC_SH_CODE:
3949 case BFD_RELOC_SH_DATA:
3950 case BFD_RELOC_SH_LABEL:
3951 /* Nothing to do here. */
3952 break;
3953
015551fc
JR		 3954 case BFD_RELOC_SH_LOOP_START:
3955 case BFD_RELOC_SH_LOOP_END:
3956
252b5132
RH		 3957 case BFD_RELOC_VTABLE_INHERIT:
3958 case BFD_RELOC_VTABLE_ENTRY:
3959 fixP->fx_done = 0;
3960 return;
3961
a1cc9221
AO		 3962#ifdef OBJ_ELF
3963 case BFD_RELOC_32_PLT_PCREL:
3964 /* Make the jump instruction point to the address of the operand. At
81d4177b 3965 runtime we merely add the offset to the actual PLT entry. */
94f592af 3966 * valP = 0xfffffffc;
0174e383 3967 val = fixP->fx_offset;
ac3f04d7
AO		 3968 if (fixP->fx_subsy)
3969 val -= S_GET_VALUE (fixP->fx_subsy);
a161fe53 3970 fixP->fx_addnumber = val;
538cd60f 3971 md_number_to_chars (buf, val, 4);
a1cc9221
AO		 3972 break;
3973
3974 case BFD_RELOC_SH_GOTPC:
3975 /* This is tough to explain. We end up with this one if we have
3976 operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]".
3977 The goal here is to obtain the absolute address of the GOT,
3978 and it is strongly preferable from a performance point of
3979 view to avoid using a runtime relocation for this. There are
3980 cases where you have something like:
81d4177b 3981
a1cc9221 3982 .long _GLOBAL_OFFSET_TABLE_+[.-.L66]
81d4177b 3983
a1cc9221
AO		 3984 and here no correction would be required. Internally in the
3985 assembler we treat operands of this form as not being pcrel
3986 since the '.' is explicitly mentioned, and I wonder whether
3987 it would simplify matters to do it this way. Who knows. In
3988 earlier versions of the PIC patches, the pcrel_adjust field
3989 was used to store the correction, but since the expression is
3990 not pcrel, I felt it would be confusing to do it this way. */
94f592af 3991 * valP -= 1;
a1cc9221
AO		 3992 md_number_to_chars (buf, val, 4);
3993 break;
3994
9efb3b7b
KK		 3995 case BFD_RELOC_SH_TLS_GD_32:
3996 case BFD_RELOC_SH_TLS_LD_32:
3997 case BFD_RELOC_SH_TLS_IE_32:
2bba4140
KK		 3998 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3999 /* Fallthrough */
4000 case BFD_RELOC_32_GOT_PCREL:
4001 case BFD_RELOC_SH_GOTPLT32:
94f592af 4002 * valP = 0; /* Fully resolved at runtime. No addend. */
a1cc9221
AO		 4003 md_number_to_chars (buf, 0, 4);
4004 break;
4005
9efb3b7b
KK		 4006 case BFD_RELOC_SH_TLS_LDO_32:
4007 case BFD_RELOC_SH_TLS_LE_32:
2bba4140
KK		 4008 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4009 /* Fallthrough */
4010 case BFD_RELOC_32_GOTOFF:
538cd60f 4011 md_number_to_chars (buf, val, 4);
a1cc9221
AO		 4012 break;
4013#endif
4014
252b5132 4015 default:
324bfcf3 4016#ifdef HAVE_SH64
55cf6793 4017 shmedia_md_apply_fix (fixP, valP);
324bfcf3
AO		 4018 return;
4019#else
252b5132 4020 abort ();
324bfcf3 4021#endif
252b5132
RH		 4022 }
4023
4024 if (shift != 0)
4025 {
4026 if ((val & ((1 << shift) - 1)) != 0)
4027 as_bad_where (fixP->fx_file, fixP->fx_line, _("misaligned offset"));
4028 if (val >= 0)
4029 val >>= shift;
4030 else
4031 val = ((val >> shift)
4032 | ((long) -1 & ~ ((long) -1 >> shift)));
4033 }
4034 if (max != 0 && (val < min || val > max))
4035 as_bad_where (fixP->fx_file, fixP->fx_line, _("offset out of range"));
4036
94f592af
NC		 4037 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4038 fixP->fx_done = 1;
252b5132
RH		 4039}
4040
4041/* Called just before address relaxation. Return the length
4042 by which a fragment must grow to reach it's destination. */
4043
4044int
8edc77b9 4045md_estimate_size_before_relax (fragS *fragP, segT segment_type)
252b5132 4046{
e66457fb
AM		 4047 int what;
4048
252b5132
RH		 4049 switch (fragP->fr_subtype)
4050 {
93c2a809 4051 default:
324bfcf3
AO		 4052#ifdef HAVE_SH64
4053 return shmedia_md_estimate_size_before_relax (fragP, segment_type);
4054#else
93c2a809 4055 abort ();
324bfcf3
AO		 4056#endif
4057
93c2a809 4058
252b5132 4059 case C (UNCOND_JUMP, UNDEF_DISP):
6b31947e 4060 /* Used to be a branch to somewhere which was unknown. */
252b5132
RH		 4061 if (!fragP->fr_symbol)
4062 {
4063 fragP->fr_subtype = C (UNCOND_JUMP, UNCOND12);
252b5132
RH		 4064 }
4065 else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4066 {
4067 fragP->fr_subtype = C (UNCOND_JUMP, UNCOND12);
252b5132
RH		 4068 }
4069 else
4070 {
4071 fragP->fr_subtype = C (UNCOND_JUMP, UNDEF_WORD_DISP);
252b5132
RH		 4072 }
4073 break;
4074
252b5132
RH		 4075 case C (COND_JUMP, UNDEF_DISP):
4076 case C (COND_JUMP_DELAY, UNDEF_DISP):
e66457fb 4077 what = GET_WHAT (fragP->fr_subtype);
6b31947e 4078 /* Used to be a branch to somewhere which was unknown. */
252b5132
RH		 4079 if (fragP->fr_symbol
4080 && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4081 {
252b5132 4082 /* Got a symbol and it's defined in this segment, become byte
6b31947e 4083 sized - maybe it will fix up. */
252b5132 4084 fragP->fr_subtype = C (what, COND8);
252b5132
RH		 4085 }
4086 else if (fragP->fr_symbol)
4087 {
6b31947e 4088 /* Its got a segment, but its not ours, so it will always be long. */
252b5132 4089 fragP->fr_subtype = C (what, UNDEF_WORD_DISP);
252b5132
RH		 4090 }
4091 else
4092 {
6b31947e 4093 /* We know the abs value. */
252b5132 4094 fragP->fr_subtype = C (what, COND8);
252b5132 4095 }
93c2a809 4096 break;
252b5132 4097
93c2a809 4098 case C (UNCOND_JUMP, UNCOND12):
e66457fb 4099 case C (UNCOND_JUMP, UNCOND32):
93c2a809
AM		 4100 case C (UNCOND_JUMP, UNDEF_WORD_DISP):
4101 case C (COND_JUMP, COND8):
e66457fb
AM		 4102 case C (COND_JUMP, COND12):
4103 case C (COND_JUMP, COND32):
93c2a809
AM		 4104 case C (COND_JUMP, UNDEF_WORD_DISP):
4105 case C (COND_JUMP_DELAY, COND8):
e66457fb
AM		 4106 case C (COND_JUMP_DELAY, COND12):
4107 case C (COND_JUMP_DELAY, COND32):
93c2a809
AM		 4108 case C (COND_JUMP_DELAY, UNDEF_WORD_DISP):
4109 /* When relaxing a section for the second time, we don't need to
e66457fb 4110 do anything besides return the current size. */
252b5132
RH		 4111 break;
4112 }
e66457fb
AM		 4113
4114 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4115 return fragP->fr_var;
4116}
4117
6b31947e 4118/* Put number into target byte order. */
252b5132
RH		 4119
4120void
8edc77b9 4121md_number_to_chars (char *ptr, valueT use, int nbytes)
252b5132 4122{
324bfcf3
AO		 4123#ifdef HAVE_SH64
4124 /* We might need to set the contents type to data. */
4125 sh64_flag_output ();
4126#endif
4127
252b5132
RH		 4128 if (! target_big_endian)
4129 number_to_chars_littleendian (ptr, use, nbytes);
4130 else
4131 number_to_chars_bigendian (ptr, use, nbytes);
4132}
4133
7be1c489 4134/* This version is used in obj-coff.c eg. for the sh-hms target. */
cce5a618
NC		 4135
4136long
8edc77b9 4137md_pcrel_from (fixS *fixP)
cce5a618
NC		 4138{
4139 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address + 2;
4140}
4141
252b5132 4142long
8edc77b9 4143md_pcrel_from_section (fixS *fixP, segT sec)
252b5132 4144{
28602ebf
KK		 4145 if (! sh_local_pcrel (fixP)
4146 && fixP->fx_addsy != (symbolS *) NULL
ae6063d4 4147 && (generic_force_reloc (fixP)
ef17112f
HPN		 4148 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
4149 {
4150 /* The symbol is undefined (or is defined but not in this section,
4151 or we're not sure about it being the final definition). Let the
4152 linker figure it out. We need to adjust the subtraction of a
4153 symbol to the position of the relocated data, though. */
4154 return fixP->fx_subsy ? fixP->fx_where + fixP->fx_frag->fr_address : 0;
4155 }
4156
cce5a618 4157 return md_pcrel_from (fixP);
252b5132
RH		 4158}
4159
252b5132
RH		 4160/* Create a reloc. */
4161
4162arelent *
8edc77b9 4163tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 4164{
4165 arelent *rel;
4166 bfd_reloc_code_real_type r_type;
4167
4168 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 4169 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4170 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 4171 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4172
4173 r_type = fixp->fx_r_type;
4174
4175 if (SWITCH_TABLE (fixp))
4176 {
bdfaef52
JR		 4177 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
4178 rel->addend = 0;
252b5132
RH		 4179 if (r_type == BFD_RELOC_16)
4180 r_type = BFD_RELOC_SH_SWITCH16;
4181 else if (r_type == BFD_RELOC_8)
4182 r_type = BFD_RELOC_8_PCREL;
4183 else if (r_type == BFD_RELOC_32)
4184 r_type = BFD_RELOC_SH_SWITCH32;
4185 else
4186 abort ();
4187 }
4188 else if (r_type == BFD_RELOC_SH_USES)
4189 rel->addend = fixp->fx_addnumber;
4190 else if (r_type == BFD_RELOC_SH_COUNT)
4191 rel->addend = fixp->fx_offset;
4192 else if (r_type == BFD_RELOC_SH_ALIGN)
4193 rel->addend = fixp->fx_offset;
4194 else if (r_type == BFD_RELOC_VTABLE_INHERIT
4195 || r_type == BFD_RELOC_VTABLE_ENTRY)
4196 rel->addend = fixp->fx_offset;
015551fc
JR		 4197 else if (r_type == BFD_RELOC_SH_LOOP_START
4198 || r_type == BFD_RELOC_SH_LOOP_END)
4199 rel->addend = fixp->fx_offset;
4200 else if (r_type == BFD_RELOC_SH_LABEL && fixp->fx_pcrel)
4201 {
4202 rel->addend = 0;
4203 rel->address = rel->addend = fixp->fx_offset;
4204 }
324bfcf3
AO		 4205#ifdef HAVE_SH64
4206 else if (shmedia_init_reloc (rel, fixp))
4207 ;
4208#endif
252b5132
RH		 4209 else if (fixp->fx_pcrel)
4210 rel->addend = fixp->fx_addnumber;
a1cc9221
AO		 4211 else if (r_type == BFD_RELOC_32 || r_type == BFD_RELOC_32_GOTOFF)
4212 rel->addend = fixp->fx_addnumber;
252b5132
RH		 4213 else
4214 rel->addend = 0;
4215
4216 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
78878175 4217
a161fe53 4218 if (rel->howto == NULL)
252b5132
RH		 4219 {
4220 as_bad_where (fixp->fx_file, fixp->fx_line,
4221 _("Cannot represent relocation type %s"),
4222 bfd_get_reloc_code_name (r_type));
4223 /* Set howto to a garbage value so that we can keep going. */
4224 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4225 assert (rel->howto != NULL);
4226 }
78878175
NC		 4227#ifdef OBJ_ELF
4228 else if (rel->howto->type == R_SH_IND12W)
4229 rel->addend += fixp->fx_offset - 4;
4230#endif
252b5132
RH		 4231
4232 return rel;
4233}
4234
538cd60f
AO		 4235#ifdef OBJ_ELF
4236inline static char *
8edc77b9 4237sh_end_of_match (char *cont, char *what)
538cd60f
AO		 4238{
4239 int len = strlen (what);
4240
4241 if (strncasecmp (cont, what, strlen (what)) == 0
4242 && ! is_part_of_name (cont[len]))
4243 return cont + len;
4244
4245 return NULL;
5d6255fe 4246}
538cd60f
AO		 4247
4248int
8edc77b9 4249sh_parse_name (char const *name, expressionS *exprP, char *nextcharP)
538cd60f
AO		 4250{
4251 char *next = input_line_pointer;
4252 char *next_end;
4253 int reloc_type;
4254 segT segment;
4255
4256 exprP->X_op_symbol = NULL;
4257
4258 if (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4259 {
4260 if (! GOT_symbol)
4261 GOT_symbol = symbol_find_or_make (name);
4262
4263 exprP->X_add_symbol = GOT_symbol;
4264 no_suffix:
4265 /* If we have an absolute symbol or a reg, then we know its
4266 value now. */
4267 segment = S_GET_SEGMENT (exprP->X_add_symbol);
4268 if (segment == absolute_section)
4269 {
4270 exprP->X_op = O_constant;
4271 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
4272 exprP->X_add_symbol = NULL;
4273 }
4274 else if (segment == reg_section)
4275 {
4276 exprP->X_op = O_register;
4277 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
4278 exprP->X_add_symbol = NULL;
4279 }
4280 else
4281 {
4282 exprP->X_op = O_symbol;
4283 exprP->X_add_number = 0;
4284 }
4285
4286 return 1;
4287 }
4288
4289 exprP->X_add_symbol = symbol_find_or_make (name);
5d6255fe 4290
538cd60f
AO		 4291 if (*nextcharP != '@')
4292 goto no_suffix;
4293 else if ((next_end = sh_end_of_match (next + 1, "GOTOFF")))
4294 reloc_type = BFD_RELOC_32_GOTOFF;
324bfcf3
AO		 4295 else if ((next_end = sh_end_of_match (next + 1, "GOTPLT")))
4296 reloc_type = BFD_RELOC_SH_GOTPLT32;
538cd60f
AO		 4297 else if ((next_end = sh_end_of_match (next + 1, "GOT")))
4298 reloc_type = BFD_RELOC_32_GOT_PCREL;
4299 else if ((next_end = sh_end_of_match (next + 1, "PLT")))
4300 reloc_type = BFD_RELOC_32_PLT_PCREL;
9efb3b7b
KK		 4301 else if ((next_end = sh_end_of_match (next + 1, "TLSGD")))
4302 reloc_type = BFD_RELOC_SH_TLS_GD_32;
4303 else if ((next_end = sh_end_of_match (next + 1, "TLSLDM")))
4304 reloc_type = BFD_RELOC_SH_TLS_LD_32;
4305 else if ((next_end = sh_end_of_match (next + 1, "GOTTPOFF")))
4306 reloc_type = BFD_RELOC_SH_TLS_IE_32;
4307 else if ((next_end = sh_end_of_match (next + 1, "TPOFF")))
4308 reloc_type = BFD_RELOC_SH_TLS_LE_32;
4309 else if ((next_end = sh_end_of_match (next + 1, "DTPOFF")))
4310 reloc_type = BFD_RELOC_SH_TLS_LDO_32;
538cd60f
AO		 4311 else
4312 goto no_suffix;
4313
4314 *input_line_pointer = *nextcharP;
4315 input_line_pointer = next_end;
4316 *nextcharP = *input_line_pointer;
4317 *input_line_pointer = '\0';
4318
4319 exprP->X_op = O_PIC_reloc;
4320 exprP->X_add_number = 0;
4321 exprP->X_md = reloc_type;
4322
4323 return 1;
4324}
2ce4cc60
KK		 4325
4326void
4327sh_cfi_frame_initial_instructions (void)
4328{
4329 cfi_add_CFA_def_cfa (15, 0);
4330}
4331
4332int
4333sh_regname_to_dw2regnum (const char *regname)
4334{
4335 unsigned int regnum = -1;
4336 unsigned int i;
4337 const char *p;
4338 char *q;
4339 static struct { char *name; int dw2regnum; } regnames[] =
4340 {
4341 { "pr", 17 }, { "t", 18 }, { "gbr", 19 }, { "mach", 20 },
4342 { "macl", 21 }, { "fpul", 23 }
4343 };
4344
4345 for (i = 0; i < ARRAY_SIZE (regnames); ++i)
4346 if (strcmp (regnames[i].name, regname) == 0)
4347 return regnames[i].dw2regnum;
4348
4349 if (regname[0] == 'r')
4350 {
4351 p = regname + 1;
4352 regnum = strtoul (p, &q, 10);
4353 if (p == q || *q || regnum >= 16)
4354 return -1;
4355 }
4356 else if (regname[0] == 'f' && regname[1] == 'r')
4357 {
4358 p = regname + 2;
4359 regnum = strtoul (p, &q, 10);
4360 if (p == q || *q || regnum >= 16)
4361 return -1;
4362 regnum += 25;
4363 }
4364 else if (regname[0] == 'x' && regname[1] == 'd')
4365 {
4366 p = regname + 2;
4367 regnum = strtoul (p, &q, 10);
4368 if (p == q || *q || regnum >= 8)
4369 return -1;
4370 regnum += 87;
4371 }
4372 return regnum;
4373}
f17c130b 4374#endif /* OBJ_ELF */
GDB Binutils - Deliverables
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