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[deliverable/binutils-gdb.git] / gas / config / tc-sh.c
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ef230218 1/* tc-sh.c -- Assemble code for the Renesas / SuperH SH
4aa3e325 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
ebd1c875 3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
252b5132 21
6b31947e 22/* Written By Steve Chamberlain <sac@cygnus.com> */
252b5132 23
252b5132 24#include "as.h"
252b5132
RH		 25#include "subsegs.h"
26#define DEFINE_TABLE
27#include "opcodes/sh-opc.h"
3882b010 28#include "safe-ctype.h"
43841e91 29#include "struc-symbol.h"
d4845d57
JR		 30
31#ifdef OBJ_ELF
32#include "elf/sh.h"
33#endif
34
0d10e182 35#include "dwarf2dbg.h"
2ce4cc60 36#include "dw2gencfi.h"
0d10e182 37
e08ae979
HPN		 38typedef struct
39 {
40 sh_arg_type type;
41 int reg;
42 expressionS immediate;
43 }
44sh_operand_info;
45
252b5132
RH		 46const char comment_chars[] = "!";
47const char line_separator_chars[] = ";";
48const char line_comment_chars[] = "!#";
49
8edc77b9
KK		 50static void s_uses (int);
51static void s_uacons (int);
252b5132 52
a1cc9221 53#ifdef OBJ_ELF
8edc77b9 54static void sh_elf_cons (int);
538cd60f 55
a1cc9221
AO		 56symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
57#endif
58
05982cac 59static void
8edc77b9 60big (int ignore ATTRIBUTE_UNUSED)
05982cac
HPN		 61{
62 if (! target_big_endian)
63 as_bad (_("directive .big encountered when option -big required"));
64
65 /* Stop further messages. */
66 target_big_endian = 1;
67}
252b5132
RH		 68
69static void
8edc77b9 70little (int ignore ATTRIBUTE_UNUSED)
252b5132 71{
05982cac
HPN		 72 if (target_big_endian)
73 as_bad (_("directive .little encountered when option -little required"));
74
75 /* Stop further messages. */
252b5132
RH		 76 target_big_endian = 0;
77}
78
d4845d57
JR		 79/* This table describes all the machine specific pseudo-ops the assembler
80 has to support. The fields are:
81 pseudo-op name without dot
82 function to call to execute this pseudo-op
6b31947e 83 Integer arg to pass to the function. */
d4845d57 84
252b5132
RH		 85const pseudo_typeS md_pseudo_table[] =
86{
a1cc9221
AO		 87#ifdef OBJ_ELF
88 {"long", sh_elf_cons, 4},
89 {"int", sh_elf_cons, 4},
90 {"word", sh_elf_cons, 2},
91 {"short", sh_elf_cons, 2},
92#else
252b5132
RH		 93 {"int", cons, 4},
94 {"word", cons, 2},
a1cc9221 95#endif /* OBJ_ELF */
05982cac 96 {"big", big, 0},
252b5132
RH		 97 {"form", listing_psize, 0},
98 {"little", little, 0},
99 {"heading", listing_title, 0},
100 {"import", s_ignore, 0},
101 {"page", listing_eject, 0},
102 {"program", s_ignore, 0},
103 {"uses", s_uses, 0},
104 {"uaword", s_uacons, 2},
105 {"ualong", s_uacons, 4},
de68de20
AO		 106 {"uaquad", s_uacons, 8},
107 {"2byte", s_uacons, 2},
108 {"4byte", s_uacons, 4},
109 {"8byte", s_uacons, 8},
324bfcf3
AO		 110#ifdef HAVE_SH64
111 {"mode", s_sh64_mode, 0 },
112
113 /* Have the old name too. */
114 {"isa", s_sh64_mode, 0 },
115
116 /* Assert that the right ABI is used. */
117 {"abi", s_sh64_abi, 0 },
118
119 { "vtable_inherit", sh64_vtable_inherit, 0 },
120 { "vtable_entry", sh64_vtable_entry, 0 },
121#endif /* HAVE_SH64 */
252b5132
RH		 122 {0, 0, 0}
123};
124
252b5132
RH		 125int sh_relax; /* set if -relax seen */
126
127/* Whether -small was seen. */
128
129int sh_small;
130
f55629b8
KK		 131/* Flag to generate relocations against symbol values for local symbols. */
132
133static int dont_adjust_reloc_32;
134
37dedf66
NC		 135/* Flag to indicate that '$' is allowed as a register prefix. */
136
137static int allow_dollar_register_prefix;
138
139/* Preset architecture set, if given; zero otherwise. */
d4845d57 140
f6f9408f 141static unsigned int preset_target_arch;
d4845d57
JR		 142
143/* The bit mask of architectures that could
67c1ffbe 144 accommodate the insns seen so far. */
f6f9408f 145static unsigned int valid_arch;
d4845d57 146
252b5132
RH		 147const char EXP_CHARS[] = "eE";
148
6b31947e 149/* Chars that mean this number is a floating point constant. */
252b5132
RH		 150/* As in 0f12.456 */
151/* or 0d1.2345e12 */
152const char FLT_CHARS[] = "rRsSfFdDxXpP";
153
154#define C(a,b) ENCODE_RELAX(a,b)
155
252b5132
RH		 156#define ENCODE_RELAX(what,length) (((what) << 4) + (length))
157#define GET_WHAT(x) ((x>>4))
158
67c1ffbe 159/* These are the three types of relaxable instruction. */
324bfcf3
AO		 160/* These are the types of relaxable instructions; except for END which is
161 a marker. */
252b5132
RH		 162#define COND_JUMP 1
163#define COND_JUMP_DELAY 2
164#define UNCOND_JUMP 3
324bfcf3
AO		 165
166#ifdef HAVE_SH64
167
168/* A 16-bit (times four) pc-relative operand, at most expanded to 32 bits. */
169#define SH64PCREL16_32 4
170/* A 16-bit (times four) pc-relative operand, at most expanded to 64 bits. */
171#define SH64PCREL16_64 5
172
173/* Variants of the above for adjusting the insn to PTA or PTB according to
174 the label. */
175#define SH64PCREL16PT_32 6
176#define SH64PCREL16PT_64 7
177
178/* A MOVI expansion, expanding to at most 32 or 64 bits. */
179#define MOVI_IMM_32 8
180#define MOVI_IMM_32_PCREL 9
181#define MOVI_IMM_64 10
182#define MOVI_IMM_64_PCREL 11
183#define END 12
184
185#else /* HAVE_SH64 */
186
252b5132
RH		 187#define END 4
188
324bfcf3
AO		 189#endif /* HAVE_SH64 */
190
252b5132
RH		 191#define UNDEF_DISP 0
192#define COND8 1
193#define COND12 2
194#define COND32 3
252b5132
RH		 195#define UNDEF_WORD_DISP 4
196
197#define UNCOND12 1
198#define UNCOND32 2
199
324bfcf3
AO		 200#ifdef HAVE_SH64
201#define UNDEF_SH64PCREL 0
202#define SH64PCREL16 1
203#define SH64PCREL32 2
204#define SH64PCREL48 3
205#define SH64PCREL64 4
206#define SH64PCRELPLT 5
207
208#define UNDEF_MOVI 0
209#define MOVI_16 1
210#define MOVI_32 2
211#define MOVI_48 3
212#define MOVI_64 4
213#define MOVI_PLT 5
214#define MOVI_GOTOFF 6
215#define MOVI_GOTPC 7
216#endif /* HAVE_SH64 */
217
252b5132
RH		 218/* Branch displacements are from the address of the branch plus
219 four, thus all minimum and maximum values have 4 added to them. */
220#define COND8_F 258
221#define COND8_M -252
222#define COND8_LENGTH 2
223
224/* There is one extra instruction before the branch, so we must add
225 two more bytes to account for it. */
226#define COND12_F 4100
227#define COND12_M -4090
228#define COND12_LENGTH 6
229
230#define COND12_DELAY_LENGTH 4
231
232/* ??? The minimum and maximum values are wrong, but this does not matter
233 since this relocation type is not supported yet. */
234#define COND32_F (1<<30)
235#define COND32_M -(1<<30)
236#define COND32_LENGTH 14
237
238#define UNCOND12_F 4098
239#define UNCOND12_M -4092
240#define UNCOND12_LENGTH 2
241
242/* ??? The minimum and maximum values are wrong, but this does not matter
243 since this relocation type is not supported yet. */
244#define UNCOND32_F (1<<30)
245#define UNCOND32_M -(1<<30)
246#define UNCOND32_LENGTH 14
247
324bfcf3
AO		 248#ifdef HAVE_SH64
249/* The trivial expansion of a SH64PCREL16 relaxation is just a "PT label,
250 TRd" as is the current insn, so no extra length. Note that the "reach"
251 is calculated from the address *after* that insn, but the offset in the
252 insn is calculated from the beginning of the insn. We also need to
253 take into account the implicit 1 coded as the "A" in PTA when counting
254 forward. If PTB reaches an odd address, we trap that as an error
255 elsewhere, so we don't have to have different relaxation entries. We
256 don't add a one to the negative range, since PTB would then have the
257 farthest backward-reaching value skipped, not generated at relaxation. */
258#define SH64PCREL16_F (32767 * 4 - 4 + 1)
259#define SH64PCREL16_M (-32768 * 4 - 4)
260#define SH64PCREL16_LENGTH 0
261
262/* The next step is to change that PT insn into
263 MOVI ((label - datalabel Ln) >> 16) & 65535, R25
264 SHORI (label - datalabel Ln) & 65535, R25
265 Ln:
266 PTREL R25,TRd
267 which means two extra insns, 8 extra bytes. This is the limit for the
268 32-bit ABI.
269
270 The expressions look a bit bad since we have to adjust this to avoid overflow on a
271 32-bit host. */
272#define SH64PCREL32_F ((((long) 1 << 30) - 1) * 2 + 1 - 4)
273#define SH64PCREL32_LENGTH (2 * 4)
274
275/* Similarly, we just change the MOVI and add a SHORI for the 48-bit
276 expansion. */
277#if BFD_HOST_64BIT_LONG
278/* The "reach" type is long, so we can only do this for a 64-bit-long
279 host. */
280#define SH64PCREL32_M (((long) -1 << 30) * 2 - 4)
281#define SH64PCREL48_F ((((long) 1 << 47) - 1) - 4)
282#define SH64PCREL48_M (((long) -1 << 47) - 4)
283#define SH64PCREL48_LENGTH (3 * 4)
284#else
285/* If the host does not have 64-bit longs, just make this state identical
286 in reach to the 32-bit state. Note that we have a slightly incorrect
287 reach, but the correct one above will overflow a 32-bit number. */
288#define SH64PCREL32_M (((long) -1 << 30) * 2)
289#define SH64PCREL48_F SH64PCREL32_F
290#define SH64PCREL48_M SH64PCREL32_M
291#define SH64PCREL48_LENGTH (3 * 4)
292#endif /* BFD_HOST_64BIT_LONG */
293
294/* And similarly for the 64-bit expansion; a MOVI + SHORI + SHORI + SHORI
295 + PTREL sequence. */
296#define SH64PCREL64_LENGTH (4 * 4)
297
298/* For MOVI, we make the MOVI + SHORI... expansion you can see in the
299 SH64PCREL expansions. The PCREL one is similar, but the other has no
300 pc-relative reach; it must be fully expanded in
301 shmedia_md_estimate_size_before_relax. */
302#define MOVI_16_LENGTH 0
303#define MOVI_16_F (32767 - 4)
304#define MOVI_16_M (-32768 - 4)
305#define MOVI_32_LENGTH 4
306#define MOVI_32_F ((((long) 1 << 30) - 1) * 2 + 1 - 4)
307#define MOVI_48_LENGTH 8
308
309#if BFD_HOST_64BIT_LONG
310/* The "reach" type is long, so we can only do this for a 64-bit-long
311 host. */
312#define MOVI_32_M (((long) -1 << 30) * 2 - 4)
313#define MOVI_48_F ((((long) 1 << 47) - 1) - 4)
314#define MOVI_48_M (((long) -1 << 47) - 4)
315#else
316/* If the host does not have 64-bit longs, just make this state identical
317 in reach to the 32-bit state. Note that we have a slightly incorrect
318 reach, but the correct one above will overflow a 32-bit number. */
319#define MOVI_32_M (((long) -1 << 30) * 2)
320#define MOVI_48_F MOVI_32_F
321#define MOVI_48_M MOVI_32_M
322#endif /* BFD_HOST_64BIT_LONG */
323
324#define MOVI_64_LENGTH 12
325#endif /* HAVE_SH64 */
326
43841e91
NC		 327#define EMPTY { 0, 0, 0, 0 }
328
252b5132 329const relax_typeS md_relax_table[C (END, 0)] = {
43841e91
NC		 330 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
331 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 332
43841e91 333 EMPTY,
252b5132
RH		 334 /* C (COND_JUMP, COND8) */
335 { COND8_F, COND8_M, COND8_LENGTH, C (COND_JUMP, COND12) },
336 /* C (COND_JUMP, COND12) */
337 { COND12_F, COND12_M, COND12_LENGTH, C (COND_JUMP, COND32), },
338 /* C (COND_JUMP, COND32) */
339 { COND32_F, COND32_M, COND32_LENGTH, 0, },
e66457fb
AM		 340 /* C (COND_JUMP, UNDEF_WORD_DISP) */
341 { 0, 0, COND32_LENGTH, 0, },
342 EMPTY, EMPTY, EMPTY,
43841e91 343 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 344
43841e91 345 EMPTY,
252b5132
RH		 346 /* C (COND_JUMP_DELAY, COND8) */
347 { COND8_F, COND8_M, COND8_LENGTH, C (COND_JUMP_DELAY, COND12) },
348 /* C (COND_JUMP_DELAY, COND12) */
349 { COND12_F, COND12_M, COND12_DELAY_LENGTH, C (COND_JUMP_DELAY, COND32), },
350 /* C (COND_JUMP_DELAY, COND32) */
351 { COND32_F, COND32_M, COND32_LENGTH, 0, },
e66457fb
AM		 352 /* C (COND_JUMP_DELAY, UNDEF_WORD_DISP) */
353 { 0, 0, COND32_LENGTH, 0, },
354 EMPTY, EMPTY, EMPTY,
43841e91 355 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
252b5132 356
43841e91 357 EMPTY,
252b5132
RH		 358 /* C (UNCOND_JUMP, UNCOND12) */
359 { UNCOND12_F, UNCOND12_M, UNCOND12_LENGTH, C (UNCOND_JUMP, UNCOND32), },
360 /* C (UNCOND_JUMP, UNCOND32) */
361 { UNCOND32_F, UNCOND32_M, UNCOND32_LENGTH, 0, },
e66457fb
AM		 362 EMPTY,
363 /* C (UNCOND_JUMP, UNDEF_WORD_DISP) */
364 { 0, 0, UNCOND32_LENGTH, 0, },
365 EMPTY, EMPTY, EMPTY,
43841e91 366 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
324bfcf3
AO		 367
368#ifdef HAVE_SH64
369 /* C (SH64PCREL16_32, SH64PCREL16) */
370 EMPTY,
371 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16_32, SH64PCREL32) },
372 /* C (SH64PCREL16_32, SH64PCREL32) */
373 { 0, 0, SH64PCREL32_LENGTH, 0 },
374 EMPTY, EMPTY,
375 /* C (SH64PCREL16_32, SH64PCRELPLT) */
376 { 0, 0, SH64PCREL32_LENGTH, 0 },
377 EMPTY, EMPTY,
378 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
379
380 /* C (SH64PCREL16_64, SH64PCREL16) */
381 EMPTY,
382 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16_64, SH64PCREL32) },
383 /* C (SH64PCREL16_64, SH64PCREL32) */
384 { SH64PCREL32_F, SH64PCREL32_M, SH64PCREL32_LENGTH, C (SH64PCREL16_64, SH64PCREL48) },
385 /* C (SH64PCREL16_64, SH64PCREL48) */
386 { SH64PCREL48_F, SH64PCREL48_M, SH64PCREL48_LENGTH, C (SH64PCREL16_64, SH64PCREL64) },
387 /* C (SH64PCREL16_64, SH64PCREL64) */
388 { 0, 0, SH64PCREL64_LENGTH, 0 },
389 /* C (SH64PCREL16_64, SH64PCRELPLT) */
390 { 0, 0, SH64PCREL64_LENGTH, 0 },
391 EMPTY, EMPTY,
392 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
393
394 /* C (SH64PCREL16PT_32, SH64PCREL16) */
395 EMPTY,
396 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16PT_32, SH64PCREL32) },
397 /* C (SH64PCREL16PT_32, SH64PCREL32) */
398 { 0, 0, SH64PCREL32_LENGTH, 0 },
399 EMPTY, EMPTY,
400 /* C (SH64PCREL16PT_32, SH64PCRELPLT) */
401 { 0, 0, SH64PCREL32_LENGTH, 0 },
402 EMPTY, EMPTY,
403 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
404
405 /* C (SH64PCREL16PT_64, SH64PCREL16) */
406 EMPTY,
407 { SH64PCREL16_F, SH64PCREL16_M, SH64PCREL16_LENGTH, C (SH64PCREL16PT_64, SH64PCREL32) },
408 /* C (SH64PCREL16PT_64, SH64PCREL32) */
409 { SH64PCREL32_F,
5d6255fe 410 SH64PCREL32_M,
324bfcf3
AO		 411 SH64PCREL32_LENGTH,
412 C (SH64PCREL16PT_64, SH64PCREL48) },
413 /* C (SH64PCREL16PT_64, SH64PCREL48) */
414 { SH64PCREL48_F, SH64PCREL48_M, SH64PCREL48_LENGTH, C (SH64PCREL16PT_64, SH64PCREL64) },
415 /* C (SH64PCREL16PT_64, SH64PCREL64) */
416 { 0, 0, SH64PCREL64_LENGTH, 0 },
417 /* C (SH64PCREL16PT_64, SH64PCRELPLT) */
418 { 0, 0, SH64PCREL64_LENGTH, 0},
419 EMPTY, EMPTY,
420 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
421
422 /* C (MOVI_IMM_32, UNDEF_MOVI) */
423 { 0, 0, MOVI_32_LENGTH, 0 },
424 /* C (MOVI_IMM_32, MOVI_16) */
425 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_32, MOVI_32) },
426 /* C (MOVI_IMM_32, MOVI_32) */
427 { MOVI_32_F, MOVI_32_M, MOVI_32_LENGTH, 0 },
428 EMPTY, EMPTY, EMPTY,
429 /* C (MOVI_IMM_32, MOVI_GOTOFF) */
430 { 0, 0, MOVI_32_LENGTH, 0 },
431 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
432
433 /* C (MOVI_IMM_32_PCREL, MOVI_16) */
434 EMPTY,
435 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_32_PCREL, MOVI_32) },
436 /* C (MOVI_IMM_32_PCREL, MOVI_32) */
437 { 0, 0, MOVI_32_LENGTH, 0 },
438 EMPTY, EMPTY,
439 /* C (MOVI_IMM_32_PCREL, MOVI_PLT) */
440 { 0, 0, MOVI_32_LENGTH, 0 },
441 EMPTY,
442 /* C (MOVI_IMM_32_PCREL, MOVI_GOTPC) */
443 { 0, 0, MOVI_32_LENGTH, 0 },
444 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
445
446 /* C (MOVI_IMM_64, UNDEF_MOVI) */
447 { 0, 0, MOVI_64_LENGTH, 0 },
448 /* C (MOVI_IMM_64, MOVI_16) */
449 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_64, MOVI_32) },
450 /* C (MOVI_IMM_64, MOVI_32) */
451 { MOVI_32_F, MOVI_32_M, MOVI_32_LENGTH, C (MOVI_IMM_64, MOVI_48) },
452 /* C (MOVI_IMM_64, MOVI_48) */
453 { MOVI_48_F, MOVI_48_M, MOVI_48_LENGTH, C (MOVI_IMM_64, MOVI_64) },
454 /* C (MOVI_IMM_64, MOVI_64) */
455 { 0, 0, MOVI_64_LENGTH, 0 },
456 EMPTY,
457 /* C (MOVI_IMM_64, MOVI_GOTOFF) */
458 { 0, 0, MOVI_64_LENGTH, 0 },
459 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
460
461 /* C (MOVI_IMM_64_PCREL, MOVI_16) */
462 EMPTY,
463 { MOVI_16_F, MOVI_16_M, MOVI_16_LENGTH, C (MOVI_IMM_64_PCREL, MOVI_32) },
464 /* C (MOVI_IMM_64_PCREL, MOVI_32) */
465 { MOVI_32_F, MOVI_32_M, MOVI_32_LENGTH, C (MOVI_IMM_64_PCREL, MOVI_48) },
466 /* C (MOVI_IMM_64_PCREL, MOVI_48) */
467 { MOVI_48_F, MOVI_48_M, MOVI_48_LENGTH, C (MOVI_IMM_64_PCREL, MOVI_64) },
468 /* C (MOVI_IMM_64_PCREL, MOVI_64) */
469 { 0, 0, MOVI_64_LENGTH, 0 },
470 /* C (MOVI_IMM_64_PCREL, MOVI_PLT) */
471 { 0, 0, MOVI_64_LENGTH, 0 },
472 EMPTY,
473 /* C (MOVI_IMM_64_PCREL, MOVI_GOTPC) */
474 { 0, 0, MOVI_64_LENGTH, 0 },
475 EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
476
477#endif /* HAVE_SH64 */
478
252b5132
RH		 479};
480
43841e91
NC		 481#undef EMPTY
482
252b5132
RH		 483static struct hash_control *opcode_hash_control; /* Opcode mnemonics */
484
a1cc9221
AO		 485\f
486#ifdef OBJ_ELF
538cd60f
AO		 487/* Determinet whether the symbol needs any kind of PIC relocation. */
488
489inline static int
8edc77b9 490sh_PIC_related_p (symbolS *sym)
a1cc9221 491{
538cd60f 492 expressionS *exp;
a1cc9221 493
538cd60f
AO		 494 if (! sym)
495 return 0;
496
497 if (sym == GOT_symbol)
498 return 1;
499
324bfcf3
AO		 500#ifdef HAVE_SH64
501 if (sh_PIC_related_p (*symbol_get_tc (sym)))
502 return 1;
503#endif
504
538cd60f
AO		 505 exp = symbol_get_value_expression (sym);
506
507 return (exp->X_op == O_PIC_reloc
508 || sh_PIC_related_p (exp->X_add_symbol)
509 || sh_PIC_related_p (exp->X_op_symbol));
510}
511
512/* Determine the relocation type to be used to represent the
513 expression, that may be rearranged. */
514
515static int
8edc77b9 516sh_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
538cd60f
AO		 517{
518 expressionS *exp = main_exp;
519
520 /* This is here for backward-compatibility only. GCC used to generated:
521
522 f@PLT + . - (.LPCS# + 2)
523
524 but we'd rather be able to handle this as a PIC-related reference
525 plus/minus a symbol. However, gas' parser gives us:
526
527 O_subtract (O_add (f@PLT, .), .LPCS#+2)
5d6255fe 528
538cd60f
AO		 529 so we attempt to transform this into:
530
531 O_subtract (f@PLT, O_subtract (.LPCS#+2, .))
532
5d6255fe 533 which we can handle simply below. */
538cd60f
AO		 534 if (exp->X_op == O_subtract)
535 {
536 if (sh_PIC_related_p (exp->X_op_symbol))
537 return 1;
538
539 exp = symbol_get_value_expression (exp->X_add_symbol);
540
541 if (exp && sh_PIC_related_p (exp->X_op_symbol))
542 return 1;
543
544 if (exp && exp->X_op == O_add
545 && sh_PIC_related_p (exp->X_add_symbol))
546 {
547 symbolS *sym = exp->X_add_symbol;
548
549 exp->X_op = O_subtract;
550 exp->X_add_symbol = main_exp->X_op_symbol;
551
552 main_exp->X_op_symbol = main_exp->X_add_symbol;
553 main_exp->X_add_symbol = sym;
554
555 main_exp->X_add_number += exp->X_add_number;
556 exp->X_add_number = 0;
557 }
558
559 exp = main_exp;
560 }
561 else if (exp->X_op == O_add && sh_PIC_related_p (exp->X_op_symbol))
562 return 1;
563
564 if (exp->X_op == O_symbol || exp->X_op == O_add || exp->X_op == O_subtract)
565 {
324bfcf3
AO		 566#ifdef HAVE_SH64
567 if (exp->X_add_symbol
568 && (exp->X_add_symbol == GOT_symbol
569 || (GOT_symbol
570 && *symbol_get_tc (exp->X_add_symbol) == GOT_symbol)))
571 {
572 switch (*r_type_p)
573 {
574 case BFD_RELOC_SH_IMM_LOW16:
575 *r_type_p = BFD_RELOC_SH_GOTPC_LOW16;
576 break;
577
578 case BFD_RELOC_SH_IMM_MEDLOW16:
579 *r_type_p = BFD_RELOC_SH_GOTPC_MEDLOW16;
580 break;
581
582 case BFD_RELOC_SH_IMM_MEDHI16:
583 *r_type_p = BFD_RELOC_SH_GOTPC_MEDHI16;
584 break;
585
586 case BFD_RELOC_SH_IMM_HI16:
587 *r_type_p = BFD_RELOC_SH_GOTPC_HI16;
588 break;
589
590 case BFD_RELOC_NONE:
591 case BFD_RELOC_UNUSED:
592 *r_type_p = BFD_RELOC_SH_GOTPC;
593 break;
5d6255fe 594
324bfcf3
AO		 595 default:
596 abort ();
597 }
598 return 0;
599 }
600#else
538cd60f
AO		 601 if (exp->X_add_symbol && exp->X_add_symbol == GOT_symbol)
602 {
603 *r_type_p = BFD_RELOC_SH_GOTPC;
604 return 0;
605 }
324bfcf3 606#endif
538cd60f
AO		 607 exp = symbol_get_value_expression (exp->X_add_symbol);
608 if (! exp)
609 return 0;
610 }
611
612 if (exp->X_op == O_PIC_reloc)
613 {
324bfcf3
AO		 614#ifdef HAVE_SH64
615 switch (*r_type_p)
616 {
617 case BFD_RELOC_NONE:
618 case BFD_RELOC_UNUSED:
619 *r_type_p = exp->X_md;
620 break;
621
622 case BFD_RELOC_SH_IMM_LOW16:
623 switch (exp->X_md)
624 {
625 case BFD_RELOC_32_GOTOFF:
626 *r_type_p = BFD_RELOC_SH_GOTOFF_LOW16;
627 break;
5d6255fe 628
324bfcf3
AO		 629 case BFD_RELOC_SH_GOTPLT32:
630 *r_type_p = BFD_RELOC_SH_GOTPLT_LOW16;
631 break;
5d6255fe 632
324bfcf3
AO		 633 case BFD_RELOC_32_GOT_PCREL:
634 *r_type_p = BFD_RELOC_SH_GOT_LOW16;
635 break;
5d6255fe 636
324bfcf3
AO		 637 case BFD_RELOC_32_PLT_PCREL:
638 *r_type_p = BFD_RELOC_SH_PLT_LOW16;
639 break;
640
641 default:
642 abort ();
643 }
644 break;
645
646 case BFD_RELOC_SH_IMM_MEDLOW16:
647 switch (exp->X_md)
648 {
649 case BFD_RELOC_32_GOTOFF:
650 *r_type_p = BFD_RELOC_SH_GOTOFF_MEDLOW16;
651 break;
5d6255fe 652
324bfcf3
AO		 653 case BFD_RELOC_SH_GOTPLT32:
654 *r_type_p = BFD_RELOC_SH_GOTPLT_MEDLOW16;
655 break;
5d6255fe 656
324bfcf3
AO		 657 case BFD_RELOC_32_GOT_PCREL:
658 *r_type_p = BFD_RELOC_SH_GOT_MEDLOW16;
659 break;
5d6255fe 660
324bfcf3
AO		 661 case BFD_RELOC_32_PLT_PCREL:
662 *r_type_p = BFD_RELOC_SH_PLT_MEDLOW16;
663 break;
664
665 default:
666 abort ();
667 }
668 break;
669
670 case BFD_RELOC_SH_IMM_MEDHI16:
671 switch (exp->X_md)
672 {
673 case BFD_RELOC_32_GOTOFF:
674 *r_type_p = BFD_RELOC_SH_GOTOFF_MEDHI16;
675 break;
5d6255fe 676
324bfcf3
AO		 677 case BFD_RELOC_SH_GOTPLT32:
678 *r_type_p = BFD_RELOC_SH_GOTPLT_MEDHI16;
679 break;
5d6255fe 680
324bfcf3
AO		 681 case BFD_RELOC_32_GOT_PCREL:
682 *r_type_p = BFD_RELOC_SH_GOT_MEDHI16;
683 break;
5d6255fe 684
324bfcf3
AO		 685 case BFD_RELOC_32_PLT_PCREL:
686 *r_type_p = BFD_RELOC_SH_PLT_MEDHI16;
687 break;
688
689 default:
690 abort ();
691 }
692 break;
693
694 case BFD_RELOC_SH_IMM_HI16:
695 switch (exp->X_md)
696 {
697 case BFD_RELOC_32_GOTOFF:
698 *r_type_p = BFD_RELOC_SH_GOTOFF_HI16;
699 break;
5d6255fe 700
324bfcf3
AO		 701 case BFD_RELOC_SH_GOTPLT32:
702 *r_type_p = BFD_RELOC_SH_GOTPLT_HI16;
703 break;
5d6255fe 704
324bfcf3
AO		 705 case BFD_RELOC_32_GOT_PCREL:
706 *r_type_p = BFD_RELOC_SH_GOT_HI16;
707 break;
5d6255fe 708
324bfcf3
AO		 709 case BFD_RELOC_32_PLT_PCREL:
710 *r_type_p = BFD_RELOC_SH_PLT_HI16;
711 break;
712
713 default:
714 abort ();
715 }
716 break;
717
718 default:
719 abort ();
720 }
721#else
538cd60f 722 *r_type_p = exp->X_md;
324bfcf3 723#endif
538cd60f
AO		 724 if (exp == main_exp)
725 exp->X_op = O_symbol;
726 else
727 {
728 main_exp->X_add_symbol = exp->X_add_symbol;
729 main_exp->X_add_number += exp->X_add_number;
730 }
731 }
732 else
733 return (sh_PIC_related_p (exp->X_add_symbol)
734 || sh_PIC_related_p (exp->X_op_symbol));
735
736 return 0;
737}
738
739/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
740
741void
8edc77b9 742sh_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
538cd60f
AO		 743{
744 bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
745
746 if (sh_check_fixup (exp, &r_type))
747 as_bad (_("Invalid PIC expression."));
748
749 if (r_type == BFD_RELOC_UNUSED)
750 switch (size)
a1cc9221 751 {
538cd60f
AO		 752 case 1:
753 r_type = BFD_RELOC_8;
754 break;
a1cc9221 755
538cd60f
AO		 756 case 2:
757 r_type = BFD_RELOC_16;
758 break;
759
760 case 4:
761 r_type = BFD_RELOC_32;
762 break;
a1cc9221 763
324bfcf3
AO		 764#ifdef HAVE_SH64
765 case 8:
766 r_type = BFD_RELOC_64;
767 break;
768#endif
769
538cd60f
AO		 770 default:
771 goto error;
772 }
773 else if (size != 4)
774 {
775 error:
776 as_bad (_("unsupported BFD relocation size %u"), size);
777 r_type = BFD_RELOC_UNUSED;
778 }
5d6255fe 779
538cd60f 780 fix_new_exp (frag, off, size, exp, 0, r_type);
a1cc9221
AO		 781}
782
783/* The regular cons() function, that reads constants, doesn't support
784 suffixes such as @GOT, @GOTOFF and @PLT, that generate
785 machine-specific relocation types. So we must define it here. */
786/* Clobbers input_line_pointer, checks end-of-line. */
8edc77b9 787/* NBYTES 1=.byte, 2=.word, 4=.long */
a1cc9221 788static void
8edc77b9 789sh_elf_cons (register int nbytes)
a1cc9221 790{
538cd60f 791 expressionS exp;
a1cc9221 792
324bfcf3
AO		 793#ifdef HAVE_SH64
794
795 /* Update existing range to include a previous insn, if there was one. */
b34976b6 796 sh64_update_contents_mark (TRUE);
324bfcf3
AO		 797
798 /* We need to make sure the contents type is set to data. */
799 sh64_flag_output ();
800
801#endif /* HAVE_SH64 */
802
a1cc9221
AO		 803 if (is_it_end_of_statement ())
804 {
805 demand_empty_rest_of_line ();
806 return;
807 }
808
028f09bd
NC		 809#ifdef md_cons_align
810 md_cons_align (nbytes);
811#endif
812
a1cc9221
AO		 813 do
814 {
815 expression (&exp);
538cd60f 816 emit_expr (&exp, (unsigned int) nbytes);
a1cc9221
AO		 817 }
818 while (*input_line_pointer++ == ',');
819
81d4177b 820 input_line_pointer--; /* Put terminator back into stream. */
a1cc9221
AO		 821 if (*input_line_pointer == '#' || *input_line_pointer == '!')
822 {
dda5ecfc 823 while (! is_end_of_line[(unsigned char) *input_line_pointer++]);
a1cc9221
AO		 824 }
825 else
826 demand_empty_rest_of_line ();
827}
0cc34095
KK		 828
829/* The regular frag_offset_fixed_p doesn't work for rs_align_test
830 frags. */
831
832static bfd_boolean
833align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
834 bfd_vma *offset)
835{
836 const fragS *frag;
837 bfd_vma off;
838
839 /* Start with offset initialised to difference between the two frags.
840 Prior to assigning frag addresses this will be zero. */
841 off = frag1->fr_address - frag2->fr_address;
842 if (frag1 == frag2)
843 {
844 *offset = off;
845 return TRUE;
846 }
847
848 /* Maybe frag2 is after frag1. */
849 frag = frag1;
850 while (frag->fr_type == rs_align_test)
851 {
852 off += frag->fr_fix;
853 frag = frag->fr_next;
854 if (frag == NULL)
855 break;
856 if (frag == frag2)
857 {
858 *offset = off;
859 return TRUE;
860 }
861 }
862
863 /* Maybe frag1 is after frag2. */
864 off = frag1->fr_address - frag2->fr_address;
865 frag = frag2;
866 while (frag->fr_type == rs_align_test)
867 {
868 off -= frag->fr_fix;
869 frag = frag->fr_next;
870 if (frag == NULL)
871 break;
872 if (frag == frag1)
873 {
874 *offset = off;
875 return TRUE;
876 }
877 }
878
879 return FALSE;
880}
a1cc9221
AO		 881#endif /* OBJ_ELF */
882
0cc34095
KK		 883/* Optimize a difference of symbols which have rs_align_test frag if
884 possible. */
885
886int
887sh_optimize_expr (expressionS *l, operatorT op, expressionS *r)
888{
889#ifdef OBJ_ELF
890 bfd_vma frag_off;
891
892 if (op == O_subtract
893 && l->X_op == O_symbol
894 && r->X_op == O_symbol
895 && S_GET_SEGMENT (l->X_add_symbol) == S_GET_SEGMENT (r->X_add_symbol)
896 && (SEG_NORMAL (S_GET_SEGMENT (l->X_add_symbol))
897 || r->X_add_symbol == l->X_add_symbol)
898 && align_test_frag_offset_fixed_p (symbol_get_frag (l->X_add_symbol),
899 symbol_get_frag (r->X_add_symbol),
900 &frag_off))
901 {
902 l->X_add_number -= r->X_add_number;
903 l->X_add_number -= frag_off / OCTETS_PER_BYTE;
904 l->X_add_number += (S_GET_VALUE (l->X_add_symbol)
905 - S_GET_VALUE (r->X_add_symbol));
906 l->X_op = O_constant;
907 l->X_add_symbol = 0;
908 return 1;
909 }
910#endif /* OBJ_ELF */
911 return 0;
912}
a1cc9221 913\f
6b31947e
NC		 914/* This function is called once, at assembler startup time. This should
915 set up all the tables, etc that the MD part of the assembler needs. */
252b5132
RH		 916
917void
8edc77b9 918md_begin (void)
252b5132 919{
5ff37431 920 const sh_opcode_info *opcode;
252b5132 921 char *prev_name = "";
f6f9408f 922 unsigned int target_arch;
252b5132 923
bdfaef52 924 target_arch
e38bc3b5 925 = preset_target_arch ? preset_target_arch : arch_sh_up & ~arch_sh_has_dsp;
d4845d57
JR		 926 valid_arch = target_arch;
927
324bfcf3
AO		 928#ifdef HAVE_SH64
929 shmedia_md_begin ();
930#endif
931
252b5132
RH		 932 opcode_hash_control = hash_new ();
933
6b31947e 934 /* Insert unique names into hash table. */
252b5132
RH		 935 for (opcode = sh_table; opcode->name; opcode++)
936 {
5ff37431 937 if (strcmp (prev_name, opcode->name) != 0)
252b5132 938 {
f6f9408f 939 if (!SH_MERGE_ARCH_SET_VALID (opcode->arch, target_arch))
a37c8f88 940 continue;
252b5132
RH		 941 prev_name = opcode->name;
942 hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
943 }
252b5132
RH		 944 }
945}
946
947static int reg_m;
948static int reg_n;
d4845d57
JR		 949static int reg_x, reg_y;
950static int reg_efg;
252b5132
RH		 951static int reg_b;
952
3882b010 953#define IDENT_CHAR(c) (ISALNUM (c) || (c) == '_')
dead1419 954
6b31947e
NC		 955/* Try to parse a reg name. Return the number of chars consumed. */
956
37dedf66
NC		 957static unsigned int
958parse_reg_without_prefix (char *src, int *mode, int *reg)
252b5132 959{
3882b010
L		 960 char l0 = TOLOWER (src[0]);
961 char l1 = l0 ? TOLOWER (src[1]) : 0;
e46fee70 962
dead1419 963 /* We use ! IDENT_CHAR for the next character after the register name, to
252b5132 964 make sure that we won't accidentally recognize a symbol name such as
dead1419 965 'sram' or sr_ram as being a reference to the register 'sr'. */
252b5132 966
e46fee70 967 if (l0 == 'r')
252b5132 968 {
e46fee70 969 if (l1 == '1')
d4845d57
JR		 970 {
971 if (src[2] >= '0' && src[2] <= '5'
dead1419 972 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 973 {
974 *mode = A_REG_N;
975 *reg = 10 + src[2] - '0';
976 return 3;
977 }
978 }
e46fee70 979 if (l1 >= '0' && l1 <= '9'
dead1419 980 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 981 {
982 *mode = A_REG_N;
e46fee70 983 *reg = (l1 - '0');
d4845d57
JR		 984 return 2;
985 }
e46fee70 986 if (l1 >= '0' && l1 <= '7' && strncasecmp (&src[2], "_bank", 5) == 0
dead1419
JR		 987 && ! IDENT_CHAR ((unsigned char) src[7]))
988 {
989 *mode = A_REG_B;
e46fee70 990 *reg = (l1 - '0');
dead1419
JR		 991 return 7;
992 }
d4845d57 993
e46fee70 994 if (l1 == 'e' && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 995 {
996 *mode = A_RE;
997 return 2;
998 }
e46fee70 999 if (l1 == 's' && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1000 {
1001 *mode = A_RS;
1002 return 2;
1003 }
252b5132
RH		 1004 }
1005
e46fee70 1006 if (l0 == 'a')
252b5132 1007 {
e46fee70 1008 if (l1 == '0')
d4845d57 1009 {
dead1419 1010 if (! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1011 {
1012 *mode = DSP_REG_N;
1013 *reg = A_A0_NUM;
1014 return 2;
1015 }
3882b010 1016 if (TOLOWER (src[2]) == 'g' && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1017 {
1018 *mode = DSP_REG_N;
1019 *reg = A_A0G_NUM;
1020 return 3;
1021 }
1022 }
e46fee70 1023 if (l1 == '1')
252b5132 1024 {
dead1419 1025 if (! IDENT_CHAR ((unsigned char) src[2]))
252b5132 1026 {
d4845d57
JR		 1027 *mode = DSP_REG_N;
1028 *reg = A_A1_NUM;
1029 return 2;
1030 }
3882b010 1031 if (TOLOWER (src[2]) == 'g' && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1032 {
1033 *mode = DSP_REG_N;
1034 *reg = A_A1G_NUM;
252b5132
RH		 1035 return 3;
1036 }
1037 }
d4845d57 1038
e46fee70 1039 if (l1 == 'x' && src[2] >= '0' && src[2] <= '1'
dead1419 1040 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1041 {
1042 *mode = A_REG_N;
e46fee70 1043 *reg = 4 + (l1 - '0');
d4845d57
JR		 1044 return 3;
1045 }
e46fee70 1046 if (l1 == 'y' && src[2] >= '0' && src[2] <= '1'
dead1419 1047 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1048 {
1049 *mode = A_REG_N;
e46fee70 1050 *reg = 6 + (l1 - '0');
d4845d57
JR		 1051 return 3;
1052 }
e46fee70 1053 if (l1 == 's' && src[2] >= '0' && src[2] <= '3'
dead1419 1054 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57 1055 {
e46fee70 1056 int n = l1 - '0';
d4845d57
JR		 1057
1058 *mode = A_REG_N;
1059 *reg = n | ((~n & 2) << 1);
1060 return 3;
1061 }
1062 }
1063
912a07db 1064 if (l0 == 'i' && l1 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57 1065 {
e46fee70 1066 if (l1 == 's')
d4845d57
JR		 1067 {
1068 *mode = A_REG_N;
1069 *reg = 8;
252b5132
RH		 1070 return 2;
1071 }
e46fee70 1072 if (l1 == 'x')
d4845d57
JR		 1073 {
1074 *mode = A_REG_N;
1075 *reg = 8;
1076 return 2;
1077 }
e46fee70 1078 if (l1 == 'y')
d4845d57
JR		 1079 {
1080 *mode = A_REG_N;
1081 *reg = 9;
1082 return 2;
1083 }
1084 }
1085
e46fee70 1086 if (l0 == 'x' && l1 >= '0' && l1 <= '1'
dead1419 1087 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1088 {
1089 *mode = DSP_REG_N;
e46fee70 1090 *reg = A_X0_NUM + l1 - '0';
d4845d57
JR		 1091 return 2;
1092 }
1093
e46fee70 1094 if (l0 == 'y' && l1 >= '0' && l1 <= '1'
dead1419 1095 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1096 {
1097 *mode = DSP_REG_N;
e46fee70 1098 *reg = A_Y0_NUM + l1 - '0';
d4845d57
JR		 1099 return 2;
1100 }
1101
e46fee70 1102 if (l0 == 'm' && l1 >= '0' && l1 <= '1'
dead1419 1103 && ! IDENT_CHAR ((unsigned char) src[2]))
d4845d57
JR		 1104 {
1105 *mode = DSP_REG_N;
e46fee70 1106 *reg = l1 == '0' ? A_M0_NUM : A_M1_NUM;
d4845d57 1107 return 2;
252b5132
RH		 1108 }
1109
e46fee70
HPN		 1110 if (l0 == 's'
1111 && l1 == 's'
3882b010 1112 && TOLOWER (src[2]) == 'r' && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1113 {
1114 *mode = A_SSR;
1115 return 3;
1116 }
1117
3882b010 1118 if (l0 == 's' && l1 == 'p' && TOLOWER (src[2]) == 'c'
dead1419 1119 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1120 {
1121 *mode = A_SPC;
1122 return 3;
1123 }
1124
3882b010 1125 if (l0 == 's' && l1 == 'g' && TOLOWER (src[2]) == 'r'
dead1419 1126 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1127 {
1128 *mode = A_SGR;
1129 return 3;
1130 }
1131
3882b010 1132 if (l0 == 'd' && l1 == 's' && TOLOWER (src[2]) == 'r'
dead1419 1133 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1134 {
1135 *mode = A_DSR;
1136 return 3;
1137 }
1138
3882b010 1139 if (l0 == 'd' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 1140 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1141 {
1142 *mode = A_DBR;
1143 return 3;
1144 }
1145
e46fee70 1146 if (l0 == 's' && l1 == 'r' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 1147 {
1148 *mode = A_SR;
1149 return 2;
1150 }
1151
e46fee70 1152 if (l0 == 's' && l1 == 'p' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 1153 {
1154 *mode = A_REG_N;
1155 *reg = 15;
1156 return 2;
1157 }
1158
e46fee70 1159 if (l0 == 'p' && l1 == 'r' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132
RH		 1160 {
1161 *mode = A_PR;
1162 return 2;
1163 }
e46fee70 1164 if (l0 == 'p' && l1 == 'c' && ! IDENT_CHAR ((unsigned char) src[2]))
252b5132 1165 {
015551fc
JR		 1166 /* Don't use A_DISP_PC here - that would accept stuff like 'mova pc,r0'
1167 and use an uninitialized immediate. */
1168 *mode = A_PC;
252b5132
RH		 1169 return 2;
1170 }
3882b010 1171 if (l0 == 'g' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 1172 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1173 {
1174 *mode = A_GBR;
1175 return 3;
1176 }
3882b010 1177 if (l0 == 'v' && l1 == 'b' && TOLOWER (src[2]) == 'r'
dead1419 1178 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1179 {
1180 *mode = A_VBR;
1181 return 3;
1182 }
1183
1d70c7fb
AO		 1184 if (l0 == 't' && l1 == 'b' && TOLOWER (src[2]) == 'r'
1185 && ! IDENT_CHAR ((unsigned char) src[3]))
1186 {
1187 *mode = A_TBR;
1188 return 3;
1189 }
3882b010 1190 if (l0 == 'm' && l1 == 'a' && TOLOWER (src[2]) == 'c'
dead1419 1191 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132 1192 {
3882b010 1193 if (TOLOWER (src[3]) == 'l')
252b5132
RH		 1194 {
1195 *mode = A_MACL;
1196 return 4;
1197 }
3882b010 1198 if (TOLOWER (src[3]) == 'h')
252b5132
RH		 1199 {
1200 *mode = A_MACH;
1201 return 4;
1202 }
1203 }
3882b010 1204 if (l0 == 'm' && l1 == 'o' && TOLOWER (src[2]) == 'd'
912a07db 1205 && ! IDENT_CHAR ((unsigned char) src[3]))
d4845d57
JR		 1206 {
1207 *mode = A_MOD;
1208 return 3;
1209 }
e46fee70 1210 if (l0 == 'f' && l1 == 'r')
252b5132
RH		 1211 {
1212 if (src[2] == '1')
1213 {
1214 if (src[3] >= '0' && src[3] <= '5'
dead1419 1215 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1216 {
1217 *mode = F_REG_N;
1218 *reg = 10 + src[3] - '0';
1219 return 4;
1220 }
1221 }
1222 if (src[2] >= '0' && src[2] <= '9'
dead1419 1223 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1224 {
1225 *mode = F_REG_N;
1226 *reg = (src[2] - '0');
1227 return 3;
1228 }
1229 }
e46fee70 1230 if (l0 == 'd' && l1 == 'r')
252b5132
RH		 1231 {
1232 if (src[2] == '1')
1233 {
1234 if (src[3] >= '0' && src[3] <= '4' && ! ((src[3] - '0') & 1)
dead1419 1235 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1236 {
1237 *mode = D_REG_N;
1238 *reg = 10 + src[3] - '0';
1239 return 4;
1240 }
1241 }
1242 if (src[2] >= '0' && src[2] <= '8' && ! ((src[2] - '0') & 1)
dead1419 1243 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1244 {
1245 *mode = D_REG_N;
1246 *reg = (src[2] - '0');
1247 return 3;
1248 }
1249 }
e46fee70 1250 if (l0 == 'x' && l1 == 'd')
252b5132
RH		 1251 {
1252 if (src[2] == '1')
1253 {
1254 if (src[3] >= '0' && src[3] <= '4' && ! ((src[3] - '0') & 1)
dead1419 1255 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1256 {
1257 *mode = X_REG_N;
1258 *reg = 11 + src[3] - '0';
1259 return 4;
1260 }
1261 }
1262 if (src[2] >= '0' && src[2] <= '8' && ! ((src[2] - '0') & 1)
dead1419 1263 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1264 {
1265 *mode = X_REG_N;
1266 *reg = (src[2] - '0') + 1;
1267 return 3;
1268 }
1269 }
e46fee70 1270 if (l0 == 'f' && l1 == 'v')
252b5132 1271 {
dead1419 1272 if (src[2] == '1'&& src[3] == '2' && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1273 {
1274 *mode = V_REG_N;
1275 *reg = 12;
1276 return 4;
1277 }
1278 if ((src[2] == '0' || src[2] == '4' || src[2] == '8')
dead1419 1279 && ! IDENT_CHAR ((unsigned char) src[3]))
252b5132
RH		 1280 {
1281 *mode = V_REG_N;
1282 *reg = (src[2] - '0');
1283 return 3;
1284 }
1285 }
3882b010
L		 1286 if (l0 == 'f' && l1 == 'p' && TOLOWER (src[2]) == 'u'
1287 && TOLOWER (src[3]) == 'l'
dead1419 1288 && ! IDENT_CHAR ((unsigned char) src[4]))
252b5132
RH		 1289 {
1290 *mode = FPUL_N;
1291 return 4;
1292 }
1293
3882b010
L		 1294 if (l0 == 'f' && l1 == 'p' && TOLOWER (src[2]) == 's'
1295 && TOLOWER (src[3]) == 'c'
1296 && TOLOWER (src[4]) == 'r' && ! IDENT_CHAR ((unsigned char) src[5]))
252b5132
RH		 1297 {
1298 *mode = FPSCR_N;
1299 return 5;
1300 }
1301
3882b010
L		 1302 if (l0 == 'x' && l1 == 'm' && TOLOWER (src[2]) == 't'
1303 && TOLOWER (src[3]) == 'r'
1304 && TOLOWER (src[4]) == 'x' && ! IDENT_CHAR ((unsigned char) src[5]))
252b5132
RH		 1305 {
1306 *mode = XMTRX_M4;
1307 return 5;
1308 }
1309
1310 return 0;
1311}
1312
37dedf66
NC		 1313/* Like parse_reg_without_prefix, but this version supports
1314 $-prefixed register names if enabled by the user. */
1315
1316static unsigned int
1317parse_reg (char *src, int *mode, int *reg)
1318{
1319 unsigned int prefix;
1320 unsigned int consumed;
1321
1322 if (src[0] == '$')
1323 {
1324 if (allow_dollar_register_prefix)
1325 {
1326 src ++;
1327 prefix = 1;
1328 }
1329 else
1330 return 0;
1331 }
1332 else
1333 prefix = 0;
1334
1335 consumed = parse_reg_without_prefix (src, mode, reg);
1336
1337 if (consumed == 0)
1338 return 0;
1339
1340 return consumed + prefix;
1341}
1342
c4aa876b 1343static char *
8edc77b9 1344parse_exp (char *s, sh_operand_info *op)
252b5132
RH		 1345{
1346 char *save;
1347 char *new;
1348
1349 save = input_line_pointer;
1350 input_line_pointer = s;
015551fc
JR		 1351 expression (&op->immediate);
1352 if (op->immediate.X_op == O_absent)
252b5132 1353 as_bad (_("missing operand"));
538cd60f
AO		 1354#ifdef OBJ_ELF
1355 else if (op->immediate.X_op == O_PIC_reloc
1356 || sh_PIC_related_p (op->immediate.X_add_symbol)
1357 || sh_PIC_related_p (op->immediate.X_op_symbol))
1358 as_bad (_("misplaced PIC operand"));
1359#endif
252b5132
RH		 1360 new = input_line_pointer;
1361 input_line_pointer = save;
1362 return new;
1363}
1364
252b5132
RH		 1365/* The many forms of operand:
1366
1367 Rn Register direct
1368 @Rn Register indirect
1369 @Rn+ Autoincrement
1370 @-Rn Autodecrement
1371 @(disp:4,Rn)
1372 @(disp:8,GBR)
1373 @(disp:8,PC)
1374
1375 @(R0,Rn)
1376 @(R0,GBR)
1377
1378 disp:8
1379 disp:12
1380 #imm8
1381 pr, gbr, vbr, macl, mach
252b5132
RH		 1382 */
1383
c4aa876b 1384static char *
8edc77b9 1385parse_at (char *src, sh_operand_info *op)
252b5132
RH		 1386{
1387 int len;
1388 int mode;
1389 src++;
1d70c7fb
AO		 1390 if (src[0] == '@')
1391 {
1392 src = parse_at (src, op);
1393 if (op->type == A_DISP_TBR)
1394 op->type = A_DISP2_TBR;
1395 else
1396 as_bad (_("illegal double indirection"));
1397 }
1398 else if (src[0] == '-')
252b5132 1399 {
6b31947e 1400 /* Must be predecrement. */
252b5132
RH		 1401 src++;
1402
1403 len = parse_reg (src, &mode, &(op->reg));
1404 if (mode != A_REG_N)
1405 as_bad (_("illegal register after @-"));
1406
1407 op->type = A_DEC_N;
1408 src += len;
1409 }
1410 else if (src[0] == '(')
1411 {
1412 /* Could be @(disp, rn), @(disp, gbr), @(disp, pc), @(r0, gbr) or
8d4d84c2 1413 @(r0, rn). */
252b5132
RH		 1414 src++;
1415 len = parse_reg (src, &mode, &(op->reg));
1416 if (len && mode == A_REG_N)
1417 {
1418 src += len;
1419 if (op->reg != 0)
1420 {
1421 as_bad (_("must be @(r0,...)"));
1422 }
1423 if (src[0] == ',')
252b5132 1424 {
8d4d84c2
AO		 1425 src++;
1426 /* Now can be rn or gbr. */
1427 len = parse_reg (src, &mode, &(op->reg));
1428 }
1429 else
1430 {
1431 len = 0;
252b5132 1432 }
8d4d84c2 1433 if (len)
252b5132 1434 {
8d4d84c2
AO		 1435 if (mode == A_GBR)
1436 {
1437 op->type = A_R0_GBR;
1438 }
1439 else if (mode == A_REG_N)
1440 {
1441 op->type = A_IND_R0_REG_N;
1442 }
1443 else
1444 {
1445 as_bad (_("syntax error in @(r0,...)"));
1446 }
252b5132
RH		 1447 }
1448 else
1449 {
8d4d84c2 1450 as_bad (_("syntax error in @(r0...)"));
252b5132
RH		 1451 }
1452 }
1453 else
1454 {
8d4d84c2 1455 /* Must be an @(disp,.. thing). */
015551fc 1456 src = parse_exp (src, op);
252b5132
RH		 1457 if (src[0] == ',')
1458 src++;
8d4d84c2 1459 /* Now can be rn, gbr or pc. */
252b5132
RH		 1460 len = parse_reg (src, &mode, &op->reg);
1461 if (len)
1462 {
1463 if (mode == A_REG_N)
1464 {
1465 op->type = A_DISP_REG_N;
1466 }
1467 else if (mode == A_GBR)
1468 {
1469 op->type = A_DISP_GBR;
1470 }
1d70c7fb
AO		 1471 else if (mode == A_TBR)
1472 {
1473 op->type = A_DISP_TBR;
1474 }
015551fc 1475 else if (mode == A_PC)
252b5132 1476 {
dbb4348d
JR		 1477 /* We want @(expr, pc) to uniformly address . + expr,
1478 no matter if expr is a constant, or a more complex
1479 expression, e.g. sym-. or sym1-sym2.
1480 However, we also used to accept @(sym,pc)
67c1ffbe 1481 as addressing sym, i.e. meaning the same as plain sym.
dbb4348d
JR		 1482 Some existing code does use the @(sym,pc) syntax, so
1483 we give it the old semantics for now, but warn about
1484 its use, so that users have some time to fix their code.
1485
1486 Note that due to this backward compatibility hack,
1487 we'll get unexpected results when @(offset, pc) is used,
1488 and offset is a symbol that is set later to an an address
1489 difference, or an external symbol that is set to an
1490 address difference in another source file, so we want to
1491 eventually remove it. */
9691d64f
JR		 1492 if (op->immediate.X_op == O_symbol)
1493 {
1494 op->type = A_DISP_PC;
1495 as_warn (_("Deprecated syntax."));
1496 }
1497 else
1498 {
1499 op->type = A_DISP_PC_ABS;
1500 /* Such operands don't get corrected for PC==.+4, so
1501 make the correction here. */
1502 op->immediate.X_add_number -= 4;
1503 }
252b5132
RH		 1504 }
1505 else
1506 {
1507 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
1508 }
1509 }
1510 else
1511 {
1512 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
1513 }
1514 }
1515 src += len;
1516 if (src[0] != ')')
1517 as_bad (_("expecting )"));
1518 else
1519 src++;
1520 }
1521 else
1522 {
1523 src += parse_reg (src, &mode, &(op->reg));
1524 if (mode != A_REG_N)
006299d3
NC		 1525 as_bad (_("illegal register after @"));
1526
252b5132
RH		 1527 if (src[0] == '+')
1528 {
1000a02a
NC		 1529 char l0, l1;
1530
252b5132 1531 src++;
1000a02a
NC		 1532 l0 = TOLOWER (src[0]);
1533 l1 = TOLOWER (src[1]);
1534
1535 if ((l0 == 'r' && l1 == '8')
1536 || (l0 == 'i' && (l1 == 'x' || l1 == 's')))
d4845d57
JR		 1537 {
1538 src += 2;
88da98f3 1539 op->type = AX_PMOD_N;
d4845d57 1540 }
006299d3
NC		 1541 else if ( (l0 == 'r' && l1 == '9')
1542 || (l0 == 'i' && l1 == 'y'))
d4845d57
JR		 1543 {
1544 src += 2;
88da98f3 1545 op->type = AY_PMOD_N;
d4845d57
JR		 1546 }
1547 else
1548 op->type = A_INC_N;
252b5132
RH		 1549 }
1550 else
006299d3 1551 op->type = A_IND_N;
252b5132
RH		 1552 }
1553 return src;
1554}
1555
1556static void
8edc77b9 1557get_operand (char **ptr, sh_operand_info *op)
252b5132
RH		 1558{
1559 char *src = *ptr;
1560 int mode = -1;
1561 unsigned int len;
1562
1563 if (src[0] == '#')
1564 {
1565 src++;
015551fc 1566 *ptr = parse_exp (src, op);
252b5132
RH		 1567 op->type = A_IMM;
1568 return;
1569 }
1570
1571 else if (src[0] == '@')
1572 {
1573 *ptr = parse_at (src, op);
1574 return;
1575 }
1576 len = parse_reg (src, &mode, &(op->reg));
1577 if (len)
1578 {
1579 *ptr = src + len;
1580 op->type = mode;
1581 return;
1582 }
1583 else
1584 {
6b31947e 1585 /* Not a reg, the only thing left is a displacement. */
015551fc 1586 *ptr = parse_exp (src, op);
252b5132
RH		 1587 op->type = A_DISP_PC;
1588 return;
1589 }
1590}
1591
c4aa876b 1592static char *
8edc77b9 1593get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
252b5132
RH		 1594{
1595 char *ptr = args;
1596 if (info->arg[0])
1597 {
d4845d57
JR		 1598 /* The pre-processor will eliminate whitespace in front of '@'
1599 after the first argument; we may be called multiple times
1600 from assemble_ppi, so don't insist on finding whitespace here. */
1601 if (*ptr == ' ')
1602 ptr++;
252b5132
RH		 1603
1604 get_operand (&ptr, operand + 0);
1605 if (info->arg[1])
1606 {
1607 if (*ptr == ',')
1608 {
1609 ptr++;
1610 }
1611 get_operand (&ptr, operand + 1);
52ccafd0
JR		 1612 /* ??? Hack: psha/pshl have a varying operand number depending on
1613 the type of the first operand. We handle this by having the
1614 three-operand version first and reducing the number of operands
1615 parsed to two if we see that the first operand is an immediate.
1616 This works because no insn with three operands has an immediate
1617 as first operand. */
1618 if (info->arg[2] && operand[0].type != A_IMM)
252b5132
RH		 1619 {
1620 if (*ptr == ',')
1621 {
1622 ptr++;
1623 }
1624 get_operand (&ptr, operand + 2);
1625 }
1626 else
1627 {
1628 operand[2].type = 0;
1629 }
1630 }
1631 else
1632 {
1633 operand[1].type = 0;
1634 operand[2].type = 0;
1635 }
1636 }
1637 else
1638 {
1639 operand[0].type = 0;
1640 operand[1].type = 0;
1641 operand[2].type = 0;
1642 }
1643 return ptr;
1644}
1645
1646/* Passed a pointer to a list of opcodes which use different
1647 addressing modes, return the opcode which matches the opcodes
6b31947e 1648 provided. */
252b5132 1649
c4aa876b 1650static sh_opcode_info *
8edc77b9 1651get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
252b5132
RH		 1652{
1653 sh_opcode_info *this_try = opcode;
1654 char *name = opcode->name;
1655 int n = 0;
c4aa876b 1656
252b5132
RH		 1657 while (opcode->name)
1658 {
1659 this_try = opcode++;
5ff37431 1660 if ((this_try->name != name) && (strcmp (this_try->name, name) != 0))
252b5132
RH		 1661 {
1662 /* We've looked so far down the table that we've run out of
6b31947e 1663 opcodes with the same name. */
252b5132
RH		 1664 return 0;
1665 }
c4aa876b 1666
6b31947e 1667 /* Look at both operands needed by the opcodes and provided by
252b5132
RH		 1668 the user - since an arg test will often fail on the same arg
1669 again and again, we'll try and test the last failing arg the
6b31947e 1670 first on each opcode try. */
252b5132
RH		 1671 for (n = 0; this_try->arg[n]; n++)
1672 {
1673 sh_operand_info *user = operands + n;
1674 sh_arg_type arg = this_try->arg[n];
c4aa876b 1675
1d70c7fb
AO		 1676 if (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh2a_nofpu_up)
1677 && ( arg == A_DISP_REG_M
1678 || arg == A_DISP_REG_N))
1679 {
1680 /* Check a few key IMM* fields for overflow. */
1681 int opf;
1682 long val = user->immediate.X_add_number;
1683
1684 for (opf = 0; opf < 4; opf ++)
1685 switch (this_try->nibbles[opf])
1686 {
1687 case IMM0_4:
1688 case IMM1_4:
1689 if (val < 0 || val > 15)
1690 goto fail;
1691 break;
1692 case IMM0_4BY2:
1693 case IMM1_4BY2:
1694 if (val < 0 || val > 15 * 2)
1695 goto fail;
1696 break;
1697 case IMM0_4BY4:
1698 case IMM1_4BY4:
1699 if (val < 0 || val > 15 * 4)
1700 goto fail;
1701 break;
1702 default:
1703 break;
1704 }
1705 }
252b5132
RH		 1706 switch (arg)
1707 {
7679ead9
AO		 1708 case A_DISP_PC:
1709 if (user->type == A_DISP_PC_ABS)
1710 break;
1711 /* Fall through. */
252b5132
RH		 1712 case A_IMM:
1713 case A_BDISP12:
1714 case A_BDISP8:
1715 case A_DISP_GBR:
1d70c7fb 1716 case A_DISP2_TBR:
252b5132
RH		 1717 case A_MACH:
1718 case A_PR:
1719 case A_MACL:
1720 if (user->type != arg)
1721 goto fail;
1722 break;
1723 case A_R0:
1724 /* opcode needs r0 */
1725 if (user->type != A_REG_N || user->reg != 0)
1726 goto fail;
1727 break;
1728 case A_R0_GBR:
1729 if (user->type != A_R0_GBR || user->reg != 0)
1730 goto fail;
1731 break;
1732 case F_FR0:
1733 if (user->type != F_REG_N || user->reg != 0)
1734 goto fail;
1735 break;
1736
1737 case A_REG_N:
1738 case A_INC_N:
1739 case A_DEC_N:
1740 case A_IND_N:
1741 case A_IND_R0_REG_N:
1742 case A_DISP_REG_N:
1743 case F_REG_N:
1744 case D_REG_N:
1745 case X_REG_N:
1746 case V_REG_N:
1747 case FPUL_N:
1748 case FPSCR_N:
d4845d57 1749 case DSP_REG_N:
252b5132
RH		 1750 /* Opcode needs rn */
1751 if (user->type != arg)
1752 goto fail;
1753 reg_n = user->reg;
1754 break;
252b5132
RH		 1755 case DX_REG_N:
1756 if (user->type != D_REG_N && user->type != X_REG_N)
1757 goto fail;
1758 reg_n = user->reg;
1759 break;
1760 case A_GBR:
1d70c7fb 1761 case A_TBR:
252b5132
RH		 1762 case A_SR:
1763 case A_VBR:
d4845d57
JR		 1764 case A_DSR:
1765 case A_MOD:
1766 case A_RE:
1767 case A_RS:
252b5132
RH		 1768 case A_SSR:
1769 case A_SPC:
1770 case A_SGR:
1771 case A_DBR:
1772 if (user->type != arg)
1773 goto fail;
1774 break;
1775
c4aa876b 1776 case A_REG_B:
252b5132
RH		 1777 if (user->type != arg)
1778 goto fail;
1779 reg_b = user->reg;
1780 break;
1781
1d70c7fb
AO		 1782 case A_INC_R15:
1783 if (user->type != A_INC_N)
1784 goto fail;
1785 if (user->reg != 15)
1786 goto fail;
1787 reg_n = user->reg;
1788 break;
1789
1790 case A_DEC_R15:
1791 if (user->type != A_DEC_N)
1792 goto fail;
1793 if (user->reg != 15)
1794 goto fail;
1795 reg_n = user->reg;
1796 break;
1797
252b5132
RH		 1798 case A_REG_M:
1799 case A_INC_M:
1800 case A_DEC_M:
1801 case A_IND_M:
1802 case A_IND_R0_REG_M:
1803 case A_DISP_REG_M:
d4845d57 1804 case DSP_REG_M:
252b5132
RH		 1805 /* Opcode needs rn */
1806 if (user->type != arg - A_REG_M + A_REG_N)
1807 goto fail;
1808 reg_m = user->reg;
1809 break;
1810
88da98f3
MS		 1811 case AS_DEC_N:
1812 if (user->type != A_DEC_N)
1813 goto fail;
1814 if (user->reg < 2 || user->reg > 5)
1815 goto fail;
1816 reg_n = user->reg;
1817 break;
13ef8878 1818
88da98f3
MS		 1819 case AS_INC_N:
1820 if (user->type != A_INC_N)
1821 goto fail;
1822 if (user->reg < 2 || user->reg > 5)
1823 goto fail;
1824 reg_n = user->reg;
1825 break;
13ef8878 1826
88da98f3
MS		 1827 case AS_IND_N:
1828 if (user->type != A_IND_N)
1829 goto fail;
1830 if (user->reg < 2 || user->reg > 5)
1831 goto fail;
1832 reg_n = user->reg;
1833 break;
13ef8878 1834
88da98f3
MS		 1835 case AS_PMOD_N:
1836 if (user->type != AX_PMOD_N)
1837 goto fail;
1838 if (user->reg < 2 || user->reg > 5)
1839 goto fail;
1840 reg_n = user->reg;
1841 break;
13ef8878 1842
88da98f3
MS		 1843 case AX_INC_N:
1844 if (user->type != A_INC_N)
1845 goto fail;
1846 if (user->reg < 4 || user->reg > 5)
1847 goto fail;
1848 reg_n = user->reg;
1849 break;
13ef8878 1850
88da98f3
MS		 1851 case AX_IND_N:
1852 if (user->type != A_IND_N)
1853 goto fail;
1854 if (user->reg < 4 || user->reg > 5)
1855 goto fail;
1856 reg_n = user->reg;
1857 break;
13ef8878 1858
88da98f3
MS		 1859 case AX_PMOD_N:
1860 if (user->type != AX_PMOD_N)
1861 goto fail;
1862 if (user->reg < 4 || user->reg > 5)
1863 goto fail;
1864 reg_n = user->reg;
1865 break;
13ef8878 1866
88da98f3
MS		 1867 case AXY_INC_N:
1868 if (user->type != A_INC_N)
1869 goto fail;
1870 if ((user->reg < 4 || user->reg > 5)
1871 && (user->reg < 0 || user->reg > 1))
1872 goto fail;
1873 reg_n = user->reg;
1874 break;
13ef8878 1875
88da98f3
MS		 1876 case AXY_IND_N:
1877 if (user->type != A_IND_N)
1878 goto fail;
1879 if ((user->reg < 4 || user->reg > 5)
1880 && (user->reg < 0 || user->reg > 1))
1881 goto fail;
1882 reg_n = user->reg;
1883 break;
13ef8878 1884
88da98f3
MS		 1885 case AXY_PMOD_N:
1886 if (user->type != AX_PMOD_N)
1887 goto fail;
1888 if ((user->reg < 4 || user->reg > 5)
1889 && (user->reg < 0 || user->reg > 1))
1890 goto fail;
1891 reg_n = user->reg;
1892 break;
13ef8878 1893
88da98f3
MS		 1894 case AY_INC_N:
1895 if (user->type != A_INC_N)
1896 goto fail;
1897 if (user->reg < 6 || user->reg > 7)
1898 goto fail;
1899 reg_n = user->reg;
1900 break;
13ef8878 1901
88da98f3
MS		 1902 case AY_IND_N:
1903 if (user->type != A_IND_N)
1904 goto fail;
1905 if (user->reg < 6 || user->reg > 7)
1906 goto fail;
1907 reg_n = user->reg;
1908 break;
13ef8878 1909
88da98f3
MS		 1910 case AY_PMOD_N:
1911 if (user->type != AY_PMOD_N)
1912 goto fail;
1913 if (user->reg < 6 || user->reg > 7)
1914 goto fail;
1915 reg_n = user->reg;
1916 break;
1917
1918 case AYX_INC_N:
1919 if (user->type != A_INC_N)
1920 goto fail;
1921 if ((user->reg < 6 || user->reg > 7)
1922 && (user->reg < 2 || user->reg > 3))
1923 goto fail;
1924 reg_n = user->reg;
1925 break;
13ef8878 1926
88da98f3
MS		 1927 case AYX_IND_N:
1928 if (user->type != A_IND_N)
1929 goto fail;
1930 if ((user->reg < 6 || user->reg > 7)
1931 && (user->reg < 2 || user->reg > 3))
1932 goto fail;
1933 reg_n = user->reg;
1934 break;
13ef8878 1935
88da98f3
MS		 1936 case AYX_PMOD_N:
1937 if (user->type != AY_PMOD_N)
1938 goto fail;
1939 if ((user->reg < 6 || user->reg > 7)
1940 && (user->reg < 2 || user->reg > 3))
1941 goto fail;
1942 reg_n = user->reg;
1943 break;
1944
1945 case DSP_REG_A_M:
1946 if (user->type != DSP_REG_N)
1947 goto fail;
1948 if (user->reg != A_A0_NUM
1949 && user->reg != A_A1_NUM)
1950 goto fail;
1951 reg_m = user->reg;
1952 break;
1953
1954 case DSP_REG_AX:
1955 if (user->type != DSP_REG_N)
1956 goto fail;
1957 switch (user->reg)
1958 {
1959 case A_A0_NUM:
1960 reg_x = 0;
1961 break;
1962 case A_A1_NUM:
1963 reg_x = 2;
1964 break;
1965 case A_X0_NUM:
1966 reg_x = 1;
1967 break;
1968 case A_X1_NUM:
1969 reg_x = 3;
1970 break;
1971 default:
1972 goto fail;
1973 }
1974 break;
1975
1976 case DSP_REG_XY:
1977 if (user->type != DSP_REG_N)
1978 goto fail;
1979 switch (user->reg)
1980 {
1981 case A_X0_NUM:
1982 reg_x = 0;
1983 break;
1984 case A_X1_NUM:
1985 reg_x = 2;
1986 break;
1987 case A_Y0_NUM:
1988 reg_x = 1;
1989 break;
1990 case A_Y1_NUM:
1991 reg_x = 3;
1992 break;
1993 default:
1994 goto fail;
1995 }
1996 break;
1997
1998 case DSP_REG_AY:
1999 if (user->type != DSP_REG_N)
2000 goto fail;
2001 switch (user->reg)
2002 {
2003 case A_A0_NUM:
2004 reg_y = 0;
2005 break;
2006 case A_A1_NUM:
2007 reg_y = 1;
2008 break;
2009 case A_Y0_NUM:
2010 reg_y = 2;
2011 break;
2012 case A_Y1_NUM:
2013 reg_y = 3;
2014 break;
2015 default:
2016 goto fail;
2017 }
2018 break;
2019
2020 case DSP_REG_YX:
2021 if (user->type != DSP_REG_N)
2022 goto fail;
2023 switch (user->reg)
2024 {
2025 case A_Y0_NUM:
2026 reg_y = 0;
2027 break;
2028 case A_Y1_NUM:
2029 reg_y = 1;
2030 break;
2031 case A_X0_NUM:
2032 reg_y = 2;
2033 break;
2034 case A_X1_NUM:
2035 reg_y = 3;
2036 break;
2037 default:
2038 goto fail;
2039 }
2040 break;
2041
d4845d57
JR		 2042 case DSP_REG_X:
2043 if (user->type != DSP_REG_N)
2044 goto fail;
2045 switch (user->reg)
2046 {
2047 case A_X0_NUM:
2048 reg_x = 0;
2049 break;
2050 case A_X1_NUM:
2051 reg_x = 1;
2052 break;
2053 case A_A0_NUM:
2054 reg_x = 2;
2055 break;
2056 case A_A1_NUM:
2057 reg_x = 3;
2058 break;
2059 default:
2060 goto fail;
2061 }
2062 break;
2063
2064 case DSP_REG_Y:
2065 if (user->type != DSP_REG_N)
2066 goto fail;
2067 switch (user->reg)
2068 {
2069 case A_Y0_NUM:
2070 reg_y = 0;
2071 break;
2072 case A_Y1_NUM:
2073 reg_y = 1;
2074 break;
2075 case A_M0_NUM:
2076 reg_y = 2;
2077 break;
2078 case A_M1_NUM:
2079 reg_y = 3;
2080 break;
2081 default:
2082 goto fail;
2083 }
2084 break;
2085
2086 case DSP_REG_E:
2087 if (user->type != DSP_REG_N)
2088 goto fail;
2089 switch (user->reg)
2090 {
2091 case A_X0_NUM:
2092 reg_efg = 0 << 10;
2093 break;
2094 case A_X1_NUM:
2095 reg_efg = 1 << 10;
2096 break;
2097 case A_Y0_NUM:
2098 reg_efg = 2 << 10;
2099 break;
2100 case A_A1_NUM:
2101 reg_efg = 3 << 10;
2102 break;
2103 default:
2104 goto fail;
2105 }
2106 break;
2107
2108 case DSP_REG_F:
2109 if (user->type != DSP_REG_N)
2110 goto fail;
2111 switch (user->reg)
2112 {
2113 case A_Y0_NUM:
2114 reg_efg |= 0 << 8;
2115 break;
2116 case A_Y1_NUM:
2117 reg_efg |= 1 << 8;
2118 break;
2119 case A_X0_NUM:
2120 reg_efg |= 2 << 8;
2121 break;
2122 case A_A1_NUM:
2123 reg_efg |= 3 << 8;
2124 break;
2125 default:
2126 goto fail;
2127 }
2128 break;
2129
2130 case DSP_REG_G:
2131 if (user->type != DSP_REG_N)
2132 goto fail;
2133 switch (user->reg)
2134 {
2135 case A_M0_NUM:
2136 reg_efg |= 0 << 2;
2137 break;
2138 case A_M1_NUM:
2139 reg_efg |= 1 << 2;
2140 break;
2141 case A_A0_NUM:
2142 reg_efg |= 2 << 2;
2143 break;
2144 case A_A1_NUM:
2145 reg_efg |= 3 << 2;
2146 break;
2147 default:
2148 goto fail;
2149 }
2150 break;
2151
2152 case A_A0:
2153 if (user->type != DSP_REG_N || user->reg != A_A0_NUM)
2154 goto fail;
2155 break;
2156 case A_X0:
2157 if (user->type != DSP_REG_N || user->reg != A_X0_NUM)
2158 goto fail;
2159 break;
2160 case A_X1:
2161 if (user->type != DSP_REG_N || user->reg != A_X1_NUM)
2162 goto fail;
2163 break;
2164 case A_Y0:
2165 if (user->type != DSP_REG_N || user->reg != A_Y0_NUM)
2166 goto fail;
2167 break;
2168 case A_Y1:
2169 if (user->type != DSP_REG_N || user->reg != A_Y1_NUM)
2170 goto fail;
2171 break;
2172
252b5132
RH		 2173 case F_REG_M:
2174 case D_REG_M:
2175 case X_REG_M:
2176 case V_REG_M:
2177 case FPUL_M:
2178 case FPSCR_M:
2179 /* Opcode needs rn */
2180 if (user->type != arg - F_REG_M + F_REG_N)
2181 goto fail;
2182 reg_m = user->reg;
2183 break;
2184 case DX_REG_M:
2185 if (user->type != D_REG_N && user->type != X_REG_N)
2186 goto fail;
2187 reg_m = user->reg;
2188 break;
2189 case XMTRX_M4:
2190 if (user->type != XMTRX_M4)
2191 goto fail;
2192 reg_m = 4;
2193 break;
c4aa876b 2194
252b5132
RH		 2195 default:
2196 printf (_("unhandled %d\n"), arg);
2197 goto fail;
2198 }
2199 }
f6f9408f 2200 if ( !SH_MERGE_ARCH_SET_VALID (valid_arch, this_try->arch))
a37c8f88 2201 goto fail;
f6f9408f 2202 valid_arch = SH_MERGE_ARCH_SET (valid_arch, this_try->arch);
252b5132 2203 return this_try;
c4aa876b
NC		 2204 fail:
2205 ;
252b5132
RH		 2206 }
2207
2208 return 0;
2209}
2210
252b5132 2211static void
8edc77b9 2212insert (char *where, int how, int pcrel, sh_operand_info *op)
252b5132
RH		 2213{
2214 fix_new_exp (frag_now,
2215 where - frag_now->fr_literal,
2216 2,
015551fc 2217 &op->immediate,
252b5132
RH		 2218 pcrel,
2219 how);
2220}
2221
1d70c7fb
AO		 2222static void
2223insert4 (char * where, int how, int pcrel, sh_operand_info * op)
2224{
2225 fix_new_exp (frag_now,
2226 where - frag_now->fr_literal,
2227 4,
2228 & op->immediate,
2229 pcrel,
2230 how);
2231}
252b5132 2232static void
8edc77b9 2233build_relax (sh_opcode_info *opcode, sh_operand_info *op)
252b5132
RH		 2234{
2235 int high_byte = target_big_endian ? 0 : 1;
2236 char *p;
2237
2238 if (opcode->arg[0] == A_BDISP8)
2239 {
2240 int what = (opcode->nibbles[1] & 4) ? COND_JUMP_DELAY : COND_JUMP;
2241 p = frag_var (rs_machine_dependent,
2242 md_relax_table[C (what, COND32)].rlx_length,
2243 md_relax_table[C (what, COND8)].rlx_length,
2244 C (what, 0),
015551fc
JR		 2245 op->immediate.X_add_symbol,
2246 op->immediate.X_add_number,
252b5132
RH		 2247 0);
2248 p[high_byte] = (opcode->nibbles[0] << 4) | (opcode->nibbles[1]);
2249 }
2250 else if (opcode->arg[0] == A_BDISP12)
2251 {
2252 p = frag_var (rs_machine_dependent,
2253 md_relax_table[C (UNCOND_JUMP, UNCOND32)].rlx_length,
2254 md_relax_table[C (UNCOND_JUMP, UNCOND12)].rlx_length,
2255 C (UNCOND_JUMP, 0),
015551fc
JR		 2256 op->immediate.X_add_symbol,
2257 op->immediate.X_add_number,
252b5132
RH		 2258 0);
2259 p[high_byte] = (opcode->nibbles[0] << 4);
2260 }
2261
2262}
2263
6b31947e 2264/* Insert ldrs & ldre with fancy relocations that relaxation can recognize. */
d67b5d6d 2265
015551fc 2266static char *
8edc77b9 2267insert_loop_bounds (char *output, sh_operand_info *operand)
015551fc
JR		 2268{
2269 char *name;
2270 symbolS *end_sym;
2271
2272 /* Since the low byte of the opcode will be overwritten by the reloc, we
2273 can just stash the high byte into both bytes and ignore endianness. */
2274 output[0] = 0x8c;
2275 output[1] = 0x8c;
2276 insert (output, BFD_RELOC_SH_LOOP_START, 1, operand);
2277 insert (output, BFD_RELOC_SH_LOOP_END, 1, operand + 1);
2278
2279 if (sh_relax)
2280 {
2281 static int count = 0;
2282
2283 /* If the last loop insn is a two-byte-insn, it is in danger of being
2284 swapped with the insn after it. To prevent this, create a new
2285 symbol - complete with SH_LABEL reloc - after the last loop insn.
2286 If the last loop insn is four bytes long, the symbol will be
2287 right in the middle, but four byte insns are not swapped anyways. */
2288 /* A REPEAT takes 6 bytes. The SH has a 32 bit address space.
2289 Hence a 9 digit number should be enough to count all REPEATs. */
2290 name = alloca (11);
2291 sprintf (name, "_R%x", count++ & 0x3fffffff);
c4aa876b 2292 end_sym = symbol_new (name, undefined_section, 0, &zero_address_frag);
015551fc
JR		 2293 /* Make this a local symbol. */
2294#ifdef OBJ_COFF
2295 SF_SET_LOCAL (end_sym);
2296#endif /* OBJ_COFF */
2297 symbol_table_insert (end_sym);
2298 end_sym->sy_value = operand[1].immediate;
2299 end_sym->sy_value.X_add_number += 2;
2300 fix_new (frag_now, frag_now_fix (), 2, end_sym, 0, 1, BFD_RELOC_SH_LABEL);
2301 }
2302
2303 output = frag_more (2);
2304 output[0] = 0x8e;
2305 output[1] = 0x8e;
2306 insert (output, BFD_RELOC_SH_LOOP_START, 1, operand);
2307 insert (output, BFD_RELOC_SH_LOOP_END, 1, operand + 1);
2308
2309 return frag_more (2);
2310}
2311
d67b5d6d 2312/* Now we know what sort of opcodes it is, let's build the bytes. */
6b31947e 2313
0d10e182 2314static unsigned int
8edc77b9 2315build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
252b5132
RH		 2316{
2317 int index;
1d70c7fb
AO		 2318 char nbuf[8];
2319 char *output;
0d10e182 2320 unsigned int size = 2;
252b5132 2321 int low_byte = target_big_endian ? 1 : 0;
1d70c7fb
AO		 2322 int max_index = 4;
2323
252b5132
RH		 2324 nbuf[0] = 0;
2325 nbuf[1] = 0;
2326 nbuf[2] = 0;
2327 nbuf[3] = 0;
1d70c7fb
AO		 2328 nbuf[4] = 0;
2329 nbuf[5] = 0;
2330 nbuf[6] = 0;
2331 nbuf[7] = 0;
2332
2333 if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
2334 {
2335 output = frag_more (4);
2336 size = 4;
2337 max_index = 8;
2338 }
2339 else
2340 output = frag_more (2);
252b5132 2341
1d70c7fb 2342 for (index = 0; index < max_index; index++)
252b5132
RH		 2343 {
2344 sh_nibble_type i = opcode->nibbles[index];
2345 if (i < 16)
2346 {
2347 nbuf[index] = i;
2348 }
2349 else
2350 {
2351 switch (i)
2352 {
2353 case REG_N:
6a5709a5 2354 case REG_N_D:
252b5132
RH		 2355 nbuf[index] = reg_n;
2356 break;
2357 case REG_M:
2358 nbuf[index] = reg_m;
2359 break;
d4845d57
JR		 2360 case SDT_REG_N:
2361 if (reg_n < 2 || reg_n > 5)
2362 as_bad (_("Invalid register: 'r%d'"), reg_n);
2363 nbuf[index] = (reg_n & 3) | 4;
2364 break;
252b5132
RH		 2365 case REG_NM:
2366 nbuf[index] = reg_n | (reg_m >> 2);
2367 break;
c4aa876b 2368 case REG_B:
252b5132
RH		 2369 nbuf[index] = reg_b | 0x08;
2370 break;
6a5709a5
JR		 2371 case REG_N_B01:
2372 nbuf[index] = reg_n | 0x01;
2373 break;
1d70c7fb
AO		 2374 case IMM0_3s:
2375 nbuf[index] |= 0x08;
2376 case IMM0_3c:
2377 insert (output + low_byte, BFD_RELOC_SH_IMM3, 0, operand);
2378 break;
2379 case IMM0_3Us:
2380 nbuf[index] |= 0x80;
2381 case IMM0_3Uc:
2382 insert (output + low_byte, BFD_RELOC_SH_IMM3U, 0, operand);
2383 break;
2384 case DISP0_12:
2385 insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand);
2386 break;
2387 case DISP0_12BY2:
2388 insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand);
2389 break;
2390 case DISP0_12BY4:
2391 insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand);
2392 break;
2393 case DISP0_12BY8:
2394 insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand);
2395 break;
2396 case DISP1_12:
2397 insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand+1);
2398 break;
2399 case DISP1_12BY2:
2400 insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand+1);
2401 break;
2402 case DISP1_12BY4:
2403 insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand+1);
2404 break;
2405 case DISP1_12BY8:
2406 insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand+1);
2407 break;
2408 case IMM0_20_4:
2409 break;
2410 case IMM0_20:
2411 insert4 (output, BFD_RELOC_SH_DISP20, 0, operand);
2412 break;
2413 case IMM0_20BY8:
2414 insert4 (output, BFD_RELOC_SH_DISP20BY8, 0, operand);
2415 break;
015551fc
JR		 2416 case IMM0_4BY4:
2417 insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand);
2418 break;
2419 case IMM0_4BY2:
2420 insert (output + low_byte, BFD_RELOC_SH_IMM4BY2, 0, operand);
2421 break;
2422 case IMM0_4:
2423 insert (output + low_byte, BFD_RELOC_SH_IMM4, 0, operand);
2424 break;
2425 case IMM1_4BY4:
2426 insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand + 1);
2427 break;
2428 case IMM1_4BY2:
2429 insert (output + low_byte, BFD_RELOC_SH_IMM4BY2, 0, operand + 1);
252b5132 2430 break;
015551fc
JR		 2431 case IMM1_4:
2432 insert (output + low_byte, BFD_RELOC_SH_IMM4, 0, operand + 1);
252b5132 2433 break;
015551fc
JR		 2434 case IMM0_8BY4:
2435 insert (output + low_byte, BFD_RELOC_SH_IMM8BY4, 0, operand);
252b5132 2436 break;
015551fc
JR		 2437 case IMM0_8BY2:
2438 insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand);
252b5132 2439 break;
015551fc
JR		 2440 case IMM0_8:
2441 insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand);
252b5132 2442 break;
015551fc
JR		 2443 case IMM1_8BY4:
2444 insert (output + low_byte, BFD_RELOC_SH_IMM8BY4, 0, operand + 1);
252b5132 2445 break;
015551fc
JR		 2446 case IMM1_8BY2:
2447 insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand + 1);
2448 break;
2449 case IMM1_8:
2450 insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand + 1);
252b5132
RH		 2451 break;
2452 case PCRELIMM_8BY4:
7679ead9
AO		 2453 insert (output, BFD_RELOC_SH_PCRELIMM8BY4,
2454 operand->type != A_DISP_PC_ABS, operand);
252b5132
RH		 2455 break;
2456 case PCRELIMM_8BY2:
7679ead9
AO		 2457 insert (output, BFD_RELOC_SH_PCRELIMM8BY2,
2458 operand->type != A_DISP_PC_ABS, operand);
015551fc
JR		 2459 break;
2460 case REPEAT:
2461 output = insert_loop_bounds (output, operand);
2462 nbuf[index] = opcode->nibbles[3];
2463 operand += 2;
252b5132
RH		 2464 break;
2465 default:
2466 printf (_("failed for %d\n"), i);
2467 }
2468 }
2469 }
c4aa876b
NC		 2470 if (!target_big_endian)
2471 {
2472 output[1] = (nbuf[0] << 4) | (nbuf[1]);
2473 output[0] = (nbuf[2] << 4) | (nbuf[3]);
2474 }
2475 else
2476 {
2477 output[0] = (nbuf[0] << 4) | (nbuf[1]);
2478 output[1] = (nbuf[2] << 4) | (nbuf[3]);
2479 }
1d70c7fb
AO		 2480 if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
2481 {
2482 if (!target_big_endian)
2483 {
2484 output[3] = (nbuf[4] << 4) | (nbuf[5]);
2485 output[2] = (nbuf[6] << 4) | (nbuf[7]);
2486 }
2487 else
2488 {
2489 output[2] = (nbuf[4] << 4) | (nbuf[5]);
2490 output[3] = (nbuf[6] << 4) | (nbuf[7]);
2491 }
2492 }
0d10e182 2493 return size;
252b5132
RH		 2494}
2495
d4845d57
JR		 2496/* Find an opcode at the start of *STR_P in the hash table, and set
2497 *STR_P to the first character after the last one read. */
252b5132 2498
d4845d57 2499static sh_opcode_info *
8edc77b9 2500find_cooked_opcode (char **str_p)
252b5132 2501{
d4845d57 2502 char *str = *str_p;
252b5132
RH		 2503 unsigned char *op_start;
2504 unsigned char *op_end;
252b5132
RH		 2505 char name[20];
2506 int nlen = 0;
c4aa876b 2507
6b31947e 2508 /* Drop leading whitespace. */
252b5132
RH		 2509 while (*str == ' ')
2510 str++;
2511
d4845d57
JR		 2512 /* Find the op code end.
2513 The pre-processor will eliminate whitespace in front of
2514 any '@' after the first argument; we may be called from
2515 assemble_ppi, so the opcode might be terminated by an '@'. */
2132e3a3 2516 for (op_start = op_end = (unsigned char *) str;
252b5132
RH		 2517 *op_end
2518 && nlen < 20
d4845d57 2519 && !is_end_of_line[*op_end] && *op_end != ' ' && *op_end != '@';
252b5132
RH		 2520 op_end++)
2521 {
2522 unsigned char c = op_start[nlen];
2523
2524 /* The machine independent code will convert CMP/EQ into cmp/EQ
d4845d57
JR		 2525 because it thinks the '/' is the end of the symbol. Moreover,
2526 all but the first sub-insn is a parallel processing insn won't
3882b010 2527 be capitalized. Instead of hacking up the machine independent
d4845d57 2528 code, we just deal with it here. */
3882b010 2529 c = TOLOWER (c);
252b5132
RH		 2530 name[nlen] = c;
2531 nlen++;
2532 }
c4aa876b 2533
252b5132 2534 name[nlen] = 0;
2132e3a3 2535 *str_p = (char *) op_end;
252b5132
RH		 2536
2537 if (nlen == 0)
6b31947e 2538 as_bad (_("can't find opcode "));
252b5132 2539
d4845d57
JR		 2540 return (sh_opcode_info *) hash_find (opcode_hash_control, name);
2541}
2542
2543/* Assemble a parallel processing insn. */
2544#define DDT_BASE 0xf000 /* Base value for double data transfer insns */
6b31947e 2545
0d10e182 2546static unsigned int
8edc77b9 2547assemble_ppi (char *op_end, sh_opcode_info *opcode)
d4845d57
JR		 2548{
2549 int movx = 0;
2550 int movy = 0;
2551 int cond = 0;
2552 int field_b = 0;
2553 char *output;
2554 int move_code;
0d10e182 2555 unsigned int size;
d4845d57 2556
d4845d57
JR		 2557 for (;;)
2558 {
2559 sh_operand_info operand[3];
2560
ac62e7a3
JR		 2561 /* Some insn ignore one or more register fields, e.g. psts machl,a0.
2562 Make sure we encode a defined insn pattern. */
2563 reg_x = 0;
2564 reg_y = 0;
2565 reg_n = 0;
2566
d4845d57
JR		 2567 if (opcode->arg[0] != A_END)
2568 op_end = get_operands (opcode, op_end, operand);
88da98f3 2569 try_another_opcode:
d4845d57
JR		 2570 opcode = get_specific (opcode, operand);
2571 if (opcode == 0)
2572 {
6b31947e 2573 /* Couldn't find an opcode which matched the operands. */
d4845d57 2574 char *where = frag_more (2);
0d10e182 2575 size = 2;
d4845d57
JR		 2576
2577 where[0] = 0x0;
2578 where[1] = 0x0;
2579 as_bad (_("invalid operands for opcode"));
0d10e182 2580 return size;
d4845d57 2581 }
c4aa876b 2582
d4845d57
JR		 2583 if (opcode->nibbles[0] != PPI)
2584 as_bad (_("insn can't be combined with parallel processing insn"));
2585
2586 switch (opcode->nibbles[1])
2587 {
2588
2589 case NOPX:
2590 if (movx)
2591 as_bad (_("multiple movx specifications"));
2592 movx = DDT_BASE;
2593 break;
2594 case NOPY:
2595 if (movy)
2596 as_bad (_("multiple movy specifications"));
2597 movy = DDT_BASE;
2598 break;
2599
88da98f3
MS		 2600 case MOVX_NOPY:
2601 if (movx)
2602 as_bad (_("multiple movx specifications"));
2603 if ((reg_n < 4 || reg_n > 5)
2604 && (reg_n < 0 || reg_n > 1))
2605 as_bad (_("invalid movx address register"));
2606 if (movy && movy != DDT_BASE)
2607 as_bad (_("insn cannot be combined with non-nopy"));
2608 movx = ((((reg_n & 1) != 0) << 9)
2609 + (((reg_n & 4) == 0) << 8)
2610 + (reg_x << 6)
2611 + (opcode->nibbles[2] << 4)
2612 + opcode->nibbles[3]
2613 + DDT_BASE);
2614 break;
2615
2616 case MOVY_NOPX:
2617 if (movy)
2618 as_bad (_("multiple movy specifications"));
2619 if ((reg_n < 6 || reg_n > 7)
2620 && (reg_n < 2 || reg_n > 3))
2621 as_bad (_("invalid movy address register"));
2622 if (movx && movx != DDT_BASE)
2623 as_bad (_("insn cannot be combined with non-nopx"));
2624 movy = ((((reg_n & 1) != 0) << 8)
2625 + (((reg_n & 4) == 0) << 9)
2626 + (reg_y << 6)
2627 + (opcode->nibbles[2] << 4)
2628 + opcode->nibbles[3]
2629 + DDT_BASE);
2630 break;
2631
d4845d57
JR		 2632 case MOVX:
2633 if (movx)
2634 as_bad (_("multiple movx specifications"));
88da98f3
MS		 2635 if (movy & 0x2ac)
2636 as_bad (_("previous movy requires nopx"));
d4845d57
JR		 2637 if (reg_n < 4 || reg_n > 5)
2638 as_bad (_("invalid movx address register"));
2639 if (opcode->nibbles[2] & 8)
2640 {
2641 if (reg_m == A_A1_NUM)
2642 movx = 1 << 7;
2643 else if (reg_m != A_A0_NUM)
2644 as_bad (_("invalid movx dsp register"));
2645 }
2646 else
2647 {
2648 if (reg_x > 1)
2649 as_bad (_("invalid movx dsp register"));
2650 movx = reg_x << 7;
2651 }
2652 movx += ((reg_n - 4) << 9) + (opcode->nibbles[2] << 2) + DDT_BASE;
2653 break;
2654
2655 case MOVY:
2656 if (movy)
2657 as_bad (_("multiple movy specifications"));
88da98f3
MS		 2658 if (movx & 0x153)
2659 as_bad (_("previous movx requires nopy"));
d4845d57
JR		 2660 if (opcode->nibbles[2] & 8)
2661 {
2662 /* Bit 3 in nibbles[2] is intended for bit 4 of the opcode,
2663 so add 8 more. */
2664 movy = 8;
2665 if (reg_m == A_A1_NUM)
2666 movy += 1 << 6;
2667 else if (reg_m != A_A0_NUM)
2668 as_bad (_("invalid movy dsp register"));
2669 }
2670 else
2671 {
2672 if (reg_y > 1)
2673 as_bad (_("invalid movy dsp register"));
2674 movy = reg_y << 6;
2675 }
2676 if (reg_n < 6 || reg_n > 7)
2677 as_bad (_("invalid movy address register"));
2678 movy += ((reg_n - 6) << 8) + opcode->nibbles[2] + DDT_BASE;
2679 break;
2680
2681 case PSH:
015551fc 2682 if (operand[0].immediate.X_op != O_constant)
d4845d57
JR		 2683 as_bad (_("dsp immediate shift value not constant"));
2684 field_b = ((opcode->nibbles[2] << 12)
015551fc 2685 | (operand[0].immediate.X_add_number & 127) << 4
d4845d57
JR		 2686 | reg_n);
2687 break;
88da98f3
MS		 2688 case PPI3NC:
2689 if (cond)
2690 {
2691 opcode++;
2692 goto try_another_opcode;
2693 }
2694 /* Fall through. */
d4845d57
JR		 2695 case PPI3:
2696 if (field_b)
2697 as_bad (_("multiple parallel processing specifications"));
2698 field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8)
2699 + (reg_x << 6) + (reg_y << 4) + reg_n);
88da98f3
MS		 2700 switch (opcode->nibbles[4])
2701 {
2702 case HEX_0:
2703 case HEX_XX00:
2704 case HEX_00YY:
2705 break;
2706 case HEX_1:
2707 case HEX_4:
2708 field_b += opcode->nibbles[4] << 4;
2709 break;
2710 default:
2711 abort ();
2712 }
d4845d57
JR		 2713 break;
2714 case PDC:
2715 if (cond)
2716 as_bad (_("multiple condition specifications"));
2717 cond = opcode->nibbles[2] << 8;
2718 if (*op_end)
2719 goto skip_cond_check;
2720 break;
2721 case PPIC:
2722 if (field_b)
2723 as_bad (_("multiple parallel processing specifications"));
2724 field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8)
2725 + cond + (reg_x << 6) + (reg_y << 4) + reg_n);
2726 cond = 0;
88da98f3
MS		 2727 switch (opcode->nibbles[4])
2728 {
2729 case HEX_0:
2730 case HEX_XX00:
2731 case HEX_00YY:
2732 break;
2733 case HEX_1:
2734 case HEX_4:
2735 field_b += opcode->nibbles[4] << 4;
2736 break;
2737 default:
2738 abort ();
2739 }
d4845d57
JR		 2740 break;
2741 case PMUL:
2742 if (field_b)
2743 {
88da98f3
MS		 2744 if ((field_b & 0xef00) == 0xa100)
2745 field_b -= 0x8100;
2746 /* pclr Dz pmuls Se,Sf,Dg */
2747 else if ((field_b & 0xff00) == 0x8d00
f6f9408f 2748 && (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh4al_dsp_up)))
88da98f3 2749 {
f6f9408f 2750 valid_arch = SH_MERGE_ARCH_SET (valid_arch, arch_sh4al_dsp_up);
88da98f3
MS		 2751 field_b -= 0x8cf0;
2752 }
2753 else
d4845d57 2754 as_bad (_("insn cannot be combined with pmuls"));
d4845d57
JR		 2755 switch (field_b & 0xf)
2756 {
2757 case A_X0_NUM:
2758 field_b += 0 - A_X0_NUM;
2759 break;
2760 case A_Y0_NUM:
2761 field_b += 1 - A_Y0_NUM;
2762 break;
2763 case A_A0_NUM:
2764 field_b += 2 - A_A0_NUM;
2765 break;
2766 case A_A1_NUM:
2767 field_b += 3 - A_A1_NUM;
2768 break;
2769 default:
88da98f3 2770 as_bad (_("bad combined pmuls output operand"));
d4845d57 2771 }
7dd04abd
JR		 2772 /* Generate warning if the destination register for padd / psub
2773 and pmuls is the same ( only for A0 or A1 ).
2774 If the last nibble is 1010 then A0 is used in both
2775 padd / psub and pmuls. If it is 1111 then A1 is used
2776 as destination register in both padd / psub and pmuls. */
5db33d76
JR		 2777
2778 if ((((field_b | reg_efg) & 0x000F) == 0x000A)
2779 || (((field_b | reg_efg) & 0x000F) == 0x000F))
2780 as_warn (_("destination register is same for parallel insns"));
d4845d57
JR		 2781 }
2782 field_b += 0x4000 + reg_efg;
2783 break;
2784 default:
2785 abort ();
2786 }
2787 if (cond)
2788 {
2789 as_bad (_("condition not followed by conditionalizable insn"));
2790 cond = 0;
2791 }
2792 if (! *op_end)
2793 break;
2794 skip_cond_check:
2795 opcode = find_cooked_opcode (&op_end);
2796 if (opcode == NULL)
2797 {
2798 (as_bad
2799 (_("unrecognized characters at end of parallel processing insn")));
2800 break;
2801 }
2802 }
2803
2804 move_code = movx | movy;
2805 if (field_b)
2806 {
2807 /* Parallel processing insn. */
2808 unsigned long ppi_code = (movx | movy | 0xf800) << 16 | field_b;
2809
2810 output = frag_more (4);
0d10e182 2811 size = 4;
d4845d57
JR		 2812 if (! target_big_endian)
2813 {
2814 output[3] = ppi_code >> 8;
2815 output[2] = ppi_code;
2816 }
2817 else
2818 {
2819 output[2] = ppi_code >> 8;
2820 output[3] = ppi_code;
2821 }
2822 move_code |= 0xf800;
2823 }
2824 else
0d10e182
JL		 2825 {
2826 /* Just a double data transfer. */
2827 output = frag_more (2);
2828 size = 2;
2829 }
d4845d57
JR		 2830 if (! target_big_endian)
2831 {
2832 output[1] = move_code >> 8;
2833 output[0] = move_code;
2834 }
2835 else
2836 {
2837 output[0] = move_code >> 8;
2838 output[1] = move_code;
2839 }
0d10e182 2840 return size;
d4845d57
JR		 2841}
2842
2843/* This is the guts of the machine-dependent assembler. STR points to a
2844 machine dependent instruction. This function is supposed to emit
6b31947e 2845 the frags/bytes it assembles to. */
d4845d57
JR		 2846
2847void
8edc77b9 2848md_assemble (char *str)
d4845d57 2849{
2132e3a3 2850 char *op_end;
d4845d57
JR		 2851 sh_operand_info operand[3];
2852 sh_opcode_info *opcode;
dda5ecfc 2853 unsigned int size = 0;
ae51a426 2854 char *initial_str = str;
d4845d57 2855
324bfcf3
AO		 2856#ifdef HAVE_SH64
2857 if (sh64_isa_mode == sh64_isa_shmedia)
2858 {
2859 shmedia_md_assemble (str);
2860 return;
2861 }
2862 else
2863 {
2864 /* If we've seen pseudo-directives, make sure any emitted data or
2865 frags are marked as data. */
b34976b6 2866 if (!seen_insn)
324bfcf3 2867 {
b34976b6 2868 sh64_update_contents_mark (TRUE);
324bfcf3
AO		 2869 sh64_set_contents_type (CRT_SH5_ISA16);
2870 }
2871
b34976b6 2872 seen_insn = TRUE;
324bfcf3
AO		 2873 }
2874#endif /* HAVE_SH64 */
2875
d4845d57
JR		 2876 opcode = find_cooked_opcode (&str);
2877 op_end = str;
252b5132
RH		 2878
2879 if (opcode == NULL)
2880 {
ae51a426 2881 /* The opcode is not in the hash table.
708587a4 2882 This means we definitely have an assembly failure,
ae51a426
JR		 2883 but the instruction may be valid in another CPU variant.
2884 In this case emit something better than 'unknown opcode'.
2885 Search the full table in sh-opc.h to check. */
2886
2887 char *name = initial_str;
2888 int name_length = 0;
2889 const sh_opcode_info *op;
2890 int found = 0;
2891
2892 /* identify opcode in string */
871ec896 2893 while (ISSPACE (*name))
ae51a426
JR		 2894 {
2895 name++;
2896 }
871ec896 2897 while (!ISSPACE (name[name_length]))
ae51a426
JR		 2898 {
2899 name_length++;
2900 }
2901
2902 /* search for opcode in full list */
2903 for (op = sh_table; op->name; op++)
2904 {
f6f9408f
JR		 2905 if (strncasecmp (op->name, name, name_length) == 0
2906 && op->name[name_length] == '\0')
ae51a426
JR		 2907 {
2908 found = 1;
2909 break;
2910 }
2911 }
2912
2913 if ( found )
2914 {
2915 as_bad (_("opcode not valid for this cpu variant"));
2916 }
2917 else
2918 {
2919 as_bad (_("unknown opcode"));
2920 }
252b5132
RH		 2921 return;
2922 }
2923
2924 if (sh_relax
2925 && ! seg_info (now_seg)->tc_segment_info_data.in_code)
2926 {
2927 /* Output a CODE reloc to tell the linker that the following
2928 bytes are instructions, not data. */
2929 fix_new (frag_now, frag_now_fix (), 2, &abs_symbol, 0, 0,
2930 BFD_RELOC_SH_CODE);
2931 seg_info (now_seg)->tc_segment_info_data.in_code = 1;
2932 }
2933
d4845d57
JR		 2934 if (opcode->nibbles[0] == PPI)
2935 {
0d10e182 2936 size = assemble_ppi (op_end, opcode);
252b5132
RH		 2937 }
2938 else
2939 {
0d10e182
JL		 2940 if (opcode->arg[0] == A_BDISP12
2941 || opcode->arg[0] == A_BDISP8)
252b5132 2942 {
26c9b704
JR		 2943 /* Since we skip get_specific here, we have to check & update
2944 valid_arch now. */
f6f9408f
JR		 2945 if (SH_MERGE_ARCH_SET_VALID (valid_arch, opcode->arch))
2946 valid_arch = SH_MERGE_ARCH_SET (valid_arch, opcode->arch);
26c9b704
JR		 2947 else
2948 as_bad (_("Delayed branches not available on SH1"));
0d10e182
JL		 2949 parse_exp (op_end + 1, &operand[0]);
2950 build_relax (opcode, &operand[0]);
86157c20
AS		 2951
2952 /* All branches are currently 16 bit. */
2953 size = 2;
5fc44b2d
JR		 2954 }
2955 else
2956 {
0d10e182
JL		 2957 if (opcode->arg[0] == A_END)
2958 {
2959 /* Ignore trailing whitespace. If there is any, it has already
2960 been compressed to a single space. */
2961 if (*op_end == ' ')
2962 op_end++;
2963 }
2964 else
2965 {
2966 op_end = get_operands (opcode, op_end, operand);
2967 }
2968 opcode = get_specific (opcode, operand);
252b5132 2969
0d10e182
JL		 2970 if (opcode == 0)
2971 {
2972 /* Couldn't find an opcode which matched the operands. */
2973 char *where = frag_more (2);
2974 size = 2;
252b5132 2975
0d10e182
JL		 2976 where[0] = 0x0;
2977 where[1] = 0x0;
2978 as_bad (_("invalid operands for opcode"));
2979 }
2980 else
2981 {
2982 if (*op_end)
2983 as_bad (_("excess operands: '%s'"), op_end);
2984
2985 size = build_Mytes (opcode, operand);
2986 }
252b5132 2987 }
0d10e182 2988 }
252b5132 2989
4dc7ead9 2990 dwarf2_emit_insn (size);
252b5132
RH		 2991}
2992
2993/* This routine is called each time a label definition is seen. It
2994 emits a BFD_RELOC_SH_LABEL reloc if necessary. */
2995
2996void
07a53e5c 2997sh_frob_label (symbolS *sym)
252b5132
RH		 2998{
2999 static fragS *last_label_frag;
3000 static int last_label_offset;
3001
3002 if (sh_relax
3003 && seg_info (now_seg)->tc_segment_info_data.in_code)
3004 {
3005 int offset;
3006
3007 offset = frag_now_fix ();
3008 if (frag_now != last_label_frag
3009 || offset != last_label_offset)
c4aa876b 3010 {
252b5132
RH		 3011 fix_new (frag_now, offset, 2, &abs_symbol, 0, 0, BFD_RELOC_SH_LABEL);
3012 last_label_frag = frag_now;
3013 last_label_offset = offset;
3014 }
3015 }
07a53e5c
RH		 3016
3017 dwarf2_emit_label (sym);
252b5132
RH		 3018}
3019
3020/* This routine is called when the assembler is about to output some
3021 data. It emits a BFD_RELOC_SH_DATA reloc if necessary. */
3022
3023void
8edc77b9 3024sh_flush_pending_output (void)
252b5132
RH		 3025{
3026 if (sh_relax
3027 && seg_info (now_seg)->tc_segment_info_data.in_code)
3028 {
3029 fix_new (frag_now, frag_now_fix (), 2, &abs_symbol, 0, 0,
3030 BFD_RELOC_SH_DATA);
3031 seg_info (now_seg)->tc_segment_info_data.in_code = 0;
3032 }
3033}
3034
3035symbolS *
8edc77b9 3036md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 3037{
3038 return 0;
3039}
3040
6b31947e
NC		 3041/* Various routines to kill one day. */
3042/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 3043#define MAX_LITTLENUMS 6
3044
6b31947e
NC		 3045/* Turn a string in input_line_pointer into a floating point constant
3046 of type TYPE, and store the appropriate bytes in *LITP. The number
3047 of LITTLENUMS emitted is stored in *SIZEP . An error message is
3048 returned, or NULL on OK. */
3049
252b5132 3050char *
8edc77b9 3051md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 3052{
3053 int prec;
3054 LITTLENUM_TYPE words[4];
3055 char *t;
3056 int i;
3057
3058 switch (type)
3059 {
3060 case 'f':
3061 prec = 2;
3062 break;
3063
3064 case 'd':
3065 prec = 4;
3066 break;
3067
3068 default:
3069 *sizeP = 0;
3070 return _("bad call to md_atof");
3071 }
3072
3073 t = atof_ieee (input_line_pointer, type, words);
3074 if (t)
3075 input_line_pointer = t;
3076
3077 *sizeP = prec * 2;
3078
3079 if (! target_big_endian)
3080 {
3081 for (i = prec - 1; i >= 0; i--)
3082 {
3083 md_number_to_chars (litP, (valueT) words[i], 2);
3084 litP += 2;
3085 }
3086 }
3087 else
3088 {
3089 for (i = 0; i < prec; i++)
3090 {
3091 md_number_to_chars (litP, (valueT) words[i], 2);
3092 litP += 2;
3093 }
3094 }
c4aa876b 3095
252b5132
RH		 3096 return NULL;
3097}
3098
3099/* Handle the .uses pseudo-op. This pseudo-op is used just before a
3100 call instruction. It refers to a label of the instruction which
3101 loads the register which the call uses. We use it to generate a
3102 special reloc for the linker. */
3103
3104static void
8edc77b9 3105s_uses (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3106{
3107 expressionS ex;
3108
3109 if (! sh_relax)
3110 as_warn (_(".uses pseudo-op seen when not relaxing"));
3111
3112 expression (&ex);
3113
3114 if (ex.X_op != O_symbol || ex.X_add_number != 0)
3115 {
3116 as_bad (_("bad .uses format"));
3117 ignore_rest_of_line ();
3118 return;
3119 }
3120
3121 fix_new_exp (frag_now, frag_now_fix (), 2, &ex, 1, BFD_RELOC_SH_USES);
3122
3123 demand_empty_rest_of_line ();
3124}
3125\f
37dedf66
NC		 3126enum options
3127{
3128 OPTION_RELAX = OPTION_MD_BASE,
3129 OPTION_BIG,
3130 OPTION_LITTLE,
3131 OPTION_SMALL,
3132 OPTION_DSP,
3133 OPTION_ISA,
3134 OPTION_RENESAS,
3135 OPTION_ALLOW_REG_PREFIX,
3136#ifdef HAVE_SH64
3137 OPTION_ABI,
3138 OPTION_NO_MIX,
3139 OPTION_SHCOMPACT_CONST_CRANGE,
3140 OPTION_NO_EXPAND,
3141 OPTION_PT32,
3142#endif
3143 OPTION_DUMMY /* Not used. This is just here to make it easy to add and subtract options from this enum. */
3144};
3145
5a38dc70 3146const char *md_shortopts = "";
6b31947e
NC		 3147struct option md_longopts[] =
3148{
252b5132 3149 {"relax", no_argument, NULL, OPTION_RELAX},
05982cac 3150 {"big", no_argument, NULL, OPTION_BIG},
252b5132 3151 {"little", no_argument, NULL, OPTION_LITTLE},
784906c5
NC		 3152 /* The next two switches are here because the
3153 generic parts of the linker testsuite uses them. */
3154 {"EB", no_argument, NULL, OPTION_BIG},
3155 {"EL", no_argument, NULL, OPTION_LITTLE},
252b5132 3156 {"small", no_argument, NULL, OPTION_SMALL},
d4845d57 3157 {"dsp", no_argument, NULL, OPTION_DSP},
37dedf66 3158 {"isa", required_argument, NULL, OPTION_ISA},
f55629b8 3159 {"renesas", no_argument, NULL, OPTION_RENESAS},
37dedf66 3160 {"allow-reg-prefix", no_argument, NULL, OPTION_ALLOW_REG_PREFIX},
f55629b8 3161
324bfcf3 3162#ifdef HAVE_SH64
324bfcf3
AO		 3163 {"abi", required_argument, NULL, OPTION_ABI},
3164 {"no-mix", no_argument, NULL, OPTION_NO_MIX},
3165 {"shcompact-const-crange", no_argument, NULL, OPTION_SHCOMPACT_CONST_CRANGE},
3166 {"no-expand", no_argument, NULL, OPTION_NO_EXPAND},
3167 {"expand-pt32", no_argument, NULL, OPTION_PT32},
3168#endif /* HAVE_SH64 */
3169
252b5132
RH		 3170 {NULL, no_argument, NULL, 0}
3171};
c4aa876b 3172size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 3173
3174int
8edc77b9 3175md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
252b5132
RH		 3176{
3177 switch (c)
3178 {
3179 case OPTION_RELAX:
3180 sh_relax = 1;
3181 break;
3182
05982cac
HPN		 3183 case OPTION_BIG:
3184 target_big_endian = 1;
3185 break;
3186
252b5132 3187 case OPTION_LITTLE:
252b5132
RH		 3188 target_big_endian = 0;
3189 break;
3190
3191 case OPTION_SMALL:
3192 sh_small = 1;
3193 break;
3194
d4845d57 3195 case OPTION_DSP:
e38bc3b5 3196 preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
d4845d57
JR		 3197 break;
3198
f55629b8
KK		 3199 case OPTION_RENESAS:
3200 dont_adjust_reloc_32 = 1;
3201 break;
3202
37dedf66
NC		 3203 case OPTION_ALLOW_REG_PREFIX:
3204 allow_dollar_register_prefix = 1;
3205 break;
3206
324bfcf3 3207 case OPTION_ISA:
871ec896 3208 if (strcasecmp (arg, "dsp") == 0)
e38bc3b5 3209 preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
88da98f3 3210 else if (strcasecmp (arg, "fp") == 0)
e38bc3b5 3211 preset_target_arch = arch_sh_up & ~arch_sh_has_dsp;
bdfaef52 3212 else if (strcasecmp (arg, "any") == 0)
e38bc3b5 3213 preset_target_arch = arch_sh_up;
bdfaef52
JR		 3214#ifdef HAVE_SH64
3215 else if (strcasecmp (arg, "shmedia") == 0)
324bfcf3
AO		 3216 {
3217 if (sh64_isa_mode == sh64_isa_shcompact)
3218 as_bad (_("Invalid combination: --isa=SHcompact with --isa=SHmedia"));
3219 sh64_isa_mode = sh64_isa_shmedia;
3220 }
3221 else if (strcasecmp (arg, "shcompact") == 0)
3222 {
3223 if (sh64_isa_mode == sh64_isa_shmedia)
3224 as_bad (_("Invalid combination: --isa=SHmedia with --isa=SHcompact"));
3225 if (sh64_abi == sh64_abi_64)
3226 as_bad (_("Invalid combination: --abi=64 with --isa=SHcompact"));
3227 sh64_isa_mode = sh64_isa_shcompact;
3228 }
bdfaef52 3229#endif /* HAVE_SH64 */
324bfcf3 3230 else
f6f9408f
JR		 3231 {
3232 extern const bfd_arch_info_type bfd_sh_arch;
871ec896 3233 bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
37dedf66 3234
f6f9408f
JR		 3235 preset_target_arch = 0;
3236 for (; bfd_arch; bfd_arch=bfd_arch->next)
3237 {
3238 int len = strlen(bfd_arch->printable_name);
3239
3240 if (bfd_arch->mach == bfd_mach_sh5)
3241 continue;
3242
3243 if (strncasecmp (bfd_arch->printable_name, arg, len) != 0)
3244 continue;
3245
3246 if (arg[len] == '\0')
3247 preset_target_arch =
3248 sh_get_arch_from_bfd_mach (bfd_arch->mach);
3249 else if (strcasecmp(&arg[len], "-up") == 0)
3250 preset_target_arch =
3251 sh_get_arch_up_from_bfd_mach (bfd_arch->mach);
3252 else
3253 continue;
3254 break;
3255 }
3256
3257 if (!preset_target_arch)
3258 as_bad ("Invalid argument to --isa option: %s", arg);
3259 }
324bfcf3
AO		 3260 break;
3261
bdfaef52 3262#ifdef HAVE_SH64
324bfcf3
AO		 3263 case OPTION_ABI:
3264 if (strcmp (arg, "32") == 0)
3265 {
3266 if (sh64_abi == sh64_abi_64)
3267 as_bad (_("Invalid combination: --abi=32 with --abi=64"));
3268 sh64_abi = sh64_abi_32;
3269 }
3270 else if (strcmp (arg, "64") == 0)
3271 {
3272 if (sh64_abi == sh64_abi_32)
3273 as_bad (_("Invalid combination: --abi=64 with --abi=32"));
3274 if (sh64_isa_mode == sh64_isa_shcompact)
3275 as_bad (_("Invalid combination: --isa=SHcompact with --abi=64"));
3276 sh64_abi = sh64_abi_64;
3277 }
3278 else
3279 as_bad ("Invalid argument to --abi option: %s", arg);
3280 break;
3281
3282 case OPTION_NO_MIX:
b34976b6 3283 sh64_mix = FALSE;
324bfcf3
AO		 3284 break;
3285
3286 case OPTION_SHCOMPACT_CONST_CRANGE:
b34976b6 3287 sh64_shcompact_const_crange = TRUE;
324bfcf3
AO		 3288 break;
3289
3290 case OPTION_NO_EXPAND:
b34976b6 3291 sh64_expand = FALSE;
324bfcf3
AO		 3292 break;
3293
3294 case OPTION_PT32:
b34976b6 3295 sh64_pt32 = TRUE;
324bfcf3
AO		 3296 break;
3297#endif /* HAVE_SH64 */
3298
252b5132
RH		 3299 default:
3300 return 0;
3301 }
3302
3303 return 1;
3304}
3305
3306void
8edc77b9 3307md_show_usage (FILE *stream)
252b5132 3308{
c4aa876b 3309 fprintf (stream, _("\
252b5132 3310SH options:\n\
37dedf66
NC		 3311--little generate little endian code\n\
3312--big generate big endian code\n\
3313--relax alter jump instructions for long displacements\n\
3314--renesas disable optimization with section symbol for\n\
f55629b8 3315 compatibility with Renesas assembler.\n\
37dedf66
NC		 3316--small align sections to 4 byte boundaries, not 16\n\
3317--dsp enable sh-dsp insns, and disable floating-point ISAs.\n\
3318--allow-reg-prefix allow '$' as a register name prefix.\n\
3319--isa=[any use most appropriate isa\n\
ae51a426 3320 | dsp same as '-dsp'\n\
f6f9408f
JR		 3321 | fp"));
3322 {
3323 extern const bfd_arch_info_type bfd_sh_arch;
871ec896 3324 bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
37dedf66 3325
f6f9408f
JR		 3326 for (; bfd_arch; bfd_arch=bfd_arch->next)
3327 if (bfd_arch->mach != bfd_mach_sh5)
3328 {
3329 fprintf (stream, "\n | %s", bfd_arch->printable_name);
3330 fprintf (stream, "\n | %s-up", bfd_arch->printable_name);
3331 }
3332 }
3333 fprintf (stream, "]\n");
ae51a426
JR		 3334#ifdef HAVE_SH64
3335 fprintf (stream, _("\
37dedf66 3336--isa=[shmedia set as the default instruction set for SH64\n\
88da98f3
MS		 3337 | SHmedia\n\
3338 | shcompact\n\
ae51a426 3339 | SHcompact]\n"));
324bfcf3 3340 fprintf (stream, _("\
37dedf66 3341--abi=[32|64] set size of expanded SHmedia operands and object\n\
324bfcf3 3342 file type\n\
37dedf66 3343--shcompact-const-crange emit code-range descriptors for constants in\n\
324bfcf3 3344 SHcompact code sections\n\
37dedf66 3345--no-mix disallow SHmedia code in the same section as\n\
324bfcf3 3346 constants and SHcompact code\n\
37dedf66
NC		 3347--no-expand do not expand MOVI, PT, PTA or PTB instructions\n\
3348--expand-pt32 with -abi=64, expand PT, PTA and PTB instructions\n\
2acb89ed 3349 to 32 bits only\n"));
324bfcf3 3350#endif /* HAVE_SH64 */
252b5132
RH		 3351}
3352\f
252b5132
RH		 3353/* This struct is used to pass arguments to sh_count_relocs through
3354 bfd_map_over_sections. */
3355
3356struct sh_count_relocs
3357{
3358 /* Symbol we are looking for. */
3359 symbolS *sym;
3360 /* Count of relocs found. */
3361 int count;
3362};
3363
3364/* Count the number of fixups in a section which refer to a particular
7be1c489 3365 symbol. This is called via bfd_map_over_sections. */
252b5132 3366
252b5132 3367static void
8edc77b9 3368sh_count_relocs (bfd *abfd ATTRIBUTE_UNUSED, segT sec, void *data)
252b5132
RH		 3369{
3370 struct sh_count_relocs *info = (struct sh_count_relocs *) data;
3371 segment_info_type *seginfo;
3372 symbolS *sym;
3373 fixS *fix;
3374
3375 seginfo = seg_info (sec);
3376 if (seginfo == NULL)
3377 return;
3378
3379 sym = info->sym;
3380 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
3381 {
3382 if (fix->fx_addsy == sym)
3383 {
3384 ++info->count;
3385 fix->fx_tcbit = 1;
3386 }
3387 }
3388}
3389
7be1c489
AM		 3390/* Handle the count relocs for a particular section.
3391 This is called via bfd_map_over_sections. */
252b5132 3392
252b5132 3393static void
8edc77b9
KK		 3394sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
3395 void *ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3396{
3397 segment_info_type *seginfo;
3398 fixS *fix;
3399
3400 seginfo = seg_info (sec);
3401 if (seginfo == NULL)
3402 return;
3403
e14e52f8
DD		 3404 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
3405 {
3406 symbolS *sym;
3407
3408 sym = fix->fx_addsy;
3409 /* Check for a local_symbol. */
3410 if (sym && sym->bsym == NULL)
3411 {
3412 struct local_symbol *ls = (struct local_symbol *)sym;
3413 /* See if it's been converted. If so, canonicalize. */
3414 if (local_symbol_converted_p (ls))
3415 fix->fx_addsy = local_symbol_get_real_symbol (ls);
3416 }
3417 }
3418
252b5132
RH		 3419 for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
3420 {
3421 symbolS *sym;
3422 bfd_vma val;
3423 fixS *fscan;
3424 struct sh_count_relocs info;
3425
3426 if (fix->fx_r_type != BFD_RELOC_SH_USES)
3427 continue;
3428
3429 /* The BFD_RELOC_SH_USES reloc should refer to a defined local
3430 symbol in the same section. */
3431 sym = fix->fx_addsy;
3432 if (sym == NULL
3433 || fix->fx_subsy != NULL
3434 || fix->fx_addnumber != 0
3435 || S_GET_SEGMENT (sym) != sec
252b5132
RH		 3436 || S_IS_EXTERNAL (sym))
3437 {
3438 as_warn_where (fix->fx_file, fix->fx_line,
3439 _(".uses does not refer to a local symbol in the same section"));
3440 continue;
3441 }
3442
3443 /* Look through the fixups again, this time looking for one
3444 at the same location as sym. */
3445 val = S_GET_VALUE (sym);
3446 for (fscan = seginfo->fix_root;
3447 fscan != NULL;
3448 fscan = fscan->fx_next)
3449 if (val == fscan->fx_frag->fr_address + fscan->fx_where
3450 && fscan->fx_r_type != BFD_RELOC_SH_ALIGN
3451 && fscan->fx_r_type != BFD_RELOC_SH_CODE
3452 && fscan->fx_r_type != BFD_RELOC_SH_DATA
3453 && fscan->fx_r_type != BFD_RELOC_SH_LABEL)
3454 break;
3455 if (fscan == NULL)
3456 {
3457 as_warn_where (fix->fx_file, fix->fx_line,
3458 _("can't find fixup pointed to by .uses"));
3459 continue;
3460 }
3461
3462 if (fscan->fx_tcbit)
3463 {
3464 /* We've already done this one. */
3465 continue;
3466 }
3467
6b31947e
NC		 3468 /* The variable fscan should also be a fixup to a local symbol
3469 in the same section. */
252b5132
RH		 3470 sym = fscan->fx_addsy;
3471 if (sym == NULL
3472 || fscan->fx_subsy != NULL
3473 || fscan->fx_addnumber != 0
3474 || S_GET_SEGMENT (sym) != sec
252b5132
RH		 3475 || S_IS_EXTERNAL (sym))
3476 {
3477 as_warn_where (fix->fx_file, fix->fx_line,
3478 _(".uses target does not refer to a local symbol in the same section"));
3479 continue;
3480 }
3481
3482 /* Now we look through all the fixups of all the sections,
3483 counting the number of times we find a reference to sym. */
3484 info.sym = sym;
3485 info.count = 0;
8edc77b9 3486 bfd_map_over_sections (stdoutput, sh_count_relocs, &info);
252b5132
RH		 3487
3488 if (info.count < 1)
3489 abort ();
3490
3491 /* Generate a BFD_RELOC_SH_COUNT fixup at the location of sym.
3492 We have already adjusted the value of sym to include the
3493 fragment address, so we undo that adjustment here. */
3494 subseg_change (sec, 0);
7bcad3e5
NC		 3495 fix_new (fscan->fx_frag,
3496 S_GET_VALUE (sym) - fscan->fx_frag->fr_address,
252b5132
RH		 3497 4, &abs_symbol, info.count, 0, BFD_RELOC_SH_COUNT);
3498 }
3499}
3500
3501/* This function is called after the symbol table has been completed,
3502 but before the relocs or section contents have been written out.
3503 If we have seen any .uses pseudo-ops, they point to an instruction
3504 which loads a register with the address of a function. We look
3505 through the fixups to find where the function address is being
3506 loaded from. We then generate a COUNT reloc giving the number of
3507 times that function address is referred to. The linker uses this
3508 information when doing relaxing, to decide when it can eliminate
3509 the stored function address entirely. */
3510
3511void
8edc77b9 3512sh_frob_file (void)
252b5132 3513{
324bfcf3
AO		 3514#ifdef HAVE_SH64
3515 shmedia_frob_file_before_adjust ();
3516#endif
3517
252b5132
RH		 3518 if (! sh_relax)
3519 return;
3520
8edc77b9 3521 bfd_map_over_sections (stdoutput, sh_frob_section, NULL);
252b5132
RH		 3522}
3523
3524/* Called after relaxing. Set the correct sizes of the fragments, and
55cf6793 3525 create relocs so that md_apply_fix will fill in the correct values. */
252b5132
RH		 3526
3527void
8edc77b9 3528md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT seg, fragS *fragP)
252b5132
RH		 3529{
3530 int donerelax = 0;
3531
3532 switch (fragP->fr_subtype)
3533 {
3534 case C (COND_JUMP, COND8):
3535 case C (COND_JUMP_DELAY, COND8):
3536 subseg_change (seg, 0);
3537 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
3538 1, BFD_RELOC_SH_PCDISP8BY2);
3539 fragP->fr_fix += 2;
3540 fragP->fr_var = 0;
3541 break;
3542
3543 case C (UNCOND_JUMP, UNCOND12):
3544 subseg_change (seg, 0);
3545 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
3546 1, BFD_RELOC_SH_PCDISP12BY2);
3547 fragP->fr_fix += 2;
3548 fragP->fr_var = 0;
3549 break;
3550
3551 case C (UNCOND_JUMP, UNCOND32):
3552 case C (UNCOND_JUMP, UNDEF_WORD_DISP):
3553 if (fragP->fr_symbol == NULL)
99b222b4
HPN		 3554 as_bad_where (fragP->fr_file, fragP->fr_line,
3555 _("displacement overflows 12-bit field"));
252b5132 3556 else if (S_IS_DEFINED (fragP->fr_symbol))
99b222b4
HPN		 3557 as_bad_where (fragP->fr_file, fragP->fr_line,
3558 _("displacement to defined symbol %s overflows 12-bit field"),
3559 S_GET_NAME (fragP->fr_symbol));
252b5132 3560 else
99b222b4
HPN		 3561 as_bad_where (fragP->fr_file, fragP->fr_line,
3562 _("displacement to undefined symbol %s overflows 12-bit field"),
3563 S_GET_NAME (fragP->fr_symbol));
3564 /* Stabilize this frag, so we don't trip an assert. */
3565 fragP->fr_fix += fragP->fr_var;
3566 fragP->fr_var = 0;
252b5132
RH		 3567 break;
3568
3569 case C (COND_JUMP, COND12):
3570 case C (COND_JUMP_DELAY, COND12):
6b31947e 3571 /* A bcond won't fit, so turn it into a b!cond; bra disp; nop. */
252b5132
RH		 3572 /* I found that a relax failure for gcc.c-torture/execute/930628-1.c
3573 was due to gas incorrectly relaxing an out-of-range conditional
3574 branch with delay slot. It turned:
3575 bf.s L6 (slot mov.l r12,@(44,r0))
3576 into:
c4aa876b 3577
252b5132
RH		 35782c: 8f 01 a0 8b bf.s 32 <_main+32> (slot bra L6)
357930: 00 09 nop
358032: 10 cb mov.l r12,@(44,r0)
3581 Therefore, branches with delay slots have to be handled
3582 differently from ones without delay slots. */
3583 {
3584 unsigned char *buffer =
3585 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
3586 int highbyte = target_big_endian ? 0 : 1;
3587 int lowbyte = target_big_endian ? 1 : 0;
3588 int delay = fragP->fr_subtype == C (COND_JUMP_DELAY, COND12);
3589
3590 /* Toggle the true/false bit of the bcond. */
3591 buffer[highbyte] ^= 0x2;
3592
d3ecfc59 3593 /* If this is a delayed branch, we may not put the bra in the
252b5132
RH		 3594 slot. So we change it to a non-delayed branch, like that:
3595 b! cond slot_label; bra disp; slot_label: slot_insn
3596 ??? We should try if swapping the conditional branch and
3597 its delay-slot insn already makes the branch reach. */
3598
3599 /* Build a relocation to six / four bytes farther on. */
3600 subseg_change (seg, 0);
7be1c489 3601 fix_new (fragP, fragP->fr_fix, 2, section_symbol (seg),
252b5132
RH		 3602 fragP->fr_address + fragP->fr_fix + (delay ? 4 : 6),
3603 1, BFD_RELOC_SH_PCDISP8BY2);
3604
3605 /* Set up a jump instruction. */
3606 buffer[highbyte + 2] = 0xa0;
3607 buffer[lowbyte + 2] = 0;
3608 fix_new (fragP, fragP->fr_fix + 2, 2, fragP->fr_symbol,
3609 fragP->fr_offset, 1, BFD_RELOC_SH_PCDISP12BY2);
3610
3611 if (delay)
3612 {
3613 buffer[highbyte] &= ~0x4; /* Removes delay slot from branch. */
3614 fragP->fr_fix += 4;
3615 }
3616 else
3617 {
3618 /* Fill in a NOP instruction. */
3619 buffer[highbyte + 4] = 0x0;
3620 buffer[lowbyte + 4] = 0x9;
3621
3622 fragP->fr_fix += 6;
3623 }
3624 fragP->fr_var = 0;
3625 donerelax = 1;
3626 }
3627 break;
3628
3629 case C (COND_JUMP, COND32):
3630 case C (COND_JUMP_DELAY, COND32):
3631 case C (COND_JUMP, UNDEF_WORD_DISP):
3632 case C (COND_JUMP_DELAY, UNDEF_WORD_DISP):
3633 if (fragP->fr_symbol == NULL)
99b222b4
HPN		 3634 as_bad_where (fragP->fr_file, fragP->fr_line,
3635 _("displacement overflows 8-bit field"));
252b5132 3636 else if (S_IS_DEFINED (fragP->fr_symbol))
99b222b4
HPN		 3637 as_bad_where (fragP->fr_file, fragP->fr_line,
3638 _("displacement to defined symbol %s overflows 8-bit field"),
3639 S_GET_NAME (fragP->fr_symbol));
252b5132 3640 else
99b222b4
HPN		 3641 as_bad_where (fragP->fr_file, fragP->fr_line,
3642 _("displacement to undefined symbol %s overflows 8-bit field "),
3643 S_GET_NAME (fragP->fr_symbol));
3644 /* Stabilize this frag, so we don't trip an assert. */
3645 fragP->fr_fix += fragP->fr_var;
3646 fragP->fr_var = 0;
252b5132
RH		 3647 break;
3648
3649 default:
324bfcf3 3650#ifdef HAVE_SH64
b34976b6 3651 shmedia_md_convert_frag (headers, seg, fragP, TRUE);
324bfcf3 3652#else
252b5132 3653 abort ();
324bfcf3 3654#endif
252b5132
RH		 3655 }
3656
3657 if (donerelax && !sh_relax)
3658 as_warn_where (fragP->fr_file, fragP->fr_line,
3659 _("overflow in branch to %s; converted into longer instruction sequence"),
3660 (fragP->fr_symbol != NULL
3661 ? S_GET_NAME (fragP->fr_symbol)
3662 : ""));
3663}
3664
3665valueT
8edc77b9 3666md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size)
252b5132 3667{
252b5132
RH		 3668#ifdef OBJ_ELF
3669 return size;
3670#else /* ! OBJ_ELF */
3671 return ((size + (1 << bfd_get_section_alignment (stdoutput, seg)) - 1)
3672 & (-1 << bfd_get_section_alignment (stdoutput, seg)));
3673#endif /* ! OBJ_ELF */
252b5132
RH		 3674}
3675
3676/* This static variable is set by s_uacons to tell sh_cons_align that
67c1ffbe 3677 the expression does not need to be aligned. */
252b5132
RH		 3678
3679static int sh_no_align_cons = 0;
3680
3681/* This handles the unaligned space allocation pseudo-ops, such as
3682 .uaword. .uaword is just like .word, but the value does not need
3683 to be aligned. */
3684
3685static void
8edc77b9 3686s_uacons (int bytes)
252b5132
RH		 3687{
3688 /* Tell sh_cons_align not to align this value. */
3689 sh_no_align_cons = 1;
3690 cons (bytes);
3691}
3692
3693/* If a .word, et. al., pseud-op is seen, warn if the value is not
3694 aligned correctly. Note that this can cause warnings to be issued
3695 when assembling initialized structured which were declared with the
3696 packed attribute. FIXME: Perhaps we should require an option to
3697 enable this warning? */
3698
3699void
8edc77b9 3700sh_cons_align (int nbytes)
252b5132
RH		 3701{
3702 int nalign;
3703 char *p;
3704
3705 if (sh_no_align_cons)
3706 {
3707 /* This is an unaligned pseudo-op. */
3708 sh_no_align_cons = 0;
3709 return;
3710 }
3711
3712 nalign = 0;
3713 while ((nbytes & 1) == 0)
3714 {
3715 ++nalign;
3716 nbytes >>= 1;
3717 }
3718
3719 if (nalign == 0)
3720 return;
3721
3722 if (now_seg == absolute_section)
3723 {
3724 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3725 as_warn (_("misaligned data"));
3726 return;
3727 }
3728
0a9ef439 3729 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
252b5132
RH		 3730 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3731
3732 record_alignment (now_seg, nalign);
3733}
3734
3735/* When relaxing, we need to output a reloc for any .align directive
3736 that requests alignment to a four byte boundary or larger. This is
3737 also where we check for misaligned data. */
3738
3739void
8edc77b9 3740sh_handle_align (fragS *frag)
252b5132 3741{
0a9ef439
RH		 3742 int bytes = frag->fr_next->fr_address - frag->fr_address - frag->fr_fix;
3743
3744 if (frag->fr_type == rs_align_code)
3745 {
3746 static const unsigned char big_nop_pattern[] = { 0x00, 0x09 };
3747 static const unsigned char little_nop_pattern[] = { 0x09, 0x00 };
3748
3749 char *p = frag->fr_literal + frag->fr_fix;
3750
3751 if (bytes & 1)
3752 {
3753 *p++ = 0;
3754 bytes--;
3755 frag->fr_fix += 1;
3756 }
3757
3758 if (target_big_endian)
3759 {
3760 memcpy (p, big_nop_pattern, sizeof big_nop_pattern);
3761 frag->fr_var = sizeof big_nop_pattern;
3762 }
3763 else
3764 {
3765 memcpy (p, little_nop_pattern, sizeof little_nop_pattern);
3766 frag->fr_var = sizeof little_nop_pattern;
3767 }
3768 }
3769 else if (frag->fr_type == rs_align_test)
3770 {
3771 if (bytes != 0)
3772 as_warn_where (frag->fr_file, frag->fr_line, _("misaligned data"));
3773 }
3774
252b5132 3775 if (sh_relax
0a9ef439
RH		 3776 && (frag->fr_type == rs_align
3777 || frag->fr_type == rs_align_code)
252b5132
RH		 3778 && frag->fr_address + frag->fr_fix > 0
3779 && frag->fr_offset > 1
3780 && now_seg != bss_section)
3781 fix_new (frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset, 0,
3782 BFD_RELOC_SH_ALIGN);
252b5132
RH		 3783}
3784
28602ebf
KK		 3785/* See whether the relocation should be resolved locally. */
3786
b34976b6 3787static bfd_boolean
8edc77b9 3788sh_local_pcrel (fixS *fix)
28602ebf 3789{
b34976b6
AM		 3790 return (! sh_relax
3791 && (fix->fx_r_type == BFD_RELOC_SH_PCDISP8BY2
3792 || fix->fx_r_type == BFD_RELOC_SH_PCDISP12BY2
3793 || fix->fx_r_type == BFD_RELOC_SH_PCRELIMM8BY2
3794 || fix->fx_r_type == BFD_RELOC_SH_PCRELIMM8BY4
3795 || fix->fx_r_type == BFD_RELOC_8_PCREL
3796 || fix->fx_r_type == BFD_RELOC_SH_SWITCH16
3797 || fix->fx_r_type == BFD_RELOC_SH_SWITCH32));
28602ebf
KK		 3798}
3799
252b5132
RH		 3800/* See whether we need to force a relocation into the output file.
3801 This is used to force out switch and PC relative relocations when
3802 relaxing. */
3803
3804int
8edc77b9 3805sh_force_relocation (fixS *fix)
252b5132 3806{
8ba4dac0
DJ		 3807 /* These relocations can't make it into a DSO, so no use forcing
3808 them for global symbols. */
28602ebf 3809 if (sh_local_pcrel (fix))
8ba4dac0
DJ		 3810 return 0;
3811
9efb3b7b 3812 /* Make sure some relocations get emitted. */
ae6063d4 3813 if (fix->fx_r_type == BFD_RELOC_SH_LOOP_START
a161fe53 3814 || fix->fx_r_type == BFD_RELOC_SH_LOOP_END
9efb3b7b
KK		 3815 || fix->fx_r_type == BFD_RELOC_SH_TLS_GD_32
3816 || fix->fx_r_type == BFD_RELOC_SH_TLS_LD_32
3817 || fix->fx_r_type == BFD_RELOC_SH_TLS_IE_32
3818 || fix->fx_r_type == BFD_RELOC_SH_TLS_LDO_32
3819 || fix->fx_r_type == BFD_RELOC_SH_TLS_LE_32
ae6063d4 3820 || generic_force_reloc (fix))
252b5132
RH		 3821 return 1;
3822
3823 if (! sh_relax)
3824 return 0;
3825
3826 return (fix->fx_pcrel
3827 || SWITCH_TABLE (fix)
3828 || fix->fx_r_type == BFD_RELOC_SH_COUNT
3829 || fix->fx_r_type == BFD_RELOC_SH_ALIGN
3830 || fix->fx_r_type == BFD_RELOC_SH_CODE
3831 || fix->fx_r_type == BFD_RELOC_SH_DATA
324bfcf3
AO		 3832#ifdef HAVE_SH64
3833 || fix->fx_r_type == BFD_RELOC_SH_SHMEDIA_CODE
3834#endif
252b5132
RH		 3835 || fix->fx_r_type == BFD_RELOC_SH_LABEL);
3836}
3837
3838#ifdef OBJ_ELF
b34976b6 3839bfd_boolean
8edc77b9 3840sh_fix_adjustable (fixS *fixP)
252b5132 3841{
a161fe53
AM		 3842 if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
3843 || fixP->fx_r_type == BFD_RELOC_32_GOT_PCREL
3844 || fixP->fx_r_type == BFD_RELOC_SH_GOTPC
f55629b8 3845 || ((fixP->fx_r_type == BFD_RELOC_32) && dont_adjust_reloc_32)
a1cc9221
AO		 3846 || fixP->fx_r_type == BFD_RELOC_RVA)
3847 return 0;
3848
252b5132
RH		 3849 /* We need the symbol name for the VTABLE entries */
3850 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3851 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3852 return 0;
3853
3854 return 1;
3855}
d4845d57 3856
6b31947e 3857void
8edc77b9 3858sh_elf_final_processing (void)
d4845d57
JR		 3859{
3860 int val;
3861
3862 /* Set file-specific flags to indicate if this code needs
88da98f3 3863 a processor with the sh-dsp / sh2e ISA to execute. */
324bfcf3
AO		 3864#ifdef HAVE_SH64
3865 /* SH5 and above don't know about the valid_arch arch_sh* bits defined
3866 in sh-opc.h, so check SH64 mode before checking valid_arch. */
3867 if (sh64_isa_mode != sh64_isa_unspecified)
3868 val = EF_SH5;
3869 else
1a320fbb
NC		 3870#elif defined TARGET_SYMBIAN
3871 if (1)
1a66a017
NC		 3872 {
3873 extern int sh_symbian_find_elf_flags (unsigned int);
3874
3875 val = sh_symbian_find_elf_flags (valid_arch);
3876 }
1a320fbb 3877 else
324bfcf3 3878#endif /* HAVE_SH64 */
f6f9408f 3879 val = sh_find_elf_flags (valid_arch);
d4845d57
JR		 3880
3881 elf_elfheader (stdoutput)->e_flags &= ~EF_SH_MACH_MASK;
3882 elf_elfheader (stdoutput)->e_flags |= val;
3883}
252b5132
RH		 3884#endif
3885
55e6e397
RS		 3886/* Apply fixup FIXP to SIZE-byte field BUF given that VAL is its
3887 assembly-time value. If we're generating a reloc for FIXP,
3888 see whether the addend should be stored in-place or whether
3889 it should be in an ELF r_addend field. */
3890
3891static void
3892apply_full_field_fix (fixS *fixP, char *buf, bfd_vma val, int size)
3893{
3894 reloc_howto_type *howto;
3895
3896 if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
3897 {
3898 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
3899 if (howto && !howto->partial_inplace)
3900 {
3901 fixP->fx_addnumber = val;
3902 return;
3903 }
3904 }
3905 md_number_to_chars (buf, val, size);
3906}
3907
252b5132
RH		 3908/* Apply a fixup to the object file. */
3909
252b5132 3910void
55cf6793 3911md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132
RH		 3912{
3913 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3914 int lowbyte = target_big_endian ? 1 : 0;
3915 int highbyte = target_big_endian ? 0 : 1;
2ed5f585 3916 long val = (long) *valP;
252b5132
RH		 3917 long max, min;
3918 int shift;
3919
a1cc9221
AO		 3920 /* A difference between two symbols, the second of which is in the
3921 current section, is transformed in a PC-relative relocation to
3922 the other symbol. We have to adjust the relocation type here. */
3923 if (fixP->fx_pcrel)
3924 {
3925 switch (fixP->fx_r_type)
3926 {
3927 default:
3928 break;
3929
3930 case BFD_RELOC_32:
3931 fixP->fx_r_type = BFD_RELOC_32_PCREL;
3932 break;
3933
3934 /* Currently, we only support 32-bit PCREL relocations.
3935 We'd need a new reloc type to handle 16_PCREL, and
3936 8_PCREL is already taken for R_SH_SWITCH8, which
3937 apparently does something completely different than what
3938 we need. FIXME. */
3939 case BFD_RELOC_16:
3940 bfd_set_error (bfd_error_bad_value);
94f592af 3941 return;
81d4177b 3942
a1cc9221
AO		 3943 case BFD_RELOC_8:
3944 bfd_set_error (bfd_error_bad_value);
94f592af 3945 return;
a1cc9221
AO		 3946 }
3947 }
3948
6b31947e
NC		 3949 /* The function adjust_reloc_syms won't convert a reloc against a weak
3950 symbol into a reloc against a section, but bfd_install_relocation
3951 will screw up if the symbol is defined, so we have to adjust val here
1308f14c
HPN		 3952 to avoid the screw up later.
3953
3954 For ordinary relocs, this does not happen for ELF, since for ELF,
3955 bfd_install_relocation uses the "special function" field of the
3956 howto, and does not execute the code that needs to be undone, as long
3957 as the special function does not return bfd_reloc_continue.
3958 It can happen for GOT- and PLT-type relocs the way they are
3959 described in elf32-sh.c as they use bfd_elf_generic_reloc, but it
3960 doesn't matter here since those relocs don't use VAL; see below. */
3961 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
3962 && fixP->fx_addsy != NULL
252b5132
RH		 3963 && S_IS_WEAK (fixP->fx_addsy))
3964 val -= S_GET_VALUE (fixP->fx_addsy);
252b5132 3965
bdfaef52
JR		 3966 if (SWITCH_TABLE (fixP))
3967 val -= S_GET_VALUE (fixP->fx_subsy);
252b5132
RH		 3968
3969 max = min = 0;
3970 shift = 0;
3971 switch (fixP->fx_r_type)
3972 {
1d70c7fb
AO		 3973 case BFD_RELOC_SH_IMM3:
3974 max = 0x7;
3975 * buf = (* buf & 0xf8) | (val & 0x7);
3976 break;
3977 case BFD_RELOC_SH_IMM3U:
3978 max = 0x7;
3979 * buf = (* buf & 0x8f) | ((val & 0x7) << 4);
3980 break;
3981 case BFD_RELOC_SH_DISP12:
3982 max = 0xfff;
3983 buf[lowbyte] = val & 0xff;
3984 buf[highbyte] |= (val >> 8) & 0x0f;
3985 break;
3986 case BFD_RELOC_SH_DISP12BY2:
3987 max = 0xfff;
3988 shift = 1;
3989 buf[lowbyte] = (val >> 1) & 0xff;
3990 buf[highbyte] |= (val >> 9) & 0x0f;
3991 break;
3992 case BFD_RELOC_SH_DISP12BY4:
3993 max = 0xfff;
3994 shift = 2;
3995 buf[lowbyte] = (val >> 2) & 0xff;
3996 buf[highbyte] |= (val >> 10) & 0x0f;
3997 break;
3998 case BFD_RELOC_SH_DISP12BY8:
3999 max = 0xfff;
4000 shift = 3;
4001 buf[lowbyte] = (val >> 3) & 0xff;
4002 buf[highbyte] |= (val >> 11) & 0x0f;
4003 break;
4004 case BFD_RELOC_SH_DISP20:
4005 if (! target_big_endian)
4006 abort();
4007 max = 0x7ffff;
4008 min = -0x80000;
28013b5c 4009 buf[1] = (buf[1] & 0x0f) | ((val >> 12) & 0xf0);
1d70c7fb
AO		 4010 buf[2] = (val >> 8) & 0xff;
4011 buf[3] = val & 0xff;
4012 break;
4013 case BFD_RELOC_SH_DISP20BY8:
4014 if (!target_big_endian)
4015 abort();
4016 max = 0x7ffff;
4017 min = -0x80000;
4018 shift = 8;
28013b5c 4019 buf[1] = (buf[1] & 0x0f) | ((val >> 20) & 0xf0);
1d70c7fb
AO		 4020 buf[2] = (val >> 16) & 0xff;
4021 buf[3] = (val >> 8) & 0xff;
4022 break;
4023
252b5132
RH		 4024 case BFD_RELOC_SH_IMM4:
4025 max = 0xf;
4026 *buf = (*buf & 0xf0) | (val & 0xf);
4027 break;
4028
4029 case BFD_RELOC_SH_IMM4BY2:
4030 max = 0xf;
4031 shift = 1;
4032 *buf = (*buf & 0xf0) | ((val >> 1) & 0xf);
4033 break;
4034
4035 case BFD_RELOC_SH_IMM4BY4:
4036 max = 0xf;
4037 shift = 2;
4038 *buf = (*buf & 0xf0) | ((val >> 2) & 0xf);
4039 break;
4040
4041 case BFD_RELOC_SH_IMM8BY2:
4042 max = 0xff;
4043 shift = 1;
4044 *buf = val >> 1;
4045 break;
4046
4047 case BFD_RELOC_SH_IMM8BY4:
4048 max = 0xff;
4049 shift = 2;
4050 *buf = val >> 2;
4051 break;
4052
4053 case BFD_RELOC_8:
4054 case BFD_RELOC_SH_IMM8:
4055 /* Sometimes the 8 bit value is sign extended (e.g., add) and
4056 sometimes it is not (e.g., and). We permit any 8 bit value.
4057 Note that adding further restrictions may invalidate
4058 reasonable looking assembly code, such as ``and -0x1,r0''. */
4059 max = 0xff;
c4aa876b 4060 min = -0xff;
252b5132
RH		 4061 *buf++ = val;
4062 break;
4063
4064 case BFD_RELOC_SH_PCRELIMM8BY4:
4065 /* The lower two bits of the PC are cleared before the
4066 displacement is added in. We can assume that the destination
67c1ffbe 4067 is on a 4 byte boundary. If this instruction is also on a 4
252b5132
RH		 4068 byte boundary, then we want
4069 (target - here) / 4
4070 and target - here is a multiple of 4.
4071 Otherwise, we are on a 2 byte boundary, and we want
4072 (target - (here - 2)) / 4
4073 and target - here is not a multiple of 4. Computing
4074 (target - (here - 2)) / 4 == (target - here + 2) / 4
4075 works for both cases, since in the first case the addition of
4076 2 will be removed by the division. target - here is in the
4077 variable val. */
4078 val = (val + 2) / 4;
4079 if (val & ~0xff)
4080 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
4081 buf[lowbyte] = val;
4082 break;
4083
4084 case BFD_RELOC_SH_PCRELIMM8BY2:
4085 val /= 2;
4086 if (val & ~0xff)
4087 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
4088 buf[lowbyte] = val;
4089 break;
4090
4091 case BFD_RELOC_SH_PCDISP8BY2:
4092 val /= 2;
4093 if (val < -0x80 || val > 0x7f)
4094 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
4095 buf[lowbyte] = val;
4096 break;
4097
4098 case BFD_RELOC_SH_PCDISP12BY2:
4099 val /= 2;
8637c045 4100 if (val < -0x800 || val > 0x7ff)
252b5132
RH		 4101 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far"));
4102 buf[lowbyte] = val & 0xff;
4103 buf[highbyte] |= (val >> 8) & 0xf;
4104 break;
4105
4106 case BFD_RELOC_32:
a1cc9221 4107 case BFD_RELOC_32_PCREL:
55e6e397 4108 apply_full_field_fix (fixP, buf, val, 4);
252b5132
RH		 4109 break;
4110
4111 case BFD_RELOC_16:
55e6e397 4112 apply_full_field_fix (fixP, buf, val, 2);
252b5132
RH		 4113 break;
4114
4115 case BFD_RELOC_SH_USES:
fefaa1aa 4116 /* Pass the value into sh_reloc(). */
252b5132
RH		 4117 fixP->fx_addnumber = val;
4118 break;
4119
4120 case BFD_RELOC_SH_COUNT:
4121 case BFD_RELOC_SH_ALIGN:
4122 case BFD_RELOC_SH_CODE:
4123 case BFD_RELOC_SH_DATA:
4124 case BFD_RELOC_SH_LABEL:
4125 /* Nothing to do here. */
4126 break;
4127
015551fc
JR		 4128 case BFD_RELOC_SH_LOOP_START:
4129 case BFD_RELOC_SH_LOOP_END:
4130
252b5132
RH		 4131 case BFD_RELOC_VTABLE_INHERIT:
4132 case BFD_RELOC_VTABLE_ENTRY:
4133 fixP->fx_done = 0;
4134 return;
4135
a1cc9221
AO		 4136#ifdef OBJ_ELF
4137 case BFD_RELOC_32_PLT_PCREL:
4138 /* Make the jump instruction point to the address of the operand. At
81d4177b 4139 runtime we merely add the offset to the actual PLT entry. */
94f592af 4140 * valP = 0xfffffffc;
0174e383 4141 val = fixP->fx_offset;
ac3f04d7
AO		 4142 if (fixP->fx_subsy)
4143 val -= S_GET_VALUE (fixP->fx_subsy);
55e6e397 4144 apply_full_field_fix (fixP, buf, val, 4);
a1cc9221
AO		 4145 break;
4146
4147 case BFD_RELOC_SH_GOTPC:
4148 /* This is tough to explain. We end up with this one if we have
4149 operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]".
4150 The goal here is to obtain the absolute address of the GOT,
4151 and it is strongly preferable from a performance point of
4152 view to avoid using a runtime relocation for this. There are
4153 cases where you have something like:
81d4177b 4154
a1cc9221 4155 .long _GLOBAL_OFFSET_TABLE_+[.-.L66]
81d4177b 4156
a1cc9221
AO		 4157 and here no correction would be required. Internally in the
4158 assembler we treat operands of this form as not being pcrel
4159 since the '.' is explicitly mentioned, and I wonder whether
4160 it would simplify matters to do it this way. Who knows. In
4161 earlier versions of the PIC patches, the pcrel_adjust field
4162 was used to store the correction, but since the expression is
4163 not pcrel, I felt it would be confusing to do it this way. */
94f592af 4164 * valP -= 1;
55e6e397 4165 apply_full_field_fix (fixP, buf, val, 4);
a1cc9221
AO		 4166 break;
4167
9efb3b7b
KK		 4168 case BFD_RELOC_SH_TLS_GD_32:
4169 case BFD_RELOC_SH_TLS_LD_32:
4170 case BFD_RELOC_SH_TLS_IE_32:
2bba4140
KK		 4171 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4172 /* Fallthrough */
4173 case BFD_RELOC_32_GOT_PCREL:
4174 case BFD_RELOC_SH_GOTPLT32:
94f592af 4175 * valP = 0; /* Fully resolved at runtime. No addend. */
55e6e397 4176 apply_full_field_fix (fixP, buf, 0, 4);
a1cc9221
AO		 4177 break;
4178
9efb3b7b
KK		 4179 case BFD_RELOC_SH_TLS_LDO_32:
4180 case BFD_RELOC_SH_TLS_LE_32:
2bba4140
KK		 4181 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4182 /* Fallthrough */
4183 case BFD_RELOC_32_GOTOFF:
55e6e397 4184 apply_full_field_fix (fixP, buf, val, 4);
a1cc9221
AO		 4185 break;
4186#endif
4187
252b5132 4188 default:
324bfcf3 4189#ifdef HAVE_SH64
55cf6793 4190 shmedia_md_apply_fix (fixP, valP);
324bfcf3
AO		 4191 return;
4192#else
252b5132 4193 abort ();
324bfcf3 4194#endif
252b5132
RH		 4195 }
4196
4197 if (shift != 0)
4198 {
4199 if ((val & ((1 << shift) - 1)) != 0)
4200 as_bad_where (fixP->fx_file, fixP->fx_line, _("misaligned offset"));
4201 if (val >= 0)
4202 val >>= shift;
4203 else
4204 val = ((val >> shift)
4205 | ((long) -1 & ~ ((long) -1 >> shift)));
4206 }
4207 if (max != 0 && (val < min || val > max))
4208 as_bad_where (fixP->fx_file, fixP->fx_line, _("offset out of range"));
01eaea5a
NC		 4209 else if (max != 0)
4210 /* Stop the generic code from trying to overlow check the value as well.
4211 It may not have the correct value anyway, as we do not store val back
4212 into *valP. */
4213 fixP->fx_no_overflow = 1;
252b5132 4214
94f592af
NC		 4215 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4216 fixP->fx_done = 1;
252b5132
RH		 4217}
4218
4219/* Called just before address relaxation. Return the length
4220 by which a fragment must grow to reach it's destination. */
4221
4222int
8edc77b9 4223md_estimate_size_before_relax (fragS *fragP, segT segment_type)
252b5132 4224{
e66457fb
AM		 4225 int what;
4226
252b5132
RH		 4227 switch (fragP->fr_subtype)
4228 {
93c2a809 4229 default:
324bfcf3
AO		 4230#ifdef HAVE_SH64
4231 return shmedia_md_estimate_size_before_relax (fragP, segment_type);
4232#else
93c2a809 4233 abort ();
324bfcf3
AO		 4234#endif
4235
93c2a809 4236
252b5132 4237 case C (UNCOND_JUMP, UNDEF_DISP):
6b31947e 4238 /* Used to be a branch to somewhere which was unknown. */
252b5132
RH		 4239 if (!fragP->fr_symbol)
4240 {
4241 fragP->fr_subtype = C (UNCOND_JUMP, UNCOND12);
252b5132
RH		 4242 }
4243 else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4244 {
4245 fragP->fr_subtype = C (UNCOND_JUMP, UNCOND12);
252b5132
RH		 4246 }
4247 else
4248 {
4249 fragP->fr_subtype = C (UNCOND_JUMP, UNDEF_WORD_DISP);
252b5132
RH		 4250 }
4251 break;
4252
252b5132
RH		 4253 case C (COND_JUMP, UNDEF_DISP):
4254 case C (COND_JUMP_DELAY, UNDEF_DISP):
e66457fb 4255 what = GET_WHAT (fragP->fr_subtype);
6b31947e 4256 /* Used to be a branch to somewhere which was unknown. */
252b5132
RH		 4257 if (fragP->fr_symbol
4258 && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4259 {
252b5132 4260 /* Got a symbol and it's defined in this segment, become byte
6b31947e 4261 sized - maybe it will fix up. */
252b5132 4262 fragP->fr_subtype = C (what, COND8);
252b5132
RH		 4263 }
4264 else if (fragP->fr_symbol)
4265 {
6b31947e 4266 /* Its got a segment, but its not ours, so it will always be long. */
252b5132 4267 fragP->fr_subtype = C (what, UNDEF_WORD_DISP);
252b5132
RH		 4268 }
4269 else
4270 {
6b31947e 4271 /* We know the abs value. */
252b5132 4272 fragP->fr_subtype = C (what, COND8);
252b5132 4273 }
93c2a809 4274 break;
252b5132 4275
93c2a809 4276 case C (UNCOND_JUMP, UNCOND12):
e66457fb 4277 case C (UNCOND_JUMP, UNCOND32):
93c2a809
AM		 4278 case C (UNCOND_JUMP, UNDEF_WORD_DISP):
4279 case C (COND_JUMP, COND8):
e66457fb
AM		 4280 case C (COND_JUMP, COND12):
4281 case C (COND_JUMP, COND32):
93c2a809
AM		 4282 case C (COND_JUMP, UNDEF_WORD_DISP):
4283 case C (COND_JUMP_DELAY, COND8):
e66457fb
AM		 4284 case C (COND_JUMP_DELAY, COND12):
4285 case C (COND_JUMP_DELAY, COND32):
93c2a809
AM		 4286 case C (COND_JUMP_DELAY, UNDEF_WORD_DISP):
4287 /* When relaxing a section for the second time, we don't need to
e66457fb 4288 do anything besides return the current size. */
252b5132
RH		 4289 break;
4290 }
e66457fb
AM		 4291
4292 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4293 return fragP->fr_var;
4294}
4295
6b31947e 4296/* Put number into target byte order. */
252b5132
RH		 4297
4298void
8edc77b9 4299md_number_to_chars (char *ptr, valueT use, int nbytes)
252b5132 4300{
324bfcf3
AO		 4301#ifdef HAVE_SH64
4302 /* We might need to set the contents type to data. */
4303 sh64_flag_output ();
4304#endif
4305
252b5132
RH		 4306 if (! target_big_endian)
4307 number_to_chars_littleendian (ptr, use, nbytes);
4308 else
4309 number_to_chars_bigendian (ptr, use, nbytes);
4310}
4311
7be1c489 4312/* This version is used in obj-coff.c eg. for the sh-hms target. */
cce5a618
NC		 4313
4314long
8edc77b9 4315md_pcrel_from (fixS *fixP)
cce5a618
NC		 4316{
4317 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address + 2;
4318}
4319
252b5132 4320long
8edc77b9 4321md_pcrel_from_section (fixS *fixP, segT sec)
252b5132 4322{
28602ebf
KK		 4323 if (! sh_local_pcrel (fixP)
4324 && fixP->fx_addsy != (symbolS *) NULL
ae6063d4 4325 && (generic_force_reloc (fixP)
ef17112f
HPN		 4326 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
4327 {
4328 /* The symbol is undefined (or is defined but not in this section,
4329 or we're not sure about it being the final definition). Let the
4330 linker figure it out. We need to adjust the subtraction of a
4331 symbol to the position of the relocated data, though. */
4332 return fixP->fx_subsy ? fixP->fx_where + fixP->fx_frag->fr_address : 0;
4333 }
4334
cce5a618 4335 return md_pcrel_from (fixP);
252b5132
RH		 4336}
4337
252b5132
RH		 4338/* Create a reloc. */
4339
4340arelent *
8edc77b9 4341tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 4342{
4343 arelent *rel;
4344 bfd_reloc_code_real_type r_type;
4345
4346 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 4347 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4348 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 4349 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4350
4351 r_type = fixp->fx_r_type;
4352
4353 if (SWITCH_TABLE (fixp))
4354 {
bdfaef52
JR		 4355 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
4356 rel->addend = 0;
252b5132
RH		 4357 if (r_type == BFD_RELOC_16)
4358 r_type = BFD_RELOC_SH_SWITCH16;
4359 else if (r_type == BFD_RELOC_8)
4360 r_type = BFD_RELOC_8_PCREL;
4361 else if (r_type == BFD_RELOC_32)
4362 r_type = BFD_RELOC_SH_SWITCH32;
4363 else
4364 abort ();
4365 }
4366 else if (r_type == BFD_RELOC_SH_USES)
4367 rel->addend = fixp->fx_addnumber;
4368 else if (r_type == BFD_RELOC_SH_COUNT)
4369 rel->addend = fixp->fx_offset;
4370 else if (r_type == BFD_RELOC_SH_ALIGN)
4371 rel->addend = fixp->fx_offset;
4372 else if (r_type == BFD_RELOC_VTABLE_INHERIT
4373 || r_type == BFD_RELOC_VTABLE_ENTRY)
4374 rel->addend = fixp->fx_offset;
015551fc
JR		 4375 else if (r_type == BFD_RELOC_SH_LOOP_START
4376 || r_type == BFD_RELOC_SH_LOOP_END)
4377 rel->addend = fixp->fx_offset;
4378 else if (r_type == BFD_RELOC_SH_LABEL && fixp->fx_pcrel)
4379 {
4380 rel->addend = 0;
4381 rel->address = rel->addend = fixp->fx_offset;
4382 }
324bfcf3
AO		 4383#ifdef HAVE_SH64
4384 else if (shmedia_init_reloc (rel, fixp))
4385 ;
4386#endif
252b5132 4387 else
55e6e397 4388 rel->addend = fixp->fx_addnumber;
252b5132
RH		 4389
4390 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
78878175 4391
a161fe53 4392 if (rel->howto == NULL)
252b5132
RH		 4393 {
4394 as_bad_where (fixp->fx_file, fixp->fx_line,
4395 _("Cannot represent relocation type %s"),
4396 bfd_get_reloc_code_name (r_type));
4397 /* Set howto to a garbage value so that we can keep going. */
4398 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4399 assert (rel->howto != NULL);
4400 }
78878175
NC		 4401#ifdef OBJ_ELF
4402 else if (rel->howto->type == R_SH_IND12W)
4403 rel->addend += fixp->fx_offset - 4;
4404#endif
252b5132
RH		 4405
4406 return rel;
4407}
4408
538cd60f
AO		 4409#ifdef OBJ_ELF
4410inline static char *
8edc77b9 4411sh_end_of_match (char *cont, char *what)
538cd60f
AO		 4412{
4413 int len = strlen (what);
4414
4415 if (strncasecmp (cont, what, strlen (what)) == 0
4416 && ! is_part_of_name (cont[len]))
4417 return cont + len;
4418
4419 return NULL;
5d6255fe 4420}
538cd60f
AO		 4421
4422int
9497f5ac
NC		 4423sh_parse_name (char const *name,
4424 expressionS *exprP,
4425 enum expr_mode mode,
4426 char *nextcharP)
538cd60f
AO		 4427{
4428 char *next = input_line_pointer;
4429 char *next_end;
4430 int reloc_type;
4431 segT segment;
4432
4433 exprP->X_op_symbol = NULL;
4434
4435 if (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4436 {
4437 if (! GOT_symbol)
4438 GOT_symbol = symbol_find_or_make (name);
4439
4440 exprP->X_add_symbol = GOT_symbol;
4441 no_suffix:
4442 /* If we have an absolute symbol or a reg, then we know its
37dedf66 4443 value now. */
538cd60f 4444 segment = S_GET_SEGMENT (exprP->X_add_symbol);
9497f5ac 4445 if (mode != expr_defer && segment == absolute_section)
538cd60f
AO		 4446 {
4447 exprP->X_op = O_constant;
4448 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
4449 exprP->X_add_symbol = NULL;
4450 }
9497f5ac 4451 else if (mode != expr_defer && segment == reg_section)
538cd60f
AO		 4452 {
4453 exprP->X_op = O_register;
4454 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
4455 exprP->X_add_symbol = NULL;
4456 }
4457 else
4458 {
4459 exprP->X_op = O_symbol;
4460 exprP->X_add_number = 0;
4461 }
4462
4463 return 1;
4464 }
4465
4466 exprP->X_add_symbol = symbol_find_or_make (name);
5d6255fe 4467
538cd60f
AO		 4468 if (*nextcharP != '@')
4469 goto no_suffix;
4470 else if ((next_end = sh_end_of_match (next + 1, "GOTOFF")))
4471 reloc_type = BFD_RELOC_32_GOTOFF;
324bfcf3
AO		 4472 else if ((next_end = sh_end_of_match (next + 1, "GOTPLT")))
4473 reloc_type = BFD_RELOC_SH_GOTPLT32;
538cd60f
AO		 4474 else if ((next_end = sh_end_of_match (next + 1, "GOT")))
4475 reloc_type = BFD_RELOC_32_GOT_PCREL;
4476 else if ((next_end = sh_end_of_match (next + 1, "PLT")))
4477 reloc_type = BFD_RELOC_32_PLT_PCREL;
9efb3b7b
KK		 4478 else if ((next_end = sh_end_of_match (next + 1, "TLSGD")))
4479 reloc_type = BFD_RELOC_SH_TLS_GD_32;
4480 else if ((next_end = sh_end_of_match (next + 1, "TLSLDM")))
4481 reloc_type = BFD_RELOC_SH_TLS_LD_32;
4482 else if ((next_end = sh_end_of_match (next + 1, "GOTTPOFF")))
4483 reloc_type = BFD_RELOC_SH_TLS_IE_32;
4484 else if ((next_end = sh_end_of_match (next + 1, "TPOFF")))
4485 reloc_type = BFD_RELOC_SH_TLS_LE_32;
4486 else if ((next_end = sh_end_of_match (next + 1, "DTPOFF")))
4487 reloc_type = BFD_RELOC_SH_TLS_LDO_32;
538cd60f
AO		 4488 else
4489 goto no_suffix;
4490
4491 *input_line_pointer = *nextcharP;
4492 input_line_pointer = next_end;
4493 *nextcharP = *input_line_pointer;
4494 *input_line_pointer = '\0';
4495
4496 exprP->X_op = O_PIC_reloc;
4497 exprP->X_add_number = 0;
4498 exprP->X_md = reloc_type;
4499
4500 return 1;
4501}
2ce4cc60
KK		 4502
4503void
4504sh_cfi_frame_initial_instructions (void)
4505{
4506 cfi_add_CFA_def_cfa (15, 0);
4507}
4508
4509int
1df69f4f 4510sh_regname_to_dw2regnum (char *regname)
2ce4cc60
KK		 4511{
4512 unsigned int regnum = -1;
4513 unsigned int i;
4514 const char *p;
4515 char *q;
4516 static struct { char *name; int dw2regnum; } regnames[] =
4517 {
4518 { "pr", 17 }, { "t", 18 }, { "gbr", 19 }, { "mach", 20 },
4519 { "macl", 21 }, { "fpul", 23 }
4520 };
4521
4522 for (i = 0; i < ARRAY_SIZE (regnames); ++i)
4523 if (strcmp (regnames[i].name, regname) == 0)
4524 return regnames[i].dw2regnum;
4525
4526 if (regname[0] == 'r')
4527 {
4528 p = regname + 1;
4529 regnum = strtoul (p, &q, 10);
4530 if (p == q || *q || regnum >= 16)
4531 return -1;
4532 }
4533 else if (regname[0] == 'f' && regname[1] == 'r')
4534 {
4535 p = regname + 2;
4536 regnum = strtoul (p, &q, 10);
4537 if (p == q || *q || regnum >= 16)
4538 return -1;
4539 regnum += 25;
4540 }
4541 else if (regname[0] == 'x' && regname[1] == 'd')
4542 {
4543 p = regname + 2;
4544 regnum = strtoul (p, &q, 10);
4545 if (p == q || *q || regnum >= 8)
4546 return -1;
4547 regnum += 87;
4548 }
4549 return regnum;
4550}
f17c130b 4551#endif /* OBJ_ELF */
GDB Binutils - Deliverables
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