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Protoization.
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
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252b5132 1/* tc-sparc.c -- Assemble for the SPARC
e0c6ed95
AM		 2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
252b5132
RH		 4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21#include <stdio.h>
22#include <ctype.h>
23
24#include "as.h"
25#include "subsegs.h"
26
27#include "opcode/sparc.h"
28
29#ifdef OBJ_ELF
30#include "elf/sparc.h"
31#endif
32
33static struct sparc_arch *lookup_arch PARAMS ((char *));
34static void init_default_arch PARAMS ((void));
a22b281c 35static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
252b5132
RH		 36static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
37static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
38static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39static int sparc_ffs PARAMS ((unsigned int));
a22b281c
RH		 40static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
41static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
42static void synthetize_setx PARAMS ((const struct sparc_opcode *));
252b5132
RH		 43static bfd_vma BSR PARAMS ((bfd_vma, int));
44static int cmp_reg_entry PARAMS ((const PTR, const PTR));
45static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
46static int parse_const_expr_arg PARAMS ((char **, int *));
47static int get_expression PARAMS ((char *str));
48
49/* Default architecture. */
50/* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "sparclite"
55#endif
56static char *default_arch = DEFAULT_ARCH;
57
58/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 have been set. */
60static int default_init_p;
61
62/* Current architecture. We don't bump up unless necessary. */
63static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
64
65/* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70static enum sparc_opcode_arch_val max_architecture;
71
72/* Either 32 or 64, selects file format. */
73static int sparc_arch_size;
74/* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76static int default_arch_size;
77
78#ifdef OBJ_ELF
79/* The currently selected v9 memory model. Currently only used for
80 ELF. */
81static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
82#endif
83
84static int architecture_requested;
85static int warn_on_bump;
86
87/* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89static enum sparc_opcode_arch_val warn_after_architecture;
90
6d8809aa
RH		 91/* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93static int no_undeclared_regs;
94
6faf3d66
JJ		 95/* Non-zero if we should try to relax jumps and calls. */
96static int sparc_relax;
97
252b5132
RH		 98/* Non-zero if we are generating PIC code. */
99int sparc_pic_code;
100
101/* Non-zero if we should give an error when misaligned data is seen. */
102static int enforce_aligned_data;
103
104extern int target_big_endian;
105
106static int target_little_endian_data;
107
6d8809aa
RH		 108/* Symbols for global registers on v9. */
109static symbolS *globals[8];
110
252b5132
RH		 111/* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115#ifndef INSN_BIG_ENDIAN
116#define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
119#endif
120
e0c6ed95 121/* Handle of the OPCODE hash table. */
252b5132
RH		 122static struct hash_control *op_hash;
123
124static int log2 PARAMS ((int));
125static void s_data1 PARAMS ((void));
126static void s_seg PARAMS ((int));
127static void s_proc PARAMS ((int));
128static void s_reserve PARAMS ((int));
129static void s_common PARAMS ((int));
130static void s_empty PARAMS ((int));
131static void s_uacons PARAMS ((int));
cf9a1301 132static void s_ncons PARAMS ((int));
6d8809aa 133static void s_register PARAMS ((int));
252b5132
RH		 134
135const pseudo_typeS md_pseudo_table[] =
136{
e0c6ed95 137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 138 {"common", s_common, 0},
139 {"empty", s_empty, 0},
140 {"global", s_globl, 0},
141 {"half", cons, 2},
cf9a1301 142 {"nword", s_ncons, 0},
252b5132
RH		 143 {"optim", s_ignore, 0},
144 {"proc", s_proc, 0},
145 {"reserve", s_reserve, 0},
146 {"seg", s_seg, 0},
147 {"skip", s_space, 0},
148 {"word", cons, 4},
149 {"xword", cons, 8},
150 {"uahalf", s_uacons, 2},
151 {"uaword", s_uacons, 4},
152 {"uaxword", s_uacons, 8},
153#ifdef OBJ_ELF
e0c6ed95 154 /* These are specific to sparc/svr4. */
252b5132
RH		 155 {"2byte", s_uacons, 2},
156 {"4byte", s_uacons, 4},
157 {"8byte", s_uacons, 8},
6d8809aa 158 {"register", s_register, 0},
252b5132
RH		 159#endif
160 {NULL, 0, 0},
161};
162
e0c6ed95
AM		 163/* Size of relocation record. */
164const int md_reloc_size = 12;
252b5132
RH		 165
166/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 167 pre-processor is disabled, these aren't very useful. */
168const char comment_chars[] = "!"; /* JF removed '|' from
169 comment_chars. */
252b5132
RH		 170
171/* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 173 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 174/* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
e0c6ed95 176 #NO_APP at the beginning of its output. */
252b5132 177/* Also note that comments started like this one will always
e0c6ed95 178 work if '/' isn't otherwise defined. */
252b5132
RH		 179const char line_comment_chars[] = "#";
180
63a0b638 181const char line_separator_chars[] = ";";
252b5132 182
e0c6ed95
AM		 183/* Chars that can be used to separate mant from exp in floating point
184 nums. */
252b5132
RH		 185const char EXP_CHARS[] = "eE";
186
e0c6ed95
AM		 187/* Chars that mean this number is a floating point constant.
188 As in 0f12.456
189 or 0d1.2345e12 */
252b5132
RH		 190const char FLT_CHARS[] = "rRsSfFdDxXpP";
191
192/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
195
a22b281c 196#define isoctal(c) ((unsigned)((c) - '0') < '8')
252b5132
RH		 197
198struct sparc_it
199 {
200 char *error;
201 unsigned long opcode;
202 struct nlist *nlistp;
203 expressionS exp;
cf9a1301 204 expressionS exp2;
252b5132
RH		 205 int pcrel;
206 bfd_reloc_code_real_type reloc;
207 };
208
209struct sparc_it the_insn, set_insn;
210
211static void output_insn
212 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
213\f
214/* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
217 and file formats. */
218
219enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
220 v8plusa, v9, v9a, v9_64};
221
222static struct sparc_arch {
223 char *name;
224 char *opcode_arch;
225 enum sparc_arch_types arch_type;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size;
229 /* Allowable arg to -A? */
230 int user_option_p;
231} sparc_arch_table[] = {
232 { "v6", "v6", v6, 0, 1 },
233 { "v7", "v7", v7, 0, 1 },
234 { "v8", "v8", v8, 32, 1 },
235 { "sparclet", "sparclet", sparclet, 32, 1 },
236 { "sparclite", "sparclite", sparclite, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x, 32, 1 },
238 { "v8plus", "v9", v9, 0, 1 },
239 { "v8plusa", "v9a", v9, 0, 1 },
240 { "v9", "v9", v9, 0, 1 },
241 { "v9a", "v9a", v9, 0, 1 },
242 /* This exists to allow configure.in/Makefile.in to pass one
243 value to specify both the default machine and default word size. */
244 { "v9-64", "v9", v9, 64, 0 },
245 { NULL, NULL, v8, 0, 0 }
246};
247
248/* Variant of default_arch */
249static enum sparc_arch_types default_arch_type;
250
251static struct sparc_arch *
252lookup_arch (name)
253 char *name;
254{
255 struct sparc_arch *sa;
256
257 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
258 if (strcmp (sa->name, name) == 0)
259 break;
260 if (sa->name == NULL)
261 return NULL;
262 return sa;
263}
264
265/* Initialize the default opcode arch and word size from the default
266 architecture name. */
267
268static void
269init_default_arch ()
270{
271 struct sparc_arch *sa = lookup_arch (default_arch);
272
273 if (sa == NULL
274 || sa->default_arch_size == 0)
275 as_fatal (_("Invalid default architecture, broken assembler."));
276
277 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
278 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
279 as_fatal (_("Bad opcode table, broken assembler."));
280 default_arch_size = sparc_arch_size = sa->default_arch_size;
281 default_init_p = 1;
282 default_arch_type = sa->arch_type;
283}
284
285/* Called by TARGET_FORMAT. */
286
287const char *
288sparc_target_format ()
289{
290 /* We don't get a chance to initialize anything before we're called,
291 so handle that now. */
292 if (! default_init_p)
293 init_default_arch ();
294
295#ifdef OBJ_AOUT
296#ifdef TE_NetBSD
297 return "a.out-sparc-netbsd";
298#else
299#ifdef TE_SPARCAOUT
300 if (target_big_endian)
301 return "a.out-sunos-big";
302 else if (default_arch_type == sparc86x && target_little_endian_data)
303 return "a.out-sunos-big";
ab3e48dc
KH		 304 else
305 return "a.out-sparc-little";
252b5132
RH		 306#else
307 return "a.out-sunos-big";
308#endif
309#endif
310#endif
311
312#ifdef OBJ_BOUT
313 return "b.out.big";
314#endif
315
316#ifdef OBJ_COFF
317#ifdef TE_LYNX
318 return "coff-sparc-lynx";
319#else
320 return "coff-sparc";
321#endif
322#endif
323
324#ifdef OBJ_ELF
325 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
326#endif
327
328 abort ();
329}
330\f
e0c6ed95 331/* md_parse_option
252b5132
RH		 332 * Invocation line includes a switch not recognized by the base assembler.
333 * See if it's a processor-specific option. These are:
334 *
335 * -bump
336 * Warn on architecture bumps. See also -A.
337 *
338 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
339 * Standard 32 bit architectures.
252b5132
RH		 340 * -Av9, -Av9a
341 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
342 * This used to only mean 64 bits, but properly specifying it
343 * complicated gcc's ASM_SPECs, so now opcode selection is
344 * specified orthogonally to word size (except when specifying
345 * the default, but that is an internal implementation detail).
c2158c24
JJ		 346 * -Av8plus, -Av8plusa
347 * Same as -Av9{,a}.
252b5132 348 * -xarch=v8plus, -xarch=v8plusa
c2158c24
JJ		 349 * Same as -Av8plus{,a} -32, for compatibility with Sun's
350 * assembler.
351 * -xarch=v9, -xarch=v9a
352 * Same as -Av9{,a} -64, for compatibility with Sun's assembler.
252b5132
RH		 353 *
354 * Select the architecture and possibly the file format.
355 * Instructions or features not supported by the selected
356 * architecture cause fatal errors.
357 *
358 * The default is to start at v6, and bump the architecture up
359 * whenever an instruction is seen at a higher level. In 32 bit
360 * environments, v9 is not bumped up to, the user must pass
361 * -Av8plus{,a}.
362 *
363 * If -bump is specified, a warning is printing when bumping to
364 * higher levels.
365 *
366 * If an architecture is specified, all instructions must match
367 * that architecture. Any higher level instructions are flagged
368 * as errors. Note that in the 32 bit environment specifying
369 * -Av8plus does not automatically create a v8plus object file, a
370 * v9 insn must be seen.
371 *
372 * If both an architecture and -bump are specified, the
373 * architecture starts at the specified level, but bumps are
374 * warnings. Note that we can't set `current_architecture' to
375 * the requested level in this case: in the 32 bit environment,
376 * we still must avoid creating v8plus object files unless v9
377 * insns are seen.
378 *
379 * Note:
380 * Bumping between incompatible architectures is always an
381 * error. For example, from sparclite to v9.
382 */
383
384#ifdef OBJ_ELF
385CONST char *md_shortopts = "A:K:VQ:sq";
386#else
387#ifdef OBJ_AOUT
388CONST char *md_shortopts = "A:k";
389#else
390CONST char *md_shortopts = "A:";
391#endif
392#endif
393struct option md_longopts[] = {
394#define OPTION_BUMP (OPTION_MD_BASE)
395 {"bump", no_argument, NULL, OPTION_BUMP},
396#define OPTION_SPARC (OPTION_MD_BASE + 1)
397 {"sparc", no_argument, NULL, OPTION_SPARC},
398#define OPTION_XARCH (OPTION_MD_BASE + 2)
399 {"xarch", required_argument, NULL, OPTION_XARCH},
400#ifdef OBJ_ELF
401#define OPTION_32 (OPTION_MD_BASE + 3)
402 {"32", no_argument, NULL, OPTION_32},
403#define OPTION_64 (OPTION_MD_BASE + 4)
404 {"64", no_argument, NULL, OPTION_64},
405#define OPTION_TSO (OPTION_MD_BASE + 5)
406 {"TSO", no_argument, NULL, OPTION_TSO},
407#define OPTION_PSO (OPTION_MD_BASE + 6)
408 {"PSO", no_argument, NULL, OPTION_PSO},
409#define OPTION_RMO (OPTION_MD_BASE + 7)
410 {"RMO", no_argument, NULL, OPTION_RMO},
411#endif
412#ifdef SPARC_BIENDIAN
413#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
414 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
415#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
416 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
417#endif
418#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
419 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
420#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
421 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 422#ifdef OBJ_ELF
423#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
424 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 425#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
426 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 427#endif
6faf3d66
JJ		 428#define OPTION_RELAX (OPTION_MD_BASE + 14)
429 {"relax", no_argument, NULL, OPTION_RELAX},
430#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
431 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 432 {NULL, no_argument, NULL, 0}
433};
e0c6ed95
AM		 434
435size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 436
437int
438md_parse_option (c, arg)
439 int c;
440 char *arg;
441{
442 /* We don't get a chance to initialize anything before we're called,
443 so handle that now. */
444 if (! default_init_p)
445 init_default_arch ();
446
447 switch (c)
448 {
449 case OPTION_BUMP:
450 warn_on_bump = 1;
451 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
452 break;
453
454 case OPTION_XARCH:
c2158c24
JJ		 455#ifdef OBJ_ELF
456 if (strncmp (arg, "v9", 2) != 0)
457 md_parse_option (OPTION_32, NULL);
458 else
459 md_parse_option (OPTION_64, NULL);
460#endif
e0c6ed95 461 /* Fall through. */
252b5132
RH		 462
463 case 'A':
464 {
465 struct sparc_arch *sa;
466 enum sparc_opcode_arch_val opcode_arch;
467
468 sa = lookup_arch (arg);
469 if (sa == NULL
470 || ! sa->user_option_p)
471 {
c2158c24
JJ		 472 if (c == OPTION_XARCH)
473 as_bad (_("invalid architecture -xarch=%s"), arg);
474 else
475 as_bad (_("invalid architecture -A%s"), arg);
252b5132
RH		 476 return 0;
477 }
478
479 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
480 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
481 as_fatal (_("Bad opcode table, broken assembler."));
482
483 max_architecture = opcode_arch;
484 architecture_requested = 1;
485 }
486 break;
487
488 case OPTION_SPARC:
489 /* Ignore -sparc, used by SunOS make default .s.o rule. */
490 break;
491
492 case OPTION_ENFORCE_ALIGNED_DATA:
493 enforce_aligned_data = 1;
494 break;
495
496#ifdef SPARC_BIENDIAN
497 case OPTION_LITTLE_ENDIAN:
498 target_big_endian = 0;
499 if (default_arch_type != sparclet)
500 as_fatal ("This target does not support -EL");
501 break;
502 case OPTION_LITTLE_ENDIAN_DATA:
503 target_little_endian_data = 1;
504 target_big_endian = 0;
505 if (default_arch_type != sparc86x
506 && default_arch_type != v9)
507 as_fatal ("This target does not support --little-endian-data");
508 break;
509 case OPTION_BIG_ENDIAN:
510 target_big_endian = 1;
511 break;
512#endif
513
514#ifdef OBJ_AOUT
515 case 'k':
516 sparc_pic_code = 1;
517 break;
518#endif
519
520#ifdef OBJ_ELF
521 case OPTION_32:
522 case OPTION_64:
523 {
524 const char **list, **l;
525
526 sparc_arch_size = c == OPTION_32 ? 32 : 64;
527 list = bfd_target_list ();
528 for (l = list; *l != NULL; l++)
529 {
530 if (sparc_arch_size == 32)
531 {
532 if (strcmp (*l, "elf32-sparc") == 0)
533 break;
534 }
535 else
536 {
537 if (strcmp (*l, "elf64-sparc") == 0)
538 break;
539 }
540 }
541 if (*l == NULL)
542 as_fatal (_("No compiled in support for %d bit object file format"),
543 sparc_arch_size);
544 free (list);
545 }
546 break;
547
548 case OPTION_TSO:
549 sparc_memory_model = MM_TSO;
550 break;
551
552 case OPTION_PSO:
553 sparc_memory_model = MM_PSO;
554 break;
555
556 case OPTION_RMO:
557 sparc_memory_model = MM_RMO;
558 break;
559
560 case 'V':
561 print_version_id ();
562 break;
563
564 case 'Q':
565 /* Qy - do emit .comment
e0c6ed95 566 Qn - do not emit .comment. */
252b5132
RH		 567 break;
568
569 case 's':
e0c6ed95 570 /* Use .stab instead of .stab.excl. */
252b5132
RH		 571 break;
572
573 case 'q':
e0c6ed95 574 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 575 break;
576
577 case 'K':
578 if (strcmp (arg, "PIC") != 0)
579 as_warn (_("Unrecognized option following -K"));
580 else
581 sparc_pic_code = 1;
582 break;
6d8809aa
RH		 583
584 case OPTION_NO_UNDECLARED_REGS:
585 no_undeclared_regs = 1;
586 break;
a25fe906
ILT		 587
588 case OPTION_UNDECLARED_REGS:
589 no_undeclared_regs = 0;
590 break;
252b5132
RH		 591#endif
592
6faf3d66
JJ		 593 case OPTION_RELAX:
594 sparc_relax = 1;
595 break;
596
597 case OPTION_NO_RELAX:
598 sparc_relax = 0;
599 break;
600
252b5132
RH		 601 default:
602 return 0;
603 }
604
605 return 1;
606}
607
608void
609md_show_usage (stream)
610 FILE *stream;
611{
612 const struct sparc_arch *arch;
c2158c24 613 int column;
252b5132
RH		 614
615 /* We don't get a chance to initialize anything before we're called,
616 so handle that now. */
617 if (! default_init_p)
618 init_default_arch ();
619
e0c6ed95 620 fprintf (stream, _("SPARC options:\n"));
c2158c24 621 column = 0;
252b5132
RH		 622 for (arch = &sparc_arch_table[0]; arch->name; arch++)
623 {
c2158c24
JJ		 624 if (!arch->user_option_p)
625 continue;
252b5132
RH		 626 if (arch != &sparc_arch_table[0])
627 fprintf (stream, " | ");
c2158c24
JJ		 628 if (column + strlen(arch->name) > 70)
629 {
630 column = 0;
631 fputc ('\n', stream);
632 }
633 column += 5 + 2 + strlen(arch->name);
634 fprintf (stream, "-A%s", arch->name);
252b5132 635 }
c2158c24
JJ		 636 for (arch = &sparc_arch_table[0]; arch->name; arch++)
637 {
638 if (!arch->user_option_p)
639 continue;
640 fprintf (stream, " | ");
641 if (column + strlen(arch->name) > 65)
642 {
643 column = 0;
644 fputc ('\n', stream);
645 }
646 column += 5 + 7 + strlen(arch->name);
647 fprintf (stream, "-xarch=%s", arch->name);
648 }
649 fprintf (stream, _("\n\
252b5132
RH		 650 specify variant of SPARC architecture\n\
651-bump warn when assembler switches architectures\n\
652-sparc ignored\n\
6faf3d66
JJ		 653--enforce-aligned-data force .long, etc., to be aligned correctly\n\
654-relax relax jumps and branches (default)\n\
655-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 656#ifdef OBJ_AOUT
657 fprintf (stream, _("\
658-k generate PIC\n"));
659#endif
660#ifdef OBJ_ELF
661 fprintf (stream, _("\
662-32 create 32 bit object file\n\
663-64 create 64 bit object file\n"));
664 fprintf (stream, _("\
665 [default is %d]\n"), default_arch_size);
666 fprintf (stream, _("\
667-TSO use Total Store Ordering\n\
668-PSO use Partial Store Ordering\n\
669-RMO use Relaxed Memory Ordering\n"));
670 fprintf (stream, _("\
671 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
672 fprintf (stream, _("\
673-KPIC generate PIC\n\
674-V print assembler version number\n\
a25fe906
ILT		 675-undeclared-regs ignore application global register usage without\n\
676 appropriate .register directive (default)\n\
677-no-undeclared-regs force error on application global register usage\n\
678 without appropriate .register directive\n\
252b5132
RH		 679-q ignored\n\
680-Qy, -Qn ignored\n\
681-s ignored\n"));
682#endif
683#ifdef SPARC_BIENDIAN
684 fprintf (stream, _("\
685-EL generate code for a little endian machine\n\
686-EB generate code for a big endian machine\n\
687--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 688 instructions and little endian data.\n"));
252b5132
RH		 689#endif
690}
691\f
e0c6ed95 692/* Native operand size opcode translation. */
cf9a1301
RH		 693struct
694 {
695 char *name;
696 char *name32;
697 char *name64;
698 } native_op_table[] =
699{
700 {"ldn", "ld", "ldx"},
701 {"ldna", "lda", "ldxa"},
702 {"stn", "st", "stx"},
703 {"stna", "sta", "stxa"},
704 {"slln", "sll", "sllx"},
705 {"srln", "srl", "srlx"},
706 {"sran", "sra", "srax"},
707 {"casn", "cas", "casx"},
708 {"casna", "casa", "casxa"},
709 {"clrn", "clr", "clrx"},
710 {NULL, NULL, NULL},
711};
712\f
e0c6ed95 713/* sparc64 priviledged registers. */
252b5132
RH		 714
715struct priv_reg_entry
ab3e48dc
KH		 716{
717 char *name;
718 int regnum;
719};
252b5132
RH		 720
721struct priv_reg_entry priv_reg_table[] =
722{
723 {"tpc", 0},
724 {"tnpc", 1},
725 {"tstate", 2},
726 {"tt", 3},
727 {"tick", 4},
728 {"tba", 5},
729 {"pstate", 6},
730 {"tl", 7},
731 {"pil", 8},
732 {"cwp", 9},
733 {"cansave", 10},
734 {"canrestore", 11},
735 {"cleanwin", 12},
736 {"otherwin", 13},
737 {"wstate", 14},
738 {"fq", 15},
739 {"ver", 31},
e0c6ed95 740 {"", -1}, /* End marker. */
252b5132
RH		 741};
742
e0c6ed95 743/* v9a specific asrs. */
252b5132
RH		 744
745struct priv_reg_entry v9a_asr_table[] =
746{
747 {"tick_cmpr", 23},
748 {"softint", 22},
749 {"set_softint", 20},
750 {"pic", 17},
751 {"pcr", 16},
752 {"gsr", 19},
753 {"dcr", 18},
754 {"clear_softint", 21},
e0c6ed95 755 {"", -1}, /* End marker. */
252b5132
RH		 756};
757
758static int
759cmp_reg_entry (parg, qarg)
760 const PTR parg;
761 const PTR qarg;
762{
763 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
764 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
765
766 return strcmp (q->name, p->name);
767}
768\f
769/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 770 set up all the tables, etc. that the MD part of the assembler will
771 need. */
252b5132
RH		 772
773void
774md_begin ()
775{
776 register const char *retval = NULL;
777 int lose = 0;
778 register unsigned int i = 0;
779
780 /* We don't get a chance to initialize anything before md_parse_option
781 is called, and it may not be called, so handle default initialization
782 now if not already done. */
783 if (! default_init_p)
784 init_default_arch ();
785
786 op_hash = hash_new ();
787
788 while (i < (unsigned int) sparc_num_opcodes)
789 {
790 const char *name = sparc_opcodes[i].name;
791 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
792 if (retval != NULL)
793 {
cf9a1301
RH		 794 as_bad (_("Internal error: can't hash `%s': %s\n"),
795 sparc_opcodes[i].name, retval);
252b5132
RH		 796 lose = 1;
797 }
798 do
799 {
800 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
801 {
cf9a1301
RH		 802 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
803 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 804 lose = 1;
805 }
806 ++i;
807 }
808 while (i < (unsigned int) sparc_num_opcodes
809 && !strcmp (sparc_opcodes[i].name, name));
810 }
811
cf9a1301
RH		 812 for (i = 0; native_op_table[i].name; i++)
813 {
814 const struct sparc_opcode *insn;
3d4ae3c0
NC		 815 char *name = ((sparc_arch_size == 32)
816 ? native_op_table[i].name32
817 : native_op_table[i].name64);
e0c6ed95 818 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 819 if (insn == NULL)
e0c6ed95
AM		 820 {
821 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
822 name, native_op_table[i].name);
823 lose = 1;
824 }
cf9a1301
RH		 825 else
826 {
827 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
828 if (retval != NULL)
829 {
830 as_bad (_("Internal error: can't hash `%s': %s\n"),
831 sparc_opcodes[i].name, retval);
832 lose = 1;
833 }
834 }
835 }
836
252b5132
RH		 837 if (lose)
838 as_fatal (_("Broken assembler. No assembly attempted."));
839
252b5132
RH		 840 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
841 sizeof (priv_reg_table[0]), cmp_reg_entry);
842
843 /* If -bump, record the architecture level at which we start issuing
844 warnings. The behaviour is different depending upon whether an
845 architecture was explicitly specified. If it wasn't, we issue warnings
846 for all upwards bumps. If it was, we don't start issuing warnings until
847 we need to bump beyond the requested architecture or when we bump between
848 conflicting architectures. */
849
850 if (warn_on_bump
851 && architecture_requested)
852 {
853 /* `max_architecture' records the requested architecture.
854 Issue warnings if we go above it. */
855 warn_after_architecture = max_architecture;
856
857 /* Find the highest architecture level that doesn't conflict with
858 the requested one. */
859 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
860 max_architecture > warn_after_architecture;
861 --max_architecture)
862 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
863 warn_after_architecture))
864 break;
865 }
866}
867
868/* Called after all assembly has been done. */
869
870void
871sparc_md_end ()
872{
873 if (sparc_arch_size == 64)
874 {
875 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
876 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
877 else
878 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
879 }
880 else
881 {
882 if (current_architecture == SPARC_OPCODE_ARCH_V9)
883 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
884 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
885 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
886 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
887 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
888 else if (default_arch_type == sparc86x && target_little_endian_data)
889 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
890 else
891 {
e0c6ed95
AM		 892 /* The sparclite is treated like a normal sparc. Perhaps it
893 shouldn't be but for now it is (since that's the way it's
894 always been treated). */
252b5132
RH		 895 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
896 }
897 }
898}
899\f
900/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
901
902static INLINE int
903in_signed_range (val, max)
904 bfd_signed_vma val, max;
905{
906 if (max <= 0)
907 abort ();
908 /* Sign-extend the value from the architecture word size, so that
909 0xffffffff is always considered -1 on sparc32. */
910 if (sparc_arch_size == 32)
911 {
e0c6ed95 912 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
252b5132
RH		 913 val = ((val & 0xffffffff) ^ sign) - sign;
914 }
915 if (val > max)
916 return 0;
917 if (val < ~max)
918 return 0;
919 return 1;
920}
921
922/* Return non-zero if VAL is in the range 0 to MAX. */
923
924static INLINE int
925in_unsigned_range (val, max)
926 bfd_vma val, max;
927{
928 if (val > max)
929 return 0;
930 return 1;
931}
932
933/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
934 (e.g. -15 to +31). */
935
936static INLINE int
937in_bitfield_range (val, max)
938 bfd_signed_vma val, max;
939{
940 if (max <= 0)
941 abort ();
942 if (val > max)
943 return 0;
944 if (val < ~(max >> 1))
945 return 0;
946 return 1;
947}
948
949static int
950sparc_ffs (mask)
951 unsigned int mask;
952{
953 int i;
954
955 if (mask == 0)
956 return -1;
957
958 for (i = 0; (mask & 1) == 0; ++i)
959 mask >>= 1;
960 return i;
961}
962
963/* Implement big shift right. */
964static bfd_vma
965BSR (val, amount)
966 bfd_vma val;
967 int amount;
968{
969 if (sizeof (bfd_vma) <= 4 && amount >= 32)
970 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
971 return val >> amount;
972}
973\f
974/* For communication between sparc_ip and get_expression. */
975static char *expr_end;
976
252b5132
RH		 977/* Values for `special_case'.
978 Instructions that require wierd handling because they're longer than
979 4 bytes. */
980#define SPECIAL_CASE_NONE 0
981#define SPECIAL_CASE_SET 1
982#define SPECIAL_CASE_SETSW 2
983#define SPECIAL_CASE_SETX 3
984/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
985#define SPECIAL_CASE_FDIV 4
986
987/* Bit masks of various insns. */
988#define NOP_INSN 0x01000000
989#define OR_INSN 0x80100000
63fab58c 990#define XOR_INSN 0x80180000
252b5132
RH		 991#define FMOVS_INSN 0x81A00020
992#define SETHI_INSN 0x01000000
993#define SLLX_INSN 0x81281000
994#define SRA_INSN 0x81380000
995
996/* The last instruction to be assembled. */
997static const struct sparc_opcode *last_insn;
998/* The assembled opcode of `last_insn'. */
999static unsigned long last_opcode;
1000\f
a22b281c 1001/* Handle the set and setuw synthetic instructions. */
e0c6ed95 1002
a22b281c
RH		 1003static void
1004synthetize_setuw (insn)
1005 const struct sparc_opcode *insn;
1006{
1007 int need_hi22_p = 0;
1008 int rd = (the_insn.opcode & RD (~0)) >> 25;
1009
1010 if (the_insn.exp.X_op == O_constant)
1011 {
1012 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1013 {
e0c6ed95 1014 if (sizeof (offsetT) > 4
a22b281c
RH		 1015 && (the_insn.exp.X_add_number < 0
1016 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1017 as_warn (_("set: number not in 0..4294967295 range"));
1018 }
1019 else
1020 {
e0c6ed95 1021 if (sizeof (offsetT) > 4
a22b281c
RH		 1022 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1023 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1024 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 1025 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1026 }
1027 }
1028
1029 /* See if operand is absolute and small; skip sethi if so. */
1030 if (the_insn.exp.X_op != O_constant
1031 || the_insn.exp.X_add_number >= (1 << 12)
1032 || the_insn.exp.X_add_number < -(1 << 12))
1033 {
1034 the_insn.opcode = (SETHI_INSN | RD (rd)
1035 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1036 & (the_insn.exp.X_op == O_constant
1037 ? 0x3fffff : 0)));
a22b281c 1038 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1039 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1040 output_insn (insn, &the_insn);
1041 need_hi22_p = 1;
1042 }
1043
1044 /* See if operand has no low-order bits; skip OR if so. */
1045 if (the_insn.exp.X_op != O_constant
1046 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1047 || ! need_hi22_p)
1048 {
1049 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1050 | RD (rd) | IMMED
1051 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1052 & (the_insn.exp.X_op != O_constant
1053 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1054 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1055 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1056 output_insn (insn, &the_insn);
1057 }
1058}
e0c6ed95 1059
a22b281c 1060/* Handle the setsw synthetic instruction. */
e0c6ed95 1061
a22b281c
RH		 1062static void
1063synthetize_setsw (insn)
1064 const struct sparc_opcode *insn;
1065{
1066 int low32, rd, opc;
1067
1068 rd = (the_insn.opcode & RD (~0)) >> 25;
1069
1070 if (the_insn.exp.X_op != O_constant)
1071 {
1072 synthetize_setuw (insn);
1073
1074 /* Need to sign extend it. */
1075 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1076 the_insn.reloc = BFD_RELOC_NONE;
1077 output_insn (insn, &the_insn);
1078 return;
1079 }
1080
e0c6ed95 1081 if (sizeof (offsetT) > 4
a22b281c
RH		 1082 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1083 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1084 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1085
e0c6ed95
AM		 1086 low32 = the_insn.exp.X_add_number;
1087
a22b281c
RH		 1088 if (low32 >= 0)
1089 {
1090 synthetize_setuw (insn);
1091 return;
1092 }
1093
1094 opc = OR_INSN;
e0c6ed95 1095
a22b281c
RH		 1096 the_insn.reloc = BFD_RELOC_NONE;
1097 /* See if operand is absolute and small; skip sethi if so. */
1098 if (low32 < -(1 << 12))
1099 {
1100 the_insn.opcode = (SETHI_INSN | RD (rd)
1101 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1102 output_insn (insn, &the_insn);
1103 low32 = 0x1c00 | (low32 & 0x3ff);
1104 opc = RS1 (rd) | XOR_INSN;
1105 }
1106
1107 the_insn.opcode = (opc | RD (rd) | IMMED
1108 | (low32 & 0x1fff));
1109 output_insn (insn, &the_insn);
1110}
1111
1112/* Handle the setsw synthetic instruction. */
e0c6ed95 1113
a22b281c
RH		 1114static void
1115synthetize_setx (insn)
1116 const struct sparc_opcode *insn;
1117{
1118 int upper32, lower32;
1119 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1120 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1121 int upper_dstreg;
1122 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1123 int need_xor10_p = 0;
e0c6ed95 1124
a22b281c
RH		 1125#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1126 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1127 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1128#undef SIGNEXT32
1129
1130 upper_dstreg = tmpreg;
1131 /* The tmp reg should not be the dst reg. */
1132 if (tmpreg == dstreg)
1133 as_warn (_("setx: temporary register same as destination register"));
1134
1135 /* ??? Obviously there are other optimizations we can do
1136 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1137 doing some of these. Later. If you do change things, try to
1138 change all of this to be table driven as well. */
1139 /* What to output depends on the number if it's constant.
1140 Compute that first, then output what we've decided upon. */
1141 if (the_insn.exp.X_op != O_constant)
1142 {
1143 if (sparc_arch_size == 32)
1144 {
1145 /* When arch size is 32, we want setx to be equivalent
1146 to setuw for anything but constants. */
1147 the_insn.exp.X_add_number &= 0xffffffff;
1148 synthetize_setuw (insn);
1149 return;
1150 }
1151 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1152 lower32 = 0;
1153 upper32 = 0;
a22b281c
RH		 1154 }
1155 else
1156 {
1157 /* Reset X_add_number, we've extracted it as upper32/lower32.
1158 Otherwise fixup_segment will complain about not being able to
1159 write an 8 byte number in a 4 byte field. */
1160 the_insn.exp.X_add_number = 0;
e0c6ed95 1161
a22b281c
RH		 1162 /* Only need hh22 if `or' insn can't handle constant. */
1163 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1164 need_hh22_p = 1;
e0c6ed95 1165
a22b281c
RH		 1166 /* Does bottom part (after sethi) have bits? */
1167 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1168 /* No hh22, but does upper32 still have bits we can't set
1169 from lower32? */
1170 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1171 need_hm10_p = 1;
e0c6ed95 1172
a22b281c
RH		 1173 /* If the lower half is all zero, we build the upper half directly
1174 into the dst reg. */
1175 if (lower32 != 0
1176 /* Need lower half if number is zero or 0xffffffff00000000. */
1177 || (! need_hh22_p && ! need_hm10_p))
1178 {
1179 /* No need for sethi if `or' insn can handle constant. */
1180 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1181 /* Note that we can't use a negative constant in the `or'
1182 insn unless the upper 32 bits are all ones. */
1183 || (lower32 < 0 && upper32 != -1)
1184 || (lower32 >= 0 && upper32 == -1))
1185 need_hi22_p = 1;
e0c6ed95 1186
a22b281c
RH		 1187 if (need_hi22_p && upper32 == -1)
1188 need_xor10_p = 1;
1189
1190 /* Does bottom part (after sethi) have bits? */
1191 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1192 /* No sethi. */
1193 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1194 /* Need `or' if we didn't set anything else. */
1195 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1196 need_lo10_p = 1;
1197 }
1198 else
1199 /* Output directly to dst reg if lower 32 bits are all zero. */
1200 upper_dstreg = dstreg;
1201 }
e0c6ed95 1202
a22b281c
RH		 1203 if (!upper_dstreg && dstreg)
1204 as_warn (_("setx: illegal temporary register g0"));
1205
1206 if (need_hh22_p)
1207 {
1208 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1209 | ((upper32 >> 10) & 0x3fffff));
1210 the_insn.reloc = (the_insn.exp.X_op != O_constant
1211 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1212 output_insn (insn, &the_insn);
1213 }
e0c6ed95 1214
a22b281c
RH		 1215 if (need_hi22_p)
1216 {
1217 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1218 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1219 >> 10) & 0x3fffff));
a22b281c
RH		 1220 the_insn.reloc = (the_insn.exp.X_op != O_constant
1221 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1222 output_insn (insn, &the_insn);
1223 }
1224
1225 if (need_hm10_p)
1226 {
1227 the_insn.opcode = (OR_INSN
1228 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1229 | RD (upper_dstreg)
1230 | IMMED
1231 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1232 the_insn.reloc = (the_insn.exp.X_op != O_constant
1233 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1234 output_insn (insn, &the_insn);
1235 }
e0c6ed95 1236
a22b281c
RH		 1237 if (need_lo10_p)
1238 {
1239 /* FIXME: One nice optimization to do here is to OR the low part
1240 with the highpart if hi22 isn't needed and the low part is
1241 positive. */
1242 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1243 | RD (dstreg)
1244 | IMMED
1245 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1246 the_insn.reloc = (the_insn.exp.X_op != O_constant
1247 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1248 output_insn (insn, &the_insn);
1249 }
e0c6ed95 1250
a22b281c
RH		 1251 /* If we needed to build the upper part, shift it into place. */
1252 if (need_hh22_p || need_hm10_p)
1253 {
1254 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1255 | IMMED | 32);
1256 the_insn.reloc = BFD_RELOC_NONE;
1257 output_insn (insn, &the_insn);
1258 }
e0c6ed95 1259
a22b281c
RH		 1260 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1261 if (need_xor10_p)
1262 {
1263 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1264 | 0x1c00 | (lower32 & 0x3ff));
1265 the_insn.reloc = BFD_RELOC_NONE;
1266 output_insn (insn, &the_insn);
1267 }
1268
1269 /* If we needed to build both upper and lower parts, OR them together. */
1270 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1271 {
1272 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1273 | RD (dstreg));
1274 the_insn.reloc = BFD_RELOC_NONE;
1275 output_insn (insn, &the_insn);
1276 }
1277}
1278\f
252b5132
RH		 1279/* Main entry point to assemble one instruction. */
1280
1281void
1282md_assemble (str)
1283 char *str;
1284{
1285 const struct sparc_opcode *insn;
a22b281c 1286 int special_case;
252b5132
RH		 1287
1288 know (str);
a22b281c 1289 special_case = sparc_ip (str, &insn);
252b5132
RH		 1290
1291 /* We warn about attempts to put a floating point branch in a delay slot,
1292 unless the delay slot has been annulled. */
1293 if (insn != NULL
1294 && last_insn != NULL
1295 && (insn->flags & F_FBR) != 0
1296 && (last_insn->flags & F_DELAYED) != 0
1297 /* ??? This test isn't completely accurate. We assume anything with
1298 F_{UNBR,CONDBR,FBR} set is annullable. */
1299 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1300 || (last_opcode & ANNUL) == 0))
1301 as_warn (_("FP branch in delay slot"));
1302
1303 /* SPARC before v9 requires a nop instruction between a floating
1304 point instruction and a floating point branch. We insert one
1305 automatically, with a warning. */
1306 if (max_architecture < SPARC_OPCODE_ARCH_V9
1307 && insn != NULL
1308 && last_insn != NULL
1309 && (insn->flags & F_FBR) != 0
1310 && (last_insn->flags & F_FLOAT) != 0)
1311 {
1312 struct sparc_it nop_insn;
1313
1314 nop_insn.opcode = NOP_INSN;
1315 nop_insn.reloc = BFD_RELOC_NONE;
1316 output_insn (insn, &nop_insn);
1317 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1318 }
1319
a22b281c
RH		 1320 switch (special_case)
1321 {
1322 case SPECIAL_CASE_NONE:
e0c6ed95 1323 /* Normal insn. */
a22b281c
RH		 1324 output_insn (insn, &the_insn);
1325 break;
252b5132 1326
a22b281c
RH		 1327 case SPECIAL_CASE_SETSW:
1328 synthetize_setsw (insn);
1329 break;
e0c6ed95 1330
a22b281c
RH		 1331 case SPECIAL_CASE_SET:
1332 synthetize_setuw (insn);
1333 break;
252b5132 1334
a22b281c
RH		 1335 case SPECIAL_CASE_SETX:
1336 synthetize_setx (insn);
1337 break;
e0c6ed95 1338
a22b281c
RH		 1339 case SPECIAL_CASE_FDIV:
1340 {
1341 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1342
a22b281c 1343 output_insn (insn, &the_insn);
e0c6ed95 1344
a22b281c
RH		 1345 /* According to information leaked from Sun, the "fdiv" instructions
1346 on early SPARC machines would produce incorrect results sometimes.
1347 The workaround is to add an fmovs of the destination register to
1348 itself just after the instruction. This was true on machines
e0c6ed95 1349 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
a22b281c
RH		 1350 assert (the_insn.reloc == BFD_RELOC_NONE);
1351 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1352 output_insn (insn, &the_insn);
1353 return;
1354 }
e0c6ed95 1355
a22b281c
RH		 1356 default:
1357 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1358 }
1359}
1360
1361/* Subroutine of md_assemble to do the actual parsing. */
1362
a22b281c 1363static int
252b5132
RH		 1364sparc_ip (str, pinsn)
1365 char *str;
1366 const struct sparc_opcode **pinsn;
1367{
1368 char *error_message = "";
1369 char *s;
1370 const char *args;
1371 char c;
1372 const struct sparc_opcode *insn;
1373 char *argsStart;
1374 unsigned long opcode;
1375 unsigned int mask = 0;
1376 int match = 0;
1377 int comma = 0;
1378 int v9_arg_p;
a22b281c 1379 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1380
1381 s = str;
1382 if (islower ((unsigned char) *s))
1383 {
1384 do
1385 ++s;
1386 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1387 }
1388
1389 switch (*s)
1390 {
1391 case '\0':
1392 break;
1393
1394 case ',':
1395 comma = 1;
e0c6ed95 1396 /* Fall through. */
252b5132
RH		 1397
1398 case ' ':
1399 *s++ = '\0';
1400 break;
1401
1402 default:
1403 as_fatal (_("Unknown opcode: `%s'"), str);
1404 }
1405 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1406 *pinsn = insn;
1407 if (insn == NULL)
1408 {
1409 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1410 return special_case;
252b5132
RH		 1411 }
1412 if (comma)
1413 {
1414 *--s = ',';
1415 }
1416
1417 argsStart = s;
1418 for (;;)
1419 {
1420 opcode = insn->match;
1421 memset (&the_insn, '\0', sizeof (the_insn));
1422 the_insn.reloc = BFD_RELOC_NONE;
1423 v9_arg_p = 0;
1424
e0c6ed95
AM		 1425 /* Build the opcode, checking as we go to make sure that the
1426 operands match. */
252b5132
RH		 1427 for (args = insn->args;; ++args)
1428 {
1429 switch (*args)
1430 {
1431 case 'K':
1432 {
1433 int kmask = 0;
1434
1435 /* Parse a series of masks. */
1436 if (*s == '#')
1437 {
1438 while (*s == '#')
1439 {
1440 int mask;
1441
1442 if (! parse_keyword_arg (sparc_encode_membar, &s,
1443 &mask))
1444 {
1445 error_message = _(": invalid membar mask name");
1446 goto error;
1447 }
1448 kmask |= mask;
47926f60
KH		 1449 while (*s == ' ')
1450 ++s;
252b5132
RH		 1451 if (*s == '|' || *s == '+')
1452 ++s;
47926f60
KH		 1453 while (*s == ' ')
1454 ++s;
252b5132
RH		 1455 }
1456 }
1457 else
1458 {
1459 if (! parse_const_expr_arg (&s, &kmask))
1460 {
1461 error_message = _(": invalid membar mask expression");
1462 goto error;
1463 }
1464 if (kmask < 0 || kmask > 127)
1465 {
1466 error_message = _(": invalid membar mask number");
1467 goto error;
1468 }
1469 }
1470
1471 opcode |= MEMBAR (kmask);
1472 continue;
1473 }
1474
1475 case '*':
1476 {
1477 int fcn = 0;
1478
1479 /* Parse a prefetch function. */
1480 if (*s == '#')
1481 {
1482 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1483 {
1484 error_message = _(": invalid prefetch function name");
1485 goto error;
1486 }
1487 }
1488 else
1489 {
1490 if (! parse_const_expr_arg (&s, &fcn))
1491 {
1492 error_message = _(": invalid prefetch function expression");
1493 goto error;
1494 }
1495 if (fcn < 0 || fcn > 31)
1496 {
1497 error_message = _(": invalid prefetch function number");
1498 goto error;
1499 }
1500 }
1501 opcode |= RD (fcn);
1502 continue;
1503 }
1504
1505 case '!':
1506 case '?':
1507 /* Parse a sparc64 privileged register. */
1508 if (*s == '%')
1509 {
1510 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1511 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1512
1513 s += 1;
1514 while (p->name[0] > s[0])
1515 p++;
1516 while (p->name[0] == s[0])
1517 {
1518 len = strlen (p->name);
1519 if (strncmp (p->name, s, len) == 0)
1520 break;
1521 p++;
1522 }
1523 if (p->name[0] != s[0])
1524 {
1525 error_message = _(": unrecognizable privileged register");
1526 goto error;
1527 }
1528 if (*args == '?')
1529 opcode |= (p->regnum << 14);
1530 else
1531 opcode |= (p->regnum << 25);
1532 s += len;
1533 continue;
1534 }
1535 else
1536 {
1537 error_message = _(": unrecognizable privileged register");
1538 goto error;
1539 }
1540
1541 case '_':
1542 case '/':
1543 /* Parse a v9a ancillary state register. */
1544 if (*s == '%')
1545 {
1546 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1547 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1548
1549 s += 1;
1550 while (p->name[0] > s[0])
1551 p++;
1552 while (p->name[0] == s[0])
1553 {
1554 len = strlen (p->name);
1555 if (strncmp (p->name, s, len) == 0)
1556 break;
1557 p++;
1558 }
1559 if (p->name[0] != s[0])
1560 {
1561 error_message = _(": unrecognizable v9a ancillary state register");
1562 goto error;
1563 }
1564 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1565 {
1566 error_message = _(": rd on write only ancillary state register");
1567 goto error;
e0c6ed95 1568 }
252b5132
RH		 1569 if (*args == '/')
1570 opcode |= (p->regnum << 14);
1571 else
1572 opcode |= (p->regnum << 25);
1573 s += len;
1574 continue;
1575 }
1576 else
1577 {
1578 error_message = _(": unrecognizable v9a ancillary state register");
1579 goto error;
1580 }
1581
1582 case 'M':
1583 case 'm':
1584 if (strncmp (s, "%asr", 4) == 0)
1585 {
1586 s += 4;
1587
1588 if (isdigit ((unsigned char) *s))
1589 {
1590 long num = 0;
1591
1592 while (isdigit ((unsigned char) *s))
1593 {
1594 num = num * 10 + *s - '0';
1595 ++s;
1596 }
1597
1598 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1599 {
1600 if (num < 16 || 31 < num)
1601 {
1602 error_message = _(": asr number must be between 16 and 31");
1603 goto error;
1604 }
1605 }
1606 else
1607 {
1608 if (num < 0 || 31 < num)
1609 {
1610 error_message = _(": asr number must be between 0 and 31");
1611 goto error;
1612 }
1613 }
1614
1615 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1616 continue;
1617 }
1618 else
1619 {
1620 error_message = _(": expecting %asrN");
1621 goto error;
1622 }
e0c6ed95 1623 } /* if %asr */
252b5132
RH		 1624 break;
1625
1626 case 'I':
1627 the_insn.reloc = BFD_RELOC_SPARC_11;
1628 goto immediate;
1629
1630 case 'j':
1631 the_insn.reloc = BFD_RELOC_SPARC_10;
1632 goto immediate;
1633
1634 case 'X':
1635 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1636 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1637 the_insn.reloc = BFD_RELOC_SPARC_5;
1638 else
1639 the_insn.reloc = BFD_RELOC_SPARC13;
1640 /* These fields are unsigned, but for upward compatibility,
1641 allow negative values as well. */
1642 goto immediate;
1643
1644 case 'Y':
1645 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1646 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1647 the_insn.reloc = BFD_RELOC_SPARC_6;
1648 else
1649 the_insn.reloc = BFD_RELOC_SPARC13;
1650 /* These fields are unsigned, but for upward compatibility,
1651 allow negative values as well. */
1652 goto immediate;
1653
1654 case 'k':
1655 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1656 the_insn.pcrel = 1;
1657 goto immediate;
1658
1659 case 'G':
1660 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1661 the_insn.pcrel = 1;
1662 goto immediate;
1663
1664 case 'N':
1665 if (*s == 'p' && s[1] == 'n')
1666 {
1667 s += 2;
1668 continue;
1669 }
1670 break;
1671
1672 case 'T':
1673 if (*s == 'p' && s[1] == 't')
1674 {
1675 s += 2;
1676 continue;
1677 }
1678 break;
1679
1680 case 'z':
1681 if (*s == ' ')
1682 {
1683 ++s;
1684 }
1685 if (strncmp (s, "%icc", 4) == 0)
1686 {
1687 s += 4;
1688 continue;
1689 }
1690 break;
1691
1692 case 'Z':
1693 if (*s == ' ')
1694 {
1695 ++s;
1696 }
1697 if (strncmp (s, "%xcc", 4) == 0)
1698 {
1699 s += 4;
1700 continue;
1701 }
1702 break;
1703
1704 case '6':
1705 if (*s == ' ')
1706 {
1707 ++s;
1708 }
1709 if (strncmp (s, "%fcc0", 5) == 0)
1710 {
1711 s += 5;
1712 continue;
1713 }
1714 break;
1715
1716 case '7':
1717 if (*s == ' ')
1718 {
1719 ++s;
1720 }
1721 if (strncmp (s, "%fcc1", 5) == 0)
1722 {
1723 s += 5;
1724 continue;
1725 }
1726 break;
1727
1728 case '8':
1729 if (*s == ' ')
1730 {
1731 ++s;
1732 }
1733 if (strncmp (s, "%fcc2", 5) == 0)
1734 {
1735 s += 5;
1736 continue;
1737 }
1738 break;
1739
1740 case '9':
1741 if (*s == ' ')
1742 {
1743 ++s;
1744 }
1745 if (strncmp (s, "%fcc3", 5) == 0)
1746 {
1747 s += 5;
1748 continue;
1749 }
1750 break;
1751
1752 case 'P':
1753 if (strncmp (s, "%pc", 3) == 0)
1754 {
1755 s += 3;
1756 continue;
1757 }
1758 break;
1759
1760 case 'W':
1761 if (strncmp (s, "%tick", 5) == 0)
1762 {
1763 s += 5;
1764 continue;
1765 }
1766 break;
1767
e0c6ed95 1768 case '\0': /* End of args. */
252b5132
RH		 1769 if (*s == '\0')
1770 {
1771 match = 1;
1772 }
1773 break;
1774
1775 case '+':
1776 if (*s == '+')
1777 {
1778 ++s;
1779 continue;
1780 }
1781 if (*s == '-')
1782 {
1783 continue;
1784 }
1785 break;
1786
e0c6ed95 1787 case '[': /* These must match exactly. */
252b5132
RH		 1788 case ']':
1789 case ',':
1790 case ' ':
1791 if (*s++ == *args)
1792 continue;
1793 break;
1794
e0c6ed95 1795 case '#': /* Must be at least one digit. */
252b5132
RH		 1796 if (isdigit ((unsigned char) *s++))
1797 {
1798 while (isdigit ((unsigned char) *s))
1799 {
1800 ++s;
1801 }
1802 continue;
1803 }
1804 break;
1805
e0c6ed95 1806 case 'C': /* Coprocessor state register. */
252b5132
RH		 1807 if (strncmp (s, "%csr", 4) == 0)
1808 {
1809 s += 4;
1810 continue;
1811 }
1812 break;
1813
e0c6ed95 1814 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 1815 case 'c':
1816 case 'D':
1817 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1818 {
1819 mask = *s++;
1820 if (isdigit ((unsigned char) *s))
1821 {
1822 mask = 10 * (mask - '0') + (*s++ - '0');
1823 if (mask >= 32)
1824 {
1825 break;
1826 }
1827 }
1828 else
1829 {
1830 mask -= '0';
1831 }
1832 switch (*args)
1833 {
1834
1835 case 'b':
1836 opcode |= mask << 14;
1837 continue;
1838
1839 case 'c':
1840 opcode |= mask;
1841 continue;
1842
1843 case 'D':
1844 opcode |= mask << 25;
1845 continue;
1846 }
1847 }
1848 break;
1849
1850 case 'r': /* next operand must be a register */
1851 case 'O':
1852 case '1':
1853 case '2':
1854 case 'd':
1855 if (*s++ == '%')
1856 {
1857 switch (c = *s++)
1858 {
1859
1860 case 'f': /* frame pointer */
1861 if (*s++ == 'p')
1862 {
1863 mask = 0x1e;
1864 break;
1865 }
1866 goto error;
1867
1868 case 'g': /* global register */
a22b281c
RH		 1869 c = *s++;
1870 if (isoctal (c))
252b5132
RH		 1871 {
1872 mask = c - '0';
1873 break;
1874 }
1875 goto error;
1876
1877 case 'i': /* in register */
a22b281c
RH		 1878 c = *s++;
1879 if (isoctal (c))
252b5132
RH		 1880 {
1881 mask = c - '0' + 24;
1882 break;
1883 }
1884 goto error;
1885
1886 case 'l': /* local register */
a22b281c
RH		 1887 c = *s++;
1888 if (isoctal (c))
252b5132
RH		 1889 {
1890 mask = (c - '0' + 16);
1891 break;
1892 }
1893 goto error;
1894
1895 case 'o': /* out register */
a22b281c
RH		 1896 c = *s++;
1897 if (isoctal (c))
252b5132
RH		 1898 {
1899 mask = (c - '0' + 8);
1900 break;
1901 }
1902 goto error;
1903
1904 case 's': /* stack pointer */
1905 if (*s++ == 'p')
1906 {
1907 mask = 0xe;
1908 break;
1909 }
1910 goto error;
1911
1912 case 'r': /* any register */
1913 if (!isdigit ((unsigned char) (c = *s++)))
1914 {
1915 goto error;
1916 }
1917 /* FALLTHROUGH */
1918 case '0':
1919 case '1':
1920 case '2':
1921 case '3':
1922 case '4':
1923 case '5':
1924 case '6':
1925 case '7':
1926 case '8':
1927 case '9':
1928 if (isdigit ((unsigned char) *s))
1929 {
1930 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1931 {
1932 goto error;
1933 }
1934 }
1935 else
1936 {
1937 c -= '0';
1938 }
1939 mask = c;
1940 break;
1941
1942 default:
1943 goto error;
1944 }
1945
6d8809aa 1946 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 1947 && no_undeclared_regs && ! globals[mask])
79bd78be 1948 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 1949
252b5132
RH		 1950 /* Got the register, now figure out where
1951 it goes in the opcode. */
1952 switch (*args)
1953 {
1954 case '1':
1955 opcode |= mask << 14;
1956 continue;
1957
1958 case '2':
1959 opcode |= mask;
1960 continue;
1961
1962 case 'd':
1963 opcode |= mask << 25;
1964 continue;
1965
1966 case 'r':
1967 opcode |= (mask << 25) | (mask << 14);
1968 continue;
1969
1970 case 'O':
1971 opcode |= (mask << 25) | (mask << 0);
1972 continue;
1973 }
1974 }
1975 break;
1976
1977 case 'e': /* next operand is a floating point register */
1978 case 'v':
1979 case 'V':
1980
1981 case 'f':
1982 case 'B':
1983 case 'R':
1984
1985 case 'g':
1986 case 'H':
1987 case 'J':
1988 {
1989 char format;
1990
1991 if (*s++ == '%'
1992 && ((format = *s) == 'f')
1993 && isdigit ((unsigned char) *++s))
1994 {
1995 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1996 {
1997 mask = 10 * mask + (*s - '0');
1998 } /* read the number */
1999
2000 if ((*args == 'v'
2001 || *args == 'B'
2002 || *args == 'H')
2003 && (mask & 1))
2004 {
2005 break;
2006 } /* register must be even numbered */
2007
2008 if ((*args == 'V'
2009 || *args == 'R'
2010 || *args == 'J')
2011 && (mask & 3))
2012 {
2013 break;
2014 } /* register must be multiple of 4 */
2015
2016 if (mask >= 64)
2017 {
2018 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2019 error_message = _(": There are only 64 f registers; [0-63]");
2020 else
2021 error_message = _(": There are only 32 f registers; [0-31]");
2022 goto error;
2023 } /* on error */
2024 else if (mask >= 32)
2025 {
2026 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2027 {
2028 v9_arg_p = 1;
2029 mask -= 31; /* wrap high bit */
2030 }
2031 else
2032 {
2033 error_message = _(": There are only 32 f registers; [0-31]");
2034 goto error;
2035 }
2036 }
2037 }
2038 else
2039 {
2040 break;
ab3e48dc 2041 } /* if not an 'f' register. */
252b5132
RH		 2042
2043 switch (*args)
2044 {
2045 case 'v':
2046 case 'V':
2047 case 'e':
2048 opcode |= RS1 (mask);
2049 continue;
2050
252b5132
RH		 2051 case 'f':
2052 case 'B':
2053 case 'R':
2054 opcode |= RS2 (mask);
2055 continue;
2056
2057 case 'g':
2058 case 'H':
2059 case 'J':
2060 opcode |= RD (mask);
2061 continue;
ab3e48dc 2062 } /* Pack it in. */
252b5132
RH		 2063
2064 know (0);
2065 break;
ab3e48dc 2066 } /* float arg */
252b5132
RH		 2067
2068 case 'F':
2069 if (strncmp (s, "%fsr", 4) == 0)
2070 {
2071 s += 4;
2072 continue;
2073 }
2074 break;
2075
ab3e48dc
KH		 2076 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2077 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2078 goto immediate;
2079
ab3e48dc 2080 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2081 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2082 the_insn.pcrel = 1;
2083 goto immediate;
2084
ab3e48dc 2085 case 'L': /* 30 bit immediate */
252b5132
RH		 2086 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2087 the_insn.pcrel = 1;
2088 goto immediate;
2089
63fab58c 2090 case 'h':
ab3e48dc 2091 case 'n': /* 22 bit immediate */
252b5132
RH		 2092 the_insn.reloc = BFD_RELOC_SPARC22;
2093 goto immediate;
2094
ab3e48dc 2095 case 'i': /* 13 bit immediate */
252b5132
RH		 2096 the_insn.reloc = BFD_RELOC_SPARC13;
2097
2098 /* fallthrough */
2099
2100 immediate:
2101 if (*s == ' ')
2102 s++;
2103
cf9a1301
RH		 2104 {
2105 char *s1;
2106 char *op_arg = NULL;
2107 expressionS op_exp;
2108 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2109
2110 /* Check for %hi, etc. */
2111 if (*s == '%')
2112 {
2113 static const struct ops {
2114 /* The name as it appears in assembler. */
2115 char *name;
2116 /* strlen (name), precomputed for speed */
2117 int len;
2118 /* The reloc this pseudo-op translates to. */
2119 int reloc;
2120 /* Non-zero if for v9 only. */
2121 int v9_p;
2122 /* Non-zero if can be used in pc-relative contexts. */
2123 int pcrel_p;/*FIXME:wip*/
2124 } ops[] = {
2125 /* hix/lox must appear before hi/lo so %hix won't be
2126 mistaken for %hi. */
2127 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2128 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2129 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2130 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2131 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2132 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2133 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2134 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2135 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2136 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2137 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2138 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
c2158c24 2139 { NULL, 0, 0, 0, 0 }
cf9a1301
RH		 2140 };
2141 const struct ops *o;
e0c6ed95 2142
cf9a1301
RH		 2143 for (o = ops; o->name; o++)
2144 if (strncmp (s + 1, o->name, o->len) == 0)
2145 break;
2146 if (o->name == NULL)
252b5132 2147 break;
e0c6ed95 2148
cf9a1301
RH		 2149 if (s[o->len + 1] != '(')
2150 {
2151 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2152 return special_case;
cf9a1301 2153 }
252b5132 2154
cf9a1301
RH		 2155 op_arg = o->name;
2156 the_insn.reloc = o->reloc;
2157 s += o->len + 2;
2158 v9_arg_p = o->v9_p;
2159 }
2160
2161 /* Note that if the get_expression() fails, we will still
2162 have created U entries in the symbol table for the
2163 'symbols' in the input string. Try not to create U
2164 symbols for registers, etc. */
252b5132 2165
252b5132
RH		 2166 /* This stuff checks to see if the expression ends in
2167 +%reg. If it does, it removes the register from
2168 the expression, and re-sets 's' to point to the
2169 right place. */
2170
cf9a1301
RH		 2171 if (op_arg)
2172 {
2173 int npar = 0;
2174
2175 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2176 if (*s1 == '(')
2177 npar++;
2178 else if (*s1 == ')')
2179 {
2180 if (!npar)
2181 break;
2182 npar--;
2183 }
2184
2185 if (*s1 != ')')
2186 {
2187 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2188 return special_case;
cf9a1301 2189 }
e0c6ed95 2190
cf9a1301
RH		 2191 *s1 = '\0';
2192 (void) get_expression (s);
2193 *s1 = ')';
2194 s = s1 + 1;
2195 if (*s == ',' || *s == ']' || !*s)
2196 continue;
2197 if (*s != '+' && *s != '-')
2198 {
2199 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2200 return special_case;
cf9a1301
RH		 2201 }
2202 *s1 = '0';
2203 s = s1;
2204 op_exp = the_insn.exp;
e0c6ed95 2205 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2206 }
252b5132 2207
e0c6ed95
AM		 2208 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2209 ;
252b5132
RH		 2210
2211 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2212 {
2213 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301
RH		 2214 s1 -= 3;
2215 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2216 s1 -= 4;
2217 else
2218 s1 = NULL;
2219 if (s1)
252b5132 2220 {
252b5132 2221 *s1 = '\0';
1eb7027c
RH		 2222 if (op_arg && s1 == s + 1)
2223 the_insn.exp.X_op = O_absent;
2224 else
2225 (void) get_expression (s);
252b5132 2226 *s1 = '+';
cf9a1301
RH		 2227 if (op_arg)
2228 *s = ')';
252b5132 2229 s = s1;
252b5132 2230 }
cf9a1301
RH		 2231 }
2232 else
2233 s1 = NULL;
2234
2235 if (!s1)
2236 {
2237 (void) get_expression (s);
2238 if (op_arg)
2239 *s = ')';
2240 s = expr_end;
2241 }
2242
2243 if (op_arg)
2244 {
2245 the_insn.exp2 = the_insn.exp;
2246 the_insn.exp = op_exp;
2247 if (the_insn.exp2.X_op == O_absent)
2248 the_insn.exp2.X_op = O_illegal;
2249 else if (the_insn.exp.X_op == O_absent)
252b5132 2250 {
cf9a1301
RH		 2251 the_insn.exp = the_insn.exp2;
2252 the_insn.exp2.X_op = O_illegal;
2253 }
2254 else if (the_insn.exp.X_op == O_constant)
2255 {
2256 valueT val = the_insn.exp.X_add_number;
2257 switch (the_insn.reloc)
2258 {
1b50c718
ILT		 2259 default:
2260 break;
2261
cf9a1301
RH		 2262 case BFD_RELOC_SPARC_HH22:
2263 val = BSR (val, 32);
e0c6ed95 2264 /* Fall through. */
cf9a1301
RH		 2265
2266 case BFD_RELOC_SPARC_LM22:
2267 case BFD_RELOC_HI22:
2268 val = (val >> 10) & 0x3fffff;
2269 break;
2270
2271 case BFD_RELOC_SPARC_HM10:
2272 val = BSR (val, 32);
e0c6ed95 2273 /* Fall through. */
cf9a1301
RH		 2274
2275 case BFD_RELOC_LO10:
2276 val &= 0x3ff;
2277 break;
2278
2279 case BFD_RELOC_SPARC_H44:
2280 val >>= 22;
2281 val &= 0x3fffff;
2282 break;
2283
2284 case BFD_RELOC_SPARC_M44:
2285 val >>= 12;
2286 val &= 0x3ff;
2287 break;
2288
2289 case BFD_RELOC_SPARC_L44:
2290 val &= 0xfff;
2291 break;
2292
2293 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2294 val = ~val;
cf9a1301
RH		 2295 val = (val >> 10) & 0x3fffff;
2296 break;
2297
2298 case BFD_RELOC_SPARC_LOX10:
2299 val = (val & 0x3ff) | 0x1c00;
2300 break;
2301 }
2302 the_insn.exp = the_insn.exp2;
2303 the_insn.exp.X_add_number += val;
2304 the_insn.exp2.X_op = O_illegal;
2305 the_insn.reloc = old_reloc;
2306 }
2307 else if (the_insn.exp2.X_op != O_constant)
2308 {
2309 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2310 return special_case;
cf9a1301
RH		 2311 }
2312 else
2313 {
dabe3bbc 2314 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2315 || the_insn.reloc != BFD_RELOC_LO10
2316 || sparc_arch_size != 64
2317 || sparc_pic_code)
2318 {
2319 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2320 return special_case;
cf9a1301
RH		 2321 }
2322 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2323 }
2324 }
2325 }
252b5132
RH		 2326 /* Check for constants that don't require emitting a reloc. */
2327 if (the_insn.exp.X_op == O_constant
2328 && the_insn.exp.X_add_symbol == 0
2329 && the_insn.exp.X_op_symbol == 0)
2330 {
2331 /* For pc-relative call instructions, we reject
2332 constants to get better code. */
2333 if (the_insn.pcrel
2334 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2335 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2336 {
2337 error_message = _(": PC-relative operand can't be a constant");
2338 goto error;
2339 }
2340
2341 /* Constants that won't fit are checked in md_apply_fix3
2342 and bfd_install_relocation.
2343 ??? It would be preferable to install the constants
2344 into the insn here and save having to create a fixS
2345 for each one. There already exists code to handle
2346 all the various cases (e.g. in md_apply_fix3 and
2347 bfd_install_relocation) so duplicating all that code
2348 here isn't right. */
2349 }
2350
2351 continue;
2352
2353 case 'a':
2354 if (*s++ == 'a')
2355 {
2356 opcode |= ANNUL;
2357 continue;
2358 }
2359 break;
2360
2361 case 'A':
2362 {
2363 int asi = 0;
2364
2365 /* Parse an asi. */
2366 if (*s == '#')
2367 {
2368 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2369 {
2370 error_message = _(": invalid ASI name");
2371 goto error;
2372 }
2373 }
2374 else
2375 {
2376 if (! parse_const_expr_arg (&s, &asi))
2377 {
2378 error_message = _(": invalid ASI expression");
2379 goto error;
2380 }
2381 if (asi < 0 || asi > 255)
2382 {
2383 error_message = _(": invalid ASI number");
2384 goto error;
2385 }
2386 }
2387 opcode |= ASI (asi);
2388 continue;
e0c6ed95 2389 } /* Alternate space. */
252b5132
RH		 2390
2391 case 'p':
2392 if (strncmp (s, "%psr", 4) == 0)
2393 {
2394 s += 4;
2395 continue;
2396 }
2397 break;
2398
e0c6ed95 2399 case 'q': /* Floating point queue. */
252b5132
RH		 2400 if (strncmp (s, "%fq", 3) == 0)
2401 {
2402 s += 3;
2403 continue;
2404 }
2405 break;
2406
e0c6ed95 2407 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2408 if (strncmp (s, "%cq", 3) == 0)
2409 {
2410 s += 3;
2411 continue;
2412 }
2413 break;
2414
2415 case 'S':
2416 if (strcmp (str, "set") == 0
2417 || strcmp (str, "setuw") == 0)
2418 {
2419 special_case = SPECIAL_CASE_SET;
2420 continue;
2421 }
2422 else if (strcmp (str, "setsw") == 0)
2423 {
2424 special_case = SPECIAL_CASE_SETSW;
2425 continue;
2426 }
2427 else if (strcmp (str, "setx") == 0)
2428 {
2429 special_case = SPECIAL_CASE_SETX;
2430 continue;
2431 }
2432 else if (strncmp (str, "fdiv", 4) == 0)
2433 {
2434 special_case = SPECIAL_CASE_FDIV;
2435 continue;
2436 }
2437 break;
2438
2439 case 'o':
2440 if (strncmp (s, "%asi", 4) != 0)
2441 break;
2442 s += 4;
2443 continue;
2444
2445 case 's':
2446 if (strncmp (s, "%fprs", 5) != 0)
2447 break;
2448 s += 5;
2449 continue;
2450
2451 case 'E':
2452 if (strncmp (s, "%ccr", 4) != 0)
2453 break;
2454 s += 4;
2455 continue;
2456
2457 case 't':
2458 if (strncmp (s, "%tbr", 4) != 0)
2459 break;
2460 s += 4;
2461 continue;
2462
2463 case 'w':
2464 if (strncmp (s, "%wim", 4) != 0)
2465 break;
2466 s += 4;
2467 continue;
2468
2469 case 'x':
2470 {
2471 char *push = input_line_pointer;
2472 expressionS e;
2473
2474 input_line_pointer = s;
2475 expression (&e);
2476 if (e.X_op == O_constant)
2477 {
2478 int n = e.X_add_number;
2479 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2480 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2481 else
2482 opcode |= e.X_add_number << 5;
2483 }
2484 else
2485 as_bad (_("non-immediate OPF operand, ignored"));
2486 s = input_line_pointer;
2487 input_line_pointer = push;
2488 continue;
2489 }
2490
2491 case 'y':
2492 if (strncmp (s, "%y", 2) != 0)
2493 break;
2494 s += 2;
2495 continue;
2496
2497 case 'u':
2498 case 'U':
2499 {
2500 /* Parse a sparclet cpreg. */
2501 int cpreg;
2502 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2503 {
2504 error_message = _(": invalid cpreg name");
2505 goto error;
2506 }
2507 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2508 continue;
2509 }
2510
2511 default:
2512 as_fatal (_("failed sanity check."));
e0c6ed95 2513 } /* switch on arg code. */
252b5132
RH		 2514
2515 /* Break out of for() loop. */
2516 break;
e0c6ed95 2517 } /* For each arg that we expect. */
252b5132
RH		 2518
2519 error:
2520 if (match == 0)
2521 {
e0c6ed95 2522 /* Args don't match. */
252b5132
RH		 2523 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2524 && (insn->name == insn[1].name
2525 || !strcmp (insn->name, insn[1].name)))
2526 {
2527 ++insn;
2528 s = argsStart;
2529 continue;
2530 }
2531 else
2532 {
2533 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2534 return special_case;
252b5132
RH		 2535 }
2536 }
2537 else
2538 {
e0c6ed95 2539 /* We have a match. Now see if the architecture is OK. */
252b5132
RH		 2540 int needed_arch_mask = insn->architecture;
2541
2542 if (v9_arg_p)
2543 {
ab3e48dc
KH		 2544 needed_arch_mask &= ~((1 << SPARC_OPCODE_ARCH_V9)
2545 | (1 << SPARC_OPCODE_ARCH_V9A));
252b5132
RH		 2546 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2547 }
2548
e0c6ed95
AM		 2549 if (needed_arch_mask
2550 & SPARC_OPCODE_SUPPORTED (current_architecture))
2551 /* OK. */
2552 ;
252b5132 2553 /* Can we bump up the architecture? */
e0c6ed95
AM		 2554 else if (needed_arch_mask
2555 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2556 {
2557 enum sparc_opcode_arch_val needed_architecture =
2558 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2559 & needed_arch_mask);
2560
2561 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2562 if (warn_on_bump
2563 && needed_architecture > warn_after_architecture)
2564 {
2565 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2566 sparc_opcode_archs[current_architecture].name,
2567 sparc_opcode_archs[needed_architecture].name,
2568 str);
2569 warn_after_architecture = needed_architecture;
2570 }
2571 current_architecture = needed_architecture;
2572 }
2573 /* Conflict. */
2574 /* ??? This seems to be a bit fragile. What if the next entry in
2575 the opcode table is the one we want and it is supported?
2576 It is possible to arrange the table today so that this can't
2577 happen but what about tomorrow? */
2578 else
2579 {
e0c6ed95 2580 int arch, printed_one_p = 0;
252b5132
RH		 2581 char *p;
2582 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2583
2584 /* Create a list of the architectures that support the insn. */
e0c6ed95 2585 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2586 p = required_archs;
2587 arch = sparc_ffs (needed_arch_mask);
2588 while ((1 << arch) <= needed_arch_mask)
2589 {
2590 if ((1 << arch) & needed_arch_mask)
2591 {
2592 if (printed_one_p)
2593 *p++ = '|';
2594 strcpy (p, sparc_opcode_archs[arch].name);
2595 p += strlen (p);
2596 printed_one_p = 1;
2597 }
2598 ++arch;
2599 }
2600
2601 as_bad (_("Architecture mismatch on \"%s\"."), str);
2602 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2603 required_archs,
2604 sparc_opcode_archs[max_architecture].name);
a22b281c 2605 return special_case;
252b5132 2606 }
e0c6ed95 2607 } /* If no match. */
252b5132
RH		 2608
2609 break;
e0c6ed95 2610 } /* Forever looking for a match. */
252b5132
RH		 2611
2612 the_insn.opcode = opcode;
a22b281c 2613 return special_case;
252b5132
RH		 2614}
2615
2616/* Parse an argument that can be expressed as a keyword.
2617 (eg: #StoreStore or %ccfr).
2618 The result is a boolean indicating success.
2619 If successful, INPUT_POINTER is updated. */
2620
2621static int
2622parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2623 int (*lookup_fn) PARAMS ((const char *));
2624 char **input_pointerP;
2625 int *valueP;
2626{
2627 int value;
2628 char c, *p, *q;
2629
2630 p = *input_pointerP;
2631 for (q = p + (*p == '#' || *p == '%');
2632 isalnum ((unsigned char) *q) || *q == '_';
2633 ++q)
2634 continue;
2635 c = *q;
2636 *q = 0;
2637 value = (*lookup_fn) (p);
2638 *q = c;
2639 if (value == -1)
2640 return 0;
2641 *valueP = value;
2642 *input_pointerP = q;
2643 return 1;
2644}
2645
2646/* Parse an argument that is a constant expression.
2647 The result is a boolean indicating success. */
2648
2649static int
2650parse_const_expr_arg (input_pointerP, valueP)
2651 char **input_pointerP;
2652 int *valueP;
2653{
2654 char *save = input_line_pointer;
2655 expressionS exp;
2656
2657 input_line_pointer = *input_pointerP;
2658 /* The next expression may be something other than a constant
2659 (say if we're not processing the right variant of the insn).
2660 Don't call expression unless we're sure it will succeed as it will
2661 signal an error (which we want to defer until later). */
2662 /* FIXME: It might be better to define md_operand and have it recognize
2663 things like %asi, etc. but continuing that route through to the end
2664 is a lot of work. */
2665 if (*input_line_pointer == '%')
2666 {
2667 input_line_pointer = save;
2668 return 0;
2669 }
2670 expression (&exp);
2671 *input_pointerP = input_line_pointer;
2672 input_line_pointer = save;
2673 if (exp.X_op != O_constant)
2674 return 0;
2675 *valueP = exp.X_add_number;
2676 return 1;
2677}
2678
2679/* Subroutine of sparc_ip to parse an expression. */
2680
2681static int
2682get_expression (str)
2683 char *str;
2684{
2685 char *save_in;
2686 segT seg;
2687
2688 save_in = input_line_pointer;
2689 input_line_pointer = str;
2690 seg = expression (&the_insn.exp);
2691 if (seg != absolute_section
2692 && seg != text_section
2693 && seg != data_section
2694 && seg != bss_section
2695 && seg != undefined_section)
2696 {
2697 the_insn.error = _("bad segment");
2698 expr_end = input_line_pointer;
2699 input_line_pointer = save_in;
2700 return 1;
2701 }
2702 expr_end = input_line_pointer;
2703 input_line_pointer = save_in;
2704 return 0;
2705}
2706
2707/* Subroutine of md_assemble to output one insn. */
2708
2709static void
2710output_insn (insn, the_insn)
2711 const struct sparc_opcode *insn;
2712 struct sparc_it *the_insn;
2713{
2714 char *toP = frag_more (4);
2715
e0c6ed95 2716 /* Put out the opcode. */
252b5132
RH		 2717 if (INSN_BIG_ENDIAN)
2718 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2719 else
2720 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2721
e0c6ed95 2722 /* Put out the symbol-dependent stuff. */
252b5132
RH		 2723 if (the_insn->reloc != BFD_RELOC_NONE)
2724 {
e0c6ed95
AM		 2725 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2726 (toP - frag_now->fr_literal), /* Where. */
2727 4, /* Size. */
252b5132
RH		 2728 &the_insn->exp,
2729 the_insn->pcrel,
2730 the_insn->reloc);
2731 /* Turn off overflow checking in fixup_segment. We'll do our
2732 own overflow checking in md_apply_fix3. This is necessary because
2733 the insn size is 4 and fixup_segment will signal an overflow for
2734 large 8 byte quantities. */
2735 fixP->fx_no_overflow = 1;
dabe3bbc
RH		 2736 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2737 fixP->tc_fix_data = the_insn->exp2.X_add_number;
252b5132
RH		 2738 }
2739
2740 last_insn = insn;
2741 last_opcode = the_insn->opcode;
2742}
2743\f
e0c6ed95
AM		 2744/* This is identical to the md_atof in m68k.c. I think this is right,
2745 but I'm not sure.
252b5132 2746
e0c6ed95
AM		 2747 Turn a string in input_line_pointer into a floating point constant
2748 of type TYPE, and store the appropriate bytes in *LITP. The number
2749 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2750 returned, or NULL on OK. */
252b5132 2751
e0c6ed95 2752/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 2753#define MAX_LITTLENUMS 6
2754
2755char *
2756md_atof (type, litP, sizeP)
2757 char type;
2758 char *litP;
2759 int *sizeP;
2760{
e0c6ed95 2761 int i, prec;
252b5132
RH		 2762 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2763 char *t;
2764
2765 switch (type)
2766 {
2767 case 'f':
2768 case 'F':
2769 case 's':
2770 case 'S':
2771 prec = 2;
2772 break;
2773
2774 case 'd':
2775 case 'D':
2776 case 'r':
2777 case 'R':
2778 prec = 4;
2779 break;
2780
2781 case 'x':
2782 case 'X':
2783 prec = 6;
2784 break;
2785
2786 case 'p':
2787 case 'P':
2788 prec = 6;
2789 break;
2790
2791 default:
2792 *sizeP = 0;
2793 return _("Bad call to MD_ATOF()");
2794 }
2795
2796 t = atof_ieee (input_line_pointer, type, words);
2797 if (t)
2798 input_line_pointer = t;
2799 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2800
2801 if (target_big_endian)
2802 {
2803 for (i = 0; i < prec; i++)
2804 {
ab3e48dc
KH		 2805 md_number_to_chars (litP, (valueT) words[i],
2806 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2807 litP += sizeof (LITTLENUM_TYPE);
2808 }
2809 }
2810 else
2811 {
2812 for (i = prec - 1; i >= 0; i--)
2813 {
ab3e48dc
KH		 2814 md_number_to_chars (litP, (valueT) words[i],
2815 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2816 litP += sizeof (LITTLENUM_TYPE);
2817 }
2818 }
e0c6ed95 2819
252b5132
RH		 2820 return 0;
2821}
2822
2823/* Write a value out to the object file, using the appropriate
2824 endianness. */
2825
2826void
2827md_number_to_chars (buf, val, n)
2828 char *buf;
2829 valueT val;
2830 int n;
2831{
2832 if (target_big_endian)
2833 number_to_chars_bigendian (buf, val, n);
2834 else if (target_little_endian_data
2835 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 2836 /* Output debug words, which are not in allocated sections, as big
2837 endian. */
252b5132
RH		 2838 number_to_chars_bigendian (buf, val, n);
2839 else if (target_little_endian_data || ! target_big_endian)
2840 number_to_chars_littleendian (buf, val, n);
2841}
2842\f
2843/* Apply a fixS to the frags, now that we know the value it ought to
2844 hold. */
2845
2846int
2847md_apply_fix3 (fixP, value, segment)
2848 fixS *fixP;
2849 valueT *value;
2850 segT segment;
2851{
2852 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2853 offsetT val;
2854 long insn;
2855
2856 val = *value;
2857
2858 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2859
e0c6ed95 2860 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 2861
2862#ifdef OBJ_ELF
2863 /* FIXME: SPARC ELF relocations don't use an addend in the data
2864 field itself. This whole approach should be somehow combined
2865 with the calls to bfd_install_relocation. Also, the value passed
2866 in by fixup_segment includes the value of a defined symbol. We
2867 don't want to include the value of an externally visible symbol. */
2868 if (fixP->fx_addsy != NULL)
2869 {
49309057 2870 if (symbol_used_in_reloc_p (fixP->fx_addsy)
252b5132
RH		 2871 && (S_IS_EXTERNAL (fixP->fx_addsy)
2872 || S_IS_WEAK (fixP->fx_addsy)
2873 || (sparc_pic_code && ! fixP->fx_pcrel)
2874 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2875 && ((bfd_get_section_flags (stdoutput,
2876 S_GET_SEGMENT (fixP->fx_addsy))
2877 & SEC_LINK_ONCE) != 0
2878 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2879 ".gnu.linkonce",
2880 sizeof ".gnu.linkonce" - 1) == 0)))
2881 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2882 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2883 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2884 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2885 return 1;
2886 }
2887#endif
2888
2889 /* This is a hack. There should be a better way to
2890 handle this. Probably in terms of howto fields, once
2891 we can look at these fixups in terms of howtos. */
2892 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2893 val += fixP->fx_where + fixP->fx_frag->fr_address;
2894
2895#ifdef OBJ_AOUT
2896 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2897 generate a reloc, then we just want to let the reloc addend set
2898 the value. We do not want to also stuff the addend into the
2899 object file. Including the addend in the object file works when
2900 doing a static link, because the linker will ignore the object
2901 file contents. However, the dynamic linker does not ignore the
2902 object file contents. */
2903 if (fixP->fx_addsy != NULL
2904 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2905 val = 0;
2906
2907 /* When generating PIC code, we do not want an addend for a reloc
2908 against a local symbol. We adjust fx_addnumber to cancel out the
2909 value already included in val, and to also cancel out the
2910 adjustment which bfd_install_relocation will create. */
2911 if (sparc_pic_code
2912 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2913 && fixP->fx_addsy != NULL
2914 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 2915 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 2916 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2917
2918 /* When generating PIC code, we need to fiddle to get
2919 bfd_install_relocation to do the right thing for a PC relative
2920 reloc against a local symbol which we are going to keep. */
2921 if (sparc_pic_code
2922 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2923 && fixP->fx_addsy != NULL
2924 && (S_IS_EXTERNAL (fixP->fx_addsy)
2925 || S_IS_WEAK (fixP->fx_addsy))
2926 && S_IS_DEFINED (fixP->fx_addsy)
2927 && ! S_IS_COMMON (fixP->fx_addsy))
2928 {
2929 val = 0;
2930 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2931 }
2932#endif
2933
2934 /* If this is a data relocation, just output VAL. */
2935
2936 if (fixP->fx_r_type == BFD_RELOC_16)
2937 {
2938 md_number_to_chars (buf, val, 2);
2939 }
2940 else if (fixP->fx_r_type == BFD_RELOC_32
2941 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2942 {
2943 md_number_to_chars (buf, val, 4);
2944 }
2945 else if (fixP->fx_r_type == BFD_RELOC_64)
2946 {
2947 md_number_to_chars (buf, val, 8);
2948 }
e0c6ed95 2949 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 2950 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2951 {
2952 fixP->fx_done = 0;
2953 return 1;
2954 }
2955 else
2956 {
2957 /* It's a relocation against an instruction. */
2958
2959 if (INSN_BIG_ENDIAN)
2960 insn = bfd_getb32 ((unsigned char *) buf);
2961 else
2962 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 2963
252b5132
RH		 2964 switch (fixP->fx_r_type)
2965 {
2966 case BFD_RELOC_32_PCREL_S2:
2967 val = val >> 2;
2968 /* FIXME: This increment-by-one deserves a comment of why it's
2969 being done! */
2970 if (! sparc_pic_code
2971 || fixP->fx_addsy == NULL
49309057 2972 || symbol_section_p (fixP->fx_addsy))
252b5132 2973 ++val;
6faf3d66 2974
252b5132 2975 insn |= val & 0x3fffffff;
6faf3d66 2976
e0c6ed95 2977 /* See if we have a delay slot. */
6faf3d66
JJ		 2978 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
2979 {
2980#define G0 0
2981#define O7 15
2982#define XCC (2 << 20)
2983#define COND(x) (((x)&0xf)<<25)
2984#define CONDA COND(0x8)
2985#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
2986#define INSN_BA (F2(0,2) | CONDA)
2987#define INSN_OR F3(2, 0x2, 0)
2988#define INSN_NOP F2(0,4)
2989
2990 long delay;
2991
2992 /* If the instruction is a call with either:
2993 restore
2994 arithmetic instruction with rd == %o7
2995 where rs1 != %o7 and rs2 if it is register != %o7
2996 then we can optimize if the call destination is near
2997 by changing the call into a branch always. */
2998 if (INSN_BIG_ENDIAN)
2999 delay = bfd_getb32 ((unsigned char *) buf + 4);
3000 else
3001 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 3002 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 3003 break;
e0c6ed95
AM		 3004 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3005 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3006 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 3007 break;
e0c6ed95
AM		 3008 if ((delay & RS1 (~0)) == RS1 (O7)
3009 || ((delay & F3I (~0)) == 0
3010 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 3011 break;
3012 /* Ensure the branch will fit into simm22. */
3013 if ((val & 0x3fe00000)
3014 && (val & 0x3fe00000) != 0x3fe00000)
3015 break;
3016 /* Check if the arch is v9 and branch will fit
3017 into simm19. */
3018 if (((val & 0x3c0000) == 0
3019 || (val & 0x3c0000) == 0x3c0000)
3020 && (sparc_arch_size == 64
3021 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 3022 /* ba,pt %xcc */
6faf3d66
JJ		 3023 insn = INSN_BPA | (val & 0x7ffff);
3024 else
e0c6ed95 3025 /* ba */
6faf3d66
JJ		 3026 insn = INSN_BA | (val & 0x3fffff);
3027 if (fixP->fx_where >= 4
e0c6ed95
AM		 3028 && ((delay & (0xffffffff ^ RS1 (~0)))
3029 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3030 {
3031 long setter;
3032 int reg;
3033
3034 if (INSN_BIG_ENDIAN)
3035 setter = bfd_getb32 ((unsigned char *) buf - 4);
3036 else
3037 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3038 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3039 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3040 break;
3041 /* The sequence was
3042 or %o7, %g0, %rN
3043 call foo
3044 or %rN, %g0, %o7
3045
3046 If call foo was replaced with ba, replace
3047 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3048 reg = (delay & RS1 (~0)) >> 14;
3049 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3050 || reg == G0 || reg == O7)
3051 break;
3052
3053 if (INSN_BIG_ENDIAN)
3054 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3055 else
3056 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3057 }
3058 }
252b5132
RH		 3059 break;
3060
3061 case BFD_RELOC_SPARC_11:
3062 if (! in_signed_range (val, 0x7ff))
3063 as_bad_where (fixP->fx_file, fixP->fx_line,
3064 _("relocation overflow"));
3065 insn |= val & 0x7ff;
3066 break;
3067
3068 case BFD_RELOC_SPARC_10:
3069 if (! in_signed_range (val, 0x3ff))
3070 as_bad_where (fixP->fx_file, fixP->fx_line,
3071 _("relocation overflow"));
3072 insn |= val & 0x3ff;
3073 break;
3074
3075 case BFD_RELOC_SPARC_7:
3076 if (! in_bitfield_range (val, 0x7f))
3077 as_bad_where (fixP->fx_file, fixP->fx_line,
3078 _("relocation overflow"));
3079 insn |= val & 0x7f;
3080 break;
3081
3082 case BFD_RELOC_SPARC_6:
3083 if (! in_bitfield_range (val, 0x3f))
3084 as_bad_where (fixP->fx_file, fixP->fx_line,
3085 _("relocation overflow"));
3086 insn |= val & 0x3f;
3087 break;
3088
3089 case BFD_RELOC_SPARC_5:
3090 if (! in_bitfield_range (val, 0x1f))
3091 as_bad_where (fixP->fx_file, fixP->fx_line,
3092 _("relocation overflow"));
3093 insn |= val & 0x1f;
3094 break;
3095
3096 case BFD_RELOC_SPARC_WDISP16:
e0c6ed95 3097 /* FIXME: simplify. */
252b5132
RH		 3098 if (((val > 0) && (val & ~0x3fffc))
3099 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3100 as_bad_where (fixP->fx_file, fixP->fx_line,
3101 _("relocation overflow"));
3102 /* FIXME: The +1 deserves a comment. */
3103 val = (val >> 2) + 1;
3104 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3105 break;
3106
3107 case BFD_RELOC_SPARC_WDISP19:
e0c6ed95 3108 /* FIXME: simplify. */
252b5132
RH		 3109 if (((val > 0) && (val & ~0x1ffffc))
3110 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3111 as_bad_where (fixP->fx_file, fixP->fx_line,
3112 _("relocation overflow"));
3113 /* FIXME: The +1 deserves a comment. */
3114 val = (val >> 2) + 1;
3115 insn |= val & 0x7ffff;
3116 break;
3117
3118 case BFD_RELOC_SPARC_HH22:
3119 val = BSR (val, 32);
e0c6ed95 3120 /* Fall through. */
252b5132
RH		 3121
3122 case BFD_RELOC_SPARC_LM22:
3123 case BFD_RELOC_HI22:
3124 if (!fixP->fx_addsy)
3125 {
3126 insn |= (val >> 10) & 0x3fffff;
3127 }
3128 else
3129 {
3130 /* FIXME: Need comment explaining why we do this. */
3131 insn &= ~0xffff;
3132 }
3133 break;
3134
3135 case BFD_RELOC_SPARC22:
3136 if (val & ~0x003fffff)
3137 as_bad_where (fixP->fx_file, fixP->fx_line,
3138 _("relocation overflow"));
3139 insn |= (val & 0x3fffff);
3140 break;
3141
3142 case BFD_RELOC_SPARC_HM10:
3143 val = BSR (val, 32);
e0c6ed95 3144 /* Fall through. */
252b5132
RH		 3145
3146 case BFD_RELOC_LO10:
3147 if (!fixP->fx_addsy)
3148 {
3149 insn |= val & 0x3ff;
3150 }
3151 else
3152 {
3153 /* FIXME: Need comment explaining why we do this. */
3154 insn &= ~0xff;
3155 }
3156 break;
3157
dabe3bbc
RH		 3158 case BFD_RELOC_SPARC_OLO10:
3159 val &= 0x3ff;
3160 val += fixP->tc_fix_data;
e0c6ed95 3161 /* Fall through. */
dabe3bbc 3162
252b5132
RH		 3163 case BFD_RELOC_SPARC13:
3164 if (! in_signed_range (val, 0x1fff))
3165 as_bad_where (fixP->fx_file, fixP->fx_line,
3166 _("relocation overflow"));
3167 insn |= val & 0x1fff;
3168 break;
3169
3170 case BFD_RELOC_SPARC_WDISP22:
3171 val = (val >> 2) + 1;
e0c6ed95 3172 /* Fall through. */
252b5132
RH		 3173 case BFD_RELOC_SPARC_BASE22:
3174 insn |= val & 0x3fffff;
3175 break;
3176
3177 case BFD_RELOC_SPARC_H44:
3178 if (!fixP->fx_addsy)
3179 {
3180 bfd_vma tval = val;
3181 tval >>= 22;
3182 insn |= tval & 0x3fffff;
3183 }
3184 break;
3185
3186 case BFD_RELOC_SPARC_M44:
3187 if (!fixP->fx_addsy)
3188 insn |= (val >> 12) & 0x3ff;
3189 break;
3190
3191 case BFD_RELOC_SPARC_L44:
3192 if (!fixP->fx_addsy)
3193 insn |= val & 0xfff;
3194 break;
3195
3196 case BFD_RELOC_SPARC_HIX22:
3197 if (!fixP->fx_addsy)
3198 {
ab3e48dc 3199 val ^= ~(offsetT) 0;
252b5132
RH		 3200 insn |= (val >> 10) & 0x3fffff;
3201 }
3202 break;
3203
3204 case BFD_RELOC_SPARC_LOX10:
3205 if (!fixP->fx_addsy)
3206 insn |= 0x1c00 | (val & 0x3ff);
3207 break;
3208
3209 case BFD_RELOC_NONE:
3210 default:
3211 as_bad_where (fixP->fx_file, fixP->fx_line,
3212 _("bad or unhandled relocation type: 0x%02x"),
3213 fixP->fx_r_type);
3214 break;
3215 }
3216
3217 if (INSN_BIG_ENDIAN)
3218 bfd_putb32 (insn, (unsigned char *) buf);
3219 else
3220 bfd_putl32 (insn, (unsigned char *) buf);
3221 }
3222
3223 /* Are we finished with this relocation now? */
3224 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3225 fixP->fx_done = 1;
3226
3227 return 1;
3228}
3229
3230/* Translate internal representation of relocation info to BFD target
3231 format. */
e0c6ed95 3232
dabe3bbc 3233arelent **
252b5132
RH		 3234tc_gen_reloc (section, fixp)
3235 asection *section;
3236 fixS *fixp;
3237{
dabe3bbc 3238 static arelent *relocs[3];
252b5132
RH		 3239 arelent *reloc;
3240 bfd_reloc_code_real_type code;
3241
dabe3bbc
RH		 3242 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3243 relocs[1] = NULL;
252b5132 3244
49309057
ILT		 3245 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3246 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3247 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3248
3249 switch (fixp->fx_r_type)
3250 {
3251 case BFD_RELOC_16:
3252 case BFD_RELOC_32:
3253 case BFD_RELOC_HI22:
3254 case BFD_RELOC_LO10:
3255 case BFD_RELOC_32_PCREL_S2:
3256 case BFD_RELOC_SPARC13:
63fab58c 3257 case BFD_RELOC_SPARC22:
252b5132
RH		 3258 case BFD_RELOC_SPARC_BASE13:
3259 case BFD_RELOC_SPARC_WDISP16:
3260 case BFD_RELOC_SPARC_WDISP19:
3261 case BFD_RELOC_SPARC_WDISP22:
3262 case BFD_RELOC_64:
3263 case BFD_RELOC_SPARC_5:
3264 case BFD_RELOC_SPARC_6:
3265 case BFD_RELOC_SPARC_7:
3266 case BFD_RELOC_SPARC_10:
3267 case BFD_RELOC_SPARC_11:
3268 case BFD_RELOC_SPARC_HH22:
3269 case BFD_RELOC_SPARC_HM10:
3270 case BFD_RELOC_SPARC_LM22:
3271 case BFD_RELOC_SPARC_PC_HH22:
3272 case BFD_RELOC_SPARC_PC_HM10:
3273 case BFD_RELOC_SPARC_PC_LM22:
3274 case BFD_RELOC_SPARC_H44:
3275 case BFD_RELOC_SPARC_M44:
3276 case BFD_RELOC_SPARC_L44:
3277 case BFD_RELOC_SPARC_HIX22:
3278 case BFD_RELOC_SPARC_LOX10:
3279 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3280 case BFD_RELOC_SPARC_OLO10:
252b5132
RH		 3281 case BFD_RELOC_VTABLE_ENTRY:
3282 case BFD_RELOC_VTABLE_INHERIT:
3283 code = fixp->fx_r_type;
3284 break;
3285 default:
3286 abort ();
3287 return NULL;
3288 }
3289
3290#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3291 /* If we are generating PIC code, we need to generate a different
3292 set of relocs. */
3293
3294#ifdef OBJ_ELF
3295#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3296#else
3297#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3298#endif
3299
153b546a
ILT		 3300 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3301
252b5132
RH		 3302 if (sparc_pic_code)
3303 {
3304 switch (code)
3305 {
3306 case BFD_RELOC_32_PCREL_S2:
3307 if (! S_IS_DEFINED (fixp->fx_addsy)
3308 || S_IS_COMMON (fixp->fx_addsy)
3309 || S_IS_EXTERNAL (fixp->fx_addsy)
3310 || S_IS_WEAK (fixp->fx_addsy))
3311 code = BFD_RELOC_SPARC_WPLT30;
3312 break;
3313 case BFD_RELOC_HI22:
3314 if (fixp->fx_addsy != NULL
3315 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3316 code = BFD_RELOC_SPARC_PC22;
3317 else
3318 code = BFD_RELOC_SPARC_GOT22;
3319 break;
3320 case BFD_RELOC_LO10:
3321 if (fixp->fx_addsy != NULL
3322 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3323 code = BFD_RELOC_SPARC_PC10;
3324 else
3325 code = BFD_RELOC_SPARC_GOT10;
3326 break;
3327 case BFD_RELOC_SPARC13:
3328 code = BFD_RELOC_SPARC_GOT13;
3329 break;
3330 default:
3331 break;
3332 }
3333 }
e0c6ed95 3334#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3335
dabe3bbc
RH		 3336 if (code == BFD_RELOC_SPARC_OLO10)
3337 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3338 else
3339 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3340 if (reloc->howto == 0)
3341 {
3342 as_bad_where (fixp->fx_file, fixp->fx_line,
3343 _("internal error: can't export reloc type %d (`%s')"),
3344 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3345 xfree (reloc);
3346 relocs[0] = NULL;
3347 return relocs;
252b5132
RH		 3348 }
3349
3350 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3351#ifdef OBJ_AOUT
3352
3353 if (reloc->howto->pc_relative == 0
3354 || code == BFD_RELOC_SPARC_PC10
3355 || code == BFD_RELOC_SPARC_PC22)
3356 reloc->addend = fixp->fx_addnumber;
3357 else if (sparc_pic_code
3358 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3359 && fixp->fx_addsy != NULL
3360 && (S_IS_EXTERNAL (fixp->fx_addsy)
3361 || S_IS_WEAK (fixp->fx_addsy))
3362 && S_IS_DEFINED (fixp->fx_addsy)
3363 && ! S_IS_COMMON (fixp->fx_addsy))
3364 reloc->addend = fixp->fx_addnumber;
3365 else
3366 reloc->addend = fixp->fx_offset - reloc->address;
3367
e0c6ed95 3368#else /* elf or coff */
252b5132
RH		 3369
3370 if (reloc->howto->pc_relative == 0
3371 || code == BFD_RELOC_SPARC_PC10
3372 || code == BFD_RELOC_SPARC_PC22)
3373 reloc->addend = fixp->fx_addnumber;
49309057 3374 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3375 reloc->addend = (section->vma
3376 + fixp->fx_addnumber
3377 + md_pcrel_from (fixp));
3378 else
3379 reloc->addend = fixp->fx_offset;
3380#endif
3381
dabe3bbc
RH		 3382 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3383 on the same location. */
3384 if (code == BFD_RELOC_SPARC_OLO10)
3385 {
3386 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3387 relocs[2] = NULL;
3388
3389 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3390 *reloc->sym_ptr_ptr
3391 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3392 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3393 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3394 reloc->addend = fixp->tc_fix_data;
3395 }
3396
3397 return relocs;
252b5132
RH		 3398}
3399\f
e0c6ed95 3400/* We have no need to default values of symbols. */
252b5132 3401
252b5132
RH		 3402symbolS *
3403md_undefined_symbol (name)
c2158c24 3404 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 3405{
3406 return 0;
e0c6ed95
AM		 3407}
3408
3409/* Round up a section size to the appropriate boundary. */
252b5132 3410
252b5132
RH		 3411valueT
3412md_section_align (segment, size)
c2158c24 3413 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 3414 valueT size;
3415{
3416#ifndef OBJ_ELF
3417 /* This is not right for ELF; a.out wants it, and COFF will force
3418 the alignment anyways. */
3419 valueT align = ((valueT) 1
3420 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3421 valueT newsize;
e0c6ed95
AM		 3422
3423 /* Turn alignment value into a mask. */
252b5132
RH		 3424 align--;
3425 newsize = (size + align) & ~align;
3426 return newsize;
3427#else
3428 return size;
3429#endif
3430}
3431
3432/* Exactly what point is a PC-relative offset relative TO?
3433 On the sparc, they're relative to the address of the offset, plus
3434 its size. This gets us to the following instruction.
e0c6ed95
AM		 3435 (??? Is this right? FIXME-SOON) */
3436long
252b5132
RH		 3437md_pcrel_from (fixP)
3438 fixS *fixP;
3439{
3440 long ret;
3441
3442 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3443 if (! sparc_pic_code
3444 || fixP->fx_addsy == NULL
49309057 3445 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3446 ret += fixP->fx_size;
3447 return ret;
3448}
3449\f
3450/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3451 of two. */
3452
3453static int
3454log2 (value)
3455 int value;
3456{
3457 int shift;
3458
3459 if (value <= 0)
3460 return -1;
3461
3462 for (shift = 0; (value & 1) == 0; value >>= 1)
3463 ++shift;
3464
3465 return (value == 1) ? shift : -1;
3466}
3467
e0c6ed95 3468/* Sort of like s_lcomm. */
252b5132
RH		 3469
3470#ifndef OBJ_ELF
3471static int max_alignment = 15;
3472#endif
3473
3474static void
3475s_reserve (ignore)
c2158c24 3476 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3477{
3478 char *name;
3479 char *p;
3480 char c;
3481 int align;
3482 int size;
3483 int temp;
3484 symbolS *symbolP;
3485
3486 name = input_line_pointer;
3487 c = get_symbol_end ();
3488 p = input_line_pointer;
3489 *p = c;
3490 SKIP_WHITESPACE ();
3491
3492 if (*input_line_pointer != ',')
3493 {
3494 as_bad (_("Expected comma after name"));
3495 ignore_rest_of_line ();
3496 return;
3497 }
3498
3499 ++input_line_pointer;
3500
3501 if ((size = get_absolute_expression ()) < 0)
3502 {
3503 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3504 ignore_rest_of_line ();
3505 return;
e0c6ed95 3506 } /* Bad length. */
252b5132
RH		 3507
3508 *p = 0;
3509 symbolP = symbol_find_or_make (name);
3510 *p = c;
3511
3512 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3513 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3514 {
3515 as_bad (_("bad .reserve segment -- expected BSS segment"));
3516 return;
3517 }
3518
3519 if (input_line_pointer[2] == '.')
3520 input_line_pointer += 7;
3521 else
3522 input_line_pointer += 6;
3523 SKIP_WHITESPACE ();
3524
3525 if (*input_line_pointer == ',')
3526 {
3527 ++input_line_pointer;
3528
3529 SKIP_WHITESPACE ();
3530 if (*input_line_pointer == '\n')
3531 {
3532 as_bad (_("missing alignment"));
3533 ignore_rest_of_line ();
3534 return;
3535 }
3536
3537 align = (int) get_absolute_expression ();
3538
3539#ifndef OBJ_ELF
3540 if (align > max_alignment)
3541 {
3542 align = max_alignment;
3543 as_warn (_("alignment too large; assuming %d"), align);
3544 }
3545#endif
3546
3547 if (align < 0)
3548 {
3549 as_bad (_("negative alignment"));
3550 ignore_rest_of_line ();
3551 return;
3552 }
3553
3554 if (align != 0)
3555 {
3556 temp = log2 (align);
3557 if (temp < 0)
3558 {
3559 as_bad (_("alignment not a power of 2"));
3560 ignore_rest_of_line ();
3561 return;
3562 }
3563
3564 align = temp;
3565 }
3566
3567 record_alignment (bss_section, align);
3568 }
3569 else
3570 align = 0;
3571
3572 if (!S_IS_DEFINED (symbolP)
3573#ifdef OBJ_AOUT
3574 && S_GET_OTHER (symbolP) == 0
3575 && S_GET_DESC (symbolP) == 0
3576#endif
3577 )
3578 {
3579 if (! need_pass_2)
3580 {
3581 char *pfrag;
3582 segT current_seg = now_seg;
3583 subsegT current_subseg = now_subseg;
3584
e0c6ed95
AM		 3585 /* Switch to bss. */
3586 subseg_set (bss_section, 1);
252b5132
RH		 3587
3588 if (align)
e0c6ed95
AM		 3589 /* Do alignment. */
3590 frag_align (align, 0, 0);
252b5132 3591
e0c6ed95 3592 /* Detach from old frag. */
ab3e48dc 3593 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3594 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3595
49309057 3596 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3597 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3598 (offsetT) size, (char *) 0);
252b5132
RH		 3599 *pfrag = 0;
3600
3601 S_SET_SEGMENT (symbolP, bss_section);
3602
3603 subseg_set (current_seg, current_subseg);
3604
3605#ifdef OBJ_ELF
3606 S_SET_SIZE (symbolP, size);
3607#endif
3608 }
3609 }
3610 else
3611 {
ab3e48dc
KH		 3612 as_warn ("Ignoring attempt to re-define symbol %s",
3613 S_GET_NAME (symbolP));
e0c6ed95 3614 } /* if not redefining. */
252b5132
RH		 3615
3616 demand_empty_rest_of_line ();
3617}
3618
3619static void
3620s_common (ignore)
c2158c24 3621 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3622{
3623 char *name;
3624 char c;
3625 char *p;
3626 int temp, size;
3627 symbolS *symbolP;
3628
3629 name = input_line_pointer;
3630 c = get_symbol_end ();
e0c6ed95 3631 /* Just after name is now '\0'. */
252b5132
RH		 3632 p = input_line_pointer;
3633 *p = c;
3634 SKIP_WHITESPACE ();
3635 if (*input_line_pointer != ',')
3636 {
3637 as_bad (_("Expected comma after symbol-name"));
3638 ignore_rest_of_line ();
3639 return;
3640 }
e0c6ed95
AM		 3641
3642 /* Skip ','. */
3643 input_line_pointer++;
3644
252b5132
RH		 3645 if ((temp = get_absolute_expression ()) < 0)
3646 {
3647 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3648 ignore_rest_of_line ();
3649 return;
3650 }
3651 size = temp;
3652 *p = 0;
3653 symbolP = symbol_find_or_make (name);
3654 *p = c;
3655 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3656 {
3657 as_bad (_("Ignoring attempt to re-define symbol"));
3658 ignore_rest_of_line ();
3659 return;
3660 }
3661 if (S_GET_VALUE (symbolP) != 0)
3662 {
3663 if (S_GET_VALUE (symbolP) != (valueT) size)
3664 {
3665 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3666 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3667 }
3668 }
3669 else
3670 {
3671#ifndef OBJ_ELF
3672 S_SET_VALUE (symbolP, (valueT) size);
3673 S_SET_EXTERNAL (symbolP);
3674#endif
3675 }
7dcc9865 3676 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3677 if (*input_line_pointer != ',')
3678 {
3679 as_bad (_("Expected comma after common length"));
3680 ignore_rest_of_line ();
3681 return;
3682 }
3683 input_line_pointer++;
3684 SKIP_WHITESPACE ();
3685 if (*input_line_pointer != '"')
3686 {
3687 temp = get_absolute_expression ();
3688
3689#ifndef OBJ_ELF
3690 if (temp > max_alignment)
3691 {
3692 temp = max_alignment;
3693 as_warn (_("alignment too large; assuming %d"), temp);
3694 }
3695#endif
3696
3697 if (temp < 0)
3698 {
3699 as_bad (_("negative alignment"));
3700 ignore_rest_of_line ();
3701 return;
3702 }
3703
3704#ifdef OBJ_ELF
49309057 3705 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3706 {
3707 segT old_sec;
3708 int old_subsec;
3709 char *p;
3710 int align;
3711
3712 old_sec = now_seg;
3713 old_subsec = now_subseg;
3714
3715 if (temp == 0)
3716 align = 0;
3717 else
3718 align = log2 (temp);
3719
3720 if (align < 0)
3721 {
3722 as_bad (_("alignment not a power of 2"));
3723 ignore_rest_of_line ();
3724 return;
3725 }
3726
3727 record_alignment (bss_section, align);
3728 subseg_set (bss_section, 0);
3729 if (align)
3730 frag_align (align, 0, 0);
3731 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3732 symbol_get_frag (symbolP)->fr_symbol = 0;
3733 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3734 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3735 (offsetT) size, (char *) 0);
3736 *p = 0;
3737 S_SET_SEGMENT (symbolP, bss_section);
3738 S_CLEAR_EXTERNAL (symbolP);
3739 S_SET_SIZE (symbolP, size);
3740 subseg_set (old_sec, old_subsec);
3741 }
3742 else
e0c6ed95 3743#endif /* OBJ_ELF */
252b5132
RH		 3744 {
3745 allocate_common:
3746 S_SET_VALUE (symbolP, (valueT) size);
3747#ifdef OBJ_ELF
3748 S_SET_ALIGN (symbolP, temp);
3749 S_SET_SIZE (symbolP, size);
3750#endif
3751 S_SET_EXTERNAL (symbolP);
3752 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3753 }
3754 }
3755 else
3756 {
3757 input_line_pointer++;
3758 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3759 if (*input_line_pointer == '.')
3760 input_line_pointer++;
3761 /* @@ Some say data, some say bss. */
3762 if (strncmp (input_line_pointer, "bss\"", 4)
3763 && strncmp (input_line_pointer, "data\"", 5))
3764 {
3765 while (*--input_line_pointer != '"')
3766 ;
3767 input_line_pointer--;
3768 goto bad_common_segment;
3769 }
3770 while (*input_line_pointer++ != '"')
3771 ;
3772 goto allocate_common;
3773 }
3774
3775#ifdef BFD_ASSEMBLER
49309057 3776 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3777#endif
3778
3779 demand_empty_rest_of_line ();
3780 return;
3781
3782 {
3783 bad_common_segment:
3784 p = input_line_pointer;
3785 while (*p && *p != '\n')
3786 p++;
3787 c = *p;
3788 *p = '\0';
3789 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3790 *p = c;
3791 input_line_pointer = p;
3792 ignore_rest_of_line ();
3793 return;
3794 }
3795}
3796
3797/* Handle the .empty pseudo-op. This supresses the warnings about
3798 invalid delay slot usage. */
3799
3800static void
3801s_empty (ignore)
c2158c24 3802 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3803{
3804 /* The easy way to implement is to just forget about the last
3805 instruction. */
3806 last_insn = NULL;
3807}
3808
3809static void
3810s_seg (ignore)
c2158c24 3811 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3812{
3813
3814 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3815 {
3816 input_line_pointer += 6;
3817 s_text (0);
3818 return;
3819 }
3820 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3821 {
3822 input_line_pointer += 6;
3823 s_data (0);
3824 return;
3825 }
3826 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3827 {
3828 input_line_pointer += 7;
3829 s_data1 ();
3830 return;
3831 }
3832 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3833 {
3834 input_line_pointer += 5;
3835 /* We only support 2 segments -- text and data -- for now, so
3836 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 3837 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3838 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 3839 return;
3840 }
3841 as_bad (_("Unknown segment type"));
3842 demand_empty_rest_of_line ();
3843}
3844
3845static void
3846s_data1 ()
3847{
3848 subseg_set (data_section, 1);
3849 demand_empty_rest_of_line ();
3850}
3851
3852static void
3853s_proc (ignore)
c2158c24 3854 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3855{
3856 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3857 {
3858 ++input_line_pointer;
3859 }
3860 ++input_line_pointer;
3861}
3862
3863/* This static variable is set by s_uacons to tell sparc_cons_align
3864 that the expession does not need to be aligned. */
3865
3866static int sparc_no_align_cons = 0;
3867
3868/* This handles the unaligned space allocation pseudo-ops, such as
3869 .uaword. .uaword is just like .word, but the value does not need
3870 to be aligned. */
3871
3872static void
3873s_uacons (bytes)
3874 int bytes;
3875{
3876 /* Tell sparc_cons_align not to align this value. */
3877 sparc_no_align_cons = 1;
3878 cons (bytes);
3879}
3880
cf9a1301
RH		 3881/* This handles the native word allocation pseudo-op .nword.
3882 For sparc_arch_size 32 it is equivalent to .word, for
3883 sparc_arch_size 64 it is equivalent to .xword. */
3884
3885static void
3886s_ncons (bytes)
c2158c24 3887 int bytes ATTRIBUTE_UNUSED;
cf9a1301
RH		 3888{
3889 cons (sparc_arch_size == 32 ? 4 : 8);
3890}
3891
6d8809aa
RH		 3892#ifdef OBJ_ELF
3893/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3894 global register.
3895 The syntax is:
e0c6ed95 3896
6d8809aa 3897 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 3898*/
6d8809aa
RH		 3899
3900static void
3901s_register (ignore)
c2158c24 3902 int ignore ATTRIBUTE_UNUSED;
6d8809aa
RH		 3903{
3904 char c;
3905 int reg;
3906 int flags;
3907 const char *regname;
3908
3909 if (input_line_pointer[0] != '%'
3910 || input_line_pointer[1] != 'g'
3911 || ((input_line_pointer[2] & ~1) != '2'
3912 && (input_line_pointer[2] & ~1) != '6')
3913 || input_line_pointer[3] != ',')
3914 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3915 reg = input_line_pointer[2] - '0';
3916 input_line_pointer += 4;
3917
3918 if (*input_line_pointer == '#')
3919 {
3920 ++input_line_pointer;
3921 regname = input_line_pointer;
3922 c = get_symbol_end ();
3923 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3924 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 3925 if (regname[0] == 'i')
6d8809aa
RH		 3926 regname = NULL;
3927 else
3928 regname = "";
3929 }
3930 else
3931 {
3932 regname = input_line_pointer;
3933 c = get_symbol_end ();
3934 }
3935 if (sparc_arch_size == 64)
3936 {
e0c6ed95 3937 if (globals[reg])
6d8809aa 3938 {
e0c6ed95
AM		 3939 if ((regname && globals[reg] != (symbolS *) 1
3940 && strcmp (S_GET_NAME (globals[reg]), regname))
3941 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 3942 as_bad (_("redefinition of global register"));
3943 }
3944 else
3945 {
3946 if (regname == NULL)
e0c6ed95 3947 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 3948 else
3949 {
3950 if (*regname)
3951 {
3952 if (symbol_find (regname))
3953 as_bad (_("Register symbol %s already defined."),
3954 regname);
3955 }
e0c6ed95
AM		 3956 globals[reg] = symbol_make (regname);
3957 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 3958 if (! *regname)
3959 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3960 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3961 flags |= BSF_GLOBAL;
e0c6ed95
AM		 3962 symbol_get_bfdsym (globals[reg])->flags = flags;
3963 S_SET_VALUE (globals[reg], (valueT) reg);
3964 S_SET_ALIGN (globals[reg], reg);
3965 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 3966 /* Although we actually want undefined_section here,
3967 we have to use absolute_section, because otherwise
3968 generic as code will make it a COM section.
3969 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 3970 S_SET_SEGMENT (globals[reg], absolute_section);
3971 S_SET_OTHER (globals[reg], 0);
3972 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 3973 ->internal_elf_sym.st_info =
3974 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 3975 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 3976 ->internal_elf_sym.st_shndx = SHN_UNDEF;
3977 }
3978 }
3979 }
3980
3981 *input_line_pointer = c;
3982
3983 demand_empty_rest_of_line ();
3984}
3985
3986/* Adjust the symbol table. We set undefined sections for STT_REGISTER
3987 symbols which need it. */
e0c6ed95 3988
6d8809aa
RH		 3989void
3990sparc_adjust_symtab ()
3991{
3992 symbolS *sym;
e0c6ed95 3993
6d8809aa
RH		 3994 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
3995 {
3996 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3997 ->internal_elf_sym.st_info) != STT_REGISTER)
3998 continue;
3999
4000 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4001 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4002 continue;
4003
4004 S_SET_SEGMENT (sym, undefined_section);
4005 }
4006}
4007#endif
4008
252b5132
RH		 4009/* If the --enforce-aligned-data option is used, we require .word,
4010 et. al., to be aligned correctly. We do it by setting up an
4011 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4012 no unexpected alignment was introduced.
4013
4014 The SunOS and Solaris native assemblers enforce aligned data by
4015 default. We don't want to do that, because gcc can deliberately
4016 generate misaligned data if the packed attribute is used. Instead,
4017 we permit misaligned data by default, and permit the user to set an
4018 option to check for it. */
4019
4020void
4021sparc_cons_align (nbytes)
4022 int nbytes;
4023{
4024 int nalign;
4025 char *p;
4026
4027 /* Only do this if we are enforcing aligned data. */
4028 if (! enforce_aligned_data)
4029 return;
4030
4031 if (sparc_no_align_cons)
4032 {
4033 /* This is an unaligned pseudo-op. */
4034 sparc_no_align_cons = 0;
4035 return;
4036 }
4037
4038 nalign = log2 (nbytes);
4039 if (nalign == 0)
4040 return;
4041
4042 assert (nalign > 0);
4043
4044 if (now_seg == absolute_section)
4045 {
4046 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4047 as_bad (_("misaligned data"));
4048 return;
4049 }
4050
4051 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
4052 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4053
4054 record_alignment (now_seg, nalign);
4055}
4056
4057/* This is where we do the unexpected alignment check.
4058 This is called from HANDLE_ALIGN in tc-sparc.h. */
4059
4060void
4061sparc_handle_align (fragp)
4062 fragS *fragp;
4063{
4064 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
4065 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
4066 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4067 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
4068 {
ab3e48dc
KH		 4069 int count =
4070 fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
e0c6ed95 4071
252b5132
RH		 4072 if (count >= 4
4073 && !(count & 3)
4074 && count <= 1024
e0c6ed95
AM		 4075 && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
4076 {
4077 unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
4078 int i;
4079
4080 for (i = 0; i < count; i += 4, p++)
4081 if (INSN_BIG_ENDIAN)
4082 /* Emit nops. */
4083 number_to_chars_bigendian ((char *) p, 0x01000000, 4);
4084 else
4085 number_to_chars_littleendian ((char *) p, 0x10000000, 4);
4086
4087 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4088 {
252b5132 4089 char *waddr = &fragp->fr_literal[fragp->fr_fix];
e0c6ed95 4090 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
252b5132
RH		 4091 if (INSN_BIG_ENDIAN)
4092 number_to_chars_bigendian (waddr, wval, 4);
4093 else
4094 number_to_chars_littleendian (waddr, wval, 4);
e0c6ed95
AM		 4095 }
4096 fragp->fr_var = count;
4097 }
252b5132
RH		 4098 }
4099}
4100
4101#ifdef OBJ_ELF
4102/* Some special processing for a Sparc ELF file. */
4103
4104void
4105sparc_elf_final_processing ()
4106{
4107 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4108 sort of BFD interface for this. */
4109 if (sparc_arch_size == 64)
4110 {
4111 switch (sparc_memory_model)
4112 {
4113 case MM_RMO:
4114 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4115 break;
4116 case MM_PSO:
4117 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4118 break;
4119 default:
4120 break;
4121 }
4122 }
4123 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4124 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4125 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4126 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4127}
4128#endif
4129
4130/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4131 reloc for a cons. We could use the definition there, except that
4132 we want to handle little endian relocs specially. */
4133
4134void
4135cons_fix_new_sparc (frag, where, nbytes, exp)
4136 fragS *frag;
4137 int where;
4138 unsigned int nbytes;
4139 expressionS *exp;
4140{
4141 bfd_reloc_code_real_type r;
4142
4143 r = (nbytes == 1 ? BFD_RELOC_8 :
4144 (nbytes == 2 ? BFD_RELOC_16 :
4145 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4146
4147 if (target_little_endian_data && nbytes == 4
e0c6ed95 4148 && now_seg->flags & SEC_ALLOC)
252b5132
RH		 4149 r = BFD_RELOC_SPARC_REV32;
4150 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4151}
4152
4153#ifdef OBJ_ELF
4154int
4155elf32_sparc_force_relocation (fixp)
e0c6ed95 4156 struct fix *fixp;
252b5132
RH		 4157{
4158 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4159 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4160 return 1;
e0c6ed95 4161
252b5132
RH		 4162 return 0;
4163}
4164#endif
GDB Binutils - Deliverables
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