projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Warn abouyt "bx pc" not being very useful.
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
CommitLineData
252b5132 1/* tc-sparc.c -- Assemble for the SPARC
e0c6ed95
AM		 2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
252b5132
RH		 4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21#include <stdio.h>
22#include <ctype.h>
23
24#include "as.h"
25#include "subsegs.h"
26
27#include "opcode/sparc.h"
28
29#ifdef OBJ_ELF
30#include "elf/sparc.h"
31#endif
32
33static struct sparc_arch *lookup_arch PARAMS ((char *));
34static void init_default_arch PARAMS ((void));
a22b281c 35static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
252b5132
RH		 36static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
37static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
38static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39static int sparc_ffs PARAMS ((unsigned int));
a22b281c
RH		 40static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
41static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
42static void synthetize_setx PARAMS ((const struct sparc_opcode *));
252b5132
RH		 43static bfd_vma BSR PARAMS ((bfd_vma, int));
44static int cmp_reg_entry PARAMS ((const PTR, const PTR));
45static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
46static int parse_const_expr_arg PARAMS ((char **, int *));
47static int get_expression PARAMS ((char *str));
48
49/* Default architecture. */
50/* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "sparclite"
55#endif
56static char *default_arch = DEFAULT_ARCH;
57
58/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 have been set. */
60static int default_init_p;
61
62/* Current architecture. We don't bump up unless necessary. */
63static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
64
65/* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70static enum sparc_opcode_arch_val max_architecture;
71
72/* Either 32 or 64, selects file format. */
73static int sparc_arch_size;
74/* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76static int default_arch_size;
77
78#ifdef OBJ_ELF
79/* The currently selected v9 memory model. Currently only used for
80 ELF. */
81static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
82#endif
83
84static int architecture_requested;
85static int warn_on_bump;
86
87/* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89static enum sparc_opcode_arch_val warn_after_architecture;
90
6d8809aa
RH		 91/* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93static int no_undeclared_regs;
94
6faf3d66
JJ		 95/* Non-zero if we should try to relax jumps and calls. */
96static int sparc_relax;
97
252b5132
RH		 98/* Non-zero if we are generating PIC code. */
99int sparc_pic_code;
100
101/* Non-zero if we should give an error when misaligned data is seen. */
102static int enforce_aligned_data;
103
104extern int target_big_endian;
105
106static int target_little_endian_data;
107
6d8809aa
RH		 108/* Symbols for global registers on v9. */
109static symbolS *globals[8];
110
252b5132
RH		 111/* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115#ifndef INSN_BIG_ENDIAN
116#define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
119#endif
120
e0c6ed95 121/* Handle of the OPCODE hash table. */
252b5132
RH		 122static struct hash_control *op_hash;
123
124static int log2 PARAMS ((int));
125static void s_data1 PARAMS ((void));
126static void s_seg PARAMS ((int));
127static void s_proc PARAMS ((int));
128static void s_reserve PARAMS ((int));
129static void s_common PARAMS ((int));
130static void s_empty PARAMS ((int));
131static void s_uacons PARAMS ((int));
cf9a1301 132static void s_ncons PARAMS ((int));
6d8809aa 133static void s_register PARAMS ((int));
252b5132
RH		 134
135const pseudo_typeS md_pseudo_table[] =
136{
e0c6ed95 137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 138 {"common", s_common, 0},
139 {"empty", s_empty, 0},
140 {"global", s_globl, 0},
141 {"half", cons, 2},
cf9a1301 142 {"nword", s_ncons, 0},
252b5132
RH		 143 {"optim", s_ignore, 0},
144 {"proc", s_proc, 0},
145 {"reserve", s_reserve, 0},
146 {"seg", s_seg, 0},
147 {"skip", s_space, 0},
148 {"word", cons, 4},
149 {"xword", cons, 8},
150 {"uahalf", s_uacons, 2},
151 {"uaword", s_uacons, 4},
152 {"uaxword", s_uacons, 8},
153#ifdef OBJ_ELF
e0c6ed95 154 /* These are specific to sparc/svr4. */
252b5132
RH		 155 {"2byte", s_uacons, 2},
156 {"4byte", s_uacons, 4},
157 {"8byte", s_uacons, 8},
6d8809aa 158 {"register", s_register, 0},
252b5132
RH		 159#endif
160 {NULL, 0, 0},
161};
162
e0c6ed95
AM		 163/* Size of relocation record. */
164const int md_reloc_size = 12;
252b5132
RH		 165
166/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 167 pre-processor is disabled, these aren't very useful. */
168const char comment_chars[] = "!"; /* JF removed '|' from
169 comment_chars. */
252b5132
RH		 170
171/* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 173 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 174/* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
e0c6ed95 176 #NO_APP at the beginning of its output. */
252b5132 177/* Also note that comments started like this one will always
e0c6ed95 178 work if '/' isn't otherwise defined. */
252b5132
RH		 179const char line_comment_chars[] = "#";
180
63a0b638 181const char line_separator_chars[] = ";";
252b5132 182
e0c6ed95
AM		 183/* Chars that can be used to separate mant from exp in floating point
184 nums. */
252b5132
RH		 185const char EXP_CHARS[] = "eE";
186
e0c6ed95
AM		 187/* Chars that mean this number is a floating point constant.
188 As in 0f12.456
189 or 0d1.2345e12 */
252b5132
RH		 190const char FLT_CHARS[] = "rRsSfFdDxXpP";
191
192/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
195
a22b281c 196#define isoctal(c) ((unsigned)((c) - '0') < '8')
252b5132
RH		 197
198struct sparc_it
199 {
200 char *error;
201 unsigned long opcode;
202 struct nlist *nlistp;
203 expressionS exp;
cf9a1301 204 expressionS exp2;
252b5132
RH		 205 int pcrel;
206 bfd_reloc_code_real_type reloc;
207 };
208
209struct sparc_it the_insn, set_insn;
210
211static void output_insn
212 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
213\f
214/* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
217 and file formats. */
218
219enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
220 v8plusa, v9, v9a, v9_64};
221
222static struct sparc_arch {
223 char *name;
224 char *opcode_arch;
225 enum sparc_arch_types arch_type;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size;
229 /* Allowable arg to -A? */
230 int user_option_p;
231} sparc_arch_table[] = {
232 { "v6", "v6", v6, 0, 1 },
233 { "v7", "v7", v7, 0, 1 },
234 { "v8", "v8", v8, 32, 1 },
235 { "sparclet", "sparclet", sparclet, 32, 1 },
236 { "sparclite", "sparclite", sparclite, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x, 32, 1 },
238 { "v8plus", "v9", v9, 0, 1 },
239 { "v8plusa", "v9a", v9, 0, 1 },
240 { "v9", "v9", v9, 0, 1 },
241 { "v9a", "v9a", v9, 0, 1 },
242 /* This exists to allow configure.in/Makefile.in to pass one
243 value to specify both the default machine and default word size. */
244 { "v9-64", "v9", v9, 64, 0 },
245 { NULL, NULL, v8, 0, 0 }
246};
247
248/* Variant of default_arch */
249static enum sparc_arch_types default_arch_type;
250
251static struct sparc_arch *
252lookup_arch (name)
253 char *name;
254{
255 struct sparc_arch *sa;
256
257 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
258 if (strcmp (sa->name, name) == 0)
259 break;
260 if (sa->name == NULL)
261 return NULL;
262 return sa;
263}
264
265/* Initialize the default opcode arch and word size from the default
266 architecture name. */
267
268static void
269init_default_arch ()
270{
271 struct sparc_arch *sa = lookup_arch (default_arch);
272
273 if (sa == NULL
274 || sa->default_arch_size == 0)
275 as_fatal (_("Invalid default architecture, broken assembler."));
276
277 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
278 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
279 as_fatal (_("Bad opcode table, broken assembler."));
280 default_arch_size = sparc_arch_size = sa->default_arch_size;
281 default_init_p = 1;
282 default_arch_type = sa->arch_type;
283}
284
285/* Called by TARGET_FORMAT. */
286
287const char *
288sparc_target_format ()
289{
290 /* We don't get a chance to initialize anything before we're called,
291 so handle that now. */
292 if (! default_init_p)
293 init_default_arch ();
294
295#ifdef OBJ_AOUT
296#ifdef TE_NetBSD
297 return "a.out-sparc-netbsd";
298#else
299#ifdef TE_SPARCAOUT
300 if (target_big_endian)
301 return "a.out-sunos-big";
302 else if (default_arch_type == sparc86x && target_little_endian_data)
303 return "a.out-sunos-big";
ab3e48dc
KH		 304 else
305 return "a.out-sparc-little";
252b5132
RH		 306#else
307 return "a.out-sunos-big";
308#endif
309#endif
310#endif
311
312#ifdef OBJ_BOUT
313 return "b.out.big";
314#endif
315
316#ifdef OBJ_COFF
317#ifdef TE_LYNX
318 return "coff-sparc-lynx";
319#else
320 return "coff-sparc";
321#endif
322#endif
323
324#ifdef OBJ_ELF
325 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
326#endif
327
328 abort ();
329}
330\f
e0c6ed95 331/* md_parse_option
252b5132
RH		 332 * Invocation line includes a switch not recognized by the base assembler.
333 * See if it's a processor-specific option. These are:
334 *
335 * -bump
336 * Warn on architecture bumps. See also -A.
337 *
338 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
339 * Standard 32 bit architectures.
340 * -Av8plus, -Av8plusa
341 * Sparc64 in a 32 bit world.
342 * -Av9, -Av9a
343 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
344 * This used to only mean 64 bits, but properly specifying it
345 * complicated gcc's ASM_SPECs, so now opcode selection is
346 * specified orthogonally to word size (except when specifying
347 * the default, but that is an internal implementation detail).
348 * -xarch=v8plus, -xarch=v8plusa
349 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
350 *
351 * Select the architecture and possibly the file format.
352 * Instructions or features not supported by the selected
353 * architecture cause fatal errors.
354 *
355 * The default is to start at v6, and bump the architecture up
356 * whenever an instruction is seen at a higher level. In 32 bit
357 * environments, v9 is not bumped up to, the user must pass
358 * -Av8plus{,a}.
359 *
360 * If -bump is specified, a warning is printing when bumping to
361 * higher levels.
362 *
363 * If an architecture is specified, all instructions must match
364 * that architecture. Any higher level instructions are flagged
365 * as errors. Note that in the 32 bit environment specifying
366 * -Av8plus does not automatically create a v8plus object file, a
367 * v9 insn must be seen.
368 *
369 * If both an architecture and -bump are specified, the
370 * architecture starts at the specified level, but bumps are
371 * warnings. Note that we can't set `current_architecture' to
372 * the requested level in this case: in the 32 bit environment,
373 * we still must avoid creating v8plus object files unless v9
374 * insns are seen.
375 *
376 * Note:
377 * Bumping between incompatible architectures is always an
378 * error. For example, from sparclite to v9.
379 */
380
381#ifdef OBJ_ELF
382CONST char *md_shortopts = "A:K:VQ:sq";
383#else
384#ifdef OBJ_AOUT
385CONST char *md_shortopts = "A:k";
386#else
387CONST char *md_shortopts = "A:";
388#endif
389#endif
390struct option md_longopts[] = {
391#define OPTION_BUMP (OPTION_MD_BASE)
392 {"bump", no_argument, NULL, OPTION_BUMP},
393#define OPTION_SPARC (OPTION_MD_BASE + 1)
394 {"sparc", no_argument, NULL, OPTION_SPARC},
395#define OPTION_XARCH (OPTION_MD_BASE + 2)
396 {"xarch", required_argument, NULL, OPTION_XARCH},
397#ifdef OBJ_ELF
398#define OPTION_32 (OPTION_MD_BASE + 3)
399 {"32", no_argument, NULL, OPTION_32},
400#define OPTION_64 (OPTION_MD_BASE + 4)
401 {"64", no_argument, NULL, OPTION_64},
402#define OPTION_TSO (OPTION_MD_BASE + 5)
403 {"TSO", no_argument, NULL, OPTION_TSO},
404#define OPTION_PSO (OPTION_MD_BASE + 6)
405 {"PSO", no_argument, NULL, OPTION_PSO},
406#define OPTION_RMO (OPTION_MD_BASE + 7)
407 {"RMO", no_argument, NULL, OPTION_RMO},
408#endif
409#ifdef SPARC_BIENDIAN
410#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
411 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
412#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
413 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
414#endif
415#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
416 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
417#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
418 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 419#ifdef OBJ_ELF
420#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
421 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 422#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
423 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 424#endif
6faf3d66
JJ		 425#define OPTION_RELAX (OPTION_MD_BASE + 14)
426 {"relax", no_argument, NULL, OPTION_RELAX},
427#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
428 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 429 {NULL, no_argument, NULL, 0}
430};
e0c6ed95
AM		 431
432size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 433
434int
435md_parse_option (c, arg)
436 int c;
437 char *arg;
438{
439 /* We don't get a chance to initialize anything before we're called,
440 so handle that now. */
441 if (! default_init_p)
442 init_default_arch ();
443
444 switch (c)
445 {
446 case OPTION_BUMP:
447 warn_on_bump = 1;
448 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
449 break;
450
451 case OPTION_XARCH:
452 /* This is for compatibility with Sun's assembler. */
453 if (strcmp (arg, "v8plus") != 0
454 && strcmp (arg, "v8plusa") != 0)
455 {
456 as_bad (_("invalid architecture -xarch=%s"), arg);
457 return 0;
458 }
e0c6ed95 459 /* Fall through. */
252b5132
RH		 460
461 case 'A':
462 {
463 struct sparc_arch *sa;
464 enum sparc_opcode_arch_val opcode_arch;
465
466 sa = lookup_arch (arg);
467 if (sa == NULL
468 || ! sa->user_option_p)
469 {
470 as_bad (_("invalid architecture -A%s"), arg);
471 return 0;
472 }
473
474 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
475 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
476 as_fatal (_("Bad opcode table, broken assembler."));
477
478 max_architecture = opcode_arch;
479 architecture_requested = 1;
480 }
481 break;
482
483 case OPTION_SPARC:
484 /* Ignore -sparc, used by SunOS make default .s.o rule. */
485 break;
486
487 case OPTION_ENFORCE_ALIGNED_DATA:
488 enforce_aligned_data = 1;
489 break;
490
491#ifdef SPARC_BIENDIAN
492 case OPTION_LITTLE_ENDIAN:
493 target_big_endian = 0;
494 if (default_arch_type != sparclet)
495 as_fatal ("This target does not support -EL");
496 break;
497 case OPTION_LITTLE_ENDIAN_DATA:
498 target_little_endian_data = 1;
499 target_big_endian = 0;
500 if (default_arch_type != sparc86x
501 && default_arch_type != v9)
502 as_fatal ("This target does not support --little-endian-data");
503 break;
504 case OPTION_BIG_ENDIAN:
505 target_big_endian = 1;
506 break;
507#endif
508
509#ifdef OBJ_AOUT
510 case 'k':
511 sparc_pic_code = 1;
512 break;
513#endif
514
515#ifdef OBJ_ELF
516 case OPTION_32:
517 case OPTION_64:
518 {
519 const char **list, **l;
520
521 sparc_arch_size = c == OPTION_32 ? 32 : 64;
522 list = bfd_target_list ();
523 for (l = list; *l != NULL; l++)
524 {
525 if (sparc_arch_size == 32)
526 {
527 if (strcmp (*l, "elf32-sparc") == 0)
528 break;
529 }
530 else
531 {
532 if (strcmp (*l, "elf64-sparc") == 0)
533 break;
534 }
535 }
536 if (*l == NULL)
537 as_fatal (_("No compiled in support for %d bit object file format"),
538 sparc_arch_size);
539 free (list);
540 }
541 break;
542
543 case OPTION_TSO:
544 sparc_memory_model = MM_TSO;
545 break;
546
547 case OPTION_PSO:
548 sparc_memory_model = MM_PSO;
549 break;
550
551 case OPTION_RMO:
552 sparc_memory_model = MM_RMO;
553 break;
554
555 case 'V':
556 print_version_id ();
557 break;
558
559 case 'Q':
560 /* Qy - do emit .comment
e0c6ed95 561 Qn - do not emit .comment. */
252b5132
RH		 562 break;
563
564 case 's':
e0c6ed95 565 /* Use .stab instead of .stab.excl. */
252b5132
RH		 566 break;
567
568 case 'q':
e0c6ed95 569 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 570 break;
571
572 case 'K':
573 if (strcmp (arg, "PIC") != 0)
574 as_warn (_("Unrecognized option following -K"));
575 else
576 sparc_pic_code = 1;
577 break;
6d8809aa
RH		 578
579 case OPTION_NO_UNDECLARED_REGS:
580 no_undeclared_regs = 1;
581 break;
a25fe906
ILT		 582
583 case OPTION_UNDECLARED_REGS:
584 no_undeclared_regs = 0;
585 break;
252b5132
RH		 586#endif
587
6faf3d66
JJ		 588 case OPTION_RELAX:
589 sparc_relax = 1;
590 break;
591
592 case OPTION_NO_RELAX:
593 sparc_relax = 0;
594 break;
595
252b5132
RH		 596 default:
597 return 0;
598 }
599
600 return 1;
601}
602
603void
604md_show_usage (stream)
605 FILE *stream;
606{
607 const struct sparc_arch *arch;
608
609 /* We don't get a chance to initialize anything before we're called,
610 so handle that now. */
611 if (! default_init_p)
612 init_default_arch ();
613
e0c6ed95 614 fprintf (stream, _("SPARC options:\n"));
252b5132
RH		 615 for (arch = &sparc_arch_table[0]; arch->name; arch++)
616 {
617 if (arch != &sparc_arch_table[0])
618 fprintf (stream, " | ");
619 if (arch->user_option_p)
620 fprintf (stream, "-A%s", arch->name);
621 }
622 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
623 fprintf (stream, _("\
624 specify variant of SPARC architecture\n\
625-bump warn when assembler switches architectures\n\
626-sparc ignored\n\
6faf3d66
JJ		 627--enforce-aligned-data force .long, etc., to be aligned correctly\n\
628-relax relax jumps and branches (default)\n\
629-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 630#ifdef OBJ_AOUT
631 fprintf (stream, _("\
632-k generate PIC\n"));
633#endif
634#ifdef OBJ_ELF
635 fprintf (stream, _("\
636-32 create 32 bit object file\n\
637-64 create 64 bit object file\n"));
638 fprintf (stream, _("\
639 [default is %d]\n"), default_arch_size);
640 fprintf (stream, _("\
641-TSO use Total Store Ordering\n\
642-PSO use Partial Store Ordering\n\
643-RMO use Relaxed Memory Ordering\n"));
644 fprintf (stream, _("\
645 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
646 fprintf (stream, _("\
647-KPIC generate PIC\n\
648-V print assembler version number\n\
a25fe906
ILT		 649-undeclared-regs ignore application global register usage without\n\
650 appropriate .register directive (default)\n\
651-no-undeclared-regs force error on application global register usage\n\
652 without appropriate .register directive\n\
252b5132
RH		 653-q ignored\n\
654-Qy, -Qn ignored\n\
655-s ignored\n"));
656#endif
657#ifdef SPARC_BIENDIAN
658 fprintf (stream, _("\
659-EL generate code for a little endian machine\n\
660-EB generate code for a big endian machine\n\
661--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 662 instructions and little endian data.\n"));
252b5132
RH		 663#endif
664}
665\f
e0c6ed95 666/* Native operand size opcode translation. */
cf9a1301
RH		 667struct
668 {
669 char *name;
670 char *name32;
671 char *name64;
672 } native_op_table[] =
673{
674 {"ldn", "ld", "ldx"},
675 {"ldna", "lda", "ldxa"},
676 {"stn", "st", "stx"},
677 {"stna", "sta", "stxa"},
678 {"slln", "sll", "sllx"},
679 {"srln", "srl", "srlx"},
680 {"sran", "sra", "srax"},
681 {"casn", "cas", "casx"},
682 {"casna", "casa", "casxa"},
683 {"clrn", "clr", "clrx"},
684 {NULL, NULL, NULL},
685};
686\f
e0c6ed95 687/* sparc64 priviledged registers. */
252b5132
RH		 688
689struct priv_reg_entry
ab3e48dc
KH		 690{
691 char *name;
692 int regnum;
693};
252b5132
RH		 694
695struct priv_reg_entry priv_reg_table[] =
696{
697 {"tpc", 0},
698 {"tnpc", 1},
699 {"tstate", 2},
700 {"tt", 3},
701 {"tick", 4},
702 {"tba", 5},
703 {"pstate", 6},
704 {"tl", 7},
705 {"pil", 8},
706 {"cwp", 9},
707 {"cansave", 10},
708 {"canrestore", 11},
709 {"cleanwin", 12},
710 {"otherwin", 13},
711 {"wstate", 14},
712 {"fq", 15},
713 {"ver", 31},
e0c6ed95 714 {"", -1}, /* End marker. */
252b5132
RH		 715};
716
e0c6ed95 717/* v9a specific asrs. */
252b5132
RH		 718
719struct priv_reg_entry v9a_asr_table[] =
720{
721 {"tick_cmpr", 23},
722 {"softint", 22},
723 {"set_softint", 20},
724 {"pic", 17},
725 {"pcr", 16},
726 {"gsr", 19},
727 {"dcr", 18},
728 {"clear_softint", 21},
e0c6ed95 729 {"", -1}, /* End marker. */
252b5132
RH		 730};
731
732static int
733cmp_reg_entry (parg, qarg)
734 const PTR parg;
735 const PTR qarg;
736{
737 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
738 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
739
740 return strcmp (q->name, p->name);
741}
742\f
743/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 744 set up all the tables, etc. that the MD part of the assembler will
745 need. */
252b5132
RH		 746
747void
748md_begin ()
749{
750 register const char *retval = NULL;
751 int lose = 0;
752 register unsigned int i = 0;
753
754 /* We don't get a chance to initialize anything before md_parse_option
755 is called, and it may not be called, so handle default initialization
756 now if not already done. */
757 if (! default_init_p)
758 init_default_arch ();
759
760 op_hash = hash_new ();
761
762 while (i < (unsigned int) sparc_num_opcodes)
763 {
764 const char *name = sparc_opcodes[i].name;
765 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
766 if (retval != NULL)
767 {
cf9a1301
RH		 768 as_bad (_("Internal error: can't hash `%s': %s\n"),
769 sparc_opcodes[i].name, retval);
252b5132
RH		 770 lose = 1;
771 }
772 do
773 {
774 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
775 {
cf9a1301
RH		 776 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
777 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 778 lose = 1;
779 }
780 ++i;
781 }
782 while (i < (unsigned int) sparc_num_opcodes
783 && !strcmp (sparc_opcodes[i].name, name));
784 }
785
cf9a1301
RH		 786 for (i = 0; native_op_table[i].name; i++)
787 {
788 const struct sparc_opcode *insn;
3d4ae3c0
NC		 789 char *name = ((sparc_arch_size == 32)
790 ? native_op_table[i].name32
791 : native_op_table[i].name64);
e0c6ed95 792 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 793 if (insn == NULL)
e0c6ed95
AM		 794 {
795 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
796 name, native_op_table[i].name);
797 lose = 1;
798 }
cf9a1301
RH		 799 else
800 {
801 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
802 if (retval != NULL)
803 {
804 as_bad (_("Internal error: can't hash `%s': %s\n"),
805 sparc_opcodes[i].name, retval);
806 lose = 1;
807 }
808 }
809 }
810
252b5132
RH		 811 if (lose)
812 as_fatal (_("Broken assembler. No assembly attempted."));
813
252b5132
RH		 814 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
815 sizeof (priv_reg_table[0]), cmp_reg_entry);
816
817 /* If -bump, record the architecture level at which we start issuing
818 warnings. The behaviour is different depending upon whether an
819 architecture was explicitly specified. If it wasn't, we issue warnings
820 for all upwards bumps. If it was, we don't start issuing warnings until
821 we need to bump beyond the requested architecture or when we bump between
822 conflicting architectures. */
823
824 if (warn_on_bump
825 && architecture_requested)
826 {
827 /* `max_architecture' records the requested architecture.
828 Issue warnings if we go above it. */
829 warn_after_architecture = max_architecture;
830
831 /* Find the highest architecture level that doesn't conflict with
832 the requested one. */
833 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
834 max_architecture > warn_after_architecture;
835 --max_architecture)
836 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
837 warn_after_architecture))
838 break;
839 }
840}
841
842/* Called after all assembly has been done. */
843
844void
845sparc_md_end ()
846{
847 if (sparc_arch_size == 64)
848 {
849 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
850 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
851 else
852 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
853 }
854 else
855 {
856 if (current_architecture == SPARC_OPCODE_ARCH_V9)
857 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
858 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
859 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
860 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
861 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
862 else if (default_arch_type == sparc86x && target_little_endian_data)
863 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
864 else
865 {
e0c6ed95
AM		 866 /* The sparclite is treated like a normal sparc. Perhaps it
867 shouldn't be but for now it is (since that's the way it's
868 always been treated). */
252b5132
RH		 869 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
870 }
871 }
872}
873\f
874/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
875
876static INLINE int
877in_signed_range (val, max)
878 bfd_signed_vma val, max;
879{
880 if (max <= 0)
881 abort ();
882 /* Sign-extend the value from the architecture word size, so that
883 0xffffffff is always considered -1 on sparc32. */
884 if (sparc_arch_size == 32)
885 {
e0c6ed95 886 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
252b5132
RH		 887 val = ((val & 0xffffffff) ^ sign) - sign;
888 }
889 if (val > max)
890 return 0;
891 if (val < ~max)
892 return 0;
893 return 1;
894}
895
896/* Return non-zero if VAL is in the range 0 to MAX. */
897
898static INLINE int
899in_unsigned_range (val, max)
900 bfd_vma val, max;
901{
902 if (val > max)
903 return 0;
904 return 1;
905}
906
907/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
908 (e.g. -15 to +31). */
909
910static INLINE int
911in_bitfield_range (val, max)
912 bfd_signed_vma val, max;
913{
914 if (max <= 0)
915 abort ();
916 if (val > max)
917 return 0;
918 if (val < ~(max >> 1))
919 return 0;
920 return 1;
921}
922
923static int
924sparc_ffs (mask)
925 unsigned int mask;
926{
927 int i;
928
929 if (mask == 0)
930 return -1;
931
932 for (i = 0; (mask & 1) == 0; ++i)
933 mask >>= 1;
934 return i;
935}
936
937/* Implement big shift right. */
938static bfd_vma
939BSR (val, amount)
940 bfd_vma val;
941 int amount;
942{
943 if (sizeof (bfd_vma) <= 4 && amount >= 32)
944 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
945 return val >> amount;
946}
947\f
948/* For communication between sparc_ip and get_expression. */
949static char *expr_end;
950
252b5132
RH		 951/* Values for `special_case'.
952 Instructions that require wierd handling because they're longer than
953 4 bytes. */
954#define SPECIAL_CASE_NONE 0
955#define SPECIAL_CASE_SET 1
956#define SPECIAL_CASE_SETSW 2
957#define SPECIAL_CASE_SETX 3
958/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
959#define SPECIAL_CASE_FDIV 4
960
961/* Bit masks of various insns. */
962#define NOP_INSN 0x01000000
963#define OR_INSN 0x80100000
63fab58c 964#define XOR_INSN 0x80180000
252b5132
RH		 965#define FMOVS_INSN 0x81A00020
966#define SETHI_INSN 0x01000000
967#define SLLX_INSN 0x81281000
968#define SRA_INSN 0x81380000
969
970/* The last instruction to be assembled. */
971static const struct sparc_opcode *last_insn;
972/* The assembled opcode of `last_insn'. */
973static unsigned long last_opcode;
974\f
a22b281c 975/* Handle the set and setuw synthetic instructions. */
e0c6ed95 976
a22b281c
RH		 977static void
978synthetize_setuw (insn)
979 const struct sparc_opcode *insn;
980{
981 int need_hi22_p = 0;
982 int rd = (the_insn.opcode & RD (~0)) >> 25;
983
984 if (the_insn.exp.X_op == O_constant)
985 {
986 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
987 {
e0c6ed95 988 if (sizeof (offsetT) > 4
a22b281c
RH		 989 && (the_insn.exp.X_add_number < 0
990 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
991 as_warn (_("set: number not in 0..4294967295 range"));
992 }
993 else
994 {
e0c6ed95 995 if (sizeof (offsetT) > 4
a22b281c
RH		 996 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
997 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
998 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 999 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1000 }
1001 }
1002
1003 /* See if operand is absolute and small; skip sethi if so. */
1004 if (the_insn.exp.X_op != O_constant
1005 || the_insn.exp.X_add_number >= (1 << 12)
1006 || the_insn.exp.X_add_number < -(1 << 12))
1007 {
1008 the_insn.opcode = (SETHI_INSN | RD (rd)
1009 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1010 & (the_insn.exp.X_op == O_constant
1011 ? 0x3fffff : 0)));
a22b281c 1012 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1013 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1014 output_insn (insn, &the_insn);
1015 need_hi22_p = 1;
1016 }
1017
1018 /* See if operand has no low-order bits; skip OR if so. */
1019 if (the_insn.exp.X_op != O_constant
1020 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1021 || ! need_hi22_p)
1022 {
1023 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1024 | RD (rd) | IMMED
1025 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1026 & (the_insn.exp.X_op != O_constant
1027 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1028 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1029 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1030 output_insn (insn, &the_insn);
1031 }
1032}
e0c6ed95 1033
a22b281c 1034/* Handle the setsw synthetic instruction. */
e0c6ed95 1035
a22b281c
RH		 1036static void
1037synthetize_setsw (insn)
1038 const struct sparc_opcode *insn;
1039{
1040 int low32, rd, opc;
1041
1042 rd = (the_insn.opcode & RD (~0)) >> 25;
1043
1044 if (the_insn.exp.X_op != O_constant)
1045 {
1046 synthetize_setuw (insn);
1047
1048 /* Need to sign extend it. */
1049 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1050 the_insn.reloc = BFD_RELOC_NONE;
1051 output_insn (insn, &the_insn);
1052 return;
1053 }
1054
e0c6ed95 1055 if (sizeof (offsetT) > 4
a22b281c
RH		 1056 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1057 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1058 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1059
e0c6ed95
AM		 1060 low32 = the_insn.exp.X_add_number;
1061
a22b281c
RH		 1062 if (low32 >= 0)
1063 {
1064 synthetize_setuw (insn);
1065 return;
1066 }
1067
1068 opc = OR_INSN;
e0c6ed95 1069
a22b281c
RH		 1070 the_insn.reloc = BFD_RELOC_NONE;
1071 /* See if operand is absolute and small; skip sethi if so. */
1072 if (low32 < -(1 << 12))
1073 {
1074 the_insn.opcode = (SETHI_INSN | RD (rd)
1075 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1076 output_insn (insn, &the_insn);
1077 low32 = 0x1c00 | (low32 & 0x3ff);
1078 opc = RS1 (rd) | XOR_INSN;
1079 }
1080
1081 the_insn.opcode = (opc | RD (rd) | IMMED
1082 | (low32 & 0x1fff));
1083 output_insn (insn, &the_insn);
1084}
1085
1086/* Handle the setsw synthetic instruction. */
e0c6ed95 1087
a22b281c
RH		 1088static void
1089synthetize_setx (insn)
1090 const struct sparc_opcode *insn;
1091{
1092 int upper32, lower32;
1093 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1094 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1095 int upper_dstreg;
1096 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1097 int need_xor10_p = 0;
e0c6ed95 1098
a22b281c
RH		 1099#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1100 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1101 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1102#undef SIGNEXT32
1103
1104 upper_dstreg = tmpreg;
1105 /* The tmp reg should not be the dst reg. */
1106 if (tmpreg == dstreg)
1107 as_warn (_("setx: temporary register same as destination register"));
1108
1109 /* ??? Obviously there are other optimizations we can do
1110 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1111 doing some of these. Later. If you do change things, try to
1112 change all of this to be table driven as well. */
1113 /* What to output depends on the number if it's constant.
1114 Compute that first, then output what we've decided upon. */
1115 if (the_insn.exp.X_op != O_constant)
1116 {
1117 if (sparc_arch_size == 32)
1118 {
1119 /* When arch size is 32, we want setx to be equivalent
1120 to setuw for anything but constants. */
1121 the_insn.exp.X_add_number &= 0xffffffff;
1122 synthetize_setuw (insn);
1123 return;
1124 }
1125 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1126 lower32 = 0;
1127 upper32 = 0;
a22b281c
RH		 1128 }
1129 else
1130 {
1131 /* Reset X_add_number, we've extracted it as upper32/lower32.
1132 Otherwise fixup_segment will complain about not being able to
1133 write an 8 byte number in a 4 byte field. */
1134 the_insn.exp.X_add_number = 0;
e0c6ed95 1135
a22b281c
RH		 1136 /* Only need hh22 if `or' insn can't handle constant. */
1137 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1138 need_hh22_p = 1;
e0c6ed95 1139
a22b281c
RH		 1140 /* Does bottom part (after sethi) have bits? */
1141 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1142 /* No hh22, but does upper32 still have bits we can't set
1143 from lower32? */
1144 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1145 need_hm10_p = 1;
e0c6ed95 1146
a22b281c
RH		 1147 /* If the lower half is all zero, we build the upper half directly
1148 into the dst reg. */
1149 if (lower32 != 0
1150 /* Need lower half if number is zero or 0xffffffff00000000. */
1151 || (! need_hh22_p && ! need_hm10_p))
1152 {
1153 /* No need for sethi if `or' insn can handle constant. */
1154 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1155 /* Note that we can't use a negative constant in the `or'
1156 insn unless the upper 32 bits are all ones. */
1157 || (lower32 < 0 && upper32 != -1)
1158 || (lower32 >= 0 && upper32 == -1))
1159 need_hi22_p = 1;
e0c6ed95 1160
a22b281c
RH		 1161 if (need_hi22_p && upper32 == -1)
1162 need_xor10_p = 1;
1163
1164 /* Does bottom part (after sethi) have bits? */
1165 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1166 /* No sethi. */
1167 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1168 /* Need `or' if we didn't set anything else. */
1169 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1170 need_lo10_p = 1;
1171 }
1172 else
1173 /* Output directly to dst reg if lower 32 bits are all zero. */
1174 upper_dstreg = dstreg;
1175 }
e0c6ed95 1176
a22b281c
RH		 1177 if (!upper_dstreg && dstreg)
1178 as_warn (_("setx: illegal temporary register g0"));
1179
1180 if (need_hh22_p)
1181 {
1182 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1183 | ((upper32 >> 10) & 0x3fffff));
1184 the_insn.reloc = (the_insn.exp.X_op != O_constant
1185 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1186 output_insn (insn, &the_insn);
1187 }
e0c6ed95 1188
a22b281c
RH		 1189 if (need_hi22_p)
1190 {
1191 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1192 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1193 >> 10) & 0x3fffff));
a22b281c
RH		 1194 the_insn.reloc = (the_insn.exp.X_op != O_constant
1195 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1196 output_insn (insn, &the_insn);
1197 }
1198
1199 if (need_hm10_p)
1200 {
1201 the_insn.opcode = (OR_INSN
1202 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1203 | RD (upper_dstreg)
1204 | IMMED
1205 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1206 the_insn.reloc = (the_insn.exp.X_op != O_constant
1207 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1208 output_insn (insn, &the_insn);
1209 }
e0c6ed95 1210
a22b281c
RH		 1211 if (need_lo10_p)
1212 {
1213 /* FIXME: One nice optimization to do here is to OR the low part
1214 with the highpart if hi22 isn't needed and the low part is
1215 positive. */
1216 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1217 | RD (dstreg)
1218 | IMMED
1219 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1220 the_insn.reloc = (the_insn.exp.X_op != O_constant
1221 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1222 output_insn (insn, &the_insn);
1223 }
e0c6ed95 1224
a22b281c
RH		 1225 /* If we needed to build the upper part, shift it into place. */
1226 if (need_hh22_p || need_hm10_p)
1227 {
1228 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1229 | IMMED | 32);
1230 the_insn.reloc = BFD_RELOC_NONE;
1231 output_insn (insn, &the_insn);
1232 }
e0c6ed95 1233
a22b281c
RH		 1234 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1235 if (need_xor10_p)
1236 {
1237 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1238 | 0x1c00 | (lower32 & 0x3ff));
1239 the_insn.reloc = BFD_RELOC_NONE;
1240 output_insn (insn, &the_insn);
1241 }
1242
1243 /* If we needed to build both upper and lower parts, OR them together. */
1244 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1245 {
1246 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1247 | RD (dstreg));
1248 the_insn.reloc = BFD_RELOC_NONE;
1249 output_insn (insn, &the_insn);
1250 }
1251}
1252\f
252b5132
RH		 1253/* Main entry point to assemble one instruction. */
1254
1255void
1256md_assemble (str)
1257 char *str;
1258{
1259 const struct sparc_opcode *insn;
a22b281c 1260 int special_case;
252b5132
RH		 1261
1262 know (str);
a22b281c 1263 special_case = sparc_ip (str, &insn);
252b5132
RH		 1264
1265 /* We warn about attempts to put a floating point branch in a delay slot,
1266 unless the delay slot has been annulled. */
1267 if (insn != NULL
1268 && last_insn != NULL
1269 && (insn->flags & F_FBR) != 0
1270 && (last_insn->flags & F_DELAYED) != 0
1271 /* ??? This test isn't completely accurate. We assume anything with
1272 F_{UNBR,CONDBR,FBR} set is annullable. */
1273 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1274 || (last_opcode & ANNUL) == 0))
1275 as_warn (_("FP branch in delay slot"));
1276
1277 /* SPARC before v9 requires a nop instruction between a floating
1278 point instruction and a floating point branch. We insert one
1279 automatically, with a warning. */
1280 if (max_architecture < SPARC_OPCODE_ARCH_V9
1281 && insn != NULL
1282 && last_insn != NULL
1283 && (insn->flags & F_FBR) != 0
1284 && (last_insn->flags & F_FLOAT) != 0)
1285 {
1286 struct sparc_it nop_insn;
1287
1288 nop_insn.opcode = NOP_INSN;
1289 nop_insn.reloc = BFD_RELOC_NONE;
1290 output_insn (insn, &nop_insn);
1291 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1292 }
1293
a22b281c
RH		 1294 switch (special_case)
1295 {
1296 case SPECIAL_CASE_NONE:
e0c6ed95 1297 /* Normal insn. */
a22b281c
RH		 1298 output_insn (insn, &the_insn);
1299 break;
252b5132 1300
a22b281c
RH		 1301 case SPECIAL_CASE_SETSW:
1302 synthetize_setsw (insn);
1303 break;
e0c6ed95 1304
a22b281c
RH		 1305 case SPECIAL_CASE_SET:
1306 synthetize_setuw (insn);
1307 break;
252b5132 1308
a22b281c
RH		 1309 case SPECIAL_CASE_SETX:
1310 synthetize_setx (insn);
1311 break;
e0c6ed95 1312
a22b281c
RH		 1313 case SPECIAL_CASE_FDIV:
1314 {
1315 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1316
a22b281c 1317 output_insn (insn, &the_insn);
e0c6ed95 1318
a22b281c
RH		 1319 /* According to information leaked from Sun, the "fdiv" instructions
1320 on early SPARC machines would produce incorrect results sometimes.
1321 The workaround is to add an fmovs of the destination register to
1322 itself just after the instruction. This was true on machines
e0c6ed95 1323 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
a22b281c
RH		 1324 assert (the_insn.reloc == BFD_RELOC_NONE);
1325 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1326 output_insn (insn, &the_insn);
1327 return;
1328 }
e0c6ed95 1329
a22b281c
RH		 1330 default:
1331 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1332 }
1333}
1334
1335/* Subroutine of md_assemble to do the actual parsing. */
1336
a22b281c 1337static int
252b5132
RH		 1338sparc_ip (str, pinsn)
1339 char *str;
1340 const struct sparc_opcode **pinsn;
1341{
1342 char *error_message = "";
1343 char *s;
1344 const char *args;
1345 char c;
1346 const struct sparc_opcode *insn;
1347 char *argsStart;
1348 unsigned long opcode;
1349 unsigned int mask = 0;
1350 int match = 0;
1351 int comma = 0;
1352 int v9_arg_p;
a22b281c 1353 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1354
1355 s = str;
1356 if (islower ((unsigned char) *s))
1357 {
1358 do
1359 ++s;
1360 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1361 }
1362
1363 switch (*s)
1364 {
1365 case '\0':
1366 break;
1367
1368 case ',':
1369 comma = 1;
e0c6ed95 1370 /* Fall through. */
252b5132
RH		 1371
1372 case ' ':
1373 *s++ = '\0';
1374 break;
1375
1376 default:
1377 as_fatal (_("Unknown opcode: `%s'"), str);
1378 }
1379 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1380 *pinsn = insn;
1381 if (insn == NULL)
1382 {
1383 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1384 return special_case;
252b5132
RH		 1385 }
1386 if (comma)
1387 {
1388 *--s = ',';
1389 }
1390
1391 argsStart = s;
1392 for (;;)
1393 {
1394 opcode = insn->match;
1395 memset (&the_insn, '\0', sizeof (the_insn));
1396 the_insn.reloc = BFD_RELOC_NONE;
1397 v9_arg_p = 0;
1398
e0c6ed95
AM		 1399 /* Build the opcode, checking as we go to make sure that the
1400 operands match. */
252b5132
RH		 1401 for (args = insn->args;; ++args)
1402 {
1403 switch (*args)
1404 {
1405 case 'K':
1406 {
1407 int kmask = 0;
1408
1409 /* Parse a series of masks. */
1410 if (*s == '#')
1411 {
1412 while (*s == '#')
1413 {
1414 int mask;
1415
1416 if (! parse_keyword_arg (sparc_encode_membar, &s,
1417 &mask))
1418 {
1419 error_message = _(": invalid membar mask name");
1420 goto error;
1421 }
1422 kmask |= mask;
47926f60
KH		 1423 while (*s == ' ')
1424 ++s;
252b5132
RH		 1425 if (*s == '|' || *s == '+')
1426 ++s;
47926f60
KH		 1427 while (*s == ' ')
1428 ++s;
252b5132
RH		 1429 }
1430 }
1431 else
1432 {
1433 if (! parse_const_expr_arg (&s, &kmask))
1434 {
1435 error_message = _(": invalid membar mask expression");
1436 goto error;
1437 }
1438 if (kmask < 0 || kmask > 127)
1439 {
1440 error_message = _(": invalid membar mask number");
1441 goto error;
1442 }
1443 }
1444
1445 opcode |= MEMBAR (kmask);
1446 continue;
1447 }
1448
1449 case '*':
1450 {
1451 int fcn = 0;
1452
1453 /* Parse a prefetch function. */
1454 if (*s == '#')
1455 {
1456 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1457 {
1458 error_message = _(": invalid prefetch function name");
1459 goto error;
1460 }
1461 }
1462 else
1463 {
1464 if (! parse_const_expr_arg (&s, &fcn))
1465 {
1466 error_message = _(": invalid prefetch function expression");
1467 goto error;
1468 }
1469 if (fcn < 0 || fcn > 31)
1470 {
1471 error_message = _(": invalid prefetch function number");
1472 goto error;
1473 }
1474 }
1475 opcode |= RD (fcn);
1476 continue;
1477 }
1478
1479 case '!':
1480 case '?':
1481 /* Parse a sparc64 privileged register. */
1482 if (*s == '%')
1483 {
1484 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1485 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1486
1487 s += 1;
1488 while (p->name[0] > s[0])
1489 p++;
1490 while (p->name[0] == s[0])
1491 {
1492 len = strlen (p->name);
1493 if (strncmp (p->name, s, len) == 0)
1494 break;
1495 p++;
1496 }
1497 if (p->name[0] != s[0])
1498 {
1499 error_message = _(": unrecognizable privileged register");
1500 goto error;
1501 }
1502 if (*args == '?')
1503 opcode |= (p->regnum << 14);
1504 else
1505 opcode |= (p->regnum << 25);
1506 s += len;
1507 continue;
1508 }
1509 else
1510 {
1511 error_message = _(": unrecognizable privileged register");
1512 goto error;
1513 }
1514
1515 case '_':
1516 case '/':
1517 /* Parse a v9a ancillary state register. */
1518 if (*s == '%')
1519 {
1520 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1521 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1522
1523 s += 1;
1524 while (p->name[0] > s[0])
1525 p++;
1526 while (p->name[0] == s[0])
1527 {
1528 len = strlen (p->name);
1529 if (strncmp (p->name, s, len) == 0)
1530 break;
1531 p++;
1532 }
1533 if (p->name[0] != s[0])
1534 {
1535 error_message = _(": unrecognizable v9a ancillary state register");
1536 goto error;
1537 }
1538 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1539 {
1540 error_message = _(": rd on write only ancillary state register");
1541 goto error;
e0c6ed95 1542 }
252b5132
RH		 1543 if (*args == '/')
1544 opcode |= (p->regnum << 14);
1545 else
1546 opcode |= (p->regnum << 25);
1547 s += len;
1548 continue;
1549 }
1550 else
1551 {
1552 error_message = _(": unrecognizable v9a ancillary state register");
1553 goto error;
1554 }
1555
1556 case 'M':
1557 case 'm':
1558 if (strncmp (s, "%asr", 4) == 0)
1559 {
1560 s += 4;
1561
1562 if (isdigit ((unsigned char) *s))
1563 {
1564 long num = 0;
1565
1566 while (isdigit ((unsigned char) *s))
1567 {
1568 num = num * 10 + *s - '0';
1569 ++s;
1570 }
1571
1572 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1573 {
1574 if (num < 16 || 31 < num)
1575 {
1576 error_message = _(": asr number must be between 16 and 31");
1577 goto error;
1578 }
1579 }
1580 else
1581 {
1582 if (num < 0 || 31 < num)
1583 {
1584 error_message = _(": asr number must be between 0 and 31");
1585 goto error;
1586 }
1587 }
1588
1589 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1590 continue;
1591 }
1592 else
1593 {
1594 error_message = _(": expecting %asrN");
1595 goto error;
1596 }
e0c6ed95 1597 } /* if %asr */
252b5132
RH		 1598 break;
1599
1600 case 'I':
1601 the_insn.reloc = BFD_RELOC_SPARC_11;
1602 goto immediate;
1603
1604 case 'j':
1605 the_insn.reloc = BFD_RELOC_SPARC_10;
1606 goto immediate;
1607
1608 case 'X':
1609 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1610 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1611 the_insn.reloc = BFD_RELOC_SPARC_5;
1612 else
1613 the_insn.reloc = BFD_RELOC_SPARC13;
1614 /* These fields are unsigned, but for upward compatibility,
1615 allow negative values as well. */
1616 goto immediate;
1617
1618 case 'Y':
1619 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1620 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1621 the_insn.reloc = BFD_RELOC_SPARC_6;
1622 else
1623 the_insn.reloc = BFD_RELOC_SPARC13;
1624 /* These fields are unsigned, but for upward compatibility,
1625 allow negative values as well. */
1626 goto immediate;
1627
1628 case 'k':
1629 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1630 the_insn.pcrel = 1;
1631 goto immediate;
1632
1633 case 'G':
1634 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1635 the_insn.pcrel = 1;
1636 goto immediate;
1637
1638 case 'N':
1639 if (*s == 'p' && s[1] == 'n')
1640 {
1641 s += 2;
1642 continue;
1643 }
1644 break;
1645
1646 case 'T':
1647 if (*s == 'p' && s[1] == 't')
1648 {
1649 s += 2;
1650 continue;
1651 }
1652 break;
1653
1654 case 'z':
1655 if (*s == ' ')
1656 {
1657 ++s;
1658 }
1659 if (strncmp (s, "%icc", 4) == 0)
1660 {
1661 s += 4;
1662 continue;
1663 }
1664 break;
1665
1666 case 'Z':
1667 if (*s == ' ')
1668 {
1669 ++s;
1670 }
1671 if (strncmp (s, "%xcc", 4) == 0)
1672 {
1673 s += 4;
1674 continue;
1675 }
1676 break;
1677
1678 case '6':
1679 if (*s == ' ')
1680 {
1681 ++s;
1682 }
1683 if (strncmp (s, "%fcc0", 5) == 0)
1684 {
1685 s += 5;
1686 continue;
1687 }
1688 break;
1689
1690 case '7':
1691 if (*s == ' ')
1692 {
1693 ++s;
1694 }
1695 if (strncmp (s, "%fcc1", 5) == 0)
1696 {
1697 s += 5;
1698 continue;
1699 }
1700 break;
1701
1702 case '8':
1703 if (*s == ' ')
1704 {
1705 ++s;
1706 }
1707 if (strncmp (s, "%fcc2", 5) == 0)
1708 {
1709 s += 5;
1710 continue;
1711 }
1712 break;
1713
1714 case '9':
1715 if (*s == ' ')
1716 {
1717 ++s;
1718 }
1719 if (strncmp (s, "%fcc3", 5) == 0)
1720 {
1721 s += 5;
1722 continue;
1723 }
1724 break;
1725
1726 case 'P':
1727 if (strncmp (s, "%pc", 3) == 0)
1728 {
1729 s += 3;
1730 continue;
1731 }
1732 break;
1733
1734 case 'W':
1735 if (strncmp (s, "%tick", 5) == 0)
1736 {
1737 s += 5;
1738 continue;
1739 }
1740 break;
1741
e0c6ed95 1742 case '\0': /* End of args. */
252b5132
RH		 1743 if (*s == '\0')
1744 {
1745 match = 1;
1746 }
1747 break;
1748
1749 case '+':
1750 if (*s == '+')
1751 {
1752 ++s;
1753 continue;
1754 }
1755 if (*s == '-')
1756 {
1757 continue;
1758 }
1759 break;
1760
e0c6ed95 1761 case '[': /* These must match exactly. */
252b5132
RH		 1762 case ']':
1763 case ',':
1764 case ' ':
1765 if (*s++ == *args)
1766 continue;
1767 break;
1768
e0c6ed95 1769 case '#': /* Must be at least one digit. */
252b5132
RH		 1770 if (isdigit ((unsigned char) *s++))
1771 {
1772 while (isdigit ((unsigned char) *s))
1773 {
1774 ++s;
1775 }
1776 continue;
1777 }
1778 break;
1779
e0c6ed95 1780 case 'C': /* Coprocessor state register. */
252b5132
RH		 1781 if (strncmp (s, "%csr", 4) == 0)
1782 {
1783 s += 4;
1784 continue;
1785 }
1786 break;
1787
e0c6ed95 1788 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 1789 case 'c':
1790 case 'D':
1791 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1792 {
1793 mask = *s++;
1794 if (isdigit ((unsigned char) *s))
1795 {
1796 mask = 10 * (mask - '0') + (*s++ - '0');
1797 if (mask >= 32)
1798 {
1799 break;
1800 }
1801 }
1802 else
1803 {
1804 mask -= '0';
1805 }
1806 switch (*args)
1807 {
1808
1809 case 'b':
1810 opcode |= mask << 14;
1811 continue;
1812
1813 case 'c':
1814 opcode |= mask;
1815 continue;
1816
1817 case 'D':
1818 opcode |= mask << 25;
1819 continue;
1820 }
1821 }
1822 break;
1823
1824 case 'r': /* next operand must be a register */
1825 case 'O':
1826 case '1':
1827 case '2':
1828 case 'd':
1829 if (*s++ == '%')
1830 {
1831 switch (c = *s++)
1832 {
1833
1834 case 'f': /* frame pointer */
1835 if (*s++ == 'p')
1836 {
1837 mask = 0x1e;
1838 break;
1839 }
1840 goto error;
1841
1842 case 'g': /* global register */
a22b281c
RH		 1843 c = *s++;
1844 if (isoctal (c))
252b5132
RH		 1845 {
1846 mask = c - '0';
1847 break;
1848 }
1849 goto error;
1850
1851 case 'i': /* in register */
a22b281c
RH		 1852 c = *s++;
1853 if (isoctal (c))
252b5132
RH		 1854 {
1855 mask = c - '0' + 24;
1856 break;
1857 }
1858 goto error;
1859
1860 case 'l': /* local register */
a22b281c
RH		 1861 c = *s++;
1862 if (isoctal (c))
252b5132
RH		 1863 {
1864 mask = (c - '0' + 16);
1865 break;
1866 }
1867 goto error;
1868
1869 case 'o': /* out register */
a22b281c
RH		 1870 c = *s++;
1871 if (isoctal (c))
252b5132
RH		 1872 {
1873 mask = (c - '0' + 8);
1874 break;
1875 }
1876 goto error;
1877
1878 case 's': /* stack pointer */
1879 if (*s++ == 'p')
1880 {
1881 mask = 0xe;
1882 break;
1883 }
1884 goto error;
1885
1886 case 'r': /* any register */
1887 if (!isdigit ((unsigned char) (c = *s++)))
1888 {
1889 goto error;
1890 }
1891 /* FALLTHROUGH */
1892 case '0':
1893 case '1':
1894 case '2':
1895 case '3':
1896 case '4':
1897 case '5':
1898 case '6':
1899 case '7':
1900 case '8':
1901 case '9':
1902 if (isdigit ((unsigned char) *s))
1903 {
1904 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1905 {
1906 goto error;
1907 }
1908 }
1909 else
1910 {
1911 c -= '0';
1912 }
1913 mask = c;
1914 break;
1915
1916 default:
1917 goto error;
1918 }
1919
6d8809aa 1920 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 1921 && no_undeclared_regs && ! globals[mask])
79bd78be 1922 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 1923
252b5132
RH		 1924 /* Got the register, now figure out where
1925 it goes in the opcode. */
1926 switch (*args)
1927 {
1928 case '1':
1929 opcode |= mask << 14;
1930 continue;
1931
1932 case '2':
1933 opcode |= mask;
1934 continue;
1935
1936 case 'd':
1937 opcode |= mask << 25;
1938 continue;
1939
1940 case 'r':
1941 opcode |= (mask << 25) | (mask << 14);
1942 continue;
1943
1944 case 'O':
1945 opcode |= (mask << 25) | (mask << 0);
1946 continue;
1947 }
1948 }
1949 break;
1950
1951 case 'e': /* next operand is a floating point register */
1952 case 'v':
1953 case 'V':
1954
1955 case 'f':
1956 case 'B':
1957 case 'R':
1958
1959 case 'g':
1960 case 'H':
1961 case 'J':
1962 {
1963 char format;
1964
1965 if (*s++ == '%'
1966 && ((format = *s) == 'f')
1967 && isdigit ((unsigned char) *++s))
1968 {
1969 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1970 {
1971 mask = 10 * mask + (*s - '0');
1972 } /* read the number */
1973
1974 if ((*args == 'v'
1975 || *args == 'B'
1976 || *args == 'H')
1977 && (mask & 1))
1978 {
1979 break;
1980 } /* register must be even numbered */
1981
1982 if ((*args == 'V'
1983 || *args == 'R'
1984 || *args == 'J')
1985 && (mask & 3))
1986 {
1987 break;
1988 } /* register must be multiple of 4 */
1989
1990 if (mask >= 64)
1991 {
1992 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1993 error_message = _(": There are only 64 f registers; [0-63]");
1994 else
1995 error_message = _(": There are only 32 f registers; [0-31]");
1996 goto error;
1997 } /* on error */
1998 else if (mask >= 32)
1999 {
2000 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2001 {
2002 v9_arg_p = 1;
2003 mask -= 31; /* wrap high bit */
2004 }
2005 else
2006 {
2007 error_message = _(": There are only 32 f registers; [0-31]");
2008 goto error;
2009 }
2010 }
2011 }
2012 else
2013 {
2014 break;
ab3e48dc 2015 } /* if not an 'f' register. */
252b5132
RH		 2016
2017 switch (*args)
2018 {
2019 case 'v':
2020 case 'V':
2021 case 'e':
2022 opcode |= RS1 (mask);
2023 continue;
2024
252b5132
RH		 2025 case 'f':
2026 case 'B':
2027 case 'R':
2028 opcode |= RS2 (mask);
2029 continue;
2030
2031 case 'g':
2032 case 'H':
2033 case 'J':
2034 opcode |= RD (mask);
2035 continue;
ab3e48dc 2036 } /* Pack it in. */
252b5132
RH		 2037
2038 know (0);
2039 break;
ab3e48dc 2040 } /* float arg */
252b5132
RH		 2041
2042 case 'F':
2043 if (strncmp (s, "%fsr", 4) == 0)
2044 {
2045 s += 4;
2046 continue;
2047 }
2048 break;
2049
ab3e48dc
KH		 2050 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2051 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2052 goto immediate;
2053
ab3e48dc 2054 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2055 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2056 the_insn.pcrel = 1;
2057 goto immediate;
2058
ab3e48dc 2059 case 'L': /* 30 bit immediate */
252b5132
RH		 2060 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2061 the_insn.pcrel = 1;
2062 goto immediate;
2063
63fab58c 2064 case 'h':
ab3e48dc 2065 case 'n': /* 22 bit immediate */
252b5132
RH		 2066 the_insn.reloc = BFD_RELOC_SPARC22;
2067 goto immediate;
2068
ab3e48dc 2069 case 'i': /* 13 bit immediate */
252b5132
RH		 2070 the_insn.reloc = BFD_RELOC_SPARC13;
2071
2072 /* fallthrough */
2073
2074 immediate:
2075 if (*s == ' ')
2076 s++;
2077
cf9a1301
RH		 2078 {
2079 char *s1;
2080 char *op_arg = NULL;
2081 expressionS op_exp;
2082 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2083
2084 /* Check for %hi, etc. */
2085 if (*s == '%')
2086 {
2087 static const struct ops {
2088 /* The name as it appears in assembler. */
2089 char *name;
2090 /* strlen (name), precomputed for speed */
2091 int len;
2092 /* The reloc this pseudo-op translates to. */
2093 int reloc;
2094 /* Non-zero if for v9 only. */
2095 int v9_p;
2096 /* Non-zero if can be used in pc-relative contexts. */
2097 int pcrel_p;/*FIXME:wip*/
2098 } ops[] = {
2099 /* hix/lox must appear before hi/lo so %hix won't be
2100 mistaken for %hi. */
2101 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2102 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2103 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2104 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2105 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2106 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2107 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2108 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2109 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2110 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2111 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2112 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2113 { NULL }
2114 };
2115 const struct ops *o;
e0c6ed95 2116
cf9a1301
RH		 2117 for (o = ops; o->name; o++)
2118 if (strncmp (s + 1, o->name, o->len) == 0)
2119 break;
2120 if (o->name == NULL)
252b5132 2121 break;
e0c6ed95 2122
cf9a1301
RH		 2123 if (s[o->len + 1] != '(')
2124 {
2125 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2126 return special_case;
cf9a1301 2127 }
252b5132 2128
cf9a1301
RH		 2129 op_arg = o->name;
2130 the_insn.reloc = o->reloc;
2131 s += o->len + 2;
2132 v9_arg_p = o->v9_p;
2133 }
2134
2135 /* Note that if the get_expression() fails, we will still
2136 have created U entries in the symbol table for the
2137 'symbols' in the input string. Try not to create U
2138 symbols for registers, etc. */
252b5132 2139
252b5132
RH		 2140 /* This stuff checks to see if the expression ends in
2141 +%reg. If it does, it removes the register from
2142 the expression, and re-sets 's' to point to the
2143 right place. */
2144
cf9a1301
RH		 2145 if (op_arg)
2146 {
2147 int npar = 0;
2148
2149 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2150 if (*s1 == '(')
2151 npar++;
2152 else if (*s1 == ')')
2153 {
2154 if (!npar)
2155 break;
2156 npar--;
2157 }
2158
2159 if (*s1 != ')')
2160 {
2161 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2162 return special_case;
cf9a1301 2163 }
e0c6ed95 2164
cf9a1301
RH		 2165 *s1 = '\0';
2166 (void) get_expression (s);
2167 *s1 = ')';
2168 s = s1 + 1;
2169 if (*s == ',' || *s == ']' || !*s)
2170 continue;
2171 if (*s != '+' && *s != '-')
2172 {
2173 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2174 return special_case;
cf9a1301
RH		 2175 }
2176 *s1 = '0';
2177 s = s1;
2178 op_exp = the_insn.exp;
e0c6ed95 2179 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2180 }
252b5132 2181
e0c6ed95
AM		 2182 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2183 ;
252b5132
RH		 2184
2185 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2186 {
2187 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301
RH		 2188 s1 -= 3;
2189 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2190 s1 -= 4;
2191 else
2192 s1 = NULL;
2193 if (s1)
252b5132 2194 {
252b5132 2195 *s1 = '\0';
1eb7027c
RH		 2196 if (op_arg && s1 == s + 1)
2197 the_insn.exp.X_op = O_absent;
2198 else
2199 (void) get_expression (s);
252b5132 2200 *s1 = '+';
cf9a1301
RH		 2201 if (op_arg)
2202 *s = ')';
252b5132 2203 s = s1;
252b5132 2204 }
cf9a1301
RH		 2205 }
2206 else
2207 s1 = NULL;
2208
2209 if (!s1)
2210 {
2211 (void) get_expression (s);
2212 if (op_arg)
2213 *s = ')';
2214 s = expr_end;
2215 }
2216
2217 if (op_arg)
2218 {
2219 the_insn.exp2 = the_insn.exp;
2220 the_insn.exp = op_exp;
2221 if (the_insn.exp2.X_op == O_absent)
2222 the_insn.exp2.X_op = O_illegal;
2223 else if (the_insn.exp.X_op == O_absent)
252b5132 2224 {
cf9a1301
RH		 2225 the_insn.exp = the_insn.exp2;
2226 the_insn.exp2.X_op = O_illegal;
2227 }
2228 else if (the_insn.exp.X_op == O_constant)
2229 {
2230 valueT val = the_insn.exp.X_add_number;
2231 switch (the_insn.reloc)
2232 {
1b50c718
ILT		 2233 default:
2234 break;
2235
cf9a1301
RH		 2236 case BFD_RELOC_SPARC_HH22:
2237 val = BSR (val, 32);
e0c6ed95 2238 /* Fall through. */
cf9a1301
RH		 2239
2240 case BFD_RELOC_SPARC_LM22:
2241 case BFD_RELOC_HI22:
2242 val = (val >> 10) & 0x3fffff;
2243 break;
2244
2245 case BFD_RELOC_SPARC_HM10:
2246 val = BSR (val, 32);
e0c6ed95 2247 /* Fall through. */
cf9a1301
RH		 2248
2249 case BFD_RELOC_LO10:
2250 val &= 0x3ff;
2251 break;
2252
2253 case BFD_RELOC_SPARC_H44:
2254 val >>= 22;
2255 val &= 0x3fffff;
2256 break;
2257
2258 case BFD_RELOC_SPARC_M44:
2259 val >>= 12;
2260 val &= 0x3ff;
2261 break;
2262
2263 case BFD_RELOC_SPARC_L44:
2264 val &= 0xfff;
2265 break;
2266
2267 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2268 val = ~val;
cf9a1301
RH		 2269 val = (val >> 10) & 0x3fffff;
2270 break;
2271
2272 case BFD_RELOC_SPARC_LOX10:
2273 val = (val & 0x3ff) | 0x1c00;
2274 break;
2275 }
2276 the_insn.exp = the_insn.exp2;
2277 the_insn.exp.X_add_number += val;
2278 the_insn.exp2.X_op = O_illegal;
2279 the_insn.reloc = old_reloc;
2280 }
2281 else if (the_insn.exp2.X_op != O_constant)
2282 {
2283 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2284 return special_case;
cf9a1301
RH		 2285 }
2286 else
2287 {
dabe3bbc 2288 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2289 || the_insn.reloc != BFD_RELOC_LO10
2290 || sparc_arch_size != 64
2291 || sparc_pic_code)
2292 {
2293 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2294 return special_case;
cf9a1301
RH		 2295 }
2296 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2297 }
2298 }
2299 }
252b5132
RH		 2300 /* Check for constants that don't require emitting a reloc. */
2301 if (the_insn.exp.X_op == O_constant
2302 && the_insn.exp.X_add_symbol == 0
2303 && the_insn.exp.X_op_symbol == 0)
2304 {
2305 /* For pc-relative call instructions, we reject
2306 constants to get better code. */
2307 if (the_insn.pcrel
2308 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2309 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2310 {
2311 error_message = _(": PC-relative operand can't be a constant");
2312 goto error;
2313 }
2314
2315 /* Constants that won't fit are checked in md_apply_fix3
2316 and bfd_install_relocation.
2317 ??? It would be preferable to install the constants
2318 into the insn here and save having to create a fixS
2319 for each one. There already exists code to handle
2320 all the various cases (e.g. in md_apply_fix3 and
2321 bfd_install_relocation) so duplicating all that code
2322 here isn't right. */
2323 }
2324
2325 continue;
2326
2327 case 'a':
2328 if (*s++ == 'a')
2329 {
2330 opcode |= ANNUL;
2331 continue;
2332 }
2333 break;
2334
2335 case 'A':
2336 {
2337 int asi = 0;
2338
2339 /* Parse an asi. */
2340 if (*s == '#')
2341 {
2342 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2343 {
2344 error_message = _(": invalid ASI name");
2345 goto error;
2346 }
2347 }
2348 else
2349 {
2350 if (! parse_const_expr_arg (&s, &asi))
2351 {
2352 error_message = _(": invalid ASI expression");
2353 goto error;
2354 }
2355 if (asi < 0 || asi > 255)
2356 {
2357 error_message = _(": invalid ASI number");
2358 goto error;
2359 }
2360 }
2361 opcode |= ASI (asi);
2362 continue;
e0c6ed95 2363 } /* Alternate space. */
252b5132
RH		 2364
2365 case 'p':
2366 if (strncmp (s, "%psr", 4) == 0)
2367 {
2368 s += 4;
2369 continue;
2370 }
2371 break;
2372
e0c6ed95 2373 case 'q': /* Floating point queue. */
252b5132
RH		 2374 if (strncmp (s, "%fq", 3) == 0)
2375 {
2376 s += 3;
2377 continue;
2378 }
2379 break;
2380
e0c6ed95 2381 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2382 if (strncmp (s, "%cq", 3) == 0)
2383 {
2384 s += 3;
2385 continue;
2386 }
2387 break;
2388
2389 case 'S':
2390 if (strcmp (str, "set") == 0
2391 || strcmp (str, "setuw") == 0)
2392 {
2393 special_case = SPECIAL_CASE_SET;
2394 continue;
2395 }
2396 else if (strcmp (str, "setsw") == 0)
2397 {
2398 special_case = SPECIAL_CASE_SETSW;
2399 continue;
2400 }
2401 else if (strcmp (str, "setx") == 0)
2402 {
2403 special_case = SPECIAL_CASE_SETX;
2404 continue;
2405 }
2406 else if (strncmp (str, "fdiv", 4) == 0)
2407 {
2408 special_case = SPECIAL_CASE_FDIV;
2409 continue;
2410 }
2411 break;
2412
2413 case 'o':
2414 if (strncmp (s, "%asi", 4) != 0)
2415 break;
2416 s += 4;
2417 continue;
2418
2419 case 's':
2420 if (strncmp (s, "%fprs", 5) != 0)
2421 break;
2422 s += 5;
2423 continue;
2424
2425 case 'E':
2426 if (strncmp (s, "%ccr", 4) != 0)
2427 break;
2428 s += 4;
2429 continue;
2430
2431 case 't':
2432 if (strncmp (s, "%tbr", 4) != 0)
2433 break;
2434 s += 4;
2435 continue;
2436
2437 case 'w':
2438 if (strncmp (s, "%wim", 4) != 0)
2439 break;
2440 s += 4;
2441 continue;
2442
2443 case 'x':
2444 {
2445 char *push = input_line_pointer;
2446 expressionS e;
2447
2448 input_line_pointer = s;
2449 expression (&e);
2450 if (e.X_op == O_constant)
2451 {
2452 int n = e.X_add_number;
2453 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2454 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2455 else
2456 opcode |= e.X_add_number << 5;
2457 }
2458 else
2459 as_bad (_("non-immediate OPF operand, ignored"));
2460 s = input_line_pointer;
2461 input_line_pointer = push;
2462 continue;
2463 }
2464
2465 case 'y':
2466 if (strncmp (s, "%y", 2) != 0)
2467 break;
2468 s += 2;
2469 continue;
2470
2471 case 'u':
2472 case 'U':
2473 {
2474 /* Parse a sparclet cpreg. */
2475 int cpreg;
2476 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2477 {
2478 error_message = _(": invalid cpreg name");
2479 goto error;
2480 }
2481 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2482 continue;
2483 }
2484
2485 default:
2486 as_fatal (_("failed sanity check."));
e0c6ed95 2487 } /* switch on arg code. */
252b5132
RH		 2488
2489 /* Break out of for() loop. */
2490 break;
e0c6ed95 2491 } /* For each arg that we expect. */
252b5132
RH		 2492
2493 error:
2494 if (match == 0)
2495 {
e0c6ed95 2496 /* Args don't match. */
252b5132
RH		 2497 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2498 && (insn->name == insn[1].name
2499 || !strcmp (insn->name, insn[1].name)))
2500 {
2501 ++insn;
2502 s = argsStart;
2503 continue;
2504 }
2505 else
2506 {
2507 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2508 return special_case;
252b5132
RH		 2509 }
2510 }
2511 else
2512 {
e0c6ed95 2513 /* We have a match. Now see if the architecture is OK. */
252b5132
RH		 2514 int needed_arch_mask = insn->architecture;
2515
2516 if (v9_arg_p)
2517 {
ab3e48dc
KH		 2518 needed_arch_mask &= ~((1 << SPARC_OPCODE_ARCH_V9)
2519 | (1 << SPARC_OPCODE_ARCH_V9A));
252b5132
RH		 2520 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2521 }
2522
e0c6ed95
AM		 2523 if (needed_arch_mask
2524 & SPARC_OPCODE_SUPPORTED (current_architecture))
2525 /* OK. */
2526 ;
252b5132 2527 /* Can we bump up the architecture? */
e0c6ed95
AM		 2528 else if (needed_arch_mask
2529 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2530 {
2531 enum sparc_opcode_arch_val needed_architecture =
2532 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2533 & needed_arch_mask);
2534
2535 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2536 if (warn_on_bump
2537 && needed_architecture > warn_after_architecture)
2538 {
2539 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2540 sparc_opcode_archs[current_architecture].name,
2541 sparc_opcode_archs[needed_architecture].name,
2542 str);
2543 warn_after_architecture = needed_architecture;
2544 }
2545 current_architecture = needed_architecture;
2546 }
2547 /* Conflict. */
2548 /* ??? This seems to be a bit fragile. What if the next entry in
2549 the opcode table is the one we want and it is supported?
2550 It is possible to arrange the table today so that this can't
2551 happen but what about tomorrow? */
2552 else
2553 {
e0c6ed95 2554 int arch, printed_one_p = 0;
252b5132
RH		 2555 char *p;
2556 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2557
2558 /* Create a list of the architectures that support the insn. */
e0c6ed95 2559 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2560 p = required_archs;
2561 arch = sparc_ffs (needed_arch_mask);
2562 while ((1 << arch) <= needed_arch_mask)
2563 {
2564 if ((1 << arch) & needed_arch_mask)
2565 {
2566 if (printed_one_p)
2567 *p++ = '|';
2568 strcpy (p, sparc_opcode_archs[arch].name);
2569 p += strlen (p);
2570 printed_one_p = 1;
2571 }
2572 ++arch;
2573 }
2574
2575 as_bad (_("Architecture mismatch on \"%s\"."), str);
2576 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2577 required_archs,
2578 sparc_opcode_archs[max_architecture].name);
a22b281c 2579 return special_case;
252b5132 2580 }
e0c6ed95 2581 } /* If no match. */
252b5132
RH		 2582
2583 break;
e0c6ed95 2584 } /* Forever looking for a match. */
252b5132
RH		 2585
2586 the_insn.opcode = opcode;
a22b281c 2587 return special_case;
252b5132
RH		 2588}
2589
2590/* Parse an argument that can be expressed as a keyword.
2591 (eg: #StoreStore or %ccfr).
2592 The result is a boolean indicating success.
2593 If successful, INPUT_POINTER is updated. */
2594
2595static int
2596parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2597 int (*lookup_fn) PARAMS ((const char *));
2598 char **input_pointerP;
2599 int *valueP;
2600{
2601 int value;
2602 char c, *p, *q;
2603
2604 p = *input_pointerP;
2605 for (q = p + (*p == '#' || *p == '%');
2606 isalnum ((unsigned char) *q) || *q == '_';
2607 ++q)
2608 continue;
2609 c = *q;
2610 *q = 0;
2611 value = (*lookup_fn) (p);
2612 *q = c;
2613 if (value == -1)
2614 return 0;
2615 *valueP = value;
2616 *input_pointerP = q;
2617 return 1;
2618}
2619
2620/* Parse an argument that is a constant expression.
2621 The result is a boolean indicating success. */
2622
2623static int
2624parse_const_expr_arg (input_pointerP, valueP)
2625 char **input_pointerP;
2626 int *valueP;
2627{
2628 char *save = input_line_pointer;
2629 expressionS exp;
2630
2631 input_line_pointer = *input_pointerP;
2632 /* The next expression may be something other than a constant
2633 (say if we're not processing the right variant of the insn).
2634 Don't call expression unless we're sure it will succeed as it will
2635 signal an error (which we want to defer until later). */
2636 /* FIXME: It might be better to define md_operand and have it recognize
2637 things like %asi, etc. but continuing that route through to the end
2638 is a lot of work. */
2639 if (*input_line_pointer == '%')
2640 {
2641 input_line_pointer = save;
2642 return 0;
2643 }
2644 expression (&exp);
2645 *input_pointerP = input_line_pointer;
2646 input_line_pointer = save;
2647 if (exp.X_op != O_constant)
2648 return 0;
2649 *valueP = exp.X_add_number;
2650 return 1;
2651}
2652
2653/* Subroutine of sparc_ip to parse an expression. */
2654
2655static int
2656get_expression (str)
2657 char *str;
2658{
2659 char *save_in;
2660 segT seg;
2661
2662 save_in = input_line_pointer;
2663 input_line_pointer = str;
2664 seg = expression (&the_insn.exp);
2665 if (seg != absolute_section
2666 && seg != text_section
2667 && seg != data_section
2668 && seg != bss_section
2669 && seg != undefined_section)
2670 {
2671 the_insn.error = _("bad segment");
2672 expr_end = input_line_pointer;
2673 input_line_pointer = save_in;
2674 return 1;
2675 }
2676 expr_end = input_line_pointer;
2677 input_line_pointer = save_in;
2678 return 0;
2679}
2680
2681/* Subroutine of md_assemble to output one insn. */
2682
2683static void
2684output_insn (insn, the_insn)
2685 const struct sparc_opcode *insn;
2686 struct sparc_it *the_insn;
2687{
2688 char *toP = frag_more (4);
2689
e0c6ed95 2690 /* Put out the opcode. */
252b5132
RH		 2691 if (INSN_BIG_ENDIAN)
2692 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2693 else
2694 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2695
e0c6ed95 2696 /* Put out the symbol-dependent stuff. */
252b5132
RH		 2697 if (the_insn->reloc != BFD_RELOC_NONE)
2698 {
e0c6ed95
AM		 2699 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2700 (toP - frag_now->fr_literal), /* Where. */
2701 4, /* Size. */
252b5132
RH		 2702 &the_insn->exp,
2703 the_insn->pcrel,
2704 the_insn->reloc);
2705 /* Turn off overflow checking in fixup_segment. We'll do our
2706 own overflow checking in md_apply_fix3. This is necessary because
2707 the insn size is 4 and fixup_segment will signal an overflow for
2708 large 8 byte quantities. */
2709 fixP->fx_no_overflow = 1;
dabe3bbc
RH		 2710 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2711 fixP->tc_fix_data = the_insn->exp2.X_add_number;
252b5132
RH		 2712 }
2713
2714 last_insn = insn;
2715 last_opcode = the_insn->opcode;
2716}
2717\f
e0c6ed95
AM		 2718/* This is identical to the md_atof in m68k.c. I think this is right,
2719 but I'm not sure.
252b5132 2720
e0c6ed95
AM		 2721 Turn a string in input_line_pointer into a floating point constant
2722 of type TYPE, and store the appropriate bytes in *LITP. The number
2723 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2724 returned, or NULL on OK. */
252b5132 2725
e0c6ed95 2726/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 2727#define MAX_LITTLENUMS 6
2728
2729char *
2730md_atof (type, litP, sizeP)
2731 char type;
2732 char *litP;
2733 int *sizeP;
2734{
e0c6ed95 2735 int i, prec;
252b5132
RH		 2736 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2737 char *t;
2738
2739 switch (type)
2740 {
2741 case 'f':
2742 case 'F':
2743 case 's':
2744 case 'S':
2745 prec = 2;
2746 break;
2747
2748 case 'd':
2749 case 'D':
2750 case 'r':
2751 case 'R':
2752 prec = 4;
2753 break;
2754
2755 case 'x':
2756 case 'X':
2757 prec = 6;
2758 break;
2759
2760 case 'p':
2761 case 'P':
2762 prec = 6;
2763 break;
2764
2765 default:
2766 *sizeP = 0;
2767 return _("Bad call to MD_ATOF()");
2768 }
2769
2770 t = atof_ieee (input_line_pointer, type, words);
2771 if (t)
2772 input_line_pointer = t;
2773 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2774
2775 if (target_big_endian)
2776 {
2777 for (i = 0; i < prec; i++)
2778 {
ab3e48dc
KH		 2779 md_number_to_chars (litP, (valueT) words[i],
2780 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2781 litP += sizeof (LITTLENUM_TYPE);
2782 }
2783 }
2784 else
2785 {
2786 for (i = prec - 1; i >= 0; i--)
2787 {
ab3e48dc
KH		 2788 md_number_to_chars (litP, (valueT) words[i],
2789 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2790 litP += sizeof (LITTLENUM_TYPE);
2791 }
2792 }
e0c6ed95 2793
252b5132
RH		 2794 return 0;
2795}
2796
2797/* Write a value out to the object file, using the appropriate
2798 endianness. */
2799
2800void
2801md_number_to_chars (buf, val, n)
2802 char *buf;
2803 valueT val;
2804 int n;
2805{
2806 if (target_big_endian)
2807 number_to_chars_bigendian (buf, val, n);
2808 else if (target_little_endian_data
2809 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 2810 /* Output debug words, which are not in allocated sections, as big
2811 endian. */
252b5132
RH		 2812 number_to_chars_bigendian (buf, val, n);
2813 else if (target_little_endian_data || ! target_big_endian)
2814 number_to_chars_littleendian (buf, val, n);
2815}
2816\f
2817/* Apply a fixS to the frags, now that we know the value it ought to
2818 hold. */
2819
2820int
2821md_apply_fix3 (fixP, value, segment)
2822 fixS *fixP;
2823 valueT *value;
2824 segT segment;
2825{
2826 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2827 offsetT val;
2828 long insn;
2829
2830 val = *value;
2831
2832 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2833
e0c6ed95 2834 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 2835
2836#ifdef OBJ_ELF
2837 /* FIXME: SPARC ELF relocations don't use an addend in the data
2838 field itself. This whole approach should be somehow combined
2839 with the calls to bfd_install_relocation. Also, the value passed
2840 in by fixup_segment includes the value of a defined symbol. We
2841 don't want to include the value of an externally visible symbol. */
2842 if (fixP->fx_addsy != NULL)
2843 {
49309057 2844 if (symbol_used_in_reloc_p (fixP->fx_addsy)
252b5132
RH		 2845 && (S_IS_EXTERNAL (fixP->fx_addsy)
2846 || S_IS_WEAK (fixP->fx_addsy)
2847 || (sparc_pic_code && ! fixP->fx_pcrel)
2848 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2849 && ((bfd_get_section_flags (stdoutput,
2850 S_GET_SEGMENT (fixP->fx_addsy))
2851 & SEC_LINK_ONCE) != 0
2852 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2853 ".gnu.linkonce",
2854 sizeof ".gnu.linkonce" - 1) == 0)))
2855 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2856 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2857 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2858 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2859 return 1;
2860 }
2861#endif
2862
2863 /* This is a hack. There should be a better way to
2864 handle this. Probably in terms of howto fields, once
2865 we can look at these fixups in terms of howtos. */
2866 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2867 val += fixP->fx_where + fixP->fx_frag->fr_address;
2868
2869#ifdef OBJ_AOUT
2870 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2871 generate a reloc, then we just want to let the reloc addend set
2872 the value. We do not want to also stuff the addend into the
2873 object file. Including the addend in the object file works when
2874 doing a static link, because the linker will ignore the object
2875 file contents. However, the dynamic linker does not ignore the
2876 object file contents. */
2877 if (fixP->fx_addsy != NULL
2878 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2879 val = 0;
2880
2881 /* When generating PIC code, we do not want an addend for a reloc
2882 against a local symbol. We adjust fx_addnumber to cancel out the
2883 value already included in val, and to also cancel out the
2884 adjustment which bfd_install_relocation will create. */
2885 if (sparc_pic_code
2886 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2887 && fixP->fx_addsy != NULL
2888 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 2889 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 2890 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2891
2892 /* When generating PIC code, we need to fiddle to get
2893 bfd_install_relocation to do the right thing for a PC relative
2894 reloc against a local symbol which we are going to keep. */
2895 if (sparc_pic_code
2896 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2897 && fixP->fx_addsy != NULL
2898 && (S_IS_EXTERNAL (fixP->fx_addsy)
2899 || S_IS_WEAK (fixP->fx_addsy))
2900 && S_IS_DEFINED (fixP->fx_addsy)
2901 && ! S_IS_COMMON (fixP->fx_addsy))
2902 {
2903 val = 0;
2904 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2905 }
2906#endif
2907
2908 /* If this is a data relocation, just output VAL. */
2909
2910 if (fixP->fx_r_type == BFD_RELOC_16)
2911 {
2912 md_number_to_chars (buf, val, 2);
2913 }
2914 else if (fixP->fx_r_type == BFD_RELOC_32
2915 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2916 {
2917 md_number_to_chars (buf, val, 4);
2918 }
2919 else if (fixP->fx_r_type == BFD_RELOC_64)
2920 {
2921 md_number_to_chars (buf, val, 8);
2922 }
e0c6ed95 2923 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 2924 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2925 {
2926 fixP->fx_done = 0;
2927 return 1;
2928 }
2929 else
2930 {
2931 /* It's a relocation against an instruction. */
2932
2933 if (INSN_BIG_ENDIAN)
2934 insn = bfd_getb32 ((unsigned char *) buf);
2935 else
2936 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 2937
252b5132
RH		 2938 switch (fixP->fx_r_type)
2939 {
2940 case BFD_RELOC_32_PCREL_S2:
2941 val = val >> 2;
2942 /* FIXME: This increment-by-one deserves a comment of why it's
2943 being done! */
2944 if (! sparc_pic_code
2945 || fixP->fx_addsy == NULL
49309057 2946 || symbol_section_p (fixP->fx_addsy))
252b5132 2947 ++val;
6faf3d66 2948
252b5132 2949 insn |= val & 0x3fffffff;
6faf3d66 2950
e0c6ed95 2951 /* See if we have a delay slot. */
6faf3d66
JJ		 2952 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
2953 {
2954#define G0 0
2955#define O7 15
2956#define XCC (2 << 20)
2957#define COND(x) (((x)&0xf)<<25)
2958#define CONDA COND(0x8)
2959#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
2960#define INSN_BA (F2(0,2) | CONDA)
2961#define INSN_OR F3(2, 0x2, 0)
2962#define INSN_NOP F2(0,4)
2963
2964 long delay;
2965
2966 /* If the instruction is a call with either:
2967 restore
2968 arithmetic instruction with rd == %o7
2969 where rs1 != %o7 and rs2 if it is register != %o7
2970 then we can optimize if the call destination is near
2971 by changing the call into a branch always. */
2972 if (INSN_BIG_ENDIAN)
2973 delay = bfd_getb32 ((unsigned char *) buf + 4);
2974 else
2975 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 2976 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 2977 break;
e0c6ed95
AM		 2978 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
2979 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
2980 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 2981 break;
e0c6ed95
AM		 2982 if ((delay & RS1 (~0)) == RS1 (O7)
2983 || ((delay & F3I (~0)) == 0
2984 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 2985 break;
2986 /* Ensure the branch will fit into simm22. */
2987 if ((val & 0x3fe00000)
2988 && (val & 0x3fe00000) != 0x3fe00000)
2989 break;
2990 /* Check if the arch is v9 and branch will fit
2991 into simm19. */
2992 if (((val & 0x3c0000) == 0
2993 || (val & 0x3c0000) == 0x3c0000)
2994 && (sparc_arch_size == 64
2995 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 2996 /* ba,pt %xcc */
6faf3d66
JJ		 2997 insn = INSN_BPA | (val & 0x7ffff);
2998 else
e0c6ed95 2999 /* ba */
6faf3d66
JJ		 3000 insn = INSN_BA | (val & 0x3fffff);
3001 if (fixP->fx_where >= 4
e0c6ed95
AM		 3002 && ((delay & (0xffffffff ^ RS1 (~0)))
3003 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3004 {
3005 long setter;
3006 int reg;
3007
3008 if (INSN_BIG_ENDIAN)
3009 setter = bfd_getb32 ((unsigned char *) buf - 4);
3010 else
3011 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3012 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3013 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3014 break;
3015 /* The sequence was
3016 or %o7, %g0, %rN
3017 call foo
3018 or %rN, %g0, %o7
3019
3020 If call foo was replaced with ba, replace
3021 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3022 reg = (delay & RS1 (~0)) >> 14;
3023 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3024 || reg == G0 || reg == O7)
3025 break;
3026
3027 if (INSN_BIG_ENDIAN)
3028 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3029 else
3030 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3031 }
3032 }
252b5132
RH		 3033 break;
3034
3035 case BFD_RELOC_SPARC_11:
3036 if (! in_signed_range (val, 0x7ff))
3037 as_bad_where (fixP->fx_file, fixP->fx_line,
3038 _("relocation overflow"));
3039 insn |= val & 0x7ff;
3040 break;
3041
3042 case BFD_RELOC_SPARC_10:
3043 if (! in_signed_range (val, 0x3ff))
3044 as_bad_where (fixP->fx_file, fixP->fx_line,
3045 _("relocation overflow"));
3046 insn |= val & 0x3ff;
3047 break;
3048
3049 case BFD_RELOC_SPARC_7:
3050 if (! in_bitfield_range (val, 0x7f))
3051 as_bad_where (fixP->fx_file, fixP->fx_line,
3052 _("relocation overflow"));
3053 insn |= val & 0x7f;
3054 break;
3055
3056 case BFD_RELOC_SPARC_6:
3057 if (! in_bitfield_range (val, 0x3f))
3058 as_bad_where (fixP->fx_file, fixP->fx_line,
3059 _("relocation overflow"));
3060 insn |= val & 0x3f;
3061 break;
3062
3063 case BFD_RELOC_SPARC_5:
3064 if (! in_bitfield_range (val, 0x1f))
3065 as_bad_where (fixP->fx_file, fixP->fx_line,
3066 _("relocation overflow"));
3067 insn |= val & 0x1f;
3068 break;
3069
3070 case BFD_RELOC_SPARC_WDISP16:
e0c6ed95 3071 /* FIXME: simplify. */
252b5132
RH		 3072 if (((val > 0) && (val & ~0x3fffc))
3073 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3074 as_bad_where (fixP->fx_file, fixP->fx_line,
3075 _("relocation overflow"));
3076 /* FIXME: The +1 deserves a comment. */
3077 val = (val >> 2) + 1;
3078 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3079 break;
3080
3081 case BFD_RELOC_SPARC_WDISP19:
e0c6ed95 3082 /* FIXME: simplify. */
252b5132
RH		 3083 if (((val > 0) && (val & ~0x1ffffc))
3084 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3085 as_bad_where (fixP->fx_file, fixP->fx_line,
3086 _("relocation overflow"));
3087 /* FIXME: The +1 deserves a comment. */
3088 val = (val >> 2) + 1;
3089 insn |= val & 0x7ffff;
3090 break;
3091
3092 case BFD_RELOC_SPARC_HH22:
3093 val = BSR (val, 32);
e0c6ed95 3094 /* Fall through. */
252b5132
RH		 3095
3096 case BFD_RELOC_SPARC_LM22:
3097 case BFD_RELOC_HI22:
3098 if (!fixP->fx_addsy)
3099 {
3100 insn |= (val >> 10) & 0x3fffff;
3101 }
3102 else
3103 {
3104 /* FIXME: Need comment explaining why we do this. */
3105 insn &= ~0xffff;
3106 }
3107 break;
3108
3109 case BFD_RELOC_SPARC22:
3110 if (val & ~0x003fffff)
3111 as_bad_where (fixP->fx_file, fixP->fx_line,
3112 _("relocation overflow"));
3113 insn |= (val & 0x3fffff);
3114 break;
3115
3116 case BFD_RELOC_SPARC_HM10:
3117 val = BSR (val, 32);
e0c6ed95 3118 /* Fall through. */
252b5132
RH		 3119
3120 case BFD_RELOC_LO10:
3121 if (!fixP->fx_addsy)
3122 {
3123 insn |= val & 0x3ff;
3124 }
3125 else
3126 {
3127 /* FIXME: Need comment explaining why we do this. */
3128 insn &= ~0xff;
3129 }
3130 break;
3131
dabe3bbc
RH		 3132 case BFD_RELOC_SPARC_OLO10:
3133 val &= 0x3ff;
3134 val += fixP->tc_fix_data;
e0c6ed95 3135 /* Fall through. */
dabe3bbc 3136
252b5132
RH		 3137 case BFD_RELOC_SPARC13:
3138 if (! in_signed_range (val, 0x1fff))
3139 as_bad_where (fixP->fx_file, fixP->fx_line,
3140 _("relocation overflow"));
3141 insn |= val & 0x1fff;
3142 break;
3143
3144 case BFD_RELOC_SPARC_WDISP22:
3145 val = (val >> 2) + 1;
e0c6ed95 3146 /* Fall through. */
252b5132
RH		 3147 case BFD_RELOC_SPARC_BASE22:
3148 insn |= val & 0x3fffff;
3149 break;
3150
3151 case BFD_RELOC_SPARC_H44:
3152 if (!fixP->fx_addsy)
3153 {
3154 bfd_vma tval = val;
3155 tval >>= 22;
3156 insn |= tval & 0x3fffff;
3157 }
3158 break;
3159
3160 case BFD_RELOC_SPARC_M44:
3161 if (!fixP->fx_addsy)
3162 insn |= (val >> 12) & 0x3ff;
3163 break;
3164
3165 case BFD_RELOC_SPARC_L44:
3166 if (!fixP->fx_addsy)
3167 insn |= val & 0xfff;
3168 break;
3169
3170 case BFD_RELOC_SPARC_HIX22:
3171 if (!fixP->fx_addsy)
3172 {
ab3e48dc 3173 val ^= ~(offsetT) 0;
252b5132
RH		 3174 insn |= (val >> 10) & 0x3fffff;
3175 }
3176 break;
3177
3178 case BFD_RELOC_SPARC_LOX10:
3179 if (!fixP->fx_addsy)
3180 insn |= 0x1c00 | (val & 0x3ff);
3181 break;
3182
3183 case BFD_RELOC_NONE:
3184 default:
3185 as_bad_where (fixP->fx_file, fixP->fx_line,
3186 _("bad or unhandled relocation type: 0x%02x"),
3187 fixP->fx_r_type);
3188 break;
3189 }
3190
3191 if (INSN_BIG_ENDIAN)
3192 bfd_putb32 (insn, (unsigned char *) buf);
3193 else
3194 bfd_putl32 (insn, (unsigned char *) buf);
3195 }
3196
3197 /* Are we finished with this relocation now? */
3198 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3199 fixP->fx_done = 1;
3200
3201 return 1;
3202}
3203
3204/* Translate internal representation of relocation info to BFD target
3205 format. */
e0c6ed95 3206
dabe3bbc 3207arelent **
252b5132
RH		 3208tc_gen_reloc (section, fixp)
3209 asection *section;
3210 fixS *fixp;
3211{
dabe3bbc 3212 static arelent *relocs[3];
252b5132
RH		 3213 arelent *reloc;
3214 bfd_reloc_code_real_type code;
3215
dabe3bbc
RH		 3216 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3217 relocs[1] = NULL;
252b5132 3218
49309057
ILT		 3219 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3220 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3221 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3222
3223 switch (fixp->fx_r_type)
3224 {
3225 case BFD_RELOC_16:
3226 case BFD_RELOC_32:
3227 case BFD_RELOC_HI22:
3228 case BFD_RELOC_LO10:
3229 case BFD_RELOC_32_PCREL_S2:
3230 case BFD_RELOC_SPARC13:
63fab58c 3231 case BFD_RELOC_SPARC22:
252b5132
RH		 3232 case BFD_RELOC_SPARC_BASE13:
3233 case BFD_RELOC_SPARC_WDISP16:
3234 case BFD_RELOC_SPARC_WDISP19:
3235 case BFD_RELOC_SPARC_WDISP22:
3236 case BFD_RELOC_64:
3237 case BFD_RELOC_SPARC_5:
3238 case BFD_RELOC_SPARC_6:
3239 case BFD_RELOC_SPARC_7:
3240 case BFD_RELOC_SPARC_10:
3241 case BFD_RELOC_SPARC_11:
3242 case BFD_RELOC_SPARC_HH22:
3243 case BFD_RELOC_SPARC_HM10:
3244 case BFD_RELOC_SPARC_LM22:
3245 case BFD_RELOC_SPARC_PC_HH22:
3246 case BFD_RELOC_SPARC_PC_HM10:
3247 case BFD_RELOC_SPARC_PC_LM22:
3248 case BFD_RELOC_SPARC_H44:
3249 case BFD_RELOC_SPARC_M44:
3250 case BFD_RELOC_SPARC_L44:
3251 case BFD_RELOC_SPARC_HIX22:
3252 case BFD_RELOC_SPARC_LOX10:
3253 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3254 case BFD_RELOC_SPARC_OLO10:
252b5132
RH		 3255 case BFD_RELOC_VTABLE_ENTRY:
3256 case BFD_RELOC_VTABLE_INHERIT:
3257 code = fixp->fx_r_type;
3258 break;
3259 default:
3260 abort ();
3261 return NULL;
3262 }
3263
3264#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3265 /* If we are generating PIC code, we need to generate a different
3266 set of relocs. */
3267
3268#ifdef OBJ_ELF
3269#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3270#else
3271#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3272#endif
3273
153b546a
ILT		 3274 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3275
252b5132
RH		 3276 if (sparc_pic_code)
3277 {
3278 switch (code)
3279 {
3280 case BFD_RELOC_32_PCREL_S2:
3281 if (! S_IS_DEFINED (fixp->fx_addsy)
3282 || S_IS_COMMON (fixp->fx_addsy)
3283 || S_IS_EXTERNAL (fixp->fx_addsy)
3284 || S_IS_WEAK (fixp->fx_addsy))
3285 code = BFD_RELOC_SPARC_WPLT30;
3286 break;
3287 case BFD_RELOC_HI22:
3288 if (fixp->fx_addsy != NULL
3289 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3290 code = BFD_RELOC_SPARC_PC22;
3291 else
3292 code = BFD_RELOC_SPARC_GOT22;
3293 break;
3294 case BFD_RELOC_LO10:
3295 if (fixp->fx_addsy != NULL
3296 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3297 code = BFD_RELOC_SPARC_PC10;
3298 else
3299 code = BFD_RELOC_SPARC_GOT10;
3300 break;
3301 case BFD_RELOC_SPARC13:
3302 code = BFD_RELOC_SPARC_GOT13;
3303 break;
3304 default:
3305 break;
3306 }
3307 }
e0c6ed95 3308#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3309
dabe3bbc
RH		 3310 if (code == BFD_RELOC_SPARC_OLO10)
3311 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3312 else
3313 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3314 if (reloc->howto == 0)
3315 {
3316 as_bad_where (fixp->fx_file, fixp->fx_line,
3317 _("internal error: can't export reloc type %d (`%s')"),
3318 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3319 xfree (reloc);
3320 relocs[0] = NULL;
3321 return relocs;
252b5132
RH		 3322 }
3323
3324 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3325#ifdef OBJ_AOUT
3326
3327 if (reloc->howto->pc_relative == 0
3328 || code == BFD_RELOC_SPARC_PC10
3329 || code == BFD_RELOC_SPARC_PC22)
3330 reloc->addend = fixp->fx_addnumber;
3331 else if (sparc_pic_code
3332 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3333 && fixp->fx_addsy != NULL
3334 && (S_IS_EXTERNAL (fixp->fx_addsy)
3335 || S_IS_WEAK (fixp->fx_addsy))
3336 && S_IS_DEFINED (fixp->fx_addsy)
3337 && ! S_IS_COMMON (fixp->fx_addsy))
3338 reloc->addend = fixp->fx_addnumber;
3339 else
3340 reloc->addend = fixp->fx_offset - reloc->address;
3341
e0c6ed95 3342#else /* elf or coff */
252b5132
RH		 3343
3344 if (reloc->howto->pc_relative == 0
3345 || code == BFD_RELOC_SPARC_PC10
3346 || code == BFD_RELOC_SPARC_PC22)
3347 reloc->addend = fixp->fx_addnumber;
49309057 3348 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3349 reloc->addend = (section->vma
3350 + fixp->fx_addnumber
3351 + md_pcrel_from (fixp));
3352 else
3353 reloc->addend = fixp->fx_offset;
3354#endif
3355
dabe3bbc
RH		 3356 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3357 on the same location. */
3358 if (code == BFD_RELOC_SPARC_OLO10)
3359 {
3360 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3361 relocs[2] = NULL;
3362
3363 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3364 *reloc->sym_ptr_ptr
3365 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3366 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3367 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3368 reloc->addend = fixp->tc_fix_data;
3369 }
3370
3371 return relocs;
252b5132
RH		 3372}
3373\f
e0c6ed95 3374/* We have no need to default values of symbols. */
252b5132 3375
252b5132
RH		 3376symbolS *
3377md_undefined_symbol (name)
3378 char *name;
3379{
3380 return 0;
e0c6ed95
AM		 3381}
3382
3383/* Round up a section size to the appropriate boundary. */
252b5132 3384
252b5132
RH		 3385valueT
3386md_section_align (segment, size)
3387 segT segment;
3388 valueT size;
3389{
3390#ifndef OBJ_ELF
3391 /* This is not right for ELF; a.out wants it, and COFF will force
3392 the alignment anyways. */
3393 valueT align = ((valueT) 1
3394 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3395 valueT newsize;
e0c6ed95
AM		 3396
3397 /* Turn alignment value into a mask. */
252b5132
RH		 3398 align--;
3399 newsize = (size + align) & ~align;
3400 return newsize;
3401#else
3402 return size;
3403#endif
3404}
3405
3406/* Exactly what point is a PC-relative offset relative TO?
3407 On the sparc, they're relative to the address of the offset, plus
3408 its size. This gets us to the following instruction.
e0c6ed95
AM		 3409 (??? Is this right? FIXME-SOON) */
3410long
252b5132
RH		 3411md_pcrel_from (fixP)
3412 fixS *fixP;
3413{
3414 long ret;
3415
3416 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3417 if (! sparc_pic_code
3418 || fixP->fx_addsy == NULL
49309057 3419 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3420 ret += fixP->fx_size;
3421 return ret;
3422}
3423\f
3424/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3425 of two. */
3426
3427static int
3428log2 (value)
3429 int value;
3430{
3431 int shift;
3432
3433 if (value <= 0)
3434 return -1;
3435
3436 for (shift = 0; (value & 1) == 0; value >>= 1)
3437 ++shift;
3438
3439 return (value == 1) ? shift : -1;
3440}
3441
e0c6ed95 3442/* Sort of like s_lcomm. */
252b5132
RH		 3443
3444#ifndef OBJ_ELF
3445static int max_alignment = 15;
3446#endif
3447
3448static void
3449s_reserve (ignore)
3450 int ignore;
3451{
3452 char *name;
3453 char *p;
3454 char c;
3455 int align;
3456 int size;
3457 int temp;
3458 symbolS *symbolP;
3459
3460 name = input_line_pointer;
3461 c = get_symbol_end ();
3462 p = input_line_pointer;
3463 *p = c;
3464 SKIP_WHITESPACE ();
3465
3466 if (*input_line_pointer != ',')
3467 {
3468 as_bad (_("Expected comma after name"));
3469 ignore_rest_of_line ();
3470 return;
3471 }
3472
3473 ++input_line_pointer;
3474
3475 if ((size = get_absolute_expression ()) < 0)
3476 {
3477 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3478 ignore_rest_of_line ();
3479 return;
e0c6ed95 3480 } /* Bad length. */
252b5132
RH		 3481
3482 *p = 0;
3483 symbolP = symbol_find_or_make (name);
3484 *p = c;
3485
3486 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3487 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3488 {
3489 as_bad (_("bad .reserve segment -- expected BSS segment"));
3490 return;
3491 }
3492
3493 if (input_line_pointer[2] == '.')
3494 input_line_pointer += 7;
3495 else
3496 input_line_pointer += 6;
3497 SKIP_WHITESPACE ();
3498
3499 if (*input_line_pointer == ',')
3500 {
3501 ++input_line_pointer;
3502
3503 SKIP_WHITESPACE ();
3504 if (*input_line_pointer == '\n')
3505 {
3506 as_bad (_("missing alignment"));
3507 ignore_rest_of_line ();
3508 return;
3509 }
3510
3511 align = (int) get_absolute_expression ();
3512
3513#ifndef OBJ_ELF
3514 if (align > max_alignment)
3515 {
3516 align = max_alignment;
3517 as_warn (_("alignment too large; assuming %d"), align);
3518 }
3519#endif
3520
3521 if (align < 0)
3522 {
3523 as_bad (_("negative alignment"));
3524 ignore_rest_of_line ();
3525 return;
3526 }
3527
3528 if (align != 0)
3529 {
3530 temp = log2 (align);
3531 if (temp < 0)
3532 {
3533 as_bad (_("alignment not a power of 2"));
3534 ignore_rest_of_line ();
3535 return;
3536 }
3537
3538 align = temp;
3539 }
3540
3541 record_alignment (bss_section, align);
3542 }
3543 else
3544 align = 0;
3545
3546 if (!S_IS_DEFINED (symbolP)
3547#ifdef OBJ_AOUT
3548 && S_GET_OTHER (symbolP) == 0
3549 && S_GET_DESC (symbolP) == 0
3550#endif
3551 )
3552 {
3553 if (! need_pass_2)
3554 {
3555 char *pfrag;
3556 segT current_seg = now_seg;
3557 subsegT current_subseg = now_subseg;
3558
e0c6ed95
AM		 3559 /* Switch to bss. */
3560 subseg_set (bss_section, 1);
252b5132
RH		 3561
3562 if (align)
e0c6ed95
AM		 3563 /* Do alignment. */
3564 frag_align (align, 0, 0);
252b5132 3565
e0c6ed95 3566 /* Detach from old frag. */
ab3e48dc 3567 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3568 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3569
49309057 3570 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3571 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3572 (offsetT) size, (char *) 0);
252b5132
RH		 3573 *pfrag = 0;
3574
3575 S_SET_SEGMENT (symbolP, bss_section);
3576
3577 subseg_set (current_seg, current_subseg);
3578
3579#ifdef OBJ_ELF
3580 S_SET_SIZE (symbolP, size);
3581#endif
3582 }
3583 }
3584 else
3585 {
ab3e48dc
KH		 3586 as_warn ("Ignoring attempt to re-define symbol %s",
3587 S_GET_NAME (symbolP));
e0c6ed95 3588 } /* if not redefining. */
252b5132
RH		 3589
3590 demand_empty_rest_of_line ();
3591}
3592
3593static void
3594s_common (ignore)
3595 int ignore;
3596{
3597 char *name;
3598 char c;
3599 char *p;
3600 int temp, size;
3601 symbolS *symbolP;
3602
3603 name = input_line_pointer;
3604 c = get_symbol_end ();
e0c6ed95 3605 /* Just after name is now '\0'. */
252b5132
RH		 3606 p = input_line_pointer;
3607 *p = c;
3608 SKIP_WHITESPACE ();
3609 if (*input_line_pointer != ',')
3610 {
3611 as_bad (_("Expected comma after symbol-name"));
3612 ignore_rest_of_line ();
3613 return;
3614 }
e0c6ed95
AM		 3615
3616 /* Skip ','. */
3617 input_line_pointer++;
3618
252b5132
RH		 3619 if ((temp = get_absolute_expression ()) < 0)
3620 {
3621 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3622 ignore_rest_of_line ();
3623 return;
3624 }
3625 size = temp;
3626 *p = 0;
3627 symbolP = symbol_find_or_make (name);
3628 *p = c;
3629 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3630 {
3631 as_bad (_("Ignoring attempt to re-define symbol"));
3632 ignore_rest_of_line ();
3633 return;
3634 }
3635 if (S_GET_VALUE (symbolP) != 0)
3636 {
3637 if (S_GET_VALUE (symbolP) != (valueT) size)
3638 {
3639 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3640 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3641 }
3642 }
3643 else
3644 {
3645#ifndef OBJ_ELF
3646 S_SET_VALUE (symbolP, (valueT) size);
3647 S_SET_EXTERNAL (symbolP);
3648#endif
3649 }
7dcc9865 3650 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3651 if (*input_line_pointer != ',')
3652 {
3653 as_bad (_("Expected comma after common length"));
3654 ignore_rest_of_line ();
3655 return;
3656 }
3657 input_line_pointer++;
3658 SKIP_WHITESPACE ();
3659 if (*input_line_pointer != '"')
3660 {
3661 temp = get_absolute_expression ();
3662
3663#ifndef OBJ_ELF
3664 if (temp > max_alignment)
3665 {
3666 temp = max_alignment;
3667 as_warn (_("alignment too large; assuming %d"), temp);
3668 }
3669#endif
3670
3671 if (temp < 0)
3672 {
3673 as_bad (_("negative alignment"));
3674 ignore_rest_of_line ();
3675 return;
3676 }
3677
3678#ifdef OBJ_ELF
49309057 3679 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3680 {
3681 segT old_sec;
3682 int old_subsec;
3683 char *p;
3684 int align;
3685
3686 old_sec = now_seg;
3687 old_subsec = now_subseg;
3688
3689 if (temp == 0)
3690 align = 0;
3691 else
3692 align = log2 (temp);
3693
3694 if (align < 0)
3695 {
3696 as_bad (_("alignment not a power of 2"));
3697 ignore_rest_of_line ();
3698 return;
3699 }
3700
3701 record_alignment (bss_section, align);
3702 subseg_set (bss_section, 0);
3703 if (align)
3704 frag_align (align, 0, 0);
3705 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3706 symbol_get_frag (symbolP)->fr_symbol = 0;
3707 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3708 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3709 (offsetT) size, (char *) 0);
3710 *p = 0;
3711 S_SET_SEGMENT (symbolP, bss_section);
3712 S_CLEAR_EXTERNAL (symbolP);
3713 S_SET_SIZE (symbolP, size);
3714 subseg_set (old_sec, old_subsec);
3715 }
3716 else
e0c6ed95 3717#endif /* OBJ_ELF */
252b5132
RH		 3718 {
3719 allocate_common:
3720 S_SET_VALUE (symbolP, (valueT) size);
3721#ifdef OBJ_ELF
3722 S_SET_ALIGN (symbolP, temp);
3723 S_SET_SIZE (symbolP, size);
3724#endif
3725 S_SET_EXTERNAL (symbolP);
3726 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3727 }
3728 }
3729 else
3730 {
3731 input_line_pointer++;
3732 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3733 if (*input_line_pointer == '.')
3734 input_line_pointer++;
3735 /* @@ Some say data, some say bss. */
3736 if (strncmp (input_line_pointer, "bss\"", 4)
3737 && strncmp (input_line_pointer, "data\"", 5))
3738 {
3739 while (*--input_line_pointer != '"')
3740 ;
3741 input_line_pointer--;
3742 goto bad_common_segment;
3743 }
3744 while (*input_line_pointer++ != '"')
3745 ;
3746 goto allocate_common;
3747 }
3748
3749#ifdef BFD_ASSEMBLER
49309057 3750 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3751#endif
3752
3753 demand_empty_rest_of_line ();
3754 return;
3755
3756 {
3757 bad_common_segment:
3758 p = input_line_pointer;
3759 while (*p && *p != '\n')
3760 p++;
3761 c = *p;
3762 *p = '\0';
3763 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3764 *p = c;
3765 input_line_pointer = p;
3766 ignore_rest_of_line ();
3767 return;
3768 }
3769}
3770
3771/* Handle the .empty pseudo-op. This supresses the warnings about
3772 invalid delay slot usage. */
3773
3774static void
3775s_empty (ignore)
3776 int ignore;
3777{
3778 /* The easy way to implement is to just forget about the last
3779 instruction. */
3780 last_insn = NULL;
3781}
3782
3783static void
3784s_seg (ignore)
3785 int ignore;
3786{
3787
3788 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3789 {
3790 input_line_pointer += 6;
3791 s_text (0);
3792 return;
3793 }
3794 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3795 {
3796 input_line_pointer += 6;
3797 s_data (0);
3798 return;
3799 }
3800 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3801 {
3802 input_line_pointer += 7;
3803 s_data1 ();
3804 return;
3805 }
3806 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3807 {
3808 input_line_pointer += 5;
3809 /* We only support 2 segments -- text and data -- for now, so
3810 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 3811 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3812 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 3813 return;
3814 }
3815 as_bad (_("Unknown segment type"));
3816 demand_empty_rest_of_line ();
3817}
3818
3819static void
3820s_data1 ()
3821{
3822 subseg_set (data_section, 1);
3823 demand_empty_rest_of_line ();
3824}
3825
3826static void
3827s_proc (ignore)
3828 int ignore;
3829{
3830 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3831 {
3832 ++input_line_pointer;
3833 }
3834 ++input_line_pointer;
3835}
3836
3837/* This static variable is set by s_uacons to tell sparc_cons_align
3838 that the expession does not need to be aligned. */
3839
3840static int sparc_no_align_cons = 0;
3841
3842/* This handles the unaligned space allocation pseudo-ops, such as
3843 .uaword. .uaword is just like .word, but the value does not need
3844 to be aligned. */
3845
3846static void
3847s_uacons (bytes)
3848 int bytes;
3849{
3850 /* Tell sparc_cons_align not to align this value. */
3851 sparc_no_align_cons = 1;
3852 cons (bytes);
3853}
3854
cf9a1301
RH		 3855/* This handles the native word allocation pseudo-op .nword.
3856 For sparc_arch_size 32 it is equivalent to .word, for
3857 sparc_arch_size 64 it is equivalent to .xword. */
3858
3859static void
3860s_ncons (bytes)
3861 int bytes;
3862{
3863 cons (sparc_arch_size == 32 ? 4 : 8);
3864}
3865
6d8809aa
RH		 3866#ifdef OBJ_ELF
3867/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3868 global register.
3869 The syntax is:
e0c6ed95 3870
6d8809aa 3871 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 3872*/
6d8809aa
RH		 3873
3874static void
3875s_register (ignore)
3876 int ignore;
3877{
3878 char c;
3879 int reg;
3880 int flags;
3881 const char *regname;
3882
3883 if (input_line_pointer[0] != '%'
3884 || input_line_pointer[1] != 'g'
3885 || ((input_line_pointer[2] & ~1) != '2'
3886 && (input_line_pointer[2] & ~1) != '6')
3887 || input_line_pointer[3] != ',')
3888 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3889 reg = input_line_pointer[2] - '0';
3890 input_line_pointer += 4;
3891
3892 if (*input_line_pointer == '#')
3893 {
3894 ++input_line_pointer;
3895 regname = input_line_pointer;
3896 c = get_symbol_end ();
3897 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3898 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 3899 if (regname[0] == 'i')
6d8809aa
RH		 3900 regname = NULL;
3901 else
3902 regname = "";
3903 }
3904 else
3905 {
3906 regname = input_line_pointer;
3907 c = get_symbol_end ();
3908 }
3909 if (sparc_arch_size == 64)
3910 {
e0c6ed95 3911 if (globals[reg])
6d8809aa 3912 {
e0c6ed95
AM		 3913 if ((regname && globals[reg] != (symbolS *) 1
3914 && strcmp (S_GET_NAME (globals[reg]), regname))
3915 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 3916 as_bad (_("redefinition of global register"));
3917 }
3918 else
3919 {
3920 if (regname == NULL)
e0c6ed95 3921 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 3922 else
3923 {
3924 if (*regname)
3925 {
3926 if (symbol_find (regname))
3927 as_bad (_("Register symbol %s already defined."),
3928 regname);
3929 }
e0c6ed95
AM		 3930 globals[reg] = symbol_make (regname);
3931 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 3932 if (! *regname)
3933 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3934 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3935 flags |= BSF_GLOBAL;
e0c6ed95
AM		 3936 symbol_get_bfdsym (globals[reg])->flags = flags;
3937 S_SET_VALUE (globals[reg], (valueT) reg);
3938 S_SET_ALIGN (globals[reg], reg);
3939 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 3940 /* Although we actually want undefined_section here,
3941 we have to use absolute_section, because otherwise
3942 generic as code will make it a COM section.
3943 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 3944 S_SET_SEGMENT (globals[reg], absolute_section);
3945 S_SET_OTHER (globals[reg], 0);
3946 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 3947 ->internal_elf_sym.st_info =
3948 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 3949 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 3950 ->internal_elf_sym.st_shndx = SHN_UNDEF;
3951 }
3952 }
3953 }
3954
3955 *input_line_pointer = c;
3956
3957 demand_empty_rest_of_line ();
3958}
3959
3960/* Adjust the symbol table. We set undefined sections for STT_REGISTER
3961 symbols which need it. */
e0c6ed95 3962
6d8809aa
RH		 3963void
3964sparc_adjust_symtab ()
3965{
3966 symbolS *sym;
e0c6ed95 3967
6d8809aa
RH		 3968 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
3969 {
3970 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3971 ->internal_elf_sym.st_info) != STT_REGISTER)
3972 continue;
3973
3974 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3975 ->internal_elf_sym.st_shndx != SHN_UNDEF))
3976 continue;
3977
3978 S_SET_SEGMENT (sym, undefined_section);
3979 }
3980}
3981#endif
3982
252b5132
RH		 3983/* If the --enforce-aligned-data option is used, we require .word,
3984 et. al., to be aligned correctly. We do it by setting up an
3985 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3986 no unexpected alignment was introduced.
3987
3988 The SunOS and Solaris native assemblers enforce aligned data by
3989 default. We don't want to do that, because gcc can deliberately
3990 generate misaligned data if the packed attribute is used. Instead,
3991 we permit misaligned data by default, and permit the user to set an
3992 option to check for it. */
3993
3994void
3995sparc_cons_align (nbytes)
3996 int nbytes;
3997{
3998 int nalign;
3999 char *p;
4000
4001 /* Only do this if we are enforcing aligned data. */
4002 if (! enforce_aligned_data)
4003 return;
4004
4005 if (sparc_no_align_cons)
4006 {
4007 /* This is an unaligned pseudo-op. */
4008 sparc_no_align_cons = 0;
4009 return;
4010 }
4011
4012 nalign = log2 (nbytes);
4013 if (nalign == 0)
4014 return;
4015
4016 assert (nalign > 0);
4017
4018 if (now_seg == absolute_section)
4019 {
4020 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4021 as_bad (_("misaligned data"));
4022 return;
4023 }
4024
4025 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
4026 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4027
4028 record_alignment (now_seg, nalign);
4029}
4030
4031/* This is where we do the unexpected alignment check.
4032 This is called from HANDLE_ALIGN in tc-sparc.h. */
4033
4034void
4035sparc_handle_align (fragp)
4036 fragS *fragp;
4037{
4038 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
4039 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
4040 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4041 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
4042 {
ab3e48dc
KH		 4043 int count =
4044 fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
e0c6ed95 4045
252b5132
RH		 4046 if (count >= 4
4047 && !(count & 3)
4048 && count <= 1024
e0c6ed95
AM		 4049 && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
4050 {
4051 unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
4052 int i;
4053
4054 for (i = 0; i < count; i += 4, p++)
4055 if (INSN_BIG_ENDIAN)
4056 /* Emit nops. */
4057 number_to_chars_bigendian ((char *) p, 0x01000000, 4);
4058 else
4059 number_to_chars_littleendian ((char *) p, 0x10000000, 4);
4060
4061 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4062 {
252b5132 4063 char *waddr = &fragp->fr_literal[fragp->fr_fix];
e0c6ed95 4064 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
252b5132
RH		 4065 if (INSN_BIG_ENDIAN)
4066 number_to_chars_bigendian (waddr, wval, 4);
4067 else
4068 number_to_chars_littleendian (waddr, wval, 4);
e0c6ed95
AM		 4069 }
4070 fragp->fr_var = count;
4071 }
252b5132
RH		 4072 }
4073}
4074
4075#ifdef OBJ_ELF
4076/* Some special processing for a Sparc ELF file. */
4077
4078void
4079sparc_elf_final_processing ()
4080{
4081 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4082 sort of BFD interface for this. */
4083 if (sparc_arch_size == 64)
4084 {
4085 switch (sparc_memory_model)
4086 {
4087 case MM_RMO:
4088 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4089 break;
4090 case MM_PSO:
4091 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4092 break;
4093 default:
4094 break;
4095 }
4096 }
4097 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4098 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4099 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4100 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4101}
4102#endif
4103
4104/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4105 reloc for a cons. We could use the definition there, except that
4106 we want to handle little endian relocs specially. */
4107
4108void
4109cons_fix_new_sparc (frag, where, nbytes, exp)
4110 fragS *frag;
4111 int where;
4112 unsigned int nbytes;
4113 expressionS *exp;
4114{
4115 bfd_reloc_code_real_type r;
4116
4117 r = (nbytes == 1 ? BFD_RELOC_8 :
4118 (nbytes == 2 ? BFD_RELOC_16 :
4119 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4120
4121 if (target_little_endian_data && nbytes == 4
e0c6ed95 4122 && now_seg->flags & SEC_ALLOC)
252b5132
RH		 4123 r = BFD_RELOC_SPARC_REV32;
4124 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4125}
4126
4127#ifdef OBJ_ELF
4128int
4129elf32_sparc_force_relocation (fixp)
e0c6ed95 4130 struct fix *fixp;
252b5132
RH		 4131{
4132 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4133 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4134 return 1;
e0c6ed95 4135
252b5132
RH		 4136 return 0;
4137}
4138#endif
GDB Binutils - Deliverables
This page took 0.233802 seconds and 4 git commands to generate.