Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
f7e42eb4 | 2 | Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
c699f087 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
e0c6ed95 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | This file is part of GAS, the GNU Assembler. |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public | |
18 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
19 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 RH |
24 | #include "subsegs.h" |
25 | ||
26 | #include "opcode/sparc.h" | |
364b6d8b | 27 | #include "dw2gencfi.h" |
252b5132 RH |
28 | |
29 | #ifdef OBJ_ELF | |
30 | #include "elf/sparc.h" | |
732d96b6 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
6c1b24e4 AO |
34 | /* Some ancient Sun C compilers would not take such hex constants as |
35 | unsigned, and would end up sign-extending them to form an offsetT, | |
36 | so use these constants instead. */ | |
37 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
38 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
39 | ||
252b5132 RH |
40 | static struct sparc_arch *lookup_arch PARAMS ((char *)); |
41 | static void init_default_arch PARAMS ((void)); | |
a22b281c | 42 | static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); |
252b5132 RH |
43 | static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); |
44 | static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); | |
45 | static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); | |
46 | static int sparc_ffs PARAMS ((unsigned int)); | |
a22b281c RH |
47 | static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); |
48 | static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); | |
49 | static void synthetize_setx PARAMS ((const struct sparc_opcode *)); | |
252b5132 RH |
50 | static bfd_vma BSR PARAMS ((bfd_vma, int)); |
51 | static int cmp_reg_entry PARAMS ((const PTR, const PTR)); | |
52 | static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); | |
53 | static int parse_const_expr_arg PARAMS ((char **, int *)); | |
54 | static int get_expression PARAMS ((char *str)); | |
55 | ||
56 | /* Default architecture. */ | |
57 | /* ??? The default value should be V8, but sparclite support was added | |
58 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
59 | the future we can set this to V8. */ | |
60 | #ifndef DEFAULT_ARCH | |
61 | #define DEFAULT_ARCH "sparclite" | |
62 | #endif | |
63 | static char *default_arch = DEFAULT_ARCH; | |
64 | ||
65 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
66 | have been set. */ | |
67 | static int default_init_p; | |
68 | ||
69 | /* Current architecture. We don't bump up unless necessary. */ | |
70 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
71 | ||
72 | /* The maximum architecture level we can bump up to. | |
73 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
74 | The native assembler works this way. The user is required to pass | |
75 | an explicit argument before we'll create v9 object files. However, if | |
76 | we don't see any v9 insns, a v8plus object file is not created. */ | |
77 | static enum sparc_opcode_arch_val max_architecture; | |
78 | ||
79 | /* Either 32 or 64, selects file format. */ | |
80 | static int sparc_arch_size; | |
81 | /* Initial (default) value, recorded separately in case a user option | |
82 | changes the value before md_show_usage is called. */ | |
83 | static int default_arch_size; | |
84 | ||
85 | #ifdef OBJ_ELF | |
86 | /* The currently selected v9 memory model. Currently only used for | |
87 | ELF. */ | |
88 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
89 | #endif | |
90 | ||
91 | static int architecture_requested; | |
92 | static int warn_on_bump; | |
93 | ||
94 | /* If warn_on_bump and the needed architecture is higher than this | |
95 | architecture, issue a warning. */ | |
96 | static enum sparc_opcode_arch_val warn_after_architecture; | |
97 | ||
6d8809aa RH |
98 | /* Non-zero if as should generate error if an undeclared g[23] register |
99 | has been used in -64. */ | |
100 | static int no_undeclared_regs; | |
101 | ||
6faf3d66 JJ |
102 | /* Non-zero if we should try to relax jumps and calls. */ |
103 | static int sparc_relax; | |
104 | ||
252b5132 RH |
105 | /* Non-zero if we are generating PIC code. */ |
106 | int sparc_pic_code; | |
107 | ||
108 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
109 | static int enforce_aligned_data; | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
113 | static int target_little_endian_data; | |
114 | ||
6d8809aa RH |
115 | /* Symbols for global registers on v9. */ |
116 | static symbolS *globals[8]; | |
117 | ||
364b6d8b JJ |
118 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
119 | int sparc_cie_data_alignment; | |
120 | ||
252b5132 RH |
121 | /* V9 and 86x have big and little endian data, but instructions are always big |
122 | endian. The sparclet has bi-endian support but both data and insns have | |
123 | the same endianness. Global `target_big_endian' is used for data. | |
124 | The following macro is used for instructions. */ | |
125 | #ifndef INSN_BIG_ENDIAN | |
126 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
127 | || default_arch_type == sparc86x \ | |
128 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
129 | #endif | |
130 | ||
e0c6ed95 | 131 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
132 | static struct hash_control *op_hash; |
133 | ||
f17c130b | 134 | static int mylog2 PARAMS ((int)); |
252b5132 RH |
135 | static void s_data1 PARAMS ((void)); |
136 | static void s_seg PARAMS ((int)); | |
137 | static void s_proc PARAMS ((int)); | |
138 | static void s_reserve PARAMS ((int)); | |
139 | static void s_common PARAMS ((int)); | |
140 | static void s_empty PARAMS ((int)); | |
141 | static void s_uacons PARAMS ((int)); | |
cf9a1301 | 142 | static void s_ncons PARAMS ((int)); |
a7982600 | 143 | #ifdef OBJ_ELF |
6d8809aa | 144 | static void s_register PARAMS ((int)); |
a7982600 | 145 | #endif |
252b5132 RH |
146 | |
147 | const pseudo_typeS md_pseudo_table[] = | |
148 | { | |
e0c6ed95 | 149 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
150 | {"common", s_common, 0}, |
151 | {"empty", s_empty, 0}, | |
152 | {"global", s_globl, 0}, | |
153 | {"half", cons, 2}, | |
cf9a1301 | 154 | {"nword", s_ncons, 0}, |
252b5132 RH |
155 | {"optim", s_ignore, 0}, |
156 | {"proc", s_proc, 0}, | |
157 | {"reserve", s_reserve, 0}, | |
158 | {"seg", s_seg, 0}, | |
159 | {"skip", s_space, 0}, | |
160 | {"word", cons, 4}, | |
161 | {"xword", cons, 8}, | |
162 | {"uahalf", s_uacons, 2}, | |
163 | {"uaword", s_uacons, 4}, | |
164 | {"uaxword", s_uacons, 8}, | |
165 | #ifdef OBJ_ELF | |
e0c6ed95 | 166 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
167 | {"2byte", s_uacons, 2}, |
168 | {"4byte", s_uacons, 4}, | |
169 | {"8byte", s_uacons, 8}, | |
6d8809aa | 170 | {"register", s_register, 0}, |
252b5132 RH |
171 | #endif |
172 | {NULL, 0, 0}, | |
173 | }; | |
174 | ||
252b5132 | 175 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
176 | pre-processor is disabled, these aren't very useful. */ |
177 | const char comment_chars[] = "!"; /* JF removed '|' from | |
178 | comment_chars. */ | |
252b5132 RH |
179 | |
180 | /* This array holds the chars that only start a comment at the beginning of | |
181 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 182 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
183 | /* Note that input_file.c hand checks for '#' at the beginning of the |
184 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 185 | #NO_APP at the beginning of its output. */ |
252b5132 | 186 | /* Also note that comments started like this one will always |
e0c6ed95 | 187 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
188 | const char line_comment_chars[] = "#"; |
189 | ||
63a0b638 | 190 | const char line_separator_chars[] = ";"; |
252b5132 | 191 | |
e0c6ed95 AM |
192 | /* Chars that can be used to separate mant from exp in floating point |
193 | nums. */ | |
252b5132 RH |
194 | const char EXP_CHARS[] = "eE"; |
195 | ||
e0c6ed95 AM |
196 | /* Chars that mean this number is a floating point constant. |
197 | As in 0f12.456 | |
198 | or 0d1.2345e12 */ | |
252b5132 RH |
199 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
200 | ||
201 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
202 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
203 | but nothing is ideal around here. */ | |
204 | ||
74b56d1f | 205 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
206 | |
207 | struct sparc_it | |
208 | { | |
209 | char *error; | |
210 | unsigned long opcode; | |
211 | struct nlist *nlistp; | |
212 | expressionS exp; | |
cf9a1301 | 213 | expressionS exp2; |
252b5132 RH |
214 | int pcrel; |
215 | bfd_reloc_code_real_type reloc; | |
216 | }; | |
217 | ||
218 | struct sparc_it the_insn, set_insn; | |
219 | ||
220 | static void output_insn | |
221 | PARAMS ((const struct sparc_opcode *, struct sparc_it *)); | |
222 | \f | |
223 | /* Table of arguments to -A. | |
224 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
225 | for this use. That table is for opcodes only. This table is for opcodes | |
226 | and file formats. */ | |
227 | ||
228 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, | |
19f7b010 | 229 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
230 | |
231 | static struct sparc_arch { | |
232 | char *name; | |
233 | char *opcode_arch; | |
234 | enum sparc_arch_types arch_type; | |
235 | /* Default word size, as specified during configuration. | |
236 | A value of zero means can't be used to specify default architecture. */ | |
237 | int default_arch_size; | |
238 | /* Allowable arg to -A? */ | |
239 | int user_option_p; | |
240 | } sparc_arch_table[] = { | |
241 | { "v6", "v6", v6, 0, 1 }, | |
242 | { "v7", "v7", v7, 0, 1 }, | |
243 | { "v8", "v8", v8, 32, 1 }, | |
244 | { "sparclet", "sparclet", sparclet, 32, 1 }, | |
245 | { "sparclite", "sparclite", sparclite, 32, 1 }, | |
246 | { "sparc86x", "sparclite", sparc86x, 32, 1 }, | |
247 | { "v8plus", "v9", v9, 0, 1 }, | |
248 | { "v8plusa", "v9a", v9, 0, 1 }, | |
19f7b010 | 249 | { "v8plusb", "v9b", v9, 0, 1 }, |
252b5132 RH |
250 | { "v9", "v9", v9, 0, 1 }, |
251 | { "v9a", "v9a", v9, 0, 1 }, | |
19f7b010 | 252 | { "v9b", "v9b", v9, 0, 1 }, |
252b5132 RH |
253 | /* This exists to allow configure.in/Makefile.in to pass one |
254 | value to specify both the default machine and default word size. */ | |
255 | { "v9-64", "v9", v9, 64, 0 }, | |
256 | { NULL, NULL, v8, 0, 0 } | |
257 | }; | |
258 | ||
259 | /* Variant of default_arch */ | |
260 | static enum sparc_arch_types default_arch_type; | |
261 | ||
262 | static struct sparc_arch * | |
263 | lookup_arch (name) | |
264 | char *name; | |
265 | { | |
266 | struct sparc_arch *sa; | |
267 | ||
268 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
269 | if (strcmp (sa->name, name) == 0) | |
270 | break; | |
271 | if (sa->name == NULL) | |
272 | return NULL; | |
273 | return sa; | |
274 | } | |
275 | ||
276 | /* Initialize the default opcode arch and word size from the default | |
277 | architecture name. */ | |
278 | ||
279 | static void | |
280 | init_default_arch () | |
281 | { | |
282 | struct sparc_arch *sa = lookup_arch (default_arch); | |
283 | ||
284 | if (sa == NULL | |
285 | || sa->default_arch_size == 0) | |
286 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
287 | ||
288 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
289 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
290 | as_fatal (_("Bad opcode table, broken assembler.")); | |
291 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
292 | default_init_p = 1; | |
293 | default_arch_type = sa->arch_type; | |
294 | } | |
295 | ||
296 | /* Called by TARGET_FORMAT. */ | |
297 | ||
298 | const char * | |
299 | sparc_target_format () | |
300 | { | |
301 | /* We don't get a chance to initialize anything before we're called, | |
302 | so handle that now. */ | |
303 | if (! default_init_p) | |
304 | init_default_arch (); | |
305 | ||
306 | #ifdef OBJ_AOUT | |
307 | #ifdef TE_NetBSD | |
308 | return "a.out-sparc-netbsd"; | |
309 | #else | |
310 | #ifdef TE_SPARCAOUT | |
311 | if (target_big_endian) | |
312 | return "a.out-sunos-big"; | |
313 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
314 | return "a.out-sunos-big"; | |
ab3e48dc KH |
315 | else |
316 | return "a.out-sparc-little"; | |
252b5132 RH |
317 | #else |
318 | return "a.out-sunos-big"; | |
319 | #endif | |
320 | #endif | |
321 | #endif | |
322 | ||
323 | #ifdef OBJ_BOUT | |
324 | return "b.out.big"; | |
325 | #endif | |
326 | ||
327 | #ifdef OBJ_COFF | |
328 | #ifdef TE_LYNX | |
329 | return "coff-sparc-lynx"; | |
330 | #else | |
331 | return "coff-sparc"; | |
332 | #endif | |
333 | #endif | |
334 | ||
910600e9 RS |
335 | #ifdef TE_VXWORKS |
336 | return "elf32-sparc-vxworks"; | |
337 | #endif | |
338 | ||
252b5132 | 339 | #ifdef OBJ_ELF |
71a75f6f | 340 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
341 | #endif |
342 | ||
343 | abort (); | |
344 | } | |
345 | \f | |
e0c6ed95 | 346 | /* md_parse_option |
252b5132 RH |
347 | * Invocation line includes a switch not recognized by the base assembler. |
348 | * See if it's a processor-specific option. These are: | |
349 | * | |
350 | * -bump | |
351 | * Warn on architecture bumps. See also -A. | |
352 | * | |
353 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
354 | * Standard 32 bit architectures. | |
19f7b010 | 355 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
356 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
357 | * This used to only mean 64 bits, but properly specifying it | |
358 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
359 | * specified orthogonally to word size (except when specifying | |
360 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
361 | * -Av8plus, -Av8plusa, -Av8plusb |
362 | * Same as -Av9{,a,b}. | |
363 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
364 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
365 | * assembler. | |
366 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
367 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 368 | * assembler. |
252b5132 RH |
369 | * |
370 | * Select the architecture and possibly the file format. | |
371 | * Instructions or features not supported by the selected | |
372 | * architecture cause fatal errors. | |
373 | * | |
374 | * The default is to start at v6, and bump the architecture up | |
375 | * whenever an instruction is seen at a higher level. In 32 bit | |
376 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 377 | * -Av8plus{,a,b}. |
252b5132 RH |
378 | * |
379 | * If -bump is specified, a warning is printing when bumping to | |
380 | * higher levels. | |
381 | * | |
382 | * If an architecture is specified, all instructions must match | |
383 | * that architecture. Any higher level instructions are flagged | |
384 | * as errors. Note that in the 32 bit environment specifying | |
385 | * -Av8plus does not automatically create a v8plus object file, a | |
386 | * v9 insn must be seen. | |
387 | * | |
388 | * If both an architecture and -bump are specified, the | |
389 | * architecture starts at the specified level, but bumps are | |
390 | * warnings. Note that we can't set `current_architecture' to | |
391 | * the requested level in this case: in the 32 bit environment, | |
392 | * we still must avoid creating v8plus object files unless v9 | |
393 | * insns are seen. | |
394 | * | |
395 | * Note: | |
396 | * Bumping between incompatible architectures is always an | |
397 | * error. For example, from sparclite to v9. | |
398 | */ | |
399 | ||
400 | #ifdef OBJ_ELF | |
5a38dc70 | 401 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
402 | #else |
403 | #ifdef OBJ_AOUT | |
5a38dc70 | 404 | const char *md_shortopts = "A:k"; |
252b5132 | 405 | #else |
5a38dc70 | 406 | const char *md_shortopts = "A:"; |
252b5132 RH |
407 | #endif |
408 | #endif | |
409 | struct option md_longopts[] = { | |
410 | #define OPTION_BUMP (OPTION_MD_BASE) | |
411 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
412 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
413 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
414 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
415 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
416 | #ifdef OBJ_ELF | |
417 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
418 | {"32", no_argument, NULL, OPTION_32}, | |
419 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
420 | {"64", no_argument, NULL, OPTION_64}, | |
421 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
422 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
423 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
424 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
425 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
426 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
427 | #endif | |
428 | #ifdef SPARC_BIENDIAN | |
429 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
430 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
431 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
432 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
433 | #endif | |
434 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
435 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
436 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
437 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
438 | #ifdef OBJ_ELF |
439 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
440 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
441 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
442 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 443 | #endif |
6faf3d66 JJ |
444 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
445 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
446 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
447 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
252b5132 RH |
448 | {NULL, no_argument, NULL, 0} |
449 | }; | |
e0c6ed95 AM |
450 | |
451 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
452 | |
453 | int | |
454 | md_parse_option (c, arg) | |
455 | int c; | |
456 | char *arg; | |
457 | { | |
458 | /* We don't get a chance to initialize anything before we're called, | |
459 | so handle that now. */ | |
460 | if (! default_init_p) | |
461 | init_default_arch (); | |
462 | ||
463 | switch (c) | |
464 | { | |
465 | case OPTION_BUMP: | |
466 | warn_on_bump = 1; | |
467 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
468 | break; | |
469 | ||
470 | case OPTION_XARCH: | |
c2158c24 JJ |
471 | #ifdef OBJ_ELF |
472 | if (strncmp (arg, "v9", 2) != 0) | |
473 | md_parse_option (OPTION_32, NULL); | |
474 | else | |
475 | md_parse_option (OPTION_64, NULL); | |
476 | #endif | |
e0c6ed95 | 477 | /* Fall through. */ |
252b5132 RH |
478 | |
479 | case 'A': | |
480 | { | |
481 | struct sparc_arch *sa; | |
482 | enum sparc_opcode_arch_val opcode_arch; | |
483 | ||
484 | sa = lookup_arch (arg); | |
485 | if (sa == NULL | |
486 | || ! sa->user_option_p) | |
487 | { | |
c2158c24 JJ |
488 | if (c == OPTION_XARCH) |
489 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
490 | else | |
491 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
492 | return 0; |
493 | } | |
494 | ||
495 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
496 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
497 | as_fatal (_("Bad opcode table, broken assembler.")); | |
498 | ||
499 | max_architecture = opcode_arch; | |
500 | architecture_requested = 1; | |
501 | } | |
502 | break; | |
503 | ||
504 | case OPTION_SPARC: | |
505 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
506 | break; | |
507 | ||
508 | case OPTION_ENFORCE_ALIGNED_DATA: | |
509 | enforce_aligned_data = 1; | |
510 | break; | |
511 | ||
512 | #ifdef SPARC_BIENDIAN | |
513 | case OPTION_LITTLE_ENDIAN: | |
514 | target_big_endian = 0; | |
515 | if (default_arch_type != sparclet) | |
516 | as_fatal ("This target does not support -EL"); | |
517 | break; | |
518 | case OPTION_LITTLE_ENDIAN_DATA: | |
519 | target_little_endian_data = 1; | |
520 | target_big_endian = 0; | |
521 | if (default_arch_type != sparc86x | |
522 | && default_arch_type != v9) | |
523 | as_fatal ("This target does not support --little-endian-data"); | |
524 | break; | |
525 | case OPTION_BIG_ENDIAN: | |
526 | target_big_endian = 1; | |
527 | break; | |
528 | #endif | |
529 | ||
530 | #ifdef OBJ_AOUT | |
531 | case 'k': | |
532 | sparc_pic_code = 1; | |
533 | break; | |
534 | #endif | |
535 | ||
536 | #ifdef OBJ_ELF | |
537 | case OPTION_32: | |
538 | case OPTION_64: | |
539 | { | |
540 | const char **list, **l; | |
541 | ||
542 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
543 | list = bfd_target_list (); | |
544 | for (l = list; *l != NULL; l++) | |
545 | { | |
546 | if (sparc_arch_size == 32) | |
547 | { | |
71a75f6f | 548 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
549 | break; |
550 | } | |
551 | else | |
552 | { | |
71a75f6f | 553 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
554 | break; |
555 | } | |
556 | } | |
557 | if (*l == NULL) | |
558 | as_fatal (_("No compiled in support for %d bit object file format"), | |
559 | sparc_arch_size); | |
560 | free (list); | |
561 | } | |
562 | break; | |
563 | ||
564 | case OPTION_TSO: | |
565 | sparc_memory_model = MM_TSO; | |
566 | break; | |
567 | ||
568 | case OPTION_PSO: | |
569 | sparc_memory_model = MM_PSO; | |
570 | break; | |
571 | ||
572 | case OPTION_RMO: | |
573 | sparc_memory_model = MM_RMO; | |
574 | break; | |
575 | ||
576 | case 'V': | |
577 | print_version_id (); | |
578 | break; | |
579 | ||
580 | case 'Q': | |
581 | /* Qy - do emit .comment | |
e0c6ed95 | 582 | Qn - do not emit .comment. */ |
252b5132 RH |
583 | break; |
584 | ||
585 | case 's': | |
e0c6ed95 | 586 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
587 | break; |
588 | ||
589 | case 'q': | |
e0c6ed95 | 590 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
591 | break; |
592 | ||
593 | case 'K': | |
594 | if (strcmp (arg, "PIC") != 0) | |
595 | as_warn (_("Unrecognized option following -K")); | |
596 | else | |
597 | sparc_pic_code = 1; | |
598 | break; | |
6d8809aa RH |
599 | |
600 | case OPTION_NO_UNDECLARED_REGS: | |
601 | no_undeclared_regs = 1; | |
602 | break; | |
a25fe906 ILT |
603 | |
604 | case OPTION_UNDECLARED_REGS: | |
605 | no_undeclared_regs = 0; | |
606 | break; | |
252b5132 RH |
607 | #endif |
608 | ||
6faf3d66 JJ |
609 | case OPTION_RELAX: |
610 | sparc_relax = 1; | |
611 | break; | |
612 | ||
613 | case OPTION_NO_RELAX: | |
614 | sparc_relax = 0; | |
615 | break; | |
616 | ||
252b5132 RH |
617 | default: |
618 | return 0; | |
619 | } | |
620 | ||
621 | return 1; | |
622 | } | |
623 | ||
624 | void | |
625 | md_show_usage (stream) | |
626 | FILE *stream; | |
627 | { | |
628 | const struct sparc_arch *arch; | |
c2158c24 | 629 | int column; |
252b5132 RH |
630 | |
631 | /* We don't get a chance to initialize anything before we're called, | |
632 | so handle that now. */ | |
633 | if (! default_init_p) | |
634 | init_default_arch (); | |
635 | ||
e0c6ed95 | 636 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 637 | column = 0; |
252b5132 RH |
638 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
639 | { | |
c2158c24 JJ |
640 | if (!arch->user_option_p) |
641 | continue; | |
252b5132 RH |
642 | if (arch != &sparc_arch_table[0]) |
643 | fprintf (stream, " | "); | |
07726851 | 644 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
645 | { |
646 | column = 0; | |
647 | fputc ('\n', stream); | |
648 | } | |
07726851 | 649 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 650 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 651 | } |
c2158c24 JJ |
652 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
653 | { | |
654 | if (!arch->user_option_p) | |
655 | continue; | |
656 | fprintf (stream, " | "); | |
07726851 | 657 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
658 | { |
659 | column = 0; | |
660 | fputc ('\n', stream); | |
661 | } | |
07726851 | 662 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
663 | fprintf (stream, "-xarch=%s", arch->name); |
664 | } | |
665 | fprintf (stream, _("\n\ | |
252b5132 RH |
666 | specify variant of SPARC architecture\n\ |
667 | -bump warn when assembler switches architectures\n\ | |
668 | -sparc ignored\n\ | |
6faf3d66 JJ |
669 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
670 | -relax relax jumps and branches (default)\n\ | |
671 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
672 | #ifdef OBJ_AOUT |
673 | fprintf (stream, _("\ | |
674 | -k generate PIC\n")); | |
675 | #endif | |
676 | #ifdef OBJ_ELF | |
677 | fprintf (stream, _("\ | |
678 | -32 create 32 bit object file\n\ | |
679 | -64 create 64 bit object file\n")); | |
680 | fprintf (stream, _("\ | |
681 | [default is %d]\n"), default_arch_size); | |
682 | fprintf (stream, _("\ | |
683 | -TSO use Total Store Ordering\n\ | |
684 | -PSO use Partial Store Ordering\n\ | |
685 | -RMO use Relaxed Memory Ordering\n")); | |
686 | fprintf (stream, _("\ | |
687 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
688 | fprintf (stream, _("\ | |
689 | -KPIC generate PIC\n\ | |
690 | -V print assembler version number\n\ | |
a25fe906 ILT |
691 | -undeclared-regs ignore application global register usage without\n\ |
692 | appropriate .register directive (default)\n\ | |
693 | -no-undeclared-regs force error on application global register usage\n\ | |
694 | without appropriate .register directive\n\ | |
252b5132 RH |
695 | -q ignored\n\ |
696 | -Qy, -Qn ignored\n\ | |
697 | -s ignored\n")); | |
698 | #endif | |
699 | #ifdef SPARC_BIENDIAN | |
700 | fprintf (stream, _("\ | |
701 | -EL generate code for a little endian machine\n\ | |
702 | -EB generate code for a big endian machine\n\ | |
703 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 704 | instructions and little endian data.\n")); |
252b5132 RH |
705 | #endif |
706 | } | |
707 | \f | |
e0c6ed95 | 708 | /* Native operand size opcode translation. */ |
cf9a1301 RH |
709 | struct |
710 | { | |
711 | char *name; | |
712 | char *name32; | |
713 | char *name64; | |
714 | } native_op_table[] = | |
715 | { | |
716 | {"ldn", "ld", "ldx"}, | |
717 | {"ldna", "lda", "ldxa"}, | |
718 | {"stn", "st", "stx"}, | |
719 | {"stna", "sta", "stxa"}, | |
720 | {"slln", "sll", "sllx"}, | |
721 | {"srln", "srl", "srlx"}, | |
722 | {"sran", "sra", "srax"}, | |
723 | {"casn", "cas", "casx"}, | |
724 | {"casna", "casa", "casxa"}, | |
725 | {"clrn", "clr", "clrx"}, | |
726 | {NULL, NULL, NULL}, | |
727 | }; | |
728 | \f | |
10156f83 | 729 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
730 | |
731 | struct priv_reg_entry | |
ab3e48dc KH |
732 | { |
733 | char *name; | |
734 | int regnum; | |
735 | }; | |
252b5132 RH |
736 | |
737 | struct priv_reg_entry priv_reg_table[] = | |
738 | { | |
739 | {"tpc", 0}, | |
740 | {"tnpc", 1}, | |
741 | {"tstate", 2}, | |
742 | {"tt", 3}, | |
743 | {"tick", 4}, | |
744 | {"tba", 5}, | |
745 | {"pstate", 6}, | |
746 | {"tl", 7}, | |
747 | {"pil", 8}, | |
748 | {"cwp", 9}, | |
749 | {"cansave", 10}, | |
750 | {"canrestore", 11}, | |
751 | {"cleanwin", 12}, | |
752 | {"otherwin", 13}, | |
753 | {"wstate", 14}, | |
754 | {"fq", 15}, | |
10156f83 | 755 | {"gl", 16}, |
252b5132 | 756 | {"ver", 31}, |
e0c6ed95 | 757 | {"", -1}, /* End marker. */ |
252b5132 RH |
758 | }; |
759 | ||
10156f83 DM |
760 | struct priv_reg_entry hpriv_reg_table[] = |
761 | { | |
762 | {"hpstate", 0}, | |
763 | {"htstate", 1}, | |
764 | {"hintp", 3}, | |
765 | {"htba", 5}, | |
766 | {"hver", 6}, | |
767 | {"hstick_cmpr", 31}, | |
768 | {"", -1}, /* End marker. */ | |
769 | }; | |
770 | ||
1a6b486f DM |
771 | /* v9a specific asrs. This table is ordered by initial |
772 | letter, in reverse. */ | |
252b5132 RH |
773 | |
774 | struct priv_reg_entry v9a_asr_table[] = | |
775 | { | |
776 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
777 | {"sys_tick_cmpr", 25}, |
778 | {"sys_tick", 24}, | |
1a6b486f DM |
779 | {"stick_cmpr", 25}, |
780 | {"stick", 24}, | |
252b5132 RH |
781 | {"softint", 22}, |
782 | {"set_softint", 20}, | |
783 | {"pic", 17}, | |
784 | {"pcr", 16}, | |
785 | {"gsr", 19}, | |
786 | {"dcr", 18}, | |
787 | {"clear_softint", 21}, | |
e0c6ed95 | 788 | {"", -1}, /* End marker. */ |
252b5132 RH |
789 | }; |
790 | ||
791 | static int | |
792 | cmp_reg_entry (parg, qarg) | |
793 | const PTR parg; | |
794 | const PTR qarg; | |
795 | { | |
796 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
797 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
798 | ||
799 | return strcmp (q->name, p->name); | |
800 | } | |
801 | \f | |
802 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
803 | set up all the tables, etc. that the MD part of the assembler will |
804 | need. */ | |
252b5132 RH |
805 | |
806 | void | |
807 | md_begin () | |
808 | { | |
809 | register const char *retval = NULL; | |
810 | int lose = 0; | |
811 | register unsigned int i = 0; | |
812 | ||
813 | /* We don't get a chance to initialize anything before md_parse_option | |
814 | is called, and it may not be called, so handle default initialization | |
815 | now if not already done. */ | |
816 | if (! default_init_p) | |
817 | init_default_arch (); | |
818 | ||
364b6d8b | 819 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
820 | op_hash = hash_new (); |
821 | ||
822 | while (i < (unsigned int) sparc_num_opcodes) | |
823 | { | |
824 | const char *name = sparc_opcodes[i].name; | |
825 | retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); | |
826 | if (retval != NULL) | |
827 | { | |
cf9a1301 RH |
828 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
829 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
830 | lose = 1; |
831 | } | |
832 | do | |
833 | { | |
834 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
835 | { | |
cf9a1301 RH |
836 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
837 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
838 | lose = 1; |
839 | } | |
840 | ++i; | |
841 | } | |
842 | while (i < (unsigned int) sparc_num_opcodes | |
843 | && !strcmp (sparc_opcodes[i].name, name)); | |
844 | } | |
845 | ||
cf9a1301 RH |
846 | for (i = 0; native_op_table[i].name; i++) |
847 | { | |
848 | const struct sparc_opcode *insn; | |
3d4ae3c0 NC |
849 | char *name = ((sparc_arch_size == 32) |
850 | ? native_op_table[i].name32 | |
851 | : native_op_table[i].name64); | |
e0c6ed95 | 852 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 853 | if (insn == NULL) |
e0c6ed95 AM |
854 | { |
855 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
856 | name, native_op_table[i].name); | |
857 | lose = 1; | |
858 | } | |
cf9a1301 RH |
859 | else |
860 | { | |
861 | retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); | |
862 | if (retval != NULL) | |
863 | { | |
864 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
865 | sparc_opcodes[i].name, retval); | |
866 | lose = 1; | |
867 | } | |
868 | } | |
869 | } | |
870 | ||
252b5132 RH |
871 | if (lose) |
872 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
873 | ||
252b5132 RH |
874 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
875 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
876 | ||
877 | /* If -bump, record the architecture level at which we start issuing | |
878 | warnings. The behaviour is different depending upon whether an | |
879 | architecture was explicitly specified. If it wasn't, we issue warnings | |
880 | for all upwards bumps. If it was, we don't start issuing warnings until | |
881 | we need to bump beyond the requested architecture or when we bump between | |
882 | conflicting architectures. */ | |
883 | ||
884 | if (warn_on_bump | |
885 | && architecture_requested) | |
886 | { | |
887 | /* `max_architecture' records the requested architecture. | |
888 | Issue warnings if we go above it. */ | |
889 | warn_after_architecture = max_architecture; | |
890 | ||
891 | /* Find the highest architecture level that doesn't conflict with | |
892 | the requested one. */ | |
893 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
894 | max_architecture > warn_after_architecture; | |
895 | --max_architecture) | |
896 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
897 | warn_after_architecture)) | |
898 | break; | |
899 | } | |
900 | } | |
901 | ||
902 | /* Called after all assembly has been done. */ | |
903 | ||
904 | void | |
905 | sparc_md_end () | |
906 | { | |
19f7b010 JJ |
907 | unsigned long mach = bfd_mach_sparc; |
908 | ||
252b5132 | 909 | if (sparc_arch_size == 64) |
19f7b010 JJ |
910 | switch (current_architecture) |
911 | { | |
912 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
913 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
914 | default: mach = bfd_mach_sparc_v9; break; | |
915 | } | |
252b5132 | 916 | else |
19f7b010 JJ |
917 | switch (current_architecture) |
918 | { | |
919 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
920 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
921 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
922 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
923 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
924 | be but for now it is (since that's the way it's always been | |
925 | treated). */ | |
926 | default: break; | |
927 | } | |
928 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
252b5132 RH |
929 | } |
930 | \f | |
931 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
932 | ||
933 | static INLINE int | |
934 | in_signed_range (val, max) | |
935 | bfd_signed_vma val, max; | |
936 | { | |
937 | if (max <= 0) | |
938 | abort (); | |
939 | /* Sign-extend the value from the architecture word size, so that | |
940 | 0xffffffff is always considered -1 on sparc32. */ | |
941 | if (sparc_arch_size == 32) | |
942 | { | |
e0c6ed95 | 943 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 944 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
945 | } |
946 | if (val > max) | |
947 | return 0; | |
948 | if (val < ~max) | |
949 | return 0; | |
950 | return 1; | |
951 | } | |
952 | ||
953 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
954 | ||
955 | static INLINE int | |
956 | in_unsigned_range (val, max) | |
957 | bfd_vma val, max; | |
958 | { | |
959 | if (val > max) | |
960 | return 0; | |
961 | return 1; | |
962 | } | |
963 | ||
964 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
965 | (e.g. -15 to +31). */ | |
966 | ||
967 | static INLINE int | |
968 | in_bitfield_range (val, max) | |
969 | bfd_signed_vma val, max; | |
970 | { | |
971 | if (max <= 0) | |
972 | abort (); | |
973 | if (val > max) | |
974 | return 0; | |
975 | if (val < ~(max >> 1)) | |
976 | return 0; | |
977 | return 1; | |
978 | } | |
979 | ||
980 | static int | |
981 | sparc_ffs (mask) | |
982 | unsigned int mask; | |
983 | { | |
984 | int i; | |
985 | ||
986 | if (mask == 0) | |
987 | return -1; | |
988 | ||
989 | for (i = 0; (mask & 1) == 0; ++i) | |
990 | mask >>= 1; | |
991 | return i; | |
992 | } | |
993 | ||
994 | /* Implement big shift right. */ | |
995 | static bfd_vma | |
996 | BSR (val, amount) | |
997 | bfd_vma val; | |
998 | int amount; | |
999 | { | |
1000 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1001 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1002 | return val >> amount; | |
1003 | } | |
1004 | \f | |
1005 | /* For communication between sparc_ip and get_expression. */ | |
1006 | static char *expr_end; | |
1007 | ||
252b5132 RH |
1008 | /* Values for `special_case'. |
1009 | Instructions that require wierd handling because they're longer than | |
1010 | 4 bytes. */ | |
1011 | #define SPECIAL_CASE_NONE 0 | |
1012 | #define SPECIAL_CASE_SET 1 | |
1013 | #define SPECIAL_CASE_SETSW 2 | |
1014 | #define SPECIAL_CASE_SETX 3 | |
1015 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1016 | #define SPECIAL_CASE_FDIV 4 | |
1017 | ||
1018 | /* Bit masks of various insns. */ | |
1019 | #define NOP_INSN 0x01000000 | |
1020 | #define OR_INSN 0x80100000 | |
63fab58c | 1021 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1022 | #define FMOVS_INSN 0x81A00020 |
1023 | #define SETHI_INSN 0x01000000 | |
1024 | #define SLLX_INSN 0x81281000 | |
1025 | #define SRA_INSN 0x81380000 | |
1026 | ||
1027 | /* The last instruction to be assembled. */ | |
1028 | static const struct sparc_opcode *last_insn; | |
1029 | /* The assembled opcode of `last_insn'. */ | |
1030 | static unsigned long last_opcode; | |
1031 | \f | |
a22b281c | 1032 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1033 | |
a22b281c RH |
1034 | static void |
1035 | synthetize_setuw (insn) | |
1036 | const struct sparc_opcode *insn; | |
1037 | { | |
1038 | int need_hi22_p = 0; | |
1039 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1040 | ||
1041 | if (the_insn.exp.X_op == O_constant) | |
1042 | { | |
1043 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1044 | { | |
e0c6ed95 | 1045 | if (sizeof (offsetT) > 4 |
a22b281c | 1046 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1047 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1048 | as_warn (_("set: number not in 0..4294967295 range")); |
1049 | } | |
1050 | else | |
1051 | { | |
e0c6ed95 | 1052 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1053 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1054 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1055 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1056 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1057 | } |
1058 | } | |
1059 | ||
1060 | /* See if operand is absolute and small; skip sethi if so. */ | |
1061 | if (the_insn.exp.X_op != O_constant | |
1062 | || the_insn.exp.X_add_number >= (1 << 12) | |
1063 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1064 | { | |
1065 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1066 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1067 | & (the_insn.exp.X_op == O_constant |
1068 | ? 0x3fffff : 0))); | |
a22b281c | 1069 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1070 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1071 | output_insn (insn, &the_insn); |
1072 | need_hi22_p = 1; | |
1073 | } | |
1074 | ||
1075 | /* See if operand has no low-order bits; skip OR if so. */ | |
1076 | if (the_insn.exp.X_op != O_constant | |
1077 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1078 | || ! need_hi22_p) | |
1079 | { | |
1080 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1081 | | RD (rd) | IMMED | |
1082 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1083 | & (the_insn.exp.X_op != O_constant |
1084 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1085 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1086 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1087 | output_insn (insn, &the_insn); |
1088 | } | |
1089 | } | |
e0c6ed95 | 1090 | |
a22b281c | 1091 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1092 | |
a22b281c RH |
1093 | static void |
1094 | synthetize_setsw (insn) | |
1095 | const struct sparc_opcode *insn; | |
1096 | { | |
1097 | int low32, rd, opc; | |
1098 | ||
1099 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1100 | ||
1101 | if (the_insn.exp.X_op != O_constant) | |
1102 | { | |
1103 | synthetize_setuw (insn); | |
1104 | ||
1105 | /* Need to sign extend it. */ | |
1106 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1107 | the_insn.reloc = BFD_RELOC_NONE; | |
1108 | output_insn (insn, &the_insn); | |
1109 | return; | |
1110 | } | |
1111 | ||
e0c6ed95 | 1112 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1113 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1114 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1115 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1116 | ||
e0c6ed95 AM |
1117 | low32 = the_insn.exp.X_add_number; |
1118 | ||
a22b281c RH |
1119 | if (low32 >= 0) |
1120 | { | |
1121 | synthetize_setuw (insn); | |
1122 | return; | |
1123 | } | |
1124 | ||
1125 | opc = OR_INSN; | |
e0c6ed95 | 1126 | |
a22b281c RH |
1127 | the_insn.reloc = BFD_RELOC_NONE; |
1128 | /* See if operand is absolute and small; skip sethi if so. */ | |
1129 | if (low32 < -(1 << 12)) | |
1130 | { | |
1131 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1132 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1133 | output_insn (insn, &the_insn); | |
1134 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1135 | opc = RS1 (rd) | XOR_INSN; | |
1136 | } | |
1137 | ||
1138 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1139 | | (low32 & 0x1fff)); | |
1140 | output_insn (insn, &the_insn); | |
1141 | } | |
1142 | ||
1143 | /* Handle the setsw synthetic instruction. */ | |
e0c6ed95 | 1144 | |
a22b281c RH |
1145 | static void |
1146 | synthetize_setx (insn) | |
1147 | const struct sparc_opcode *insn; | |
1148 | { | |
1149 | int upper32, lower32; | |
1150 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1151 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1152 | int upper_dstreg; | |
1153 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1154 | int need_xor10_p = 0; | |
e0c6ed95 | 1155 | |
6c1b24e4 | 1156 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1157 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1158 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1159 | #undef SIGNEXT32 | |
1160 | ||
1161 | upper_dstreg = tmpreg; | |
1162 | /* The tmp reg should not be the dst reg. */ | |
1163 | if (tmpreg == dstreg) | |
1164 | as_warn (_("setx: temporary register same as destination register")); | |
1165 | ||
1166 | /* ??? Obviously there are other optimizations we can do | |
1167 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1168 | doing some of these. Later. If you do change things, try to | |
1169 | change all of this to be table driven as well. */ | |
1170 | /* What to output depends on the number if it's constant. | |
1171 | Compute that first, then output what we've decided upon. */ | |
1172 | if (the_insn.exp.X_op != O_constant) | |
1173 | { | |
1174 | if (sparc_arch_size == 32) | |
1175 | { | |
1176 | /* When arch size is 32, we want setx to be equivalent | |
1177 | to setuw for anything but constants. */ | |
1178 | the_insn.exp.X_add_number &= 0xffffffff; | |
1179 | synthetize_setuw (insn); | |
1180 | return; | |
1181 | } | |
1182 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1183 | lower32 = 0; |
1184 | upper32 = 0; | |
a22b281c RH |
1185 | } |
1186 | else | |
1187 | { | |
1188 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1189 | Otherwise fixup_segment will complain about not being able to | |
1190 | write an 8 byte number in a 4 byte field. */ | |
1191 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1192 | |
a22b281c RH |
1193 | /* Only need hh22 if `or' insn can't handle constant. */ |
1194 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1195 | need_hh22_p = 1; | |
e0c6ed95 | 1196 | |
a22b281c RH |
1197 | /* Does bottom part (after sethi) have bits? */ |
1198 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1199 | /* No hh22, but does upper32 still have bits we can't set | |
1200 | from lower32? */ | |
1201 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1202 | need_hm10_p = 1; | |
e0c6ed95 | 1203 | |
a22b281c RH |
1204 | /* If the lower half is all zero, we build the upper half directly |
1205 | into the dst reg. */ | |
1206 | if (lower32 != 0 | |
1207 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1208 | || (! need_hh22_p && ! need_hm10_p)) | |
1209 | { | |
1210 | /* No need for sethi if `or' insn can handle constant. */ | |
1211 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1212 | /* Note that we can't use a negative constant in the `or' | |
1213 | insn unless the upper 32 bits are all ones. */ | |
1214 | || (lower32 < 0 && upper32 != -1) | |
1215 | || (lower32 >= 0 && upper32 == -1)) | |
1216 | need_hi22_p = 1; | |
e0c6ed95 | 1217 | |
a22b281c RH |
1218 | if (need_hi22_p && upper32 == -1) |
1219 | need_xor10_p = 1; | |
1220 | ||
1221 | /* Does bottom part (after sethi) have bits? */ | |
1222 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1223 | /* No sethi. */ | |
1224 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1225 | /* Need `or' if we didn't set anything else. */ | |
1226 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1227 | need_lo10_p = 1; | |
1228 | } | |
1229 | else | |
1230 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1231 | upper_dstreg = dstreg; | |
1232 | } | |
e0c6ed95 | 1233 | |
a22b281c RH |
1234 | if (!upper_dstreg && dstreg) |
1235 | as_warn (_("setx: illegal temporary register g0")); | |
1236 | ||
1237 | if (need_hh22_p) | |
1238 | { | |
1239 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1240 | | ((upper32 >> 10) & 0x3fffff)); | |
1241 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1242 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1243 | output_insn (insn, &the_insn); | |
1244 | } | |
e0c6ed95 | 1245 | |
a22b281c RH |
1246 | if (need_hi22_p) |
1247 | { | |
1248 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1249 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1250 | >> 10) & 0x3fffff)); |
a22b281c RH |
1251 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1252 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1253 | output_insn (insn, &the_insn); | |
1254 | } | |
1255 | ||
1256 | if (need_hm10_p) | |
1257 | { | |
1258 | the_insn.opcode = (OR_INSN | |
1259 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1260 | | RD (upper_dstreg) | |
1261 | | IMMED | |
1262 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1263 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1264 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1265 | output_insn (insn, &the_insn); | |
1266 | } | |
e0c6ed95 | 1267 | |
a22b281c RH |
1268 | if (need_lo10_p) |
1269 | { | |
1270 | /* FIXME: One nice optimization to do here is to OR the low part | |
1271 | with the highpart if hi22 isn't needed and the low part is | |
1272 | positive. */ | |
1273 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1274 | | RD (dstreg) | |
1275 | | IMMED | |
1276 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1277 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1278 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1279 | output_insn (insn, &the_insn); | |
1280 | } | |
e0c6ed95 | 1281 | |
a22b281c RH |
1282 | /* If we needed to build the upper part, shift it into place. */ |
1283 | if (need_hh22_p || need_hm10_p) | |
1284 | { | |
1285 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1286 | | IMMED | 32); | |
1287 | the_insn.reloc = BFD_RELOC_NONE; | |
1288 | output_insn (insn, &the_insn); | |
1289 | } | |
e0c6ed95 | 1290 | |
a22b281c RH |
1291 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1292 | if (need_xor10_p) | |
1293 | { | |
1294 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1295 | | 0x1c00 | (lower32 & 0x3ff)); | |
1296 | the_insn.reloc = BFD_RELOC_NONE; | |
1297 | output_insn (insn, &the_insn); | |
1298 | } | |
1299 | ||
1300 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1301 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1302 | { | |
1303 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1304 | | RD (dstreg)); | |
1305 | the_insn.reloc = BFD_RELOC_NONE; | |
1306 | output_insn (insn, &the_insn); | |
1307 | } | |
1308 | } | |
1309 | \f | |
252b5132 RH |
1310 | /* Main entry point to assemble one instruction. */ |
1311 | ||
1312 | void | |
1313 | md_assemble (str) | |
1314 | char *str; | |
1315 | { | |
1316 | const struct sparc_opcode *insn; | |
a22b281c | 1317 | int special_case; |
252b5132 RH |
1318 | |
1319 | know (str); | |
a22b281c | 1320 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1321 | if (insn == NULL) |
1322 | return; | |
252b5132 RH |
1323 | |
1324 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1325 | unless the delay slot has been annulled. */ | |
b0825cc2 | 1326 | if (last_insn != NULL |
252b5132 RH |
1327 | && (insn->flags & F_FBR) != 0 |
1328 | && (last_insn->flags & F_DELAYED) != 0 | |
1329 | /* ??? This test isn't completely accurate. We assume anything with | |
1330 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1331 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1332 | || (last_opcode & ANNUL) == 0)) | |
1333 | as_warn (_("FP branch in delay slot")); | |
1334 | ||
1335 | /* SPARC before v9 requires a nop instruction between a floating | |
1336 | point instruction and a floating point branch. We insert one | |
1337 | automatically, with a warning. */ | |
1338 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1339 | && last_insn != NULL |
1340 | && (insn->flags & F_FBR) != 0 | |
1341 | && (last_insn->flags & F_FLOAT) != 0) | |
1342 | { | |
1343 | struct sparc_it nop_insn; | |
1344 | ||
1345 | nop_insn.opcode = NOP_INSN; | |
1346 | nop_insn.reloc = BFD_RELOC_NONE; | |
1347 | output_insn (insn, &nop_insn); | |
1348 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1349 | } | |
1350 | ||
a22b281c RH |
1351 | switch (special_case) |
1352 | { | |
1353 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1354 | /* Normal insn. */ |
a22b281c RH |
1355 | output_insn (insn, &the_insn); |
1356 | break; | |
252b5132 | 1357 | |
a22b281c RH |
1358 | case SPECIAL_CASE_SETSW: |
1359 | synthetize_setsw (insn); | |
1360 | break; | |
e0c6ed95 | 1361 | |
a22b281c RH |
1362 | case SPECIAL_CASE_SET: |
1363 | synthetize_setuw (insn); | |
1364 | break; | |
252b5132 | 1365 | |
a22b281c RH |
1366 | case SPECIAL_CASE_SETX: |
1367 | synthetize_setx (insn); | |
1368 | break; | |
e0c6ed95 | 1369 | |
a22b281c RH |
1370 | case SPECIAL_CASE_FDIV: |
1371 | { | |
1372 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1373 | |
a22b281c | 1374 | output_insn (insn, &the_insn); |
e0c6ed95 | 1375 | |
a22b281c RH |
1376 | /* According to information leaked from Sun, the "fdiv" instructions |
1377 | on early SPARC machines would produce incorrect results sometimes. | |
1378 | The workaround is to add an fmovs of the destination register to | |
1379 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1380 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
a22b281c RH |
1381 | assert (the_insn.reloc == BFD_RELOC_NONE); |
1382 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); | |
1383 | output_insn (insn, &the_insn); | |
1384 | return; | |
1385 | } | |
e0c6ed95 | 1386 | |
a22b281c RH |
1387 | default: |
1388 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1389 | } |
1390 | } | |
1391 | ||
1392 | /* Subroutine of md_assemble to do the actual parsing. */ | |
1393 | ||
a22b281c | 1394 | static int |
252b5132 RH |
1395 | sparc_ip (str, pinsn) |
1396 | char *str; | |
1397 | const struct sparc_opcode **pinsn; | |
1398 | { | |
1399 | char *error_message = ""; | |
1400 | char *s; | |
1401 | const char *args; | |
1402 | char c; | |
1403 | const struct sparc_opcode *insn; | |
1404 | char *argsStart; | |
1405 | unsigned long opcode; | |
1406 | unsigned int mask = 0; | |
1407 | int match = 0; | |
1408 | int comma = 0; | |
1409 | int v9_arg_p; | |
a22b281c | 1410 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1411 | |
1412 | s = str; | |
3882b010 | 1413 | if (ISLOWER (*s)) |
252b5132 RH |
1414 | { |
1415 | do | |
1416 | ++s; | |
3882b010 | 1417 | while (ISLOWER (*s) || ISDIGIT (*s)); |
252b5132 RH |
1418 | } |
1419 | ||
1420 | switch (*s) | |
1421 | { | |
1422 | case '\0': | |
1423 | break; | |
1424 | ||
1425 | case ',': | |
1426 | comma = 1; | |
e0c6ed95 | 1427 | /* Fall through. */ |
252b5132 RH |
1428 | |
1429 | case ' ': | |
1430 | *s++ = '\0'; | |
1431 | break; | |
1432 | ||
1433 | default: | |
b0825cc2 DM |
1434 | as_bad (_("Unknown opcode: `%s'"), str); |
1435 | *pinsn = NULL; | |
1436 | return special_case; | |
252b5132 RH |
1437 | } |
1438 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1439 | *pinsn = insn; | |
1440 | if (insn == NULL) | |
1441 | { | |
1442 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1443 | return special_case; |
252b5132 RH |
1444 | } |
1445 | if (comma) | |
1446 | { | |
1447 | *--s = ','; | |
1448 | } | |
1449 | ||
1450 | argsStart = s; | |
1451 | for (;;) | |
1452 | { | |
1453 | opcode = insn->match; | |
1454 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1455 | the_insn.reloc = BFD_RELOC_NONE; | |
1456 | v9_arg_p = 0; | |
1457 | ||
e0c6ed95 AM |
1458 | /* Build the opcode, checking as we go to make sure that the |
1459 | operands match. */ | |
252b5132 RH |
1460 | for (args = insn->args;; ++args) |
1461 | { | |
1462 | switch (*args) | |
1463 | { | |
1464 | case 'K': | |
1465 | { | |
1466 | int kmask = 0; | |
1467 | ||
1468 | /* Parse a series of masks. */ | |
1469 | if (*s == '#') | |
1470 | { | |
1471 | while (*s == '#') | |
1472 | { | |
1473 | int mask; | |
1474 | ||
1475 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
1476 | &mask)) | |
1477 | { | |
1478 | error_message = _(": invalid membar mask name"); | |
1479 | goto error; | |
1480 | } | |
1481 | kmask |= mask; | |
47926f60 KH |
1482 | while (*s == ' ') |
1483 | ++s; | |
252b5132 RH |
1484 | if (*s == '|' || *s == '+') |
1485 | ++s; | |
47926f60 KH |
1486 | while (*s == ' ') |
1487 | ++s; | |
252b5132 RH |
1488 | } |
1489 | } | |
1490 | else | |
1491 | { | |
1492 | if (! parse_const_expr_arg (&s, &kmask)) | |
1493 | { | |
1494 | error_message = _(": invalid membar mask expression"); | |
1495 | goto error; | |
1496 | } | |
1497 | if (kmask < 0 || kmask > 127) | |
1498 | { | |
1499 | error_message = _(": invalid membar mask number"); | |
1500 | goto error; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | opcode |= MEMBAR (kmask); | |
1505 | continue; | |
1506 | } | |
1507 | ||
19f7b010 JJ |
1508 | case '3': |
1509 | { | |
1510 | int smask = 0; | |
1511 | ||
1512 | if (! parse_const_expr_arg (&s, &smask)) | |
1513 | { | |
1514 | error_message = _(": invalid siam mode expression"); | |
1515 | goto error; | |
1516 | } | |
1517 | if (smask < 0 || smask > 7) | |
1518 | { | |
1519 | error_message = _(": invalid siam mode number"); | |
1520 | goto error; | |
1521 | } | |
1522 | opcode |= smask; | |
1523 | continue; | |
1524 | } | |
1525 | ||
252b5132 RH |
1526 | case '*': |
1527 | { | |
1528 | int fcn = 0; | |
1529 | ||
1530 | /* Parse a prefetch function. */ | |
1531 | if (*s == '#') | |
1532 | { | |
1533 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1534 | { | |
1535 | error_message = _(": invalid prefetch function name"); | |
1536 | goto error; | |
1537 | } | |
1538 | } | |
1539 | else | |
1540 | { | |
1541 | if (! parse_const_expr_arg (&s, &fcn)) | |
1542 | { | |
1543 | error_message = _(": invalid prefetch function expression"); | |
1544 | goto error; | |
1545 | } | |
1546 | if (fcn < 0 || fcn > 31) | |
1547 | { | |
1548 | error_message = _(": invalid prefetch function number"); | |
1549 | goto error; | |
1550 | } | |
1551 | } | |
1552 | opcode |= RD (fcn); | |
1553 | continue; | |
1554 | } | |
1555 | ||
1556 | case '!': | |
1557 | case '?': | |
1558 | /* Parse a sparc64 privileged register. */ | |
1559 | if (*s == '%') | |
1560 | { | |
1561 | struct priv_reg_entry *p = priv_reg_table; | |
e0c6ed95 | 1562 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1563 | |
1564 | s += 1; | |
1565 | while (p->name[0] > s[0]) | |
1566 | p++; | |
1567 | while (p->name[0] == s[0]) | |
1568 | { | |
1569 | len = strlen (p->name); | |
1570 | if (strncmp (p->name, s, len) == 0) | |
1571 | break; | |
1572 | p++; | |
1573 | } | |
1574 | if (p->name[0] != s[0]) | |
1575 | { | |
1576 | error_message = _(": unrecognizable privileged register"); | |
1577 | goto error; | |
1578 | } | |
1579 | if (*args == '?') | |
1580 | opcode |= (p->regnum << 14); | |
1581 | else | |
1582 | opcode |= (p->regnum << 25); | |
1583 | s += len; | |
1584 | continue; | |
1585 | } | |
1586 | else | |
1587 | { | |
1588 | error_message = _(": unrecognizable privileged register"); | |
1589 | goto error; | |
1590 | } | |
1591 | ||
10156f83 DM |
1592 | case '$': |
1593 | case '%': | |
1594 | /* Parse a sparc64 hyperprivileged register. */ | |
1595 | if (*s == '%') | |
1596 | { | |
1597 | struct priv_reg_entry *p = hpriv_reg_table; | |
1598 | unsigned int len = 9999999; /* Init to make gcc happy. */ | |
1599 | ||
1600 | s += 1; | |
1601 | while (p->name[0] > s[0]) | |
1602 | p++; | |
1603 | while (p->name[0] == s[0]) | |
1604 | { | |
1605 | len = strlen (p->name); | |
1606 | if (strncmp (p->name, s, len) == 0) | |
1607 | break; | |
1608 | p++; | |
1609 | } | |
1610 | if (p->name[0] != s[0]) | |
1611 | { | |
1612 | error_message = _(": unrecognizable hyperprivileged register"); | |
1613 | goto error; | |
1614 | } | |
1615 | if (*args == '$') | |
1616 | opcode |= (p->regnum << 14); | |
1617 | else | |
1618 | opcode |= (p->regnum << 25); | |
1619 | s += len; | |
1620 | continue; | |
1621 | } | |
1622 | else | |
1623 | { | |
1624 | error_message = _(": unrecognizable hyperprivileged register"); | |
1625 | goto error; | |
1626 | } | |
1627 | ||
252b5132 RH |
1628 | case '_': |
1629 | case '/': | |
19f7b010 | 1630 | /* Parse a v9a/v9b ancillary state register. */ |
252b5132 RH |
1631 | if (*s == '%') |
1632 | { | |
1633 | struct priv_reg_entry *p = v9a_asr_table; | |
e0c6ed95 | 1634 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1635 | |
1636 | s += 1; | |
1637 | while (p->name[0] > s[0]) | |
1638 | p++; | |
1639 | while (p->name[0] == s[0]) | |
1640 | { | |
1641 | len = strlen (p->name); | |
1642 | if (strncmp (p->name, s, len) == 0) | |
1643 | break; | |
1644 | p++; | |
1645 | } | |
1646 | if (p->name[0] != s[0]) | |
1647 | { | |
19f7b010 | 1648 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1649 | goto error; |
1650 | } | |
1651 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1652 | { | |
1653 | error_message = _(": rd on write only ancillary state register"); | |
1654 | goto error; | |
e0c6ed95 | 1655 | } |
19f7b010 JJ |
1656 | if (p->regnum >= 24 |
1657 | && (insn->architecture | |
1658 | & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) | |
1659 | { | |
1660 | /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ | |
1661 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1662 | goto error; | |
1663 | } | |
252b5132 RH |
1664 | if (*args == '/') |
1665 | opcode |= (p->regnum << 14); | |
1666 | else | |
1667 | opcode |= (p->regnum << 25); | |
1668 | s += len; | |
1669 | continue; | |
1670 | } | |
1671 | else | |
1672 | { | |
19f7b010 | 1673 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1674 | goto error; |
1675 | } | |
1676 | ||
1677 | case 'M': | |
1678 | case 'm': | |
1679 | if (strncmp (s, "%asr", 4) == 0) | |
1680 | { | |
1681 | s += 4; | |
1682 | ||
3882b010 | 1683 | if (ISDIGIT (*s)) |
252b5132 RH |
1684 | { |
1685 | long num = 0; | |
1686 | ||
3882b010 | 1687 | while (ISDIGIT (*s)) |
252b5132 RH |
1688 | { |
1689 | num = num * 10 + *s - '0'; | |
1690 | ++s; | |
1691 | } | |
1692 | ||
1693 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1694 | { | |
1695 | if (num < 16 || 31 < num) | |
1696 | { | |
1697 | error_message = _(": asr number must be between 16 and 31"); | |
1698 | goto error; | |
1699 | } | |
1700 | } | |
1701 | else | |
1702 | { | |
1703 | if (num < 0 || 31 < num) | |
1704 | { | |
1705 | error_message = _(": asr number must be between 0 and 31"); | |
1706 | goto error; | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1711 | continue; | |
1712 | } | |
1713 | else | |
1714 | { | |
1715 | error_message = _(": expecting %asrN"); | |
1716 | goto error; | |
1717 | } | |
e0c6ed95 | 1718 | } /* if %asr */ |
252b5132 RH |
1719 | break; |
1720 | ||
1721 | case 'I': | |
1722 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1723 | goto immediate; | |
1724 | ||
1725 | case 'j': | |
1726 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1727 | goto immediate; | |
1728 | ||
1729 | case 'X': | |
1730 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1731 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1732 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1733 | else | |
1734 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1735 | /* These fields are unsigned, but for upward compatibility, | |
1736 | allow negative values as well. */ | |
1737 | goto immediate; | |
1738 | ||
1739 | case 'Y': | |
1740 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1741 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1742 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1743 | else | |
1744 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1745 | /* These fields are unsigned, but for upward compatibility, | |
1746 | allow negative values as well. */ | |
1747 | goto immediate; | |
1748 | ||
1749 | case 'k': | |
1750 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1751 | the_insn.pcrel = 1; | |
1752 | goto immediate; | |
1753 | ||
1754 | case 'G': | |
1755 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1756 | the_insn.pcrel = 1; | |
1757 | goto immediate; | |
1758 | ||
1759 | case 'N': | |
1760 | if (*s == 'p' && s[1] == 'n') | |
1761 | { | |
1762 | s += 2; | |
1763 | continue; | |
1764 | } | |
1765 | break; | |
1766 | ||
1767 | case 'T': | |
1768 | if (*s == 'p' && s[1] == 't') | |
1769 | { | |
1770 | s += 2; | |
1771 | continue; | |
1772 | } | |
1773 | break; | |
1774 | ||
1775 | case 'z': | |
1776 | if (*s == ' ') | |
1777 | { | |
1778 | ++s; | |
1779 | } | |
1780 | if (strncmp (s, "%icc", 4) == 0) | |
1781 | { | |
1782 | s += 4; | |
1783 | continue; | |
1784 | } | |
1785 | break; | |
1786 | ||
1787 | case 'Z': | |
1788 | if (*s == ' ') | |
1789 | { | |
1790 | ++s; | |
1791 | } | |
1792 | if (strncmp (s, "%xcc", 4) == 0) | |
1793 | { | |
1794 | s += 4; | |
1795 | continue; | |
1796 | } | |
1797 | break; | |
1798 | ||
1799 | case '6': | |
1800 | if (*s == ' ') | |
1801 | { | |
1802 | ++s; | |
1803 | } | |
1804 | if (strncmp (s, "%fcc0", 5) == 0) | |
1805 | { | |
1806 | s += 5; | |
1807 | continue; | |
1808 | } | |
1809 | break; | |
1810 | ||
1811 | case '7': | |
1812 | if (*s == ' ') | |
1813 | { | |
1814 | ++s; | |
1815 | } | |
1816 | if (strncmp (s, "%fcc1", 5) == 0) | |
1817 | { | |
1818 | s += 5; | |
1819 | continue; | |
1820 | } | |
1821 | break; | |
1822 | ||
1823 | case '8': | |
1824 | if (*s == ' ') | |
1825 | { | |
1826 | ++s; | |
1827 | } | |
1828 | if (strncmp (s, "%fcc2", 5) == 0) | |
1829 | { | |
1830 | s += 5; | |
1831 | continue; | |
1832 | } | |
1833 | break; | |
1834 | ||
1835 | case '9': | |
1836 | if (*s == ' ') | |
1837 | { | |
1838 | ++s; | |
1839 | } | |
1840 | if (strncmp (s, "%fcc3", 5) == 0) | |
1841 | { | |
1842 | s += 5; | |
1843 | continue; | |
1844 | } | |
1845 | break; | |
1846 | ||
1847 | case 'P': | |
1848 | if (strncmp (s, "%pc", 3) == 0) | |
1849 | { | |
1850 | s += 3; | |
1851 | continue; | |
1852 | } | |
1853 | break; | |
1854 | ||
1855 | case 'W': | |
1856 | if (strncmp (s, "%tick", 5) == 0) | |
1857 | { | |
1858 | s += 5; | |
1859 | continue; | |
1860 | } | |
1861 | break; | |
1862 | ||
e0c6ed95 | 1863 | case '\0': /* End of args. */ |
b9734f35 | 1864 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 1865 | { |
739f7f82 | 1866 | static const struct ops |
dfeb0666 | 1867 | { |
b9734f35 JJ |
1868 | /* The name as it appears in assembler. */ |
1869 | char *name; | |
1870 | /* strlen (name), precomputed for speed */ | |
1871 | int len; | |
1872 | /* The reloc this pseudo-op translates to. */ | |
1873 | int reloc; | |
739f7f82 DM |
1874 | /* 1 if tls call. */ |
1875 | int tls_call; | |
dfeb0666 | 1876 | } |
739f7f82 | 1877 | ops[] = |
dfeb0666 | 1878 | { |
b9734f35 JJ |
1879 | { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, |
1880 | { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, | |
1881 | { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, | |
1882 | { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, | |
1883 | { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, | |
1884 | { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, | |
1885 | { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, | |
dfeb0666 | 1886 | { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, |
739f7f82 | 1887 | { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, |
dfeb0666 | 1888 | { NULL, 0, 0, 0 } |
b9734f35 | 1889 | }; |
739f7f82 | 1890 | const struct ops *o; |
b9734f35 JJ |
1891 | char *s1; |
1892 | int npar = 0; | |
1893 | ||
739f7f82 | 1894 | for (o = ops; o->name; o++) |
b9734f35 JJ |
1895 | if (strncmp (s + 2, o->name, o->len) == 0) |
1896 | break; | |
1897 | if (o->name == NULL) | |
1898 | break; | |
1899 | ||
1900 | if (s[o->len + 2] != '(') | |
1901 | { | |
1902 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
1903 | return special_case; | |
1904 | } | |
1905 | ||
739f7f82 | 1906 | if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) |
b9734f35 JJ |
1907 | { |
1908 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
1909 | o->name); | |
1910 | return special_case; | |
1911 | } | |
1912 | ||
739f7f82 | 1913 | if (o->tls_call |
b9734f35 JJ |
1914 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
1915 | || the_insn.exp.X_add_number != 0 | |
1916 | || the_insn.exp.X_add_symbol | |
1917 | != symbol_find_or_make ("__tls_get_addr"))) | |
1918 | { | |
1919 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
1920 | o->name); | |
1921 | return special_case; | |
1922 | } | |
1923 | ||
1924 | the_insn.reloc = o->reloc; | |
1925 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); | |
1926 | s += o->len + 3; | |
1927 | ||
1928 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
1929 | if (*s1 == '(') | |
1930 | npar++; | |
1931 | else if (*s1 == ')') | |
1932 | { | |
1933 | if (!npar) | |
1934 | break; | |
1935 | npar--; | |
1936 | } | |
1937 | ||
1938 | if (*s1 != ')') | |
1939 | { | |
1940 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
1941 | return special_case; | |
1942 | } | |
1943 | ||
1944 | *s1 = '\0'; | |
1945 | (void) get_expression (s); | |
1946 | *s1 = ')'; | |
1947 | s = s1 + 1; | |
252b5132 | 1948 | } |
b9734f35 JJ |
1949 | if (*s == '\0') |
1950 | match = 1; | |
252b5132 RH |
1951 | break; |
1952 | ||
1953 | case '+': | |
1954 | if (*s == '+') | |
1955 | { | |
1956 | ++s; | |
1957 | continue; | |
1958 | } | |
1959 | if (*s == '-') | |
1960 | { | |
1961 | continue; | |
1962 | } | |
1963 | break; | |
1964 | ||
e0c6ed95 | 1965 | case '[': /* These must match exactly. */ |
252b5132 RH |
1966 | case ']': |
1967 | case ',': | |
1968 | case ' ': | |
1969 | if (*s++ == *args) | |
1970 | continue; | |
1971 | break; | |
1972 | ||
e0c6ed95 | 1973 | case '#': /* Must be at least one digit. */ |
3882b010 | 1974 | if (ISDIGIT (*s++)) |
252b5132 | 1975 | { |
3882b010 | 1976 | while (ISDIGIT (*s)) |
252b5132 RH |
1977 | { |
1978 | ++s; | |
1979 | } | |
1980 | continue; | |
1981 | } | |
1982 | break; | |
1983 | ||
e0c6ed95 | 1984 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
1985 | if (strncmp (s, "%csr", 4) == 0) |
1986 | { | |
1987 | s += 4; | |
1988 | continue; | |
1989 | } | |
1990 | break; | |
1991 | ||
e0c6ed95 | 1992 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
1993 | case 'c': |
1994 | case 'D': | |
3882b010 | 1995 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
1996 | { |
1997 | mask = *s++; | |
3882b010 | 1998 | if (ISDIGIT (*s)) |
252b5132 RH |
1999 | { |
2000 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2001 | if (mask >= 32) | |
2002 | { | |
2003 | break; | |
2004 | } | |
2005 | } | |
2006 | else | |
2007 | { | |
2008 | mask -= '0'; | |
2009 | } | |
2010 | switch (*args) | |
2011 | { | |
2012 | ||
2013 | case 'b': | |
2014 | opcode |= mask << 14; | |
2015 | continue; | |
2016 | ||
2017 | case 'c': | |
2018 | opcode |= mask; | |
2019 | continue; | |
2020 | ||
2021 | case 'D': | |
2022 | opcode |= mask << 25; | |
2023 | continue; | |
2024 | } | |
2025 | } | |
2026 | break; | |
2027 | ||
2028 | case 'r': /* next operand must be a register */ | |
2029 | case 'O': | |
2030 | case '1': | |
2031 | case '2': | |
2032 | case 'd': | |
2033 | if (*s++ == '%') | |
2034 | { | |
2035 | switch (c = *s++) | |
2036 | { | |
2037 | ||
2038 | case 'f': /* frame pointer */ | |
2039 | if (*s++ == 'p') | |
2040 | { | |
2041 | mask = 0x1e; | |
2042 | break; | |
2043 | } | |
2044 | goto error; | |
2045 | ||
2046 | case 'g': /* global register */ | |
a22b281c RH |
2047 | c = *s++; |
2048 | if (isoctal (c)) | |
252b5132 RH |
2049 | { |
2050 | mask = c - '0'; | |
2051 | break; | |
2052 | } | |
2053 | goto error; | |
2054 | ||
2055 | case 'i': /* in register */ | |
a22b281c RH |
2056 | c = *s++; |
2057 | if (isoctal (c)) | |
252b5132 RH |
2058 | { |
2059 | mask = c - '0' + 24; | |
2060 | break; | |
2061 | } | |
2062 | goto error; | |
2063 | ||
2064 | case 'l': /* local register */ | |
a22b281c RH |
2065 | c = *s++; |
2066 | if (isoctal (c)) | |
252b5132 RH |
2067 | { |
2068 | mask = (c - '0' + 16); | |
2069 | break; | |
2070 | } | |
2071 | goto error; | |
2072 | ||
2073 | case 'o': /* out register */ | |
a22b281c RH |
2074 | c = *s++; |
2075 | if (isoctal (c)) | |
252b5132 RH |
2076 | { |
2077 | mask = (c - '0' + 8); | |
2078 | break; | |
2079 | } | |
2080 | goto error; | |
2081 | ||
2082 | case 's': /* stack pointer */ | |
2083 | if (*s++ == 'p') | |
2084 | { | |
2085 | mask = 0xe; | |
2086 | break; | |
2087 | } | |
2088 | goto error; | |
2089 | ||
2090 | case 'r': /* any register */ | |
3882b010 | 2091 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2092 | { |
2093 | goto error; | |
2094 | } | |
2095 | /* FALLTHROUGH */ | |
2096 | case '0': | |
2097 | case '1': | |
2098 | case '2': | |
2099 | case '3': | |
2100 | case '4': | |
2101 | case '5': | |
2102 | case '6': | |
2103 | case '7': | |
2104 | case '8': | |
2105 | case '9': | |
3882b010 | 2106 | if (ISDIGIT (*s)) |
252b5132 RH |
2107 | { |
2108 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2109 | { | |
2110 | goto error; | |
2111 | } | |
2112 | } | |
2113 | else | |
2114 | { | |
2115 | c -= '0'; | |
2116 | } | |
2117 | mask = c; | |
2118 | break; | |
2119 | ||
2120 | default: | |
2121 | goto error; | |
2122 | } | |
2123 | ||
6d8809aa | 2124 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2125 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2126 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2127 | |
252b5132 RH |
2128 | /* Got the register, now figure out where |
2129 | it goes in the opcode. */ | |
2130 | switch (*args) | |
2131 | { | |
2132 | case '1': | |
2133 | opcode |= mask << 14; | |
2134 | continue; | |
2135 | ||
2136 | case '2': | |
2137 | opcode |= mask; | |
2138 | continue; | |
2139 | ||
2140 | case 'd': | |
2141 | opcode |= mask << 25; | |
2142 | continue; | |
2143 | ||
2144 | case 'r': | |
2145 | opcode |= (mask << 25) | (mask << 14); | |
2146 | continue; | |
2147 | ||
2148 | case 'O': | |
2149 | opcode |= (mask << 25) | (mask << 0); | |
2150 | continue; | |
2151 | } | |
2152 | } | |
2153 | break; | |
2154 | ||
2155 | case 'e': /* next operand is a floating point register */ | |
2156 | case 'v': | |
2157 | case 'V': | |
2158 | ||
2159 | case 'f': | |
2160 | case 'B': | |
2161 | case 'R': | |
2162 | ||
2163 | case 'g': | |
2164 | case 'H': | |
2165 | case 'J': | |
2166 | { | |
2167 | char format; | |
2168 | ||
2169 | if (*s++ == '%' | |
2170 | && ((format = *s) == 'f') | |
3882b010 | 2171 | && ISDIGIT (*++s)) |
252b5132 | 2172 | { |
3882b010 | 2173 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2174 | { |
2175 | mask = 10 * mask + (*s - '0'); | |
2176 | } /* read the number */ | |
2177 | ||
2178 | if ((*args == 'v' | |
2179 | || *args == 'B' | |
2180 | || *args == 'H') | |
2181 | && (mask & 1)) | |
2182 | { | |
2183 | break; | |
2184 | } /* register must be even numbered */ | |
2185 | ||
2186 | if ((*args == 'V' | |
2187 | || *args == 'R' | |
2188 | || *args == 'J') | |
2189 | && (mask & 3)) | |
2190 | { | |
2191 | break; | |
2192 | } /* register must be multiple of 4 */ | |
2193 | ||
2194 | if (mask >= 64) | |
2195 | { | |
2196 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2197 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2198 | else | |
2199 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2200 | goto error; | |
2201 | } /* on error */ | |
2202 | else if (mask >= 32) | |
2203 | { | |
2204 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2205 | { | |
26664553 JJ |
2206 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2207 | { | |
2208 | error_message | |
2209 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2210 | goto error; | |
2211 | } | |
252b5132 RH |
2212 | v9_arg_p = 1; |
2213 | mask -= 31; /* wrap high bit */ | |
2214 | } | |
2215 | else | |
2216 | { | |
2217 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2218 | goto error; | |
2219 | } | |
2220 | } | |
2221 | } | |
2222 | else | |
2223 | { | |
2224 | break; | |
ab3e48dc | 2225 | } /* if not an 'f' register. */ |
252b5132 RH |
2226 | |
2227 | switch (*args) | |
2228 | { | |
2229 | case 'v': | |
2230 | case 'V': | |
2231 | case 'e': | |
2232 | opcode |= RS1 (mask); | |
2233 | continue; | |
2234 | ||
252b5132 RH |
2235 | case 'f': |
2236 | case 'B': | |
2237 | case 'R': | |
2238 | opcode |= RS2 (mask); | |
2239 | continue; | |
2240 | ||
2241 | case 'g': | |
2242 | case 'H': | |
2243 | case 'J': | |
2244 | opcode |= RD (mask); | |
2245 | continue; | |
ab3e48dc | 2246 | } /* Pack it in. */ |
252b5132 RH |
2247 | |
2248 | know (0); | |
2249 | break; | |
ab3e48dc | 2250 | } /* float arg */ |
252b5132 RH |
2251 | |
2252 | case 'F': | |
2253 | if (strncmp (s, "%fsr", 4) == 0) | |
2254 | { | |
2255 | s += 4; | |
2256 | continue; | |
2257 | } | |
2258 | break; | |
2259 | ||
ab3e48dc KH |
2260 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2261 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2262 | goto immediate; |
2263 | ||
ab3e48dc | 2264 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2265 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2266 | the_insn.pcrel = 1; | |
2267 | goto immediate; | |
2268 | ||
ab3e48dc | 2269 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2270 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2271 | the_insn.pcrel = 1; | |
2272 | goto immediate; | |
2273 | ||
63fab58c | 2274 | case 'h': |
ab3e48dc | 2275 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2276 | the_insn.reloc = BFD_RELOC_SPARC22; |
2277 | goto immediate; | |
2278 | ||
ab3e48dc | 2279 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2280 | the_insn.reloc = BFD_RELOC_SPARC13; |
2281 | ||
2282 | /* fallthrough */ | |
2283 | ||
2284 | immediate: | |
2285 | if (*s == ' ') | |
2286 | s++; | |
2287 | ||
cf9a1301 RH |
2288 | { |
2289 | char *s1; | |
2290 | char *op_arg = NULL; | |
30eb9c17 | 2291 | static expressionS op_exp; |
cf9a1301 RH |
2292 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2293 | ||
2294 | /* Check for %hi, etc. */ | |
2295 | if (*s == '%') | |
2296 | { | |
2297 | static const struct ops { | |
2298 | /* The name as it appears in assembler. */ | |
2299 | char *name; | |
2300 | /* strlen (name), precomputed for speed */ | |
2301 | int len; | |
2302 | /* The reloc this pseudo-op translates to. */ | |
2303 | int reloc; | |
2304 | /* Non-zero if for v9 only. */ | |
2305 | int v9_p; | |
2306 | /* Non-zero if can be used in pc-relative contexts. */ | |
2307 | int pcrel_p;/*FIXME:wip*/ | |
2308 | } ops[] = { | |
2309 | /* hix/lox must appear before hi/lo so %hix won't be | |
2310 | mistaken for %hi. */ | |
2311 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2312 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2313 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2314 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
14865d76 DM |
2315 | { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, |
2316 | { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, | |
cf9a1301 RH |
2317 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, |
2318 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2319 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2320 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, | |
2321 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2322 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2323 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2324 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
b9734f35 JJ |
2325 | { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, |
2326 | { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, | |
2327 | { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, | |
2328 | { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, | |
2329 | { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, | |
2330 | 0 }, | |
2331 | { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, | |
2332 | 0 }, | |
2333 | { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, | |
2334 | { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, | |
2335 | { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, | |
2336 | { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, | |
739f7f82 DM |
2337 | { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, |
2338 | 0, 0 }, | |
2339 | { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, | |
2340 | 0, 0 }, | |
c2158c24 | 2341 | { NULL, 0, 0, 0, 0 } |
cf9a1301 RH |
2342 | }; |
2343 | const struct ops *o; | |
e0c6ed95 | 2344 | |
cf9a1301 RH |
2345 | for (o = ops; o->name; o++) |
2346 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2347 | break; | |
2348 | if (o->name == NULL) | |
252b5132 | 2349 | break; |
e0c6ed95 | 2350 | |
cf9a1301 RH |
2351 | if (s[o->len + 1] != '(') |
2352 | { | |
2353 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2354 | return special_case; |
cf9a1301 | 2355 | } |
252b5132 | 2356 | |
cf9a1301 RH |
2357 | op_arg = o->name; |
2358 | the_insn.reloc = o->reloc; | |
2359 | s += o->len + 2; | |
2360 | v9_arg_p = o->v9_p; | |
2361 | } | |
2362 | ||
2363 | /* Note that if the get_expression() fails, we will still | |
2364 | have created U entries in the symbol table for the | |
2365 | 'symbols' in the input string. Try not to create U | |
2366 | symbols for registers, etc. */ | |
252b5132 | 2367 | |
252b5132 RH |
2368 | /* This stuff checks to see if the expression ends in |
2369 | +%reg. If it does, it removes the register from | |
2370 | the expression, and re-sets 's' to point to the | |
2371 | right place. */ | |
2372 | ||
cf9a1301 RH |
2373 | if (op_arg) |
2374 | { | |
2375 | int npar = 0; | |
2376 | ||
2377 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2378 | if (*s1 == '(') | |
2379 | npar++; | |
2380 | else if (*s1 == ')') | |
2381 | { | |
2382 | if (!npar) | |
2383 | break; | |
2384 | npar--; | |
2385 | } | |
2386 | ||
2387 | if (*s1 != ')') | |
2388 | { | |
2389 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2390 | return special_case; |
cf9a1301 | 2391 | } |
e0c6ed95 | 2392 | |
cf9a1301 RH |
2393 | *s1 = '\0'; |
2394 | (void) get_expression (s); | |
2395 | *s1 = ')'; | |
2396 | s = s1 + 1; | |
2397 | if (*s == ',' || *s == ']' || !*s) | |
2398 | continue; | |
2399 | if (*s != '+' && *s != '-') | |
2400 | { | |
2401 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2402 | return special_case; |
cf9a1301 RH |
2403 | } |
2404 | *s1 = '0'; | |
2405 | s = s1; | |
2406 | op_exp = the_insn.exp; | |
e0c6ed95 | 2407 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2408 | } |
252b5132 | 2409 | |
e0c6ed95 AM |
2410 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2411 | ; | |
252b5132 | 2412 | |
3882b010 | 2413 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2414 | { |
2415 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 RH |
2416 | s1 -= 3; |
2417 | else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') | |
2418 | s1 -= 4; | |
2419 | else | |
2420 | s1 = NULL; | |
2421 | if (s1) | |
252b5132 | 2422 | { |
252b5132 | 2423 | *s1 = '\0'; |
1eb7027c RH |
2424 | if (op_arg && s1 == s + 1) |
2425 | the_insn.exp.X_op = O_absent; | |
2426 | else | |
2427 | (void) get_expression (s); | |
252b5132 | 2428 | *s1 = '+'; |
cf9a1301 RH |
2429 | if (op_arg) |
2430 | *s = ')'; | |
252b5132 | 2431 | s = s1; |
252b5132 | 2432 | } |
cf9a1301 RH |
2433 | } |
2434 | else | |
2435 | s1 = NULL; | |
2436 | ||
2437 | if (!s1) | |
2438 | { | |
2439 | (void) get_expression (s); | |
2440 | if (op_arg) | |
2441 | *s = ')'; | |
2442 | s = expr_end; | |
2443 | } | |
2444 | ||
2445 | if (op_arg) | |
2446 | { | |
2447 | the_insn.exp2 = the_insn.exp; | |
2448 | the_insn.exp = op_exp; | |
2449 | if (the_insn.exp2.X_op == O_absent) | |
2450 | the_insn.exp2.X_op = O_illegal; | |
2451 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2452 | { |
cf9a1301 RH |
2453 | the_insn.exp = the_insn.exp2; |
2454 | the_insn.exp2.X_op = O_illegal; | |
2455 | } | |
2456 | else if (the_insn.exp.X_op == O_constant) | |
2457 | { | |
2458 | valueT val = the_insn.exp.X_add_number; | |
2459 | switch (the_insn.reloc) | |
2460 | { | |
1b50c718 ILT |
2461 | default: |
2462 | break; | |
2463 | ||
cf9a1301 RH |
2464 | case BFD_RELOC_SPARC_HH22: |
2465 | val = BSR (val, 32); | |
e0c6ed95 | 2466 | /* Fall through. */ |
cf9a1301 RH |
2467 | |
2468 | case BFD_RELOC_SPARC_LM22: | |
2469 | case BFD_RELOC_HI22: | |
2470 | val = (val >> 10) & 0x3fffff; | |
2471 | break; | |
2472 | ||
2473 | case BFD_RELOC_SPARC_HM10: | |
2474 | val = BSR (val, 32); | |
e0c6ed95 | 2475 | /* Fall through. */ |
cf9a1301 RH |
2476 | |
2477 | case BFD_RELOC_LO10: | |
2478 | val &= 0x3ff; | |
2479 | break; | |
2480 | ||
2481 | case BFD_RELOC_SPARC_H44: | |
2482 | val >>= 22; | |
2483 | val &= 0x3fffff; | |
2484 | break; | |
2485 | ||
2486 | case BFD_RELOC_SPARC_M44: | |
2487 | val >>= 12; | |
2488 | val &= 0x3ff; | |
2489 | break; | |
2490 | ||
2491 | case BFD_RELOC_SPARC_L44: | |
2492 | val &= 0xfff; | |
2493 | break; | |
2494 | ||
2495 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2496 | val = ~val; |
cf9a1301 RH |
2497 | val = (val >> 10) & 0x3fffff; |
2498 | break; | |
2499 | ||
2500 | case BFD_RELOC_SPARC_LOX10: | |
2501 | val = (val & 0x3ff) | 0x1c00; | |
2502 | break; | |
2503 | } | |
2504 | the_insn.exp = the_insn.exp2; | |
2505 | the_insn.exp.X_add_number += val; | |
2506 | the_insn.exp2.X_op = O_illegal; | |
2507 | the_insn.reloc = old_reloc; | |
2508 | } | |
2509 | else if (the_insn.exp2.X_op != O_constant) | |
2510 | { | |
2511 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2512 | return special_case; |
cf9a1301 RH |
2513 | } |
2514 | else | |
2515 | { | |
dabe3bbc | 2516 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2517 | || the_insn.reloc != BFD_RELOC_LO10 |
2518 | || sparc_arch_size != 64 | |
2519 | || sparc_pic_code) | |
2520 | { | |
2521 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2522 | return special_case; |
cf9a1301 RH |
2523 | } |
2524 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2525 | } |
2526 | } | |
2527 | } | |
252b5132 RH |
2528 | /* Check for constants that don't require emitting a reloc. */ |
2529 | if (the_insn.exp.X_op == O_constant | |
2530 | && the_insn.exp.X_add_symbol == 0 | |
2531 | && the_insn.exp.X_op_symbol == 0) | |
2532 | { | |
2533 | /* For pc-relative call instructions, we reject | |
2534 | constants to get better code. */ | |
2535 | if (the_insn.pcrel | |
2536 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2537 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2538 | { | |
2539 | error_message = _(": PC-relative operand can't be a constant"); | |
2540 | goto error; | |
2541 | } | |
2542 | ||
b9734f35 JJ |
2543 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2544 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2545 | { | |
2546 | error_message = _(": TLS operand can't be a constant"); | |
2547 | goto error; | |
2548 | } | |
2549 | ||
55cf6793 | 2550 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2551 | and bfd_install_relocation. |
2552 | ??? It would be preferable to install the constants | |
2553 | into the insn here and save having to create a fixS | |
2554 | for each one. There already exists code to handle | |
55cf6793 | 2555 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2556 | bfd_install_relocation) so duplicating all that code |
2557 | here isn't right. */ | |
2558 | } | |
2559 | ||
2560 | continue; | |
2561 | ||
2562 | case 'a': | |
2563 | if (*s++ == 'a') | |
2564 | { | |
2565 | opcode |= ANNUL; | |
2566 | continue; | |
2567 | } | |
2568 | break; | |
2569 | ||
2570 | case 'A': | |
2571 | { | |
2572 | int asi = 0; | |
2573 | ||
2574 | /* Parse an asi. */ | |
2575 | if (*s == '#') | |
2576 | { | |
2577 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2578 | { | |
2579 | error_message = _(": invalid ASI name"); | |
2580 | goto error; | |
2581 | } | |
2582 | } | |
2583 | else | |
2584 | { | |
2585 | if (! parse_const_expr_arg (&s, &asi)) | |
2586 | { | |
2587 | error_message = _(": invalid ASI expression"); | |
2588 | goto error; | |
2589 | } | |
2590 | if (asi < 0 || asi > 255) | |
2591 | { | |
2592 | error_message = _(": invalid ASI number"); | |
2593 | goto error; | |
2594 | } | |
2595 | } | |
2596 | opcode |= ASI (asi); | |
2597 | continue; | |
e0c6ed95 | 2598 | } /* Alternate space. */ |
252b5132 RH |
2599 | |
2600 | case 'p': | |
2601 | if (strncmp (s, "%psr", 4) == 0) | |
2602 | { | |
2603 | s += 4; | |
2604 | continue; | |
2605 | } | |
2606 | break; | |
2607 | ||
e0c6ed95 | 2608 | case 'q': /* Floating point queue. */ |
252b5132 RH |
2609 | if (strncmp (s, "%fq", 3) == 0) |
2610 | { | |
2611 | s += 3; | |
2612 | continue; | |
2613 | } | |
2614 | break; | |
2615 | ||
e0c6ed95 | 2616 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
2617 | if (strncmp (s, "%cq", 3) == 0) |
2618 | { | |
2619 | s += 3; | |
2620 | continue; | |
2621 | } | |
2622 | break; | |
2623 | ||
2624 | case 'S': | |
2625 | if (strcmp (str, "set") == 0 | |
2626 | || strcmp (str, "setuw") == 0) | |
2627 | { | |
2628 | special_case = SPECIAL_CASE_SET; | |
2629 | continue; | |
2630 | } | |
2631 | else if (strcmp (str, "setsw") == 0) | |
2632 | { | |
2633 | special_case = SPECIAL_CASE_SETSW; | |
2634 | continue; | |
2635 | } | |
2636 | else if (strcmp (str, "setx") == 0) | |
2637 | { | |
2638 | special_case = SPECIAL_CASE_SETX; | |
2639 | continue; | |
2640 | } | |
2641 | else if (strncmp (str, "fdiv", 4) == 0) | |
2642 | { | |
2643 | special_case = SPECIAL_CASE_FDIV; | |
2644 | continue; | |
2645 | } | |
2646 | break; | |
2647 | ||
2648 | case 'o': | |
2649 | if (strncmp (s, "%asi", 4) != 0) | |
2650 | break; | |
2651 | s += 4; | |
2652 | continue; | |
2653 | ||
2654 | case 's': | |
2655 | if (strncmp (s, "%fprs", 5) != 0) | |
2656 | break; | |
2657 | s += 5; | |
2658 | continue; | |
2659 | ||
2660 | case 'E': | |
2661 | if (strncmp (s, "%ccr", 4) != 0) | |
2662 | break; | |
2663 | s += 4; | |
2664 | continue; | |
2665 | ||
2666 | case 't': | |
2667 | if (strncmp (s, "%tbr", 4) != 0) | |
2668 | break; | |
2669 | s += 4; | |
2670 | continue; | |
2671 | ||
2672 | case 'w': | |
2673 | if (strncmp (s, "%wim", 4) != 0) | |
2674 | break; | |
2675 | s += 4; | |
2676 | continue; | |
2677 | ||
2678 | case 'x': | |
2679 | { | |
2680 | char *push = input_line_pointer; | |
2681 | expressionS e; | |
2682 | ||
2683 | input_line_pointer = s; | |
2684 | expression (&e); | |
2685 | if (e.X_op == O_constant) | |
2686 | { | |
2687 | int n = e.X_add_number; | |
2688 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2689 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2690 | else | |
2691 | opcode |= e.X_add_number << 5; | |
2692 | } | |
2693 | else | |
2694 | as_bad (_("non-immediate OPF operand, ignored")); | |
2695 | s = input_line_pointer; | |
2696 | input_line_pointer = push; | |
2697 | continue; | |
2698 | } | |
2699 | ||
2700 | case 'y': | |
2701 | if (strncmp (s, "%y", 2) != 0) | |
2702 | break; | |
2703 | s += 2; | |
2704 | continue; | |
2705 | ||
2706 | case 'u': | |
2707 | case 'U': | |
2708 | { | |
2709 | /* Parse a sparclet cpreg. */ | |
2710 | int cpreg; | |
2711 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2712 | { | |
2713 | error_message = _(": invalid cpreg name"); | |
2714 | goto error; | |
2715 | } | |
2716 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2717 | continue; | |
2718 | } | |
2719 | ||
2720 | default: | |
2721 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 2722 | } /* switch on arg code. */ |
252b5132 RH |
2723 | |
2724 | /* Break out of for() loop. */ | |
2725 | break; | |
e0c6ed95 | 2726 | } /* For each arg that we expect. */ |
252b5132 RH |
2727 | |
2728 | error: | |
2729 | if (match == 0) | |
2730 | { | |
e0c6ed95 | 2731 | /* Args don't match. */ |
252b5132 RH |
2732 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
2733 | && (insn->name == insn[1].name | |
2734 | || !strcmp (insn->name, insn[1].name))) | |
2735 | { | |
2736 | ++insn; | |
2737 | s = argsStart; | |
2738 | continue; | |
2739 | } | |
2740 | else | |
2741 | { | |
2742 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 2743 | return special_case; |
252b5132 RH |
2744 | } |
2745 | } | |
2746 | else | |
2747 | { | |
e0c6ed95 | 2748 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 RH |
2749 | int needed_arch_mask = insn->architecture; |
2750 | ||
2751 | if (v9_arg_p) | |
2752 | { | |
19f7b010 JJ |
2753 | needed_arch_mask &= |
2754 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
2755 | if (! needed_arch_mask) | |
2756 | needed_arch_mask = | |
2757 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
2758 | } |
2759 | ||
e0c6ed95 AM |
2760 | if (needed_arch_mask |
2761 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2762 | /* OK. */ | |
2763 | ; | |
252b5132 | 2764 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
2765 | else if (needed_arch_mask |
2766 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
2767 | { |
2768 | enum sparc_opcode_arch_val needed_architecture = | |
2769 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2770 | & needed_arch_mask); | |
2771 | ||
2772 | assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); | |
2773 | if (warn_on_bump | |
2774 | && needed_architecture > warn_after_architecture) | |
2775 | { | |
2776 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
2777 | sparc_opcode_archs[current_architecture].name, | |
2778 | sparc_opcode_archs[needed_architecture].name, | |
2779 | str); | |
2780 | warn_after_architecture = needed_architecture; | |
2781 | } | |
2782 | current_architecture = needed_architecture; | |
2783 | } | |
2784 | /* Conflict. */ | |
2785 | /* ??? This seems to be a bit fragile. What if the next entry in | |
2786 | the opcode table is the one we want and it is supported? | |
2787 | It is possible to arrange the table today so that this can't | |
2788 | happen but what about tomorrow? */ | |
2789 | else | |
2790 | { | |
e0c6ed95 | 2791 | int arch, printed_one_p = 0; |
252b5132 RH |
2792 | char *p; |
2793 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2794 | ||
2795 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 2796 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
2797 | p = required_archs; |
2798 | arch = sparc_ffs (needed_arch_mask); | |
2799 | while ((1 << arch) <= needed_arch_mask) | |
2800 | { | |
2801 | if ((1 << arch) & needed_arch_mask) | |
2802 | { | |
2803 | if (printed_one_p) | |
2804 | *p++ = '|'; | |
2805 | strcpy (p, sparc_opcode_archs[arch].name); | |
2806 | p += strlen (p); | |
2807 | printed_one_p = 1; | |
2808 | } | |
2809 | ++arch; | |
2810 | } | |
2811 | ||
2812 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
2813 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
2814 | required_archs, | |
2815 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 2816 | return special_case; |
252b5132 | 2817 | } |
e0c6ed95 | 2818 | } /* If no match. */ |
252b5132 RH |
2819 | |
2820 | break; | |
e0c6ed95 | 2821 | } /* Forever looking for a match. */ |
252b5132 RH |
2822 | |
2823 | the_insn.opcode = opcode; | |
a22b281c | 2824 | return special_case; |
252b5132 RH |
2825 | } |
2826 | ||
2827 | /* Parse an argument that can be expressed as a keyword. | |
2828 | (eg: #StoreStore or %ccfr). | |
2829 | The result is a boolean indicating success. | |
2830 | If successful, INPUT_POINTER is updated. */ | |
2831 | ||
2832 | static int | |
2833 | parse_keyword_arg (lookup_fn, input_pointerP, valueP) | |
2834 | int (*lookup_fn) PARAMS ((const char *)); | |
2835 | char **input_pointerP; | |
2836 | int *valueP; | |
2837 | { | |
2838 | int value; | |
2839 | char c, *p, *q; | |
2840 | ||
2841 | p = *input_pointerP; | |
2842 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 2843 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
2844 | ++q) |
2845 | continue; | |
2846 | c = *q; | |
2847 | *q = 0; | |
2848 | value = (*lookup_fn) (p); | |
2849 | *q = c; | |
2850 | if (value == -1) | |
2851 | return 0; | |
2852 | *valueP = value; | |
2853 | *input_pointerP = q; | |
2854 | return 1; | |
2855 | } | |
2856 | ||
2857 | /* Parse an argument that is a constant expression. | |
2858 | The result is a boolean indicating success. */ | |
2859 | ||
2860 | static int | |
2861 | parse_const_expr_arg (input_pointerP, valueP) | |
2862 | char **input_pointerP; | |
2863 | int *valueP; | |
2864 | { | |
2865 | char *save = input_line_pointer; | |
2866 | expressionS exp; | |
2867 | ||
2868 | input_line_pointer = *input_pointerP; | |
2869 | /* The next expression may be something other than a constant | |
2870 | (say if we're not processing the right variant of the insn). | |
2871 | Don't call expression unless we're sure it will succeed as it will | |
2872 | signal an error (which we want to defer until later). */ | |
2873 | /* FIXME: It might be better to define md_operand and have it recognize | |
2874 | things like %asi, etc. but continuing that route through to the end | |
2875 | is a lot of work. */ | |
2876 | if (*input_line_pointer == '%') | |
2877 | { | |
2878 | input_line_pointer = save; | |
2879 | return 0; | |
2880 | } | |
2881 | expression (&exp); | |
2882 | *input_pointerP = input_line_pointer; | |
2883 | input_line_pointer = save; | |
2884 | if (exp.X_op != O_constant) | |
2885 | return 0; | |
2886 | *valueP = exp.X_add_number; | |
2887 | return 1; | |
2888 | } | |
2889 | ||
2890 | /* Subroutine of sparc_ip to parse an expression. */ | |
2891 | ||
2892 | static int | |
2893 | get_expression (str) | |
2894 | char *str; | |
2895 | { | |
2896 | char *save_in; | |
2897 | segT seg; | |
2898 | ||
2899 | save_in = input_line_pointer; | |
2900 | input_line_pointer = str; | |
2901 | seg = expression (&the_insn.exp); | |
2902 | if (seg != absolute_section | |
2903 | && seg != text_section | |
2904 | && seg != data_section | |
2905 | && seg != bss_section | |
2906 | && seg != undefined_section) | |
2907 | { | |
2908 | the_insn.error = _("bad segment"); | |
2909 | expr_end = input_line_pointer; | |
2910 | input_line_pointer = save_in; | |
2911 | return 1; | |
2912 | } | |
2913 | expr_end = input_line_pointer; | |
2914 | input_line_pointer = save_in; | |
2915 | return 0; | |
2916 | } | |
2917 | ||
2918 | /* Subroutine of md_assemble to output one insn. */ | |
2919 | ||
2920 | static void | |
2921 | output_insn (insn, the_insn) | |
2922 | const struct sparc_opcode *insn; | |
2923 | struct sparc_it *the_insn; | |
2924 | { | |
2925 | char *toP = frag_more (4); | |
2926 | ||
e0c6ed95 | 2927 | /* Put out the opcode. */ |
252b5132 RH |
2928 | if (INSN_BIG_ENDIAN) |
2929 | number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); | |
2930 | else | |
2931 | number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); | |
2932 | ||
e0c6ed95 | 2933 | /* Put out the symbol-dependent stuff. */ |
252b5132 RH |
2934 | if (the_insn->reloc != BFD_RELOC_NONE) |
2935 | { | |
e0c6ed95 AM |
2936 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
2937 | (toP - frag_now->fr_literal), /* Where. */ | |
2938 | 4, /* Size. */ | |
252b5132 RH |
2939 | &the_insn->exp, |
2940 | the_insn->pcrel, | |
2941 | the_insn->reloc); | |
2942 | /* Turn off overflow checking in fixup_segment. We'll do our | |
55cf6793 | 2943 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
2944 | the insn size is 4 and fixup_segment will signal an overflow for |
2945 | large 8 byte quantities. */ | |
2946 | fixP->fx_no_overflow = 1; | |
dabe3bbc RH |
2947 | if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) |
2948 | fixP->tc_fix_data = the_insn->exp2.X_add_number; | |
252b5132 RH |
2949 | } |
2950 | ||
2951 | last_insn = insn; | |
2952 | last_opcode = the_insn->opcode; | |
732d96b6 JJ |
2953 | |
2954 | #ifdef OBJ_ELF | |
2955 | dwarf2_emit_insn (4); | |
2956 | #endif | |
252b5132 RH |
2957 | } |
2958 | \f | |
252b5132 | 2959 | char * |
499ac353 | 2960 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2961 | { |
499ac353 | 2962 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
2963 | } |
2964 | ||
2965 | /* Write a value out to the object file, using the appropriate | |
2966 | endianness. */ | |
2967 | ||
2968 | void | |
2969 | md_number_to_chars (buf, val, n) | |
2970 | char *buf; | |
2971 | valueT val; | |
2972 | int n; | |
2973 | { | |
2974 | if (target_big_endian) | |
2975 | number_to_chars_bigendian (buf, val, n); | |
2976 | else if (target_little_endian_data | |
2977 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
2978 | /* Output debug words, which are not in allocated sections, as big |
2979 | endian. */ | |
252b5132 RH |
2980 | number_to_chars_bigendian (buf, val, n); |
2981 | else if (target_little_endian_data || ! target_big_endian) | |
2982 | number_to_chars_littleendian (buf, val, n); | |
2983 | } | |
2984 | \f | |
2985 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 2986 | hold. */ |
252b5132 | 2987 | |
94f592af | 2988 | void |
55cf6793 | 2989 | md_apply_fix (fixP, valP, segment) |
252b5132 | 2990 | fixS *fixP; |
94f592af | 2991 | valueT *valP; |
a7982600 | 2992 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
2993 | { |
2994 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 2995 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
2996 | long insn; |
2997 | ||
252b5132 RH |
2998 | assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
2999 | ||
e0c6ed95 | 3000 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3001 | |
3002 | #ifdef OBJ_ELF | |
a161fe53 | 3003 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3004 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3005 | { |
3006 | switch (fixP->fx_r_type) | |
3007 | { | |
3008 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3009 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3010 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3011 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3012 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3013 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3014 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3015 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3016 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3017 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3018 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3019 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3020 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3021 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3022 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3023 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3024 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3025 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3026 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3027 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3028 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3029 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3030 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3031 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3032 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3033 | ||
3034 | default: | |
3035 | break; | |
3036 | } | |
3037 | ||
3038 | return; | |
3039 | } | |
252b5132 RH |
3040 | #endif |
3041 | ||
3042 | /* This is a hack. There should be a better way to | |
3043 | handle this. Probably in terms of howto fields, once | |
3044 | we can look at these fixups in terms of howtos. */ | |
3045 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3046 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3047 | ||
3048 | #ifdef OBJ_AOUT | |
3049 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3050 | generate a reloc, then we just want to let the reloc addend set | |
3051 | the value. We do not want to also stuff the addend into the | |
3052 | object file. Including the addend in the object file works when | |
3053 | doing a static link, because the linker will ignore the object | |
3054 | file contents. However, the dynamic linker does not ignore the | |
3055 | object file contents. */ | |
3056 | if (fixP->fx_addsy != NULL | |
3057 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3058 | val = 0; | |
3059 | ||
3060 | /* When generating PIC code, we do not want an addend for a reloc | |
3061 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3062 | value already included in val, and to also cancel out the | |
3063 | adjustment which bfd_install_relocation will create. */ | |
3064 | if (sparc_pic_code | |
3065 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3066 | && fixP->fx_addsy != NULL | |
3067 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3068 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3069 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3070 | ||
3071 | /* When generating PIC code, we need to fiddle to get | |
3072 | bfd_install_relocation to do the right thing for a PC relative | |
3073 | reloc against a local symbol which we are going to keep. */ | |
3074 | if (sparc_pic_code | |
3075 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3076 | && fixP->fx_addsy != NULL | |
3077 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3078 | || S_IS_WEAK (fixP->fx_addsy)) | |
3079 | && S_IS_DEFINED (fixP->fx_addsy) | |
3080 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3081 | { | |
3082 | val = 0; | |
3083 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3084 | } | |
3085 | #endif | |
3086 | ||
3087 | /* If this is a data relocation, just output VAL. */ | |
3088 | ||
0f2712ed NC |
3089 | if (fixP->fx_r_type == BFD_RELOC_16 |
3090 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3091 | { |
3092 | md_number_to_chars (buf, val, 2); | |
3093 | } | |
3094 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3095 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3096 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3097 | { | |
3098 | md_number_to_chars (buf, val, 4); | |
3099 | } | |
0f2712ed NC |
3100 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3101 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3102 | { |
3103 | md_number_to_chars (buf, val, 8); | |
3104 | } | |
e0c6ed95 | 3105 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3106 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3107 | { | |
3108 | fixP->fx_done = 0; | |
94f592af | 3109 | return; |
252b5132 RH |
3110 | } |
3111 | else | |
3112 | { | |
3113 | /* It's a relocation against an instruction. */ | |
3114 | ||
3115 | if (INSN_BIG_ENDIAN) | |
3116 | insn = bfd_getb32 ((unsigned char *) buf); | |
3117 | else | |
3118 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3119 | |
252b5132 RH |
3120 | switch (fixP->fx_r_type) |
3121 | { | |
3122 | case BFD_RELOC_32_PCREL_S2: | |
3123 | val = val >> 2; | |
3124 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3125 | being done! */ | |
3126 | if (! sparc_pic_code | |
3127 | || fixP->fx_addsy == NULL | |
49309057 | 3128 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3129 | ++val; |
6faf3d66 | 3130 | |
252b5132 | 3131 | insn |= val & 0x3fffffff; |
6faf3d66 | 3132 | |
e0c6ed95 | 3133 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3134 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3135 | { | |
3136 | #define G0 0 | |
3137 | #define O7 15 | |
3138 | #define XCC (2 << 20) | |
3139 | #define COND(x) (((x)&0xf)<<25) | |
3140 | #define CONDA COND(0x8) | |
3141 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3142 | #define INSN_BA (F2(0,2) | CONDA) | |
3143 | #define INSN_OR F3(2, 0x2, 0) | |
3144 | #define INSN_NOP F2(0,4) | |
3145 | ||
3146 | long delay; | |
3147 | ||
3148 | /* If the instruction is a call with either: | |
3149 | restore | |
3150 | arithmetic instruction with rd == %o7 | |
3151 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3152 | then we can optimize if the call destination is near | |
3153 | by changing the call into a branch always. */ | |
3154 | if (INSN_BIG_ENDIAN) | |
3155 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3156 | else | |
3157 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3158 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3159 | break; |
e0c6ed95 AM |
3160 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3161 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3162 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3163 | break; |
e0c6ed95 AM |
3164 | if ((delay & RS1 (~0)) == RS1 (O7) |
3165 | || ((delay & F3I (~0)) == 0 | |
3166 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3167 | break; |
3168 | /* Ensure the branch will fit into simm22. */ | |
3169 | if ((val & 0x3fe00000) | |
3170 | && (val & 0x3fe00000) != 0x3fe00000) | |
3171 | break; | |
3172 | /* Check if the arch is v9 and branch will fit | |
3173 | into simm19. */ | |
3174 | if (((val & 0x3c0000) == 0 | |
3175 | || (val & 0x3c0000) == 0x3c0000) | |
3176 | && (sparc_arch_size == 64 | |
3177 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3178 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3179 | insn = INSN_BPA | (val & 0x7ffff); |
3180 | else | |
e0c6ed95 | 3181 | /* ba */ |
6faf3d66 JJ |
3182 | insn = INSN_BA | (val & 0x3fffff); |
3183 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3184 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3185 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3186 | { |
3187 | long setter; | |
3188 | int reg; | |
3189 | ||
3190 | if (INSN_BIG_ENDIAN) | |
3191 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3192 | else | |
3193 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3194 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3195 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3196 | break; |
3197 | /* The sequence was | |
3198 | or %o7, %g0, %rN | |
3199 | call foo | |
3200 | or %rN, %g0, %o7 | |
3201 | ||
3202 | If call foo was replaced with ba, replace | |
3203 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3204 | reg = (delay & RS1 (~0)) >> 14; |
3205 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3206 | || reg == G0 || reg == O7) |
3207 | break; | |
3208 | ||
3209 | if (INSN_BIG_ENDIAN) | |
3210 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3211 | else | |
3212 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3213 | } | |
3214 | } | |
252b5132 RH |
3215 | break; |
3216 | ||
3217 | case BFD_RELOC_SPARC_11: | |
3218 | if (! in_signed_range (val, 0x7ff)) | |
3219 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3220 | _("relocation overflow")); | |
3221 | insn |= val & 0x7ff; | |
3222 | break; | |
3223 | ||
3224 | case BFD_RELOC_SPARC_10: | |
3225 | if (! in_signed_range (val, 0x3ff)) | |
3226 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3227 | _("relocation overflow")); | |
3228 | insn |= val & 0x3ff; | |
3229 | break; | |
3230 | ||
3231 | case BFD_RELOC_SPARC_7: | |
3232 | if (! in_bitfield_range (val, 0x7f)) | |
3233 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3234 | _("relocation overflow")); | |
3235 | insn |= val & 0x7f; | |
3236 | break; | |
3237 | ||
3238 | case BFD_RELOC_SPARC_6: | |
3239 | if (! in_bitfield_range (val, 0x3f)) | |
3240 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3241 | _("relocation overflow")); | |
3242 | insn |= val & 0x3f; | |
3243 | break; | |
3244 | ||
3245 | case BFD_RELOC_SPARC_5: | |
3246 | if (! in_bitfield_range (val, 0x1f)) | |
3247 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3248 | _("relocation overflow")); | |
3249 | insn |= val & 0x1f; | |
3250 | break; | |
3251 | ||
3252 | case BFD_RELOC_SPARC_WDISP16: | |
c699f087 JJ |
3253 | if ((val & 3) |
3254 | || val >= 0x1fffc | |
3255 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3256 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3257 | _("relocation overflow")); | |
3258 | /* FIXME: The +1 deserves a comment. */ | |
3259 | val = (val >> 2) + 1; | |
3260 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3261 | break; | |
3262 | ||
3263 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3264 | if ((val & 3) |
3265 | || val >= 0xffffc | |
3266 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3267 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3268 | _("relocation overflow")); | |
3269 | /* FIXME: The +1 deserves a comment. */ | |
3270 | val = (val >> 2) + 1; | |
3271 | insn |= val & 0x7ffff; | |
3272 | break; | |
3273 | ||
3274 | case BFD_RELOC_SPARC_HH22: | |
3275 | val = BSR (val, 32); | |
e0c6ed95 | 3276 | /* Fall through. */ |
252b5132 RH |
3277 | |
3278 | case BFD_RELOC_SPARC_LM22: | |
3279 | case BFD_RELOC_HI22: | |
3280 | if (!fixP->fx_addsy) | |
94f592af | 3281 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3282 | else |
94f592af NC |
3283 | /* FIXME: Need comment explaining why we do this. */ |
3284 | insn &= ~0xffff; | |
252b5132 RH |
3285 | break; |
3286 | ||
3287 | case BFD_RELOC_SPARC22: | |
3288 | if (val & ~0x003fffff) | |
3289 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3290 | _("relocation overflow")); | |
3291 | insn |= (val & 0x3fffff); | |
3292 | break; | |
3293 | ||
3294 | case BFD_RELOC_SPARC_HM10: | |
3295 | val = BSR (val, 32); | |
e0c6ed95 | 3296 | /* Fall through. */ |
252b5132 RH |
3297 | |
3298 | case BFD_RELOC_LO10: | |
3299 | if (!fixP->fx_addsy) | |
94f592af | 3300 | insn |= val & 0x3ff; |
252b5132 | 3301 | else |
94f592af NC |
3302 | /* FIXME: Need comment explaining why we do this. */ |
3303 | insn &= ~0xff; | |
252b5132 RH |
3304 | break; |
3305 | ||
dabe3bbc RH |
3306 | case BFD_RELOC_SPARC_OLO10: |
3307 | val &= 0x3ff; | |
3308 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3309 | /* Fall through. */ |
dabe3bbc | 3310 | |
252b5132 RH |
3311 | case BFD_RELOC_SPARC13: |
3312 | if (! in_signed_range (val, 0x1fff)) | |
3313 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3314 | _("relocation overflow")); | |
3315 | insn |= val & 0x1fff; | |
3316 | break; | |
3317 | ||
3318 | case BFD_RELOC_SPARC_WDISP22: | |
3319 | val = (val >> 2) + 1; | |
e0c6ed95 | 3320 | /* Fall through. */ |
252b5132 RH |
3321 | case BFD_RELOC_SPARC_BASE22: |
3322 | insn |= val & 0x3fffff; | |
3323 | break; | |
3324 | ||
3325 | case BFD_RELOC_SPARC_H44: | |
3326 | if (!fixP->fx_addsy) | |
3327 | { | |
3328 | bfd_vma tval = val; | |
3329 | tval >>= 22; | |
3330 | insn |= tval & 0x3fffff; | |
3331 | } | |
3332 | break; | |
3333 | ||
3334 | case BFD_RELOC_SPARC_M44: | |
3335 | if (!fixP->fx_addsy) | |
3336 | insn |= (val >> 12) & 0x3ff; | |
3337 | break; | |
3338 | ||
3339 | case BFD_RELOC_SPARC_L44: | |
3340 | if (!fixP->fx_addsy) | |
3341 | insn |= val & 0xfff; | |
3342 | break; | |
3343 | ||
3344 | case BFD_RELOC_SPARC_HIX22: | |
3345 | if (!fixP->fx_addsy) | |
3346 | { | |
ab3e48dc | 3347 | val ^= ~(offsetT) 0; |
252b5132 RH |
3348 | insn |= (val >> 10) & 0x3fffff; |
3349 | } | |
3350 | break; | |
3351 | ||
3352 | case BFD_RELOC_SPARC_LOX10: | |
3353 | if (!fixP->fx_addsy) | |
3354 | insn |= 0x1c00 | (val & 0x3ff); | |
3355 | break; | |
3356 | ||
3357 | case BFD_RELOC_NONE: | |
3358 | default: | |
3359 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3360 | _("bad or unhandled relocation type: 0x%02x"), | |
3361 | fixP->fx_r_type); | |
3362 | break; | |
3363 | } | |
3364 | ||
3365 | if (INSN_BIG_ENDIAN) | |
3366 | bfd_putb32 (insn, (unsigned char *) buf); | |
3367 | else | |
3368 | bfd_putl32 (insn, (unsigned char *) buf); | |
3369 | } | |
3370 | ||
3371 | /* Are we finished with this relocation now? */ | |
3372 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3373 | fixP->fx_done = 1; | |
252b5132 RH |
3374 | } |
3375 | ||
3376 | /* Translate internal representation of relocation info to BFD target | |
3377 | format. */ | |
e0c6ed95 | 3378 | |
dabe3bbc | 3379 | arelent ** |
252b5132 | 3380 | tc_gen_reloc (section, fixp) |
062cf837 | 3381 | asection *section; |
252b5132 RH |
3382 | fixS *fixp; |
3383 | { | |
dabe3bbc | 3384 | static arelent *relocs[3]; |
252b5132 RH |
3385 | arelent *reloc; |
3386 | bfd_reloc_code_real_type code; | |
3387 | ||
dabe3bbc RH |
3388 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3389 | relocs[1] = NULL; | |
252b5132 | 3390 | |
49309057 ILT |
3391 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3392 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3393 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3394 | ||
3395 | switch (fixp->fx_r_type) | |
3396 | { | |
3397 | case BFD_RELOC_16: | |
3398 | case BFD_RELOC_32: | |
3399 | case BFD_RELOC_HI22: | |
3400 | case BFD_RELOC_LO10: | |
3401 | case BFD_RELOC_32_PCREL_S2: | |
3402 | case BFD_RELOC_SPARC13: | |
63fab58c | 3403 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3404 | case BFD_RELOC_SPARC_PC22: |
3405 | case BFD_RELOC_SPARC_PC10: | |
252b5132 RH |
3406 | case BFD_RELOC_SPARC_BASE13: |
3407 | case BFD_RELOC_SPARC_WDISP16: | |
3408 | case BFD_RELOC_SPARC_WDISP19: | |
3409 | case BFD_RELOC_SPARC_WDISP22: | |
3410 | case BFD_RELOC_64: | |
3411 | case BFD_RELOC_SPARC_5: | |
3412 | case BFD_RELOC_SPARC_6: | |
3413 | case BFD_RELOC_SPARC_7: | |
3414 | case BFD_RELOC_SPARC_10: | |
3415 | case BFD_RELOC_SPARC_11: | |
3416 | case BFD_RELOC_SPARC_HH22: | |
3417 | case BFD_RELOC_SPARC_HM10: | |
3418 | case BFD_RELOC_SPARC_LM22: | |
3419 | case BFD_RELOC_SPARC_PC_HH22: | |
3420 | case BFD_RELOC_SPARC_PC_HM10: | |
3421 | case BFD_RELOC_SPARC_PC_LM22: | |
3422 | case BFD_RELOC_SPARC_H44: | |
3423 | case BFD_RELOC_SPARC_M44: | |
3424 | case BFD_RELOC_SPARC_L44: | |
3425 | case BFD_RELOC_SPARC_HIX22: | |
3426 | case BFD_RELOC_SPARC_LOX10: | |
3427 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3428 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3429 | case BFD_RELOC_SPARC_UA16: |
3430 | case BFD_RELOC_SPARC_UA32: | |
3431 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3432 | case BFD_RELOC_8_PCREL: |
3433 | case BFD_RELOC_16_PCREL: | |
3434 | case BFD_RELOC_32_PCREL: | |
3435 | case BFD_RELOC_64_PCREL: | |
3436 | case BFD_RELOC_SPARC_PLT32: | |
3437 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3438 | case BFD_RELOC_VTABLE_ENTRY: |
3439 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3440 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3441 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3442 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3443 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3444 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3445 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3446 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3447 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3448 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3449 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3450 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3451 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3452 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3453 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3454 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3455 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3456 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3457 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3458 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3459 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3460 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3461 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3462 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3463 | code = fixp->fx_r_type; |
3464 | break; | |
3465 | default: | |
3466 | abort (); | |
3467 | return NULL; | |
3468 | } | |
3469 | ||
3470 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3471 | /* If we are generating PIC code, we need to generate a different | |
3472 | set of relocs. */ | |
3473 | ||
3474 | #ifdef OBJ_ELF | |
3475 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3476 | #else | |
3477 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3478 | #endif |
3479 | #ifdef TE_VXWORKS | |
3480 | #define GOTT_BASE "__GOTT_BASE__" | |
3481 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3482 | #endif |
3483 | ||
153b546a ILT |
3484 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3485 | ||
252b5132 RH |
3486 | if (sparc_pic_code) |
3487 | { | |
3488 | switch (code) | |
3489 | { | |
3490 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3491 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3492 | code = BFD_RELOC_SPARC_WPLT30; |
3493 | break; | |
3494 | case BFD_RELOC_HI22: | |
910600e9 RS |
3495 | code = BFD_RELOC_SPARC_GOT22; |
3496 | if (fixp->fx_addsy != NULL) | |
3497 | { | |
3498 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3499 | code = BFD_RELOC_SPARC_PC22; | |
3500 | #ifdef TE_VXWORKS | |
3501 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3502 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3503 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3504 | #endif | |
3505 | } | |
252b5132 RH |
3506 | break; |
3507 | case BFD_RELOC_LO10: | |
910600e9 RS |
3508 | code = BFD_RELOC_SPARC_GOT10; |
3509 | if (fixp->fx_addsy != NULL) | |
3510 | { | |
3511 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3512 | code = BFD_RELOC_SPARC_PC10; | |
3513 | #ifdef TE_VXWORKS | |
3514 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3515 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3516 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3517 | #endif | |
3518 | } | |
252b5132 RH |
3519 | break; |
3520 | case BFD_RELOC_SPARC13: | |
3521 | code = BFD_RELOC_SPARC_GOT13; | |
3522 | break; | |
3523 | default: | |
3524 | break; | |
3525 | } | |
3526 | } | |
e0c6ed95 | 3527 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3528 | |
062cf837 EB |
3529 | /* Nothing is aligned in DWARF debugging sections. */ |
3530 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3531 | switch (code) | |
3532 | { | |
3533 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3534 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3535 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3536 | default: break; | |
3537 | } | |
3538 | ||
dabe3bbc RH |
3539 | if (code == BFD_RELOC_SPARC_OLO10) |
3540 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3541 | else | |
3542 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3543 | if (reloc->howto == 0) |
3544 | { | |
3545 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3546 | _("internal error: can't export reloc type %d (`%s')"), | |
3547 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3548 | xfree (reloc); |
3549 | relocs[0] = NULL; | |
3550 | return relocs; | |
252b5132 RH |
3551 | } |
3552 | ||
3553 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3554 | #ifdef OBJ_AOUT | |
3555 | ||
3556 | if (reloc->howto->pc_relative == 0 | |
3557 | || code == BFD_RELOC_SPARC_PC10 | |
3558 | || code == BFD_RELOC_SPARC_PC22) | |
3559 | reloc->addend = fixp->fx_addnumber; | |
3560 | else if (sparc_pic_code | |
3561 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3562 | && fixp->fx_addsy != NULL | |
3563 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3564 | || S_IS_WEAK (fixp->fx_addsy)) | |
3565 | && S_IS_DEFINED (fixp->fx_addsy) | |
3566 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3567 | reloc->addend = fixp->fx_addnumber; | |
3568 | else | |
3569 | reloc->addend = fixp->fx_offset - reloc->address; | |
3570 | ||
e0c6ed95 | 3571 | #else /* elf or coff */ |
252b5132 | 3572 | |
bd5e6e7e JJ |
3573 | if (code != BFD_RELOC_32_PCREL_S2 |
3574 | && code != BFD_RELOC_SPARC_WDISP22 | |
3575 | && code != BFD_RELOC_SPARC_WDISP16 | |
3576 | && code != BFD_RELOC_SPARC_WDISP19 | |
b9734f35 JJ |
3577 | && code != BFD_RELOC_SPARC_WPLT30 |
3578 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
3579 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 3580 | reloc->addend = fixp->fx_addnumber; |
49309057 | 3581 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3582 | reloc->addend = (section->vma |
3583 | + fixp->fx_addnumber | |
3584 | + md_pcrel_from (fixp)); | |
3585 | else | |
3586 | reloc->addend = fixp->fx_offset; | |
3587 | #endif | |
3588 | ||
dabe3bbc RH |
3589 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3590 | on the same location. */ | |
3591 | if (code == BFD_RELOC_SPARC_OLO10) | |
3592 | { | |
3593 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3594 | relocs[2] = NULL; | |
3595 | ||
3596 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
ab3e48dc KH |
3597 | *reloc->sym_ptr_ptr |
3598 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
3599 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3600 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3601 | reloc->addend = fixp->tc_fix_data; | |
3602 | } | |
3603 | ||
3604 | return relocs; | |
252b5132 RH |
3605 | } |
3606 | \f | |
e0c6ed95 | 3607 | /* We have no need to default values of symbols. */ |
252b5132 | 3608 | |
252b5132 RH |
3609 | symbolS * |
3610 | md_undefined_symbol (name) | |
c2158c24 | 3611 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
3612 | { |
3613 | return 0; | |
e0c6ed95 AM |
3614 | } |
3615 | ||
3616 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 3617 | |
252b5132 RH |
3618 | valueT |
3619 | md_section_align (segment, size) | |
c2158c24 | 3620 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
3621 | valueT size; |
3622 | { | |
3623 | #ifndef OBJ_ELF | |
3624 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3625 | the alignment anyways. */ | |
3626 | valueT align = ((valueT) 1 | |
3627 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3628 | valueT newsize; | |
e0c6ed95 AM |
3629 | |
3630 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
3631 | align--; |
3632 | newsize = (size + align) & ~align; | |
3633 | return newsize; | |
3634 | #else | |
3635 | return size; | |
3636 | #endif | |
3637 | } | |
3638 | ||
3639 | /* Exactly what point is a PC-relative offset relative TO? | |
3640 | On the sparc, they're relative to the address of the offset, plus | |
3641 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
3642 | (??? Is this right? FIXME-SOON) */ |
3643 | long | |
252b5132 RH |
3644 | md_pcrel_from (fixP) |
3645 | fixS *fixP; | |
3646 | { | |
3647 | long ret; | |
3648 | ||
3649 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3650 | if (! sparc_pic_code | |
3651 | || fixP->fx_addsy == NULL | |
49309057 | 3652 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3653 | ret += fixP->fx_size; |
3654 | return ret; | |
3655 | } | |
3656 | \f | |
3657 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3658 | of two. */ | |
3659 | ||
3660 | static int | |
f17c130b | 3661 | mylog2 (value) |
252b5132 RH |
3662 | int value; |
3663 | { | |
3664 | int shift; | |
3665 | ||
3666 | if (value <= 0) | |
3667 | return -1; | |
3668 | ||
3669 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3670 | ++shift; | |
3671 | ||
3672 | return (value == 1) ? shift : -1; | |
3673 | } | |
3674 | ||
e0c6ed95 | 3675 | /* Sort of like s_lcomm. */ |
252b5132 RH |
3676 | |
3677 | #ifndef OBJ_ELF | |
3678 | static int max_alignment = 15; | |
3679 | #endif | |
3680 | ||
3681 | static void | |
3682 | s_reserve (ignore) | |
c2158c24 | 3683 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3684 | { |
3685 | char *name; | |
3686 | char *p; | |
3687 | char c; | |
3688 | int align; | |
3689 | int size; | |
3690 | int temp; | |
3691 | symbolS *symbolP; | |
3692 | ||
3693 | name = input_line_pointer; | |
3694 | c = get_symbol_end (); | |
3695 | p = input_line_pointer; | |
3696 | *p = c; | |
3697 | SKIP_WHITESPACE (); | |
3698 | ||
3699 | if (*input_line_pointer != ',') | |
3700 | { | |
3701 | as_bad (_("Expected comma after name")); | |
3702 | ignore_rest_of_line (); | |
3703 | return; | |
3704 | } | |
3705 | ||
3706 | ++input_line_pointer; | |
3707 | ||
3708 | if ((size = get_absolute_expression ()) < 0) | |
3709 | { | |
3710 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3711 | ignore_rest_of_line (); | |
3712 | return; | |
e0c6ed95 | 3713 | } /* Bad length. */ |
252b5132 RH |
3714 | |
3715 | *p = 0; | |
3716 | symbolP = symbol_find_or_make (name); | |
3717 | *p = c; | |
3718 | ||
3719 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3720 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3721 | { | |
3722 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
3723 | return; | |
3724 | } | |
3725 | ||
3726 | if (input_line_pointer[2] == '.') | |
3727 | input_line_pointer += 7; | |
3728 | else | |
3729 | input_line_pointer += 6; | |
3730 | SKIP_WHITESPACE (); | |
3731 | ||
3732 | if (*input_line_pointer == ',') | |
3733 | { | |
3734 | ++input_line_pointer; | |
3735 | ||
3736 | SKIP_WHITESPACE (); | |
3737 | if (*input_line_pointer == '\n') | |
3738 | { | |
3739 | as_bad (_("missing alignment")); | |
3740 | ignore_rest_of_line (); | |
3741 | return; | |
3742 | } | |
3743 | ||
3744 | align = (int) get_absolute_expression (); | |
3745 | ||
3746 | #ifndef OBJ_ELF | |
3747 | if (align > max_alignment) | |
3748 | { | |
3749 | align = max_alignment; | |
3750 | as_warn (_("alignment too large; assuming %d"), align); | |
3751 | } | |
3752 | #endif | |
3753 | ||
3754 | if (align < 0) | |
3755 | { | |
3756 | as_bad (_("negative alignment")); | |
3757 | ignore_rest_of_line (); | |
3758 | return; | |
3759 | } | |
3760 | ||
3761 | if (align != 0) | |
3762 | { | |
f17c130b | 3763 | temp = mylog2 (align); |
252b5132 RH |
3764 | if (temp < 0) |
3765 | { | |
3766 | as_bad (_("alignment not a power of 2")); | |
3767 | ignore_rest_of_line (); | |
3768 | return; | |
3769 | } | |
3770 | ||
3771 | align = temp; | |
3772 | } | |
3773 | ||
3774 | record_alignment (bss_section, align); | |
3775 | } | |
3776 | else | |
3777 | align = 0; | |
3778 | ||
3779 | if (!S_IS_DEFINED (symbolP) | |
3780 | #ifdef OBJ_AOUT | |
3781 | && S_GET_OTHER (symbolP) == 0 | |
3782 | && S_GET_DESC (symbolP) == 0 | |
3783 | #endif | |
3784 | ) | |
3785 | { | |
3786 | if (! need_pass_2) | |
3787 | { | |
3788 | char *pfrag; | |
3789 | segT current_seg = now_seg; | |
3790 | subsegT current_subseg = now_subseg; | |
3791 | ||
e0c6ed95 AM |
3792 | /* Switch to bss. */ |
3793 | subseg_set (bss_section, 1); | |
252b5132 RH |
3794 | |
3795 | if (align) | |
e0c6ed95 AM |
3796 | /* Do alignment. */ |
3797 | frag_align (align, 0, 0); | |
252b5132 | 3798 | |
e0c6ed95 | 3799 | /* Detach from old frag. */ |
ab3e48dc | 3800 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 3801 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 3802 | |
49309057 | 3803 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
3804 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3805 | (offsetT) size, (char *) 0); | |
252b5132 RH |
3806 | *pfrag = 0; |
3807 | ||
3808 | S_SET_SEGMENT (symbolP, bss_section); | |
3809 | ||
3810 | subseg_set (current_seg, current_subseg); | |
3811 | ||
3812 | #ifdef OBJ_ELF | |
3813 | S_SET_SIZE (symbolP, size); | |
3814 | #endif | |
3815 | } | |
3816 | } | |
3817 | else | |
3818 | { | |
ab3e48dc KH |
3819 | as_warn ("Ignoring attempt to re-define symbol %s", |
3820 | S_GET_NAME (symbolP)); | |
e0c6ed95 | 3821 | } /* if not redefining. */ |
252b5132 RH |
3822 | |
3823 | demand_empty_rest_of_line (); | |
3824 | } | |
3825 | ||
3826 | static void | |
3827 | s_common (ignore) | |
c2158c24 | 3828 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3829 | { |
3830 | char *name; | |
3831 | char c; | |
3832 | char *p; | |
685736be | 3833 | offsetT temp, size; |
252b5132 RH |
3834 | symbolS *symbolP; |
3835 | ||
3836 | name = input_line_pointer; | |
3837 | c = get_symbol_end (); | |
e0c6ed95 | 3838 | /* Just after name is now '\0'. */ |
252b5132 RH |
3839 | p = input_line_pointer; |
3840 | *p = c; | |
3841 | SKIP_WHITESPACE (); | |
3842 | if (*input_line_pointer != ',') | |
3843 | { | |
3844 | as_bad (_("Expected comma after symbol-name")); | |
3845 | ignore_rest_of_line (); | |
3846 | return; | |
3847 | } | |
e0c6ed95 AM |
3848 | |
3849 | /* Skip ','. */ | |
3850 | input_line_pointer++; | |
3851 | ||
252b5132 RH |
3852 | if ((temp = get_absolute_expression ()) < 0) |
3853 | { | |
685736be NC |
3854 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
3855 | (unsigned long) temp); | |
252b5132 RH |
3856 | ignore_rest_of_line (); |
3857 | return; | |
3858 | } | |
3859 | size = temp; | |
3860 | *p = 0; | |
3861 | symbolP = symbol_find_or_make (name); | |
3862 | *p = c; | |
3863 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
3864 | { | |
3865 | as_bad (_("Ignoring attempt to re-define symbol")); | |
3866 | ignore_rest_of_line (); | |
3867 | return; | |
3868 | } | |
3869 | if (S_GET_VALUE (symbolP) != 0) | |
3870 | { | |
3871 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
3872 | { | |
364b6d8b JJ |
3873 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
3874 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
3875 | } |
3876 | } | |
3877 | else | |
3878 | { | |
3879 | #ifndef OBJ_ELF | |
3880 | S_SET_VALUE (symbolP, (valueT) size); | |
3881 | S_SET_EXTERNAL (symbolP); | |
3882 | #endif | |
3883 | } | |
7dcc9865 | 3884 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
3885 | if (*input_line_pointer != ',') |
3886 | { | |
3887 | as_bad (_("Expected comma after common length")); | |
3888 | ignore_rest_of_line (); | |
3889 | return; | |
3890 | } | |
3891 | input_line_pointer++; | |
3892 | SKIP_WHITESPACE (); | |
3893 | if (*input_line_pointer != '"') | |
3894 | { | |
3895 | temp = get_absolute_expression (); | |
3896 | ||
3897 | #ifndef OBJ_ELF | |
3898 | if (temp > max_alignment) | |
3899 | { | |
3900 | temp = max_alignment; | |
f17c130b | 3901 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
3902 | } |
3903 | #endif | |
3904 | ||
3905 | if (temp < 0) | |
3906 | { | |
3907 | as_bad (_("negative alignment")); | |
3908 | ignore_rest_of_line (); | |
3909 | return; | |
3910 | } | |
3911 | ||
3912 | #ifdef OBJ_ELF | |
49309057 | 3913 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
3914 | { |
3915 | segT old_sec; | |
3916 | int old_subsec; | |
3917 | char *p; | |
3918 | int align; | |
3919 | ||
3920 | old_sec = now_seg; | |
3921 | old_subsec = now_subseg; | |
3922 | ||
3923 | if (temp == 0) | |
3924 | align = 0; | |
3925 | else | |
f17c130b | 3926 | align = mylog2 (temp); |
252b5132 RH |
3927 | |
3928 | if (align < 0) | |
3929 | { | |
3930 | as_bad (_("alignment not a power of 2")); | |
3931 | ignore_rest_of_line (); | |
3932 | return; | |
3933 | } | |
3934 | ||
3935 | record_alignment (bss_section, align); | |
3936 | subseg_set (bss_section, 0); | |
3937 | if (align) | |
3938 | frag_align (align, 0, 0); | |
3939 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
3940 | symbol_get_frag (symbolP)->fr_symbol = 0; |
3941 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
3942 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3943 | (offsetT) size, (char *) 0); | |
3944 | *p = 0; | |
3945 | S_SET_SEGMENT (symbolP, bss_section); | |
3946 | S_CLEAR_EXTERNAL (symbolP); | |
3947 | S_SET_SIZE (symbolP, size); | |
3948 | subseg_set (old_sec, old_subsec); | |
3949 | } | |
3950 | else | |
e0c6ed95 | 3951 | #endif /* OBJ_ELF */ |
252b5132 RH |
3952 | { |
3953 | allocate_common: | |
3954 | S_SET_VALUE (symbolP, (valueT) size); | |
3955 | #ifdef OBJ_ELF | |
3956 | S_SET_ALIGN (symbolP, temp); | |
3957 | S_SET_SIZE (symbolP, size); | |
3958 | #endif | |
3959 | S_SET_EXTERNAL (symbolP); | |
3960 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
3961 | } | |
3962 | } | |
3963 | else | |
3964 | { | |
3965 | input_line_pointer++; | |
3966 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
3967 | if (*input_line_pointer == '.') | |
3968 | input_line_pointer++; | |
3969 | /* @@ Some say data, some say bss. */ | |
3970 | if (strncmp (input_line_pointer, "bss\"", 4) | |
3971 | && strncmp (input_line_pointer, "data\"", 5)) | |
3972 | { | |
3973 | while (*--input_line_pointer != '"') | |
3974 | ; | |
3975 | input_line_pointer--; | |
3976 | goto bad_common_segment; | |
3977 | } | |
3978 | while (*input_line_pointer++ != '"') | |
3979 | ; | |
3980 | goto allocate_common; | |
3981 | } | |
3982 | ||
49309057 | 3983 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
3984 | |
3985 | demand_empty_rest_of_line (); | |
3986 | return; | |
3987 | ||
3988 | { | |
3989 | bad_common_segment: | |
3990 | p = input_line_pointer; | |
3991 | while (*p && *p != '\n') | |
3992 | p++; | |
3993 | c = *p; | |
3994 | *p = '\0'; | |
3995 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
3996 | *p = c; | |
3997 | input_line_pointer = p; | |
3998 | ignore_rest_of_line (); | |
3999 | return; | |
4000 | } | |
4001 | } | |
4002 | ||
67c1ffbe | 4003 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4004 | invalid delay slot usage. */ |
4005 | ||
4006 | static void | |
4007 | s_empty (ignore) | |
c2158c24 | 4008 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4009 | { |
4010 | /* The easy way to implement is to just forget about the last | |
4011 | instruction. */ | |
4012 | last_insn = NULL; | |
4013 | } | |
4014 | ||
4015 | static void | |
4016 | s_seg (ignore) | |
c2158c24 | 4017 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4018 | { |
4019 | ||
4020 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4021 | { | |
4022 | input_line_pointer += 6; | |
4023 | s_text (0); | |
4024 | return; | |
4025 | } | |
4026 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4027 | { | |
4028 | input_line_pointer += 6; | |
4029 | s_data (0); | |
4030 | return; | |
4031 | } | |
4032 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4033 | { | |
4034 | input_line_pointer += 7; | |
4035 | s_data1 (); | |
4036 | return; | |
4037 | } | |
4038 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4039 | { | |
4040 | input_line_pointer += 5; | |
4041 | /* We only support 2 segments -- text and data -- for now, so | |
4042 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4043 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4044 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4045 | return; |
4046 | } | |
4047 | as_bad (_("Unknown segment type")); | |
4048 | demand_empty_rest_of_line (); | |
4049 | } | |
4050 | ||
4051 | static void | |
4052 | s_data1 () | |
4053 | { | |
4054 | subseg_set (data_section, 1); | |
4055 | demand_empty_rest_of_line (); | |
4056 | } | |
4057 | ||
4058 | static void | |
4059 | s_proc (ignore) | |
c2158c24 | 4060 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4061 | { |
4062 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4063 | { | |
4064 | ++input_line_pointer; | |
4065 | } | |
4066 | ++input_line_pointer; | |
4067 | } | |
4068 | ||
4069 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4070 | that the expression does not need to be aligned. */ |
252b5132 RH |
4071 | |
4072 | static int sparc_no_align_cons = 0; | |
4073 | ||
bd5e6e7e JJ |
4074 | /* This static variable is set by sparc_cons to emit requested types |
4075 | of relocations in cons_fix_new_sparc. */ | |
4076 | ||
4077 | static const char *sparc_cons_special_reloc; | |
4078 | ||
252b5132 RH |
4079 | /* This handles the unaligned space allocation pseudo-ops, such as |
4080 | .uaword. .uaword is just like .word, but the value does not need | |
4081 | to be aligned. */ | |
4082 | ||
4083 | static void | |
4084 | s_uacons (bytes) | |
4085 | int bytes; | |
4086 | { | |
4087 | /* Tell sparc_cons_align not to align this value. */ | |
4088 | sparc_no_align_cons = 1; | |
4089 | cons (bytes); | |
4ffadb11 | 4090 | sparc_no_align_cons = 0; |
252b5132 RH |
4091 | } |
4092 | ||
cf9a1301 RH |
4093 | /* This handles the native word allocation pseudo-op .nword. |
4094 | For sparc_arch_size 32 it is equivalent to .word, for | |
4095 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4096 | ||
4097 | static void | |
4098 | s_ncons (bytes) | |
c2158c24 | 4099 | int bytes ATTRIBUTE_UNUSED; |
cf9a1301 RH |
4100 | { |
4101 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4102 | } | |
4103 | ||
6d8809aa RH |
4104 | #ifdef OBJ_ELF |
4105 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4106 | global register. | |
4107 | The syntax is: | |
e0c6ed95 | 4108 | |
6d8809aa | 4109 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4110 | */ |
6d8809aa RH |
4111 | |
4112 | static void | |
4113 | s_register (ignore) | |
c2158c24 | 4114 | int ignore ATTRIBUTE_UNUSED; |
6d8809aa RH |
4115 | { |
4116 | char c; | |
4117 | int reg; | |
4118 | int flags; | |
4119 | const char *regname; | |
4120 | ||
4121 | if (input_line_pointer[0] != '%' | |
4122 | || input_line_pointer[1] != 'g' | |
4123 | || ((input_line_pointer[2] & ~1) != '2' | |
4124 | && (input_line_pointer[2] & ~1) != '6') | |
4125 | || input_line_pointer[3] != ',') | |
4126 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4127 | reg = input_line_pointer[2] - '0'; | |
4128 | input_line_pointer += 4; | |
4129 | ||
4130 | if (*input_line_pointer == '#') | |
4131 | { | |
4132 | ++input_line_pointer; | |
4133 | regname = input_line_pointer; | |
4134 | c = get_symbol_end (); | |
4135 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) | |
4136 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4137 | if (regname[0] == 'i') |
6d8809aa RH |
4138 | regname = NULL; |
4139 | else | |
4140 | regname = ""; | |
4141 | } | |
4142 | else | |
4143 | { | |
4144 | regname = input_line_pointer; | |
4145 | c = get_symbol_end (); | |
4146 | } | |
4147 | if (sparc_arch_size == 64) | |
4148 | { | |
e0c6ed95 | 4149 | if (globals[reg]) |
6d8809aa | 4150 | { |
e0c6ed95 AM |
4151 | if ((regname && globals[reg] != (symbolS *) 1 |
4152 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4153 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4154 | as_bad (_("redefinition of global register")); |
4155 | } | |
4156 | else | |
4157 | { | |
4158 | if (regname == NULL) | |
e0c6ed95 | 4159 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4160 | else |
4161 | { | |
4162 | if (*regname) | |
4163 | { | |
4164 | if (symbol_find (regname)) | |
4165 | as_bad (_("Register symbol %s already defined."), | |
4166 | regname); | |
4167 | } | |
e0c6ed95 AM |
4168 | globals[reg] = symbol_make (regname); |
4169 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4170 | if (! *regname) |
4171 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4172 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4173 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4174 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4175 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4176 | S_SET_ALIGN (globals[reg], reg); | |
4177 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4178 | /* Although we actually want undefined_section here, |
4179 | we have to use absolute_section, because otherwise | |
4180 | generic as code will make it a COM section. | |
4181 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4182 | S_SET_SEGMENT (globals[reg], absolute_section); |
4183 | S_SET_OTHER (globals[reg], 0); | |
4184 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4185 | ->internal_elf_sym.st_info = |
4186 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4187 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4188 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4189 | } | |
4190 | } | |
4191 | } | |
4192 | ||
4193 | *input_line_pointer = c; | |
4194 | ||
4195 | demand_empty_rest_of_line (); | |
4196 | } | |
4197 | ||
4198 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4199 | symbols which need it. */ | |
e0c6ed95 | 4200 | |
6d8809aa RH |
4201 | void |
4202 | sparc_adjust_symtab () | |
4203 | { | |
4204 | symbolS *sym; | |
e0c6ed95 | 4205 | |
6d8809aa RH |
4206 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4207 | { | |
4208 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4209 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4210 | continue; | |
4211 | ||
4212 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4213 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4214 | continue; | |
4215 | ||
4216 | S_SET_SEGMENT (sym, undefined_section); | |
4217 | } | |
4218 | } | |
4219 | #endif | |
4220 | ||
252b5132 RH |
4221 | /* If the --enforce-aligned-data option is used, we require .word, |
4222 | et. al., to be aligned correctly. We do it by setting up an | |
4223 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4224 | no unexpected alignment was introduced. | |
4225 | ||
4226 | The SunOS and Solaris native assemblers enforce aligned data by | |
4227 | default. We don't want to do that, because gcc can deliberately | |
4228 | generate misaligned data if the packed attribute is used. Instead, | |
4229 | we permit misaligned data by default, and permit the user to set an | |
4230 | option to check for it. */ | |
4231 | ||
4232 | void | |
4233 | sparc_cons_align (nbytes) | |
4234 | int nbytes; | |
4235 | { | |
4236 | int nalign; | |
4237 | char *p; | |
4238 | ||
4239 | /* Only do this if we are enforcing aligned data. */ | |
4240 | if (! enforce_aligned_data) | |
4241 | return; | |
4242 | ||
0f2712ed | 4243 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4244 | if (sparc_no_align_cons) |
0f2712ed | 4245 | return; |
252b5132 | 4246 | |
f17c130b | 4247 | nalign = mylog2 (nbytes); |
252b5132 RH |
4248 | if (nalign == 0) |
4249 | return; | |
4250 | ||
4251 | assert (nalign > 0); | |
4252 | ||
4253 | if (now_seg == absolute_section) | |
4254 | { | |
4255 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4256 | as_bad (_("misaligned data")); | |
4257 | return; | |
4258 | } | |
4259 | ||
0a9ef439 | 4260 | p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
252b5132 RH |
4261 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); |
4262 | ||
4263 | record_alignment (now_seg, nalign); | |
4264 | } | |
4265 | ||
0a9ef439 | 4266 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4267 | |
4268 | void | |
4269 | sparc_handle_align (fragp) | |
4270 | fragS *fragp; | |
4271 | { | |
0a9ef439 RH |
4272 | int count, fix; |
4273 | char *p; | |
4274 | ||
4275 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4276 | |
0a9ef439 | 4277 | switch (fragp->fr_type) |
252b5132 | 4278 | { |
0a9ef439 RH |
4279 | case rs_align_test: |
4280 | if (count != 0) | |
4281 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4282 | break; | |
e0c6ed95 | 4283 | |
0a9ef439 RH |
4284 | case rs_align_code: |
4285 | p = fragp->fr_literal + fragp->fr_fix; | |
4286 | fix = 0; | |
e0c6ed95 | 4287 | |
0a9ef439 RH |
4288 | if (count & 3) |
4289 | { | |
4290 | fix = count & 3; | |
4291 | memset (p, 0, fix); | |
4292 | p += fix; | |
4293 | count -= fix; | |
4294 | } | |
e0c6ed95 | 4295 | |
0a9ef439 RH |
4296 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4297 | { | |
4298 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4299 | if (INSN_BIG_ENDIAN) | |
4300 | number_to_chars_bigendian (p, wval, 4); | |
4301 | else | |
4302 | number_to_chars_littleendian (p, wval, 4); | |
4303 | p += 4; | |
4304 | count -= 4; | |
4305 | fix += 4; | |
e0c6ed95 | 4306 | } |
0a9ef439 RH |
4307 | |
4308 | if (INSN_BIG_ENDIAN) | |
4309 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4310 | else | |
4311 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4312 | ||
4313 | fragp->fr_fix += fix; | |
4314 | fragp->fr_var = 4; | |
4315 | break; | |
4316 | ||
4317 | default: | |
4318 | break; | |
252b5132 RH |
4319 | } |
4320 | } | |
4321 | ||
4322 | #ifdef OBJ_ELF | |
4323 | /* Some special processing for a Sparc ELF file. */ | |
4324 | ||
4325 | void | |
4326 | sparc_elf_final_processing () | |
4327 | { | |
4328 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4329 | sort of BFD interface for this. */ | |
4330 | if (sparc_arch_size == 64) | |
4331 | { | |
4332 | switch (sparc_memory_model) | |
4333 | { | |
4334 | case MM_RMO: | |
4335 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4336 | break; | |
4337 | case MM_PSO: | |
4338 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4339 | break; | |
4340 | default: | |
4341 | break; | |
4342 | } | |
4343 | } | |
4344 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4345 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4346 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4347 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4348 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4349 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4350 | } |
bd5e6e7e JJ |
4351 | |
4352 | void | |
4353 | sparc_cons (exp, size) | |
4354 | expressionS *exp; | |
4355 | int size; | |
4356 | { | |
4357 | char *save; | |
4358 | ||
4359 | SKIP_WHITESPACE (); | |
4360 | sparc_cons_special_reloc = NULL; | |
4361 | save = input_line_pointer; | |
4362 | if (input_line_pointer[0] == '%' | |
4363 | && input_line_pointer[1] == 'r' | |
4364 | && input_line_pointer[2] == '_') | |
4365 | { | |
4366 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4367 | { | |
4368 | input_line_pointer += 7; | |
4369 | sparc_cons_special_reloc = "disp"; | |
4370 | } | |
4371 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4372 | { | |
4373 | if (size != 4 && size != 8) | |
4374 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4375 | else | |
4376 | { | |
4377 | input_line_pointer += 6; | |
4378 | sparc_cons_special_reloc = "plt"; | |
4379 | } | |
4380 | } | |
b9734f35 JJ |
4381 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4382 | { | |
4383 | if (size != 4 && size != 8) | |
4384 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4385 | else | |
4386 | { | |
4387 | input_line_pointer += 13; | |
4388 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4389 | } | |
4390 | } | |
bd5e6e7e JJ |
4391 | if (sparc_cons_special_reloc) |
4392 | { | |
4393 | int bad = 0; | |
4394 | ||
4395 | switch (size) | |
4396 | { | |
4397 | case 1: | |
4398 | if (*input_line_pointer != '8') | |
4399 | bad = 1; | |
4400 | input_line_pointer--; | |
4401 | break; | |
4402 | case 2: | |
4403 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4404 | bad = 1; | |
4405 | break; | |
4406 | case 4: | |
4407 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4408 | bad = 1; | |
4409 | break; | |
4410 | case 8: | |
4411 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4412 | bad = 1; | |
4413 | break; | |
4414 | default: | |
4415 | bad = 1; | |
4416 | break; | |
4417 | } | |
4418 | ||
4419 | if (bad) | |
4420 | { | |
4421 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4422 | sparc_cons_special_reloc, size * 8, size); | |
4423 | } | |
4424 | else | |
4425 | { | |
4426 | input_line_pointer += 2; | |
4427 | if (*input_line_pointer != '(') | |
4428 | { | |
4429 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4430 | sparc_cons_special_reloc, size * 8); | |
4431 | bad = 1; | |
4432 | } | |
4433 | } | |
4434 | ||
4435 | if (bad) | |
4436 | { | |
4437 | input_line_pointer = save; | |
4438 | sparc_cons_special_reloc = NULL; | |
4439 | } | |
4440 | else | |
4441 | { | |
4442 | int c; | |
4443 | char *end = ++input_line_pointer; | |
4444 | int npar = 0; | |
4445 | ||
4446 | while (! is_end_of_line[(c = *end)]) | |
4447 | { | |
4448 | if (c == '(') | |
4449 | npar++; | |
4450 | else if (c == ')') | |
4451 | { | |
4452 | if (!npar) | |
4453 | break; | |
4454 | npar--; | |
4455 | } | |
4456 | end++; | |
4457 | } | |
4458 | ||
4459 | if (c != ')') | |
4460 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4461 | sparc_cons_special_reloc, size * 8); | |
4462 | else | |
4463 | { | |
4464 | *end = '\0'; | |
4465 | expression (exp); | |
4466 | *end = c; | |
4467 | if (input_line_pointer != end) | |
4468 | { | |
4469 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4470 | sparc_cons_special_reloc, size * 8); | |
4471 | } | |
4472 | else | |
4473 | { | |
4474 | input_line_pointer++; | |
4475 | SKIP_WHITESPACE (); | |
4476 | c = *input_line_pointer; | |
4477 | if (! is_end_of_line[c] && c != ',') | |
4478 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4479 | sparc_cons_special_reloc, size * 8); | |
4480 | } | |
4481 | } | |
4482 | } | |
4483 | } | |
4484 | } | |
4485 | if (sparc_cons_special_reloc == NULL) | |
4486 | expression (exp); | |
4487 | } | |
4488 | ||
252b5132 RH |
4489 | #endif |
4490 | ||
4491 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4492 | reloc for a cons. We could use the definition there, except that | |
4493 | we want to handle little endian relocs specially. */ | |
4494 | ||
4495 | void | |
4496 | cons_fix_new_sparc (frag, where, nbytes, exp) | |
4497 | fragS *frag; | |
4498 | int where; | |
4499 | unsigned int nbytes; | |
4500 | expressionS *exp; | |
4501 | { | |
4502 | bfd_reloc_code_real_type r; | |
4503 | ||
4504 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4505 | (nbytes == 2 ? BFD_RELOC_16 : | |
4506 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4507 | ||
0f2712ed NC |
4508 | if (target_little_endian_data |
4509 | && nbytes == 4 | |
e0c6ed95 | 4510 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4511 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4512 | |
bd5e6e7e JJ |
4513 | if (sparc_cons_special_reloc) |
4514 | { | |
4515 | if (*sparc_cons_special_reloc == 'd') | |
4516 | switch (nbytes) | |
4517 | { | |
4518 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4519 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4520 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4521 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4522 | default: abort (); | |
4523 | } | |
b9734f35 | 4524 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4525 | switch (nbytes) |
4526 | { | |
4527 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4528 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4529 | } | |
b9734f35 JJ |
4530 | else |
4531 | switch (nbytes) | |
4532 | { | |
4533 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4534 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4535 | } | |
bd5e6e7e JJ |
4536 | } |
4537 | else if (sparc_no_align_cons) | |
0f2712ed NC |
4538 | { |
4539 | switch (nbytes) | |
4540 | { | |
4541 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4542 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
4543 | case 8: r = BFD_RELOC_SPARC_UA64; break; | |
4544 | default: abort (); | |
4545 | } | |
4ffadb11 | 4546 | } |
0f2712ed | 4547 | |
252b5132 | 4548 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4549 | sparc_cons_special_reloc = NULL; |
4550 | } | |
4551 | ||
4552 | void | |
4553 | sparc_cfi_frame_initial_instructions () | |
4554 | { | |
4555 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4556 | } | |
4557 | ||
4558 | int | |
1df69f4f | 4559 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b JJ |
4560 | { |
4561 | char *p, *q; | |
4562 | ||
4563 | if (!regname[0]) | |
4564 | return -1; | |
4565 | ||
4566 | q = "goli"; | |
4567 | p = strchr (q, regname[0]); | |
4568 | if (p) | |
4569 | { | |
4570 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
4571 | return -1; | |
4572 | return (p - q) * 8 + regname[1] - '0'; | |
4573 | } | |
4574 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
4575 | return 14; | |
4576 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
4577 | return 30; | |
4578 | if (regname[0] == 'f' || regname[0] == 'r') | |
4579 | { | |
4580 | unsigned int regnum; | |
4581 | ||
4582 | regnum = strtoul (regname + 1, &q, 10); | |
4583 | if (p == q || *q) | |
4584 | return -1; | |
4585 | if (regnum >= ((regname[0] == 'f' | |
4586 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
4587 | ? 64 : 32)) | |
4588 | return -1; | |
4589 | if (regname[0] == 'f') | |
4590 | { | |
4591 | regnum += 32; | |
4592 | if (regnum >= 64 && (regnum & 1)) | |
4593 | return -1; | |
4594 | } | |
4595 | return regnum; | |
4596 | } | |
4597 | return -1; | |
4598 | } | |
4599 | ||
4600 | void | |
4601 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
4602 | { | |
4603 | sparc_cons_special_reloc = "disp"; | |
4604 | sparc_no_align_cons = 1; | |
4605 | emit_expr (exp, nbytes); | |
4606 | sparc_no_align_cons = 0; | |
4607 | sparc_cons_special_reloc = NULL; | |
252b5132 | 4608 | } |