Commit | Line | Data |
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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
e0c6ed95 AM |
2 | Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | This file is part of GAS, the GNU Assembler. |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public | |
17 | License along with GAS; see the file COPYING. If not, write | |
18 | to the Free Software Foundation, 59 Temple Place - Suite 330, | |
81d4177b | 19 | Boston, MA 02111-1307, USA. */ |
252b5132 RH |
20 | |
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | ||
24 | #include "as.h" | |
25 | #include "subsegs.h" | |
26 | ||
27 | #include "opcode/sparc.h" | |
28 | ||
29 | #ifdef OBJ_ELF | |
30 | #include "elf/sparc.h" | |
732d96b6 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
34 | static struct sparc_arch *lookup_arch PARAMS ((char *)); | |
35 | static void init_default_arch PARAMS ((void)); | |
a22b281c | 36 | static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); |
252b5132 RH |
37 | static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); |
38 | static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); | |
39 | static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); | |
40 | static int sparc_ffs PARAMS ((unsigned int)); | |
a22b281c RH |
41 | static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); |
42 | static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); | |
43 | static void synthetize_setx PARAMS ((const struct sparc_opcode *)); | |
252b5132 RH |
44 | static bfd_vma BSR PARAMS ((bfd_vma, int)); |
45 | static int cmp_reg_entry PARAMS ((const PTR, const PTR)); | |
46 | static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); | |
47 | static int parse_const_expr_arg PARAMS ((char **, int *)); | |
48 | static int get_expression PARAMS ((char *str)); | |
49 | ||
50 | /* Default architecture. */ | |
51 | /* ??? The default value should be V8, but sparclite support was added | |
52 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
53 | the future we can set this to V8. */ | |
54 | #ifndef DEFAULT_ARCH | |
55 | #define DEFAULT_ARCH "sparclite" | |
56 | #endif | |
57 | static char *default_arch = DEFAULT_ARCH; | |
58 | ||
59 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
60 | have been set. */ | |
61 | static int default_init_p; | |
62 | ||
63 | /* Current architecture. We don't bump up unless necessary. */ | |
64 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
65 | ||
66 | /* The maximum architecture level we can bump up to. | |
67 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
68 | The native assembler works this way. The user is required to pass | |
69 | an explicit argument before we'll create v9 object files. However, if | |
70 | we don't see any v9 insns, a v8plus object file is not created. */ | |
71 | static enum sparc_opcode_arch_val max_architecture; | |
72 | ||
73 | /* Either 32 or 64, selects file format. */ | |
74 | static int sparc_arch_size; | |
75 | /* Initial (default) value, recorded separately in case a user option | |
76 | changes the value before md_show_usage is called. */ | |
77 | static int default_arch_size; | |
78 | ||
79 | #ifdef OBJ_ELF | |
80 | /* The currently selected v9 memory model. Currently only used for | |
81 | ELF. */ | |
82 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
83 | #endif | |
84 | ||
85 | static int architecture_requested; | |
86 | static int warn_on_bump; | |
87 | ||
88 | /* If warn_on_bump and the needed architecture is higher than this | |
89 | architecture, issue a warning. */ | |
90 | static enum sparc_opcode_arch_val warn_after_architecture; | |
91 | ||
6d8809aa RH |
92 | /* Non-zero if as should generate error if an undeclared g[23] register |
93 | has been used in -64. */ | |
94 | static int no_undeclared_regs; | |
95 | ||
6faf3d66 JJ |
96 | /* Non-zero if we should try to relax jumps and calls. */ |
97 | static int sparc_relax; | |
98 | ||
252b5132 RH |
99 | /* Non-zero if we are generating PIC code. */ |
100 | int sparc_pic_code; | |
101 | ||
102 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
103 | static int enforce_aligned_data; | |
104 | ||
105 | extern int target_big_endian; | |
106 | ||
107 | static int target_little_endian_data; | |
108 | ||
6d8809aa RH |
109 | /* Symbols for global registers on v9. */ |
110 | static symbolS *globals[8]; | |
111 | ||
252b5132 RH |
112 | /* V9 and 86x have big and little endian data, but instructions are always big |
113 | endian. The sparclet has bi-endian support but both data and insns have | |
114 | the same endianness. Global `target_big_endian' is used for data. | |
115 | The following macro is used for instructions. */ | |
116 | #ifndef INSN_BIG_ENDIAN | |
117 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
118 | || default_arch_type == sparc86x \ | |
119 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
120 | #endif | |
121 | ||
e0c6ed95 | 122 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
123 | static struct hash_control *op_hash; |
124 | ||
125 | static int log2 PARAMS ((int)); | |
126 | static void s_data1 PARAMS ((void)); | |
127 | static void s_seg PARAMS ((int)); | |
128 | static void s_proc PARAMS ((int)); | |
129 | static void s_reserve PARAMS ((int)); | |
130 | static void s_common PARAMS ((int)); | |
131 | static void s_empty PARAMS ((int)); | |
132 | static void s_uacons PARAMS ((int)); | |
cf9a1301 | 133 | static void s_ncons PARAMS ((int)); |
6d8809aa | 134 | static void s_register PARAMS ((int)); |
252b5132 RH |
135 | |
136 | const pseudo_typeS md_pseudo_table[] = | |
137 | { | |
e0c6ed95 | 138 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
139 | {"common", s_common, 0}, |
140 | {"empty", s_empty, 0}, | |
141 | {"global", s_globl, 0}, | |
142 | {"half", cons, 2}, | |
cf9a1301 | 143 | {"nword", s_ncons, 0}, |
252b5132 RH |
144 | {"optim", s_ignore, 0}, |
145 | {"proc", s_proc, 0}, | |
146 | {"reserve", s_reserve, 0}, | |
147 | {"seg", s_seg, 0}, | |
148 | {"skip", s_space, 0}, | |
149 | {"word", cons, 4}, | |
150 | {"xword", cons, 8}, | |
151 | {"uahalf", s_uacons, 2}, | |
152 | {"uaword", s_uacons, 4}, | |
153 | {"uaxword", s_uacons, 8}, | |
154 | #ifdef OBJ_ELF | |
732d96b6 JJ |
155 | {"file", dwarf2_directive_file, 0}, |
156 | {"loc", dwarf2_directive_loc, 0}, | |
e0c6ed95 | 157 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
158 | {"2byte", s_uacons, 2}, |
159 | {"4byte", s_uacons, 4}, | |
160 | {"8byte", s_uacons, 8}, | |
6d8809aa | 161 | {"register", s_register, 0}, |
252b5132 RH |
162 | #endif |
163 | {NULL, 0, 0}, | |
164 | }; | |
165 | ||
e0c6ed95 AM |
166 | /* Size of relocation record. */ |
167 | const int md_reloc_size = 12; | |
252b5132 RH |
168 | |
169 | /* This array holds the chars that always start a comment. If the | |
e0c6ed95 AM |
170 | pre-processor is disabled, these aren't very useful. */ |
171 | const char comment_chars[] = "!"; /* JF removed '|' from | |
172 | comment_chars. */ | |
252b5132 RH |
173 | |
174 | /* This array holds the chars that only start a comment at the beginning of | |
175 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 176 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
177 | /* Note that input_file.c hand checks for '#' at the beginning of the |
178 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 179 | #NO_APP at the beginning of its output. */ |
252b5132 | 180 | /* Also note that comments started like this one will always |
e0c6ed95 | 181 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
182 | const char line_comment_chars[] = "#"; |
183 | ||
63a0b638 | 184 | const char line_separator_chars[] = ";"; |
252b5132 | 185 | |
e0c6ed95 AM |
186 | /* Chars that can be used to separate mant from exp in floating point |
187 | nums. */ | |
252b5132 RH |
188 | const char EXP_CHARS[] = "eE"; |
189 | ||
e0c6ed95 AM |
190 | /* Chars that mean this number is a floating point constant. |
191 | As in 0f12.456 | |
192 | or 0d1.2345e12 */ | |
252b5132 RH |
193 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
194 | ||
195 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
196 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
197 | but nothing is ideal around here. */ | |
198 | ||
bc805888 | 199 | #define isoctal(c) ((unsigned) ((c) - '0') < '8') |
252b5132 RH |
200 | |
201 | struct sparc_it | |
202 | { | |
203 | char *error; | |
204 | unsigned long opcode; | |
205 | struct nlist *nlistp; | |
206 | expressionS exp; | |
cf9a1301 | 207 | expressionS exp2; |
252b5132 RH |
208 | int pcrel; |
209 | bfd_reloc_code_real_type reloc; | |
210 | }; | |
211 | ||
212 | struct sparc_it the_insn, set_insn; | |
213 | ||
214 | static void output_insn | |
215 | PARAMS ((const struct sparc_opcode *, struct sparc_it *)); | |
216 | \f | |
217 | /* Table of arguments to -A. | |
218 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
219 | for this use. That table is for opcodes only. This table is for opcodes | |
220 | and file formats. */ | |
221 | ||
222 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, | |
19f7b010 | 223 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
224 | |
225 | static struct sparc_arch { | |
226 | char *name; | |
227 | char *opcode_arch; | |
228 | enum sparc_arch_types arch_type; | |
229 | /* Default word size, as specified during configuration. | |
230 | A value of zero means can't be used to specify default architecture. */ | |
231 | int default_arch_size; | |
232 | /* Allowable arg to -A? */ | |
233 | int user_option_p; | |
234 | } sparc_arch_table[] = { | |
235 | { "v6", "v6", v6, 0, 1 }, | |
236 | { "v7", "v7", v7, 0, 1 }, | |
237 | { "v8", "v8", v8, 32, 1 }, | |
238 | { "sparclet", "sparclet", sparclet, 32, 1 }, | |
239 | { "sparclite", "sparclite", sparclite, 32, 1 }, | |
240 | { "sparc86x", "sparclite", sparc86x, 32, 1 }, | |
241 | { "v8plus", "v9", v9, 0, 1 }, | |
242 | { "v8plusa", "v9a", v9, 0, 1 }, | |
19f7b010 | 243 | { "v8plusb", "v9b", v9, 0, 1 }, |
252b5132 RH |
244 | { "v9", "v9", v9, 0, 1 }, |
245 | { "v9a", "v9a", v9, 0, 1 }, | |
19f7b010 | 246 | { "v9b", "v9b", v9, 0, 1 }, |
252b5132 RH |
247 | /* This exists to allow configure.in/Makefile.in to pass one |
248 | value to specify both the default machine and default word size. */ | |
249 | { "v9-64", "v9", v9, 64, 0 }, | |
250 | { NULL, NULL, v8, 0, 0 } | |
251 | }; | |
252 | ||
253 | /* Variant of default_arch */ | |
254 | static enum sparc_arch_types default_arch_type; | |
255 | ||
256 | static struct sparc_arch * | |
257 | lookup_arch (name) | |
258 | char *name; | |
259 | { | |
260 | struct sparc_arch *sa; | |
261 | ||
262 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
263 | if (strcmp (sa->name, name) == 0) | |
264 | break; | |
265 | if (sa->name == NULL) | |
266 | return NULL; | |
267 | return sa; | |
268 | } | |
269 | ||
270 | /* Initialize the default opcode arch and word size from the default | |
271 | architecture name. */ | |
272 | ||
273 | static void | |
274 | init_default_arch () | |
275 | { | |
276 | struct sparc_arch *sa = lookup_arch (default_arch); | |
277 | ||
278 | if (sa == NULL | |
279 | || sa->default_arch_size == 0) | |
280 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
281 | ||
282 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
283 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
284 | as_fatal (_("Bad opcode table, broken assembler.")); | |
285 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
286 | default_init_p = 1; | |
287 | default_arch_type = sa->arch_type; | |
288 | } | |
289 | ||
290 | /* Called by TARGET_FORMAT. */ | |
291 | ||
292 | const char * | |
293 | sparc_target_format () | |
294 | { | |
295 | /* We don't get a chance to initialize anything before we're called, | |
296 | so handle that now. */ | |
297 | if (! default_init_p) | |
298 | init_default_arch (); | |
299 | ||
300 | #ifdef OBJ_AOUT | |
301 | #ifdef TE_NetBSD | |
302 | return "a.out-sparc-netbsd"; | |
303 | #else | |
304 | #ifdef TE_SPARCAOUT | |
305 | if (target_big_endian) | |
306 | return "a.out-sunos-big"; | |
307 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
308 | return "a.out-sunos-big"; | |
ab3e48dc KH |
309 | else |
310 | return "a.out-sparc-little"; | |
252b5132 RH |
311 | #else |
312 | return "a.out-sunos-big"; | |
313 | #endif | |
314 | #endif | |
315 | #endif | |
316 | ||
317 | #ifdef OBJ_BOUT | |
318 | return "b.out.big"; | |
319 | #endif | |
320 | ||
321 | #ifdef OBJ_COFF | |
322 | #ifdef TE_LYNX | |
323 | return "coff-sparc-lynx"; | |
324 | #else | |
325 | return "coff-sparc"; | |
326 | #endif | |
327 | #endif | |
328 | ||
329 | #ifdef OBJ_ELF | |
330 | return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; | |
331 | #endif | |
332 | ||
333 | abort (); | |
334 | } | |
335 | \f | |
e0c6ed95 | 336 | /* md_parse_option |
252b5132 RH |
337 | * Invocation line includes a switch not recognized by the base assembler. |
338 | * See if it's a processor-specific option. These are: | |
339 | * | |
340 | * -bump | |
341 | * Warn on architecture bumps. See also -A. | |
342 | * | |
343 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
344 | * Standard 32 bit architectures. | |
19f7b010 | 345 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
346 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
347 | * This used to only mean 64 bits, but properly specifying it | |
348 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
349 | * specified orthogonally to word size (except when specifying | |
350 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
351 | * -Av8plus, -Av8plusa, -Av8plusb |
352 | * Same as -Av9{,a,b}. | |
353 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
354 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
355 | * assembler. | |
356 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
357 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 358 | * assembler. |
252b5132 RH |
359 | * |
360 | * Select the architecture and possibly the file format. | |
361 | * Instructions or features not supported by the selected | |
362 | * architecture cause fatal errors. | |
363 | * | |
364 | * The default is to start at v6, and bump the architecture up | |
365 | * whenever an instruction is seen at a higher level. In 32 bit | |
366 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 367 | * -Av8plus{,a,b}. |
252b5132 RH |
368 | * |
369 | * If -bump is specified, a warning is printing when bumping to | |
370 | * higher levels. | |
371 | * | |
372 | * If an architecture is specified, all instructions must match | |
373 | * that architecture. Any higher level instructions are flagged | |
374 | * as errors. Note that in the 32 bit environment specifying | |
375 | * -Av8plus does not automatically create a v8plus object file, a | |
376 | * v9 insn must be seen. | |
377 | * | |
378 | * If both an architecture and -bump are specified, the | |
379 | * architecture starts at the specified level, but bumps are | |
380 | * warnings. Note that we can't set `current_architecture' to | |
381 | * the requested level in this case: in the 32 bit environment, | |
382 | * we still must avoid creating v8plus object files unless v9 | |
383 | * insns are seen. | |
384 | * | |
385 | * Note: | |
386 | * Bumping between incompatible architectures is always an | |
387 | * error. For example, from sparclite to v9. | |
388 | */ | |
389 | ||
390 | #ifdef OBJ_ELF | |
391 | CONST char *md_shortopts = "A:K:VQ:sq"; | |
392 | #else | |
393 | #ifdef OBJ_AOUT | |
394 | CONST char *md_shortopts = "A:k"; | |
395 | #else | |
396 | CONST char *md_shortopts = "A:"; | |
397 | #endif | |
398 | #endif | |
399 | struct option md_longopts[] = { | |
400 | #define OPTION_BUMP (OPTION_MD_BASE) | |
401 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
402 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
403 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
404 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
405 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
406 | #ifdef OBJ_ELF | |
407 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
408 | {"32", no_argument, NULL, OPTION_32}, | |
409 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
410 | {"64", no_argument, NULL, OPTION_64}, | |
411 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
412 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
413 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
414 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
415 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
416 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
417 | #endif | |
418 | #ifdef SPARC_BIENDIAN | |
419 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
420 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
421 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
422 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
423 | #endif | |
424 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
425 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
426 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
427 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
428 | #ifdef OBJ_ELF |
429 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
430 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
431 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
432 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 433 | #endif |
6faf3d66 JJ |
434 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
435 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
436 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
437 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
252b5132 RH |
438 | {NULL, no_argument, NULL, 0} |
439 | }; | |
e0c6ed95 AM |
440 | |
441 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
442 | |
443 | int | |
444 | md_parse_option (c, arg) | |
445 | int c; | |
446 | char *arg; | |
447 | { | |
448 | /* We don't get a chance to initialize anything before we're called, | |
449 | so handle that now. */ | |
450 | if (! default_init_p) | |
451 | init_default_arch (); | |
452 | ||
453 | switch (c) | |
454 | { | |
455 | case OPTION_BUMP: | |
456 | warn_on_bump = 1; | |
457 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
458 | break; | |
459 | ||
460 | case OPTION_XARCH: | |
c2158c24 JJ |
461 | #ifdef OBJ_ELF |
462 | if (strncmp (arg, "v9", 2) != 0) | |
463 | md_parse_option (OPTION_32, NULL); | |
464 | else | |
465 | md_parse_option (OPTION_64, NULL); | |
466 | #endif | |
e0c6ed95 | 467 | /* Fall through. */ |
252b5132 RH |
468 | |
469 | case 'A': | |
470 | { | |
471 | struct sparc_arch *sa; | |
472 | enum sparc_opcode_arch_val opcode_arch; | |
473 | ||
474 | sa = lookup_arch (arg); | |
475 | if (sa == NULL | |
476 | || ! sa->user_option_p) | |
477 | { | |
c2158c24 JJ |
478 | if (c == OPTION_XARCH) |
479 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
480 | else | |
481 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
482 | return 0; |
483 | } | |
484 | ||
485 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
486 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
487 | as_fatal (_("Bad opcode table, broken assembler.")); | |
488 | ||
489 | max_architecture = opcode_arch; | |
490 | architecture_requested = 1; | |
491 | } | |
492 | break; | |
493 | ||
494 | case OPTION_SPARC: | |
495 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
496 | break; | |
497 | ||
498 | case OPTION_ENFORCE_ALIGNED_DATA: | |
499 | enforce_aligned_data = 1; | |
500 | break; | |
501 | ||
502 | #ifdef SPARC_BIENDIAN | |
503 | case OPTION_LITTLE_ENDIAN: | |
504 | target_big_endian = 0; | |
505 | if (default_arch_type != sparclet) | |
506 | as_fatal ("This target does not support -EL"); | |
507 | break; | |
508 | case OPTION_LITTLE_ENDIAN_DATA: | |
509 | target_little_endian_data = 1; | |
510 | target_big_endian = 0; | |
511 | if (default_arch_type != sparc86x | |
512 | && default_arch_type != v9) | |
513 | as_fatal ("This target does not support --little-endian-data"); | |
514 | break; | |
515 | case OPTION_BIG_ENDIAN: | |
516 | target_big_endian = 1; | |
517 | break; | |
518 | #endif | |
519 | ||
520 | #ifdef OBJ_AOUT | |
521 | case 'k': | |
522 | sparc_pic_code = 1; | |
523 | break; | |
524 | #endif | |
525 | ||
526 | #ifdef OBJ_ELF | |
527 | case OPTION_32: | |
528 | case OPTION_64: | |
529 | { | |
530 | const char **list, **l; | |
531 | ||
532 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
533 | list = bfd_target_list (); | |
534 | for (l = list; *l != NULL; l++) | |
535 | { | |
536 | if (sparc_arch_size == 32) | |
537 | { | |
538 | if (strcmp (*l, "elf32-sparc") == 0) | |
539 | break; | |
540 | } | |
541 | else | |
542 | { | |
543 | if (strcmp (*l, "elf64-sparc") == 0) | |
544 | break; | |
545 | } | |
546 | } | |
547 | if (*l == NULL) | |
548 | as_fatal (_("No compiled in support for %d bit object file format"), | |
549 | sparc_arch_size); | |
550 | free (list); | |
551 | } | |
552 | break; | |
553 | ||
554 | case OPTION_TSO: | |
555 | sparc_memory_model = MM_TSO; | |
556 | break; | |
557 | ||
558 | case OPTION_PSO: | |
559 | sparc_memory_model = MM_PSO; | |
560 | break; | |
561 | ||
562 | case OPTION_RMO: | |
563 | sparc_memory_model = MM_RMO; | |
564 | break; | |
565 | ||
566 | case 'V': | |
567 | print_version_id (); | |
568 | break; | |
569 | ||
570 | case 'Q': | |
571 | /* Qy - do emit .comment | |
e0c6ed95 | 572 | Qn - do not emit .comment. */ |
252b5132 RH |
573 | break; |
574 | ||
575 | case 's': | |
e0c6ed95 | 576 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
577 | break; |
578 | ||
579 | case 'q': | |
e0c6ed95 | 580 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
581 | break; |
582 | ||
583 | case 'K': | |
584 | if (strcmp (arg, "PIC") != 0) | |
585 | as_warn (_("Unrecognized option following -K")); | |
586 | else | |
587 | sparc_pic_code = 1; | |
588 | break; | |
6d8809aa RH |
589 | |
590 | case OPTION_NO_UNDECLARED_REGS: | |
591 | no_undeclared_regs = 1; | |
592 | break; | |
a25fe906 ILT |
593 | |
594 | case OPTION_UNDECLARED_REGS: | |
595 | no_undeclared_regs = 0; | |
596 | break; | |
252b5132 RH |
597 | #endif |
598 | ||
6faf3d66 JJ |
599 | case OPTION_RELAX: |
600 | sparc_relax = 1; | |
601 | break; | |
602 | ||
603 | case OPTION_NO_RELAX: | |
604 | sparc_relax = 0; | |
605 | break; | |
606 | ||
252b5132 RH |
607 | default: |
608 | return 0; | |
609 | } | |
610 | ||
611 | return 1; | |
612 | } | |
613 | ||
614 | void | |
615 | md_show_usage (stream) | |
616 | FILE *stream; | |
617 | { | |
618 | const struct sparc_arch *arch; | |
c2158c24 | 619 | int column; |
252b5132 RH |
620 | |
621 | /* We don't get a chance to initialize anything before we're called, | |
622 | so handle that now. */ | |
623 | if (! default_init_p) | |
624 | init_default_arch (); | |
625 | ||
e0c6ed95 | 626 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 627 | column = 0; |
252b5132 RH |
628 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
629 | { | |
c2158c24 JJ |
630 | if (!arch->user_option_p) |
631 | continue; | |
252b5132 RH |
632 | if (arch != &sparc_arch_table[0]) |
633 | fprintf (stream, " | "); | |
c2158c24 JJ |
634 | if (column + strlen(arch->name) > 70) |
635 | { | |
636 | column = 0; | |
637 | fputc ('\n', stream); | |
638 | } | |
639 | column += 5 + 2 + strlen(arch->name); | |
640 | fprintf (stream, "-A%s", arch->name); | |
252b5132 | 641 | } |
c2158c24 JJ |
642 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
643 | { | |
644 | if (!arch->user_option_p) | |
645 | continue; | |
646 | fprintf (stream, " | "); | |
647 | if (column + strlen(arch->name) > 65) | |
648 | { | |
649 | column = 0; | |
650 | fputc ('\n', stream); | |
651 | } | |
652 | column += 5 + 7 + strlen(arch->name); | |
653 | fprintf (stream, "-xarch=%s", arch->name); | |
654 | } | |
655 | fprintf (stream, _("\n\ | |
252b5132 RH |
656 | specify variant of SPARC architecture\n\ |
657 | -bump warn when assembler switches architectures\n\ | |
658 | -sparc ignored\n\ | |
6faf3d66 JJ |
659 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
660 | -relax relax jumps and branches (default)\n\ | |
661 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
662 | #ifdef OBJ_AOUT |
663 | fprintf (stream, _("\ | |
664 | -k generate PIC\n")); | |
665 | #endif | |
666 | #ifdef OBJ_ELF | |
667 | fprintf (stream, _("\ | |
668 | -32 create 32 bit object file\n\ | |
669 | -64 create 64 bit object file\n")); | |
670 | fprintf (stream, _("\ | |
671 | [default is %d]\n"), default_arch_size); | |
672 | fprintf (stream, _("\ | |
673 | -TSO use Total Store Ordering\n\ | |
674 | -PSO use Partial Store Ordering\n\ | |
675 | -RMO use Relaxed Memory Ordering\n")); | |
676 | fprintf (stream, _("\ | |
677 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
678 | fprintf (stream, _("\ | |
679 | -KPIC generate PIC\n\ | |
680 | -V print assembler version number\n\ | |
a25fe906 ILT |
681 | -undeclared-regs ignore application global register usage without\n\ |
682 | appropriate .register directive (default)\n\ | |
683 | -no-undeclared-regs force error on application global register usage\n\ | |
684 | without appropriate .register directive\n\ | |
252b5132 RH |
685 | -q ignored\n\ |
686 | -Qy, -Qn ignored\n\ | |
687 | -s ignored\n")); | |
688 | #endif | |
689 | #ifdef SPARC_BIENDIAN | |
690 | fprintf (stream, _("\ | |
691 | -EL generate code for a little endian machine\n\ | |
692 | -EB generate code for a big endian machine\n\ | |
693 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 694 | instructions and little endian data.\n")); |
252b5132 RH |
695 | #endif |
696 | } | |
697 | \f | |
e0c6ed95 | 698 | /* Native operand size opcode translation. */ |
cf9a1301 RH |
699 | struct |
700 | { | |
701 | char *name; | |
702 | char *name32; | |
703 | char *name64; | |
704 | } native_op_table[] = | |
705 | { | |
706 | {"ldn", "ld", "ldx"}, | |
707 | {"ldna", "lda", "ldxa"}, | |
708 | {"stn", "st", "stx"}, | |
709 | {"stna", "sta", "stxa"}, | |
710 | {"slln", "sll", "sllx"}, | |
711 | {"srln", "srl", "srlx"}, | |
712 | {"sran", "sra", "srax"}, | |
713 | {"casn", "cas", "casx"}, | |
714 | {"casna", "casa", "casxa"}, | |
715 | {"clrn", "clr", "clrx"}, | |
716 | {NULL, NULL, NULL}, | |
717 | }; | |
718 | \f | |
e0c6ed95 | 719 | /* sparc64 priviledged registers. */ |
252b5132 RH |
720 | |
721 | struct priv_reg_entry | |
ab3e48dc KH |
722 | { |
723 | char *name; | |
724 | int regnum; | |
725 | }; | |
252b5132 RH |
726 | |
727 | struct priv_reg_entry priv_reg_table[] = | |
728 | { | |
729 | {"tpc", 0}, | |
730 | {"tnpc", 1}, | |
731 | {"tstate", 2}, | |
732 | {"tt", 3}, | |
733 | {"tick", 4}, | |
734 | {"tba", 5}, | |
735 | {"pstate", 6}, | |
736 | {"tl", 7}, | |
737 | {"pil", 8}, | |
738 | {"cwp", 9}, | |
739 | {"cansave", 10}, | |
740 | {"canrestore", 11}, | |
741 | {"cleanwin", 12}, | |
742 | {"otherwin", 13}, | |
743 | {"wstate", 14}, | |
744 | {"fq", 15}, | |
745 | {"ver", 31}, | |
e0c6ed95 | 746 | {"", -1}, /* End marker. */ |
252b5132 RH |
747 | }; |
748 | ||
e0c6ed95 | 749 | /* v9a specific asrs. */ |
252b5132 RH |
750 | |
751 | struct priv_reg_entry v9a_asr_table[] = | |
752 | { | |
753 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
754 | {"sys_tick_cmpr", 25}, |
755 | {"sys_tick", 24}, | |
252b5132 RH |
756 | {"softint", 22}, |
757 | {"set_softint", 20}, | |
758 | {"pic", 17}, | |
759 | {"pcr", 16}, | |
760 | {"gsr", 19}, | |
761 | {"dcr", 18}, | |
762 | {"clear_softint", 21}, | |
e0c6ed95 | 763 | {"", -1}, /* End marker. */ |
252b5132 RH |
764 | }; |
765 | ||
766 | static int | |
767 | cmp_reg_entry (parg, qarg) | |
768 | const PTR parg; | |
769 | const PTR qarg; | |
770 | { | |
771 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
772 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
773 | ||
774 | return strcmp (q->name, p->name); | |
775 | } | |
776 | \f | |
777 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
778 | set up all the tables, etc. that the MD part of the assembler will |
779 | need. */ | |
252b5132 RH |
780 | |
781 | void | |
782 | md_begin () | |
783 | { | |
784 | register const char *retval = NULL; | |
785 | int lose = 0; | |
786 | register unsigned int i = 0; | |
787 | ||
788 | /* We don't get a chance to initialize anything before md_parse_option | |
789 | is called, and it may not be called, so handle default initialization | |
790 | now if not already done. */ | |
791 | if (! default_init_p) | |
792 | init_default_arch (); | |
793 | ||
794 | op_hash = hash_new (); | |
795 | ||
796 | while (i < (unsigned int) sparc_num_opcodes) | |
797 | { | |
798 | const char *name = sparc_opcodes[i].name; | |
799 | retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); | |
800 | if (retval != NULL) | |
801 | { | |
cf9a1301 RH |
802 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
803 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
804 | lose = 1; |
805 | } | |
806 | do | |
807 | { | |
808 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
809 | { | |
cf9a1301 RH |
810 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
811 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
812 | lose = 1; |
813 | } | |
814 | ++i; | |
815 | } | |
816 | while (i < (unsigned int) sparc_num_opcodes | |
817 | && !strcmp (sparc_opcodes[i].name, name)); | |
818 | } | |
819 | ||
cf9a1301 RH |
820 | for (i = 0; native_op_table[i].name; i++) |
821 | { | |
822 | const struct sparc_opcode *insn; | |
3d4ae3c0 NC |
823 | char *name = ((sparc_arch_size == 32) |
824 | ? native_op_table[i].name32 | |
825 | : native_op_table[i].name64); | |
e0c6ed95 | 826 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 827 | if (insn == NULL) |
e0c6ed95 AM |
828 | { |
829 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
830 | name, native_op_table[i].name); | |
831 | lose = 1; | |
832 | } | |
cf9a1301 RH |
833 | else |
834 | { | |
835 | retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); | |
836 | if (retval != NULL) | |
837 | { | |
838 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
839 | sparc_opcodes[i].name, retval); | |
840 | lose = 1; | |
841 | } | |
842 | } | |
843 | } | |
844 | ||
252b5132 RH |
845 | if (lose) |
846 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
847 | ||
252b5132 RH |
848 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
849 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
850 | ||
851 | /* If -bump, record the architecture level at which we start issuing | |
852 | warnings. The behaviour is different depending upon whether an | |
853 | architecture was explicitly specified. If it wasn't, we issue warnings | |
854 | for all upwards bumps. If it was, we don't start issuing warnings until | |
855 | we need to bump beyond the requested architecture or when we bump between | |
856 | conflicting architectures. */ | |
857 | ||
858 | if (warn_on_bump | |
859 | && architecture_requested) | |
860 | { | |
861 | /* `max_architecture' records the requested architecture. | |
862 | Issue warnings if we go above it. */ | |
863 | warn_after_architecture = max_architecture; | |
864 | ||
865 | /* Find the highest architecture level that doesn't conflict with | |
866 | the requested one. */ | |
867 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
868 | max_architecture > warn_after_architecture; | |
869 | --max_architecture) | |
870 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
871 | warn_after_architecture)) | |
872 | break; | |
873 | } | |
874 | } | |
875 | ||
876 | /* Called after all assembly has been done. */ | |
877 | ||
878 | void | |
879 | sparc_md_end () | |
880 | { | |
19f7b010 JJ |
881 | unsigned long mach = bfd_mach_sparc; |
882 | ||
252b5132 | 883 | if (sparc_arch_size == 64) |
19f7b010 JJ |
884 | switch (current_architecture) |
885 | { | |
886 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
887 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
888 | default: mach = bfd_mach_sparc_v9; break; | |
889 | } | |
252b5132 | 890 | else |
19f7b010 JJ |
891 | switch (current_architecture) |
892 | { | |
893 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
894 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
895 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
896 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
897 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
898 | be but for now it is (since that's the way it's always been | |
899 | treated). */ | |
900 | default: break; | |
901 | } | |
902 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
252b5132 RH |
903 | } |
904 | \f | |
905 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
906 | ||
907 | static INLINE int | |
908 | in_signed_range (val, max) | |
909 | bfd_signed_vma val, max; | |
910 | { | |
911 | if (max <= 0) | |
912 | abort (); | |
913 | /* Sign-extend the value from the architecture word size, so that | |
914 | 0xffffffff is always considered -1 on sparc32. */ | |
915 | if (sparc_arch_size == 32) | |
916 | { | |
e0c6ed95 | 917 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
252b5132 RH |
918 | val = ((val & 0xffffffff) ^ sign) - sign; |
919 | } | |
920 | if (val > max) | |
921 | return 0; | |
922 | if (val < ~max) | |
923 | return 0; | |
924 | return 1; | |
925 | } | |
926 | ||
927 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
928 | ||
929 | static INLINE int | |
930 | in_unsigned_range (val, max) | |
931 | bfd_vma val, max; | |
932 | { | |
933 | if (val > max) | |
934 | return 0; | |
935 | return 1; | |
936 | } | |
937 | ||
938 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
939 | (e.g. -15 to +31). */ | |
940 | ||
941 | static INLINE int | |
942 | in_bitfield_range (val, max) | |
943 | bfd_signed_vma val, max; | |
944 | { | |
945 | if (max <= 0) | |
946 | abort (); | |
947 | if (val > max) | |
948 | return 0; | |
949 | if (val < ~(max >> 1)) | |
950 | return 0; | |
951 | return 1; | |
952 | } | |
953 | ||
954 | static int | |
955 | sparc_ffs (mask) | |
956 | unsigned int mask; | |
957 | { | |
958 | int i; | |
959 | ||
960 | if (mask == 0) | |
961 | return -1; | |
962 | ||
963 | for (i = 0; (mask & 1) == 0; ++i) | |
964 | mask >>= 1; | |
965 | return i; | |
966 | } | |
967 | ||
968 | /* Implement big shift right. */ | |
969 | static bfd_vma | |
970 | BSR (val, amount) | |
971 | bfd_vma val; | |
972 | int amount; | |
973 | { | |
974 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
975 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
976 | return val >> amount; | |
977 | } | |
978 | \f | |
979 | /* For communication between sparc_ip and get_expression. */ | |
980 | static char *expr_end; | |
981 | ||
252b5132 RH |
982 | /* Values for `special_case'. |
983 | Instructions that require wierd handling because they're longer than | |
984 | 4 bytes. */ | |
985 | #define SPECIAL_CASE_NONE 0 | |
986 | #define SPECIAL_CASE_SET 1 | |
987 | #define SPECIAL_CASE_SETSW 2 | |
988 | #define SPECIAL_CASE_SETX 3 | |
989 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
990 | #define SPECIAL_CASE_FDIV 4 | |
991 | ||
992 | /* Bit masks of various insns. */ | |
993 | #define NOP_INSN 0x01000000 | |
994 | #define OR_INSN 0x80100000 | |
63fab58c | 995 | #define XOR_INSN 0x80180000 |
252b5132 RH |
996 | #define FMOVS_INSN 0x81A00020 |
997 | #define SETHI_INSN 0x01000000 | |
998 | #define SLLX_INSN 0x81281000 | |
999 | #define SRA_INSN 0x81380000 | |
1000 | ||
1001 | /* The last instruction to be assembled. */ | |
1002 | static const struct sparc_opcode *last_insn; | |
1003 | /* The assembled opcode of `last_insn'. */ | |
1004 | static unsigned long last_opcode; | |
1005 | \f | |
a22b281c | 1006 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1007 | |
a22b281c RH |
1008 | static void |
1009 | synthetize_setuw (insn) | |
1010 | const struct sparc_opcode *insn; | |
1011 | { | |
1012 | int need_hi22_p = 0; | |
1013 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1014 | ||
1015 | if (the_insn.exp.X_op == O_constant) | |
1016 | { | |
1017 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1018 | { | |
e0c6ed95 | 1019 | if (sizeof (offsetT) > 4 |
a22b281c RH |
1020 | && (the_insn.exp.X_add_number < 0 |
1021 | || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) | |
1022 | as_warn (_("set: number not in 0..4294967295 range")); | |
1023 | } | |
1024 | else | |
1025 | { | |
e0c6ed95 | 1026 | if (sizeof (offsetT) > 4 |
a22b281c RH |
1027 | && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 |
1028 | || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) | |
1029 | as_warn (_("set: number not in -2147483648..4294967295 range")); | |
e0c6ed95 | 1030 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1031 | } |
1032 | } | |
1033 | ||
1034 | /* See if operand is absolute and small; skip sethi if so. */ | |
1035 | if (the_insn.exp.X_op != O_constant | |
1036 | || the_insn.exp.X_add_number >= (1 << 12) | |
1037 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1038 | { | |
1039 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1040 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1041 | & (the_insn.exp.X_op == O_constant |
1042 | ? 0x3fffff : 0))); | |
a22b281c | 1043 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1044 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1045 | output_insn (insn, &the_insn); |
1046 | need_hi22_p = 1; | |
1047 | } | |
1048 | ||
1049 | /* See if operand has no low-order bits; skip OR if so. */ | |
1050 | if (the_insn.exp.X_op != O_constant | |
1051 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1052 | || ! need_hi22_p) | |
1053 | { | |
1054 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1055 | | RD (rd) | IMMED | |
1056 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1057 | & (the_insn.exp.X_op != O_constant |
1058 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1059 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1060 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1061 | output_insn (insn, &the_insn); |
1062 | } | |
1063 | } | |
e0c6ed95 | 1064 | |
a22b281c | 1065 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1066 | |
a22b281c RH |
1067 | static void |
1068 | synthetize_setsw (insn) | |
1069 | const struct sparc_opcode *insn; | |
1070 | { | |
1071 | int low32, rd, opc; | |
1072 | ||
1073 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1074 | ||
1075 | if (the_insn.exp.X_op != O_constant) | |
1076 | { | |
1077 | synthetize_setuw (insn); | |
1078 | ||
1079 | /* Need to sign extend it. */ | |
1080 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1081 | the_insn.reloc = BFD_RELOC_NONE; | |
1082 | output_insn (insn, &the_insn); | |
1083 | return; | |
1084 | } | |
1085 | ||
e0c6ed95 | 1086 | if (sizeof (offsetT) > 4 |
a22b281c RH |
1087 | && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 |
1088 | || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) | |
1089 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); | |
1090 | ||
e0c6ed95 AM |
1091 | low32 = the_insn.exp.X_add_number; |
1092 | ||
a22b281c RH |
1093 | if (low32 >= 0) |
1094 | { | |
1095 | synthetize_setuw (insn); | |
1096 | return; | |
1097 | } | |
1098 | ||
1099 | opc = OR_INSN; | |
e0c6ed95 | 1100 | |
a22b281c RH |
1101 | the_insn.reloc = BFD_RELOC_NONE; |
1102 | /* See if operand is absolute and small; skip sethi if so. */ | |
1103 | if (low32 < -(1 << 12)) | |
1104 | { | |
1105 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1106 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1107 | output_insn (insn, &the_insn); | |
1108 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1109 | opc = RS1 (rd) | XOR_INSN; | |
1110 | } | |
1111 | ||
1112 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1113 | | (low32 & 0x1fff)); | |
1114 | output_insn (insn, &the_insn); | |
1115 | } | |
1116 | ||
1117 | /* Handle the setsw synthetic instruction. */ | |
e0c6ed95 | 1118 | |
a22b281c RH |
1119 | static void |
1120 | synthetize_setx (insn) | |
1121 | const struct sparc_opcode *insn; | |
1122 | { | |
1123 | int upper32, lower32; | |
1124 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1125 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1126 | int upper_dstreg; | |
1127 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1128 | int need_xor10_p = 0; | |
e0c6ed95 | 1129 | |
a22b281c RH |
1130 | #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000) |
1131 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); | |
1132 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1133 | #undef SIGNEXT32 | |
1134 | ||
1135 | upper_dstreg = tmpreg; | |
1136 | /* The tmp reg should not be the dst reg. */ | |
1137 | if (tmpreg == dstreg) | |
1138 | as_warn (_("setx: temporary register same as destination register")); | |
1139 | ||
1140 | /* ??? Obviously there are other optimizations we can do | |
1141 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1142 | doing some of these. Later. If you do change things, try to | |
1143 | change all of this to be table driven as well. */ | |
1144 | /* What to output depends on the number if it's constant. | |
1145 | Compute that first, then output what we've decided upon. */ | |
1146 | if (the_insn.exp.X_op != O_constant) | |
1147 | { | |
1148 | if (sparc_arch_size == 32) | |
1149 | { | |
1150 | /* When arch size is 32, we want setx to be equivalent | |
1151 | to setuw for anything but constants. */ | |
1152 | the_insn.exp.X_add_number &= 0xffffffff; | |
1153 | synthetize_setuw (insn); | |
1154 | return; | |
1155 | } | |
1156 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1157 | lower32 = 0; |
1158 | upper32 = 0; | |
a22b281c RH |
1159 | } |
1160 | else | |
1161 | { | |
1162 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1163 | Otherwise fixup_segment will complain about not being able to | |
1164 | write an 8 byte number in a 4 byte field. */ | |
1165 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1166 | |
a22b281c RH |
1167 | /* Only need hh22 if `or' insn can't handle constant. */ |
1168 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1169 | need_hh22_p = 1; | |
e0c6ed95 | 1170 | |
a22b281c RH |
1171 | /* Does bottom part (after sethi) have bits? */ |
1172 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1173 | /* No hh22, but does upper32 still have bits we can't set | |
1174 | from lower32? */ | |
1175 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1176 | need_hm10_p = 1; | |
e0c6ed95 | 1177 | |
a22b281c RH |
1178 | /* If the lower half is all zero, we build the upper half directly |
1179 | into the dst reg. */ | |
1180 | if (lower32 != 0 | |
1181 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1182 | || (! need_hh22_p && ! need_hm10_p)) | |
1183 | { | |
1184 | /* No need for sethi if `or' insn can handle constant. */ | |
1185 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1186 | /* Note that we can't use a negative constant in the `or' | |
1187 | insn unless the upper 32 bits are all ones. */ | |
1188 | || (lower32 < 0 && upper32 != -1) | |
1189 | || (lower32 >= 0 && upper32 == -1)) | |
1190 | need_hi22_p = 1; | |
e0c6ed95 | 1191 | |
a22b281c RH |
1192 | if (need_hi22_p && upper32 == -1) |
1193 | need_xor10_p = 1; | |
1194 | ||
1195 | /* Does bottom part (after sethi) have bits? */ | |
1196 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1197 | /* No sethi. */ | |
1198 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1199 | /* Need `or' if we didn't set anything else. */ | |
1200 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1201 | need_lo10_p = 1; | |
1202 | } | |
1203 | else | |
1204 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1205 | upper_dstreg = dstreg; | |
1206 | } | |
e0c6ed95 | 1207 | |
a22b281c RH |
1208 | if (!upper_dstreg && dstreg) |
1209 | as_warn (_("setx: illegal temporary register g0")); | |
1210 | ||
1211 | if (need_hh22_p) | |
1212 | { | |
1213 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1214 | | ((upper32 >> 10) & 0x3fffff)); | |
1215 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1216 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1217 | output_insn (insn, &the_insn); | |
1218 | } | |
e0c6ed95 | 1219 | |
a22b281c RH |
1220 | if (need_hi22_p) |
1221 | { | |
1222 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1223 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1224 | >> 10) & 0x3fffff)); |
a22b281c RH |
1225 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1226 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1227 | output_insn (insn, &the_insn); | |
1228 | } | |
1229 | ||
1230 | if (need_hm10_p) | |
1231 | { | |
1232 | the_insn.opcode = (OR_INSN | |
1233 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1234 | | RD (upper_dstreg) | |
1235 | | IMMED | |
1236 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1237 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1238 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1239 | output_insn (insn, &the_insn); | |
1240 | } | |
e0c6ed95 | 1241 | |
a22b281c RH |
1242 | if (need_lo10_p) |
1243 | { | |
1244 | /* FIXME: One nice optimization to do here is to OR the low part | |
1245 | with the highpart if hi22 isn't needed and the low part is | |
1246 | positive. */ | |
1247 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1248 | | RD (dstreg) | |
1249 | | IMMED | |
1250 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1251 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1252 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1253 | output_insn (insn, &the_insn); | |
1254 | } | |
e0c6ed95 | 1255 | |
a22b281c RH |
1256 | /* If we needed to build the upper part, shift it into place. */ |
1257 | if (need_hh22_p || need_hm10_p) | |
1258 | { | |
1259 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1260 | | IMMED | 32); | |
1261 | the_insn.reloc = BFD_RELOC_NONE; | |
1262 | output_insn (insn, &the_insn); | |
1263 | } | |
e0c6ed95 | 1264 | |
a22b281c RH |
1265 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1266 | if (need_xor10_p) | |
1267 | { | |
1268 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1269 | | 0x1c00 | (lower32 & 0x3ff)); | |
1270 | the_insn.reloc = BFD_RELOC_NONE; | |
1271 | output_insn (insn, &the_insn); | |
1272 | } | |
1273 | ||
1274 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1275 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1276 | { | |
1277 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1278 | | RD (dstreg)); | |
1279 | the_insn.reloc = BFD_RELOC_NONE; | |
1280 | output_insn (insn, &the_insn); | |
1281 | } | |
1282 | } | |
1283 | \f | |
252b5132 RH |
1284 | /* Main entry point to assemble one instruction. */ |
1285 | ||
1286 | void | |
1287 | md_assemble (str) | |
1288 | char *str; | |
1289 | { | |
1290 | const struct sparc_opcode *insn; | |
a22b281c | 1291 | int special_case; |
252b5132 RH |
1292 | |
1293 | know (str); | |
a22b281c | 1294 | special_case = sparc_ip (str, &insn); |
252b5132 RH |
1295 | |
1296 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1297 | unless the delay slot has been annulled. */ | |
1298 | if (insn != NULL | |
1299 | && last_insn != NULL | |
1300 | && (insn->flags & F_FBR) != 0 | |
1301 | && (last_insn->flags & F_DELAYED) != 0 | |
1302 | /* ??? This test isn't completely accurate. We assume anything with | |
1303 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1304 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1305 | || (last_opcode & ANNUL) == 0)) | |
1306 | as_warn (_("FP branch in delay slot")); | |
1307 | ||
1308 | /* SPARC before v9 requires a nop instruction between a floating | |
1309 | point instruction and a floating point branch. We insert one | |
1310 | automatically, with a warning. */ | |
1311 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
1312 | && insn != NULL | |
1313 | && last_insn != NULL | |
1314 | && (insn->flags & F_FBR) != 0 | |
1315 | && (last_insn->flags & F_FLOAT) != 0) | |
1316 | { | |
1317 | struct sparc_it nop_insn; | |
1318 | ||
1319 | nop_insn.opcode = NOP_INSN; | |
1320 | nop_insn.reloc = BFD_RELOC_NONE; | |
1321 | output_insn (insn, &nop_insn); | |
1322 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1323 | } | |
1324 | ||
a22b281c RH |
1325 | switch (special_case) |
1326 | { | |
1327 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1328 | /* Normal insn. */ |
a22b281c RH |
1329 | output_insn (insn, &the_insn); |
1330 | break; | |
252b5132 | 1331 | |
a22b281c RH |
1332 | case SPECIAL_CASE_SETSW: |
1333 | synthetize_setsw (insn); | |
1334 | break; | |
e0c6ed95 | 1335 | |
a22b281c RH |
1336 | case SPECIAL_CASE_SET: |
1337 | synthetize_setuw (insn); | |
1338 | break; | |
252b5132 | 1339 | |
a22b281c RH |
1340 | case SPECIAL_CASE_SETX: |
1341 | synthetize_setx (insn); | |
1342 | break; | |
e0c6ed95 | 1343 | |
a22b281c RH |
1344 | case SPECIAL_CASE_FDIV: |
1345 | { | |
1346 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1347 | |
a22b281c | 1348 | output_insn (insn, &the_insn); |
e0c6ed95 | 1349 | |
a22b281c RH |
1350 | /* According to information leaked from Sun, the "fdiv" instructions |
1351 | on early SPARC machines would produce incorrect results sometimes. | |
1352 | The workaround is to add an fmovs of the destination register to | |
1353 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1354 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
a22b281c RH |
1355 | assert (the_insn.reloc == BFD_RELOC_NONE); |
1356 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); | |
1357 | output_insn (insn, &the_insn); | |
1358 | return; | |
1359 | } | |
e0c6ed95 | 1360 | |
a22b281c RH |
1361 | default: |
1362 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1363 | } |
1364 | } | |
1365 | ||
1366 | /* Subroutine of md_assemble to do the actual parsing. */ | |
1367 | ||
a22b281c | 1368 | static int |
252b5132 RH |
1369 | sparc_ip (str, pinsn) |
1370 | char *str; | |
1371 | const struct sparc_opcode **pinsn; | |
1372 | { | |
1373 | char *error_message = ""; | |
1374 | char *s; | |
1375 | const char *args; | |
1376 | char c; | |
1377 | const struct sparc_opcode *insn; | |
1378 | char *argsStart; | |
1379 | unsigned long opcode; | |
1380 | unsigned int mask = 0; | |
1381 | int match = 0; | |
1382 | int comma = 0; | |
1383 | int v9_arg_p; | |
a22b281c | 1384 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1385 | |
1386 | s = str; | |
1387 | if (islower ((unsigned char) *s)) | |
1388 | { | |
1389 | do | |
1390 | ++s; | |
1391 | while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s)); | |
1392 | } | |
1393 | ||
1394 | switch (*s) | |
1395 | { | |
1396 | case '\0': | |
1397 | break; | |
1398 | ||
1399 | case ',': | |
1400 | comma = 1; | |
e0c6ed95 | 1401 | /* Fall through. */ |
252b5132 RH |
1402 | |
1403 | case ' ': | |
1404 | *s++ = '\0'; | |
1405 | break; | |
1406 | ||
1407 | default: | |
1408 | as_fatal (_("Unknown opcode: `%s'"), str); | |
1409 | } | |
1410 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1411 | *pinsn = insn; | |
1412 | if (insn == NULL) | |
1413 | { | |
1414 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1415 | return special_case; |
252b5132 RH |
1416 | } |
1417 | if (comma) | |
1418 | { | |
1419 | *--s = ','; | |
1420 | } | |
1421 | ||
1422 | argsStart = s; | |
1423 | for (;;) | |
1424 | { | |
1425 | opcode = insn->match; | |
1426 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1427 | the_insn.reloc = BFD_RELOC_NONE; | |
1428 | v9_arg_p = 0; | |
1429 | ||
e0c6ed95 AM |
1430 | /* Build the opcode, checking as we go to make sure that the |
1431 | operands match. */ | |
252b5132 RH |
1432 | for (args = insn->args;; ++args) |
1433 | { | |
1434 | switch (*args) | |
1435 | { | |
1436 | case 'K': | |
1437 | { | |
1438 | int kmask = 0; | |
1439 | ||
1440 | /* Parse a series of masks. */ | |
1441 | if (*s == '#') | |
1442 | { | |
1443 | while (*s == '#') | |
1444 | { | |
1445 | int mask; | |
1446 | ||
1447 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
1448 | &mask)) | |
1449 | { | |
1450 | error_message = _(": invalid membar mask name"); | |
1451 | goto error; | |
1452 | } | |
1453 | kmask |= mask; | |
47926f60 KH |
1454 | while (*s == ' ') |
1455 | ++s; | |
252b5132 RH |
1456 | if (*s == '|' || *s == '+') |
1457 | ++s; | |
47926f60 KH |
1458 | while (*s == ' ') |
1459 | ++s; | |
252b5132 RH |
1460 | } |
1461 | } | |
1462 | else | |
1463 | { | |
1464 | if (! parse_const_expr_arg (&s, &kmask)) | |
1465 | { | |
1466 | error_message = _(": invalid membar mask expression"); | |
1467 | goto error; | |
1468 | } | |
1469 | if (kmask < 0 || kmask > 127) | |
1470 | { | |
1471 | error_message = _(": invalid membar mask number"); | |
1472 | goto error; | |
1473 | } | |
1474 | } | |
1475 | ||
1476 | opcode |= MEMBAR (kmask); | |
1477 | continue; | |
1478 | } | |
1479 | ||
19f7b010 JJ |
1480 | case '3': |
1481 | { | |
1482 | int smask = 0; | |
1483 | ||
1484 | if (! parse_const_expr_arg (&s, &smask)) | |
1485 | { | |
1486 | error_message = _(": invalid siam mode expression"); | |
1487 | goto error; | |
1488 | } | |
1489 | if (smask < 0 || smask > 7) | |
1490 | { | |
1491 | error_message = _(": invalid siam mode number"); | |
1492 | goto error; | |
1493 | } | |
1494 | opcode |= smask; | |
1495 | continue; | |
1496 | } | |
1497 | ||
252b5132 RH |
1498 | case '*': |
1499 | { | |
1500 | int fcn = 0; | |
1501 | ||
1502 | /* Parse a prefetch function. */ | |
1503 | if (*s == '#') | |
1504 | { | |
1505 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1506 | { | |
1507 | error_message = _(": invalid prefetch function name"); | |
1508 | goto error; | |
1509 | } | |
1510 | } | |
1511 | else | |
1512 | { | |
1513 | if (! parse_const_expr_arg (&s, &fcn)) | |
1514 | { | |
1515 | error_message = _(": invalid prefetch function expression"); | |
1516 | goto error; | |
1517 | } | |
1518 | if (fcn < 0 || fcn > 31) | |
1519 | { | |
1520 | error_message = _(": invalid prefetch function number"); | |
1521 | goto error; | |
1522 | } | |
1523 | } | |
1524 | opcode |= RD (fcn); | |
1525 | continue; | |
1526 | } | |
1527 | ||
1528 | case '!': | |
1529 | case '?': | |
1530 | /* Parse a sparc64 privileged register. */ | |
1531 | if (*s == '%') | |
1532 | { | |
1533 | struct priv_reg_entry *p = priv_reg_table; | |
e0c6ed95 | 1534 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1535 | |
1536 | s += 1; | |
1537 | while (p->name[0] > s[0]) | |
1538 | p++; | |
1539 | while (p->name[0] == s[0]) | |
1540 | { | |
1541 | len = strlen (p->name); | |
1542 | if (strncmp (p->name, s, len) == 0) | |
1543 | break; | |
1544 | p++; | |
1545 | } | |
1546 | if (p->name[0] != s[0]) | |
1547 | { | |
1548 | error_message = _(": unrecognizable privileged register"); | |
1549 | goto error; | |
1550 | } | |
1551 | if (*args == '?') | |
1552 | opcode |= (p->regnum << 14); | |
1553 | else | |
1554 | opcode |= (p->regnum << 25); | |
1555 | s += len; | |
1556 | continue; | |
1557 | } | |
1558 | else | |
1559 | { | |
1560 | error_message = _(": unrecognizable privileged register"); | |
1561 | goto error; | |
1562 | } | |
1563 | ||
1564 | case '_': | |
1565 | case '/': | |
19f7b010 | 1566 | /* Parse a v9a/v9b ancillary state register. */ |
252b5132 RH |
1567 | if (*s == '%') |
1568 | { | |
1569 | struct priv_reg_entry *p = v9a_asr_table; | |
e0c6ed95 | 1570 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1571 | |
1572 | s += 1; | |
1573 | while (p->name[0] > s[0]) | |
1574 | p++; | |
1575 | while (p->name[0] == s[0]) | |
1576 | { | |
1577 | len = strlen (p->name); | |
1578 | if (strncmp (p->name, s, len) == 0) | |
1579 | break; | |
1580 | p++; | |
1581 | } | |
1582 | if (p->name[0] != s[0]) | |
1583 | { | |
19f7b010 | 1584 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1585 | goto error; |
1586 | } | |
1587 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1588 | { | |
1589 | error_message = _(": rd on write only ancillary state register"); | |
1590 | goto error; | |
e0c6ed95 | 1591 | } |
19f7b010 JJ |
1592 | if (p->regnum >= 24 |
1593 | && (insn->architecture | |
1594 | & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) | |
1595 | { | |
1596 | /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ | |
1597 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1598 | goto error; | |
1599 | } | |
252b5132 RH |
1600 | if (*args == '/') |
1601 | opcode |= (p->regnum << 14); | |
1602 | else | |
1603 | opcode |= (p->regnum << 25); | |
1604 | s += len; | |
1605 | continue; | |
1606 | } | |
1607 | else | |
1608 | { | |
19f7b010 | 1609 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1610 | goto error; |
1611 | } | |
1612 | ||
1613 | case 'M': | |
1614 | case 'm': | |
1615 | if (strncmp (s, "%asr", 4) == 0) | |
1616 | { | |
1617 | s += 4; | |
1618 | ||
1619 | if (isdigit ((unsigned char) *s)) | |
1620 | { | |
1621 | long num = 0; | |
1622 | ||
1623 | while (isdigit ((unsigned char) *s)) | |
1624 | { | |
1625 | num = num * 10 + *s - '0'; | |
1626 | ++s; | |
1627 | } | |
1628 | ||
1629 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1630 | { | |
1631 | if (num < 16 || 31 < num) | |
1632 | { | |
1633 | error_message = _(": asr number must be between 16 and 31"); | |
1634 | goto error; | |
1635 | } | |
1636 | } | |
1637 | else | |
1638 | { | |
1639 | if (num < 0 || 31 < num) | |
1640 | { | |
1641 | error_message = _(": asr number must be between 0 and 31"); | |
1642 | goto error; | |
1643 | } | |
1644 | } | |
1645 | ||
1646 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1647 | continue; | |
1648 | } | |
1649 | else | |
1650 | { | |
1651 | error_message = _(": expecting %asrN"); | |
1652 | goto error; | |
1653 | } | |
e0c6ed95 | 1654 | } /* if %asr */ |
252b5132 RH |
1655 | break; |
1656 | ||
1657 | case 'I': | |
1658 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1659 | goto immediate; | |
1660 | ||
1661 | case 'j': | |
1662 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1663 | goto immediate; | |
1664 | ||
1665 | case 'X': | |
1666 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1667 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1668 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1669 | else | |
1670 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1671 | /* These fields are unsigned, but for upward compatibility, | |
1672 | allow negative values as well. */ | |
1673 | goto immediate; | |
1674 | ||
1675 | case 'Y': | |
1676 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1677 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1678 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1679 | else | |
1680 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1681 | /* These fields are unsigned, but for upward compatibility, | |
1682 | allow negative values as well. */ | |
1683 | goto immediate; | |
1684 | ||
1685 | case 'k': | |
1686 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1687 | the_insn.pcrel = 1; | |
1688 | goto immediate; | |
1689 | ||
1690 | case 'G': | |
1691 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1692 | the_insn.pcrel = 1; | |
1693 | goto immediate; | |
1694 | ||
1695 | case 'N': | |
1696 | if (*s == 'p' && s[1] == 'n') | |
1697 | { | |
1698 | s += 2; | |
1699 | continue; | |
1700 | } | |
1701 | break; | |
1702 | ||
1703 | case 'T': | |
1704 | if (*s == 'p' && s[1] == 't') | |
1705 | { | |
1706 | s += 2; | |
1707 | continue; | |
1708 | } | |
1709 | break; | |
1710 | ||
1711 | case 'z': | |
1712 | if (*s == ' ') | |
1713 | { | |
1714 | ++s; | |
1715 | } | |
1716 | if (strncmp (s, "%icc", 4) == 0) | |
1717 | { | |
1718 | s += 4; | |
1719 | continue; | |
1720 | } | |
1721 | break; | |
1722 | ||
1723 | case 'Z': | |
1724 | if (*s == ' ') | |
1725 | { | |
1726 | ++s; | |
1727 | } | |
1728 | if (strncmp (s, "%xcc", 4) == 0) | |
1729 | { | |
1730 | s += 4; | |
1731 | continue; | |
1732 | } | |
1733 | break; | |
1734 | ||
1735 | case '6': | |
1736 | if (*s == ' ') | |
1737 | { | |
1738 | ++s; | |
1739 | } | |
1740 | if (strncmp (s, "%fcc0", 5) == 0) | |
1741 | { | |
1742 | s += 5; | |
1743 | continue; | |
1744 | } | |
1745 | break; | |
1746 | ||
1747 | case '7': | |
1748 | if (*s == ' ') | |
1749 | { | |
1750 | ++s; | |
1751 | } | |
1752 | if (strncmp (s, "%fcc1", 5) == 0) | |
1753 | { | |
1754 | s += 5; | |
1755 | continue; | |
1756 | } | |
1757 | break; | |
1758 | ||
1759 | case '8': | |
1760 | if (*s == ' ') | |
1761 | { | |
1762 | ++s; | |
1763 | } | |
1764 | if (strncmp (s, "%fcc2", 5) == 0) | |
1765 | { | |
1766 | s += 5; | |
1767 | continue; | |
1768 | } | |
1769 | break; | |
1770 | ||
1771 | case '9': | |
1772 | if (*s == ' ') | |
1773 | { | |
1774 | ++s; | |
1775 | } | |
1776 | if (strncmp (s, "%fcc3", 5) == 0) | |
1777 | { | |
1778 | s += 5; | |
1779 | continue; | |
1780 | } | |
1781 | break; | |
1782 | ||
1783 | case 'P': | |
1784 | if (strncmp (s, "%pc", 3) == 0) | |
1785 | { | |
1786 | s += 3; | |
1787 | continue; | |
1788 | } | |
1789 | break; | |
1790 | ||
1791 | case 'W': | |
1792 | if (strncmp (s, "%tick", 5) == 0) | |
1793 | { | |
1794 | s += 5; | |
1795 | continue; | |
1796 | } | |
1797 | break; | |
1798 | ||
e0c6ed95 | 1799 | case '\0': /* End of args. */ |
252b5132 RH |
1800 | if (*s == '\0') |
1801 | { | |
1802 | match = 1; | |
1803 | } | |
1804 | break; | |
1805 | ||
1806 | case '+': | |
1807 | if (*s == '+') | |
1808 | { | |
1809 | ++s; | |
1810 | continue; | |
1811 | } | |
1812 | if (*s == '-') | |
1813 | { | |
1814 | continue; | |
1815 | } | |
1816 | break; | |
1817 | ||
e0c6ed95 | 1818 | case '[': /* These must match exactly. */ |
252b5132 RH |
1819 | case ']': |
1820 | case ',': | |
1821 | case ' ': | |
1822 | if (*s++ == *args) | |
1823 | continue; | |
1824 | break; | |
1825 | ||
e0c6ed95 | 1826 | case '#': /* Must be at least one digit. */ |
252b5132 RH |
1827 | if (isdigit ((unsigned char) *s++)) |
1828 | { | |
1829 | while (isdigit ((unsigned char) *s)) | |
1830 | { | |
1831 | ++s; | |
1832 | } | |
1833 | continue; | |
1834 | } | |
1835 | break; | |
1836 | ||
e0c6ed95 | 1837 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
1838 | if (strncmp (s, "%csr", 4) == 0) |
1839 | { | |
1840 | s += 4; | |
1841 | continue; | |
1842 | } | |
1843 | break; | |
1844 | ||
e0c6ed95 | 1845 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
1846 | case 'c': |
1847 | case 'D': | |
1848 | if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s)) | |
1849 | { | |
1850 | mask = *s++; | |
1851 | if (isdigit ((unsigned char) *s)) | |
1852 | { | |
1853 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
1854 | if (mask >= 32) | |
1855 | { | |
1856 | break; | |
1857 | } | |
1858 | } | |
1859 | else | |
1860 | { | |
1861 | mask -= '0'; | |
1862 | } | |
1863 | switch (*args) | |
1864 | { | |
1865 | ||
1866 | case 'b': | |
1867 | opcode |= mask << 14; | |
1868 | continue; | |
1869 | ||
1870 | case 'c': | |
1871 | opcode |= mask; | |
1872 | continue; | |
1873 | ||
1874 | case 'D': | |
1875 | opcode |= mask << 25; | |
1876 | continue; | |
1877 | } | |
1878 | } | |
1879 | break; | |
1880 | ||
1881 | case 'r': /* next operand must be a register */ | |
1882 | case 'O': | |
1883 | case '1': | |
1884 | case '2': | |
1885 | case 'd': | |
1886 | if (*s++ == '%') | |
1887 | { | |
1888 | switch (c = *s++) | |
1889 | { | |
1890 | ||
1891 | case 'f': /* frame pointer */ | |
1892 | if (*s++ == 'p') | |
1893 | { | |
1894 | mask = 0x1e; | |
1895 | break; | |
1896 | } | |
1897 | goto error; | |
1898 | ||
1899 | case 'g': /* global register */ | |
a22b281c RH |
1900 | c = *s++; |
1901 | if (isoctal (c)) | |
252b5132 RH |
1902 | { |
1903 | mask = c - '0'; | |
1904 | break; | |
1905 | } | |
1906 | goto error; | |
1907 | ||
1908 | case 'i': /* in register */ | |
a22b281c RH |
1909 | c = *s++; |
1910 | if (isoctal (c)) | |
252b5132 RH |
1911 | { |
1912 | mask = c - '0' + 24; | |
1913 | break; | |
1914 | } | |
1915 | goto error; | |
1916 | ||
1917 | case 'l': /* local register */ | |
a22b281c RH |
1918 | c = *s++; |
1919 | if (isoctal (c)) | |
252b5132 RH |
1920 | { |
1921 | mask = (c - '0' + 16); | |
1922 | break; | |
1923 | } | |
1924 | goto error; | |
1925 | ||
1926 | case 'o': /* out register */ | |
a22b281c RH |
1927 | c = *s++; |
1928 | if (isoctal (c)) | |
252b5132 RH |
1929 | { |
1930 | mask = (c - '0' + 8); | |
1931 | break; | |
1932 | } | |
1933 | goto error; | |
1934 | ||
1935 | case 's': /* stack pointer */ | |
1936 | if (*s++ == 'p') | |
1937 | { | |
1938 | mask = 0xe; | |
1939 | break; | |
1940 | } | |
1941 | goto error; | |
1942 | ||
1943 | case 'r': /* any register */ | |
1944 | if (!isdigit ((unsigned char) (c = *s++))) | |
1945 | { | |
1946 | goto error; | |
1947 | } | |
1948 | /* FALLTHROUGH */ | |
1949 | case '0': | |
1950 | case '1': | |
1951 | case '2': | |
1952 | case '3': | |
1953 | case '4': | |
1954 | case '5': | |
1955 | case '6': | |
1956 | case '7': | |
1957 | case '8': | |
1958 | case '9': | |
1959 | if (isdigit ((unsigned char) *s)) | |
1960 | { | |
1961 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
1962 | { | |
1963 | goto error; | |
1964 | } | |
1965 | } | |
1966 | else | |
1967 | { | |
1968 | c -= '0'; | |
1969 | } | |
1970 | mask = c; | |
1971 | break; | |
1972 | ||
1973 | default: | |
1974 | goto error; | |
1975 | } | |
1976 | ||
6d8809aa | 1977 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 1978 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 1979 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 1980 | |
252b5132 RH |
1981 | /* Got the register, now figure out where |
1982 | it goes in the opcode. */ | |
1983 | switch (*args) | |
1984 | { | |
1985 | case '1': | |
1986 | opcode |= mask << 14; | |
1987 | continue; | |
1988 | ||
1989 | case '2': | |
1990 | opcode |= mask; | |
1991 | continue; | |
1992 | ||
1993 | case 'd': | |
1994 | opcode |= mask << 25; | |
1995 | continue; | |
1996 | ||
1997 | case 'r': | |
1998 | opcode |= (mask << 25) | (mask << 14); | |
1999 | continue; | |
2000 | ||
2001 | case 'O': | |
2002 | opcode |= (mask << 25) | (mask << 0); | |
2003 | continue; | |
2004 | } | |
2005 | } | |
2006 | break; | |
2007 | ||
2008 | case 'e': /* next operand is a floating point register */ | |
2009 | case 'v': | |
2010 | case 'V': | |
2011 | ||
2012 | case 'f': | |
2013 | case 'B': | |
2014 | case 'R': | |
2015 | ||
2016 | case 'g': | |
2017 | case 'H': | |
2018 | case 'J': | |
2019 | { | |
2020 | char format; | |
2021 | ||
2022 | if (*s++ == '%' | |
2023 | && ((format = *s) == 'f') | |
2024 | && isdigit ((unsigned char) *++s)) | |
2025 | { | |
2026 | for (mask = 0; isdigit ((unsigned char) *s); ++s) | |
2027 | { | |
2028 | mask = 10 * mask + (*s - '0'); | |
2029 | } /* read the number */ | |
2030 | ||
2031 | if ((*args == 'v' | |
2032 | || *args == 'B' | |
2033 | || *args == 'H') | |
2034 | && (mask & 1)) | |
2035 | { | |
2036 | break; | |
2037 | } /* register must be even numbered */ | |
2038 | ||
2039 | if ((*args == 'V' | |
2040 | || *args == 'R' | |
2041 | || *args == 'J') | |
2042 | && (mask & 3)) | |
2043 | { | |
2044 | break; | |
2045 | } /* register must be multiple of 4 */ | |
2046 | ||
2047 | if (mask >= 64) | |
2048 | { | |
2049 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2050 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2051 | else | |
2052 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2053 | goto error; | |
2054 | } /* on error */ | |
2055 | else if (mask >= 32) | |
2056 | { | |
2057 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2058 | { | |
2059 | v9_arg_p = 1; | |
2060 | mask -= 31; /* wrap high bit */ | |
2061 | } | |
2062 | else | |
2063 | { | |
2064 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2065 | goto error; | |
2066 | } | |
2067 | } | |
2068 | } | |
2069 | else | |
2070 | { | |
2071 | break; | |
ab3e48dc | 2072 | } /* if not an 'f' register. */ |
252b5132 RH |
2073 | |
2074 | switch (*args) | |
2075 | { | |
2076 | case 'v': | |
2077 | case 'V': | |
2078 | case 'e': | |
2079 | opcode |= RS1 (mask); | |
2080 | continue; | |
2081 | ||
252b5132 RH |
2082 | case 'f': |
2083 | case 'B': | |
2084 | case 'R': | |
2085 | opcode |= RS2 (mask); | |
2086 | continue; | |
2087 | ||
2088 | case 'g': | |
2089 | case 'H': | |
2090 | case 'J': | |
2091 | opcode |= RD (mask); | |
2092 | continue; | |
ab3e48dc | 2093 | } /* Pack it in. */ |
252b5132 RH |
2094 | |
2095 | know (0); | |
2096 | break; | |
ab3e48dc | 2097 | } /* float arg */ |
252b5132 RH |
2098 | |
2099 | case 'F': | |
2100 | if (strncmp (s, "%fsr", 4) == 0) | |
2101 | { | |
2102 | s += 4; | |
2103 | continue; | |
2104 | } | |
2105 | break; | |
2106 | ||
ab3e48dc KH |
2107 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2108 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2109 | goto immediate; |
2110 | ||
ab3e48dc | 2111 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2112 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2113 | the_insn.pcrel = 1; | |
2114 | goto immediate; | |
2115 | ||
ab3e48dc | 2116 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2117 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2118 | the_insn.pcrel = 1; | |
2119 | goto immediate; | |
2120 | ||
63fab58c | 2121 | case 'h': |
ab3e48dc | 2122 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2123 | the_insn.reloc = BFD_RELOC_SPARC22; |
2124 | goto immediate; | |
2125 | ||
ab3e48dc | 2126 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2127 | the_insn.reloc = BFD_RELOC_SPARC13; |
2128 | ||
2129 | /* fallthrough */ | |
2130 | ||
2131 | immediate: | |
2132 | if (*s == ' ') | |
2133 | s++; | |
2134 | ||
cf9a1301 RH |
2135 | { |
2136 | char *s1; | |
2137 | char *op_arg = NULL; | |
2138 | expressionS op_exp; | |
2139 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; | |
2140 | ||
2141 | /* Check for %hi, etc. */ | |
2142 | if (*s == '%') | |
2143 | { | |
2144 | static const struct ops { | |
2145 | /* The name as it appears in assembler. */ | |
2146 | char *name; | |
2147 | /* strlen (name), precomputed for speed */ | |
2148 | int len; | |
2149 | /* The reloc this pseudo-op translates to. */ | |
2150 | int reloc; | |
2151 | /* Non-zero if for v9 only. */ | |
2152 | int v9_p; | |
2153 | /* Non-zero if can be used in pc-relative contexts. */ | |
2154 | int pcrel_p;/*FIXME:wip*/ | |
2155 | } ops[] = { | |
2156 | /* hix/lox must appear before hi/lo so %hix won't be | |
2157 | mistaken for %hi. */ | |
2158 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2159 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2160 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2161 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
2162 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, | |
2163 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2164 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2165 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, | |
2166 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2167 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2168 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2169 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
c2158c24 | 2170 | { NULL, 0, 0, 0, 0 } |
cf9a1301 RH |
2171 | }; |
2172 | const struct ops *o; | |
e0c6ed95 | 2173 | |
cf9a1301 RH |
2174 | for (o = ops; o->name; o++) |
2175 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2176 | break; | |
2177 | if (o->name == NULL) | |
252b5132 | 2178 | break; |
e0c6ed95 | 2179 | |
cf9a1301 RH |
2180 | if (s[o->len + 1] != '(') |
2181 | { | |
2182 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2183 | return special_case; |
cf9a1301 | 2184 | } |
252b5132 | 2185 | |
cf9a1301 RH |
2186 | op_arg = o->name; |
2187 | the_insn.reloc = o->reloc; | |
2188 | s += o->len + 2; | |
2189 | v9_arg_p = o->v9_p; | |
2190 | } | |
2191 | ||
2192 | /* Note that if the get_expression() fails, we will still | |
2193 | have created U entries in the symbol table for the | |
2194 | 'symbols' in the input string. Try not to create U | |
2195 | symbols for registers, etc. */ | |
252b5132 | 2196 | |
252b5132 RH |
2197 | /* This stuff checks to see if the expression ends in |
2198 | +%reg. If it does, it removes the register from | |
2199 | the expression, and re-sets 's' to point to the | |
2200 | right place. */ | |
2201 | ||
cf9a1301 RH |
2202 | if (op_arg) |
2203 | { | |
2204 | int npar = 0; | |
2205 | ||
2206 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2207 | if (*s1 == '(') | |
2208 | npar++; | |
2209 | else if (*s1 == ')') | |
2210 | { | |
2211 | if (!npar) | |
2212 | break; | |
2213 | npar--; | |
2214 | } | |
2215 | ||
2216 | if (*s1 != ')') | |
2217 | { | |
2218 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2219 | return special_case; |
cf9a1301 | 2220 | } |
e0c6ed95 | 2221 | |
cf9a1301 RH |
2222 | *s1 = '\0'; |
2223 | (void) get_expression (s); | |
2224 | *s1 = ')'; | |
2225 | s = s1 + 1; | |
2226 | if (*s == ',' || *s == ']' || !*s) | |
2227 | continue; | |
2228 | if (*s != '+' && *s != '-') | |
2229 | { | |
2230 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2231 | return special_case; |
cf9a1301 RH |
2232 | } |
2233 | *s1 = '0'; | |
2234 | s = s1; | |
2235 | op_exp = the_insn.exp; | |
e0c6ed95 | 2236 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2237 | } |
252b5132 | 2238 | |
e0c6ed95 AM |
2239 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2240 | ; | |
252b5132 RH |
2241 | |
2242 | if (s1 != s && isdigit ((unsigned char) s1[-1])) | |
2243 | { | |
2244 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 RH |
2245 | s1 -= 3; |
2246 | else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') | |
2247 | s1 -= 4; | |
2248 | else | |
2249 | s1 = NULL; | |
2250 | if (s1) | |
252b5132 | 2251 | { |
252b5132 | 2252 | *s1 = '\0'; |
1eb7027c RH |
2253 | if (op_arg && s1 == s + 1) |
2254 | the_insn.exp.X_op = O_absent; | |
2255 | else | |
2256 | (void) get_expression (s); | |
252b5132 | 2257 | *s1 = '+'; |
cf9a1301 RH |
2258 | if (op_arg) |
2259 | *s = ')'; | |
252b5132 | 2260 | s = s1; |
252b5132 | 2261 | } |
cf9a1301 RH |
2262 | } |
2263 | else | |
2264 | s1 = NULL; | |
2265 | ||
2266 | if (!s1) | |
2267 | { | |
2268 | (void) get_expression (s); | |
2269 | if (op_arg) | |
2270 | *s = ')'; | |
2271 | s = expr_end; | |
2272 | } | |
2273 | ||
2274 | if (op_arg) | |
2275 | { | |
2276 | the_insn.exp2 = the_insn.exp; | |
2277 | the_insn.exp = op_exp; | |
2278 | if (the_insn.exp2.X_op == O_absent) | |
2279 | the_insn.exp2.X_op = O_illegal; | |
2280 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2281 | { |
cf9a1301 RH |
2282 | the_insn.exp = the_insn.exp2; |
2283 | the_insn.exp2.X_op = O_illegal; | |
2284 | } | |
2285 | else if (the_insn.exp.X_op == O_constant) | |
2286 | { | |
2287 | valueT val = the_insn.exp.X_add_number; | |
2288 | switch (the_insn.reloc) | |
2289 | { | |
1b50c718 ILT |
2290 | default: |
2291 | break; | |
2292 | ||
cf9a1301 RH |
2293 | case BFD_RELOC_SPARC_HH22: |
2294 | val = BSR (val, 32); | |
e0c6ed95 | 2295 | /* Fall through. */ |
cf9a1301 RH |
2296 | |
2297 | case BFD_RELOC_SPARC_LM22: | |
2298 | case BFD_RELOC_HI22: | |
2299 | val = (val >> 10) & 0x3fffff; | |
2300 | break; | |
2301 | ||
2302 | case BFD_RELOC_SPARC_HM10: | |
2303 | val = BSR (val, 32); | |
e0c6ed95 | 2304 | /* Fall through. */ |
cf9a1301 RH |
2305 | |
2306 | case BFD_RELOC_LO10: | |
2307 | val &= 0x3ff; | |
2308 | break; | |
2309 | ||
2310 | case BFD_RELOC_SPARC_H44: | |
2311 | val >>= 22; | |
2312 | val &= 0x3fffff; | |
2313 | break; | |
2314 | ||
2315 | case BFD_RELOC_SPARC_M44: | |
2316 | val >>= 12; | |
2317 | val &= 0x3ff; | |
2318 | break; | |
2319 | ||
2320 | case BFD_RELOC_SPARC_L44: | |
2321 | val &= 0xfff; | |
2322 | break; | |
2323 | ||
2324 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2325 | val = ~val; |
cf9a1301 RH |
2326 | val = (val >> 10) & 0x3fffff; |
2327 | break; | |
2328 | ||
2329 | case BFD_RELOC_SPARC_LOX10: | |
2330 | val = (val & 0x3ff) | 0x1c00; | |
2331 | break; | |
2332 | } | |
2333 | the_insn.exp = the_insn.exp2; | |
2334 | the_insn.exp.X_add_number += val; | |
2335 | the_insn.exp2.X_op = O_illegal; | |
2336 | the_insn.reloc = old_reloc; | |
2337 | } | |
2338 | else if (the_insn.exp2.X_op != O_constant) | |
2339 | { | |
2340 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2341 | return special_case; |
cf9a1301 RH |
2342 | } |
2343 | else | |
2344 | { | |
dabe3bbc | 2345 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2346 | || the_insn.reloc != BFD_RELOC_LO10 |
2347 | || sparc_arch_size != 64 | |
2348 | || sparc_pic_code) | |
2349 | { | |
2350 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2351 | return special_case; |
cf9a1301 RH |
2352 | } |
2353 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2354 | } |
2355 | } | |
2356 | } | |
252b5132 RH |
2357 | /* Check for constants that don't require emitting a reloc. */ |
2358 | if (the_insn.exp.X_op == O_constant | |
2359 | && the_insn.exp.X_add_symbol == 0 | |
2360 | && the_insn.exp.X_op_symbol == 0) | |
2361 | { | |
2362 | /* For pc-relative call instructions, we reject | |
2363 | constants to get better code. */ | |
2364 | if (the_insn.pcrel | |
2365 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2366 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2367 | { | |
2368 | error_message = _(": PC-relative operand can't be a constant"); | |
2369 | goto error; | |
2370 | } | |
2371 | ||
2372 | /* Constants that won't fit are checked in md_apply_fix3 | |
2373 | and bfd_install_relocation. | |
2374 | ??? It would be preferable to install the constants | |
2375 | into the insn here and save having to create a fixS | |
2376 | for each one. There already exists code to handle | |
2377 | all the various cases (e.g. in md_apply_fix3 and | |
2378 | bfd_install_relocation) so duplicating all that code | |
2379 | here isn't right. */ | |
2380 | } | |
2381 | ||
2382 | continue; | |
2383 | ||
2384 | case 'a': | |
2385 | if (*s++ == 'a') | |
2386 | { | |
2387 | opcode |= ANNUL; | |
2388 | continue; | |
2389 | } | |
2390 | break; | |
2391 | ||
2392 | case 'A': | |
2393 | { | |
2394 | int asi = 0; | |
2395 | ||
2396 | /* Parse an asi. */ | |
2397 | if (*s == '#') | |
2398 | { | |
2399 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2400 | { | |
2401 | error_message = _(": invalid ASI name"); | |
2402 | goto error; | |
2403 | } | |
2404 | } | |
2405 | else | |
2406 | { | |
2407 | if (! parse_const_expr_arg (&s, &asi)) | |
2408 | { | |
2409 | error_message = _(": invalid ASI expression"); | |
2410 | goto error; | |
2411 | } | |
2412 | if (asi < 0 || asi > 255) | |
2413 | { | |
2414 | error_message = _(": invalid ASI number"); | |
2415 | goto error; | |
2416 | } | |
2417 | } | |
2418 | opcode |= ASI (asi); | |
2419 | continue; | |
e0c6ed95 | 2420 | } /* Alternate space. */ |
252b5132 RH |
2421 | |
2422 | case 'p': | |
2423 | if (strncmp (s, "%psr", 4) == 0) | |
2424 | { | |
2425 | s += 4; | |
2426 | continue; | |
2427 | } | |
2428 | break; | |
2429 | ||
e0c6ed95 | 2430 | case 'q': /* Floating point queue. */ |
252b5132 RH |
2431 | if (strncmp (s, "%fq", 3) == 0) |
2432 | { | |
2433 | s += 3; | |
2434 | continue; | |
2435 | } | |
2436 | break; | |
2437 | ||
e0c6ed95 | 2438 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
2439 | if (strncmp (s, "%cq", 3) == 0) |
2440 | { | |
2441 | s += 3; | |
2442 | continue; | |
2443 | } | |
2444 | break; | |
2445 | ||
2446 | case 'S': | |
2447 | if (strcmp (str, "set") == 0 | |
2448 | || strcmp (str, "setuw") == 0) | |
2449 | { | |
2450 | special_case = SPECIAL_CASE_SET; | |
2451 | continue; | |
2452 | } | |
2453 | else if (strcmp (str, "setsw") == 0) | |
2454 | { | |
2455 | special_case = SPECIAL_CASE_SETSW; | |
2456 | continue; | |
2457 | } | |
2458 | else if (strcmp (str, "setx") == 0) | |
2459 | { | |
2460 | special_case = SPECIAL_CASE_SETX; | |
2461 | continue; | |
2462 | } | |
2463 | else if (strncmp (str, "fdiv", 4) == 0) | |
2464 | { | |
2465 | special_case = SPECIAL_CASE_FDIV; | |
2466 | continue; | |
2467 | } | |
2468 | break; | |
2469 | ||
2470 | case 'o': | |
2471 | if (strncmp (s, "%asi", 4) != 0) | |
2472 | break; | |
2473 | s += 4; | |
2474 | continue; | |
2475 | ||
2476 | case 's': | |
2477 | if (strncmp (s, "%fprs", 5) != 0) | |
2478 | break; | |
2479 | s += 5; | |
2480 | continue; | |
2481 | ||
2482 | case 'E': | |
2483 | if (strncmp (s, "%ccr", 4) != 0) | |
2484 | break; | |
2485 | s += 4; | |
2486 | continue; | |
2487 | ||
2488 | case 't': | |
2489 | if (strncmp (s, "%tbr", 4) != 0) | |
2490 | break; | |
2491 | s += 4; | |
2492 | continue; | |
2493 | ||
2494 | case 'w': | |
2495 | if (strncmp (s, "%wim", 4) != 0) | |
2496 | break; | |
2497 | s += 4; | |
2498 | continue; | |
2499 | ||
2500 | case 'x': | |
2501 | { | |
2502 | char *push = input_line_pointer; | |
2503 | expressionS e; | |
2504 | ||
2505 | input_line_pointer = s; | |
2506 | expression (&e); | |
2507 | if (e.X_op == O_constant) | |
2508 | { | |
2509 | int n = e.X_add_number; | |
2510 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2511 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2512 | else | |
2513 | opcode |= e.X_add_number << 5; | |
2514 | } | |
2515 | else | |
2516 | as_bad (_("non-immediate OPF operand, ignored")); | |
2517 | s = input_line_pointer; | |
2518 | input_line_pointer = push; | |
2519 | continue; | |
2520 | } | |
2521 | ||
2522 | case 'y': | |
2523 | if (strncmp (s, "%y", 2) != 0) | |
2524 | break; | |
2525 | s += 2; | |
2526 | continue; | |
2527 | ||
2528 | case 'u': | |
2529 | case 'U': | |
2530 | { | |
2531 | /* Parse a sparclet cpreg. */ | |
2532 | int cpreg; | |
2533 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2534 | { | |
2535 | error_message = _(": invalid cpreg name"); | |
2536 | goto error; | |
2537 | } | |
2538 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2539 | continue; | |
2540 | } | |
2541 | ||
2542 | default: | |
2543 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 2544 | } /* switch on arg code. */ |
252b5132 RH |
2545 | |
2546 | /* Break out of for() loop. */ | |
2547 | break; | |
e0c6ed95 | 2548 | } /* For each arg that we expect. */ |
252b5132 RH |
2549 | |
2550 | error: | |
2551 | if (match == 0) | |
2552 | { | |
e0c6ed95 | 2553 | /* Args don't match. */ |
252b5132 RH |
2554 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
2555 | && (insn->name == insn[1].name | |
2556 | || !strcmp (insn->name, insn[1].name))) | |
2557 | { | |
2558 | ++insn; | |
2559 | s = argsStart; | |
2560 | continue; | |
2561 | } | |
2562 | else | |
2563 | { | |
2564 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 2565 | return special_case; |
252b5132 RH |
2566 | } |
2567 | } | |
2568 | else | |
2569 | { | |
e0c6ed95 | 2570 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 RH |
2571 | int needed_arch_mask = insn->architecture; |
2572 | ||
2573 | if (v9_arg_p) | |
2574 | { | |
19f7b010 JJ |
2575 | needed_arch_mask &= |
2576 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
2577 | if (! needed_arch_mask) | |
2578 | needed_arch_mask = | |
2579 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
2580 | } |
2581 | ||
e0c6ed95 AM |
2582 | if (needed_arch_mask |
2583 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2584 | /* OK. */ | |
2585 | ; | |
252b5132 | 2586 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
2587 | else if (needed_arch_mask |
2588 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
2589 | { |
2590 | enum sparc_opcode_arch_val needed_architecture = | |
2591 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2592 | & needed_arch_mask); | |
2593 | ||
2594 | assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); | |
2595 | if (warn_on_bump | |
2596 | && needed_architecture > warn_after_architecture) | |
2597 | { | |
2598 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
2599 | sparc_opcode_archs[current_architecture].name, | |
2600 | sparc_opcode_archs[needed_architecture].name, | |
2601 | str); | |
2602 | warn_after_architecture = needed_architecture; | |
2603 | } | |
2604 | current_architecture = needed_architecture; | |
2605 | } | |
2606 | /* Conflict. */ | |
2607 | /* ??? This seems to be a bit fragile. What if the next entry in | |
2608 | the opcode table is the one we want and it is supported? | |
2609 | It is possible to arrange the table today so that this can't | |
2610 | happen but what about tomorrow? */ | |
2611 | else | |
2612 | { | |
e0c6ed95 | 2613 | int arch, printed_one_p = 0; |
252b5132 RH |
2614 | char *p; |
2615 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2616 | ||
2617 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 2618 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
2619 | p = required_archs; |
2620 | arch = sparc_ffs (needed_arch_mask); | |
2621 | while ((1 << arch) <= needed_arch_mask) | |
2622 | { | |
2623 | if ((1 << arch) & needed_arch_mask) | |
2624 | { | |
2625 | if (printed_one_p) | |
2626 | *p++ = '|'; | |
2627 | strcpy (p, sparc_opcode_archs[arch].name); | |
2628 | p += strlen (p); | |
2629 | printed_one_p = 1; | |
2630 | } | |
2631 | ++arch; | |
2632 | } | |
2633 | ||
2634 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
2635 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
2636 | required_archs, | |
2637 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 2638 | return special_case; |
252b5132 | 2639 | } |
e0c6ed95 | 2640 | } /* If no match. */ |
252b5132 RH |
2641 | |
2642 | break; | |
e0c6ed95 | 2643 | } /* Forever looking for a match. */ |
252b5132 RH |
2644 | |
2645 | the_insn.opcode = opcode; | |
a22b281c | 2646 | return special_case; |
252b5132 RH |
2647 | } |
2648 | ||
2649 | /* Parse an argument that can be expressed as a keyword. | |
2650 | (eg: #StoreStore or %ccfr). | |
2651 | The result is a boolean indicating success. | |
2652 | If successful, INPUT_POINTER is updated. */ | |
2653 | ||
2654 | static int | |
2655 | parse_keyword_arg (lookup_fn, input_pointerP, valueP) | |
2656 | int (*lookup_fn) PARAMS ((const char *)); | |
2657 | char **input_pointerP; | |
2658 | int *valueP; | |
2659 | { | |
2660 | int value; | |
2661 | char c, *p, *q; | |
2662 | ||
2663 | p = *input_pointerP; | |
2664 | for (q = p + (*p == '#' || *p == '%'); | |
2665 | isalnum ((unsigned char) *q) || *q == '_'; | |
2666 | ++q) | |
2667 | continue; | |
2668 | c = *q; | |
2669 | *q = 0; | |
2670 | value = (*lookup_fn) (p); | |
2671 | *q = c; | |
2672 | if (value == -1) | |
2673 | return 0; | |
2674 | *valueP = value; | |
2675 | *input_pointerP = q; | |
2676 | return 1; | |
2677 | } | |
2678 | ||
2679 | /* Parse an argument that is a constant expression. | |
2680 | The result is a boolean indicating success. */ | |
2681 | ||
2682 | static int | |
2683 | parse_const_expr_arg (input_pointerP, valueP) | |
2684 | char **input_pointerP; | |
2685 | int *valueP; | |
2686 | { | |
2687 | char *save = input_line_pointer; | |
2688 | expressionS exp; | |
2689 | ||
2690 | input_line_pointer = *input_pointerP; | |
2691 | /* The next expression may be something other than a constant | |
2692 | (say if we're not processing the right variant of the insn). | |
2693 | Don't call expression unless we're sure it will succeed as it will | |
2694 | signal an error (which we want to defer until later). */ | |
2695 | /* FIXME: It might be better to define md_operand and have it recognize | |
2696 | things like %asi, etc. but continuing that route through to the end | |
2697 | is a lot of work. */ | |
2698 | if (*input_line_pointer == '%') | |
2699 | { | |
2700 | input_line_pointer = save; | |
2701 | return 0; | |
2702 | } | |
2703 | expression (&exp); | |
2704 | *input_pointerP = input_line_pointer; | |
2705 | input_line_pointer = save; | |
2706 | if (exp.X_op != O_constant) | |
2707 | return 0; | |
2708 | *valueP = exp.X_add_number; | |
2709 | return 1; | |
2710 | } | |
2711 | ||
2712 | /* Subroutine of sparc_ip to parse an expression. */ | |
2713 | ||
2714 | static int | |
2715 | get_expression (str) | |
2716 | char *str; | |
2717 | { | |
2718 | char *save_in; | |
2719 | segT seg; | |
2720 | ||
2721 | save_in = input_line_pointer; | |
2722 | input_line_pointer = str; | |
2723 | seg = expression (&the_insn.exp); | |
2724 | if (seg != absolute_section | |
2725 | && seg != text_section | |
2726 | && seg != data_section | |
2727 | && seg != bss_section | |
2728 | && seg != undefined_section) | |
2729 | { | |
2730 | the_insn.error = _("bad segment"); | |
2731 | expr_end = input_line_pointer; | |
2732 | input_line_pointer = save_in; | |
2733 | return 1; | |
2734 | } | |
2735 | expr_end = input_line_pointer; | |
2736 | input_line_pointer = save_in; | |
2737 | return 0; | |
2738 | } | |
2739 | ||
2740 | /* Subroutine of md_assemble to output one insn. */ | |
2741 | ||
2742 | static void | |
2743 | output_insn (insn, the_insn) | |
2744 | const struct sparc_opcode *insn; | |
2745 | struct sparc_it *the_insn; | |
2746 | { | |
2747 | char *toP = frag_more (4); | |
2748 | ||
e0c6ed95 | 2749 | /* Put out the opcode. */ |
252b5132 RH |
2750 | if (INSN_BIG_ENDIAN) |
2751 | number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); | |
2752 | else | |
2753 | number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); | |
2754 | ||
e0c6ed95 | 2755 | /* Put out the symbol-dependent stuff. */ |
252b5132 RH |
2756 | if (the_insn->reloc != BFD_RELOC_NONE) |
2757 | { | |
e0c6ed95 AM |
2758 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
2759 | (toP - frag_now->fr_literal), /* Where. */ | |
2760 | 4, /* Size. */ | |
252b5132 RH |
2761 | &the_insn->exp, |
2762 | the_insn->pcrel, | |
2763 | the_insn->reloc); | |
2764 | /* Turn off overflow checking in fixup_segment. We'll do our | |
2765 | own overflow checking in md_apply_fix3. This is necessary because | |
2766 | the insn size is 4 and fixup_segment will signal an overflow for | |
2767 | large 8 byte quantities. */ | |
2768 | fixP->fx_no_overflow = 1; | |
dabe3bbc RH |
2769 | if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) |
2770 | fixP->tc_fix_data = the_insn->exp2.X_add_number; | |
252b5132 RH |
2771 | } |
2772 | ||
2773 | last_insn = insn; | |
2774 | last_opcode = the_insn->opcode; | |
732d96b6 JJ |
2775 | |
2776 | #ifdef OBJ_ELF | |
2777 | dwarf2_emit_insn (4); | |
2778 | #endif | |
252b5132 RH |
2779 | } |
2780 | \f | |
e0c6ed95 AM |
2781 | /* This is identical to the md_atof in m68k.c. I think this is right, |
2782 | but I'm not sure. | |
252b5132 | 2783 | |
e0c6ed95 AM |
2784 | Turn a string in input_line_pointer into a floating point constant |
2785 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2786 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
2787 | returned, or NULL on OK. */ | |
252b5132 | 2788 | |
e0c6ed95 | 2789 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
2790 | #define MAX_LITTLENUMS 6 |
2791 | ||
2792 | char * | |
2793 | md_atof (type, litP, sizeP) | |
2794 | char type; | |
2795 | char *litP; | |
2796 | int *sizeP; | |
2797 | { | |
e0c6ed95 | 2798 | int i, prec; |
252b5132 RH |
2799 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
2800 | char *t; | |
2801 | ||
2802 | switch (type) | |
2803 | { | |
2804 | case 'f': | |
2805 | case 'F': | |
2806 | case 's': | |
2807 | case 'S': | |
2808 | prec = 2; | |
2809 | break; | |
2810 | ||
2811 | case 'd': | |
2812 | case 'D': | |
2813 | case 'r': | |
2814 | case 'R': | |
2815 | prec = 4; | |
2816 | break; | |
2817 | ||
2818 | case 'x': | |
2819 | case 'X': | |
2820 | prec = 6; | |
2821 | break; | |
2822 | ||
2823 | case 'p': | |
2824 | case 'P': | |
2825 | prec = 6; | |
2826 | break; | |
2827 | ||
2828 | default: | |
2829 | *sizeP = 0; | |
2830 | return _("Bad call to MD_ATOF()"); | |
2831 | } | |
2832 | ||
2833 | t = atof_ieee (input_line_pointer, type, words); | |
2834 | if (t) | |
2835 | input_line_pointer = t; | |
2836 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
2837 | ||
2838 | if (target_big_endian) | |
2839 | { | |
2840 | for (i = 0; i < prec; i++) | |
2841 | { | |
ab3e48dc KH |
2842 | md_number_to_chars (litP, (valueT) words[i], |
2843 | sizeof (LITTLENUM_TYPE)); | |
252b5132 RH |
2844 | litP += sizeof (LITTLENUM_TYPE); |
2845 | } | |
2846 | } | |
2847 | else | |
2848 | { | |
2849 | for (i = prec - 1; i >= 0; i--) | |
2850 | { | |
ab3e48dc KH |
2851 | md_number_to_chars (litP, (valueT) words[i], |
2852 | sizeof (LITTLENUM_TYPE)); | |
252b5132 RH |
2853 | litP += sizeof (LITTLENUM_TYPE); |
2854 | } | |
2855 | } | |
e0c6ed95 | 2856 | |
252b5132 RH |
2857 | return 0; |
2858 | } | |
2859 | ||
2860 | /* Write a value out to the object file, using the appropriate | |
2861 | endianness. */ | |
2862 | ||
2863 | void | |
2864 | md_number_to_chars (buf, val, n) | |
2865 | char *buf; | |
2866 | valueT val; | |
2867 | int n; | |
2868 | { | |
2869 | if (target_big_endian) | |
2870 | number_to_chars_bigendian (buf, val, n); | |
2871 | else if (target_little_endian_data | |
2872 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
2873 | /* Output debug words, which are not in allocated sections, as big |
2874 | endian. */ | |
252b5132 RH |
2875 | number_to_chars_bigendian (buf, val, n); |
2876 | else if (target_little_endian_data || ! target_big_endian) | |
2877 | number_to_chars_littleendian (buf, val, n); | |
2878 | } | |
2879 | \f | |
2880 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 2881 | hold. */ |
252b5132 RH |
2882 | |
2883 | int | |
2884 | md_apply_fix3 (fixP, value, segment) | |
2885 | fixS *fixP; | |
2886 | valueT *value; | |
2887 | segT segment; | |
2888 | { | |
2889 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
2890 | offsetT val; | |
2891 | long insn; | |
2892 | ||
2893 | val = *value; | |
2894 | ||
2895 | assert (fixP->fx_r_type < BFD_RELOC_UNUSED); | |
2896 | ||
e0c6ed95 | 2897 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
2898 | |
2899 | #ifdef OBJ_ELF | |
2900 | /* FIXME: SPARC ELF relocations don't use an addend in the data | |
2901 | field itself. This whole approach should be somehow combined | |
2902 | with the calls to bfd_install_relocation. Also, the value passed | |
2903 | in by fixup_segment includes the value of a defined symbol. We | |
2904 | don't want to include the value of an externally visible symbol. */ | |
2905 | if (fixP->fx_addsy != NULL) | |
2906 | { | |
49309057 | 2907 | if (symbol_used_in_reloc_p (fixP->fx_addsy) |
252b5132 RH |
2908 | && (S_IS_EXTERNAL (fixP->fx_addsy) |
2909 | || S_IS_WEAK (fixP->fx_addsy) | |
2910 | || (sparc_pic_code && ! fixP->fx_pcrel) | |
2911 | || (S_GET_SEGMENT (fixP->fx_addsy) != segment | |
2912 | && ((bfd_get_section_flags (stdoutput, | |
2913 | S_GET_SEGMENT (fixP->fx_addsy)) | |
2914 | & SEC_LINK_ONCE) != 0 | |
2915 | || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
2916 | ".gnu.linkonce", | |
2917 | sizeof ".gnu.linkonce" - 1) == 0))) | |
2918 | && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section | |
2919 | && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section | |
2920 | && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
2921 | fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy); | |
2922 | return 1; | |
2923 | } | |
2924 | #endif | |
2925 | ||
2926 | /* This is a hack. There should be a better way to | |
2927 | handle this. Probably in terms of howto fields, once | |
2928 | we can look at these fixups in terms of howtos. */ | |
2929 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
2930 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
2931 | ||
2932 | #ifdef OBJ_AOUT | |
2933 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
2934 | generate a reloc, then we just want to let the reloc addend set | |
2935 | the value. We do not want to also stuff the addend into the | |
2936 | object file. Including the addend in the object file works when | |
2937 | doing a static link, because the linker will ignore the object | |
2938 | file contents. However, the dynamic linker does not ignore the | |
2939 | object file contents. */ | |
2940 | if (fixP->fx_addsy != NULL | |
2941 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
2942 | val = 0; | |
2943 | ||
2944 | /* When generating PIC code, we do not want an addend for a reloc | |
2945 | against a local symbol. We adjust fx_addnumber to cancel out the | |
2946 | value already included in val, and to also cancel out the | |
2947 | adjustment which bfd_install_relocation will create. */ | |
2948 | if (sparc_pic_code | |
2949 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
2950 | && fixP->fx_addsy != NULL | |
2951 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 2952 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
2953 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
2954 | ||
2955 | /* When generating PIC code, we need to fiddle to get | |
2956 | bfd_install_relocation to do the right thing for a PC relative | |
2957 | reloc against a local symbol which we are going to keep. */ | |
2958 | if (sparc_pic_code | |
2959 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
2960 | && fixP->fx_addsy != NULL | |
2961 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
2962 | || S_IS_WEAK (fixP->fx_addsy)) | |
2963 | && S_IS_DEFINED (fixP->fx_addsy) | |
2964 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
2965 | { | |
2966 | val = 0; | |
2967 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
2968 | } | |
2969 | #endif | |
2970 | ||
2971 | /* If this is a data relocation, just output VAL. */ | |
2972 | ||
2973 | if (fixP->fx_r_type == BFD_RELOC_16) | |
2974 | { | |
2975 | md_number_to_chars (buf, val, 2); | |
2976 | } | |
2977 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
2978 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) | |
2979 | { | |
2980 | md_number_to_chars (buf, val, 4); | |
2981 | } | |
2982 | else if (fixP->fx_r_type == BFD_RELOC_64) | |
2983 | { | |
2984 | md_number_to_chars (buf, val, 8); | |
2985 | } | |
e0c6ed95 | 2986 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
2987 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
2988 | { | |
2989 | fixP->fx_done = 0; | |
2990 | return 1; | |
2991 | } | |
2992 | else | |
2993 | { | |
2994 | /* It's a relocation against an instruction. */ | |
2995 | ||
2996 | if (INSN_BIG_ENDIAN) | |
2997 | insn = bfd_getb32 ((unsigned char *) buf); | |
2998 | else | |
2999 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3000 | |
252b5132 RH |
3001 | switch (fixP->fx_r_type) |
3002 | { | |
3003 | case BFD_RELOC_32_PCREL_S2: | |
3004 | val = val >> 2; | |
3005 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3006 | being done! */ | |
3007 | if (! sparc_pic_code | |
3008 | || fixP->fx_addsy == NULL | |
49309057 | 3009 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3010 | ++val; |
6faf3d66 | 3011 | |
252b5132 | 3012 | insn |= val & 0x3fffffff; |
6faf3d66 | 3013 | |
e0c6ed95 | 3014 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3015 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3016 | { | |
3017 | #define G0 0 | |
3018 | #define O7 15 | |
3019 | #define XCC (2 << 20) | |
3020 | #define COND(x) (((x)&0xf)<<25) | |
3021 | #define CONDA COND(0x8) | |
3022 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3023 | #define INSN_BA (F2(0,2) | CONDA) | |
3024 | #define INSN_OR F3(2, 0x2, 0) | |
3025 | #define INSN_NOP F2(0,4) | |
3026 | ||
3027 | long delay; | |
3028 | ||
3029 | /* If the instruction is a call with either: | |
3030 | restore | |
3031 | arithmetic instruction with rd == %o7 | |
3032 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3033 | then we can optimize if the call destination is near | |
3034 | by changing the call into a branch always. */ | |
3035 | if (INSN_BIG_ENDIAN) | |
3036 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3037 | else | |
3038 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3039 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3040 | break; |
e0c6ed95 AM |
3041 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3042 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3043 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3044 | break; |
e0c6ed95 AM |
3045 | if ((delay & RS1 (~0)) == RS1 (O7) |
3046 | || ((delay & F3I (~0)) == 0 | |
3047 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3048 | break; |
3049 | /* Ensure the branch will fit into simm22. */ | |
3050 | if ((val & 0x3fe00000) | |
3051 | && (val & 0x3fe00000) != 0x3fe00000) | |
3052 | break; | |
3053 | /* Check if the arch is v9 and branch will fit | |
3054 | into simm19. */ | |
3055 | if (((val & 0x3c0000) == 0 | |
3056 | || (val & 0x3c0000) == 0x3c0000) | |
3057 | && (sparc_arch_size == 64 | |
3058 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3059 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3060 | insn = INSN_BPA | (val & 0x7ffff); |
3061 | else | |
e0c6ed95 | 3062 | /* ba */ |
6faf3d66 JJ |
3063 | insn = INSN_BA | (val & 0x3fffff); |
3064 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3065 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3066 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3067 | { |
3068 | long setter; | |
3069 | int reg; | |
3070 | ||
3071 | if (INSN_BIG_ENDIAN) | |
3072 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3073 | else | |
3074 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3075 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3076 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3077 | break; |
3078 | /* The sequence was | |
3079 | or %o7, %g0, %rN | |
3080 | call foo | |
3081 | or %rN, %g0, %o7 | |
3082 | ||
3083 | If call foo was replaced with ba, replace | |
3084 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3085 | reg = (delay & RS1 (~0)) >> 14; |
3086 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3087 | || reg == G0 || reg == O7) |
3088 | break; | |
3089 | ||
3090 | if (INSN_BIG_ENDIAN) | |
3091 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3092 | else | |
3093 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3094 | } | |
3095 | } | |
252b5132 RH |
3096 | break; |
3097 | ||
3098 | case BFD_RELOC_SPARC_11: | |
3099 | if (! in_signed_range (val, 0x7ff)) | |
3100 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3101 | _("relocation overflow")); | |
3102 | insn |= val & 0x7ff; | |
3103 | break; | |
3104 | ||
3105 | case BFD_RELOC_SPARC_10: | |
3106 | if (! in_signed_range (val, 0x3ff)) | |
3107 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3108 | _("relocation overflow")); | |
3109 | insn |= val & 0x3ff; | |
3110 | break; | |
3111 | ||
3112 | case BFD_RELOC_SPARC_7: | |
3113 | if (! in_bitfield_range (val, 0x7f)) | |
3114 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3115 | _("relocation overflow")); | |
3116 | insn |= val & 0x7f; | |
3117 | break; | |
3118 | ||
3119 | case BFD_RELOC_SPARC_6: | |
3120 | if (! in_bitfield_range (val, 0x3f)) | |
3121 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3122 | _("relocation overflow")); | |
3123 | insn |= val & 0x3f; | |
3124 | break; | |
3125 | ||
3126 | case BFD_RELOC_SPARC_5: | |
3127 | if (! in_bitfield_range (val, 0x1f)) | |
3128 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3129 | _("relocation overflow")); | |
3130 | insn |= val & 0x1f; | |
3131 | break; | |
3132 | ||
3133 | case BFD_RELOC_SPARC_WDISP16: | |
e0c6ed95 | 3134 | /* FIXME: simplify. */ |
252b5132 RH |
3135 | if (((val > 0) && (val & ~0x3fffc)) |
3136 | || ((val < 0) && (~(val - 1) & ~0x3fffc))) | |
3137 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3138 | _("relocation overflow")); | |
3139 | /* FIXME: The +1 deserves a comment. */ | |
3140 | val = (val >> 2) + 1; | |
3141 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3142 | break; | |
3143 | ||
3144 | case BFD_RELOC_SPARC_WDISP19: | |
e0c6ed95 | 3145 | /* FIXME: simplify. */ |
252b5132 RH |
3146 | if (((val > 0) && (val & ~0x1ffffc)) |
3147 | || ((val < 0) && (~(val - 1) & ~0x1ffffc))) | |
3148 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3149 | _("relocation overflow")); | |
3150 | /* FIXME: The +1 deserves a comment. */ | |
3151 | val = (val >> 2) + 1; | |
3152 | insn |= val & 0x7ffff; | |
3153 | break; | |
3154 | ||
3155 | case BFD_RELOC_SPARC_HH22: | |
3156 | val = BSR (val, 32); | |
e0c6ed95 | 3157 | /* Fall through. */ |
252b5132 RH |
3158 | |
3159 | case BFD_RELOC_SPARC_LM22: | |
3160 | case BFD_RELOC_HI22: | |
3161 | if (!fixP->fx_addsy) | |
3162 | { | |
3163 | insn |= (val >> 10) & 0x3fffff; | |
3164 | } | |
3165 | else | |
3166 | { | |
3167 | /* FIXME: Need comment explaining why we do this. */ | |
3168 | insn &= ~0xffff; | |
3169 | } | |
3170 | break; | |
3171 | ||
3172 | case BFD_RELOC_SPARC22: | |
3173 | if (val & ~0x003fffff) | |
3174 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3175 | _("relocation overflow")); | |
3176 | insn |= (val & 0x3fffff); | |
3177 | break; | |
3178 | ||
3179 | case BFD_RELOC_SPARC_HM10: | |
3180 | val = BSR (val, 32); | |
e0c6ed95 | 3181 | /* Fall through. */ |
252b5132 RH |
3182 | |
3183 | case BFD_RELOC_LO10: | |
3184 | if (!fixP->fx_addsy) | |
3185 | { | |
3186 | insn |= val & 0x3ff; | |
3187 | } | |
3188 | else | |
3189 | { | |
3190 | /* FIXME: Need comment explaining why we do this. */ | |
3191 | insn &= ~0xff; | |
3192 | } | |
3193 | break; | |
3194 | ||
dabe3bbc RH |
3195 | case BFD_RELOC_SPARC_OLO10: |
3196 | val &= 0x3ff; | |
3197 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3198 | /* Fall through. */ |
dabe3bbc | 3199 | |
252b5132 RH |
3200 | case BFD_RELOC_SPARC13: |
3201 | if (! in_signed_range (val, 0x1fff)) | |
3202 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3203 | _("relocation overflow")); | |
3204 | insn |= val & 0x1fff; | |
3205 | break; | |
3206 | ||
3207 | case BFD_RELOC_SPARC_WDISP22: | |
3208 | val = (val >> 2) + 1; | |
e0c6ed95 | 3209 | /* Fall through. */ |
252b5132 RH |
3210 | case BFD_RELOC_SPARC_BASE22: |
3211 | insn |= val & 0x3fffff; | |
3212 | break; | |
3213 | ||
3214 | case BFD_RELOC_SPARC_H44: | |
3215 | if (!fixP->fx_addsy) | |
3216 | { | |
3217 | bfd_vma tval = val; | |
3218 | tval >>= 22; | |
3219 | insn |= tval & 0x3fffff; | |
3220 | } | |
3221 | break; | |
3222 | ||
3223 | case BFD_RELOC_SPARC_M44: | |
3224 | if (!fixP->fx_addsy) | |
3225 | insn |= (val >> 12) & 0x3ff; | |
3226 | break; | |
3227 | ||
3228 | case BFD_RELOC_SPARC_L44: | |
3229 | if (!fixP->fx_addsy) | |
3230 | insn |= val & 0xfff; | |
3231 | break; | |
3232 | ||
3233 | case BFD_RELOC_SPARC_HIX22: | |
3234 | if (!fixP->fx_addsy) | |
3235 | { | |
ab3e48dc | 3236 | val ^= ~(offsetT) 0; |
252b5132 RH |
3237 | insn |= (val >> 10) & 0x3fffff; |
3238 | } | |
3239 | break; | |
3240 | ||
3241 | case BFD_RELOC_SPARC_LOX10: | |
3242 | if (!fixP->fx_addsy) | |
3243 | insn |= 0x1c00 | (val & 0x3ff); | |
3244 | break; | |
3245 | ||
3246 | case BFD_RELOC_NONE: | |
3247 | default: | |
3248 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3249 | _("bad or unhandled relocation type: 0x%02x"), | |
3250 | fixP->fx_r_type); | |
3251 | break; | |
3252 | } | |
3253 | ||
3254 | if (INSN_BIG_ENDIAN) | |
3255 | bfd_putb32 (insn, (unsigned char *) buf); | |
3256 | else | |
3257 | bfd_putl32 (insn, (unsigned char *) buf); | |
3258 | } | |
3259 | ||
3260 | /* Are we finished with this relocation now? */ | |
3261 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3262 | fixP->fx_done = 1; | |
3263 | ||
3264 | return 1; | |
3265 | } | |
3266 | ||
3267 | /* Translate internal representation of relocation info to BFD target | |
3268 | format. */ | |
e0c6ed95 | 3269 | |
dabe3bbc | 3270 | arelent ** |
252b5132 RH |
3271 | tc_gen_reloc (section, fixp) |
3272 | asection *section; | |
3273 | fixS *fixp; | |
3274 | { | |
dabe3bbc | 3275 | static arelent *relocs[3]; |
252b5132 RH |
3276 | arelent *reloc; |
3277 | bfd_reloc_code_real_type code; | |
3278 | ||
dabe3bbc RH |
3279 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3280 | relocs[1] = NULL; | |
252b5132 | 3281 | |
49309057 ILT |
3282 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3283 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3284 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3285 | ||
3286 | switch (fixp->fx_r_type) | |
3287 | { | |
3288 | case BFD_RELOC_16: | |
3289 | case BFD_RELOC_32: | |
3290 | case BFD_RELOC_HI22: | |
3291 | case BFD_RELOC_LO10: | |
3292 | case BFD_RELOC_32_PCREL_S2: | |
3293 | case BFD_RELOC_SPARC13: | |
63fab58c | 3294 | case BFD_RELOC_SPARC22: |
252b5132 RH |
3295 | case BFD_RELOC_SPARC_BASE13: |
3296 | case BFD_RELOC_SPARC_WDISP16: | |
3297 | case BFD_RELOC_SPARC_WDISP19: | |
3298 | case BFD_RELOC_SPARC_WDISP22: | |
3299 | case BFD_RELOC_64: | |
3300 | case BFD_RELOC_SPARC_5: | |
3301 | case BFD_RELOC_SPARC_6: | |
3302 | case BFD_RELOC_SPARC_7: | |
3303 | case BFD_RELOC_SPARC_10: | |
3304 | case BFD_RELOC_SPARC_11: | |
3305 | case BFD_RELOC_SPARC_HH22: | |
3306 | case BFD_RELOC_SPARC_HM10: | |
3307 | case BFD_RELOC_SPARC_LM22: | |
3308 | case BFD_RELOC_SPARC_PC_HH22: | |
3309 | case BFD_RELOC_SPARC_PC_HM10: | |
3310 | case BFD_RELOC_SPARC_PC_LM22: | |
3311 | case BFD_RELOC_SPARC_H44: | |
3312 | case BFD_RELOC_SPARC_M44: | |
3313 | case BFD_RELOC_SPARC_L44: | |
3314 | case BFD_RELOC_SPARC_HIX22: | |
3315 | case BFD_RELOC_SPARC_LOX10: | |
3316 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3317 | case BFD_RELOC_SPARC_OLO10: |
252b5132 RH |
3318 | case BFD_RELOC_VTABLE_ENTRY: |
3319 | case BFD_RELOC_VTABLE_INHERIT: | |
3320 | code = fixp->fx_r_type; | |
3321 | break; | |
3322 | default: | |
3323 | abort (); | |
3324 | return NULL; | |
3325 | } | |
3326 | ||
3327 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3328 | /* If we are generating PIC code, we need to generate a different | |
3329 | set of relocs. */ | |
3330 | ||
3331 | #ifdef OBJ_ELF | |
3332 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3333 | #else | |
3334 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
3335 | #endif | |
3336 | ||
153b546a ILT |
3337 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3338 | ||
252b5132 RH |
3339 | if (sparc_pic_code) |
3340 | { | |
3341 | switch (code) | |
3342 | { | |
3343 | case BFD_RELOC_32_PCREL_S2: | |
3344 | if (! S_IS_DEFINED (fixp->fx_addsy) | |
3345 | || S_IS_COMMON (fixp->fx_addsy) | |
3346 | || S_IS_EXTERNAL (fixp->fx_addsy) | |
3347 | || S_IS_WEAK (fixp->fx_addsy)) | |
3348 | code = BFD_RELOC_SPARC_WPLT30; | |
3349 | break; | |
3350 | case BFD_RELOC_HI22: | |
3351 | if (fixp->fx_addsy != NULL | |
3352 | && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3353 | code = BFD_RELOC_SPARC_PC22; | |
3354 | else | |
3355 | code = BFD_RELOC_SPARC_GOT22; | |
3356 | break; | |
3357 | case BFD_RELOC_LO10: | |
3358 | if (fixp->fx_addsy != NULL | |
3359 | && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3360 | code = BFD_RELOC_SPARC_PC10; | |
3361 | else | |
3362 | code = BFD_RELOC_SPARC_GOT10; | |
3363 | break; | |
3364 | case BFD_RELOC_SPARC13: | |
3365 | code = BFD_RELOC_SPARC_GOT13; | |
3366 | break; | |
3367 | default: | |
3368 | break; | |
3369 | } | |
3370 | } | |
e0c6ed95 | 3371 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3372 | |
dabe3bbc RH |
3373 | if (code == BFD_RELOC_SPARC_OLO10) |
3374 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3375 | else | |
3376 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3377 | if (reloc->howto == 0) |
3378 | { | |
3379 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3380 | _("internal error: can't export reloc type %d (`%s')"), | |
3381 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3382 | xfree (reloc); |
3383 | relocs[0] = NULL; | |
3384 | return relocs; | |
252b5132 RH |
3385 | } |
3386 | ||
3387 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3388 | #ifdef OBJ_AOUT | |
3389 | ||
3390 | if (reloc->howto->pc_relative == 0 | |
3391 | || code == BFD_RELOC_SPARC_PC10 | |
3392 | || code == BFD_RELOC_SPARC_PC22) | |
3393 | reloc->addend = fixp->fx_addnumber; | |
3394 | else if (sparc_pic_code | |
3395 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3396 | && fixp->fx_addsy != NULL | |
3397 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3398 | || S_IS_WEAK (fixp->fx_addsy)) | |
3399 | && S_IS_DEFINED (fixp->fx_addsy) | |
3400 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3401 | reloc->addend = fixp->fx_addnumber; | |
3402 | else | |
3403 | reloc->addend = fixp->fx_offset - reloc->address; | |
3404 | ||
e0c6ed95 | 3405 | #else /* elf or coff */ |
252b5132 RH |
3406 | |
3407 | if (reloc->howto->pc_relative == 0 | |
3408 | || code == BFD_RELOC_SPARC_PC10 | |
3409 | || code == BFD_RELOC_SPARC_PC22) | |
3410 | reloc->addend = fixp->fx_addnumber; | |
49309057 | 3411 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3412 | reloc->addend = (section->vma |
3413 | + fixp->fx_addnumber | |
3414 | + md_pcrel_from (fixp)); | |
3415 | else | |
3416 | reloc->addend = fixp->fx_offset; | |
3417 | #endif | |
3418 | ||
dabe3bbc RH |
3419 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3420 | on the same location. */ | |
3421 | if (code == BFD_RELOC_SPARC_OLO10) | |
3422 | { | |
3423 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3424 | relocs[2] = NULL; | |
3425 | ||
3426 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
ab3e48dc KH |
3427 | *reloc->sym_ptr_ptr |
3428 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
3429 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3430 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3431 | reloc->addend = fixp->tc_fix_data; | |
3432 | } | |
3433 | ||
3434 | return relocs; | |
252b5132 RH |
3435 | } |
3436 | \f | |
e0c6ed95 | 3437 | /* We have no need to default values of symbols. */ |
252b5132 | 3438 | |
252b5132 RH |
3439 | symbolS * |
3440 | md_undefined_symbol (name) | |
c2158c24 | 3441 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
3442 | { |
3443 | return 0; | |
e0c6ed95 AM |
3444 | } |
3445 | ||
3446 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 3447 | |
252b5132 RH |
3448 | valueT |
3449 | md_section_align (segment, size) | |
c2158c24 | 3450 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
3451 | valueT size; |
3452 | { | |
3453 | #ifndef OBJ_ELF | |
3454 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3455 | the alignment anyways. */ | |
3456 | valueT align = ((valueT) 1 | |
3457 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3458 | valueT newsize; | |
e0c6ed95 AM |
3459 | |
3460 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
3461 | align--; |
3462 | newsize = (size + align) & ~align; | |
3463 | return newsize; | |
3464 | #else | |
3465 | return size; | |
3466 | #endif | |
3467 | } | |
3468 | ||
3469 | /* Exactly what point is a PC-relative offset relative TO? | |
3470 | On the sparc, they're relative to the address of the offset, plus | |
3471 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
3472 | (??? Is this right? FIXME-SOON) */ |
3473 | long | |
252b5132 RH |
3474 | md_pcrel_from (fixP) |
3475 | fixS *fixP; | |
3476 | { | |
3477 | long ret; | |
3478 | ||
3479 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3480 | if (! sparc_pic_code | |
3481 | || fixP->fx_addsy == NULL | |
49309057 | 3482 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3483 | ret += fixP->fx_size; |
3484 | return ret; | |
3485 | } | |
3486 | \f | |
3487 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3488 | of two. */ | |
3489 | ||
3490 | static int | |
3491 | log2 (value) | |
3492 | int value; | |
3493 | { | |
3494 | int shift; | |
3495 | ||
3496 | if (value <= 0) | |
3497 | return -1; | |
3498 | ||
3499 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3500 | ++shift; | |
3501 | ||
3502 | return (value == 1) ? shift : -1; | |
3503 | } | |
3504 | ||
e0c6ed95 | 3505 | /* Sort of like s_lcomm. */ |
252b5132 RH |
3506 | |
3507 | #ifndef OBJ_ELF | |
3508 | static int max_alignment = 15; | |
3509 | #endif | |
3510 | ||
3511 | static void | |
3512 | s_reserve (ignore) | |
c2158c24 | 3513 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3514 | { |
3515 | char *name; | |
3516 | char *p; | |
3517 | char c; | |
3518 | int align; | |
3519 | int size; | |
3520 | int temp; | |
3521 | symbolS *symbolP; | |
3522 | ||
3523 | name = input_line_pointer; | |
3524 | c = get_symbol_end (); | |
3525 | p = input_line_pointer; | |
3526 | *p = c; | |
3527 | SKIP_WHITESPACE (); | |
3528 | ||
3529 | if (*input_line_pointer != ',') | |
3530 | { | |
3531 | as_bad (_("Expected comma after name")); | |
3532 | ignore_rest_of_line (); | |
3533 | return; | |
3534 | } | |
3535 | ||
3536 | ++input_line_pointer; | |
3537 | ||
3538 | if ((size = get_absolute_expression ()) < 0) | |
3539 | { | |
3540 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3541 | ignore_rest_of_line (); | |
3542 | return; | |
e0c6ed95 | 3543 | } /* Bad length. */ |
252b5132 RH |
3544 | |
3545 | *p = 0; | |
3546 | symbolP = symbol_find_or_make (name); | |
3547 | *p = c; | |
3548 | ||
3549 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3550 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3551 | { | |
3552 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
3553 | return; | |
3554 | } | |
3555 | ||
3556 | if (input_line_pointer[2] == '.') | |
3557 | input_line_pointer += 7; | |
3558 | else | |
3559 | input_line_pointer += 6; | |
3560 | SKIP_WHITESPACE (); | |
3561 | ||
3562 | if (*input_line_pointer == ',') | |
3563 | { | |
3564 | ++input_line_pointer; | |
3565 | ||
3566 | SKIP_WHITESPACE (); | |
3567 | if (*input_line_pointer == '\n') | |
3568 | { | |
3569 | as_bad (_("missing alignment")); | |
3570 | ignore_rest_of_line (); | |
3571 | return; | |
3572 | } | |
3573 | ||
3574 | align = (int) get_absolute_expression (); | |
3575 | ||
3576 | #ifndef OBJ_ELF | |
3577 | if (align > max_alignment) | |
3578 | { | |
3579 | align = max_alignment; | |
3580 | as_warn (_("alignment too large; assuming %d"), align); | |
3581 | } | |
3582 | #endif | |
3583 | ||
3584 | if (align < 0) | |
3585 | { | |
3586 | as_bad (_("negative alignment")); | |
3587 | ignore_rest_of_line (); | |
3588 | return; | |
3589 | } | |
3590 | ||
3591 | if (align != 0) | |
3592 | { | |
3593 | temp = log2 (align); | |
3594 | if (temp < 0) | |
3595 | { | |
3596 | as_bad (_("alignment not a power of 2")); | |
3597 | ignore_rest_of_line (); | |
3598 | return; | |
3599 | } | |
3600 | ||
3601 | align = temp; | |
3602 | } | |
3603 | ||
3604 | record_alignment (bss_section, align); | |
3605 | } | |
3606 | else | |
3607 | align = 0; | |
3608 | ||
3609 | if (!S_IS_DEFINED (symbolP) | |
3610 | #ifdef OBJ_AOUT | |
3611 | && S_GET_OTHER (symbolP) == 0 | |
3612 | && S_GET_DESC (symbolP) == 0 | |
3613 | #endif | |
3614 | ) | |
3615 | { | |
3616 | if (! need_pass_2) | |
3617 | { | |
3618 | char *pfrag; | |
3619 | segT current_seg = now_seg; | |
3620 | subsegT current_subseg = now_subseg; | |
3621 | ||
e0c6ed95 AM |
3622 | /* Switch to bss. */ |
3623 | subseg_set (bss_section, 1); | |
252b5132 RH |
3624 | |
3625 | if (align) | |
e0c6ed95 AM |
3626 | /* Do alignment. */ |
3627 | frag_align (align, 0, 0); | |
252b5132 | 3628 | |
e0c6ed95 | 3629 | /* Detach from old frag. */ |
ab3e48dc | 3630 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 3631 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 3632 | |
49309057 | 3633 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
3634 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3635 | (offsetT) size, (char *) 0); | |
252b5132 RH |
3636 | *pfrag = 0; |
3637 | ||
3638 | S_SET_SEGMENT (symbolP, bss_section); | |
3639 | ||
3640 | subseg_set (current_seg, current_subseg); | |
3641 | ||
3642 | #ifdef OBJ_ELF | |
3643 | S_SET_SIZE (symbolP, size); | |
3644 | #endif | |
3645 | } | |
3646 | } | |
3647 | else | |
3648 | { | |
ab3e48dc KH |
3649 | as_warn ("Ignoring attempt to re-define symbol %s", |
3650 | S_GET_NAME (symbolP)); | |
e0c6ed95 | 3651 | } /* if not redefining. */ |
252b5132 RH |
3652 | |
3653 | demand_empty_rest_of_line (); | |
3654 | } | |
3655 | ||
3656 | static void | |
3657 | s_common (ignore) | |
c2158c24 | 3658 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3659 | { |
3660 | char *name; | |
3661 | char c; | |
3662 | char *p; | |
3663 | int temp, size; | |
3664 | symbolS *symbolP; | |
3665 | ||
3666 | name = input_line_pointer; | |
3667 | c = get_symbol_end (); | |
e0c6ed95 | 3668 | /* Just after name is now '\0'. */ |
252b5132 RH |
3669 | p = input_line_pointer; |
3670 | *p = c; | |
3671 | SKIP_WHITESPACE (); | |
3672 | if (*input_line_pointer != ',') | |
3673 | { | |
3674 | as_bad (_("Expected comma after symbol-name")); | |
3675 | ignore_rest_of_line (); | |
3676 | return; | |
3677 | } | |
e0c6ed95 AM |
3678 | |
3679 | /* Skip ','. */ | |
3680 | input_line_pointer++; | |
3681 | ||
252b5132 RH |
3682 | if ((temp = get_absolute_expression ()) < 0) |
3683 | { | |
3684 | as_bad (_(".COMMon length (%d.) <0! Ignored."), temp); | |
3685 | ignore_rest_of_line (); | |
3686 | return; | |
3687 | } | |
3688 | size = temp; | |
3689 | *p = 0; | |
3690 | symbolP = symbol_find_or_make (name); | |
3691 | *p = c; | |
3692 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
3693 | { | |
3694 | as_bad (_("Ignoring attempt to re-define symbol")); | |
3695 | ignore_rest_of_line (); | |
3696 | return; | |
3697 | } | |
3698 | if (S_GET_VALUE (symbolP) != 0) | |
3699 | { | |
3700 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
3701 | { | |
3702 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), | |
3703 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); | |
3704 | } | |
3705 | } | |
3706 | else | |
3707 | { | |
3708 | #ifndef OBJ_ELF | |
3709 | S_SET_VALUE (symbolP, (valueT) size); | |
3710 | S_SET_EXTERNAL (symbolP); | |
3711 | #endif | |
3712 | } | |
7dcc9865 | 3713 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
3714 | if (*input_line_pointer != ',') |
3715 | { | |
3716 | as_bad (_("Expected comma after common length")); | |
3717 | ignore_rest_of_line (); | |
3718 | return; | |
3719 | } | |
3720 | input_line_pointer++; | |
3721 | SKIP_WHITESPACE (); | |
3722 | if (*input_line_pointer != '"') | |
3723 | { | |
3724 | temp = get_absolute_expression (); | |
3725 | ||
3726 | #ifndef OBJ_ELF | |
3727 | if (temp > max_alignment) | |
3728 | { | |
3729 | temp = max_alignment; | |
3730 | as_warn (_("alignment too large; assuming %d"), temp); | |
3731 | } | |
3732 | #endif | |
3733 | ||
3734 | if (temp < 0) | |
3735 | { | |
3736 | as_bad (_("negative alignment")); | |
3737 | ignore_rest_of_line (); | |
3738 | return; | |
3739 | } | |
3740 | ||
3741 | #ifdef OBJ_ELF | |
49309057 | 3742 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
3743 | { |
3744 | segT old_sec; | |
3745 | int old_subsec; | |
3746 | char *p; | |
3747 | int align; | |
3748 | ||
3749 | old_sec = now_seg; | |
3750 | old_subsec = now_subseg; | |
3751 | ||
3752 | if (temp == 0) | |
3753 | align = 0; | |
3754 | else | |
3755 | align = log2 (temp); | |
3756 | ||
3757 | if (align < 0) | |
3758 | { | |
3759 | as_bad (_("alignment not a power of 2")); | |
3760 | ignore_rest_of_line (); | |
3761 | return; | |
3762 | } | |
3763 | ||
3764 | record_alignment (bss_section, align); | |
3765 | subseg_set (bss_section, 0); | |
3766 | if (align) | |
3767 | frag_align (align, 0, 0); | |
3768 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
3769 | symbol_get_frag (symbolP)->fr_symbol = 0; |
3770 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
3771 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3772 | (offsetT) size, (char *) 0); | |
3773 | *p = 0; | |
3774 | S_SET_SEGMENT (symbolP, bss_section); | |
3775 | S_CLEAR_EXTERNAL (symbolP); | |
3776 | S_SET_SIZE (symbolP, size); | |
3777 | subseg_set (old_sec, old_subsec); | |
3778 | } | |
3779 | else | |
e0c6ed95 | 3780 | #endif /* OBJ_ELF */ |
252b5132 RH |
3781 | { |
3782 | allocate_common: | |
3783 | S_SET_VALUE (symbolP, (valueT) size); | |
3784 | #ifdef OBJ_ELF | |
3785 | S_SET_ALIGN (symbolP, temp); | |
3786 | S_SET_SIZE (symbolP, size); | |
3787 | #endif | |
3788 | S_SET_EXTERNAL (symbolP); | |
3789 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
3790 | } | |
3791 | } | |
3792 | else | |
3793 | { | |
3794 | input_line_pointer++; | |
3795 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
3796 | if (*input_line_pointer == '.') | |
3797 | input_line_pointer++; | |
3798 | /* @@ Some say data, some say bss. */ | |
3799 | if (strncmp (input_line_pointer, "bss\"", 4) | |
3800 | && strncmp (input_line_pointer, "data\"", 5)) | |
3801 | { | |
3802 | while (*--input_line_pointer != '"') | |
3803 | ; | |
3804 | input_line_pointer--; | |
3805 | goto bad_common_segment; | |
3806 | } | |
3807 | while (*input_line_pointer++ != '"') | |
3808 | ; | |
3809 | goto allocate_common; | |
3810 | } | |
3811 | ||
3812 | #ifdef BFD_ASSEMBLER | |
49309057 | 3813 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
3814 | #endif |
3815 | ||
3816 | demand_empty_rest_of_line (); | |
3817 | return; | |
3818 | ||
3819 | { | |
3820 | bad_common_segment: | |
3821 | p = input_line_pointer; | |
3822 | while (*p && *p != '\n') | |
3823 | p++; | |
3824 | c = *p; | |
3825 | *p = '\0'; | |
3826 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
3827 | *p = c; | |
3828 | input_line_pointer = p; | |
3829 | ignore_rest_of_line (); | |
3830 | return; | |
3831 | } | |
3832 | } | |
3833 | ||
3834 | /* Handle the .empty pseudo-op. This supresses the warnings about | |
3835 | invalid delay slot usage. */ | |
3836 | ||
3837 | static void | |
3838 | s_empty (ignore) | |
c2158c24 | 3839 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3840 | { |
3841 | /* The easy way to implement is to just forget about the last | |
3842 | instruction. */ | |
3843 | last_insn = NULL; | |
3844 | } | |
3845 | ||
3846 | static void | |
3847 | s_seg (ignore) | |
c2158c24 | 3848 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3849 | { |
3850 | ||
3851 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
3852 | { | |
3853 | input_line_pointer += 6; | |
3854 | s_text (0); | |
3855 | return; | |
3856 | } | |
3857 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
3858 | { | |
3859 | input_line_pointer += 6; | |
3860 | s_data (0); | |
3861 | return; | |
3862 | } | |
3863 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
3864 | { | |
3865 | input_line_pointer += 7; | |
3866 | s_data1 (); | |
3867 | return; | |
3868 | } | |
3869 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
3870 | { | |
3871 | input_line_pointer += 5; | |
3872 | /* We only support 2 segments -- text and data -- for now, so | |
3873 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
3874 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
3875 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
3876 | return; |
3877 | } | |
3878 | as_bad (_("Unknown segment type")); | |
3879 | demand_empty_rest_of_line (); | |
3880 | } | |
3881 | ||
3882 | static void | |
3883 | s_data1 () | |
3884 | { | |
3885 | subseg_set (data_section, 1); | |
3886 | demand_empty_rest_of_line (); | |
3887 | } | |
3888 | ||
3889 | static void | |
3890 | s_proc (ignore) | |
c2158c24 | 3891 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
3892 | { |
3893 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
3894 | { | |
3895 | ++input_line_pointer; | |
3896 | } | |
3897 | ++input_line_pointer; | |
3898 | } | |
3899 | ||
3900 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
3901 | that the expession does not need to be aligned. */ | |
3902 | ||
3903 | static int sparc_no_align_cons = 0; | |
3904 | ||
3905 | /* This handles the unaligned space allocation pseudo-ops, such as | |
3906 | .uaword. .uaword is just like .word, but the value does not need | |
3907 | to be aligned. */ | |
3908 | ||
3909 | static void | |
3910 | s_uacons (bytes) | |
3911 | int bytes; | |
3912 | { | |
3913 | /* Tell sparc_cons_align not to align this value. */ | |
3914 | sparc_no_align_cons = 1; | |
3915 | cons (bytes); | |
3916 | } | |
3917 | ||
cf9a1301 RH |
3918 | /* This handles the native word allocation pseudo-op .nword. |
3919 | For sparc_arch_size 32 it is equivalent to .word, for | |
3920 | sparc_arch_size 64 it is equivalent to .xword. */ | |
3921 | ||
3922 | static void | |
3923 | s_ncons (bytes) | |
c2158c24 | 3924 | int bytes ATTRIBUTE_UNUSED; |
cf9a1301 RH |
3925 | { |
3926 | cons (sparc_arch_size == 32 ? 4 : 8); | |
3927 | } | |
3928 | ||
6d8809aa RH |
3929 | #ifdef OBJ_ELF |
3930 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
3931 | global register. | |
3932 | The syntax is: | |
e0c6ed95 | 3933 | |
6d8809aa | 3934 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 3935 | */ |
6d8809aa RH |
3936 | |
3937 | static void | |
3938 | s_register (ignore) | |
c2158c24 | 3939 | int ignore ATTRIBUTE_UNUSED; |
6d8809aa RH |
3940 | { |
3941 | char c; | |
3942 | int reg; | |
3943 | int flags; | |
3944 | const char *regname; | |
3945 | ||
3946 | if (input_line_pointer[0] != '%' | |
3947 | || input_line_pointer[1] != 'g' | |
3948 | || ((input_line_pointer[2] & ~1) != '2' | |
3949 | && (input_line_pointer[2] & ~1) != '6') | |
3950 | || input_line_pointer[3] != ',') | |
3951 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
3952 | reg = input_line_pointer[2] - '0'; | |
3953 | input_line_pointer += 4; | |
3954 | ||
3955 | if (*input_line_pointer == '#') | |
3956 | { | |
3957 | ++input_line_pointer; | |
3958 | regname = input_line_pointer; | |
3959 | c = get_symbol_end (); | |
3960 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) | |
3961 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 3962 | if (regname[0] == 'i') |
6d8809aa RH |
3963 | regname = NULL; |
3964 | else | |
3965 | regname = ""; | |
3966 | } | |
3967 | else | |
3968 | { | |
3969 | regname = input_line_pointer; | |
3970 | c = get_symbol_end (); | |
3971 | } | |
3972 | if (sparc_arch_size == 64) | |
3973 | { | |
e0c6ed95 | 3974 | if (globals[reg]) |
6d8809aa | 3975 | { |
e0c6ed95 AM |
3976 | if ((regname && globals[reg] != (symbolS *) 1 |
3977 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
3978 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
3979 | as_bad (_("redefinition of global register")); |
3980 | } | |
3981 | else | |
3982 | { | |
3983 | if (regname == NULL) | |
e0c6ed95 | 3984 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
3985 | else |
3986 | { | |
3987 | if (*regname) | |
3988 | { | |
3989 | if (symbol_find (regname)) | |
3990 | as_bad (_("Register symbol %s already defined."), | |
3991 | regname); | |
3992 | } | |
e0c6ed95 AM |
3993 | globals[reg] = symbol_make (regname); |
3994 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
3995 | if (! *regname) |
3996 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
3997 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
3998 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
3999 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4000 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4001 | S_SET_ALIGN (globals[reg], reg); | |
4002 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4003 | /* Although we actually want undefined_section here, |
4004 | we have to use absolute_section, because otherwise | |
4005 | generic as code will make it a COM section. | |
4006 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4007 | S_SET_SEGMENT (globals[reg], absolute_section); |
4008 | S_SET_OTHER (globals[reg], 0); | |
4009 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4010 | ->internal_elf_sym.st_info = |
4011 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4012 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4013 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4014 | } | |
4015 | } | |
4016 | } | |
4017 | ||
4018 | *input_line_pointer = c; | |
4019 | ||
4020 | demand_empty_rest_of_line (); | |
4021 | } | |
4022 | ||
4023 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4024 | symbols which need it. */ | |
e0c6ed95 | 4025 | |
6d8809aa RH |
4026 | void |
4027 | sparc_adjust_symtab () | |
4028 | { | |
4029 | symbolS *sym; | |
e0c6ed95 | 4030 | |
6d8809aa RH |
4031 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4032 | { | |
4033 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4034 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4035 | continue; | |
4036 | ||
4037 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4038 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4039 | continue; | |
4040 | ||
4041 | S_SET_SEGMENT (sym, undefined_section); | |
4042 | } | |
4043 | } | |
4044 | #endif | |
4045 | ||
252b5132 RH |
4046 | /* If the --enforce-aligned-data option is used, we require .word, |
4047 | et. al., to be aligned correctly. We do it by setting up an | |
4048 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4049 | no unexpected alignment was introduced. | |
4050 | ||
4051 | The SunOS and Solaris native assemblers enforce aligned data by | |
4052 | default. We don't want to do that, because gcc can deliberately | |
4053 | generate misaligned data if the packed attribute is used. Instead, | |
4054 | we permit misaligned data by default, and permit the user to set an | |
4055 | option to check for it. */ | |
4056 | ||
4057 | void | |
4058 | sparc_cons_align (nbytes) | |
4059 | int nbytes; | |
4060 | { | |
4061 | int nalign; | |
4062 | char *p; | |
4063 | ||
4064 | /* Only do this if we are enforcing aligned data. */ | |
4065 | if (! enforce_aligned_data) | |
4066 | return; | |
4067 | ||
4068 | if (sparc_no_align_cons) | |
4069 | { | |
4070 | /* This is an unaligned pseudo-op. */ | |
4071 | sparc_no_align_cons = 0; | |
4072 | return; | |
4073 | } | |
4074 | ||
4075 | nalign = log2 (nbytes); | |
4076 | if (nalign == 0) | |
4077 | return; | |
4078 | ||
4079 | assert (nalign > 0); | |
4080 | ||
4081 | if (now_seg == absolute_section) | |
4082 | { | |
4083 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4084 | as_bad (_("misaligned data")); | |
4085 | return; | |
4086 | } | |
4087 | ||
4088 | p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0, | |
4089 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
4090 | ||
4091 | record_alignment (now_seg, nalign); | |
4092 | } | |
4093 | ||
4094 | /* This is where we do the unexpected alignment check. | |
4095 | This is called from HANDLE_ALIGN in tc-sparc.h. */ | |
4096 | ||
4097 | void | |
4098 | sparc_handle_align (fragp) | |
4099 | fragS *fragp; | |
4100 | { | |
4101 | if (fragp->fr_type == rs_align_code && !fragp->fr_subtype | |
4102 | && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0) | |
4103 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4104 | if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024) | |
4105 | { | |
ab3e48dc KH |
4106 | int count = |
4107 | fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
e0c6ed95 | 4108 | |
252b5132 RH |
4109 | if (count >= 4 |
4110 | && !(count & 3) | |
4111 | && count <= 1024 | |
e0c6ed95 AM |
4112 | && !((long) (fragp->fr_literal + fragp->fr_fix) & 3)) |
4113 | { | |
4114 | unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix); | |
4115 | int i; | |
4116 | ||
4117 | for (i = 0; i < count; i += 4, p++) | |
4118 | if (INSN_BIG_ENDIAN) | |
4119 | /* Emit nops. */ | |
4120 | number_to_chars_bigendian ((char *) p, 0x01000000, 4); | |
4121 | else | |
4122 | number_to_chars_littleendian ((char *) p, 0x10000000, 4); | |
4123 | ||
4124 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) | |
4125 | { | |
252b5132 | 4126 | char *waddr = &fragp->fr_literal[fragp->fr_fix]; |
e0c6ed95 | 4127 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ |
252b5132 RH |
4128 | if (INSN_BIG_ENDIAN) |
4129 | number_to_chars_bigendian (waddr, wval, 4); | |
4130 | else | |
4131 | number_to_chars_littleendian (waddr, wval, 4); | |
e0c6ed95 AM |
4132 | } |
4133 | fragp->fr_var = count; | |
4134 | } | |
252b5132 RH |
4135 | } |
4136 | } | |
4137 | ||
4138 | #ifdef OBJ_ELF | |
4139 | /* Some special processing for a Sparc ELF file. */ | |
4140 | ||
4141 | void | |
4142 | sparc_elf_final_processing () | |
4143 | { | |
4144 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4145 | sort of BFD interface for this. */ | |
4146 | if (sparc_arch_size == 64) | |
4147 | { | |
4148 | switch (sparc_memory_model) | |
4149 | { | |
4150 | case MM_RMO: | |
4151 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4152 | break; | |
4153 | case MM_PSO: | |
4154 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4155 | break; | |
4156 | default: | |
4157 | break; | |
4158 | } | |
4159 | } | |
4160 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4161 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4162 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4163 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4164 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4165 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 RH |
4166 | } |
4167 | #endif | |
4168 | ||
4169 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4170 | reloc for a cons. We could use the definition there, except that | |
4171 | we want to handle little endian relocs specially. */ | |
4172 | ||
4173 | void | |
4174 | cons_fix_new_sparc (frag, where, nbytes, exp) | |
4175 | fragS *frag; | |
4176 | int where; | |
4177 | unsigned int nbytes; | |
4178 | expressionS *exp; | |
4179 | { | |
4180 | bfd_reloc_code_real_type r; | |
4181 | ||
4182 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4183 | (nbytes == 2 ? BFD_RELOC_16 : | |
4184 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4185 | ||
4186 | if (target_little_endian_data && nbytes == 4 | |
e0c6ed95 | 4187 | && now_seg->flags & SEC_ALLOC) |
252b5132 RH |
4188 | r = BFD_RELOC_SPARC_REV32; |
4189 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); | |
4190 | } | |
4191 | ||
4192 | #ifdef OBJ_ELF | |
4193 | int | |
4194 | elf32_sparc_force_relocation (fixp) | |
e0c6ed95 | 4195 | struct fix *fixp; |
252b5132 RH |
4196 | { |
4197 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4198 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4199 | return 1; | |
e0c6ed95 | 4200 | |
252b5132 RH |
4201 | return 0; |
4202 | } | |
4203 | #endif |