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Rmeove i370-mvs architecture - it is not supported.
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
CommitLineData
252b5132 1/* tc-sparc.c -- Assemble for the SPARC
f7e42eb4
NC		 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001
e0c6ed95 4 Free Software Foundation, Inc.
252b5132
RH		 5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
81d4177b 20 Boston, MA 02111-1307, USA. */
252b5132
RH		 21
22#include <stdio.h>
23#include <ctype.h>
24
25#include "as.h"
26#include "subsegs.h"
27
28#include "opcode/sparc.h"
29
30#ifdef OBJ_ELF
31#include "elf/sparc.h"
732d96b6 32#include "dwarf2dbg.h"
252b5132
RH		 33#endif
34
35static struct sparc_arch *lookup_arch PARAMS ((char *));
36static void init_default_arch PARAMS ((void));
a22b281c 37static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
252b5132
RH		 38static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
40static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
41static int sparc_ffs PARAMS ((unsigned int));
a22b281c
RH		 42static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
43static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
44static void synthetize_setx PARAMS ((const struct sparc_opcode *));
252b5132
RH		 45static bfd_vma BSR PARAMS ((bfd_vma, int));
46static int cmp_reg_entry PARAMS ((const PTR, const PTR));
47static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
48static int parse_const_expr_arg PARAMS ((char **, int *));
49static int get_expression PARAMS ((char *str));
50
51/* Default architecture. */
52/* ??? The default value should be V8, but sparclite support was added
53 by making it the default. GCC now passes -Asparclite, so maybe sometime in
54 the future we can set this to V8. */
55#ifndef DEFAULT_ARCH
56#define DEFAULT_ARCH "sparclite"
57#endif
58static char *default_arch = DEFAULT_ARCH;
59
60/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
61 have been set. */
62static int default_init_p;
63
64/* Current architecture. We don't bump up unless necessary. */
65static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
66
67/* The maximum architecture level we can bump up to.
68 In a 32 bit environment, don't allow bumping up to v9 by default.
69 The native assembler works this way. The user is required to pass
70 an explicit argument before we'll create v9 object files. However, if
71 we don't see any v9 insns, a v8plus object file is not created. */
72static enum sparc_opcode_arch_val max_architecture;
73
74/* Either 32 or 64, selects file format. */
75static int sparc_arch_size;
76/* Initial (default) value, recorded separately in case a user option
77 changes the value before md_show_usage is called. */
78static int default_arch_size;
79
80#ifdef OBJ_ELF
81/* The currently selected v9 memory model. Currently only used for
82 ELF. */
83static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
84#endif
85
86static int architecture_requested;
87static int warn_on_bump;
88
89/* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91static enum sparc_opcode_arch_val warn_after_architecture;
92
6d8809aa
RH		 93/* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95static int no_undeclared_regs;
96
6faf3d66
JJ		 97/* Non-zero if we should try to relax jumps and calls. */
98static int sparc_relax;
99
252b5132
RH		 100/* Non-zero if we are generating PIC code. */
101int sparc_pic_code;
102
103/* Non-zero if we should give an error when misaligned data is seen. */
104static int enforce_aligned_data;
105
106extern int target_big_endian;
107
108static int target_little_endian_data;
109
6d8809aa
RH		 110/* Symbols for global registers on v9. */
111static symbolS *globals[8];
112
252b5132
RH		 113/* V9 and 86x have big and little endian data, but instructions are always big
114 endian. The sparclet has bi-endian support but both data and insns have
115 the same endianness. Global `target_big_endian' is used for data.
116 The following macro is used for instructions. */
117#ifndef INSN_BIG_ENDIAN
118#define INSN_BIG_ENDIAN (target_big_endian \
119 || default_arch_type == sparc86x \
120 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
121#endif
122
e0c6ed95 123/* Handle of the OPCODE hash table. */
252b5132
RH		 124static struct hash_control *op_hash;
125
126static int log2 PARAMS ((int));
127static void s_data1 PARAMS ((void));
128static void s_seg PARAMS ((int));
129static void s_proc PARAMS ((int));
130static void s_reserve PARAMS ((int));
131static void s_common PARAMS ((int));
132static void s_empty PARAMS ((int));
133static void s_uacons PARAMS ((int));
cf9a1301 134static void s_ncons PARAMS ((int));
6d8809aa 135static void s_register PARAMS ((int));
252b5132
RH		 136
137const pseudo_typeS md_pseudo_table[] =
138{
e0c6ed95 139 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 140 {"common", s_common, 0},
141 {"empty", s_empty, 0},
142 {"global", s_globl, 0},
143 {"half", cons, 2},
cf9a1301 144 {"nword", s_ncons, 0},
252b5132
RH		 145 {"optim", s_ignore, 0},
146 {"proc", s_proc, 0},
147 {"reserve", s_reserve, 0},
148 {"seg", s_seg, 0},
149 {"skip", s_space, 0},
150 {"word", cons, 4},
151 {"xword", cons, 8},
152 {"uahalf", s_uacons, 2},
153 {"uaword", s_uacons, 4},
154 {"uaxword", s_uacons, 8},
155#ifdef OBJ_ELF
732d96b6
JJ		 156 {"file", dwarf2_directive_file, 0},
157 {"loc", dwarf2_directive_loc, 0},
e0c6ed95 158 /* These are specific to sparc/svr4. */
252b5132
RH		 159 {"2byte", s_uacons, 2},
160 {"4byte", s_uacons, 4},
161 {"8byte", s_uacons, 8},
6d8809aa 162 {"register", s_register, 0},
252b5132
RH		 163#endif
164 {NULL, 0, 0},
165};
166
e0c6ed95
AM		 167/* Size of relocation record. */
168const int md_reloc_size = 12;
252b5132
RH		 169
170/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 171 pre-processor is disabled, these aren't very useful. */
172const char comment_chars[] = "!"; /* JF removed '|' from
173 comment_chars. */
252b5132
RH		 174
175/* This array holds the chars that only start a comment at the beginning of
176 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 177 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 178/* Note that input_file.c hand checks for '#' at the beginning of the
179 first line of the input file. This is because the compiler outputs
e0c6ed95 180 #NO_APP at the beginning of its output. */
252b5132 181/* Also note that comments started like this one will always
e0c6ed95 182 work if '/' isn't otherwise defined. */
252b5132
RH		 183const char line_comment_chars[] = "#";
184
63a0b638 185const char line_separator_chars[] = ";";
252b5132 186
e0c6ed95
AM		 187/* Chars that can be used to separate mant from exp in floating point
188 nums. */
252b5132
RH		 189const char EXP_CHARS[] = "eE";
190
e0c6ed95
AM		 191/* Chars that mean this number is a floating point constant.
192 As in 0f12.456
193 or 0d1.2345e12 */
252b5132
RH		 194const char FLT_CHARS[] = "rRsSfFdDxXpP";
195
196/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
197 changed in read.c. Ideally it shouldn't have to know about it at all,
198 but nothing is ideal around here. */
199
bc805888 200#define isoctal(c) ((unsigned) ((c) - '0') < '8')
252b5132
RH		 201
202struct sparc_it
203 {
204 char *error;
205 unsigned long opcode;
206 struct nlist *nlistp;
207 expressionS exp;
cf9a1301 208 expressionS exp2;
252b5132
RH		 209 int pcrel;
210 bfd_reloc_code_real_type reloc;
211 };
212
213struct sparc_it the_insn, set_insn;
214
215static void output_insn
216 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
217\f
218/* Table of arguments to -A.
219 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
220 for this use. That table is for opcodes only. This table is for opcodes
221 and file formats. */
222
223enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
19f7b010 224 v8plusa, v9, v9a, v9b, v9_64};
252b5132
RH		 225
226static struct sparc_arch {
227 char *name;
228 char *opcode_arch;
229 enum sparc_arch_types arch_type;
230 /* Default word size, as specified during configuration.
231 A value of zero means can't be used to specify default architecture. */
232 int default_arch_size;
233 /* Allowable arg to -A? */
234 int user_option_p;
235} sparc_arch_table[] = {
236 { "v6", "v6", v6, 0, 1 },
237 { "v7", "v7", v7, 0, 1 },
238 { "v8", "v8", v8, 32, 1 },
239 { "sparclet", "sparclet", sparclet, 32, 1 },
240 { "sparclite", "sparclite", sparclite, 32, 1 },
241 { "sparc86x", "sparclite", sparc86x, 32, 1 },
242 { "v8plus", "v9", v9, 0, 1 },
243 { "v8plusa", "v9a", v9, 0, 1 },
19f7b010 244 { "v8plusb", "v9b", v9, 0, 1 },
252b5132
RH		 245 { "v9", "v9", v9, 0, 1 },
246 { "v9a", "v9a", v9, 0, 1 },
19f7b010 247 { "v9b", "v9b", v9, 0, 1 },
252b5132
RH		 248 /* This exists to allow configure.in/Makefile.in to pass one
249 value to specify both the default machine and default word size. */
250 { "v9-64", "v9", v9, 64, 0 },
251 { NULL, NULL, v8, 0, 0 }
252};
253
254/* Variant of default_arch */
255static enum sparc_arch_types default_arch_type;
256
257static struct sparc_arch *
258lookup_arch (name)
259 char *name;
260{
261 struct sparc_arch *sa;
262
263 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
264 if (strcmp (sa->name, name) == 0)
265 break;
266 if (sa->name == NULL)
267 return NULL;
268 return sa;
269}
270
271/* Initialize the default opcode arch and word size from the default
272 architecture name. */
273
274static void
275init_default_arch ()
276{
277 struct sparc_arch *sa = lookup_arch (default_arch);
278
279 if (sa == NULL
280 || sa->default_arch_size == 0)
281 as_fatal (_("Invalid default architecture, broken assembler."));
282
283 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
284 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
285 as_fatal (_("Bad opcode table, broken assembler."));
286 default_arch_size = sparc_arch_size = sa->default_arch_size;
287 default_init_p = 1;
288 default_arch_type = sa->arch_type;
289}
290
291/* Called by TARGET_FORMAT. */
292
293const char *
294sparc_target_format ()
295{
296 /* We don't get a chance to initialize anything before we're called,
297 so handle that now. */
298 if (! default_init_p)
299 init_default_arch ();
300
301#ifdef OBJ_AOUT
302#ifdef TE_NetBSD
303 return "a.out-sparc-netbsd";
304#else
305#ifdef TE_SPARCAOUT
306 if (target_big_endian)
307 return "a.out-sunos-big";
308 else if (default_arch_type == sparc86x && target_little_endian_data)
309 return "a.out-sunos-big";
ab3e48dc
KH		 310 else
311 return "a.out-sparc-little";
252b5132
RH		 312#else
313 return "a.out-sunos-big";
314#endif
315#endif
316#endif
317
318#ifdef OBJ_BOUT
319 return "b.out.big";
320#endif
321
322#ifdef OBJ_COFF
323#ifdef TE_LYNX
324 return "coff-sparc-lynx";
325#else
326 return "coff-sparc";
327#endif
328#endif
329
330#ifdef OBJ_ELF
331 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
332#endif
333
334 abort ();
335}
336\f
e0c6ed95 337/* md_parse_option
252b5132
RH		 338 * Invocation line includes a switch not recognized by the base assembler.
339 * See if it's a processor-specific option. These are:
340 *
341 * -bump
342 * Warn on architecture bumps. See also -A.
343 *
344 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
345 * Standard 32 bit architectures.
19f7b010 346 * -Av9, -Av9a, -Av9b
252b5132
RH		 347 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
348 * This used to only mean 64 bits, but properly specifying it
349 * complicated gcc's ASM_SPECs, so now opcode selection is
350 * specified orthogonally to word size (except when specifying
351 * the default, but that is an internal implementation detail).
19f7b010
JJ		 352 * -Av8plus, -Av8plusa, -Av8plusb
353 * Same as -Av9{,a,b}.
354 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
355 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
356 * assembler.
357 * -xarch=v9, -xarch=v9a, -xarch=v9b
358 * Same as -Av9{,a,b} -64, for compatibility with Sun's
c2158c24 359 * assembler.
252b5132
RH		 360 *
361 * Select the architecture and possibly the file format.
362 * Instructions or features not supported by the selected
363 * architecture cause fatal errors.
364 *
365 * The default is to start at v6, and bump the architecture up
366 * whenever an instruction is seen at a higher level. In 32 bit
367 * environments, v9 is not bumped up to, the user must pass
19f7b010 368 * -Av8plus{,a,b}.
252b5132
RH		 369 *
370 * If -bump is specified, a warning is printing when bumping to
371 * higher levels.
372 *
373 * If an architecture is specified, all instructions must match
374 * that architecture. Any higher level instructions are flagged
375 * as errors. Note that in the 32 bit environment specifying
376 * -Av8plus does not automatically create a v8plus object file, a
377 * v9 insn must be seen.
378 *
379 * If both an architecture and -bump are specified, the
380 * architecture starts at the specified level, but bumps are
381 * warnings. Note that we can't set `current_architecture' to
382 * the requested level in this case: in the 32 bit environment,
383 * we still must avoid creating v8plus object files unless v9
384 * insns are seen.
385 *
386 * Note:
387 * Bumping between incompatible architectures is always an
388 * error. For example, from sparclite to v9.
389 */
390
391#ifdef OBJ_ELF
392CONST char *md_shortopts = "A:K:VQ:sq";
393#else
394#ifdef OBJ_AOUT
395CONST char *md_shortopts = "A:k";
396#else
397CONST char *md_shortopts = "A:";
398#endif
399#endif
400struct option md_longopts[] = {
401#define OPTION_BUMP (OPTION_MD_BASE)
402 {"bump", no_argument, NULL, OPTION_BUMP},
403#define OPTION_SPARC (OPTION_MD_BASE + 1)
404 {"sparc", no_argument, NULL, OPTION_SPARC},
405#define OPTION_XARCH (OPTION_MD_BASE + 2)
406 {"xarch", required_argument, NULL, OPTION_XARCH},
407#ifdef OBJ_ELF
408#define OPTION_32 (OPTION_MD_BASE + 3)
409 {"32", no_argument, NULL, OPTION_32},
410#define OPTION_64 (OPTION_MD_BASE + 4)
411 {"64", no_argument, NULL, OPTION_64},
412#define OPTION_TSO (OPTION_MD_BASE + 5)
413 {"TSO", no_argument, NULL, OPTION_TSO},
414#define OPTION_PSO (OPTION_MD_BASE + 6)
415 {"PSO", no_argument, NULL, OPTION_PSO},
416#define OPTION_RMO (OPTION_MD_BASE + 7)
417 {"RMO", no_argument, NULL, OPTION_RMO},
418#endif
419#ifdef SPARC_BIENDIAN
420#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
421 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
422#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
423 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
424#endif
425#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
426 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
427#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
428 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 429#ifdef OBJ_ELF
430#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
431 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 432#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
433 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 434#endif
6faf3d66
JJ		 435#define OPTION_RELAX (OPTION_MD_BASE + 14)
436 {"relax", no_argument, NULL, OPTION_RELAX},
437#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
438 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 439 {NULL, no_argument, NULL, 0}
440};
e0c6ed95
AM		 441
442size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 443
444int
445md_parse_option (c, arg)
446 int c;
447 char *arg;
448{
449 /* We don't get a chance to initialize anything before we're called,
450 so handle that now. */
451 if (! default_init_p)
452 init_default_arch ();
453
454 switch (c)
455 {
456 case OPTION_BUMP:
457 warn_on_bump = 1;
458 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
459 break;
460
461 case OPTION_XARCH:
c2158c24
JJ		 462#ifdef OBJ_ELF
463 if (strncmp (arg, "v9", 2) != 0)
464 md_parse_option (OPTION_32, NULL);
465 else
466 md_parse_option (OPTION_64, NULL);
467#endif
e0c6ed95 468 /* Fall through. */
252b5132
RH		 469
470 case 'A':
471 {
472 struct sparc_arch *sa;
473 enum sparc_opcode_arch_val opcode_arch;
474
475 sa = lookup_arch (arg);
476 if (sa == NULL
477 || ! sa->user_option_p)
478 {
c2158c24
JJ		 479 if (c == OPTION_XARCH)
480 as_bad (_("invalid architecture -xarch=%s"), arg);
481 else
482 as_bad (_("invalid architecture -A%s"), arg);
252b5132
RH		 483 return 0;
484 }
485
486 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
487 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
488 as_fatal (_("Bad opcode table, broken assembler."));
489
490 max_architecture = opcode_arch;
491 architecture_requested = 1;
492 }
493 break;
494
495 case OPTION_SPARC:
496 /* Ignore -sparc, used by SunOS make default .s.o rule. */
497 break;
498
499 case OPTION_ENFORCE_ALIGNED_DATA:
500 enforce_aligned_data = 1;
501 break;
502
503#ifdef SPARC_BIENDIAN
504 case OPTION_LITTLE_ENDIAN:
505 target_big_endian = 0;
506 if (default_arch_type != sparclet)
507 as_fatal ("This target does not support -EL");
508 break;
509 case OPTION_LITTLE_ENDIAN_DATA:
510 target_little_endian_data = 1;
511 target_big_endian = 0;
512 if (default_arch_type != sparc86x
513 && default_arch_type != v9)
514 as_fatal ("This target does not support --little-endian-data");
515 break;
516 case OPTION_BIG_ENDIAN:
517 target_big_endian = 1;
518 break;
519#endif
520
521#ifdef OBJ_AOUT
522 case 'k':
523 sparc_pic_code = 1;
524 break;
525#endif
526
527#ifdef OBJ_ELF
528 case OPTION_32:
529 case OPTION_64:
530 {
531 const char **list, **l;
532
533 sparc_arch_size = c == OPTION_32 ? 32 : 64;
534 list = bfd_target_list ();
535 for (l = list; *l != NULL; l++)
536 {
537 if (sparc_arch_size == 32)
538 {
539 if (strcmp (*l, "elf32-sparc") == 0)
540 break;
541 }
542 else
543 {
544 if (strcmp (*l, "elf64-sparc") == 0)
545 break;
546 }
547 }
548 if (*l == NULL)
549 as_fatal (_("No compiled in support for %d bit object file format"),
550 sparc_arch_size);
551 free (list);
552 }
553 break;
554
555 case OPTION_TSO:
556 sparc_memory_model = MM_TSO;
557 break;
558
559 case OPTION_PSO:
560 sparc_memory_model = MM_PSO;
561 break;
562
563 case OPTION_RMO:
564 sparc_memory_model = MM_RMO;
565 break;
566
567 case 'V':
568 print_version_id ();
569 break;
570
571 case 'Q':
572 /* Qy - do emit .comment
e0c6ed95 573 Qn - do not emit .comment. */
252b5132
RH		 574 break;
575
576 case 's':
e0c6ed95 577 /* Use .stab instead of .stab.excl. */
252b5132
RH		 578 break;
579
580 case 'q':
e0c6ed95 581 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 582 break;
583
584 case 'K':
585 if (strcmp (arg, "PIC") != 0)
586 as_warn (_("Unrecognized option following -K"));
587 else
588 sparc_pic_code = 1;
589 break;
6d8809aa
RH		 590
591 case OPTION_NO_UNDECLARED_REGS:
592 no_undeclared_regs = 1;
593 break;
a25fe906
ILT		 594
595 case OPTION_UNDECLARED_REGS:
596 no_undeclared_regs = 0;
597 break;
252b5132
RH		 598#endif
599
6faf3d66
JJ		 600 case OPTION_RELAX:
601 sparc_relax = 1;
602 break;
603
604 case OPTION_NO_RELAX:
605 sparc_relax = 0;
606 break;
607
252b5132
RH		 608 default:
609 return 0;
610 }
611
612 return 1;
613}
614
615void
616md_show_usage (stream)
617 FILE *stream;
618{
619 const struct sparc_arch *arch;
c2158c24 620 int column;
252b5132
RH		 621
622 /* We don't get a chance to initialize anything before we're called,
623 so handle that now. */
624 if (! default_init_p)
625 init_default_arch ();
626
e0c6ed95 627 fprintf (stream, _("SPARC options:\n"));
c2158c24 628 column = 0;
252b5132
RH		 629 for (arch = &sparc_arch_table[0]; arch->name; arch++)
630 {
c2158c24
JJ		 631 if (!arch->user_option_p)
632 continue;
252b5132
RH		 633 if (arch != &sparc_arch_table[0])
634 fprintf (stream, " | ");
c2158c24
JJ		 635 if (column + strlen(arch->name) > 70)
636 {
637 column = 0;
638 fputc ('\n', stream);
639 }
640 column += 5 + 2 + strlen(arch->name);
641 fprintf (stream, "-A%s", arch->name);
252b5132 642 }
c2158c24
JJ		 643 for (arch = &sparc_arch_table[0]; arch->name; arch++)
644 {
645 if (!arch->user_option_p)
646 continue;
647 fprintf (stream, " | ");
648 if (column + strlen(arch->name) > 65)
649 {
650 column = 0;
651 fputc ('\n', stream);
652 }
653 column += 5 + 7 + strlen(arch->name);
654 fprintf (stream, "-xarch=%s", arch->name);
655 }
656 fprintf (stream, _("\n\
252b5132
RH		 657 specify variant of SPARC architecture\n\
658-bump warn when assembler switches architectures\n\
659-sparc ignored\n\
6faf3d66
JJ		 660--enforce-aligned-data force .long, etc., to be aligned correctly\n\
661-relax relax jumps and branches (default)\n\
662-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 663#ifdef OBJ_AOUT
664 fprintf (stream, _("\
665-k generate PIC\n"));
666#endif
667#ifdef OBJ_ELF
668 fprintf (stream, _("\
669-32 create 32 bit object file\n\
670-64 create 64 bit object file\n"));
671 fprintf (stream, _("\
672 [default is %d]\n"), default_arch_size);
673 fprintf (stream, _("\
674-TSO use Total Store Ordering\n\
675-PSO use Partial Store Ordering\n\
676-RMO use Relaxed Memory Ordering\n"));
677 fprintf (stream, _("\
678 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
679 fprintf (stream, _("\
680-KPIC generate PIC\n\
681-V print assembler version number\n\
a25fe906
ILT		 682-undeclared-regs ignore application global register usage without\n\
683 appropriate .register directive (default)\n\
684-no-undeclared-regs force error on application global register usage\n\
685 without appropriate .register directive\n\
252b5132
RH		 686-q ignored\n\
687-Qy, -Qn ignored\n\
688-s ignored\n"));
689#endif
690#ifdef SPARC_BIENDIAN
691 fprintf (stream, _("\
692-EL generate code for a little endian machine\n\
693-EB generate code for a big endian machine\n\
694--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 695 instructions and little endian data.\n"));
252b5132
RH		 696#endif
697}
698\f
e0c6ed95 699/* Native operand size opcode translation. */
cf9a1301
RH		 700struct
701 {
702 char *name;
703 char *name32;
704 char *name64;
705 } native_op_table[] =
706{
707 {"ldn", "ld", "ldx"},
708 {"ldna", "lda", "ldxa"},
709 {"stn", "st", "stx"},
710 {"stna", "sta", "stxa"},
711 {"slln", "sll", "sllx"},
712 {"srln", "srl", "srlx"},
713 {"sran", "sra", "srax"},
714 {"casn", "cas", "casx"},
715 {"casna", "casa", "casxa"},
716 {"clrn", "clr", "clrx"},
717 {NULL, NULL, NULL},
718};
719\f
e0c6ed95 720/* sparc64 priviledged registers. */
252b5132
RH		 721
722struct priv_reg_entry
ab3e48dc
KH		 723{
724 char *name;
725 int regnum;
726};
252b5132
RH		 727
728struct priv_reg_entry priv_reg_table[] =
729{
730 {"tpc", 0},
731 {"tnpc", 1},
732 {"tstate", 2},
733 {"tt", 3},
734 {"tick", 4},
735 {"tba", 5},
736 {"pstate", 6},
737 {"tl", 7},
738 {"pil", 8},
739 {"cwp", 9},
740 {"cansave", 10},
741 {"canrestore", 11},
742 {"cleanwin", 12},
743 {"otherwin", 13},
744 {"wstate", 14},
745 {"fq", 15},
746 {"ver", 31},
e0c6ed95 747 {"", -1}, /* End marker. */
252b5132
RH		 748};
749
e0c6ed95 750/* v9a specific asrs. */
252b5132
RH		 751
752struct priv_reg_entry v9a_asr_table[] =
753{
754 {"tick_cmpr", 23},
19f7b010
JJ		 755 {"sys_tick_cmpr", 25},
756 {"sys_tick", 24},
252b5132
RH		 757 {"softint", 22},
758 {"set_softint", 20},
759 {"pic", 17},
760 {"pcr", 16},
761 {"gsr", 19},
762 {"dcr", 18},
763 {"clear_softint", 21},
e0c6ed95 764 {"", -1}, /* End marker. */
252b5132
RH		 765};
766
767static int
768cmp_reg_entry (parg, qarg)
769 const PTR parg;
770 const PTR qarg;
771{
772 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
773 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
774
775 return strcmp (q->name, p->name);
776}
777\f
778/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 779 set up all the tables, etc. that the MD part of the assembler will
780 need. */
252b5132
RH		 781
782void
783md_begin ()
784{
785 register const char *retval = NULL;
786 int lose = 0;
787 register unsigned int i = 0;
788
789 /* We don't get a chance to initialize anything before md_parse_option
790 is called, and it may not be called, so handle default initialization
791 now if not already done. */
792 if (! default_init_p)
793 init_default_arch ();
794
795 op_hash = hash_new ();
796
797 while (i < (unsigned int) sparc_num_opcodes)
798 {
799 const char *name = sparc_opcodes[i].name;
800 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
801 if (retval != NULL)
802 {
cf9a1301
RH		 803 as_bad (_("Internal error: can't hash `%s': %s\n"),
804 sparc_opcodes[i].name, retval);
252b5132
RH		 805 lose = 1;
806 }
807 do
808 {
809 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
810 {
cf9a1301
RH		 811 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
812 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 813 lose = 1;
814 }
815 ++i;
816 }
817 while (i < (unsigned int) sparc_num_opcodes
818 && !strcmp (sparc_opcodes[i].name, name));
819 }
820
cf9a1301
RH		 821 for (i = 0; native_op_table[i].name; i++)
822 {
823 const struct sparc_opcode *insn;
3d4ae3c0
NC		 824 char *name = ((sparc_arch_size == 32)
825 ? native_op_table[i].name32
826 : native_op_table[i].name64);
e0c6ed95 827 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 828 if (insn == NULL)
e0c6ed95
AM		 829 {
830 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
831 name, native_op_table[i].name);
832 lose = 1;
833 }
cf9a1301
RH		 834 else
835 {
836 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
837 if (retval != NULL)
838 {
839 as_bad (_("Internal error: can't hash `%s': %s\n"),
840 sparc_opcodes[i].name, retval);
841 lose = 1;
842 }
843 }
844 }
845
252b5132
RH		 846 if (lose)
847 as_fatal (_("Broken assembler. No assembly attempted."));
848
252b5132
RH		 849 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
850 sizeof (priv_reg_table[0]), cmp_reg_entry);
851
852 /* If -bump, record the architecture level at which we start issuing
853 warnings. The behaviour is different depending upon whether an
854 architecture was explicitly specified. If it wasn't, we issue warnings
855 for all upwards bumps. If it was, we don't start issuing warnings until
856 we need to bump beyond the requested architecture or when we bump between
857 conflicting architectures. */
858
859 if (warn_on_bump
860 && architecture_requested)
861 {
862 /* `max_architecture' records the requested architecture.
863 Issue warnings if we go above it. */
864 warn_after_architecture = max_architecture;
865
866 /* Find the highest architecture level that doesn't conflict with
867 the requested one. */
868 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
869 max_architecture > warn_after_architecture;
870 --max_architecture)
871 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
872 warn_after_architecture))
873 break;
874 }
875}
876
877/* Called after all assembly has been done. */
878
879void
880sparc_md_end ()
881{
19f7b010
JJ		 882 unsigned long mach = bfd_mach_sparc;
883
252b5132 884 if (sparc_arch_size == 64)
19f7b010
JJ		 885 switch (current_architecture)
886 {
887 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
888 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
889 default: mach = bfd_mach_sparc_v9; break;
890 }
252b5132 891 else
19f7b010
JJ		 892 switch (current_architecture)
893 {
894 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
895 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
896 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
897 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
898 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
899 be but for now it is (since that's the way it's always been
900 treated). */
901 default: break;
902 }
903 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
252b5132
RH		 904}
905\f
906/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
907
908static INLINE int
909in_signed_range (val, max)
910 bfd_signed_vma val, max;
911{
912 if (max <= 0)
913 abort ();
914 /* Sign-extend the value from the architecture word size, so that
915 0xffffffff is always considered -1 on sparc32. */
916 if (sparc_arch_size == 32)
917 {
e0c6ed95 918 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
252b5132
RH		 919 val = ((val & 0xffffffff) ^ sign) - sign;
920 }
921 if (val > max)
922 return 0;
923 if (val < ~max)
924 return 0;
925 return 1;
926}
927
928/* Return non-zero if VAL is in the range 0 to MAX. */
929
930static INLINE int
931in_unsigned_range (val, max)
932 bfd_vma val, max;
933{
934 if (val > max)
935 return 0;
936 return 1;
937}
938
939/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
940 (e.g. -15 to +31). */
941
942static INLINE int
943in_bitfield_range (val, max)
944 bfd_signed_vma val, max;
945{
946 if (max <= 0)
947 abort ();
948 if (val > max)
949 return 0;
950 if (val < ~(max >> 1))
951 return 0;
952 return 1;
953}
954
955static int
956sparc_ffs (mask)
957 unsigned int mask;
958{
959 int i;
960
961 if (mask == 0)
962 return -1;
963
964 for (i = 0; (mask & 1) == 0; ++i)
965 mask >>= 1;
966 return i;
967}
968
969/* Implement big shift right. */
970static bfd_vma
971BSR (val, amount)
972 bfd_vma val;
973 int amount;
974{
975 if (sizeof (bfd_vma) <= 4 && amount >= 32)
976 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
977 return val >> amount;
978}
979\f
980/* For communication between sparc_ip and get_expression. */
981static char *expr_end;
982
252b5132
RH		 983/* Values for `special_case'.
984 Instructions that require wierd handling because they're longer than
985 4 bytes. */
986#define SPECIAL_CASE_NONE 0
987#define SPECIAL_CASE_SET 1
988#define SPECIAL_CASE_SETSW 2
989#define SPECIAL_CASE_SETX 3
990/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
991#define SPECIAL_CASE_FDIV 4
992
993/* Bit masks of various insns. */
994#define NOP_INSN 0x01000000
995#define OR_INSN 0x80100000
63fab58c 996#define XOR_INSN 0x80180000
252b5132
RH		 997#define FMOVS_INSN 0x81A00020
998#define SETHI_INSN 0x01000000
999#define SLLX_INSN 0x81281000
1000#define SRA_INSN 0x81380000
1001
1002/* The last instruction to be assembled. */
1003static const struct sparc_opcode *last_insn;
1004/* The assembled opcode of `last_insn'. */
1005static unsigned long last_opcode;
1006\f
a22b281c 1007/* Handle the set and setuw synthetic instructions. */
e0c6ed95 1008
a22b281c
RH		 1009static void
1010synthetize_setuw (insn)
1011 const struct sparc_opcode *insn;
1012{
1013 int need_hi22_p = 0;
1014 int rd = (the_insn.opcode & RD (~0)) >> 25;
1015
1016 if (the_insn.exp.X_op == O_constant)
1017 {
1018 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1019 {
e0c6ed95 1020 if (sizeof (offsetT) > 4
a22b281c
RH		 1021 && (the_insn.exp.X_add_number < 0
1022 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1023 as_warn (_("set: number not in 0..4294967295 range"));
1024 }
1025 else
1026 {
e0c6ed95 1027 if (sizeof (offsetT) > 4
a22b281c
RH		 1028 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1029 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1030 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 1031 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1032 }
1033 }
1034
1035 /* See if operand is absolute and small; skip sethi if so. */
1036 if (the_insn.exp.X_op != O_constant
1037 || the_insn.exp.X_add_number >= (1 << 12)
1038 || the_insn.exp.X_add_number < -(1 << 12))
1039 {
1040 the_insn.opcode = (SETHI_INSN | RD (rd)
1041 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1042 & (the_insn.exp.X_op == O_constant
1043 ? 0x3fffff : 0)));
a22b281c 1044 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1045 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1046 output_insn (insn, &the_insn);
1047 need_hi22_p = 1;
1048 }
1049
1050 /* See if operand has no low-order bits; skip OR if so. */
1051 if (the_insn.exp.X_op != O_constant
1052 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1053 || ! need_hi22_p)
1054 {
1055 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1056 | RD (rd) | IMMED
1057 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1058 & (the_insn.exp.X_op != O_constant
1059 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1060 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1061 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1062 output_insn (insn, &the_insn);
1063 }
1064}
e0c6ed95 1065
a22b281c 1066/* Handle the setsw synthetic instruction. */
e0c6ed95 1067
a22b281c
RH		 1068static void
1069synthetize_setsw (insn)
1070 const struct sparc_opcode *insn;
1071{
1072 int low32, rd, opc;
1073
1074 rd = (the_insn.opcode & RD (~0)) >> 25;
1075
1076 if (the_insn.exp.X_op != O_constant)
1077 {
1078 synthetize_setuw (insn);
1079
1080 /* Need to sign extend it. */
1081 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1082 the_insn.reloc = BFD_RELOC_NONE;
1083 output_insn (insn, &the_insn);
1084 return;
1085 }
1086
e0c6ed95 1087 if (sizeof (offsetT) > 4
a22b281c
RH		 1088 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1089 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1090 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1091
e0c6ed95
AM		 1092 low32 = the_insn.exp.X_add_number;
1093
a22b281c
RH		 1094 if (low32 >= 0)
1095 {
1096 synthetize_setuw (insn);
1097 return;
1098 }
1099
1100 opc = OR_INSN;
e0c6ed95 1101
a22b281c
RH		 1102 the_insn.reloc = BFD_RELOC_NONE;
1103 /* See if operand is absolute and small; skip sethi if so. */
1104 if (low32 < -(1 << 12))
1105 {
1106 the_insn.opcode = (SETHI_INSN | RD (rd)
1107 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1108 output_insn (insn, &the_insn);
1109 low32 = 0x1c00 | (low32 & 0x3ff);
1110 opc = RS1 (rd) | XOR_INSN;
1111 }
1112
1113 the_insn.opcode = (opc | RD (rd) | IMMED
1114 | (low32 & 0x1fff));
1115 output_insn (insn, &the_insn);
1116}
1117
1118/* Handle the setsw synthetic instruction. */
e0c6ed95 1119
a22b281c
RH		 1120static void
1121synthetize_setx (insn)
1122 const struct sparc_opcode *insn;
1123{
1124 int upper32, lower32;
1125 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1126 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1127 int upper_dstreg;
1128 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1129 int need_xor10_p = 0;
e0c6ed95 1130
a22b281c
RH		 1131#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1132 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1133 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1134#undef SIGNEXT32
1135
1136 upper_dstreg = tmpreg;
1137 /* The tmp reg should not be the dst reg. */
1138 if (tmpreg == dstreg)
1139 as_warn (_("setx: temporary register same as destination register"));
1140
1141 /* ??? Obviously there are other optimizations we can do
1142 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1143 doing some of these. Later. If you do change things, try to
1144 change all of this to be table driven as well. */
1145 /* What to output depends on the number if it's constant.
1146 Compute that first, then output what we've decided upon. */
1147 if (the_insn.exp.X_op != O_constant)
1148 {
1149 if (sparc_arch_size == 32)
1150 {
1151 /* When arch size is 32, we want setx to be equivalent
1152 to setuw for anything but constants. */
1153 the_insn.exp.X_add_number &= 0xffffffff;
1154 synthetize_setuw (insn);
1155 return;
1156 }
1157 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1158 lower32 = 0;
1159 upper32 = 0;
a22b281c
RH		 1160 }
1161 else
1162 {
1163 /* Reset X_add_number, we've extracted it as upper32/lower32.
1164 Otherwise fixup_segment will complain about not being able to
1165 write an 8 byte number in a 4 byte field. */
1166 the_insn.exp.X_add_number = 0;
e0c6ed95 1167
a22b281c
RH		 1168 /* Only need hh22 if `or' insn can't handle constant. */
1169 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1170 need_hh22_p = 1;
e0c6ed95 1171
a22b281c
RH		 1172 /* Does bottom part (after sethi) have bits? */
1173 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1174 /* No hh22, but does upper32 still have bits we can't set
1175 from lower32? */
1176 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1177 need_hm10_p = 1;
e0c6ed95 1178
a22b281c
RH		 1179 /* If the lower half is all zero, we build the upper half directly
1180 into the dst reg. */
1181 if (lower32 != 0
1182 /* Need lower half if number is zero or 0xffffffff00000000. */
1183 || (! need_hh22_p && ! need_hm10_p))
1184 {
1185 /* No need for sethi if `or' insn can handle constant. */
1186 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1187 /* Note that we can't use a negative constant in the `or'
1188 insn unless the upper 32 bits are all ones. */
1189 || (lower32 < 0 && upper32 != -1)
1190 || (lower32 >= 0 && upper32 == -1))
1191 need_hi22_p = 1;
e0c6ed95 1192
a22b281c
RH		 1193 if (need_hi22_p && upper32 == -1)
1194 need_xor10_p = 1;
1195
1196 /* Does bottom part (after sethi) have bits? */
1197 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1198 /* No sethi. */
1199 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1200 /* Need `or' if we didn't set anything else. */
1201 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1202 need_lo10_p = 1;
1203 }
1204 else
1205 /* Output directly to dst reg if lower 32 bits are all zero. */
1206 upper_dstreg = dstreg;
1207 }
e0c6ed95 1208
a22b281c
RH		 1209 if (!upper_dstreg && dstreg)
1210 as_warn (_("setx: illegal temporary register g0"));
1211
1212 if (need_hh22_p)
1213 {
1214 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1215 | ((upper32 >> 10) & 0x3fffff));
1216 the_insn.reloc = (the_insn.exp.X_op != O_constant
1217 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1218 output_insn (insn, &the_insn);
1219 }
e0c6ed95 1220
a22b281c
RH		 1221 if (need_hi22_p)
1222 {
1223 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1224 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1225 >> 10) & 0x3fffff));
a22b281c
RH		 1226 the_insn.reloc = (the_insn.exp.X_op != O_constant
1227 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1228 output_insn (insn, &the_insn);
1229 }
1230
1231 if (need_hm10_p)
1232 {
1233 the_insn.opcode = (OR_INSN
1234 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1235 | RD (upper_dstreg)
1236 | IMMED
1237 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1238 the_insn.reloc = (the_insn.exp.X_op != O_constant
1239 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1240 output_insn (insn, &the_insn);
1241 }
e0c6ed95 1242
a22b281c
RH		 1243 if (need_lo10_p)
1244 {
1245 /* FIXME: One nice optimization to do here is to OR the low part
1246 with the highpart if hi22 isn't needed and the low part is
1247 positive. */
1248 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1249 | RD (dstreg)
1250 | IMMED
1251 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1252 the_insn.reloc = (the_insn.exp.X_op != O_constant
1253 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1254 output_insn (insn, &the_insn);
1255 }
e0c6ed95 1256
a22b281c
RH		 1257 /* If we needed to build the upper part, shift it into place. */
1258 if (need_hh22_p || need_hm10_p)
1259 {
1260 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1261 | IMMED | 32);
1262 the_insn.reloc = BFD_RELOC_NONE;
1263 output_insn (insn, &the_insn);
1264 }
e0c6ed95 1265
a22b281c
RH		 1266 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1267 if (need_xor10_p)
1268 {
1269 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1270 | 0x1c00 | (lower32 & 0x3ff));
1271 the_insn.reloc = BFD_RELOC_NONE;
1272 output_insn (insn, &the_insn);
1273 }
1274
1275 /* If we needed to build both upper and lower parts, OR them together. */
1276 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1277 {
1278 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1279 | RD (dstreg));
1280 the_insn.reloc = BFD_RELOC_NONE;
1281 output_insn (insn, &the_insn);
1282 }
1283}
1284\f
252b5132
RH		 1285/* Main entry point to assemble one instruction. */
1286
1287void
1288md_assemble (str)
1289 char *str;
1290{
1291 const struct sparc_opcode *insn;
a22b281c 1292 int special_case;
252b5132
RH		 1293
1294 know (str);
a22b281c 1295 special_case = sparc_ip (str, &insn);
252b5132
RH		 1296
1297 /* We warn about attempts to put a floating point branch in a delay slot,
1298 unless the delay slot has been annulled. */
1299 if (insn != NULL
1300 && last_insn != NULL
1301 && (insn->flags & F_FBR) != 0
1302 && (last_insn->flags & F_DELAYED) != 0
1303 /* ??? This test isn't completely accurate. We assume anything with
1304 F_{UNBR,CONDBR,FBR} set is annullable. */
1305 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1306 || (last_opcode & ANNUL) == 0))
1307 as_warn (_("FP branch in delay slot"));
1308
1309 /* SPARC before v9 requires a nop instruction between a floating
1310 point instruction and a floating point branch. We insert one
1311 automatically, with a warning. */
1312 if (max_architecture < SPARC_OPCODE_ARCH_V9
1313 && insn != NULL
1314 && last_insn != NULL
1315 && (insn->flags & F_FBR) != 0
1316 && (last_insn->flags & F_FLOAT) != 0)
1317 {
1318 struct sparc_it nop_insn;
1319
1320 nop_insn.opcode = NOP_INSN;
1321 nop_insn.reloc = BFD_RELOC_NONE;
1322 output_insn (insn, &nop_insn);
1323 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1324 }
1325
a22b281c
RH		 1326 switch (special_case)
1327 {
1328 case SPECIAL_CASE_NONE:
e0c6ed95 1329 /* Normal insn. */
a22b281c
RH		 1330 output_insn (insn, &the_insn);
1331 break;
252b5132 1332
a22b281c
RH		 1333 case SPECIAL_CASE_SETSW:
1334 synthetize_setsw (insn);
1335 break;
e0c6ed95 1336
a22b281c
RH		 1337 case SPECIAL_CASE_SET:
1338 synthetize_setuw (insn);
1339 break;
252b5132 1340
a22b281c
RH		 1341 case SPECIAL_CASE_SETX:
1342 synthetize_setx (insn);
1343 break;
e0c6ed95 1344
a22b281c
RH		 1345 case SPECIAL_CASE_FDIV:
1346 {
1347 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1348
a22b281c 1349 output_insn (insn, &the_insn);
e0c6ed95 1350
a22b281c
RH		 1351 /* According to information leaked from Sun, the "fdiv" instructions
1352 on early SPARC machines would produce incorrect results sometimes.
1353 The workaround is to add an fmovs of the destination register to
1354 itself just after the instruction. This was true on machines
e0c6ed95 1355 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
a22b281c
RH		 1356 assert (the_insn.reloc == BFD_RELOC_NONE);
1357 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1358 output_insn (insn, &the_insn);
1359 return;
1360 }
e0c6ed95 1361
a22b281c
RH		 1362 default:
1363 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1364 }
1365}
1366
1367/* Subroutine of md_assemble to do the actual parsing. */
1368
a22b281c 1369static int
252b5132
RH		 1370sparc_ip (str, pinsn)
1371 char *str;
1372 const struct sparc_opcode **pinsn;
1373{
1374 char *error_message = "";
1375 char *s;
1376 const char *args;
1377 char c;
1378 const struct sparc_opcode *insn;
1379 char *argsStart;
1380 unsigned long opcode;
1381 unsigned int mask = 0;
1382 int match = 0;
1383 int comma = 0;
1384 int v9_arg_p;
a22b281c 1385 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1386
1387 s = str;
1388 if (islower ((unsigned char) *s))
1389 {
1390 do
1391 ++s;
1392 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1393 }
1394
1395 switch (*s)
1396 {
1397 case '\0':
1398 break;
1399
1400 case ',':
1401 comma = 1;
e0c6ed95 1402 /* Fall through. */
252b5132
RH		 1403
1404 case ' ':
1405 *s++ = '\0';
1406 break;
1407
1408 default:
1409 as_fatal (_("Unknown opcode: `%s'"), str);
1410 }
1411 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1412 *pinsn = insn;
1413 if (insn == NULL)
1414 {
1415 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1416 return special_case;
252b5132
RH		 1417 }
1418 if (comma)
1419 {
1420 *--s = ',';
1421 }
1422
1423 argsStart = s;
1424 for (;;)
1425 {
1426 opcode = insn->match;
1427 memset (&the_insn, '\0', sizeof (the_insn));
1428 the_insn.reloc = BFD_RELOC_NONE;
1429 v9_arg_p = 0;
1430
e0c6ed95
AM		 1431 /* Build the opcode, checking as we go to make sure that the
1432 operands match. */
252b5132
RH		 1433 for (args = insn->args;; ++args)
1434 {
1435 switch (*args)
1436 {
1437 case 'K':
1438 {
1439 int kmask = 0;
1440
1441 /* Parse a series of masks. */
1442 if (*s == '#')
1443 {
1444 while (*s == '#')
1445 {
1446 int mask;
1447
1448 if (! parse_keyword_arg (sparc_encode_membar, &s,
1449 &mask))
1450 {
1451 error_message = _(": invalid membar mask name");
1452 goto error;
1453 }
1454 kmask |= mask;
47926f60
KH		 1455 while (*s == ' ')
1456 ++s;
252b5132
RH		 1457 if (*s == '|' || *s == '+')
1458 ++s;
47926f60
KH		 1459 while (*s == ' ')
1460 ++s;
252b5132
RH		 1461 }
1462 }
1463 else
1464 {
1465 if (! parse_const_expr_arg (&s, &kmask))
1466 {
1467 error_message = _(": invalid membar mask expression");
1468 goto error;
1469 }
1470 if (kmask < 0 || kmask > 127)
1471 {
1472 error_message = _(": invalid membar mask number");
1473 goto error;
1474 }
1475 }
1476
1477 opcode |= MEMBAR (kmask);
1478 continue;
1479 }
1480
19f7b010
JJ		 1481 case '3':
1482 {
1483 int smask = 0;
1484
1485 if (! parse_const_expr_arg (&s, &smask))
1486 {
1487 error_message = _(": invalid siam mode expression");
1488 goto error;
1489 }
1490 if (smask < 0 || smask > 7)
1491 {
1492 error_message = _(": invalid siam mode number");
1493 goto error;
1494 }
1495 opcode |= smask;
1496 continue;
1497 }
1498
252b5132
RH		 1499 case '*':
1500 {
1501 int fcn = 0;
1502
1503 /* Parse a prefetch function. */
1504 if (*s == '#')
1505 {
1506 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1507 {
1508 error_message = _(": invalid prefetch function name");
1509 goto error;
1510 }
1511 }
1512 else
1513 {
1514 if (! parse_const_expr_arg (&s, &fcn))
1515 {
1516 error_message = _(": invalid prefetch function expression");
1517 goto error;
1518 }
1519 if (fcn < 0 || fcn > 31)
1520 {
1521 error_message = _(": invalid prefetch function number");
1522 goto error;
1523 }
1524 }
1525 opcode |= RD (fcn);
1526 continue;
1527 }
1528
1529 case '!':
1530 case '?':
1531 /* Parse a sparc64 privileged register. */
1532 if (*s == '%')
1533 {
1534 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1535 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1536
1537 s += 1;
1538 while (p->name[0] > s[0])
1539 p++;
1540 while (p->name[0] == s[0])
1541 {
1542 len = strlen (p->name);
1543 if (strncmp (p->name, s, len) == 0)
1544 break;
1545 p++;
1546 }
1547 if (p->name[0] != s[0])
1548 {
1549 error_message = _(": unrecognizable privileged register");
1550 goto error;
1551 }
1552 if (*args == '?')
1553 opcode |= (p->regnum << 14);
1554 else
1555 opcode |= (p->regnum << 25);
1556 s += len;
1557 continue;
1558 }
1559 else
1560 {
1561 error_message = _(": unrecognizable privileged register");
1562 goto error;
1563 }
1564
1565 case '_':
1566 case '/':
19f7b010 1567 /* Parse a v9a/v9b ancillary state register. */
252b5132
RH		 1568 if (*s == '%')
1569 {
1570 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1571 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1572
1573 s += 1;
1574 while (p->name[0] > s[0])
1575 p++;
1576 while (p->name[0] == s[0])
1577 {
1578 len = strlen (p->name);
1579 if (strncmp (p->name, s, len) == 0)
1580 break;
1581 p++;
1582 }
1583 if (p->name[0] != s[0])
1584 {
19f7b010 1585 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1586 goto error;
1587 }
1588 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1589 {
1590 error_message = _(": rd on write only ancillary state register");
1591 goto error;
e0c6ed95 1592 }
19f7b010
JJ		 1593 if (p->regnum >= 24
1594 && (insn->architecture
1595 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1596 {
1597 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1598 error_message = _(": unrecognizable v9a ancillary state register");
1599 goto error;
1600 }
252b5132
RH		 1601 if (*args == '/')
1602 opcode |= (p->regnum << 14);
1603 else
1604 opcode |= (p->regnum << 25);
1605 s += len;
1606 continue;
1607 }
1608 else
1609 {
19f7b010 1610 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1611 goto error;
1612 }
1613
1614 case 'M':
1615 case 'm':
1616 if (strncmp (s, "%asr", 4) == 0)
1617 {
1618 s += 4;
1619
1620 if (isdigit ((unsigned char) *s))
1621 {
1622 long num = 0;
1623
1624 while (isdigit ((unsigned char) *s))
1625 {
1626 num = num * 10 + *s - '0';
1627 ++s;
1628 }
1629
1630 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1631 {
1632 if (num < 16 || 31 < num)
1633 {
1634 error_message = _(": asr number must be between 16 and 31");
1635 goto error;
1636 }
1637 }
1638 else
1639 {
1640 if (num < 0 || 31 < num)
1641 {
1642 error_message = _(": asr number must be between 0 and 31");
1643 goto error;
1644 }
1645 }
1646
1647 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1648 continue;
1649 }
1650 else
1651 {
1652 error_message = _(": expecting %asrN");
1653 goto error;
1654 }
e0c6ed95 1655 } /* if %asr */
252b5132
RH		 1656 break;
1657
1658 case 'I':
1659 the_insn.reloc = BFD_RELOC_SPARC_11;
1660 goto immediate;
1661
1662 case 'j':
1663 the_insn.reloc = BFD_RELOC_SPARC_10;
1664 goto immediate;
1665
1666 case 'X':
1667 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1668 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1669 the_insn.reloc = BFD_RELOC_SPARC_5;
1670 else
1671 the_insn.reloc = BFD_RELOC_SPARC13;
1672 /* These fields are unsigned, but for upward compatibility,
1673 allow negative values as well. */
1674 goto immediate;
1675
1676 case 'Y':
1677 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1678 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1679 the_insn.reloc = BFD_RELOC_SPARC_6;
1680 else
1681 the_insn.reloc = BFD_RELOC_SPARC13;
1682 /* These fields are unsigned, but for upward compatibility,
1683 allow negative values as well. */
1684 goto immediate;
1685
1686 case 'k':
1687 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1688 the_insn.pcrel = 1;
1689 goto immediate;
1690
1691 case 'G':
1692 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1693 the_insn.pcrel = 1;
1694 goto immediate;
1695
1696 case 'N':
1697 if (*s == 'p' && s[1] == 'n')
1698 {
1699 s += 2;
1700 continue;
1701 }
1702 break;
1703
1704 case 'T':
1705 if (*s == 'p' && s[1] == 't')
1706 {
1707 s += 2;
1708 continue;
1709 }
1710 break;
1711
1712 case 'z':
1713 if (*s == ' ')
1714 {
1715 ++s;
1716 }
1717 if (strncmp (s, "%icc", 4) == 0)
1718 {
1719 s += 4;
1720 continue;
1721 }
1722 break;
1723
1724 case 'Z':
1725 if (*s == ' ')
1726 {
1727 ++s;
1728 }
1729 if (strncmp (s, "%xcc", 4) == 0)
1730 {
1731 s += 4;
1732 continue;
1733 }
1734 break;
1735
1736 case '6':
1737 if (*s == ' ')
1738 {
1739 ++s;
1740 }
1741 if (strncmp (s, "%fcc0", 5) == 0)
1742 {
1743 s += 5;
1744 continue;
1745 }
1746 break;
1747
1748 case '7':
1749 if (*s == ' ')
1750 {
1751 ++s;
1752 }
1753 if (strncmp (s, "%fcc1", 5) == 0)
1754 {
1755 s += 5;
1756 continue;
1757 }
1758 break;
1759
1760 case '8':
1761 if (*s == ' ')
1762 {
1763 ++s;
1764 }
1765 if (strncmp (s, "%fcc2", 5) == 0)
1766 {
1767 s += 5;
1768 continue;
1769 }
1770 break;
1771
1772 case '9':
1773 if (*s == ' ')
1774 {
1775 ++s;
1776 }
1777 if (strncmp (s, "%fcc3", 5) == 0)
1778 {
1779 s += 5;
1780 continue;
1781 }
1782 break;
1783
1784 case 'P':
1785 if (strncmp (s, "%pc", 3) == 0)
1786 {
1787 s += 3;
1788 continue;
1789 }
1790 break;
1791
1792 case 'W':
1793 if (strncmp (s, "%tick", 5) == 0)
1794 {
1795 s += 5;
1796 continue;
1797 }
1798 break;
1799
e0c6ed95 1800 case '\0': /* End of args. */
252b5132
RH		 1801 if (*s == '\0')
1802 {
1803 match = 1;
1804 }
1805 break;
1806
1807 case '+':
1808 if (*s == '+')
1809 {
1810 ++s;
1811 continue;
1812 }
1813 if (*s == '-')
1814 {
1815 continue;
1816 }
1817 break;
1818
e0c6ed95 1819 case '[': /* These must match exactly. */
252b5132
RH		 1820 case ']':
1821 case ',':
1822 case ' ':
1823 if (*s++ == *args)
1824 continue;
1825 break;
1826
e0c6ed95 1827 case '#': /* Must be at least one digit. */
252b5132
RH		 1828 if (isdigit ((unsigned char) *s++))
1829 {
1830 while (isdigit ((unsigned char) *s))
1831 {
1832 ++s;
1833 }
1834 continue;
1835 }
1836 break;
1837
e0c6ed95 1838 case 'C': /* Coprocessor state register. */
252b5132
RH		 1839 if (strncmp (s, "%csr", 4) == 0)
1840 {
1841 s += 4;
1842 continue;
1843 }
1844 break;
1845
e0c6ed95 1846 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 1847 case 'c':
1848 case 'D':
1849 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1850 {
1851 mask = *s++;
1852 if (isdigit ((unsigned char) *s))
1853 {
1854 mask = 10 * (mask - '0') + (*s++ - '0');
1855 if (mask >= 32)
1856 {
1857 break;
1858 }
1859 }
1860 else
1861 {
1862 mask -= '0';
1863 }
1864 switch (*args)
1865 {
1866
1867 case 'b':
1868 opcode |= mask << 14;
1869 continue;
1870
1871 case 'c':
1872 opcode |= mask;
1873 continue;
1874
1875 case 'D':
1876 opcode |= mask << 25;
1877 continue;
1878 }
1879 }
1880 break;
1881
1882 case 'r': /* next operand must be a register */
1883 case 'O':
1884 case '1':
1885 case '2':
1886 case 'd':
1887 if (*s++ == '%')
1888 {
1889 switch (c = *s++)
1890 {
1891
1892 case 'f': /* frame pointer */
1893 if (*s++ == 'p')
1894 {
1895 mask = 0x1e;
1896 break;
1897 }
1898 goto error;
1899
1900 case 'g': /* global register */
a22b281c
RH		 1901 c = *s++;
1902 if (isoctal (c))
252b5132
RH		 1903 {
1904 mask = c - '0';
1905 break;
1906 }
1907 goto error;
1908
1909 case 'i': /* in register */
a22b281c
RH		 1910 c = *s++;
1911 if (isoctal (c))
252b5132
RH		 1912 {
1913 mask = c - '0' + 24;
1914 break;
1915 }
1916 goto error;
1917
1918 case 'l': /* local register */
a22b281c
RH		 1919 c = *s++;
1920 if (isoctal (c))
252b5132
RH		 1921 {
1922 mask = (c - '0' + 16);
1923 break;
1924 }
1925 goto error;
1926
1927 case 'o': /* out register */
a22b281c
RH		 1928 c = *s++;
1929 if (isoctal (c))
252b5132
RH		 1930 {
1931 mask = (c - '0' + 8);
1932 break;
1933 }
1934 goto error;
1935
1936 case 's': /* stack pointer */
1937 if (*s++ == 'p')
1938 {
1939 mask = 0xe;
1940 break;
1941 }
1942 goto error;
1943
1944 case 'r': /* any register */
1945 if (!isdigit ((unsigned char) (c = *s++)))
1946 {
1947 goto error;
1948 }
1949 /* FALLTHROUGH */
1950 case '0':
1951 case '1':
1952 case '2':
1953 case '3':
1954 case '4':
1955 case '5':
1956 case '6':
1957 case '7':
1958 case '8':
1959 case '9':
1960 if (isdigit ((unsigned char) *s))
1961 {
1962 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1963 {
1964 goto error;
1965 }
1966 }
1967 else
1968 {
1969 c -= '0';
1970 }
1971 mask = c;
1972 break;
1973
1974 default:
1975 goto error;
1976 }
1977
6d8809aa 1978 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 1979 && no_undeclared_regs && ! globals[mask])
79bd78be 1980 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 1981
252b5132
RH		 1982 /* Got the register, now figure out where
1983 it goes in the opcode. */
1984 switch (*args)
1985 {
1986 case '1':
1987 opcode |= mask << 14;
1988 continue;
1989
1990 case '2':
1991 opcode |= mask;
1992 continue;
1993
1994 case 'd':
1995 opcode |= mask << 25;
1996 continue;
1997
1998 case 'r':
1999 opcode |= (mask << 25) | (mask << 14);
2000 continue;
2001
2002 case 'O':
2003 opcode |= (mask << 25) | (mask << 0);
2004 continue;
2005 }
2006 }
2007 break;
2008
2009 case 'e': /* next operand is a floating point register */
2010 case 'v':
2011 case 'V':
2012
2013 case 'f':
2014 case 'B':
2015 case 'R':
2016
2017 case 'g':
2018 case 'H':
2019 case 'J':
2020 {
2021 char format;
2022
2023 if (*s++ == '%'
2024 && ((format = *s) == 'f')
2025 && isdigit ((unsigned char) *++s))
2026 {
2027 for (mask = 0; isdigit ((unsigned char) *s); ++s)
2028 {
2029 mask = 10 * mask + (*s - '0');
2030 } /* read the number */
2031
2032 if ((*args == 'v'
2033 || *args == 'B'
2034 || *args == 'H')
2035 && (mask & 1))
2036 {
2037 break;
2038 } /* register must be even numbered */
2039
2040 if ((*args == 'V'
2041 || *args == 'R'
2042 || *args == 'J')
2043 && (mask & 3))
2044 {
2045 break;
2046 } /* register must be multiple of 4 */
2047
2048 if (mask >= 64)
2049 {
2050 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2051 error_message = _(": There are only 64 f registers; [0-63]");
2052 else
2053 error_message = _(": There are only 32 f registers; [0-31]");
2054 goto error;
2055 } /* on error */
2056 else if (mask >= 32)
2057 {
2058 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2059 {
2060 v9_arg_p = 1;
2061 mask -= 31; /* wrap high bit */
2062 }
2063 else
2064 {
2065 error_message = _(": There are only 32 f registers; [0-31]");
2066 goto error;
2067 }
2068 }
2069 }
2070 else
2071 {
2072 break;
ab3e48dc 2073 } /* if not an 'f' register. */
252b5132
RH		 2074
2075 switch (*args)
2076 {
2077 case 'v':
2078 case 'V':
2079 case 'e':
2080 opcode |= RS1 (mask);
2081 continue;
2082
252b5132
RH		 2083 case 'f':
2084 case 'B':
2085 case 'R':
2086 opcode |= RS2 (mask);
2087 continue;
2088
2089 case 'g':
2090 case 'H':
2091 case 'J':
2092 opcode |= RD (mask);
2093 continue;
ab3e48dc 2094 } /* Pack it in. */
252b5132
RH		 2095
2096 know (0);
2097 break;
ab3e48dc 2098 } /* float arg */
252b5132
RH		 2099
2100 case 'F':
2101 if (strncmp (s, "%fsr", 4) == 0)
2102 {
2103 s += 4;
2104 continue;
2105 }
2106 break;
2107
ab3e48dc
KH		 2108 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2109 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2110 goto immediate;
2111
ab3e48dc 2112 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2113 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2114 the_insn.pcrel = 1;
2115 goto immediate;
2116
ab3e48dc 2117 case 'L': /* 30 bit immediate */
252b5132
RH		 2118 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2119 the_insn.pcrel = 1;
2120 goto immediate;
2121
63fab58c 2122 case 'h':
ab3e48dc 2123 case 'n': /* 22 bit immediate */
252b5132
RH		 2124 the_insn.reloc = BFD_RELOC_SPARC22;
2125 goto immediate;
2126
ab3e48dc 2127 case 'i': /* 13 bit immediate */
252b5132
RH		 2128 the_insn.reloc = BFD_RELOC_SPARC13;
2129
2130 /* fallthrough */
2131
2132 immediate:
2133 if (*s == ' ')
2134 s++;
2135
cf9a1301
RH		 2136 {
2137 char *s1;
2138 char *op_arg = NULL;
2139 expressionS op_exp;
2140 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2141
2142 /* Check for %hi, etc. */
2143 if (*s == '%')
2144 {
2145 static const struct ops {
2146 /* The name as it appears in assembler. */
2147 char *name;
2148 /* strlen (name), precomputed for speed */
2149 int len;
2150 /* The reloc this pseudo-op translates to. */
2151 int reloc;
2152 /* Non-zero if for v9 only. */
2153 int v9_p;
2154 /* Non-zero if can be used in pc-relative contexts. */
2155 int pcrel_p;/*FIXME:wip*/
2156 } ops[] = {
2157 /* hix/lox must appear before hi/lo so %hix won't be
2158 mistaken for %hi. */
2159 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2160 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2161 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2162 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2163 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2164 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2165 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2166 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2167 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2168 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2169 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2170 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
c2158c24 2171 { NULL, 0, 0, 0, 0 }
cf9a1301
RH		 2172 };
2173 const struct ops *o;
e0c6ed95 2174
cf9a1301
RH		 2175 for (o = ops; o->name; o++)
2176 if (strncmp (s + 1, o->name, o->len) == 0)
2177 break;
2178 if (o->name == NULL)
252b5132 2179 break;
e0c6ed95 2180
cf9a1301
RH		 2181 if (s[o->len + 1] != '(')
2182 {
2183 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2184 return special_case;
cf9a1301 2185 }
252b5132 2186
cf9a1301
RH		 2187 op_arg = o->name;
2188 the_insn.reloc = o->reloc;
2189 s += o->len + 2;
2190 v9_arg_p = o->v9_p;
2191 }
2192
2193 /* Note that if the get_expression() fails, we will still
2194 have created U entries in the symbol table for the
2195 'symbols' in the input string. Try not to create U
2196 symbols for registers, etc. */
252b5132 2197
252b5132
RH		 2198 /* This stuff checks to see if the expression ends in
2199 +%reg. If it does, it removes the register from
2200 the expression, and re-sets 's' to point to the
2201 right place. */
2202
cf9a1301
RH		 2203 if (op_arg)
2204 {
2205 int npar = 0;
2206
2207 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2208 if (*s1 == '(')
2209 npar++;
2210 else if (*s1 == ')')
2211 {
2212 if (!npar)
2213 break;
2214 npar--;
2215 }
2216
2217 if (*s1 != ')')
2218 {
2219 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2220 return special_case;
cf9a1301 2221 }
e0c6ed95 2222
cf9a1301
RH		 2223 *s1 = '\0';
2224 (void) get_expression (s);
2225 *s1 = ')';
2226 s = s1 + 1;
2227 if (*s == ',' || *s == ']' || !*s)
2228 continue;
2229 if (*s != '+' && *s != '-')
2230 {
2231 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2232 return special_case;
cf9a1301
RH		 2233 }
2234 *s1 = '0';
2235 s = s1;
2236 op_exp = the_insn.exp;
e0c6ed95 2237 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2238 }
252b5132 2239
e0c6ed95
AM		 2240 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2241 ;
252b5132
RH		 2242
2243 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2244 {
2245 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301
RH		 2246 s1 -= 3;
2247 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2248 s1 -= 4;
2249 else
2250 s1 = NULL;
2251 if (s1)
252b5132 2252 {
252b5132 2253 *s1 = '\0';
1eb7027c
RH		 2254 if (op_arg && s1 == s + 1)
2255 the_insn.exp.X_op = O_absent;
2256 else
2257 (void) get_expression (s);
252b5132 2258 *s1 = '+';
cf9a1301
RH		 2259 if (op_arg)
2260 *s = ')';
252b5132 2261 s = s1;
252b5132 2262 }
cf9a1301
RH		 2263 }
2264 else
2265 s1 = NULL;
2266
2267 if (!s1)
2268 {
2269 (void) get_expression (s);
2270 if (op_arg)
2271 *s = ')';
2272 s = expr_end;
2273 }
2274
2275 if (op_arg)
2276 {
2277 the_insn.exp2 = the_insn.exp;
2278 the_insn.exp = op_exp;
2279 if (the_insn.exp2.X_op == O_absent)
2280 the_insn.exp2.X_op = O_illegal;
2281 else if (the_insn.exp.X_op == O_absent)
252b5132 2282 {
cf9a1301
RH		 2283 the_insn.exp = the_insn.exp2;
2284 the_insn.exp2.X_op = O_illegal;
2285 }
2286 else if (the_insn.exp.X_op == O_constant)
2287 {
2288 valueT val = the_insn.exp.X_add_number;
2289 switch (the_insn.reloc)
2290 {
1b50c718
ILT		 2291 default:
2292 break;
2293
cf9a1301
RH		 2294 case BFD_RELOC_SPARC_HH22:
2295 val = BSR (val, 32);
e0c6ed95 2296 /* Fall through. */
cf9a1301
RH		 2297
2298 case BFD_RELOC_SPARC_LM22:
2299 case BFD_RELOC_HI22:
2300 val = (val >> 10) & 0x3fffff;
2301 break;
2302
2303 case BFD_RELOC_SPARC_HM10:
2304 val = BSR (val, 32);
e0c6ed95 2305 /* Fall through. */
cf9a1301
RH		 2306
2307 case BFD_RELOC_LO10:
2308 val &= 0x3ff;
2309 break;
2310
2311 case BFD_RELOC_SPARC_H44:
2312 val >>= 22;
2313 val &= 0x3fffff;
2314 break;
2315
2316 case BFD_RELOC_SPARC_M44:
2317 val >>= 12;
2318 val &= 0x3ff;
2319 break;
2320
2321 case BFD_RELOC_SPARC_L44:
2322 val &= 0xfff;
2323 break;
2324
2325 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2326 val = ~val;
cf9a1301
RH		 2327 val = (val >> 10) & 0x3fffff;
2328 break;
2329
2330 case BFD_RELOC_SPARC_LOX10:
2331 val = (val & 0x3ff) | 0x1c00;
2332 break;
2333 }
2334 the_insn.exp = the_insn.exp2;
2335 the_insn.exp.X_add_number += val;
2336 the_insn.exp2.X_op = O_illegal;
2337 the_insn.reloc = old_reloc;
2338 }
2339 else if (the_insn.exp2.X_op != O_constant)
2340 {
2341 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2342 return special_case;
cf9a1301
RH		 2343 }
2344 else
2345 {
dabe3bbc 2346 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2347 || the_insn.reloc != BFD_RELOC_LO10
2348 || sparc_arch_size != 64
2349 || sparc_pic_code)
2350 {
2351 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2352 return special_case;
cf9a1301
RH		 2353 }
2354 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2355 }
2356 }
2357 }
252b5132
RH		 2358 /* Check for constants that don't require emitting a reloc. */
2359 if (the_insn.exp.X_op == O_constant
2360 && the_insn.exp.X_add_symbol == 0
2361 && the_insn.exp.X_op_symbol == 0)
2362 {
2363 /* For pc-relative call instructions, we reject
2364 constants to get better code. */
2365 if (the_insn.pcrel
2366 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2367 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2368 {
2369 error_message = _(": PC-relative operand can't be a constant");
2370 goto error;
2371 }
2372
2373 /* Constants that won't fit are checked in md_apply_fix3
2374 and bfd_install_relocation.
2375 ??? It would be preferable to install the constants
2376 into the insn here and save having to create a fixS
2377 for each one. There already exists code to handle
2378 all the various cases (e.g. in md_apply_fix3 and
2379 bfd_install_relocation) so duplicating all that code
2380 here isn't right. */
2381 }
2382
2383 continue;
2384
2385 case 'a':
2386 if (*s++ == 'a')
2387 {
2388 opcode |= ANNUL;
2389 continue;
2390 }
2391 break;
2392
2393 case 'A':
2394 {
2395 int asi = 0;
2396
2397 /* Parse an asi. */
2398 if (*s == '#')
2399 {
2400 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2401 {
2402 error_message = _(": invalid ASI name");
2403 goto error;
2404 }
2405 }
2406 else
2407 {
2408 if (! parse_const_expr_arg (&s, &asi))
2409 {
2410 error_message = _(": invalid ASI expression");
2411 goto error;
2412 }
2413 if (asi < 0 || asi > 255)
2414 {
2415 error_message = _(": invalid ASI number");
2416 goto error;
2417 }
2418 }
2419 opcode |= ASI (asi);
2420 continue;
e0c6ed95 2421 } /* Alternate space. */
252b5132
RH		 2422
2423 case 'p':
2424 if (strncmp (s, "%psr", 4) == 0)
2425 {
2426 s += 4;
2427 continue;
2428 }
2429 break;
2430
e0c6ed95 2431 case 'q': /* Floating point queue. */
252b5132
RH		 2432 if (strncmp (s, "%fq", 3) == 0)
2433 {
2434 s += 3;
2435 continue;
2436 }
2437 break;
2438
e0c6ed95 2439 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2440 if (strncmp (s, "%cq", 3) == 0)
2441 {
2442 s += 3;
2443 continue;
2444 }
2445 break;
2446
2447 case 'S':
2448 if (strcmp (str, "set") == 0
2449 || strcmp (str, "setuw") == 0)
2450 {
2451 special_case = SPECIAL_CASE_SET;
2452 continue;
2453 }
2454 else if (strcmp (str, "setsw") == 0)
2455 {
2456 special_case = SPECIAL_CASE_SETSW;
2457 continue;
2458 }
2459 else if (strcmp (str, "setx") == 0)
2460 {
2461 special_case = SPECIAL_CASE_SETX;
2462 continue;
2463 }
2464 else if (strncmp (str, "fdiv", 4) == 0)
2465 {
2466 special_case = SPECIAL_CASE_FDIV;
2467 continue;
2468 }
2469 break;
2470
2471 case 'o':
2472 if (strncmp (s, "%asi", 4) != 0)
2473 break;
2474 s += 4;
2475 continue;
2476
2477 case 's':
2478 if (strncmp (s, "%fprs", 5) != 0)
2479 break;
2480 s += 5;
2481 continue;
2482
2483 case 'E':
2484 if (strncmp (s, "%ccr", 4) != 0)
2485 break;
2486 s += 4;
2487 continue;
2488
2489 case 't':
2490 if (strncmp (s, "%tbr", 4) != 0)
2491 break;
2492 s += 4;
2493 continue;
2494
2495 case 'w':
2496 if (strncmp (s, "%wim", 4) != 0)
2497 break;
2498 s += 4;
2499 continue;
2500
2501 case 'x':
2502 {
2503 char *push = input_line_pointer;
2504 expressionS e;
2505
2506 input_line_pointer = s;
2507 expression (&e);
2508 if (e.X_op == O_constant)
2509 {
2510 int n = e.X_add_number;
2511 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2512 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2513 else
2514 opcode |= e.X_add_number << 5;
2515 }
2516 else
2517 as_bad (_("non-immediate OPF operand, ignored"));
2518 s = input_line_pointer;
2519 input_line_pointer = push;
2520 continue;
2521 }
2522
2523 case 'y':
2524 if (strncmp (s, "%y", 2) != 0)
2525 break;
2526 s += 2;
2527 continue;
2528
2529 case 'u':
2530 case 'U':
2531 {
2532 /* Parse a sparclet cpreg. */
2533 int cpreg;
2534 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2535 {
2536 error_message = _(": invalid cpreg name");
2537 goto error;
2538 }
2539 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2540 continue;
2541 }
2542
2543 default:
2544 as_fatal (_("failed sanity check."));
e0c6ed95 2545 } /* switch on arg code. */
252b5132
RH		 2546
2547 /* Break out of for() loop. */
2548 break;
e0c6ed95 2549 } /* For each arg that we expect. */
252b5132
RH		 2550
2551 error:
2552 if (match == 0)
2553 {
e0c6ed95 2554 /* Args don't match. */
252b5132
RH		 2555 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2556 && (insn->name == insn[1].name
2557 || !strcmp (insn->name, insn[1].name)))
2558 {
2559 ++insn;
2560 s = argsStart;
2561 continue;
2562 }
2563 else
2564 {
2565 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2566 return special_case;
252b5132
RH		 2567 }
2568 }
2569 else
2570 {
e0c6ed95 2571 /* We have a match. Now see if the architecture is OK. */
252b5132
RH		 2572 int needed_arch_mask = insn->architecture;
2573
2574 if (v9_arg_p)
2575 {
19f7b010
JJ		 2576 needed_arch_mask &=
2577 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2578 if (! needed_arch_mask)
2579 needed_arch_mask =
2580 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
252b5132
RH		 2581 }
2582
e0c6ed95
AM		 2583 if (needed_arch_mask
2584 & SPARC_OPCODE_SUPPORTED (current_architecture))
2585 /* OK. */
2586 ;
252b5132 2587 /* Can we bump up the architecture? */
e0c6ed95
AM		 2588 else if (needed_arch_mask
2589 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2590 {
2591 enum sparc_opcode_arch_val needed_architecture =
2592 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2593 & needed_arch_mask);
2594
2595 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2596 if (warn_on_bump
2597 && needed_architecture > warn_after_architecture)
2598 {
2599 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2600 sparc_opcode_archs[current_architecture].name,
2601 sparc_opcode_archs[needed_architecture].name,
2602 str);
2603 warn_after_architecture = needed_architecture;
2604 }
2605 current_architecture = needed_architecture;
2606 }
2607 /* Conflict. */
2608 /* ??? This seems to be a bit fragile. What if the next entry in
2609 the opcode table is the one we want and it is supported?
2610 It is possible to arrange the table today so that this can't
2611 happen but what about tomorrow? */
2612 else
2613 {
e0c6ed95 2614 int arch, printed_one_p = 0;
252b5132
RH		 2615 char *p;
2616 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2617
2618 /* Create a list of the architectures that support the insn. */
e0c6ed95 2619 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2620 p = required_archs;
2621 arch = sparc_ffs (needed_arch_mask);
2622 while ((1 << arch) <= needed_arch_mask)
2623 {
2624 if ((1 << arch) & needed_arch_mask)
2625 {
2626 if (printed_one_p)
2627 *p++ = '|';
2628 strcpy (p, sparc_opcode_archs[arch].name);
2629 p += strlen (p);
2630 printed_one_p = 1;
2631 }
2632 ++arch;
2633 }
2634
2635 as_bad (_("Architecture mismatch on \"%s\"."), str);
2636 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2637 required_archs,
2638 sparc_opcode_archs[max_architecture].name);
a22b281c 2639 return special_case;
252b5132 2640 }
e0c6ed95 2641 } /* If no match. */
252b5132
RH		 2642
2643 break;
e0c6ed95 2644 } /* Forever looking for a match. */
252b5132
RH		 2645
2646 the_insn.opcode = opcode;
a22b281c 2647 return special_case;
252b5132
RH		 2648}
2649
2650/* Parse an argument that can be expressed as a keyword.
2651 (eg: #StoreStore or %ccfr).
2652 The result is a boolean indicating success.
2653 If successful, INPUT_POINTER is updated. */
2654
2655static int
2656parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2657 int (*lookup_fn) PARAMS ((const char *));
2658 char **input_pointerP;
2659 int *valueP;
2660{
2661 int value;
2662 char c, *p, *q;
2663
2664 p = *input_pointerP;
2665 for (q = p + (*p == '#' || *p == '%');
2666 isalnum ((unsigned char) *q) || *q == '_';
2667 ++q)
2668 continue;
2669 c = *q;
2670 *q = 0;
2671 value = (*lookup_fn) (p);
2672 *q = c;
2673 if (value == -1)
2674 return 0;
2675 *valueP = value;
2676 *input_pointerP = q;
2677 return 1;
2678}
2679
2680/* Parse an argument that is a constant expression.
2681 The result is a boolean indicating success. */
2682
2683static int
2684parse_const_expr_arg (input_pointerP, valueP)
2685 char **input_pointerP;
2686 int *valueP;
2687{
2688 char *save = input_line_pointer;
2689 expressionS exp;
2690
2691 input_line_pointer = *input_pointerP;
2692 /* The next expression may be something other than a constant
2693 (say if we're not processing the right variant of the insn).
2694 Don't call expression unless we're sure it will succeed as it will
2695 signal an error (which we want to defer until later). */
2696 /* FIXME: It might be better to define md_operand and have it recognize
2697 things like %asi, etc. but continuing that route through to the end
2698 is a lot of work. */
2699 if (*input_line_pointer == '%')
2700 {
2701 input_line_pointer = save;
2702 return 0;
2703 }
2704 expression (&exp);
2705 *input_pointerP = input_line_pointer;
2706 input_line_pointer = save;
2707 if (exp.X_op != O_constant)
2708 return 0;
2709 *valueP = exp.X_add_number;
2710 return 1;
2711}
2712
2713/* Subroutine of sparc_ip to parse an expression. */
2714
2715static int
2716get_expression (str)
2717 char *str;
2718{
2719 char *save_in;
2720 segT seg;
2721
2722 save_in = input_line_pointer;
2723 input_line_pointer = str;
2724 seg = expression (&the_insn.exp);
2725 if (seg != absolute_section
2726 && seg != text_section
2727 && seg != data_section
2728 && seg != bss_section
2729 && seg != undefined_section)
2730 {
2731 the_insn.error = _("bad segment");
2732 expr_end = input_line_pointer;
2733 input_line_pointer = save_in;
2734 return 1;
2735 }
2736 expr_end = input_line_pointer;
2737 input_line_pointer = save_in;
2738 return 0;
2739}
2740
2741/* Subroutine of md_assemble to output one insn. */
2742
2743static void
2744output_insn (insn, the_insn)
2745 const struct sparc_opcode *insn;
2746 struct sparc_it *the_insn;
2747{
2748 char *toP = frag_more (4);
2749
e0c6ed95 2750 /* Put out the opcode. */
252b5132
RH		 2751 if (INSN_BIG_ENDIAN)
2752 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2753 else
2754 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2755
e0c6ed95 2756 /* Put out the symbol-dependent stuff. */
252b5132
RH		 2757 if (the_insn->reloc != BFD_RELOC_NONE)
2758 {
e0c6ed95
AM		 2759 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2760 (toP - frag_now->fr_literal), /* Where. */
2761 4, /* Size. */
252b5132
RH		 2762 &the_insn->exp,
2763 the_insn->pcrel,
2764 the_insn->reloc);
2765 /* Turn off overflow checking in fixup_segment. We'll do our
2766 own overflow checking in md_apply_fix3. This is necessary because
2767 the insn size is 4 and fixup_segment will signal an overflow for
2768 large 8 byte quantities. */
2769 fixP->fx_no_overflow = 1;
dabe3bbc
RH		 2770 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2771 fixP->tc_fix_data = the_insn->exp2.X_add_number;
252b5132
RH		 2772 }
2773
2774 last_insn = insn;
2775 last_opcode = the_insn->opcode;
732d96b6
JJ		 2776
2777#ifdef OBJ_ELF
2778 dwarf2_emit_insn (4);
2779#endif
252b5132
RH		 2780}
2781\f
e0c6ed95
AM		 2782/* This is identical to the md_atof in m68k.c. I think this is right,
2783 but I'm not sure.
252b5132 2784
e0c6ed95
AM		 2785 Turn a string in input_line_pointer into a floating point constant
2786 of type TYPE, and store the appropriate bytes in *LITP. The number
2787 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2788 returned, or NULL on OK. */
252b5132 2789
e0c6ed95 2790/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 2791#define MAX_LITTLENUMS 6
2792
2793char *
2794md_atof (type, litP, sizeP)
2795 char type;
2796 char *litP;
2797 int *sizeP;
2798{
e0c6ed95 2799 int i, prec;
252b5132
RH		 2800 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2801 char *t;
2802
2803 switch (type)
2804 {
2805 case 'f':
2806 case 'F':
2807 case 's':
2808 case 'S':
2809 prec = 2;
2810 break;
2811
2812 case 'd':
2813 case 'D':
2814 case 'r':
2815 case 'R':
2816 prec = 4;
2817 break;
2818
2819 case 'x':
2820 case 'X':
2821 prec = 6;
2822 break;
2823
2824 case 'p':
2825 case 'P':
2826 prec = 6;
2827 break;
2828
2829 default:
2830 *sizeP = 0;
2831 return _("Bad call to MD_ATOF()");
2832 }
2833
2834 t = atof_ieee (input_line_pointer, type, words);
2835 if (t)
2836 input_line_pointer = t;
2837 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2838
2839 if (target_big_endian)
2840 {
2841 for (i = 0; i < prec; i++)
2842 {
ab3e48dc
KH		 2843 md_number_to_chars (litP, (valueT) words[i],
2844 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2845 litP += sizeof (LITTLENUM_TYPE);
2846 }
2847 }
2848 else
2849 {
2850 for (i = prec - 1; i >= 0; i--)
2851 {
ab3e48dc
KH		 2852 md_number_to_chars (litP, (valueT) words[i],
2853 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2854 litP += sizeof (LITTLENUM_TYPE);
2855 }
2856 }
e0c6ed95 2857
252b5132
RH		 2858 return 0;
2859}
2860
2861/* Write a value out to the object file, using the appropriate
2862 endianness. */
2863
2864void
2865md_number_to_chars (buf, val, n)
2866 char *buf;
2867 valueT val;
2868 int n;
2869{
2870 if (target_big_endian)
2871 number_to_chars_bigendian (buf, val, n);
2872 else if (target_little_endian_data
2873 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 2874 /* Output debug words, which are not in allocated sections, as big
2875 endian. */
252b5132
RH		 2876 number_to_chars_bigendian (buf, val, n);
2877 else if (target_little_endian_data || ! target_big_endian)
2878 number_to_chars_littleendian (buf, val, n);
2879}
2880\f
2881/* Apply a fixS to the frags, now that we know the value it ought to
81d4177b 2882 hold. */
252b5132
RH		 2883
2884int
2885md_apply_fix3 (fixP, value, segment)
2886 fixS *fixP;
2887 valueT *value;
2888 segT segment;
2889{
2890 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2891 offsetT val;
2892 long insn;
2893
2894 val = *value;
2895
2896 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2897
e0c6ed95 2898 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 2899
2900#ifdef OBJ_ELF
2901 /* FIXME: SPARC ELF relocations don't use an addend in the data
2902 field itself. This whole approach should be somehow combined
2903 with the calls to bfd_install_relocation. Also, the value passed
2904 in by fixup_segment includes the value of a defined symbol. We
2905 don't want to include the value of an externally visible symbol. */
2906 if (fixP->fx_addsy != NULL)
2907 {
49309057 2908 if (symbol_used_in_reloc_p (fixP->fx_addsy)
252b5132
RH		 2909 && (S_IS_EXTERNAL (fixP->fx_addsy)
2910 || S_IS_WEAK (fixP->fx_addsy)
2911 || (sparc_pic_code && ! fixP->fx_pcrel)
2912 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2913 && ((bfd_get_section_flags (stdoutput,
2914 S_GET_SEGMENT (fixP->fx_addsy))
2915 & SEC_LINK_ONCE) != 0
2916 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2917 ".gnu.linkonce",
2918 sizeof ".gnu.linkonce" - 1) == 0)))
2919 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2920 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2921 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2922 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2923 return 1;
2924 }
2925#endif
2926
2927 /* This is a hack. There should be a better way to
2928 handle this. Probably in terms of howto fields, once
2929 we can look at these fixups in terms of howtos. */
2930 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2931 val += fixP->fx_where + fixP->fx_frag->fr_address;
2932
2933#ifdef OBJ_AOUT
2934 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2935 generate a reloc, then we just want to let the reloc addend set
2936 the value. We do not want to also stuff the addend into the
2937 object file. Including the addend in the object file works when
2938 doing a static link, because the linker will ignore the object
2939 file contents. However, the dynamic linker does not ignore the
2940 object file contents. */
2941 if (fixP->fx_addsy != NULL
2942 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2943 val = 0;
2944
2945 /* When generating PIC code, we do not want an addend for a reloc
2946 against a local symbol. We adjust fx_addnumber to cancel out the
2947 value already included in val, and to also cancel out the
2948 adjustment which bfd_install_relocation will create. */
2949 if (sparc_pic_code
2950 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2951 && fixP->fx_addsy != NULL
2952 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 2953 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 2954 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2955
2956 /* When generating PIC code, we need to fiddle to get
2957 bfd_install_relocation to do the right thing for a PC relative
2958 reloc against a local symbol which we are going to keep. */
2959 if (sparc_pic_code
2960 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2961 && fixP->fx_addsy != NULL
2962 && (S_IS_EXTERNAL (fixP->fx_addsy)
2963 || S_IS_WEAK (fixP->fx_addsy))
2964 && S_IS_DEFINED (fixP->fx_addsy)
2965 && ! S_IS_COMMON (fixP->fx_addsy))
2966 {
2967 val = 0;
2968 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2969 }
2970#endif
2971
2972 /* If this is a data relocation, just output VAL. */
2973
2974 if (fixP->fx_r_type == BFD_RELOC_16)
2975 {
2976 md_number_to_chars (buf, val, 2);
2977 }
2978 else if (fixP->fx_r_type == BFD_RELOC_32
2979 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2980 {
2981 md_number_to_chars (buf, val, 4);
2982 }
2983 else if (fixP->fx_r_type == BFD_RELOC_64)
2984 {
2985 md_number_to_chars (buf, val, 8);
2986 }
e0c6ed95 2987 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 2988 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2989 {
2990 fixP->fx_done = 0;
2991 return 1;
2992 }
2993 else
2994 {
2995 /* It's a relocation against an instruction. */
2996
2997 if (INSN_BIG_ENDIAN)
2998 insn = bfd_getb32 ((unsigned char *) buf);
2999 else
3000 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 3001
252b5132
RH		 3002 switch (fixP->fx_r_type)
3003 {
3004 case BFD_RELOC_32_PCREL_S2:
3005 val = val >> 2;
3006 /* FIXME: This increment-by-one deserves a comment of why it's
3007 being done! */
3008 if (! sparc_pic_code
3009 || fixP->fx_addsy == NULL
49309057 3010 || symbol_section_p (fixP->fx_addsy))
252b5132 3011 ++val;
6faf3d66 3012
252b5132 3013 insn |= val & 0x3fffffff;
6faf3d66 3014
e0c6ed95 3015 /* See if we have a delay slot. */
6faf3d66
JJ		 3016 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3017 {
3018#define G0 0
3019#define O7 15
3020#define XCC (2 << 20)
3021#define COND(x) (((x)&0xf)<<25)
3022#define CONDA COND(0x8)
3023#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3024#define INSN_BA (F2(0,2) | CONDA)
3025#define INSN_OR F3(2, 0x2, 0)
3026#define INSN_NOP F2(0,4)
3027
3028 long delay;
3029
3030 /* If the instruction is a call with either:
3031 restore
3032 arithmetic instruction with rd == %o7
3033 where rs1 != %o7 and rs2 if it is register != %o7
3034 then we can optimize if the call destination is near
3035 by changing the call into a branch always. */
3036 if (INSN_BIG_ENDIAN)
3037 delay = bfd_getb32 ((unsigned char *) buf + 4);
3038 else
3039 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 3040 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 3041 break;
e0c6ed95
AM		 3042 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3043 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3044 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 3045 break;
e0c6ed95
AM		 3046 if ((delay & RS1 (~0)) == RS1 (O7)
3047 || ((delay & F3I (~0)) == 0
3048 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 3049 break;
3050 /* Ensure the branch will fit into simm22. */
3051 if ((val & 0x3fe00000)
3052 && (val & 0x3fe00000) != 0x3fe00000)
3053 break;
3054 /* Check if the arch is v9 and branch will fit
3055 into simm19. */
3056 if (((val & 0x3c0000) == 0
3057 || (val & 0x3c0000) == 0x3c0000)
3058 && (sparc_arch_size == 64
3059 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 3060 /* ba,pt %xcc */
6faf3d66
JJ		 3061 insn = INSN_BPA | (val & 0x7ffff);
3062 else
e0c6ed95 3063 /* ba */
6faf3d66
JJ		 3064 insn = INSN_BA | (val & 0x3fffff);
3065 if (fixP->fx_where >= 4
e0c6ed95
AM		 3066 && ((delay & (0xffffffff ^ RS1 (~0)))
3067 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3068 {
3069 long setter;
3070 int reg;
3071
3072 if (INSN_BIG_ENDIAN)
3073 setter = bfd_getb32 ((unsigned char *) buf - 4);
3074 else
3075 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3076 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3077 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3078 break;
3079 /* The sequence was
3080 or %o7, %g0, %rN
3081 call foo
3082 or %rN, %g0, %o7
3083
3084 If call foo was replaced with ba, replace
3085 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3086 reg = (delay & RS1 (~0)) >> 14;
3087 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3088 || reg == G0 || reg == O7)
3089 break;
3090
3091 if (INSN_BIG_ENDIAN)
3092 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3093 else
3094 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3095 }
3096 }
252b5132
RH		 3097 break;
3098
3099 case BFD_RELOC_SPARC_11:
3100 if (! in_signed_range (val, 0x7ff))
3101 as_bad_where (fixP->fx_file, fixP->fx_line,
3102 _("relocation overflow"));
3103 insn |= val & 0x7ff;
3104 break;
3105
3106 case BFD_RELOC_SPARC_10:
3107 if (! in_signed_range (val, 0x3ff))
3108 as_bad_where (fixP->fx_file, fixP->fx_line,
3109 _("relocation overflow"));
3110 insn |= val & 0x3ff;
3111 break;
3112
3113 case BFD_RELOC_SPARC_7:
3114 if (! in_bitfield_range (val, 0x7f))
3115 as_bad_where (fixP->fx_file, fixP->fx_line,
3116 _("relocation overflow"));
3117 insn |= val & 0x7f;
3118 break;
3119
3120 case BFD_RELOC_SPARC_6:
3121 if (! in_bitfield_range (val, 0x3f))
3122 as_bad_where (fixP->fx_file, fixP->fx_line,
3123 _("relocation overflow"));
3124 insn |= val & 0x3f;
3125 break;
3126
3127 case BFD_RELOC_SPARC_5:
3128 if (! in_bitfield_range (val, 0x1f))
3129 as_bad_where (fixP->fx_file, fixP->fx_line,
3130 _("relocation overflow"));
3131 insn |= val & 0x1f;
3132 break;
3133
3134 case BFD_RELOC_SPARC_WDISP16:
e0c6ed95 3135 /* FIXME: simplify. */
252b5132
RH		 3136 if (((val > 0) && (val & ~0x3fffc))
3137 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3138 as_bad_where (fixP->fx_file, fixP->fx_line,
3139 _("relocation overflow"));
3140 /* FIXME: The +1 deserves a comment. */
3141 val = (val >> 2) + 1;
3142 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3143 break;
3144
3145 case BFD_RELOC_SPARC_WDISP19:
e0c6ed95 3146 /* FIXME: simplify. */
252b5132
RH		 3147 if (((val > 0) && (val & ~0x1ffffc))
3148 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3149 as_bad_where (fixP->fx_file, fixP->fx_line,
3150 _("relocation overflow"));
3151 /* FIXME: The +1 deserves a comment. */
3152 val = (val >> 2) + 1;
3153 insn |= val & 0x7ffff;
3154 break;
3155
3156 case BFD_RELOC_SPARC_HH22:
3157 val = BSR (val, 32);
e0c6ed95 3158 /* Fall through. */
252b5132
RH		 3159
3160 case BFD_RELOC_SPARC_LM22:
3161 case BFD_RELOC_HI22:
3162 if (!fixP->fx_addsy)
3163 {
3164 insn |= (val >> 10) & 0x3fffff;
3165 }
3166 else
3167 {
3168 /* FIXME: Need comment explaining why we do this. */
3169 insn &= ~0xffff;
3170 }
3171 break;
3172
3173 case BFD_RELOC_SPARC22:
3174 if (val & ~0x003fffff)
3175 as_bad_where (fixP->fx_file, fixP->fx_line,
3176 _("relocation overflow"));
3177 insn |= (val & 0x3fffff);
3178 break;
3179
3180 case BFD_RELOC_SPARC_HM10:
3181 val = BSR (val, 32);
e0c6ed95 3182 /* Fall through. */
252b5132
RH		 3183
3184 case BFD_RELOC_LO10:
3185 if (!fixP->fx_addsy)
3186 {
3187 insn |= val & 0x3ff;
3188 }
3189 else
3190 {
3191 /* FIXME: Need comment explaining why we do this. */
3192 insn &= ~0xff;
3193 }
3194 break;
3195
dabe3bbc
RH		 3196 case BFD_RELOC_SPARC_OLO10:
3197 val &= 0x3ff;
3198 val += fixP->tc_fix_data;
e0c6ed95 3199 /* Fall through. */
dabe3bbc 3200
252b5132
RH		 3201 case BFD_RELOC_SPARC13:
3202 if (! in_signed_range (val, 0x1fff))
3203 as_bad_where (fixP->fx_file, fixP->fx_line,
3204 _("relocation overflow"));
3205 insn |= val & 0x1fff;
3206 break;
3207
3208 case BFD_RELOC_SPARC_WDISP22:
3209 val = (val >> 2) + 1;
e0c6ed95 3210 /* Fall through. */
252b5132
RH		 3211 case BFD_RELOC_SPARC_BASE22:
3212 insn |= val & 0x3fffff;
3213 break;
3214
3215 case BFD_RELOC_SPARC_H44:
3216 if (!fixP->fx_addsy)
3217 {
3218 bfd_vma tval = val;
3219 tval >>= 22;
3220 insn |= tval & 0x3fffff;
3221 }
3222 break;
3223
3224 case BFD_RELOC_SPARC_M44:
3225 if (!fixP->fx_addsy)
3226 insn |= (val >> 12) & 0x3ff;
3227 break;
3228
3229 case BFD_RELOC_SPARC_L44:
3230 if (!fixP->fx_addsy)
3231 insn |= val & 0xfff;
3232 break;
3233
3234 case BFD_RELOC_SPARC_HIX22:
3235 if (!fixP->fx_addsy)
3236 {
ab3e48dc 3237 val ^= ~(offsetT) 0;
252b5132
RH		 3238 insn |= (val >> 10) & 0x3fffff;
3239 }
3240 break;
3241
3242 case BFD_RELOC_SPARC_LOX10:
3243 if (!fixP->fx_addsy)
3244 insn |= 0x1c00 | (val & 0x3ff);
3245 break;
3246
3247 case BFD_RELOC_NONE:
3248 default:
3249 as_bad_where (fixP->fx_file, fixP->fx_line,
3250 _("bad or unhandled relocation type: 0x%02x"),
3251 fixP->fx_r_type);
3252 break;
3253 }
3254
3255 if (INSN_BIG_ENDIAN)
3256 bfd_putb32 (insn, (unsigned char *) buf);
3257 else
3258 bfd_putl32 (insn, (unsigned char *) buf);
3259 }
3260
3261 /* Are we finished with this relocation now? */
3262 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3263 fixP->fx_done = 1;
3264
3265 return 1;
3266}
3267
3268/* Translate internal representation of relocation info to BFD target
3269 format. */
e0c6ed95 3270
dabe3bbc 3271arelent **
252b5132
RH		 3272tc_gen_reloc (section, fixp)
3273 asection *section;
3274 fixS *fixp;
3275{
dabe3bbc 3276 static arelent *relocs[3];
252b5132
RH		 3277 arelent *reloc;
3278 bfd_reloc_code_real_type code;
3279
dabe3bbc
RH		 3280 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3281 relocs[1] = NULL;
252b5132 3282
49309057
ILT		 3283 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3284 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3285 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3286
3287 switch (fixp->fx_r_type)
3288 {
3289 case BFD_RELOC_16:
3290 case BFD_RELOC_32:
3291 case BFD_RELOC_HI22:
3292 case BFD_RELOC_LO10:
3293 case BFD_RELOC_32_PCREL_S2:
3294 case BFD_RELOC_SPARC13:
63fab58c 3295 case BFD_RELOC_SPARC22:
252b5132
RH		 3296 case BFD_RELOC_SPARC_BASE13:
3297 case BFD_RELOC_SPARC_WDISP16:
3298 case BFD_RELOC_SPARC_WDISP19:
3299 case BFD_RELOC_SPARC_WDISP22:
3300 case BFD_RELOC_64:
3301 case BFD_RELOC_SPARC_5:
3302 case BFD_RELOC_SPARC_6:
3303 case BFD_RELOC_SPARC_7:
3304 case BFD_RELOC_SPARC_10:
3305 case BFD_RELOC_SPARC_11:
3306 case BFD_RELOC_SPARC_HH22:
3307 case BFD_RELOC_SPARC_HM10:
3308 case BFD_RELOC_SPARC_LM22:
3309 case BFD_RELOC_SPARC_PC_HH22:
3310 case BFD_RELOC_SPARC_PC_HM10:
3311 case BFD_RELOC_SPARC_PC_LM22:
3312 case BFD_RELOC_SPARC_H44:
3313 case BFD_RELOC_SPARC_M44:
3314 case BFD_RELOC_SPARC_L44:
3315 case BFD_RELOC_SPARC_HIX22:
3316 case BFD_RELOC_SPARC_LOX10:
3317 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3318 case BFD_RELOC_SPARC_OLO10:
252b5132
RH		 3319 case BFD_RELOC_VTABLE_ENTRY:
3320 case BFD_RELOC_VTABLE_INHERIT:
3321 code = fixp->fx_r_type;
3322 break;
3323 default:
3324 abort ();
3325 return NULL;
3326 }
3327
3328#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3329 /* If we are generating PIC code, we need to generate a different
3330 set of relocs. */
3331
3332#ifdef OBJ_ELF
3333#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3334#else
3335#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3336#endif
3337
153b546a
ILT		 3338 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3339
252b5132
RH		 3340 if (sparc_pic_code)
3341 {
3342 switch (code)
3343 {
3344 case BFD_RELOC_32_PCREL_S2:
3345 if (! S_IS_DEFINED (fixp->fx_addsy)
3346 || S_IS_COMMON (fixp->fx_addsy)
3347 || S_IS_EXTERNAL (fixp->fx_addsy)
3348 || S_IS_WEAK (fixp->fx_addsy))
3349 code = BFD_RELOC_SPARC_WPLT30;
3350 break;
3351 case BFD_RELOC_HI22:
3352 if (fixp->fx_addsy != NULL
3353 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3354 code = BFD_RELOC_SPARC_PC22;
3355 else
3356 code = BFD_RELOC_SPARC_GOT22;
3357 break;
3358 case BFD_RELOC_LO10:
3359 if (fixp->fx_addsy != NULL
3360 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3361 code = BFD_RELOC_SPARC_PC10;
3362 else
3363 code = BFD_RELOC_SPARC_GOT10;
3364 break;
3365 case BFD_RELOC_SPARC13:
3366 code = BFD_RELOC_SPARC_GOT13;
3367 break;
3368 default:
3369 break;
3370 }
3371 }
e0c6ed95 3372#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3373
dabe3bbc
RH		 3374 if (code == BFD_RELOC_SPARC_OLO10)
3375 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3376 else
3377 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3378 if (reloc->howto == 0)
3379 {
3380 as_bad_where (fixp->fx_file, fixp->fx_line,
3381 _("internal error: can't export reloc type %d (`%s')"),
3382 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3383 xfree (reloc);
3384 relocs[0] = NULL;
3385 return relocs;
252b5132
RH		 3386 }
3387
3388 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3389#ifdef OBJ_AOUT
3390
3391 if (reloc->howto->pc_relative == 0
3392 || code == BFD_RELOC_SPARC_PC10
3393 || code == BFD_RELOC_SPARC_PC22)
3394 reloc->addend = fixp->fx_addnumber;
3395 else if (sparc_pic_code
3396 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3397 && fixp->fx_addsy != NULL
3398 && (S_IS_EXTERNAL (fixp->fx_addsy)
3399 || S_IS_WEAK (fixp->fx_addsy))
3400 && S_IS_DEFINED (fixp->fx_addsy)
3401 && ! S_IS_COMMON (fixp->fx_addsy))
3402 reloc->addend = fixp->fx_addnumber;
3403 else
3404 reloc->addend = fixp->fx_offset - reloc->address;
3405
e0c6ed95 3406#else /* elf or coff */
252b5132
RH		 3407
3408 if (reloc->howto->pc_relative == 0
3409 || code == BFD_RELOC_SPARC_PC10
3410 || code == BFD_RELOC_SPARC_PC22)
3411 reloc->addend = fixp->fx_addnumber;
49309057 3412 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3413 reloc->addend = (section->vma
3414 + fixp->fx_addnumber
3415 + md_pcrel_from (fixp));
3416 else
3417 reloc->addend = fixp->fx_offset;
3418#endif
3419
dabe3bbc
RH		 3420 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3421 on the same location. */
3422 if (code == BFD_RELOC_SPARC_OLO10)
3423 {
3424 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3425 relocs[2] = NULL;
3426
3427 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3428 *reloc->sym_ptr_ptr
3429 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3430 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3431 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3432 reloc->addend = fixp->tc_fix_data;
3433 }
3434
3435 return relocs;
252b5132
RH		 3436}
3437\f
e0c6ed95 3438/* We have no need to default values of symbols. */
252b5132 3439
252b5132
RH		 3440symbolS *
3441md_undefined_symbol (name)
c2158c24 3442 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 3443{
3444 return 0;
e0c6ed95
AM		 3445}
3446
3447/* Round up a section size to the appropriate boundary. */
252b5132 3448
252b5132
RH		 3449valueT
3450md_section_align (segment, size)
c2158c24 3451 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 3452 valueT size;
3453{
3454#ifndef OBJ_ELF
3455 /* This is not right for ELF; a.out wants it, and COFF will force
3456 the alignment anyways. */
3457 valueT align = ((valueT) 1
3458 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3459 valueT newsize;
e0c6ed95
AM		 3460
3461 /* Turn alignment value into a mask. */
252b5132
RH		 3462 align--;
3463 newsize = (size + align) & ~align;
3464 return newsize;
3465#else
3466 return size;
3467#endif
3468}
3469
3470/* Exactly what point is a PC-relative offset relative TO?
3471 On the sparc, they're relative to the address of the offset, plus
3472 its size. This gets us to the following instruction.
e0c6ed95
AM		 3473 (??? Is this right? FIXME-SOON) */
3474long
252b5132
RH		 3475md_pcrel_from (fixP)
3476 fixS *fixP;
3477{
3478 long ret;
3479
3480 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3481 if (! sparc_pic_code
3482 || fixP->fx_addsy == NULL
49309057 3483 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3484 ret += fixP->fx_size;
3485 return ret;
3486}
3487\f
3488/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3489 of two. */
3490
3491static int
3492log2 (value)
3493 int value;
3494{
3495 int shift;
3496
3497 if (value <= 0)
3498 return -1;
3499
3500 for (shift = 0; (value & 1) == 0; value >>= 1)
3501 ++shift;
3502
3503 return (value == 1) ? shift : -1;
3504}
3505
e0c6ed95 3506/* Sort of like s_lcomm. */
252b5132
RH		 3507
3508#ifndef OBJ_ELF
3509static int max_alignment = 15;
3510#endif
3511
3512static void
3513s_reserve (ignore)
c2158c24 3514 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3515{
3516 char *name;
3517 char *p;
3518 char c;
3519 int align;
3520 int size;
3521 int temp;
3522 symbolS *symbolP;
3523
3524 name = input_line_pointer;
3525 c = get_symbol_end ();
3526 p = input_line_pointer;
3527 *p = c;
3528 SKIP_WHITESPACE ();
3529
3530 if (*input_line_pointer != ',')
3531 {
3532 as_bad (_("Expected comma after name"));
3533 ignore_rest_of_line ();
3534 return;
3535 }
3536
3537 ++input_line_pointer;
3538
3539 if ((size = get_absolute_expression ()) < 0)
3540 {
3541 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3542 ignore_rest_of_line ();
3543 return;
e0c6ed95 3544 } /* Bad length. */
252b5132
RH		 3545
3546 *p = 0;
3547 symbolP = symbol_find_or_make (name);
3548 *p = c;
3549
3550 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3551 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3552 {
3553 as_bad (_("bad .reserve segment -- expected BSS segment"));
3554 return;
3555 }
3556
3557 if (input_line_pointer[2] == '.')
3558 input_line_pointer += 7;
3559 else
3560 input_line_pointer += 6;
3561 SKIP_WHITESPACE ();
3562
3563 if (*input_line_pointer == ',')
3564 {
3565 ++input_line_pointer;
3566
3567 SKIP_WHITESPACE ();
3568 if (*input_line_pointer == '\n')
3569 {
3570 as_bad (_("missing alignment"));
3571 ignore_rest_of_line ();
3572 return;
3573 }
3574
3575 align = (int) get_absolute_expression ();
3576
3577#ifndef OBJ_ELF
3578 if (align > max_alignment)
3579 {
3580 align = max_alignment;
3581 as_warn (_("alignment too large; assuming %d"), align);
3582 }
3583#endif
3584
3585 if (align < 0)
3586 {
3587 as_bad (_("negative alignment"));
3588 ignore_rest_of_line ();
3589 return;
3590 }
3591
3592 if (align != 0)
3593 {
3594 temp = log2 (align);
3595 if (temp < 0)
3596 {
3597 as_bad (_("alignment not a power of 2"));
3598 ignore_rest_of_line ();
3599 return;
3600 }
3601
3602 align = temp;
3603 }
3604
3605 record_alignment (bss_section, align);
3606 }
3607 else
3608 align = 0;
3609
3610 if (!S_IS_DEFINED (symbolP)
3611#ifdef OBJ_AOUT
3612 && S_GET_OTHER (symbolP) == 0
3613 && S_GET_DESC (symbolP) == 0
3614#endif
3615 )
3616 {
3617 if (! need_pass_2)
3618 {
3619 char *pfrag;
3620 segT current_seg = now_seg;
3621 subsegT current_subseg = now_subseg;
3622
e0c6ed95
AM		 3623 /* Switch to bss. */
3624 subseg_set (bss_section, 1);
252b5132
RH		 3625
3626 if (align)
e0c6ed95
AM		 3627 /* Do alignment. */
3628 frag_align (align, 0, 0);
252b5132 3629
e0c6ed95 3630 /* Detach from old frag. */
ab3e48dc 3631 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3632 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3633
49309057 3634 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3635 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3636 (offsetT) size, (char *) 0);
252b5132
RH		 3637 *pfrag = 0;
3638
3639 S_SET_SEGMENT (symbolP, bss_section);
3640
3641 subseg_set (current_seg, current_subseg);
3642
3643#ifdef OBJ_ELF
3644 S_SET_SIZE (symbolP, size);
3645#endif
3646 }
3647 }
3648 else
3649 {
ab3e48dc
KH		 3650 as_warn ("Ignoring attempt to re-define symbol %s",
3651 S_GET_NAME (symbolP));
e0c6ed95 3652 } /* if not redefining. */
252b5132
RH		 3653
3654 demand_empty_rest_of_line ();
3655}
3656
3657static void
3658s_common (ignore)
c2158c24 3659 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3660{
3661 char *name;
3662 char c;
3663 char *p;
3664 int temp, size;
3665 symbolS *symbolP;
3666
3667 name = input_line_pointer;
3668 c = get_symbol_end ();
e0c6ed95 3669 /* Just after name is now '\0'. */
252b5132
RH		 3670 p = input_line_pointer;
3671 *p = c;
3672 SKIP_WHITESPACE ();
3673 if (*input_line_pointer != ',')
3674 {
3675 as_bad (_("Expected comma after symbol-name"));
3676 ignore_rest_of_line ();
3677 return;
3678 }
e0c6ed95
AM		 3679
3680 /* Skip ','. */
3681 input_line_pointer++;
3682
252b5132
RH		 3683 if ((temp = get_absolute_expression ()) < 0)
3684 {
3685 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3686 ignore_rest_of_line ();
3687 return;
3688 }
3689 size = temp;
3690 *p = 0;
3691 symbolP = symbol_find_or_make (name);
3692 *p = c;
3693 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3694 {
3695 as_bad (_("Ignoring attempt to re-define symbol"));
3696 ignore_rest_of_line ();
3697 return;
3698 }
3699 if (S_GET_VALUE (symbolP) != 0)
3700 {
3701 if (S_GET_VALUE (symbolP) != (valueT) size)
3702 {
3703 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3704 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3705 }
3706 }
3707 else
3708 {
3709#ifndef OBJ_ELF
3710 S_SET_VALUE (symbolP, (valueT) size);
3711 S_SET_EXTERNAL (symbolP);
3712#endif
3713 }
7dcc9865 3714 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3715 if (*input_line_pointer != ',')
3716 {
3717 as_bad (_("Expected comma after common length"));
3718 ignore_rest_of_line ();
3719 return;
3720 }
3721 input_line_pointer++;
3722 SKIP_WHITESPACE ();
3723 if (*input_line_pointer != '"')
3724 {
3725 temp = get_absolute_expression ();
3726
3727#ifndef OBJ_ELF
3728 if (temp > max_alignment)
3729 {
3730 temp = max_alignment;
3731 as_warn (_("alignment too large; assuming %d"), temp);
3732 }
3733#endif
3734
3735 if (temp < 0)
3736 {
3737 as_bad (_("negative alignment"));
3738 ignore_rest_of_line ();
3739 return;
3740 }
3741
3742#ifdef OBJ_ELF
49309057 3743 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3744 {
3745 segT old_sec;
3746 int old_subsec;
3747 char *p;
3748 int align;
3749
3750 old_sec = now_seg;
3751 old_subsec = now_subseg;
3752
3753 if (temp == 0)
3754 align = 0;
3755 else
3756 align = log2 (temp);
3757
3758 if (align < 0)
3759 {
3760 as_bad (_("alignment not a power of 2"));
3761 ignore_rest_of_line ();
3762 return;
3763 }
3764
3765 record_alignment (bss_section, align);
3766 subseg_set (bss_section, 0);
3767 if (align)
3768 frag_align (align, 0, 0);
3769 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3770 symbol_get_frag (symbolP)->fr_symbol = 0;
3771 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3772 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3773 (offsetT) size, (char *) 0);
3774 *p = 0;
3775 S_SET_SEGMENT (symbolP, bss_section);
3776 S_CLEAR_EXTERNAL (symbolP);
3777 S_SET_SIZE (symbolP, size);
3778 subseg_set (old_sec, old_subsec);
3779 }
3780 else
e0c6ed95 3781#endif /* OBJ_ELF */
252b5132
RH		 3782 {
3783 allocate_common:
3784 S_SET_VALUE (symbolP, (valueT) size);
3785#ifdef OBJ_ELF
3786 S_SET_ALIGN (symbolP, temp);
3787 S_SET_SIZE (symbolP, size);
3788#endif
3789 S_SET_EXTERNAL (symbolP);
3790 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3791 }
3792 }
3793 else
3794 {
3795 input_line_pointer++;
3796 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3797 if (*input_line_pointer == '.')
3798 input_line_pointer++;
3799 /* @@ Some say data, some say bss. */
3800 if (strncmp (input_line_pointer, "bss\"", 4)
3801 && strncmp (input_line_pointer, "data\"", 5))
3802 {
3803 while (*--input_line_pointer != '"')
3804 ;
3805 input_line_pointer--;
3806 goto bad_common_segment;
3807 }
3808 while (*input_line_pointer++ != '"')
3809 ;
3810 goto allocate_common;
3811 }
3812
3813#ifdef BFD_ASSEMBLER
49309057 3814 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3815#endif
3816
3817 demand_empty_rest_of_line ();
3818 return;
3819
3820 {
3821 bad_common_segment:
3822 p = input_line_pointer;
3823 while (*p && *p != '\n')
3824 p++;
3825 c = *p;
3826 *p = '\0';
3827 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3828 *p = c;
3829 input_line_pointer = p;
3830 ignore_rest_of_line ();
3831 return;
3832 }
3833}
3834
3835/* Handle the .empty pseudo-op. This supresses the warnings about
3836 invalid delay slot usage. */
3837
3838static void
3839s_empty (ignore)
c2158c24 3840 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3841{
3842 /* The easy way to implement is to just forget about the last
3843 instruction. */
3844 last_insn = NULL;
3845}
3846
3847static void
3848s_seg (ignore)
c2158c24 3849 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3850{
3851
3852 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3853 {
3854 input_line_pointer += 6;
3855 s_text (0);
3856 return;
3857 }
3858 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3859 {
3860 input_line_pointer += 6;
3861 s_data (0);
3862 return;
3863 }
3864 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3865 {
3866 input_line_pointer += 7;
3867 s_data1 ();
3868 return;
3869 }
3870 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3871 {
3872 input_line_pointer += 5;
3873 /* We only support 2 segments -- text and data -- for now, so
3874 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 3875 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3876 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 3877 return;
3878 }
3879 as_bad (_("Unknown segment type"));
3880 demand_empty_rest_of_line ();
3881}
3882
3883static void
3884s_data1 ()
3885{
3886 subseg_set (data_section, 1);
3887 demand_empty_rest_of_line ();
3888}
3889
3890static void
3891s_proc (ignore)
c2158c24 3892 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3893{
3894 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3895 {
3896 ++input_line_pointer;
3897 }
3898 ++input_line_pointer;
3899}
3900
3901/* This static variable is set by s_uacons to tell sparc_cons_align
3902 that the expession does not need to be aligned. */
3903
3904static int sparc_no_align_cons = 0;
3905
3906/* This handles the unaligned space allocation pseudo-ops, such as
3907 .uaword. .uaword is just like .word, but the value does not need
3908 to be aligned. */
3909
3910static void
3911s_uacons (bytes)
3912 int bytes;
3913{
3914 /* Tell sparc_cons_align not to align this value. */
3915 sparc_no_align_cons = 1;
3916 cons (bytes);
3917}
3918
cf9a1301
RH		 3919/* This handles the native word allocation pseudo-op .nword.
3920 For sparc_arch_size 32 it is equivalent to .word, for
3921 sparc_arch_size 64 it is equivalent to .xword. */
3922
3923static void
3924s_ncons (bytes)
c2158c24 3925 int bytes ATTRIBUTE_UNUSED;
cf9a1301
RH		 3926{
3927 cons (sparc_arch_size == 32 ? 4 : 8);
3928}
3929
6d8809aa
RH		 3930#ifdef OBJ_ELF
3931/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3932 global register.
3933 The syntax is:
e0c6ed95 3934
6d8809aa 3935 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 3936*/
6d8809aa
RH		 3937
3938static void
3939s_register (ignore)
c2158c24 3940 int ignore ATTRIBUTE_UNUSED;
6d8809aa
RH		 3941{
3942 char c;
3943 int reg;
3944 int flags;
3945 const char *regname;
3946
3947 if (input_line_pointer[0] != '%'
3948 || input_line_pointer[1] != 'g'
3949 || ((input_line_pointer[2] & ~1) != '2'
3950 && (input_line_pointer[2] & ~1) != '6')
3951 || input_line_pointer[3] != ',')
3952 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3953 reg = input_line_pointer[2] - '0';
3954 input_line_pointer += 4;
3955
3956 if (*input_line_pointer == '#')
3957 {
3958 ++input_line_pointer;
3959 regname = input_line_pointer;
3960 c = get_symbol_end ();
3961 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3962 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 3963 if (regname[0] == 'i')
6d8809aa
RH		 3964 regname = NULL;
3965 else
3966 regname = "";
3967 }
3968 else
3969 {
3970 regname = input_line_pointer;
3971 c = get_symbol_end ();
3972 }
3973 if (sparc_arch_size == 64)
3974 {
e0c6ed95 3975 if (globals[reg])
6d8809aa 3976 {
e0c6ed95
AM		 3977 if ((regname && globals[reg] != (symbolS *) 1
3978 && strcmp (S_GET_NAME (globals[reg]), regname))
3979 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 3980 as_bad (_("redefinition of global register"));
3981 }
3982 else
3983 {
3984 if (regname == NULL)
e0c6ed95 3985 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 3986 else
3987 {
3988 if (*regname)
3989 {
3990 if (symbol_find (regname))
3991 as_bad (_("Register symbol %s already defined."),
3992 regname);
3993 }
e0c6ed95
AM		 3994 globals[reg] = symbol_make (regname);
3995 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 3996 if (! *regname)
3997 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3998 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3999 flags |= BSF_GLOBAL;
e0c6ed95
AM		 4000 symbol_get_bfdsym (globals[reg])->flags = flags;
4001 S_SET_VALUE (globals[reg], (valueT) reg);
4002 S_SET_ALIGN (globals[reg], reg);
4003 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 4004 /* Although we actually want undefined_section here,
4005 we have to use absolute_section, because otherwise
4006 generic as code will make it a COM section.
4007 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 4008 S_SET_SEGMENT (globals[reg], absolute_section);
4009 S_SET_OTHER (globals[reg], 0);
4010 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4011 ->internal_elf_sym.st_info =
4012 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 4013 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4014 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4015 }
4016 }
4017 }
4018
4019 *input_line_pointer = c;
4020
4021 demand_empty_rest_of_line ();
4022}
4023
4024/* Adjust the symbol table. We set undefined sections for STT_REGISTER
4025 symbols which need it. */
e0c6ed95 4026
6d8809aa
RH		 4027void
4028sparc_adjust_symtab ()
4029{
4030 symbolS *sym;
e0c6ed95 4031
6d8809aa
RH		 4032 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4033 {
4034 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4035 ->internal_elf_sym.st_info) != STT_REGISTER)
4036 continue;
4037
4038 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4039 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4040 continue;
4041
4042 S_SET_SEGMENT (sym, undefined_section);
4043 }
4044}
4045#endif
4046
252b5132
RH		 4047/* If the --enforce-aligned-data option is used, we require .word,
4048 et. al., to be aligned correctly. We do it by setting up an
4049 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4050 no unexpected alignment was introduced.
4051
4052 The SunOS and Solaris native assemblers enforce aligned data by
4053 default. We don't want to do that, because gcc can deliberately
4054 generate misaligned data if the packed attribute is used. Instead,
4055 we permit misaligned data by default, and permit the user to set an
4056 option to check for it. */
4057
4058void
4059sparc_cons_align (nbytes)
4060 int nbytes;
4061{
4062 int nalign;
4063 char *p;
4064
4065 /* Only do this if we are enforcing aligned data. */
4066 if (! enforce_aligned_data)
4067 return;
4068
4069 if (sparc_no_align_cons)
4070 {
4071 /* This is an unaligned pseudo-op. */
4072 sparc_no_align_cons = 0;
4073 return;
4074 }
4075
4076 nalign = log2 (nbytes);
4077 if (nalign == 0)
4078 return;
4079
4080 assert (nalign > 0);
4081
4082 if (now_seg == absolute_section)
4083 {
4084 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4085 as_bad (_("misaligned data"));
4086 return;
4087 }
4088
0a9ef439 4089 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
252b5132
RH		 4090 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4091
4092 record_alignment (now_seg, nalign);
4093}
4094
0a9ef439 4095/* This is called from HANDLE_ALIGN in tc-sparc.h. */
252b5132
RH		 4096
4097void
4098sparc_handle_align (fragp)
4099 fragS *fragp;
4100{
0a9ef439
RH		 4101 int count, fix;
4102 char *p;
4103
4104 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
bfb32b52 4105
0a9ef439 4106 switch (fragp->fr_type)
252b5132 4107 {
0a9ef439
RH		 4108 case rs_align_test:
4109 if (count != 0)
4110 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4111 break;
e0c6ed95 4112
0a9ef439
RH		 4113 case rs_align_code:
4114 p = fragp->fr_literal + fragp->fr_fix;
4115 fix = 0;
e0c6ed95 4116
0a9ef439
RH		 4117 if (count & 3)
4118 {
4119 fix = count & 3;
4120 memset (p, 0, fix);
4121 p += fix;
4122 count -= fix;
4123 }
e0c6ed95 4124
0a9ef439
RH		 4125 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4126 {
4127 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4128 if (INSN_BIG_ENDIAN)
4129 number_to_chars_bigendian (p, wval, 4);
4130 else
4131 number_to_chars_littleendian (p, wval, 4);
4132 p += 4;
4133 count -= 4;
4134 fix += 4;
e0c6ed95 4135 }
0a9ef439
RH		 4136
4137 if (INSN_BIG_ENDIAN)
4138 number_to_chars_bigendian (p, 0x01000000, 4);
4139 else
4140 number_to_chars_littleendian (p, 0x01000000, 4);
4141
4142 fragp->fr_fix += fix;
4143 fragp->fr_var = 4;
4144 break;
4145
4146 default:
4147 break;
252b5132
RH		 4148 }
4149}
4150
4151#ifdef OBJ_ELF
4152/* Some special processing for a Sparc ELF file. */
4153
4154void
4155sparc_elf_final_processing ()
4156{
4157 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4158 sort of BFD interface for this. */
4159 if (sparc_arch_size == 64)
4160 {
4161 switch (sparc_memory_model)
4162 {
4163 case MM_RMO:
4164 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4165 break;
4166 case MM_PSO:
4167 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4168 break;
4169 default:
4170 break;
4171 }
4172 }
4173 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4174 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4175 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4176 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
19f7b010
JJ		 4177 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4178 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
252b5132
RH		 4179}
4180#endif
4181
4182/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4183 reloc for a cons. We could use the definition there, except that
4184 we want to handle little endian relocs specially. */
4185
4186void
4187cons_fix_new_sparc (frag, where, nbytes, exp)
4188 fragS *frag;
4189 int where;
4190 unsigned int nbytes;
4191 expressionS *exp;
4192{
4193 bfd_reloc_code_real_type r;
4194
4195 r = (nbytes == 1 ? BFD_RELOC_8 :
4196 (nbytes == 2 ? BFD_RELOC_16 :
4197 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4198
4199 if (target_little_endian_data && nbytes == 4
e0c6ed95 4200 && now_seg->flags & SEC_ALLOC)
252b5132
RH		 4201 r = BFD_RELOC_SPARC_REV32;
4202 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4203}
4204
4205#ifdef OBJ_ELF
4206int
4207elf32_sparc_force_relocation (fixp)
e0c6ed95 4208 struct fix *fixp;
252b5132
RH		 4209{
4210 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4211 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4212 return 1;
e0c6ed95 4213
252b5132
RH		 4214 return 0;
4215}
4216#endif
GDB Binutils - Deliverables
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