projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PR ld/12549
[deliverable/binutils-gdb.git] / gas / config / tc-v850.c
CommitLineData
252b5132 1/* tc-v850.c -- Assembler code for the NEC V850
78c8d46c 2 Copyright 1996-2013 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
252b5132 20
252b5132 21#include "as.h"
3882b010 22#include "safe-ctype.h"
28e4f854 23#include "subsegs.h"
252b5132 24#include "opcode/v850.h"
a8761a19 25#include "dwarf2dbg.h"
252b5132 26
28e4f854
KH		 27/* Sign-extend a 16-bit number. */
28#define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
252b5132
RH		 29
30/* Temporarily holds the reloc in a cons expression. */
a8761a19 31static bfd_reloc_code_real_type hold_cons_reloc = BFD_RELOC_UNUSED;
252b5132
RH		 32
33/* Set to TRUE if we want to be pedantic about signed overflows. */
b34976b6
AM		 34static bfd_boolean warn_signed_overflows = FALSE;
35static bfd_boolean warn_unsigned_overflows = FALSE;
252b5132
RH		 36
37/* Indicates the target BFD machine number. */
28e4f854 38static int machine = -1;
252b5132 39
de863c74
NC		 40
41/* Indiciates the target BFD architecture. */
42int v850_target_arch = bfd_arch_v850_rh850;
43const char * v850_target_format = "elf32-v850-rh850";
44static flagword v850_e_flags = 0;
45
252b5132 46/* Indicates the target processor(s) for the assemble. */
1cd986c5 47static int processor_mask = 0;
252b5132
RH		 48\f
49/* Structure to hold information about predefined registers. */
ea1562b3
NC		 50struct reg_name
51{
28e4f854
KH		 52 const char *name;
53 int value;
1cd986c5 54 unsigned int processors;
252b5132
RH		 55};
56
28e4f854
KH		 57/* Generic assembler global variables which must be defined by all
58 targets. */
252b5132 59
28e4f854 60/* Characters which always start a comment. */
252b5132
RH		 61const char comment_chars[] = "#";
62
63/* Characters which start a comment at the beginning of a line. */
64const char line_comment_chars[] = ";#";
65
28e4f854 66/* Characters which may be used to separate multiple commands on a
252b5132
RH		 67 single line. */
68const char line_separator_chars[] = ";";
69
28e4f854 70/* Characters which are used to indicate an exponent in a floating
252b5132
RH		 71 point number. */
72const char EXP_CHARS[] = "eE";
73
28e4f854 74/* Characters which mean that a number is a floating point constant,
252b5132
RH		 75 as in 0d1.0. */
76const char FLT_CHARS[] = "dD";
77\f
ea1562b3
NC		 78const relax_typeS md_relax_table[] =
79{
1cd986c5
NC		 80 /* Conditional branches.(V850/V850E, max 22bit) */
81#define SUBYPTE_COND_9_22 0
82 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1},
83 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
84 /* Conditional branches.(V850/V850E, max 22bit) */
85#define SUBYPTE_SA_9_22 2
86 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1},
87 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
88 /* Unconditional branches.(V850/V850E, max 22bit) */
89#define SUBYPTE_UNCOND_9_22 4
90 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1},
91 {0x1ffffe, -0x200000, 4, 0},
92 /* Conditional branches.(V850E2, max 32bit) */
93#define SUBYPTE_COND_9_22_32 6
94 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1},
95 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2},
96 {0x7ffffffe, -0x80000000, 8, 0},
97 /* Conditional branches.(V850E2, max 32bit) */
98#define SUBYPTE_SA_9_22_32 9
99 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1},
100 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2},
101 {0x7ffffffe, -0x80000000, 10, 0},
102 /* Unconditional branches.(V850E2, max 32bit) */
103#define SUBYPTE_UNCOND_9_22_32 12
104 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1},
105 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2},
106 {0x7ffffffe, -0x80000000, 6, 0},
107 /* Conditional branches.(V850E2R max 22bit) */
108#define SUBYPTE_COND_9_17_22 15
109 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1},
110 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2},
111 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
112 /* Conditional branches.(V850E2R max 22bit) */
113#define SUBYPTE_SA_9_17_22 18
114 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1},
115 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2},
116 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
117 /* Conditional branches.(V850E2R max 32bit) */
118#define SUBYPTE_COND_9_17_22_32 21
119 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1},
120 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2},
121 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3},
122 {0x7ffffffe, -0x80000000, 8, 0},
123 /* Conditional branches.(V850E2R max 32bit) */
124#define SUBYPTE_SA_9_17_22_32 25
125 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1},
126 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2},
127 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
128 {0x7ffffffe, -0x80000000, 10, 0},
78c8d46c
NC		 129 /* Loop. (V850E2V4_UP, max 22-bit). */
130#define SUBYPTE_LOOP_16_22 29
131 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1},
132 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
252b5132
RH		 133};
134
1cd986c5
NC		 135static int v850_relax = 0;
136
137/* Default branch disp size 22 or 32. */
138static int default_disp_size = 22;
139
140/* Default no using bcond17. */
141static int no_bcond17 = 0;
142
143/* Default no using ld/st 23bit offset. */
144static int no_stld23 = 0;
86aba9db 145
28e4f854 146/* Fixups. */
ea1562b3
NC		 147#define MAX_INSN_FIXUPS 5
148
149struct v850_fixup
150{
28e4f854
KH		 151 expressionS exp;
152 int opindex;
252b5132
RH		 153 bfd_reloc_code_real_type reloc;
154};
155
28e4f854 156struct v850_fixup fixups[MAX_INSN_FIXUPS];
252b5132 157static int fc;
252b5132 158
9e0665bc 159struct v850_seg_entry
252b5132 160{
9e0665bc
AM		 161 segT s;
162 const char *name;
163 flagword flags;
164};
252b5132 165
9e0665bc 166struct v850_seg_entry v850_seg_table[] =
252b5132 167{
9e0665bc
AM		 168 { NULL, ".sdata",
169 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
170 | SEC_SMALL_DATA },
171 { NULL, ".tdata",
172 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
173 { NULL, ".zdata",
174 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
175 { NULL, ".sbss",
176 SEC_ALLOC | SEC_SMALL_DATA },
177 { NULL, ".tbss",
178 SEC_ALLOC },
179 { NULL, ".zbss",
180 SEC_ALLOC},
181 { NULL, ".rosdata",
182 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
183 | SEC_HAS_CONTENTS | SEC_SMALL_DATA },
184 { NULL, ".rozdata",
185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
186 | SEC_HAS_CONTENTS },
187 { NULL, ".scommon",
188 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
189 | SEC_SMALL_DATA | SEC_IS_COMMON },
190 { NULL, ".tcommon",
191 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
192 | SEC_IS_COMMON },
193 { NULL, ".zcommon",
194 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
195 | SEC_IS_COMMON },
196 { NULL, ".call_table_data",
197 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
198 { NULL, ".call_table_text",
199 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE
200 | SEC_HAS_CONTENTS},
201 { NULL, ".bss",
202 SEC_ALLOC }
203};
28e4f854 204
9e0665bc
AM		 205#define SDATA_SECTION 0
206#define TDATA_SECTION 1
207#define ZDATA_SECTION 2
208#define SBSS_SECTION 3
209#define TBSS_SECTION 4
210#define ZBSS_SECTION 5
211#define ROSDATA_SECTION 6
212#define ROZDATA_SECTION 7
213#define SCOMMON_SECTION 8
214#define TCOMMON_SECTION 9
215#define ZCOMMON_SECTION 10
216#define CALL_TABLE_DATA_SECTION 11
217#define CALL_TABLE_TEXT_SECTION 12
218#define BSS_SECTION 13
219
9e0665bc 220static void
ea1562b3 221do_v850_seg (int i, subsegT sub)
252b5132 222{
9e0665bc 223 struct v850_seg_entry *seg = v850_seg_table + i;
28e4f854 224
28e4f854 225 obj_elf_section_change_hook ();
ea1562b3 226
9e0665bc 227 if (seg->s != NULL)
ea1562b3 228 subseg_set (seg->s, sub);
9e0665bc
AM		 229 else
230 {
231 seg->s = subseg_new (seg->name, sub);
232 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
233 if ((seg->flags & SEC_LOAD) == 0)
234 seg_info (seg->s)->bss = 1;
235 }
252b5132
RH		 236}
237
9e0665bc 238static void
ea1562b3 239v850_seg (int i)
252b5132 240{
9e0665bc 241 subsegT sub = get_absolute_expression ();
28e4f854 242
9e0665bc 243 do_v850_seg (i, sub);
252b5132
RH		 244 demand_empty_rest_of_line ();
245}
246
9e0665bc 247static void
ea1562b3 248v850_offset (int ignore ATTRIBUTE_UNUSED)
252b5132 249{
825487fa 250 char *pfrag;
252b5132 251 int temp = get_absolute_expression ();
685736be 252
825487fa 253 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0,
ec178e1b 254 (offsetT) temp, (char *) 0);
825487fa 255 *pfrag = 0;
28e4f854 256
252b5132
RH		 257 demand_empty_rest_of_line ();
258}
259
28e4f854
KH		 260/* Copied from obj_elf_common() in gas/config/obj-elf.c. */
261
252b5132 262static void
ea1562b3 263v850_comm (int area)
252b5132 264{
28e4f854
KH		 265 char *name;
266 char c;
267 char *p;
268 int temp;
269 unsigned int size;
270 symbolS *symbolP;
271 int have_align;
252b5132
RH		 272
273 name = input_line_pointer;
274 c = get_symbol_end ();
28e4f854
KH		 275
276 /* Just after name is now '\0'. */
252b5132
RH		 277 p = input_line_pointer;
278 *p = c;
28e4f854 279
252b5132 280 SKIP_WHITESPACE ();
28e4f854 281
252b5132
RH		 282 if (*input_line_pointer != ',')
283 {
284 as_bad (_("Expected comma after symbol-name"));
285 ignore_rest_of_line ();
286 return;
287 }
28e4f854
KH		 288
289 /* Skip ','. */
290 input_line_pointer++;
291
252b5132
RH		 292 if ((temp = get_absolute_expression ()) < 0)
293 {
28e4f854 294 /* xgettext:c-format */
252b5132
RH		 295 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp);
296 ignore_rest_of_line ();
297 return;
298 }
28e4f854 299
252b5132
RH		 300 size = temp;
301 *p = 0;
302 symbolP = symbol_find_or_make (name);
303 *p = c;
28e4f854 304
252b5132
RH		 305 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
306 {
307 as_bad (_("Ignoring attempt to re-define symbol"));
308 ignore_rest_of_line ();
309 return;
310 }
28e4f854 311
252b5132
RH		 312 if (S_GET_VALUE (symbolP) != 0)
313 {
314 if (S_GET_VALUE (symbolP) != size)
ea1562b3
NC		 315 /* xgettext:c-format */
316 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
317 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
252b5132 318 }
28e4f854
KH		 319
320 know (symbol_get_frag (symbolP) == &zero_address_frag);
321
252b5132
RH		 322 if (*input_line_pointer != ',')
323 have_align = 0;
324 else
325 {
326 have_align = 1;
327 input_line_pointer++;
328 SKIP_WHITESPACE ();
329 }
28e4f854 330
252b5132
RH		 331 if (! have_align || *input_line_pointer != '"')
332 {
333 if (! have_align)
334 temp = 0;
335 else
336 {
337 temp = get_absolute_expression ();
28e4f854 338
252b5132
RH		 339 if (temp < 0)
340 {
341 temp = 0;
342 as_warn (_("Common alignment negative; 0 assumed"));
343 }
344 }
28e4f854 345
cac58fa6 346 if (symbol_get_obj (symbolP)->local)
252b5132 347 {
28e4f854
KH		 348 segT old_sec;
349 int old_subsec;
350 char *pfrag;
351 int align;
352 flagword applicable;
252b5132
RH		 353
354 old_sec = now_seg;
355 old_subsec = now_subseg;
28e4f854 356
252b5132 357 applicable = bfd_applicable_section_flags (stdoutput);
28e4f854 358
252b5132 359 applicable &= SEC_ALLOC;
28e4f854 360
252b5132
RH		 361 switch (area)
362 {
9e0665bc
AM		 363 case SCOMMON_SECTION:
364 do_v850_seg (SBSS_SECTION, 0);
252b5132 365 break;
28e4f854 366
9e0665bc
AM		 367 case ZCOMMON_SECTION:
368 do_v850_seg (ZBSS_SECTION, 0);
252b5132 369 break;
28e4f854 370
9e0665bc
AM		 371 case TCOMMON_SECTION:
372 do_v850_seg (TBSS_SECTION, 0);
252b5132
RH		 373 break;
374 }
375
376 if (temp)
377 {
28e4f854 378 /* Convert to a power of 2 alignment. */
252b5132
RH		 379 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align)
380 ;
28e4f854 381
252b5132
RH		 382 if (temp != 1)
383 {
384 as_bad (_("Common alignment not a power of 2"));
385 ignore_rest_of_line ();
386 return;
387 }
388 }
389 else
390 align = 0;
28e4f854 391
9e0665bc 392 record_alignment (now_seg, align);
28e4f854 393
252b5132
RH		 394 if (align)
395 frag_align (align, 0, 0);
396
397 switch (area)
398 {
9e0665bc
AM		 399 case SCOMMON_SECTION:
400 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s)
7dcc9865 401 symbol_get_frag (symbolP)->fr_symbol = 0;
252b5132
RH		 402 break;
403
9e0665bc
AM		 404 case ZCOMMON_SECTION:
405 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s)
7dcc9865 406 symbol_get_frag (symbolP)->fr_symbol = 0;
252b5132
RH		 407 break;
408
9e0665bc
AM		 409 case TCOMMON_SECTION:
410 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s)
7dcc9865 411 symbol_get_frag (symbolP)->fr_symbol = 0;
252b5132
RH		 412 break;
413
414 default:
cac58fa6 415 abort ();
252b5132 416 }
28e4f854 417
7dcc9865 418 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 419 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
420 (offsetT) size, (char *) 0);
421 *pfrag = 0;
422 S_SET_SIZE (symbolP, size);
28e4f854 423
252b5132
RH		 424 switch (area)
425 {
9e0665bc
AM		 426 case SCOMMON_SECTION:
427 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s);
252b5132 428 break;
28e4f854 429
9e0665bc
AM		 430 case ZCOMMON_SECTION:
431 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s);
252b5132 432 break;
28e4f854 433
9e0665bc
AM		 434 case TCOMMON_SECTION:
435 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s);
252b5132 436 break;
28e4f854 437
252b5132 438 default:
28e4f854 439 abort ();
252b5132 440 }
28e4f854 441
252b5132 442 S_CLEAR_EXTERNAL (symbolP);
28e4f854 443 obj_elf_section_change_hook ();
252b5132
RH		 444 subseg_set (old_sec, old_subsec);
445 }
446 else
447 {
ec178e1b
AM		 448 segT old_sec;
449 int old_subsec;
86aba9db 450
252b5132 451 allocate_common:
ec178e1b
AM		 452 old_sec = now_seg;
453 old_subsec = now_subseg;
86aba9db 454
252b5132
RH		 455 S_SET_VALUE (symbolP, (valueT) size);
456 S_SET_ALIGN (symbolP, temp);
457 S_SET_EXTERNAL (symbolP);
28e4f854 458
252b5132
RH		 459 switch (area)
460 {
9e0665bc
AM		 461 case SCOMMON_SECTION:
462 case ZCOMMON_SECTION:
463 case TCOMMON_SECTION:
464 do_v850_seg (area, 0);
465 S_SET_SEGMENT (symbolP, v850_seg_table[area].s);
252b5132 466 break;
28e4f854 467
252b5132 468 default:
28e4f854 469 abort ();
252b5132 470 }
86aba9db
NC		 471
472 obj_elf_section_change_hook ();
473 subseg_set (old_sec, old_subsec);
252b5132
RH		 474 }
475 }
476 else
477 {
478 input_line_pointer++;
28e4f854 479
252b5132
RH		 480 /* @@ Some use the dot, some don't. Can we get some consistency?? */
481 if (*input_line_pointer == '.')
482 input_line_pointer++;
28e4f854 483
252b5132
RH		 484 /* @@ Some say data, some say bss. */
485 if (strncmp (input_line_pointer, "bss\"", 4)
486 && strncmp (input_line_pointer, "data\"", 5))
487 {
488 while (*--input_line_pointer != '"')
489 ;
490 input_line_pointer--;
491 goto bad_common_segment;
492 }
ea1562b3 493
252b5132
RH		 494 while (*input_line_pointer++ != '"')
495 ;
ea1562b3 496
252b5132
RH		 497 goto allocate_common;
498 }
499
fed9b18a 500 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 501
502 demand_empty_rest_of_line ();
503 return;
504
505 {
506 bad_common_segment:
507 p = input_line_pointer;
508 while (*p && *p != '\n')
509 p++;
510 c = *p;
511 *p = '\0';
512 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
513 *p = c;
514 input_line_pointer = p;
515 ignore_rest_of_line ();
516 return;
517 }
518}
519
9e0665bc 520static void
ea1562b3 521set_machine (int number)
252b5132
RH		 522{
523 machine = number;
de863c74 524 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
252b5132
RH		 525
526 switch (machine)
527 {
1cd986c5
NC		 528 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
529 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
530 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
531 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
532 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break;
533 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
78c8d46c 534 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break;
252b5132
RH		 535 }
536}
537
86aba9db 538static void
ea1562b3 539v850_longcode (int type)
86aba9db
NC		 540{
541 expressionS ex;
542
543 if (! v850_relax)
544 {
545 if (type == 1)
20203fb9 546 as_warn (_(".longcall pseudo-op seen when not relaxing"));
86aba9db 547 else
20203fb9 548 as_warn (_(".longjump pseudo-op seen when not relaxing"));
86aba9db
NC		 549 }
550
551 expression (&ex);
552
553 if (ex.X_op != O_symbol || ex.X_add_number != 0)
554 {
20203fb9 555 as_bad (_("bad .longcall format"));
86aba9db
NC		 556 ignore_rest_of_line ();
557
558 return;
559 }
560
ec178e1b 561 if (type == 1)
86aba9db
NC		 562 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
563 BFD_RELOC_V850_LONGCALL);
564 else
565 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
566 BFD_RELOC_V850_LONGJUMP);
567
568 demand_empty_rest_of_line ();
569}
570
252b5132 571/* The target specific pseudo-ops which we support. */
77c6dd37
NC		 572const pseudo_typeS md_pseudo_table[] =
573{
9e0665bc
AM		 574 { "sdata", v850_seg, SDATA_SECTION },
575 { "tdata", v850_seg, TDATA_SECTION },
576 { "zdata", v850_seg, ZDATA_SECTION },
577 { "sbss", v850_seg, SBSS_SECTION },
578 { "tbss", v850_seg, TBSS_SECTION },
579 { "zbss", v850_seg, ZBSS_SECTION },
580 { "rosdata", v850_seg, ROSDATA_SECTION },
581 { "rozdata", v850_seg, ROZDATA_SECTION },
582 { "bss", v850_seg, BSS_SECTION },
583 { "offset", v850_offset, 0 },
584 { "word", cons, 4 },
585 { "zcomm", v850_comm, ZCOMMON_SECTION },
586 { "scomm", v850_comm, SCOMMON_SECTION },
587 { "tcomm", v850_comm, TCOMMON_SECTION },
588 { "v850", set_machine, 0 },
589 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
590 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
591 { "v850e", set_machine, bfd_mach_v850e },
1cd986c5
NC		 592 { "v850e1", set_machine, bfd_mach_v850e1 },
593 { "v850e2", set_machine, bfd_mach_v850e2 },
594 { "v850e2v3", set_machine, bfd_mach_v850e2v3 },
78c8d46c
NC		 595 { "v850e2v4", set_machine, bfd_mach_v850e3v5 },
596 { "v850e3v5", set_machine, bfd_mach_v850e3v5 },
ec178e1b
AM		 597 { "longcall", v850_longcode, 1 },
598 { "longjump", v850_longcode, 2 },
9e0665bc 599 { NULL, NULL, 0 }
252b5132
RH		 600};
601
602/* Opcode hash table. */
603static struct hash_control *v850_hash;
604
28e4f854 605/* This table is sorted. Suitable for searching by a binary search. */
77c6dd37
NC		 606static const struct reg_name pre_defined_registers[] =
607{
1cd986c5
NC		 608 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */
609 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */
610 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */
611 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */
612 { "r0", 0, PROCESSOR_ALL },
613 { "r1", 1, PROCESSOR_ALL },
614 { "r10", 10, PROCESSOR_ALL },
615 { "r11", 11, PROCESSOR_ALL },
616 { "r12", 12, PROCESSOR_ALL },
617 { "r13", 13, PROCESSOR_ALL },
618 { "r14", 14, PROCESSOR_ALL },
619 { "r15", 15, PROCESSOR_ALL },
620 { "r16", 16, PROCESSOR_ALL },
621 { "r17", 17, PROCESSOR_ALL },
622 { "r18", 18, PROCESSOR_ALL },
623 { "r19", 19, PROCESSOR_ALL },
624 { "r2", 2, PROCESSOR_ALL },
625 { "r20", 20, PROCESSOR_ALL },
626 { "r21", 21, PROCESSOR_ALL },
627 { "r22", 22, PROCESSOR_ALL },
628 { "r23", 23, PROCESSOR_ALL },
629 { "r24", 24, PROCESSOR_ALL },
630 { "r25", 25, PROCESSOR_ALL },
631 { "r26", 26, PROCESSOR_ALL },
632 { "r27", 27, PROCESSOR_ALL },
633 { "r28", 28, PROCESSOR_ALL },
634 { "r29", 29, PROCESSOR_ALL },
635 { "r3", 3, PROCESSOR_ALL },
636 { "r30", 30, PROCESSOR_ALL },
637 { "r31", 31, PROCESSOR_ALL },
638 { "r4", 4, PROCESSOR_ALL },
639 { "r5", 5, PROCESSOR_ALL },
640 { "r6", 6, PROCESSOR_ALL },
641 { "r7", 7, PROCESSOR_ALL },
642 { "r8", 8, PROCESSOR_ALL },
643 { "r9", 9, PROCESSOR_ALL },
644 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */
645 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */
646 { "zero", 0, PROCESSOR_ALL },
252b5132 647};
252b5132 648
28e4f854
KH		 649#define REG_NAME_CNT \
650 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
252b5132 651
77c6dd37
NC		 652static const struct reg_name system_registers[] =
653{
1cd986c5
NC		 654 { "asid", 23, PROCESSOR_NOT_V850 },
655 { "bpam", 25, PROCESSOR_NOT_V850 },
656 { "bpav", 24, PROCESSOR_NOT_V850 },
657 { "bpc", 22, PROCESSOR_NOT_V850 },
658 { "bpdm", 27, PROCESSOR_NOT_V850 },
659 { "bpdv", 26, PROCESSOR_NOT_V850 },
78c8d46c
NC		 660 { "bsel", 31, PROCESSOR_V850E2_UP },
661 { "cfg", 7, PROCESSOR_V850E2V3_UP },
1cd986c5
NC		 662 { "ctbp", 20, PROCESSOR_NOT_V850 },
663 { "ctpc", 16, PROCESSOR_NOT_V850 },
664 { "ctpsw", 17, PROCESSOR_NOT_V850 },
78c8d46c 665 { "dbic", 15, PROCESSOR_V850E2_UP },
1cd986c5
NC		 666 { "dbpc", 18, PROCESSOR_NOT_V850 },
667 { "dbpsw", 19, PROCESSOR_NOT_V850 },
78c8d46c 668 { "dbwr", 30, PROCESSOR_V850E2_UP },
1cd986c5 669 { "dir", 21, PROCESSOR_NOT_V850 },
78c8d46c
NC		 670 { "dpa0l", 16, PROCESSOR_V850E2V3_UP },
671 { "dpa0u", 17, PROCESSOR_V850E2V3_UP },
672 { "dpa1l", 18, PROCESSOR_V850E2V3_UP },
673 { "dpa1u", 19, PROCESSOR_V850E2V3_UP },
674 { "dpa2l", 20, PROCESSOR_V850E2V3_UP },
675 { "dpa2u", 21, PROCESSOR_V850E2V3_UP },
676 { "dpa3l", 22, PROCESSOR_V850E2V3_UP },
677 { "dpa3u", 23, PROCESSOR_V850E2V3_UP },
678 { "dpa4l", 24, PROCESSOR_V850E2V3_UP },
679 { "dpa4u", 25, PROCESSOR_V850E2V3_UP },
680 { "dpa5l", 26, PROCESSOR_V850E2V3_UP },
681 { "dpa5u", 27, PROCESSOR_V850E2V3_UP },
1cd986c5 682 { "ecr", 4, PROCESSOR_ALL },
78c8d46c
NC		 683 { "eh_base", 3, PROCESSOR_V850E2V3_UP },
684 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP },
685 { "eh_reset", 2, PROCESSOR_V850E2V3_UP },
686 { "eiic", 13, PROCESSOR_V850E2_UP },
1cd986c5
NC		 687 { "eipc", 0, PROCESSOR_ALL },
688 { "eipsw", 1, PROCESSOR_ALL },
78c8d46c
NC		 689 { "eiwr", 28, PROCESSOR_V850E2_UP },
690 { "feic", 14, PROCESSOR_V850E2_UP },
1cd986c5
NC		 691 { "fepc", 2, PROCESSOR_ALL },
692 { "fepsw", 3, PROCESSOR_ALL },
78c8d46c
NC		 693 { "fewr", 29, PROCESSOR_V850E2_UP },
694 { "fpcc", 9, PROCESSOR_V850E2V3_UP },
695 { "fpcfg", 10, PROCESSOR_V850E2V3_UP },
696 { "fpec", 11, PROCESSOR_V850E2V3_UP },
697 { "fpepc", 7, PROCESSOR_V850E2V3_UP },
698 { "fpspc", 27, PROCESSOR_V850E2V3_UP },
699 { "fpsr", 6, PROCESSOR_V850E2V3_UP },
700 { "fpst", 8, PROCESSOR_V850E2V3_UP },
701 { "ipa0l", 6, PROCESSOR_V850E2V3_UP },
702 { "ipa0u", 7, PROCESSOR_V850E2V3_UP },
703 { "ipa1l", 8, PROCESSOR_V850E2V3_UP },
704 { "ipa1u", 9, PROCESSOR_V850E2V3_UP },
705 { "ipa2l", 10, PROCESSOR_V850E2V3_UP },
706 { "ipa2u", 11, PROCESSOR_V850E2V3_UP },
707 { "ipa3l", 12, PROCESSOR_V850E2V3_UP },
708 { "ipa3u", 13, PROCESSOR_V850E2V3_UP },
709 { "ipa4l", 14, PROCESSOR_V850E2V3_UP },
710 { "ipa4u", 15, PROCESSOR_V850E2V3_UP },
711 { "mca", 24, PROCESSOR_V850E2V3_UP },
712 { "mcc", 26, PROCESSOR_V850E2V3_UP },
713 { "mcr", 27, PROCESSOR_V850E2V3_UP },
714 { "mcs", 25, PROCESSOR_V850E2V3_UP },
715 { "mpc", 1, PROCESSOR_V850E2V3_UP },
716 { "mpm", 0, PROCESSOR_V850E2V3_UP },
717 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP },
718 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP },
719 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP },
720 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP },
721 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP },
722 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP },
723 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP },
724 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP },
725 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP },
726 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP },
727 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP },
728 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP },
729 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP },
730 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP },
731 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP },
732 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP },
733 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP },
734 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP },
735 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP },
736 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP },
737 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP },
738 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP },
739 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP },
740 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP },
741 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP },
742 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP },
743 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP },
744 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP },
745 { "pid", 6, PROCESSOR_V850E2V3_UP },
746 { "pmcr0", 4, PROCESSOR_V850E2V3_UP },
747 { "pmis2", 14, PROCESSOR_V850E2V3_UP },
1cd986c5 748 { "psw", 5, PROCESSOR_ALL },
78c8d46c
NC		 749 { "scbp", 12, PROCESSOR_V850E2V3_UP },
750 { "sccfg", 11, PROCESSOR_V850E2V3_UP },
1cd986c5
NC		 751 { "sr0", 0, PROCESSOR_ALL },
752 { "sr1", 1, PROCESSOR_ALL },
753 { "sr10", 10, PROCESSOR_ALL },
754 { "sr11", 11, PROCESSOR_ALL },
755 { "sr12", 12, PROCESSOR_ALL },
756 { "sr13", 13, PROCESSOR_ALL },
757 { "sr14", 14, PROCESSOR_ALL },
758 { "sr15", 15, PROCESSOR_ALL },
759 { "sr16", 16, PROCESSOR_ALL },
760 { "sr17", 17, PROCESSOR_ALL },
761 { "sr18", 18, PROCESSOR_ALL },
762 { "sr19", 19, PROCESSOR_ALL },
763 { "sr2", 2, PROCESSOR_ALL },
764 { "sr20", 20, PROCESSOR_ALL },
765 { "sr21", 21, PROCESSOR_ALL },
766 { "sr22", 22, PROCESSOR_ALL },
767 { "sr23", 23, PROCESSOR_ALL },
768 { "sr24", 24, PROCESSOR_ALL },
769 { "sr25", 25, PROCESSOR_ALL },
770 { "sr26", 26, PROCESSOR_ALL },
771 { "sr27", 27, PROCESSOR_ALL },
772 { "sr28", 28, PROCESSOR_ALL },
773 { "sr29", 29, PROCESSOR_ALL },
774 { "sr3", 3, PROCESSOR_ALL },
775 { "sr30", 30, PROCESSOR_ALL },
776 { "sr31", 31, PROCESSOR_ALL },
777 { "sr4", 4, PROCESSOR_ALL },
778 { "sr5", 5, PROCESSOR_ALL },
779 { "sr6", 6, PROCESSOR_ALL },
780 { "sr7", 7, PROCESSOR_ALL },
781 { "sr8", 8, PROCESSOR_ALL },
782 { "sr9", 9, PROCESSOR_ALL },
78c8d46c
NC		 783 { "sw_base", 3, PROCESSOR_V850E2V3_UP },
784 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP },
785 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP },
786 { "tid", 2, PROCESSOR_V850E2V3_UP },
787 { "vmadr", 6, PROCESSOR_V850E2V3_UP },
788 { "vmecr", 4, PROCESSOR_V850E2V3_UP },
789 { "vmtid", 5, PROCESSOR_V850E2V3_UP },
790 { "vsadr", 2, PROCESSOR_V850E2V3_UP },
791 { "vsecr", 0, PROCESSOR_V850E2V3_UP },
792 { "vstid", 1, PROCESSOR_V850E2V3_UP },
252b5132 793};
28e4f854
KH		 794
795#define SYSREG_NAME_CNT \
796 (sizeof (system_registers) / sizeof (struct reg_name))
252b5132 797
252b5132 798
77c6dd37
NC		 799static const struct reg_name cc_names[] =
800{
1cd986c5
NC		 801 { "c", 0x1, PROCESSOR_ALL },
802 { "e", 0x2, PROCESSOR_ALL },
803 { "ge", 0xe, PROCESSOR_ALL },
804 { "gt", 0xf, PROCESSOR_ALL },
805 { "h", 0xb, PROCESSOR_ALL },
806 { "l", 0x1, PROCESSOR_ALL },
807 { "le", 0x7, PROCESSOR_ALL },
808 { "lt", 0x6, PROCESSOR_ALL },
809 { "n", 0x4, PROCESSOR_ALL },
810 { "nc", 0x9, PROCESSOR_ALL },
811 { "ne", 0xa, PROCESSOR_ALL },
812 { "nh", 0x3, PROCESSOR_ALL },
813 { "nl", 0x9, PROCESSOR_ALL },
814 { "ns", 0xc, PROCESSOR_ALL },
815 { "nv", 0x8, PROCESSOR_ALL },
816 { "nz", 0xa, PROCESSOR_ALL },
817 { "p", 0xc, PROCESSOR_ALL },
818 { "s", 0x4, PROCESSOR_ALL },
819#define COND_SA_NUM 0xd
820 { "sa", COND_SA_NUM, PROCESSOR_ALL },
821 { "t", 0x5, PROCESSOR_ALL },
822 { "v", 0x0, PROCESSOR_ALL },
823 { "z", 0x2, PROCESSOR_ALL },
252b5132 824};
252b5132 825
28e4f854
KH		 826#define CC_NAME_CNT \
827 (sizeof (cc_names) / sizeof (struct reg_name))
828
1cd986c5
NC		 829static const struct reg_name float_cc_names[] =
830{
78c8d46c
NC		 831 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */
832 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */
833 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */
834 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */
835 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */
836 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */
837 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */
838 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */
839 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */
840 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */
841 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */
842 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */
843 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */
844 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */
845 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */
846 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */
847 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */
848 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */
849 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */
850 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */
851 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */
852 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */
853 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */
854 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */
855 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */
856 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */
857 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */
858 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */
859 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */
860 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */
861 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */
862 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */
1cd986c5
NC		 863};
864
865#define FLOAT_CC_NAME_CNT \
866 (sizeof (float_cc_names) / sizeof (struct reg_name))
867
78c8d46c
NC		 868
869static const struct reg_name cacheop_names[] =
870{
871 { "cfald", 0x44, PROCESSOR_V850E3V5_UP },
872 { "cfali", 0x40, PROCESSOR_V850E3V5_UP },
873 { "chbid", 0x04, PROCESSOR_V850E3V5_UP },
874 { "chbii", 0x00, PROCESSOR_V850E3V5_UP },
875 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP },
876 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP },
877 { "cibid", 0x24, PROCESSOR_V850E3V5_UP },
878 { "cibii", 0x20, PROCESSOR_V850E3V5_UP },
879 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP },
880 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP },
881 { "cildd", 0x65, PROCESSOR_V850E3V5_UP },
882 { "cildi", 0x61, PROCESSOR_V850E3V5_UP },
883 { "cistd", 0x64, PROCESSOR_V850E3V5_UP },
884 { "cisti", 0x60, PROCESSOR_V850E3V5_UP },
885};
886
887#define CACHEOP_NAME_CNT \
888 (sizeof (cacheop_names) / sizeof (struct reg_name))
889
890static const struct reg_name prefop_names[] =
891{
892 { "prefd", 0x04, PROCESSOR_V850E3V5_UP },
893 { "prefi", 0x00, PROCESSOR_V850E3V5_UP },
894};
895
896#define PREFOP_NAME_CNT \
897 (sizeof (prefop_names) / sizeof (struct reg_name))
898
899static const struct reg_name vector_registers[] =
900{
901 { "vr0", 0, PROCESSOR_V850E3V5_UP },
902 { "vr1", 1, PROCESSOR_V850E3V5_UP },
903 { "vr10", 10, PROCESSOR_V850E3V5_UP },
904 { "vr11", 11, PROCESSOR_V850E3V5_UP },
905 { "vr12", 12, PROCESSOR_V850E3V5_UP },
906 { "vr13", 13, PROCESSOR_V850E3V5_UP },
907 { "vr14", 14, PROCESSOR_V850E3V5_UP },
908 { "vr15", 15, PROCESSOR_V850E3V5_UP },
909 { "vr16", 16, PROCESSOR_V850E3V5_UP },
910 { "vr17", 17, PROCESSOR_V850E3V5_UP },
911 { "vr18", 18, PROCESSOR_V850E3V5_UP },
912 { "vr19", 19, PROCESSOR_V850E3V5_UP },
913 { "vr2", 2, PROCESSOR_V850E3V5_UP },
914 { "vr20", 20, PROCESSOR_V850E3V5_UP },
915 { "vr21", 21, PROCESSOR_V850E3V5_UP },
916 { "vr22", 22, PROCESSOR_V850E3V5_UP },
917 { "vr23", 23, PROCESSOR_V850E3V5_UP },
918 { "vr24", 24, PROCESSOR_V850E3V5_UP },
919 { "vr25", 25, PROCESSOR_V850E3V5_UP },
920 { "vr26", 26, PROCESSOR_V850E3V5_UP },
921 { "vr27", 27, PROCESSOR_V850E3V5_UP },
922 { "vr28", 28, PROCESSOR_V850E3V5_UP },
923 { "vr29", 29, PROCESSOR_V850E3V5_UP },
924 { "vr3", 3, PROCESSOR_V850E3V5_UP },
925 { "vr30", 30, PROCESSOR_V850E3V5_UP },
926 { "vr31", 31, PROCESSOR_V850E3V5_UP },
927 { "vr4", 4, PROCESSOR_V850E3V5_UP },
928 { "vr5", 5, PROCESSOR_V850E3V5_UP },
929 { "vr6", 6, PROCESSOR_V850E3V5_UP },
930 { "vr7", 7, PROCESSOR_V850E3V5_UP },
931 { "vr8", 8, PROCESSOR_V850E3V5_UP },
932 { "vr9", 9, PROCESSOR_V850E3V5_UP },
933};
934
935#define VREG_NAME_CNT \
936 (sizeof (vector_registers) / sizeof (struct reg_name))
937
28e4f854
KH		 938/* Do a binary search of the given register table to see if NAME is a
939 valid regiter name. Return the register number from the array on
940 success, or -1 on failure. */
252b5132
RH		 941
942static int
ea1562b3
NC		 943reg_name_search (const struct reg_name *regs,
944 int regcount,
945 const char *name,
946 bfd_boolean accept_numbers)
252b5132
RH		 947{
948 int middle, low, high;
949 int cmp;
28e4f854 950 symbolS *symbolP;
252b5132
RH		 951
952 /* If the register name is a symbol, then evaluate it. */
953 if ((symbolP = symbol_find (name)) != NULL)
954 {
955 /* If the symbol is an alias for another name then use that.
956 If the symbol is an alias for a number, then return the number. */
a77f5182 957 if (symbol_equated_p (symbolP))
ea1562b3
NC		 958 name
959 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
252b5132
RH		 960 else if (accept_numbers)
961 {
962 int reg = S_GET_VALUE (symbolP);
1cd986c5 963 return reg;
252b5132
RH		 964 }
965
966 /* Otherwise drop through and try parsing name normally. */
967 }
28e4f854 968
252b5132
RH		 969 low = 0;
970 high = regcount - 1;
971
972 do
973 {
974 middle = (low + high) / 2;
975 cmp = strcasecmp (name, regs[middle].name);
976 if (cmp < 0)
977 high = middle - 1;
978 else if (cmp > 0)
979 low = middle + 1;
980 else
1cd986c5
NC		 981 return ((regs[middle].processors & processor_mask)
982 ? regs[middle].value
983 : -1);
252b5132
RH		 984 }
985 while (low <= high);
986 return -1;
987}
988
252b5132 989/* Summary of register_name().
ec178e1b 990
77c6dd37 991 in: Input_line_pointer points to 1st char of operand.
ec178e1b 992
77c6dd37
NC		 993 out: An expressionS.
994 The operand may have been a register: in this case, X_op == O_register,
995 X_add_number is set to the register number, and truth is returned.
996 Input_line_pointer->(next non-blank) char after operand, or is in
997 its original state. */
28e4f854 998
b34976b6 999static bfd_boolean
ea1562b3 1000register_name (expressionS *expressionP)
252b5132 1001{
28e4f854
KH		 1002 int reg_number;
1003 char *name;
1004 char *start;
1005 char c;
252b5132 1006
28e4f854 1007 /* Find the spelling of the operand. */
252b5132
RH		 1008 start = name = input_line_pointer;
1009
1010 c = get_symbol_end ();
1011
1012 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
1013 name, FALSE);
1014
28e4f854
KH		 1015 /* Put back the delimiting char. */
1016 *input_line_pointer = c;
1017
1cd986c5
NC		 1018 expressionP->X_add_symbol = NULL;
1019 expressionP->X_op_symbol = NULL;
1020
28e4f854
KH		 1021 /* Look to see if it's in the register table. */
1022 if (reg_number >= 0)
252b5132 1023 {
ec178e1b 1024 expressionP->X_op = O_register;
252b5132
RH		 1025 expressionP->X_add_number = reg_number;
1026
b34976b6 1027 return TRUE;
252b5132 1028 }
28e4f854 1029
1cd986c5
NC		 1030 /* Reset the line as if we had not done anything. */
1031 input_line_pointer = start;
1032
1033 expressionP->X_op = O_illegal;
1034
1035 return FALSE;
252b5132
RH		 1036}
1037
1038/* Summary of system_register_name().
ec178e1b 1039
77c6dd37 1040 in: INPUT_LINE_POINTER points to 1st char of operand.
ec178e1b
AM		 1041 EXPRESSIONP points to an expression structure to be filled in.
1042 ACCEPT_NUMBERS is true iff numerical register names may be used.
ec178e1b 1043
77c6dd37
NC		 1044 out: An expressionS structure in expressionP.
1045 The operand may have been a register: in this case, X_op == O_register,
1046 X_add_number is set to the register number, and truth is returned.
1047 Input_line_pointer->(next non-blank) char after operand, or is in
1048 its original state. */
28e4f854 1049
b34976b6 1050static bfd_boolean
ea1562b3 1051system_register_name (expressionS *expressionP,
1cd986c5 1052 bfd_boolean accept_numbers)
252b5132 1053{
28e4f854
KH		 1054 int reg_number;
1055 char *name;
1056 char *start;
1057 char c;
252b5132 1058
28e4f854 1059 /* Find the spelling of the operand. */
252b5132
RH		 1060 start = name = input_line_pointer;
1061
1062 c = get_symbol_end ();
1063 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name,
1064 accept_numbers);
1065
28e4f854
KH		 1066 /* Put back the delimiting char. */
1067 *input_line_pointer = c;
1068
252b5132
RH		 1069 if (reg_number < 0
1070 && accept_numbers)
1071 {
28e4f854
KH		 1072 /* Reset input_line pointer. */
1073 input_line_pointer = start;
252b5132 1074
3882b010 1075 if (ISDIGIT (*input_line_pointer))
252b5132 1076 {
1cd986c5 1077 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
252b5132
RH		 1078 }
1079 }
28e4f854 1080
1cd986c5
NC		 1081 expressionP->X_add_symbol = NULL;
1082 expressionP->X_op_symbol = NULL;
1083
28e4f854
KH		 1084 /* Look to see if it's in the register table. */
1085 if (reg_number >= 0)
252b5132 1086 {
ec178e1b 1087 expressionP->X_op = O_register;
252b5132
RH		 1088 expressionP->X_add_number = reg_number;
1089
b34976b6 1090 return TRUE;
252b5132 1091 }
28e4f854 1092
1cd986c5
NC		 1093 /* Reset the line as if we had not done anything. */
1094 input_line_pointer = start;
1095
1096 expressionP->X_op = O_illegal;
1097
1098 return FALSE;
252b5132
RH		 1099}
1100
1101/* Summary of cc_name().
ec178e1b 1102
77c6dd37 1103 in: INPUT_LINE_POINTER points to 1st char of operand.
ec178e1b 1104
77c6dd37
NC		 1105 out: An expressionS.
1106 The operand may have been a register: in this case, X_op == O_register,
1107 X_add_number is set to the register number, and truth is returned.
1108 Input_line_pointer->(next non-blank) char after operand, or is in
1109 its original state. */
28e4f854 1110
b34976b6 1111static bfd_boolean
1cd986c5
NC		 1112cc_name (expressionS *expressionP,
1113 bfd_boolean accept_numbers)
252b5132 1114{
28e4f854
KH		 1115 int reg_number;
1116 char *name;
1117 char *start;
1118 char c;
252b5132 1119
28e4f854 1120 /* Find the spelling of the operand. */
252b5132
RH		 1121 start = name = input_line_pointer;
1122
1123 c = get_symbol_end ();
1cd986c5 1124 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers);
252b5132 1125
28e4f854
KH		 1126 /* Put back the delimiting char. */
1127 *input_line_pointer = c;
1128
1cd986c5
NC		 1129 if (reg_number < 0
1130 && accept_numbers)
1131 {
1132 /* Reset input_line pointer. */
1133 input_line_pointer = start;
1134
1135 if (ISDIGIT (*input_line_pointer))
1136 {
1137 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1138 }
1139 }
1140
1141 expressionP->X_add_symbol = NULL;
1142 expressionP->X_op_symbol = NULL;
1143
28e4f854
KH		 1144 /* Look to see if it's in the register table. */
1145 if (reg_number >= 0)
252b5132 1146 {
ec178e1b 1147 expressionP->X_op = O_constant;
252b5132
RH		 1148 expressionP->X_add_number = reg_number;
1149
b34976b6 1150 return TRUE;
252b5132 1151 }
1cd986c5
NC		 1152
1153 /* Reset the line as if we had not done anything. */
1154 input_line_pointer = start;
1155
1156 expressionP->X_op = O_illegal;
1157 expressionP->X_add_number = 0;
1158
1159 return FALSE;
1160}
1161
1162static bfd_boolean
1163float_cc_name (expressionS *expressionP,
1164 bfd_boolean accept_numbers)
1165{
1166 int reg_number;
1167 char *name;
1168 char *start;
1169 char c;
1170
1171 /* Find the spelling of the operand. */
1172 start = name = input_line_pointer;
1173
1174 c = get_symbol_end ();
1175 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers);
1176
1177 /* Put back the delimiting char. */
1178 *input_line_pointer = c;
1179
1180 if (reg_number < 0
1181 && accept_numbers)
252b5132 1182 {
1cd986c5 1183 /* Reset input_line pointer. */
252b5132 1184 input_line_pointer = start;
28e4f854 1185
1cd986c5
NC		 1186 if (ISDIGIT (*input_line_pointer))
1187 {
1188 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1189 }
1190 }
1191
1192 expressionP->X_add_symbol = NULL;
1193 expressionP->X_op_symbol = NULL;
1194
1195 /* Look to see if it's in the register table. */
1196 if (reg_number >= 0)
1197 {
1198 expressionP->X_op = O_constant;
1199 expressionP->X_add_number = reg_number;
1200
1201 return TRUE;
252b5132 1202 }
1cd986c5
NC		 1203
1204 /* Reset the line as if we had not done anything. */
1205 input_line_pointer = start;
1206
1207 expressionP->X_op = O_illegal;
1208 expressionP->X_add_number = 0;
1209
1210 return FALSE;
252b5132
RH		 1211}
1212
78c8d46c
NC		 1213static bfd_boolean
1214cacheop_name (expressionS * expressionP,
1215 bfd_boolean accept_numbers)
1216{
1217 int reg_number;
1218 char *name;
1219 char *start;
1220 char c;
1221
1222 /* Find the spelling of the operand. */
1223 start = name = input_line_pointer;
1224
1225 c = get_symbol_end ();
1226 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers);
1227
1228 /* Put back the delimiting char. */
1229 *input_line_pointer = c;
1230
1231 if (reg_number < 0
1232 && accept_numbers)
1233 {
1234 /* Reset input_line pointer. */
1235 input_line_pointer = start;
1236
1237 if (ISDIGIT (*input_line_pointer))
1238 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1239 }
1240
1241 expressionP->X_add_symbol = NULL;
1242 expressionP->X_op_symbol = NULL;
1243
1244 /* Look to see if it's in the register table. */
1245 if (reg_number >= 0)
1246 {
1247 expressionP->X_op = O_constant;
1248 expressionP->X_add_number = reg_number;
1249
1250 return TRUE;
1251 }
1252
1253 /* Reset the line as if we had not done anything. */
1254 input_line_pointer = start;
1255
1256 expressionP->X_op = O_illegal;
1257 expressionP->X_add_number = 0;
1258
1259 return FALSE;
1260}
1261
1262static bfd_boolean
1263prefop_name (expressionS * expressionP,
1264 bfd_boolean accept_numbers)
1265{
1266 int reg_number;
1267 char *name;
1268 char *start;
1269 char c;
1270
1271 /* Find the spelling of the operand. */
1272 start = name = input_line_pointer;
1273
1274 c = get_symbol_end ();
1275 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers);
1276
1277 /* Put back the delimiting char. */
1278 *input_line_pointer = c;
1279
1280 if (reg_number < 0
1281 && accept_numbers)
1282 {
1283 /* Reset input_line pointer. */
1284 input_line_pointer = start;
1285
1286 if (ISDIGIT (*input_line_pointer))
1287 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1288 }
1289
1290 expressionP->X_add_symbol = NULL;
1291 expressionP->X_op_symbol = NULL;
1292
1293 /* Look to see if it's in the register table. */
1294 if (reg_number >= 0)
1295 {
1296 expressionP->X_op = O_constant;
1297 expressionP->X_add_number = reg_number;
1298
1299 return TRUE;
1300 }
1301
1302 /* Reset the line as if we had not done anything. */
1303 input_line_pointer = start;
1304
1305 expressionP->X_op = O_illegal;
1306 expressionP->X_add_number = 0;
1307
1308 return FALSE;
1309}
1310
1311static bfd_boolean
1312vector_register_name (expressionS *expressionP)
1313{
1314 int reg_number;
1315 char *name;
1316 char *start;
1317 char c;
1318
1319 /* Find the spelling of the operand. */
1320 start = name = input_line_pointer;
1321
1322 c = get_symbol_end ();
1323
1324 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT,
1325 name, FALSE);
1326
1327 /* Put back the delimiting char. */
1328 *input_line_pointer = c;
1329
1330 expressionP->X_add_symbol = NULL;
1331 expressionP->X_op_symbol = NULL;
1332
1333 /* Look to see if it's in the register table. */
1334 if (reg_number >= 0)
1335 {
1336 expressionP->X_op = O_register;
1337 expressionP->X_add_number = reg_number;
1338
1339 return TRUE;
1340 }
1341
1342 /* Reset the line as if we had not done anything. */
1343 input_line_pointer = start;
1344
1345 expressionP->X_op = O_illegal;
1346
1347 return FALSE;
1348}
1349
252b5132 1350static void
ea1562b3 1351skip_white_space (void)
252b5132 1352{
28e4f854
KH		 1353 while (*input_line_pointer == ' '
1354 || *input_line_pointer == '\t')
1355 ++input_line_pointer;
252b5132
RH		 1356}
1357
1358/* Summary of parse_register_list ().
ec178e1b 1359
77c6dd37 1360 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
ec178e1b
AM		 1361 INSN is the partially constructed instruction.
1362 OPERAND is the operand being inserted.
1363
77c6dd37 1364 out: NULL if the parse completed successfully, otherwise a
ec178e1b
AM		 1365 pointer to an error message is returned. If the parse
1366 completes the correct bit fields in the instruction
1367 will be filled in.
1368
77c6dd37 1369 Parses register lists with the syntax:
ec178e1b 1370
77c6dd37
NC		 1371 { rX }
1372 { rX, rY }
1373 { rX - rY }
1374 { rX - rY, rZ }
1375 etc
ec178e1b 1376
33b7f697 1377 and also parses constant expressions whoes bits indicate the
77c6dd37 1378 registers in the lists. The LSB in the expression refers to
33b7f697 1379 the lowest numbered permissible register in the register list,
77c6dd37
NC		 1380 and so on upwards. System registers are considered to be very
1381 high numbers. */
28e4f854 1382
252b5132 1383static char *
ea1562b3
NC		 1384parse_register_list (unsigned long *insn,
1385 const struct v850_operand *operand)
252b5132 1386{
ea1562b3
NC		 1387 static int type1_regs[32] =
1388 {
28e4f854
KH		 1389 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1390 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1391 };
1cd986c5 1392
28e4f854 1393 int *regs;
252b5132
RH		 1394 expressionS exp;
1395
28e4f854 1396 /* Select a register array to parse. */
252b5132
RH		 1397 switch (operand->shift)
1398 {
1399 case 0xffe00001: regs = type1_regs; break;
252b5132
RH		 1400 default:
1401 as_bad (_("unknown operand shift: %x\n"), operand->shift);
1402 return _("internal failure in parse_register_list");
1403 }
1404
1405 skip_white_space ();
1406
1407 /* If the expression starts with a curly brace it is a register list.
1408 Otherwise it is a constant expression, whoes bits indicate which
1409 registers are to be included in the list. */
28e4f854 1410 if (*input_line_pointer != '{')
252b5132 1411 {
252b5132
RH		 1412 int reg;
1413 int i;
28e4f854
KH		 1414
1415 expression (&exp);
1416
252b5132
RH		 1417 if (exp.X_op != O_constant)
1418 return _("constant expression or register list expected");
1419
1420 if (regs == type1_regs)
1421 {
1422 if (exp.X_add_number & 0xFFFFF000)
1423 return _("high bits set in register list expression");
28e4f854
KH		 1424
1425 for (reg = 20; reg < 32; reg++)
252b5132
RH		 1426 if (exp.X_add_number & (1 << (reg - 20)))
1427 {
1428 for (i = 0; i < 32; i++)
1429 if (regs[i] == reg)
28e4f854 1430 *insn |= (1 << i);
252b5132
RH		 1431 }
1432 }
252b5132
RH		 1433
1434 return NULL;
1435 }
1436
28e4f854 1437 input_line_pointer++;
252b5132
RH		 1438
1439 /* Parse the register list until a terminator (closing curly brace or
1440 new-line) is found. */
1441 for (;;)
1442 {
1cd986c5
NC		 1443 skip_white_space ();
1444
28e4f854 1445 if (register_name (&exp))
252b5132 1446 {
28e4f854
KH		 1447 int i;
1448
252b5132
RH		 1449 /* Locate the given register in the list, and if it is there,
1450 insert the corresponding bit into the instruction. */
1451 for (i = 0; i < 32; i++)
1452 {
28e4f854 1453 if (regs[i] == exp.X_add_number)
252b5132 1454 {
28e4f854 1455 *insn |= (1 << i);
252b5132
RH		 1456 break;
1457 }
1458 }
1459
1460 if (i == 32)
77c6dd37 1461 return _("illegal register included in list");
252b5132 1462 }
1cd986c5 1463 else if (system_register_name (&exp, TRUE))
252b5132
RH		 1464 {
1465 if (regs == type1_regs)
1466 {
1467 return _("system registers cannot be included in list");
1468 }
252b5132 1469 }
1cd986c5
NC		 1470
1471 if (*input_line_pointer == '}')
252b5132 1472 {
28e4f854 1473 input_line_pointer++;
252b5132
RH		 1474 break;
1475 }
28e4f854 1476 else if (*input_line_pointer == ',')
252b5132 1477 {
28e4f854 1478 input_line_pointer++;
252b5132
RH		 1479 continue;
1480 }
28e4f854 1481 else if (*input_line_pointer == '-')
252b5132 1482 {
28e4f854
KH		 1483 /* We have encountered a range of registers: rX - rY. */
1484 int j;
252b5132
RH		 1485 expressionS exp2;
1486
1487 /* Skip the dash. */
28e4f854 1488 ++input_line_pointer;
252b5132
RH		 1489
1490 /* Get the second register in the range. */
28e4f854 1491 if (! register_name (&exp2))
252b5132
RH		 1492 {
1493 return _("second register should follow dash in register list");
1cd986c5
NC		 1494 }
1495
1496 if (exp.X_add_number > exp2.X_add_number)
1497 {
5648d7c7 1498 return _("second register should be greater than first register");
252b5132
RH		 1499 }
1500
1501 /* Add the rest of the registers in the range. */
1502 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++)
1503 {
28e4f854
KH		 1504 int i;
1505
252b5132
RH		 1506 /* Locate the given register in the list, and if it is there,
1507 insert the corresponding bit into the instruction. */
1508 for (i = 0; i < 32; i++)
1509 {
28e4f854 1510 if (regs[i] == j)
252b5132 1511 {
28e4f854 1512 *insn |= (1 << i);
252b5132
RH		 1513 break;
1514 }
1515 }
1516
1517 if (i == 32)
1518 return _("illegal register included in list");
1519 }
1cd986c5
NC		 1520
1521 exp = exp2;
252b5132
RH		 1522 }
1523 else
77c6dd37 1524 break;
252b5132
RH		 1525 }
1526
1527 return NULL;
1528}
1529
5a38dc70 1530const char *md_shortopts = "m:";
252b5132 1531
ea1562b3
NC		 1532struct option md_longopts[] =
1533{
1cd986c5
NC		 1534#define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1535 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22},
1536#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1537 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
252b5132
RH		 1538 {NULL, no_argument, NULL, 0}
1539};
252b5132 1540
28e4f854 1541size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 1542
1543void
ea1562b3 1544md_show_usage (FILE *stream)
252b5132
RH		 1545{
1546 fprintf (stream, _(" V850 options:\n"));
1547 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1548 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1549 fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
1550 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
8ad30312 1551 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
1cd986c5
NC		 1552 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n"));
1553 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
78c8d46c
NC		 1554 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n"));
1555 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n"));
86aba9db 1556 fprintf (stream, _(" -mrelax Enable relaxation\n"));
1cd986c5
NC		 1557 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1558 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1559 fprintf (stream, _(" -mextension enable extension opcode support\n"));
1560 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1561 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
de863c74
NC		 1562 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n"));
1563 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n"));
1564 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n"));
1565 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n"));
252b5132
RH		 1566}
1567
1568int
ea1562b3 1569md_parse_option (int c, char *arg)
252b5132
RH		 1570{
1571 if (c != 'm')
1cd986c5
NC		 1572 {
1573 switch (c)
1574 {
1575 case OPTION_DISP_SIZE_DEFAULT_22:
1576 default_disp_size = 22;
1577 return 1;
1578
1579 case OPTION_DISP_SIZE_DEFAULT_32:
1580 default_disp_size = 32;
1581 return 1;
1582 }
1583 return 0;
1584 }
252b5132
RH		 1585
1586 if (strcmp (arg, "warn-signed-overflow") == 0)
329e276d
NC		 1587 warn_signed_overflows = TRUE;
1588
252b5132 1589 else if (strcmp (arg, "warn-unsigned-overflow") == 0)
329e276d
NC		 1590 warn_unsigned_overflows = TRUE;
1591
252b5132
RH		 1592 else if (strcmp (arg, "v850") == 0)
1593 {
1594 machine = 0;
1cd986c5 1595 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
252b5132
RH		 1596 }
1597 else if (strcmp (arg, "v850e") == 0)
1598 {
1599 machine = bfd_mach_v850e;
1cd986c5 1600 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
252b5132 1601 }
8ad30312
NC		 1602 else if (strcmp (arg, "v850e1") == 0)
1603 {
1604 machine = bfd_mach_v850e1;
1cd986c5 1605 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
8ad30312 1606 }
1cd986c5 1607 else if (strcmp (arg, "v850e2") == 0)
252b5132 1608 {
1cd986c5
NC		 1609 machine = bfd_mach_v850e2;
1610 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1611 }
1612 else if (strcmp (arg, "v850e2v3") == 0)
1613 {
1614 machine = bfd_mach_v850e2v3;
1615 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1616 }
78c8d46c
NC		 1617 else if (strcmp (arg, "v850e2v4") == 0)
1618 {
1619 machine = bfd_mach_v850e3v5;
1620 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1621 }
1622 else if (strcmp (arg, "v850e3v5") == 0)
1623 {
1624 machine = bfd_mach_v850e3v5;
1625 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1626 }
1cd986c5
NC		 1627 else if (strcmp (arg, "extension") == 0)
1628 {
5bb3703f 1629 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;
1cd986c5
NC		 1630 }
1631 else if (strcmp (arg, "no-bcond17") == 0)
1632 {
1633 no_bcond17 = 1;
1634 }
1635 else if (strcmp (arg, "no-stld23") == 0)
1636 {
1637 no_stld23 = 1;
252b5132 1638 }
86aba9db
NC		 1639 else if (strcmp (arg, "relax") == 0)
1640 v850_relax = 1;
de863c74
NC		 1641 else if (strcmp (arg, "gcc-abi") == 0)
1642 {
1643 v850_target_arch = bfd_arch_v850;
1644 v850_target_format = "elf32-v850";
1645 }
1646 else if (strcmp (arg, "rh850-abi") == 0)
1647 {
1648 v850_target_arch = bfd_arch_v850_rh850;
1649 v850_target_format = "elf32-v850-rh850";
1650 }
1651 else if (strcmp (arg, "8byte-align") == 0)
1652 v850_e_flags |= EF_RH850_DATA_ALIGN8;
1653 else if (strcmp (arg, "4byte-align") == 0)
1654 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8;
252b5132 1655 else
329e276d 1656 return 0;
28e4f854 1657
252b5132
RH		 1658 return 1;
1659}
1660
1661symbolS *
ea1562b3 1662md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 1663{
1664 return 0;
1665}
1666
1667char *
ea1562b3 1668md_atof (int type, char *litp, int *sizep)
252b5132 1669{
499ac353 1670 return ieee_md_atof (type, litp, sizep, FALSE);
252b5132
RH		 1671}
1672
252b5132 1673/* Very gross. */
28e4f854 1674
252b5132 1675void
ea1562b3
NC		 1676md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1677 asection *sec,
1678 fragS *fragP)
252b5132 1679{
8ad7c533
NC		 1680 union u
1681 {
1682 bfd_reloc_code_real_type fx_r_type;
1683 char * fr_opcode;
1684 }
1685 opcode_converter;
252b5132 1686 subseg_change (sec, 0);
28e4f854 1687
8ad7c533 1688 opcode_converter.fr_opcode = fragP->fr_opcode;
1cd986c5
NC		 1689
1690 subseg_change (sec, 0);
1691
78c8d46c
NC		 1692 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22)
1693 {
1694 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1695 fragP->fr_offset, 1,
1696 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1697 fragP->fr_fix += 4;
1698 }
1699 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1)
1700 {
1701 unsigned char * buffer =
1702 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1703 int loop_reg = (buffer[0] & 0x1f);
1704
1705 /* Add -1.reg. */
1706 md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2);
1707 /* Now create the conditional branch + fixup to the final target. */
1708 /* 0x000107ea = bne LBL(disp17). */
1709 md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4);
1710 fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol,
1711 fragP->fr_offset, 1,
1712 BFD_RELOC_V850_17_PCREL);
1713 fragP->fr_fix += 6;
1714 }
252b5132 1715 /* In range conditional or unconditional branch. */
78c8d46c 1716 else if (fragP->fr_subtype == SUBYPTE_COND_9_22
1cd986c5
NC		 1717 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
1718 || fragP->fr_subtype == SUBYPTE_COND_9_22_32
1719 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
1720 || fragP->fr_subtype == SUBYPTE_COND_9_17_22
1721 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32
1722 || fragP->fr_subtype == SUBYPTE_SA_9_22
1723 || fragP->fr_subtype == SUBYPTE_SA_9_22_32
1724 || fragP->fr_subtype == SUBYPTE_SA_9_17_22
1725 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32)
1726
252b5132
RH		 1727 {
1728 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
8ad7c533
NC		 1729 fragP->fr_offset, 1,
1730 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
252b5132
RH		 1731 fragP->fr_fix += 2;
1732 }
1cd986c5
NC		 1733 /* V850e2r-v3 17bit conditional branch. */
1734 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1
1735 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1
1736 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1
1737 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1)
1738 {
1739 unsigned char *buffer =
1740 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1741
1742 buffer[0] &= 0x0f; /* Use condition. */
1743 buffer[0] |= 0xe0;
1744 buffer[1] = 0x07;
1745
1746 /* Now create the unconditional branch + fixup to the final
1747 target. */
1748 md_number_to_chars ((char *) buffer + 2, 0x0001, 2);
1749 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1750 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL);
1751 fragP->fr_fix += 4;
1752 }
1753 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1754 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
1755 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
1756 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
1757 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
252b5132 1758 {
28e4f854 1759 unsigned char *buffer =
252b5132
RH		 1760 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1761
1762 /* Reverse the condition of the first branch. */
1763 buffer[0] ^= 0x08;
1764 /* Mask off all the displacement bits. */
1765 buffer[0] &= 0x8f;
1766 buffer[1] &= 0x07;
1767 /* Now set the displacement bits so that we branch
1768 around the unconditional branch. */
1769 buffer[0] |= 0x30;
1770
1771 /* Now create the unconditional branch + fixup to the final
1772 target. */
2132e3a3 1773 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
252b5132 1774 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
1cd986c5 1775 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
252b5132
RH		 1776 fragP->fr_fix += 6;
1777 }
1cd986c5
NC		 1778 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1779 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2
1780 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3)
1781 {
1782 unsigned char *buffer =
1783 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1784
1785 /* Reverse the condition of the first branch. */
1786 buffer[0] ^= 0x08;
1787 /* Mask off all the displacement bits. */
1788 buffer[0] &= 0x8f;
1789 buffer[1] &= 0x07;
1790 /* Now set the displacement bits so that we branch
1791 around the unconditional branch. */
1792 buffer[0] |= 0x40;
1793
1794 /* Now create the unconditional branch + fixup to the final
1795 target. */
1796 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2);
1797 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1798 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1799 fragP->fr_fix += 8;
1800 }
1801 /* Out of range unconditional branch. Emit a 22bit jump. */
1802 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1
1803 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1)
252b5132
RH		 1804 {
1805 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
1806 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1cd986c5 1807 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
252b5132
RH		 1808 fragP->fr_fix += 4;
1809 }
1cd986c5
NC		 1810 /* Out of range unconditional branch. Emit a 32bit jump. */
1811 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2)
1812 {
1813 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2);
1814 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1815 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1816 fragP->fr_fix += 6;
1817 }
1818 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1819 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1
1820 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1
1821 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2
1822 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2)
1823 {
1824 unsigned char *buffer =
1825 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1826
1827 /* bsa .+4 */
1828 buffer[0] &= 0x8f;
1829 buffer[0] |= 0x20;
1830 buffer[1] &= 0x07;
1831
1832 /* br .+6 */
1833 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2);
1834
1835 /* Now create the unconditional branch + fixup to the final
1836 target. */
1837 /* jr SYM */
1838 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4);
1839 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1840 fragP->fr_offset, 1,
1841 BFD_RELOC_V850_22_PCREL);
1842 fragP->fr_fix += 8;
1843 }
1844 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1845 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2
1846 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3)
1847 {
1848 unsigned char *buffer =
1849 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1850
1851 /* bsa .+2 */
1852 buffer[0] &= 0x8f;
1853 buffer[0] |= 0x20;
1854 buffer[1] &= 0x07;
1855
1856 /* br .+8 */
1857 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2);
1858
1859 /* Now create the unconditional branch + fixup to the final
1860 target. */
1861 /* jr SYM */
1862 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2);
1863 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol,
1864 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1865
1866 fragP->fr_fix += 10;
1867 }
252b5132
RH		 1868 else
1869 abort ();
1870}
1871
1872valueT
ea1562b3 1873md_section_align (asection *seg, valueT addr)
252b5132
RH		 1874{
1875 int align = bfd_get_section_alignment (stdoutput, seg);
1876 return ((addr + (1 << align) - 1) & (-1 << align));
1877}
1878
1879void
ea1562b3 1880md_begin (void)
252b5132 1881{
28e4f854 1882 char *prev_name = "";
86aba9db 1883 const struct v850_opcode *op;
28e4f854 1884
78c8d46c
NC		 1885 if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0)
1886 {
1887 if (machine == -1)
1888 machine = bfd_mach_v850e3v5;
1889
1890 if (!processor_mask)
1891 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1892 }
1893 else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0)
1894 {
1895 if (machine == -1)
1896 machine = bfd_mach_v850e3v5;
1897
1898 if (!processor_mask)
1899 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1900 }
1901 else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
1cd986c5
NC		 1902 {
1903 if (machine == -1)
1904 machine = bfd_mach_v850e2v3;
1905
1906 if (!processor_mask)
1907 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1908 }
1909 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0)
1910 {
1911 if (machine == -1)
1912 machine = bfd_mach_v850e2;
1913
1914 if (!processor_mask)
1915 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1916 }
1917 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
8ad30312
NC		 1918 {
1919 if (machine == -1)
1cd986c5 1920 machine = bfd_mach_v850e1;
8ad30312 1921
1cd986c5
NC		 1922 if (!processor_mask)
1923 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
8ad30312
NC		 1924 }
1925 else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
252b5132
RH		 1926 {
1927 if (machine == -1)
28e4f854
KH		 1928 machine = bfd_mach_v850e;
1929
1cd986c5
NC		 1930 if (!processor_mask)
1931 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
252b5132 1932 }
28e4f854 1933 else if (strncmp (TARGET_CPU, "v850", 4) == 0)
252b5132
RH		 1934 {
1935 if (machine == -1)
28e4f854
KH		 1936 machine = 0;
1937
1cd986c5
NC		 1938 if (!processor_mask)
1939 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
252b5132
RH		 1940 }
1941 else
28e4f854
KH		 1942 /* xgettext:c-format */
1943 as_bad (_("Unable to determine default target processor from string: %s"),
ec178e1b 1944 TARGET_CPU);
252b5132 1945
19d63e5d 1946 v850_hash = hash_new ();
252b5132
RH		 1947
1948 /* Insert unique names into hash table. The V850 instruction set
1949 has many identical opcode names that have different opcodes based
1950 on the operands. This hash table then provides a quick index to
1951 the first opcode with a particular name in the opcode table. */
252b5132
RH		 1952 op = v850_opcodes;
1953 while (op->name)
1954 {
28e4f854 1955 if (strcmp (prev_name, op->name))
252b5132
RH		 1956 {
1957 prev_name = (char *) op->name;
1958 hash_insert (v850_hash, op->name, (char *) op);
1959 }
1960 op++;
1961 }
1962
9e0665bc 1963 v850_seg_table[BSS_SECTION].s = bss_section;
de863c74
NC		 1964 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
1965 bfd_set_private_flags (stdoutput, v850_e_flags);
252b5132
RH		 1966}
1967
1cd986c5 1968
1e50d24d 1969static bfd_reloc_code_real_type
1cd986c5 1970handle_hi016 (const struct v850_operand *operand, const char **errmsg)
1e50d24d 1971{
1cd986c5
NC		 1972 if (operand == NULL)
1973 return BFD_RELOC_HI16;
1e50d24d 1974
1cd986c5
NC		 1975 if (operand->default_reloc == BFD_RELOC_HI16)
1976 return BFD_RELOC_HI16;
1977
1978 if (operand->default_reloc == BFD_RELOC_HI16_S)
1979 return BFD_RELOC_HI16;
1980
1981 if (operand->default_reloc == BFD_RELOC_16)
1982 return BFD_RELOC_HI16;
1983
1984 *errmsg = _("hi0() relocation used on an instruction which does "
1985 "not support it");
1986 return BFD_RELOC_64; /* Used to indicate an error condition. */
1e50d24d
RS		 1987}
1988
252b5132 1989static bfd_reloc_code_real_type
1cd986c5 1990handle_hi16 (const struct v850_operand *operand, const char **errmsg)
252b5132
RH		 1991{
1992 if (operand == NULL)
1cd986c5 1993 return BFD_RELOC_HI16_S;
252b5132 1994
1cd986c5
NC		 1995 if (operand->default_reloc == BFD_RELOC_HI16_S)
1996 return BFD_RELOC_HI16_S;
1997
1998 if (operand->default_reloc == BFD_RELOC_HI16)
1999 return BFD_RELOC_HI16_S;
2000
2001 if (operand->default_reloc == BFD_RELOC_16)
2002 return BFD_RELOC_HI16_S;
28e4f854 2003
1cd986c5
NC		 2004 *errmsg = _("hi() relocation used on an instruction which does "
2005 "not support it");
2006 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2007}
2008
2009static bfd_reloc_code_real_type
1cd986c5 2010handle_lo16 (const struct v850_operand *operand, const char **errmsg)
252b5132 2011{
28e4f854 2012 if (operand == NULL)
1cd986c5 2013 return BFD_RELOC_LO16;
28e4f854 2014
1cd986c5
NC		 2015 if (operand->default_reloc == BFD_RELOC_LO16)
2016 return BFD_RELOC_LO16;
28e4f854 2017
1cd986c5
NC		 2018 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2019 return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
28e4f854 2020
1cd986c5
NC		 2021 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2022 return BFD_RELOC_V850_LO16_S1;
2023
2024 if (operand->default_reloc == BFD_RELOC_16)
2025 return BFD_RELOC_LO16;
28e4f854 2026
1cd986c5
NC		 2027 *errmsg = _("lo() relocation used on an instruction which does "
2028 "not support it");
2029 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2030}
2031
2032static bfd_reloc_code_real_type
1cd986c5 2033handle_ctoff (const struct v850_operand *operand, const char **errmsg)
252b5132 2034{
28e4f854 2035 if (operand == NULL)
1cd986c5 2036 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
28e4f854 2037
1cd986c5
NC		 2038 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET)
2039 return operand->default_reloc;
252b5132 2040
1cd986c5
NC		 2041 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2042 return BFD_RELOC_V850_CALLT_15_16_OFFSET;
28e4f854 2043
1cd986c5
NC		 2044 if (operand->default_reloc == BFD_RELOC_16)
2045 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
28e4f854 2046
1cd986c5
NC		 2047 *errmsg = _("ctoff() relocation used on an instruction which does not support it");
2048 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2049}
2050
2051static bfd_reloc_code_real_type
1cd986c5 2052handle_sdaoff (const struct v850_operand *operand, const char **errmsg)
252b5132 2053{
28e4f854 2054 if (operand == NULL)
1cd986c5 2055 return BFD_RELOC_V850_SDA_16_16_OFFSET;
28e4f854 2056
1cd986c5
NC		 2057 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2058 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET;
28e4f854 2059
1cd986c5
NC		 2060 if (operand->default_reloc == BFD_RELOC_16)
2061 return BFD_RELOC_V850_SDA_16_16_OFFSET;
28e4f854 2062
1cd986c5
NC		 2063 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2064 return BFD_RELOC_V850_SDA_15_16_OFFSET;
28e4f854 2065
1cd986c5
NC		 2066 *errmsg = _("sdaoff() relocation used on an instruction which does not support it");
2067 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2068}
2069
252b5132 2070static bfd_reloc_code_real_type
1cd986c5 2071handle_zdaoff (const struct v850_operand *operand, const char **errmsg)
252b5132 2072{
1cd986c5
NC		 2073 if (operand == NULL)
2074 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
252b5132 2075
1cd986c5
NC		 2076 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2077 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET;
252b5132 2078
1cd986c5
NC		 2079 if (operand->default_reloc == BFD_RELOC_16)
2080 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
2081
2082 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2083 return BFD_RELOC_V850_ZDA_15_16_OFFSET;
2084
2085 *errmsg = _("zdaoff() relocation used on an instruction which does not support it");
2086 return BFD_RELOC_64; /* Used to indicate an error condition. */
2087}
2088
2089static bfd_reloc_code_real_type
2090handle_tdaoff (const struct v850_operand *operand, const char **errmsg)
2091{
2092 if (operand == NULL)
2093 /* Data item, not an instruction. */
2094 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2095
2096 switch (operand->default_reloc)
2097 {
2098 /* sld.hu, operand: D5-4. */
2099 case BFD_RELOC_V850_TDA_4_5_OFFSET:
2100 /* sld.bu, operand: D4. */
2101 case BFD_RELOC_V850_TDA_4_4_OFFSET:
2102 /* sld.w/sst.w, operand: D8_6. */
2103 case BFD_RELOC_V850_TDA_6_8_OFFSET:
2104 /* sld.h/sst.h, operand: D8_7. */
2105 case BFD_RELOC_V850_TDA_7_8_OFFSET:
2106 /* sld.b/sst.b, operand: D7. */
2107 case BFD_RELOC_V850_TDA_7_7_OFFSET:
2108 return operand->default_reloc;
2109 default:
2110 break;
2111 }
2112
2113 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16)
2114 /* set1 & chums, operands: D16. */
2115 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2116
2117 *errmsg = _("tdaoff() relocation used on an instruction which does not support it");
2118 /* Used to indicate an error condition. */
2119 return BFD_RELOC_64;
2120}
2121
2122/* Warning: The code in this function relies upon the definitions
2123 in the v850_operands[] array (defined in opcodes/v850-opc.c)
2124 matching the hard coded values contained herein. */
2125
2126static bfd_reloc_code_real_type
2127v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
2128{
2129 bfd_boolean paren_skipped = FALSE;
2130
2131 /* Skip leading opening parenthesis. */
2132 if (*input_line_pointer == '(')
2133 {
2134 ++input_line_pointer;
2135 paren_skipped = TRUE;
2136 }
2137
2138#define CHECK_(name, reloc) \
ec266e19 2139 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
252b5132
RH		 2140 { \
2141 input_line_pointer += strlen (name); \
2142 return reloc; \
2143 }
28e4f854 2144
1cd986c5
NC		 2145 CHECK_ ("hi0", handle_hi016(operand, errmsg) );
2146 CHECK_ ("hi", handle_hi16(operand, errmsg) );
2147 CHECK_ ("lo", handle_lo16 (operand, errmsg) );
2148 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg));
2149 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg));
2150 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg));
2151 CHECK_ ("hilo", BFD_RELOC_32);
2152 CHECK_ ("lo23", BFD_RELOC_V850_23);
2153 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) );
28e4f854 2154
252b5132
RH		 2155 /* Restore skipped parenthesis. */
2156 if (paren_skipped)
28e4f854
KH		 2157 --input_line_pointer;
2158
252b5132
RH		 2159 return BFD_RELOC_UNUSED;
2160}
2161
2162/* Insert an operand value into an instruction. */
2163
2164static unsigned long
ea1562b3
NC		 2165v850_insert_operand (unsigned long insn,
2166 const struct v850_operand *operand,
2167 offsetT val,
1cd986c5 2168 const char **errmsg)
252b5132
RH		 2169{
2170 if (operand->insert)
2171 {
28e4f854
KH		 2172 const char *message = NULL;
2173
2174 insn = operand->insert (insn, val, &message);
252b5132
RH		 2175 if (message != NULL)
2176 {
2177 if ((operand->flags & V850_OPERAND_SIGNED)
2178 && ! warn_signed_overflows
1cd986c5 2179 && v850_msg_is_out_of_range (message))
252b5132 2180 {
28e4f854 2181 /* Skip warning... */
252b5132
RH		 2182 }
2183 else if ((operand->flags & V850_OPERAND_SIGNED) == 0
2184 && ! warn_unsigned_overflows
1cd986c5 2185 && v850_msg_is_out_of_range (message))
252b5132 2186 {
28e4f854 2187 /* Skip warning... */
252b5132 2188 }
252b5132
RH		 2189 else
2190 {
1cd986c5
NC		 2191 if (errmsg != NULL)
2192 *errmsg = message;
252b5132
RH		 2193 }
2194 }
2195 }
1cd986c5
NC		 2196 else if (operand->bits == -1
2197 || operand->flags & V850E_IMMEDIATE16
2198 || operand->flags & V850E_IMMEDIATE23
2199 || operand->flags & V850E_IMMEDIATE32)
2200 {
2201 abort ();
2202 }
252b5132
RH		 2203 else
2204 {
1cd986c5 2205 if (operand->bits < 32)
252b5132 2206 {
28e4f854 2207 long min, max;
252b5132
RH		 2208
2209 if ((operand->flags & V850_OPERAND_SIGNED) != 0)
2210 {
2211 if (! warn_signed_overflows)
2212 max = (1 << operand->bits) - 1;
2213 else
2214 max = (1 << (operand->bits - 1)) - 1;
28e4f854
KH		 2215
2216 min = -(1 << (operand->bits - 1));
252b5132
RH		 2217 }
2218 else
2219 {
2220 max = (1 << operand->bits) - 1;
28e4f854 2221
252b5132 2222 if (! warn_unsigned_overflows)
28e4f854 2223 min = -(1 << (operand->bits - 1));
252b5132
RH		 2224 else
2225 min = 0;
2226 }
28e4f854 2227
dc86b458
SB		 2228 /* Some people write constants with the sign extension done by
2229 hand but only up to 32 bits. This shouldn't really be valid,
2230 but, to permit this code to assemble on a 64-bit host, we
2231 sign extend the 32-bit value to 64 bits if so doing makes the
2232 value valid. */
2233 if (val > max
2234 && (offsetT) (val - 0x80000000 - 0x80000000) >= min
2235 && (offsetT) (val - 0x80000000 - 0x80000000) <= max)
2236 val = val - 0x80000000 - 0x80000000;
2237
2238 /* Similarly, people write expressions like ~(1<<15), and expect
2239 this to be OK for a 32-bit unsigned value. */
2240 else if (val < min
2241 && (offsetT) (val + 0x80000000 + 0x80000000) >= min
2242 && (offsetT) (val + 0x80000000 + 0x80000000) <= max)
2243 val = val + 0x80000000 + 0x80000000;
2244
2245 else if (val < (offsetT) min || val > (offsetT) max)
252b5132 2246 {
04ee5257 2247 static char buf [128];
28e4f854 2248
252b5132
RH		 2249 /* Restore min and mix to expected values for decimal ranges. */
2250 if ((operand->flags & V850_OPERAND_SIGNED)
2251 && ! warn_signed_overflows)
2252 max = (1 << (operand->bits - 1)) - 1;
2253
2254 if (! (operand->flags & V850_OPERAND_SIGNED)
2255 && ! warn_unsigned_overflows)
2256 min = 0;
2257
1cd986c5
NC		 2258 sprintf (buf, _("operand out of range (%d is not between %d and %d)"),
2259 (int) val, (int) min, (int) max);
2260 *errmsg = buf;
252b5132 2261 }
252b5132 2262
1cd986c5
NC		 2263 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
2264 }
2265 else
2266 {
2267 insn |= (((long) val) << operand->shift);
2268 }
252b5132 2269 }
28e4f854 2270
252b5132
RH		 2271 return insn;
2272}
252b5132 2273\f
28e4f854 2274static char copy_of_instruction[128];
252b5132
RH		 2275
2276void
ea1562b3 2277md_assemble (char *str)
252b5132 2278{
28e4f854
KH		 2279 char *s;
2280 char *start_of_operands;
2281 struct v850_opcode *opcode;
2282 struct v850_opcode *next_opcode;
2283 const unsigned char *opindex_ptr;
2284 int next_opindex;
2285 int relaxable = 0;
2286 unsigned long insn;
2287 unsigned long insn_size;
de863c74 2288 char *f = NULL;
28e4f854
KH		 2289 int i;
2290 int match;
b34976b6 2291 bfd_boolean extra_data_after_insn = FALSE;
28e4f854
KH		 2292 unsigned extra_data_len = 0;
2293 unsigned long extra_data = 0;
2294 char *saved_input_line_pointer;
1cd986c5
NC		 2295 char most_match_errmsg[1024];
2296 int most_match_count = -1;
28e4f854 2297
252b5132 2298 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1);
1cd986c5 2299 most_match_errmsg[0] = 0;
28e4f854 2300
252b5132 2301 /* Get the opcode. */
3882b010 2302 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
252b5132 2303 continue;
28e4f854 2304
252b5132
RH		 2305 if (*s != '\0')
2306 *s++ = '\0';
2307
28e4f854 2308 /* Find the first opcode with the proper name. */
252b5132
RH		 2309 opcode = (struct v850_opcode *) hash_find (v850_hash, str);
2310 if (opcode == NULL)
2311 {
28e4f854 2312 /* xgettext:c-format */
252b5132
RH		 2313 as_bad (_("Unrecognized opcode: `%s'"), str);
2314 ignore_rest_of_line ();
2315 return;
2316 }
2317
2318 str = s;
3882b010 2319 while (ISSPACE (*str))
28e4f854 2320 ++str;
252b5132
RH		 2321
2322 start_of_operands = str;
2323
2324 saved_input_line_pointer = input_line_pointer;
28e4f854 2325
252b5132
RH		 2326 for (;;)
2327 {
28e4f854 2328 const char *errmsg = NULL;
1cd986c5 2329 const char *warningmsg = NULL;
252b5132
RH		 2330
2331 match = 0;
1cd986c5 2332 opindex_ptr = opcode->operands;
28e4f854 2333
1cd986c5
NC		 2334 if (no_stld23)
2335 {
2336 if ((strncmp (opcode->name, "st.", 3) == 0
2337 && v850_operands[opcode->operands[1]].bits == 23)
2338 || (strncmp (opcode->name, "ld.", 3) == 0
2339 && v850_operands[opcode->operands[0]].bits == 23))
2340 {
2341 errmsg = _("st/ld offset 23 instruction was disabled .");
2342 goto error;
2343 }
2344 }
2345
2346 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0
2347 || (((opcode->processors & ~PROCESSOR_MASK) != 0)
2348 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0)))
252b5132
RH		 2349 {
2350 errmsg = _("Target processor does not support this instruction.");
2351 goto error;
2352 }
28e4f854 2353
252b5132
RH		 2354 relaxable = 0;
2355 fc = 0;
2356 next_opindex = 0;
2357 insn = opcode->opcode;
1cd986c5 2358 extra_data_len = 0;
b34976b6 2359 extra_data_after_insn = FALSE;
252b5132
RH		 2360
2361 input_line_pointer = str = start_of_operands;
2362
28e4f854 2363 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
252b5132 2364 {
28e4f854
KH		 2365 const struct v850_operand *operand;
2366 char *hold;
2367 expressionS ex;
2368 bfd_reloc_code_real_type reloc;
252b5132
RH		 2369
2370 if (next_opindex == 0)
ea1562b3 2371 operand = &v850_operands[*opindex_ptr];
252b5132
RH		 2372 else
2373 {
28e4f854 2374 operand = &v850_operands[next_opindex];
252b5132
RH		 2375 next_opindex = 0;
2376 }
2377
2378 errmsg = NULL;
2379
1cd986c5
NC		 2380 while (*str == ' ')
2381 ++str;
2382
2383 if (operand->flags & V850_OPERAND_BANG
2384 && *str == '!')
2385 ++str;
2386 else if (operand->flags & V850_OPERAND_PERCENT
2387 && *str == '%')
2388 ++str;
2389
2390 if (*str == ',' || *str == '[' || *str == ']')
2391 ++str;
2392
2393 while (*str == ' ')
28e4f854 2394 ++str;
252b5132 2395
78c8d46c
NC		 2396 if ( (strcmp (opcode->name, "pushsp") == 0
2397 || strcmp (opcode->name, "popsp") == 0
2398 || strcmp (opcode->name, "dbpush") == 0)
2399 && (*str == '-'))
2400 ++str;
2401
252b5132
RH		 2402 if (operand->flags & V850_OPERAND_RELAX)
2403 relaxable = 1;
2404
28e4f854 2405 /* Gather the operand. */
252b5132
RH		 2406 hold = input_line_pointer;
2407 input_line_pointer = str;
28e4f854
KH		 2408
2409 /* lo(), hi(), hi0(), etc... */
1cd986c5 2410 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_UNUSED)
252b5132
RH		 2411 {
2412 /* This is a fake reloc, used to indicate an error condition. */
2413 if (reloc == BFD_RELOC_64)
2414 {
1cd986c5 2415 /* match = 1; */
252b5132
RH		 2416 goto error;
2417 }
28e4f854
KH		 2418
2419 expression (&ex);
252b5132
RH		 2420
2421 if (ex.X_op == O_constant)
2422 {
2423 switch (reloc)
2424 {
2425 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
1cd986c5
NC		 2426 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
2427 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
252b5132
RH		 2428 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2429 and the like. */
2430 /* Fall through. */
28e4f854 2431
252b5132 2432 case BFD_RELOC_LO16:
1cd986c5 2433 case BFD_RELOC_V850_LO16_S1:
1e50d24d 2434 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
252b5132
RH		 2435 {
2436 /* Truncate, then sign extend the value. */
2437 ex.X_add_number = SEXT16 (ex.X_add_number);
2438 break;
2439 }
2440
2441 case BFD_RELOC_HI16:
2442 {
2443 /* Truncate, then sign extend the value. */
2444 ex.X_add_number = SEXT16 (ex.X_add_number >> 16);
2445 break;
2446 }
2447
2448 case BFD_RELOC_HI16_S:
2449 {
2450 /* Truncate, then sign extend the value. */
28e4f854 2451 int temp = (ex.X_add_number >> 16) & 0xffff;
252b5132
RH		 2452
2453 temp += (ex.X_add_number >> 15) & 1;
2454
2455 ex.X_add_number = SEXT16 (temp);
2456 break;
2457 }
28e4f854 2458
1cd986c5
NC		 2459 case BFD_RELOC_V850_23:
2460 if ((operand->flags & V850E_IMMEDIATE23) == 0)
2461 {
2462 errmsg = _("immediate operand is too large");
2463 goto error;
2464 }
2465 break;
2466
252b5132 2467 case BFD_RELOC_32:
1cd986c5
NC		 2468 case BFD_RELOC_V850_32_ABS:
2469 case BFD_RELOC_V850_32_PCREL:
252b5132
RH		 2470 if ((operand->flags & V850E_IMMEDIATE32) == 0)
2471 {
2472 errmsg = _("immediate operand is too large");
2473 goto error;
2474 }
28e4f854 2475
252b5132 2476 break;
28e4f854 2477
252b5132 2478 default:
78c8d46c 2479 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc);
252b5132
RH		 2480 break;
2481 }
2482
1cd986c5
NC		 2483 if (operand->flags & V850E_IMMEDIATE32)
2484 {
2485 extra_data_after_insn = TRUE;
2486 extra_data_len = 4;
2487 extra_data = 0;
2488 }
2489 else if (operand->flags & V850E_IMMEDIATE23)
2490 {
2491 if (reloc != BFD_RELOC_V850_23)
2492 {
2493 errmsg = _("immediate operand is too large");
2494 goto error;
2495 }
2496 extra_data_after_insn = TRUE;
2497 extra_data_len = 2;
2498 extra_data = 0;
2499 }
2500 else if ((operand->flags & V850E_IMMEDIATE16)
2501 || (operand->flags & V850E_IMMEDIATE16HI))
2502 {
2503 if (operand->flags & V850E_IMMEDIATE16HI
2504 && reloc != BFD_RELOC_HI16
2505 && reloc != BFD_RELOC_HI16_S)
2506 {
2507 errmsg = _("immediate operand is too large");
2508 goto error;
2509 }
2510 else if (operand->flags & V850E_IMMEDIATE16
2511 && reloc != BFD_RELOC_LO16)
2512 {
2513 errmsg = _("immediate operand is too large");
2514 goto error;
2515 }
2516
2517 extra_data_after_insn = TRUE;
2518 extra_data_len = 2;
2519 extra_data = 0;
2520 }
2521
252b5132
RH		 2522 if (fc > MAX_INSN_FIXUPS)
2523 as_fatal (_("too many fixups"));
28e4f854
KH		 2524
2525 fixups[fc].exp = ex;
2526 fixups[fc].opindex = *opindex_ptr;
2527 fixups[fc].reloc = reloc;
252b5132
RH		 2528 fc++;
2529 }
1cd986c5 2530 else /* ex.X_op != O_constant. */
252b5132 2531 {
1cd986c5
NC		 2532 if ((reloc == BFD_RELOC_32
2533 || reloc == BFD_RELOC_V850_32_ABS
2534 || reloc == BFD_RELOC_V850_32_PCREL)
2535 && operand->bits < 32)
252b5132 2536 {
1cd986c5
NC		 2537 errmsg = _("immediate operand is too large");
2538 goto error;
2539 }
2540 else if (reloc == BFD_RELOC_V850_23
2541 && (operand->flags & V850E_IMMEDIATE23) == 0)
2542 {
2543 errmsg = _("immediate operand is too large");
2544 goto error;
2545 }
2546 else if ((reloc == BFD_RELOC_HI16
2547 || reloc == BFD_RELOC_HI16_S)
2548 && operand->bits < 16)
2549 {
2550 errmsg = _("immediate operand is too large");
2551 goto error;
2552 }
2553
2554 if (operand->flags & V850E_IMMEDIATE32)
2555 {
2556 extra_data_after_insn = TRUE;
2557 extra_data_len = 4;
2558 extra_data = 0;
2559 }
2560 else if (operand->flags & V850E_IMMEDIATE23)
2561 {
2562 if (reloc != BFD_RELOC_V850_23)
2563 {
2564 errmsg = _("immediate operand is too large");
2565 goto error;
2566 }
2567 extra_data_after_insn = TRUE;
2568 extra_data_len = 2;
2569 extra_data = 0;
2570 }
2571 else if ((operand->flags & V850E_IMMEDIATE16)
2572 || (operand->flags & V850E_IMMEDIATE16HI))
2573 {
2574 if (operand->flags & V850E_IMMEDIATE16HI
2575 && reloc != BFD_RELOC_HI16
2576 && reloc != BFD_RELOC_HI16_S)
2577 {
2578 errmsg = _("immediate operand is too large");
2579 goto error;
2580 }
2581 else if (operand->flags & V850E_IMMEDIATE16
2582 && reloc != BFD_RELOC_LO16)
252b5132
RH		 2583 {
2584 errmsg = _("immediate operand is too large");
2585 goto error;
2586 }
28e4f854 2587
b34976b6 2588 extra_data_after_insn = TRUE;
1cd986c5
NC		 2589 extra_data_len = 2;
2590 extra_data = 0;
252b5132 2591 }
28e4f854 2592
252b5132
RH		 2593 if (fc > MAX_INSN_FIXUPS)
2594 as_fatal (_("too many fixups"));
2595
28e4f854
KH		 2596 fixups[fc].exp = ex;
2597 fixups[fc].opindex = *opindex_ptr;
2598 fixups[fc].reloc = reloc;
252b5132
RH		 2599 fc++;
2600 }
2601 }
1cd986c5
NC		 2602 else if (operand->flags & V850E_IMMEDIATE16
2603 || operand->flags & V850E_IMMEDIATE16HI)
2604 {
2605 expression (&ex);
2606
2607 switch (ex.X_op)
2608 {
2609 case O_constant:
2610 if (operand->flags & V850E_IMMEDIATE16HI)
2611 {
2612 if (ex.X_add_number & 0xffff)
2613 {
2614 errmsg = _("constant too big to fit into instruction");
2615 goto error;
2616 }
2617
2618 ex.X_add_number >>= 16;
2619 }
2620 if (operand->flags & V850E_IMMEDIATE16)
2621 {
78c8d46c
NC		 2622 if ((ex.X_add_number & 0xffff8000)
2623 && ((ex.X_add_number & 0xffff8000) != 0xffff8000))
1cd986c5
NC		 2624 {
2625 errmsg = _("constant too big to fit into instruction");
2626 goto error;
2627 }
2628 }
2629 break;
2630
2631 case O_illegal:
2632 errmsg = _("illegal operand");
2633 goto error;
2634
2635 case O_absent:
2636 errmsg = _("missing operand");
2637 goto error;
2638
2639 default:
2640 if (fc >= MAX_INSN_FIXUPS)
2641 as_fatal (_("too many fixups"));
2642
2643 fixups[fc].exp = ex;
2644 fixups[fc].opindex = *opindex_ptr;
2645 fixups[fc].reloc = operand->default_reloc;
2646 ++fc;
2647
2648 ex.X_add_number = 0;
2649 break;
2650 }
2651
2652 extra_data_after_insn = TRUE;
2653 extra_data_len = 2;
2654 extra_data = ex.X_add_number;
2655 }
2656 else if (operand->flags & V850E_IMMEDIATE23)
2657 {
2658 expression (&ex);
2659
2660 switch (ex.X_op)
2661 {
2662 case O_constant:
2663 break;
2664
2665 case O_illegal:
2666 errmsg = _("illegal operand");
2667 goto error;
2668
2669 case O_absent:
2670 errmsg = _("missing operand");
2671 goto error;
2672
2673 default:
2674 break;
2675 }
2676
2677 if (fc >= MAX_INSN_FIXUPS)
2678 as_fatal (_("too many fixups"));
2679
2680 fixups[fc].exp = ex;
2681 fixups[fc].opindex = *opindex_ptr;
2682 fixups[fc].reloc = operand->default_reloc;
2683 ++fc;
2684
2685 extra_data_after_insn = TRUE;
2686 extra_data_len = 2;
2687 extra_data = 0;
2688 }
2689 else if (operand->flags & V850E_IMMEDIATE32)
2690 {
2691 expression (&ex);
2692
2693 switch (ex.X_op)
2694 {
2695 case O_constant:
2696 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS
2697 || operand->default_reloc == BFD_RELOC_V850_32_PCREL)
2698 && (ex.X_add_number & 1))
2699 {
2700 errmsg = _("odd number cannot be used here");
2701 goto error;
2702 }
2703 break;
2704
2705 case O_illegal:
2706 errmsg = _("illegal operand");
2707 goto error;
2708
2709 case O_absent:
2710 errmsg = _("missing operand");
2711 goto error;
2712
2713 default:
2714 if (fc >= MAX_INSN_FIXUPS)
2715 as_fatal (_("too many fixups"));
2716
2717 fixups[fc].exp = ex;
2718 fixups[fc].opindex = *opindex_ptr;
2719 fixups[fc].reloc = operand->default_reloc;
2720 ++fc;
2721
2722 ex.X_add_number = 0;
2723 break;
2724 }
2725
2726 extra_data_after_insn = TRUE;
2727 extra_data_len = 4;
2728 extra_data = ex.X_add_number;
2729 }
2730 else if (operand->flags & V850E_OPERAND_REG_LIST)
2731 {
2732 errmsg = parse_register_list (&insn, operand);
2733
2734 if (errmsg)
2735 goto error;
2736 }
252b5132
RH		 2737 else
2738 {
2739 errmsg = NULL;
28e4f854
KH		 2740
2741 if ((operand->flags & V850_OPERAND_REG) != 0)
252b5132 2742 {
28e4f854 2743 if (!register_name (&ex))
1cd986c5
NC		 2744 {
2745 errmsg = _("invalid register name");
2746 }
2747
2748 if ((operand->flags & V850_NOT_R0)
28e4f854 2749 && ex.X_add_number == 0)
252b5132
RH		 2750 {
2751 errmsg = _("register r0 cannot be used here");
1cd986c5 2752 }
28e4f854 2753
1cd986c5
NC		 2754 if (operand->flags & V850_REG_EVEN)
2755 {
2756 if (ex.X_add_number % 2)
2757 errmsg = _("odd register cannot be used here");
2758 ex.X_add_number = ex.X_add_number / 2;
252b5132 2759 }
1cd986c5 2760
252b5132 2761 }
28e4f854 2762 else if ((operand->flags & V850_OPERAND_SRG) != 0)
252b5132 2763 {
1cd986c5
NC		 2764 if (!system_register_name (&ex, TRUE))
2765 {
2766 errmsg = _("invalid system register name");
2767 }
252b5132
RH		 2768 }
2769 else if ((operand->flags & V850_OPERAND_EP) != 0)
2770 {
28e4f854
KH		 2771 char *start = input_line_pointer;
2772 char c = get_symbol_end ();
2773
252b5132
RH		 2774 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
2775 {
2776 /* Put things back the way we found them. */
2777 *input_line_pointer = c;
2778 input_line_pointer = start;
2779 errmsg = _("expected EP register");
2780 goto error;
2781 }
28e4f854 2782
252b5132
RH		 2783 *input_line_pointer = c;
2784 str = input_line_pointer;
2785 input_line_pointer = hold;
28e4f854
KH		 2786
2787 while (*str == ' ' || *str == ','
2788 || *str == '[' || *str == ']')
2789 ++str;
252b5132
RH		 2790 continue;
2791 }
28e4f854 2792 else if ((operand->flags & V850_OPERAND_CC) != 0)
252b5132 2793 {
1cd986c5 2794 if (!cc_name (&ex, TRUE))
252b5132 2795 {
1cd986c5 2796 errmsg = _("invalid condition code name");
252b5132 2797 }
28e4f854 2798
1cd986c5
NC		 2799 if ((operand->flags & V850_NOT_SA)
2800 && ex.X_add_number == COND_SA_NUM)
2801 {
2802 errmsg = _("condition sa cannot be used here");
2803 }
252b5132 2804 }
1cd986c5 2805 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
252b5132 2806 {
1cd986c5
NC		 2807 if (!float_cc_name (&ex, TRUE))
2808 {
2809 errmsg = _("invalid condition code name");
2810 }
252b5132 2811 }
78c8d46c
NC		 2812 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
2813 {
2814 if (!cacheop_name (&ex, TRUE))
2815 errmsg = _("invalid cache oparation name");
2816 }
2817 else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
2818 {
2819 if (!prefop_name (&ex, TRUE))
2820 errmsg = _("invalid pref oparation name");
2821 }
2822 else if ((operand->flags & V850_OPERAND_VREG) != 0)
2823 {
2824 if (!vector_register_name (&ex))
2825 errmsg = _("invalid vector register name");
2826 }
1cd986c5
NC		 2827 else if ((register_name (&ex)
2828 && (operand->flags & V850_OPERAND_REG) == 0))
252b5132
RH		 2829 {
2830 char c;
28e4f854
KH		 2831 int exists = 0;
2832
252b5132
RH		 2833 /* It is possible that an alias has been defined that
2834 matches a register name. For example the code may
2835 include a ".set ZERO, 0" directive, which matches
2836 the register name "zero". Attempt to reparse the
2837 field as an expression, and only complain if we
2838 cannot generate a constant. */
2839
2840 input_line_pointer = str;
2841
2842 c = get_symbol_end ();
28e4f854 2843
252b5132
RH		 2844 if (symbol_find (str) != NULL)
2845 exists = 1;
28e4f854
KH		 2846
2847 *input_line_pointer = c;
252b5132 2848 input_line_pointer = str;
28e4f854
KH		 2849
2850 expression (&ex);
252b5132
RH		 2851
2852 if (ex.X_op != O_constant)
2853 {
33b7f697 2854 /* If this register is actually occurring too early on
252b5132
RH		 2855 the parsing of the instruction, (because another
2856 field is missing) then report this. */
2857 if (opindex_ptr[1] != 0
1cd986c5
NC		 2858 && ((v850_operands[opindex_ptr[1]].flags
2859 & V850_OPERAND_REG)
2860 ||(v850_operands[opindex_ptr[1]].flags
2861 & V850_OPERAND_VREG)))
252b5132
RH		 2862 errmsg = _("syntax error: value is missing before the register name");
2863 else
2864 errmsg = _("syntax error: register not expected");
2865
28e4f854
KH		 2866 /* If we created a symbol in the process of this
2867 test then delete it now, so that it will not
2868 be output with the real symbols... */
252b5132
RH		 2869 if (exists == 0
2870 && ex.X_op == O_symbol)
2871 symbol_remove (ex.X_add_symbol,
28e4f854 2872 &symbol_rootP, &symbol_lastP);
252b5132
RH		 2873 }
2874 }
1cd986c5 2875 else if (system_register_name (&ex, FALSE)
252b5132 2876 && (operand->flags & V850_OPERAND_SRG) == 0)
1cd986c5
NC		 2877 {
2878 errmsg = _("syntax error: system register not expected");
2879 }
2880 else if (cc_name (&ex, FALSE)
252b5132 2881 && (operand->flags & V850_OPERAND_CC) == 0)
1cd986c5
NC		 2882 {
2883 errmsg = _("syntax error: condition code not expected");
2884 }
2885 else if (float_cc_name (&ex, FALSE)
2886 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
2887 {
2888 errmsg = _("syntax error: condition code not expected");
2889 }
78c8d46c
NC		 2890 else if (vector_register_name (&ex)
2891 && (operand->flags & V850_OPERAND_VREG) == 0)
2892 {
2893 errmsg = _("syntax error: vector register not expected");
2894 }
252b5132
RH		 2895 else
2896 {
28e4f854 2897 expression (&ex);
1cd986c5
NC		 2898
2899 if ((operand->flags & V850_NOT_IMM0)
2900 && ex.X_op == O_constant
2901 && ex.X_add_number == 0)
2902 {
2903 errmsg = _("immediate 0 cannot be used here");
2904 }
2905
252b5132 2906 /* Special case:
1cd986c5 2907 If we are assembling a MOV/JARL/JR instruction and the immediate
50b15da2 2908 value does not fit into the bits available then create a
1cd986c5 2909 fake error so that the next MOV/JARL/JR instruction will be
50b15da2 2910 selected. This one has a 32 bit immediate field. */
252b5132 2911
1cd986c5
NC		 2912 if ((strcmp (opcode->name, "mov") == 0
2913 || strcmp (opcode->name, "jarl") == 0
2914 || strcmp (opcode->name, "jr") == 0)
252b5132 2915 && ex.X_op == O_constant
28e4f854 2916 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
03223580 2917 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
1cd986c5
NC		 2918 {
2919 errmsg = _("immediate operand is too large");
2920 }
2921
2922 if ((strcmp (opcode->name, "jarl") == 0
2923 || strcmp (opcode->name, "jr") == 0)
2924 && ex.X_op != O_constant
2925 && operand->bits != default_disp_size)
2926 {
2927 errmsg = _("immediate operand is not match");
2928 }
78c8d46c
NC		 2929
2930 /* Special case2 :
2931 If we are assembling a ld/st instruction and the immediate
2932 value does not fit into the bits available then create a
2933 fake error so that the next ld/st instruction will be
2934 selected. */
2935 if ( ( (strncmp (opcode->name, "st.", 3) == 0)
2936 || (strncmp (opcode->name, "ld.", 3) == 0))
2937 && ex.X_op == O_constant
2938 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2939 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2940 errmsg = _("displacement is too large");
252b5132
RH		 2941 }
2942
2943 if (errmsg)
2944 goto error;
252b5132 2945
28e4f854 2946 switch (ex.X_op)
252b5132
RH		 2947 {
2948 case O_illegal:
2949 errmsg = _("illegal operand");
2950 goto error;
2951 case O_absent:
2952 errmsg = _("missing operand");
2953 goto error;
2954 case O_register:
28e4f854 2955 if ((operand->flags
1cd986c5 2956 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0)
252b5132
RH		 2957 {
2958 errmsg = _("invalid operand");
2959 goto error;
2960 }
1cd986c5
NC		 2961
2962 insn = v850_insert_operand (insn, operand,
2963 ex.X_add_number,
2964 &warningmsg);
2965
252b5132
RH		 2966 break;
2967
2968 case O_constant:
2969 insn = v850_insert_operand (insn, operand, ex.X_add_number,
1cd986c5 2970 &warningmsg);
252b5132
RH		 2971 break;
2972
2973 default:
2974 /* We need to generate a fixup for this expression. */
2975 if (fc >= MAX_INSN_FIXUPS)
2976 as_fatal (_("too many fixups"));
2977
28e4f854
KH		 2978 fixups[fc].exp = ex;
2979 fixups[fc].opindex = *opindex_ptr;
2980 fixups[fc].reloc = BFD_RELOC_UNUSED;
252b5132
RH		 2981 ++fc;
2982 break;
2983 }
2984 }
2985
2986 str = input_line_pointer;
2987 input_line_pointer = hold;
2988
2989 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']'
2990 || *str == ')')
2991 ++str;
2992 }
1cd986c5
NC		 2993
2994 while (ISSPACE (*str))
2995 ++str;
2996
2997 if (*str == '\0')
2998 match = 1;
252b5132
RH		 2999
3000 error:
3001 if (match == 0)
28e4f854 3002 {
1cd986c5
NC		 3003 if ((opindex_ptr - opcode->operands) >= most_match_count)
3004 {
3005 most_match_count = opindex_ptr - opcode->operands;
3006 if (errmsg != NULL)
3007 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1);
3008 }
3009
252b5132
RH		 3010 next_opcode = opcode + 1;
3011 if (next_opcode->name != NULL
3012 && strcmp (next_opcode->name, opcode->name) == 0)
3013 {
3014 opcode = next_opcode;
3015
3016 /* Skip versions that are not supported by the target
3017 processor. */
3018 if ((opcode->processors & processor_mask) == 0)
3019 goto error;
28e4f854 3020
252b5132
RH		 3021 continue;
3022 }
28e4f854 3023
1cd986c5
NC		 3024 if (most_match_errmsg[0] == 0)
3025 /* xgettext:c-format. */
3026 as_bad (_("junk at end of line: `%s'"), str);
3027 else
3028 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg);
28e4f854
KH		 3029
3030 if (*input_line_pointer == ']')
3031 ++input_line_pointer;
3032
252b5132
RH		 3033 ignore_rest_of_line ();
3034 input_line_pointer = saved_input_line_pointer;
3035 return;
28e4f854 3036 }
1cd986c5
NC		 3037
3038 if (warningmsg != NULL)
cd94c7fb 3039 as_warn ("%s", warningmsg);
252b5132
RH		 3040 break;
3041 }
28e4f854 3042
252b5132
RH		 3043 input_line_pointer = str;
3044
9fcc94b6
AM		 3045 /* Tie dwarf2 debug info to the address at the start of the insn.
3046 We can't do this after the insn has been output as the current
3047 frag may have been closed off. eg. by frag_var. */
3048 dwarf2_emit_insn (0);
3049
28e4f854
KH		 3050 /* Write out the instruction. */
3051
252b5132
RH		 3052 if (relaxable && fc > 0)
3053 {
3054 insn_size = 2;
3055 fc = 0;
3056
78c8d46c
NC		 3057 if (strcmp (opcode->name, "loop") == 0)
3058 {
3059 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22)
3060 {
3061 insn_size = 4;
3062 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22,
3063 fixups[0].exp.X_add_symbol,
3064 fixups[0].exp.X_add_number,
3065 (char *)(size_t) fixups[0].opindex);
3066 md_number_to_chars (f, insn, insn_size);
3067 md_number_to_chars (f+4, 0, 4);
3068 }
3069 else
3070 {
3071 as_bad (_("loop: 32-bit displacement not supported"));
3072 }
3073 }
3074 else if (strcmp (opcode->name, "br") == 0
3075 || strcmp (opcode->name, "jbr") == 0)
252b5132 3076 {
78c8d46c 3077 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
1cd986c5
NC		 3078 {
3079 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
3080 fixups[0].exp.X_add_symbol,
3081 fixups[0].exp.X_add_number,
3082 (char *)(size_t) fixups[0].opindex);
3083 md_number_to_chars (f, insn, insn_size);
3084 md_number_to_chars (f + 2, 0, 2);
3085 }
3086 else
3087 {
3088 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32,
3089 fixups[0].exp.X_add_symbol,
3090 fixups[0].exp.X_add_number,
3091 (char *)(size_t) fixups[0].opindex);
3092 md_number_to_chars (f, insn, insn_size);
3093 md_number_to_chars (f + 2, 0, 4);
3094 }
252b5132 3095 }
1cd986c5 3096 else /* b<cond>, j<cond>. */
252b5132 3097 {
1cd986c5 3098 if (default_disp_size == 22
78c8d46c 3099 || (processor_mask & PROCESSOR_V850E2_UP) == 0)
1cd986c5 3100 {
78c8d46c 3101 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
1cd986c5
NC		 3102 {
3103 if (strcmp (opcode->name, "bsa") == 0)
3104 {
3105 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22,
3106 fixups[0].exp.X_add_symbol,
3107 fixups[0].exp.X_add_number,
3108 (char *)(size_t) fixups[0].opindex);
3109 md_number_to_chars (f, insn, insn_size);
3110 md_number_to_chars (f + 2, 0, 6);
3111 }
3112 else
3113 {
3114 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22,
3115 fixups[0].exp.X_add_symbol,
3116 fixups[0].exp.X_add_number,
3117 (char *)(size_t) fixups[0].opindex);
3118 md_number_to_chars (f, insn, insn_size);
3119 md_number_to_chars (f + 2, 0, 4);
3120 }
3121 }
3122 else
3123 {
3124 if (strcmp (opcode->name, "bsa") == 0)
3125 {
3126 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22,
3127 fixups[0].exp.X_add_symbol,
3128 fixups[0].exp.X_add_number,
3129 (char *)(size_t) fixups[0].opindex);
3130 md_number_to_chars (f, insn, insn_size);
3131 md_number_to_chars (f + 2, 0, 6);
3132 }
3133 else
3134 {
3135 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22,
3136 fixups[0].exp.X_add_symbol,
3137 fixups[0].exp.X_add_number,
3138 (char *)(size_t) fixups[0].opindex);
3139 md_number_to_chars (f, insn, insn_size);
3140 md_number_to_chars (f + 2, 0, 4);
3141 }
3142 }
3143 }
3144 else
3145 {
78c8d46c 3146 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
1cd986c5
NC		 3147 {
3148 if (strcmp (opcode->name, "bsa") == 0)
3149 {
3150 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32,
3151 fixups[0].exp.X_add_symbol,
3152 fixups[0].exp.X_add_number,
3153 (char *)(size_t) fixups[0].opindex);
3154 md_number_to_chars (f, insn, insn_size);
3155 md_number_to_chars (f + 2, 0, 8);
3156 }
3157 else
3158 {
3159 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32,
3160 fixups[0].exp.X_add_symbol,
3161 fixups[0].exp.X_add_number,
3162 (char *)(size_t) fixups[0].opindex);
3163 md_number_to_chars (f, insn, insn_size);
3164 md_number_to_chars (f + 2, 0, 6);
3165 }
3166 }
3167 else
3168 {
3169 if (strcmp (opcode->name, "bsa") == 0)
3170 {
3171 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32,
3172 fixups[0].exp.X_add_symbol,
3173 fixups[0].exp.X_add_number,
3174 (char *)(size_t) fixups[0].opindex);
3175 md_number_to_chars (f, insn, insn_size);
3176 md_number_to_chars (f + 2, 0, 8);
3177 }
3178 else
3179 {
3180 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32,
3181 fixups[0].exp.X_add_symbol,
3182 fixups[0].exp.X_add_number,
3183 (char *)(size_t) fixups[0].opindex);
3184 md_number_to_chars (f, insn, insn_size);
3185 md_number_to_chars (f + 2, 0, 6);
3186 }
3187 }
3188 }
252b5132
RH		 3189 }
3190 }
28e4f854 3191 else
252b5132
RH		 3192 {
3193 /* Four byte insns have an opcode with the two high bits on. */
3194 if ((insn & 0x0600) == 0x0600)
3195 insn_size = 4;
3196 else
3197 insn_size = 2;
3198
28e4f854 3199 /* Special case: 32 bit MOV. */
252b5132
RH		 3200 if ((insn & 0xffe0) == 0x0620)
3201 insn_size = 2;
28e4f854 3202
1cd986c5
NC		 3203 /* Special case: 32 bit JARL,JMP,JR. */
3204 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */
3205 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */
3206 || (insn & 0x1ffff) == 0x2e0) /* JR. */
3207 insn_size = 2;
3208
78c8d46c
NC		 3209 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len))
3210 {
3211 frag_wane (frag_now);
3212 frag_new (0);
3213 }
3214
252b5132 3215 f = frag_more (insn_size);
252b5132
RH		 3216 md_number_to_chars (f, insn, insn_size);
3217
3218 if (extra_data_after_insn)
3219 {
3220 f = frag_more (extra_data_len);
252b5132
RH		 3221 md_number_to_chars (f, extra_data, extra_data_len);
3222
b34976b6 3223 extra_data_after_insn = FALSE;
252b5132
RH		 3224 }
3225 }
3226
3227 /* Create any fixups. At this point we do not use a
3228 bfd_reloc_code_real_type, but instead just use the
3229 BFD_RELOC_UNUSED plus the operand index. This lets us easily
3230 handle fixups for any operand type, although that is admittedly
3231 not a very exciting feature. We pick a BFD reloc type in
55cf6793 3232 md_apply_fix. */
252b5132
RH		 3233 for (i = 0; i < fc; i++)
3234 {
28e4f854
KH		 3235 const struct v850_operand *operand;
3236 bfd_reloc_code_real_type reloc;
3237
3238 operand = &v850_operands[fixups[i].opindex];
252b5132
RH		 3239
3240 reloc = fixups[i].reloc;
28e4f854 3241
252b5132
RH		 3242 if (reloc != BFD_RELOC_UNUSED)
3243 {
28e4f854
KH		 3244 reloc_howto_type *reloc_howto =
3245 bfd_reloc_type_lookup (stdoutput, reloc);
3246 int size;
3247 int address;
3248 fixS *fixP;
252b5132
RH		 3249
3250 if (!reloc_howto)
28e4f854
KH		 3251 abort ();
3252
252b5132
RH		 3253 size = bfd_get_reloc_size (reloc_howto);
3254
3255 /* XXX This will abort on an R_V850_8 reloc -
28e4f854
KH		 3256 is this reloc actually used? */
3257 if (size != 2 && size != 4)
252b5132
RH		 3258 abort ();
3259
1cd986c5
NC		 3260 if (extra_data_len == 0)
3261 {
3262 address = (f - frag_now->fr_literal) + insn_size - size;
3263 }
3264 else
3265 {
3266 address = (f - frag_now->fr_literal) + extra_data_len - size;
3267 }
252b5132 3268
1cd986c5
NC		 3269 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL))
3270 {
3271 fixups[i].exp.X_add_number += 2;
3272 }
3273 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3274 {
3275 fixups[i].exp.X_add_number += 2;
3276 address += 2;
3277 }
28e4f854 3278
1cd986c5 3279 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
252b5132 3280 fixP = fix_new_exp (frag_now, address, size,
28e4f854 3281 &fixups[i].exp,
252b5132
RH		 3282 reloc_howto->pc_relative,
3283 reloc);
3284
2d034539
NC		 3285 fixP->tc_fix_data = (void *) operand;
3286
252b5132
RH		 3287 switch (reloc)
3288 {
3289 case BFD_RELOC_LO16:
1cd986c5 3290 case BFD_RELOC_V850_LO16_S1:
1e50d24d 3291 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
252b5132
RH		 3292 case BFD_RELOC_HI16:
3293 case BFD_RELOC_HI16_S:
3294 fixP->fx_no_overflow = 1;
3295 break;
5480ccf3
NC		 3296 default:
3297 break;
252b5132
RH		 3298 }
3299 }
3300 else
3301 {
78c8d46c 3302 gas_assert (f != NULL);
28e4f854 3303 fix_new_exp (frag_now,
252b5132
RH		 3304 f - frag_now->fr_literal, 4,
3305 & fixups[i].exp,
1cd986c5 3306 (operand->flags & V850_PCREL) != 0,
252b5132 3307 (bfd_reloc_code_real_type) (fixups[i].opindex
28e4f854 3308 + (int) BFD_RELOC_UNUSED));
252b5132
RH		 3309 }
3310 }
3311
3312 input_line_pointer = saved_input_line_pointer;
3313}
3314
28e4f854
KH		 3315/* If while processing a fixup, a reloc really needs to be created
3316 then it is done here. */
252b5132 3317
252b5132 3318arelent *
ea1562b3 3319tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
252b5132 3320{
28e4f854
KH		 3321 arelent *reloc;
3322
ea1562b3
NC		 3323 reloc = xmalloc (sizeof (arelent));
3324 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
28e4f854
KH		 3325 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3326 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
e30ddb24
NC		 3327
3328 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
3329 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3330 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL
3331 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP
3332 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN)
3333 reloc->addend = fixp->fx_offset;
3334 else
3335 {
1cd986c5 3336#if 0
e30ddb24
NC		 3337 if (fixp->fx_r_type == BFD_RELOC_32
3338 && fixp->fx_pcrel)
3339 fixp->fx_r_type = BFD_RELOC_32_PCREL;
1cd986c5 3340#endif
e30ddb24
NC		 3341
3342 reloc->addend = fixp->fx_addnumber;
3343 }
3344
ec178e1b 3345 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
252b5132 3346
ea1562b3 3347 if (reloc->howto == NULL)
252b5132
RH		 3348 {
3349 as_bad_where (fixp->fx_file, fixp->fx_line,
28e4f854
KH		 3350 /* xgettext:c-format */
3351 _("reloc %d not supported by object file format"),
252b5132
RH		 3352 (int) fixp->fx_r_type);
3353
3354 xfree (reloc);
28e4f854 3355
252b5132
RH		 3356 return NULL;
3357 }
28e4f854 3358
252b5132
RH		 3359 return reloc;
3360}
3361
86aba9db 3362void
ea1562b3 3363v850_handle_align (fragS * frag)
86aba9db
NC		 3364{
3365 if (v850_relax
3366 && frag->fr_type == rs_align
3367 && frag->fr_address + frag->fr_fix > 0
3368 && frag->fr_offset > 1
3369 && now_seg != bss_section
3370 && now_seg != v850_seg_table[SBSS_SECTION].s
3371 && now_seg != v850_seg_table[TBSS_SECTION].s
3372 && now_seg != v850_seg_table[ZBSS_SECTION].s)
3373 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0,
ec178e1b 3374 BFD_RELOC_V850_ALIGN);
86aba9db
NC		 3375}
3376
606ab118 3377/* Return current size of variable part of frag. */
28e4f854 3378
252b5132 3379int
ea1562b3 3380md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
252b5132 3381{
606ab118 3382 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
252b5132 3383 abort ();
606ab118
AM		 3384
3385 return md_relax_table[fragp->fr_subtype].rlx_length;
28e4f854 3386}
252b5132
RH		 3387
3388long
ea1562b3 3389v850_pcrel_from_section (fixS *fixp, segT section)
252b5132
RH		 3390{
3391 /* If the symbol is undefined, or in a section other than our own,
d6c497c7 3392 or it is weak (in which case it may well be in another section,
252b5132
RH		 3393 then let the linker figure it out. */
3394 if (fixp->fx_addsy != (symbolS *) NULL
3395 && (! S_IS_DEFINED (fixp->fx_addsy)
d6c497c7 3396 || S_IS_WEAK (fixp->fx_addsy)
252b5132 3397 || (S_GET_SEGMENT (fixp->fx_addsy) != section)))
d6c497c7 3398 return 0;
28e4f854 3399
252b5132
RH		 3400 return fixp->fx_frag->fr_address + fixp->fx_where;
3401}
3402
94f592af 3403void
55cf6793 3404md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
252b5132 3405{
94f592af 3406 valueT value = * valueP;
28e4f854 3407 char *where;
252b5132 3408
94f592af 3409 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
86aba9db
NC		 3410 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3411 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP
94f592af 3412 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132 3413 {
94f592af
NC		 3414 fixP->fx_done = 0;
3415 return;
252b5132
RH		 3416 }
3417
94f592af 3418 if (fixP->fx_addsy == (symbolS *) NULL)
86aba9db 3419 fixP->fx_addnumber = value,
94f592af
NC		 3420 fixP->fx_done = 1;
3421
3422 else if (fixP->fx_pcrel)
86aba9db 3423 fixP->fx_addnumber = fixP->fx_offset;
94f592af 3424
252b5132
RH		 3425 else
3426 {
94f592af
NC		 3427 value = fixP->fx_offset;
3428 if (fixP->fx_subsy != (symbolS *) NULL)
252b5132 3429 {
94f592af
NC		 3430 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
3431 value -= S_GET_VALUE (fixP->fx_subsy);
252b5132 3432 else
ea1562b3
NC		 3433 /* We don't actually support subtracting a symbol. */
3434 as_bad_where (fixP->fx_file, fixP->fx_line,
3435 _("expression too complex"));
252b5132 3436 }
86aba9db 3437 fixP->fx_addnumber = value;
252b5132
RH		 3438 }
3439
94f592af 3440 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
252b5132 3441 {
28e4f854
KH		 3442 int opindex;
3443 const struct v850_operand *operand;
3444 unsigned long insn;
1cd986c5 3445 const char *errmsg = NULL;
252b5132 3446
94f592af 3447 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
28e4f854 3448 operand = &v850_operands[opindex];
252b5132
RH		 3449
3450 /* Fetch the instruction, insert the fully resolved operand
ec178e1b 3451 value, and stuff the instruction back again.
252b5132
RH		 3452
3453 Note the instruction has been stored in little endian
3454 format! */
94f592af 3455 where = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 3456
1cd986c5
NC		 3457 if (fixP->fx_size > 2)
3458 insn = bfd_getl32 ((unsigned char *) where);
3459 else
3460 insn = bfd_getl16 ((unsigned char *) where);
3461
252b5132 3462 insn = v850_insert_operand (insn, operand, (offsetT) value,
1cd986c5
NC		 3463 &errmsg);
3464 if (errmsg)
cd94c7fb 3465 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg);
1cd986c5
NC		 3466
3467 if (fixP->fx_size > 2)
3468 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3469 else
3470 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
252b5132 3471
94f592af
NC		 3472 if (fixP->fx_done)
3473 /* Nothing else to do here. */
3474 return;
252b5132 3475
28e4f854
KH		 3476 /* Determine a BFD reloc value based on the operand information.
3477 We are only prepared to turn a few of the operands into relocs. */
252b5132 3478
1cd986c5 3479 if (operand->default_reloc == BFD_RELOC_NONE)
252b5132 3480 {
94f592af 3481 as_bad_where (fixP->fx_file, fixP->fx_line,
28e4f854 3482 _("unresolved expression that must be resolved"));
94f592af
NC		 3483 fixP->fx_done = 1;
3484 return;
252b5132 3485 }
1cd986c5
NC		 3486
3487 {
3488 fixP->fx_r_type = operand->default_reloc;
3489 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3490 {
3491 fixP->fx_where += 2;
3492 fixP->fx_size = 2;
3493 fixP->fx_addnumber += 2;
3494 }
3495 }
252b5132 3496 }
94f592af 3497 else if (fixP->fx_done)
252b5132
RH		 3498 {
3499 /* We still have to insert the value into memory! */
94f592af 3500 where = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 3501
a0ef61f7 3502 if (fixP->tc_fix_data != NULL
1cd986c5
NC		 3503 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
3504 {
3505 const char * message = NULL;
3506 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
3507 unsigned long insn;
3508
3509 /* The variable "where" currently points at the exact point inside
3510 the insn where we need to insert the value. But we need to
3511 extract the entire insn so we probably need to move "where"
3512 back a few bytes. */
3513
3514 if (fixP->fx_size == 2)
3515 where -= 2;
3516 else if (fixP->fx_size == 1)
3517 where -= 3;
3518
3519 insn = bfd_getl32 ((unsigned char *) where);
3520
3521 /* Use the operand's insertion procedure, if present, in order to
3522 make sure that the value is correctly stored in the insn. */
3523 insn = operand->insert (insn, (offsetT) value, & message);
3524 /* Ignore message even if it is set. */
3525
3526 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3527 }
2d034539 3528 else
1cd986c5
NC		 3529 {
3530 switch (fixP->fx_r_type)
3531 {
3532 case BFD_RELOC_V850_32_ABS:
3533 case BFD_RELOC_V850_32_PCREL:
3534 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where);
3535 break;
3536
3537 case BFD_RELOC_32:
3538 bfd_putl32 (value, (unsigned char *) where);
3539 break;
3540
3541 case BFD_RELOC_V850_23:
3542 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7))
3543 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))),
3544 (unsigned char *) where);
3545 break;
3546
3547 case BFD_RELOC_16:
3548 case BFD_RELOC_HI16:
3549 case BFD_RELOC_HI16_S:
3550 case BFD_RELOC_LO16:
3551 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
3552 case BFD_RELOC_V850_SDA_16_16_OFFSET:
3553 case BFD_RELOC_V850_TDA_16_16_OFFSET:
3554 case BFD_RELOC_V850_CALLT_16_16_OFFSET:
3555 bfd_putl16 (value & 0xffff, (unsigned char *) where);
3556 break;
3557
3558 case BFD_RELOC_8:
3559 *where = value & 0xff;
3560 break;
3561
3562 case BFD_RELOC_V850_9_PCREL:
3563 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3)
3564 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where);
3565 break;
3566
3567 case BFD_RELOC_V850_17_PCREL:
3568 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16)
3569 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where);
3570 break;
3571
3572 case BFD_RELOC_V850_16_PCREL:
de863c74
NC		 3573 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001),
3574 (unsigned char *) (where + 2));
1cd986c5
NC		 3575 break;
3576
3577 case BFD_RELOC_V850_22_PCREL:
3578 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)
3579 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where);
3580 break;
3581
3582 case BFD_RELOC_V850_16_S1:
3583 case BFD_RELOC_V850_LO16_S1:
3584 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
3585 case BFD_RELOC_V850_SDA_15_16_OFFSET:
3586 bfd_putl16 (value & 0xfffe, (unsigned char *) where);
3587 break;
3588
3589 case BFD_RELOC_V850_16_SPLIT_OFFSET:
3590 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3591 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
3592 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET:
3593 bfd_putl32 (((value << 16) & 0xfffe0000)
3594 | ((value << 5) & 0x20)
3595 | (bfd_getl32 (where) & ~0xfffe0020), where);
3596 break;
3597
3598 case BFD_RELOC_V850_TDA_6_8_OFFSET:
3599 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e);
3600 break;
3601
3602 case BFD_RELOC_V850_TDA_7_8_OFFSET:
3603 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f);
3604 break;
3605
3606 case BFD_RELOC_V850_TDA_7_7_OFFSET:
3607 *where = (*where & ~0x7f) | (value & 0x7f);
3608 break;
3609
3610 case BFD_RELOC_V850_TDA_4_5_OFFSET:
3611 *where = (*where & ~0xf) | ((value >> 1) & 0xf);
3612 break;
3613
3614 case BFD_RELOC_V850_TDA_4_4_OFFSET:
3615 *where = (*where & ~0xf) | (value & 0xf);
3616 break;
3617
3618 case BFD_RELOC_V850_CALLT_6_7_OFFSET:
3619 *where = (*where & ~0x3f) | (value & 0x3f);
3620 break;
3621
3622 default:
3623 abort ();
3624 }
3625 }
252b5132 3626 }
252b5132 3627}
1cd986c5 3628
252b5132
RH		 3629/* Parse a cons expression. We have to handle hi(), lo(), etc
3630 on the v850. */
28e4f854 3631
252b5132 3632void
ea1562b3 3633parse_cons_expression_v850 (expressionS *exp)
252b5132 3634{
1cd986c5 3635 const char *errmsg;
252b5132 3636 /* See if there's a reloc prefix like hi() we have to handle. */
1cd986c5 3637 hold_cons_reloc = v850_reloc_prefix (NULL, &errmsg);
252b5132
RH		 3638
3639 /* Do normal expression parsing. */
3640 expression (exp);
3641}
3642
3643/* Create a fixup for a cons expression. If parse_cons_expression_v850
3644 found a reloc prefix, then we use that reloc, else we choose an
3645 appropriate one based on the size of the expression. */
28e4f854 3646
252b5132 3647void
ea1562b3
NC		 3648cons_fix_new_v850 (fragS *frag,
3649 int where,
3650 int size,
3651 expressionS *exp)
252b5132
RH		 3652{
3653 if (hold_cons_reloc == BFD_RELOC_UNUSED)
3654 {
3655 if (size == 4)
3656 hold_cons_reloc = BFD_RELOC_32;
3657 if (size == 2)
3658 hold_cons_reloc = BFD_RELOC_16;
3659 if (size == 1)
3660 hold_cons_reloc = BFD_RELOC_8;
3661 }
3662
3663 if (exp != NULL)
3664 fix_new_exp (frag, where, size, exp, 0, hold_cons_reloc);
3665 else
3666 fix_new (frag, where, size, NULL, 0, 0, hold_cons_reloc);
a8761a19
DD		 3667
3668 hold_cons_reloc = BFD_RELOC_UNUSED;
252b5132 3669}
d6c497c7 3670
b34976b6 3671bfd_boolean
ea1562b3 3672v850_fix_adjustable (fixS *fixP)
252b5132 3673{
252b5132
RH		 3674 if (fixP->fx_addsy == NULL)
3675 return 1;
28e4f854 3676
28e4f854 3677 /* Don't adjust function names. */
252b5132
RH		 3678 if (S_IS_FUNCTION (fixP->fx_addsy))
3679 return 0;
3680
28e4f854
KH		 3681 /* We need the symbol name for the VTABLE entries. */
3682 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 3683 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3684 return 0;
28e4f854 3685
252b5132
RH		 3686 return 1;
3687}
28e4f854 3688
252b5132 3689int
ea1562b3 3690v850_force_relocation (struct fix *fixP)
252b5132 3691{
a161fe53 3692 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
86aba9db
NC		 3693 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
3694 return 1;
3695
3696 if (v850_relax
3697 && (fixP->fx_pcrel
a161fe53 3698 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN
a161fe53 3699 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL
1cd986c5
NC		 3700 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL
3701 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL
3702 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL
3703 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL
a161fe53 3704 || fixP->fx_r_type >= BFD_RELOC_UNUSED))
86aba9db
NC		 3705 return 1;
3706
ae6063d4 3707 return generic_force_reloc (fixP);
252b5132 3708}
GDB Binutils - Deliverables
This page took 0.808471 seconds and 4 git commands to generate.