Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-v850.c -- Assembler code for the NEC V850 |
8ad7c533 | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, |
de863c74 | 3 | 2006, 2007, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
28e4f854 | 24 | #include "subsegs.h" |
252b5132 | 25 | #include "opcode/v850.h" |
a8761a19 | 26 | #include "dwarf2dbg.h" |
252b5132 | 27 | |
28e4f854 KH |
28 | /* Sign-extend a 16-bit number. */ |
29 | #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) | |
252b5132 RH |
30 | |
31 | /* Temporarily holds the reloc in a cons expression. */ | |
a8761a19 | 32 | static bfd_reloc_code_real_type hold_cons_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
33 | |
34 | /* Set to TRUE if we want to be pedantic about signed overflows. */ | |
b34976b6 AM |
35 | static bfd_boolean warn_signed_overflows = FALSE; |
36 | static bfd_boolean warn_unsigned_overflows = FALSE; | |
252b5132 RH |
37 | |
38 | /* Indicates the target BFD machine number. */ | |
28e4f854 | 39 | static int machine = -1; |
252b5132 | 40 | |
de863c74 NC |
41 | |
42 | /* Indiciates the target BFD architecture. */ | |
43 | int v850_target_arch = bfd_arch_v850_rh850; | |
44 | const char * v850_target_format = "elf32-v850-rh850"; | |
45 | static flagword v850_e_flags = 0; | |
46 | ||
252b5132 | 47 | /* Indicates the target processor(s) for the assemble. */ |
1cd986c5 | 48 | static int processor_mask = 0; |
252b5132 RH |
49 | \f |
50 | /* Structure to hold information about predefined registers. */ | |
ea1562b3 NC |
51 | struct reg_name |
52 | { | |
28e4f854 KH |
53 | const char *name; |
54 | int value; | |
1cd986c5 | 55 | unsigned int processors; |
252b5132 RH |
56 | }; |
57 | ||
28e4f854 KH |
58 | /* Generic assembler global variables which must be defined by all |
59 | targets. */ | |
252b5132 | 60 | |
28e4f854 | 61 | /* Characters which always start a comment. */ |
252b5132 RH |
62 | const char comment_chars[] = "#"; |
63 | ||
64 | /* Characters which start a comment at the beginning of a line. */ | |
65 | const char line_comment_chars[] = ";#"; | |
66 | ||
28e4f854 | 67 | /* Characters which may be used to separate multiple commands on a |
252b5132 RH |
68 | single line. */ |
69 | const char line_separator_chars[] = ";"; | |
70 | ||
28e4f854 | 71 | /* Characters which are used to indicate an exponent in a floating |
252b5132 RH |
72 | point number. */ |
73 | const char EXP_CHARS[] = "eE"; | |
74 | ||
28e4f854 | 75 | /* Characters which mean that a number is a floating point constant, |
252b5132 RH |
76 | as in 0d1.0. */ |
77 | const char FLT_CHARS[] = "dD"; | |
78 | \f | |
ea1562b3 NC |
79 | const relax_typeS md_relax_table[] = |
80 | { | |
1cd986c5 NC |
81 | /* Conditional branches.(V850/V850E, max 22bit) */ |
82 | #define SUBYPTE_COND_9_22 0 | |
83 | {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, | |
84 | {0x1ffffe + 2, -0x200000 + 2, 6, 0}, | |
85 | /* Conditional branches.(V850/V850E, max 22bit) */ | |
86 | #define SUBYPTE_SA_9_22 2 | |
87 | {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, | |
88 | {0x1ffffe + 4, -0x200000 + 4, 8, 0}, | |
89 | /* Unconditional branches.(V850/V850E, max 22bit) */ | |
90 | #define SUBYPTE_UNCOND_9_22 4 | |
91 | {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, | |
92 | {0x1ffffe, -0x200000, 4, 0}, | |
93 | /* Conditional branches.(V850E2, max 32bit) */ | |
94 | #define SUBYPTE_COND_9_22_32 6 | |
95 | {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, | |
96 | {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, | |
97 | {0x7ffffffe, -0x80000000, 8, 0}, | |
98 | /* Conditional branches.(V850E2, max 32bit) */ | |
99 | #define SUBYPTE_SA_9_22_32 9 | |
100 | {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, | |
101 | {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, | |
102 | {0x7ffffffe, -0x80000000, 10, 0}, | |
103 | /* Unconditional branches.(V850E2, max 32bit) */ | |
104 | #define SUBYPTE_UNCOND_9_22_32 12 | |
105 | {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, | |
106 | {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, | |
107 | {0x7ffffffe, -0x80000000, 6, 0}, | |
108 | /* Conditional branches.(V850E2R max 22bit) */ | |
109 | #define SUBYPTE_COND_9_17_22 15 | |
110 | {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, | |
111 | {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, | |
112 | {0x1ffffe + 2, -0x200000 + 2, 6, 0}, | |
113 | /* Conditional branches.(V850E2R max 22bit) */ | |
114 | #define SUBYPTE_SA_9_17_22 18 | |
115 | {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, | |
116 | {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, | |
117 | {0x1ffffe + 4, -0x200000 + 4, 8, 0}, | |
118 | /* Conditional branches.(V850E2R max 32bit) */ | |
119 | #define SUBYPTE_COND_9_17_22_32 21 | |
120 | {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, | |
121 | {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, | |
122 | {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, | |
123 | {0x7ffffffe, -0x80000000, 8, 0}, | |
124 | /* Conditional branches.(V850E2R max 32bit) */ | |
125 | #define SUBYPTE_SA_9_17_22_32 25 | |
126 | {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, | |
127 | {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, | |
128 | {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, | |
129 | {0x7ffffffe, -0x80000000, 10, 0}, | |
252b5132 RH |
130 | }; |
131 | ||
1cd986c5 NC |
132 | static int v850_relax = 0; |
133 | ||
134 | /* Default branch disp size 22 or 32. */ | |
135 | static int default_disp_size = 22; | |
136 | ||
137 | /* Default no using bcond17. */ | |
138 | static int no_bcond17 = 0; | |
139 | ||
140 | /* Default no using ld/st 23bit offset. */ | |
141 | static int no_stld23 = 0; | |
86aba9db | 142 | |
28e4f854 | 143 | /* Fixups. */ |
ea1562b3 NC |
144 | #define MAX_INSN_FIXUPS 5 |
145 | ||
146 | struct v850_fixup | |
147 | { | |
28e4f854 KH |
148 | expressionS exp; |
149 | int opindex; | |
252b5132 RH |
150 | bfd_reloc_code_real_type reloc; |
151 | }; | |
152 | ||
28e4f854 | 153 | struct v850_fixup fixups[MAX_INSN_FIXUPS]; |
252b5132 | 154 | static int fc; |
252b5132 | 155 | |
9e0665bc | 156 | struct v850_seg_entry |
252b5132 | 157 | { |
9e0665bc AM |
158 | segT s; |
159 | const char *name; | |
160 | flagword flags; | |
161 | }; | |
252b5132 | 162 | |
9e0665bc | 163 | struct v850_seg_entry v850_seg_table[] = |
252b5132 | 164 | { |
9e0665bc AM |
165 | { NULL, ".sdata", |
166 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
167 | | SEC_SMALL_DATA }, | |
168 | { NULL, ".tdata", | |
169 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, | |
170 | { NULL, ".zdata", | |
171 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, | |
172 | { NULL, ".sbss", | |
173 | SEC_ALLOC | SEC_SMALL_DATA }, | |
174 | { NULL, ".tbss", | |
175 | SEC_ALLOC }, | |
176 | { NULL, ".zbss", | |
177 | SEC_ALLOC}, | |
178 | { NULL, ".rosdata", | |
179 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA | |
180 | | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, | |
181 | { NULL, ".rozdata", | |
182 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA | |
183 | | SEC_HAS_CONTENTS }, | |
184 | { NULL, ".scommon", | |
185 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
186 | | SEC_SMALL_DATA | SEC_IS_COMMON }, | |
187 | { NULL, ".tcommon", | |
188 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
189 | | SEC_IS_COMMON }, | |
190 | { NULL, ".zcommon", | |
191 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
192 | | SEC_IS_COMMON }, | |
193 | { NULL, ".call_table_data", | |
194 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, | |
195 | { NULL, ".call_table_text", | |
196 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE | |
197 | | SEC_HAS_CONTENTS}, | |
198 | { NULL, ".bss", | |
199 | SEC_ALLOC } | |
200 | }; | |
28e4f854 | 201 | |
9e0665bc AM |
202 | #define SDATA_SECTION 0 |
203 | #define TDATA_SECTION 1 | |
204 | #define ZDATA_SECTION 2 | |
205 | #define SBSS_SECTION 3 | |
206 | #define TBSS_SECTION 4 | |
207 | #define ZBSS_SECTION 5 | |
208 | #define ROSDATA_SECTION 6 | |
209 | #define ROZDATA_SECTION 7 | |
210 | #define SCOMMON_SECTION 8 | |
211 | #define TCOMMON_SECTION 9 | |
212 | #define ZCOMMON_SECTION 10 | |
213 | #define CALL_TABLE_DATA_SECTION 11 | |
214 | #define CALL_TABLE_TEXT_SECTION 12 | |
215 | #define BSS_SECTION 13 | |
216 | ||
9e0665bc | 217 | static void |
ea1562b3 | 218 | do_v850_seg (int i, subsegT sub) |
252b5132 | 219 | { |
9e0665bc | 220 | struct v850_seg_entry *seg = v850_seg_table + i; |
28e4f854 | 221 | |
28e4f854 | 222 | obj_elf_section_change_hook (); |
ea1562b3 | 223 | |
9e0665bc | 224 | if (seg->s != NULL) |
ea1562b3 | 225 | subseg_set (seg->s, sub); |
9e0665bc AM |
226 | else |
227 | { | |
228 | seg->s = subseg_new (seg->name, sub); | |
229 | bfd_set_section_flags (stdoutput, seg->s, seg->flags); | |
230 | if ((seg->flags & SEC_LOAD) == 0) | |
231 | seg_info (seg->s)->bss = 1; | |
232 | } | |
252b5132 RH |
233 | } |
234 | ||
9e0665bc | 235 | static void |
ea1562b3 | 236 | v850_seg (int i) |
252b5132 | 237 | { |
9e0665bc | 238 | subsegT sub = get_absolute_expression (); |
28e4f854 | 239 | |
9e0665bc | 240 | do_v850_seg (i, sub); |
252b5132 RH |
241 | demand_empty_rest_of_line (); |
242 | } | |
243 | ||
9e0665bc | 244 | static void |
ea1562b3 | 245 | v850_offset (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 246 | { |
825487fa | 247 | char *pfrag; |
252b5132 | 248 | int temp = get_absolute_expression (); |
685736be | 249 | |
825487fa | 250 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0, |
ec178e1b | 251 | (offsetT) temp, (char *) 0); |
825487fa | 252 | *pfrag = 0; |
28e4f854 | 253 | |
252b5132 RH |
254 | demand_empty_rest_of_line (); |
255 | } | |
256 | ||
28e4f854 KH |
257 | /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ |
258 | ||
252b5132 | 259 | static void |
ea1562b3 | 260 | v850_comm (int area) |
252b5132 | 261 | { |
28e4f854 KH |
262 | char *name; |
263 | char c; | |
264 | char *p; | |
265 | int temp; | |
266 | unsigned int size; | |
267 | symbolS *symbolP; | |
268 | int have_align; | |
252b5132 RH |
269 | |
270 | name = input_line_pointer; | |
271 | c = get_symbol_end (); | |
28e4f854 KH |
272 | |
273 | /* Just after name is now '\0'. */ | |
252b5132 RH |
274 | p = input_line_pointer; |
275 | *p = c; | |
28e4f854 | 276 | |
252b5132 | 277 | SKIP_WHITESPACE (); |
28e4f854 | 278 | |
252b5132 RH |
279 | if (*input_line_pointer != ',') |
280 | { | |
281 | as_bad (_("Expected comma after symbol-name")); | |
282 | ignore_rest_of_line (); | |
283 | return; | |
284 | } | |
28e4f854 KH |
285 | |
286 | /* Skip ','. */ | |
287 | input_line_pointer++; | |
288 | ||
252b5132 RH |
289 | if ((temp = get_absolute_expression ()) < 0) |
290 | { | |
28e4f854 | 291 | /* xgettext:c-format */ |
252b5132 RH |
292 | as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); |
293 | ignore_rest_of_line (); | |
294 | return; | |
295 | } | |
28e4f854 | 296 | |
252b5132 RH |
297 | size = temp; |
298 | *p = 0; | |
299 | symbolP = symbol_find_or_make (name); | |
300 | *p = c; | |
28e4f854 | 301 | |
252b5132 RH |
302 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) |
303 | { | |
304 | as_bad (_("Ignoring attempt to re-define symbol")); | |
305 | ignore_rest_of_line (); | |
306 | return; | |
307 | } | |
28e4f854 | 308 | |
252b5132 RH |
309 | if (S_GET_VALUE (symbolP) != 0) |
310 | { | |
311 | if (S_GET_VALUE (symbolP) != size) | |
ea1562b3 NC |
312 | /* xgettext:c-format */ |
313 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), | |
314 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); | |
252b5132 | 315 | } |
28e4f854 KH |
316 | |
317 | know (symbol_get_frag (symbolP) == &zero_address_frag); | |
318 | ||
252b5132 RH |
319 | if (*input_line_pointer != ',') |
320 | have_align = 0; | |
321 | else | |
322 | { | |
323 | have_align = 1; | |
324 | input_line_pointer++; | |
325 | SKIP_WHITESPACE (); | |
326 | } | |
28e4f854 | 327 | |
252b5132 RH |
328 | if (! have_align || *input_line_pointer != '"') |
329 | { | |
330 | if (! have_align) | |
331 | temp = 0; | |
332 | else | |
333 | { | |
334 | temp = get_absolute_expression (); | |
28e4f854 | 335 | |
252b5132 RH |
336 | if (temp < 0) |
337 | { | |
338 | temp = 0; | |
339 | as_warn (_("Common alignment negative; 0 assumed")); | |
340 | } | |
341 | } | |
28e4f854 | 342 | |
cac58fa6 | 343 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 344 | { |
28e4f854 KH |
345 | segT old_sec; |
346 | int old_subsec; | |
347 | char *pfrag; | |
348 | int align; | |
349 | flagword applicable; | |
252b5132 RH |
350 | |
351 | old_sec = now_seg; | |
352 | old_subsec = now_subseg; | |
28e4f854 | 353 | |
252b5132 | 354 | applicable = bfd_applicable_section_flags (stdoutput); |
28e4f854 | 355 | |
252b5132 | 356 | applicable &= SEC_ALLOC; |
28e4f854 | 357 | |
252b5132 RH |
358 | switch (area) |
359 | { | |
9e0665bc AM |
360 | case SCOMMON_SECTION: |
361 | do_v850_seg (SBSS_SECTION, 0); | |
252b5132 | 362 | break; |
28e4f854 | 363 | |
9e0665bc AM |
364 | case ZCOMMON_SECTION: |
365 | do_v850_seg (ZBSS_SECTION, 0); | |
252b5132 | 366 | break; |
28e4f854 | 367 | |
9e0665bc AM |
368 | case TCOMMON_SECTION: |
369 | do_v850_seg (TBSS_SECTION, 0); | |
252b5132 RH |
370 | break; |
371 | } | |
372 | ||
373 | if (temp) | |
374 | { | |
28e4f854 | 375 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
376 | for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) |
377 | ; | |
28e4f854 | 378 | |
252b5132 RH |
379 | if (temp != 1) |
380 | { | |
381 | as_bad (_("Common alignment not a power of 2")); | |
382 | ignore_rest_of_line (); | |
383 | return; | |
384 | } | |
385 | } | |
386 | else | |
387 | align = 0; | |
28e4f854 | 388 | |
9e0665bc | 389 | record_alignment (now_seg, align); |
28e4f854 | 390 | |
252b5132 RH |
391 | if (align) |
392 | frag_align (align, 0, 0); | |
393 | ||
394 | switch (area) | |
395 | { | |
9e0665bc AM |
396 | case SCOMMON_SECTION: |
397 | if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) | |
7dcc9865 | 398 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 RH |
399 | break; |
400 | ||
9e0665bc AM |
401 | case ZCOMMON_SECTION: |
402 | if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) | |
7dcc9865 | 403 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 RH |
404 | break; |
405 | ||
9e0665bc AM |
406 | case TCOMMON_SECTION: |
407 | if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) | |
7dcc9865 | 408 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 RH |
409 | break; |
410 | ||
411 | default: | |
cac58fa6 | 412 | abort (); |
252b5132 | 413 | } |
28e4f854 | 414 | |
7dcc9865 | 415 | symbol_set_frag (symbolP, frag_now); |
252b5132 RH |
416 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
417 | (offsetT) size, (char *) 0); | |
418 | *pfrag = 0; | |
419 | S_SET_SIZE (symbolP, size); | |
28e4f854 | 420 | |
252b5132 RH |
421 | switch (area) |
422 | { | |
9e0665bc AM |
423 | case SCOMMON_SECTION: |
424 | S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); | |
252b5132 | 425 | break; |
28e4f854 | 426 | |
9e0665bc AM |
427 | case ZCOMMON_SECTION: |
428 | S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); | |
252b5132 | 429 | break; |
28e4f854 | 430 | |
9e0665bc AM |
431 | case TCOMMON_SECTION: |
432 | S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); | |
252b5132 | 433 | break; |
28e4f854 | 434 | |
252b5132 | 435 | default: |
28e4f854 | 436 | abort (); |
252b5132 | 437 | } |
28e4f854 | 438 | |
252b5132 | 439 | S_CLEAR_EXTERNAL (symbolP); |
28e4f854 | 440 | obj_elf_section_change_hook (); |
252b5132 RH |
441 | subseg_set (old_sec, old_subsec); |
442 | } | |
443 | else | |
444 | { | |
ec178e1b AM |
445 | segT old_sec; |
446 | int old_subsec; | |
86aba9db | 447 | |
252b5132 | 448 | allocate_common: |
ec178e1b AM |
449 | old_sec = now_seg; |
450 | old_subsec = now_subseg; | |
86aba9db | 451 | |
252b5132 RH |
452 | S_SET_VALUE (symbolP, (valueT) size); |
453 | S_SET_ALIGN (symbolP, temp); | |
454 | S_SET_EXTERNAL (symbolP); | |
28e4f854 | 455 | |
252b5132 RH |
456 | switch (area) |
457 | { | |
9e0665bc AM |
458 | case SCOMMON_SECTION: |
459 | case ZCOMMON_SECTION: | |
460 | case TCOMMON_SECTION: | |
461 | do_v850_seg (area, 0); | |
462 | S_SET_SEGMENT (symbolP, v850_seg_table[area].s); | |
252b5132 | 463 | break; |
28e4f854 | 464 | |
252b5132 | 465 | default: |
28e4f854 | 466 | abort (); |
252b5132 | 467 | } |
86aba9db NC |
468 | |
469 | obj_elf_section_change_hook (); | |
470 | subseg_set (old_sec, old_subsec); | |
252b5132 RH |
471 | } |
472 | } | |
473 | else | |
474 | { | |
475 | input_line_pointer++; | |
28e4f854 | 476 | |
252b5132 RH |
477 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ |
478 | if (*input_line_pointer == '.') | |
479 | input_line_pointer++; | |
28e4f854 | 480 | |
252b5132 RH |
481 | /* @@ Some say data, some say bss. */ |
482 | if (strncmp (input_line_pointer, "bss\"", 4) | |
483 | && strncmp (input_line_pointer, "data\"", 5)) | |
484 | { | |
485 | while (*--input_line_pointer != '"') | |
486 | ; | |
487 | input_line_pointer--; | |
488 | goto bad_common_segment; | |
489 | } | |
ea1562b3 | 490 | |
252b5132 RH |
491 | while (*input_line_pointer++ != '"') |
492 | ; | |
ea1562b3 | 493 | |
252b5132 RH |
494 | goto allocate_common; |
495 | } | |
496 | ||
fed9b18a | 497 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
498 | |
499 | demand_empty_rest_of_line (); | |
500 | return; | |
501 | ||
502 | { | |
503 | bad_common_segment: | |
504 | p = input_line_pointer; | |
505 | while (*p && *p != '\n') | |
506 | p++; | |
507 | c = *p; | |
508 | *p = '\0'; | |
509 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
510 | *p = c; | |
511 | input_line_pointer = p; | |
512 | ignore_rest_of_line (); | |
513 | return; | |
514 | } | |
515 | } | |
516 | ||
9e0665bc | 517 | static void |
ea1562b3 | 518 | set_machine (int number) |
252b5132 RH |
519 | { |
520 | machine = number; | |
de863c74 | 521 | bfd_set_arch_mach (stdoutput, v850_target_arch, machine); |
252b5132 RH |
522 | |
523 | switch (machine) | |
524 | { | |
1cd986c5 NC |
525 | case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; |
526 | case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; | |
527 | case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; | |
528 | case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; | |
529 | case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; | |
530 | case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; | |
252b5132 RH |
531 | } |
532 | } | |
533 | ||
86aba9db | 534 | static void |
ea1562b3 | 535 | v850_longcode (int type) |
86aba9db NC |
536 | { |
537 | expressionS ex; | |
538 | ||
539 | if (! v850_relax) | |
540 | { | |
541 | if (type == 1) | |
20203fb9 | 542 | as_warn (_(".longcall pseudo-op seen when not relaxing")); |
86aba9db | 543 | else |
20203fb9 | 544 | as_warn (_(".longjump pseudo-op seen when not relaxing")); |
86aba9db NC |
545 | } |
546 | ||
547 | expression (&ex); | |
548 | ||
549 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
550 | { | |
20203fb9 | 551 | as_bad (_("bad .longcall format")); |
86aba9db NC |
552 | ignore_rest_of_line (); |
553 | ||
554 | return; | |
555 | } | |
556 | ||
ec178e1b | 557 | if (type == 1) |
86aba9db NC |
558 | fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, |
559 | BFD_RELOC_V850_LONGCALL); | |
560 | else | |
561 | fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, | |
562 | BFD_RELOC_V850_LONGJUMP); | |
563 | ||
564 | demand_empty_rest_of_line (); | |
565 | } | |
566 | ||
252b5132 | 567 | /* The target specific pseudo-ops which we support. */ |
77c6dd37 NC |
568 | const pseudo_typeS md_pseudo_table[] = |
569 | { | |
9e0665bc AM |
570 | { "sdata", v850_seg, SDATA_SECTION }, |
571 | { "tdata", v850_seg, TDATA_SECTION }, | |
572 | { "zdata", v850_seg, ZDATA_SECTION }, | |
573 | { "sbss", v850_seg, SBSS_SECTION }, | |
574 | { "tbss", v850_seg, TBSS_SECTION }, | |
575 | { "zbss", v850_seg, ZBSS_SECTION }, | |
576 | { "rosdata", v850_seg, ROSDATA_SECTION }, | |
577 | { "rozdata", v850_seg, ROZDATA_SECTION }, | |
578 | { "bss", v850_seg, BSS_SECTION }, | |
579 | { "offset", v850_offset, 0 }, | |
580 | { "word", cons, 4 }, | |
581 | { "zcomm", v850_comm, ZCOMMON_SECTION }, | |
582 | { "scomm", v850_comm, SCOMMON_SECTION }, | |
583 | { "tcomm", v850_comm, TCOMMON_SECTION }, | |
584 | { "v850", set_machine, 0 }, | |
585 | { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, | |
586 | { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, | |
587 | { "v850e", set_machine, bfd_mach_v850e }, | |
1cd986c5 NC |
588 | { "v850e1", set_machine, bfd_mach_v850e1 }, |
589 | { "v850e2", set_machine, bfd_mach_v850e2 }, | |
590 | { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, | |
ec178e1b AM |
591 | { "longcall", v850_longcode, 1 }, |
592 | { "longjump", v850_longcode, 2 }, | |
9e0665bc | 593 | { NULL, NULL, 0 } |
252b5132 RH |
594 | }; |
595 | ||
596 | /* Opcode hash table. */ | |
597 | static struct hash_control *v850_hash; | |
598 | ||
28e4f854 | 599 | /* This table is sorted. Suitable for searching by a binary search. */ |
77c6dd37 NC |
600 | static const struct reg_name pre_defined_registers[] = |
601 | { | |
1cd986c5 NC |
602 | { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ |
603 | { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ | |
604 | { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ | |
605 | { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ | |
606 | { "r0", 0, PROCESSOR_ALL }, | |
607 | { "r1", 1, PROCESSOR_ALL }, | |
608 | { "r10", 10, PROCESSOR_ALL }, | |
609 | { "r11", 11, PROCESSOR_ALL }, | |
610 | { "r12", 12, PROCESSOR_ALL }, | |
611 | { "r13", 13, PROCESSOR_ALL }, | |
612 | { "r14", 14, PROCESSOR_ALL }, | |
613 | { "r15", 15, PROCESSOR_ALL }, | |
614 | { "r16", 16, PROCESSOR_ALL }, | |
615 | { "r17", 17, PROCESSOR_ALL }, | |
616 | { "r18", 18, PROCESSOR_ALL }, | |
617 | { "r19", 19, PROCESSOR_ALL }, | |
618 | { "r2", 2, PROCESSOR_ALL }, | |
619 | { "r20", 20, PROCESSOR_ALL }, | |
620 | { "r21", 21, PROCESSOR_ALL }, | |
621 | { "r22", 22, PROCESSOR_ALL }, | |
622 | { "r23", 23, PROCESSOR_ALL }, | |
623 | { "r24", 24, PROCESSOR_ALL }, | |
624 | { "r25", 25, PROCESSOR_ALL }, | |
625 | { "r26", 26, PROCESSOR_ALL }, | |
626 | { "r27", 27, PROCESSOR_ALL }, | |
627 | { "r28", 28, PROCESSOR_ALL }, | |
628 | { "r29", 29, PROCESSOR_ALL }, | |
629 | { "r3", 3, PROCESSOR_ALL }, | |
630 | { "r30", 30, PROCESSOR_ALL }, | |
631 | { "r31", 31, PROCESSOR_ALL }, | |
632 | { "r4", 4, PROCESSOR_ALL }, | |
633 | { "r5", 5, PROCESSOR_ALL }, | |
634 | { "r6", 6, PROCESSOR_ALL }, | |
635 | { "r7", 7, PROCESSOR_ALL }, | |
636 | { "r8", 8, PROCESSOR_ALL }, | |
637 | { "r9", 9, PROCESSOR_ALL }, | |
638 | { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ | |
639 | { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ | |
640 | { "zero", 0, PROCESSOR_ALL }, | |
252b5132 | 641 | }; |
252b5132 | 642 | |
28e4f854 KH |
643 | #define REG_NAME_CNT \ |
644 | (sizeof (pre_defined_registers) / sizeof (struct reg_name)) | |
252b5132 | 645 | |
77c6dd37 NC |
646 | static const struct reg_name system_registers[] = |
647 | { | |
1cd986c5 NC |
648 | { "asid", 23, PROCESSOR_NOT_V850 }, |
649 | { "bpam", 25, PROCESSOR_NOT_V850 }, | |
650 | { "bpav", 24, PROCESSOR_NOT_V850 }, | |
651 | { "bpc", 22, PROCESSOR_NOT_V850 }, | |
652 | { "bpdm", 27, PROCESSOR_NOT_V850 }, | |
653 | { "bpdv", 26, PROCESSOR_NOT_V850 }, | |
654 | { "bsel", 31, PROCESSOR_V850E2_ALL }, | |
655 | { "cfg", 7, PROCESSOR_V850E2V3 }, | |
656 | { "ctbp", 20, PROCESSOR_NOT_V850 }, | |
657 | { "ctpc", 16, PROCESSOR_NOT_V850 }, | |
658 | { "ctpsw", 17, PROCESSOR_NOT_V850 }, | |
659 | { "dbic", 15, PROCESSOR_V850E2_ALL }, | |
660 | { "dbpc", 18, PROCESSOR_NOT_V850 }, | |
661 | { "dbpsw", 19, PROCESSOR_NOT_V850 }, | |
662 | { "dbwr", 30, PROCESSOR_V850E2_ALL }, | |
663 | { "dir", 21, PROCESSOR_NOT_V850 }, | |
664 | { "dpa0l", 16, PROCESSOR_V850E2V3 }, | |
665 | { "dpa0u", 17, PROCESSOR_V850E2V3 }, | |
666 | { "dpa1l", 18, PROCESSOR_V850E2V3 }, | |
667 | { "dpa1u", 19, PROCESSOR_V850E2V3 }, | |
668 | { "dpa2l", 20, PROCESSOR_V850E2V3 }, | |
669 | { "dpa2u", 21, PROCESSOR_V850E2V3 }, | |
670 | { "dpa3l", 22, PROCESSOR_V850E2V3 }, | |
671 | { "dpa3u", 23, PROCESSOR_V850E2V3 }, | |
672 | { "dpa4l", 24, PROCESSOR_V850E2V3 }, | |
673 | { "dpa4u", 25, PROCESSOR_V850E2V3 }, | |
674 | { "dpa5l", 26, PROCESSOR_V850E2V3 }, | |
675 | { "dpa5u", 27, PROCESSOR_V850E2V3 }, | |
676 | { "ecr", 4, PROCESSOR_ALL }, | |
677 | { "eh_base", 3, PROCESSOR_V850E2V3 }, | |
678 | { "eh_cfg", 1, PROCESSOR_V850E2V3 }, | |
679 | { "eh_reset", 2, PROCESSOR_V850E2V3 }, | |
680 | { "eiic", 13, PROCESSOR_V850E2_ALL }, | |
681 | { "eipc", 0, PROCESSOR_ALL }, | |
682 | { "eipsw", 1, PROCESSOR_ALL }, | |
683 | { "eiwr", 28, PROCESSOR_V850E2_ALL }, | |
684 | { "feic", 14, PROCESSOR_V850E2_ALL }, | |
685 | { "fepc", 2, PROCESSOR_ALL }, | |
686 | { "fepsw", 3, PROCESSOR_ALL }, | |
687 | { "fewr", 29, PROCESSOR_V850E2_ALL }, | |
688 | { "fpcc", 9, PROCESSOR_V850E2V3 }, | |
689 | { "fpcfg", 10, PROCESSOR_V850E2V3 }, | |
690 | { "fpec", 11, PROCESSOR_V850E2V3 }, | |
691 | { "fpepc", 7, PROCESSOR_V850E2V3 }, | |
692 | { "fpspc", 27, PROCESSOR_V850E2V3 }, | |
693 | { "fpsr", 6, PROCESSOR_V850E2V3 }, | |
694 | { "fpst", 8, PROCESSOR_V850E2V3 }, | |
695 | { "ipa0l", 6, PROCESSOR_V850E2V3 }, | |
696 | { "ipa0u", 7, PROCESSOR_V850E2V3 }, | |
697 | { "ipa1l", 8, PROCESSOR_V850E2V3 }, | |
698 | { "ipa1u", 9, PROCESSOR_V850E2V3 }, | |
699 | { "ipa2l", 10, PROCESSOR_V850E2V3 }, | |
700 | { "ipa2u", 11, PROCESSOR_V850E2V3 }, | |
701 | { "ipa3l", 12, PROCESSOR_V850E2V3 }, | |
702 | { "ipa3u", 13, PROCESSOR_V850E2V3 }, | |
703 | { "ipa4l", 14, PROCESSOR_V850E2V3 }, | |
704 | { "ipa4u", 15, PROCESSOR_V850E2V3 }, | |
705 | { "mca", 24, PROCESSOR_V850E2V3 }, | |
706 | { "mcc", 26, PROCESSOR_V850E2V3 }, | |
707 | { "mcr", 27, PROCESSOR_V850E2V3 }, | |
708 | { "mcs", 25, PROCESSOR_V850E2V3 }, | |
709 | { "mpc", 1, PROCESSOR_V850E2V3 }, | |
710 | { "mpm", 0, PROCESSOR_V850E2V3 }, | |
711 | { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3 }, | |
712 | { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3 }, | |
713 | { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3 }, | |
714 | { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3 }, | |
715 | { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3 }, | |
716 | { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3 }, | |
717 | { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3 }, | |
718 | { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3 }, | |
719 | { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3 }, | |
720 | { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3 }, | |
721 | { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3 }, | |
722 | { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3 }, | |
723 | { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3 }, | |
724 | { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3 }, | |
725 | { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3 }, | |
726 | { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3 }, | |
727 | { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3 }, | |
728 | { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3 }, | |
729 | { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3 }, | |
730 | { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3 }, | |
731 | { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3 }, | |
732 | { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3 }, | |
733 | { "mpu10_mpc", 1, PROCESSOR_V850E2V3 }, | |
734 | { "mpu10_mpm", 0, PROCESSOR_V850E2V3 }, | |
735 | { "mpu10_tid", 2, PROCESSOR_V850E2V3 }, | |
736 | { "mpu10_vmadr", 5, PROCESSOR_V850E2V3 }, | |
737 | { "mpu10_vmecr", 3, PROCESSOR_V850E2V3 }, | |
738 | { "mpu10_vmtid", 4, PROCESSOR_V850E2V3 }, | |
739 | { "pid", 6, PROCESSOR_V850E2V3 }, | |
740 | { "pmcr0", 4, PROCESSOR_V850E2V3 }, | |
741 | { "pmis2", 14, PROCESSOR_V850E2V3 }, | |
742 | { "psw", 5, PROCESSOR_ALL }, | |
743 | { "scbp", 12, PROCESSOR_V850E2V3 }, | |
744 | { "sccfg", 11, PROCESSOR_V850E2V3 }, | |
745 | { "sr0", 0, PROCESSOR_ALL }, | |
746 | { "sr1", 1, PROCESSOR_ALL }, | |
747 | { "sr10", 10, PROCESSOR_ALL }, | |
748 | { "sr11", 11, PROCESSOR_ALL }, | |
749 | { "sr12", 12, PROCESSOR_ALL }, | |
750 | { "sr13", 13, PROCESSOR_ALL }, | |
751 | { "sr14", 14, PROCESSOR_ALL }, | |
752 | { "sr15", 15, PROCESSOR_ALL }, | |
753 | { "sr16", 16, PROCESSOR_ALL }, | |
754 | { "sr17", 17, PROCESSOR_ALL }, | |
755 | { "sr18", 18, PROCESSOR_ALL }, | |
756 | { "sr19", 19, PROCESSOR_ALL }, | |
757 | { "sr2", 2, PROCESSOR_ALL }, | |
758 | { "sr20", 20, PROCESSOR_ALL }, | |
759 | { "sr21", 21, PROCESSOR_ALL }, | |
760 | { "sr22", 22, PROCESSOR_ALL }, | |
761 | { "sr23", 23, PROCESSOR_ALL }, | |
762 | { "sr24", 24, PROCESSOR_ALL }, | |
763 | { "sr25", 25, PROCESSOR_ALL }, | |
764 | { "sr26", 26, PROCESSOR_ALL }, | |
765 | { "sr27", 27, PROCESSOR_ALL }, | |
766 | { "sr28", 28, PROCESSOR_ALL }, | |
767 | { "sr29", 29, PROCESSOR_ALL }, | |
768 | { "sr3", 3, PROCESSOR_ALL }, | |
769 | { "sr30", 30, PROCESSOR_ALL }, | |
770 | { "sr31", 31, PROCESSOR_ALL }, | |
771 | { "sr4", 4, PROCESSOR_ALL }, | |
772 | { "sr5", 5, PROCESSOR_ALL }, | |
773 | { "sr6", 6, PROCESSOR_ALL }, | |
774 | { "sr7", 7, PROCESSOR_ALL }, | |
775 | { "sr8", 8, PROCESSOR_ALL }, | |
776 | { "sr9", 9, PROCESSOR_ALL }, | |
777 | { "sw_base", 3, PROCESSOR_V850E2V3 }, | |
778 | { "sw_cfg", 1, PROCESSOR_V850E2V3 }, | |
779 | { "sw_ctl", 0, PROCESSOR_V850E2V3 }, | |
780 | { "tid", 2, PROCESSOR_V850E2V3 }, | |
781 | { "vmadr", 6, PROCESSOR_V850E2V3 }, | |
782 | { "vmecr", 4, PROCESSOR_V850E2V3 }, | |
783 | { "vmtid", 5, PROCESSOR_V850E2V3 }, | |
784 | { "vsadr", 2, PROCESSOR_V850E2V3 }, | |
785 | { "vsecr", 0, PROCESSOR_V850E2V3 }, | |
786 | { "vstid", 1, PROCESSOR_V850E2V3 }, | |
252b5132 | 787 | }; |
28e4f854 KH |
788 | |
789 | #define SYSREG_NAME_CNT \ | |
790 | (sizeof (system_registers) / sizeof (struct reg_name)) | |
252b5132 | 791 | |
252b5132 | 792 | |
77c6dd37 NC |
793 | static const struct reg_name cc_names[] = |
794 | { | |
1cd986c5 NC |
795 | { "c", 0x1, PROCESSOR_ALL }, |
796 | { "e", 0x2, PROCESSOR_ALL }, | |
797 | { "ge", 0xe, PROCESSOR_ALL }, | |
798 | { "gt", 0xf, PROCESSOR_ALL }, | |
799 | { "h", 0xb, PROCESSOR_ALL }, | |
800 | { "l", 0x1, PROCESSOR_ALL }, | |
801 | { "le", 0x7, PROCESSOR_ALL }, | |
802 | { "lt", 0x6, PROCESSOR_ALL }, | |
803 | { "n", 0x4, PROCESSOR_ALL }, | |
804 | { "nc", 0x9, PROCESSOR_ALL }, | |
805 | { "ne", 0xa, PROCESSOR_ALL }, | |
806 | { "nh", 0x3, PROCESSOR_ALL }, | |
807 | { "nl", 0x9, PROCESSOR_ALL }, | |
808 | { "ns", 0xc, PROCESSOR_ALL }, | |
809 | { "nv", 0x8, PROCESSOR_ALL }, | |
810 | { "nz", 0xa, PROCESSOR_ALL }, | |
811 | { "p", 0xc, PROCESSOR_ALL }, | |
812 | { "s", 0x4, PROCESSOR_ALL }, | |
813 | #define COND_SA_NUM 0xd | |
814 | { "sa", COND_SA_NUM, PROCESSOR_ALL }, | |
815 | { "t", 0x5, PROCESSOR_ALL }, | |
816 | { "v", 0x0, PROCESSOR_ALL }, | |
817 | { "z", 0x2, PROCESSOR_ALL }, | |
252b5132 | 818 | }; |
252b5132 | 819 | |
28e4f854 KH |
820 | #define CC_NAME_CNT \ |
821 | (sizeof (cc_names) / sizeof (struct reg_name)) | |
822 | ||
1cd986c5 NC |
823 | static const struct reg_name float_cc_names[] = |
824 | { | |
825 | { "eq", 0x2, PROCESSOR_V850E2V3 }, /* true. */ | |
826 | { "f", 0x0, PROCESSOR_V850E2V3 }, /* true. */ | |
827 | { "ge", 0xd, PROCESSOR_V850E2V3 }, /* false. */ | |
828 | { "gl", 0xb, PROCESSOR_V850E2V3 }, /* false. */ | |
829 | { "gle", 0x9, PROCESSOR_V850E2V3 }, /* false. */ | |
830 | { "gt", 0xf, PROCESSOR_V850E2V3 }, /* false. */ | |
831 | { "le", 0xe, PROCESSOR_V850E2V3 }, /* true. */ | |
832 | { "lt", 0xc, PROCESSOR_V850E2V3 }, /* true. */ | |
833 | { "neq", 0x2, PROCESSOR_V850E2V3 }, /* false. */ | |
834 | { "nge", 0xd, PROCESSOR_V850E2V3 }, /* true. */ | |
835 | { "ngl", 0xb, PROCESSOR_V850E2V3 }, /* true. */ | |
836 | { "ngle",0x9, PROCESSOR_V850E2V3 }, /* true. */ | |
837 | { "ngt", 0xf, PROCESSOR_V850E2V3 }, /* true. */ | |
838 | { "nle", 0xe, PROCESSOR_V850E2V3 }, /* false. */ | |
839 | { "nlt", 0xc, PROCESSOR_V850E2V3 }, /* false. */ | |
840 | { "oge", 0x5, PROCESSOR_V850E2V3 }, /* false. */ | |
841 | { "ogl", 0x3, PROCESSOR_V850E2V3 }, /* false. */ | |
842 | { "ogt", 0x7, PROCESSOR_V850E2V3 }, /* false. */ | |
843 | { "ole", 0x6, PROCESSOR_V850E2V3 }, /* true. */ | |
844 | { "olt", 0x4, PROCESSOR_V850E2V3 }, /* true. */ | |
845 | { "or", 0x1, PROCESSOR_V850E2V3 }, /* false. */ | |
846 | { "seq", 0xa, PROCESSOR_V850E2V3 }, /* true. */ | |
847 | { "sf", 0x8, PROCESSOR_V850E2V3 }, /* true. */ | |
848 | { "sne", 0xa, PROCESSOR_V850E2V3 }, /* false. */ | |
849 | { "st", 0x8, PROCESSOR_V850E2V3 }, /* false. */ | |
850 | { "t", 0x0, PROCESSOR_V850E2V3 }, /* false. */ | |
851 | { "ueq", 0x3, PROCESSOR_V850E2V3 }, /* true. */ | |
852 | { "uge", 0x4, PROCESSOR_V850E2V3 }, /* false. */ | |
853 | { "ugt", 0x6, PROCESSOR_V850E2V3 }, /* false. */ | |
854 | { "ule", 0x7, PROCESSOR_V850E2V3 }, /* true. */ | |
855 | { "ult", 0x5, PROCESSOR_V850E2V3 }, /* true. */ | |
856 | { "un", 0x1, PROCESSOR_V850E2V3 }, /* true. */ | |
857 | }; | |
858 | ||
859 | #define FLOAT_CC_NAME_CNT \ | |
860 | (sizeof (float_cc_names) / sizeof (struct reg_name)) | |
861 | ||
28e4f854 KH |
862 | /* Do a binary search of the given register table to see if NAME is a |
863 | valid regiter name. Return the register number from the array on | |
864 | success, or -1 on failure. */ | |
252b5132 RH |
865 | |
866 | static int | |
ea1562b3 NC |
867 | reg_name_search (const struct reg_name *regs, |
868 | int regcount, | |
869 | const char *name, | |
870 | bfd_boolean accept_numbers) | |
252b5132 RH |
871 | { |
872 | int middle, low, high; | |
873 | int cmp; | |
28e4f854 | 874 | symbolS *symbolP; |
252b5132 RH |
875 | |
876 | /* If the register name is a symbol, then evaluate it. */ | |
877 | if ((symbolP = symbol_find (name)) != NULL) | |
878 | { | |
879 | /* If the symbol is an alias for another name then use that. | |
880 | If the symbol is an alias for a number, then return the number. */ | |
a77f5182 | 881 | if (symbol_equated_p (symbolP)) |
ea1562b3 NC |
882 | name |
883 | = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); | |
252b5132 RH |
884 | else if (accept_numbers) |
885 | { | |
886 | int reg = S_GET_VALUE (symbolP); | |
1cd986c5 | 887 | return reg; |
252b5132 RH |
888 | } |
889 | ||
890 | /* Otherwise drop through and try parsing name normally. */ | |
891 | } | |
28e4f854 | 892 | |
252b5132 RH |
893 | low = 0; |
894 | high = regcount - 1; | |
895 | ||
896 | do | |
897 | { | |
898 | middle = (low + high) / 2; | |
899 | cmp = strcasecmp (name, regs[middle].name); | |
900 | if (cmp < 0) | |
901 | high = middle - 1; | |
902 | else if (cmp > 0) | |
903 | low = middle + 1; | |
904 | else | |
1cd986c5 NC |
905 | return ((regs[middle].processors & processor_mask) |
906 | ? regs[middle].value | |
907 | : -1); | |
252b5132 RH |
908 | } |
909 | while (low <= high); | |
910 | return -1; | |
911 | } | |
912 | ||
252b5132 | 913 | /* Summary of register_name(). |
ec178e1b | 914 | |
77c6dd37 | 915 | in: Input_line_pointer points to 1st char of operand. |
ec178e1b | 916 | |
77c6dd37 NC |
917 | out: An expressionS. |
918 | The operand may have been a register: in this case, X_op == O_register, | |
919 | X_add_number is set to the register number, and truth is returned. | |
920 | Input_line_pointer->(next non-blank) char after operand, or is in | |
921 | its original state. */ | |
28e4f854 | 922 | |
b34976b6 | 923 | static bfd_boolean |
ea1562b3 | 924 | register_name (expressionS *expressionP) |
252b5132 | 925 | { |
28e4f854 KH |
926 | int reg_number; |
927 | char *name; | |
928 | char *start; | |
929 | char c; | |
252b5132 | 930 | |
28e4f854 | 931 | /* Find the spelling of the operand. */ |
252b5132 RH |
932 | start = name = input_line_pointer; |
933 | ||
934 | c = get_symbol_end (); | |
935 | ||
936 | reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, | |
937 | name, FALSE); | |
938 | ||
28e4f854 KH |
939 | /* Put back the delimiting char. */ |
940 | *input_line_pointer = c; | |
941 | ||
1cd986c5 NC |
942 | expressionP->X_add_symbol = NULL; |
943 | expressionP->X_op_symbol = NULL; | |
944 | ||
28e4f854 KH |
945 | /* Look to see if it's in the register table. */ |
946 | if (reg_number >= 0) | |
252b5132 | 947 | { |
ec178e1b | 948 | expressionP->X_op = O_register; |
252b5132 RH |
949 | expressionP->X_add_number = reg_number; |
950 | ||
b34976b6 | 951 | return TRUE; |
252b5132 | 952 | } |
28e4f854 | 953 | |
1cd986c5 NC |
954 | /* Reset the line as if we had not done anything. */ |
955 | input_line_pointer = start; | |
956 | ||
957 | expressionP->X_op = O_illegal; | |
958 | ||
959 | return FALSE; | |
252b5132 RH |
960 | } |
961 | ||
962 | /* Summary of system_register_name(). | |
ec178e1b | 963 | |
77c6dd37 | 964 | in: INPUT_LINE_POINTER points to 1st char of operand. |
ec178e1b AM |
965 | EXPRESSIONP points to an expression structure to be filled in. |
966 | ACCEPT_NUMBERS is true iff numerical register names may be used. | |
ec178e1b | 967 | |
77c6dd37 NC |
968 | out: An expressionS structure in expressionP. |
969 | The operand may have been a register: in this case, X_op == O_register, | |
970 | X_add_number is set to the register number, and truth is returned. | |
971 | Input_line_pointer->(next non-blank) char after operand, or is in | |
972 | its original state. */ | |
28e4f854 | 973 | |
b34976b6 | 974 | static bfd_boolean |
ea1562b3 | 975 | system_register_name (expressionS *expressionP, |
1cd986c5 | 976 | bfd_boolean accept_numbers) |
252b5132 | 977 | { |
28e4f854 KH |
978 | int reg_number; |
979 | char *name; | |
980 | char *start; | |
981 | char c; | |
252b5132 | 982 | |
28e4f854 | 983 | /* Find the spelling of the operand. */ |
252b5132 RH |
984 | start = name = input_line_pointer; |
985 | ||
986 | c = get_symbol_end (); | |
987 | reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, | |
988 | accept_numbers); | |
989 | ||
28e4f854 KH |
990 | /* Put back the delimiting char. */ |
991 | *input_line_pointer = c; | |
992 | ||
252b5132 RH |
993 | if (reg_number < 0 |
994 | && accept_numbers) | |
995 | { | |
28e4f854 KH |
996 | /* Reset input_line pointer. */ |
997 | input_line_pointer = start; | |
252b5132 | 998 | |
3882b010 | 999 | if (ISDIGIT (*input_line_pointer)) |
252b5132 | 1000 | { |
1cd986c5 | 1001 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); |
252b5132 RH |
1002 | } |
1003 | } | |
28e4f854 | 1004 | |
1cd986c5 NC |
1005 | expressionP->X_add_symbol = NULL; |
1006 | expressionP->X_op_symbol = NULL; | |
1007 | ||
28e4f854 KH |
1008 | /* Look to see if it's in the register table. */ |
1009 | if (reg_number >= 0) | |
252b5132 | 1010 | { |
ec178e1b | 1011 | expressionP->X_op = O_register; |
252b5132 RH |
1012 | expressionP->X_add_number = reg_number; |
1013 | ||
b34976b6 | 1014 | return TRUE; |
252b5132 | 1015 | } |
28e4f854 | 1016 | |
1cd986c5 NC |
1017 | /* Reset the line as if we had not done anything. */ |
1018 | input_line_pointer = start; | |
1019 | ||
1020 | expressionP->X_op = O_illegal; | |
1021 | ||
1022 | return FALSE; | |
252b5132 RH |
1023 | } |
1024 | ||
1025 | /* Summary of cc_name(). | |
ec178e1b | 1026 | |
77c6dd37 | 1027 | in: INPUT_LINE_POINTER points to 1st char of operand. |
ec178e1b | 1028 | |
77c6dd37 NC |
1029 | out: An expressionS. |
1030 | The operand may have been a register: in this case, X_op == O_register, | |
1031 | X_add_number is set to the register number, and truth is returned. | |
1032 | Input_line_pointer->(next non-blank) char after operand, or is in | |
1033 | its original state. */ | |
28e4f854 | 1034 | |
b34976b6 | 1035 | static bfd_boolean |
1cd986c5 NC |
1036 | cc_name (expressionS *expressionP, |
1037 | bfd_boolean accept_numbers) | |
252b5132 | 1038 | { |
28e4f854 KH |
1039 | int reg_number; |
1040 | char *name; | |
1041 | char *start; | |
1042 | char c; | |
252b5132 | 1043 | |
28e4f854 | 1044 | /* Find the spelling of the operand. */ |
252b5132 RH |
1045 | start = name = input_line_pointer; |
1046 | ||
1047 | c = get_symbol_end (); | |
1cd986c5 | 1048 | reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); |
252b5132 | 1049 | |
28e4f854 KH |
1050 | /* Put back the delimiting char. */ |
1051 | *input_line_pointer = c; | |
1052 | ||
1cd986c5 NC |
1053 | if (reg_number < 0 |
1054 | && accept_numbers) | |
1055 | { | |
1056 | /* Reset input_line pointer. */ | |
1057 | input_line_pointer = start; | |
1058 | ||
1059 | if (ISDIGIT (*input_line_pointer)) | |
1060 | { | |
1061 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | expressionP->X_add_symbol = NULL; | |
1066 | expressionP->X_op_symbol = NULL; | |
1067 | ||
28e4f854 KH |
1068 | /* Look to see if it's in the register table. */ |
1069 | if (reg_number >= 0) | |
252b5132 | 1070 | { |
ec178e1b | 1071 | expressionP->X_op = O_constant; |
252b5132 RH |
1072 | expressionP->X_add_number = reg_number; |
1073 | ||
b34976b6 | 1074 | return TRUE; |
252b5132 | 1075 | } |
1cd986c5 NC |
1076 | |
1077 | /* Reset the line as if we had not done anything. */ | |
1078 | input_line_pointer = start; | |
1079 | ||
1080 | expressionP->X_op = O_illegal; | |
1081 | expressionP->X_add_number = 0; | |
1082 | ||
1083 | return FALSE; | |
1084 | } | |
1085 | ||
1086 | static bfd_boolean | |
1087 | float_cc_name (expressionS *expressionP, | |
1088 | bfd_boolean accept_numbers) | |
1089 | { | |
1090 | int reg_number; | |
1091 | char *name; | |
1092 | char *start; | |
1093 | char c; | |
1094 | ||
1095 | /* Find the spelling of the operand. */ | |
1096 | start = name = input_line_pointer; | |
1097 | ||
1098 | c = get_symbol_end (); | |
1099 | reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); | |
1100 | ||
1101 | /* Put back the delimiting char. */ | |
1102 | *input_line_pointer = c; | |
1103 | ||
1104 | if (reg_number < 0 | |
1105 | && accept_numbers) | |
252b5132 | 1106 | { |
1cd986c5 | 1107 | /* Reset input_line pointer. */ |
252b5132 | 1108 | input_line_pointer = start; |
28e4f854 | 1109 | |
1cd986c5 NC |
1110 | if (ISDIGIT (*input_line_pointer)) |
1111 | { | |
1112 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | expressionP->X_add_symbol = NULL; | |
1117 | expressionP->X_op_symbol = NULL; | |
1118 | ||
1119 | /* Look to see if it's in the register table. */ | |
1120 | if (reg_number >= 0) | |
1121 | { | |
1122 | expressionP->X_op = O_constant; | |
1123 | expressionP->X_add_number = reg_number; | |
1124 | ||
1125 | return TRUE; | |
252b5132 | 1126 | } |
1cd986c5 NC |
1127 | |
1128 | /* Reset the line as if we had not done anything. */ | |
1129 | input_line_pointer = start; | |
1130 | ||
1131 | expressionP->X_op = O_illegal; | |
1132 | expressionP->X_add_number = 0; | |
1133 | ||
1134 | return FALSE; | |
252b5132 RH |
1135 | } |
1136 | ||
1137 | static void | |
ea1562b3 | 1138 | skip_white_space (void) |
252b5132 | 1139 | { |
28e4f854 KH |
1140 | while (*input_line_pointer == ' ' |
1141 | || *input_line_pointer == '\t') | |
1142 | ++input_line_pointer; | |
252b5132 RH |
1143 | } |
1144 | ||
1145 | /* Summary of parse_register_list (). | |
ec178e1b | 1146 | |
77c6dd37 | 1147 | in: INPUT_LINE_POINTER points to 1st char of a list of registers. |
ec178e1b AM |
1148 | INSN is the partially constructed instruction. |
1149 | OPERAND is the operand being inserted. | |
1150 | ||
77c6dd37 | 1151 | out: NULL if the parse completed successfully, otherwise a |
ec178e1b AM |
1152 | pointer to an error message is returned. If the parse |
1153 | completes the correct bit fields in the instruction | |
1154 | will be filled in. | |
1155 | ||
77c6dd37 | 1156 | Parses register lists with the syntax: |
ec178e1b | 1157 | |
77c6dd37 NC |
1158 | { rX } |
1159 | { rX, rY } | |
1160 | { rX - rY } | |
1161 | { rX - rY, rZ } | |
1162 | etc | |
ec178e1b | 1163 | |
33b7f697 | 1164 | and also parses constant expressions whoes bits indicate the |
77c6dd37 | 1165 | registers in the lists. The LSB in the expression refers to |
33b7f697 | 1166 | the lowest numbered permissible register in the register list, |
77c6dd37 NC |
1167 | and so on upwards. System registers are considered to be very |
1168 | high numbers. */ | |
28e4f854 | 1169 | |
252b5132 | 1170 | static char * |
ea1562b3 NC |
1171 | parse_register_list (unsigned long *insn, |
1172 | const struct v850_operand *operand) | |
252b5132 | 1173 | { |
ea1562b3 NC |
1174 | static int type1_regs[32] = |
1175 | { | |
28e4f854 KH |
1176 | 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
1177 | 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 | |
1178 | }; | |
1cd986c5 | 1179 | |
28e4f854 | 1180 | int *regs; |
252b5132 RH |
1181 | expressionS exp; |
1182 | ||
28e4f854 | 1183 | /* Select a register array to parse. */ |
252b5132 RH |
1184 | switch (operand->shift) |
1185 | { | |
1186 | case 0xffe00001: regs = type1_regs; break; | |
252b5132 RH |
1187 | default: |
1188 | as_bad (_("unknown operand shift: %x\n"), operand->shift); | |
1189 | return _("internal failure in parse_register_list"); | |
1190 | } | |
1191 | ||
1192 | skip_white_space (); | |
1193 | ||
1194 | /* If the expression starts with a curly brace it is a register list. | |
1195 | Otherwise it is a constant expression, whoes bits indicate which | |
1196 | registers are to be included in the list. */ | |
28e4f854 | 1197 | if (*input_line_pointer != '{') |
252b5132 | 1198 | { |
252b5132 RH |
1199 | int reg; |
1200 | int i; | |
28e4f854 KH |
1201 | |
1202 | expression (&exp); | |
1203 | ||
252b5132 RH |
1204 | if (exp.X_op != O_constant) |
1205 | return _("constant expression or register list expected"); | |
1206 | ||
1207 | if (regs == type1_regs) | |
1208 | { | |
1209 | if (exp.X_add_number & 0xFFFFF000) | |
1210 | return _("high bits set in register list expression"); | |
28e4f854 KH |
1211 | |
1212 | for (reg = 20; reg < 32; reg++) | |
252b5132 RH |
1213 | if (exp.X_add_number & (1 << (reg - 20))) |
1214 | { | |
1215 | for (i = 0; i < 32; i++) | |
1216 | if (regs[i] == reg) | |
28e4f854 | 1217 | *insn |= (1 << i); |
252b5132 RH |
1218 | } |
1219 | } | |
252b5132 RH |
1220 | |
1221 | return NULL; | |
1222 | } | |
1223 | ||
28e4f854 | 1224 | input_line_pointer++; |
252b5132 RH |
1225 | |
1226 | /* Parse the register list until a terminator (closing curly brace or | |
1227 | new-line) is found. */ | |
1228 | for (;;) | |
1229 | { | |
1cd986c5 NC |
1230 | skip_white_space (); |
1231 | ||
28e4f854 | 1232 | if (register_name (&exp)) |
252b5132 | 1233 | { |
28e4f854 KH |
1234 | int i; |
1235 | ||
252b5132 RH |
1236 | /* Locate the given register in the list, and if it is there, |
1237 | insert the corresponding bit into the instruction. */ | |
1238 | for (i = 0; i < 32; i++) | |
1239 | { | |
28e4f854 | 1240 | if (regs[i] == exp.X_add_number) |
252b5132 | 1241 | { |
28e4f854 | 1242 | *insn |= (1 << i); |
252b5132 RH |
1243 | break; |
1244 | } | |
1245 | } | |
1246 | ||
1247 | if (i == 32) | |
77c6dd37 | 1248 | return _("illegal register included in list"); |
252b5132 | 1249 | } |
1cd986c5 | 1250 | else if (system_register_name (&exp, TRUE)) |
252b5132 RH |
1251 | { |
1252 | if (regs == type1_regs) | |
1253 | { | |
1254 | return _("system registers cannot be included in list"); | |
1255 | } | |
252b5132 | 1256 | } |
1cd986c5 NC |
1257 | |
1258 | if (*input_line_pointer == '}') | |
252b5132 | 1259 | { |
28e4f854 | 1260 | input_line_pointer++; |
252b5132 RH |
1261 | break; |
1262 | } | |
28e4f854 | 1263 | else if (*input_line_pointer == ',') |
252b5132 | 1264 | { |
28e4f854 | 1265 | input_line_pointer++; |
252b5132 RH |
1266 | continue; |
1267 | } | |
28e4f854 | 1268 | else if (*input_line_pointer == '-') |
252b5132 | 1269 | { |
28e4f854 KH |
1270 | /* We have encountered a range of registers: rX - rY. */ |
1271 | int j; | |
252b5132 RH |
1272 | expressionS exp2; |
1273 | ||
1274 | /* Skip the dash. */ | |
28e4f854 | 1275 | ++input_line_pointer; |
252b5132 RH |
1276 | |
1277 | /* Get the second register in the range. */ | |
28e4f854 | 1278 | if (! register_name (&exp2)) |
252b5132 RH |
1279 | { |
1280 | return _("second register should follow dash in register list"); | |
1cd986c5 NC |
1281 | } |
1282 | ||
1283 | if (exp.X_add_number > exp2.X_add_number) | |
1284 | { | |
5648d7c7 | 1285 | return _("second register should be greater than first register"); |
252b5132 RH |
1286 | } |
1287 | ||
1288 | /* Add the rest of the registers in the range. */ | |
1289 | for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) | |
1290 | { | |
28e4f854 KH |
1291 | int i; |
1292 | ||
252b5132 RH |
1293 | /* Locate the given register in the list, and if it is there, |
1294 | insert the corresponding bit into the instruction. */ | |
1295 | for (i = 0; i < 32; i++) | |
1296 | { | |
28e4f854 | 1297 | if (regs[i] == j) |
252b5132 | 1298 | { |
28e4f854 | 1299 | *insn |= (1 << i); |
252b5132 RH |
1300 | break; |
1301 | } | |
1302 | } | |
1303 | ||
1304 | if (i == 32) | |
1305 | return _("illegal register included in list"); | |
1306 | } | |
1cd986c5 NC |
1307 | |
1308 | exp = exp2; | |
252b5132 RH |
1309 | } |
1310 | else | |
77c6dd37 | 1311 | break; |
252b5132 RH |
1312 | } |
1313 | ||
1314 | return NULL; | |
1315 | } | |
1316 | ||
5a38dc70 | 1317 | const char *md_shortopts = "m:"; |
252b5132 | 1318 | |
ea1562b3 NC |
1319 | struct option md_longopts[] = |
1320 | { | |
1cd986c5 NC |
1321 | #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) |
1322 | {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, | |
1323 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) | |
1324 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, | |
252b5132 RH |
1325 | {NULL, no_argument, NULL, 0} |
1326 | }; | |
252b5132 | 1327 | |
28e4f854 | 1328 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1329 | |
1330 | void | |
ea1562b3 | 1331 | md_show_usage (FILE *stream) |
252b5132 RH |
1332 | { |
1333 | fprintf (stream, _(" V850 options:\n")); | |
1334 | fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); | |
1335 | fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); | |
1336 | fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); | |
1337 | fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); | |
8ad30312 | 1338 | fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); |
1cd986c5 NC |
1339 | fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); |
1340 | fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); | |
86aba9db | 1341 | fprintf (stream, _(" -mrelax Enable relaxation\n")); |
1cd986c5 NC |
1342 | fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); |
1343 | fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); | |
1344 | fprintf (stream, _(" -mextension enable extension opcode support\n")); | |
1345 | fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); | |
1346 | fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); | |
de863c74 NC |
1347 | fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n")); |
1348 | fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n")); | |
1349 | fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n")); | |
1350 | fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n")); | |
252b5132 RH |
1351 | } |
1352 | ||
1353 | int | |
ea1562b3 | 1354 | md_parse_option (int c, char *arg) |
252b5132 RH |
1355 | { |
1356 | if (c != 'm') | |
1cd986c5 NC |
1357 | { |
1358 | switch (c) | |
1359 | { | |
1360 | case OPTION_DISP_SIZE_DEFAULT_22: | |
1361 | default_disp_size = 22; | |
1362 | return 1; | |
1363 | ||
1364 | case OPTION_DISP_SIZE_DEFAULT_32: | |
1365 | default_disp_size = 32; | |
1366 | return 1; | |
1367 | } | |
1368 | return 0; | |
1369 | } | |
252b5132 RH |
1370 | |
1371 | if (strcmp (arg, "warn-signed-overflow") == 0) | |
329e276d NC |
1372 | warn_signed_overflows = TRUE; |
1373 | ||
252b5132 | 1374 | else if (strcmp (arg, "warn-unsigned-overflow") == 0) |
329e276d NC |
1375 | warn_unsigned_overflows = TRUE; |
1376 | ||
252b5132 RH |
1377 | else if (strcmp (arg, "v850") == 0) |
1378 | { | |
1379 | machine = 0; | |
1cd986c5 | 1380 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); |
252b5132 RH |
1381 | } |
1382 | else if (strcmp (arg, "v850e") == 0) | |
1383 | { | |
1384 | machine = bfd_mach_v850e; | |
1cd986c5 | 1385 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); |
252b5132 | 1386 | } |
8ad30312 NC |
1387 | else if (strcmp (arg, "v850e1") == 0) |
1388 | { | |
1389 | machine = bfd_mach_v850e1; | |
1cd986c5 | 1390 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); |
8ad30312 | 1391 | } |
1cd986c5 | 1392 | else if (strcmp (arg, "v850e2") == 0) |
252b5132 | 1393 | { |
1cd986c5 NC |
1394 | machine = bfd_mach_v850e2; |
1395 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); | |
1396 | } | |
1397 | else if (strcmp (arg, "v850e2v3") == 0) | |
1398 | { | |
1399 | machine = bfd_mach_v850e2v3; | |
1400 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); | |
1401 | } | |
1402 | else if (strcmp (arg, "extension") == 0) | |
1403 | { | |
5bb3703f | 1404 | processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS; |
1cd986c5 NC |
1405 | } |
1406 | else if (strcmp (arg, "no-bcond17") == 0) | |
1407 | { | |
1408 | no_bcond17 = 1; | |
1409 | } | |
1410 | else if (strcmp (arg, "no-stld23") == 0) | |
1411 | { | |
1412 | no_stld23 = 1; | |
252b5132 | 1413 | } |
86aba9db NC |
1414 | else if (strcmp (arg, "relax") == 0) |
1415 | v850_relax = 1; | |
de863c74 NC |
1416 | else if (strcmp (arg, "gcc-abi") == 0) |
1417 | { | |
1418 | v850_target_arch = bfd_arch_v850; | |
1419 | v850_target_format = "elf32-v850"; | |
1420 | } | |
1421 | else if (strcmp (arg, "rh850-abi") == 0) | |
1422 | { | |
1423 | v850_target_arch = bfd_arch_v850_rh850; | |
1424 | v850_target_format = "elf32-v850-rh850"; | |
1425 | } | |
1426 | else if (strcmp (arg, "8byte-align") == 0) | |
1427 | v850_e_flags |= EF_RH850_DATA_ALIGN8; | |
1428 | else if (strcmp (arg, "4byte-align") == 0) | |
1429 | v850_e_flags &= ~ EF_RH850_DATA_ALIGN8; | |
252b5132 | 1430 | else |
329e276d | 1431 | return 0; |
28e4f854 | 1432 | |
252b5132 RH |
1433 | return 1; |
1434 | } | |
1435 | ||
1436 | symbolS * | |
ea1562b3 | 1437 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
1438 | { |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | char * | |
ea1562b3 | 1443 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 1444 | { |
499ac353 | 1445 | return ieee_md_atof (type, litp, sizep, FALSE); |
252b5132 RH |
1446 | } |
1447 | ||
252b5132 | 1448 | /* Very gross. */ |
28e4f854 | 1449 | |
252b5132 | 1450 | void |
ea1562b3 NC |
1451 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
1452 | asection *sec, | |
1453 | fragS *fragP) | |
252b5132 | 1454 | { |
8ad7c533 NC |
1455 | union u |
1456 | { | |
1457 | bfd_reloc_code_real_type fx_r_type; | |
1458 | char * fr_opcode; | |
1459 | } | |
1460 | opcode_converter; | |
252b5132 | 1461 | subseg_change (sec, 0); |
28e4f854 | 1462 | |
8ad7c533 | 1463 | opcode_converter.fr_opcode = fragP->fr_opcode; |
1cd986c5 NC |
1464 | |
1465 | subseg_change (sec, 0); | |
1466 | ||
252b5132 | 1467 | /* In range conditional or unconditional branch. */ |
1cd986c5 NC |
1468 | if (fragP->fr_subtype == SUBYPTE_COND_9_22 |
1469 | || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 | |
1470 | || fragP->fr_subtype == SUBYPTE_COND_9_22_32 | |
1471 | || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 | |
1472 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22 | |
1473 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 | |
1474 | || fragP->fr_subtype == SUBYPTE_SA_9_22 | |
1475 | || fragP->fr_subtype == SUBYPTE_SA_9_22_32 | |
1476 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22 | |
1477 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) | |
1478 | ||
252b5132 RH |
1479 | { |
1480 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, | |
8ad7c533 NC |
1481 | fragP->fr_offset, 1, |
1482 | BFD_RELOC_UNUSED + opcode_converter.fx_r_type); | |
252b5132 RH |
1483 | fragP->fr_fix += 2; |
1484 | } | |
1cd986c5 NC |
1485 | /* V850e2r-v3 17bit conditional branch. */ |
1486 | else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 | |
1487 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 | |
1488 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 | |
1489 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) | |
1490 | { | |
1491 | unsigned char *buffer = | |
1492 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1493 | ||
1494 | buffer[0] &= 0x0f; /* Use condition. */ | |
1495 | buffer[0] |= 0xe0; | |
1496 | buffer[1] = 0x07; | |
1497 | ||
1498 | /* Now create the unconditional branch + fixup to the final | |
1499 | target. */ | |
1500 | md_number_to_chars ((char *) buffer + 2, 0x0001, 2); | |
1501 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
1502 | fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); | |
1503 | fragP->fr_fix += 4; | |
1504 | } | |
1505 | /* Out of range conditional branch. Emit a branch around a 22bit jump. */ | |
1506 | else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 | |
1507 | || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 | |
1508 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 | |
1509 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) | |
252b5132 | 1510 | { |
28e4f854 | 1511 | unsigned char *buffer = |
252b5132 RH |
1512 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); |
1513 | ||
1514 | /* Reverse the condition of the first branch. */ | |
1515 | buffer[0] ^= 0x08; | |
1516 | /* Mask off all the displacement bits. */ | |
1517 | buffer[0] &= 0x8f; | |
1518 | buffer[1] &= 0x07; | |
1519 | /* Now set the displacement bits so that we branch | |
1520 | around the unconditional branch. */ | |
1521 | buffer[0] |= 0x30; | |
1522 | ||
1523 | /* Now create the unconditional branch + fixup to the final | |
1524 | target. */ | |
2132e3a3 | 1525 | md_number_to_chars ((char *) buffer + 2, 0x00000780, 4); |
252b5132 | 1526 | fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, |
1cd986c5 | 1527 | fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); |
252b5132 RH |
1528 | fragP->fr_fix += 6; |
1529 | } | |
1cd986c5 NC |
1530 | /* Out of range conditional branch. Emit a branch around a 32bit jump. */ |
1531 | else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 | |
1532 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) | |
1533 | { | |
1534 | unsigned char *buffer = | |
1535 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1536 | ||
1537 | /* Reverse the condition of the first branch. */ | |
1538 | buffer[0] ^= 0x08; | |
1539 | /* Mask off all the displacement bits. */ | |
1540 | buffer[0] &= 0x8f; | |
1541 | buffer[1] &= 0x07; | |
1542 | /* Now set the displacement bits so that we branch | |
1543 | around the unconditional branch. */ | |
1544 | buffer[0] |= 0x40; | |
1545 | ||
1546 | /* Now create the unconditional branch + fixup to the final | |
1547 | target. */ | |
1548 | md_number_to_chars ((char *) buffer + 2, 0x02e0, 2); | |
1549 | fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, | |
1550 | fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); | |
1551 | fragP->fr_fix += 8; | |
1552 | } | |
1553 | /* Out of range unconditional branch. Emit a 22bit jump. */ | |
1554 | else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 | |
1555 | || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) | |
252b5132 RH |
1556 | { |
1557 | md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); | |
1558 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
1cd986c5 | 1559 | fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); |
252b5132 RH |
1560 | fragP->fr_fix += 4; |
1561 | } | |
1cd986c5 NC |
1562 | /* Out of range unconditional branch. Emit a 32bit jump. */ |
1563 | else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) | |
1564 | { | |
1565 | md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); | |
1566 | fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, | |
1567 | fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); | |
1568 | fragP->fr_fix += 6; | |
1569 | } | |
1570 | /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ | |
1571 | else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 | |
1572 | || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 | |
1573 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 | |
1574 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) | |
1575 | { | |
1576 | unsigned char *buffer = | |
1577 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1578 | ||
1579 | /* bsa .+4 */ | |
1580 | buffer[0] &= 0x8f; | |
1581 | buffer[0] |= 0x20; | |
1582 | buffer[1] &= 0x07; | |
1583 | ||
1584 | /* br .+6 */ | |
1585 | md_number_to_chars ((char *) buffer + 2, 0x05b5, 2); | |
1586 | ||
1587 | /* Now create the unconditional branch + fixup to the final | |
1588 | target. */ | |
1589 | /* jr SYM */ | |
1590 | md_number_to_chars ((char *) buffer + 4, 0x00000780, 4); | |
1591 | fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, | |
1592 | fragP->fr_offset, 1, | |
1593 | BFD_RELOC_V850_22_PCREL); | |
1594 | fragP->fr_fix += 8; | |
1595 | } | |
1596 | /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ | |
1597 | else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 | |
1598 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) | |
1599 | { | |
1600 | unsigned char *buffer = | |
1601 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1602 | ||
1603 | /* bsa .+2 */ | |
1604 | buffer[0] &= 0x8f; | |
1605 | buffer[0] |= 0x20; | |
1606 | buffer[1] &= 0x07; | |
1607 | ||
1608 | /* br .+8 */ | |
1609 | md_number_to_chars ((char *) buffer + 2, 0x05c5, 2); | |
1610 | ||
1611 | /* Now create the unconditional branch + fixup to the final | |
1612 | target. */ | |
1613 | /* jr SYM */ | |
1614 | md_number_to_chars ((char *) buffer + 4, 0x02e0, 2); | |
1615 | fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, | |
1616 | fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); | |
1617 | ||
1618 | fragP->fr_fix += 10; | |
1619 | } | |
252b5132 RH |
1620 | else |
1621 | abort (); | |
1622 | } | |
1623 | ||
1624 | valueT | |
ea1562b3 | 1625 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
1626 | { |
1627 | int align = bfd_get_section_alignment (stdoutput, seg); | |
1628 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
1629 | } | |
1630 | ||
1631 | void | |
ea1562b3 | 1632 | md_begin (void) |
252b5132 | 1633 | { |
28e4f854 | 1634 | char *prev_name = ""; |
86aba9db | 1635 | const struct v850_opcode *op; |
28e4f854 | 1636 | |
1cd986c5 NC |
1637 | if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0) |
1638 | { | |
1639 | if (machine == -1) | |
1640 | machine = bfd_mach_v850e2v3; | |
1641 | ||
1642 | if (!processor_mask) | |
1643 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); | |
1644 | } | |
1645 | else if (strncmp (TARGET_CPU, "v850e2", 6) == 0) | |
1646 | { | |
1647 | if (machine == -1) | |
1648 | machine = bfd_mach_v850e2; | |
1649 | ||
1650 | if (!processor_mask) | |
1651 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); | |
1652 | } | |
1653 | else if (strncmp (TARGET_CPU, "v850e1", 6) == 0) | |
8ad30312 NC |
1654 | { |
1655 | if (machine == -1) | |
1cd986c5 | 1656 | machine = bfd_mach_v850e1; |
8ad30312 | 1657 | |
1cd986c5 NC |
1658 | if (!processor_mask) |
1659 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); | |
8ad30312 NC |
1660 | } |
1661 | else if (strncmp (TARGET_CPU, "v850e", 5) == 0) | |
252b5132 RH |
1662 | { |
1663 | if (machine == -1) | |
28e4f854 KH |
1664 | machine = bfd_mach_v850e; |
1665 | ||
1cd986c5 NC |
1666 | if (!processor_mask) |
1667 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); | |
252b5132 | 1668 | } |
28e4f854 | 1669 | else if (strncmp (TARGET_CPU, "v850", 4) == 0) |
252b5132 RH |
1670 | { |
1671 | if (machine == -1) | |
28e4f854 KH |
1672 | machine = 0; |
1673 | ||
1cd986c5 NC |
1674 | if (!processor_mask) |
1675 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); | |
252b5132 RH |
1676 | } |
1677 | else | |
28e4f854 KH |
1678 | /* xgettext:c-format */ |
1679 | as_bad (_("Unable to determine default target processor from string: %s"), | |
ec178e1b | 1680 | TARGET_CPU); |
252b5132 | 1681 | |
19d63e5d | 1682 | v850_hash = hash_new (); |
252b5132 RH |
1683 | |
1684 | /* Insert unique names into hash table. The V850 instruction set | |
1685 | has many identical opcode names that have different opcodes based | |
1686 | on the operands. This hash table then provides a quick index to | |
1687 | the first opcode with a particular name in the opcode table. */ | |
252b5132 RH |
1688 | op = v850_opcodes; |
1689 | while (op->name) | |
1690 | { | |
28e4f854 | 1691 | if (strcmp (prev_name, op->name)) |
252b5132 RH |
1692 | { |
1693 | prev_name = (char *) op->name; | |
1694 | hash_insert (v850_hash, op->name, (char *) op); | |
1695 | } | |
1696 | op++; | |
1697 | } | |
1698 | ||
9e0665bc | 1699 | v850_seg_table[BSS_SECTION].s = bss_section; |
de863c74 NC |
1700 | bfd_set_arch_mach (stdoutput, v850_target_arch, machine); |
1701 | bfd_set_private_flags (stdoutput, v850_e_flags); | |
252b5132 RH |
1702 | } |
1703 | ||
1cd986c5 | 1704 | |
1e50d24d | 1705 | static bfd_reloc_code_real_type |
1cd986c5 | 1706 | handle_hi016 (const struct v850_operand *operand, const char **errmsg) |
1e50d24d | 1707 | { |
1cd986c5 NC |
1708 | if (operand == NULL) |
1709 | return BFD_RELOC_HI16; | |
1e50d24d | 1710 | |
1cd986c5 NC |
1711 | if (operand->default_reloc == BFD_RELOC_HI16) |
1712 | return BFD_RELOC_HI16; | |
1713 | ||
1714 | if (operand->default_reloc == BFD_RELOC_HI16_S) | |
1715 | return BFD_RELOC_HI16; | |
1716 | ||
1717 | if (operand->default_reloc == BFD_RELOC_16) | |
1718 | return BFD_RELOC_HI16; | |
1719 | ||
1720 | *errmsg = _("hi0() relocation used on an instruction which does " | |
1721 | "not support it"); | |
1722 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
1e50d24d RS |
1723 | } |
1724 | ||
252b5132 | 1725 | static bfd_reloc_code_real_type |
1cd986c5 | 1726 | handle_hi16 (const struct v850_operand *operand, const char **errmsg) |
252b5132 RH |
1727 | { |
1728 | if (operand == NULL) | |
1cd986c5 | 1729 | return BFD_RELOC_HI16_S; |
252b5132 | 1730 | |
1cd986c5 NC |
1731 | if (operand->default_reloc == BFD_RELOC_HI16_S) |
1732 | return BFD_RELOC_HI16_S; | |
1733 | ||
1734 | if (operand->default_reloc == BFD_RELOC_HI16) | |
1735 | return BFD_RELOC_HI16_S; | |
1736 | ||
1737 | if (operand->default_reloc == BFD_RELOC_16) | |
1738 | return BFD_RELOC_HI16_S; | |
28e4f854 | 1739 | |
1cd986c5 NC |
1740 | *errmsg = _("hi() relocation used on an instruction which does " |
1741 | "not support it"); | |
1742 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
1743 | } |
1744 | ||
1745 | static bfd_reloc_code_real_type | |
1cd986c5 | 1746 | handle_lo16 (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 1747 | { |
28e4f854 | 1748 | if (operand == NULL) |
1cd986c5 | 1749 | return BFD_RELOC_LO16; |
28e4f854 | 1750 | |
1cd986c5 NC |
1751 | if (operand->default_reloc == BFD_RELOC_LO16) |
1752 | return BFD_RELOC_LO16; | |
28e4f854 | 1753 | |
1cd986c5 NC |
1754 | if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) |
1755 | return BFD_RELOC_V850_LO16_SPLIT_OFFSET; | |
28e4f854 | 1756 | |
1cd986c5 NC |
1757 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) |
1758 | return BFD_RELOC_V850_LO16_S1; | |
1759 | ||
1760 | if (operand->default_reloc == BFD_RELOC_16) | |
1761 | return BFD_RELOC_LO16; | |
28e4f854 | 1762 | |
1cd986c5 NC |
1763 | *errmsg = _("lo() relocation used on an instruction which does " |
1764 | "not support it"); | |
1765 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
1766 | } |
1767 | ||
1768 | static bfd_reloc_code_real_type | |
1cd986c5 | 1769 | handle_ctoff (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 1770 | { |
28e4f854 | 1771 | if (operand == NULL) |
1cd986c5 | 1772 | return BFD_RELOC_V850_CALLT_16_16_OFFSET; |
28e4f854 | 1773 | |
1cd986c5 NC |
1774 | if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) |
1775 | return operand->default_reloc; | |
252b5132 | 1776 | |
1cd986c5 NC |
1777 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) |
1778 | return BFD_RELOC_V850_CALLT_15_16_OFFSET; | |
28e4f854 | 1779 | |
1cd986c5 NC |
1780 | if (operand->default_reloc == BFD_RELOC_16) |
1781 | return BFD_RELOC_V850_CALLT_16_16_OFFSET; | |
28e4f854 | 1782 | |
1cd986c5 NC |
1783 | *errmsg = _("ctoff() relocation used on an instruction which does not support it"); |
1784 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
1785 | } |
1786 | ||
1787 | static bfd_reloc_code_real_type | |
1cd986c5 | 1788 | handle_sdaoff (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 1789 | { |
28e4f854 | 1790 | if (operand == NULL) |
1cd986c5 | 1791 | return BFD_RELOC_V850_SDA_16_16_OFFSET; |
28e4f854 | 1792 | |
1cd986c5 NC |
1793 | if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) |
1794 | return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; | |
28e4f854 | 1795 | |
1cd986c5 NC |
1796 | if (operand->default_reloc == BFD_RELOC_16) |
1797 | return BFD_RELOC_V850_SDA_16_16_OFFSET; | |
28e4f854 | 1798 | |
1cd986c5 NC |
1799 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) |
1800 | return BFD_RELOC_V850_SDA_15_16_OFFSET; | |
28e4f854 | 1801 | |
1cd986c5 NC |
1802 | *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); |
1803 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
1804 | } |
1805 | ||
252b5132 | 1806 | static bfd_reloc_code_real_type |
1cd986c5 | 1807 | handle_zdaoff (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 1808 | { |
1cd986c5 NC |
1809 | if (operand == NULL) |
1810 | return BFD_RELOC_V850_ZDA_16_16_OFFSET; | |
252b5132 | 1811 | |
1cd986c5 NC |
1812 | if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) |
1813 | return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; | |
252b5132 | 1814 | |
1cd986c5 NC |
1815 | if (operand->default_reloc == BFD_RELOC_16) |
1816 | return BFD_RELOC_V850_ZDA_16_16_OFFSET; | |
1817 | ||
1818 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) | |
1819 | return BFD_RELOC_V850_ZDA_15_16_OFFSET; | |
1820 | ||
1821 | *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); | |
1822 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
1823 | } | |
1824 | ||
1825 | static bfd_reloc_code_real_type | |
1826 | handle_tdaoff (const struct v850_operand *operand, const char **errmsg) | |
1827 | { | |
1828 | if (operand == NULL) | |
1829 | /* Data item, not an instruction. */ | |
1830 | return BFD_RELOC_V850_TDA_16_16_OFFSET; | |
1831 | ||
1832 | switch (operand->default_reloc) | |
1833 | { | |
1834 | /* sld.hu, operand: D5-4. */ | |
1835 | case BFD_RELOC_V850_TDA_4_5_OFFSET: | |
1836 | /* sld.bu, operand: D4. */ | |
1837 | case BFD_RELOC_V850_TDA_4_4_OFFSET: | |
1838 | /* sld.w/sst.w, operand: D8_6. */ | |
1839 | case BFD_RELOC_V850_TDA_6_8_OFFSET: | |
1840 | /* sld.h/sst.h, operand: D8_7. */ | |
1841 | case BFD_RELOC_V850_TDA_7_8_OFFSET: | |
1842 | /* sld.b/sst.b, operand: D7. */ | |
1843 | case BFD_RELOC_V850_TDA_7_7_OFFSET: | |
1844 | return operand->default_reloc; | |
1845 | default: | |
1846 | break; | |
1847 | } | |
1848 | ||
1849 | if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) | |
1850 | /* set1 & chums, operands: D16. */ | |
1851 | return BFD_RELOC_V850_TDA_16_16_OFFSET; | |
1852 | ||
1853 | *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); | |
1854 | /* Used to indicate an error condition. */ | |
1855 | return BFD_RELOC_64; | |
1856 | } | |
1857 | ||
1858 | /* Warning: The code in this function relies upon the definitions | |
1859 | in the v850_operands[] array (defined in opcodes/v850-opc.c) | |
1860 | matching the hard coded values contained herein. */ | |
1861 | ||
1862 | static bfd_reloc_code_real_type | |
1863 | v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) | |
1864 | { | |
1865 | bfd_boolean paren_skipped = FALSE; | |
1866 | ||
1867 | /* Skip leading opening parenthesis. */ | |
1868 | if (*input_line_pointer == '(') | |
1869 | { | |
1870 | ++input_line_pointer; | |
1871 | paren_skipped = TRUE; | |
1872 | } | |
1873 | ||
1874 | #define CHECK_(name, reloc) \ | |
ec266e19 | 1875 | if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ |
252b5132 RH |
1876 | { \ |
1877 | input_line_pointer += strlen (name); \ | |
1878 | return reloc; \ | |
1879 | } | |
28e4f854 | 1880 | |
1cd986c5 NC |
1881 | CHECK_ ("hi0", handle_hi016(operand, errmsg) ); |
1882 | CHECK_ ("hi", handle_hi16(operand, errmsg) ); | |
1883 | CHECK_ ("lo", handle_lo16 (operand, errmsg) ); | |
1884 | CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); | |
1885 | CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); | |
1886 | CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); | |
1887 | CHECK_ ("hilo", BFD_RELOC_32); | |
1888 | CHECK_ ("lo23", BFD_RELOC_V850_23); | |
1889 | CHECK_ ("ctoff", handle_ctoff (operand, errmsg) ); | |
28e4f854 | 1890 | |
252b5132 RH |
1891 | /* Restore skipped parenthesis. */ |
1892 | if (paren_skipped) | |
28e4f854 KH |
1893 | --input_line_pointer; |
1894 | ||
252b5132 RH |
1895 | return BFD_RELOC_UNUSED; |
1896 | } | |
1897 | ||
1898 | /* Insert an operand value into an instruction. */ | |
1899 | ||
1900 | static unsigned long | |
ea1562b3 NC |
1901 | v850_insert_operand (unsigned long insn, |
1902 | const struct v850_operand *operand, | |
1903 | offsetT val, | |
1cd986c5 | 1904 | const char **errmsg) |
252b5132 RH |
1905 | { |
1906 | if (operand->insert) | |
1907 | { | |
28e4f854 KH |
1908 | const char *message = NULL; |
1909 | ||
1910 | insn = operand->insert (insn, val, &message); | |
252b5132 RH |
1911 | if (message != NULL) |
1912 | { | |
1913 | if ((operand->flags & V850_OPERAND_SIGNED) | |
1914 | && ! warn_signed_overflows | |
1cd986c5 | 1915 | && v850_msg_is_out_of_range (message)) |
252b5132 | 1916 | { |
28e4f854 | 1917 | /* Skip warning... */ |
252b5132 RH |
1918 | } |
1919 | else if ((operand->flags & V850_OPERAND_SIGNED) == 0 | |
1920 | && ! warn_unsigned_overflows | |
1cd986c5 | 1921 | && v850_msg_is_out_of_range (message)) |
252b5132 | 1922 | { |
28e4f854 | 1923 | /* Skip warning... */ |
252b5132 | 1924 | } |
252b5132 RH |
1925 | else |
1926 | { | |
1cd986c5 NC |
1927 | if (errmsg != NULL) |
1928 | *errmsg = message; | |
252b5132 RH |
1929 | } |
1930 | } | |
1931 | } | |
1cd986c5 NC |
1932 | else if (operand->bits == -1 |
1933 | || operand->flags & V850E_IMMEDIATE16 | |
1934 | || operand->flags & V850E_IMMEDIATE23 | |
1935 | || operand->flags & V850E_IMMEDIATE32) | |
1936 | { | |
1937 | abort (); | |
1938 | } | |
252b5132 RH |
1939 | else |
1940 | { | |
1cd986c5 | 1941 | if (operand->bits < 32) |
252b5132 | 1942 | { |
28e4f854 | 1943 | long min, max; |
252b5132 RH |
1944 | |
1945 | if ((operand->flags & V850_OPERAND_SIGNED) != 0) | |
1946 | { | |
1947 | if (! warn_signed_overflows) | |
1948 | max = (1 << operand->bits) - 1; | |
1949 | else | |
1950 | max = (1 << (operand->bits - 1)) - 1; | |
28e4f854 KH |
1951 | |
1952 | min = -(1 << (operand->bits - 1)); | |
252b5132 RH |
1953 | } |
1954 | else | |
1955 | { | |
1956 | max = (1 << operand->bits) - 1; | |
28e4f854 | 1957 | |
252b5132 | 1958 | if (! warn_unsigned_overflows) |
28e4f854 | 1959 | min = -(1 << (operand->bits - 1)); |
252b5132 RH |
1960 | else |
1961 | min = 0; | |
1962 | } | |
28e4f854 | 1963 | |
dc86b458 SB |
1964 | /* Some people write constants with the sign extension done by |
1965 | hand but only up to 32 bits. This shouldn't really be valid, | |
1966 | but, to permit this code to assemble on a 64-bit host, we | |
1967 | sign extend the 32-bit value to 64 bits if so doing makes the | |
1968 | value valid. */ | |
1969 | if (val > max | |
1970 | && (offsetT) (val - 0x80000000 - 0x80000000) >= min | |
1971 | && (offsetT) (val - 0x80000000 - 0x80000000) <= max) | |
1972 | val = val - 0x80000000 - 0x80000000; | |
1973 | ||
1974 | /* Similarly, people write expressions like ~(1<<15), and expect | |
1975 | this to be OK for a 32-bit unsigned value. */ | |
1976 | else if (val < min | |
1977 | && (offsetT) (val + 0x80000000 + 0x80000000) >= min | |
1978 | && (offsetT) (val + 0x80000000 + 0x80000000) <= max) | |
1979 | val = val + 0x80000000 + 0x80000000; | |
1980 | ||
1981 | else if (val < (offsetT) min || val > (offsetT) max) | |
252b5132 | 1982 | { |
04ee5257 | 1983 | static char buf [128]; |
28e4f854 | 1984 | |
252b5132 RH |
1985 | /* Restore min and mix to expected values for decimal ranges. */ |
1986 | if ((operand->flags & V850_OPERAND_SIGNED) | |
1987 | && ! warn_signed_overflows) | |
1988 | max = (1 << (operand->bits - 1)) - 1; | |
1989 | ||
1990 | if (! (operand->flags & V850_OPERAND_SIGNED) | |
1991 | && ! warn_unsigned_overflows) | |
1992 | min = 0; | |
1993 | ||
1cd986c5 NC |
1994 | sprintf (buf, _("operand out of range (%d is not between %d and %d)"), |
1995 | (int) val, (int) min, (int) max); | |
1996 | *errmsg = buf; | |
252b5132 | 1997 | } |
252b5132 | 1998 | |
1cd986c5 NC |
1999 | insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); |
2000 | } | |
2001 | else | |
2002 | { | |
2003 | insn |= (((long) val) << operand->shift); | |
2004 | } | |
252b5132 | 2005 | } |
28e4f854 | 2006 | |
252b5132 RH |
2007 | return insn; |
2008 | } | |
252b5132 | 2009 | \f |
28e4f854 | 2010 | static char copy_of_instruction[128]; |
252b5132 RH |
2011 | |
2012 | void | |
ea1562b3 | 2013 | md_assemble (char *str) |
252b5132 | 2014 | { |
28e4f854 KH |
2015 | char *s; |
2016 | char *start_of_operands; | |
2017 | struct v850_opcode *opcode; | |
2018 | struct v850_opcode *next_opcode; | |
2019 | const unsigned char *opindex_ptr; | |
2020 | int next_opindex; | |
2021 | int relaxable = 0; | |
2022 | unsigned long insn; | |
2023 | unsigned long insn_size; | |
de863c74 | 2024 | char *f = NULL; |
28e4f854 KH |
2025 | int i; |
2026 | int match; | |
b34976b6 | 2027 | bfd_boolean extra_data_after_insn = FALSE; |
28e4f854 KH |
2028 | unsigned extra_data_len = 0; |
2029 | unsigned long extra_data = 0; | |
2030 | char *saved_input_line_pointer; | |
1cd986c5 NC |
2031 | char most_match_errmsg[1024]; |
2032 | int most_match_count = -1; | |
28e4f854 | 2033 | |
252b5132 | 2034 | strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); |
1cd986c5 | 2035 | most_match_errmsg[0] = 0; |
28e4f854 | 2036 | |
252b5132 | 2037 | /* Get the opcode. */ |
3882b010 | 2038 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 | 2039 | continue; |
28e4f854 | 2040 | |
252b5132 RH |
2041 | if (*s != '\0') |
2042 | *s++ = '\0'; | |
2043 | ||
28e4f854 | 2044 | /* Find the first opcode with the proper name. */ |
252b5132 RH |
2045 | opcode = (struct v850_opcode *) hash_find (v850_hash, str); |
2046 | if (opcode == NULL) | |
2047 | { | |
28e4f854 | 2048 | /* xgettext:c-format */ |
252b5132 RH |
2049 | as_bad (_("Unrecognized opcode: `%s'"), str); |
2050 | ignore_rest_of_line (); | |
2051 | return; | |
2052 | } | |
2053 | ||
2054 | str = s; | |
3882b010 | 2055 | while (ISSPACE (*str)) |
28e4f854 | 2056 | ++str; |
252b5132 RH |
2057 | |
2058 | start_of_operands = str; | |
2059 | ||
2060 | saved_input_line_pointer = input_line_pointer; | |
28e4f854 | 2061 | |
252b5132 RH |
2062 | for (;;) |
2063 | { | |
28e4f854 | 2064 | const char *errmsg = NULL; |
1cd986c5 | 2065 | const char *warningmsg = NULL; |
252b5132 RH |
2066 | |
2067 | match = 0; | |
1cd986c5 | 2068 | opindex_ptr = opcode->operands; |
28e4f854 | 2069 | |
1cd986c5 NC |
2070 | if (no_stld23) |
2071 | { | |
2072 | if ((strncmp (opcode->name, "st.", 3) == 0 | |
2073 | && v850_operands[opcode->operands[1]].bits == 23) | |
2074 | || (strncmp (opcode->name, "ld.", 3) == 0 | |
2075 | && v850_operands[opcode->operands[0]].bits == 23)) | |
2076 | { | |
2077 | errmsg = _("st/ld offset 23 instruction was disabled ."); | |
2078 | goto error; | |
2079 | } | |
2080 | } | |
2081 | ||
2082 | if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 | |
2083 | || (((opcode->processors & ~PROCESSOR_MASK) != 0) | |
2084 | && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) | |
252b5132 RH |
2085 | { |
2086 | errmsg = _("Target processor does not support this instruction."); | |
2087 | goto error; | |
2088 | } | |
28e4f854 | 2089 | |
252b5132 RH |
2090 | relaxable = 0; |
2091 | fc = 0; | |
2092 | next_opindex = 0; | |
2093 | insn = opcode->opcode; | |
1cd986c5 | 2094 | extra_data_len = 0; |
b34976b6 | 2095 | extra_data_after_insn = FALSE; |
252b5132 RH |
2096 | |
2097 | input_line_pointer = str = start_of_operands; | |
2098 | ||
28e4f854 | 2099 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) |
252b5132 | 2100 | { |
28e4f854 KH |
2101 | const struct v850_operand *operand; |
2102 | char *hold; | |
2103 | expressionS ex; | |
2104 | bfd_reloc_code_real_type reloc; | |
252b5132 RH |
2105 | |
2106 | if (next_opindex == 0) | |
ea1562b3 | 2107 | operand = &v850_operands[*opindex_ptr]; |
252b5132 RH |
2108 | else |
2109 | { | |
28e4f854 | 2110 | operand = &v850_operands[next_opindex]; |
252b5132 RH |
2111 | next_opindex = 0; |
2112 | } | |
2113 | ||
2114 | errmsg = NULL; | |
2115 | ||
1cd986c5 NC |
2116 | while (*str == ' ') |
2117 | ++str; | |
2118 | ||
2119 | if (operand->flags & V850_OPERAND_BANG | |
2120 | && *str == '!') | |
2121 | ++str; | |
2122 | else if (operand->flags & V850_OPERAND_PERCENT | |
2123 | && *str == '%') | |
2124 | ++str; | |
2125 | ||
2126 | if (*str == ',' || *str == '[' || *str == ']') | |
2127 | ++str; | |
2128 | ||
2129 | while (*str == ' ') | |
28e4f854 | 2130 | ++str; |
252b5132 RH |
2131 | |
2132 | if (operand->flags & V850_OPERAND_RELAX) | |
2133 | relaxable = 1; | |
2134 | ||
28e4f854 | 2135 | /* Gather the operand. */ |
252b5132 RH |
2136 | hold = input_line_pointer; |
2137 | input_line_pointer = str; | |
28e4f854 KH |
2138 | |
2139 | /* lo(), hi(), hi0(), etc... */ | |
1cd986c5 | 2140 | if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_UNUSED) |
252b5132 RH |
2141 | { |
2142 | /* This is a fake reloc, used to indicate an error condition. */ | |
2143 | if (reloc == BFD_RELOC_64) | |
2144 | { | |
1cd986c5 | 2145 | /* match = 1; */ |
252b5132 RH |
2146 | goto error; |
2147 | } | |
28e4f854 KH |
2148 | |
2149 | expression (&ex); | |
252b5132 RH |
2150 | |
2151 | if (ex.X_op == O_constant) | |
2152 | { | |
2153 | switch (reloc) | |
2154 | { | |
2155 | case BFD_RELOC_V850_ZDA_16_16_OFFSET: | |
1cd986c5 NC |
2156 | case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: |
2157 | case BFD_RELOC_V850_ZDA_15_16_OFFSET: | |
252b5132 RH |
2158 | /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" |
2159 | and the like. */ | |
2160 | /* Fall through. */ | |
28e4f854 | 2161 | |
252b5132 | 2162 | case BFD_RELOC_LO16: |
1cd986c5 | 2163 | case BFD_RELOC_V850_LO16_S1: |
1e50d24d | 2164 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: |
252b5132 RH |
2165 | { |
2166 | /* Truncate, then sign extend the value. */ | |
2167 | ex.X_add_number = SEXT16 (ex.X_add_number); | |
2168 | break; | |
2169 | } | |
2170 | ||
2171 | case BFD_RELOC_HI16: | |
2172 | { | |
2173 | /* Truncate, then sign extend the value. */ | |
2174 | ex.X_add_number = SEXT16 (ex.X_add_number >> 16); | |
2175 | break; | |
2176 | } | |
2177 | ||
2178 | case BFD_RELOC_HI16_S: | |
2179 | { | |
2180 | /* Truncate, then sign extend the value. */ | |
28e4f854 | 2181 | int temp = (ex.X_add_number >> 16) & 0xffff; |
252b5132 RH |
2182 | |
2183 | temp += (ex.X_add_number >> 15) & 1; | |
2184 | ||
2185 | ex.X_add_number = SEXT16 (temp); | |
2186 | break; | |
2187 | } | |
28e4f854 | 2188 | |
1cd986c5 NC |
2189 | case BFD_RELOC_V850_23: |
2190 | if ((operand->flags & V850E_IMMEDIATE23) == 0) | |
2191 | { | |
2192 | errmsg = _("immediate operand is too large"); | |
2193 | goto error; | |
2194 | } | |
2195 | break; | |
2196 | ||
252b5132 | 2197 | case BFD_RELOC_32: |
1cd986c5 NC |
2198 | case BFD_RELOC_V850_32_ABS: |
2199 | case BFD_RELOC_V850_32_PCREL: | |
252b5132 RH |
2200 | if ((operand->flags & V850E_IMMEDIATE32) == 0) |
2201 | { | |
2202 | errmsg = _("immediate operand is too large"); | |
2203 | goto error; | |
2204 | } | |
28e4f854 | 2205 | |
252b5132 | 2206 | break; |
28e4f854 | 2207 | |
252b5132 RH |
2208 | default: |
2209 | fprintf (stderr, "reloc: %d\n", reloc); | |
2210 | as_bad (_("AAARG -> unhandled constant reloc")); | |
2211 | break; | |
2212 | } | |
2213 | ||
1cd986c5 NC |
2214 | if (operand->flags & V850E_IMMEDIATE32) |
2215 | { | |
2216 | extra_data_after_insn = TRUE; | |
2217 | extra_data_len = 4; | |
2218 | extra_data = 0; | |
2219 | } | |
2220 | else if (operand->flags & V850E_IMMEDIATE23) | |
2221 | { | |
2222 | if (reloc != BFD_RELOC_V850_23) | |
2223 | { | |
2224 | errmsg = _("immediate operand is too large"); | |
2225 | goto error; | |
2226 | } | |
2227 | extra_data_after_insn = TRUE; | |
2228 | extra_data_len = 2; | |
2229 | extra_data = 0; | |
2230 | } | |
2231 | else if ((operand->flags & V850E_IMMEDIATE16) | |
2232 | || (operand->flags & V850E_IMMEDIATE16HI)) | |
2233 | { | |
2234 | if (operand->flags & V850E_IMMEDIATE16HI | |
2235 | && reloc != BFD_RELOC_HI16 | |
2236 | && reloc != BFD_RELOC_HI16_S) | |
2237 | { | |
2238 | errmsg = _("immediate operand is too large"); | |
2239 | goto error; | |
2240 | } | |
2241 | else if (operand->flags & V850E_IMMEDIATE16 | |
2242 | && reloc != BFD_RELOC_LO16) | |
2243 | { | |
2244 | errmsg = _("immediate operand is too large"); | |
2245 | goto error; | |
2246 | } | |
2247 | ||
2248 | extra_data_after_insn = TRUE; | |
2249 | extra_data_len = 2; | |
2250 | extra_data = 0; | |
2251 | } | |
2252 | ||
252b5132 RH |
2253 | if (fc > MAX_INSN_FIXUPS) |
2254 | as_fatal (_("too many fixups")); | |
28e4f854 KH |
2255 | |
2256 | fixups[fc].exp = ex; | |
2257 | fixups[fc].opindex = *opindex_ptr; | |
2258 | fixups[fc].reloc = reloc; | |
252b5132 RH |
2259 | fc++; |
2260 | } | |
1cd986c5 | 2261 | else /* ex.X_op != O_constant. */ |
252b5132 | 2262 | { |
1cd986c5 NC |
2263 | if ((reloc == BFD_RELOC_32 |
2264 | || reloc == BFD_RELOC_V850_32_ABS | |
2265 | || reloc == BFD_RELOC_V850_32_PCREL) | |
2266 | && operand->bits < 32) | |
252b5132 | 2267 | { |
1cd986c5 NC |
2268 | errmsg = _("immediate operand is too large"); |
2269 | goto error; | |
2270 | } | |
2271 | else if (reloc == BFD_RELOC_V850_23 | |
2272 | && (operand->flags & V850E_IMMEDIATE23) == 0) | |
2273 | { | |
2274 | errmsg = _("immediate operand is too large"); | |
2275 | goto error; | |
2276 | } | |
2277 | else if ((reloc == BFD_RELOC_HI16 | |
2278 | || reloc == BFD_RELOC_HI16_S) | |
2279 | && operand->bits < 16) | |
2280 | { | |
2281 | errmsg = _("immediate operand is too large"); | |
2282 | goto error; | |
2283 | } | |
2284 | ||
2285 | if (operand->flags & V850E_IMMEDIATE32) | |
2286 | { | |
2287 | extra_data_after_insn = TRUE; | |
2288 | extra_data_len = 4; | |
2289 | extra_data = 0; | |
2290 | } | |
2291 | else if (operand->flags & V850E_IMMEDIATE23) | |
2292 | { | |
2293 | if (reloc != BFD_RELOC_V850_23) | |
2294 | { | |
2295 | errmsg = _("immediate operand is too large"); | |
2296 | goto error; | |
2297 | } | |
2298 | extra_data_after_insn = TRUE; | |
2299 | extra_data_len = 2; | |
2300 | extra_data = 0; | |
2301 | } | |
2302 | else if ((operand->flags & V850E_IMMEDIATE16) | |
2303 | || (operand->flags & V850E_IMMEDIATE16HI)) | |
2304 | { | |
2305 | if (operand->flags & V850E_IMMEDIATE16HI | |
2306 | && reloc != BFD_RELOC_HI16 | |
2307 | && reloc != BFD_RELOC_HI16_S) | |
2308 | { | |
2309 | errmsg = _("immediate operand is too large"); | |
2310 | goto error; | |
2311 | } | |
2312 | else if (operand->flags & V850E_IMMEDIATE16 | |
2313 | && reloc != BFD_RELOC_LO16) | |
252b5132 RH |
2314 | { |
2315 | errmsg = _("immediate operand is too large"); | |
2316 | goto error; | |
2317 | } | |
28e4f854 | 2318 | |
b34976b6 | 2319 | extra_data_after_insn = TRUE; |
1cd986c5 NC |
2320 | extra_data_len = 2; |
2321 | extra_data = 0; | |
252b5132 | 2322 | } |
28e4f854 | 2323 | |
252b5132 RH |
2324 | if (fc > MAX_INSN_FIXUPS) |
2325 | as_fatal (_("too many fixups")); | |
2326 | ||
28e4f854 KH |
2327 | fixups[fc].exp = ex; |
2328 | fixups[fc].opindex = *opindex_ptr; | |
2329 | fixups[fc].reloc = reloc; | |
252b5132 RH |
2330 | fc++; |
2331 | } | |
2332 | } | |
1cd986c5 NC |
2333 | else if (operand->flags & V850E_IMMEDIATE16 |
2334 | || operand->flags & V850E_IMMEDIATE16HI) | |
2335 | { | |
2336 | expression (&ex); | |
2337 | ||
2338 | switch (ex.X_op) | |
2339 | { | |
2340 | case O_constant: | |
2341 | if (operand->flags & V850E_IMMEDIATE16HI) | |
2342 | { | |
2343 | if (ex.X_add_number & 0xffff) | |
2344 | { | |
2345 | errmsg = _("constant too big to fit into instruction"); | |
2346 | goto error; | |
2347 | } | |
2348 | ||
2349 | ex.X_add_number >>= 16; | |
2350 | } | |
2351 | if (operand->flags & V850E_IMMEDIATE16) | |
2352 | { | |
2353 | if (ex.X_add_number & 0xffff0000) | |
2354 | { | |
2355 | errmsg = _("constant too big to fit into instruction"); | |
2356 | goto error; | |
2357 | } | |
2358 | } | |
2359 | break; | |
2360 | ||
2361 | case O_illegal: | |
2362 | errmsg = _("illegal operand"); | |
2363 | goto error; | |
2364 | ||
2365 | case O_absent: | |
2366 | errmsg = _("missing operand"); | |
2367 | goto error; | |
2368 | ||
2369 | default: | |
2370 | if (fc >= MAX_INSN_FIXUPS) | |
2371 | as_fatal (_("too many fixups")); | |
2372 | ||
2373 | fixups[fc].exp = ex; | |
2374 | fixups[fc].opindex = *opindex_ptr; | |
2375 | fixups[fc].reloc = operand->default_reloc; | |
2376 | ++fc; | |
2377 | ||
2378 | ex.X_add_number = 0; | |
2379 | break; | |
2380 | } | |
2381 | ||
2382 | extra_data_after_insn = TRUE; | |
2383 | extra_data_len = 2; | |
2384 | extra_data = ex.X_add_number; | |
2385 | } | |
2386 | else if (operand->flags & V850E_IMMEDIATE23) | |
2387 | { | |
2388 | expression (&ex); | |
2389 | ||
2390 | switch (ex.X_op) | |
2391 | { | |
2392 | case O_constant: | |
2393 | break; | |
2394 | ||
2395 | case O_illegal: | |
2396 | errmsg = _("illegal operand"); | |
2397 | goto error; | |
2398 | ||
2399 | case O_absent: | |
2400 | errmsg = _("missing operand"); | |
2401 | goto error; | |
2402 | ||
2403 | default: | |
2404 | break; | |
2405 | } | |
2406 | ||
2407 | if (fc >= MAX_INSN_FIXUPS) | |
2408 | as_fatal (_("too many fixups")); | |
2409 | ||
2410 | fixups[fc].exp = ex; | |
2411 | fixups[fc].opindex = *opindex_ptr; | |
2412 | fixups[fc].reloc = operand->default_reloc; | |
2413 | ++fc; | |
2414 | ||
2415 | extra_data_after_insn = TRUE; | |
2416 | extra_data_len = 2; | |
2417 | extra_data = 0; | |
2418 | } | |
2419 | else if (operand->flags & V850E_IMMEDIATE32) | |
2420 | { | |
2421 | expression (&ex); | |
2422 | ||
2423 | switch (ex.X_op) | |
2424 | { | |
2425 | case O_constant: | |
2426 | if ((operand->default_reloc == BFD_RELOC_V850_32_ABS | |
2427 | || operand->default_reloc == BFD_RELOC_V850_32_PCREL) | |
2428 | && (ex.X_add_number & 1)) | |
2429 | { | |
2430 | errmsg = _("odd number cannot be used here"); | |
2431 | goto error; | |
2432 | } | |
2433 | break; | |
2434 | ||
2435 | case O_illegal: | |
2436 | errmsg = _("illegal operand"); | |
2437 | goto error; | |
2438 | ||
2439 | case O_absent: | |
2440 | errmsg = _("missing operand"); | |
2441 | goto error; | |
2442 | ||
2443 | default: | |
2444 | if (fc >= MAX_INSN_FIXUPS) | |
2445 | as_fatal (_("too many fixups")); | |
2446 | ||
2447 | fixups[fc].exp = ex; | |
2448 | fixups[fc].opindex = *opindex_ptr; | |
2449 | fixups[fc].reloc = operand->default_reloc; | |
2450 | ++fc; | |
2451 | ||
2452 | ex.X_add_number = 0; | |
2453 | break; | |
2454 | } | |
2455 | ||
2456 | extra_data_after_insn = TRUE; | |
2457 | extra_data_len = 4; | |
2458 | extra_data = ex.X_add_number; | |
2459 | } | |
2460 | else if (operand->flags & V850E_OPERAND_REG_LIST) | |
2461 | { | |
2462 | errmsg = parse_register_list (&insn, operand); | |
2463 | ||
2464 | if (errmsg) | |
2465 | goto error; | |
2466 | } | |
252b5132 RH |
2467 | else |
2468 | { | |
2469 | errmsg = NULL; | |
28e4f854 KH |
2470 | |
2471 | if ((operand->flags & V850_OPERAND_REG) != 0) | |
252b5132 | 2472 | { |
28e4f854 | 2473 | if (!register_name (&ex)) |
1cd986c5 NC |
2474 | { |
2475 | errmsg = _("invalid register name"); | |
2476 | } | |
2477 | ||
2478 | if ((operand->flags & V850_NOT_R0) | |
28e4f854 | 2479 | && ex.X_add_number == 0) |
252b5132 RH |
2480 | { |
2481 | errmsg = _("register r0 cannot be used here"); | |
1cd986c5 | 2482 | } |
28e4f854 | 2483 | |
1cd986c5 NC |
2484 | if (operand->flags & V850_REG_EVEN) |
2485 | { | |
2486 | if (ex.X_add_number % 2) | |
2487 | errmsg = _("odd register cannot be used here"); | |
2488 | ex.X_add_number = ex.X_add_number / 2; | |
252b5132 | 2489 | } |
1cd986c5 | 2490 | |
252b5132 | 2491 | } |
28e4f854 | 2492 | else if ((operand->flags & V850_OPERAND_SRG) != 0) |
252b5132 | 2493 | { |
1cd986c5 NC |
2494 | if (!system_register_name (&ex, TRUE)) |
2495 | { | |
2496 | errmsg = _("invalid system register name"); | |
2497 | } | |
252b5132 RH |
2498 | } |
2499 | else if ((operand->flags & V850_OPERAND_EP) != 0) | |
2500 | { | |
28e4f854 KH |
2501 | char *start = input_line_pointer; |
2502 | char c = get_symbol_end (); | |
2503 | ||
252b5132 RH |
2504 | if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0) |
2505 | { | |
2506 | /* Put things back the way we found them. */ | |
2507 | *input_line_pointer = c; | |
2508 | input_line_pointer = start; | |
2509 | errmsg = _("expected EP register"); | |
2510 | goto error; | |
2511 | } | |
28e4f854 | 2512 | |
252b5132 RH |
2513 | *input_line_pointer = c; |
2514 | str = input_line_pointer; | |
2515 | input_line_pointer = hold; | |
28e4f854 KH |
2516 | |
2517 | while (*str == ' ' || *str == ',' | |
2518 | || *str == '[' || *str == ']') | |
2519 | ++str; | |
252b5132 RH |
2520 | continue; |
2521 | } | |
28e4f854 | 2522 | else if ((operand->flags & V850_OPERAND_CC) != 0) |
252b5132 | 2523 | { |
1cd986c5 | 2524 | if (!cc_name (&ex, TRUE)) |
252b5132 | 2525 | { |
1cd986c5 | 2526 | errmsg = _("invalid condition code name"); |
252b5132 | 2527 | } |
28e4f854 | 2528 | |
1cd986c5 NC |
2529 | if ((operand->flags & V850_NOT_SA) |
2530 | && ex.X_add_number == COND_SA_NUM) | |
2531 | { | |
2532 | errmsg = _("condition sa cannot be used here"); | |
2533 | } | |
252b5132 | 2534 | } |
1cd986c5 | 2535 | else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) |
252b5132 | 2536 | { |
1cd986c5 NC |
2537 | if (!float_cc_name (&ex, TRUE)) |
2538 | { | |
2539 | errmsg = _("invalid condition code name"); | |
2540 | } | |
252b5132 | 2541 | } |
1cd986c5 NC |
2542 | else if ((register_name (&ex) |
2543 | && (operand->flags & V850_OPERAND_REG) == 0)) | |
252b5132 RH |
2544 | { |
2545 | char c; | |
28e4f854 KH |
2546 | int exists = 0; |
2547 | ||
252b5132 RH |
2548 | /* It is possible that an alias has been defined that |
2549 | matches a register name. For example the code may | |
2550 | include a ".set ZERO, 0" directive, which matches | |
2551 | the register name "zero". Attempt to reparse the | |
2552 | field as an expression, and only complain if we | |
2553 | cannot generate a constant. */ | |
2554 | ||
2555 | input_line_pointer = str; | |
2556 | ||
2557 | c = get_symbol_end (); | |
28e4f854 | 2558 | |
252b5132 RH |
2559 | if (symbol_find (str) != NULL) |
2560 | exists = 1; | |
28e4f854 KH |
2561 | |
2562 | *input_line_pointer = c; | |
252b5132 | 2563 | input_line_pointer = str; |
28e4f854 KH |
2564 | |
2565 | expression (&ex); | |
252b5132 RH |
2566 | |
2567 | if (ex.X_op != O_constant) | |
2568 | { | |
33b7f697 | 2569 | /* If this register is actually occurring too early on |
252b5132 RH |
2570 | the parsing of the instruction, (because another |
2571 | field is missing) then report this. */ | |
2572 | if (opindex_ptr[1] != 0 | |
1cd986c5 NC |
2573 | && ((v850_operands[opindex_ptr[1]].flags |
2574 | & V850_OPERAND_REG) | |
2575 | ||(v850_operands[opindex_ptr[1]].flags | |
2576 | & V850_OPERAND_VREG))) | |
252b5132 RH |
2577 | errmsg = _("syntax error: value is missing before the register name"); |
2578 | else | |
2579 | errmsg = _("syntax error: register not expected"); | |
2580 | ||
28e4f854 KH |
2581 | /* If we created a symbol in the process of this |
2582 | test then delete it now, so that it will not | |
2583 | be output with the real symbols... */ | |
252b5132 RH |
2584 | if (exists == 0 |
2585 | && ex.X_op == O_symbol) | |
2586 | symbol_remove (ex.X_add_symbol, | |
28e4f854 | 2587 | &symbol_rootP, &symbol_lastP); |
252b5132 RH |
2588 | } |
2589 | } | |
1cd986c5 | 2590 | else if (system_register_name (&ex, FALSE) |
252b5132 | 2591 | && (operand->flags & V850_OPERAND_SRG) == 0) |
1cd986c5 NC |
2592 | { |
2593 | errmsg = _("syntax error: system register not expected"); | |
2594 | } | |
2595 | else if (cc_name (&ex, FALSE) | |
252b5132 | 2596 | && (operand->flags & V850_OPERAND_CC) == 0) |
1cd986c5 NC |
2597 | { |
2598 | errmsg = _("syntax error: condition code not expected"); | |
2599 | } | |
2600 | else if (float_cc_name (&ex, FALSE) | |
2601 | && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) | |
2602 | { | |
2603 | errmsg = _("syntax error: condition code not expected"); | |
2604 | } | |
252b5132 RH |
2605 | else |
2606 | { | |
28e4f854 | 2607 | expression (&ex); |
1cd986c5 NC |
2608 | |
2609 | if ((operand->flags & V850_NOT_IMM0) | |
2610 | && ex.X_op == O_constant | |
2611 | && ex.X_add_number == 0) | |
2612 | { | |
2613 | errmsg = _("immediate 0 cannot be used here"); | |
2614 | } | |
2615 | ||
252b5132 | 2616 | /* Special case: |
1cd986c5 | 2617 | If we are assembling a MOV/JARL/JR instruction and the immediate |
50b15da2 | 2618 | value does not fit into the bits available then create a |
1cd986c5 | 2619 | fake error so that the next MOV/JARL/JR instruction will be |
50b15da2 | 2620 | selected. This one has a 32 bit immediate field. */ |
252b5132 | 2621 | |
1cd986c5 NC |
2622 | if ((strcmp (opcode->name, "mov") == 0 |
2623 | || strcmp (opcode->name, "jarl") == 0 | |
2624 | || strcmp (opcode->name, "jr") == 0) | |
252b5132 | 2625 | && ex.X_op == O_constant |
28e4f854 | 2626 | && (ex.X_add_number < (-(1 << (operand->bits - 1))) |
03223580 | 2627 | || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) |
1cd986c5 NC |
2628 | { |
2629 | errmsg = _("immediate operand is too large"); | |
2630 | } | |
2631 | ||
2632 | if ((strcmp (opcode->name, "jarl") == 0 | |
2633 | || strcmp (opcode->name, "jr") == 0) | |
2634 | && ex.X_op != O_constant | |
2635 | && operand->bits != default_disp_size) | |
2636 | { | |
2637 | errmsg = _("immediate operand is not match"); | |
2638 | } | |
252b5132 RH |
2639 | } |
2640 | ||
2641 | if (errmsg) | |
2642 | goto error; | |
252b5132 | 2643 | |
28e4f854 | 2644 | switch (ex.X_op) |
252b5132 RH |
2645 | { |
2646 | case O_illegal: | |
2647 | errmsg = _("illegal operand"); | |
2648 | goto error; | |
2649 | case O_absent: | |
2650 | errmsg = _("missing operand"); | |
2651 | goto error; | |
2652 | case O_register: | |
28e4f854 | 2653 | if ((operand->flags |
1cd986c5 | 2654 | & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) |
252b5132 RH |
2655 | { |
2656 | errmsg = _("invalid operand"); | |
2657 | goto error; | |
2658 | } | |
1cd986c5 NC |
2659 | |
2660 | insn = v850_insert_operand (insn, operand, | |
2661 | ex.X_add_number, | |
2662 | &warningmsg); | |
2663 | ||
252b5132 RH |
2664 | break; |
2665 | ||
2666 | case O_constant: | |
2667 | insn = v850_insert_operand (insn, operand, ex.X_add_number, | |
1cd986c5 | 2668 | &warningmsg); |
252b5132 RH |
2669 | break; |
2670 | ||
2671 | default: | |
2672 | /* We need to generate a fixup for this expression. */ | |
2673 | if (fc >= MAX_INSN_FIXUPS) | |
2674 | as_fatal (_("too many fixups")); | |
2675 | ||
28e4f854 KH |
2676 | fixups[fc].exp = ex; |
2677 | fixups[fc].opindex = *opindex_ptr; | |
2678 | fixups[fc].reloc = BFD_RELOC_UNUSED; | |
252b5132 RH |
2679 | ++fc; |
2680 | break; | |
2681 | } | |
2682 | } | |
2683 | ||
2684 | str = input_line_pointer; | |
2685 | input_line_pointer = hold; | |
2686 | ||
2687 | while (*str == ' ' || *str == ',' || *str == '[' || *str == ']' | |
2688 | || *str == ')') | |
2689 | ++str; | |
2690 | } | |
1cd986c5 NC |
2691 | |
2692 | while (ISSPACE (*str)) | |
2693 | ++str; | |
2694 | ||
2695 | if (*str == '\0') | |
2696 | match = 1; | |
252b5132 RH |
2697 | |
2698 | error: | |
2699 | if (match == 0) | |
28e4f854 | 2700 | { |
1cd986c5 NC |
2701 | if ((opindex_ptr - opcode->operands) >= most_match_count) |
2702 | { | |
2703 | most_match_count = opindex_ptr - opcode->operands; | |
2704 | if (errmsg != NULL) | |
2705 | strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); | |
2706 | } | |
2707 | ||
252b5132 RH |
2708 | next_opcode = opcode + 1; |
2709 | if (next_opcode->name != NULL | |
2710 | && strcmp (next_opcode->name, opcode->name) == 0) | |
2711 | { | |
2712 | opcode = next_opcode; | |
2713 | ||
2714 | /* Skip versions that are not supported by the target | |
2715 | processor. */ | |
2716 | if ((opcode->processors & processor_mask) == 0) | |
2717 | goto error; | |
28e4f854 | 2718 | |
252b5132 RH |
2719 | continue; |
2720 | } | |
28e4f854 | 2721 | |
1cd986c5 NC |
2722 | if (most_match_errmsg[0] == 0) |
2723 | /* xgettext:c-format. */ | |
2724 | as_bad (_("junk at end of line: `%s'"), str); | |
2725 | else | |
2726 | as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); | |
28e4f854 KH |
2727 | |
2728 | if (*input_line_pointer == ']') | |
2729 | ++input_line_pointer; | |
2730 | ||
252b5132 RH |
2731 | ignore_rest_of_line (); |
2732 | input_line_pointer = saved_input_line_pointer; | |
2733 | return; | |
28e4f854 | 2734 | } |
1cd986c5 NC |
2735 | |
2736 | if (warningmsg != NULL) | |
cd94c7fb | 2737 | as_warn ("%s", warningmsg); |
252b5132 RH |
2738 | break; |
2739 | } | |
28e4f854 | 2740 | |
252b5132 RH |
2741 | input_line_pointer = str; |
2742 | ||
9fcc94b6 AM |
2743 | /* Tie dwarf2 debug info to the address at the start of the insn. |
2744 | We can't do this after the insn has been output as the current | |
2745 | frag may have been closed off. eg. by frag_var. */ | |
2746 | dwarf2_emit_insn (0); | |
2747 | ||
28e4f854 KH |
2748 | /* Write out the instruction. */ |
2749 | ||
252b5132 RH |
2750 | if (relaxable && fc > 0) |
2751 | { | |
2752 | insn_size = 2; | |
2753 | fc = 0; | |
2754 | ||
1cd986c5 NC |
2755 | if (strcmp (opcode->name, "br") == 0 |
2756 | || strcmp (opcode->name, "jbr") == 0) | |
252b5132 | 2757 | { |
1cd986c5 NC |
2758 | if ((processor_mask & PROCESSOR_V850E2_ALL) == 0 || default_disp_size == 22) |
2759 | { | |
2760 | f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, | |
2761 | fixups[0].exp.X_add_symbol, | |
2762 | fixups[0].exp.X_add_number, | |
2763 | (char *)(size_t) fixups[0].opindex); | |
2764 | md_number_to_chars (f, insn, insn_size); | |
2765 | md_number_to_chars (f + 2, 0, 2); | |
2766 | } | |
2767 | else | |
2768 | { | |
2769 | f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, | |
2770 | fixups[0].exp.X_add_symbol, | |
2771 | fixups[0].exp.X_add_number, | |
2772 | (char *)(size_t) fixups[0].opindex); | |
2773 | md_number_to_chars (f, insn, insn_size); | |
2774 | md_number_to_chars (f + 2, 0, 4); | |
2775 | } | |
252b5132 | 2776 | } |
1cd986c5 | 2777 | else /* b<cond>, j<cond>. */ |
252b5132 | 2778 | { |
1cd986c5 NC |
2779 | if (default_disp_size == 22 |
2780 | || (processor_mask & PROCESSOR_V850E2_ALL) == 0) | |
2781 | { | |
2782 | if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17) | |
2783 | { | |
2784 | if (strcmp (opcode->name, "bsa") == 0) | |
2785 | { | |
2786 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, | |
2787 | fixups[0].exp.X_add_symbol, | |
2788 | fixups[0].exp.X_add_number, | |
2789 | (char *)(size_t) fixups[0].opindex); | |
2790 | md_number_to_chars (f, insn, insn_size); | |
2791 | md_number_to_chars (f + 2, 0, 6); | |
2792 | } | |
2793 | else | |
2794 | { | |
2795 | f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, | |
2796 | fixups[0].exp.X_add_symbol, | |
2797 | fixups[0].exp.X_add_number, | |
2798 | (char *)(size_t) fixups[0].opindex); | |
2799 | md_number_to_chars (f, insn, insn_size); | |
2800 | md_number_to_chars (f + 2, 0, 4); | |
2801 | } | |
2802 | } | |
2803 | else | |
2804 | { | |
2805 | if (strcmp (opcode->name, "bsa") == 0) | |
2806 | { | |
2807 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, | |
2808 | fixups[0].exp.X_add_symbol, | |
2809 | fixups[0].exp.X_add_number, | |
2810 | (char *)(size_t) fixups[0].opindex); | |
2811 | md_number_to_chars (f, insn, insn_size); | |
2812 | md_number_to_chars (f + 2, 0, 6); | |
2813 | } | |
2814 | else | |
2815 | { | |
2816 | f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, | |
2817 | fixups[0].exp.X_add_symbol, | |
2818 | fixups[0].exp.X_add_number, | |
2819 | (char *)(size_t) fixups[0].opindex); | |
2820 | md_number_to_chars (f, insn, insn_size); | |
2821 | md_number_to_chars (f + 2, 0, 4); | |
2822 | } | |
2823 | } | |
2824 | } | |
2825 | else | |
2826 | { | |
2827 | if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17) | |
2828 | { | |
2829 | if (strcmp (opcode->name, "bsa") == 0) | |
2830 | { | |
2831 | f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, | |
2832 | fixups[0].exp.X_add_symbol, | |
2833 | fixups[0].exp.X_add_number, | |
2834 | (char *)(size_t) fixups[0].opindex); | |
2835 | md_number_to_chars (f, insn, insn_size); | |
2836 | md_number_to_chars (f + 2, 0, 8); | |
2837 | } | |
2838 | else | |
2839 | { | |
2840 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, | |
2841 | fixups[0].exp.X_add_symbol, | |
2842 | fixups[0].exp.X_add_number, | |
2843 | (char *)(size_t) fixups[0].opindex); | |
2844 | md_number_to_chars (f, insn, insn_size); | |
2845 | md_number_to_chars (f + 2, 0, 6); | |
2846 | } | |
2847 | } | |
2848 | else | |
2849 | { | |
2850 | if (strcmp (opcode->name, "bsa") == 0) | |
2851 | { | |
2852 | f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, | |
2853 | fixups[0].exp.X_add_symbol, | |
2854 | fixups[0].exp.X_add_number, | |
2855 | (char *)(size_t) fixups[0].opindex); | |
2856 | md_number_to_chars (f, insn, insn_size); | |
2857 | md_number_to_chars (f + 2, 0, 8); | |
2858 | } | |
2859 | else | |
2860 | { | |
2861 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, | |
2862 | fixups[0].exp.X_add_symbol, | |
2863 | fixups[0].exp.X_add_number, | |
2864 | (char *)(size_t) fixups[0].opindex); | |
2865 | md_number_to_chars (f, insn, insn_size); | |
2866 | md_number_to_chars (f + 2, 0, 6); | |
2867 | } | |
2868 | } | |
2869 | } | |
252b5132 RH |
2870 | } |
2871 | } | |
28e4f854 | 2872 | else |
252b5132 RH |
2873 | { |
2874 | /* Four byte insns have an opcode with the two high bits on. */ | |
2875 | if ((insn & 0x0600) == 0x0600) | |
2876 | insn_size = 4; | |
2877 | else | |
2878 | insn_size = 2; | |
2879 | ||
28e4f854 | 2880 | /* Special case: 32 bit MOV. */ |
252b5132 RH |
2881 | if ((insn & 0xffe0) == 0x0620) |
2882 | insn_size = 2; | |
28e4f854 | 2883 | |
1cd986c5 NC |
2884 | /* Special case: 32 bit JARL,JMP,JR. */ |
2885 | if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ | |
2886 | || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ | |
2887 | || (insn & 0x1ffff) == 0x2e0) /* JR. */ | |
2888 | insn_size = 2; | |
2889 | ||
252b5132 | 2890 | f = frag_more (insn_size); |
252b5132 RH |
2891 | md_number_to_chars (f, insn, insn_size); |
2892 | ||
2893 | if (extra_data_after_insn) | |
2894 | { | |
2895 | f = frag_more (extra_data_len); | |
252b5132 RH |
2896 | md_number_to_chars (f, extra_data, extra_data_len); |
2897 | ||
b34976b6 | 2898 | extra_data_after_insn = FALSE; |
252b5132 RH |
2899 | } |
2900 | } | |
2901 | ||
2902 | /* Create any fixups. At this point we do not use a | |
2903 | bfd_reloc_code_real_type, but instead just use the | |
2904 | BFD_RELOC_UNUSED plus the operand index. This lets us easily | |
2905 | handle fixups for any operand type, although that is admittedly | |
2906 | not a very exciting feature. We pick a BFD reloc type in | |
55cf6793 | 2907 | md_apply_fix. */ |
252b5132 RH |
2908 | for (i = 0; i < fc; i++) |
2909 | { | |
28e4f854 KH |
2910 | const struct v850_operand *operand; |
2911 | bfd_reloc_code_real_type reloc; | |
2912 | ||
2913 | operand = &v850_operands[fixups[i].opindex]; | |
252b5132 RH |
2914 | |
2915 | reloc = fixups[i].reloc; | |
28e4f854 | 2916 | |
252b5132 RH |
2917 | if (reloc != BFD_RELOC_UNUSED) |
2918 | { | |
28e4f854 KH |
2919 | reloc_howto_type *reloc_howto = |
2920 | bfd_reloc_type_lookup (stdoutput, reloc); | |
2921 | int size; | |
2922 | int address; | |
2923 | fixS *fixP; | |
252b5132 RH |
2924 | |
2925 | if (!reloc_howto) | |
28e4f854 KH |
2926 | abort (); |
2927 | ||
252b5132 RH |
2928 | size = bfd_get_reloc_size (reloc_howto); |
2929 | ||
2930 | /* XXX This will abort on an R_V850_8 reloc - | |
28e4f854 KH |
2931 | is this reloc actually used? */ |
2932 | if (size != 2 && size != 4) | |
252b5132 RH |
2933 | abort (); |
2934 | ||
1cd986c5 NC |
2935 | if (extra_data_len == 0) |
2936 | { | |
2937 | address = (f - frag_now->fr_literal) + insn_size - size; | |
2938 | } | |
2939 | else | |
2940 | { | |
2941 | address = (f - frag_now->fr_literal) + extra_data_len - size; | |
2942 | } | |
252b5132 | 2943 | |
1cd986c5 NC |
2944 | if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) |
2945 | { | |
2946 | fixups[i].exp.X_add_number += 2; | |
2947 | } | |
2948 | else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) | |
2949 | { | |
2950 | fixups[i].exp.X_add_number += 2; | |
2951 | address += 2; | |
2952 | } | |
28e4f854 | 2953 | |
1cd986c5 | 2954 | /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ |
252b5132 | 2955 | fixP = fix_new_exp (frag_now, address, size, |
28e4f854 | 2956 | &fixups[i].exp, |
252b5132 RH |
2957 | reloc_howto->pc_relative, |
2958 | reloc); | |
2959 | ||
2d034539 NC |
2960 | fixP->tc_fix_data = (void *) operand; |
2961 | ||
252b5132 RH |
2962 | switch (reloc) |
2963 | { | |
2964 | case BFD_RELOC_LO16: | |
1cd986c5 | 2965 | case BFD_RELOC_V850_LO16_S1: |
1e50d24d | 2966 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: |
252b5132 RH |
2967 | case BFD_RELOC_HI16: |
2968 | case BFD_RELOC_HI16_S: | |
2969 | fixP->fx_no_overflow = 1; | |
2970 | break; | |
5480ccf3 NC |
2971 | default: |
2972 | break; | |
252b5132 RH |
2973 | } |
2974 | } | |
2975 | else | |
2976 | { | |
28e4f854 | 2977 | fix_new_exp (frag_now, |
252b5132 RH |
2978 | f - frag_now->fr_literal, 4, |
2979 | & fixups[i].exp, | |
1cd986c5 | 2980 | (operand->flags & V850_PCREL) != 0, |
252b5132 | 2981 | (bfd_reloc_code_real_type) (fixups[i].opindex |
28e4f854 | 2982 | + (int) BFD_RELOC_UNUSED)); |
252b5132 RH |
2983 | } |
2984 | } | |
2985 | ||
2986 | input_line_pointer = saved_input_line_pointer; | |
2987 | } | |
2988 | ||
28e4f854 KH |
2989 | /* If while processing a fixup, a reloc really needs to be created |
2990 | then it is done here. */ | |
252b5132 | 2991 | |
252b5132 | 2992 | arelent * |
ea1562b3 | 2993 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 | 2994 | { |
28e4f854 KH |
2995 | arelent *reloc; |
2996 | ||
ea1562b3 NC |
2997 | reloc = xmalloc (sizeof (arelent)); |
2998 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
28e4f854 KH |
2999 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
3000 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
e30ddb24 NC |
3001 | |
3002 | if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
3003 | || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
3004 | || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL | |
3005 | || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP | |
3006 | || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) | |
3007 | reloc->addend = fixp->fx_offset; | |
3008 | else | |
3009 | { | |
1cd986c5 | 3010 | #if 0 |
e30ddb24 NC |
3011 | if (fixp->fx_r_type == BFD_RELOC_32 |
3012 | && fixp->fx_pcrel) | |
3013 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
1cd986c5 | 3014 | #endif |
e30ddb24 NC |
3015 | |
3016 | reloc->addend = fixp->fx_addnumber; | |
3017 | } | |
3018 | ||
ec178e1b | 3019 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
252b5132 | 3020 | |
ea1562b3 | 3021 | if (reloc->howto == NULL) |
252b5132 RH |
3022 | { |
3023 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
28e4f854 KH |
3024 | /* xgettext:c-format */ |
3025 | _("reloc %d not supported by object file format"), | |
252b5132 RH |
3026 | (int) fixp->fx_r_type); |
3027 | ||
3028 | xfree (reloc); | |
28e4f854 | 3029 | |
252b5132 RH |
3030 | return NULL; |
3031 | } | |
28e4f854 | 3032 | |
252b5132 RH |
3033 | return reloc; |
3034 | } | |
3035 | ||
86aba9db | 3036 | void |
ea1562b3 | 3037 | v850_handle_align (fragS * frag) |
86aba9db NC |
3038 | { |
3039 | if (v850_relax | |
3040 | && frag->fr_type == rs_align | |
3041 | && frag->fr_address + frag->fr_fix > 0 | |
3042 | && frag->fr_offset > 1 | |
3043 | && now_seg != bss_section | |
3044 | && now_seg != v850_seg_table[SBSS_SECTION].s | |
3045 | && now_seg != v850_seg_table[TBSS_SECTION].s | |
3046 | && now_seg != v850_seg_table[ZBSS_SECTION].s) | |
3047 | fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, | |
ec178e1b | 3048 | BFD_RELOC_V850_ALIGN); |
86aba9db NC |
3049 | } |
3050 | ||
606ab118 | 3051 | /* Return current size of variable part of frag. */ |
28e4f854 | 3052 | |
252b5132 | 3053 | int |
ea1562b3 | 3054 | md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) |
252b5132 | 3055 | { |
606ab118 | 3056 | if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) |
252b5132 | 3057 | abort (); |
606ab118 AM |
3058 | |
3059 | return md_relax_table[fragp->fr_subtype].rlx_length; | |
28e4f854 | 3060 | } |
252b5132 RH |
3061 | |
3062 | long | |
ea1562b3 | 3063 | v850_pcrel_from_section (fixS *fixp, segT section) |
252b5132 RH |
3064 | { |
3065 | /* If the symbol is undefined, or in a section other than our own, | |
d6c497c7 | 3066 | or it is weak (in which case it may well be in another section, |
252b5132 RH |
3067 | then let the linker figure it out. */ |
3068 | if (fixp->fx_addsy != (symbolS *) NULL | |
3069 | && (! S_IS_DEFINED (fixp->fx_addsy) | |
d6c497c7 | 3070 | || S_IS_WEAK (fixp->fx_addsy) |
252b5132 | 3071 | || (S_GET_SEGMENT (fixp->fx_addsy) != section))) |
d6c497c7 | 3072 | return 0; |
28e4f854 | 3073 | |
252b5132 RH |
3074 | return fixp->fx_frag->fr_address + fixp->fx_where; |
3075 | } | |
3076 | ||
94f592af | 3077 | void |
55cf6793 | 3078 | md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 3079 | { |
94f592af | 3080 | valueT value = * valueP; |
28e4f854 | 3081 | char *where; |
252b5132 | 3082 | |
94f592af | 3083 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
86aba9db NC |
3084 | || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL |
3085 | || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP | |
94f592af | 3086 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
252b5132 | 3087 | { |
94f592af NC |
3088 | fixP->fx_done = 0; |
3089 | return; | |
252b5132 RH |
3090 | } |
3091 | ||
94f592af | 3092 | if (fixP->fx_addsy == (symbolS *) NULL) |
86aba9db | 3093 | fixP->fx_addnumber = value, |
94f592af NC |
3094 | fixP->fx_done = 1; |
3095 | ||
3096 | else if (fixP->fx_pcrel) | |
86aba9db | 3097 | fixP->fx_addnumber = fixP->fx_offset; |
94f592af | 3098 | |
252b5132 RH |
3099 | else |
3100 | { | |
94f592af NC |
3101 | value = fixP->fx_offset; |
3102 | if (fixP->fx_subsy != (symbolS *) NULL) | |
252b5132 | 3103 | { |
94f592af NC |
3104 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) |
3105 | value -= S_GET_VALUE (fixP->fx_subsy); | |
252b5132 | 3106 | else |
ea1562b3 NC |
3107 | /* We don't actually support subtracting a symbol. */ |
3108 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3109 | _("expression too complex")); | |
252b5132 | 3110 | } |
86aba9db | 3111 | fixP->fx_addnumber = value; |
252b5132 RH |
3112 | } |
3113 | ||
94f592af | 3114 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
252b5132 | 3115 | { |
28e4f854 KH |
3116 | int opindex; |
3117 | const struct v850_operand *operand; | |
3118 | unsigned long insn; | |
1cd986c5 | 3119 | const char *errmsg = NULL; |
252b5132 | 3120 | |
94f592af | 3121 | opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; |
28e4f854 | 3122 | operand = &v850_operands[opindex]; |
252b5132 RH |
3123 | |
3124 | /* Fetch the instruction, insert the fully resolved operand | |
ec178e1b | 3125 | value, and stuff the instruction back again. |
252b5132 RH |
3126 | |
3127 | Note the instruction has been stored in little endian | |
3128 | format! */ | |
94f592af | 3129 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 3130 | |
1cd986c5 NC |
3131 | if (fixP->fx_size > 2) |
3132 | insn = bfd_getl32 ((unsigned char *) where); | |
3133 | else | |
3134 | insn = bfd_getl16 ((unsigned char *) where); | |
3135 | ||
252b5132 | 3136 | insn = v850_insert_operand (insn, operand, (offsetT) value, |
1cd986c5 NC |
3137 | &errmsg); |
3138 | if (errmsg) | |
cd94c7fb | 3139 | as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); |
1cd986c5 NC |
3140 | |
3141 | if (fixP->fx_size > 2) | |
3142 | bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); | |
3143 | else | |
3144 | bfd_putl16 ((bfd_vma) insn, (unsigned char *) where); | |
252b5132 | 3145 | |
94f592af NC |
3146 | if (fixP->fx_done) |
3147 | /* Nothing else to do here. */ | |
3148 | return; | |
252b5132 | 3149 | |
28e4f854 KH |
3150 | /* Determine a BFD reloc value based on the operand information. |
3151 | We are only prepared to turn a few of the operands into relocs. */ | |
252b5132 | 3152 | |
1cd986c5 | 3153 | if (operand->default_reloc == BFD_RELOC_NONE) |
252b5132 | 3154 | { |
94f592af | 3155 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28e4f854 | 3156 | _("unresolved expression that must be resolved")); |
94f592af NC |
3157 | fixP->fx_done = 1; |
3158 | return; | |
252b5132 | 3159 | } |
1cd986c5 NC |
3160 | |
3161 | { | |
3162 | fixP->fx_r_type = operand->default_reloc; | |
3163 | if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) | |
3164 | { | |
3165 | fixP->fx_where += 2; | |
3166 | fixP->fx_size = 2; | |
3167 | fixP->fx_addnumber += 2; | |
3168 | } | |
3169 | } | |
252b5132 | 3170 | } |
94f592af | 3171 | else if (fixP->fx_done) |
252b5132 RH |
3172 | { |
3173 | /* We still have to insert the value into memory! */ | |
94f592af | 3174 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 3175 | |
a0ef61f7 | 3176 | if (fixP->tc_fix_data != NULL |
1cd986c5 NC |
3177 | && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) |
3178 | { | |
3179 | const char * message = NULL; | |
3180 | struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data; | |
3181 | unsigned long insn; | |
3182 | ||
3183 | /* The variable "where" currently points at the exact point inside | |
3184 | the insn where we need to insert the value. But we need to | |
3185 | extract the entire insn so we probably need to move "where" | |
3186 | back a few bytes. */ | |
3187 | ||
3188 | if (fixP->fx_size == 2) | |
3189 | where -= 2; | |
3190 | else if (fixP->fx_size == 1) | |
3191 | where -= 3; | |
3192 | ||
3193 | insn = bfd_getl32 ((unsigned char *) where); | |
3194 | ||
3195 | /* Use the operand's insertion procedure, if present, in order to | |
3196 | make sure that the value is correctly stored in the insn. */ | |
3197 | insn = operand->insert (insn, (offsetT) value, & message); | |
3198 | /* Ignore message even if it is set. */ | |
3199 | ||
3200 | bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); | |
3201 | } | |
2d034539 | 3202 | else |
1cd986c5 NC |
3203 | { |
3204 | switch (fixP->fx_r_type) | |
3205 | { | |
3206 | case BFD_RELOC_V850_32_ABS: | |
3207 | case BFD_RELOC_V850_32_PCREL: | |
3208 | bfd_putl32 (value & 0xfffffffe, (unsigned char *) where); | |
3209 | break; | |
3210 | ||
3211 | case BFD_RELOC_32: | |
3212 | bfd_putl32 (value, (unsigned char *) where); | |
3213 | break; | |
3214 | ||
3215 | case BFD_RELOC_V850_23: | |
3216 | bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) | |
3217 | | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), | |
3218 | (unsigned char *) where); | |
3219 | break; | |
3220 | ||
3221 | case BFD_RELOC_16: | |
3222 | case BFD_RELOC_HI16: | |
3223 | case BFD_RELOC_HI16_S: | |
3224 | case BFD_RELOC_LO16: | |
3225 | case BFD_RELOC_V850_ZDA_16_16_OFFSET: | |
3226 | case BFD_RELOC_V850_SDA_16_16_OFFSET: | |
3227 | case BFD_RELOC_V850_TDA_16_16_OFFSET: | |
3228 | case BFD_RELOC_V850_CALLT_16_16_OFFSET: | |
3229 | bfd_putl16 (value & 0xffff, (unsigned char *) where); | |
3230 | break; | |
3231 | ||
3232 | case BFD_RELOC_8: | |
3233 | *where = value & 0xff; | |
3234 | break; | |
3235 | ||
3236 | case BFD_RELOC_V850_9_PCREL: | |
3237 | bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) | |
3238 | | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); | |
3239 | break; | |
3240 | ||
3241 | case BFD_RELOC_V850_17_PCREL: | |
3242 | bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) | |
3243 | | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); | |
3244 | break; | |
3245 | ||
3246 | case BFD_RELOC_V850_16_PCREL: | |
de863c74 NC |
3247 | bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001), |
3248 | (unsigned char *) (where + 2)); | |
1cd986c5 NC |
3249 | break; |
3250 | ||
3251 | case BFD_RELOC_V850_22_PCREL: | |
3252 | bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) | |
3253 | | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); | |
3254 | break; | |
3255 | ||
3256 | case BFD_RELOC_V850_16_S1: | |
3257 | case BFD_RELOC_V850_LO16_S1: | |
3258 | case BFD_RELOC_V850_ZDA_15_16_OFFSET: | |
3259 | case BFD_RELOC_V850_SDA_15_16_OFFSET: | |
3260 | bfd_putl16 (value & 0xfffe, (unsigned char *) where); | |
3261 | break; | |
3262 | ||
3263 | case BFD_RELOC_V850_16_SPLIT_OFFSET: | |
3264 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: | |
3265 | case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: | |
3266 | case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: | |
3267 | bfd_putl32 (((value << 16) & 0xfffe0000) | |
3268 | | ((value << 5) & 0x20) | |
3269 | | (bfd_getl32 (where) & ~0xfffe0020), where); | |
3270 | break; | |
3271 | ||
3272 | case BFD_RELOC_V850_TDA_6_8_OFFSET: | |
3273 | *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); | |
3274 | break; | |
3275 | ||
3276 | case BFD_RELOC_V850_TDA_7_8_OFFSET: | |
3277 | *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); | |
3278 | break; | |
3279 | ||
3280 | case BFD_RELOC_V850_TDA_7_7_OFFSET: | |
3281 | *where = (*where & ~0x7f) | (value & 0x7f); | |
3282 | break; | |
3283 | ||
3284 | case BFD_RELOC_V850_TDA_4_5_OFFSET: | |
3285 | *where = (*where & ~0xf) | ((value >> 1) & 0xf); | |
3286 | break; | |
3287 | ||
3288 | case BFD_RELOC_V850_TDA_4_4_OFFSET: | |
3289 | *where = (*where & ~0xf) | (value & 0xf); | |
3290 | break; | |
3291 | ||
3292 | case BFD_RELOC_V850_CALLT_6_7_OFFSET: | |
3293 | *where = (*where & ~0x3f) | (value & 0x3f); | |
3294 | break; | |
3295 | ||
3296 | default: | |
3297 | abort (); | |
3298 | } | |
3299 | } | |
252b5132 | 3300 | } |
252b5132 | 3301 | } |
1cd986c5 | 3302 | |
252b5132 RH |
3303 | /* Parse a cons expression. We have to handle hi(), lo(), etc |
3304 | on the v850. */ | |
28e4f854 | 3305 | |
252b5132 | 3306 | void |
ea1562b3 | 3307 | parse_cons_expression_v850 (expressionS *exp) |
252b5132 | 3308 | { |
1cd986c5 | 3309 | const char *errmsg; |
252b5132 | 3310 | /* See if there's a reloc prefix like hi() we have to handle. */ |
1cd986c5 | 3311 | hold_cons_reloc = v850_reloc_prefix (NULL, &errmsg); |
252b5132 RH |
3312 | |
3313 | /* Do normal expression parsing. */ | |
3314 | expression (exp); | |
3315 | } | |
3316 | ||
3317 | /* Create a fixup for a cons expression. If parse_cons_expression_v850 | |
3318 | found a reloc prefix, then we use that reloc, else we choose an | |
3319 | appropriate one based on the size of the expression. */ | |
28e4f854 | 3320 | |
252b5132 | 3321 | void |
ea1562b3 NC |
3322 | cons_fix_new_v850 (fragS *frag, |
3323 | int where, | |
3324 | int size, | |
3325 | expressionS *exp) | |
252b5132 RH |
3326 | { |
3327 | if (hold_cons_reloc == BFD_RELOC_UNUSED) | |
3328 | { | |
3329 | if (size == 4) | |
3330 | hold_cons_reloc = BFD_RELOC_32; | |
3331 | if (size == 2) | |
3332 | hold_cons_reloc = BFD_RELOC_16; | |
3333 | if (size == 1) | |
3334 | hold_cons_reloc = BFD_RELOC_8; | |
3335 | } | |
3336 | ||
3337 | if (exp != NULL) | |
3338 | fix_new_exp (frag, where, size, exp, 0, hold_cons_reloc); | |
3339 | else | |
3340 | fix_new (frag, where, size, NULL, 0, 0, hold_cons_reloc); | |
a8761a19 DD |
3341 | |
3342 | hold_cons_reloc = BFD_RELOC_UNUSED; | |
252b5132 | 3343 | } |
d6c497c7 | 3344 | |
b34976b6 | 3345 | bfd_boolean |
ea1562b3 | 3346 | v850_fix_adjustable (fixS *fixP) |
252b5132 | 3347 | { |
252b5132 RH |
3348 | if (fixP->fx_addsy == NULL) |
3349 | return 1; | |
28e4f854 | 3350 | |
28e4f854 | 3351 | /* Don't adjust function names. */ |
252b5132 RH |
3352 | if (S_IS_FUNCTION (fixP->fx_addsy)) |
3353 | return 0; | |
3354 | ||
28e4f854 KH |
3355 | /* We need the symbol name for the VTABLE entries. */ |
3356 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
252b5132 RH |
3357 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3358 | return 0; | |
28e4f854 | 3359 | |
252b5132 RH |
3360 | return 1; |
3361 | } | |
28e4f854 | 3362 | |
252b5132 | 3363 | int |
ea1562b3 | 3364 | v850_force_relocation (struct fix *fixP) |
252b5132 | 3365 | { |
a161fe53 | 3366 | if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL |
86aba9db NC |
3367 | || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) |
3368 | return 1; | |
3369 | ||
3370 | if (v850_relax | |
3371 | && (fixP->fx_pcrel | |
a161fe53 | 3372 | || fixP->fx_r_type == BFD_RELOC_V850_ALIGN |
a161fe53 | 3373 | || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL |
1cd986c5 NC |
3374 | || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL |
3375 | || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL | |
3376 | || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL | |
3377 | || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL | |
a161fe53 | 3378 | || fixP->fx_r_type >= BFD_RELOC_UNUSED)) |
86aba9db NC |
3379 | return 1; |
3380 | ||
ae6063d4 | 3381 | return generic_force_reloc (fixP); |
252b5132 | 3382 | } |