Commit | Line | Data |
---|---|---|
b6605ddd EB |
1 | /* This is the machine dependent code of the Visium Assembler. |
2 | ||
250d07de | 3 | Copyright (C) 2005-2021 Free Software Foundation, Inc. |
b6605ddd EB |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
863f7a5f NC |
18 | along with this program; if not, write to the Free Software |
19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
b6605ddd EB |
21 | |
22 | #include "as.h" | |
23 | #include "safe-ctype.h" | |
24 | #include "subsegs.h" | |
25 | #include "obstack.h" | |
26 | ||
27 | #include "opcode/visium.h" | |
28 | #include "elf/visium.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
32 | /* Relocations and fixups: | |
33 | ||
34 | There are two different cases where an instruction or data | |
35 | directive operand requires relocation, or fixup. | |
36 | ||
37 | 1. Relative branch instructions, take an 16-bit signed word | |
38 | offset. The formula for computing the offset is this: | |
39 | ||
40 | offset = (destination - pc) / 4 | |
41 | ||
42 | Branch instructions never branch to a label not declared | |
43 | locally, so the actual offset can always be computed by the assembler. | |
44 | However, we provide a relocation type to support this. | |
45 | ||
46 | 2. Load literal instructions, such as MOVIU, which take a 16-bit | |
47 | literal operand. The literal may be the top or bottom half of | |
48 | a 32-bit value computed by the assembler, or by the linker. We provide | |
49 | two relocation types here. | |
50 | ||
51 | 3. Data items (long, word and byte) preset with a value computed by | |
52 | the linker. */ | |
53 | ||
54 | ||
55 | /* This string holds the chars that always start a comment. If the | |
56 | pre-processor is disabled, these aren't very useful. The macro | |
57 | tc_comment_chars points to this. */ | |
58 | const char *visium_comment_chars = "!;"; | |
59 | ||
60 | /* This array holds the chars that only start a comment at the beginning | |
61 | of a line. If the line seems to have the form '# 123 filename' .line | |
62 | and .file directives will appear in the pre-processed output. Note that | |
63 | input_file.c hand checks for '#' at the beginning of the first line of | |
64 | the input file. This is because the compiler outputs #NO_APP at the | |
65 | beginning of its output. Also note that comments like this one will | |
66 | always work. */ | |
67 | const char line_comment_chars[] = "#!;"; | |
68 | const char line_separator_chars[] = ""; | |
69 | ||
70 | /* Chars that can be used to separate mantissa from exponent in floating point | |
71 | numbers. */ | |
72 | const char EXP_CHARS[] = "eE"; | |
73 | ||
74 | /* Chars that mean this number is a floating point constant, as in | |
75 | "0f12.456" or "0d1.2345e12". | |
76 | ||
77 | ...Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
78 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
79 | but nothing is ideal around here. */ | |
80 | const char FLT_CHARS[] = "rRsSfFdDxXeE"; | |
81 | ||
82 | /* The size of a relocation record. */ | |
83 | const int md_reloc_size = 8; | |
84 | ||
85 | /* The architecture for which we are assembling. */ | |
86 | enum visium_arch_val | |
87 | { | |
88 | VISIUM_ARCH_DEF, | |
89 | VISIUM_ARCH_MCM24, | |
90 | VISIUM_ARCH_MCM, | |
91 | VISIUM_ARCH_GR6 | |
92 | }; | |
93 | ||
94 | static enum visium_arch_val visium_arch = VISIUM_ARCH_DEF; | |
95 | ||
96 | /* The opcode architecture for which we are assembling. In contrast to the | |
97 | previous one, this only determines which instructions are supported. */ | |
98 | static enum visium_opcode_arch_val visium_opcode_arch = VISIUM_OPCODE_ARCH_DEF; | |
99 | ||
100 | /* Flags to set in the ELF header e_flags field. */ | |
101 | static flagword visium_flags = 0; | |
102 | ||
103 | /* More than this number of nops in an alignment op gets a branch instead. */ | |
104 | static unsigned int nop_limit = 5; | |
105 | ||
106 | ||
107 | /* Translate internal representation of relocation info to BFD target | |
108 | format. */ | |
109 | arelent * | |
110 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
111 | { | |
112 | arelent *reloc; | |
113 | bfd_reloc_code_real_type code; | |
114 | ||
add39d23 | 115 | reloc = XNEW (arelent); |
b6605ddd | 116 | |
add39d23 | 117 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
b6605ddd EB |
118 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
119 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
120 | ||
121 | switch (fixp->fx_r_type) | |
122 | { | |
123 | case BFD_RELOC_8: | |
124 | case BFD_RELOC_16: | |
125 | case BFD_RELOC_32: | |
126 | case BFD_RELOC_8_PCREL: | |
127 | case BFD_RELOC_16_PCREL: | |
128 | case BFD_RELOC_32_PCREL: | |
129 | case BFD_RELOC_VISIUM_HI16: | |
130 | case BFD_RELOC_VISIUM_LO16: | |
131 | case BFD_RELOC_VISIUM_IM16: | |
132 | case BFD_RELOC_VISIUM_REL16: | |
133 | case BFD_RELOC_VISIUM_HI16_PCREL: | |
134 | case BFD_RELOC_VISIUM_LO16_PCREL: | |
135 | case BFD_RELOC_VISIUM_IM16_PCREL: | |
136 | case BFD_RELOC_VTABLE_INHERIT: | |
137 | case BFD_RELOC_VTABLE_ENTRY: | |
138 | code = fixp->fx_r_type; | |
139 | break; | |
140 | default: | |
141 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
142 | "internal error: unknown relocation type %d (`%s')", | |
143 | fixp->fx_r_type, | |
144 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
145 | return 0; | |
146 | } | |
147 | ||
148 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
149 | if (reloc->howto == 0) | |
150 | { | |
151 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
152 | "internal error: can't export reloc type %d (`%s')", | |
153 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | /* Write the addend. */ | |
158 | if (reloc->howto->pc_relative == 0) | |
159 | reloc->addend = fixp->fx_addnumber; | |
160 | else | |
161 | reloc->addend = fixp->fx_offset; | |
162 | ||
163 | return reloc; | |
164 | } | |
165 | ||
166 | extern char *input_line_pointer; | |
167 | ||
168 | ||
169 | static void s_bss (int); | |
170 | static void visium_rdata (int); | |
171 | ||
172 | static void visium_update_parity_bit (char *); | |
173 | static char *parse_exp (char *, expressionS *); | |
174 | ||
175 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
176 | void demand_empty_rest_of_line (void); | |
177 | ||
178 | ||
179 | static void | |
180 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
181 | { | |
182 | /* We don't support putting frags in the BSS segment, we fake it | |
183 | by marking in_bss, then looking at s_skip for clues. */ | |
184 | ||
185 | subseg_set (bss_section, 0); | |
186 | demand_empty_rest_of_line (); | |
187 | } | |
188 | ||
189 | ||
190 | /* This table describes all the machine specific pseudo-ops the assembler | |
191 | has to support. The fields are: | |
192 | ||
193 | 1: Pseudo-op name without dot. | |
194 | 2: Function to call to execute this pseudo-op. | |
195 | 3: Integer arg to pass to the function. */ | |
196 | const pseudo_typeS md_pseudo_table[] = | |
197 | { | |
198 | {"bss", s_bss, 0}, | |
199 | {"skip", s_space, 0}, | |
200 | {"align", s_align_bytes, 0}, | |
201 | {"noopt", s_ignore, 0}, | |
202 | {"optim", s_ignore, 0}, | |
203 | {"rdata", visium_rdata, 0}, | |
204 | {"rodata", visium_rdata, 0}, | |
205 | {0, 0, 0} | |
206 | }; | |
207 | ||
208 | ||
209 | static void | |
210 | visium_rdata (int xxx) | |
211 | { | |
212 | char *save_line = input_line_pointer; | |
213 | static char section[] = ".rodata\n"; | |
214 | ||
215 | /* Just pretend this is .section .rodata */ | |
216 | input_line_pointer = section; | |
217 | obj_elf_section (xxx); | |
218 | input_line_pointer = save_line; | |
219 | } | |
220 | ||
221 | /* Align a section. */ | |
222 | valueT | |
223 | md_section_align (asection *seg, valueT addr) | |
224 | { | |
fd361982 | 225 | int align = bfd_section_alignment (seg); |
b6605ddd | 226 | |
8d3842cd | 227 | return ((addr + (1 << align) - 1) & -(1 << align)); |
b6605ddd EB |
228 | } |
229 | ||
230 | void | |
231 | md_number_to_chars (char *buf, valueT val, int n) | |
232 | { | |
233 | number_to_chars_bigendian (buf, val, n); | |
234 | } | |
235 | ||
236 | symbolS * | |
237 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) | |
238 | { | |
239 | return 0; | |
240 | } | |
241 | ||
242 | /* The parse options. */ | |
243 | const char *md_shortopts = "m:"; | |
244 | ||
245 | struct option md_longopts[] = | |
246 | { | |
247 | {NULL, no_argument, NULL, 0} | |
248 | }; | |
249 | ||
250 | size_t md_longopts_size = sizeof (md_longopts); | |
251 | ||
252 | struct visium_option_table | |
253 | { | |
254 | char *option; /* Option name to match. */ | |
255 | char *help; /* Help information. */ | |
256 | int *var; /* Variable to change. */ | |
257 | int value; /* To what to change it. */ | |
258 | char *deprecated; /* If non-null, print this message. */ | |
259 | }; | |
260 | ||
261 | static struct visium_option_table visium_opts[] = | |
262 | { | |
263 | {NULL, NULL, NULL, 0, NULL} | |
264 | }; | |
265 | ||
266 | struct visium_arch_option_table | |
267 | { | |
e0471c16 | 268 | const char *name; |
b6605ddd EB |
269 | enum visium_arch_val value; |
270 | }; | |
271 | ||
272 | static struct visium_arch_option_table visium_archs[] = | |
273 | { | |
274 | {"mcm24", VISIUM_ARCH_MCM24}, | |
275 | {"mcm", VISIUM_ARCH_MCM}, | |
276 | {"gr5", VISIUM_ARCH_MCM}, | |
277 | {"gr6", VISIUM_ARCH_GR6}, | |
b6605ddd EB |
278 | }; |
279 | ||
280 | struct visium_long_option_table | |
281 | { | |
e0471c16 TS |
282 | const char *option; /* Substring to match. */ |
283 | const char *help; /* Help information. */ | |
17b9d67d | 284 | int (*func) (const char *subopt); /* Function to decode sub-option. */ |
e0471c16 | 285 | const char *deprecated; /* If non-null, print this message. */ |
b6605ddd EB |
286 | }; |
287 | ||
288 | static int | |
17b9d67d | 289 | visium_parse_arch (const char *str) |
b6605ddd | 290 | { |
5703197e | 291 | unsigned int i; |
b6605ddd EB |
292 | |
293 | if (strlen (str) == 0) | |
294 | { | |
295 | as_bad ("missing architecture name `%s'", str); | |
296 | return 0; | |
297 | } | |
298 | ||
5703197e TS |
299 | for (i = 0; i < ARRAY_SIZE (visium_archs); i++) |
300 | if (strcmp (visium_archs[i].name, str) == 0) | |
b6605ddd | 301 | { |
5703197e | 302 | visium_arch = visium_archs[i].value; |
b6605ddd EB |
303 | return 1; |
304 | } | |
305 | ||
306 | as_bad ("unknown architecture `%s'\n", str); | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static struct visium_long_option_table visium_long_opts[] = | |
311 | { | |
312 | {"mtune=", "<arch_name>\t assemble for architecture <arch name>", | |
313 | visium_parse_arch, NULL}, | |
314 | {NULL, NULL, NULL, NULL} | |
315 | }; | |
316 | ||
317 | int | |
17b9d67d | 318 | md_parse_option (int c, const char *arg) |
b6605ddd EB |
319 | { |
320 | struct visium_option_table *opt; | |
321 | struct visium_long_option_table *lopt; | |
322 | ||
323 | switch (c) | |
324 | { | |
325 | case 'a': | |
326 | /* Listing option. Just ignore these, we don't support additional | |
327 | ones. */ | |
328 | return 0; | |
329 | ||
330 | default: | |
331 | for (opt = visium_opts; opt->option != NULL; opt++) | |
332 | { | |
333 | if (c == opt->option[0] | |
334 | && ((arg == NULL && opt->option[1] == 0) | |
335 | || strcmp (arg, opt->option + 1) == 0)) | |
336 | { | |
337 | /* If the option is deprecated, tell the user. */ | |
338 | if (opt->deprecated != NULL) | |
339 | as_tsktsk ("option `-%c%s' is deprecated: %s", c, | |
340 | arg ? arg : "", opt->deprecated); | |
341 | ||
342 | if (opt->var != NULL) | |
343 | *opt->var = opt->value; | |
344 | ||
345 | return 1; | |
346 | } | |
347 | } | |
348 | ||
349 | for (lopt = visium_long_opts; lopt->option != NULL; lopt++) | |
350 | { | |
351 | /* These options are expected to have an argument. */ | |
352 | if (c == lopt->option[0] | |
353 | && arg != NULL | |
354 | && strncmp (arg, lopt->option + 1, | |
355 | strlen (lopt->option + 1)) == 0) | |
356 | { | |
357 | /* If the option is deprecated, tell the user. */ | |
358 | if (lopt->deprecated != NULL) | |
359 | as_tsktsk ("option `-%c%s' is deprecated: %s", c, arg, | |
360 | lopt->deprecated); | |
361 | ||
362 | /* Call the sup-option parser. */ | |
363 | return lopt->func (arg + strlen (lopt->option) - 1); | |
364 | } | |
365 | } | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | return 1; | |
371 | } | |
372 | ||
373 | void | |
374 | md_show_usage (FILE * fp) | |
375 | { | |
376 | struct visium_option_table *opt; | |
377 | struct visium_long_option_table *lopt; | |
378 | ||
379 | fprintf (fp, " Visium-specific assembler options:\n"); | |
380 | ||
381 | for (opt = visium_opts; opt->option != NULL; opt++) | |
382 | if (opt->help != NULL) | |
383 | fprintf (fp, " -%-23s%s\n", opt->option, opt->help); | |
384 | ||
385 | for (lopt = visium_long_opts; lopt->option != NULL; lopt++) | |
386 | if (lopt->help != NULL) | |
387 | fprintf (fp, " -%s%s\n", lopt->option, lopt->help); | |
388 | ||
389 | } | |
390 | ||
391 | /* Interface to relax_segment. */ | |
392 | ||
393 | /* Return the estimate of the size of a machine dependent frag | |
394 | before any relaxing is done. It may also create any necessary | |
395 | relocations. */ | |
396 | int | |
397 | md_estimate_size_before_relax (fragS * fragP, | |
398 | segT segment ATTRIBUTE_UNUSED) | |
399 | { | |
400 | fragP->fr_var = 4; | |
401 | return 4; | |
402 | } | |
403 | ||
404 | /* Get the address of a symbol during relaxation. From tc-arm.c. */ | |
405 | static addressT | |
406 | relaxed_symbol_addr (fragS *fragp, long stretch) | |
407 | { | |
408 | fragS *sym_frag; | |
409 | addressT addr; | |
410 | symbolS *sym; | |
411 | ||
412 | sym = fragp->fr_symbol; | |
413 | sym_frag = symbol_get_frag (sym); | |
414 | know (S_GET_SEGMENT (sym) != absolute_section | |
415 | || sym_frag == &zero_address_frag); | |
416 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
417 | ||
418 | /* If frag has yet to be reached on this pass, assume it will | |
419 | move by STRETCH just as we did. If this is not so, it will | |
420 | be because some frag between grows, and that will force | |
421 | another pass. */ | |
422 | if (stretch != 0 | |
423 | && sym_frag->relax_marker != fragp->relax_marker) | |
424 | { | |
425 | fragS *f; | |
426 | ||
427 | /* Adjust stretch for any alignment frag. Note that if have | |
428 | been expanding the earlier code, the symbol may be | |
429 | defined in what appears to be an earlier frag. FIXME: | |
430 | This doesn't handle the fr_subtype field, which specifies | |
431 | a maximum number of bytes to skip when doing an | |
432 | alignment. */ | |
433 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
434 | { | |
435 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
436 | { | |
437 | if (stretch < 0) | |
438 | stretch = - ((- stretch) | |
439 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
440 | else | |
441 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
442 | if (stretch == 0) | |
443 | break; | |
444 | } | |
445 | } | |
446 | if (f != NULL) | |
447 | addr += stretch; | |
448 | } | |
449 | ||
450 | return addr; | |
451 | } | |
452 | ||
453 | /* Relax a machine dependent frag. This returns the amount by which | |
454 | the current size of the frag should change. */ | |
455 | int | |
456 | visium_relax_frag (asection *sec, fragS *fragP, long stretch) | |
457 | { | |
458 | int old_size, new_size; | |
459 | addressT addr; | |
460 | ||
461 | /* We only handle relaxation for the BRR instruction. */ | |
462 | gas_assert (fragP->fr_subtype == mode_ci); | |
463 | ||
464 | if (!S_IS_DEFINED (fragP->fr_symbol) | |
465 | || sec != S_GET_SEGMENT (fragP->fr_symbol) | |
466 | || S_IS_WEAK (fragP->fr_symbol)) | |
467 | return 0; | |
468 | ||
469 | old_size = fragP->fr_var; | |
470 | addr = relaxed_symbol_addr (fragP, stretch); | |
471 | ||
472 | /* If the target is the address of the instruction, we'll insert a NOP. */ | |
473 | if (addr == fragP->fr_address + fragP->fr_fix) | |
474 | new_size = 8; | |
475 | else | |
476 | new_size = 4; | |
477 | ||
478 | fragP->fr_var = new_size; | |
479 | return new_size - old_size; | |
480 | } | |
481 | ||
482 | /* Convert a machine dependent frag. */ | |
483 | void | |
484 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, | |
485 | fragS * fragP) | |
486 | { | |
8bbc5da5 | 487 | char *buf = &fragP->fr_literal[0] + fragP->fr_fix; |
b6605ddd EB |
488 | expressionS exp; |
489 | fixS *fixP; | |
490 | ||
491 | /* We only handle relaxation for the BRR instruction. */ | |
492 | gas_assert (fragP->fr_subtype == mode_ci); | |
493 | ||
494 | /* Insert the NOP if requested. */ | |
495 | if (fragP->fr_var == 8) | |
496 | { | |
497 | memcpy (buf + 4, buf, 4); | |
498 | memset (buf, 0, 4); | |
499 | fragP->fr_fix += 4; | |
500 | } | |
501 | ||
502 | exp.X_op = O_symbol; | |
503 | exp.X_add_symbol = fragP->fr_symbol; | |
504 | exp.X_add_number = fragP->fr_offset; | |
505 | ||
506 | /* Now we can create the relocation at the correct offset. */ | |
507 | fixP = fix_new_exp (fragP, fragP->fr_fix, 4, &exp, 1, BFD_RELOC_VISIUM_REL16); | |
508 | fixP->fx_file = fragP->fr_file; | |
509 | fixP->fx_line = fragP->fr_line; | |
510 | fragP->fr_fix += 4; | |
511 | fragP->fr_var = 0; | |
512 | } | |
513 | ||
514 | /* The location from which a PC relative jump should be calculated, | |
515 | given a PC relative jump reloc. */ | |
516 | long | |
517 | visium_pcrel_from_section (fixS *fixP, segT sec) | |
518 | { | |
519 | if (fixP->fx_addsy != (symbolS *) NULL | |
520 | && (!S_IS_DEFINED (fixP->fx_addsy) | |
521 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
522 | { | |
523 | /* The symbol is undefined (or is defined but not in this section). | |
524 | Let the linker figure it out. */ | |
525 | return 0; | |
526 | } | |
527 | ||
528 | /* Return the address of the instruction. */ | |
529 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
530 | } | |
531 | ||
532 | /* Indicate whether a fixup against a locally defined | |
533 | symbol should be adjusted to be against the section | |
534 | symbol. */ | |
535 | bfd_boolean | |
536 | visium_fix_adjustable (fixS *fix) | |
537 | { | |
538 | /* We need the symbol name for the VTABLE entries. */ | |
539 | return (fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT | |
540 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY); | |
541 | } | |
542 | ||
543 | /* Update the parity bit of the 4-byte instruction in BUF. */ | |
544 | static void | |
545 | visium_update_parity_bit (char *buf) | |
546 | { | |
547 | int p1 = (buf[0] & 0x7f) ^ buf[1] ^ buf[2] ^ buf[3]; | |
548 | int p2 = 0; | |
549 | int i; | |
550 | ||
551 | for (i = 1; i <= 8; i++) | |
552 | { | |
553 | p2 ^= (p1 & 1); | |
554 | p1 >>= 1; | |
555 | } | |
556 | ||
557 | buf[0] = (buf[0] & 0x7f) | ((p2 << 7) & 0x80); | |
558 | } | |
559 | ||
560 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents | |
561 | of an rs_align_code fragment. */ | |
562 | void | |
563 | visium_handle_align (fragS *fragP) | |
564 | { | |
565 | valueT count | |
566 | = fragP->fr_next->fr_address - (fragP->fr_address + fragP->fr_fix); | |
567 | valueT fix = count & 3; | |
568 | char *p = fragP->fr_literal + fragP->fr_fix; | |
569 | ||
570 | if (fix) | |
571 | { | |
572 | memset (p, 0, fix); | |
573 | p += fix; | |
574 | count -= fix; | |
575 | fragP->fr_fix += fix; | |
576 | } | |
577 | ||
578 | if (count == 0) | |
579 | return; | |
580 | ||
581 | fragP->fr_var = 4; | |
582 | ||
583 | if (count > 4 * nop_limit && count <= 131068) | |
584 | { | |
585 | struct frag *rest; | |
586 | ||
587 | /* Make a branch, then follow with nops. Insert another | |
588 | frag to handle the nops. */ | |
589 | md_number_to_chars (p, 0x78000000 + (count >> 2), 4); | |
590 | visium_update_parity_bit (p); | |
591 | ||
592 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
593 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
594 | fragP->fr_next = rest; | |
595 | rest->fr_address += rest->fr_fix + 4; | |
596 | rest->fr_fix = 0; | |
597 | /* If we leave the next frag as rs_align_code we'll come here | |
598 | again, resulting in a bunch of branches rather than a | |
599 | branch followed by nops. */ | |
600 | rest->fr_type = rs_align; | |
601 | p = rest->fr_literal; | |
602 | } | |
603 | ||
604 | memset (p, 0, 4); | |
605 | } | |
606 | ||
607 | /* Apply a fixS to the frags, now that we know the value it ought to | |
608 | hold. */ | |
609 | void | |
610 | md_apply_fix (fixS * fixP, valueT * value, segT segment) | |
611 | { | |
612 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
613 | offsetT val; | |
614 | long insn; | |
615 | ||
616 | val = *value; | |
617 | ||
618 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); | |
619 | ||
620 | /* Remember value for tc_gen_reloc. */ | |
621 | fixP->fx_addnumber = val; | |
622 | ||
623 | /* Since DIFF_EXPR_OK is defined, .-foo gets turned into PC | |
624 | relative relocs. If this has happened, a non-PC relative | |
625 | reloc must be reinstalled with its PC relative version here. */ | |
626 | if (fixP->fx_pcrel) | |
627 | { | |
628 | switch (fixP->fx_r_type) | |
629 | { | |
630 | case BFD_RELOC_8: | |
631 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
632 | break; | |
633 | case BFD_RELOC_16: | |
634 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
635 | break; | |
636 | case BFD_RELOC_32: | |
637 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
638 | break; | |
639 | case BFD_RELOC_VISIUM_HI16: | |
640 | fixP->fx_r_type = BFD_RELOC_VISIUM_HI16_PCREL; | |
641 | break; | |
642 | case BFD_RELOC_VISIUM_LO16: | |
643 | fixP->fx_r_type = BFD_RELOC_VISIUM_LO16_PCREL; | |
644 | break; | |
645 | case BFD_RELOC_VISIUM_IM16: | |
646 | fixP->fx_r_type = BFD_RELOC_VISIUM_IM16_PCREL; | |
647 | break; | |
648 | default: | |
649 | break; | |
650 | } | |
651 | } | |
652 | ||
653 | /* If this is a data relocation, just output VAL. */ | |
654 | switch (fixP->fx_r_type) | |
655 | { | |
656 | case BFD_RELOC_8: | |
657 | case BFD_RELOC_8_PCREL: | |
658 | md_number_to_chars (buf, val, 1); | |
659 | break; | |
660 | case BFD_RELOC_16: | |
661 | case BFD_RELOC_16_PCREL: | |
662 | md_number_to_chars (buf, val, 2); | |
663 | break; | |
664 | case BFD_RELOC_32: | |
665 | case BFD_RELOC_32_PCREL: | |
666 | md_number_to_chars (buf, val, 4); | |
667 | break; | |
668 | case BFD_RELOC_VTABLE_INHERIT: | |
669 | case BFD_RELOC_VTABLE_ENTRY: | |
670 | fixP->fx_done = 0; | |
671 | break; | |
672 | default: | |
673 | /* It's a relocation against an instruction. */ | |
674 | insn = bfd_getb32 ((unsigned char *) buf); | |
675 | ||
676 | switch (fixP->fx_r_type) | |
677 | { | |
678 | case BFD_RELOC_VISIUM_REL16: | |
679 | if (fixP->fx_addsy == NULL | |
680 | || (S_IS_DEFINED (fixP->fx_addsy) | |
681 | && S_GET_SEGMENT (fixP->fx_addsy) == segment)) | |
682 | { | |
683 | if (val > 0x1fffc || val < -0x20000) | |
684 | as_bad_where | |
685 | (fixP->fx_file, fixP->fx_line, | |
686 | "16-bit word displacement out of range: value = %d", | |
687 | (int) val); | |
688 | val = (val >> 2); | |
689 | ||
690 | insn = (insn & 0xffff0000) | (val & 0x0000ffff); | |
691 | } | |
692 | break; | |
693 | ||
694 | case BFD_RELOC_VISIUM_HI16: | |
695 | case BFD_RELOC_VISIUM_HI16_PCREL: | |
696 | if (fixP->fx_addsy == NULL) | |
697 | insn = (insn & 0xffff0000) | ((val >> 16) & 0x0000ffff); | |
698 | break; | |
699 | ||
700 | case BFD_RELOC_VISIUM_LO16: | |
701 | case BFD_RELOC_VISIUM_LO16_PCREL: | |
702 | if (fixP->fx_addsy == NULL) | |
703 | insn = (insn & 0xffff0000) | (val & 0x0000ffff); | |
704 | break; | |
705 | ||
706 | case BFD_RELOC_VISIUM_IM16: | |
707 | case BFD_RELOC_VISIUM_IM16_PCREL: | |
708 | if (fixP->fx_addsy == NULL) | |
709 | { | |
710 | if ((val & 0xffff0000) != 0) | |
711 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
712 | "16-bit immediate out of range: value = %d", | |
713 | (int) val); | |
714 | ||
715 | insn = (insn & 0xffff0000) | val; | |
716 | } | |
717 | break; | |
718 | ||
719 | case BFD_RELOC_NONE: | |
720 | default: | |
721 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
722 | "bad or unhandled relocation type: 0x%02x", | |
723 | fixP->fx_r_type); | |
724 | break; | |
725 | } | |
726 | ||
727 | bfd_putb32 (insn, (unsigned char *) buf); | |
728 | visium_update_parity_bit (buf); | |
729 | break; | |
730 | } | |
731 | ||
732 | /* Are we finished with this relocation now? */ | |
733 | if (fixP->fx_addsy == NULL) | |
734 | fixP->fx_done = 1; | |
735 | } | |
736 | ||
737 | char * | |
738 | parse_exp (char *s, expressionS * op) | |
739 | { | |
740 | char *save = input_line_pointer; | |
741 | char *new; | |
742 | ||
743 | if (!s) | |
744 | { | |
745 | return s; | |
746 | } | |
747 | ||
748 | input_line_pointer = s; | |
749 | expression (op); | |
750 | new = input_line_pointer; | |
751 | input_line_pointer = save; | |
752 | return new; | |
753 | } | |
754 | ||
755 | /* If the given string is a Visium opcode mnemonic return the code | |
756 | otherwise return -1. Use binary chop to find matching entry. */ | |
757 | static int | |
758 | get_opcode (int *code, enum addressing_mode *mode, char *flags, char *mnem) | |
759 | { | |
760 | int l = 0; | |
761 | int r = sizeof (opcode_table) / sizeof (struct opcode_entry) - 1; | |
762 | ||
763 | do | |
764 | { | |
765 | int mid = (l + r) / 2; | |
766 | int ans = strcmp (mnem, opcode_table[mid].mnem); | |
767 | ||
768 | if (ans < 0) | |
769 | r = mid - 1; | |
770 | else if (ans > 0) | |
771 | l = mid + 1; | |
772 | else | |
773 | { | |
774 | *code = opcode_table[mid].code; | |
775 | *mode = opcode_table[mid].mode; | |
776 | *flags = opcode_table[mid].flags; | |
777 | ||
778 | return 0; | |
779 | } | |
780 | } | |
781 | while (l <= r); | |
782 | ||
783 | return -1; | |
784 | } | |
785 | ||
786 | /* This function is called when the assembler starts up. It is called | |
787 | after the options have been parsed and the output file has been | |
788 | opened. */ | |
789 | void | |
790 | md_begin (void) | |
791 | { | |
792 | switch (visium_arch) | |
793 | { | |
794 | case VISIUM_ARCH_DEF: | |
795 | break; | |
796 | case VISIUM_ARCH_MCM24: | |
797 | visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5; | |
798 | visium_flags |= EF_VISIUM_ARCH_MCM24; | |
799 | break; | |
800 | case VISIUM_ARCH_MCM: | |
801 | visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5; | |
802 | visium_flags |= EF_VISIUM_ARCH_MCM; | |
803 | break; | |
804 | case VISIUM_ARCH_GR6: | |
805 | visium_opcode_arch = VISIUM_OPCODE_ARCH_GR6; | |
806 | visium_flags |= EF_VISIUM_ARCH_MCM | EF_VISIUM_ARCH_GR6; | |
807 | nop_limit = 2; | |
808 | break; | |
809 | default: | |
810 | gas_assert (0); | |
811 | } | |
812 | ||
813 | bfd_set_private_flags (stdoutput, visium_flags); | |
814 | } | |
815 | ||
816 | /* This is identical to the md_atof in m68k.c. I think this is right, | |
817 | but I'm not sure. | |
818 | ||
819 | Turn a string in input_line_pointer into a floating point constant of type | |
820 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
821 | emitted is stored in *sizeP . An error message is returned, | |
822 | or NULL on OK. */ | |
823 | ||
6d4af3c2 | 824 | const char * |
b6605ddd EB |
825 | md_atof (int type, char *litP, int *sizeP) |
826 | { | |
827 | int i, prec; | |
828 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
829 | char *t; | |
830 | ||
831 | switch (type) | |
832 | { | |
833 | case 'f': | |
834 | case 'F': | |
835 | case 's': | |
836 | case 'S': | |
837 | prec = 2; | |
838 | break; | |
839 | ||
840 | case 'd': | |
841 | case 'D': | |
842 | case 'r': | |
843 | case 'R': | |
844 | prec = 4; | |
845 | break; | |
846 | ||
847 | case 'x': | |
848 | case 'X': | |
849 | prec = 6; | |
850 | break; | |
851 | ||
852 | case 'p': | |
853 | case 'P': | |
854 | prec = 6; | |
855 | break; | |
856 | ||
857 | default: | |
858 | *sizeP = 0; | |
eda6e9a4 | 859 | return _("Bad call to MD_ATOF()"); |
b6605ddd EB |
860 | } |
861 | ||
862 | t = atof_ieee (input_line_pointer, type, words); | |
863 | if (t) | |
864 | input_line_pointer = t; | |
865 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
866 | ||
867 | if (target_big_endian) | |
868 | { | |
869 | for (i = 0; i < prec; i++) | |
870 | { | |
871 | md_number_to_chars (litP, (valueT) words[i], | |
872 | sizeof (LITTLENUM_TYPE)); | |
873 | litP += sizeof (LITTLENUM_TYPE); | |
874 | } | |
875 | } | |
876 | else | |
877 | { | |
878 | for (i = prec - 1; i >= 0; i--) | |
879 | { | |
880 | md_number_to_chars (litP, (valueT) words[i], | |
881 | sizeof (LITTLENUM_TYPE)); | |
882 | litP += sizeof (LITTLENUM_TYPE); | |
883 | } | |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
889 | static inline char * | |
890 | skip_space (char *s) | |
891 | { | |
892 | while (*s == ' ' || *s == '\t') | |
893 | ++s; | |
894 | ||
895 | return s; | |
896 | } | |
897 | ||
898 | static int | |
899 | parse_gen_reg (char **sptr, int *rptr) | |
900 | { | |
901 | char *s = skip_space (*sptr); | |
902 | char buf[10]; | |
903 | int cnt; | |
904 | int l, r; | |
905 | ||
906 | cnt = 0; | |
907 | memset (buf, '\0', 10); | |
908 | while ((ISALNUM (*s)) && cnt < 10) | |
909 | buf[cnt++] = TOLOWER (*s++); | |
910 | ||
911 | l = 0; | |
912 | r = sizeof (gen_reg_table) / sizeof (struct reg_entry) - 1; | |
913 | ||
914 | do | |
915 | { | |
916 | int mid = (l + r) / 2; | |
917 | int ans = strcmp (buf, gen_reg_table[mid].name); | |
918 | ||
919 | if (ans < 0) | |
920 | r = mid - 1; | |
921 | else if (ans > 0) | |
922 | l = mid + 1; | |
923 | else | |
924 | { | |
925 | *rptr = gen_reg_table[mid].code; | |
926 | *sptr = s; | |
927 | return 0; | |
928 | } | |
929 | } | |
930 | while (l <= r); | |
931 | ||
932 | return -1; | |
933 | } | |
934 | ||
935 | static int | |
936 | parse_fp_reg (char **sptr, int *rptr) | |
937 | { | |
938 | char *s = skip_space (*sptr); | |
939 | char buf[10]; | |
940 | int cnt; | |
941 | int l, r; | |
942 | ||
943 | cnt = 0; | |
944 | memset (buf, '\0', 10); | |
945 | while ((ISALNUM (*s)) && cnt < 10) | |
946 | buf[cnt++] = TOLOWER (*s++); | |
947 | ||
948 | l = 0; | |
949 | r = sizeof (fp_reg_table) / sizeof (struct reg_entry) - 1; | |
950 | ||
951 | do | |
952 | { | |
953 | int mid = (l + r) / 2; | |
954 | int ans = strcmp (buf, fp_reg_table[mid].name); | |
955 | ||
956 | if (ans < 0) | |
957 | r = mid - 1; | |
958 | else if (ans > 0) | |
959 | l = mid + 1; | |
960 | else | |
961 | { | |
962 | *rptr = fp_reg_table[mid].code; | |
963 | *sptr = s; | |
964 | return 0; | |
965 | } | |
966 | } | |
967 | while (l <= r); | |
968 | ||
969 | return -1; | |
970 | } | |
971 | ||
972 | static int | |
973 | parse_cc (char **sptr, int *rptr) | |
974 | { | |
975 | char *s = skip_space (*sptr); | |
976 | char buf[10]; | |
977 | int cnt; | |
978 | int l, r; | |
979 | ||
980 | cnt = 0; | |
981 | memset (buf, '\0', 10); | |
982 | while ((ISALNUM (*s)) && cnt < 10) | |
983 | buf[cnt++] = TOLOWER (*s++); | |
984 | ||
985 | l = 0; | |
986 | r = sizeof (cc_table) / sizeof (struct cc_entry) - 1; | |
987 | ||
988 | do | |
989 | { | |
990 | int mid = (l + r) / 2; | |
991 | int ans = strcmp (buf, cc_table[mid].name); | |
992 | ||
993 | if (ans < 0) | |
994 | r = mid - 1; | |
995 | else if (ans > 0) | |
996 | l = mid + 1; | |
997 | else | |
998 | { | |
999 | *rptr = cc_table[mid].code; | |
1000 | *sptr = s; | |
1001 | return 0; | |
1002 | } | |
1003 | } | |
1004 | while (l <= r); | |
1005 | ||
1006 | return -1; | |
1007 | } | |
1008 | ||
1009 | /* Previous dest is the destination register number of the instruction | |
1010 | before the current one. */ | |
1011 | static int previous_dest = 0; | |
1012 | static int previous_mode = 0; | |
1013 | static int condition_code = 0; | |
1014 | static int this_dest = 0; | |
1015 | static int this_mode = 0; | |
1016 | ||
1017 | ||
1018 | /* This is the main function in this file. It takes a line of assembly language | |
1019 | source code and assembles it. Note, labels and pseudo ops have already | |
1020 | been removed, so too has leading white space. */ | |
1021 | void | |
1022 | md_assemble (char *str0) | |
1023 | { | |
1024 | char *str = str0; | |
1025 | int cnt; | |
1026 | char mnem[10]; | |
1027 | int opcode; | |
1028 | enum addressing_mode amode; | |
1029 | char arch_flags; | |
1030 | int ans; | |
1031 | ||
1032 | char *output; | |
1033 | int reloc = 0; | |
1034 | relax_substateT relax = 0; | |
1035 | expressionS e1; | |
1036 | int r1, r2, r3; | |
1037 | int cc; | |
1038 | int indx; | |
1039 | ||
1040 | /* Initialize the expression. */ | |
1041 | e1.X_op = O_absent; | |
1042 | ||
1043 | /* Initialize destination register. | |
1044 | If the instruction we just looked at is in the delay slot of an | |
1045 | unconditional branch, then there is no index hazard. */ | |
1046 | if ((previous_mode == mode_cad || previous_mode == mode_ci) | |
1047 | && condition_code == 15) | |
1048 | this_dest = 0; | |
1049 | ||
1050 | previous_dest = this_dest; | |
1051 | previous_mode = this_mode; | |
1052 | this_dest = 0; | |
1053 | ||
1054 | /* Drop leading whitespace (probably not required). */ | |
1055 | while (*str == ' ') | |
1056 | str++; | |
1057 | ||
1058 | /* Get opcode mnemonic and make sure it's in lower case. */ | |
1059 | cnt = 0; | |
1060 | memset (mnem, '\0', 10); | |
1061 | while ((ISALNUM (*str) || *str == '.' || *str == '_') && cnt < 10) | |
1062 | mnem[cnt++] = TOLOWER (*str++); | |
1063 | ||
1064 | /* Look up mnemonic in opcode table, and get the code, | |
1065 | the instruction format, and the flags that indicate | |
33eaf5de | 1066 | which family members support this mnemonic. */ |
b6605ddd EB |
1067 | if (get_opcode (&opcode, &amode, &arch_flags, mnem) < 0) |
1068 | { | |
33eaf5de | 1069 | as_bad ("Unknown instruction mnemonic `%s'", mnem); |
b6605ddd EB |
1070 | return; |
1071 | } | |
1072 | ||
1073 | if ((VISIUM_OPCODE_ARCH_MASK (visium_opcode_arch) & arch_flags) == 0) | |
1074 | { | |
1075 | as_bad ("Architecture mismatch on `%s'", mnem); | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | this_mode = amode; | |
1080 | ||
1081 | switch (amode) | |
1082 | { | |
1083 | case mode_d: | |
1084 | /* register := | |
1085 | Example: | |
1086 | readmda r1 */ | |
1087 | ans = parse_gen_reg (&str, &r1); | |
1088 | if (ans < 0) | |
1089 | { | |
1090 | as_bad ("Dest register required"); | |
1091 | return; | |
1092 | } | |
1093 | opcode |= (r1 << 10); | |
1094 | this_dest = r1; | |
1095 | break; | |
1096 | ||
1097 | case mode_a: | |
1098 | /* op= register | |
1099 | Example: asld r1 */ | |
1100 | ans = parse_gen_reg (&str, &r1); | |
1101 | if (ans < 0) | |
1102 | { | |
1103 | as_bad ("SourceA register required"); | |
1104 | return; | |
1105 | } | |
1106 | opcode |= (r1 << 16); | |
1107 | break; | |
1108 | ||
1109 | case mode_ab: | |
1110 | /* register * register | |
1111 | Example: | |
1112 | mults r1,r2 */ | |
1113 | ans = parse_gen_reg (&str, &r1); | |
1114 | if (ans < 0) | |
1115 | { | |
1116 | as_bad ("SourceA register required"); | |
1117 | return; | |
1118 | } | |
1119 | str = skip_space (str); | |
1120 | if (*str == ',') | |
1121 | { | |
1122 | str++; | |
1123 | ans = parse_gen_reg (&str, &r2); | |
1124 | if (ans < 0) | |
1125 | { | |
1126 | as_bad ("SourceB register required"); | |
1127 | return; | |
1128 | } | |
1129 | opcode |= (r1 << 16) | (r2 << 4); | |
1130 | } | |
1131 | else | |
1132 | { | |
1133 | as_bad ("SourceB register required"); | |
1134 | return; | |
1135 | } | |
1136 | break; | |
1137 | ||
1138 | case mode_da: | |
1139 | /* register := register | |
1140 | Example: | |
1141 | extb.l r1,r2 */ | |
1142 | ans = parse_gen_reg (&str, &r1); | |
1143 | if (ans < 0) | |
1144 | { | |
1145 | as_bad ("Dest register required"); | |
1146 | return; | |
1147 | } | |
1148 | str = skip_space (str); | |
1149 | if (*str == ',') | |
1150 | { | |
1151 | str++; | |
1152 | ans = parse_gen_reg (&str, &r2); | |
1153 | if (ans < 0) | |
1154 | { | |
1155 | as_bad ("SourceA register required"); | |
1156 | return; | |
1157 | } | |
1158 | opcode |= (r1 << 10) | (r2 << 16); | |
1159 | } | |
1160 | else | |
1161 | { | |
1162 | as_bad ("SourceB register required"); | |
1163 | return; | |
1164 | } | |
1165 | this_dest = r1; | |
1166 | break; | |
1167 | ||
1168 | case mode_dab: | |
1169 | /* register := register * register | |
1170 | Example: | |
1171 | add.l r1,r2,r3 */ | |
1172 | ans = parse_gen_reg (&str, &r1); | |
1173 | if (ans < 0) | |
1174 | { | |
1175 | as_bad ("Dest register required"); | |
1176 | return; | |
1177 | } | |
1178 | str = skip_space (str); | |
1179 | if (*str == ',') | |
1180 | { | |
1181 | str++; | |
1182 | ans = parse_gen_reg (&str, &r2); | |
1183 | if (ans < 0) | |
1184 | { | |
1185 | as_bad ("SourceA register required"); | |
1186 | return; | |
1187 | } | |
1188 | str = skip_space (str); | |
1189 | if (*str == ',') | |
1190 | { | |
1191 | str++; | |
1192 | ans = parse_gen_reg (&str, &r3); | |
1193 | if (ans < 0) | |
1194 | { | |
1195 | as_bad ("SourceB register required"); | |
1196 | return; | |
1197 | } | |
1198 | ||
1199 | /* Got three regs, assemble instruction. */ | |
1200 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
1201 | } | |
1202 | else | |
1203 | { | |
1204 | as_bad ("SourceA register required"); | |
1205 | return; | |
1206 | } | |
1207 | } | |
1208 | else | |
1209 | { | |
1210 | as_bad ("Dest register required"); | |
1211 | return; | |
1212 | } | |
1213 | this_dest = r1; | |
1214 | break; | |
1215 | ||
1216 | case mode_iab: | |
1217 | /* 5-bit immediate * register * register | |
1218 | Example: | |
1219 | eamwrite 3,r1,r2 */ | |
1220 | str = parse_exp (str, &e1); | |
1221 | str = skip_space (str); | |
1222 | if (e1.X_op != O_absent && *str == ',') | |
1223 | { | |
1224 | int eam_op = e1.X_add_number; | |
1225 | ||
1226 | str = skip_space (str + 1); | |
1227 | ans = parse_gen_reg (&str, &r2); | |
1228 | if (ans < 0) | |
1229 | { | |
1230 | as_bad ("SourceA register required"); | |
1231 | return; | |
1232 | } | |
1233 | str = skip_space (str); | |
1234 | if (*str == ',') | |
1235 | { | |
1236 | str++; | |
1237 | ans = parse_gen_reg (&str, &r3); | |
1238 | if (ans < 0) | |
1239 | { | |
1240 | as_bad ("SourceB register required"); | |
1241 | return; | |
1242 | } | |
1243 | ||
1244 | /* Got three operands, assemble instruction. */ | |
1245 | if (eam_op < 0 || eam_op > 31) | |
1246 | { | |
1247 | as_bad ("eam_op out of range"); | |
1248 | } | |
1249 | opcode |= ((eam_op & 0x1f) << 10) | (r2 << 16) | (r3 << 4); | |
1250 | } | |
1251 | } | |
1252 | else | |
1253 | { | |
1254 | as_bad ("EAM_OP required"); | |
1255 | return; | |
1256 | } | |
1257 | break; | |
1258 | ||
1259 | case mode_0ab: | |
1260 | /* zero * register * register | |
1261 | Example: | |
1262 | cmp.l r1,r2 */ | |
1263 | ans = parse_gen_reg (&str, &r1); | |
1264 | if (ans < 0) | |
1265 | { | |
1266 | as_bad ("SourceA register required"); | |
1267 | return; | |
1268 | } | |
1269 | str = skip_space (str); | |
1270 | if (*str == ',') | |
1271 | { | |
1272 | str++; | |
1273 | ans = parse_gen_reg (&str, &r2); | |
1274 | if (ans < 0) | |
1275 | { | |
1276 | as_bad ("SourceB register required"); | |
1277 | return; | |
1278 | } | |
1279 | opcode |= (r1 << 16) | (r2 << 4); | |
1280 | } | |
1281 | else | |
1282 | { | |
1283 | as_bad ("SourceB register required"); | |
1284 | return; | |
1285 | } | |
1286 | break; | |
1287 | ||
1288 | case mode_da0: | |
1289 | /* register * register * zero | |
1290 | Example: | |
1291 | move.l r1,r2 */ | |
1292 | ans = parse_gen_reg (&str, &r1); | |
1293 | if (ans < 0) | |
1294 | { | |
1295 | as_bad ("Dest register required"); | |
1296 | return; | |
1297 | } | |
1298 | str = skip_space (str); | |
1299 | if (*str == ',') | |
1300 | { | |
1301 | str++; | |
1302 | ans = parse_gen_reg (&str, &r2); | |
1303 | if (ans < 0) | |
1304 | { | |
1305 | as_bad ("SourceA register required"); | |
1306 | return; | |
1307 | } | |
1308 | opcode |= (r1 << 10) | (r2 << 16); | |
1309 | } | |
1310 | else | |
1311 | { | |
1312 | as_bad ("SourceA register required"); | |
1313 | return; | |
1314 | } | |
1315 | this_dest = r1; | |
1316 | break; | |
1317 | ||
1318 | case mode_cad: | |
1319 | /* condition * register * register | |
1320 | Example: | |
1321 | bra tr,r1,r2 */ | |
1322 | ans = parse_cc (&str, &cc); | |
1323 | if (ans < 0) | |
1324 | { | |
1325 | as_bad ("condition code required"); | |
1326 | return; | |
1327 | } | |
1328 | ||
1329 | str = skip_space (str); | |
1330 | if (*str == ',') | |
1331 | { | |
1332 | str = skip_space (str + 1); | |
1333 | ans = parse_gen_reg (&str, &r2); | |
1334 | if (ans < 0) | |
1335 | { | |
1336 | as_bad ("SourceA register required"); | |
1337 | return; | |
1338 | } | |
1339 | str = skip_space (str); | |
1340 | if (*str == ',') | |
1341 | { | |
1342 | str++; | |
1343 | ans = parse_gen_reg (&str, &r3); | |
1344 | if (ans < 0) | |
1345 | { | |
1346 | as_bad ("Dest register required"); | |
1347 | return; | |
1348 | } | |
1349 | ||
1350 | /* Got three operands, assemble instruction. */ | |
1351 | opcode |= (cc << 27) | (r2 << 16) | (r3 << 10); | |
1352 | } | |
1353 | else | |
1354 | { | |
1355 | as_bad ("Dest register required"); | |
1356 | return; | |
1357 | } | |
1358 | } | |
1359 | else | |
1360 | { | |
1361 | as_bad ("SourceA register required"); | |
1362 | return; | |
1363 | } | |
1364 | ||
1365 | if (previous_mode == mode_cad || previous_mode == mode_ci) | |
1366 | as_bad ("branch instruction in delay slot"); | |
1367 | ||
0e7e9601 EB |
1368 | /* For the GR6, BRA insns must be aligned on 64-bit boundaries. */ |
1369 | if (visium_arch == VISIUM_ARCH_GR6) | |
1370 | do_align (3, NULL, 0, 0); | |
1371 | ||
b6605ddd EB |
1372 | this_dest = r3; |
1373 | condition_code = cc; | |
1374 | break; | |
1375 | ||
1376 | case mode_das: | |
33eaf5de | 1377 | /* register := register * 5-bit immediate/register shift count |
b6605ddd EB |
1378 | Example: |
1379 | asl.l r1,r2,4 */ | |
1380 | ans = parse_gen_reg (&str, &r1); | |
1381 | if (ans < 0) | |
1382 | { | |
1383 | as_bad ("Dest register required"); | |
1384 | return; | |
1385 | } | |
1386 | str = skip_space (str); | |
1387 | if (*str == ',') | |
1388 | { | |
1389 | str++; | |
1390 | ans = parse_gen_reg (&str, &r2); | |
1391 | if (ans < 0) | |
1392 | { | |
1393 | as_bad ("SourceA register required"); | |
1394 | return; | |
1395 | } | |
1396 | str = skip_space (str); | |
1397 | if (*str == ',') | |
1398 | { | |
1399 | str++; | |
1400 | ans = parse_gen_reg (&str, &r3); | |
1401 | if (ans == 0) | |
1402 | { | |
1403 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
1404 | } | |
1405 | else | |
1406 | { | |
1407 | str = parse_exp (str, &e1); | |
1408 | if (e1.X_op == O_constant) | |
1409 | { | |
1410 | int imm = e1.X_add_number; | |
1411 | ||
1412 | if (imm < 0 || imm > 31) | |
1413 | as_bad ("immediate value out of range"); | |
1414 | ||
1415 | opcode |= | |
1416 | (r1 << 10) | (r2 << 16) | (1 << 9) | ((imm & 0x1f) << | |
1417 | 4); | |
1418 | } | |
1419 | else | |
1420 | { | |
1421 | as_bad ("immediate operand required"); | |
1422 | return; | |
1423 | } | |
1424 | } | |
1425 | } | |
1426 | } | |
1427 | else | |
1428 | { | |
1429 | as_bad ("SourceA register required"); | |
1430 | return; | |
1431 | } | |
1432 | this_dest = r1; | |
1433 | break; | |
1434 | ||
1435 | case mode_di: | |
1436 | /* register := 5-bit immediate | |
1437 | Example: | |
1438 | eamread r1,3 */ | |
1439 | ans = parse_gen_reg (&str, &r1); | |
1440 | if (ans < 0) | |
1441 | { | |
1442 | as_bad ("Dest register required"); | |
1443 | return; | |
1444 | } | |
1445 | str = skip_space (str); | |
1446 | if (*str == ',') | |
1447 | { | |
1448 | str++; | |
1449 | str = parse_exp (str, &e1); | |
1450 | if (e1.X_op == O_constant) | |
1451 | { | |
1452 | int opnd2 = e1.X_add_number; | |
1453 | ||
1454 | if (opnd2 < 0 || opnd2 > 31) | |
1455 | { | |
1456 | as_bad ("immediate operand out of range"); | |
1457 | return; | |
1458 | } | |
1459 | opcode |= (r1 << 10) | ((opnd2 & 0x1f) << 4); | |
1460 | } | |
1461 | else | |
1462 | { | |
1463 | as_bad ("immediate operand required"); | |
1464 | return; | |
1465 | } | |
1466 | } | |
1467 | else | |
1468 | { | |
1469 | as_bad ("immediate operand required"); | |
1470 | return; | |
1471 | } | |
1472 | this_dest = r1; | |
1473 | break; | |
1474 | ||
1475 | case mode_ir: | |
1476 | /* 5-bit immediate * register, e.g. trace 1,r1 */ | |
1477 | str = parse_exp (str, &e1); | |
1478 | str = skip_space (str); | |
1479 | if (e1.X_op == O_constant && *str == ',') | |
1480 | { | |
1481 | int opnd1 = e1.X_add_number; | |
1482 | ||
1483 | str = skip_space (str + 1); | |
1484 | ans = parse_gen_reg (&str, &r2); | |
1485 | if (ans < 0) | |
1486 | { | |
1487 | as_bad ("SourceA register required"); | |
1488 | return; | |
1489 | } | |
1490 | ||
1491 | /* Got two operands, assemble instruction. */ | |
1492 | if (opnd1 < 0 || opnd1 > 31) | |
1493 | { | |
1494 | as_bad ("1st operand out of range"); | |
1495 | } | |
1496 | opcode |= ((opnd1 & 0x1f) << 10) | (r2 << 16); | |
1497 | } | |
1498 | else | |
1499 | { | |
1500 | as_bad ("Immediate operand required"); | |
1501 | return; | |
1502 | } | |
1503 | break; | |
1504 | ||
1505 | case mode_ai: | |
1506 | /* register *= 16-bit unsigned immediate | |
1507 | Example: | |
1508 | addi r1,123 */ | |
1509 | ans = parse_gen_reg (&str, &r1); | |
1510 | if (ans < 0) | |
1511 | { | |
1512 | as_bad ("Dest register required"); | |
1513 | return; | |
1514 | } | |
1515 | opcode |= (r1 << 16); | |
1516 | ||
1517 | str = skip_space (str); | |
1518 | if (*str != ',') | |
1519 | { | |
1520 | as_bad ("immediate value missing"); | |
1521 | return; | |
1522 | } | |
1523 | this_dest = r1; | |
1a0670f3 | 1524 | /* Fall through. */ |
b6605ddd EB |
1525 | |
1526 | case mode_i: | |
1527 | /* MOVIL/WRTL traditionally get an implicit "%l" applied | |
1528 | to their immediate value. For other opcodes, unless | |
1529 | the immediate value is decorated with "%u" or "%l" | |
1530 | it must be in the range 0 .. 65535. */ | |
1531 | if ((opcode & 0x7fe00000) == 0x04800000 | |
1532 | || (opcode & 0x7fe00000) == 0x05000000) | |
1533 | reloc = BFD_RELOC_VISIUM_LO16; | |
1534 | else | |
1535 | reloc = BFD_RELOC_VISIUM_IM16; | |
1536 | ||
1537 | str = skip_space (str + 1); | |
1538 | ||
1539 | if (*str == '%') | |
1540 | { | |
1541 | if (str[1] == 'u') | |
1542 | reloc = BFD_RELOC_VISIUM_HI16; | |
1543 | else if (str[1] == 'l') | |
1544 | reloc = BFD_RELOC_VISIUM_LO16; | |
1545 | else | |
1546 | { | |
1547 | as_bad ("bad char after %%"); | |
1548 | return; | |
1549 | } | |
1550 | ||
1551 | str += 2; | |
1552 | } | |
1553 | str = parse_exp (str, &e1); | |
1554 | if (e1.X_op != O_absent) | |
1555 | { | |
1556 | if (e1.X_op == O_constant) | |
1557 | { | |
1558 | int imm = e1.X_add_number; | |
1559 | ||
1560 | if (reloc == BFD_RELOC_VISIUM_HI16) | |
1561 | opcode |= ((imm >> 16) & 0xffff); | |
1562 | else if (reloc == BFD_RELOC_VISIUM_LO16) | |
1563 | opcode |= (imm & 0xffff); | |
1564 | else | |
1565 | { | |
1566 | if (imm < 0 || imm > 0xffff) | |
1567 | as_bad ("immediate value out of range"); | |
1568 | ||
1569 | opcode |= (imm & 0xffff); | |
1570 | } | |
1571 | /* No relocation is needed. */ | |
1572 | reloc = 0; | |
1573 | } | |
1574 | } | |
1575 | else | |
1576 | { | |
1577 | as_bad ("immediate value missing"); | |
1578 | return; | |
1579 | } | |
1580 | break; | |
1581 | ||
1582 | case mode_bax: | |
1583 | /* register * register * 5-bit immediate, | |
1584 | SourceB * SourceA * Index | |
1585 | Examples | |
1586 | write.l (r1),r2 | |
1587 | write.l 3(r1),r2 */ | |
1588 | str = skip_space (str); | |
1589 | ||
1590 | indx = 0; | |
1591 | if (*str != '(') | |
1592 | { | |
1593 | str = parse_exp (str, &e1); | |
1594 | if (e1.X_op == O_constant) | |
1595 | { | |
1596 | indx = e1.X_add_number; | |
1597 | ||
1598 | if (indx < 0 || indx > 31) | |
1599 | { | |
1600 | as_bad ("Index out of range"); | |
1601 | return; | |
1602 | } | |
1603 | } | |
1604 | else | |
1605 | { | |
1606 | as_bad ("Index(SourceA) required"); | |
1607 | return; | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | str = skip_space (str); | |
1612 | ||
1613 | if (*str != '(') | |
1614 | { | |
1615 | as_bad ("Index(SourceA) required"); | |
1616 | return; | |
1617 | } | |
1618 | ||
1619 | str = skip_space (str + 1); | |
1620 | ||
1621 | ans = parse_gen_reg (&str, &r1); | |
1622 | if (ans < 0) | |
1623 | { | |
1624 | as_bad ("SourceA register required"); | |
1625 | return; | |
1626 | } | |
1627 | str = skip_space (str); | |
1628 | if (*str != ')') | |
1629 | { | |
1630 | as_bad ("(SourceA) required"); | |
1631 | return; | |
1632 | } | |
1633 | str = skip_space (str + 1); | |
1634 | ||
1635 | if (*str == ',') | |
1636 | { | |
1637 | str = skip_space (str + 1); | |
1638 | ans = parse_gen_reg (&str, &r2); | |
1639 | if (ans < 0) | |
1640 | { | |
1641 | as_bad ("SourceB register required"); | |
1642 | return; | |
1643 | } | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | as_bad ("SourceB register required"); | |
1648 | return; | |
1649 | } | |
1650 | ||
1651 | opcode |= (r1 << 16) | (r2 << 4) | ((indx & 0x1f) << 10); | |
1652 | ||
1653 | if (indx != 0 && previous_mode == mode_cad) | |
1654 | { | |
1655 | /* We're in a delay slot. | |
1656 | If the base reg is the destination of the branch, then issue | |
1657 | an error message. | |
1658 | Otherwise it is safe to use the base and index. */ | |
1659 | if (previous_dest != 0 && r1 == previous_dest) | |
1660 | { | |
1661 | as_bad ("base register not ready"); | |
1662 | return; | |
1663 | } | |
1664 | } | |
1665 | else if (previous_dest != 0 | |
1666 | && r1 == previous_dest | |
1667 | && (visium_arch == VISIUM_ARCH_MCM | |
1668 | || visium_arch == VISIUM_ARCH_MCM24 | |
1669 | || (visium_arch == VISIUM_ARCH_DEF && indx != 0))) | |
1670 | { | |
1671 | as_warn ("base register not ready, NOP inserted."); | |
1672 | /* Insert a NOP before the write instruction. */ | |
1673 | output = frag_more (4); | |
1674 | memset (output, 0, 4); | |
1675 | } | |
1676 | break; | |
1677 | ||
1678 | case mode_dax: | |
1679 | /* register := register * 5-bit immediate | |
1680 | Examples: | |
1681 | read.b r1,(r2) | |
1682 | read.w r1,3(r2) */ | |
1683 | ans = parse_gen_reg (&str, &r1); | |
1684 | if (ans < 0) | |
1685 | { | |
1686 | as_bad ("Dest register required"); | |
1687 | return; | |
1688 | } | |
1689 | str = skip_space (str); | |
1690 | if (*str != ',') | |
1691 | { | |
1692 | as_bad ("SourceA required"); | |
1693 | return; | |
1694 | } | |
1695 | str = skip_space (str + 1); | |
1696 | ||
1697 | indx = 0; | |
1698 | if (*str != '(') | |
1699 | { | |
1700 | str = parse_exp (str, &e1); | |
1701 | if (e1.X_op == O_constant) | |
1702 | { | |
1703 | indx = e1.X_add_number; | |
1704 | ||
1705 | if (indx < 0 || indx > 31) | |
1706 | { | |
1707 | as_bad ("Index out of range"); | |
1708 | return; | |
1709 | } | |
1710 | } | |
1711 | else | |
1712 | { | |
1713 | as_bad ("Immediate 0 to 31 required"); | |
1714 | return; | |
1715 | } | |
1716 | } | |
1717 | if (*str != '(') | |
1718 | { | |
1719 | as_bad ("(SourceA) required"); | |
1720 | return; | |
1721 | } | |
1722 | str++; | |
1723 | ans = parse_gen_reg (&str, &r2); | |
1724 | if (ans < 0) | |
1725 | { | |
1726 | as_bad ("SourceA register required"); | |
1727 | return; | |
1728 | } | |
1729 | str = skip_space (str); | |
1730 | if (*str != ')') | |
1731 | { | |
1732 | as_bad ("(SourceA) required"); | |
1733 | return; | |
1734 | } | |
1735 | str++; | |
1736 | opcode |= (r1 << 10) | (r2 << 16) | ((indx & 0x1f) << 4); | |
1737 | this_dest = r1; | |
1738 | ||
1739 | if (indx != 0 && previous_mode == mode_cad) | |
1740 | { | |
1741 | /* We're in a delay slot. | |
1742 | If the base reg is the destination of the branch, then issue | |
1743 | an error message. | |
1744 | Otherwise it is safe to use the base and index. */ | |
1745 | if (previous_dest != 0 && r2 == previous_dest) | |
1746 | { | |
1747 | as_bad ("base register not ready"); | |
1748 | return; | |
1749 | } | |
1750 | } | |
1751 | else if (previous_dest != 0 | |
1752 | && r2 == previous_dest | |
1753 | && (visium_arch == VISIUM_ARCH_MCM | |
1754 | || visium_arch == VISIUM_ARCH_MCM24 | |
1755 | || (visium_arch == VISIUM_ARCH_DEF && indx != 0))) | |
1756 | { | |
1757 | as_warn ("base register not ready, NOP inserted."); | |
1758 | /* Insert a NOP before the read instruction. */ | |
1759 | output = frag_more (4); | |
1760 | memset (output, 0, 4); | |
1761 | } | |
1762 | break; | |
1763 | ||
1764 | case mode_s: | |
1765 | /* special mode | |
1766 | Example: | |
1767 | nop */ | |
1768 | str = skip_space (str); | |
1769 | break; | |
1770 | ||
1771 | case mode_ci: | |
1772 | /* condition * 16-bit signed word displacement | |
1773 | Example: | |
1774 | brr L1 */ | |
1775 | ans = parse_cc (&str, &cc); | |
1776 | if (ans < 0) | |
1777 | { | |
1778 | as_bad ("condition code required"); | |
1779 | return; | |
1780 | } | |
1781 | opcode |= (cc << 27); | |
1782 | ||
1783 | str = skip_space (str); | |
1784 | if (*str == ',') | |
1785 | { | |
1786 | str = skip_space (str + 1); | |
1787 | str = parse_exp (str, &e1); | |
1788 | if (e1.X_op != O_absent) | |
1789 | { | |
1790 | if (e1.X_op == O_constant) | |
1791 | { | |
1792 | int imm = e1.X_add_number; | |
1793 | ||
1794 | if (imm < -32768 || imm > 32767) | |
1795 | as_bad ("immediate value out of range"); | |
1796 | ||
1797 | /* The GR6 doesn't correctly handle a 0 displacement | |
1798 | so we insert a NOP and change it to -1. */ | |
1799 | if (imm == 0 && cc != 0 && visium_arch == VISIUM_ARCH_GR6) | |
1800 | { | |
1801 | output = frag_more (4); | |
1802 | memset (output, 0, 4); | |
1803 | imm = -1; | |
1804 | } | |
1805 | ||
1806 | opcode |= (imm & 0xffff); | |
1807 | } | |
1808 | else if (e1.X_op == O_symbol) | |
1809 | { | |
1810 | /* The GR6 doesn't correctly handle a 0 displacement | |
1811 | so the instruction requires relaxation. */ | |
1812 | if (cc != 0 && visium_arch == VISIUM_ARCH_GR6) | |
1813 | relax = amode; | |
1814 | else | |
1815 | reloc = BFD_RELOC_VISIUM_REL16; | |
1816 | } | |
1817 | else | |
1818 | { | |
1819 | as_bad ("immediate value missing"); | |
1820 | return; | |
1821 | } | |
1822 | } | |
1823 | else | |
1824 | { | |
1825 | as_bad ("immediate value missing"); | |
1826 | return; | |
1827 | } | |
1828 | } | |
1829 | else | |
1830 | { | |
1831 | as_bad ("immediate value missing"); | |
1832 | return; | |
1833 | } | |
1834 | ||
1835 | if (previous_mode == mode_cad || previous_mode == mode_ci) | |
1836 | as_bad ("branch instruction in delay slot"); | |
1837 | ||
1838 | condition_code = cc; | |
1839 | break; | |
1840 | ||
1841 | case mode_fdab: | |
1842 | /* float := float * float | |
1843 | Example | |
1844 | fadd f4,f3,f2 */ | |
1845 | ans = parse_fp_reg (&str, &r1); | |
1846 | if (ans < 0) | |
1847 | { | |
1848 | as_bad ("floating point destination register required"); | |
1849 | return; | |
1850 | } | |
1851 | str = skip_space (str); | |
1852 | if (*str == ',') | |
1853 | { | |
1854 | str++; | |
1855 | ans = parse_fp_reg (&str, &r2); | |
1856 | if (ans < 0) | |
1857 | { | |
1858 | as_bad ("floating point SourceA register required"); | |
1859 | return; | |
1860 | } | |
1861 | str = skip_space (str); | |
1862 | if (*str == ',') | |
1863 | { | |
1864 | str++; | |
1865 | ans = parse_fp_reg (&str, &r3); | |
1866 | if (ans < 0) | |
1867 | { | |
1868 | as_bad ("floating point SourceB register required"); | |
1869 | return; | |
1870 | } | |
1871 | ||
1872 | /* Got 3 floating regs, assemble instruction. */ | |
1873 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
1874 | } | |
1875 | else | |
1876 | { | |
1877 | as_bad ("floating point SourceB register required"); | |
1878 | return; | |
1879 | } | |
1880 | } | |
1881 | else | |
1882 | { | |
1883 | as_bad ("floating point SourceA register required"); | |
1884 | return; | |
1885 | } | |
1886 | break; | |
1887 | ||
1888 | case mode_ifdab: | |
1889 | /* 4-bit immediate * float * float * float | |
1890 | Example | |
1891 | fpinst 10,f1,f2,f3 */ | |
1892 | str = parse_exp (str, &e1); | |
1893 | str = skip_space (str); | |
1894 | if (e1.X_op != O_absent && *str == ',') | |
1895 | { | |
1896 | int finst = e1.X_add_number; | |
1897 | ||
1898 | str = skip_space (str + 1); | |
1899 | ans = parse_fp_reg (&str, &r1); | |
1900 | if (ans < 0) | |
1901 | { | |
1902 | as_bad ("floating point destination register required"); | |
1903 | return; | |
1904 | } | |
1905 | str = skip_space (str); | |
1906 | if (*str == ',') | |
1907 | { | |
1908 | str++; | |
1909 | ans = parse_fp_reg (&str, &r2); | |
1910 | if (ans < 0) | |
1911 | { | |
1912 | as_bad ("floating point SourceA register required"); | |
1913 | return; | |
1914 | } | |
1915 | str = skip_space (str); | |
1916 | if (*str == ',') | |
1917 | { | |
1918 | str++; | |
1919 | ans = parse_fp_reg (&str, &r3); | |
1920 | if (ans < 0) | |
1921 | { | |
1922 | as_bad ("floating point SourceB register required"); | |
1923 | return; | |
1924 | } | |
1925 | ||
1926 | /* Got immediate and 3 floating regs, | |
1927 | assemble instruction. */ | |
1928 | if (finst < 0 || finst > 15) | |
1929 | as_bad ("finst out of range"); | |
1930 | ||
1931 | opcode |= | |
1932 | ((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 << | |
1933 | 4); | |
1934 | } | |
1935 | else | |
1936 | { | |
1937 | as_bad ("floating point SourceB register required"); | |
1938 | return; | |
1939 | } | |
1940 | } | |
1941 | else | |
1942 | { | |
1943 | as_bad ("floating point SourceA register required"); | |
1944 | return; | |
1945 | } | |
1946 | } | |
1947 | else | |
1948 | { | |
1949 | as_bad ("finst missing"); | |
1950 | return; | |
1951 | } | |
1952 | break; | |
1953 | ||
1954 | case mode_idfab: | |
1955 | /* 4-bit immediate * register * float * float | |
1956 | Example | |
1957 | fpuread 4,r25,f2,f3 */ | |
1958 | str = parse_exp (str, &e1); | |
1959 | str = skip_space (str); | |
1960 | if (e1.X_op != O_absent && *str == ',') | |
1961 | { | |
1962 | int finst = e1.X_add_number; | |
1963 | ||
1964 | str = skip_space (str + 1); | |
1965 | ans = parse_gen_reg (&str, &r1); | |
1966 | if (ans < 0) | |
1967 | { | |
1968 | as_bad ("destination general register required"); | |
1969 | return; | |
1970 | } | |
1971 | str = skip_space (str); | |
1972 | if (*str == ',') | |
1973 | { | |
1974 | str++; | |
1975 | ans = parse_fp_reg (&str, &r2); | |
1976 | if (ans < 0) | |
1977 | { | |
1978 | as_bad ("floating point SourceA register required"); | |
1979 | return; | |
1980 | } | |
1981 | str = skip_space (str); | |
1982 | if (*str == ',') | |
1983 | { | |
1984 | str++; | |
1985 | ans = parse_fp_reg (&str, &r3); | |
1986 | if (ans < 0) | |
1987 | { | |
1988 | as_bad ("floating point SourceB register required"); | |
1989 | return; | |
1990 | } | |
1991 | ||
1992 | /* Got immediate and 3 floating regs, | |
1993 | assemble instruction. */ | |
1994 | if (finst < 0 || finst > 15) | |
1995 | as_bad ("finst out of range"); | |
1996 | ||
1997 | opcode |= | |
1998 | ((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 << | |
1999 | 4); | |
2000 | } | |
2001 | else | |
2002 | { | |
2003 | as_bad ("floating point SourceB register required"); | |
2004 | return; | |
2005 | } | |
2006 | } | |
2007 | else | |
2008 | { | |
2009 | as_bad ("floating point SourceA register required"); | |
2010 | return; | |
2011 | } | |
2012 | } | |
2013 | else | |
2014 | { | |
2015 | as_bad ("finst missing"); | |
2016 | return; | |
2017 | } | |
2018 | break; | |
2019 | ||
2020 | case mode_fda: | |
2021 | /* float := float | |
2022 | Example | |
2023 | fsqrt f4,f3 */ | |
2024 | ans = parse_fp_reg (&str, &r1); | |
2025 | if (ans < 0) | |
2026 | { | |
2027 | as_bad ("floating point destination register required"); | |
2028 | return; | |
2029 | } | |
2030 | str = skip_space (str); | |
2031 | if (*str == ',') | |
2032 | { | |
2033 | str++; | |
2034 | ans = parse_fp_reg (&str, &r2); | |
2035 | if (ans < 0) | |
2036 | { | |
2037 | as_bad ("floating point source register required"); | |
2038 | return; | |
2039 | } | |
2040 | ||
2041 | /* Got 2 floating regs, assemble instruction. */ | |
2042 | opcode |= (r1 << 10) | (r2 << 16); | |
2043 | } | |
2044 | else | |
2045 | { | |
2046 | as_bad ("floating point source register required"); | |
2047 | return; | |
2048 | } | |
2049 | break; | |
2050 | ||
2051 | case mode_fdra: | |
2052 | /* float := register | |
2053 | Example | |
2054 | fload f15,r6 */ | |
2055 | ans = parse_fp_reg (&str, &r1); | |
2056 | if (ans < 0) | |
2057 | { | |
2058 | as_bad ("floating point destination register required"); | |
2059 | return; | |
2060 | } | |
2061 | str = skip_space (str); | |
2062 | if (*str == ',') | |
2063 | { | |
2064 | str++; | |
2065 | ans = parse_gen_reg (&str, &r2); | |
2066 | if (ans < 0) | |
2067 | { | |
2068 | as_bad ("SourceA general register required"); | |
2069 | return; | |
2070 | } | |
2071 | ||
2072 | /* Got 2 regs, assemble instruction. */ | |
2073 | opcode |= (r1 << 10) | (r2 << 16); | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | as_bad ("SourceA general register required"); | |
2078 | return; | |
2079 | } | |
2080 | break; | |
2081 | ||
2082 | case mode_rdfab: | |
2083 | /* register := float * float | |
2084 | Example | |
2085 | fcmp r0,f4,f8 | |
2086 | For the GR6, register must be r0 and can be omitted. */ | |
2087 | ans = parse_gen_reg (&str, &r1); | |
2088 | if (ans < 0) | |
2089 | { | |
2090 | if (visium_opcode_arch == VISIUM_OPCODE_ARCH_GR5) | |
2091 | { | |
2092 | as_bad ("Dest general register required"); | |
2093 | return; | |
2094 | } | |
2095 | r1 = 0; | |
2096 | } | |
2097 | else | |
2098 | { | |
2099 | if (r1 != 0 && visium_opcode_arch != VISIUM_OPCODE_ARCH_GR5) | |
2100 | { | |
2101 | as_bad ("FCMP/FCMPE can only use r0 as Dest register"); | |
2102 | return; | |
2103 | } | |
2104 | ||
2105 | str = skip_space (str); | |
2106 | if (*str == ',') | |
2107 | str++; | |
2108 | else | |
2109 | { | |
2110 | as_bad ("floating point SourceA register required"); | |
2111 | return; | |
2112 | } | |
2113 | } | |
2114 | ||
2115 | ans = parse_fp_reg (&str, &r2); | |
2116 | if (ans < 0) | |
2117 | { | |
2118 | as_bad ("floating point SourceA register required"); | |
2119 | return; | |
2120 | } | |
2121 | str = skip_space (str); | |
2122 | if (*str == ',') | |
2123 | { | |
2124 | str++; | |
2125 | ans = parse_fp_reg (&str, &r3); | |
2126 | if (ans < 0) | |
2127 | { | |
2128 | as_bad ("floating point SourceB register required"); | |
2129 | return; | |
2130 | } | |
2131 | ||
2132 | /* Got 3 regs, assemble instruction. */ | |
2133 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
2134 | } | |
2135 | ||
2136 | this_dest = r1; | |
2137 | break; | |
2138 | ||
2139 | case mode_rdfa: | |
2140 | /* register := float | |
2141 | Example | |
2142 | fstore r5,f12 */ | |
2143 | ans = parse_gen_reg (&str, &r1); | |
2144 | if (ans < 0) | |
2145 | { | |
2146 | as_bad ("Dest general register required"); | |
2147 | return; | |
2148 | } | |
2149 | str = skip_space (str); | |
2150 | if (*str == ',') | |
2151 | { | |
2152 | str++; | |
2153 | ans = parse_fp_reg (&str, &r2); | |
2154 | if (ans < 0) | |
2155 | { | |
2156 | as_bad ("floating point source register required"); | |
2157 | return; | |
2158 | } | |
2159 | ||
2160 | /* Got 2 regs, assemble instruction. */ | |
2161 | opcode |= (r1 << 10) | (r2 << 16); | |
2162 | } | |
2163 | else | |
2164 | { | |
2165 | as_bad ("floating point source register required"); | |
2166 | return; | |
2167 | } | |
2168 | ||
2169 | this_dest = r1; | |
2170 | break; | |
2171 | ||
2172 | case mode_rrr: | |
2173 | /* register register register, all sources and destinations | |
2174 | Example: | |
2175 | bmd r1,r2,r3 */ | |
2176 | ||
2177 | ans = parse_gen_reg (&str, &r1); | |
2178 | if (ans < 0) | |
2179 | { | |
2180 | as_bad ("destination address register required"); | |
2181 | return; | |
2182 | } | |
2183 | str = skip_space (str); | |
2184 | if (*str == ',') | |
2185 | { | |
2186 | str++; | |
2187 | ans = parse_gen_reg (&str, &r2); | |
2188 | if (ans < 0) | |
2189 | { | |
2190 | as_bad ("source address register required"); | |
2191 | return; | |
2192 | } | |
2193 | str = skip_space (str); | |
2194 | if (*str == ',') | |
2195 | { | |
2196 | str++; | |
2197 | ans = parse_gen_reg (&str, &r3); | |
2198 | if (ans < 0) | |
2199 | { | |
2200 | as_bad ("count register required"); | |
2201 | return; | |
2202 | } | |
2203 | ||
2204 | /* We insist on three registers but the opcode can only use | |
2205 | r1,r2,r3. */ | |
2206 | if (r1 != 1 || r2 != 2 || r3 != 3) | |
2207 | { | |
2208 | as_bad ("BMI/BMD can only use format op r1,r2,r3"); | |
2209 | return; | |
2210 | } | |
2211 | ||
2212 | /* Opcode is unmodified by what comes out of the table. */ | |
2213 | } | |
2214 | else | |
2215 | { | |
2216 | as_bad ("register required"); | |
2217 | return; | |
2218 | } | |
2219 | } | |
2220 | else | |
2221 | { | |
2222 | as_bad ("register required"); | |
2223 | return; | |
2224 | } | |
2225 | ||
2226 | this_dest = r1; | |
2227 | break; | |
2228 | ||
2229 | default: | |
2230 | break; | |
2231 | } | |
2232 | ||
2233 | if (relax) | |
2234 | output = frag_var (rs_machine_dependent, 8, 4, relax, e1.X_add_symbol, | |
2235 | e1.X_add_number, NULL); | |
2236 | else | |
2237 | output = frag_more (4); | |
2238 | ||
2239 | /* Build the 32-bit instruction in a host-endian-neutral fashion. */ | |
2240 | output[0] = (opcode >> 24) & 0xff; | |
2241 | output[1] = (opcode >> 16) & 0xff; | |
2242 | output[2] = (opcode >> 8) & 0xff; | |
2243 | output[3] = (opcode >> 0) & 0xff; | |
2244 | ||
2245 | if (relax) | |
2246 | /* The size of the instruction is unknown, so tie the debug info to the | |
2247 | start of the instruction. */ | |
2248 | dwarf2_emit_insn (0); | |
2249 | else | |
2250 | { | |
2251 | if (reloc) | |
2252 | fix_new_exp (frag_now, output - frag_now->fr_literal, 4, &e1, | |
2253 | reloc == BFD_RELOC_VISIUM_REL16, reloc); | |
2254 | else | |
2255 | visium_update_parity_bit (output); | |
2256 | ||
2257 | dwarf2_emit_insn (4); | |
2258 | } | |
2259 | ||
2260 | if (*str != '\0') | |
2261 | as_bad ("junk after instruction"); | |
2262 | } | |
2263 | ||
2264 | void | |
2265 | visium_cfi_frame_initial_instructions (void) | |
2266 | { | |
2267 | /* The CFA is in SP on function entry. */ | |
2268 | cfi_add_CFA_def_cfa (23, 0); | |
2269 | } | |
2270 | ||
2271 | int | |
2272 | visium_regname_to_dw2regnum (char *regname) | |
2273 | { | |
2274 | if (!regname[0]) | |
2275 | return -1; | |
2276 | ||
2277 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
2278 | return 22; | |
2279 | ||
2280 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
2281 | return 23; | |
2282 | ||
2283 | if (regname[0] == 'm' && regname[1] == 'd' && !regname[3]) | |
2284 | switch (regname[2]) | |
2285 | { | |
2286 | case 'b': return 32; | |
2287 | case 'a': return 33; | |
2288 | case 'c': return 34; | |
2289 | default : return -1; | |
2290 | } | |
2291 | ||
2292 | if (regname[0] == 'f' || regname[0] == 'r') | |
2293 | { | |
2294 | char *p; | |
2295 | unsigned int regnum = strtoul (regname + 1, &p, 10); | |
2296 | if (*p) | |
2297 | return -1; | |
2298 | if (regnum >= (regname[0] == 'f' ? 16 : 32)) | |
2299 | return -1; | |
2300 | if (regname[0] == 'f') | |
2301 | regnum += 35; | |
2302 | return regnum; | |
2303 | } | |
2304 | ||
2305 | return -1; | |
2306 | } |