Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
fb227da0 | 2 | Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
77cba8a3 | 82 | unsigned xtensa_num_pipe_stages; |
d77b99c9 | 83 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
84 | |
85 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
86 | ||
87 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 88 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
89 | back end. */ |
90 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
91 | |
92 | /* Flags for properties of the last instruction in a segment. */ | |
93 | #define FLAG_IS_A0_WRITER 0x1 | |
94 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
95 | ||
96 | ||
97 | /* We define a special segment names ".literal" to place literals | |
98 | into. The .fini and .init sections are special because they | |
99 | contain code that is moved together by the linker. We give them | |
100 | their own special .fini.literal and .init.literal sections. */ | |
101 | ||
102 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 103 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 104 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 105 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
106 | |
107 | ||
43cd72b9 | 108 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
109 | state of the literal collection pools. If lit_prefix is set, it is |
110 | used to determine the literal section names; otherwise, the literal | |
111 | sections are determined based on the current text section. The | |
112 | lit_seg and lit4_seg fields cache these literal sections, with the | |
113 | current_text_seg field used a tag to indicate whether the cached | |
114 | values are valid. */ | |
e0001a05 NC |
115 | |
116 | typedef struct lit_state_struct | |
117 | { | |
74869ac7 BW |
118 | char *lit_prefix; |
119 | segT current_text_seg; | |
e0001a05 | 120 | segT lit_seg; |
43cd72b9 | 121 | segT lit4_seg; |
e0001a05 NC |
122 | } lit_state; |
123 | ||
124 | static lit_state default_lit_sections; | |
125 | ||
126 | ||
74869ac7 BW |
127 | /* We keep a list of literal segments. The seg_list type is the node |
128 | for this list. The literal_head pointer is the head of the list, | |
129 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
130 | |
131 | typedef struct seg_list_struct | |
132 | { | |
133 | struct seg_list_struct *next; | |
134 | segT seg; | |
135 | } seg_list; | |
136 | ||
137 | static seg_list literal_head_h; | |
138 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
139 | |
140 | ||
82e7541d BW |
141 | /* Lists of symbols. We keep a list of symbols that label the current |
142 | instruction, so that we can adjust the symbols when inserting alignment | |
143 | for various instructions. We also keep a list of all the symbols on | |
144 | literals, so that we can fix up those symbols when the literals are | |
145 | later moved into the text sections. */ | |
146 | ||
147 | typedef struct sym_list_struct | |
148 | { | |
149 | struct sym_list_struct *next; | |
150 | symbolS *sym; | |
151 | } sym_list; | |
152 | ||
153 | static sym_list *insn_labels = NULL; | |
154 | static sym_list *free_insn_labels = NULL; | |
155 | static sym_list *saved_insn_labels = NULL; | |
156 | ||
157 | static sym_list *literal_syms; | |
158 | ||
159 | ||
43cd72b9 BW |
160 | /* Flags to determine whether to prefer const16 or l32r |
161 | if both options are available. */ | |
162 | int prefer_const16 = 0; | |
163 | int prefer_l32r = 0; | |
164 | ||
e0001a05 NC |
165 | /* Global flag to indicate when we are emitting literals. */ |
166 | int generating_literals = 0; | |
167 | ||
43cd72b9 BW |
168 | /* The following PROPERTY table definitions are copied from |
169 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
170 | ||
171 | /* Flags in the property tables to specify whether blocks of memory | |
172 | are literals, instructions, data, or unreachable. For | |
173 | instructions, blocks that begin loop targets and branch targets are | |
174 | designated. Blocks that do not allow density, instruction | |
175 | reordering or transformation are also specified. Finally, for | |
176 | branch targets, branch target alignment priority is included. | |
177 | Alignment of the next block is specified in the current block | |
178 | and the size of the current block does not include any fill required | |
179 | to align to the next block. */ | |
180 | ||
181 | #define XTENSA_PROP_LITERAL 0x00000001 | |
182 | #define XTENSA_PROP_INSN 0x00000002 | |
183 | #define XTENSA_PROP_DATA 0x00000004 | |
184 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
185 | /* Instruction only properties at beginning of code. */ | |
186 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
187 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
188 | /* Instruction only properties about code. */ | |
189 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
190 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
191 | /* Historically, NO_TRANSFORM was a property of instructions, |
192 | but it should apply to literals under certain circumstances. */ | |
193 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
194 | |
195 | /* Branch target alignment information. This transmits information | |
196 | to the linker optimization about the priority of aligning a | |
197 | particular block for branch target alignment: None, low priority, | |
198 | high priority, or required. These only need to be checked in | |
199 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
200 | Common usage is | |
201 | ||
202 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
203 | case XTENSA_PROP_BT_ALIGN_NONE: | |
204 | case XTENSA_PROP_BT_ALIGN_LOW: | |
205 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
206 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
207 | */ | |
208 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
209 | ||
210 | /* No branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
212 | /* Low priority branch target alignment. */ | |
213 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
214 | /* High priority branch target alignment. */ | |
215 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
216 | /* Required branch target alignment. */ | |
217 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
218 | ||
219 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
220 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
221 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
222 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
223 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
224 | ||
225 | ||
226 | /* Alignment is specified in the block BEFORE the one that needs | |
227 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
228 | get the required alignment specified as a power of 2. Use | |
229 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
230 | alignment. Be careful of side effects since the SET will evaluate | |
231 | flags twice. Also, note that the SIZE of a block in the property | |
232 | table does not include the alignment size, so the alignment fill | |
233 | must be calculated to determine if two blocks are contiguous. | |
234 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
235 | possible future implementation. */ | |
236 | ||
237 | #define XTENSA_PROP_ALIGN 0x00000800 | |
238 | ||
239 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
240 | ||
241 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
242 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
243 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
244 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
245 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
246 | ||
247 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
248 | ||
249 | ||
250 | /* Structure for saving instruction and alignment per-fragment data | |
251 | that will be written to the object file. This structure is | |
252 | equivalent to the actual data that will be written out to the file | |
253 | but is easier to use. We provide a conversion to file flags | |
254 | in frag_flags_to_number. */ | |
255 | ||
256 | typedef struct frag_flags_struct frag_flags; | |
257 | ||
258 | struct frag_flags_struct | |
259 | { | |
260 | /* is_literal should only be used after xtensa_move_literals. | |
261 | If you need to check if you are generating a literal fragment, | |
262 | then use the generating_literals global. */ | |
263 | ||
264 | unsigned is_literal : 1; | |
265 | unsigned is_insn : 1; | |
266 | unsigned is_data : 1; | |
267 | unsigned is_unreachable : 1; | |
268 | ||
99ded152 BW |
269 | /* is_specific_opcode implies no_transform. */ |
270 | unsigned is_no_transform : 1; | |
271 | ||
43cd72b9 BW |
272 | struct |
273 | { | |
274 | unsigned is_loop_target : 1; | |
275 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
276 | unsigned bt_align_priority : 2; | |
277 | ||
278 | unsigned is_no_density : 1; | |
279 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
280 | |
281 | unsigned is_no_reorder : 1; | |
282 | ||
283 | /* Uses absolute literal addressing for l32r. */ | |
284 | unsigned is_abslit : 1; | |
285 | } insn; | |
286 | unsigned is_align : 1; | |
287 | unsigned alignment : 5; | |
288 | }; | |
289 | ||
290 | ||
291 | /* Structure for saving information about a block of property data | |
292 | for frags that have the same flags. */ | |
293 | struct xtensa_block_info_struct | |
294 | { | |
295 | segT sec; | |
296 | bfd_vma offset; | |
297 | size_t size; | |
298 | frag_flags flags; | |
299 | struct xtensa_block_info_struct *next; | |
300 | }; | |
301 | ||
e0001a05 NC |
302 | |
303 | /* Structure for saving the current state before emitting literals. */ | |
304 | typedef struct emit_state_struct | |
305 | { | |
306 | const char *name; | |
307 | segT now_seg; | |
308 | subsegT now_subseg; | |
309 | int generating_literals; | |
310 | } emit_state; | |
311 | ||
312 | ||
43cd72b9 BW |
313 | /* Opcode placement information */ |
314 | ||
315 | typedef unsigned long long bitfield; | |
316 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
317 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
318 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
319 | ||
320 | #define MAX_FORMATS 32 | |
321 | ||
322 | typedef struct op_placement_info_struct | |
323 | { | |
324 | int num_formats; | |
325 | /* A number describing how restrictive the issue is for this | |
326 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 327 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 328 | only one format but many slots in that format. The most |
c138bc38 | 329 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
330 | format. */ |
331 | int issuef; | |
43cd72b9 | 332 | xtensa_format narrowest; |
43cd72b9 | 333 | char narrowest_size; |
b2d179be | 334 | char narrowest_slot; |
43cd72b9 BW |
335 | |
336 | /* formats is a bitfield with the Nth bit set | |
337 | if the opcode fits in the Nth xtensa_format. */ | |
338 | bitfield formats; | |
339 | ||
340 | /* slots[N]'s Mth bit is set if the op fits in the | |
341 | Mth slot of the Nth xtensa_format. */ | |
342 | bitfield slots[MAX_FORMATS]; | |
343 | ||
344 | /* A count of the number of slots in a given format | |
345 | an op can fit (i.e., the bitcount of the slot field above). */ | |
346 | char slots_in_format[MAX_FORMATS]; | |
347 | ||
348 | } op_placement_info, *op_placement_info_table; | |
349 | ||
350 | op_placement_info_table op_placement_table; | |
351 | ||
352 | ||
353 | /* Extra expression types. */ | |
354 | ||
355 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
356 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
357 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 358 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
359 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
360 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
361 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
362 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
363 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 364 | |
bbdd25a8 BW |
365 | struct suffix_reloc_map |
366 | { | |
367 | char *suffix; | |
368 | int length; | |
369 | bfd_reloc_code_real_type reloc; | |
370 | unsigned char operator; | |
371 | }; | |
372 | ||
373 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
374 | ||
375 | static struct suffix_reloc_map suffix_relocs[] = | |
376 | { | |
377 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
378 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
379 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 380 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
381 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
382 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
383 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
384 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
385 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
386 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } |
387 | }; | |
388 | ||
43cd72b9 | 389 | |
e0001a05 NC |
390 | /* Directives. */ |
391 | ||
392 | typedef enum | |
393 | { | |
394 | directive_none = 0, | |
395 | directive_literal, | |
396 | directive_density, | |
43cd72b9 | 397 | directive_transform, |
e0001a05 NC |
398 | directive_freeregs, |
399 | directive_longcalls, | |
43cd72b9 BW |
400 | directive_literal_prefix, |
401 | directive_schedule, | |
402 | directive_absolute_literals, | |
403 | directive_last_directive | |
e0001a05 NC |
404 | } directiveE; |
405 | ||
406 | typedef struct | |
407 | { | |
408 | const char *name; | |
409 | bfd_boolean can_be_negated; | |
410 | } directive_infoS; | |
411 | ||
412 | const directive_infoS directive_info[] = | |
413 | { | |
43cd72b9 BW |
414 | { "none", FALSE }, |
415 | { "literal", FALSE }, | |
416 | { "density", TRUE }, | |
417 | { "transform", TRUE }, | |
418 | { "freeregs", FALSE }, | |
419 | { "longcalls", TRUE }, | |
420 | { "literal_prefix", FALSE }, | |
421 | { "schedule", TRUE }, | |
422 | { "absolute-literals", TRUE } | |
e0001a05 NC |
423 | }; |
424 | ||
425 | bfd_boolean directive_state[] = | |
426 | { | |
427 | FALSE, /* none */ | |
428 | FALSE, /* literal */ | |
43cd72b9 | 429 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
430 | FALSE, /* density */ |
431 | #else | |
432 | TRUE, /* density */ | |
433 | #endif | |
43cd72b9 | 434 | TRUE, /* transform */ |
e0001a05 NC |
435 | FALSE, /* freeregs */ |
436 | FALSE, /* longcalls */ | |
43cd72b9 | 437 | FALSE, /* literal_prefix */ |
2caa7ca0 | 438 | FALSE, /* schedule */ |
43cd72b9 BW |
439 | #if XSHAL_USE_ABSOLUTE_LITERALS |
440 | TRUE /* absolute_literals */ | |
441 | #else | |
442 | FALSE /* absolute_literals */ | |
443 | #endif | |
e0001a05 NC |
444 | }; |
445 | ||
e0001a05 NC |
446 | |
447 | /* Directive functions. */ | |
448 | ||
7fa3d080 BW |
449 | static void xtensa_begin_directive (int); |
450 | static void xtensa_end_directive (int); | |
74869ac7 | 451 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
452 | static void xtensa_literal_position (int); |
453 | static void xtensa_literal_pseudo (int); | |
454 | static void xtensa_frequency_pseudo (int); | |
455 | static void xtensa_elf_cons (int); | |
fb227da0 | 456 | static void xtensa_leb128 (int); |
e0001a05 | 457 | |
7fa3d080 | 458 | /* Parsing and Idiom Translation. */ |
e0001a05 | 459 | |
7fa3d080 | 460 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 461 | |
e0001a05 NC |
462 | /* Various Other Internal Functions. */ |
463 | ||
84b08ed9 BW |
464 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
465 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
466 | static void xtensa_mark_literal_pool_location (void); |
467 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
468 | static fragS *get_literal_pool_location (segT); | |
469 | static void set_literal_pool_location (segT, fragS *); | |
470 | static void xtensa_set_frag_assembly_state (fragS *); | |
471 | static void finish_vinsn (vliw_insn *); | |
472 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 473 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
474 | |
475 | /* Alignment Functions. */ | |
476 | ||
d77b99c9 BW |
477 | static int get_text_align_power (unsigned); |
478 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 479 | static int branch_align_power (segT); |
e0001a05 NC |
480 | |
481 | /* Helpers for xtensa_relax_frag(). */ | |
482 | ||
7fa3d080 | 483 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 484 | |
b08b5071 | 485 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 486 | |
7fa3d080 BW |
487 | static unsigned get_last_insn_flags (segT, subsegT); |
488 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
489 | static float get_subseg_total_freq (segT, subsegT); |
490 | static float get_subseg_target_freq (segT, subsegT); | |
491 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
492 | |
493 | /* Segment list functions. */ | |
494 | ||
7fa3d080 BW |
495 | static void xtensa_move_literals (void); |
496 | static void xtensa_reorder_segments (void); | |
497 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
498 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
499 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
500 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 501 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 502 | |
e0001a05 | 503 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 504 | |
51c8ebc1 | 505 | extern asection *xtensa_make_property_section (asection *, const char *); |
e0001a05 | 506 | |
43cd72b9 BW |
507 | /* op_placement_info functions. */ |
508 | ||
7fa3d080 BW |
509 | static void init_op_placement_info_table (void); |
510 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
511 | static int xg_get_single_size (xtensa_opcode); | |
512 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 513 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 514 | |
e0001a05 | 515 | /* TInsn and IStack functions. */ |
43cd72b9 | 516 | |
7fa3d080 BW |
517 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
518 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
519 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
520 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
521 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
522 | static void tinsn_from_chars (TInsn *, char *, int); | |
523 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
524 | static int get_num_stack_text_bytes (IStack *); | |
525 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 526 | |
43cd72b9 BW |
527 | /* vliw_insn functions. */ |
528 | ||
7fa3d080 | 529 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 530 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 BW |
531 | static void xg_clear_vinsn (vliw_insn *); |
532 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
533 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 534 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
535 | (vliw_insn *, char *, fragS *, bfd_boolean); |
536 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 537 | |
e0001a05 | 538 | /* Expression Utilities. */ |
43cd72b9 | 539 | |
7fa3d080 BW |
540 | bfd_boolean expr_is_const (const expressionS *); |
541 | offsetT get_expr_const (const expressionS *); | |
542 | void set_expr_const (expressionS *, offsetT); | |
543 | bfd_boolean expr_is_register (const expressionS *); | |
544 | offsetT get_expr_register (const expressionS *); | |
545 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
546 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
547 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 548 | |
9456465c BW |
549 | /* Section renaming. */ |
550 | ||
7fa3d080 | 551 | static void build_section_rename (const char *); |
e0001a05 | 552 | |
e0001a05 NC |
553 | |
554 | /* ISA imported from bfd. */ | |
555 | extern xtensa_isa xtensa_default_isa; | |
556 | ||
557 | extern int target_big_endian; | |
558 | ||
559 | static xtensa_opcode xtensa_addi_opcode; | |
560 | static xtensa_opcode xtensa_addmi_opcode; | |
561 | static xtensa_opcode xtensa_call0_opcode; | |
562 | static xtensa_opcode xtensa_call4_opcode; | |
563 | static xtensa_opcode xtensa_call8_opcode; | |
564 | static xtensa_opcode xtensa_call12_opcode; | |
565 | static xtensa_opcode xtensa_callx0_opcode; | |
566 | static xtensa_opcode xtensa_callx4_opcode; | |
567 | static xtensa_opcode xtensa_callx8_opcode; | |
568 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 569 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 570 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 571 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
572 | static xtensa_opcode xtensa_movi_opcode; |
573 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 574 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 575 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 576 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 577 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
578 | static xtensa_opcode xtensa_loop_opcode; |
579 | static xtensa_opcode xtensa_loopnez_opcode; | |
580 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 581 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
582 | static xtensa_opcode xtensa_nop_n_opcode; |
583 | static xtensa_opcode xtensa_or_opcode; | |
584 | static xtensa_opcode xtensa_ret_opcode; | |
585 | static xtensa_opcode xtensa_ret_n_opcode; | |
586 | static xtensa_opcode xtensa_retw_opcode; | |
587 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 588 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 589 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 590 | static int config_max_slots = 0; |
e0001a05 NC |
591 | |
592 | \f | |
593 | /* Command-line Options. */ | |
594 | ||
595 | bfd_boolean use_literal_section = TRUE; | |
19fc3723 | 596 | enum flix_level produce_flix = FLIX_ALL; |
e0001a05 | 597 | static bfd_boolean align_targets = TRUE; |
43cd72b9 | 598 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 599 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
600 | static bfd_boolean workaround_a0_b_retw = FALSE; |
601 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
602 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 603 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 604 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 605 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 606 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 607 | |
43cd72b9 BW |
608 | /* When workaround_short_loops is TRUE, all loops with early exits must |
609 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
610 | to the workaround_short_loop flag. In addition to the | |
611 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
612 | must have at least 3 instructions. */ | |
e0001a05 | 613 | |
43cd72b9 | 614 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 615 | |
7fa3d080 BW |
616 | |
617 | static void | |
618 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
619 | { | |
620 | if (earliest > latest) | |
621 | as_fatal (_("illegal range of target hardware versions")); | |
622 | ||
623 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
624 | if (earliest < 105000 || latest < 105000) | |
625 | { | |
626 | workaround_a0_b_retw |= TRUE; | |
627 | workaround_b_j_loop_end |= TRUE; | |
628 | workaround_short_loop |= TRUE; | |
629 | workaround_close_loop_end |= TRUE; | |
630 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 631 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
632 | } |
633 | } | |
634 | ||
635 | ||
e0001a05 NC |
636 | enum |
637 | { | |
638 | option_density = OPTION_MD_BASE, | |
639 | option_no_density, | |
640 | ||
19fc3723 SA |
641 | option_flix, |
642 | option_no_generate_flix, | |
643 | option_no_flix, | |
644 | ||
e0001a05 NC |
645 | option_relax, |
646 | option_no_relax, | |
647 | ||
43cd72b9 BW |
648 | option_link_relax, |
649 | option_no_link_relax, | |
650 | ||
e0001a05 NC |
651 | option_generics, |
652 | option_no_generics, | |
653 | ||
43cd72b9 BW |
654 | option_transform, |
655 | option_no_transform, | |
656 | ||
e0001a05 NC |
657 | option_text_section_literals, |
658 | option_no_text_section_literals, | |
659 | ||
43cd72b9 BW |
660 | option_absolute_literals, |
661 | option_no_absolute_literals, | |
662 | ||
e0001a05 NC |
663 | option_align_targets, |
664 | option_no_align_targets, | |
665 | ||
43cd72b9 | 666 | option_warn_unaligned_targets, |
e0001a05 NC |
667 | |
668 | option_longcalls, | |
669 | option_no_longcalls, | |
670 | ||
671 | option_workaround_a0_b_retw, | |
672 | option_no_workaround_a0_b_retw, | |
673 | ||
674 | option_workaround_b_j_loop_end, | |
675 | option_no_workaround_b_j_loop_end, | |
676 | ||
677 | option_workaround_short_loop, | |
678 | option_no_workaround_short_loop, | |
679 | ||
680 | option_workaround_all_short_loops, | |
681 | option_no_workaround_all_short_loops, | |
682 | ||
683 | option_workaround_close_loop_end, | |
684 | option_no_workaround_close_loop_end, | |
685 | ||
686 | option_no_workarounds, | |
687 | ||
e0001a05 | 688 | option_rename_section_name, |
e0001a05 | 689 | |
43cd72b9 BW |
690 | option_prefer_l32r, |
691 | option_prefer_const16, | |
692 | ||
693 | option_target_hardware | |
e0001a05 NC |
694 | }; |
695 | ||
696 | const char *md_shortopts = ""; | |
697 | ||
698 | struct option md_longopts[] = | |
699 | { | |
43cd72b9 BW |
700 | { "density", no_argument, NULL, option_density }, |
701 | { "no-density", no_argument, NULL, option_no_density }, | |
702 | ||
19fc3723 SA |
703 | { "flix", no_argument, NULL, option_flix }, |
704 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
705 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
706 | ||
43cd72b9 BW |
707 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
708 | to the "transform" option. */ | |
709 | { "relax", no_argument, NULL, option_relax }, | |
710 | { "no-relax", no_argument, NULL, option_no_relax }, | |
711 | { "generics", no_argument, NULL, option_generics }, | |
712 | { "no-generics", no_argument, NULL, option_no_generics }, | |
713 | ||
714 | { "transform", no_argument, NULL, option_transform }, | |
715 | { "no-transform", no_argument, NULL, option_no_transform }, | |
716 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
717 | { "no-text-section-literals", no_argument, NULL, | |
718 | option_no_text_section_literals }, | |
719 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
720 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
721 | /* This option was changed from -align-target to -target-align |
722 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 723 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
724 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
725 | { "warn-unaligned-targets", no_argument, NULL, | |
726 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
727 | { "longcalls", no_argument, NULL, option_longcalls }, |
728 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
729 | ||
730 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
731 | option_no_workaround_a0_b_retw }, | |
732 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 733 | |
43cd72b9 BW |
734 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
735 | option_no_workaround_b_j_loop_end }, | |
736 | { "workaround-b-j-loop-end", no_argument, NULL, | |
737 | option_workaround_b_j_loop_end }, | |
e0001a05 | 738 | |
43cd72b9 BW |
739 | { "no-workaround-short-loops", no_argument, NULL, |
740 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
741 | { "workaround-short-loops", no_argument, NULL, |
742 | option_workaround_short_loop }, | |
e0001a05 | 743 | |
43cd72b9 BW |
744 | { "no-workaround-all-short-loops", no_argument, NULL, |
745 | option_no_workaround_all_short_loops }, | |
746 | { "workaround-all-short-loop", no_argument, NULL, | |
747 | option_workaround_all_short_loops }, | |
748 | ||
749 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
750 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
751 | ||
752 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
753 | ||
754 | { "no-workaround-close-loop-end", no_argument, NULL, | |
755 | option_no_workaround_close_loop_end }, | |
756 | { "workaround-close-loop-end", no_argument, NULL, | |
757 | option_workaround_close_loop_end }, | |
e0001a05 | 758 | |
7fa3d080 | 759 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 760 | |
43cd72b9 BW |
761 | { "link-relax", no_argument, NULL, option_link_relax }, |
762 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
763 | ||
764 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
765 | ||
766 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
767 | }; |
768 | ||
769 | size_t md_longopts_size = sizeof md_longopts; | |
770 | ||
771 | ||
772 | int | |
7fa3d080 | 773 | md_parse_option (int c, char *arg) |
e0001a05 NC |
774 | { |
775 | switch (c) | |
776 | { | |
777 | case option_density: | |
43cd72b9 | 778 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
779 | return 1; |
780 | case option_no_density: | |
43cd72b9 | 781 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 782 | return 1; |
43cd72b9 BW |
783 | case option_link_relax: |
784 | linkrelax = 1; | |
e0001a05 | 785 | return 1; |
43cd72b9 BW |
786 | case option_no_link_relax: |
787 | linkrelax = 0; | |
e0001a05 | 788 | return 1; |
19fc3723 SA |
789 | case option_flix: |
790 | produce_flix = FLIX_ALL; | |
791 | return 1; | |
792 | case option_no_generate_flix: | |
793 | produce_flix = FLIX_NO_GENERATE; | |
794 | return 1; | |
795 | case option_no_flix: | |
796 | produce_flix = FLIX_NONE; | |
797 | return 1; | |
43cd72b9 BW |
798 | case option_generics: |
799 | as_warn (_("--generics is deprecated; use --transform instead")); | |
800 | return md_parse_option (option_transform, arg); | |
801 | case option_no_generics: | |
802 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
803 | return md_parse_option (option_no_transform, arg); | |
804 | case option_relax: | |
805 | as_warn (_("--relax is deprecated; use --transform instead")); | |
806 | return md_parse_option (option_transform, arg); | |
807 | case option_no_relax: | |
808 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
809 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
810 | case option_longcalls: |
811 | directive_state[directive_longcalls] = TRUE; | |
812 | return 1; | |
813 | case option_no_longcalls: | |
814 | directive_state[directive_longcalls] = FALSE; | |
815 | return 1; | |
816 | case option_text_section_literals: | |
817 | use_literal_section = FALSE; | |
818 | return 1; | |
819 | case option_no_text_section_literals: | |
820 | use_literal_section = TRUE; | |
821 | return 1; | |
43cd72b9 BW |
822 | case option_absolute_literals: |
823 | if (!absolute_literals_supported) | |
824 | { | |
825 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
826 | return 0; | |
827 | } | |
828 | directive_state[directive_absolute_literals] = TRUE; | |
829 | return 1; | |
830 | case option_no_absolute_literals: | |
831 | directive_state[directive_absolute_literals] = FALSE; | |
832 | return 1; | |
833 | ||
e0001a05 NC |
834 | case option_workaround_a0_b_retw: |
835 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
836 | return 1; |
837 | case option_no_workaround_a0_b_retw: | |
838 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
839 | return 1; |
840 | case option_workaround_b_j_loop_end: | |
841 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
842 | return 1; |
843 | case option_no_workaround_b_j_loop_end: | |
844 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
845 | return 1; |
846 | ||
847 | case option_workaround_short_loop: | |
848 | workaround_short_loop = TRUE; | |
e0001a05 NC |
849 | return 1; |
850 | case option_no_workaround_short_loop: | |
851 | workaround_short_loop = FALSE; | |
e0001a05 NC |
852 | return 1; |
853 | ||
854 | case option_workaround_all_short_loops: | |
855 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
856 | return 1; |
857 | case option_no_workaround_all_short_loops: | |
858 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
859 | return 1; |
860 | ||
861 | case option_workaround_close_loop_end: | |
862 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
863 | return 1; |
864 | case option_no_workaround_close_loop_end: | |
865 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
866 | return 1; |
867 | ||
868 | case option_no_workarounds: | |
869 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 870 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 871 | workaround_short_loop = FALSE; |
e0001a05 | 872 | workaround_all_short_loops = FALSE; |
e0001a05 | 873 | workaround_close_loop_end = FALSE; |
e0001a05 | 874 | return 1; |
43cd72b9 | 875 | |
e0001a05 NC |
876 | case option_align_targets: |
877 | align_targets = TRUE; | |
878 | return 1; | |
879 | case option_no_align_targets: | |
880 | align_targets = FALSE; | |
881 | return 1; | |
882 | ||
43cd72b9 BW |
883 | case option_warn_unaligned_targets: |
884 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
885 | return 1; |
886 | ||
e0001a05 NC |
887 | case option_rename_section_name: |
888 | build_section_rename (arg); | |
889 | return 1; | |
e0001a05 NC |
890 | |
891 | case 'Q': | |
892 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
893 | should be emitted or not. FIXME: Not implemented. */ | |
894 | return 1; | |
c138bc38 | 895 | |
43cd72b9 BW |
896 | case option_prefer_l32r: |
897 | if (prefer_const16) | |
898 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
899 | prefer_l32r = 1; | |
900 | return 1; | |
901 | ||
902 | case option_prefer_const16: | |
903 | if (prefer_l32r) | |
904 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
905 | prefer_const16 = 1; | |
906 | return 1; | |
907 | ||
c138bc38 | 908 | case option_target_hardware: |
43cd72b9 BW |
909 | { |
910 | int earliest, latest = 0; | |
911 | if (*arg == 0 || *arg == '-') | |
912 | as_fatal (_("invalid target hardware version")); | |
913 | ||
914 | earliest = strtol (arg, &arg, 0); | |
915 | ||
916 | if (*arg == 0) | |
917 | latest = earliest; | |
918 | else if (*arg == '-') | |
919 | { | |
920 | if (*++arg == 0) | |
921 | as_fatal (_("invalid target hardware version")); | |
922 | latest = strtol (arg, &arg, 0); | |
923 | } | |
924 | if (*arg != 0) | |
925 | as_fatal (_("invalid target hardware version")); | |
926 | ||
927 | xtensa_setup_hw_workarounds (earliest, latest); | |
928 | return 1; | |
929 | } | |
930 | ||
931 | case option_transform: | |
932 | /* This option has no affect other than to use the defaults, | |
933 | which are already set. */ | |
934 | return 1; | |
935 | ||
936 | case option_no_transform: | |
937 | /* This option turns off all transformations of any kind. | |
938 | However, because we want to preserve the state of other | |
939 | directives, we only change its own field. Thus, before | |
940 | you perform any transformation, always check if transform | |
941 | is available. If you use the functions we provide for this | |
942 | purpose, you will be ok. */ | |
943 | directive_state[directive_transform] = FALSE; | |
944 | return 1; | |
945 | ||
e0001a05 NC |
946 | default: |
947 | return 0; | |
948 | } | |
949 | } | |
950 | ||
951 | ||
952 | void | |
7fa3d080 | 953 | md_show_usage (FILE *stream) |
e0001a05 | 954 | { |
43cd72b9 BW |
955 | fputs ("\n\ |
956 | Xtensa options:\n\ | |
9456465c BW |
957 | --[no-]text-section-literals\n\ |
958 | [Do not] put literals in the text section\n\ | |
959 | --[no-]absolute-literals\n\ | |
960 | [Do not] default to use non-PC-relative literals\n\ | |
961 | --[no-]target-align [Do not] try to align branch targets\n\ | |
962 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
963 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
964 | --flix both allow hand-written and generate flix bundles\n\ |
965 | --no-generate-flix allow hand-written but do not generate\n\ | |
966 | flix bundles\n\ | |
967 | --no-allow-flix neither allow hand-written nor generate\n\ | |
968 | flix bundles\n\ | |
9456465c | 969 | --rename-section old=new Rename section 'old' to 'new'\n", stream); |
e0001a05 NC |
970 | } |
971 | ||
7fa3d080 BW |
972 | \f |
973 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
974 | |
975 | static void | |
7fa3d080 | 976 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 977 | { |
7fa3d080 | 978 | sym_list *l; |
43cd72b9 | 979 | |
7fa3d080 BW |
980 | if (!free_insn_labels) |
981 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
982 | else | |
43cd72b9 | 983 | { |
7fa3d080 BW |
984 | l = free_insn_labels; |
985 | free_insn_labels = l->next; | |
986 | } | |
987 | ||
988 | l->sym = sym; | |
989 | l->next = insn_labels; | |
990 | insn_labels = l; | |
991 | } | |
992 | ||
993 | ||
994 | static void | |
995 | xtensa_clear_insn_labels (void) | |
996 | { | |
997 | sym_list **pl; | |
998 | ||
999 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1000 | ; | |
1001 | *pl = insn_labels; | |
1002 | insn_labels = NULL; | |
1003 | } | |
1004 | ||
1005 | ||
7fa3d080 | 1006 | static void |
c3ea6048 | 1007 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1008 | { |
1009 | sym_list *lit; | |
1010 | ||
1011 | for (lit = insn_labels; lit; lit = lit->next) | |
1012 | { | |
1013 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1014 | S_SET_VALUE (lit_sym, new_offset); |
1015 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1016 | } |
1017 | } | |
1018 | ||
e0001a05 NC |
1019 | \f |
1020 | /* Directive data and functions. */ | |
1021 | ||
1022 | typedef struct state_stackS_struct | |
1023 | { | |
1024 | directiveE directive; | |
1025 | bfd_boolean negated; | |
1026 | bfd_boolean old_state; | |
1027 | const char *file; | |
1028 | unsigned int line; | |
1029 | const void *datum; | |
1030 | struct state_stackS_struct *prev; | |
1031 | } state_stackS; | |
1032 | ||
1033 | state_stackS *directive_state_stack; | |
1034 | ||
1035 | const pseudo_typeS md_pseudo_table[] = | |
1036 | { | |
43cd72b9 BW |
1037 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1038 | { "literal_position", xtensa_literal_position, 0 }, | |
1039 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1040 | { "long", xtensa_elf_cons, 4 }, | |
1041 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1042 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1043 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1044 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1045 | { "sleb128", xtensa_leb128, 1}, |
1046 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1047 | { "begin", xtensa_begin_directive, 0 }, |
1048 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1049 | { "literal", xtensa_literal_pseudo, 0 }, |
1050 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1051 | { NULL, 0, 0 }, | |
e0001a05 NC |
1052 | }; |
1053 | ||
1054 | ||
7fa3d080 BW |
1055 | static bfd_boolean |
1056 | use_transform (void) | |
e0001a05 | 1057 | { |
43cd72b9 BW |
1058 | /* After md_end, you should be checking frag by frag, rather |
1059 | than state directives. */ | |
9c2799c2 | 1060 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1061 | return directive_state[directive_transform]; |
e0001a05 NC |
1062 | } |
1063 | ||
1064 | ||
7fa3d080 BW |
1065 | static bfd_boolean |
1066 | do_align_targets (void) | |
e0001a05 | 1067 | { |
7b1cc377 BW |
1068 | /* Do not use this function after md_end; just look at align_targets |
1069 | instead. There is no target-align directive, so alignment is either | |
1070 | enabled for all frags or not done at all. */ | |
9c2799c2 | 1071 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1072 | return align_targets && use_transform (); |
e0001a05 NC |
1073 | } |
1074 | ||
1075 | ||
1076 | static void | |
7fa3d080 | 1077 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1078 | { |
1079 | char *file; | |
1080 | unsigned int line; | |
1081 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1082 | ||
1083 | as_where (&file, &line); | |
1084 | ||
1085 | stack->directive = directive; | |
1086 | stack->negated = negated; | |
1087 | stack->old_state = directive_state[directive]; | |
1088 | stack->file = file; | |
1089 | stack->line = line; | |
1090 | stack->datum = datum; | |
1091 | stack->prev = directive_state_stack; | |
1092 | directive_state_stack = stack; | |
1093 | ||
1094 | directive_state[directive] = !negated; | |
1095 | } | |
1096 | ||
7fa3d080 | 1097 | |
e0001a05 | 1098 | static void |
7fa3d080 BW |
1099 | directive_pop (directiveE *directive, |
1100 | bfd_boolean *negated, | |
1101 | const char **file, | |
1102 | unsigned int *line, | |
1103 | const void **datum) | |
e0001a05 NC |
1104 | { |
1105 | state_stackS *top = directive_state_stack; | |
1106 | ||
1107 | if (!directive_state_stack) | |
1108 | { | |
1109 | as_bad (_("unmatched end directive")); | |
1110 | *directive = directive_none; | |
1111 | return; | |
1112 | } | |
1113 | ||
1114 | directive_state[directive_state_stack->directive] = top->old_state; | |
1115 | *directive = top->directive; | |
1116 | *negated = top->negated; | |
1117 | *file = top->file; | |
1118 | *line = top->line; | |
1119 | *datum = top->datum; | |
1120 | directive_state_stack = top->prev; | |
1121 | free (top); | |
1122 | } | |
1123 | ||
1124 | ||
1125 | static void | |
7fa3d080 | 1126 | directive_balance (void) |
e0001a05 NC |
1127 | { |
1128 | while (directive_state_stack) | |
1129 | { | |
1130 | directiveE directive; | |
1131 | bfd_boolean negated; | |
1132 | const char *file; | |
1133 | unsigned int line; | |
1134 | const void *datum; | |
1135 | ||
1136 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1137 | as_warn_where ((char *) file, line, | |
1138 | _(".begin directive with no matching .end directive")); | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | ||
1143 | static bfd_boolean | |
7fa3d080 | 1144 | inside_directive (directiveE dir) |
e0001a05 NC |
1145 | { |
1146 | state_stackS *top = directive_state_stack; | |
1147 | ||
1148 | while (top && top->directive != dir) | |
1149 | top = top->prev; | |
1150 | ||
1151 | return (top != NULL); | |
1152 | } | |
1153 | ||
1154 | ||
1155 | static void | |
7fa3d080 | 1156 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1157 | { |
1158 | int len; | |
1159 | unsigned i; | |
43cd72b9 | 1160 | char *directive_string; |
e0001a05 NC |
1161 | |
1162 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1163 | *negated = FALSE; | |
1164 | else | |
1165 | { | |
1166 | *negated = TRUE; | |
1167 | input_line_pointer += 3; | |
1168 | } | |
1169 | ||
1170 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1171 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1172 | ||
1173 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1174 | equivalent to .begin [no-]transform. We should remove it when | |
1175 | we stop accepting those options. */ | |
c138bc38 | 1176 | |
43cd72b9 BW |
1177 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1178 | { | |
1179 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1180 | directive_string = "transform"; | |
1181 | } | |
1182 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1183 | { | |
1184 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1185 | directive_string = "transform"; | |
c138bc38 | 1186 | } |
43cd72b9 BW |
1187 | else |
1188 | directive_string = input_line_pointer; | |
e0001a05 NC |
1189 | |
1190 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1191 | { | |
43cd72b9 | 1192 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1193 | { |
1194 | input_line_pointer += len; | |
1195 | *directive = (directiveE) i; | |
1196 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1197 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1198 | directive_info[i].name); |
1199 | return; | |
1200 | } | |
1201 | } | |
1202 | ||
1203 | as_bad (_("unknown directive")); | |
1204 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1205 | } | |
1206 | ||
1207 | ||
1208 | static void | |
7fa3d080 | 1209 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1210 | { |
1211 | directiveE directive; | |
1212 | bfd_boolean negated; | |
1213 | emit_state *state; | |
e0001a05 NC |
1214 | lit_state *ls; |
1215 | ||
1216 | get_directive (&directive, &negated); | |
1217 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1218 | { | |
1219 | discard_rest_of_line (); | |
1220 | return; | |
1221 | } | |
1222 | ||
43cd72b9 BW |
1223 | if (cur_vinsn.inside_bundle) |
1224 | as_bad (_("directives are not valid inside bundles")); | |
1225 | ||
e0001a05 NC |
1226 | switch (directive) |
1227 | { | |
1228 | case directive_literal: | |
82e7541d BW |
1229 | if (!inside_directive (directive_literal)) |
1230 | { | |
1231 | /* Previous labels go with whatever follows this directive, not with | |
1232 | the literal, so save them now. */ | |
1233 | saved_insn_labels = insn_labels; | |
1234 | insn_labels = NULL; | |
1235 | } | |
43cd72b9 | 1236 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1237 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1238 | xtensa_switch_to_literal_fragment (state); | |
1239 | directive_push (directive_literal, negated, state); | |
1240 | break; | |
1241 | ||
1242 | case directive_literal_prefix: | |
c138bc38 | 1243 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1244 | might produce a literal. */ |
1245 | md_flush_pending_output (); | |
e0001a05 NC |
1246 | /* Check to see if the current fragment is a literal |
1247 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1248 | if (generating_literals) |
e0001a05 NC |
1249 | { |
1250 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1251 | return; | |
1252 | } | |
1253 | ||
1254 | /* Allocate the literal state for this section and push | |
1255 | onto the directive stack. */ | |
1256 | ls = xmalloc (sizeof (lit_state)); | |
9c2799c2 | 1257 | gas_assert (ls); |
e0001a05 NC |
1258 | |
1259 | *ls = default_lit_sections; | |
e0001a05 NC |
1260 | directive_push (directive_literal_prefix, negated, ls); |
1261 | ||
e0001a05 | 1262 | /* Process the new prefix. */ |
74869ac7 | 1263 | xtensa_literal_prefix (); |
e0001a05 NC |
1264 | break; |
1265 | ||
1266 | case directive_freeregs: | |
1267 | /* This information is currently unused, but we'll accept the statement | |
1268 | and just discard the rest of the line. This won't check the syntax, | |
1269 | but it will accept every correct freeregs directive. */ | |
1270 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1271 | directive_push (directive_freeregs, negated, 0); | |
1272 | break; | |
1273 | ||
43cd72b9 BW |
1274 | case directive_schedule: |
1275 | md_flush_pending_output (); | |
1276 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1277 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1278 | directive_push (directive_schedule, negated, 0); | |
1279 | xtensa_set_frag_assembly_state (frag_now); | |
1280 | break; | |
1281 | ||
e0001a05 | 1282 | case directive_density: |
43cd72b9 BW |
1283 | as_warn (_(".begin [no-]density is ignored")); |
1284 | break; | |
1285 | ||
1286 | case directive_absolute_literals: | |
1287 | md_flush_pending_output (); | |
1288 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1289 | { |
43cd72b9 | 1290 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1291 | break; |
1292 | } | |
43cd72b9 BW |
1293 | xtensa_set_frag_assembly_state (frag_now); |
1294 | directive_push (directive, negated, 0); | |
1295 | break; | |
e0001a05 NC |
1296 | |
1297 | default: | |
43cd72b9 BW |
1298 | md_flush_pending_output (); |
1299 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1300 | directive_push (directive, negated, 0); |
1301 | break; | |
1302 | } | |
1303 | ||
1304 | demand_empty_rest_of_line (); | |
1305 | } | |
1306 | ||
1307 | ||
1308 | static void | |
7fa3d080 | 1309 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1310 | { |
1311 | directiveE begin_directive, end_directive; | |
1312 | bfd_boolean begin_negated, end_negated; | |
1313 | const char *file; | |
1314 | unsigned int line; | |
1315 | emit_state *state; | |
43cd72b9 | 1316 | emit_state **state_ptr; |
e0001a05 NC |
1317 | lit_state *s; |
1318 | ||
43cd72b9 BW |
1319 | if (cur_vinsn.inside_bundle) |
1320 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1321 | |
e0001a05 | 1322 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1323 | |
1324 | md_flush_pending_output (); | |
1325 | ||
1326 | switch (end_directive) | |
e0001a05 | 1327 | { |
43cd72b9 | 1328 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1329 | discard_rest_of_line (); |
1330 | return; | |
e0001a05 | 1331 | |
43cd72b9 BW |
1332 | case directive_density: |
1333 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1334 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1335 | break; |
1336 | ||
1337 | case directive_absolute_literals: | |
1338 | if (!absolute_literals_supported && !end_negated) | |
1339 | { | |
1340 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1341 | demand_empty_rest_of_line (); | |
1342 | return; | |
1343 | } | |
1344 | break; | |
1345 | ||
1346 | default: | |
1347 | break; | |
e0001a05 NC |
1348 | } |
1349 | ||
43cd72b9 | 1350 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1351 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1352 | (const void **) state_ptr); |
e0001a05 NC |
1353 | |
1354 | if (begin_directive != directive_none) | |
1355 | { | |
1356 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1357 | { | |
1358 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1359 | begin_negated ? "no-" : "", | |
1360 | directive_info[begin_directive].name, file, line); | |
1361 | } | |
1362 | else | |
1363 | { | |
1364 | switch (end_directive) | |
1365 | { | |
1366 | case directive_literal: | |
1367 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1368 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1369 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1370 | free (state); |
82e7541d BW |
1371 | if (!inside_directive (directive_literal)) |
1372 | { | |
1373 | /* Restore the list of current labels. */ | |
1374 | xtensa_clear_insn_labels (); | |
1375 | insn_labels = saved_insn_labels; | |
1376 | } | |
e0001a05 NC |
1377 | break; |
1378 | ||
e0001a05 NC |
1379 | case directive_literal_prefix: |
1380 | /* Restore the default collection sections from saved state. */ | |
1381 | s = (lit_state *) state; | |
9c2799c2 | 1382 | gas_assert (s); |
e8247da7 | 1383 | default_lit_sections = *s; |
e0001a05 | 1384 | |
74869ac7 BW |
1385 | /* Free the state storage. */ |
1386 | free (s->lit_prefix); | |
e0001a05 NC |
1387 | free (s); |
1388 | break; | |
1389 | ||
43cd72b9 BW |
1390 | case directive_schedule: |
1391 | case directive_freeregs: | |
1392 | break; | |
1393 | ||
e0001a05 | 1394 | default: |
43cd72b9 | 1395 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1396 | break; |
1397 | } | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | demand_empty_rest_of_line (); | |
1402 | } | |
1403 | ||
1404 | ||
1405 | /* Place an aligned literal fragment at the current location. */ | |
1406 | ||
1407 | static void | |
7fa3d080 | 1408 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1409 | { |
43cd72b9 BW |
1410 | md_flush_pending_output (); |
1411 | ||
e0001a05 NC |
1412 | if (inside_directive (directive_literal)) |
1413 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1414 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1415 | |
1416 | demand_empty_rest_of_line (); | |
82e7541d | 1417 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1418 | } |
1419 | ||
1420 | ||
43cd72b9 | 1421 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1422 | |
1423 | static void | |
7fa3d080 | 1424 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1425 | { |
1426 | emit_state state; | |
1745fcba | 1427 | char *p, *base_name; |
e0001a05 | 1428 | char c; |
e0001a05 NC |
1429 | segT dest_seg; |
1430 | ||
82e7541d BW |
1431 | if (inside_directive (directive_literal)) |
1432 | { | |
1433 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1434 | ignore_rest_of_line (); | |
1435 | return; | |
1436 | } | |
1437 | ||
43cd72b9 BW |
1438 | md_flush_pending_output (); |
1439 | ||
82e7541d BW |
1440 | /* Previous labels go with whatever follows this directive, not with |
1441 | the literal, so save them now. */ | |
1442 | saved_insn_labels = insn_labels; | |
1443 | insn_labels = NULL; | |
1444 | ||
e0001a05 NC |
1445 | /* If we are using text-section literals, then this is the right value... */ |
1446 | dest_seg = now_seg; | |
1447 | ||
1448 | base_name = input_line_pointer; | |
1449 | ||
1450 | xtensa_switch_to_literal_fragment (&state); | |
1451 | ||
43cd72b9 | 1452 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1453 | need to put them in the section we just switched to. */ |
43cd72b9 | 1454 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1455 | dest_seg = now_seg; |
1456 | ||
43cd72b9 BW |
1457 | /* All literals are aligned to four-byte boundaries. */ |
1458 | frag_align (2, 0, 0); | |
1459 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1460 | |
1461 | c = get_symbol_end (); | |
1462 | /* Just after name is now '\0'. */ | |
1463 | p = input_line_pointer; | |
1464 | *p = c; | |
1465 | SKIP_WHITESPACE (); | |
1466 | ||
1467 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1468 | { | |
1469 | as_bad (_("expected comma or colon after symbol name; " | |
1470 | "rest of line ignored")); | |
1471 | ignore_rest_of_line (); | |
1472 | xtensa_restore_emit_state (&state); | |
1473 | return; | |
1474 | } | |
1475 | *p = 0; | |
1476 | ||
e0001a05 | 1477 | colon (base_name); |
e0001a05 | 1478 | |
e0001a05 | 1479 | *p = c; |
43cd72b9 | 1480 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1481 | |
43cd72b9 | 1482 | xtensa_elf_cons (4); |
e0001a05 NC |
1483 | |
1484 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1485 | |
1486 | /* Restore the list of current labels. */ | |
1487 | xtensa_clear_insn_labels (); | |
1488 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1489 | } |
1490 | ||
1491 | ||
1492 | static void | |
74869ac7 | 1493 | xtensa_literal_prefix (void) |
e0001a05 | 1494 | { |
74869ac7 BW |
1495 | char *name; |
1496 | int len; | |
1497 | ||
1498 | /* Parse the new prefix from the input_line_pointer. */ | |
1499 | SKIP_WHITESPACE (); | |
1500 | len = strspn (input_line_pointer, | |
1501 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1502 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1503 | |
1504 | /* Get a null-terminated copy of the name. */ | |
1505 | name = xmalloc (len + 1); | |
9c2799c2 | 1506 | gas_assert (name); |
74869ac7 | 1507 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1508 | name[len] = 0; |
1509 | ||
74869ac7 BW |
1510 | /* Skip the name in the input line. */ |
1511 | input_line_pointer += len; | |
43cd72b9 | 1512 | |
74869ac7 | 1513 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1514 | |
74869ac7 | 1515 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1516 | default_lit_sections.lit_seg = NULL; |
1517 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1518 | } |
1519 | ||
1520 | ||
1521 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1522 | ||
1523 | static void | |
7fa3d080 | 1524 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1525 | { |
1526 | float fall_through_f, target_f; | |
43cd72b9 BW |
1527 | |
1528 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1529 | if (fall_through_f < 0) | |
1530 | { | |
1531 | as_bad (_("fall through frequency must be greater than 0")); | |
1532 | ignore_rest_of_line (); | |
1533 | return; | |
1534 | } | |
1535 | ||
1536 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1537 | if (target_f < 0) | |
1538 | { | |
1539 | as_bad (_("branch target frequency must be greater than 0")); | |
1540 | ignore_rest_of_line (); | |
1541 | return; | |
1542 | } | |
1543 | ||
b08b5071 | 1544 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1545 | |
1546 | demand_empty_rest_of_line (); | |
1547 | } | |
1548 | ||
1549 | ||
1550 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1551 | Clobbers input_line_pointer, checks end-of-line. */ | |
1552 | ||
1553 | static void | |
7fa3d080 | 1554 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1555 | { |
1556 | expressionS exp; | |
1557 | bfd_reloc_code_real_type reloc; | |
1558 | ||
1559 | md_flush_pending_output (); | |
1560 | ||
1561 | if (cur_vinsn.inside_bundle) | |
1562 | as_bad (_("directives are not valid inside bundles")); | |
1563 | ||
1564 | if (is_it_end_of_statement ()) | |
1565 | { | |
1566 | demand_empty_rest_of_line (); | |
1567 | return; | |
1568 | } | |
1569 | ||
1570 | do | |
1571 | { | |
1572 | expression (&exp); | |
1573 | if (exp.X_op == O_symbol | |
1574 | && *input_line_pointer == '@' | |
1575 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1576 | != BFD_RELOC_NONE)) | |
1577 | { | |
1578 | reloc_howto_type *reloc_howto = | |
1579 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1580 | ||
1581 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1582 | as_bad (_("unsupported relocation")); | |
1583 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1584 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1585 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1586 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1587 | as_bad (_("opcode-specific %s relocation used outside " | |
1588 | "an instruction"), reloc_howto->name); | |
1589 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1590 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1591 | reloc_howto->name, nbytes); | |
28dbbc02 BW |
1592 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1593 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1594 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1595 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1596 | else |
1597 | { | |
1598 | char *p = frag_more ((int) nbytes); | |
1599 | xtensa_set_frag_assembly_state (frag_now); | |
1600 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1601 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1602 | } |
1603 | } | |
1604 | else | |
1f7efbae BW |
1605 | { |
1606 | xtensa_set_frag_assembly_state (frag_now); | |
1607 | emit_expr (&exp, (unsigned int) nbytes); | |
1608 | } | |
43cd72b9 BW |
1609 | } |
1610 | while (*input_line_pointer++ == ','); | |
1611 | ||
1612 | input_line_pointer--; /* Put terminator back into stream. */ | |
1613 | demand_empty_rest_of_line (); | |
1614 | } | |
1615 | ||
fb227da0 BW |
1616 | static bfd_boolean is_leb128_expr; |
1617 | ||
1618 | static void | |
1619 | xtensa_leb128 (int sign) | |
1620 | { | |
1621 | is_leb128_expr = TRUE; | |
1622 | s_leb128 (sign); | |
1623 | is_leb128_expr = FALSE; | |
1624 | } | |
1625 | ||
7fa3d080 BW |
1626 | \f |
1627 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1628 | |
1629 | /* Parse @plt, etc. and return the desired relocation. */ | |
1630 | static bfd_reloc_code_real_type | |
7fa3d080 | 1631 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1632 | { |
43cd72b9 BW |
1633 | char ident[20]; |
1634 | char *str = *str_p; | |
1635 | char *str2; | |
1636 | int ch; | |
1637 | int len; | |
bbdd25a8 | 1638 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1639 | |
1640 | if (*str++ != '@') | |
1641 | return BFD_RELOC_NONE; | |
1642 | ||
1643 | for (ch = *str, str2 = ident; | |
1644 | (str2 < ident + sizeof (ident) - 1 | |
1645 | && (ISALNUM (ch) || ch == '@')); | |
1646 | ch = *++str) | |
1647 | { | |
1648 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1649 | } | |
1650 | ||
1651 | *str2 = '\0'; | |
1652 | len = str2 - ident; | |
1653 | ||
1654 | ch = ident[0]; | |
bbdd25a8 BW |
1655 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1656 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1657 | && len == ptr->length |
bbdd25a8 | 1658 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1659 | { |
1660 | /* Now check for "identifier@suffix+constant". */ | |
1661 | if (*str == '-' || *str == '+') | |
1662 | { | |
1663 | char *orig_line = input_line_pointer; | |
1664 | expressionS new_exp; | |
1665 | ||
1666 | input_line_pointer = str; | |
1667 | expression (&new_exp); | |
1668 | if (new_exp.X_op == O_constant) | |
1669 | { | |
1670 | exp_p->X_add_number += new_exp.X_add_number; | |
1671 | str = input_line_pointer; | |
1672 | } | |
1673 | ||
1674 | if (&input_line_pointer != str_p) | |
1675 | input_line_pointer = orig_line; | |
1676 | } | |
1677 | ||
1678 | *str_p = str; | |
1679 | return ptr->reloc; | |
1680 | } | |
1681 | ||
1682 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1683 | } |
1684 | ||
e0001a05 | 1685 | |
bbdd25a8 BW |
1686 | /* Find the matching operator type. */ |
1687 | static unsigned char | |
1688 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1689 | { | |
1690 | struct suffix_reloc_map *sfx; | |
1691 | unsigned char operator = (unsigned char) -1; | |
1692 | ||
1693 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1694 | { | |
1695 | if (sfx->reloc == reloc) | |
1696 | { | |
1697 | operator = sfx->operator; | |
1698 | break; | |
1699 | } | |
1700 | } | |
9c2799c2 | 1701 | gas_assert (operator != (unsigned char) -1); |
bbdd25a8 BW |
1702 | return operator; |
1703 | } | |
1704 | ||
1705 | ||
1706 | /* Find the matching reloc type. */ | |
1707 | static bfd_reloc_code_real_type | |
28dbbc02 | 1708 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 BW |
1709 | { |
1710 | struct suffix_reloc_map *sfx; | |
1711 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1712 | ||
1713 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1714 | { | |
1715 | if (sfx->operator == operator) | |
1716 | { | |
1717 | reloc = sfx->reloc; | |
1718 | break; | |
1719 | } | |
1720 | } | |
1721 | ||
28dbbc02 BW |
1722 | if (is_literal) |
1723 | { | |
1724 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1725 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1726 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1727 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1728 | } | |
1729 | ||
bbdd25a8 BW |
1730 | if (reloc == BFD_RELOC_UNUSED) |
1731 | return BFD_RELOC_32; | |
1732 | ||
1733 | return reloc; | |
1734 | } | |
1735 | ||
1736 | ||
e0001a05 | 1737 | static const char * |
7fa3d080 | 1738 | expression_end (const char *name) |
e0001a05 NC |
1739 | { |
1740 | while (1) | |
1741 | { | |
1742 | switch (*name) | |
1743 | { | |
43cd72b9 | 1744 | case '}': |
e0001a05 NC |
1745 | case ';': |
1746 | case '\0': | |
1747 | case ',': | |
43cd72b9 | 1748 | case ':': |
e0001a05 NC |
1749 | return name; |
1750 | case ' ': | |
1751 | case '\t': | |
1752 | ++name; | |
1753 | continue; | |
1754 | default: | |
1755 | return 0; | |
1756 | } | |
1757 | } | |
1758 | } | |
1759 | ||
1760 | ||
1761 | #define ERROR_REG_NUM ((unsigned) -1) | |
1762 | ||
1763 | static unsigned | |
7fa3d080 | 1764 | tc_get_register (const char *prefix) |
e0001a05 NC |
1765 | { |
1766 | unsigned reg; | |
1767 | const char *next_expr; | |
1768 | const char *old_line_pointer; | |
1769 | ||
1770 | SKIP_WHITESPACE (); | |
1771 | old_line_pointer = input_line_pointer; | |
1772 | ||
1773 | if (*input_line_pointer == '$') | |
1774 | ++input_line_pointer; | |
1775 | ||
1776 | /* Accept "sp" as a synonym for "a1". */ | |
1777 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1778 | && expression_end (input_line_pointer + 2)) | |
1779 | { | |
1780 | input_line_pointer += 2; | |
1781 | return 1; /* AR[1] */ | |
1782 | } | |
1783 | ||
1784 | while (*input_line_pointer++ == *prefix++) | |
1785 | ; | |
1786 | --input_line_pointer; | |
1787 | --prefix; | |
1788 | ||
1789 | if (*prefix) | |
1790 | { | |
1791 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1792 | return ERROR_REG_NUM; | |
1793 | } | |
1794 | ||
1795 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1796 | { | |
1797 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1798 | return ERROR_REG_NUM; | |
1799 | } | |
1800 | ||
1801 | reg = 0; | |
1802 | ||
1803 | while (ISDIGIT ((int) *input_line_pointer)) | |
1804 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1805 | ||
1806 | if (!(next_expr = expression_end (input_line_pointer))) | |
1807 | { | |
1808 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1809 | return ERROR_REG_NUM; | |
1810 | } | |
1811 | ||
1812 | input_line_pointer = (char *) next_expr; | |
1813 | ||
1814 | return reg; | |
1815 | } | |
1816 | ||
1817 | ||
e0001a05 | 1818 | static void |
7fa3d080 | 1819 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1820 | { |
43cd72b9 | 1821 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1822 | |
43cd72b9 BW |
1823 | /* Check if this is an immediate operand. */ |
1824 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1825 | { |
43cd72b9 | 1826 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1827 | segT t = expression (tok); |
43cd72b9 BW |
1828 | if (t == absolute_section |
1829 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1830 | { |
9c2799c2 | 1831 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1832 | tok->X_op = O_symbol; |
1833 | tok->X_add_symbol = &abs_symbol; | |
1834 | } | |
43cd72b9 BW |
1835 | |
1836 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1837 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1838 | != BFD_RELOC_NONE)) | |
e0001a05 | 1839 | { |
1bbb5f21 | 1840 | switch (reloc) |
43cd72b9 | 1841 | { |
1bbb5f21 BW |
1842 | case BFD_RELOC_LO16: |
1843 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1844 | { |
43cd72b9 | 1845 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1846 | return; |
1bbb5f21 BW |
1847 | } |
1848 | break; | |
1849 | case BFD_RELOC_HI16: | |
1850 | if (tok->X_op == O_constant) | |
1851 | { | |
43cd72b9 | 1852 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1853 | return; |
bbdd25a8 | 1854 | } |
1bbb5f21 BW |
1855 | break; |
1856 | case BFD_RELOC_UNUSED: | |
1857 | as_bad (_("unsupported relocation")); | |
1858 | return; | |
1859 | case BFD_RELOC_32_PCREL: | |
1860 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1861 | return; | |
1862 | default: | |
1863 | break; | |
43cd72b9 | 1864 | } |
bbdd25a8 | 1865 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1866 | } |
e0001a05 NC |
1867 | } |
1868 | else | |
1869 | { | |
43cd72b9 BW |
1870 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1871 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1872 | |
1873 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1874 | { | |
1875 | uint32 buf = reg; | |
43cd72b9 | 1876 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1877 | as_bad (_("register number out of range")); |
1878 | } | |
1879 | ||
1880 | tok->X_op = O_register; | |
1881 | tok->X_add_symbol = 0; | |
1882 | tok->X_add_number = reg; | |
1883 | } | |
1884 | } | |
1885 | ||
1886 | ||
1887 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1888 | ||
1889 | static int | |
7fa3d080 | 1890 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1891 | { |
1892 | char *old_input_line_pointer; | |
1893 | bfd_boolean saw_comma = FALSE; | |
1894 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1895 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1896 | int num_args = 0; |
1897 | char *arg_end, *arg; | |
1898 | int arg_len; | |
43cd72b9 BW |
1899 | |
1900 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1901 | old_input_line_pointer = input_line_pointer; |
1902 | input_line_pointer = str; | |
1903 | ||
1904 | while (*input_line_pointer) | |
1905 | { | |
1906 | SKIP_WHITESPACE (); | |
1907 | switch (*input_line_pointer) | |
1908 | { | |
1909 | case '\0': | |
43cd72b9 | 1910 | case '}': |
e0001a05 NC |
1911 | goto fini; |
1912 | ||
43cd72b9 BW |
1913 | case ':': |
1914 | input_line_pointer++; | |
1915 | if (saw_comma || saw_colon || !saw_arg) | |
1916 | goto err; | |
1917 | saw_colon = TRUE; | |
1918 | break; | |
1919 | ||
e0001a05 NC |
1920 | case ',': |
1921 | input_line_pointer++; | |
43cd72b9 | 1922 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1923 | goto err; |
1924 | saw_comma = TRUE; | |
1925 | break; | |
1926 | ||
1927 | default: | |
43cd72b9 | 1928 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1929 | goto err; |
1930 | ||
1931 | arg_end = input_line_pointer + 1; | |
1932 | while (!expression_end (arg_end)) | |
1933 | arg_end += 1; | |
43cd72b9 | 1934 | |
e0001a05 | 1935 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1936 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1937 | args[num_args] = arg; |
1938 | ||
43cd72b9 BW |
1939 | if (saw_colon) |
1940 | *arg++ = ':'; | |
e0001a05 NC |
1941 | strncpy (arg, input_line_pointer, arg_len); |
1942 | arg[arg_len] = '\0'; | |
43cd72b9 | 1943 | |
e0001a05 NC |
1944 | input_line_pointer = arg_end; |
1945 | num_args += 1; | |
c138bc38 | 1946 | saw_comma = FALSE; |
43cd72b9 | 1947 | saw_colon = FALSE; |
c138bc38 | 1948 | saw_arg = TRUE; |
e0001a05 NC |
1949 | break; |
1950 | } | |
1951 | } | |
1952 | ||
1953 | fini: | |
43cd72b9 | 1954 | if (saw_comma || saw_colon) |
e0001a05 NC |
1955 | goto err; |
1956 | input_line_pointer = old_input_line_pointer; | |
1957 | return num_args; | |
1958 | ||
1959 | err: | |
43cd72b9 BW |
1960 | if (saw_comma) |
1961 | as_bad (_("extra comma")); | |
1962 | else if (saw_colon) | |
1963 | as_bad (_("extra colon")); | |
1964 | else if (!saw_arg) | |
c138bc38 | 1965 | as_bad (_("missing argument")); |
43cd72b9 BW |
1966 | else |
1967 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1968 | input_line_pointer = old_input_line_pointer; |
1969 | return -1; | |
1970 | } | |
1971 | ||
1972 | ||
43cd72b9 | 1973 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1974 | |
1975 | static bfd_boolean | |
7fa3d080 | 1976 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1977 | { |
43cd72b9 | 1978 | expressionS *tok, *last_tok; |
e0001a05 NC |
1979 | xtensa_opcode opcode = insn->opcode; |
1980 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1981 | xtensa_isa isa = xtensa_default_isa; |
1982 | int n, num_regs = 0; | |
e0001a05 | 1983 | int opcode_operand_count; |
43cd72b9 BW |
1984 | int opnd_cnt, last_opnd_cnt; |
1985 | unsigned int next_reg = 0; | |
e0001a05 NC |
1986 | char *old_input_line_pointer; |
1987 | ||
1988 | if (insn->insn_type == ITYPE_LITERAL) | |
1989 | opcode_operand_count = 1; | |
1990 | else | |
43cd72b9 | 1991 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1992 | |
43cd72b9 | 1993 | tok = insn->tok; |
e0001a05 NC |
1994 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1995 | ||
1996 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1997 | old_input_line_pointer = input_line_pointer; |
1998 | ||
1999 | last_tok = 0; | |
2000 | last_opnd_cnt = -1; | |
2001 | opnd_cnt = 0; | |
2002 | ||
2003 | /* Skip invisible operands. */ | |
2004 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2005 | { | |
2006 | opnd_cnt += 1; | |
2007 | tok++; | |
2008 | } | |
e0001a05 NC |
2009 | |
2010 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2011 | { |
e0001a05 | 2012 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2013 | if (*input_line_pointer == ':') |
2014 | { | |
2015 | xtensa_regfile opnd_rf; | |
2016 | input_line_pointer++; | |
2017 | if (num_regs == 0) | |
2018 | goto err; | |
9c2799c2 | 2019 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2020 | num_regs--; |
2021 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2022 | if (next_reg | |
2023 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2024 | as_warn (_("incorrect register number, ignoring")); | |
2025 | next_reg++; | |
2026 | } | |
2027 | else | |
2028 | { | |
2029 | if (opnd_cnt >= opcode_operand_count) | |
2030 | { | |
2031 | as_warn (_("too many arguments")); | |
2032 | goto err; | |
2033 | } | |
9c2799c2 | 2034 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2035 | |
2036 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2037 | next_reg = tok->X_add_number + 1; | |
2038 | ||
2039 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2040 | goto err; | |
2041 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2042 | { | |
2043 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2044 | /* minus 1 because we are seeing one right now */ | |
2045 | } | |
2046 | else | |
2047 | num_regs = 0; | |
e0001a05 | 2048 | |
43cd72b9 BW |
2049 | last_tok = tok; |
2050 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2051 | demand_empty_rest_of_line (); |
e0001a05 | 2052 | |
43cd72b9 BW |
2053 | do |
2054 | { | |
2055 | opnd_cnt += 1; | |
2056 | tok++; | |
2057 | } | |
2058 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2059 | } | |
2060 | } | |
e0001a05 | 2061 | |
43cd72b9 BW |
2062 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2063 | goto err; | |
e0001a05 NC |
2064 | |
2065 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2066 | had_error = FALSE; |
e0001a05 NC |
2067 | |
2068 | err: | |
43cd72b9 | 2069 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2070 | return had_error; |
2071 | } | |
2072 | ||
2073 | ||
43cd72b9 | 2074 | static int |
7fa3d080 | 2075 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2076 | { |
2077 | xtensa_isa isa = xtensa_default_isa; | |
2078 | static xtensa_insnbuf slotbuf = NULL; | |
2079 | xtensa_format fmt; | |
2080 | xtensa_opcode opc = insn->opcode; | |
2081 | int slot, opnd, fmt_found; | |
2082 | unsigned val; | |
2083 | ||
2084 | if (!slotbuf) | |
2085 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2086 | ||
2087 | /* Find format/slot where this can be encoded. */ | |
2088 | fmt_found = 0; | |
2089 | slot = 0; | |
2090 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2091 | { | |
2092 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2093 | { | |
2094 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2095 | { | |
2096 | fmt_found = 1; | |
2097 | break; | |
2098 | } | |
2099 | } | |
2100 | if (fmt_found) break; | |
2101 | } | |
2102 | ||
2103 | if (!fmt_found) | |
2104 | { | |
2105 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2106 | return -1; | |
2107 | } | |
2108 | ||
2109 | /* First encode all the visible operands | |
2110 | (to deal with shared field operands). */ | |
2111 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2112 | { | |
2113 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2114 | && (insn->tok[opnd].X_op == O_register | |
2115 | || insn->tok[opnd].X_op == O_constant)) | |
2116 | { | |
2117 | val = insn->tok[opnd].X_add_number; | |
2118 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2119 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2120 | } | |
2121 | } | |
2122 | ||
2123 | /* Then pull out the values for the invisible ones. */ | |
2124 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2125 | { | |
2126 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2127 | { | |
2128 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2129 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2130 | insn->tok[opnd].X_add_number = val; | |
2131 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2132 | insn->tok[opnd].X_op = O_register; | |
2133 | else | |
2134 | insn->tok[opnd].X_op = O_constant; | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
2141 | ||
e0001a05 | 2142 | static void |
7fa3d080 | 2143 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2144 | { |
2145 | char *cnt_arg, *new_arg; | |
2146 | cnt_arg = *cnt_argp; | |
2147 | ||
2148 | /* replace the argument with "31-(argument)" */ | |
2149 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2150 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2151 | ||
2152 | free (cnt_arg); | |
2153 | *cnt_argp = new_arg; | |
2154 | } | |
2155 | ||
2156 | ||
2157 | /* If "arg" is a constant expression, return non-zero with the value | |
2158 | in *valp. */ | |
2159 | ||
2160 | static int | |
7fa3d080 | 2161 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2162 | { |
2163 | expressionS exp; | |
2164 | char *save_ptr = input_line_pointer; | |
2165 | ||
2166 | input_line_pointer = arg; | |
2167 | expression (&exp); | |
2168 | input_line_pointer = save_ptr; | |
2169 | ||
2170 | if (exp.X_op == O_constant) | |
2171 | { | |
2172 | *valp = exp.X_add_number; | |
2173 | return 1; | |
2174 | } | |
2175 | ||
2176 | return 0; | |
2177 | } | |
2178 | ||
2179 | ||
2180 | static void | |
7fa3d080 | 2181 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2182 | { |
2183 | free (*popname); | |
2184 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2185 | strcpy (*popname, newop); | |
2186 | } | |
2187 | ||
2188 | ||
2189 | static int | |
7fa3d080 BW |
2190 | xg_check_num_args (int *pnum_args, |
2191 | int expected_num, | |
2192 | char *opname, | |
2193 | char **arg_strings) | |
e0001a05 NC |
2194 | { |
2195 | int num_args = *pnum_args; | |
2196 | ||
43cd72b9 | 2197 | if (num_args < expected_num) |
e0001a05 NC |
2198 | { |
2199 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2200 | num_args, opname, expected_num); | |
2201 | return -1; | |
2202 | } | |
2203 | ||
2204 | if (num_args > expected_num) | |
2205 | { | |
2206 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2207 | num_args, opname, expected_num); | |
2208 | while (num_args-- > expected_num) | |
2209 | { | |
2210 | free (arg_strings[num_args]); | |
2211 | arg_strings[num_args] = 0; | |
2212 | } | |
2213 | *pnum_args = expected_num; | |
2214 | return -1; | |
2215 | } | |
2216 | ||
2217 | return 0; | |
2218 | } | |
2219 | ||
2220 | ||
43cd72b9 BW |
2221 | /* If the register is not specified as part of the opcode, |
2222 | then get it from the operand and move it to the opcode. */ | |
2223 | ||
e0001a05 | 2224 | static int |
7fa3d080 | 2225 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2226 | { |
43cd72b9 BW |
2227 | xtensa_isa isa = xtensa_default_isa; |
2228 | xtensa_sysreg sr; | |
e0001a05 | 2229 | char *opname, *new_opname; |
43cd72b9 BW |
2230 | const char *sr_name; |
2231 | int is_user, is_write; | |
e0001a05 NC |
2232 | |
2233 | opname = *popname; | |
2234 | if (*opname == '_') | |
80ca4e2c | 2235 | opname += 1; |
43cd72b9 BW |
2236 | is_user = (opname[1] == 'u'); |
2237 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2238 | |
43cd72b9 | 2239 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2240 | |
43cd72b9 BW |
2241 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2242 | return -1; | |
e0001a05 | 2243 | |
43cd72b9 BW |
2244 | /* Check if the argument is a symbolic register name. */ |
2245 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2246 | /* Handle WSR to "INTSET" as a special case. */ | |
2247 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2248 | && !strcasecmp (arg_strings[1], "intset")) | |
2249 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2250 | if (sr == XTENSA_UNDEFINED | |
2251 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2252 | { | |
2253 | /* Maybe it's a register number.... */ | |
2254 | offsetT val; | |
e0001a05 NC |
2255 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2256 | { | |
43cd72b9 BW |
2257 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2258 | arg_strings[1], opname); | |
e0001a05 NC |
2259 | return -1; |
2260 | } | |
43cd72b9 BW |
2261 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2262 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2263 | { |
43cd72b9 | 2264 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2265 | (long) val, opname); |
e0001a05 NC |
2266 | return -1; |
2267 | } | |
43cd72b9 | 2268 | } |
e0001a05 | 2269 | |
43cd72b9 BW |
2270 | /* Remove the last argument, which is now part of the opcode. */ |
2271 | free (arg_strings[1]); | |
2272 | arg_strings[1] = 0; | |
2273 | *pnum_args = 1; | |
2274 | ||
2275 | /* Translate the opcode. */ | |
2276 | sr_name = xtensa_sysreg_name (isa, sr); | |
2277 | /* Another special case for "WSR.INTSET".... */ | |
2278 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2279 | sr_name = "intset"; | |
2280 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2281 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2282 | free (*popname); |
2283 | *popname = new_opname; | |
2284 | ||
2285 | return 0; | |
2286 | } | |
2287 | ||
2288 | ||
2289 | static int | |
7fa3d080 | 2290 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2291 | { |
2292 | xtensa_isa isa = xtensa_default_isa; | |
2293 | xtensa_sysreg sr; | |
2294 | char *opname, *new_opname; | |
2295 | const char *sr_name; | |
2296 | bfd_boolean has_underbar = FALSE; | |
2297 | ||
2298 | opname = *popname; | |
2299 | if (opname[0] == '_') | |
2300 | { | |
2301 | has_underbar = TRUE; | |
2302 | opname += 1; | |
2303 | } | |
2304 | ||
2305 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2306 | if (sr != XTENSA_UNDEFINED) | |
2307 | { | |
2308 | /* The new default name ("nnn") is different from the old default | |
2309 | name ("URnnn"). The old default is handled below, and we don't | |
2310 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2311 | default. */ | |
2312 | static char namebuf[10]; | |
2313 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2314 | if (strcmp (namebuf, opname + 1) == 0) | |
2315 | return 0; | |
2316 | } | |
2317 | else | |
2318 | { | |
2319 | offsetT val; | |
2320 | char *end; | |
2321 | ||
2322 | /* Only continue if the reg name is "URnnn". */ | |
2323 | if (opname[1] != 'u' || opname[2] != 'r') | |
2324 | return 0; | |
2325 | val = strtoul (opname + 3, &end, 10); | |
2326 | if (*end != '\0') | |
2327 | return 0; | |
2328 | ||
2329 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2330 | if (sr == XTENSA_UNDEFINED) | |
2331 | { | |
2332 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2333 | (long) val, opname); |
43cd72b9 BW |
2334 | return -1; |
2335 | } | |
2336 | } | |
2337 | ||
2338 | /* Translate the opcode. */ | |
2339 | sr_name = xtensa_sysreg_name (isa, sr); | |
2340 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2341 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2342 | opname[0], sr_name); | |
2343 | free (*popname); | |
2344 | *popname = new_opname; | |
2345 | ||
2346 | return 0; | |
2347 | } | |
2348 | ||
2349 | ||
2350 | static int | |
7fa3d080 BW |
2351 | xtensa_translate_zero_immed (char *old_op, |
2352 | char *new_op, | |
2353 | char **popname, | |
2354 | int *pnum_args, | |
2355 | char **arg_strings) | |
43cd72b9 BW |
2356 | { |
2357 | char *opname; | |
2358 | offsetT val; | |
2359 | ||
2360 | opname = *popname; | |
9c2799c2 | 2361 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2362 | |
2363 | if (strcmp (opname, old_op) != 0) | |
2364 | return 0; | |
e0001a05 | 2365 | |
43cd72b9 BW |
2366 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2367 | return -1; | |
2368 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2369 | { | |
2370 | xg_replace_opname (popname, new_op); | |
2371 | free (arg_strings[1]); | |
2372 | arg_strings[1] = arg_strings[2]; | |
2373 | arg_strings[2] = 0; | |
2374 | *pnum_args = 2; | |
e0001a05 NC |
2375 | } |
2376 | ||
2377 | return 0; | |
2378 | } | |
2379 | ||
2380 | ||
2381 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2382 | Returns non-zero if an error was found. */ | |
2383 | ||
2384 | static int | |
7fa3d080 | 2385 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2386 | { |
2387 | char *opname = *popname; | |
2388 | bfd_boolean has_underbar = FALSE; | |
2389 | ||
2390 | if (*opname == '_') | |
2391 | { | |
2392 | has_underbar = TRUE; | |
2393 | opname += 1; | |
2394 | } | |
2395 | ||
2396 | if (strcmp (opname, "mov") == 0) | |
2397 | { | |
43cd72b9 | 2398 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2399 | xg_replace_opname (popname, "mov.n"); |
2400 | else | |
2401 | { | |
2402 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2403 | return -1; | |
2404 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2405 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2406 | strcpy (arg_strings[2], arg_strings[1]); | |
2407 | *pnum_args = 3; | |
2408 | } | |
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | if (strcmp (opname, "bbsi.l") == 0) | |
2413 | { | |
2414 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2415 | return -1; | |
2416 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2417 | if (target_big_endian) | |
2418 | xg_reverse_shift_count (&arg_strings[1]); | |
2419 | return 0; | |
2420 | } | |
2421 | ||
2422 | if (strcmp (opname, "bbci.l") == 0) | |
2423 | { | |
2424 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2425 | return -1; | |
2426 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2427 | if (target_big_endian) | |
2428 | xg_reverse_shift_count (&arg_strings[1]); | |
2429 | return 0; | |
2430 | } | |
2431 | ||
eb6d9dce BW |
2432 | /* Don't do anything special with NOPs inside FLIX instructions. They |
2433 | are handled elsewhere. Real NOP instructions are always available | |
2434 | in configurations with FLIX, so this should never be an issue but | |
2435 | check for it anyway. */ | |
2436 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2437 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2438 | { |
43cd72b9 | 2439 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2440 | xg_replace_opname (popname, "nop.n"); |
2441 | else | |
2442 | { | |
2443 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2444 | return -1; | |
2445 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2446 | arg_strings[0] = (char *) xmalloc (3); | |
2447 | arg_strings[1] = (char *) xmalloc (3); | |
2448 | arg_strings[2] = (char *) xmalloc (3); | |
2449 | strcpy (arg_strings[0], "a1"); | |
2450 | strcpy (arg_strings[1], "a1"); | |
2451 | strcpy (arg_strings[2], "a1"); | |
2452 | *pnum_args = 3; | |
2453 | } | |
2454 | return 0; | |
2455 | } | |
2456 | ||
43cd72b9 BW |
2457 | /* Recognize [RW]UR and [RWX]SR. */ |
2458 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2459 | && (opname[1] == 'u' || opname[1] == 's')) | |
2460 | || (opname[0] == 'x' && opname[1] == 's')) | |
2461 | && opname[2] == 'r' | |
2462 | && opname[3] == '\0') | |
e0001a05 NC |
2463 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2464 | ||
43cd72b9 BW |
2465 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2466 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2467 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2468 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2469 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2470 | |
43cd72b9 BW |
2471 | /* Relax branches that don't allow comparisons against an immediate value |
2472 | of zero to the corresponding branches with implicit zero immediates. */ | |
2473 | if (!has_underbar && use_transform ()) | |
2474 | { | |
2475 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2476 | pnum_args, arg_strings)) | |
2477 | return -1; | |
e0001a05 | 2478 | |
43cd72b9 BW |
2479 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2480 | pnum_args, arg_strings)) | |
2481 | return -1; | |
e0001a05 | 2482 | |
43cd72b9 BW |
2483 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2484 | pnum_args, arg_strings)) | |
2485 | return -1; | |
e0001a05 | 2486 | |
43cd72b9 BW |
2487 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2488 | pnum_args, arg_strings)) | |
2489 | return -1; | |
2490 | } | |
e0001a05 | 2491 | |
43cd72b9 BW |
2492 | return 0; |
2493 | } | |
e0001a05 | 2494 | |
43cd72b9 BW |
2495 | \f |
2496 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2497 | |
43cd72b9 BW |
2498 | /* Currently the assembler only allows us to use a single target per |
2499 | fragment. Because of this, only one operand for a given | |
2500 | instruction may be symbolic. If there is a PC-relative operand, | |
2501 | the last one is chosen. Otherwise, the result is the number of the | |
2502 | last immediate operand, and if there are none of those, we fail and | |
2503 | return -1. */ | |
e0001a05 | 2504 | |
7fa3d080 BW |
2505 | static int |
2506 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2507 | { |
2508 | int last_immed = -1; | |
2509 | int noperands, opi; | |
e0001a05 | 2510 | |
43cd72b9 BW |
2511 | if (opcode == XTENSA_UNDEFINED) |
2512 | return -1; | |
e0001a05 | 2513 | |
43cd72b9 BW |
2514 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2515 | for (opi = noperands - 1; opi >= 0; opi--) | |
2516 | { | |
2517 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2518 | continue; | |
2519 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2520 | return opi; | |
2521 | if (last_immed == -1 | |
2522 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2523 | last_immed = opi; | |
e0001a05 | 2524 | } |
43cd72b9 | 2525 | return last_immed; |
e0001a05 NC |
2526 | } |
2527 | ||
e0001a05 | 2528 | |
43cd72b9 | 2529 | static xtensa_opcode |
7fa3d080 | 2530 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2531 | { |
43cd72b9 BW |
2532 | static xtensa_insnbuf insnbuf = NULL; |
2533 | static xtensa_insnbuf slotbuf = NULL; | |
2534 | xtensa_isa isa = xtensa_default_isa; | |
2535 | xtensa_format fmt; | |
2536 | ||
2537 | if (!insnbuf) | |
e0001a05 | 2538 | { |
43cd72b9 BW |
2539 | insnbuf = xtensa_insnbuf_alloc (isa); |
2540 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2541 | } |
e0001a05 | 2542 | |
d77b99c9 | 2543 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2544 | fmt = xtensa_format_decode (isa, insnbuf); |
2545 | if (fmt == XTENSA_UNDEFINED) | |
2546 | return XTENSA_UNDEFINED; | |
e0001a05 | 2547 | |
43cd72b9 BW |
2548 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2549 | return XTENSA_UNDEFINED; | |
e0001a05 | 2550 | |
43cd72b9 BW |
2551 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2552 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2553 | } |
2554 | ||
2555 | ||
43cd72b9 | 2556 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2557 | |
43cd72b9 | 2558 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2559 | |
7fa3d080 BW |
2560 | static void |
2561 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2562 | { |
2563 | int num_opcodes, num_operands; | |
2564 | xtensa_opcode opcode; | |
2565 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2566 | |
43cd72b9 BW |
2567 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2568 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2569 | { |
43cd72b9 BW |
2570 | int opn; |
2571 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2572 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2573 | for (opn = 0; opn < num_operands; opn++) | |
2574 | { | |
2575 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2576 | continue; | |
2577 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2578 | { | |
2579 | xtensa_regfile opnd_rf = | |
2580 | xtensa_operand_regfile (isa, opcode, opn); | |
2581 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2582 | } | |
2583 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2584 | fputs ("[lLr] ", stderr); | |
2585 | else | |
2586 | fputs ("i ", stderr); | |
2587 | } | |
2588 | fprintf (stderr, "\n"); | |
e0001a05 | 2589 | } |
e0001a05 NC |
2590 | } |
2591 | ||
2592 | ||
43cd72b9 | 2593 | static void |
7fa3d080 | 2594 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2595 | { |
e0001a05 | 2596 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2597 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2598 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2599 | int op; | |
e0001a05 | 2600 | |
43cd72b9 | 2601 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2602 | |
43cd72b9 BW |
2603 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2604 | { | |
2605 | xtensa_opcode opcode; | |
2606 | const char *opname; | |
2607 | int operands; | |
2608 | ||
2609 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2610 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2611 | opname = xtensa_opcode_name (isa, opcode); | |
2612 | ||
2613 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2614 | fprintf (stderr, " operands = "); | |
2615 | for (operands = 0; | |
2616 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2617 | operands++) | |
2618 | { | |
2619 | unsigned int val; | |
2620 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2621 | continue; | |
2622 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2623 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2624 | fprintf (stderr, "%d ", val); | |
2625 | } | |
2626 | fprintf (stderr, "\n"); | |
2627 | } | |
2628 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2629 | } |
2630 | ||
43cd72b9 BW |
2631 | #endif /* TENSILICA_DEBUG */ |
2632 | ||
e0001a05 NC |
2633 | |
2634 | static bfd_boolean | |
7fa3d080 | 2635 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2636 | { |
43cd72b9 BW |
2637 | xtensa_isa isa = xtensa_default_isa; |
2638 | int n, num_operands; | |
e0001a05 | 2639 | |
64b607e6 | 2640 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2641 | return FALSE; |
2642 | ||
43cd72b9 BW |
2643 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2644 | for (n = 0; n < num_operands; n++) | |
2645 | { | |
2646 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2647 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2648 | return TRUE; | |
2649 | } | |
2650 | return FALSE; | |
e0001a05 NC |
2651 | } |
2652 | ||
2653 | ||
43cd72b9 BW |
2654 | /* Convert from BFD relocation type code to slot and operand number. |
2655 | Returns non-zero on failure. */ | |
e0001a05 | 2656 | |
43cd72b9 | 2657 | static int |
7fa3d080 | 2658 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2659 | { |
43cd72b9 BW |
2660 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2661 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2662 | { |
43cd72b9 BW |
2663 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2664 | *is_alt = FALSE; | |
e0001a05 | 2665 | } |
43cd72b9 BW |
2666 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2667 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2668 | { |
43cd72b9 BW |
2669 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2670 | *is_alt = TRUE; | |
e0001a05 | 2671 | } |
43cd72b9 BW |
2672 | else |
2673 | return -1; | |
2674 | ||
2675 | return 0; | |
e0001a05 NC |
2676 | } |
2677 | ||
2678 | ||
43cd72b9 BW |
2679 | /* Convert from slot number to BFD relocation type code for the |
2680 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2681 | failure. */ | |
e0001a05 | 2682 | |
43cd72b9 | 2683 | static bfd_reloc_code_real_type |
7fa3d080 | 2684 | encode_reloc (int slot) |
e0001a05 | 2685 | { |
43cd72b9 BW |
2686 | if (slot < 0 || slot > 14) |
2687 | return BFD_RELOC_NONE; | |
2688 | ||
2689 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2690 | } |
2691 | ||
2692 | ||
43cd72b9 BW |
2693 | /* Convert from slot numbers to BFD relocation type code for the |
2694 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2695 | |
43cd72b9 | 2696 | static bfd_reloc_code_real_type |
7fa3d080 | 2697 | encode_alt_reloc (int slot) |
e0001a05 | 2698 | { |
43cd72b9 BW |
2699 | if (slot < 0 || slot > 14) |
2700 | return BFD_RELOC_NONE; | |
2701 | ||
2702 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2703 | } |
2704 | ||
2705 | ||
2706 | static void | |
7fa3d080 BW |
2707 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2708 | xtensa_format fmt, | |
2709 | int slot, | |
2710 | xtensa_opcode opcode, | |
2711 | int operand, | |
2712 | uint32 value, | |
2713 | const char *file, | |
2714 | unsigned int line) | |
e0001a05 | 2715 | { |
e0001a05 NC |
2716 | uint32 valbuf = value; |
2717 | ||
43cd72b9 | 2718 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2719 | { |
43cd72b9 BW |
2720 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2721 | == 1) | |
2722 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2723 | _("operand %d of '%s' has out of range value '%u'"), |
2724 | operand + 1, | |
2725 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2726 | value); | |
43cd72b9 BW |
2727 | else |
2728 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2729 | _("operand %d of '%s' has invalid value '%u'"), |
2730 | operand + 1, | |
2731 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2732 | value); | |
43cd72b9 | 2733 | return; |
e0001a05 NC |
2734 | } |
2735 | ||
43cd72b9 BW |
2736 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2737 | slotbuf, valbuf); | |
e0001a05 NC |
2738 | } |
2739 | ||
2740 | ||
2741 | static uint32 | |
7fa3d080 BW |
2742 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2743 | xtensa_format fmt, | |
2744 | int slot, | |
2745 | xtensa_opcode opcode, | |
2746 | int opnum) | |
e0001a05 | 2747 | { |
43cd72b9 BW |
2748 | uint32 val = 0; |
2749 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2750 | fmt, slot, slotbuf, &val); | |
2751 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2752 | return val; | |
e0001a05 NC |
2753 | } |
2754 | ||
e0001a05 | 2755 | \f |
7fa3d080 | 2756 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2757 | |
7fa3d080 BW |
2758 | /* The routine xg_instruction_matches_option_term must return TRUE |
2759 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2760 | terms is given interpretation by this function. */ |
e0001a05 | 2761 | |
7fa3d080 | 2762 | static bfd_boolean |
19e8f41a | 2763 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2764 | { |
7fa3d080 BW |
2765 | if (strcmp (option->option_name, "realnop") == 0 |
2766 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2767 | { | |
2768 | /* These conditions were evaluated statically when building the | |
2769 | relaxation table. There's no need to reevaluate them now. */ | |
2770 | return TRUE; | |
2771 | } | |
19e8f41a BW |
2772 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2773 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2774 | else |
2775 | { | |
2776 | as_fatal (_("internal error: unknown option name '%s'"), | |
2777 | option->option_name); | |
2778 | } | |
e0001a05 NC |
2779 | } |
2780 | ||
2781 | ||
7fa3d080 BW |
2782 | static bfd_boolean |
2783 | xg_instruction_matches_or_options (TInsn *insn, | |
2784 | const ReqOrOptionList *or_option) | |
e0001a05 | 2785 | { |
7fa3d080 BW |
2786 | const ReqOrOption *option; |
2787 | /* Must match each of the AND terms. */ | |
2788 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2789 | { |
7fa3d080 BW |
2790 | if (xg_instruction_matches_option_term (insn, option)) |
2791 | return TRUE; | |
e0001a05 | 2792 | } |
7fa3d080 | 2793 | return FALSE; |
e0001a05 NC |
2794 | } |
2795 | ||
2796 | ||
7fa3d080 BW |
2797 | static bfd_boolean |
2798 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2799 | { |
7fa3d080 BW |
2800 | const ReqOption *req_options; |
2801 | /* Must match each of the AND terms. */ | |
2802 | for (req_options = options; | |
2803 | req_options != NULL; | |
2804 | req_options = req_options->next) | |
e0001a05 | 2805 | { |
7fa3d080 BW |
2806 | /* Must match one of the OR clauses. */ |
2807 | if (!xg_instruction_matches_or_options (insn, | |
2808 | req_options->or_option_terms)) | |
2809 | return FALSE; | |
e0001a05 | 2810 | } |
7fa3d080 | 2811 | return TRUE; |
e0001a05 NC |
2812 | } |
2813 | ||
2814 | ||
7fa3d080 | 2815 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2816 | |
7fa3d080 BW |
2817 | static bfd_boolean |
2818 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2819 | { |
7fa3d080 | 2820 | PreconditionList *condition_l; |
e0001a05 | 2821 | |
7fa3d080 BW |
2822 | if (rule->opcode != insn->opcode) |
2823 | return FALSE; | |
e0001a05 | 2824 | |
7fa3d080 BW |
2825 | for (condition_l = rule->conditions; |
2826 | condition_l != NULL; | |
2827 | condition_l = condition_l->next) | |
e0001a05 | 2828 | { |
7fa3d080 BW |
2829 | expressionS *exp1; |
2830 | expressionS *exp2; | |
2831 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2832 | |
7fa3d080 | 2833 | switch (cond->typ) |
e0001a05 | 2834 | { |
7fa3d080 BW |
2835 | case OP_CONSTANT: |
2836 | /* The expression must be the constant. */ | |
9c2799c2 | 2837 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2838 | exp1 = &insn->tok[cond->op_num]; |
2839 | if (expr_is_const (exp1)) | |
2840 | { | |
2841 | switch (cond->cmp) | |
2842 | { | |
2843 | case OP_EQUAL: | |
2844 | if (get_expr_const (exp1) != cond->op_data) | |
2845 | return FALSE; | |
2846 | break; | |
2847 | case OP_NOTEQUAL: | |
2848 | if (get_expr_const (exp1) == cond->op_data) | |
2849 | return FALSE; | |
2850 | break; | |
2851 | default: | |
2852 | return FALSE; | |
2853 | } | |
2854 | } | |
2855 | else if (expr_is_register (exp1)) | |
2856 | { | |
2857 | switch (cond->cmp) | |
2858 | { | |
2859 | case OP_EQUAL: | |
2860 | if (get_expr_register (exp1) != cond->op_data) | |
2861 | return FALSE; | |
2862 | break; | |
2863 | case OP_NOTEQUAL: | |
2864 | if (get_expr_register (exp1) == cond->op_data) | |
2865 | return FALSE; | |
2866 | break; | |
2867 | default: | |
2868 | return FALSE; | |
2869 | } | |
2870 | } | |
2871 | else | |
2872 | return FALSE; | |
2873 | break; | |
2874 | ||
2875 | case OP_OPERAND: | |
9c2799c2 NC |
2876 | gas_assert (cond->op_num < insn->ntok); |
2877 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
2878 | exp1 = &insn->tok[cond->op_num]; |
2879 | exp2 = &insn->tok[cond->op_data]; | |
2880 | ||
2881 | switch (cond->cmp) | |
2882 | { | |
2883 | case OP_EQUAL: | |
2884 | if (!expr_is_equal (exp1, exp2)) | |
2885 | return FALSE; | |
2886 | break; | |
2887 | case OP_NOTEQUAL: | |
2888 | if (expr_is_equal (exp1, exp2)) | |
2889 | return FALSE; | |
2890 | break; | |
2891 | } | |
2892 | break; | |
2893 | ||
2894 | case OP_LITERAL: | |
2895 | case OP_LABEL: | |
2896 | default: | |
2897 | return FALSE; | |
2898 | } | |
2899 | } | |
2900 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2901 | return FALSE; | |
2902 | ||
2903 | return TRUE; | |
2904 | } | |
2905 | ||
2906 | ||
2907 | static int | |
2908 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2909 | { | |
2910 | bfd_boolean a_greater = FALSE; | |
2911 | bfd_boolean b_greater = FALSE; | |
2912 | ||
2913 | ReqOptionList *l_a = a->options; | |
2914 | ReqOptionList *l_b = b->options; | |
2915 | ||
2916 | /* We only care if they both are the same except for | |
2917 | a const16 vs. an l32r. */ | |
2918 | ||
2919 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2920 | { | |
2921 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2922 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2923 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2924 | { | |
2925 | if (l_or_a->is_true != l_or_b->is_true) | |
2926 | return 0; | |
2927 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2928 | { | |
2929 | /* This is the case we care about. */ | |
2930 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2931 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2932 | { | |
2933 | if (prefer_const16) | |
2934 | a_greater = TRUE; | |
2935 | else | |
2936 | b_greater = TRUE; | |
2937 | } | |
2938 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2939 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2940 | { | |
2941 | if (prefer_const16) | |
2942 | b_greater = TRUE; | |
2943 | else | |
2944 | a_greater = TRUE; | |
2945 | } | |
2946 | else | |
2947 | return 0; | |
2948 | } | |
2949 | l_or_a = l_or_a->next; | |
2950 | l_or_b = l_or_b->next; | |
2951 | } | |
2952 | if (l_or_a || l_or_b) | |
2953 | return 0; | |
2954 | ||
2955 | l_a = l_a->next; | |
2956 | l_b = l_b->next; | |
2957 | } | |
2958 | if (l_a || l_b) | |
2959 | return 0; | |
2960 | ||
2961 | /* Incomparable if the substitution was used differently in two cases. */ | |
2962 | if (a_greater && b_greater) | |
2963 | return 0; | |
2964 | ||
2965 | if (b_greater) | |
2966 | return 1; | |
2967 | if (a_greater) | |
2968 | return -1; | |
2969 | ||
2970 | return 0; | |
2971 | } | |
2972 | ||
2973 | ||
2974 | static TransitionRule * | |
2975 | xg_instruction_match (TInsn *insn) | |
2976 | { | |
2977 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2978 | TransitionList *l; | |
9c2799c2 | 2979 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
2980 | |
2981 | /* Walk through all of the possible transitions. */ | |
2982 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2983 | { | |
2984 | TransitionRule *rule = l->rule; | |
2985 | if (xg_instruction_matches_rule (insn, rule)) | |
2986 | return rule; | |
2987 | } | |
2988 | return NULL; | |
2989 | } | |
2990 | ||
2991 | \f | |
2992 | /* Various Other Internal Functions. */ | |
2993 | ||
2994 | static bfd_boolean | |
2995 | is_unique_insn_expansion (TransitionRule *r) | |
2996 | { | |
2997 | if (!r->to_instr || r->to_instr->next != NULL) | |
2998 | return FALSE; | |
2999 | if (r->to_instr->typ != INSTR_INSTR) | |
3000 | return FALSE; | |
3001 | return TRUE; | |
3002 | } | |
3003 | ||
3004 | ||
84b08ed9 BW |
3005 | /* Check if there is exactly one relaxation for INSN that converts it to |
3006 | another instruction of equal or larger size. If so, and if TARG is | |
3007 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3008 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3009 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3010 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3011 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3012 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3013 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3014 | |
84b08ed9 BW |
3015 | bfd_boolean |
3016 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
3017 | { |
3018 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3019 | TransitionList *l; | |
84b08ed9 | 3020 | TransitionRule *match = 0; |
7fa3d080 | 3021 | |
9c2799c2 NC |
3022 | gas_assert (insn->insn_type == ITYPE_INSN); |
3023 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3024 | |
3025 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3026 | { | |
3027 | TransitionRule *rule = l->rule; | |
3028 | ||
3029 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3030 | && is_unique_insn_expansion (rule) |
3031 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3032 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3033 | { |
84b08ed9 BW |
3034 | if (match) |
3035 | return FALSE; | |
3036 | match = rule; | |
7fa3d080 BW |
3037 | } |
3038 | } | |
84b08ed9 BW |
3039 | if (!match) |
3040 | return FALSE; | |
3041 | ||
3042 | if (targ) | |
3043 | xg_build_to_insn (targ, insn, match->to_instr); | |
3044 | return TRUE; | |
7fa3d080 BW |
3045 | } |
3046 | ||
3047 | ||
3048 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3049 | ||
3050 | static int | |
3051 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3052 | { | |
3053 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3054 | TransitionList *l; | |
3055 | int max_size = xg_get_single_size (opcode); | |
3056 | ||
9c2799c2 | 3057 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3058 | |
3059 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3060 | { | |
3061 | TransitionRule *rule = l->rule; | |
3062 | BuildInstr *build_list; | |
3063 | int this_size = 0; | |
3064 | ||
3065 | if (!rule) | |
3066 | continue; | |
3067 | build_list = rule->to_instr; | |
3068 | if (is_unique_insn_expansion (rule)) | |
3069 | { | |
9c2799c2 | 3070 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3071 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3072 | } | |
3073 | else | |
3074 | for (; build_list != NULL; build_list = build_list->next) | |
3075 | { | |
3076 | switch (build_list->typ) | |
3077 | { | |
3078 | case INSTR_INSTR: | |
3079 | this_size += xg_get_single_size (build_list->opcode); | |
3080 | break; | |
3081 | case INSTR_LITERAL_DEF: | |
3082 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3083 | default: |
3084 | break; | |
3085 | } | |
3086 | } | |
3087 | if (this_size > max_size) | |
3088 | max_size = this_size; | |
3089 | } | |
3090 | return max_size; | |
3091 | } | |
3092 | ||
3093 | ||
3094 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3095 | ||
7fa3d080 BW |
3096 | static int |
3097 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3098 | { |
43cd72b9 | 3099 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3100 | TransitionList *l; |
3101 | int max_size = 0; | |
3102 | ||
9c2799c2 | 3103 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3104 | |
3105 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3106 | { | |
3107 | TransitionRule *rule = l->rule; | |
3108 | BuildInstr *build_list; | |
3109 | int this_size = 0; | |
3110 | ||
3111 | if (!rule) | |
3112 | continue; | |
3113 | build_list = rule->to_instr; | |
3114 | if (is_unique_insn_expansion (rule)) | |
3115 | { | |
9c2799c2 | 3116 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3117 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3118 | } | |
3119 | else | |
3120 | for (; build_list != NULL; build_list = build_list->next) | |
3121 | { | |
3122 | switch (build_list->typ) | |
3123 | { | |
3124 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3125 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3126 | this_size += 4; |
3127 | break; | |
3128 | case INSTR_INSTR: | |
3129 | case INSTR_LABEL_DEF: | |
3130 | default: | |
3131 | break; | |
3132 | } | |
3133 | } | |
3134 | if (this_size > max_size) | |
3135 | max_size = this_size; | |
3136 | } | |
3137 | return max_size; | |
3138 | } | |
3139 | ||
3140 | ||
7fa3d080 BW |
3141 | static bfd_boolean |
3142 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3143 | { | |
3144 | int steps_taken = 0; | |
3145 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3146 | TransitionList *l; | |
3147 | ||
9c2799c2 NC |
3148 | gas_assert (insn->insn_type == ITYPE_INSN); |
3149 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3150 | |
3151 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3152 | { | |
3153 | TransitionRule *rule = l->rule; | |
3154 | ||
3155 | if (xg_instruction_matches_rule (insn, rule)) | |
3156 | { | |
3157 | if (steps_taken == lateral_steps) | |
3158 | return TRUE; | |
3159 | steps_taken++; | |
3160 | } | |
3161 | } | |
3162 | return FALSE; | |
3163 | } | |
3164 | ||
3165 | ||
3166 | static symbolS * | |
3167 | get_special_literal_symbol (void) | |
3168 | { | |
3169 | static symbolS *sym = NULL; | |
3170 | ||
3171 | if (sym == NULL) | |
3172 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3173 | return sym; | |
3174 | } | |
3175 | ||
3176 | ||
3177 | static symbolS * | |
3178 | get_special_label_symbol (void) | |
3179 | { | |
3180 | static symbolS *sym = NULL; | |
3181 | ||
3182 | if (sym == NULL) | |
3183 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3184 | return sym; | |
3185 | } | |
3186 | ||
3187 | ||
3188 | static bfd_boolean | |
3189 | xg_valid_literal_expression (const expressionS *exp) | |
3190 | { | |
3191 | switch (exp->X_op) | |
3192 | { | |
3193 | case O_constant: | |
3194 | case O_symbol: | |
3195 | case O_big: | |
3196 | case O_uminus: | |
3197 | case O_subtract: | |
3198 | case O_pltrel: | |
1bbb5f21 | 3199 | case O_pcrel: |
28dbbc02 BW |
3200 | case O_tlsfunc: |
3201 | case O_tlsarg: | |
3202 | case O_tpoff: | |
3203 | case O_dtpoff: | |
7fa3d080 BW |
3204 | return TRUE; |
3205 | default: | |
3206 | return FALSE; | |
3207 | } | |
3208 | } | |
3209 | ||
3210 | ||
3211 | /* This will check to see if the value can be converted into the | |
3212 | operand type. It will return TRUE if it does not fit. */ | |
3213 | ||
3214 | static bfd_boolean | |
3215 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3216 | { | |
3217 | uint32 valbuf = value; | |
3218 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3219 | return TRUE; | |
3220 | return FALSE; | |
3221 | } | |
3222 | ||
3223 | ||
3224 | /* Assumes: All immeds are constants. Check that all constants fit | |
3225 | into their immeds; return FALSE if not. */ | |
3226 | ||
3227 | static bfd_boolean | |
3228 | xg_immeds_fit (const TInsn *insn) | |
3229 | { | |
3230 | xtensa_isa isa = xtensa_default_isa; | |
3231 | int i; | |
3232 | ||
3233 | int n = insn->ntok; | |
9c2799c2 | 3234 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3235 | for (i = 0; i < n; ++i) |
3236 | { | |
3237 | const expressionS *expr = &insn->tok[i]; | |
3238 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3239 | continue; | |
3240 | ||
3241 | switch (expr->X_op) | |
3242 | { | |
3243 | case O_register: | |
3244 | case O_constant: | |
3245 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3246 | return FALSE; | |
3247 | break; | |
3248 | ||
3249 | default: | |
3250 | /* The symbol should have a fixup associated with it. */ | |
9c2799c2 | 3251 | gas_assert (FALSE); |
7fa3d080 BW |
3252 | break; |
3253 | } | |
3254 | } | |
3255 | return TRUE; | |
3256 | } | |
3257 | ||
3258 | ||
3259 | /* This should only be called after we have an initial | |
3260 | estimate of the addresses. */ | |
3261 | ||
3262 | static bfd_boolean | |
3263 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3264 | segT pc_seg, | |
3265 | fragS *pc_frag, | |
3266 | offsetT pc_offset, | |
3267 | long stretch) | |
e0001a05 | 3268 | { |
7fa3d080 BW |
3269 | xtensa_isa isa = xtensa_default_isa; |
3270 | symbolS *symbolP; | |
3271 | fragS *sym_frag; | |
3272 | offsetT target, pc; | |
3273 | uint32 new_offset; | |
3274 | int i; | |
3275 | int n = insn->ntok; | |
e0001a05 | 3276 | |
9c2799c2 | 3277 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3278 | |
7fa3d080 | 3279 | for (i = 0; i < n; ++i) |
e0001a05 | 3280 | { |
7fa3d080 BW |
3281 | const expressionS *expr = &insn->tok[i]; |
3282 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3283 | continue; | |
e0001a05 | 3284 | |
7fa3d080 | 3285 | switch (expr->X_op) |
e0001a05 | 3286 | { |
7fa3d080 BW |
3287 | case O_register: |
3288 | case O_constant: | |
3289 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3290 | return FALSE; | |
3291 | break; | |
e0001a05 | 3292 | |
7fa3d080 BW |
3293 | case O_lo16: |
3294 | case O_hi16: | |
3295 | /* Check for the worst case. */ | |
3296 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3297 | return FALSE; | |
3298 | break; | |
e0001a05 | 3299 | |
7fa3d080 | 3300 | case O_symbol: |
7c834684 | 3301 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3302 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3303 | if (pc_frag == 0 |
3304 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3305 | return FALSE; |
e0001a05 | 3306 | |
8e6bc631 BW |
3307 | /* If it is a weak symbol or a symbol in a different section, |
3308 | it cannot be known to fit at assembly time. */ | |
3309 | if (S_IS_WEAK (expr->X_add_symbol) | |
3310 | || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7c834684 | 3311 | { |
8e6bc631 | 3312 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3313 | assume it will be in range. If the symbol is weak and |
3314 | undefined, it may remain undefined at link-time, in which | |
3315 | case it will have a zero value and almost certainly be out | |
3316 | of range for a direct call; thus, relax for undefined weak | |
3317 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3318 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f BW |
3319 | && ! pc_frag->tc_frag_data.use_longcalls |
3320 | && (! S_IS_WEAK (expr->X_add_symbol) | |
3321 | || S_IS_DEFINED (expr->X_add_symbol))) | |
7c834684 | 3322 | return TRUE; |
7c834684 | 3323 | |
8e6bc631 BW |
3324 | return FALSE; |
3325 | } | |
e0001a05 | 3326 | |
7fa3d080 BW |
3327 | symbolP = expr->X_add_symbol; |
3328 | sym_frag = symbol_get_frag (symbolP); | |
3329 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3330 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3331 | |
7fa3d080 BW |
3332 | /* If frag has yet to be reached on this pass, assume it |
3333 | will move by STRETCH just as we did. If this is not so, | |
3334 | it will be because some frag between grows, and that will | |
3335 | force another pass. Beware zero-length frags. There | |
3336 | should be a faster way to do this. */ | |
3337 | ||
3338 | if (stretch != 0 | |
3339 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3340 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3341 | { | |
3342 | target += stretch; | |
3343 | } | |
c138bc38 | 3344 | |
7fa3d080 BW |
3345 | new_offset = target; |
3346 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3347 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3348 | return FALSE; | |
3349 | break; | |
3350 | ||
3351 | default: | |
3352 | /* The symbol should have a fixup associated with it. */ | |
3353 | return FALSE; | |
3354 | } | |
3355 | } | |
3356 | ||
3357 | return TRUE; | |
e0001a05 NC |
3358 | } |
3359 | ||
3360 | ||
43cd72b9 | 3361 | /* Return TRUE on success. */ |
e0001a05 | 3362 | |
7fa3d080 BW |
3363 | static bfd_boolean |
3364 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3365 | { |
3366 | BuildOp *op; | |
3367 | symbolS *sym; | |
3368 | ||
60242db2 | 3369 | tinsn_init (targ); |
b224e962 BW |
3370 | targ->debug_line = insn->debug_line; |
3371 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3372 | switch (bi->typ) |
3373 | { | |
3374 | case INSTR_INSTR: | |
3375 | op = bi->ops; | |
3376 | targ->opcode = bi->opcode; | |
3377 | targ->insn_type = ITYPE_INSN; | |
3378 | targ->is_specific_opcode = FALSE; | |
3379 | ||
3380 | for (; op != NULL; op = op->next) | |
3381 | { | |
3382 | int op_num = op->op_num; | |
3383 | int op_data = op->op_data; | |
3384 | ||
9c2799c2 | 3385 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3386 | |
3387 | if (targ->ntok <= op_num) | |
3388 | targ->ntok = op_num + 1; | |
3389 | ||
3390 | switch (op->typ) | |
3391 | { | |
3392 | case OP_CONSTANT: | |
3393 | set_expr_const (&targ->tok[op_num], op_data); | |
3394 | break; | |
3395 | case OP_OPERAND: | |
9c2799c2 | 3396 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3397 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3398 | break; | |
19e8f41a BW |
3399 | case OP_FREEREG: |
3400 | if (insn->extra_arg.X_op != O_register) | |
3401 | return FALSE; | |
3402 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3403 | break; | |
e0001a05 NC |
3404 | case OP_LITERAL: |
3405 | sym = get_special_literal_symbol (); | |
3406 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3407 | if (insn->tok[op_data].X_op == O_tlsfunc |
3408 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3409 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3410 | break; |
3411 | case OP_LABEL: | |
3412 | sym = get_special_label_symbol (); | |
3413 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3414 | break; | |
43cd72b9 BW |
3415 | case OP_OPERAND_HI16U: |
3416 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3417 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3418 | if (expr_is_const (&insn->tok[op_data])) |
3419 | { | |
3420 | long val; | |
3421 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3422 | val = xg_apply_userdef_op_fn (op->typ, | |
3423 | targ->tok[op_num]. | |
3424 | X_add_number); | |
3425 | targ->tok[op_num].X_add_number = val; | |
3426 | } | |
3427 | else | |
3428 | { | |
3429 | /* For const16 we can create relocations for these. */ | |
3430 | if (targ->opcode == XTENSA_UNDEFINED | |
3431 | || (targ->opcode != xtensa_const16_opcode)) | |
3432 | return FALSE; | |
9c2799c2 | 3433 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3434 | /* Need to build a O_lo16 or O_hi16. */ |
3435 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3436 | if (targ->tok[op_num].X_op == O_symbol) | |
3437 | { | |
3438 | if (op->typ == OP_OPERAND_HI16U) | |
3439 | targ->tok[op_num].X_op = O_hi16; | |
3440 | else if (op->typ == OP_OPERAND_LOW16U) | |
3441 | targ->tok[op_num].X_op = O_lo16; | |
3442 | else | |
3443 | return FALSE; | |
3444 | } | |
3445 | } | |
3446 | break; | |
e0001a05 NC |
3447 | default: |
3448 | /* currently handles: | |
3449 | OP_OPERAND_LOW8 | |
3450 | OP_OPERAND_HI24S | |
3451 | OP_OPERAND_F32MINUS */ | |
3452 | if (xg_has_userdef_op_fn (op->typ)) | |
3453 | { | |
9c2799c2 | 3454 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3455 | if (expr_is_const (&insn->tok[op_data])) |
3456 | { | |
3457 | long val; | |
3458 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3459 | val = xg_apply_userdef_op_fn (op->typ, | |
3460 | targ->tok[op_num]. | |
3461 | X_add_number); | |
3462 | targ->tok[op_num].X_add_number = val; | |
3463 | } | |
3464 | else | |
3465 | return FALSE; /* We cannot use a relocation for this. */ | |
3466 | break; | |
3467 | } | |
9c2799c2 | 3468 | gas_assert (0); |
e0001a05 NC |
3469 | break; |
3470 | } | |
3471 | } | |
3472 | break; | |
3473 | ||
3474 | case INSTR_LITERAL_DEF: | |
3475 | op = bi->ops; | |
3476 | targ->opcode = XTENSA_UNDEFINED; | |
3477 | targ->insn_type = ITYPE_LITERAL; | |
3478 | targ->is_specific_opcode = FALSE; | |
3479 | for (; op != NULL; op = op->next) | |
3480 | { | |
3481 | int op_num = op->op_num; | |
3482 | int op_data = op->op_data; | |
9c2799c2 | 3483 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3484 | |
3485 | if (targ->ntok <= op_num) | |
3486 | targ->ntok = op_num + 1; | |
3487 | ||
3488 | switch (op->typ) | |
3489 | { | |
3490 | case OP_OPERAND: | |
9c2799c2 | 3491 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3492 | /* We can only pass resolvable literals through. */ |
3493 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3494 | return FALSE; | |
e0001a05 NC |
3495 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3496 | break; | |
3497 | case OP_LITERAL: | |
3498 | case OP_CONSTANT: | |
3499 | case OP_LABEL: | |
3500 | default: | |
9c2799c2 | 3501 | gas_assert (0); |
e0001a05 NC |
3502 | break; |
3503 | } | |
3504 | } | |
3505 | break; | |
3506 | ||
3507 | case INSTR_LABEL_DEF: | |
3508 | op = bi->ops; | |
3509 | targ->opcode = XTENSA_UNDEFINED; | |
3510 | targ->insn_type = ITYPE_LABEL; | |
3511 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3512 | /* Literal with no ops is a label? */ |
9c2799c2 | 3513 | gas_assert (op == NULL); |
e0001a05 NC |
3514 | break; |
3515 | ||
3516 | default: | |
9c2799c2 | 3517 | gas_assert (0); |
e0001a05 NC |
3518 | } |
3519 | ||
3520 | return TRUE; | |
3521 | } | |
3522 | ||
3523 | ||
43cd72b9 | 3524 | /* Return TRUE on success. */ |
e0001a05 | 3525 | |
7fa3d080 BW |
3526 | static bfd_boolean |
3527 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3528 | { |
3529 | for (; bi != NULL; bi = bi->next) | |
3530 | { | |
3531 | TInsn *next_insn = istack_push_space (istack); | |
3532 | ||
3533 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3534 | return FALSE; | |
3535 | } | |
3536 | return TRUE; | |
3537 | } | |
3538 | ||
3539 | ||
43cd72b9 | 3540 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3541 | |
7fa3d080 BW |
3542 | static bfd_boolean |
3543 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3544 | { |
3545 | int stack_size = istack->ninsn; | |
3546 | int steps_taken = 0; | |
43cd72b9 | 3547 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3548 | TransitionList *l; |
3549 | ||
9c2799c2 NC |
3550 | gas_assert (insn->insn_type == ITYPE_INSN); |
3551 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3552 | |
3553 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3554 | { | |
3555 | TransitionRule *rule = l->rule; | |
3556 | ||
3557 | if (xg_instruction_matches_rule (insn, rule)) | |
3558 | { | |
3559 | if (lateral_steps == steps_taken) | |
3560 | { | |
3561 | int i; | |
3562 | ||
3563 | /* This is it. Expand the rule to the stack. */ | |
3564 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3565 | return FALSE; | |
3566 | ||
3567 | /* Check to see if it fits. */ | |
3568 | for (i = stack_size; i < istack->ninsn; i++) | |
3569 | { | |
3570 | TInsn *insn = &istack->insn[i]; | |
3571 | ||
3572 | if (insn->insn_type == ITYPE_INSN | |
3573 | && !tinsn_has_symbolic_operands (insn) | |
3574 | && !xg_immeds_fit (insn)) | |
3575 | { | |
3576 | istack->ninsn = stack_size; | |
3577 | return FALSE; | |
3578 | } | |
3579 | } | |
3580 | return TRUE; | |
3581 | } | |
3582 | steps_taken++; | |
3583 | } | |
3584 | } | |
3585 | return FALSE; | |
3586 | } | |
3587 | ||
43cd72b9 | 3588 | \f |
43cd72b9 | 3589 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3590 | Return the number of steps taken. |
3591 | ||
3592 | For relaxation to correctly terminate, every relaxation chain must | |
3593 | terminate in one of two ways: | |
3594 | ||
3595 | 1. If the chain from one instruction to the next consists entirely of | |
3596 | single instructions, then the chain *must* handle all possible | |
3597 | immediates without failing. It must not ever fail because an | |
3598 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3599 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3600 | immediate larger than 32 bits, so it satisfies this condition. | |
3601 | Single instruction relaxation chains are as defined by | |
3602 | xg_is_single_relaxable_instruction. | |
3603 | ||
3604 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3605 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3606 | ||
3607 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3608 | -- in particular when the last two instructions have the same single | |
3609 | size. But nevertheless, you should guarantee the above two conditions. | |
3610 | ||
3611 | We could fix this so that single-instruction expansions correctly | |
3612 | terminate when they can't handle the range, but the error messages are | |
3613 | worse, and it actually turns out that in every case but one (18-bit wide | |
3614 | branches), you need a multi-instruction expansion to get the full range | |
3615 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3616 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3617 | |
7fa3d080 BW |
3618 | static int |
3619 | xg_assembly_relax (IStack *istack, | |
3620 | TInsn *insn, | |
3621 | segT pc_seg, | |
3622 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3623 | offsetT pc_offset, /* offset in fragment */ | |
3624 | int min_steps, /* minimum conversion steps */ | |
3625 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3626 | { |
3627 | int steps_taken = 0; | |
3628 | ||
b81bf389 BW |
3629 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3630 | This may go through a couple of stages of single instruction | |
3631 | transformations before we get there. */ | |
e0001a05 NC |
3632 | |
3633 | TInsn single_target; | |
3634 | TInsn current_insn; | |
3635 | int lateral_steps = 0; | |
3636 | int istack_size = istack->ninsn; | |
3637 | ||
3638 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3639 | && steps_taken >= min_steps) | |
3640 | { | |
3641 | istack_push (istack, insn); | |
3642 | return steps_taken; | |
3643 | } | |
43cd72b9 | 3644 | current_insn = *insn; |
e0001a05 | 3645 | |
7c834684 | 3646 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3647 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3648 | { |
21af2bbd | 3649 | steps_taken++; |
e0001a05 NC |
3650 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3651 | stretch)) | |
3652 | { | |
e0001a05 NC |
3653 | if (steps_taken >= min_steps) |
3654 | { | |
3655 | istack_push (istack, &single_target); | |
3656 | return steps_taken; | |
3657 | } | |
3658 | } | |
43cd72b9 | 3659 | current_insn = single_target; |
e0001a05 NC |
3660 | } |
3661 | ||
3662 | /* Now check for a multi-instruction expansion. */ | |
3663 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3664 | { | |
3665 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3666 | stretch)) | |
3667 | { | |
3668 | if (steps_taken >= min_steps) | |
3669 | { | |
3670 | istack_push (istack, ¤t_insn); | |
3671 | return steps_taken; | |
3672 | } | |
3673 | } | |
3674 | steps_taken++; | |
3675 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3676 | { | |
3677 | if (steps_taken >= min_steps) | |
3678 | return steps_taken; | |
3679 | } | |
3680 | lateral_steps++; | |
3681 | istack->ninsn = istack_size; | |
3682 | } | |
3683 | ||
3684 | /* It's not going to work -- use the original. */ | |
3685 | istack_push (istack, insn); | |
3686 | return steps_taken; | |
3687 | } | |
3688 | ||
3689 | ||
7fa3d080 BW |
3690 | static void |
3691 | xg_finish_frag (char *last_insn, | |
3692 | enum xtensa_relax_statesE frag_state, | |
3693 | enum xtensa_relax_statesE slot0_state, | |
3694 | int max_growth, | |
3695 | bfd_boolean is_insn) | |
e0001a05 NC |
3696 | { |
3697 | /* Finish off this fragment so that it has at LEAST the desired | |
3698 | max_growth. If it doesn't fit in this fragment, close this one | |
3699 | and start a new one. In either case, return a pointer to the | |
3700 | beginning of the growth area. */ | |
3701 | ||
3702 | fragS *old_frag; | |
43cd72b9 | 3703 | |
542f8b94 | 3704 | frag_grow (max_growth); |
e0001a05 NC |
3705 | old_frag = frag_now; |
3706 | ||
3707 | frag_now->fr_opcode = last_insn; | |
3708 | if (is_insn) | |
3709 | frag_now->tc_frag_data.is_insn = TRUE; | |
3710 | ||
3711 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3712 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3713 | ||
3714 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3715 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3716 | |
3717 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3718 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3719 | } |
3720 | ||
3721 | ||
7fa3d080 BW |
3722 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3723 | ||
3724 | static bfd_boolean | |
3725 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3726 | { | |
3727 | if (fragP == NULL) | |
3728 | return FALSE; | |
3729 | ||
3730 | for (; fragP; fragP = fragP->fr_next) | |
3731 | { | |
3732 | if (fragP == target) | |
3733 | return TRUE; | |
3734 | if (fragP->fr_fix != 0) | |
3735 | return FALSE; | |
3736 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3737 | return FALSE; | |
3738 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3739 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3740 | return FALSE; | |
3741 | if (fragP->fr_type == rs_space) | |
3742 | return FALSE; | |
3743 | } | |
3744 | return FALSE; | |
3745 | } | |
3746 | ||
3747 | ||
e0001a05 | 3748 | static bfd_boolean |
7fa3d080 | 3749 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3750 | { |
3751 | xtensa_isa isa = xtensa_default_isa; | |
3752 | int i; | |
43cd72b9 | 3753 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3754 | int target_op = -1; |
3755 | symbolS *sym; | |
3756 | fragS *target_frag; | |
3757 | ||
64b607e6 BW |
3758 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3759 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3760 | return FALSE; |
3761 | ||
3762 | for (i = 0; i < num_ops; i++) | |
3763 | { | |
43cd72b9 | 3764 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3765 | { |
3766 | target_op = i; | |
3767 | break; | |
3768 | } | |
3769 | } | |
3770 | if (target_op == -1) | |
3771 | return FALSE; | |
3772 | ||
3773 | if (insn->ntok <= target_op) | |
3774 | return FALSE; | |
3775 | ||
3776 | if (insn->tok[target_op].X_op != O_symbol) | |
3777 | return FALSE; | |
3778 | ||
3779 | sym = insn->tok[target_op].X_add_symbol; | |
3780 | if (sym == NULL) | |
3781 | return FALSE; | |
3782 | ||
3783 | if (insn->tok[target_op].X_add_number != 0) | |
3784 | return FALSE; | |
3785 | ||
3786 | target_frag = symbol_get_frag (sym); | |
3787 | if (target_frag == NULL) | |
3788 | return FALSE; | |
3789 | ||
c138bc38 | 3790 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3791 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3792 | return TRUE; | |
3793 | ||
3794 | return FALSE; | |
3795 | } | |
3796 | ||
3797 | ||
3798 | static void | |
7fa3d080 | 3799 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3800 | { |
3801 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3802 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3803 | |
7fa3d080 BW |
3804 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3805 | { | |
3806 | int i = 1; | |
3807 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3808 | && insn->tok[i].X_op == O_symbol) | |
3809 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3810 | return; | |
3811 | } | |
e0001a05 | 3812 | |
7fa3d080 BW |
3813 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3814 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3815 | { |
7fa3d080 BW |
3816 | int i; |
3817 | ||
3818 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3819 | { | |
3820 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3821 | && insn->tok[i].X_op == O_symbol) | |
3822 | { | |
3823 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3824 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3825 | if (S_IS_DEFINED (sym)) | |
3826 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3827 | } | |
3828 | } | |
e0001a05 | 3829 | } |
e0001a05 NC |
3830 | } |
3831 | ||
3832 | ||
43cd72b9 | 3833 | /* Return FALSE if no error. */ |
e0001a05 | 3834 | |
7fa3d080 BW |
3835 | static bfd_boolean |
3836 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3837 | { |
3838 | int num_ops = 0; | |
3839 | BuildOp *b_op; | |
3840 | ||
3841 | switch (instr_spec->typ) | |
3842 | { | |
3843 | case INSTR_INSTR: | |
3844 | new_insn->insn_type = ITYPE_INSN; | |
3845 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3846 | break; |
3847 | case INSTR_LITERAL_DEF: | |
3848 | new_insn->insn_type = ITYPE_LITERAL; | |
3849 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3850 | break; |
3851 | case INSTR_LABEL_DEF: | |
b224e962 | 3852 | abort (); |
e0001a05 | 3853 | } |
b224e962 BW |
3854 | new_insn->is_specific_opcode = FALSE; |
3855 | new_insn->debug_line = old_insn->debug_line; | |
3856 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3857 | |
3858 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3859 | { | |
3860 | expressionS *exp; | |
3861 | const expressionS *src_exp; | |
3862 | ||
3863 | num_ops++; | |
3864 | switch (b_op->typ) | |
3865 | { | |
3866 | case OP_CONSTANT: | |
3867 | /* The expression must be the constant. */ | |
9c2799c2 | 3868 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3869 | exp = &new_insn->tok[b_op->op_num]; |
3870 | set_expr_const (exp, b_op->op_data); | |
3871 | break; | |
3872 | ||
3873 | case OP_OPERAND: | |
9c2799c2 NC |
3874 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
3875 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
3876 | src_exp = &old_insn->tok[b_op->op_data]; |
3877 | exp = &new_insn->tok[b_op->op_num]; | |
3878 | copy_expr (exp, src_exp); | |
3879 | break; | |
3880 | ||
3881 | case OP_LITERAL: | |
3882 | case OP_LABEL: | |
3883 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 3884 | gas_assert (0); |
e0001a05 NC |
3885 | |
3886 | default: | |
3887 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 3888 | gas_assert (0); |
e0001a05 NC |
3889 | } |
3890 | } | |
3891 | ||
3892 | new_insn->ntok = num_ops; | |
3893 | return FALSE; | |
3894 | } | |
3895 | ||
3896 | ||
43cd72b9 | 3897 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3898 | |
7fa3d080 BW |
3899 | static bfd_boolean |
3900 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3901 | { |
43cd72b9 | 3902 | TransitionRule *rule; |
e0001a05 | 3903 | BuildInstr *insn_spec; |
43cd72b9 BW |
3904 | |
3905 | if (old_insn->is_specific_opcode || !density_supported) | |
3906 | return FALSE; | |
3907 | ||
3908 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3909 | if (rule == NULL) |
3910 | return FALSE; | |
3911 | ||
3912 | insn_spec = rule->to_instr; | |
3913 | /* There should only be one. */ | |
9c2799c2 NC |
3914 | gas_assert (insn_spec != NULL); |
3915 | gas_assert (insn_spec->next == NULL); | |
e0001a05 NC |
3916 | if (insn_spec->next != NULL) |
3917 | return FALSE; | |
3918 | ||
3919 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3920 | ||
3921 | return TRUE; | |
3922 | } | |
3923 | ||
3924 | ||
3925 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3926 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3927 | tokens into the stack or relax it and place multiple |
3928 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3929 | |
3930 | static bfd_boolean | |
7fa3d080 | 3931 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3932 | { |
3933 | int noperands; | |
3934 | TInsn new_insn; | |
7c834684 BW |
3935 | bfd_boolean do_expand; |
3936 | ||
60242db2 | 3937 | tinsn_init (&new_insn); |
e0001a05 | 3938 | |
43cd72b9 BW |
3939 | /* Narrow it if we can. xg_simplify_insn now does all the |
3940 | appropriate checking (e.g., for the density option). */ | |
3941 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3942 | orig_insn = &new_insn; | |
e0001a05 | 3943 | |
43cd72b9 BW |
3944 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3945 | orig_insn->opcode); | |
e0001a05 NC |
3946 | if (orig_insn->ntok < noperands) |
3947 | { | |
3948 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3949 | orig_insn->ntok, | |
3950 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3951 | noperands); | |
3952 | return TRUE; | |
3953 | } | |
3954 | if (orig_insn->ntok > noperands) | |
3955 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3956 | orig_insn->ntok, | |
3957 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3958 | noperands); | |
3959 | ||
43cd72b9 | 3960 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3961 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3962 | orig_insn->ntok = noperands; |
3963 | ||
e0001a05 NC |
3964 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3965 | return TRUE; | |
3966 | ||
d12f9798 BW |
3967 | /* Special case for extui opcode which has constraints not handled |
3968 | by the ordinary operand encoding checks. The number of operands | |
3969 | and related syntax issues have already been checked. */ | |
3970 | if (orig_insn->opcode == xtensa_extui_opcode) | |
3971 | { | |
3972 | int shiftimm = orig_insn->tok[2].X_add_number; | |
3973 | int maskimm = orig_insn->tok[3].X_add_number; | |
3974 | if (shiftimm + maskimm > 32) | |
3975 | { | |
3976 | as_bad (_("immediate operands sum to greater than 32")); | |
3977 | return TRUE; | |
3978 | } | |
3979 | } | |
3980 | ||
7c834684 BW |
3981 | /* If the instruction will definitely need to be relaxed, it is better |
3982 | to expand it now for better scheduling. Decide whether to expand | |
3983 | now.... */ | |
3984 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3985 | ||
3986 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3987 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3988 | adjacent. */ | |
3989 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3990 | do_expand = FALSE; | |
e0001a05 NC |
3991 | |
3992 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3993 | { | |
7c834684 BW |
3994 | /* The values of symbolic operands are not known yet, so only expand |
3995 | now if an operand is "complex" (e.g., difference of symbols) and | |
3996 | will have to be stored as a literal regardless of the value. */ | |
3997 | if (!tinsn_has_complex_operands (orig_insn)) | |
3998 | do_expand = FALSE; | |
e0001a05 | 3999 | } |
7c834684 BW |
4000 | else if (xg_immeds_fit (orig_insn)) |
4001 | do_expand = FALSE; | |
4002 | ||
4003 | if (do_expand) | |
4004 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4005 | else |
7c834684 | 4006 | istack_push (istack, orig_insn); |
e0001a05 | 4007 | |
e0001a05 NC |
4008 | return FALSE; |
4009 | } | |
4010 | ||
4011 | ||
7fa3d080 | 4012 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4013 | or the name is .gnu.linkonce.*. */ |
4014 | ||
4015 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
4016 | |
4017 | static bfd_boolean | |
4018 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4019 | { | |
4020 | flagword flags, link_once_flags; | |
4021 | ||
4022 | flags = bfd_get_section_flags (abfd, sec); | |
4023 | link_once_flags = (flags & SEC_LINK_ONCE); | |
4024 | ||
4025 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4026 | if (!link_once_flags |
4027 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4028 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4029 | |
7fa3d080 BW |
4030 | return (link_once_flags != 0); |
4031 | } | |
4032 | ||
4033 | ||
4034 | static void | |
4035 | xtensa_add_literal_sym (symbolS *sym) | |
4036 | { | |
4037 | sym_list *l; | |
4038 | ||
4039 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
4040 | l->sym = sym; | |
4041 | l->next = literal_syms; | |
4042 | literal_syms = l; | |
4043 | } | |
4044 | ||
4045 | ||
4046 | static symbolS * | |
4047 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4048 | { | |
4049 | static int lit_num = 0; | |
4050 | static char name[256]; | |
4051 | symbolS *symbolP; | |
4052 | ||
4053 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4054 | ||
4055 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4056 | be careful to make sure that if it is used in a relocation that the | |
4057 | symbol will be in the output file. */ | |
4058 | if (get_is_linkonce_section (stdoutput, sec)) | |
4059 | { | |
4060 | symbolP = symbol_new (name, sec, 0, frag); | |
4061 | S_CLEAR_EXTERNAL (symbolP); | |
4062 | /* symbolP->local = 1; */ | |
4063 | } | |
4064 | else | |
4065 | symbolP = symbol_new (name, sec, 0, frag); | |
4066 | ||
4067 | xtensa_add_literal_sym (symbolP); | |
4068 | ||
7fa3d080 BW |
4069 | lit_num++; |
4070 | return symbolP; | |
4071 | } | |
4072 | ||
4073 | ||
e0001a05 NC |
4074 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4075 | ||
7fa3d080 BW |
4076 | static symbolS * |
4077 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4078 | { |
4079 | emit_state state; | |
4080 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4081 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4082 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4083 | char *p; |
e0001a05 NC |
4084 | |
4085 | /* size = 4 for L32R. It could easily be larger when we move to | |
4086 | larger constants. Add a parameter later. */ | |
4087 | offsetT litsize = 4; | |
4088 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4089 | expressionS saved_loc; | |
43cd72b9 BW |
4090 | expressionS * emit_val; |
4091 | ||
e0001a05 NC |
4092 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4093 | ||
9c2799c2 NC |
4094 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4095 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4096 | |
4097 | xtensa_switch_to_literal_fragment (&state); | |
4098 | ||
43cd72b9 BW |
4099 | emit_val = &insn->tok[0]; |
4100 | if (emit_val->X_op == O_big) | |
4101 | { | |
4102 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4103 | if (size > litsize) | |
4104 | { | |
4105 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4106 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4107 | _("invalid immediate")); |
4108 | xtensa_restore_emit_state (&state); | |
4109 | return NULL; | |
4110 | } | |
4111 | } | |
4112 | ||
e0001a05 NC |
4113 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4114 | literals done with this function have a frag to themselves. That's | |
4115 | important for the way text section literals work. */ | |
4116 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4117 | record_alignment (now_seg, litalign); |
e0001a05 | 4118 | |
bbdd25a8 | 4119 | switch (emit_val->X_op) |
43cd72b9 | 4120 | { |
1bbb5f21 BW |
4121 | case O_pcrel: |
4122 | pcrel = TRUE; | |
4123 | /* fall through */ | |
bbdd25a8 | 4124 | case O_pltrel: |
28dbbc02 BW |
4125 | case O_tlsfunc: |
4126 | case O_tlsarg: | |
4127 | case O_tpoff: | |
4128 | case O_dtpoff: | |
bbdd25a8 | 4129 | p = frag_more (litsize); |
43cd72b9 | 4130 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4131 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4132 | if (emit_val->X_add_symbol) |
4133 | emit_val->X_op = O_symbol; | |
4134 | else | |
4135 | emit_val->X_op = O_constant; | |
4136 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4137 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4138 | break; |
4139 | ||
4140 | default: | |
4141 | emit_expr (emit_val, litsize); | |
4142 | break; | |
43cd72b9 | 4143 | } |
e0001a05 | 4144 | |
9c2799c2 | 4145 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4146 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4147 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4148 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4149 | |
4150 | /* Go back. */ | |
4151 | xtensa_restore_emit_state (&state); | |
4152 | return lit_sym; | |
4153 | } | |
4154 | ||
4155 | ||
4156 | static void | |
7fa3d080 | 4157 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4158 | { |
4159 | emit_state state; | |
43cd72b9 | 4160 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4161 | takes effect if something is placed here. */ |
4162 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4163 | fragS *lit_saved_frag; | |
4164 | ||
9c2799c2 | 4165 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4166 | |
4167 | xtensa_switch_to_literal_fragment (&state); | |
4168 | ||
4169 | /* Force a 4-byte align here. */ | |
4170 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4171 | record_alignment (now_seg, litalign); |
e0001a05 | 4172 | |
542f8b94 | 4173 | frag_grow (size); |
e0001a05 NC |
4174 | |
4175 | lit_saved_frag = frag_now; | |
4176 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4177 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4178 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4179 | |
4180 | /* Go back. */ | |
4181 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4182 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4183 | } |
4184 | ||
4185 | ||
e0001a05 | 4186 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4187 | Return TRUE on success. */ |
e0001a05 | 4188 | |
7fa3d080 BW |
4189 | static bfd_boolean |
4190 | xg_add_opcode_fix (TInsn *tinsn, | |
4191 | int opnum, | |
4192 | xtensa_format fmt, | |
4193 | int slot, | |
4194 | expressionS *expr, | |
4195 | fragS *fragP, | |
4196 | offsetT offset) | |
43cd72b9 BW |
4197 | { |
4198 | xtensa_opcode opcode = tinsn->opcode; | |
4199 | bfd_reloc_code_real_type reloc; | |
4200 | reloc_howto_type *howto; | |
4201 | int fmt_length; | |
e0001a05 NC |
4202 | fixS *the_fix; |
4203 | ||
43cd72b9 BW |
4204 | reloc = BFD_RELOC_NONE; |
4205 | ||
4206 | /* First try the special cases for "alternate" relocs. */ | |
4207 | if (opcode == xtensa_l32r_opcode) | |
4208 | { | |
4209 | if (fragP->tc_frag_data.use_absolute_literals) | |
4210 | reloc = encode_alt_reloc (slot); | |
4211 | } | |
4212 | else if (opcode == xtensa_const16_opcode) | |
4213 | { | |
4214 | if (expr->X_op == O_lo16) | |
4215 | { | |
4216 | reloc = encode_reloc (slot); | |
4217 | expr->X_op = O_symbol; | |
4218 | } | |
4219 | else if (expr->X_op == O_hi16) | |
4220 | { | |
4221 | reloc = encode_alt_reloc (slot); | |
4222 | expr->X_op = O_symbol; | |
4223 | } | |
4224 | } | |
4225 | ||
4226 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4227 | { |
43cd72b9 | 4228 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4229 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4230 | return FALSE; |
4231 | } | |
4232 | ||
43cd72b9 BW |
4233 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4234 | into the symbol table where the generic portions of the assembler | |
4235 | won't know what to do with them. */ | |
4236 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4237 | { | |
4238 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4239 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4240 | return FALSE; |
4241 | } | |
4242 | ||
4243 | /* Next try the generic relocs. */ | |
4244 | if (reloc == BFD_RELOC_NONE) | |
4245 | reloc = encode_reloc (slot); | |
4246 | if (reloc == BFD_RELOC_NONE) | |
4247 | { | |
4248 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4249 | return FALSE; | |
4250 | } | |
e0001a05 | 4251 | |
43cd72b9 | 4252 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4253 | if (!howto) |
4254 | { | |
43cd72b9 | 4255 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4256 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4257 | return FALSE; | |
4258 | } | |
4259 | ||
43cd72b9 BW |
4260 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4261 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4262 | howto->pc_relative, reloc); |
d9740523 | 4263 | the_fix->fx_no_overflow = 1; |
7fa3d080 BW |
4264 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; |
4265 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4266 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4267 | |
7fa3d080 BW |
4268 | return TRUE; |
4269 | } | |
4270 | ||
4271 | ||
4272 | static bfd_boolean | |
4273 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4274 | char *buf, |
4275 | fragS *fragP, | |
4276 | offsetT offset, | |
4277 | bfd_boolean build_fix) | |
4278 | { | |
4279 | static xtensa_insnbuf insnbuf = NULL; | |
4280 | bfd_boolean has_symbolic_immed = FALSE; | |
4281 | bfd_boolean ok = TRUE; | |
b2d179be | 4282 | |
7fa3d080 BW |
4283 | if (!insnbuf) |
4284 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4285 | ||
4286 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4287 | if (has_symbolic_immed && build_fix) | |
4288 | { | |
4289 | /* Add a fixup. */ | |
b2d179be BW |
4290 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4291 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4292 | int opnum = get_relaxable_immed (tinsn->opcode); |
4293 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4294 | |
b2d179be | 4295 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4296 | ok = FALSE; |
4297 | } | |
4298 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4299 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4300 | (unsigned char *) buf, 0); | |
7fa3d080 | 4301 | return ok; |
e0001a05 NC |
4302 | } |
4303 | ||
4304 | ||
7fa3d080 BW |
4305 | static void |
4306 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4307 | { |
4308 | symbolS *sym = get_special_literal_symbol (); | |
4309 | int i; | |
4310 | if (lit_sym == 0) | |
4311 | return; | |
9c2799c2 | 4312 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4313 | for (i = 0; i < insn->ntok; i++) |
4314 | if (insn->tok[i].X_add_symbol == sym) | |
4315 | insn->tok[i].X_add_symbol = lit_sym; | |
4316 | ||
4317 | } | |
4318 | ||
4319 | ||
7fa3d080 BW |
4320 | static void |
4321 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4322 | { |
4323 | symbolS *sym = get_special_label_symbol (); | |
4324 | int i; | |
e0001a05 NC |
4325 | for (i = 0; i < insn->ntok; i++) |
4326 | if (insn->tok[i].X_add_symbol == sym) | |
4327 | insn->tok[i].X_add_symbol = label_sym; | |
4328 | ||
4329 | } | |
4330 | ||
4331 | ||
43cd72b9 | 4332 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4333 | integer register. */ |
4334 | ||
4335 | static bfd_boolean | |
7fa3d080 | 4336 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4337 | { |
4338 | int i; | |
4339 | int num_ops; | |
4340 | xtensa_isa isa = xtensa_default_isa; | |
4341 | ||
43cd72b9 | 4342 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4343 | |
4344 | for (i = 0; i < num_ops; i++) | |
4345 | { | |
43cd72b9 BW |
4346 | char inout; |
4347 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4348 | if ((inout == 'o' || inout == 'm') | |
4349 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4350 | { |
43cd72b9 BW |
4351 | xtensa_regfile opnd_rf = |
4352 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4353 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4354 | { |
4355 | if ((insn->tok[i].X_op == O_register) | |
4356 | && (insn->tok[i].X_add_number == regnum)) | |
4357 | return TRUE; | |
4358 | } | |
4359 | } | |
4360 | } | |
4361 | return FALSE; | |
4362 | } | |
4363 | ||
4364 | ||
4365 | static bfd_boolean | |
7fa3d080 | 4366 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4367 | { |
4368 | xtensa_opcode opcode = tinsn->opcode; | |
4369 | ||
4370 | if (opcode == XTENSA_UNDEFINED) | |
4371 | return FALSE; | |
4372 | ||
4373 | if (opcode == xtensa_call0_opcode | |
4374 | || opcode == xtensa_callx0_opcode | |
4375 | || opcode == xtensa_call4_opcode | |
4376 | || opcode == xtensa_callx4_opcode | |
4377 | || opcode == xtensa_call8_opcode | |
4378 | || opcode == xtensa_callx8_opcode | |
4379 | || opcode == xtensa_call12_opcode | |
4380 | || opcode == xtensa_callx12_opcode | |
4381 | || opcode == xtensa_isync_opcode | |
4382 | || opcode == xtensa_ret_opcode | |
4383 | || opcode == xtensa_ret_n_opcode | |
4384 | || opcode == xtensa_retw_opcode | |
4385 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4386 | || opcode == xtensa_waiti_opcode |
4387 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4388 | return TRUE; |
c138bc38 | 4389 | |
e0001a05 NC |
4390 | return FALSE; |
4391 | } | |
4392 | ||
4393 | ||
4394 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4395 | This allows the debugger to add unaligned labels. | |
4396 | Also, the assembler generates stabs labels that need | |
4397 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4398 | ||
7fa3d080 BW |
4399 | static bfd_boolean |
4400 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4401 | { |
4402 | const char *name = S_GET_NAME (sym); | |
4403 | static size_t fake_size = 0; | |
4404 | ||
4405 | if (name | |
4406 | && name[0] == '.' | |
4407 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4408 | return TRUE; | |
4409 | ||
4410 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4411 | if (fake_size == 0) | |
4412 | fake_size = strlen (FAKE_LABEL_NAME); | |
4413 | ||
43cd72b9 | 4414 | if (name |
e0001a05 NC |
4415 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4416 | && (name[fake_size] == 'F' | |
4417 | || name[fake_size] == 'L' | |
4418 | || (name[fake_size] == 'e' | |
4419 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4420 | return TRUE; | |
4421 | ||
4422 | return FALSE; | |
4423 | } | |
4424 | ||
4425 | ||
7fa3d080 BW |
4426 | static fragS * |
4427 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4428 | { |
4429 | fragS *next_fragP = fragP->fr_next; | |
4430 | ||
c138bc38 | 4431 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4432 | So we have to skip until we find something legit. */ |
4433 | while (next_fragP && next_fragP->fr_fix == 0) | |
4434 | next_fragP = next_fragP->fr_next; | |
4435 | ||
4436 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4437 | return NULL; | |
4438 | ||
4439 | return next_fragP; | |
4440 | } | |
4441 | ||
4442 | ||
43cd72b9 | 4443 | static bfd_boolean |
7fa3d080 | 4444 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4445 | { |
4446 | xtensa_opcode out_opcode; | |
4447 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4448 | ||
4449 | if (next_fragP == NULL) | |
4450 | return FALSE; | |
4451 | ||
4452 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4453 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4454 | { | |
4455 | *opcode = out_opcode; | |
4456 | return TRUE; | |
4457 | } | |
4458 | return FALSE; | |
4459 | } | |
4460 | ||
4461 | ||
4462 | static int | |
7fa3d080 | 4463 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4464 | { |
e0001a05 NC |
4465 | static xtensa_insnbuf insnbuf = NULL; |
4466 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4467 | xtensa_format fmt; |
c138bc38 | 4468 | int fmt_size; |
e0001a05 NC |
4469 | |
4470 | if (!insnbuf) | |
4471 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4472 | ||
43cd72b9 BW |
4473 | if (fragP == NULL) |
4474 | return XTENSA_UNDEFINED; | |
4475 | ||
d77b99c9 BW |
4476 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4477 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4478 | |
4479 | fmt = xtensa_format_decode (isa, insnbuf); | |
4480 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4481 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4482 | fmt_size = xtensa_format_length (isa, fmt); |
4483 | ||
4484 | /* If the next format won't be changing due to relaxation, just | |
4485 | return the length of the first format. */ | |
4486 | if (fragP->fr_opcode != fragP->fr_literal) | |
4487 | return fmt_size; | |
4488 | ||
c138bc38 | 4489 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4490 | multi-slot instruction, we will return the more conservative |
4491 | number. This works because alignment on bigger instructions | |
4492 | is more restrictive than alignment on smaller instructions. | |
4493 | This is more conservative than we would like, but it happens | |
4494 | infrequently. */ | |
4495 | ||
4496 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4497 | return fmt_size; | |
4498 | ||
4499 | /* If we aren't doing one of our own relaxations or it isn't | |
4500 | slot-based, then the insn size won't change. */ | |
4501 | if (fragP->fr_type != rs_machine_dependent) | |
4502 | return fmt_size; | |
4503 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4504 | return fmt_size; | |
4505 | ||
4506 | /* If an instruction is about to grow, return the longer size. */ | |
4507 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4508 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4509 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4510 | { |
4511 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4512 | instruction in the relaxed version is of length 3. (The case | |
4513 | where we have to pull the instruction out of a FLIX bundle | |
4514 | is handled conservatively above.) However, frags with opcodes | |
4515 | that are expanding to wide branches end up having formats that | |
4516 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4517 | we can't tell directly what format the relaxer picked. This | |
4518 | is a wart in the design of the relaxer that should someday be | |
4519 | fixed, but would require major changes, or at least should | |
4520 | be accompanied by major changes to make use of that data. | |
4521 | ||
4522 | In any event, we can tell that we are expanding from a single-slot | |
4523 | three-byte format to a wider one with the logic below. */ | |
4524 | ||
4525 | if (fmt_size <= 3 && fragP->tc_frag_data.text_expansion[0] != 3) | |
4526 | return 3 + fragP->tc_frag_data.text_expansion[0]; | |
4527 | else | |
4528 | return 3; | |
4529 | } | |
c138bc38 | 4530 | |
43cd72b9 BW |
4531 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4532 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4533 | |
43cd72b9 | 4534 | return fmt_size; |
e0001a05 NC |
4535 | } |
4536 | ||
4537 | ||
7fa3d080 BW |
4538 | static int |
4539 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4540 | { |
7fa3d080 BW |
4541 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4542 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4543 | } |
4544 | ||
4545 | ||
03aaa593 BW |
4546 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4547 | required two-byte instructions to be treated as three-byte instructions | |
4548 | for loop instruction alignment. This restriction was removed beginning | |
4549 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4550 | is that the first instruction of the loop must appear at an address that | |
4551 | does not cross a fetch boundary. */ | |
4552 | ||
4553 | static int | |
4554 | get_loop_align_size (int insn_size) | |
4555 | { | |
4556 | if (insn_size == XTENSA_UNDEFINED) | |
4557 | return xtensa_fetch_width; | |
4558 | ||
4559 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4560 | return 3; | |
4561 | ||
4562 | return insn_size; | |
4563 | } | |
4564 | ||
4565 | ||
e0001a05 NC |
4566 | /* If the next legit fragment is an end-of-loop marker, |
4567 | switch its state so it will instantiate a NOP. */ | |
4568 | ||
4569 | static void | |
1d19a770 | 4570 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4571 | { |
4572 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4573 | fragS *new_target = NULL; |
e0001a05 | 4574 | |
7b1cc377 | 4575 | if (align_targets) |
43cd72b9 BW |
4576 | { |
4577 | /* We are guaranteed there will be one of these... */ | |
4578 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4579 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4580 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4581 | next_fragP = next_fragP->fr_next; | |
4582 | ||
9c2799c2 | 4583 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4584 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4585 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4586 | ||
4587 | /* ...and one of these. */ | |
4588 | new_target = next_fragP->fr_next; | |
4589 | while (!(new_target->fr_type == rs_machine_dependent | |
4590 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4591 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4592 | new_target = new_target->fr_next; | |
4593 | ||
9c2799c2 | 4594 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4595 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4596 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4597 | } | |
43cd72b9 | 4598 | |
1d19a770 | 4599 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4600 | { |
1d19a770 BW |
4601 | if (next_fragP->fr_type == rs_machine_dependent |
4602 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4603 | { |
1d19a770 BW |
4604 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4605 | return; | |
e0001a05 | 4606 | } |
1d19a770 BW |
4607 | |
4608 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4609 | } |
4610 | } | |
4611 | ||
4612 | ||
4613 | static bfd_boolean | |
7fa3d080 | 4614 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4615 | { |
43cd72b9 | 4616 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4617 | so we have to skip until we find something legit. */ |
4618 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4619 | { | |
4620 | if (fragP->tc_frag_data.is_branch_target) | |
4621 | return TRUE; | |
4622 | if (fragP->fr_fix != 0) | |
4623 | break; | |
4624 | } | |
4625 | return FALSE; | |
4626 | } | |
4627 | ||
4628 | ||
4629 | static bfd_boolean | |
7fa3d080 | 4630 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4631 | { |
c138bc38 | 4632 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4633 | So we have to skip until we find something legit. */ |
4634 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4635 | { | |
4636 | if (fragP->tc_frag_data.is_loop_target) | |
4637 | return TRUE; | |
4638 | if (fragP->fr_fix != 0) | |
4639 | break; | |
4640 | } | |
4641 | return FALSE; | |
4642 | } | |
4643 | ||
4644 | ||
4645 | static addressT | |
7fa3d080 | 4646 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4647 | { |
4648 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4649 | xtensa_opcode next_opcode; |
e0001a05 | 4650 | |
43cd72b9 | 4651 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4652 | return 0; |
4653 | ||
43cd72b9 BW |
4654 | /* Sometimes an empty will end up here due to storage allocation issues, |
4655 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4656 | while (next_fragp->fr_fix == 0) |
4657 | next_fragp = next_fragp->fr_next; | |
4658 | ||
4659 | if (next_fragp->fr_type != rs_machine_dependent) | |
4660 | return 0; | |
4661 | ||
4662 | /* There is some implicit knowledge encoded in here. | |
4663 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4664 | been relaxed. Note that we can assume that the LOOP |
4665 | instruction is in slot 0 because loops aren't bundleable. */ | |
4666 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4667 | return get_expanded_loop_offset (next_opcode); |
4668 | ||
4669 | return 0; | |
4670 | } | |
4671 | ||
4672 | ||
4673 | /* Mark a location where we can later insert literal frags. Update | |
4674 | the section's literal_pool_loc, so subsequent literals can be | |
4675 | placed nearest to their use. */ | |
4676 | ||
4677 | static void | |
7fa3d080 | 4678 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4679 | { |
4680 | /* Any labels pointing to the current location need | |
4681 | to be adjusted to after the literal pool. */ | |
4682 | emit_state s; | |
e0001a05 | 4683 | fragS *pool_location; |
e0001a05 | 4684 | |
1f2a7e38 | 4685 | if (use_literal_section) |
43cd72b9 BW |
4686 | return; |
4687 | ||
dd49a749 BW |
4688 | /* We stash info in these frags so we can later move the literal's |
4689 | fixes into this frchain's fix list. */ | |
e0001a05 | 4690 | pool_location = frag_now; |
dd49a749 | 4691 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4692 | frag_now->tc_frag_data.literal_frag = frag_now; |
dd49a749 | 4693 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4694 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4695 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4696 | frag_now->tc_frag_data.lit_seg = now_seg; |
4697 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4698 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4699 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4700 | |
4701 | /* Now put a frag into the literal pool that points to this location. */ | |
4702 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4703 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4704 | frag_align (2, 0, 0); | |
4705 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4706 | |
4707 | /* Close whatever frag is there. */ | |
4708 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4709 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4710 | frag_now->tc_frag_data.literal_frag = pool_location; |
4711 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4712 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4713 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4714 | } |
4715 | ||
4716 | ||
43cd72b9 BW |
4717 | /* Build a nop of the correct size into tinsn. */ |
4718 | ||
4719 | static void | |
7fa3d080 | 4720 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4721 | { |
4722 | tinsn_init (tinsn); | |
4723 | switch (size) | |
4724 | { | |
4725 | case 2: | |
4726 | tinsn->opcode = xtensa_nop_n_opcode; | |
4727 | tinsn->ntok = 0; | |
4728 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4729 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4730 | break; | |
4731 | ||
4732 | case 3: | |
4733 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4734 | { | |
4735 | tinsn->opcode = xtensa_or_opcode; | |
4736 | set_expr_const (&tinsn->tok[0], 1); | |
4737 | set_expr_const (&tinsn->tok[1], 1); | |
4738 | set_expr_const (&tinsn->tok[2], 1); | |
4739 | tinsn->ntok = 3; | |
4740 | } | |
4741 | else | |
4742 | tinsn->opcode = xtensa_nop_opcode; | |
4743 | ||
9c2799c2 | 4744 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4745 | } |
4746 | } | |
4747 | ||
4748 | ||
e0001a05 NC |
4749 | /* Assemble a NOP of the requested size in the buffer. User must have |
4750 | allocated "buf" with at least "size" bytes. */ | |
4751 | ||
7fa3d080 | 4752 | static void |
d77b99c9 | 4753 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4754 | { |
4755 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4756 | TInsn tinsn; |
e0001a05 | 4757 | |
43cd72b9 | 4758 | build_nop (&tinsn, size); |
e0001a05 | 4759 | |
43cd72b9 BW |
4760 | if (!insnbuf) |
4761 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4762 | |
43cd72b9 | 4763 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4764 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4765 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4766 | } |
4767 | ||
4768 | ||
4769 | /* Return the number of bytes for the offset of the expanded loop | |
4770 | instruction. This should be incorporated into the relaxation | |
4771 | specification but is hard-coded here. This is used to auto-align | |
4772 | the loop instruction. It is invalid to call this function if the | |
4773 | configuration does not have loops or if the opcode is not a loop | |
4774 | opcode. */ | |
4775 | ||
4776 | static addressT | |
7fa3d080 | 4777 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4778 | { |
4779 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4780 | This MUST correspond directly to the specification of the loop | |
4781 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4782 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4783 | if (opcode == xtensa_loop_opcode) |
4784 | return 0; | |
4785 | if (opcode == xtensa_loopnez_opcode) | |
4786 | return 3; | |
4787 | if (opcode == xtensa_loopgtz_opcode) | |
4788 | return 6; | |
4789 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4790 | return 0; | |
4791 | } | |
4792 | ||
4793 | ||
7fa3d080 BW |
4794 | static fragS * |
4795 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4796 | { |
4797 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4798 | } | |
4799 | ||
4800 | ||
4801 | static void | |
7fa3d080 | 4802 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4803 | { |
4804 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4805 | } | |
4806 | ||
43cd72b9 BW |
4807 | |
4808 | /* Set frag assembly state should be called when a new frag is | |
4809 | opened and after a frag has been closed. */ | |
4810 | ||
7fa3d080 BW |
4811 | static void |
4812 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4813 | { |
4814 | if (!density_supported) | |
4815 | fragP->tc_frag_data.is_no_density = TRUE; | |
4816 | ||
4817 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4818 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4819 | "use_schedule" here. */ |
4820 | if (!directive_state[directive_transform]) | |
4821 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4822 | if (directive_state[directive_longcalls]) |
4823 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4824 | fragP->tc_frag_data.use_absolute_literals = |
4825 | directive_state[directive_absolute_literals]; | |
4826 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4827 | } | |
4828 | ||
4829 | ||
7fa3d080 BW |
4830 | static bfd_boolean |
4831 | relaxable_section (asection *sec) | |
43cd72b9 | 4832 | { |
11ac2671 BW |
4833 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4834 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4835 | } |
4836 | ||
4837 | ||
99ded152 BW |
4838 | static void |
4839 | xtensa_mark_frags_for_org (void) | |
4840 | { | |
4841 | segT *seclist; | |
4842 | ||
4843 | /* Walk over each fragment of all of the current segments. If we find | |
4844 | a .org frag in any of the segments, mark all frags prior to it as | |
4845 | "no transform", which will prevent linker optimizations from messing | |
4846 | up the .org distance. This should be done after | |
4847 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4848 | about that function trashing the data we save here. */ | |
4849 | ||
4850 | for (seclist = &stdoutput->sections; | |
4851 | seclist && *seclist; | |
4852 | seclist = &(*seclist)->next) | |
4853 | { | |
4854 | segT sec = *seclist; | |
4855 | segment_info_type *seginfo; | |
4856 | fragS *fragP; | |
4857 | flagword flags; | |
4858 | flags = bfd_get_section_flags (stdoutput, sec); | |
4859 | if (flags & SEC_DEBUGGING) | |
4860 | continue; | |
4861 | if (!(flags & SEC_ALLOC)) | |
4862 | continue; | |
4863 | ||
4864 | seginfo = seg_info (sec); | |
4865 | if (seginfo && seginfo->frchainP) | |
4866 | { | |
4867 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4868 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4869 | fragP = fragP->fr_next) | |
4870 | { | |
4871 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4872 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4873 | if (fragP->fr_subtype == RELAX_ORG) | |
4874 | { | |
4875 | while (last_fragP != fragP->fr_next) | |
4876 | { | |
4877 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4878 | last_fragP = last_fragP->fr_next; | |
4879 | } | |
4880 | } | |
4881 | } | |
4882 | } | |
4883 | } | |
4884 | } | |
4885 | ||
4886 | ||
43cd72b9 | 4887 | static void |
7fa3d080 | 4888 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4889 | { |
4890 | segT *seclist; | |
4891 | ||
4892 | /* Walk over each fragment of all of the current segments. For each | |
4893 | unmarked fragment, mark it with the same info as the previous | |
4894 | fragment. */ | |
4895 | for (seclist = &stdoutput->sections; | |
4896 | seclist && *seclist; | |
4897 | seclist = &(*seclist)->next) | |
4898 | { | |
4899 | segT sec = *seclist; | |
4900 | segment_info_type *seginfo; | |
4901 | fragS *fragP; | |
4902 | flagword flags; | |
4903 | flags = bfd_get_section_flags (stdoutput, sec); | |
4904 | if (flags & SEC_DEBUGGING) | |
4905 | continue; | |
4906 | if (!(flags & SEC_ALLOC)) | |
4907 | continue; | |
4908 | ||
4909 | seginfo = seg_info (sec); | |
4910 | if (seginfo && seginfo->frchainP) | |
4911 | { | |
4912 | fragS *last_fragP = 0; | |
4913 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4914 | fragP = fragP->fr_next) | |
4915 | { | |
4916 | if (fragP->fr_fix != 0 | |
4917 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4918 | { | |
4919 | if (last_fragP == 0) | |
4920 | { | |
4921 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4922 | _("assembly state not set for first frag in section %s"), | |
4923 | sec->name); | |
4924 | } | |
4925 | else | |
4926 | { | |
4927 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4928 | fragP->tc_frag_data.is_no_density = | |
4929 | last_fragP->tc_frag_data.is_no_density; | |
4930 | fragP->tc_frag_data.is_no_transform = | |
4931 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4932 | fragP->tc_frag_data.use_longcalls = |
4933 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4934 | fragP->tc_frag_data.use_absolute_literals = |
4935 | last_fragP->tc_frag_data.use_absolute_literals; | |
4936 | } | |
4937 | } | |
4938 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4939 | last_fragP = fragP; | |
4940 | } | |
4941 | } | |
4942 | } | |
4943 | } | |
4944 | ||
4945 | ||
4946 | static void | |
7fa3d080 BW |
4947 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4948 | asection *sec, | |
4949 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4950 | { |
4951 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4952 | segment_info_type *seginfo = seg_info (sec); | |
4953 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4954 | |
43cd72b9 | 4955 | if (flags & SEC_CODE) |
c138bc38 | 4956 | { |
43cd72b9 BW |
4957 | xtensa_isa isa = xtensa_default_isa; |
4958 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4959 | while (frag != NULL) | |
4960 | { | |
4961 | if (frag->tc_frag_data.is_branch_target) | |
4962 | { | |
4963 | int op_size; | |
664df4e4 | 4964 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4965 | xtensa_format fmt; |
4966 | ||
d77b99c9 BW |
4967 | xtensa_insnbuf_from_chars |
4968 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4969 | fmt = xtensa_format_decode (isa, insnbuf); |
4970 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4971 | branch_align = 1 << branch_align_power (sec); |
4972 | frag_addr = frag->fr_address % branch_align; | |
4973 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4974 | as_warn_where (frag->fr_file, frag->fr_line, |
4975 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4976 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4977 | } |
4978 | frag = frag->fr_next; | |
4979 | } | |
4980 | xtensa_insnbuf_free (isa, insnbuf); | |
4981 | } | |
4982 | } | |
4983 | ||
4984 | ||
4985 | static void | |
7fa3d080 BW |
4986 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4987 | asection *sec, | |
4988 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4989 | { |
4990 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4991 | segment_info_type *seginfo = seg_info (sec); | |
4992 | fragS *frag = seginfo->frchainP->frch_root; | |
4993 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4994 | |
43cd72b9 | 4995 | if (flags & SEC_CODE) |
c138bc38 | 4996 | { |
43cd72b9 BW |
4997 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4998 | while (frag != NULL) | |
4999 | { | |
5000 | if (frag->tc_frag_data.is_first_loop_insn) | |
5001 | { | |
5002 | int op_size; | |
d77b99c9 | 5003 | addressT frag_addr; |
43cd72b9 BW |
5004 | xtensa_format fmt; |
5005 | ||
d77b99c9 BW |
5006 | xtensa_insnbuf_from_chars |
5007 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5008 | fmt = xtensa_format_decode (isa, insnbuf); |
5009 | op_size = xtensa_format_length (isa, fmt); | |
5010 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
5011 | ||
d77b99c9 | 5012 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
5013 | as_warn_where (frag->fr_file, frag->fr_line, |
5014 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 5015 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5016 | } |
5017 | frag = frag->fr_next; | |
5018 | } | |
5019 | xtensa_insnbuf_free (isa, insnbuf); | |
5020 | } | |
5021 | } | |
5022 | ||
5023 | ||
30f725a1 BW |
5024 | static int |
5025 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5026 | { |
5027 | xtensa_isa isa = xtensa_default_isa; | |
5028 | static xtensa_insnbuf insnbuf = NULL; | |
5029 | static xtensa_insnbuf slotbuf = NULL; | |
5030 | xtensa_format fmt; | |
5031 | int slot; | |
5032 | bfd_boolean alt_reloc; | |
5033 | xtensa_opcode opcode; | |
5034 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5035 | ||
1b6e95c2 BW |
5036 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5037 | || alt_reloc) | |
43cd72b9 BW |
5038 | as_fatal (_("unexpected fix")); |
5039 | ||
5040 | if (!insnbuf) | |
5041 | { | |
5042 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5043 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5044 | } | |
5045 | ||
d77b99c9 | 5046 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5047 | fmt = xtensa_format_decode (isa, insnbuf); |
5048 | if (fmt == XTENSA_UNDEFINED) | |
5049 | as_fatal (_("undecodable fix")); | |
5050 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5051 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5052 | if (opcode == XTENSA_UNDEFINED) | |
5053 | as_fatal (_("undecodable fix")); | |
5054 | ||
5055 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5056 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5057 | of a CONST16 operand. */ |
43cd72b9 | 5058 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5059 | return 0; |
43cd72b9 BW |
5060 | |
5061 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5062 | get_relaxable_immed (opcode), val, | |
5063 | fixP->fx_file, fixP->fx_line); | |
5064 | ||
5065 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5066 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5067 | |
5068 | return 1; | |
43cd72b9 BW |
5069 | } |
5070 | ||
e0001a05 NC |
5071 | \f |
5072 | /* External Functions and Other GAS Hooks. */ | |
5073 | ||
5074 | const char * | |
7fa3d080 | 5075 | xtensa_target_format (void) |
e0001a05 NC |
5076 | { |
5077 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5078 | } | |
5079 | ||
5080 | ||
5081 | void | |
7fa3d080 | 5082 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5083 | { |
5084 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5085 | } | |
5086 | ||
5087 | ||
5088 | void | |
7fa3d080 | 5089 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5090 | { |
5091 | if (target_big_endian) | |
5092 | number_to_chars_bigendian (buf, val, n); | |
5093 | else | |
5094 | number_to_chars_littleendian (buf, val, n); | |
5095 | } | |
5096 | ||
5097 | ||
5098 | /* This function is called once, at assembler startup time. It should | |
5099 | set up all the tables, etc. that the MD part of the assembler will | |
5100 | need. */ | |
5101 | ||
5102 | void | |
7fa3d080 | 5103 | md_begin (void) |
e0001a05 NC |
5104 | { |
5105 | segT current_section = now_seg; | |
5106 | int current_subsec = now_subseg; | |
5107 | xtensa_isa isa; | |
62af60e2 | 5108 | int i; |
e0001a05 | 5109 | |
43cd72b9 | 5110 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5111 | isa = xtensa_default_isa; |
e0001a05 | 5112 | |
43cd72b9 BW |
5113 | linkrelax = 1; |
5114 | ||
74869ac7 | 5115 | /* Set up the literal sections. */ |
e0001a05 | 5116 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5117 | |
5118 | subseg_set (current_section, current_subsec); | |
5119 | ||
5120 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5121 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5122 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5123 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5124 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5125 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5126 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5127 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5128 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5129 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5130 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5131 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5132 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5133 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5134 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5135 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5136 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5137 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5138 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5139 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5140 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5141 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5142 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5143 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5144 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5145 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5146 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5147 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5148 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5149 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5150 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5151 | |
62af60e2 SA |
5152 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
5153 | { | |
5154 | int format_slots = xtensa_format_num_slots (isa, i); | |
5155 | if (format_slots > config_max_slots) | |
5156 | config_max_slots = format_slots; | |
5157 | } | |
5158 | ||
5159 | xg_init_vinsn (&cur_vinsn); | |
5160 | ||
77cba8a3 BW |
5161 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5162 | ||
43cd72b9 BW |
5163 | init_op_placement_info_table (); |
5164 | ||
5165 | /* Set up the assembly state. */ | |
5166 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5167 | xtensa_set_frag_assembly_state (frag_now); | |
5168 | } | |
5169 | ||
5170 | ||
5171 | /* TC_INIT_FIX_DATA hook */ | |
5172 | ||
5173 | void | |
7fa3d080 | 5174 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5175 | { |
5176 | x->tc_fix_data.slot = 0; | |
5177 | x->tc_fix_data.X_add_symbol = NULL; | |
5178 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5179 | } |
5180 | ||
5181 | ||
5182 | /* tc_frob_label hook */ | |
5183 | ||
5184 | void | |
7fa3d080 | 5185 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5186 | { |
3ea38ac2 BW |
5187 | float freq; |
5188 | ||
5189 | if (cur_vinsn.inside_bundle) | |
5190 | { | |
5191 | as_bad (_("labels are not valid inside bundles")); | |
5192 | return; | |
5193 | } | |
5194 | ||
5195 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5196 | |
43cd72b9 BW |
5197 | /* Since the label was already attached to a frag associated with the |
5198 | previous basic block, it now needs to be reset to the current frag. */ | |
5199 | symbol_set_frag (sym, frag_now); | |
5200 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5201 | ||
82e7541d BW |
5202 | if (generating_literals) |
5203 | xtensa_add_literal_sym (sym); | |
5204 | else | |
5205 | xtensa_add_insn_label (sym); | |
5206 | ||
7b1cc377 BW |
5207 | if (symbol_get_tc (sym)->is_loop_target) |
5208 | { | |
5209 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5210 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5211 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5212 | ||
5213 | xtensa_set_frag_assembly_state (frag_now); | |
5214 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5215 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5216 | ||
5217 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5218 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5219 | } |
e0001a05 NC |
5220 | |
5221 | /* No target aligning in the absolute section. */ | |
61846f28 | 5222 | if (now_seg != absolute_section |
61846f28 | 5223 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5224 | && !generating_literals) |
5225 | { | |
43cd72b9 BW |
5226 | xtensa_set_frag_assembly_state (frag_now); |
5227 | ||
b7afdeef SA |
5228 | if (do_align_targets ()) |
5229 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5230 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5231 | frag_now->fr_offset, NULL); | |
5232 | else | |
5233 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5234 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5235 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5236 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5237 | } |
5238 | ||
5239 | /* We need to mark the following properties even if we aren't aligning. */ | |
5240 | ||
5241 | /* If the label is already known to be a branch target, i.e., a | |
5242 | forward branch, mark the frag accordingly. Backward branches | |
5243 | are handled by xg_add_branch_and_loop_targets. */ | |
5244 | if (symbol_get_tc (sym)->is_branch_target) | |
5245 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5246 | ||
5247 | /* Loops only go forward, so they can be identified here. */ | |
5248 | if (symbol_get_tc (sym)->is_loop_target) | |
5249 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5250 | |
5251 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5252 | } |
5253 | ||
5254 | ||
5255 | /* tc_unrecognized_line hook */ | |
5256 | ||
5257 | int | |
7fa3d080 | 5258 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5259 | { |
5260 | switch (ch) | |
5261 | { | |
5262 | case '{' : | |
5263 | if (cur_vinsn.inside_bundle == 0) | |
5264 | { | |
5265 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5266 | when using --gstabs. Temporarily disable debug info. */ | |
5267 | generate_lineno_debug (); | |
5268 | if (debug_type == DEBUG_STABS) | |
5269 | { | |
5270 | xt_saved_debug_type = debug_type; | |
5271 | debug_type = DEBUG_NONE; | |
5272 | } | |
82e7541d | 5273 | |
43cd72b9 BW |
5274 | cur_vinsn.inside_bundle = 1; |
5275 | } | |
5276 | else | |
5277 | { | |
5278 | as_bad (_("extra opening brace")); | |
5279 | return 0; | |
5280 | } | |
5281 | break; | |
82e7541d | 5282 | |
43cd72b9 BW |
5283 | case '}' : |
5284 | if (cur_vinsn.inside_bundle) | |
5285 | finish_vinsn (&cur_vinsn); | |
5286 | else | |
5287 | { | |
5288 | as_bad (_("extra closing brace")); | |
5289 | return 0; | |
5290 | } | |
5291 | break; | |
5292 | default: | |
5293 | as_bad (_("syntax error")); | |
5294 | return 0; | |
e0001a05 | 5295 | } |
43cd72b9 | 5296 | return 1; |
e0001a05 NC |
5297 | } |
5298 | ||
5299 | ||
5300 | /* md_flush_pending_output hook */ | |
5301 | ||
5302 | void | |
7fa3d080 | 5303 | xtensa_flush_pending_output (void) |
e0001a05 | 5304 | { |
a3582eee BW |
5305 | /* This line fixes a bug where automatically generated gstabs info |
5306 | separates a function label from its entry instruction, ending up | |
5307 | with the literal position between the function label and the entry | |
5308 | instruction and crashing code. It only happens with --gstabs and | |
5309 | --text-section-literals, and when several other obscure relaxation | |
5310 | conditions are met. */ | |
5311 | if (outputting_stabs_line_debug) | |
5312 | return; | |
5313 | ||
43cd72b9 BW |
5314 | if (cur_vinsn.inside_bundle) |
5315 | as_bad (_("missing closing brace")); | |
5316 | ||
e0001a05 NC |
5317 | /* If there is a non-zero instruction fragment, close it. */ |
5318 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5319 | { | |
5320 | frag_wane (frag_now); | |
5321 | frag_new (0); | |
43cd72b9 | 5322 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5323 | } |
5324 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5325 | |
5326 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5327 | } |
5328 | ||
5329 | ||
43cd72b9 BW |
5330 | /* We had an error while parsing an instruction. The string might look |
5331 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5332 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5333 | and the num_slots field will grow past the end of the array of slots, | |
5334 | and bad things happen. */ | |
5335 | ||
5336 | static void | |
7fa3d080 | 5337 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5338 | { |
5339 | if (cur_vinsn.inside_bundle) | |
5340 | { | |
5341 | if (*input_line_pointer == '}' | |
5342 | || *(input_line_pointer - 1) == '}' | |
5343 | || *(input_line_pointer - 2) == '}') | |
5344 | xg_clear_vinsn (&cur_vinsn); | |
5345 | } | |
5346 | } | |
5347 | ||
5348 | ||
e0001a05 | 5349 | void |
7fa3d080 | 5350 | md_assemble (char *str) |
e0001a05 NC |
5351 | { |
5352 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5353 | char *opname; |
e0001a05 NC |
5354 | unsigned opnamelen; |
5355 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5356 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5357 | int num_args; |
e0001a05 | 5358 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5359 | |
e0001a05 NC |
5360 | tinsn_init (&orig_insn); |
5361 | ||
5362 | /* Split off the opcode. */ | |
5363 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5364 | opname = xmalloc (opnamelen + 1); | |
5365 | memcpy (opname, str, opnamelen); | |
5366 | opname[opnamelen] = '\0'; | |
5367 | ||
5368 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5369 | if (num_args == -1) | |
5370 | { | |
5371 | as_bad (_("syntax error")); | |
5372 | return; | |
5373 | } | |
5374 | ||
5375 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5376 | return; | |
5377 | ||
5378 | /* Check for an underbar prefix. */ | |
5379 | if (*opname == '_') | |
5380 | { | |
5381 | has_underbar = TRUE; | |
5382 | opname += 1; | |
5383 | } | |
5384 | ||
5385 | orig_insn.insn_type = ITYPE_INSN; | |
5386 | orig_insn.ntok = 0; | |
43cd72b9 | 5387 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5388 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 BW |
5389 | |
5390 | /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its | |
5391 | extra argument and set the opcode to "CALLXn". */ | |
5392 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5393 | && strncasecmp (opname, "callx", 5) == 0) | |
5394 | { | |
5395 | unsigned long window_size; | |
5396 | char *suffix; | |
5397 | ||
5398 | window_size = strtoul (opname + 5, &suffix, 10); | |
5399 | if (suffix != opname + 5 | |
5400 | && (window_size == 0 | |
5401 | || window_size == 4 | |
5402 | || window_size == 8 | |
5403 | || window_size == 12) | |
5404 | && strcasecmp (suffix, ".tls") == 0) | |
5405 | { | |
5406 | switch (window_size) | |
5407 | { | |
5408 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5409 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5410 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5411 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5412 | } | |
5413 | ||
5414 | if (num_args != 2) | |
5415 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5416 | else | |
5417 | { | |
5418 | bfd_reloc_code_real_type reloc; | |
5419 | char *old_input_line_pointer; | |
19e8f41a | 5420 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5421 | segT t; |
5422 | ||
5423 | old_input_line_pointer = input_line_pointer; | |
5424 | input_line_pointer = arg_strings[num_args - 1]; | |
5425 | ||
5426 | t = expression (tok); | |
5427 | if (tok->X_op == O_symbol | |
5428 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5429 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5430 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5431 | else | |
5432 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5433 | ||
5434 | input_line_pointer = old_input_line_pointer; | |
5435 | num_args -= 1; | |
5436 | } | |
5437 | } | |
5438 | } | |
5439 | ||
19e8f41a BW |
5440 | /* Special case: Check for "j.l" psuedo op. */ |
5441 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5442 | && strncasecmp (opname, "j.l", 3) == 0) | |
5443 | { | |
5444 | if (num_args != 2) | |
5445 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5446 | else | |
5447 | { | |
5448 | char *old_input_line_pointer; | |
5449 | expressionS *tok = &orig_insn.extra_arg; | |
5450 | ||
5451 | old_input_line_pointer = input_line_pointer; | |
5452 | input_line_pointer = arg_strings[num_args - 1]; | |
5453 | ||
5454 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5455 | input_line_pointer = old_input_line_pointer; | |
5456 | ||
5457 | num_args -= 1; | |
5458 | orig_insn.opcode = xtensa_j_opcode; | |
5459 | } | |
5460 | } | |
5461 | ||
e0001a05 NC |
5462 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5463 | { | |
43cd72b9 BW |
5464 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5465 | if (fmt == XTENSA_UNDEFINED) | |
5466 | { | |
5467 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5468 | error_reset_cur_vinsn (); | |
5469 | return; | |
5470 | } | |
5471 | if (!cur_vinsn.inside_bundle) | |
5472 | { | |
5473 | as_bad (_("format names only valid inside bundles")); | |
5474 | error_reset_cur_vinsn (); | |
5475 | return; | |
5476 | } | |
5477 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5478 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5479 | opname); | |
5480 | cur_vinsn.format = fmt; | |
5481 | free (has_underbar ? opname - 1 : opname); | |
5482 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5483 | return; |
5484 | } | |
5485 | ||
e0001a05 NC |
5486 | /* Parse the arguments. */ |
5487 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5488 | { | |
5489 | as_bad (_("syntax error")); | |
43cd72b9 | 5490 | error_reset_cur_vinsn (); |
e0001a05 NC |
5491 | return; |
5492 | } | |
5493 | ||
5494 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5495 | free (has_underbar ? opname - 1 : opname); | |
5496 | opname = 0; | |
5497 | while (num_args-- > 0) | |
5498 | free (arg_strings[num_args]); | |
5499 | ||
43cd72b9 BW |
5500 | /* Get expressions for invisible operands. */ |
5501 | if (get_invisible_operands (&orig_insn)) | |
5502 | { | |
5503 | error_reset_cur_vinsn (); | |
5504 | return; | |
5505 | } | |
5506 | ||
e0001a05 NC |
5507 | /* Check for the right number and type of arguments. */ |
5508 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5509 | { |
43cd72b9 BW |
5510 | error_reset_cur_vinsn (); |
5511 | return; | |
e0001a05 NC |
5512 | } |
5513 | ||
b224e962 BW |
5514 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5515 | spread across multiple input lines and individual instructions may be | |
5516 | moved around in some cases. */ | |
5517 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5518 | dwarf2_where (&orig_insn.debug_line); | |
5519 | dwarf2_consume_line_info (); | |
c138bc38 | 5520 | |
43cd72b9 BW |
5521 | xg_add_branch_and_loop_targets (&orig_insn); |
5522 | ||
431ad2d0 BW |
5523 | /* Check that immediate value for ENTRY is >= 16. */ |
5524 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5525 | { |
431ad2d0 BW |
5526 | expressionS *exp = &orig_insn.tok[2]; |
5527 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5528 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5529 | } |
5530 | ||
e0001a05 | 5531 | /* Finish it off: |
43cd72b9 BW |
5532 | assemble_tokens (opcode, tok, ntok); |
5533 | expand the tokens from the orig_insn into the | |
5534 | stack of instructions that will not expand | |
e0001a05 | 5535 | unless required at relaxation time. */ |
e0001a05 | 5536 | |
43cd72b9 BW |
5537 | if (!cur_vinsn.inside_bundle) |
5538 | emit_single_op (&orig_insn); | |
5539 | else /* We are inside a bundle. */ | |
e0001a05 | 5540 | { |
43cd72b9 BW |
5541 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5542 | cur_vinsn.num_slots++; | |
5543 | if (*input_line_pointer == '}' | |
5544 | || *(input_line_pointer - 1) == '}' | |
5545 | || *(input_line_pointer - 2) == '}') | |
5546 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5547 | } |
5548 | ||
43cd72b9 BW |
5549 | /* We've just emitted a new instruction so clear the list of labels. */ |
5550 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5551 | } |
5552 | ||
5553 | ||
43cd72b9 | 5554 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5555 | |
43cd72b9 BW |
5556 | /* For a .align directive, we mark the previous block with the alignment |
5557 | information. This will be placed in the object file in the | |
5558 | property section corresponding to this section. */ | |
e0001a05 | 5559 | |
43cd72b9 | 5560 | void |
7fa3d080 | 5561 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5562 | { |
5563 | if (linkrelax | |
b08b5071 | 5564 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5565 | && (fragP->fr_type == rs_align |
5566 | || fragP->fr_type == rs_align_code) | |
5567 | && fragP->fr_address + fragP->fr_fix > 0 | |
5568 | && fragP->fr_offset > 0 | |
5569 | && now_seg != bss_section) | |
e0001a05 | 5570 | { |
43cd72b9 BW |
5571 | fragP->tc_frag_data.is_align = TRUE; |
5572 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5573 | } |
5574 | ||
43cd72b9 | 5575 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5576 | { |
43cd72b9 BW |
5577 | int count; |
5578 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5579 | if (count != 0) | |
c138bc38 | 5580 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5581 | _("unaligned entry instruction")); |
e0001a05 | 5582 | } |
99ded152 BW |
5583 | |
5584 | if (linkrelax && fragP->fr_type == rs_org) | |
5585 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5586 | } |
43cd72b9 | 5587 | |
e0001a05 NC |
5588 | |
5589 | /* TC_FRAG_INIT hook */ | |
5590 | ||
5591 | void | |
7fa3d080 | 5592 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5593 | { |
43cd72b9 | 5594 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5595 | } |
5596 | ||
5597 | ||
5598 | symbolS * | |
7fa3d080 | 5599 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5600 | { |
5601 | return NULL; | |
5602 | } | |
5603 | ||
5604 | ||
5605 | /* Round up a section size to the appropriate boundary. */ | |
5606 | ||
5607 | valueT | |
7fa3d080 | 5608 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5609 | { |
5610 | return size; /* Byte alignment is fine. */ | |
5611 | } | |
5612 | ||
5613 | ||
5614 | long | |
7fa3d080 | 5615 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5616 | { |
5617 | char *insn_p; | |
5618 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5619 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5620 | int opnum; |
43cd72b9 | 5621 | uint32 opnd_value; |
e0001a05 | 5622 | xtensa_opcode opcode; |
43cd72b9 BW |
5623 | xtensa_format fmt; |
5624 | int slot; | |
e0001a05 NC |
5625 | xtensa_isa isa = xtensa_default_isa; |
5626 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5627 | bfd_boolean alt_reloc; |
e0001a05 | 5628 | |
e0001a05 | 5629 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5630 | return 0; |
e0001a05 | 5631 | |
1bbb5f21 BW |
5632 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5633 | return addr; | |
5634 | ||
e0001a05 | 5635 | if (!insnbuf) |
43cd72b9 BW |
5636 | { |
5637 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5638 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5639 | } | |
e0001a05 NC |
5640 | |
5641 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5642 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5643 | fmt = xtensa_format_decode (isa, insnbuf); |
5644 | ||
5645 | if (fmt == XTENSA_UNDEFINED) | |
5646 | as_fatal (_("bad instruction format")); | |
5647 | ||
5648 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5649 | as_fatal (_("invalid relocation")); | |
5650 | ||
5651 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5652 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5653 | ||
30f725a1 BW |
5654 | /* Check for "alternate" relocations (operand not specified). None |
5655 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5656 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5657 | { | |
5658 | if (opcode != xtensa_l32r_opcode | |
5659 | && opcode != xtensa_const16_opcode) | |
5660 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5661 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5662 | return 0; |
e0001a05 NC |
5663 | } |
5664 | ||
43cd72b9 BW |
5665 | opnum = get_relaxable_immed (opcode); |
5666 | opnd_value = 0; | |
5667 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5668 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5669 | { |
5670 | as_bad_where (fixP->fx_file, | |
5671 | fixP->fx_line, | |
5672 | _("invalid relocation for operand %d of '%s'"), | |
5673 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5674 | return 0; |
e0001a05 | 5675 | } |
43cd72b9 BW |
5676 | return 0 - opnd_value; |
5677 | } | |
5678 | ||
5679 | ||
5680 | /* TC_FORCE_RELOCATION hook */ | |
5681 | ||
5682 | int | |
7fa3d080 | 5683 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5684 | { |
5685 | switch (fix->fx_r_type) | |
30f725a1 BW |
5686 | { |
5687 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5688 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5689 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5690 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5691 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5692 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5693 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5694 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5695 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5696 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5697 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5698 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5699 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5700 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5701 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5702 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5703 | return 1; |
5704 | default: | |
5705 | break; | |
e0001a05 NC |
5706 | } |
5707 | ||
43cd72b9 BW |
5708 | if (linkrelax && fix->fx_addsy |
5709 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5710 | return 1; | |
5711 | ||
5712 | return generic_force_reloc (fix); | |
5713 | } | |
5714 | ||
5715 | ||
30f725a1 BW |
5716 | /* TC_VALIDATE_FIX_SUB hook */ |
5717 | ||
5718 | int | |
5719 | xtensa_validate_fix_sub (fixS *fix) | |
5720 | { | |
5721 | segT add_symbol_segment, sub_symbol_segment; | |
5722 | ||
5723 | /* The difference of two symbols should be resolved by the assembler when | |
5724 | linkrelax is not set. If the linker may relax the section containing | |
5725 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5726 | the linker knows to adjust the difference value. */ | |
5727 | if (!linkrelax || fix->fx_addsy == NULL) | |
5728 | return 0; | |
5729 | ||
5730 | /* Make sure both symbols are in the same segment, and that segment is | |
5731 | "normal" and relaxable. If the segment is not "normal", then the | |
5732 | fix is not valid. If the segment is not "relaxable", then the fix | |
5733 | should have been handled earlier. */ | |
5734 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5735 | if (! SEG_NORMAL (add_symbol_segment) || | |
5736 | ! relaxable_section (add_symbol_segment)) | |
5737 | return 0; | |
5738 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5739 | return (sub_symbol_segment == add_symbol_segment); | |
5740 | } | |
5741 | ||
5742 | ||
43cd72b9 BW |
5743 | /* NO_PSEUDO_DOT hook */ |
5744 | ||
5745 | /* This function has nothing to do with pseudo dots, but this is the | |
5746 | nearest macro to where the check needs to take place. FIXME: This | |
5747 | seems wrong. */ | |
5748 | ||
5749 | bfd_boolean | |
7fa3d080 | 5750 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5751 | { |
5752 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5753 | as_bad (_("directives are not valid inside bundles")); | |
5754 | ||
5755 | /* This function must always return FALSE because it is called via a | |
5756 | macro that has nothing to do with bundling. */ | |
5757 | return FALSE; | |
e0001a05 NC |
5758 | } |
5759 | ||
5760 | ||
43cd72b9 | 5761 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5762 | |
5763 | void | |
7fa3d080 | 5764 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5765 | { |
43cd72b9 BW |
5766 | /* Set up the assembly state. */ |
5767 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5768 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5769 | } |
5770 | ||
5771 | ||
5772 | /* tc_fix_adjustable hook */ | |
5773 | ||
5774 | bfd_boolean | |
7fa3d080 | 5775 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5776 | { |
43cd72b9 BW |
5777 | /* An offset is not allowed in combination with the difference of two |
5778 | symbols, but that cannot be easily detected after a local symbol | |
5779 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5780 | an fix will not be adjusted. */ | |
5781 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5782 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5783 | return 0; | |
5784 | ||
e0001a05 NC |
5785 | /* We need the symbol name for the VTABLE entries. */ |
5786 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5787 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5788 | return 0; | |
5789 | ||
5790 | return 1; | |
5791 | } | |
5792 | ||
5793 | ||
6a7eedfe BW |
5794 | /* tc_symbol_new_hook */ |
5795 | ||
5796 | symbolS *expr_symbols = NULL; | |
5797 | ||
5798 | void | |
5799 | xtensa_symbol_new_hook (symbolS *sym) | |
5800 | { | |
fb227da0 | 5801 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5802 | { |
5803 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5804 | expr_symbols = sym; | |
5805 | } | |
5806 | } | |
5807 | ||
5808 | ||
e0001a05 | 5809 | void |
55cf6793 | 5810 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5811 | { |
30f725a1 | 5812 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5813 | valueT val = 0; |
30f725a1 | 5814 | |
e7da6241 BW |
5815 | /* Subtracted symbols are only allowed for a few relocation types, and |
5816 | unless linkrelax is enabled, they should not make it to this point. */ | |
5817 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5818 | || fixP->fx_r_type == BFD_RELOC_16 | |
5819 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5820 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5821 | ||
30f725a1 | 5822 | switch (fixP->fx_r_type) |
e0001a05 | 5823 | { |
1bbb5f21 | 5824 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5825 | case BFD_RELOC_32: |
5826 | case BFD_RELOC_16: | |
5827 | case BFD_RELOC_8: | |
e7da6241 | 5828 | if (fixP->fx_subsy) |
30f725a1 BW |
5829 | { |
5830 | switch (fixP->fx_r_type) | |
5831 | { | |
5832 | case BFD_RELOC_8: | |
5833 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5834 | break; | |
5835 | case BFD_RELOC_16: | |
5836 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5837 | break; | |
5838 | case BFD_RELOC_32: | |
5839 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5840 | break; | |
5841 | default: | |
5842 | break; | |
5843 | } | |
e0001a05 | 5844 | |
30f725a1 BW |
5845 | /* An offset is only allowed when it results from adjusting a |
5846 | local symbol into a section-relative offset. If the offset | |
5847 | came from the original expression, tc_fix_adjustable will have | |
5848 | prevented the fix from being converted to a section-relative | |
5849 | form so that we can flag the error here. */ | |
5850 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5851 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5852 | _("cannot represent subtraction with an offset")); | |
5853 | ||
5854 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5855 | - S_GET_VALUE (fixP->fx_subsy)); | |
5856 | ||
5857 | /* The difference value gets written out, and the DIFF reloc | |
5858 | identifies the address of the subtracted symbol (i.e., the one | |
5859 | with the lowest address). */ | |
5860 | *valP = val; | |
5861 | fixP->fx_offset -= val; | |
5862 | fixP->fx_subsy = NULL; | |
5863 | } | |
5864 | else if (! fixP->fx_addsy) | |
e0001a05 | 5865 | { |
30f725a1 | 5866 | val = *valP; |
e0001a05 | 5867 | fixP->fx_done = 1; |
30f725a1 | 5868 | } |
d47d412e BW |
5869 | /* fall through */ |
5870 | ||
5871 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5872 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5873 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5874 | break; | |
e0001a05 | 5875 | |
28dbbc02 BW |
5876 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
5877 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
5878 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
5879 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
5880 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
5881 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
5882 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5883 | break; | |
5884 | ||
30f725a1 BW |
5885 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5886 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5887 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5888 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5889 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5890 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5891 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5892 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5893 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5894 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5895 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5896 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5897 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5898 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5899 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5900 | if (linkrelax) | |
5901 | { | |
5902 | /* Write the tentative value of a PC-relative relocation to a | |
5903 | local symbol into the instruction. The value will be ignored | |
5904 | by the linker, and it makes the object file disassembly | |
5905 | readable when all branch targets are encoded in relocations. */ | |
5906 | ||
9c2799c2 | 5907 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 5908 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5909 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5910 | { | |
5911 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5912 | - md_pcrel_from (fixP)); | |
5913 | (void) xg_apply_fix_value (fixP, val); | |
5914 | } | |
5915 | } | |
5916 | else if (! fixP->fx_addsy) | |
5917 | { | |
5918 | val = *valP; | |
5919 | if (xg_apply_fix_value (fixP, val)) | |
5920 | fixP->fx_done = 1; | |
5921 | } | |
5922 | break; | |
e0001a05 | 5923 | |
30f725a1 | 5924 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
5925 | case BFD_RELOC_XTENSA_TLS_FUNC: |
5926 | case BFD_RELOC_XTENSA_TLS_ARG: | |
5927 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
5928 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5929 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5930 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5931 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5932 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5933 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5934 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5935 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5936 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5937 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5938 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5939 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5940 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5941 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5942 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5943 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5944 | break; | |
e0001a05 | 5945 | |
30f725a1 BW |
5946 | case BFD_RELOC_VTABLE_INHERIT: |
5947 | case BFD_RELOC_VTABLE_ENTRY: | |
5948 | fixP->fx_done = 0; | |
5949 | break; | |
e0001a05 | 5950 | |
30f725a1 BW |
5951 | default: |
5952 | as_bad (_("unhandled local relocation fix %s"), | |
5953 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5954 | } |
5955 | } | |
5956 | ||
5957 | ||
5958 | char * | |
7fa3d080 | 5959 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 5960 | { |
499ac353 | 5961 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
5962 | } |
5963 | ||
5964 | ||
5965 | int | |
7fa3d080 | 5966 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5967 | { |
34e41783 | 5968 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5969 | } |
5970 | ||
5971 | ||
5972 | /* Translate internal representation of relocation info to BFD target | |
5973 | format. */ | |
5974 | ||
5975 | arelent * | |
30f725a1 | 5976 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5977 | { |
5978 | arelent *reloc; | |
5979 | ||
5980 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5981 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5982 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5983 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5984 | ||
5985 | /* Make sure none of our internal relocations make it this far. | |
5986 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 5987 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 5988 | |
30f725a1 | 5989 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5990 | |
e0001a05 NC |
5991 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5992 | if (reloc->howto == NULL) | |
5993 | { | |
5994 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5995 | _("cannot represent `%s' relocation in object file"), | |
5996 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5997 | free (reloc->sym_ptr_ptr); |
5998 | free (reloc); | |
e0001a05 NC |
5999 | return NULL; |
6000 | } | |
6001 | ||
6002 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 6003 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 6004 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 6005 | |
e0001a05 NC |
6006 | return reloc; |
6007 | } | |
6008 | ||
7fa3d080 BW |
6009 | \f |
6010 | /* Checks for resource conflicts between instructions. */ | |
6011 | ||
c138bc38 BW |
6012 | /* The func unit stuff could be implemented as bit-vectors rather |
6013 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6014 | slow, we will switch it. */ |
6015 | ||
c138bc38 | 6016 | resource_table * |
7fa3d080 BW |
6017 | new_resource_table (void *data, |
6018 | int cycles, | |
6019 | int nu, | |
6020 | unit_num_copies_func uncf, | |
6021 | opcode_num_units_func onuf, | |
6022 | opcode_funcUnit_use_unit_func ouuf, | |
6023 | opcode_funcUnit_use_stage_func ousf) | |
6024 | { | |
6025 | int i; | |
6026 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
6027 | rt->data = data; | |
6028 | rt->cycles = cycles; | |
6029 | rt->allocated_cycles = cycles; | |
6030 | rt->num_units = nu; | |
6031 | rt->unit_num_copies = uncf; | |
6032 | rt->opcode_num_units = onuf; | |
6033 | rt->opcode_unit_use = ouuf; | |
6034 | rt->opcode_unit_stage = ousf; | |
6035 | ||
0bf60745 | 6036 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 6037 | for (i = 0; i < cycles; i++) |
0bf60745 | 6038 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
6039 | |
6040 | return rt; | |
6041 | } | |
6042 | ||
6043 | ||
c138bc38 | 6044 | void |
7fa3d080 BW |
6045 | clear_resource_table (resource_table *rt) |
6046 | { | |
6047 | int i, j; | |
6048 | for (i = 0; i < rt->allocated_cycles; i++) | |
6049 | for (j = 0; j < rt->num_units; j++) | |
6050 | rt->units[i][j] = 0; | |
6051 | } | |
6052 | ||
6053 | ||
6054 | /* We never shrink it, just fake it into thinking so. */ | |
6055 | ||
c138bc38 | 6056 | void |
7fa3d080 BW |
6057 | resize_resource_table (resource_table *rt, int cycles) |
6058 | { | |
6059 | int i, old_cycles; | |
6060 | ||
6061 | rt->cycles = cycles; | |
6062 | if (cycles <= rt->allocated_cycles) | |
6063 | return; | |
6064 | ||
6065 | old_cycles = rt->allocated_cycles; | |
6066 | rt->allocated_cycles = cycles; | |
6067 | ||
0bf60745 BW |
6068 | rt->units = xrealloc (rt->units, |
6069 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 6070 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
6071 | rt->units[i] = xrealloc (rt->units[i], |
6072 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 6073 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 6074 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
6075 | } |
6076 | ||
6077 | ||
c138bc38 | 6078 | bfd_boolean |
7fa3d080 BW |
6079 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6080 | { | |
6081 | int i; | |
6082 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6083 | ||
c138bc38 | 6084 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6085 | { |
6086 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6087 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6088 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6089 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6090 | if (copies_in_use >= copies) | |
6091 | return FALSE; | |
6092 | } | |
6093 | return TRUE; | |
6094 | } | |
7fa3d080 | 6095 | |
c138bc38 BW |
6096 | |
6097 | void | |
7fa3d080 BW |
6098 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6099 | { | |
6100 | int i; | |
6101 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6102 | ||
c138bc38 | 6103 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6104 | { |
6105 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6106 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6107 | /* Note that this allows resources to be oversubscribed. That's |
6108 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6109 | resources_available reports when a resource is over-subscribed, |
6110 | so it's easy to tell. */ | |
6111 | rt->units[stage + cycle][unit]++; | |
6112 | } | |
6113 | } | |
6114 | ||
6115 | ||
c138bc38 | 6116 | void |
7fa3d080 BW |
6117 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6118 | { | |
6119 | int i; | |
6120 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6121 | ||
c138bc38 | 6122 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6123 | { |
6124 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6125 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6126 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6127 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6128 | } |
6129 | } | |
c138bc38 | 6130 | |
7fa3d080 BW |
6131 | |
6132 | /* Wrapper functions make parameterized resource reservation | |
6133 | more convenient. */ | |
6134 | ||
c138bc38 | 6135 | int |
7fa3d080 BW |
6136 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6137 | { | |
6138 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6139 | return use->unit; |
7fa3d080 BW |
6140 | } |
6141 | ||
6142 | ||
c138bc38 | 6143 | int |
7fa3d080 BW |
6144 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6145 | { | |
6146 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6147 | return use->stage; | |
6148 | } | |
6149 | ||
6150 | ||
6151 | /* Note that this function does not check issue constraints, but | |
6152 | solely whether the hardware is available to execute the given | |
c138bc38 | 6153 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6154 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6155 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6156 | |
6157 | static bfd_boolean | |
6158 | resources_conflict (vliw_insn *vinsn) | |
6159 | { | |
6160 | int i; | |
6161 | static resource_table *rt = NULL; | |
6162 | ||
6163 | /* This is the most common case by far. Optimize it. */ | |
6164 | if (vinsn->num_slots == 1) | |
6165 | return FALSE; | |
43cd72b9 | 6166 | |
c138bc38 | 6167 | if (rt == NULL) |
7fa3d080 BW |
6168 | { |
6169 | xtensa_isa isa = xtensa_default_isa; | |
6170 | rt = new_resource_table | |
77cba8a3 | 6171 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6172 | xtensa_isa_num_funcUnits (isa), |
6173 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6174 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6175 | opcode_funcUnit_use_unit, | |
6176 | opcode_funcUnit_use_stage); | |
6177 | } | |
43cd72b9 | 6178 | |
7fa3d080 | 6179 | clear_resource_table (rt); |
43cd72b9 | 6180 | |
7fa3d080 BW |
6181 | for (i = 0; i < vinsn->num_slots; i++) |
6182 | { | |
6183 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6184 | return TRUE; | |
6185 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6186 | } | |
e0001a05 | 6187 | |
7fa3d080 BW |
6188 | return FALSE; |
6189 | } | |
e0001a05 | 6190 | |
7fa3d080 BW |
6191 | \f |
6192 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6193 | |
7fa3d080 BW |
6194 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6195 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6196 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6197 | |
6198 | ||
43cd72b9 BW |
6199 | /* We have reached the end of a bundle; emit into the frag. */ |
6200 | ||
e0001a05 | 6201 | static void |
7fa3d080 | 6202 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6203 | { |
43cd72b9 BW |
6204 | IStack slotstack; |
6205 | int i; | |
6206 | char *file_name; | |
d77b99c9 | 6207 | unsigned line; |
e0001a05 | 6208 | |
43cd72b9 | 6209 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6210 | { |
6211 | xg_clear_vinsn (vinsn); | |
6212 | return; | |
6213 | } | |
43cd72b9 BW |
6214 | |
6215 | /* First, find a format that works. */ | |
6216 | if (vinsn->format == XTENSA_UNDEFINED) | |
6217 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6218 | ||
19fc3723 SA |
6219 | if (xtensa_format_num_slots (xtensa_default_isa, vinsn->format) > 1 |
6220 | && produce_flix == FLIX_NONE) | |
6221 | { | |
6222 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6223 | xg_clear_vinsn (vinsn); | |
6224 | return; | |
6225 | } | |
6226 | ||
43cd72b9 BW |
6227 | if (vinsn->format == XTENSA_UNDEFINED) |
6228 | { | |
6229 | as_where (&file_name, &line); | |
6230 | as_bad_where (file_name, line, | |
6231 | _("couldn't find a valid instruction format")); | |
6232 | fprintf (stderr, _(" ops were: ")); | |
6233 | for (i = 0; i < vinsn->num_slots; i++) | |
6234 | fprintf (stderr, _(" %s;"), | |
6235 | xtensa_opcode_name (xtensa_default_isa, | |
6236 | vinsn->slots[i].opcode)); | |
6237 | fprintf (stderr, _("\n")); | |
6238 | xg_clear_vinsn (vinsn); | |
6239 | return; | |
6240 | } | |
6241 | ||
6242 | if (vinsn->num_slots | |
6243 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6244 | { |
43cd72b9 BW |
6245 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6246 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6247 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6248 | vinsn->num_slots); | |
6249 | xg_clear_vinsn (vinsn); | |
6250 | return; | |
6251 | } | |
e0001a05 | 6252 | |
c138bc38 | 6253 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6254 | { |
6255 | as_where (&file_name, &line); | |
6256 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6257 | fprintf (stderr, " ops were: "); | |
6258 | for (i = 0; i < vinsn->num_slots; i++) | |
6259 | fprintf (stderr, " %s;", | |
6260 | xtensa_opcode_name (xtensa_default_isa, | |
6261 | vinsn->slots[i].opcode)); | |
6262 | fprintf (stderr, "\n"); | |
6263 | xg_clear_vinsn (vinsn); | |
6264 | return; | |
6265 | } | |
6266 | ||
6267 | for (i = 0; i < vinsn->num_slots; i++) | |
6268 | { | |
6269 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6270 | { |
43cd72b9 BW |
6271 | symbolS *lit_sym = NULL; |
6272 | int j; | |
6273 | bfd_boolean e = FALSE; | |
6274 | bfd_boolean saved_density = density_supported; | |
6275 | ||
6276 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6277 | if (vinsn->num_slots > 1) | |
6278 | density_supported = FALSE; | |
6279 | ||
6280 | istack_init (&slotstack); | |
6281 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6282 | { |
43cd72b9 BW |
6283 | vinsn->slots[i].opcode = |
6284 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6285 | vinsn->format, i); | |
6286 | vinsn->slots[i].ntok = 0; | |
6287 | } | |
e0001a05 | 6288 | |
43cd72b9 BW |
6289 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6290 | { | |
6291 | e = TRUE; | |
6292 | continue; | |
e0001a05 | 6293 | } |
e0001a05 | 6294 | |
43cd72b9 | 6295 | density_supported = saved_density; |
e0001a05 | 6296 | |
43cd72b9 BW |
6297 | if (e) |
6298 | { | |
6299 | xg_clear_vinsn (vinsn); | |
6300 | return; | |
6301 | } | |
e0001a05 | 6302 | |
0fa77c95 | 6303 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6304 | { |
6305 | TInsn *insn = &slotstack.insn[j]; | |
6306 | if (insn->insn_type == ITYPE_LITERAL) | |
6307 | { | |
9c2799c2 | 6308 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6309 | lit_sym = xg_assemble_literal (insn); |
6310 | } | |
6311 | else | |
6312 | { | |
9c2799c2 | 6313 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6314 | if (lit_sym) |
6315 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6316 | if (j != slotstack.ninsn - 1) |
6317 | emit_single_op (insn); | |
43cd72b9 BW |
6318 | } |
6319 | } | |
6320 | ||
6321 | if (vinsn->num_slots > 1) | |
6322 | { | |
6323 | if (opcode_fits_format_slot | |
6324 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6325 | vinsn->format, i)) | |
6326 | { | |
6327 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6328 | } | |
6329 | else | |
6330 | { | |
b2d179be | 6331 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6332 | if (vinsn->format == XTENSA_UNDEFINED) |
6333 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6334 | else | |
c138bc38 | 6335 | vinsn->slots[i].opcode |
43cd72b9 BW |
6336 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6337 | vinsn->format, i); | |
6338 | ||
6339 | vinsn->slots[i].ntok = 0; | |
6340 | } | |
6341 | } | |
6342 | else | |
6343 | { | |
6344 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6345 | vinsn->format = XTENSA_UNDEFINED; | |
6346 | } | |
6347 | } | |
6348 | } | |
6349 | ||
6350 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6351 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6352 | { |
6353 | as_where (&file_name, &line); | |
6354 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6355 | fprintf (stderr, " ops were: "); | |
6356 | for (i = 0; i < vinsn->num_slots; i++) | |
6357 | fprintf (stderr, " %s;", | |
6358 | xtensa_opcode_name (xtensa_default_isa, | |
6359 | vinsn->slots[i].opcode)); | |
6360 | fprintf (stderr, "\n"); | |
6361 | xg_clear_vinsn (vinsn); | |
6362 | return; | |
6363 | } | |
6364 | ||
6365 | /* First, find a format that works. */ | |
6366 | if (vinsn->format == XTENSA_UNDEFINED) | |
6367 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6368 | ||
6369 | xg_assemble_vliw_tokens (vinsn); | |
6370 | ||
6371 | xg_clear_vinsn (vinsn); | |
6372 | } | |
6373 | ||
6374 | ||
6375 | /* Given an vliw instruction, what conflicts are there in register | |
6376 | usage and in writes to states and queues? | |
6377 | ||
6378 | This function does two things: | |
6379 | 1. Reports an error when a vinsn contains illegal combinations | |
6380 | of writes to registers states or queues. | |
6381 | 2. Marks individual tinsns as not relaxable if the combination | |
6382 | contains antidependencies. | |
6383 | ||
6384 | Job 2 handles things like swap semantics in instructions that need | |
6385 | to be relaxed. For example, | |
6386 | ||
6387 | addi a0, a1, 100000 | |
6388 | ||
6389 | normally would be relaxed to | |
6390 | ||
6391 | l32r a0, some_label | |
6392 | add a0, a1, a0 | |
6393 | ||
6394 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6395 | ||
6396 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6397 | ||
6398 | then we can't relax it into | |
6399 | ||
6400 | l32r a0, some_label | |
6401 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6402 | ||
6403 | because the value of a0 is trashed before the second add can read it. */ | |
6404 | ||
7fa3d080 BW |
6405 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6406 | ||
43cd72b9 | 6407 | static bfd_boolean |
7fa3d080 | 6408 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6409 | { |
6410 | int i, j; | |
6411 | int branches = 0; | |
6412 | xtensa_isa isa = xtensa_default_isa; | |
6413 | ||
9c2799c2 | 6414 | gas_assert (!past_xtensa_end); |
43cd72b9 BW |
6415 | |
6416 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6417 | { | |
6418 | TInsn *op1 = &vinsn->slots[i]; | |
6419 | if (op1->is_specific_opcode) | |
6420 | op1->keep_wide = TRUE; | |
6421 | else | |
6422 | op1->keep_wide = FALSE; | |
6423 | } | |
6424 | ||
6425 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6426 | { | |
6427 | TInsn *op1 = &vinsn->slots[i]; | |
6428 | ||
6429 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6430 | branches++; | |
6431 | ||
6432 | for (j = 0; j < vinsn->num_slots; j++) | |
6433 | { | |
6434 | if (i != j) | |
6435 | { | |
6436 | TInsn *op2 = &vinsn->slots[j]; | |
6437 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6438 | switch (conflict_type) | |
6439 | { | |
6440 | case 'c': | |
6441 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6442 | xtensa_opcode_name (isa, op1->opcode), i, | |
6443 | xtensa_opcode_name (isa, op2->opcode), j); | |
6444 | return TRUE; | |
6445 | case 'd': | |
6446 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6447 | xtensa_opcode_name (isa, op1->opcode), i, | |
6448 | xtensa_opcode_name (isa, op2->opcode), j); | |
6449 | return TRUE; | |
6450 | case 'e': | |
53dfbcc7 | 6451 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6452 | xtensa_opcode_name (isa, op1->opcode), i, |
6453 | xtensa_opcode_name (isa, op2->opcode), j); | |
6454 | return TRUE; | |
6455 | case 'f': | |
53dfbcc7 | 6456 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6457 | xtensa_opcode_name (isa, op1->opcode), i, |
6458 | xtensa_opcode_name (isa, op2->opcode), j); | |
6459 | return TRUE; | |
6460 | default: | |
6461 | /* Everything is OK. */ | |
6462 | break; | |
6463 | } | |
6464 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6465 | || conflict_type == 'a'); | |
6466 | } | |
6467 | } | |
6468 | } | |
6469 | ||
6470 | if (branches > 1) | |
6471 | { | |
6472 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6473 | return TRUE; | |
6474 | } | |
6475 | ||
6476 | return FALSE; | |
6477 | } | |
6478 | ||
6479 | ||
a1ace8d8 | 6480 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6481 | Cases found are: |
6482 | ||
6483 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6484 | case B: no relationship between what is read and written (both could | |
6485 | read the same reg though) | |
c138bc38 | 6486 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6487 | bundle) |
6488 | case D: t1 writes a state that t2 also writes | |
6489 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6490 | case F: two volatile queue accesses |
43cd72b9 BW |
6491 | */ |
6492 | ||
6493 | static char | |
7fa3d080 | 6494 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6495 | { |
6496 | xtensa_isa isa = xtensa_default_isa; | |
6497 | xtensa_regfile t1_regfile, t2_regfile; | |
6498 | int t1_reg, t2_reg; | |
6499 | int t1_base_reg, t1_last_reg; | |
6500 | int t2_base_reg, t2_last_reg; | |
6501 | char t1_inout, t2_inout; | |
6502 | int i, j; | |
6503 | char conflict = 'b'; | |
6504 | int t1_states; | |
6505 | int t2_states; | |
6506 | int t1_interfaces; | |
6507 | int t2_interfaces; | |
6508 | bfd_boolean t1_volatile = FALSE; | |
6509 | bfd_boolean t2_volatile = FALSE; | |
6510 | ||
6511 | /* Check registers. */ | |
6512 | for (j = 0; j < t2->ntok; j++) | |
6513 | { | |
6514 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6515 | continue; | |
6516 | ||
6517 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6518 | t2_base_reg = t2->tok[j].X_add_number; | |
6519 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6520 | ||
6521 | for (i = 0; i < t1->ntok; i++) | |
6522 | { | |
6523 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6524 | continue; | |
6525 | ||
6526 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6527 | ||
6528 | if (t1_regfile != t2_regfile) | |
6529 | continue; | |
6530 | ||
6531 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6532 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6533 | ||
6534 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6535 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6536 | { | |
6537 | if (t1_inout == 'm' || t1_inout == 'o' | |
6538 | || t2_inout == 'm' || t2_inout == 'o') | |
6539 | { | |
6540 | conflict = 'a'; | |
6541 | continue; | |
6542 | } | |
6543 | } | |
6544 | ||
6545 | t1_base_reg = t1->tok[i].X_add_number; | |
6546 | t1_last_reg = (t1_base_reg | |
6547 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6548 | ||
6549 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6550 | { | |
6551 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6552 | { | |
6553 | if (t1_reg != t2_reg) | |
6554 | continue; | |
6555 | ||
6556 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6557 | { |
6558 | conflict = 'a'; | |
6559 | continue; | |
6560 | } | |
43cd72b9 | 6561 | |
7fa3d080 BW |
6562 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6563 | { | |
6564 | conflict = 'a'; | |
6565 | continue; | |
6566 | } | |
43cd72b9 | 6567 | |
7fa3d080 BW |
6568 | if (t1_inout != 'i' && t2_inout != 'i') |
6569 | return 'c'; | |
6570 | } | |
6571 | } | |
6572 | } | |
6573 | } | |
43cd72b9 | 6574 | |
7fa3d080 BW |
6575 | /* Check states. */ |
6576 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6577 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6578 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6579 | { |
7fa3d080 BW |
6580 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6581 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6582 | for (i = 0; i < t1_states; i++) | |
6583 | { | |
6584 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6585 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6586 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6587 | continue; |
43cd72b9 | 6588 | |
7fa3d080 BW |
6589 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6590 | { | |
6591 | conflict = 'a'; | |
6592 | continue; | |
6593 | } | |
c138bc38 | 6594 | |
7fa3d080 BW |
6595 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6596 | { | |
6597 | conflict = 'a'; | |
6598 | continue; | |
6599 | } | |
c138bc38 | 6600 | |
7fa3d080 BW |
6601 | if (t1_inout != 'i' && t2_inout != 'i') |
6602 | return 'd'; | |
c138bc38 | 6603 | } |
7fa3d080 | 6604 | } |
43cd72b9 | 6605 | |
7fa3d080 BW |
6606 | /* Check tieports. */ |
6607 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6608 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6609 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6610 | { |
7fa3d080 BW |
6611 | xtensa_interface t2_int |
6612 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6613 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6614 | ||
53dfbcc7 | 6615 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6616 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6617 | t2_volatile = TRUE; |
a1ace8d8 | 6618 | |
7fa3d080 BW |
6619 | for (i = 0; i < t1_interfaces; i++) |
6620 | { | |
6621 | xtensa_interface t1_int | |
6622 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6623 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6624 | |
53dfbcc7 | 6625 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6626 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6627 | t1_volatile = TRUE; |
a1ace8d8 BW |
6628 | |
6629 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6630 | return 'f'; | |
c138bc38 | 6631 | |
7fa3d080 BW |
6632 | if (t1_int != t2_int) |
6633 | continue; | |
c138bc38 | 6634 | |
7fa3d080 BW |
6635 | if (t2_inout == 'i' && t1_inout == 'o') |
6636 | { | |
6637 | conflict = 'a'; | |
6638 | continue; | |
6639 | } | |
c138bc38 | 6640 | |
7fa3d080 BW |
6641 | if (t1_inout == 'i' && t2_inout == 'o') |
6642 | { | |
6643 | conflict = 'a'; | |
6644 | continue; | |
6645 | } | |
c138bc38 | 6646 | |
7fa3d080 BW |
6647 | if (t1_inout != 'i' && t2_inout != 'i') |
6648 | return 'e'; | |
6649 | } | |
43cd72b9 | 6650 | } |
c138bc38 | 6651 | |
7fa3d080 | 6652 | return conflict; |
43cd72b9 BW |
6653 | } |
6654 | ||
6655 | ||
6656 | static xtensa_format | |
7fa3d080 | 6657 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6658 | { |
6659 | /* Right now we assume that the ops within the vinsn are properly | |
6660 | ordered for the slots that the programmer wanted them in. In | |
6661 | other words, we don't rearrange the ops in hopes of finding a | |
6662 | better format. The scheduler handles that. */ | |
6663 | ||
6664 | xtensa_isa isa = xtensa_default_isa; | |
6665 | xtensa_format format; | |
43cd72b9 BW |
6666 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6667 | ||
65738a7d BW |
6668 | if (vinsn->num_slots == 1) |
6669 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6670 | ||
43cd72b9 BW |
6671 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6672 | { | |
d8392fd9 SA |
6673 | vliw_insn v_copy; |
6674 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6675 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6676 | { | |
6677 | int slot; | |
6678 | int fit = 0; | |
6679 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6680 | { | |
6681 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6682 | { | |
6683 | v_copy.slots[slot].opcode = | |
6684 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6685 | v_copy.slots[slot].ntok = 0; | |
6686 | } | |
6687 | ||
6688 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6689 | format, slot)) | |
6690 | fit++; | |
7fa3d080 | 6691 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6692 | { |
7fa3d080 BW |
6693 | TInsn widened; |
6694 | /* Try the widened version. */ | |
6695 | if (!v_copy.slots[slot].keep_wide | |
6696 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6697 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6698 | &widened, TRUE) | |
7fa3d080 BW |
6699 | && opcode_fits_format_slot (widened.opcode, |
6700 | format, slot)) | |
43cd72b9 | 6701 | { |
7fa3d080 BW |
6702 | v_copy.slots[slot] = widened; |
6703 | fit++; | |
43cd72b9 BW |
6704 | } |
6705 | } | |
6706 | } | |
6707 | if (fit == v_copy.num_slots) | |
6708 | { | |
d8392fd9 | 6709 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6710 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6711 | vinsn->format = format; | |
6712 | break; | |
6713 | } | |
6714 | } | |
6715 | } | |
6716 | ||
6717 | if (format == xtensa_isa_num_formats (isa)) | |
6718 | return XTENSA_UNDEFINED; | |
6719 | ||
6720 | return format; | |
6721 | } | |
6722 | ||
6723 | ||
6724 | /* Return the additional space needed in a frag | |
6725 | for possible relaxations of any ops in a VLIW insn. | |
6726 | Also fill out the relaxations that might be required of | |
6727 | each tinsn in the vinsn. */ | |
6728 | ||
6729 | static int | |
e7da6241 | 6730 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6731 | { |
e7da6241 | 6732 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6733 | int extra_space = 0; |
6734 | int slot; | |
6735 | ||
6736 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6737 | { | |
6738 | TInsn *tinsn = &vinsn->slots[slot]; | |
6739 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6740 | { | |
6741 | /* A narrow instruction could be widened later to help | |
6742 | alignment issues. */ | |
84b08ed9 | 6743 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6744 | && !tinsn->is_specific_opcode |
6745 | && vinsn->num_slots == 1) | |
6746 | { | |
6747 | /* Difference in bytes between narrow and wide insns... */ | |
6748 | extra_space += 1; | |
6749 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6750 | } |
6751 | } | |
6752 | else | |
6753 | { | |
b08b5071 BW |
6754 | if (workaround_b_j_loop_end |
6755 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6756 | && use_transform ()) |
6757 | { | |
6758 | /* Add 2 of these. */ | |
6759 | extra_space += 3; /* for the nop size */ | |
6760 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6761 | } | |
c138bc38 | 6762 | |
43cd72b9 BW |
6763 | /* Need to assemble it with space for the relocation. */ |
6764 | if (xg_is_relaxable_insn (tinsn, 0) | |
6765 | && !tinsn->is_specific_opcode) | |
6766 | { | |
6767 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6768 | int max_literal_size = | |
6769 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6770 | |
43cd72b9 | 6771 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6772 | |
43cd72b9 | 6773 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6774 | extra_space += max_size; |
6775 | } | |
6776 | else | |
6777 | { | |
e7da6241 BW |
6778 | /* A fix record will be added for this instruction prior |
6779 | to relaxation, so make it end the frag. */ | |
6780 | finish_frag = TRUE; | |
43cd72b9 BW |
6781 | } |
6782 | } | |
6783 | } | |
e7da6241 | 6784 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6785 | return extra_space; |
6786 | } | |
6787 | ||
6788 | ||
6789 | static void | |
b2d179be | 6790 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6791 | { |
6792 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6793 | int slot, chosen_slot; |
43cd72b9 | 6794 | |
b2d179be | 6795 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6796 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6797 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6798 | |
b2d179be BW |
6799 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6800 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6801 | { |
b2d179be BW |
6802 | if (slot == chosen_slot) |
6803 | vinsn->slots[slot] = *tinsn; | |
6804 | else | |
6805 | { | |
6806 | vinsn->slots[slot].opcode = | |
6807 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6808 | vinsn->slots[slot].ntok = 0; | |
6809 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6810 | } | |
43cd72b9 | 6811 | } |
43cd72b9 BW |
6812 | } |
6813 | ||
6814 | ||
6815 | static bfd_boolean | |
7fa3d080 | 6816 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6817 | { |
6818 | int i; | |
6819 | IStack istack; /* put instructions into here */ | |
6820 | symbolS *lit_sym = NULL; | |
6821 | symbolS *label_sym = NULL; | |
6822 | ||
6823 | istack_init (&istack); | |
6824 | ||
6825 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6826 | Because the scheduling and bundling characteristics of movi and |
6827 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6828 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6829 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6830 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6831 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6832 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
6833 | || orig_insn->tok[1].X_op == O_pltrel |
6834 | || orig_insn->tok[1].X_op == O_tlsfunc | |
6835 | || orig_insn->tok[1].X_op == O_tlsarg | |
6836 | || orig_insn->tok[1].X_op == O_tpoff | |
6837 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 6838 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
6839 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6840 | else | |
6841 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6842 | return TRUE; | |
6843 | ||
6844 | for (i = 0; i < istack.ninsn; i++) | |
6845 | { | |
6846 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6847 | switch (insn->insn_type) |
43cd72b9 BW |
6848 | { |
6849 | case ITYPE_LITERAL: | |
9c2799c2 | 6850 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6851 | lit_sym = xg_assemble_literal (insn); |
6852 | break; | |
6853 | case ITYPE_LABEL: | |
6854 | { | |
6855 | static int relaxed_sym_idx = 0; | |
6856 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6857 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6858 | colon (label); | |
9c2799c2 | 6859 | gas_assert (label_sym == NULL); |
43cd72b9 | 6860 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 6861 | gas_assert (label_sym); |
43cd72b9 BW |
6862 | free (label); |
6863 | } | |
6864 | break; | |
6865 | case ITYPE_INSN: | |
b2d179be BW |
6866 | { |
6867 | vliw_insn v; | |
6868 | if (lit_sym) | |
6869 | xg_resolve_literals (insn, lit_sym); | |
6870 | if (label_sym) | |
6871 | xg_resolve_labels (insn, label_sym); | |
6872 | xg_init_vinsn (&v); | |
6873 | bundle_tinsn (insn, &v); | |
6874 | finish_vinsn (&v); | |
6875 | xg_free_vinsn (&v); | |
6876 | } | |
43cd72b9 BW |
6877 | break; |
6878 | default: | |
9c2799c2 | 6879 | gas_assert (0); |
43cd72b9 BW |
6880 | break; |
6881 | } | |
6882 | } | |
6883 | return FALSE; | |
6884 | } | |
6885 | ||
6886 | ||
34e41783 BW |
6887 | static int |
6888 | total_frag_text_expansion (fragS *fragP) | |
6889 | { | |
6890 | int slot; | |
6891 | int total_expansion = 0; | |
6892 | ||
62af60e2 | 6893 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
6894 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
6895 | ||
6896 | return total_expansion; | |
6897 | } | |
6898 | ||
6899 | ||
43cd72b9 BW |
6900 | /* Emit a vliw instruction to the current fragment. */ |
6901 | ||
7fa3d080 BW |
6902 | static void |
6903 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6904 | { |
e7da6241 | 6905 | bfd_boolean finish_frag; |
43cd72b9 BW |
6906 | bfd_boolean is_jump = FALSE; |
6907 | bfd_boolean is_branch = FALSE; | |
6908 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
6909 | int insn_size; |
6910 | int extra_space; | |
6911 | char *f = NULL; | |
6912 | int slot; | |
b224e962 BW |
6913 | struct dwarf2_line_info debug_line; |
6914 | bfd_boolean loc_directive_seen = FALSE; | |
6915 | TInsn *tinsn; | |
43cd72b9 | 6916 | |
b224e962 | 6917 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
6918 | |
6919 | if (generating_literals) | |
6920 | { | |
6921 | static int reported = 0; | |
6922 | if (reported < 4) | |
6923 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6924 | _("cannot assemble into a literal fragment")); | |
6925 | if (reported == 3) | |
6926 | as_bad (_("...")); | |
6927 | reported++; | |
6928 | return; | |
6929 | } | |
6930 | ||
6931 | if (frag_now_fix () != 0 | |
b08b5071 | 6932 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6933 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6934 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6935 | || (directive_state[directive_longcalls] |
6936 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6937 | || (directive_state[directive_absolute_literals] |
6938 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6939 | { | |
6940 | frag_wane (frag_now); | |
6941 | frag_new (0); | |
6942 | xtensa_set_frag_assembly_state (frag_now); | |
6943 | } | |
6944 | ||
6945 | if (workaround_a0_b_retw | |
6946 | && vinsn->num_slots == 1 | |
6947 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6948 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6949 | && use_transform ()) | |
6950 | { | |
6951 | has_a0_b_retw = TRUE; | |
6952 | ||
6953 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6954 | After the first assembly pass we will check all of them and | |
6955 | add a nop if needed. */ | |
6956 | frag_now->tc_frag_data.is_insn = TRUE; | |
6957 | frag_var (rs_machine_dependent, 4, 4, | |
6958 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6959 | frag_now->fr_symbol, | |
6960 | frag_now->fr_offset, | |
6961 | NULL); | |
6962 | xtensa_set_frag_assembly_state (frag_now); | |
6963 | frag_now->tc_frag_data.is_insn = TRUE; | |
6964 | frag_var (rs_machine_dependent, 4, 4, | |
6965 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6966 | frag_now->fr_symbol, | |
6967 | frag_now->fr_offset, | |
6968 | NULL); | |
6969 | xtensa_set_frag_assembly_state (frag_now); | |
6970 | } | |
6971 | ||
b224e962 | 6972 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 6973 | { |
b224e962 BW |
6974 | tinsn = &vinsn->slots[slot]; |
6975 | ||
43cd72b9 | 6976 | /* See if the instruction implies an aligned section. */ |
b224e962 | 6977 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 6978 | record_alignment (now_seg, 2); |
c138bc38 | 6979 | |
b224e962 BW |
6980 | /* Determine the best line number for debug info. */ |
6981 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
6982 | && (tinsn->debug_line.filenum != debug_line.filenum | |
6983 | || tinsn->debug_line.line < debug_line.line | |
6984 | || tinsn->debug_line.column < debug_line.column)) | |
6985 | debug_line = tinsn->debug_line; | |
6986 | if (tinsn->loc_directive_seen) | |
6987 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
6988 | } |
6989 | ||
6990 | /* Special cases for instructions that force an alignment... */ | |
6991 | /* None of these opcodes are bundle-able. */ | |
6992 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6993 | { | |
d77b99c9 | 6994 | int max_fill; |
c138bc38 | 6995 | |
05d58145 BW |
6996 | /* Remember the symbol that marks the end of the loop in the frag |
6997 | that marks the start of the loop. This way we can easily find | |
6998 | the end of the loop at the beginning, without adding special code | |
6999 | to mark the loop instructions themselves. */ | |
7000 | symbolS *target_sym = NULL; | |
7001 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
7002 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
7003 | ||
43cd72b9 BW |
7004 | xtensa_set_frag_assembly_state (frag_now); |
7005 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 7006 | |
43cd72b9 BW |
7007 | max_fill = get_text_align_max_fill_size |
7008 | (get_text_align_power (xtensa_fetch_width), | |
7009 | TRUE, frag_now->tc_frag_data.is_no_density); | |
7010 | ||
7011 | if (use_transform ()) | |
7012 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7013 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7014 | else |
c138bc38 | 7015 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7016 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7017 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7018 | } |
7019 | ||
b08b5071 | 7020 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7021 | && !vinsn->slots[0].is_specific_opcode) |
7022 | { | |
7023 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7024 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7025 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7026 | } | |
7027 | ||
7028 | if (vinsn->num_slots == 1) | |
7029 | { | |
7030 | if (workaround_a0_b_retw && use_transform ()) | |
7031 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7032 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7033 | ||
7034 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7035 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7036 | } | |
7037 | else | |
7038 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
7039 | ||
7040 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7041 | ||
e7da6241 | 7042 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7043 | |
7044 | /* vinsn_to_insnbuf will produce the error. */ | |
7045 | if (vinsn->format != XTENSA_UNDEFINED) | |
7046 | { | |
d77b99c9 | 7047 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7048 | xtensa_set_frag_assembly_state (frag_now); |
7049 | frag_now->tc_frag_data.is_insn = TRUE; | |
7050 | } | |
7051 | ||
e7da6241 | 7052 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7053 | if (vinsn->format == XTENSA_UNDEFINED) |
7054 | return; | |
7055 | ||
d77b99c9 | 7056 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7057 | |
b224e962 BW |
7058 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7059 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7060 | &debug_line); | |
43cd72b9 BW |
7061 | |
7062 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7063 | { | |
b224e962 | 7064 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7065 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7066 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7067 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
7068 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
7069 | if (tinsn->literal_space != 0) | |
7070 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7071 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7072 | |
7073 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7074 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 BW |
7075 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
7076 | is_jump = TRUE; | |
7077 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7078 | is_branch = TRUE; | |
7079 | ||
e7da6241 BW |
7080 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7081 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7082 | finish_frag = TRUE; |
7083 | } | |
7084 | ||
7085 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7086 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7087 | |
7088 | if (finish_frag) | |
7089 | { | |
7090 | frag_variant (rs_machine_dependent, | |
7091 | extra_space, extra_space, RELAX_SLOTS, | |
7092 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7093 | xtensa_set_frag_assembly_state (frag_now); | |
7094 | } | |
7095 | ||
7096 | /* Special cases for loops: | |
7097 | close_loop_end should be inserted AFTER short_loop. | |
7098 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7099 | when converting them. */ | |
7100 | ||
7101 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7102 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7103 | && !vinsn->slots[0].is_specific_opcode) |
7104 | { | |
7105 | if (workaround_short_loop && use_transform ()) | |
7106 | { | |
7107 | maybe_has_short_loop = TRUE; | |
7108 | frag_now->tc_frag_data.is_insn = TRUE; | |
7109 | frag_var (rs_machine_dependent, 4, 4, | |
7110 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7111 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7112 | frag_now->tc_frag_data.is_insn = TRUE; | |
7113 | frag_var (rs_machine_dependent, 4, 4, | |
7114 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7115 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7116 | } | |
7117 | ||
7118 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7119 | loop at least 12 bytes away from another loop's end. */ | |
7120 | if (workaround_close_loop_end && use_transform ()) | |
7121 | { | |
7122 | maybe_has_close_loop_end = TRUE; | |
7123 | frag_now->tc_frag_data.is_insn = TRUE; | |
7124 | frag_var (rs_machine_dependent, 12, 12, | |
7125 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7126 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7127 | } | |
7128 | } | |
7129 | ||
7130 | if (use_transform ()) | |
7131 | { | |
7132 | if (is_jump) | |
7133 | { | |
9c2799c2 | 7134 | gas_assert (finish_frag); |
43cd72b9 BW |
7135 | frag_var (rs_machine_dependent, |
7136 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
7137 | RELAX_UNREACHABLE, | |
7138 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7139 | xtensa_set_frag_assembly_state (frag_now); | |
7140 | } | |
7b1cc377 | 7141 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7142 | { |
9c2799c2 | 7143 | gas_assert (finish_frag); |
43cd72b9 BW |
7144 | frag_var (rs_machine_dependent, |
7145 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
7146 | RELAX_MAYBE_UNREACHABLE, | |
7147 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7148 | xtensa_set_frag_assembly_state (frag_now); | |
7149 | frag_var (rs_machine_dependent, | |
7150 | 0, 0, | |
7151 | RELAX_MAYBE_DESIRE_ALIGN, | |
7152 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7153 | xtensa_set_frag_assembly_state (frag_now); | |
7154 | } | |
7155 | } | |
7156 | ||
7157 | /* Now, if the original opcode was a call... */ | |
7158 | if (do_align_targets () | |
7159 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7160 | { | |
b08b5071 | 7161 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7162 | frag_now->tc_frag_data.is_insn = TRUE; |
7163 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7164 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7165 | xtensa_set_frag_assembly_state (frag_now); | |
7166 | } | |
7167 | ||
7168 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7169 | { | |
7170 | frag_wane (frag_now); | |
7171 | frag_new (0); | |
7172 | xtensa_set_frag_assembly_state (frag_now); | |
7173 | } | |
7174 | } | |
7175 | ||
7176 | \f | |
7fa3d080 BW |
7177 | /* xtensa_end and helper functions. */ |
7178 | ||
7179 | static void xtensa_cleanup_align_frags (void); | |
7180 | static void xtensa_fix_target_frags (void); | |
7181 | static void xtensa_mark_narrow_branches (void); | |
7182 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7183 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7184 | static void xtensa_fix_a0_b_retw_frags (void); |
7185 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7186 | static void xtensa_fix_close_loop_end_frags (void); | |
7187 | static void xtensa_fix_short_loop_frags (void); | |
7188 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7189 | static void xtensa_add_config_info (void); |
7fa3d080 | 7190 | |
43cd72b9 | 7191 | void |
7fa3d080 | 7192 | xtensa_end (void) |
43cd72b9 BW |
7193 | { |
7194 | directive_balance (); | |
7195 | xtensa_flush_pending_output (); | |
7196 | ||
7197 | past_xtensa_end = TRUE; | |
7198 | ||
7199 | xtensa_move_literals (); | |
7200 | ||
7201 | xtensa_reorder_segments (); | |
7202 | xtensa_cleanup_align_frags (); | |
7203 | xtensa_fix_target_frags (); | |
7204 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7205 | xtensa_fix_a0_b_retw_frags (); | |
7206 | if (workaround_b_j_loop_end) | |
7207 | xtensa_fix_b_j_loop_end_frags (); | |
7208 | ||
7209 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7210 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7211 | xtensa_fix_close_loop_end_frags (); | |
7212 | ||
7213 | if (workaround_short_loop && maybe_has_short_loop) | |
7214 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7215 | if (align_targets) |
7216 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7217 | xtensa_mark_zcl_first_insns (); |
7218 | ||
7219 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7220 | |
7221 | xtensa_add_config_info (); | |
43cd72b9 BW |
7222 | } |
7223 | ||
7224 | ||
7225 | static void | |
7fa3d080 | 7226 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7227 | { |
7228 | frchainS *frchP; | |
c9049d30 | 7229 | asection *s; |
43cd72b9 | 7230 | |
c9049d30 AM |
7231 | for (s = stdoutput->sections; s; s = s->next) |
7232 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7233 | { | |
7234 | fragS *fragP; | |
7235 | /* Walk over all of the fragments in a subsection. */ | |
7236 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7237 | { | |
7238 | if ((fragP->fr_type == rs_align | |
7239 | || fragP->fr_type == rs_align_code | |
7240 | || (fragP->fr_type == rs_machine_dependent | |
7241 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7242 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7243 | && fragP->fr_fix == 0) | |
7244 | { | |
7245 | fragS *next = fragP->fr_next; | |
7246 | ||
7247 | while (next | |
7248 | && next->fr_fix == 0 | |
7249 | && next->fr_type == rs_machine_dependent | |
7250 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7251 | { | |
7252 | frag_wane (next); | |
7253 | next = next->fr_next; | |
7254 | } | |
7255 | } | |
7256 | /* If we don't widen branch targets, then they | |
7257 | will be easier to align. */ | |
7258 | if (fragP->tc_frag_data.is_branch_target | |
7259 | && fragP->fr_opcode == fragP->fr_literal | |
7260 | && fragP->fr_type == rs_machine_dependent | |
7261 | && fragP->fr_subtype == RELAX_SLOTS | |
7262 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7263 | frag_wane (fragP); | |
7264 | if (fragP->fr_type == rs_machine_dependent | |
7265 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7266 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7267 | } | |
7268 | } | |
43cd72b9 BW |
7269 | } |
7270 | ||
7271 | ||
7272 | /* Re-process all of the fragments looking to convert all of the | |
7273 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7274 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7275 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7276 | |
43cd72b9 | 7277 | static void |
7fa3d080 | 7278 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7279 | { |
7280 | frchainS *frchP; | |
c9049d30 | 7281 | asection *s; |
e0001a05 NC |
7282 | |
7283 | /* When this routine is called, all of the subsections are still intact | |
7284 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7285 | for (s = stdoutput->sections; s; s = s->next) |
7286 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7287 | { | |
7288 | fragS *fragP; | |
e0001a05 | 7289 | |
c9049d30 AM |
7290 | /* Walk over all of the fragments in a subsection. */ |
7291 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7292 | { | |
7293 | if (fragP->fr_type == rs_machine_dependent | |
7294 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7295 | { | |
7296 | if (next_frag_is_branch_target (fragP)) | |
7297 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7298 | else | |
7299 | frag_wane (fragP); | |
7300 | } | |
7301 | } | |
7302 | } | |
e0001a05 NC |
7303 | } |
7304 | ||
7305 | ||
7fa3d080 BW |
7306 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7307 | ||
43cd72b9 | 7308 | static void |
7fa3d080 | 7309 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7310 | { |
7311 | frchainS *frchP; | |
c9049d30 | 7312 | asection *s; |
43cd72b9 | 7313 | |
c9049d30 AM |
7314 | for (s = stdoutput->sections; s; s = s->next) |
7315 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7316 | { | |
7317 | fragS *fragP; | |
7318 | /* Walk over all of the fragments in a subsection. */ | |
7319 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7320 | { | |
7321 | if (fragP->fr_type == rs_machine_dependent | |
7322 | && fragP->fr_subtype == RELAX_SLOTS | |
7323 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7324 | { | |
7325 | vliw_insn vinsn; | |
7326 | ||
7327 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7328 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7329 | ||
7330 | if (vinsn.num_slots == 1 | |
7331 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7332 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7333 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7334 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7335 | &vinsn.slots[0])) | |
7336 | { | |
7337 | fragP->fr_subtype = RELAX_SLOTS; | |
7338 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7339 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7340 | } | |
7341 | } | |
7342 | } | |
7343 | } | |
43cd72b9 BW |
7344 | } |
7345 | ||
7346 | ||
7347 | /* A branch is typically widened only when its target is out of | |
7348 | range. However, we would like to widen them to align a subsequent | |
7349 | branch target when possible. | |
7350 | ||
7351 | Because the branch relaxation code is so convoluted, the optimal solution | |
7352 | (combining the two cases) is difficult to get right in all circumstances. | |
7353 | We therefore go with an "almost as good" solution, where we only | |
7354 | use for alignment narrow branches that definitely will not expand to a | |
7355 | jump and a branch. These functions find and mark these cases. */ | |
7356 | ||
a67517f4 BW |
7357 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7358 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7359 | We start counting beginning with the frag after the 2-byte branch, so the | |
7360 | maximum offset is (4 - 2) + 63 = 65. */ | |
7361 | #define MAX_IMMED6 65 | |
43cd72b9 | 7362 | |
d77b99c9 | 7363 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7364 | |
43cd72b9 | 7365 | static bfd_boolean |
7fa3d080 | 7366 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7367 | { |
7368 | const expressionS *expr = &tinsn->tok[1]; | |
7369 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7370 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7371 | fragS *target_frag; |
7372 | ||
7373 | if (expr->X_op != O_symbol) | |
7374 | return FALSE; | |
7375 | ||
7376 | target_frag = symbol_get_frag (symbolP); | |
7377 | ||
43cd72b9 BW |
7378 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7379 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7380 | return FALSE; | |
7381 | ||
7382 | /* The branch doesn't branch over it's own frag, | |
7383 | but over the subsequent ones. */ | |
7384 | fragP = fragP->fr_next; | |
7385 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7386 | { | |
7387 | max_distance += unrelaxed_frag_max_size (fragP); | |
7388 | fragP = fragP->fr_next; | |
7389 | } | |
7390 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7391 | return TRUE; | |
e0001a05 NC |
7392 | return FALSE; |
7393 | } | |
7394 | ||
7395 | ||
43cd72b9 | 7396 | static void |
7fa3d080 | 7397 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7398 | { |
7399 | frchainS *frchP; | |
c9049d30 | 7400 | asection *s; |
43cd72b9 | 7401 | |
c9049d30 AM |
7402 | for (s = stdoutput->sections; s; s = s->next) |
7403 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7404 | { | |
7405 | fragS *fragP; | |
7406 | /* Walk over all of the fragments in a subsection. */ | |
7407 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7408 | { | |
7409 | if (fragP->fr_type == rs_machine_dependent | |
7410 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7411 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7412 | { | |
7413 | /* Find the loop frag. */ | |
7414 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7415 | /* Find the first insn frag. */ | |
7416 | targ_frag = next_non_empty_frag (targ_frag); | |
7417 | ||
7418 | /* Of course, sometimes (mostly for toy test cases) a | |
7419 | zero-cost loop instruction is the last in a section. */ | |
7420 | if (targ_frag) | |
7421 | { | |
7422 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7423 | /* Do not widen a frag that is the first instruction of a | |
7424 | zero-cost loop. It makes that loop harder to align. */ | |
7425 | if (targ_frag->fr_type == rs_machine_dependent | |
7426 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7427 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7428 | == RELAX_NARROW)) | |
7429 | { | |
7430 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7431 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7432 | else | |
7433 | { | |
7434 | frag_wane (targ_frag); | |
7435 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7436 | } | |
7437 | } | |
7438 | } | |
7439 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7440 | frag_wane (fragP); | |
7441 | } | |
7442 | } | |
7443 | } | |
43cd72b9 BW |
7444 | } |
7445 | ||
7446 | ||
fb227da0 BW |
7447 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
7448 | sleb128 value, the linker is unable to adjust that value to account for | |
7449 | link-time relaxation. Mark all the code between such symbols so that | |
7450 | its size cannot be changed by linker relaxation. */ | |
7451 | ||
6a7eedfe BW |
7452 | static void |
7453 | xtensa_mark_difference_of_two_symbols (void) | |
7454 | { | |
7455 | symbolS *expr_sym; | |
7456 | ||
7457 | for (expr_sym = expr_symbols; expr_sym; | |
7458 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) | |
7459 | { | |
7460 | expressionS *expr = symbol_get_value_expression (expr_sym); | |
7461 | ||
7462 | if (expr->X_op == O_subtract) | |
7463 | { | |
7464 | symbolS *left = expr->X_add_symbol; | |
7465 | symbolS *right = expr->X_op_symbol; | |
7466 | ||
7467 | /* Difference of two symbols not in the same section | |
7468 | are handled with relocations in the linker. */ | |
7469 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7470 | { | |
7471 | fragS *start; | |
7472 | fragS *end; | |
983f90e3 | 7473 | fragS *walk; |
6a7eedfe BW |
7474 | |
7475 | if (symbol_get_frag (left)->fr_address | |
7476 | <= symbol_get_frag (right)->fr_address) | |
7477 | { | |
7478 | start = symbol_get_frag (left); | |
7479 | end = symbol_get_frag (right); | |
7480 | } | |
7481 | else | |
7482 | { | |
7483 | start = symbol_get_frag (right); | |
7484 | end = symbol_get_frag (left); | |
7485 | } | |
983f90e3 SA |
7486 | |
7487 | if (start->tc_frag_data.no_transform_end != NULL) | |
7488 | walk = start->tc_frag_data.no_transform_end; | |
7489 | else | |
7490 | walk = start; | |
6a7eedfe BW |
7491 | do |
7492 | { | |
983f90e3 SA |
7493 | walk->tc_frag_data.is_no_transform = 1; |
7494 | walk = walk->fr_next; | |
6a7eedfe | 7495 | } |
983f90e3 SA |
7496 | while (walk && walk->fr_address < end->fr_address); |
7497 | ||
7498 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
7499 | } |
7500 | } | |
7501 | } | |
7502 | } | |
7503 | ||
7504 | ||
e0001a05 NC |
7505 | /* Re-process all of the fragments looking to convert all of the |
7506 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7507 | conditional branch or a retw/retw.n, convert this frag to one that | |
7508 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7509 | ||
7fa3d080 BW |
7510 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7511 | ||
e0001a05 | 7512 | static void |
7fa3d080 | 7513 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7514 | { |
7515 | frchainS *frchP; | |
c9049d30 | 7516 | asection *s; |
e0001a05 NC |
7517 | |
7518 | /* When this routine is called, all of the subsections are still intact | |
7519 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7520 | for (s = stdoutput->sections; s; s = s->next) |
7521 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7522 | { | |
7523 | fragS *fragP; | |
e0001a05 | 7524 | |
c9049d30 AM |
7525 | /* Walk over all of the fragments in a subsection. */ |
7526 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7527 | { | |
7528 | if (fragP->fr_type == rs_machine_dependent | |
7529 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7530 | { | |
7531 | if (next_instrs_are_b_retw (fragP)) | |
7532 | { | |
7533 | if (fragP->tc_frag_data.is_no_transform) | |
7534 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7535 | else | |
7536 | relax_frag_add_nop (fragP); | |
7537 | } | |
7538 | frag_wane (fragP); | |
7539 | } | |
7540 | } | |
7541 | } | |
e0001a05 NC |
7542 | } |
7543 | ||
7544 | ||
7fa3d080 BW |
7545 | static bfd_boolean |
7546 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7547 | { |
7548 | xtensa_opcode opcode; | |
43cd72b9 | 7549 | xtensa_format fmt; |
e0001a05 NC |
7550 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7551 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7552 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7553 | xtensa_isa isa = xtensa_default_isa; |
7554 | int offset = 0; | |
43cd72b9 BW |
7555 | int slot; |
7556 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7557 | |
7558 | if (!insnbuf) | |
43cd72b9 BW |
7559 | { |
7560 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7561 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7562 | } | |
e0001a05 NC |
7563 | |
7564 | if (next_fragP == NULL) | |
7565 | return FALSE; | |
7566 | ||
7567 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7568 | xtensa_insnbuf_from_chars |
7569 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7570 | fmt = xtensa_format_decode (isa, insnbuf); |
7571 | if (fmt == XTENSA_UNDEFINED) | |
7572 | return FALSE; | |
7573 | ||
7574 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7575 | { | |
7576 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7577 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7578 | ||
7579 | branch_seen = (branch_seen | |
7580 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7581 | } | |
e0001a05 | 7582 | |
43cd72b9 | 7583 | if (!branch_seen) |
e0001a05 NC |
7584 | return FALSE; |
7585 | ||
43cd72b9 | 7586 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7587 | if (offset == next_fragP->fr_fix) |
7588 | { | |
7589 | next_fragP = next_non_empty_frag (next_fragP); | |
7590 | offset = 0; | |
7591 | } | |
43cd72b9 | 7592 | |
e0001a05 NC |
7593 | if (next_fragP == NULL) |
7594 | return FALSE; | |
7595 | ||
7596 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7597 | xtensa_insnbuf_from_chars |
7598 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7599 | fmt = xtensa_format_decode (isa, insnbuf); |
7600 | ||
7601 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7602 | have no problems. */ | |
7603 | if (fmt == XTENSA_UNDEFINED | |
7604 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7605 | return FALSE; | |
7606 | ||
7607 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7608 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7609 | |
b08b5071 | 7610 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7611 | return TRUE; |
43cd72b9 | 7612 | |
e0001a05 NC |
7613 | return FALSE; |
7614 | } | |
7615 | ||
7616 | ||
7617 | /* Re-process all of the fragments looking to convert all of the | |
7618 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7619 | loop end label, convert this frag to one that will generate a NOP. | |
7620 | In any case close it off with a .fill 0. */ | |
7621 | ||
7fa3d080 BW |
7622 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7623 | ||
e0001a05 | 7624 | static void |
7fa3d080 | 7625 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7626 | { |
7627 | frchainS *frchP; | |
c9049d30 | 7628 | asection *s; |
e0001a05 NC |
7629 | |
7630 | /* When this routine is called, all of the subsections are still intact | |
7631 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7632 | for (s = stdoutput->sections; s; s = s->next) |
7633 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7634 | { | |
7635 | fragS *fragP; | |
e0001a05 | 7636 | |
c9049d30 AM |
7637 | /* Walk over all of the fragments in a subsection. */ |
7638 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7639 | { | |
7640 | if (fragP->fr_type == rs_machine_dependent | |
7641 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7642 | { | |
7643 | if (next_instr_is_loop_end (fragP)) | |
7644 | { | |
7645 | if (fragP->tc_frag_data.is_no_transform) | |
7646 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7647 | else | |
7648 | relax_frag_add_nop (fragP); | |
7649 | } | |
7650 | frag_wane (fragP); | |
7651 | } | |
7652 | } | |
7653 | } | |
e0001a05 NC |
7654 | } |
7655 | ||
7656 | ||
7fa3d080 BW |
7657 | static bfd_boolean |
7658 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7659 | { |
7660 | const fragS *next_fragP; | |
7661 | ||
7662 | if (next_frag_is_loop_target (fragP)) | |
7663 | return FALSE; | |
7664 | ||
7665 | next_fragP = next_non_empty_frag (fragP); | |
7666 | if (next_fragP == NULL) | |
7667 | return FALSE; | |
7668 | ||
7669 | if (!next_frag_is_loop_target (next_fragP)) | |
7670 | return FALSE; | |
7671 | ||
7672 | /* If the size is >= 3 then there is more than one instruction here. | |
7673 | The hardware bug will not fire. */ | |
7674 | if (next_fragP->fr_fix > 3) | |
7675 | return FALSE; | |
7676 | ||
7677 | return TRUE; | |
7678 | } | |
7679 | ||
7680 | ||
7681 | /* Re-process all of the fragments looking to convert all of the | |
7682 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7683 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7684 | make it at least 12 bytes away. In any case close it off with a | |
7685 | .fill 0. */ | |
7686 | ||
d77b99c9 | 7687 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7688 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7689 | |
e0001a05 | 7690 | static void |
7fa3d080 | 7691 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7692 | { |
7693 | frchainS *frchP; | |
c9049d30 | 7694 | asection *s; |
e0001a05 NC |
7695 | |
7696 | /* When this routine is called, all of the subsections are still intact | |
7697 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7698 | for (s = stdoutput->sections; s; s = s->next) |
7699 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7700 | { | |
7701 | fragS *fragP; | |
e0001a05 | 7702 | |
c9049d30 | 7703 | fragS *current_target = NULL; |
e0001a05 | 7704 | |
c9049d30 AM |
7705 | /* Walk over all of the fragments in a subsection. */ |
7706 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7707 | { | |
7708 | if (fragP->fr_type == rs_machine_dependent | |
7709 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7710 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7711 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7712 | |
c9049d30 AM |
7713 | if (current_target |
7714 | && fragP->fr_type == rs_machine_dependent | |
7715 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7716 | { | |
7717 | offsetT min_bytes; | |
7718 | int bytes_added = 0; | |
e0001a05 NC |
7719 | |
7720 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7721 | /* Max out at 12. */ |
7722 | min_bytes = min_bytes_to_other_loop_end | |
7723 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7724 | ||
7725 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7726 | { | |
7727 | if (fragP->tc_frag_data.is_no_transform) | |
7728 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7729 | else | |
7730 | { | |
7731 | while (min_bytes + bytes_added | |
7732 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7733 | { | |
7734 | int length = 3; | |
7735 | ||
7736 | if (fragP->fr_var < length) | |
7737 | as_fatal (_("fr_var %lu < length %d"), | |
7738 | (long) fragP->fr_var, length); | |
7739 | else | |
7740 | { | |
7741 | assemble_nop (length, | |
7742 | fragP->fr_literal + fragP->fr_fix); | |
7743 | fragP->fr_fix += length; | |
7744 | fragP->fr_var -= length; | |
7745 | } | |
7746 | bytes_added += length; | |
7747 | } | |
7748 | } | |
7749 | } | |
7750 | frag_wane (fragP); | |
7751 | } | |
9c2799c2 | 7752 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
7753 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
7754 | } | |
7755 | } | |
e0001a05 NC |
7756 | } |
7757 | ||
7758 | ||
d77b99c9 | 7759 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7760 | |
d77b99c9 | 7761 | static offsetT |
7fa3d080 BW |
7762 | min_bytes_to_other_loop_end (fragS *fragP, |
7763 | fragS *current_target, | |
d77b99c9 | 7764 | offsetT max_size) |
e0001a05 | 7765 | { |
d77b99c9 | 7766 | offsetT offset = 0; |
e0001a05 NC |
7767 | fragS *current_fragP; |
7768 | ||
7769 | for (current_fragP = fragP; | |
7770 | current_fragP; | |
7771 | current_fragP = current_fragP->fr_next) | |
7772 | { | |
7773 | if (current_fragP->tc_frag_data.is_loop_target | |
7774 | && current_fragP != current_target) | |
05d58145 | 7775 | return offset; |
e0001a05 NC |
7776 | |
7777 | offset += unrelaxed_frag_min_size (current_fragP); | |
7778 | ||
05d58145 | 7779 | if (offset >= max_size) |
e0001a05 NC |
7780 | return max_size; |
7781 | } | |
7782 | return max_size; | |
7783 | } | |
7784 | ||
7785 | ||
d77b99c9 | 7786 | static offsetT |
7fa3d080 | 7787 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7788 | { |
d77b99c9 | 7789 | offsetT size = fragP->fr_fix; |
e0001a05 | 7790 | |
d77b99c9 | 7791 | /* Add fill size. */ |
e0001a05 NC |
7792 | if (fragP->fr_type == rs_fill) |
7793 | size += fragP->fr_offset; | |
7794 | ||
7795 | return size; | |
7796 | } | |
7797 | ||
7798 | ||
d77b99c9 | 7799 | static offsetT |
7fa3d080 | 7800 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7801 | { |
d77b99c9 | 7802 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7803 | switch (fragP->fr_type) |
7804 | { | |
7805 | case 0: | |
c138bc38 | 7806 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7807 | end up with type 0. */ |
7808 | break; | |
7809 | case rs_fill: | |
7810 | case rs_org: | |
7811 | case rs_space: | |
7812 | size += fragP->fr_offset; | |
7813 | break; | |
7814 | case rs_align: | |
7815 | case rs_align_code: | |
7816 | case rs_align_test: | |
7817 | case rs_leb128: | |
7818 | case rs_cfa: | |
7819 | case rs_dwarf2dbg: | |
7820 | /* No further adjustments needed. */ | |
7821 | break; | |
7822 | case rs_machine_dependent: | |
7823 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7824 | size += fragP->fr_var; | |
7825 | break; | |
7826 | default: | |
7827 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 7828 | gas_assert (0); |
43cd72b9 BW |
7829 | break; |
7830 | } | |
7831 | ||
7832 | return size; | |
7833 | } | |
7834 | ||
7835 | ||
e0001a05 NC |
7836 | /* Re-process all of the fragments looking to convert all |
7837 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7838 | ||
7839 | A) | |
7840 | 1) the instruction size count to the loop end label | |
7841 | is too short (<= 2 instructions), | |
7842 | 2) loop has a jump or branch in it | |
7843 | ||
7844 | or B) | |
43cd72b9 | 7845 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7846 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7847 | 3) the instruction size count to the loop end label is too short | |
7848 | (<= 2 instructions) | |
7849 | then convert this frag (and maybe the next one) to generate a NOP. | |
7850 | In any case close it off with a .fill 0. */ | |
7851 | ||
d77b99c9 | 7852 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7853 | static bfd_boolean branch_before_loop_end (fragS *); |
7854 | ||
e0001a05 | 7855 | static void |
7fa3d080 | 7856 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7857 | { |
7858 | frchainS *frchP; | |
c9049d30 | 7859 | asection *s; |
e0001a05 NC |
7860 | |
7861 | /* When this routine is called, all of the subsections are still intact | |
7862 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7863 | for (s = stdoutput->sections; s; s = s->next) |
7864 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7865 | { | |
7866 | fragS *fragP; | |
7867 | fragS *current_target = NULL; | |
7868 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7869 | |
c9049d30 AM |
7870 | /* Walk over all of the fragments in a subsection. */ |
7871 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7872 | { | |
7873 | if (fragP->fr_type == rs_machine_dependent | |
7874 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7875 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7876 | { | |
7877 | TInsn t_insn; | |
7878 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7879 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7880 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7881 | current_opcode = t_insn.opcode; | |
9c2799c2 | 7882 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 7883 | current_opcode) == 1); |
c9049d30 | 7884 | } |
e0001a05 | 7885 | |
c9049d30 AM |
7886 | if (fragP->fr_type == rs_machine_dependent |
7887 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7888 | { | |
7889 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7890 | && (branch_before_loop_end (fragP->fr_next) | |
7891 | || (workaround_all_short_loops | |
7892 | && current_opcode != XTENSA_UNDEFINED | |
7893 | && current_opcode != xtensa_loop_opcode))) | |
7894 | { | |
7895 | if (fragP->tc_frag_data.is_no_transform) | |
7896 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7897 | else | |
7898 | relax_frag_add_nop (fragP); | |
7899 | } | |
7900 | frag_wane (fragP); | |
7901 | } | |
7902 | } | |
7903 | } | |
e0001a05 NC |
7904 | } |
7905 | ||
7906 | ||
d77b99c9 | 7907 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7908 | |
d77b99c9 | 7909 | static int |
7fa3d080 BW |
7910 | count_insns_to_loop_end (fragS *base_fragP, |
7911 | bfd_boolean count_relax_add, | |
d77b99c9 | 7912 | int max_count) |
e0001a05 NC |
7913 | { |
7914 | fragS *fragP = NULL; | |
d77b99c9 | 7915 | int insn_count = 0; |
e0001a05 NC |
7916 | |
7917 | fragP = base_fragP; | |
7918 | ||
7919 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7920 | { | |
7921 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7922 | if (insn_count >= max_count) | |
7923 | return max_count; | |
7924 | ||
7925 | if (count_relax_add) | |
7926 | { | |
7927 | if (fragP->fr_type == rs_machine_dependent | |
7928 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7929 | { | |
7930 | /* In order to add the appropriate number of | |
7931 | NOPs, we count an instruction for downstream | |
7932 | occurrences. */ | |
7933 | insn_count++; | |
7934 | if (insn_count >= max_count) | |
7935 | return max_count; | |
7936 | } | |
7937 | } | |
7938 | } | |
7939 | return insn_count; | |
7940 | } | |
7941 | ||
7942 | ||
d77b99c9 | 7943 | static int |
7fa3d080 | 7944 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7945 | { |
43cd72b9 BW |
7946 | xtensa_isa isa = xtensa_default_isa; |
7947 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7948 | int insn_count = 0; |
e0001a05 NC |
7949 | int offset = 0; |
7950 | ||
7951 | if (!fragP->tc_frag_data.is_insn) | |
7952 | return insn_count; | |
7953 | ||
43cd72b9 BW |
7954 | if (!insnbuf) |
7955 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7956 | ||
e0001a05 NC |
7957 | /* Decode the fixed instructions. */ |
7958 | while (offset < fragP->fr_fix) | |
7959 | { | |
43cd72b9 BW |
7960 | xtensa_format fmt; |
7961 | ||
d77b99c9 BW |
7962 | xtensa_insnbuf_from_chars |
7963 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7964 | fmt = xtensa_format_decode (isa, insnbuf); |
7965 | ||
7966 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7967 | { |
7968 | as_fatal (_("undecodable instruction in instruction frag")); | |
7969 | return insn_count; | |
7970 | } | |
43cd72b9 | 7971 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7972 | insn_count++; |
7973 | } | |
7974 | ||
7975 | return insn_count; | |
7976 | } | |
7977 | ||
7978 | ||
7fa3d080 BW |
7979 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7980 | ||
43cd72b9 | 7981 | static bfd_boolean |
7fa3d080 | 7982 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7983 | { |
7984 | fragS *fragP; | |
7985 | ||
7986 | for (fragP = base_fragP; | |
7987 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7988 | fragP = fragP->fr_next) | |
7989 | { | |
7990 | if (unrelaxed_frag_has_b_j (fragP)) | |
7991 | return TRUE; | |
7992 | } | |
7993 | return FALSE; | |
7994 | } | |
7995 | ||
7996 | ||
43cd72b9 | 7997 | static bfd_boolean |
7fa3d080 | 7998 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7999 | { |
43cd72b9 BW |
8000 | static xtensa_insnbuf insnbuf = NULL; |
8001 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8002 | int offset = 0; |
8003 | ||
8004 | if (!fragP->tc_frag_data.is_insn) | |
8005 | return FALSE; | |
8006 | ||
43cd72b9 BW |
8007 | if (!insnbuf) |
8008 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8009 | ||
e0001a05 NC |
8010 | /* Decode the fixed instructions. */ |
8011 | while (offset < fragP->fr_fix) | |
8012 | { | |
43cd72b9 BW |
8013 | xtensa_format fmt; |
8014 | int slot; | |
8015 | ||
d77b99c9 BW |
8016 | xtensa_insnbuf_from_chars |
8017 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8018 | fmt = xtensa_format_decode (isa, insnbuf); |
8019 | if (fmt == XTENSA_UNDEFINED) | |
8020 | return FALSE; | |
8021 | ||
8022 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8023 | { |
43cd72b9 BW |
8024 | xtensa_opcode opcode = |
8025 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8026 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8027 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
8028 | return TRUE; | |
e0001a05 | 8029 | } |
43cd72b9 | 8030 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8031 | } |
8032 | return FALSE; | |
8033 | } | |
8034 | ||
8035 | ||
8036 | /* Checks to be made after initial assembly but before relaxation. */ | |
8037 | ||
7fa3d080 BW |
8038 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
8039 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
8040 | ||
e0001a05 | 8041 | static void |
7fa3d080 | 8042 | xtensa_sanity_check (void) |
e0001a05 NC |
8043 | { |
8044 | char *file_name; | |
d77b99c9 | 8045 | unsigned line; |
e0001a05 | 8046 | frchainS *frchP; |
c9049d30 | 8047 | asection *s; |
e0001a05 NC |
8048 | |
8049 | as_where (&file_name, &line); | |
c9049d30 AM |
8050 | for (s = stdoutput->sections; s; s = s->next) |
8051 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8052 | { | |
8053 | fragS *fragP; | |
e0001a05 | 8054 | |
c9049d30 AM |
8055 | /* Walk over all of the fragments in a subsection. */ |
8056 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8057 | { | |
c9049d30 | 8058 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
8059 | && fragP->fr_subtype == RELAX_SLOTS |
8060 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
8061 | { |
8062 | static xtensa_insnbuf insnbuf = NULL; | |
8063 | TInsn t_insn; | |
8064 | ||
8065 | if (fragP->fr_opcode != NULL) | |
8066 | { | |
8067 | if (!insnbuf) | |
8068 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8069 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8070 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8071 | ||
8072 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8073 | t_insn.opcode) == 1) | |
8074 | { | |
8075 | if (is_empty_loop (&t_insn, fragP)) | |
8076 | { | |
8077 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8078 | as_bad (_("invalid empty loop")); | |
8079 | } | |
8080 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8081 | { | |
8082 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8083 | as_bad (_("loop target does not follow " | |
8084 | "loop instruction in section")); | |
8085 | } | |
8086 | } | |
8087 | } | |
8088 | } | |
8089 | } | |
8090 | } | |
e0001a05 NC |
8091 | new_logical_line (file_name, line); |
8092 | } | |
8093 | ||
8094 | ||
8095 | #define LOOP_IMMED_OPN 1 | |
8096 | ||
43cd72b9 | 8097 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8098 | |
7fa3d080 BW |
8099 | static bfd_boolean |
8100 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
8101 | { |
8102 | const expressionS *expr; | |
8103 | symbolS *symbolP; | |
8104 | fragS *next_fragP; | |
8105 | ||
8106 | if (insn->insn_type != ITYPE_INSN) | |
8107 | return FALSE; | |
8108 | ||
43cd72b9 | 8109 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8110 | return FALSE; |
8111 | ||
8112 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8113 | return FALSE; | |
8114 | ||
8115 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
8116 | ||
8117 | if (expr->X_op != O_symbol) | |
8118 | return FALSE; | |
8119 | ||
8120 | symbolP = expr->X_add_symbol; | |
8121 | if (!symbolP) | |
8122 | return FALSE; | |
8123 | ||
8124 | if (symbol_get_frag (symbolP) == NULL) | |
8125 | return FALSE; | |
8126 | ||
8127 | if (S_GET_VALUE (symbolP) != 0) | |
8128 | return FALSE; | |
8129 | ||
8130 | /* Walk through the zero-size fragments from this one. If we find | |
8131 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8132 | |
e0001a05 NC |
8133 | for (next_fragP = fragP->fr_next; |
8134 | next_fragP != NULL; | |
8135 | next_fragP = next_fragP->fr_next) | |
8136 | { | |
8137 | if (next_fragP == symbol_get_frag (symbolP)) | |
8138 | return TRUE; | |
8139 | if (next_fragP->fr_fix != 0) | |
8140 | return FALSE; | |
8141 | } | |
8142 | return FALSE; | |
8143 | } | |
8144 | ||
8145 | ||
7fa3d080 BW |
8146 | static bfd_boolean |
8147 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
8148 | { |
8149 | const expressionS *expr; | |
8150 | symbolS *symbolP; | |
8151 | fragS *next_fragP; | |
8152 | ||
8153 | if (insn->insn_type != ITYPE_INSN) | |
8154 | return FALSE; | |
8155 | ||
64b607e6 | 8156 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8157 | return FALSE; |
8158 | ||
8159 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8160 | return FALSE; | |
8161 | ||
8162 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
8163 | ||
8164 | if (expr->X_op != O_symbol) | |
8165 | return FALSE; | |
8166 | ||
8167 | symbolP = expr->X_add_symbol; | |
8168 | if (!symbolP) | |
8169 | return FALSE; | |
8170 | ||
8171 | if (symbol_get_frag (symbolP) == NULL) | |
8172 | return FALSE; | |
8173 | ||
8174 | /* Walk through fragments until we find the target. | |
8175 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8176 | |
e0001a05 NC |
8177 | for (next_fragP = fragP->fr_next; |
8178 | next_fragP != NULL; | |
8179 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8180 | { |
8181 | if (next_fragP == symbol_get_frag (symbolP)) | |
8182 | return TRUE; | |
8183 | } | |
e0001a05 NC |
8184 | |
8185 | return FALSE; | |
8186 | } | |
8187 | ||
2caa7ca0 BW |
8188 | |
8189 | #define XTINFO_NAME "Xtensa_Info" | |
8190 | #define XTINFO_NAMESZ 12 | |
8191 | #define XTINFO_TYPE 1 | |
8192 | ||
8193 | static void | |
8194 | xtensa_add_config_info (void) | |
8195 | { | |
8196 | asection *info_sec; | |
8197 | char *data, *p; | |
8198 | int sz; | |
8199 | ||
8200 | info_sec = subseg_new (".xtensa.info", 0); | |
8201 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8202 | ||
8203 | data = xmalloc (100); | |
8204 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
8205 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8206 | sz = strlen (data) + 1; | |
8207 | ||
8208 | /* Add enough null terminators to pad to a word boundary. */ | |
8209 | do | |
8210 | data[sz++] = 0; | |
8211 | while ((sz & 3) != 0); | |
8212 | ||
8213 | /* Follow the standard note section layout: | |
8214 | First write the length of the name string. */ | |
8215 | p = frag_more (4); | |
8216 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8217 | ||
8218 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8219 | p = frag_more (4); | |
8220 | md_number_to_chars (p, (valueT) sz, 4); | |
8221 | ||
8222 | /* Write the note type. */ | |
8223 | p = frag_more (4); | |
8224 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8225 | ||
8226 | /* Write the name field. */ | |
8227 | p = frag_more (XTINFO_NAMESZ); | |
8228 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8229 | ||
8230 | /* Finally, write the descriptor. */ | |
8231 | p = frag_more (sz); | |
8232 | memcpy (p, data, sz); | |
8233 | ||
8234 | free (data); | |
8235 | } | |
8236 | ||
e0001a05 NC |
8237 | \f |
8238 | /* Alignment Functions. */ | |
8239 | ||
d77b99c9 BW |
8240 | static int |
8241 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8242 | { |
03aaa593 BW |
8243 | if (target_size <= 4) |
8244 | return 2; | |
9c2799c2 | 8245 | gas_assert (target_size == 8); |
03aaa593 | 8246 | return 3; |
e0001a05 NC |
8247 | } |
8248 | ||
8249 | ||
d77b99c9 | 8250 | static int |
7fa3d080 BW |
8251 | get_text_align_max_fill_size (int align_pow, |
8252 | bfd_boolean use_nops, | |
8253 | bfd_boolean use_no_density) | |
e0001a05 NC |
8254 | { |
8255 | if (!use_nops) | |
8256 | return (1 << align_pow); | |
8257 | if (use_no_density) | |
8258 | return 3 * (1 << align_pow); | |
8259 | ||
8260 | return 1 + (1 << align_pow); | |
8261 | } | |
8262 | ||
8263 | ||
d77b99c9 BW |
8264 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8265 | target instruction of size "target_size" so that it does not cross a | |
8266 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8267 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8268 | be filled by NOP instructions. */ | |
e0001a05 | 8269 | |
d77b99c9 | 8270 | static int |
7fa3d080 BW |
8271 | get_text_align_fill_size (addressT address, |
8272 | int align_pow, | |
8273 | int target_size, | |
8274 | bfd_boolean use_nops, | |
8275 | bfd_boolean use_no_density) | |
e0001a05 | 8276 | { |
d77b99c9 BW |
8277 | addressT alignment, fill, fill_limit, fill_step; |
8278 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8279 | |
d77b99c9 | 8280 | alignment = (1 << align_pow); |
9c2799c2 | 8281 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 8282 | |
e0001a05 NC |
8283 | if (!use_nops) |
8284 | { | |
d77b99c9 BW |
8285 | fill_limit = alignment; |
8286 | fill_step = 1; | |
e0001a05 | 8287 | } |
d77b99c9 | 8288 | else if (!use_no_density) |
e0001a05 | 8289 | { |
d77b99c9 BW |
8290 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8291 | fill_limit = alignment * 2; | |
8292 | fill_step = 1; | |
8293 | skip_one = TRUE; | |
e0001a05 NC |
8294 | } |
8295 | else | |
8296 | { | |
d77b99c9 BW |
8297 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8298 | fill_limit = alignment * 3; | |
8299 | fill_step = 3; | |
8300 | } | |
e0001a05 | 8301 | |
d77b99c9 BW |
8302 | /* Try all fill sizes until finding one that works. */ |
8303 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8304 | { | |
8305 | if (skip_one && fill == 1) | |
8306 | continue; | |
8307 | if ((address + fill) >> align_pow | |
8308 | == (address + fill + target_size - 1) >> align_pow) | |
8309 | return fill; | |
e0001a05 | 8310 | } |
9c2799c2 | 8311 | gas_assert (0); |
e0001a05 NC |
8312 | return 0; |
8313 | } | |
8314 | ||
8315 | ||
664df4e4 BW |
8316 | static int |
8317 | branch_align_power (segT sec) | |
8318 | { | |
8319 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8320 | is aligned to at least an 8-byte boundary, then a branch target need | |
8321 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8322 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8323 | (which may be insufficient, e.g., if the section has no alignment, but | |
8324 | it's good enough). */ | |
8325 | if (xtensa_fetch_width == 8) | |
8326 | { | |
8327 | if (get_recorded_alignment (sec) >= 3) | |
8328 | return 3; | |
8329 | } | |
8330 | else | |
9c2799c2 | 8331 | gas_assert (xtensa_fetch_width == 4); |
664df4e4 BW |
8332 | |
8333 | return 2; | |
8334 | } | |
8335 | ||
8336 | ||
e0001a05 NC |
8337 | /* This will assert if it is not possible. */ |
8338 | ||
d77b99c9 BW |
8339 | static int |
8340 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8341 | { |
d77b99c9 BW |
8342 | int count = 0; |
8343 | ||
e0001a05 NC |
8344 | if (use_no_density) |
8345 | { | |
9c2799c2 | 8346 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
8347 | return (fill_size / 3); |
8348 | } | |
8349 | ||
9c2799c2 | 8350 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
8351 | |
8352 | while (fill_size > 1) | |
8353 | { | |
d77b99c9 | 8354 | int insn_size = 3; |
e0001a05 NC |
8355 | if (fill_size == 2 || fill_size == 4) |
8356 | insn_size = 2; | |
8357 | fill_size -= insn_size; | |
8358 | count++; | |
8359 | } | |
9c2799c2 | 8360 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
8361 | return count; |
8362 | } | |
8363 | ||
8364 | ||
d77b99c9 BW |
8365 | static int |
8366 | get_text_align_nth_nop_size (offsetT fill_size, | |
8367 | int n, | |
7fa3d080 | 8368 | bfd_boolean use_no_density) |
e0001a05 | 8369 | { |
d77b99c9 | 8370 | int count = 0; |
e0001a05 NC |
8371 | |
8372 | if (use_no_density) | |
8373 | return 3; | |
8374 | ||
9c2799c2 | 8375 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 8376 | |
e0001a05 NC |
8377 | while (fill_size > 1) |
8378 | { | |
d77b99c9 | 8379 | int insn_size = 3; |
e0001a05 NC |
8380 | if (fill_size == 2 || fill_size == 4) |
8381 | insn_size = 2; | |
8382 | fill_size -= insn_size; | |
8383 | count++; | |
8384 | if (n + 1 == count) | |
8385 | return insn_size; | |
8386 | } | |
9c2799c2 | 8387 | gas_assert (0); |
e0001a05 NC |
8388 | return 0; |
8389 | } | |
8390 | ||
8391 | ||
8392 | /* For the given fragment, find the appropriate address | |
8393 | for it to begin at if we are using NOPs to align it. */ | |
8394 | ||
8395 | static addressT | |
7fa3d080 | 8396 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8397 | { |
43cd72b9 BW |
8398 | /* The rule is: get next fragment's FIRST instruction. Find |
8399 | the smallest number of bytes that need to be added to | |
8400 | ensure that the next fragment's FIRST instruction will fit | |
8401 | in a single word. | |
c138bc38 | 8402 | |
43cd72b9 BW |
8403 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8404 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8405 | |
43cd72b9 BW |
8406 | If the FIRST instruction MIGHT be relaxed, |
8407 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8408 | |
43cd72b9 BW |
8409 | Note again here that LOOP instructions are not bundleable, |
8410 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8411 | |
d77b99c9 | 8412 | int fill_size = 0; |
43cd72b9 BW |
8413 | int first_insn_size; |
8414 | int loop_insn_size; | |
8415 | addressT pre_opcode_bytes; | |
d77b99c9 | 8416 | int align_power; |
43cd72b9 BW |
8417 | fragS *first_insn; |
8418 | xtensa_opcode opcode; | |
8419 | bfd_boolean is_loop; | |
e0001a05 | 8420 | |
9c2799c2 NC |
8421 | gas_assert (fragP->fr_type == rs_machine_dependent); |
8422 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8423 | |
43cd72b9 BW |
8424 | /* Find the loop frag. */ |
8425 | first_insn = next_non_empty_frag (fragP); | |
8426 | /* Now find the first insn frag. */ | |
8427 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8428 | |
43cd72b9 | 8429 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 8430 | gas_assert (is_loop); |
43cd72b9 | 8431 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 8432 | |
43cd72b9 BW |
8433 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8434 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8435 | |
43cd72b9 BW |
8436 | /* For loops, the alignment depends on the size of the |
8437 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8438 | |
43cd72b9 | 8439 | if (first_insn == NULL) |
03aaa593 BW |
8440 | first_insn_size = xtensa_fetch_width; |
8441 | else | |
8442 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8443 | |
43cd72b9 | 8444 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8445 | align_power = get_text_align_power (first_insn_size); |
8446 | record_alignment (now_seg, align_power); | |
c138bc38 | 8447 | |
43cd72b9 | 8448 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8449 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8450 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8451 | |
8452 | return address + fill_size; | |
8453 | } | |
8454 | ||
8455 | ||
43cd72b9 BW |
8456 | /* 3 mechanisms for relaxing an alignment: |
8457 | ||
8458 | Align to a power of 2. | |
8459 | Align so the next fragment's instruction does not cross a word boundary. | |
8460 | Align the current instruction so that if the next instruction | |
8461 | were 3 bytes, it would not cross a word boundary. | |
8462 | ||
e0001a05 NC |
8463 | We can align with: |
8464 | ||
43cd72b9 BW |
8465 | zeros - This is easy; always insert zeros. |
8466 | nops - 3-byte and 2-byte instructions | |
8467 | 2 - 2-byte nop | |
8468 | 3 - 3-byte nop | |
8469 | 4 - 2 2-byte nops | |
8470 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8471 | widening - widen previous instructions. */ |
8472 | ||
d77b99c9 BW |
8473 | static offsetT |
8474 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8475 | { |
43cd72b9 BW |
8476 | addressT target_address, loop_insn_offset; |
8477 | int target_size; | |
8478 | xtensa_opcode loop_opcode; | |
8479 | bfd_boolean is_loop; | |
d77b99c9 BW |
8480 | int align_power; |
8481 | offsetT opt_diff; | |
5f9084e9 | 8482 | offsetT branch_align; |
def13efb | 8483 | fragS *loop_frag; |
e0001a05 | 8484 | |
9c2799c2 | 8485 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 8486 | switch (fragP->fr_subtype) |
e0001a05 | 8487 | { |
43cd72b9 BW |
8488 | case RELAX_DESIRE_ALIGN: |
8489 | target_size = next_frag_format_size (fragP); | |
8490 | if (target_size == XTENSA_UNDEFINED) | |
8491 | target_size = 3; | |
664df4e4 BW |
8492 | align_power = branch_align_power (now_seg); |
8493 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8494 | /* Don't count on the section alignment being as large as the target. */ |
8495 | if (target_size > branch_align) | |
8496 | target_size = branch_align; | |
d77b99c9 | 8497 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8498 | target_size, FALSE, FALSE); |
8499 | ||
664df4e4 BW |
8500 | *max_diff = (opt_diff + branch_align |
8501 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 8502 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 8503 | return opt_diff; |
e0001a05 | 8504 | |
43cd72b9 | 8505 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
8506 | /* The next non-empty frag after this one holds the LOOP instruction |
8507 | that needs to be aligned. The required alignment depends on the | |
8508 | size of the next non-empty frag after the loop frag, i.e., the | |
8509 | first instruction in the loop. */ | |
8510 | loop_frag = next_non_empty_frag (fragP); | |
8511 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
8512 | loop_insn_offset = 0; |
8513 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 8514 | gas_assert (is_loop); |
43cd72b9 BW |
8515 | |
8516 | /* If the loop has been expanded then the LOOP instruction | |
8517 | could be at an offset from this fragment. */ | |
def13efb | 8518 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
8519 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
8520 | ||
43cd72b9 BW |
8521 | /* In an ideal world, which is what we are shooting for here, |
8522 | we wouldn't need to use any NOPs immediately prior to the | |
8523 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8524 | will call get_noop_aligned_address. */ | |
8525 | target_address = | |
8526 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 8527 | align_power = get_text_align_power (target_size); |
d77b99c9 | 8528 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
8529 | target_size, FALSE, FALSE); |
8530 | ||
8531 | *max_diff = xtensa_fetch_width | |
8532 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8533 | - target_size + opt_diff; | |
9c2799c2 | 8534 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 8535 | return opt_diff; |
e0001a05 | 8536 | |
43cd72b9 BW |
8537 | default: |
8538 | break; | |
e0001a05 | 8539 | } |
9c2799c2 | 8540 | gas_assert (0); |
43cd72b9 | 8541 | return 0; |
e0001a05 NC |
8542 | } |
8543 | ||
8544 | \f | |
8545 | /* md_relax_frag Hook and Helper Functions. */ | |
8546 | ||
7fa3d080 BW |
8547 | static long relax_frag_loop_align (fragS *, long); |
8548 | static long relax_frag_for_align (fragS *, long); | |
8549 | static long relax_frag_immed | |
8550 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8551 | ||
8552 | ||
e0001a05 NC |
8553 | /* Return the number of bytes added to this fragment, given that the |
8554 | input has been stretched already by "stretch". */ | |
8555 | ||
8556 | long | |
7fa3d080 | 8557 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8558 | { |
43cd72b9 | 8559 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8560 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8561 | long new_stretch = 0; | |
8562 | char *file_name; | |
d77b99c9 BW |
8563 | unsigned line; |
8564 | int lit_size; | |
43cd72b9 BW |
8565 | static xtensa_insnbuf vbuf = NULL; |
8566 | int slot, num_slots; | |
8567 | xtensa_format fmt; | |
e0001a05 NC |
8568 | |
8569 | as_where (&file_name, &line); | |
8570 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8571 | ||
8572 | fragP->tc_frag_data.unreported_expansion = 0; | |
8573 | ||
8574 | switch (fragP->fr_subtype) | |
8575 | { | |
8576 | case RELAX_ALIGN_NEXT_OPCODE: | |
8577 | /* Always convert. */ | |
43cd72b9 BW |
8578 | if (fragP->tc_frag_data.relax_seen) |
8579 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8580 | break; |
8581 | ||
8582 | case RELAX_LOOP_END: | |
8583 | /* Do nothing. */ | |
8584 | break; | |
8585 | ||
8586 | case RELAX_LOOP_END_ADD_NOP: | |
8587 | /* Add a NOP and switch to .fill 0. */ | |
8588 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8589 | frag_wane (fragP); |
e0001a05 NC |
8590 | break; |
8591 | ||
8592 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8593 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8594 | it or not. */ |
8595 | break; | |
8596 | ||
8597 | case RELAX_LITERAL: | |
8598 | case RELAX_LITERAL_FINAL: | |
8599 | return 0; | |
8600 | ||
8601 | case RELAX_LITERAL_NR: | |
8602 | lit_size = 4; | |
8603 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 8604 | gas_assert (unreported == lit_size); |
e0001a05 NC |
8605 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
8606 | fragP->fr_var -= lit_size; | |
8607 | fragP->fr_fix += lit_size; | |
8608 | new_stretch = 4; | |
8609 | break; | |
8610 | ||
43cd72b9 BW |
8611 | case RELAX_SLOTS: |
8612 | if (vbuf == NULL) | |
8613 | vbuf = xtensa_insnbuf_alloc (isa); | |
8614 | ||
d77b99c9 BW |
8615 | xtensa_insnbuf_from_chars |
8616 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8617 | fmt = xtensa_format_decode (isa, vbuf); |
8618 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8619 | |
43cd72b9 BW |
8620 | for (slot = 0; slot < num_slots; slot++) |
8621 | { | |
8622 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8623 | { | |
8624 | case RELAX_NARROW: | |
8625 | if (fragP->tc_frag_data.relax_seen) | |
8626 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8627 | break; | |
8628 | ||
8629 | case RELAX_IMMED: | |
8630 | case RELAX_IMMED_STEP1: | |
8631 | case RELAX_IMMED_STEP2: | |
b81bf389 | 8632 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
8633 | /* Place the immediate. */ |
8634 | new_stretch += relax_frag_immed | |
8635 | (now_seg, fragP, stretch, | |
8636 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8637 | fmt, slot, stretched_p, FALSE); | |
8638 | break; | |
8639 | ||
8640 | default: | |
8641 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8642 | break; | |
8643 | } | |
8644 | } | |
e0001a05 NC |
8645 | break; |
8646 | ||
8647 | case RELAX_LITERAL_POOL_BEGIN: | |
8648 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8649 | case RELAX_MAYBE_UNREACHABLE: |
8650 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8651 | /* No relaxation required. */ |
8652 | break; | |
8653 | ||
43cd72b9 BW |
8654 | case RELAX_FILL_NOP: |
8655 | case RELAX_UNREACHABLE: | |
8656 | if (fragP->tc_frag_data.relax_seen) | |
8657 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8658 | break; | |
8659 | ||
e0001a05 NC |
8660 | default: |
8661 | as_bad (_("bad relaxation state")); | |
8662 | } | |
8663 | ||
43cd72b9 | 8664 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8665 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8666 | { |
8667 | fragP->tc_frag_data.relax_seen = TRUE; | |
8668 | *stretched_p = 1; | |
8669 | } | |
8670 | ||
e0001a05 NC |
8671 | new_logical_line (file_name, line); |
8672 | return new_stretch; | |
8673 | } | |
8674 | ||
8675 | ||
8676 | static long | |
7fa3d080 | 8677 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8678 | { |
8679 | addressT old_address, old_next_address, old_size; | |
8680 | addressT new_address, new_next_address, new_size; | |
8681 | addressT growth; | |
8682 | ||
43cd72b9 BW |
8683 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8684 | section have been done, hopefully eliminating the need for a NOP here. | |
8685 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8686 | |
8687 | /* Calculate the old address of this fragment and the next fragment. */ | |
8688 | old_address = fragP->fr_address - stretch; | |
8689 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8690 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8691 | old_size = old_next_address - old_address; |
8692 | ||
8693 | /* Calculate the new address of this fragment and the next fragment. */ | |
8694 | new_address = fragP->fr_address; | |
8695 | new_next_address = | |
8696 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8697 | new_size = new_next_address - new_address; | |
8698 | ||
8699 | growth = new_size - old_size; | |
8700 | ||
8701 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8702 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8703 | return growth; |
8704 | } | |
8705 | ||
8706 | ||
43cd72b9 | 8707 | /* Add a NOP instruction. */ |
e0001a05 NC |
8708 | |
8709 | static long | |
7fa3d080 | 8710 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8711 | { |
e0001a05 | 8712 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8713 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8714 | assemble_nop (length, nop_buf); | |
e0001a05 | 8715 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8716 | |
e0001a05 NC |
8717 | if (fragP->fr_var < length) |
8718 | { | |
dd49a749 | 8719 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8720 | return 0; |
8721 | } | |
8722 | ||
8723 | fragP->fr_fix += length; | |
8724 | fragP->fr_var -= length; | |
e0001a05 NC |
8725 | return length; |
8726 | } | |
8727 | ||
8728 | ||
7fa3d080 BW |
8729 | static long future_alignment_required (fragS *, long); |
8730 | ||
e0001a05 | 8731 | static long |
7fa3d080 | 8732 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8733 | { |
43cd72b9 BW |
8734 | /* Overview of the relaxation procedure for alignment: |
8735 | We can widen with NOPs or by widening instructions or by filling | |
8736 | bytes after jump instructions. Find the opportune places and widen | |
8737 | them if necessary. */ | |
8738 | ||
8739 | long stretch_me; | |
8740 | long diff; | |
e0001a05 | 8741 | |
9c2799c2 | 8742 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
8743 | || fragP->fr_subtype == RELAX_UNREACHABLE |
8744 | || (fragP->fr_subtype == RELAX_SLOTS | |
8745 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8746 | ||
8747 | stretch_me = future_alignment_required (fragP, stretch); | |
8748 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8749 | if (diff == 0) | |
8750 | return 0; | |
e0001a05 | 8751 | |
43cd72b9 | 8752 | if (diff < 0) |
e0001a05 | 8753 | { |
43cd72b9 BW |
8754 | /* We expanded on a previous pass. Can we shrink now? */ |
8755 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8756 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8757 | { |
43cd72b9 BW |
8758 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8759 | return -shrink; | |
e0001a05 NC |
8760 | } |
8761 | return 0; | |
8762 | } | |
8763 | ||
43cd72b9 BW |
8764 | /* Below here, diff > 0. */ |
8765 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8766 | |
43cd72b9 | 8767 | return diff; |
e0001a05 NC |
8768 | } |
8769 | ||
8770 | ||
43cd72b9 BW |
8771 | /* Return the address of the next frag that should be aligned. |
8772 | ||
8773 | By "address" we mean the address it _would_ be at if there | |
8774 | is no action taken to align it between here and the target frag. | |
8775 | In other words, if no narrows and no fill nops are used between | |
8776 | here and the frag to align, _even_if_ some of the frags we use | |
8777 | to align targets have already expanded on a previous relaxation | |
8778 | pass. | |
8779 | ||
8780 | Also, count each frag that may be used to help align the target. | |
8781 | ||
8782 | Return 0 if there are no frags left in the chain that need to be | |
8783 | aligned. */ | |
8784 | ||
8785 | static addressT | |
7fa3d080 BW |
8786 | find_address_of_next_align_frag (fragS **fragPP, |
8787 | int *wide_nops, | |
8788 | int *narrow_nops, | |
8789 | int *widens, | |
8790 | bfd_boolean *paddable) | |
e0001a05 | 8791 | { |
43cd72b9 BW |
8792 | fragS *fragP = *fragPP; |
8793 | addressT address = fragP->fr_address; | |
8794 | ||
8795 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8796 | |
8797 | while (fragP) | |
8798 | { | |
8799 | /* Limit this to a small search. */ | |
b5e4a23d | 8800 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8801 | { |
8802 | *fragPP = fragP; | |
8803 | return 0; | |
8804 | } | |
e0001a05 NC |
8805 | address += fragP->fr_fix; |
8806 | ||
43cd72b9 BW |
8807 | if (fragP->fr_type == rs_fill) |
8808 | address += fragP->fr_offset * fragP->fr_var; | |
8809 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8810 | { |
e0001a05 NC |
8811 | switch (fragP->fr_subtype) |
8812 | { | |
43cd72b9 BW |
8813 | case RELAX_UNREACHABLE: |
8814 | *paddable = TRUE; | |
8815 | break; | |
8816 | ||
8817 | case RELAX_FILL_NOP: | |
8818 | (*wide_nops)++; | |
8819 | if (!fragP->tc_frag_data.is_no_density) | |
8820 | (*narrow_nops)++; | |
8821 | break; | |
8822 | ||
8823 | case RELAX_SLOTS: | |
8824 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8825 | { | |
8826 | (*widens)++; | |
8827 | break; | |
8828 | } | |
34e41783 | 8829 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8830 | break; |
8831 | ||
8832 | case RELAX_IMMED: | |
43cd72b9 | 8833 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8834 | break; |
8835 | ||
8836 | case RELAX_ALIGN_NEXT_OPCODE: | |
8837 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8838 | *fragPP = fragP; |
8839 | return address; | |
8840 | ||
8841 | case RELAX_MAYBE_UNREACHABLE: | |
8842 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8843 | /* Do nothing. */ | |
e0001a05 NC |
8844 | break; |
8845 | ||
8846 | default: | |
43cd72b9 BW |
8847 | /* Just punt if we don't know the type. */ |
8848 | *fragPP = fragP; | |
8849 | return 0; | |
e0001a05 | 8850 | } |
43cd72b9 | 8851 | } |
c138bc38 | 8852 | else |
43cd72b9 BW |
8853 | { |
8854 | /* Just punt if we don't know the type. */ | |
8855 | *fragPP = fragP; | |
8856 | return 0; | |
8857 | } | |
8858 | fragP = fragP->fr_next; | |
8859 | } | |
8860 | ||
8861 | *fragPP = fragP; | |
8862 | return 0; | |
8863 | } | |
8864 | ||
8865 | ||
7fa3d080 BW |
8866 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8867 | ||
43cd72b9 | 8868 | static long |
7fa3d080 | 8869 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8870 | { |
8871 | fragS *this_frag = fragP; | |
8872 | long address; | |
8873 | int num_widens = 0; | |
8874 | int wide_nops = 0; | |
8875 | int narrow_nops = 0; | |
8876 | bfd_boolean paddable = FALSE; | |
8877 | offsetT local_opt_diff; | |
8878 | offsetT opt_diff; | |
8879 | offsetT max_diff; | |
8880 | int stretch_amount = 0; | |
8881 | int local_stretch_amount; | |
8882 | int global_stretch_amount; | |
8883 | ||
7fa3d080 BW |
8884 | address = find_address_of_next_align_frag |
8885 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8886 | |
b5e4a23d BW |
8887 | if (!address) |
8888 | { | |
8889 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8890 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8891 | else | |
8892 | frag_wane (this_frag); | |
8893 | } | |
8894 | else | |
43cd72b9 BW |
8895 | { |
8896 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8897 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
8898 | gas_assert (opt_diff >= 0); |
8899 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 8900 | if (max_diff == 0) |
43cd72b9 | 8901 | return 0; |
d2a033cd | 8902 | |
43cd72b9 BW |
8903 | if (fragP) |
8904 | fragP = fragP->fr_next; | |
8905 | ||
8906 | while (fragP && opt_diff < max_diff && address) | |
8907 | { | |
8908 | /* We only use these to determine if we can exit early | |
c138bc38 | 8909 | because there will be plenty of ways to align future |
43cd72b9 | 8910 | align frags. */ |
d77b99c9 | 8911 | int glob_widens = 0; |
43cd72b9 BW |
8912 | int dnn = 0; |
8913 | int dw = 0; | |
8914 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8915 | address = find_address_of_next_align_frag |
8916 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8917 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8918 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8919 | address = 0; |
43cd72b9 | 8920 | |
c138bc38 | 8921 | if (address) |
43cd72b9 BW |
8922 | { |
8923 | offsetT next_m_diff; | |
8924 | offsetT next_o_diff; | |
8925 | ||
8926 | /* Downrange frags haven't had stretch added to them yet. */ | |
8927 | address += stretch; | |
8928 | ||
8929 | /* The address also includes any text expansion from this | |
8930 | frag in a previous pass, but we don't want that. */ | |
8931 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8932 | ||
8933 | /* Assume we are going to move at least opt_diff. In | |
8934 | reality, we might not be able to, but assuming that | |
8935 | we will helps catch cases where moving opt_diff pushes | |
8936 | the next target from aligned to unaligned. */ | |
8937 | address += opt_diff; | |
8938 | ||
8939 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8940 | ||
8941 | /* Now cleanup for the adjustments to address. */ | |
8942 | next_o_diff += opt_diff; | |
8943 | next_m_diff += opt_diff; | |
8944 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8945 | opt_diff = next_o_diff; | |
8946 | if (next_m_diff < max_diff) | |
8947 | max_diff = next_m_diff; | |
8948 | fragP = fragP->fr_next; | |
8949 | } | |
8950 | } | |
d2a033cd | 8951 | |
43cd72b9 BW |
8952 | /* If there are enough wideners in between, do it. */ |
8953 | if (paddable) | |
8954 | { | |
8955 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8956 | { | |
9c2799c2 | 8957 | gas_assert (opt_diff <= UNREACHABLE_MAX_WIDTH); |
43cd72b9 BW |
8958 | return opt_diff; |
8959 | } | |
8960 | return 0; | |
8961 | } | |
c138bc38 | 8962 | local_stretch_amount |
43cd72b9 BW |
8963 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8964 | num_widens, local_opt_diff); | |
c138bc38 BW |
8965 | global_stretch_amount |
8966 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8967 | num_widens, opt_diff); |
c138bc38 BW |
8968 | /* If the condition below is true, then the frag couldn't |
8969 | stretch the correct amount for the global case, so we just | |
8970 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8971 | the correct alignment in the global case. */ |
8972 | if (global_stretch_amount < local_stretch_amount) | |
8973 | stretch_amount = local_stretch_amount; | |
8974 | else | |
8975 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8976 | |
43cd72b9 BW |
8977 | if (this_frag->fr_subtype == RELAX_SLOTS |
8978 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 8979 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
8980 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
8981 | { | |
8982 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 8983 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 8984 | else |
9c2799c2 | 8985 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
8986 | } |
8987 | } | |
8988 | return stretch_amount; | |
8989 | } | |
8990 | ||
8991 | ||
8992 | /* The idea: widen everything you can to get a target or loop aligned, | |
8993 | then start using NOPs. | |
8994 | ||
8995 | When we must have a NOP, here is a table of how we decide | |
8996 | (so you don't have to fight through the control flow below): | |
8997 | ||
8998 | wide_nops = the number of wide NOPs available for aligning | |
8999 | narrow_nops = the number of narrow NOPs available for aligning | |
9000 | (a subset of wide_nops) | |
9001 | widens = the number of narrow instructions that should be widened | |
9002 | ||
9003 | Desired wide narrow | |
9004 | Diff nop nop widens | |
9005 | 1 0 0 1 | |
9006 | 2 0 1 0 | |
9007 | 3a 1 0 0 | |
9008 | b 0 1 1 (case 3a makes this case unnecessary) | |
9009 | 4a 1 0 1 | |
9010 | b 0 2 0 | |
9011 | c 0 1 2 (case 4a makes this case unnecessary) | |
9012 | 5a 1 0 2 | |
9013 | b 1 1 0 | |
9014 | c 0 2 1 (case 5b makes this case unnecessary) | |
9015 | 6a 2 0 0 | |
9016 | b 1 0 3 | |
708587a4 | 9017 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
9018 | d 1 1 1 (case 6a makes this case unnecessary) |
9019 | e 0 2 2 (case 6a makes this case unnecessary) | |
9020 | f 0 3 0 (case 6a makes this case unnecessary) | |
9021 | 7a 1 0 4 | |
9022 | b 2 0 1 | |
9023 | c 1 1 2 (case 7b makes this case unnecessary) | |
9024 | d 0 1 5 (case 7a makes this case unnecessary) | |
9025 | e 0 2 3 (case 7b makes this case unnecessary) | |
9026 | f 0 3 1 (case 7b makes this case unnecessary) | |
9027 | g 1 2 1 (case 7b makes this case unnecessary) | |
9028 | */ | |
9029 | ||
9030 | static long | |
7fa3d080 BW |
9031 | bytes_to_stretch (fragS *this_frag, |
9032 | int wide_nops, | |
9033 | int narrow_nops, | |
9034 | int num_widens, | |
9035 | int desired_diff) | |
43cd72b9 BW |
9036 | { |
9037 | int bytes_short = desired_diff - num_widens; | |
9038 | ||
9c2799c2 | 9039 | gas_assert (desired_diff >= 0 && desired_diff < 8); |
43cd72b9 BW |
9040 | if (desired_diff == 0) |
9041 | return 0; | |
c138bc38 | 9042 | |
9c2799c2 | 9043 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 9044 | |
43cd72b9 BW |
9045 | /* Always prefer widening to NOP-filling. */ |
9046 | if (bytes_short < 0) | |
9047 | { | |
9048 | /* There are enough RELAX_NARROW frags after this one | |
9049 | to align the target without widening this frag in any way. */ | |
9050 | return 0; | |
9051 | } | |
c138bc38 | 9052 | |
43cd72b9 BW |
9053 | if (bytes_short == 0) |
9054 | { | |
9055 | /* Widen every narrow between here and the align target | |
9056 | and the align target will be properly aligned. */ | |
9057 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9058 | return 0; | |
9059 | else | |
9060 | return 1; | |
9061 | } | |
c138bc38 | 9062 | |
43cd72b9 BW |
9063 | /* From here we will need at least one NOP to get an alignment. |
9064 | However, we may not be able to align at all, in which case, | |
9065 | don't widen. */ | |
9066 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9067 | { | |
9068 | switch (desired_diff) | |
9069 | { | |
9070 | case 1: | |
9071 | return 0; | |
9072 | case 2: | |
9073 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
9074 | return 2; /* case 2 */ | |
9075 | return 0; | |
c138bc38 | 9076 | case 3: |
43cd72b9 BW |
9077 | if (wide_nops > 1) |
9078 | return 0; | |
9079 | else | |
9080 | return 3; /* case 3a */ | |
9081 | case 4: | |
9082 | if (num_widens >= 1 && wide_nops == 1) | |
9083 | return 3; /* case 4a */ | |
9084 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
9085 | return 2; /* case 4b */ | |
9086 | return 0; | |
9087 | case 5: | |
9088 | if (num_widens >= 2 && wide_nops == 1) | |
9089 | return 3; /* case 5a */ | |
c138bc38 | 9090 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
9091 | between here and the align target? */ |
9092 | if (wide_nops < 2 || narrow_nops == 0) | |
9093 | return 0; | |
9094 | /* Are there other nops closer that can serve instead? */ | |
9095 | if (wide_nops > 2 && narrow_nops > 1) | |
9096 | return 0; | |
9097 | /* Take the density one first, because there might not be | |
9098 | another density one available. */ | |
9099 | if (!this_frag->tc_frag_data.is_no_density) | |
9100 | return 2; /* case 5b narrow */ | |
9101 | else | |
9102 | return 3; /* case 5b wide */ | |
9103 | return 0; | |
9104 | case 6: | |
9105 | if (wide_nops == 2) | |
9106 | return 3; /* case 6a */ | |
9107 | else if (num_widens >= 3 && wide_nops == 1) | |
9108 | return 3; /* case 6b */ | |
9109 | return 0; | |
9110 | case 7: | |
9111 | if (wide_nops == 1 && num_widens >= 4) | |
9112 | return 3; /* case 7a */ | |
9113 | else if (wide_nops == 2 && num_widens >= 1) | |
9114 | return 3; /* case 7b */ | |
9115 | return 0; | |
e0001a05 | 9116 | default: |
9c2799c2 | 9117 | gas_assert (0); |
e0001a05 | 9118 | } |
e0001a05 | 9119 | } |
43cd72b9 BW |
9120 | else |
9121 | { | |
c138bc38 | 9122 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 9123 | this instruction to help? |
e0001a05 | 9124 | |
03aaa593 | 9125 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
9126 | switch (desired_diff) |
9127 | { | |
9128 | case 1: | |
9c2799c2 | 9129 | gas_assert (0); |
43cd72b9 BW |
9130 | return 0; |
9131 | case 2: | |
9132 | case 3: | |
9133 | return 0; | |
9134 | case 4: | |
9135 | if (wide_nops >= 1 && num_widens == 1) | |
9136 | return 1; /* case 4a */ | |
9137 | return 0; | |
9138 | case 5: | |
9139 | if (wide_nops >= 1 && num_widens == 2) | |
9140 | return 1; /* case 5a */ | |
9141 | return 0; | |
9142 | case 6: | |
9143 | if (wide_nops >= 2) | |
9144 | return 0; /* case 6a */ | |
9145 | else if (wide_nops >= 1 && num_widens == 3) | |
9146 | return 1; /* case 6b */ | |
9147 | return 0; | |
9148 | case 7: | |
9149 | if (wide_nops >= 1 && num_widens == 4) | |
9150 | return 1; /* case 7a */ | |
9151 | else if (wide_nops >= 2 && num_widens == 1) | |
9152 | return 1; /* case 7b */ | |
9153 | return 0; | |
9154 | default: | |
9c2799c2 | 9155 | gas_assert (0); |
43cd72b9 BW |
9156 | return 0; |
9157 | } | |
9158 | } | |
9c2799c2 | 9159 | gas_assert (0); |
43cd72b9 | 9160 | return 0; |
e0001a05 NC |
9161 | } |
9162 | ||
9163 | ||
9164 | static long | |
7fa3d080 BW |
9165 | relax_frag_immed (segT segP, |
9166 | fragS *fragP, | |
9167 | long stretch, | |
9168 | int min_steps, | |
9169 | xtensa_format fmt, | |
9170 | int slot, | |
9171 | int *stretched_p, | |
9172 | bfd_boolean estimate_only) | |
e0001a05 | 9173 | { |
43cd72b9 | 9174 | TInsn tinsn; |
e0001a05 NC |
9175 | int old_size; |
9176 | bfd_boolean negatable_branch = FALSE; | |
9177 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 9178 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 9179 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9180 | IStack istack; |
9181 | offsetT frag_offset; | |
9182 | int num_steps; | |
e0001a05 | 9183 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 9184 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 9185 | |
9c2799c2 | 9186 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 9187 | |
b5e4a23d BW |
9188 | xg_clear_vinsn (&cur_vinsn); |
9189 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 9190 | if (cur_vinsn.num_slots > 1) |
def13efb | 9191 | from_wide_insn = TRUE; |
43cd72b9 | 9192 | |
b5e4a23d | 9193 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 9194 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 9195 | |
64b607e6 | 9196 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 9197 | return 0; |
e0001a05 | 9198 | |
b08b5071 | 9199 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9200 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 9201 | |
43cd72b9 | 9202 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 9203 | |
43cd72b9 | 9204 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9205 | |
9206 | /* Special case: replace a branch to the next instruction with a NOP. | |
9207 | This is required to work around a hardware bug in T1040.0 and also | |
9208 | serves as an optimization. */ | |
9209 | ||
9210 | if (branch_jmp_to_next | |
9211 | && ((old_size == 2) || (old_size == 3)) | |
9212 | && !next_frag_is_loop_target (fragP)) | |
9213 | return 0; | |
9214 | ||
9215 | /* Here is the fun stuff: Get the immediate field from this | |
9216 | instruction. If it fits, we are done. If not, find the next | |
9217 | instruction sequence that fits. */ | |
9218 | ||
9219 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9220 | istack_init (&istack); | |
43cd72b9 | 9221 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 9222 | min_steps, stretch); |
9c2799c2 | 9223 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 9224 | |
43cd72b9 | 9225 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
9226 | |
9227 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 9228 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
9229 | literal_diff |
9230 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 9231 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
9232 | |
9233 | if (from_wide_insn) | |
43cd72b9 | 9234 | { |
2276bc20 BW |
9235 | int first = 0; |
9236 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
9237 | first++; | |
9238 | ||
43cd72b9 BW |
9239 | num_text_bytes += old_size; |
9240 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
9241 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
9242 | else |
9243 | { | |
9244 | /* The first instruction in the relaxed sequence will go after | |
9245 | the current wide instruction, and thus its symbolic immediates | |
9246 | might not fit. */ | |
9247 | ||
9248 | istack_init (&istack); | |
9249 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, | |
9250 | frag_offset + old_size, | |
9251 | min_steps, stretch + old_size); | |
9c2799c2 | 9252 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 BW |
9253 | |
9254 | fragP->tc_frag_data.slot_subtypes[slot] | |
9255 | = (int) RELAX_IMMED + num_steps; | |
9256 | ||
9257 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
9258 | literal_diff | |
9259 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
9260 | ||
9261 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; | |
9262 | } | |
43cd72b9 | 9263 | } |
def13efb | 9264 | |
43cd72b9 BW |
9265 | total_text_diff = num_text_bytes - old_size; |
9266 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
9267 | |
9268 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
9269 | gas_assert (num_text_bytes >= 0); |
9270 | gas_assert (literal_diff >= 0); | |
9271 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 9272 | |
43cd72b9 BW |
9273 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
9274 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
9275 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
9276 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
9277 | |
9278 | /* Find the associated expandable literal for this. */ | |
9279 | if (literal_diff != 0) | |
9280 | { | |
2276bc20 | 9281 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9282 | if (lit_fragP) |
9283 | { | |
9c2799c2 | 9284 | gas_assert (literal_diff == 4); |
e0001a05 NC |
9285 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
9286 | ||
9287 | /* We expect that the literal section state has NOT been | |
9288 | modified yet. */ | |
9c2799c2 | 9289 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
9290 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
9291 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
9292 | ||
9293 | /* We need to mark this section for another iteration | |
9294 | of relaxation. */ | |
9295 | (*stretched_p)++; | |
9296 | } | |
9297 | } | |
9298 | ||
43cd72b9 | 9299 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 9300 | update_next_frag_state (fragP); |
e0001a05 | 9301 | |
43cd72b9 | 9302 | return this_text_diff; |
e0001a05 NC |
9303 | } |
9304 | ||
9305 | \f | |
9306 | /* md_convert_frag Hook and Helper Functions. */ | |
9307 | ||
7fa3d080 BW |
9308 | static void convert_frag_align_next_opcode (fragS *); |
9309 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
9310 | static void convert_frag_fill_nop (fragS *); | |
9311 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
9312 | ||
e0001a05 | 9313 | void |
7fa3d080 | 9314 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9315 | { |
43cd72b9 BW |
9316 | static xtensa_insnbuf vbuf = NULL; |
9317 | xtensa_isa isa = xtensa_default_isa; | |
9318 | int slot; | |
9319 | int num_slots; | |
9320 | xtensa_format fmt; | |
e0001a05 | 9321 | char *file_name; |
d77b99c9 | 9322 | unsigned line; |
e0001a05 NC |
9323 | |
9324 | as_where (&file_name, &line); | |
9325 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9326 | ||
9327 | switch (fragp->fr_subtype) | |
9328 | { | |
9329 | case RELAX_ALIGN_NEXT_OPCODE: | |
9330 | /* Always convert. */ | |
9331 | convert_frag_align_next_opcode (fragp); | |
9332 | break; | |
9333 | ||
9334 | case RELAX_DESIRE_ALIGN: | |
9335 | /* Do nothing. If not aligned already, too bad. */ | |
9336 | break; | |
9337 | ||
43cd72b9 BW |
9338 | case RELAX_LITERAL: |
9339 | case RELAX_LITERAL_FINAL: | |
9340 | break; | |
9341 | ||
9342 | case RELAX_SLOTS: | |
9343 | if (vbuf == NULL) | |
9344 | vbuf = xtensa_insnbuf_alloc (isa); | |
9345 | ||
d77b99c9 BW |
9346 | xtensa_insnbuf_from_chars |
9347 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9348 | fmt = xtensa_format_decode (isa, vbuf); |
9349 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9350 | ||
9351 | for (slot = 0; slot < num_slots; slot++) | |
9352 | { | |
9353 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9354 | { | |
9355 | case RELAX_NARROW: | |
9356 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9357 | break; | |
9358 | ||
9359 | case RELAX_IMMED: | |
9360 | case RELAX_IMMED_STEP1: | |
9361 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9362 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9363 | /* Place the immediate. */ |
9364 | convert_frag_immed | |
9365 | (sec, fragp, | |
9366 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9367 | fmt, slot); | |
9368 | break; | |
9369 | ||
9370 | default: | |
9371 | /* This is OK because some slots could have | |
9372 | relaxations and others have none. */ | |
9373 | break; | |
9374 | } | |
9375 | } | |
9376 | break; | |
9377 | ||
9378 | case RELAX_UNREACHABLE: | |
9379 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9380 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9381 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9382 | frag_wane (fragp); | |
e0001a05 NC |
9383 | break; |
9384 | ||
43cd72b9 BW |
9385 | case RELAX_MAYBE_UNREACHABLE: |
9386 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9387 | frag_wane (fragp); | |
e0001a05 NC |
9388 | break; |
9389 | ||
43cd72b9 BW |
9390 | case RELAX_FILL_NOP: |
9391 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9392 | break; |
9393 | ||
9394 | case RELAX_LITERAL_NR: | |
9395 | if (use_literal_section) | |
9396 | { | |
9397 | /* This should have been handled during relaxation. When | |
9398 | relaxing a code segment, literals sometimes need to be | |
9399 | added to the corresponding literal segment. If that | |
9400 | literal segment has already been relaxed, then we end up | |
9401 | in this situation. Marking the literal segments as data | |
9402 | would make this happen less often (since GAS always relaxes | |
9403 | code before data), but we could still get into trouble if | |
9404 | there are instructions in a segment that is not marked as | |
9405 | containing code. Until we can implement a better solution, | |
9406 | cheat and adjust the addresses of all the following frags. | |
9407 | This could break subsequent alignments, but the linker's | |
9408 | literal coalescing will do that anyway. */ | |
9409 | ||
9410 | fragS *f; | |
9411 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9412 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
9413 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
9414 | fragp->fr_var -= 4; | |
9415 | fragp->fr_fix += 4; | |
9416 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9417 | f->fr_address += 4; | |
9418 | } | |
9419 | else | |
9420 | as_bad (_("invalid relaxation fragment result")); | |
9421 | break; | |
9422 | } | |
9423 | ||
9424 | fragp->fr_var = 0; | |
9425 | new_logical_line (file_name, line); | |
9426 | } | |
9427 | ||
9428 | ||
7fa3d080 BW |
9429 | static void |
9430 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9431 | { |
9432 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9433 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9434 | addressT aligned_address; | |
d77b99c9 BW |
9435 | offsetT fill_size; |
9436 | int nop, nop_count; | |
e0001a05 NC |
9437 | |
9438 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9439 | fragp->fr_fix); | |
9440 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9441 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9442 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9443 | ||
d77b99c9 | 9444 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9445 | { |
d77b99c9 BW |
9446 | int nop_size; |
9447 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9448 | |
9449 | assemble_nop (nop_size, nop_buf); | |
9450 | nop_buf += nop_size; | |
9451 | } | |
9452 | ||
9453 | fragp->fr_fix += fill_size; | |
9454 | fragp->fr_var -= fill_size; | |
9455 | } | |
9456 | ||
9457 | ||
9458 | static void | |
7fa3d080 | 9459 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9460 | { |
43cd72b9 | 9461 | TInsn tinsn, single_target; |
84b08ed9 | 9462 | int size, old_size, diff; |
e0001a05 NC |
9463 | offsetT frag_offset; |
9464 | ||
9c2799c2 | 9465 | gas_assert (slot == 0); |
43cd72b9 BW |
9466 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
9467 | ||
b5e4a23d | 9468 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 9469 | { |
9c2799c2 | 9470 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
9471 | || fragP->tc_frag_data.text_expansion[0] == 0); |
9472 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9473 | fmt, slot); | |
9474 | return; | |
9475 | } | |
9476 | ||
9477 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9478 | { |
9479 | /* No conversion. */ | |
9480 | fragP->fr_var = 0; | |
9481 | return; | |
9482 | } | |
9483 | ||
9c2799c2 | 9484 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 9485 | |
43cd72b9 BW |
9486 | /* Frags in this relaxation state should only contain |
9487 | single instruction bundles. */ | |
9488 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9489 | |
9490 | /* Just convert it to a wide form.... */ | |
9491 | size = 0; | |
43cd72b9 | 9492 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9493 | |
9494 | tinsn_init (&single_target); | |
9495 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9496 | ||
84b08ed9 | 9497 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9498 | { |
9499 | as_bad (_("unable to widen instruction")); | |
9500 | return; | |
9501 | } | |
9502 | ||
9503 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9504 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9505 | frag_offset, TRUE); | |
e0001a05 NC |
9506 | |
9507 | diff = size - old_size; | |
9c2799c2 NC |
9508 | gas_assert (diff >= 0); |
9509 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
9510 | fragP->fr_var -= diff; |
9511 | fragP->fr_fix += diff; | |
9512 | ||
9513 | /* clean it up */ | |
9514 | fragP->fr_var = 0; | |
9515 | } | |
9516 | ||
9517 | ||
9518 | static void | |
7fa3d080 | 9519 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9520 | { |
9521 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9522 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 9523 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
9524 | - fragP->fr_address - fragP->fr_fix)); |
9525 | if (size == 0) | |
9526 | { | |
9527 | /* No conversion. */ | |
9528 | fragP->fr_var = 0; | |
9529 | return; | |
9530 | } | |
9531 | assemble_nop (size, loc); | |
9532 | fragP->tc_frag_data.is_insn = TRUE; | |
9533 | fragP->fr_var -= size; | |
9534 | fragP->fr_fix += size; | |
9535 | frag_wane (fragP); | |
9536 | } | |
9537 | ||
9538 | ||
7fa3d080 BW |
9539 | static fixS *fix_new_exp_in_seg |
9540 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9541 | bfd_reloc_code_real_type); | |
9542 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9543 | ||
43cd72b9 | 9544 | static void |
7fa3d080 BW |
9545 | convert_frag_immed (segT segP, |
9546 | fragS *fragP, | |
9547 | int min_steps, | |
9548 | xtensa_format fmt, | |
9549 | int slot) | |
e0001a05 NC |
9550 | { |
9551 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9552 | TInsn orig_tinsn; |
e0001a05 | 9553 | bfd_boolean expanded = FALSE; |
e0001a05 | 9554 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9555 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 9556 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 9557 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
9558 | int bytes; |
9559 | bfd_boolean is_loop; | |
e0001a05 | 9560 | |
9c2799c2 | 9561 | gas_assert (fr_opcode != NULL); |
e0001a05 | 9562 | |
b5e4a23d | 9563 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9564 | |
b5e4a23d | 9565 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9566 | if (cur_vinsn.num_slots > 1) |
def13efb | 9567 | from_wide_insn = TRUE; |
e0001a05 | 9568 | |
b5e4a23d | 9569 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9570 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9571 | ||
9572 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9573 | |
b08b5071 | 9574 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9575 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9576 | |
9577 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9578 | { | |
9579 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9580 | bytes = xtensa_format_length (isa, fmt); |
9581 | if (bytes >= 4) | |
9582 | { | |
b5e4a23d BW |
9583 | cur_vinsn.slots[slot].opcode = |
9584 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9585 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9586 | } |
9587 | else | |
9588 | { | |
9589 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 9590 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 9591 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9592 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9593 | } | |
e7da6241 | 9594 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9595 | xtensa_insnbuf_to_chars |
b5e4a23d | 9596 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9597 | fragP->fr_var = 0; |
9598 | } | |
7c834684 | 9599 | else |
e0001a05 | 9600 | { |
43cd72b9 BW |
9601 | /* Here is the fun stuff: Get the immediate field from this |
9602 | instruction. If it fits, we're done. If not, find the next | |
9603 | instruction sequence that fits. */ | |
9604 | ||
e0001a05 NC |
9605 | IStack istack; |
9606 | int i; | |
9607 | symbolS *lit_sym = NULL; | |
9608 | int total_size = 0; | |
43cd72b9 | 9609 | int target_offset = 0; |
e0001a05 NC |
9610 | int old_size; |
9611 | int diff; | |
9612 | symbolS *gen_label = NULL; | |
9613 | offsetT frag_offset; | |
43cd72b9 BW |
9614 | bfd_boolean first = TRUE; |
9615 | bfd_boolean last_is_jump; | |
e0001a05 | 9616 | |
43cd72b9 | 9617 | /* It does not fit. Find something that does and |
e0001a05 | 9618 | convert immediately. */ |
43cd72b9 | 9619 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9620 | istack_init (&istack); |
43cd72b9 | 9621 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9622 | segP, fragP, frag_offset, min_steps, 0); |
9623 | ||
43cd72b9 | 9624 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9625 | |
9626 | /* Assemble this right inline. */ | |
9627 | ||
9628 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9629 | target_offset = 0; |
e0001a05 NC |
9630 | for (i = 0; i < istack.ninsn; i++) |
9631 | { | |
43cd72b9 | 9632 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9633 | fragS *lit_frag; |
9634 | ||
43cd72b9 | 9635 | switch (tinsn->insn_type) |
e0001a05 NC |
9636 | { |
9637 | case ITYPE_LITERAL: | |
9638 | if (lit_sym != NULL) | |
9639 | as_bad (_("multiple literals in expansion")); | |
9640 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9641 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9642 | if (lit_frag == NULL) |
9643 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9644 | if (tinsn->ntok != 1) |
e0001a05 NC |
9645 | as_bad (_("number of literal tokens != 1")); |
9646 | ||
9647 | /* Set the literal symbol and add a fixup. */ | |
9648 | lit_sym = lit_frag->fr_symbol; | |
9649 | break; | |
9650 | ||
9651 | case ITYPE_LABEL: | |
43cd72b9 BW |
9652 | if (align_targets && !is_loop) |
9653 | { | |
9654 | fragS *unreach = fragP->fr_next; | |
9655 | while (!(unreach->fr_type == rs_machine_dependent | |
9656 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9657 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9658 | { | |
9659 | unreach = unreach->fr_next; | |
9660 | } | |
9661 | ||
9c2799c2 | 9662 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
9663 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
9664 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9665 | ||
9666 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9667 | } | |
9c2799c2 | 9668 | gas_assert (gen_label == NULL); |
e0001a05 | 9669 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, |
43cd72b9 BW |
9670 | fr_opcode - fragP->fr_literal |
9671 | + target_offset, fragP); | |
e0001a05 NC |
9672 | break; |
9673 | ||
9674 | case ITYPE_INSN: | |
def13efb | 9675 | if (first && from_wide_insn) |
43cd72b9 BW |
9676 | { |
9677 | target_offset += xtensa_format_length (isa, fmt); | |
9678 | first = FALSE; | |
9679 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9680 | target_offset += xg_get_single_size (tinsn->opcode); | |
9681 | } | |
9682 | else | |
9683 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9684 | break; |
9685 | } | |
9686 | } | |
9687 | ||
9688 | total_size = 0; | |
43cd72b9 BW |
9689 | first = TRUE; |
9690 | last_is_jump = FALSE; | |
e0001a05 NC |
9691 | for (i = 0; i < istack.ninsn; i++) |
9692 | { | |
43cd72b9 | 9693 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9694 | fragS *lit_frag; |
9695 | int size; | |
9696 | segT target_seg; | |
43cd72b9 | 9697 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9698 | |
43cd72b9 | 9699 | switch (tinsn->insn_type) |
e0001a05 NC |
9700 | { |
9701 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9702 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9703 | /* Already checked. */ | |
9c2799c2 NC |
9704 | gas_assert (lit_frag != NULL); |
9705 | gas_assert (lit_sym != NULL); | |
9706 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 9707 | /* Add a fixup. */ |
e0001a05 | 9708 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 9709 | gas_assert (target_seg); |
28dbbc02 | 9710 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 9711 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9712 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9713 | break; |
9714 | ||
9715 | case ITYPE_LABEL: | |
9716 | break; | |
9717 | ||
9718 | case ITYPE_INSN: | |
43cd72b9 BW |
9719 | xg_resolve_labels (tinsn, gen_label); |
9720 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 9721 | if (from_wide_insn && first) |
43cd72b9 BW |
9722 | { |
9723 | first = FALSE; | |
9724 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9725 | { | |
b5e4a23d | 9726 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9727 | } |
9728 | else | |
9729 | { | |
b5e4a23d | 9730 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9731 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9732 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9733 | } |
b5e4a23d BW |
9734 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9735 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9736 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9737 | fragP->tc_frag_data.is_insn = TRUE; |
9738 | size = xtensa_format_length (isa, fmt); | |
9739 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9740 | { | |
43cd72b9 | 9741 | xg_emit_insn_to_buf |
b2d179be | 9742 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9743 | immed_instr - fragP->fr_literal + size, TRUE); |
9744 | size += xg_get_single_size (tinsn->opcode); | |
9745 | } | |
9746 | } | |
9747 | else | |
9748 | { | |
43cd72b9 | 9749 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9750 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9751 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9752 | } |
e0001a05 | 9753 | immed_instr += size; |
43cd72b9 | 9754 | total_size += size; |
e0001a05 NC |
9755 | break; |
9756 | } | |
9757 | } | |
9758 | ||
9759 | diff = total_size - old_size; | |
9c2799c2 | 9760 | gas_assert (diff >= 0); |
e0001a05 NC |
9761 | if (diff != 0) |
9762 | expanded = TRUE; | |
9c2799c2 | 9763 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
9764 | fragP->fr_var -= diff; |
9765 | fragP->fr_fix += diff; | |
9766 | } | |
9767 | ||
e0001a05 | 9768 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9769 | if (is_loop) |
e0001a05 NC |
9770 | { |
9771 | symbolS *sym; | |
43cd72b9 | 9772 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9773 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9774 | { | |
9775 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9776 | return; | |
9777 | } | |
43cd72b9 | 9778 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9779 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9780 | { | |
9781 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9782 | return; | |
9783 | } | |
9784 | } | |
9785 | ||
43cd72b9 BW |
9786 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9787 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9788 | |
43cd72b9 | 9789 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9790 | { |
9791 | /* Add an expansion note on the expanded instruction. */ | |
9792 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9793 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9794 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9795 | } |
9796 | } | |
9797 | ||
9798 | ||
9799 | /* Add a new fix expression into the desired segment. We have to | |
9800 | switch to that segment to do this. */ | |
9801 | ||
9802 | static fixS * | |
7fa3d080 BW |
9803 | fix_new_exp_in_seg (segT new_seg, |
9804 | subsegT new_subseg, | |
9805 | fragS *frag, | |
9806 | int where, | |
9807 | int size, | |
9808 | expressionS *exp, | |
9809 | int pcrel, | |
9810 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9811 | { |
9812 | fixS *new_fix; | |
9813 | segT seg = now_seg; | |
9814 | subsegT subseg = now_subseg; | |
43cd72b9 | 9815 | |
9c2799c2 | 9816 | gas_assert (new_seg != 0); |
e0001a05 NC |
9817 | subseg_set (new_seg, new_subseg); |
9818 | ||
e0001a05 NC |
9819 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9820 | subseg_set (seg, subseg); | |
9821 | return new_fix; | |
9822 | } | |
9823 | ||
9824 | ||
43cd72b9 BW |
9825 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9826 | ||
9827 | loop as, .L1 | |
9828 | .L0: | |
9829 | rsr as, LEND | |
9830 | wsr as, LBEG | |
9831 | addi as, as, lo8 (label-.L1) | |
9832 | addmi as, as, mid8 (label-.L1) | |
9833 | wsr as, LEND | |
9834 | isync | |
9835 | rsr as, LCOUNT | |
9836 | addi as, as, 1 | |
9837 | .L1: | |
9838 | <<body>> | |
9839 | label: | |
9840 | */ | |
e0001a05 NC |
9841 | |
9842 | static void | |
7fa3d080 | 9843 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9844 | { |
9845 | TInsn loop_insn; | |
9846 | TInsn addi_insn; | |
9847 | TInsn addmi_insn; | |
9848 | unsigned long target; | |
9849 | static xtensa_insnbuf insnbuf = NULL; | |
9850 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9851 | xtensa_isa isa = xtensa_default_isa; | |
9852 | addressT loop_offset; | |
9853 | addressT addi_offset = 9; | |
9854 | addressT addmi_offset = 12; | |
43cd72b9 | 9855 | fragS *next_fragP; |
d77b99c9 | 9856 | int target_count; |
e0001a05 NC |
9857 | |
9858 | if (!insnbuf) | |
9859 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9860 | ||
9861 | /* Get the loop offset. */ | |
43cd72b9 | 9862 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9863 | |
43cd72b9 BW |
9864 | /* Validate that there really is a LOOP at the loop_offset. Because |
9865 | loops are not bundleable, we can assume that the instruction will be | |
9866 | in slot 0. */ | |
9867 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9868 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9869 | ||
9c2799c2 | 9870 | gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); |
e0001a05 NC |
9871 | addi_offset += loop_offset; |
9872 | addmi_offset += loop_offset; | |
9873 | ||
9c2799c2 | 9874 | gas_assert (tinsn->ntok == 2); |
b08b5071 BW |
9875 | if (tinsn->tok[1].X_op == O_constant) |
9876 | target = tinsn->tok[1].X_add_number; | |
9877 | else if (tinsn->tok[1].X_op == O_symbol) | |
9878 | { | |
9879 | /* Find the fragment. */ | |
9880 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9c2799c2 | 9881 | gas_assert (S_GET_SEGMENT (sym) == segP |
b08b5071 BW |
9882 | || S_GET_SEGMENT (sym) == absolute_section); |
9883 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9884 | } | |
9885 | else | |
9886 | { | |
9887 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9888 | target = 0; | |
9889 | } | |
e0001a05 | 9890 | |
e0001a05 NC |
9891 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
9892 | loop_length_hi = loop_length & ~0x0ff; | |
9893 | loop_length_lo = loop_length & 0x0ff; | |
9894 | if (loop_length_lo >= 128) | |
9895 | { | |
9896 | loop_length_lo -= 256; | |
9897 | loop_length_hi += 256; | |
9898 | } | |
9899 | ||
43cd72b9 | 9900 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9901 | 32512. If the loop is larger than that, then we just fail. */ |
9902 | if (loop_length_hi > 32512) | |
9903 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9904 | _("loop too long for LOOP instruction")); | |
9905 | ||
43cd72b9 | 9906 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
9c2799c2 | 9907 | gas_assert (addi_insn.opcode == xtensa_addi_opcode); |
e0001a05 | 9908 | |
43cd72b9 | 9909 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
9c2799c2 | 9910 | gas_assert (addmi_insn.opcode == xtensa_addmi_opcode); |
e0001a05 NC |
9911 | |
9912 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9913 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9914 | |
e0001a05 | 9915 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9916 | xtensa_insnbuf_to_chars |
9917 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9918 | |
9919 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9920 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9921 | xtensa_insnbuf_to_chars |
9922 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9923 | |
9924 | /* Walk through all of the frags from here to the loop end | |
9925 | and mark them as no_transform to keep them from being modified | |
9926 | by the linker. If we ever have a relocation for the | |
9927 | addi/addmi of the difference of two symbols we can remove this. */ | |
9928 | ||
9929 | target_count = 0; | |
9930 | for (next_fragP = fragP; next_fragP != NULL; | |
9931 | next_fragP = next_fragP->fr_next) | |
9932 | { | |
b08b5071 | 9933 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9934 | if (next_fragP->tc_frag_data.is_loop_target) |
9935 | target_count++; | |
9936 | if (target_count == 2) | |
9937 | break; | |
9938 | } | |
e0001a05 NC |
9939 | } |
9940 | ||
b08b5071 BW |
9941 | \f |
9942 | /* A map that keeps information on a per-subsegment basis. This is | |
9943 | maintained during initial assembly, but is invalid once the | |
9944 | subsegments are smashed together. I.E., it cannot be used during | |
9945 | the relaxation. */ | |
e0001a05 | 9946 | |
b08b5071 | 9947 | typedef struct subseg_map_struct |
e0001a05 | 9948 | { |
b08b5071 BW |
9949 | /* the key */ |
9950 | segT seg; | |
9951 | subsegT subseg; | |
e0001a05 | 9952 | |
b08b5071 BW |
9953 | /* the data */ |
9954 | unsigned flags; | |
9955 | float total_freq; /* fall-through + branch target frequency */ | |
9956 | float target_freq; /* branch target frequency alone */ | |
9957 | ||
9958 | struct subseg_map_struct *next; | |
9959 | } subseg_map; | |
e0001a05 | 9960 | |
e0001a05 | 9961 | |
e0001a05 NC |
9962 | static subseg_map *sseg_map = NULL; |
9963 | ||
43cd72b9 | 9964 | static subseg_map * |
7fa3d080 | 9965 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9966 | { |
9967 | subseg_map *subseg_e; | |
9968 | ||
9969 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9970 | { |
43cd72b9 | 9971 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9972 | break; |
e0001a05 | 9973 | } |
b08b5071 BW |
9974 | return subseg_e; |
9975 | } | |
9976 | ||
9977 | ||
9978 | static subseg_map * | |
9979 | add_subseg_info (segT seg, subsegT subseg) | |
9980 | { | |
9981 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9982 | memset (subseg_e, 0, sizeof (subseg_map)); |
9983 | subseg_e->seg = seg; | |
9984 | subseg_e->subseg = subseg; | |
9985 | subseg_e->flags = 0; | |
9986 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9987 | subseg_e->target_freq = 1.0; |
9988 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9989 | subseg_e->next = sseg_map; |
9990 | sseg_map = subseg_e; | |
43cd72b9 BW |
9991 | return subseg_e; |
9992 | } | |
e0001a05 | 9993 | |
7fa3d080 BW |
9994 | |
9995 | static unsigned | |
9996 | get_last_insn_flags (segT seg, subsegT subseg) | |
9997 | { | |
9998 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9999 | if (subseg_e) |
10000 | return subseg_e->flags; | |
10001 | return 0; | |
7fa3d080 BW |
10002 | } |
10003 | ||
10004 | ||
43cd72b9 | 10005 | static void |
7fa3d080 BW |
10006 | set_last_insn_flags (segT seg, |
10007 | subsegT subseg, | |
10008 | unsigned fl, | |
10009 | bfd_boolean val) | |
43cd72b9 BW |
10010 | { |
10011 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
10012 | if (! subseg_e) |
10013 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
10014 | if (val) |
10015 | subseg_e->flags |= fl; | |
10016 | else | |
10017 | subseg_e->flags &= ~fl; | |
10018 | } | |
10019 | ||
b08b5071 BW |
10020 | |
10021 | static float | |
10022 | get_subseg_total_freq (segT seg, subsegT subseg) | |
10023 | { | |
10024 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10025 | if (subseg_e) | |
10026 | return subseg_e->total_freq; | |
10027 | return 1.0; | |
10028 | } | |
10029 | ||
10030 | ||
10031 | static float | |
10032 | get_subseg_target_freq (segT seg, subsegT subseg) | |
10033 | { | |
10034 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10035 | if (subseg_e) | |
10036 | return subseg_e->target_freq; | |
10037 | return 1.0; | |
10038 | } | |
10039 | ||
10040 | ||
10041 | static void | |
10042 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
10043 | { | |
10044 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10045 | if (! subseg_e) | |
10046 | subseg_e = add_subseg_info (seg, subseg); | |
10047 | subseg_e->total_freq = total_f; | |
10048 | subseg_e->target_freq = target_f; | |
10049 | } | |
10050 | ||
e0001a05 NC |
10051 | \f |
10052 | /* Segment Lists and emit_state Stuff. */ | |
10053 | ||
e0001a05 | 10054 | static void |
7fa3d080 | 10055 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
10056 | { |
10057 | head = head->next; | |
10058 | while (head) | |
10059 | { | |
10060 | segT literal_section = head->seg; | |
10061 | ||
10062 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 10063 | gas_assert (literal_section); |
69852798 AM |
10064 | if (literal_section != stdoutput->sections) |
10065 | { | |
10066 | bfd_section_list_remove (stdoutput, literal_section); | |
10067 | bfd_section_list_prepend (stdoutput, literal_section); | |
10068 | } | |
e0001a05 NC |
10069 | head = head->next; |
10070 | } | |
10071 | } | |
10072 | ||
10073 | ||
7fa3d080 BW |
10074 | static void mark_literal_frags (seg_list *); |
10075 | ||
10076 | static void | |
10077 | xtensa_move_literals (void) | |
e0001a05 NC |
10078 | { |
10079 | seg_list *segment; | |
10080 | frchainS *frchain_from, *frchain_to; | |
10081 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
10082 | fragS **frag_splice; | |
10083 | emit_state state; | |
10084 | segT dest_seg; | |
10085 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 10086 | sym_list *lit; |
e0001a05 | 10087 | |
a7877748 | 10088 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
10089 | |
10090 | if (use_literal_section) | |
10091 | return; | |
10092 | ||
74869ac7 | 10093 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 10094 | { |
74869ac7 BW |
10095 | /* Keep the literals for .init and .fini in separate sections. */ |
10096 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
10097 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
10098 | continue; | |
10099 | ||
e0001a05 NC |
10100 | frchain_from = seg_info (segment->seg)->frchainP; |
10101 | search_frag = frchain_from->frch_root; | |
10102 | literal_pool = NULL; | |
10103 | frchain_to = NULL; | |
10104 | frag_splice = &(frchain_from->frch_root); | |
10105 | ||
10106 | while (!search_frag->tc_frag_data.literal_frag) | |
10107 | { | |
9c2799c2 | 10108 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
10109 | || search_frag->fr_type == rs_align); |
10110 | search_frag = search_frag->fr_next; | |
10111 | } | |
10112 | ||
9c2799c2 | 10113 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
10114 | == RELAX_LITERAL_POOL_BEGIN); |
10115 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
10116 | ||
10117 | /* Make sure that all the frags in this series are closed, and | |
10118 | that there is at least one left over of zero-size. This | |
10119 | prevents us from making a segment with an frchain without any | |
10120 | frags in it. */ | |
10121 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10122 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10123 | last_frag = frag_now; |
10124 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10125 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10126 | |
43cd72b9 | 10127 | while (search_frag != frag_now) |
e0001a05 NC |
10128 | { |
10129 | next_frag = search_frag->fr_next; | |
10130 | ||
43cd72b9 | 10131 | /* First, move the frag out of the literal section and |
e0001a05 NC |
10132 | to the appropriate place. */ |
10133 | if (search_frag->tc_frag_data.literal_frag) | |
10134 | { | |
10135 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 10136 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 10137 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 10138 | gas_assert (frchain_to); |
e0001a05 | 10139 | } |
c48aaca0 | 10140 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 10141 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 10142 | |
e0001a05 NC |
10143 | *frag_splice = next_frag; |
10144 | search_frag->fr_next = insert_after->fr_next; | |
10145 | insert_after->fr_next = search_frag; | |
10146 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 10147 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
10148 | |
10149 | /* Now move any fixups associated with this frag to the | |
10150 | right section. */ | |
10151 | fix = frchain_from->fix_root; | |
10152 | fix_splice = &(frchain_from->fix_root); | |
10153 | while (fix) | |
10154 | { | |
10155 | next_fix = fix->fx_next; | |
10156 | if (fix->fx_frag == search_frag) | |
10157 | { | |
10158 | *fix_splice = next_fix; | |
10159 | fix->fx_next = frchain_to->fix_root; | |
10160 | frchain_to->fix_root = fix; | |
10161 | if (frchain_to->fix_tail == NULL) | |
10162 | frchain_to->fix_tail = fix; | |
10163 | } | |
10164 | else | |
10165 | fix_splice = &(fix->fx_next); | |
10166 | fix = next_fix; | |
10167 | } | |
10168 | search_frag = next_frag; | |
10169 | } | |
10170 | ||
10171 | if (frchain_from->fix_root != NULL) | |
10172 | { | |
10173 | frchain_from = seg_info (segment->seg)->frchainP; | |
10174 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
10175 | ||
9c2799c2 | 10176 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
10177 | } |
10178 | frchain_from->fix_tail = NULL; | |
10179 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
10180 | } |
10181 | ||
82e7541d BW |
10182 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
10183 | for (lit = literal_syms; lit; lit = lit->next) | |
10184 | { | |
10185 | symbolS *lit_sym = lit->sym; | |
10186 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
10187 | if (dest_seg) |
10188 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 10189 | } |
e0001a05 NC |
10190 | } |
10191 | ||
10192 | ||
a7877748 BW |
10193 | /* Walk over all the frags for segments in a list and mark them as |
10194 | containing literals. As clunky as this is, we can't rely on frag_var | |
10195 | and frag_variant to get called in all situations. */ | |
10196 | ||
10197 | static void | |
7fa3d080 | 10198 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
10199 | { |
10200 | frchainS *frchain_from; | |
10201 | fragS *search_frag; | |
10202 | ||
10203 | while (segment) | |
10204 | { | |
10205 | frchain_from = seg_info (segment->seg)->frchainP; | |
10206 | search_frag = frchain_from->frch_root; | |
c138bc38 | 10207 | while (search_frag) |
a7877748 BW |
10208 | { |
10209 | search_frag->tc_frag_data.is_literal = TRUE; | |
10210 | search_frag = search_frag->fr_next; | |
10211 | } | |
10212 | segment = segment->next; | |
10213 | } | |
10214 | } | |
10215 | ||
10216 | ||
e0001a05 | 10217 | static void |
7fa3d080 | 10218 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
10219 | { |
10220 | /* Move all of the sections in the section list to come | |
10221 | after "after" in the gnu segment list. */ | |
10222 | ||
10223 | head = head->next; | |
10224 | while (head) | |
10225 | { | |
10226 | segT literal_section = head->seg; | |
10227 | ||
10228 | /* Move the literal section after "after". */ | |
9c2799c2 | 10229 | gas_assert (literal_section); |
e0001a05 NC |
10230 | if (literal_section != after) |
10231 | { | |
69852798 AM |
10232 | bfd_section_list_remove (stdoutput, literal_section); |
10233 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
10234 | } |
10235 | ||
10236 | head = head->next; | |
10237 | } | |
10238 | } | |
10239 | ||
10240 | ||
10241 | /* Push all the literal segments to the end of the gnu list. */ | |
10242 | ||
7fa3d080 BW |
10243 | static void |
10244 | xtensa_reorder_segments (void) | |
e0001a05 NC |
10245 | { |
10246 | segT sec; | |
b08b5071 | 10247 | segT last_sec = 0; |
e0001a05 NC |
10248 | int old_count = 0; |
10249 | int new_count = 0; | |
10250 | ||
10251 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
10252 | { |
10253 | last_sec = sec; | |
10254 | old_count++; | |
10255 | } | |
e0001a05 NC |
10256 | |
10257 | /* Now that we have the last section, push all the literal | |
10258 | sections to the end. */ | |
e0001a05 | 10259 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
10260 | |
10261 | /* Now perform the final error check. */ | |
10262 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10263 | new_count++; | |
9c2799c2 | 10264 | gas_assert (new_count == old_count); |
e0001a05 NC |
10265 | } |
10266 | ||
10267 | ||
e0001a05 NC |
10268 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10269 | correct location. Return a emit_state which can be passed to | |
10270 | xtensa_restore_emit_state to return to current fragment. */ | |
10271 | ||
7fa3d080 BW |
10272 | static void |
10273 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10274 | { |
10275 | if (directive_state[directive_absolute_literals]) | |
10276 | { | |
74869ac7 BW |
10277 | segT lit4_seg = cache_literal_section (TRUE); |
10278 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
10279 | } |
10280 | else | |
10281 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10282 | ||
10283 | /* Do a 4-byte align here. */ | |
10284 | frag_align (2, 0, 0); | |
10285 | record_alignment (now_seg, 2); | |
10286 | } | |
10287 | ||
10288 | ||
7fa3d080 BW |
10289 | static void |
10290 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 10291 | { |
e0001a05 NC |
10292 | static bfd_boolean recursive = FALSE; |
10293 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 10294 | segT lit_seg; |
c138bc38 | 10295 | bfd_boolean is_init = |
e0001a05 | 10296 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 10297 | bfd_boolean is_fini = |
e0001a05 | 10298 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 10299 | |
43cd72b9 BW |
10300 | if (pool_location == NULL |
10301 | && !use_literal_section | |
e0001a05 NC |
10302 | && !recursive |
10303 | && !is_init && ! is_fini) | |
10304 | { | |
43cd72b9 | 10305 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
10306 | |
10307 | /* When we mark a literal pool location, we want to put a frag in | |
10308 | the literal pool that points to it. But to do that, we want to | |
10309 | switch_to_literal_fragment. But literal sections don't have | |
10310 | literal pools, so their location is always null, so we would | |
10311 | recurse forever. This is kind of hacky, but it works. */ | |
10312 | ||
e0001a05 | 10313 | recursive = TRUE; |
61846f28 | 10314 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10315 | recursive = FALSE; |
10316 | } | |
10317 | ||
74869ac7 BW |
10318 | lit_seg = cache_literal_section (FALSE); |
10319 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 10320 | |
43cd72b9 BW |
10321 | if (!use_literal_section |
10322 | && !is_init && !is_fini | |
10323 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10324 | { |
10325 | /* Close whatever frag is there. */ | |
10326 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10327 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10328 | frag_now->tc_frag_data.literal_frag = pool_location; |
10329 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10330 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10331 | } |
e0001a05 NC |
10332 | } |
10333 | ||
10334 | ||
10335 | /* Call this function before emitting data into the literal section. | |
10336 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10337 | This is similar to a .section new_now_seg subseg. */ | |
10338 | ||
7fa3d080 BW |
10339 | static void |
10340 | xtensa_switch_section_emit_state (emit_state *state, | |
10341 | segT new_now_seg, | |
10342 | subsegT new_now_subseg) | |
e0001a05 NC |
10343 | { |
10344 | state->name = now_seg->name; | |
10345 | state->now_seg = now_seg; | |
10346 | state->now_subseg = now_subseg; | |
10347 | state->generating_literals = generating_literals; | |
10348 | generating_literals++; | |
2b0210eb | 10349 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10350 | } |
10351 | ||
10352 | ||
10353 | /* Use to restore the emitting into the normal place. */ | |
10354 | ||
7fa3d080 BW |
10355 | static void |
10356 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10357 | { |
10358 | generating_literals = state->generating_literals; | |
2b0210eb | 10359 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10360 | } |
10361 | ||
10362 | ||
74869ac7 | 10363 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10364 | |
74869ac7 BW |
10365 | static bfd_boolean |
10366 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10367 | { |
74869ac7 BW |
10368 | const char *gname = inf; |
10369 | const char *group_name = elf_group_name (sec); | |
10370 | ||
10371 | return (group_name == gname | |
10372 | || (group_name != NULL | |
10373 | && gname != NULL | |
10374 | && strcmp (group_name, gname) == 0)); | |
10375 | } | |
e0001a05 | 10376 | |
e0001a05 | 10377 | |
74869ac7 BW |
10378 | /* Get the literal section to be used for the current text section. |
10379 | The result may be cached in the default_lit_sections structure. */ | |
10380 | ||
10381 | static segT | |
10382 | cache_literal_section (bfd_boolean use_abs_literals) | |
10383 | { | |
10384 | const char *text_name, *group_name = 0; | |
10385 | char *base_name, *name, *suffix; | |
10386 | segT *pcached; | |
10387 | segT seg, current_section; | |
10388 | int current_subsec; | |
10389 | bfd_boolean linkonce = FALSE; | |
10390 | ||
10391 | /* Save the current section/subsection. */ | |
10392 | current_section = now_seg; | |
10393 | current_subsec = now_subseg; | |
10394 | ||
10395 | /* Clear the cached values if they are no longer valid. */ | |
10396 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10397 | { |
74869ac7 BW |
10398 | default_lit_sections.current_text_seg = now_seg; |
10399 | default_lit_sections.lit_seg = NULL; | |
10400 | default_lit_sections.lit4_seg = NULL; | |
10401 | } | |
10402 | ||
10403 | /* Check if the literal section is already cached. */ | |
10404 | if (use_abs_literals) | |
10405 | pcached = &default_lit_sections.lit4_seg; | |
10406 | else | |
10407 | pcached = &default_lit_sections.lit_seg; | |
10408 | ||
10409 | if (*pcached) | |
10410 | return *pcached; | |
10411 | ||
10412 | text_name = default_lit_sections.lit_prefix; | |
10413 | if (! text_name || ! *text_name) | |
10414 | { | |
10415 | text_name = segment_name (current_section); | |
10416 | group_name = elf_group_name (current_section); | |
10417 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10418 | } | |
10419 | ||
10420 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10421 | if (group_name) | |
10422 | { | |
10423 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10424 | sprintf (name, "%s.%s", base_name, group_name); | |
10425 | } | |
10426 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10427 | { | |
10428 | suffix = strchr (text_name + linkonce_len, '.'); | |
10429 | ||
10430 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10431 | + (suffix ? strlen (suffix) : 0)); | |
10432 | strcpy (name, ".gnu.linkonce"); | |
10433 | strcat (name, base_name); | |
10434 | if (suffix) | |
10435 | strcat (name, suffix); | |
10436 | linkonce = TRUE; | |
10437 | } | |
10438 | else | |
10439 | { | |
10440 | /* If the section name ends with ".text", then replace that suffix | |
10441 | instead of appending an additional suffix. */ | |
10442 | size_t len = strlen (text_name); | |
10443 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10444 | len -= 5; | |
10445 | ||
10446 | name = xmalloc (len + strlen (base_name) + 1); | |
10447 | strcpy (name, text_name); | |
10448 | strcpy (name + len, base_name); | |
b08b5071 | 10449 | } |
e0001a05 | 10450 | |
74869ac7 BW |
10451 | /* Canonicalize section names to allow renaming literal sections. |
10452 | The group name, if any, came from the current text section and | |
10453 | has already been canonicalized. */ | |
10454 | name = tc_canonicalize_symbol_name (name); | |
10455 | ||
10456 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10457 | (void *) group_name); | |
10458 | if (! seg) | |
e0001a05 | 10459 | { |
74869ac7 BW |
10460 | flagword flags; |
10461 | ||
10462 | seg = subseg_force_new (name, 0); | |
10463 | ||
10464 | if (! use_abs_literals) | |
b08b5071 | 10465 | { |
74869ac7 | 10466 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10467 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10468 | n->seg = seg; | |
74869ac7 BW |
10469 | n->next = literal_head->next; |
10470 | literal_head->next = n; | |
b08b5071 | 10471 | } |
74869ac7 BW |
10472 | |
10473 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10474 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10475 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10476 | ||
10477 | elf_group_name (seg) = group_name; | |
10478 | ||
10479 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10480 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10481 | } |
10482 | ||
74869ac7 | 10483 | *pcached = seg; |
b08b5071 | 10484 | subseg_set (current_section, current_subsec); |
74869ac7 | 10485 | return seg; |
e0001a05 NC |
10486 | } |
10487 | ||
43cd72b9 BW |
10488 | \f |
10489 | /* Property Tables Stuff. */ | |
10490 | ||
7fa3d080 BW |
10491 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10492 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10493 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10494 | ||
10495 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10496 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10497 | ||
b08b5071 | 10498 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10499 | static void xtensa_create_property_segments |
10500 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10501 | static void xtensa_create_xproperty_segments | |
10502 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 10503 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
10504 | static bfd_boolean section_has_property (segT, frag_predicate); |
10505 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10506 | static void add_xt_block_frags | |
542f8b94 | 10507 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
10508 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
10509 | static void xtensa_frag_flags_init (frag_flags *); | |
10510 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 10511 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 10512 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
10513 | |
10514 | /* Set up property tables after relaxation. */ | |
10515 | ||
10516 | void | |
10517 | xtensa_post_relax_hook (void) | |
10518 | { | |
10519 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10520 | |
10521 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 10522 | xtensa_mark_frags_for_org (); |
6a7eedfe | 10523 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 10524 | |
b29757dc BW |
10525 | xtensa_create_property_segments (get_frag_is_literal, |
10526 | NULL, | |
10527 | XTENSA_LIT_SEC_NAME, | |
10528 | xt_literal_sec); | |
7fa3d080 BW |
10529 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10530 | XTENSA_PROP_SEC_NAME, | |
10531 | xt_prop_sec); | |
10532 | ||
10533 | if (warn_unaligned_branch_targets) | |
10534 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10535 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10536 | } | |
10537 | ||
10538 | ||
43cd72b9 BW |
10539 | /* This function is only meaningful after xtensa_move_literals. */ |
10540 | ||
10541 | static bfd_boolean | |
7fa3d080 | 10542 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 10543 | { |
9c2799c2 | 10544 | gas_assert (fragP != NULL); |
43cd72b9 BW |
10545 | return fragP->tc_frag_data.is_literal; |
10546 | } | |
10547 | ||
10548 | ||
43cd72b9 | 10549 | static void |
7fa3d080 BW |
10550 | xtensa_create_property_segments (frag_predicate property_function, |
10551 | frag_predicate end_property_function, | |
10552 | const char *section_name_base, | |
10553 | xt_section_type sec_type) | |
43cd72b9 BW |
10554 | { |
10555 | segT *seclist; | |
10556 | ||
10557 | /* Walk over all of the current segments. | |
10558 | Walk over each fragment | |
10559 | For each non-empty fragment, | |
10560 | Build a property record (append where possible). */ | |
10561 | ||
10562 | for (seclist = &stdoutput->sections; | |
10563 | seclist && *seclist; | |
10564 | seclist = &(*seclist)->next) | |
10565 | { | |
10566 | segT sec = *seclist; | |
43cd72b9 | 10567 | |
532f93bd | 10568 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
10569 | continue; |
10570 | ||
10571 | if (section_has_property (sec, property_function)) | |
10572 | { | |
542f8b94 BW |
10573 | segment_info_type *xt_seg_info; |
10574 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 10575 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
10576 | |
10577 | prop_sec->output_section = prop_sec; | |
10578 | subseg_set (prop_sec, 0); | |
10579 | xt_seg_info = seg_info (prop_sec); | |
10580 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10581 | ||
43cd72b9 | 10582 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10583 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
10584 | end_property_function); |
10585 | } | |
10586 | } | |
10587 | ||
10588 | /* Now we fill them out.... */ | |
10589 | ||
10590 | for (seclist = &stdoutput->sections; | |
10591 | seclist && *seclist; | |
10592 | seclist = &(*seclist)->next) | |
10593 | { | |
10594 | segment_info_type *seginfo; | |
10595 | xtensa_block_info *block; | |
10596 | segT sec = *seclist; | |
10597 | ||
10598 | seginfo = seg_info (sec); | |
10599 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10600 | ||
10601 | if (block) | |
10602 | { | |
10603 | xtensa_block_info *cur_block; | |
43cd72b9 | 10604 | int num_recs = 0; |
d77b99c9 | 10605 | bfd_size_type rec_size; |
43cd72b9 BW |
10606 | |
10607 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10608 | num_recs++; | |
10609 | ||
10610 | rec_size = num_recs * 8; | |
10611 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10612 | ||
43cd72b9 BW |
10613 | if (num_recs) |
10614 | { | |
43cd72b9 | 10615 | char *frag_data; |
542f8b94 | 10616 | int i; |
43cd72b9 | 10617 | |
542f8b94 BW |
10618 | subseg_set (sec, 0); |
10619 | frag_data = frag_more (rec_size); | |
43cd72b9 | 10620 | cur_block = block; |
43cd72b9 BW |
10621 | for (i = 0; i < num_recs; i++) |
10622 | { | |
542f8b94 | 10623 | fixS *fix; |
e0001a05 | 10624 | |
43cd72b9 | 10625 | /* Write the fixup. */ |
9c2799c2 | 10626 | gas_assert (cur_block); |
542f8b94 BW |
10627 | fix = fix_new (frag_now, i * 8, 4, |
10628 | section_symbol (cur_block->sec), | |
10629 | cur_block->offset, | |
10630 | FALSE, BFD_RELOC_32); | |
10631 | fix->fx_file = "<internal>"; | |
43cd72b9 | 10632 | fix->fx_line = 0; |
e0001a05 | 10633 | |
43cd72b9 | 10634 | /* Write the length. */ |
542f8b94 | 10635 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
10636 | cur_block->size, 4); |
10637 | cur_block = cur_block->next; | |
10638 | } | |
542f8b94 BW |
10639 | frag_wane (frag_now); |
10640 | frag_new (0); | |
10641 | frag_wane (frag_now); | |
43cd72b9 BW |
10642 | } |
10643 | } | |
10644 | } | |
e0001a05 NC |
10645 | } |
10646 | ||
10647 | ||
7fa3d080 BW |
10648 | static void |
10649 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10650 | const char *section_name_base, | |
10651 | xt_section_type sec_type) | |
e0001a05 NC |
10652 | { |
10653 | segT *seclist; | |
10654 | ||
10655 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10656 | Walk over each fragment. |
10657 | For each fragment that has instructions, | |
10658 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10659 | |
10660 | for (seclist = &stdoutput->sections; | |
10661 | seclist && *seclist; | |
10662 | seclist = &(*seclist)->next) | |
10663 | { | |
10664 | segT sec = *seclist; | |
43cd72b9 | 10665 | |
532f93bd | 10666 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
10667 | continue; |
10668 | ||
10669 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10670 | { |
542f8b94 BW |
10671 | segment_info_type *xt_seg_info; |
10672 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 10673 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
10674 | |
10675 | prop_sec->output_section = prop_sec; | |
10676 | subseg_set (prop_sec, 0); | |
10677 | xt_seg_info = seg_info (prop_sec); | |
10678 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10679 | ||
e0001a05 | 10680 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10681 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
10682 | } |
10683 | } | |
10684 | ||
10685 | /* Now we fill them out.... */ | |
10686 | ||
10687 | for (seclist = &stdoutput->sections; | |
10688 | seclist && *seclist; | |
10689 | seclist = &(*seclist)->next) | |
10690 | { | |
10691 | segment_info_type *seginfo; | |
10692 | xtensa_block_info *block; | |
10693 | segT sec = *seclist; | |
43cd72b9 | 10694 | |
e0001a05 NC |
10695 | seginfo = seg_info (sec); |
10696 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10697 | ||
10698 | if (block) | |
10699 | { | |
10700 | xtensa_block_info *cur_block; | |
43cd72b9 | 10701 | int num_recs = 0; |
d77b99c9 | 10702 | bfd_size_type rec_size; |
e0001a05 NC |
10703 | |
10704 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10705 | num_recs++; | |
10706 | ||
43cd72b9 | 10707 | rec_size = num_recs * (8 + 4); |
e0001a05 | 10708 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
10709 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10710 | ||
e0001a05 NC |
10711 | if (num_recs) |
10712 | { | |
e0001a05 | 10713 | char *frag_data; |
542f8b94 | 10714 | int i; |
e0001a05 | 10715 | |
542f8b94 BW |
10716 | subseg_set (sec, 0); |
10717 | frag_data = frag_more (rec_size); | |
e0001a05 | 10718 | cur_block = block; |
e0001a05 NC |
10719 | for (i = 0; i < num_recs; i++) |
10720 | { | |
542f8b94 | 10721 | fixS *fix; |
e0001a05 NC |
10722 | |
10723 | /* Write the fixup. */ | |
9c2799c2 | 10724 | gas_assert (cur_block); |
542f8b94 BW |
10725 | fix = fix_new (frag_now, i * 12, 4, |
10726 | section_symbol (cur_block->sec), | |
10727 | cur_block->offset, | |
10728 | FALSE, BFD_RELOC_32); | |
10729 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
10730 | fix->fx_line = 0; |
10731 | ||
10732 | /* Write the length. */ | |
542f8b94 | 10733 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 10734 | cur_block->size, 4); |
542f8b94 | 10735 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 10736 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 10737 | sizeof (flagword)); |
e0001a05 NC |
10738 | cur_block = cur_block->next; |
10739 | } | |
542f8b94 BW |
10740 | frag_wane (frag_now); |
10741 | frag_new (0); | |
10742 | frag_wane (frag_now); | |
e0001a05 NC |
10743 | } |
10744 | } | |
10745 | } | |
10746 | } | |
10747 | ||
10748 | ||
532f93bd BW |
10749 | static bfd_boolean |
10750 | exclude_section_from_property_tables (segT sec) | |
10751 | { | |
10752 | flagword flags = bfd_get_section_flags (stdoutput, sec); | |
10753 | ||
10754 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
10755 | if ((flags & SEC_DEBUGGING) | |
10756 | || !(flags & SEC_ALLOC) | |
10757 | || (flags & SEC_MERGE)) | |
10758 | return TRUE; | |
10759 | ||
10760 | /* Linker cie and fde optimizations mess up property entries for | |
10761 | eh_frame sections, but there is nothing inside them relevant to | |
10762 | property tables anyway. */ | |
10763 | if (strcmp (sec->name, ".eh_frame") == 0) | |
10764 | return TRUE; | |
10765 | ||
10766 | return FALSE; | |
10767 | } | |
10768 | ||
10769 | ||
7fa3d080 BW |
10770 | static bfd_boolean |
10771 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10772 | { |
10773 | segment_info_type *seginfo = seg_info (sec); | |
10774 | fragS *fragP; | |
10775 | ||
10776 | if (seginfo && seginfo->frchainP) | |
10777 | { | |
10778 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10779 | { | |
10780 | if (property_function (fragP) | |
10781 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10782 | return TRUE; | |
10783 | } | |
10784 | } | |
10785 | return FALSE; | |
10786 | } | |
10787 | ||
10788 | ||
7fa3d080 BW |
10789 | static bfd_boolean |
10790 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10791 | { |
10792 | segment_info_type *seginfo = seg_info (sec); | |
10793 | fragS *fragP; | |
10794 | ||
10795 | if (seginfo && seginfo->frchainP) | |
10796 | { | |
10797 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10798 | { | |
10799 | frag_flags prop_flags; | |
10800 | property_function (fragP, &prop_flags); | |
10801 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10802 | return TRUE; | |
10803 | } | |
10804 | } | |
10805 | return FALSE; | |
10806 | } | |
10807 | ||
10808 | ||
e0001a05 NC |
10809 | /* Two types of block sections exist right now: literal and insns. */ |
10810 | ||
7fa3d080 BW |
10811 | static void |
10812 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
10813 | xtensa_block_info **xt_block, |
10814 | frag_predicate property_function, | |
10815 | frag_predicate end_property_function) | |
e0001a05 | 10816 | { |
e0001a05 NC |
10817 | fragS *fragP; |
10818 | ||
e0001a05 NC |
10819 | /* Build it if needed. */ |
10820 | while (*xt_block != NULL) | |
10821 | xt_block = &(*xt_block)->next; | |
10822 | /* We are either at NULL at the beginning or at the end. */ | |
10823 | ||
10824 | /* Walk through the frags. */ | |
542f8b94 | 10825 | if (seg_info (sec)->frchainP) |
e0001a05 | 10826 | { |
542f8b94 | 10827 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
10828 | fragP; |
10829 | fragP = fragP->fr_next) | |
10830 | { | |
10831 | if (property_function (fragP) | |
10832 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10833 | { | |
10834 | if (*xt_block != NULL) | |
10835 | { | |
10836 | if ((*xt_block)->offset + (*xt_block)->size | |
10837 | == fragP->fr_address) | |
10838 | (*xt_block)->size += fragP->fr_fix; | |
10839 | else | |
10840 | xt_block = &((*xt_block)->next); | |
10841 | } | |
10842 | if (*xt_block == NULL) | |
10843 | { | |
43cd72b9 BW |
10844 | xtensa_block_info *new_block = (xtensa_block_info *) |
10845 | xmalloc (sizeof (xtensa_block_info)); | |
10846 | new_block->sec = sec; | |
10847 | new_block->offset = fragP->fr_address; | |
10848 | new_block->size = fragP->fr_fix; | |
10849 | new_block->next = NULL; | |
10850 | xtensa_frag_flags_init (&new_block->flags); | |
10851 | *xt_block = new_block; | |
10852 | } | |
10853 | if (end_property_function | |
10854 | && end_property_function (fragP)) | |
10855 | { | |
10856 | xt_block = &((*xt_block)->next); | |
10857 | } | |
10858 | } | |
10859 | } | |
10860 | } | |
10861 | } | |
10862 | ||
10863 | ||
10864 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10865 | ||
7fa3d080 BW |
10866 | static bfd_boolean |
10867 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10868 | { |
10869 | if (prop_flags->is_literal | |
10870 | || prop_flags->is_insn | |
10871 | || prop_flags->is_data | |
10872 | || prop_flags->is_unreachable) | |
10873 | return FALSE; | |
10874 | return TRUE; | |
10875 | } | |
10876 | ||
10877 | ||
7fa3d080 BW |
10878 | static void |
10879 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10880 | { |
10881 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10882 | } | |
10883 | ||
10884 | ||
7fa3d080 BW |
10885 | static void |
10886 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10887 | { |
10888 | xtensa_frag_flags_init (prop_flags); | |
10889 | if (fragP->tc_frag_data.is_literal) | |
10890 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
10891 | if (fragP->tc_frag_data.is_specific_opcode |
10892 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
10893 | { |
10894 | prop_flags->is_no_transform = TRUE; | |
10895 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10896 | prop_flags->is_data = TRUE; | |
10897 | } | |
43cd72b9 | 10898 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 10899 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10900 | else if (fragP->tc_frag_data.is_insn) |
10901 | { | |
10902 | prop_flags->is_insn = TRUE; | |
10903 | if (fragP->tc_frag_data.is_loop_target) | |
10904 | prop_flags->insn.is_loop_target = TRUE; | |
10905 | if (fragP->tc_frag_data.is_branch_target) | |
10906 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
10907 | if (fragP->tc_frag_data.is_no_density) |
10908 | prop_flags->insn.is_no_density = TRUE; | |
10909 | if (fragP->tc_frag_data.use_absolute_literals) | |
10910 | prop_flags->insn.is_abslit = TRUE; | |
10911 | } | |
10912 | if (fragP->tc_frag_data.is_align) | |
10913 | { | |
10914 | prop_flags->is_align = TRUE; | |
10915 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10916 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10917 | prop_flags->is_data = TRUE; | |
10918 | } | |
10919 | } | |
10920 | ||
10921 | ||
2f1bf5c1 | 10922 | static flagword |
7fa3d080 | 10923 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 10924 | { |
2f1bf5c1 | 10925 | flagword num = 0; |
43cd72b9 BW |
10926 | if (prop_flags->is_literal) |
10927 | num |= XTENSA_PROP_LITERAL; | |
10928 | if (prop_flags->is_insn) | |
10929 | num |= XTENSA_PROP_INSN; | |
10930 | if (prop_flags->is_data) | |
10931 | num |= XTENSA_PROP_DATA; | |
10932 | if (prop_flags->is_unreachable) | |
10933 | num |= XTENSA_PROP_UNREACHABLE; | |
10934 | if (prop_flags->insn.is_loop_target) | |
10935 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10936 | if (prop_flags->insn.is_branch_target) | |
10937 | { | |
10938 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10939 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10940 | } | |
10941 | ||
10942 | if (prop_flags->insn.is_no_density) | |
10943 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
10944 | if (prop_flags->is_no_transform) |
10945 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
10946 | if (prop_flags->insn.is_no_reorder) |
10947 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10948 | if (prop_flags->insn.is_abslit) | |
10949 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10950 | ||
10951 | if (prop_flags->is_align) | |
10952 | { | |
10953 | num |= XTENSA_PROP_ALIGN; | |
10954 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10955 | } | |
10956 | ||
10957 | return num; | |
10958 | } | |
10959 | ||
10960 | ||
10961 | static bfd_boolean | |
7fa3d080 BW |
10962 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10963 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10964 | { |
10965 | /* Cannot combine with an end marker. */ | |
10966 | ||
10967 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10968 | return FALSE; | |
10969 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10970 | return FALSE; | |
10971 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10972 | return FALSE; | |
10973 | ||
10974 | if (prop_flags_1->is_insn) | |
10975 | { | |
10976 | /* Properties of the beginning of the frag. */ | |
10977 | if (prop_flags_2->insn.is_loop_target) | |
10978 | return FALSE; | |
10979 | if (prop_flags_2->insn.is_branch_target) | |
10980 | return FALSE; | |
10981 | if (prop_flags_1->insn.is_no_density != | |
10982 | prop_flags_2->insn.is_no_density) | |
10983 | return FALSE; | |
99ded152 BW |
10984 | if (prop_flags_1->is_no_transform != |
10985 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
10986 | return FALSE; |
10987 | if (prop_flags_1->insn.is_no_reorder != | |
10988 | prop_flags_2->insn.is_no_reorder) | |
10989 | return FALSE; | |
10990 | if (prop_flags_1->insn.is_abslit != | |
10991 | prop_flags_2->insn.is_abslit) | |
10992 | return FALSE; | |
10993 | } | |
10994 | ||
10995 | if (prop_flags_1->is_align) | |
10996 | return FALSE; | |
10997 | ||
10998 | return TRUE; | |
10999 | } | |
11000 | ||
11001 | ||
7fa3d080 BW |
11002 | static bfd_vma |
11003 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
11004 | { |
11005 | bfd_vma end_addr; | |
d77b99c9 | 11006 | unsigned align_bits; |
43cd72b9 BW |
11007 | |
11008 | if (!xt_block->flags.is_align) | |
11009 | return xt_block->size; | |
11010 | ||
11011 | end_addr = xt_block->offset + xt_block->size; | |
11012 | align_bits = xt_block->flags.alignment; | |
11013 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
11014 | return end_addr - xt_block->offset; | |
11015 | } | |
11016 | ||
11017 | ||
11018 | static bfd_boolean | |
7fa3d080 BW |
11019 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
11020 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
11021 | { |
11022 | if (xt_block->sec != xt_block_2->sec) | |
11023 | return FALSE; | |
11024 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
11025 | != xt_block_2->offset) | |
11026 | return FALSE; | |
11027 | ||
11028 | if (xt_block_2->size == 0 | |
11029 | && (!xt_block_2->flags.is_unreachable | |
11030 | || xt_block->flags.is_unreachable)) | |
11031 | { | |
11032 | if (xt_block_2->flags.is_align | |
11033 | && xt_block->flags.is_align) | |
11034 | { | |
11035 | /* Nothing needed. */ | |
11036 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
11037 | return TRUE; | |
11038 | } | |
11039 | else | |
11040 | { | |
11041 | if (xt_block_2->flags.is_align) | |
11042 | { | |
11043 | /* Push alignment to previous entry. */ | |
11044 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
11045 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
11046 | } | |
11047 | return TRUE; | |
11048 | } | |
11049 | } | |
11050 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
11051 | &xt_block_2->flags)) | |
11052 | return FALSE; | |
11053 | ||
11054 | xt_block->size += xt_block_2->size; | |
11055 | ||
11056 | if (xt_block_2->flags.is_align) | |
11057 | { | |
11058 | xt_block->flags.is_align = TRUE; | |
11059 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
11060 | } | |
11061 | ||
11062 | return TRUE; | |
11063 | } | |
11064 | ||
11065 | ||
7fa3d080 BW |
11066 | static void |
11067 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
11068 | xtensa_block_info **xt_block, |
11069 | frag_flags_fn property_function) | |
43cd72b9 | 11070 | { |
43cd72b9 BW |
11071 | fragS *fragP; |
11072 | ||
43cd72b9 BW |
11073 | /* Build it if needed. */ |
11074 | while (*xt_block != NULL) | |
11075 | { | |
11076 | xt_block = &(*xt_block)->next; | |
11077 | } | |
11078 | /* We are either at NULL at the beginning or at the end. */ | |
11079 | ||
11080 | /* Walk through the frags. */ | |
542f8b94 | 11081 | if (seg_info (sec)->frchainP) |
43cd72b9 | 11082 | { |
542f8b94 | 11083 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
11084 | fragP = fragP->fr_next) |
11085 | { | |
11086 | xtensa_block_info tmp_block; | |
11087 | tmp_block.sec = sec; | |
11088 | tmp_block.offset = fragP->fr_address; | |
11089 | tmp_block.size = fragP->fr_fix; | |
11090 | tmp_block.next = NULL; | |
11091 | property_function (fragP, &tmp_block.flags); | |
11092 | ||
11093 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
11094 | /* && fragP->fr_fix != 0) */ | |
11095 | { | |
11096 | if ((*xt_block) == NULL | |
11097 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
11098 | { | |
11099 | xtensa_block_info *new_block; | |
11100 | if ((*xt_block) != NULL) | |
11101 | xt_block = &(*xt_block)->next; | |
11102 | new_block = (xtensa_block_info *) | |
11103 | xmalloc (sizeof (xtensa_block_info)); | |
11104 | *new_block = tmp_block; | |
11105 | *xt_block = new_block; | |
11106 | } | |
11107 | } | |
11108 | } | |
11109 | } | |
11110 | } | |
11111 | ||
11112 | \f | |
11113 | /* op_placement_info_table */ | |
11114 | ||
11115 | /* op_placement_info makes it easier to determine which | |
11116 | ops can go in which slots. */ | |
11117 | ||
11118 | static void | |
7fa3d080 | 11119 | init_op_placement_info_table (void) |
43cd72b9 BW |
11120 | { |
11121 | xtensa_isa isa = xtensa_default_isa; | |
11122 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
11123 | xtensa_opcode opcode; | |
11124 | xtensa_format fmt; | |
11125 | int slot; | |
11126 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
11127 | ||
11128 | op_placement_table = (op_placement_info_table) | |
11129 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
9c2799c2 | 11130 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
11131 | |
11132 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
11133 | { | |
11134 | op_placement_info *opi = &op_placement_table[opcode]; | |
11135 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 11136 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 11137 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
11138 | opi->narrowest = XTENSA_UNDEFINED; |
11139 | opi->narrowest_size = 0x7F; | |
b2d179be | 11140 | opi->narrowest_slot = 0; |
43cd72b9 BW |
11141 | opi->formats = 0; |
11142 | opi->num_formats = 0; | |
11143 | opi->issuef = 0; | |
11144 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
11145 | { | |
11146 | opi->slots[fmt] = 0; | |
11147 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
11148 | { | |
11149 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
11150 | { | |
11151 | int fmt_length = xtensa_format_length (isa, fmt); | |
11152 | opi->issuef++; | |
11153 | set_bit (fmt, opi->formats); | |
11154 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
11155 | if (fmt_length < opi->narrowest_size |
11156 | || (fmt_length == opi->narrowest_size | |
11157 | && (xtensa_format_num_slots (isa, fmt) | |
11158 | < xtensa_format_num_slots (isa, | |
11159 | opi->narrowest)))) | |
43cd72b9 BW |
11160 | { |
11161 | opi->narrowest = fmt; | |
11162 | opi->narrowest_size = fmt_length; | |
b2d179be | 11163 | opi->narrowest_slot = slot; |
43cd72b9 | 11164 | } |
e0001a05 NC |
11165 | } |
11166 | } | |
43cd72b9 BW |
11167 | if (opi->formats) |
11168 | opi->num_formats++; | |
e0001a05 NC |
11169 | } |
11170 | } | |
43cd72b9 BW |
11171 | xtensa_insnbuf_free (isa, ibuf); |
11172 | } | |
11173 | ||
11174 | ||
11175 | bfd_boolean | |
7fa3d080 | 11176 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
11177 | { |
11178 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
11179 | } | |
11180 | ||
11181 | ||
11182 | /* If the opcode is available in a single slot format, return its size. */ | |
11183 | ||
7fa3d080 BW |
11184 | static int |
11185 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 11186 | { |
b2d179be | 11187 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
11188 | } |
11189 | ||
11190 | ||
7fa3d080 BW |
11191 | static xtensa_format |
11192 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 11193 | { |
b2d179be BW |
11194 | return op_placement_table[opcode].narrowest; |
11195 | } | |
11196 | ||
11197 | ||
11198 | static int | |
11199 | xg_get_single_slot (xtensa_opcode opcode) | |
11200 | { | |
11201 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
11202 | } |
11203 | ||
11204 | \f | |
11205 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
11206 | ||
11207 | void | |
7fa3d080 | 11208 | istack_init (IStack *stack) |
e0001a05 NC |
11209 | { |
11210 | memset (stack, 0, sizeof (IStack)); | |
11211 | stack->ninsn = 0; | |
11212 | } | |
11213 | ||
11214 | ||
11215 | bfd_boolean | |
7fa3d080 | 11216 | istack_empty (IStack *stack) |
e0001a05 NC |
11217 | { |
11218 | return (stack->ninsn == 0); | |
11219 | } | |
11220 | ||
11221 | ||
11222 | bfd_boolean | |
7fa3d080 | 11223 | istack_full (IStack *stack) |
e0001a05 NC |
11224 | { |
11225 | return (stack->ninsn == MAX_ISTACK); | |
11226 | } | |
11227 | ||
11228 | ||
11229 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 11230 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
11231 | |
11232 | TInsn * | |
7fa3d080 | 11233 | istack_top (IStack *stack) |
e0001a05 NC |
11234 | { |
11235 | int rec = stack->ninsn - 1; | |
9c2799c2 | 11236 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
11237 | return &stack->insn[rec]; |
11238 | } | |
11239 | ||
11240 | ||
11241 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 11242 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11243 | |
11244 | void | |
7fa3d080 | 11245 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
11246 | { |
11247 | int rec = stack->ninsn; | |
9c2799c2 | 11248 | gas_assert (!istack_full (stack)); |
43cd72b9 | 11249 | stack->insn[rec] = *insn; |
e0001a05 NC |
11250 | stack->ninsn++; |
11251 | } | |
11252 | ||
11253 | ||
11254 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11255 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11256 | |
11257 | TInsn * | |
7fa3d080 | 11258 | istack_push_space (IStack *stack) |
e0001a05 NC |
11259 | { |
11260 | int rec = stack->ninsn; | |
11261 | TInsn *insn; | |
9c2799c2 | 11262 | gas_assert (!istack_full (stack)); |
e0001a05 | 11263 | insn = &stack->insn[rec]; |
60242db2 | 11264 | tinsn_init (insn); |
e0001a05 NC |
11265 | stack->ninsn++; |
11266 | return insn; | |
11267 | } | |
11268 | ||
11269 | ||
11270 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11271 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11272 | |
11273 | void | |
7fa3d080 | 11274 | istack_pop (IStack *stack) |
e0001a05 NC |
11275 | { |
11276 | int rec = stack->ninsn - 1; | |
9c2799c2 | 11277 | gas_assert (!istack_empty (stack)); |
e0001a05 | 11278 | stack->ninsn--; |
60242db2 | 11279 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11280 | } |
11281 | ||
11282 | \f | |
11283 | /* TInsn functions. */ | |
11284 | ||
11285 | void | |
7fa3d080 | 11286 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11287 | { |
11288 | memset (dst, 0, sizeof (TInsn)); | |
11289 | } | |
11290 | ||
11291 | ||
43cd72b9 | 11292 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11293 | |
11294 | static bfd_boolean | |
7fa3d080 | 11295 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11296 | { |
11297 | int i; | |
11298 | int n = insn->ntok; | |
11299 | ||
9c2799c2 | 11300 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
11301 | |
11302 | for (i = 0; i < n; ++i) | |
11303 | { | |
11304 | switch (insn->tok[i].X_op) | |
11305 | { | |
11306 | case O_register: | |
11307 | case O_constant: | |
11308 | break; | |
11309 | default: | |
11310 | return TRUE; | |
11311 | } | |
11312 | } | |
11313 | return FALSE; | |
11314 | } | |
11315 | ||
11316 | ||
11317 | bfd_boolean | |
7fa3d080 | 11318 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11319 | { |
43cd72b9 | 11320 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11321 | int i; |
11322 | int n = insn->ntok; | |
11323 | ||
9c2799c2 | 11324 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
11325 | |
11326 | for (i = 0; i < n; ++i) | |
11327 | { | |
11328 | switch (insn->tok[i].X_op) | |
11329 | { | |
11330 | case O_register: | |
11331 | case O_constant: | |
11332 | break; | |
43cd72b9 BW |
11333 | case O_big: |
11334 | case O_illegal: | |
11335 | case O_absent: | |
11336 | /* Errors for these types are caught later. */ | |
11337 | break; | |
11338 | case O_hi16: | |
11339 | case O_lo16: | |
e0001a05 | 11340 | default: |
43cd72b9 BW |
11341 | /* Symbolic immediates are only allowed on the last immediate |
11342 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11343 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11344 | if (i != get_relaxable_immed (insn->opcode) |
11345 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11346 | && insn->opcode != xtensa_const16_opcode)) | |
11347 | { | |
431ad2d0 | 11348 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11349 | return TRUE; |
11350 | } | |
e0001a05 NC |
11351 | } |
11352 | } | |
11353 | return FALSE; | |
11354 | } | |
11355 | ||
11356 | ||
11357 | /* For assembly code with complex expressions (e.g. subtraction), | |
11358 | we have to build them in the literal pool so that | |
11359 | their results are calculated correctly after relaxation. | |
11360 | The relaxation only handles expressions that | |
11361 | boil down to SYMBOL + OFFSET. */ | |
11362 | ||
11363 | static bfd_boolean | |
7fa3d080 | 11364 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11365 | { |
11366 | int i; | |
11367 | int n = insn->ntok; | |
9c2799c2 | 11368 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
11369 | for (i = 0; i < n; ++i) |
11370 | { | |
11371 | switch (insn->tok[i].X_op) | |
11372 | { | |
11373 | case O_register: | |
11374 | case O_constant: | |
11375 | case O_symbol: | |
43cd72b9 BW |
11376 | case O_lo16: |
11377 | case O_hi16: | |
e0001a05 NC |
11378 | break; |
11379 | default: | |
11380 | return TRUE; | |
11381 | } | |
11382 | } | |
11383 | return FALSE; | |
11384 | } | |
11385 | ||
11386 | ||
b2d179be BW |
11387 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11388 | Return TRUE if there is a symbol in the immediate field. This | |
11389 | function assumes that: | |
11390 | 1) The number of operands are correct. | |
11391 | 2) The insn_type is ITYPE_INSN. | |
11392 | 3) The opcode can be encoded in the specified format and slot. | |
11393 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11394 | |
11395 | static bfd_boolean | |
7fa3d080 BW |
11396 | tinsn_to_slotbuf (xtensa_format fmt, |
11397 | int slot, | |
11398 | TInsn *tinsn, | |
11399 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11400 | { |
11401 | xtensa_isa isa = xtensa_default_isa; | |
11402 | xtensa_opcode opcode = tinsn->opcode; | |
11403 | bfd_boolean has_fixup = FALSE; | |
11404 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11405 | int i; | |
11406 | ||
9c2799c2 | 11407 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
11408 | if (noperands != tinsn->ntok) |
11409 | as_fatal (_("operand number mismatch")); | |
11410 | ||
11411 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11412 | { | |
11413 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11414 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11415 | return FALSE; | |
11416 | } | |
11417 | ||
11418 | for (i = 0; i < noperands; i++) | |
11419 | { | |
11420 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11421 | int rc; |
11422 | unsigned line; | |
43cd72b9 BW |
11423 | char *file_name; |
11424 | uint32 opnd_value; | |
11425 | ||
11426 | switch (expr->X_op) | |
11427 | { | |
11428 | case O_register: | |
11429 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11430 | break; | |
11431 | /* The register number has already been checked in | |
11432 | expression_maybe_register, so we don't need to check here. */ | |
11433 | opnd_value = expr->X_add_number; | |
11434 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11435 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11436 | opnd_value); | |
11437 | if (rc != 0) | |
11438 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11439 | break; | |
11440 | ||
11441 | case O_constant: | |
11442 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11443 | break; | |
11444 | as_where (&file_name, &line); | |
11445 | /* It is a constant and we called this function | |
11446 | then we have to try to fit it. */ | |
11447 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11448 | expr->X_add_number, file_name, line); |
11449 | break; | |
11450 | ||
e0001a05 NC |
11451 | default: |
11452 | has_fixup = TRUE; | |
11453 | break; | |
11454 | } | |
11455 | } | |
43cd72b9 | 11456 | |
e0001a05 NC |
11457 | return has_fixup; |
11458 | } | |
11459 | ||
11460 | ||
b2d179be BW |
11461 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11462 | into a multi-slot instruction, fill the other slots with NOPs. | |
11463 | Return TRUE if there is a symbol in the immediate field. See also the | |
11464 | assumptions listed for tinsn_to_slotbuf. */ | |
11465 | ||
11466 | static bfd_boolean | |
11467 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11468 | { | |
11469 | static xtensa_insnbuf slotbuf = 0; | |
11470 | static vliw_insn vinsn; | |
11471 | xtensa_isa isa = xtensa_default_isa; | |
11472 | bfd_boolean has_fixup = FALSE; | |
11473 | int i; | |
11474 | ||
11475 | if (!slotbuf) | |
11476 | { | |
11477 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11478 | xg_init_vinsn (&vinsn); | |
11479 | } | |
11480 | ||
11481 | xg_clear_vinsn (&vinsn); | |
11482 | ||
11483 | bundle_tinsn (tinsn, &vinsn); | |
11484 | ||
11485 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11486 | ||
11487 | for (i = 0; i < vinsn.num_slots; i++) | |
11488 | { | |
11489 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11490 | has_fixup |= | |
11491 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11492 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11493 | } | |
11494 | ||
11495 | return has_fixup; | |
11496 | } | |
11497 | ||
11498 | ||
43cd72b9 | 11499 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11500 | |
7fa3d080 BW |
11501 | static bfd_boolean |
11502 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11503 | { |
11504 | xtensa_isa isa = xtensa_default_isa; | |
11505 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
11506 | xtensa_regfile t1_regfile, t2_regfile; |
11507 | int t1_reg, t2_reg; | |
11508 | int t1_base_reg, t1_last_reg; | |
11509 | int t2_base_reg, t2_last_reg; | |
11510 | char t1_inout, t2_inout; | |
11511 | int i, j; | |
e0001a05 NC |
11512 | |
11513 | if (opcode == XTENSA_UNDEFINED) | |
11514 | { | |
11515 | as_bad (_("invalid opcode")); | |
11516 | return TRUE; | |
11517 | } | |
11518 | ||
43cd72b9 | 11519 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11520 | { |
11521 | as_bad (_("too few operands")); | |
11522 | return TRUE; | |
11523 | } | |
11524 | ||
43cd72b9 | 11525 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11526 | { |
11527 | as_bad (_("too many operands")); | |
11528 | return TRUE; | |
11529 | } | |
6dc6b655 BW |
11530 | |
11531 | /* Check registers. */ | |
11532 | for (j = 0; j < insn->ntok; j++) | |
11533 | { | |
11534 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
11535 | continue; | |
11536 | ||
11537 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
11538 | t2_base_reg = insn->tok[j].X_add_number; | |
11539 | t2_last_reg | |
11540 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
11541 | ||
11542 | for (i = 0; i < insn->ntok; i++) | |
11543 | { | |
11544 | if (i == j) | |
11545 | continue; | |
11546 | ||
11547 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
11548 | continue; | |
11549 | ||
11550 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
11551 | ||
11552 | if (t1_regfile != t2_regfile) | |
11553 | continue; | |
11554 | ||
11555 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
11556 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
11557 | ||
11558 | t1_base_reg = insn->tok[i].X_add_number; | |
11559 | t1_last_reg = (t1_base_reg | |
11560 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
11561 | ||
11562 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
11563 | { | |
11564 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
11565 | { | |
11566 | if (t1_reg != t2_reg) | |
11567 | continue; | |
11568 | ||
11569 | if (t1_inout != 'i' && t2_inout != 'i') | |
11570 | { | |
11571 | as_bad (_("multiple writes to the same register")); | |
11572 | return TRUE; | |
11573 | } | |
11574 | } | |
11575 | } | |
11576 | } | |
11577 | } | |
e0001a05 NC |
11578 | return FALSE; |
11579 | } | |
11580 | ||
11581 | ||
11582 | /* Load an instruction from its encoded form. */ | |
11583 | ||
11584 | static void | |
7fa3d080 | 11585 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11586 | { |
43cd72b9 | 11587 | vliw_insn vinsn; |
e0001a05 | 11588 | |
43cd72b9 BW |
11589 | xg_init_vinsn (&vinsn); |
11590 | vinsn_from_chars (&vinsn, f); | |
11591 | ||
11592 | *tinsn = vinsn.slots[slot]; | |
11593 | xg_free_vinsn (&vinsn); | |
11594 | } | |
e0001a05 | 11595 | |
43cd72b9 BW |
11596 | |
11597 | static void | |
7fa3d080 BW |
11598 | tinsn_from_insnbuf (TInsn *tinsn, |
11599 | xtensa_insnbuf slotbuf, | |
11600 | xtensa_format fmt, | |
11601 | int slot) | |
43cd72b9 BW |
11602 | { |
11603 | int i; | |
11604 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11605 | |
11606 | /* Find the immed. */ | |
43cd72b9 BW |
11607 | tinsn_init (tinsn); |
11608 | tinsn->insn_type = ITYPE_INSN; | |
11609 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11610 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11611 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11612 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11613 | { |
43cd72b9 BW |
11614 | set_expr_const (&tinsn->tok[i], |
11615 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11616 | tinsn->opcode, i)); | |
e0001a05 NC |
11617 | } |
11618 | } | |
11619 | ||
11620 | ||
11621 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11622 | ||
11623 | static void | |
7fa3d080 | 11624 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11625 | { |
43cd72b9 | 11626 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11627 | int opnum; |
11628 | ||
43cd72b9 | 11629 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11630 | { |
11631 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 11632 | gas_assert (opnum >= 0); |
e7da6241 BW |
11633 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11634 | fragP->tc_frag_data.slot_symbols[slot], | |
11635 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 11636 | } |
19e8f41a | 11637 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
11638 | } |
11639 | ||
11640 | ||
11641 | static int | |
7fa3d080 | 11642 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11643 | { |
11644 | int i; | |
11645 | int text_bytes = 0; | |
11646 | ||
11647 | for (i = 0; i < istack->ninsn; i++) | |
11648 | { | |
43cd72b9 BW |
11649 | TInsn *tinsn = &istack->insn[i]; |
11650 | if (tinsn->insn_type == ITYPE_INSN) | |
11651 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11652 | } |
11653 | return text_bytes; | |
11654 | } | |
11655 | ||
11656 | ||
11657 | static int | |
7fa3d080 | 11658 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11659 | { |
11660 | int i; | |
11661 | int lit_bytes = 0; | |
11662 | ||
11663 | for (i = 0; i < istack->ninsn; i++) | |
11664 | { | |
43cd72b9 BW |
11665 | TInsn *tinsn = &istack->insn[i]; |
11666 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11667 | lit_bytes += 4; |
11668 | } | |
11669 | return lit_bytes; | |
11670 | } | |
11671 | ||
43cd72b9 BW |
11672 | \f |
11673 | /* vliw_insn functions. */ | |
11674 | ||
7fa3d080 BW |
11675 | static void |
11676 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11677 | { |
11678 | int i; | |
11679 | xtensa_isa isa = xtensa_default_isa; | |
11680 | ||
11681 | xg_clear_vinsn (v); | |
11682 | ||
11683 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11684 | if (v->insnbuf == NULL) | |
11685 | as_fatal (_("out of memory")); | |
11686 | ||
62af60e2 | 11687 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 11688 | { |
43cd72b9 BW |
11689 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11690 | if (v->slotbuf[i] == NULL) | |
11691 | as_fatal (_("out of memory")); | |
11692 | } | |
11693 | } | |
11694 | ||
11695 | ||
7fa3d080 BW |
11696 | static void |
11697 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11698 | { |
11699 | int i; | |
65738a7d | 11700 | |
62af60e2 SA |
11701 | memset (v, 0, offsetof (vliw_insn, slots) |
11702 | + sizeof(TInsn) * config_max_slots); | |
65738a7d | 11703 | |
43cd72b9 BW |
11704 | v->format = XTENSA_UNDEFINED; |
11705 | v->num_slots = 0; | |
11706 | v->inside_bundle = FALSE; | |
11707 | ||
11708 | if (xt_saved_debug_type != DEBUG_NONE) | |
11709 | debug_type = xt_saved_debug_type; | |
11710 | ||
62af60e2 | 11711 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 11712 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11713 | } |
11714 | ||
11715 | ||
d8392fd9 SA |
11716 | static void |
11717 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
11718 | { | |
11719 | memcpy (dst, src, | |
11720 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); | |
11721 | dst->insnbuf = src->insnbuf; | |
11722 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
11723 | } | |
11724 | ||
11725 | ||
7fa3d080 BW |
11726 | static bfd_boolean |
11727 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11728 | { |
11729 | int i; | |
c138bc38 | 11730 | |
43cd72b9 BW |
11731 | for (i = 0; i < v->num_slots; i++) |
11732 | { | |
11733 | if (v->slots[i].is_specific_opcode) | |
11734 | return TRUE; | |
11735 | } | |
11736 | return FALSE; | |
11737 | } | |
11738 | ||
11739 | ||
7fa3d080 BW |
11740 | static void |
11741 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11742 | { |
11743 | int i; | |
11744 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 11745 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
11746 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
11747 | } | |
11748 | ||
11749 | ||
e7da6241 BW |
11750 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11751 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11752 | |
11753 | static bfd_boolean | |
7fa3d080 BW |
11754 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11755 | char *frag_offset, | |
11756 | fragS *fragP, | |
11757 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11758 | { |
11759 | xtensa_isa isa = xtensa_default_isa; | |
11760 | xtensa_format fmt = vinsn->format; | |
11761 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11762 | int slot; | |
11763 | bfd_boolean has_fixup = FALSE; | |
11764 | ||
11765 | xtensa_format_encode (isa, fmt, insnbuf); | |
11766 | ||
11767 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11768 | { | |
11769 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 11770 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
11771 | bfd_boolean tinsn_has_fixup = |
11772 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11773 | vinsn->slotbuf[slot]); | |
11774 | ||
11775 | xtensa_format_set_slot (isa, fmt, slot, | |
11776 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 11777 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
11778 | { |
11779 | if (vinsn->num_slots != 1) | |
11780 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
11781 | else if (record_fixup) | |
11782 | /* Instructions that generate TLS relocations should always be | |
11783 | relaxed in the front-end. If "record_fixup" is set, then this | |
11784 | function is being called during back-end relaxation, so flag | |
11785 | the unexpected behavior as an error. */ | |
11786 | as_bad (_("unexpected TLS relocation")); | |
11787 | else | |
11788 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
11789 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
11790 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
11791 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 11792 | } |
e7da6241 | 11793 | if (tinsn_has_fixup) |
43cd72b9 BW |
11794 | { |
11795 | int i; | |
11796 | xtensa_opcode opcode = tinsn->opcode; | |
11797 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11798 | has_fixup = TRUE; | |
11799 | ||
11800 | for (i = 0; i < noperands; i++) | |
11801 | { | |
11802 | expressionS* expr = &tinsn->tok[i]; | |
11803 | switch (expr->X_op) | |
11804 | { | |
11805 | case O_symbol: | |
11806 | case O_lo16: | |
11807 | case O_hi16: | |
11808 | if (get_relaxable_immed (opcode) == i) | |
11809 | { | |
e7da6241 BW |
11810 | /* Add a fix record for the instruction, except if this |
11811 | function is being called prior to relaxation, i.e., | |
11812 | if record_fixup is false, and the instruction might | |
11813 | be relaxed later. */ | |
11814 | if (record_fixup | |
11815 | || tinsn->is_specific_opcode | |
11816 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11817 | { |
e7da6241 BW |
11818 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11819 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11820 | } |
11821 | else | |
11822 | { | |
e7da6241 BW |
11823 | if (expr->X_op != O_symbol) |
11824 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11825 | tinsn->symbol = expr->X_add_symbol; |
11826 | tinsn->offset = expr->X_add_number; | |
11827 | } | |
11828 | } | |
11829 | else | |
e7da6241 | 11830 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11831 | break; |
11832 | ||
11833 | case O_constant: | |
11834 | case O_register: | |
11835 | break; | |
11836 | ||
43cd72b9 | 11837 | default: |
e7da6241 | 11838 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11839 | break; |
11840 | } | |
11841 | } | |
11842 | } | |
11843 | } | |
11844 | ||
11845 | return has_fixup; | |
11846 | } | |
11847 | ||
11848 | ||
11849 | static void | |
7fa3d080 | 11850 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11851 | { |
11852 | static xtensa_insnbuf insnbuf = NULL; | |
11853 | static xtensa_insnbuf slotbuf = NULL; | |
11854 | int i; | |
11855 | xtensa_format fmt; | |
11856 | xtensa_isa isa = xtensa_default_isa; | |
11857 | ||
11858 | if (!insnbuf) | |
11859 | { | |
11860 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11861 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11862 | } | |
11863 | ||
d77b99c9 | 11864 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11865 | fmt = xtensa_format_decode (isa, insnbuf); |
11866 | if (fmt == XTENSA_UNDEFINED) | |
11867 | as_fatal (_("cannot decode instruction format")); | |
11868 | vinsn->format = fmt; | |
11869 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11870 | ||
11871 | for (i = 0; i < vinsn->num_slots; i++) | |
11872 | { | |
11873 | TInsn *tinsn = &vinsn->slots[i]; | |
11874 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11875 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11876 | } | |
11877 | } | |
11878 | ||
e0001a05 NC |
11879 | \f |
11880 | /* Expression utilities. */ | |
11881 | ||
43cd72b9 | 11882 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11883 | |
11884 | bfd_boolean | |
7fa3d080 | 11885 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11886 | { |
11887 | return (s->X_op == O_constant); | |
11888 | } | |
11889 | ||
11890 | ||
11891 | /* Get the expression constant. | |
43cd72b9 | 11892 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11893 | |
11894 | offsetT | |
7fa3d080 | 11895 | get_expr_const (const expressionS *s) |
e0001a05 | 11896 | { |
9c2799c2 | 11897 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
11898 | return s->X_add_number; |
11899 | } | |
11900 | ||
11901 | ||
11902 | /* Set the expression to a constant value. */ | |
11903 | ||
11904 | void | |
7fa3d080 | 11905 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11906 | { |
11907 | s->X_op = O_constant; | |
11908 | s->X_add_number = val; | |
11909 | s->X_add_symbol = NULL; | |
11910 | s->X_op_symbol = NULL; | |
11911 | } | |
11912 | ||
11913 | ||
43cd72b9 | 11914 | bfd_boolean |
7fa3d080 | 11915 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11916 | { |
11917 | return (s->X_op == O_register); | |
11918 | } | |
11919 | ||
11920 | ||
11921 | /* Get the expression constant. | |
11922 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11923 | ||
11924 | offsetT | |
7fa3d080 | 11925 | get_expr_register (const expressionS *s) |
43cd72b9 | 11926 | { |
9c2799c2 | 11927 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
11928 | return s->X_add_number; |
11929 | } | |
11930 | ||
11931 | ||
e0001a05 NC |
11932 | /* Set the expression to a symbol + constant offset. */ |
11933 | ||
11934 | void | |
7fa3d080 | 11935 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11936 | { |
11937 | s->X_op = O_symbol; | |
11938 | s->X_add_symbol = sym; | |
11939 | s->X_op_symbol = NULL; /* unused */ | |
11940 | s->X_add_number = offset; | |
11941 | } | |
11942 | ||
11943 | ||
43cd72b9 BW |
11944 | /* Return TRUE if the two expressions are equal. */ |
11945 | ||
e0001a05 | 11946 | bfd_boolean |
7fa3d080 | 11947 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11948 | { |
11949 | if (s1->X_op != s2->X_op) | |
11950 | return FALSE; | |
11951 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11952 | return FALSE; | |
11953 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11954 | return FALSE; | |
11955 | if (s1->X_add_number != s2->X_add_number) | |
11956 | return FALSE; | |
11957 | return TRUE; | |
11958 | } | |
11959 | ||
11960 | ||
11961 | static void | |
7fa3d080 | 11962 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11963 | { |
11964 | memcpy (dst, src, sizeof (expressionS)); | |
11965 | } | |
11966 | ||
11967 | \f | |
9456465c | 11968 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11969 | |
11970 | struct rename_section_struct | |
11971 | { | |
11972 | char *old_name; | |
11973 | char *new_name; | |
11974 | struct rename_section_struct *next; | |
11975 | }; | |
11976 | ||
11977 | static struct rename_section_struct *section_rename; | |
11978 | ||
11979 | ||
9456465c BW |
11980 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11981 | entries to the section_rename list. Note: Specifying multiple | |
11982 | renamings separated by colons is not documented and is retained only | |
11983 | for backward compatibility. */ | |
e0001a05 | 11984 | |
7fa3d080 BW |
11985 | static void |
11986 | build_section_rename (const char *arg) | |
e0001a05 | 11987 | { |
9456465c | 11988 | struct rename_section_struct *r; |
e0001a05 NC |
11989 | char *this_arg = NULL; |
11990 | char *next_arg = NULL; | |
11991 | ||
9456465c | 11992 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11993 | { |
9456465c BW |
11994 | char *old_name, *new_name; |
11995 | ||
e0001a05 NC |
11996 | if (this_arg) |
11997 | { | |
11998 | next_arg = strchr (this_arg, ':'); | |
11999 | if (next_arg) | |
12000 | { | |
12001 | *next_arg = '\0'; | |
12002 | next_arg++; | |
12003 | } | |
12004 | } | |
e0001a05 | 12005 | |
9456465c BW |
12006 | old_name = this_arg; |
12007 | new_name = strchr (this_arg, '='); | |
e0001a05 | 12008 | |
9456465c BW |
12009 | if (*old_name == '\0') |
12010 | { | |
12011 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
12012 | continue; | |
12013 | } | |
12014 | if (!new_name || new_name[1] == '\0') | |
12015 | { | |
12016 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
12017 | old_name); | |
12018 | continue; | |
12019 | } | |
12020 | *new_name = '\0'; | |
12021 | new_name++; | |
e0001a05 | 12022 | |
9456465c BW |
12023 | /* Check for invalid section renaming. */ |
12024 | for (r = section_rename; r != NULL; r = r->next) | |
12025 | { | |
12026 | if (strcmp (r->old_name, old_name) == 0) | |
12027 | as_bad (_("section %s renamed multiple times"), old_name); | |
12028 | if (strcmp (r->new_name, new_name) == 0) | |
12029 | as_bad (_("multiple sections remapped to output section %s"), | |
12030 | new_name); | |
12031 | } | |
e0001a05 | 12032 | |
9456465c BW |
12033 | /* Now add it. */ |
12034 | r = (struct rename_section_struct *) | |
12035 | xmalloc (sizeof (struct rename_section_struct)); | |
12036 | r->old_name = xstrdup (old_name); | |
12037 | r->new_name = xstrdup (new_name); | |
12038 | r->next = section_rename; | |
12039 | section_rename = r; | |
e0001a05 | 12040 | } |
e0001a05 NC |
12041 | } |
12042 | ||
12043 | ||
9456465c BW |
12044 | char * |
12045 | xtensa_section_rename (char *name) | |
e0001a05 NC |
12046 | { |
12047 | struct rename_section_struct *r = section_rename; | |
12048 | ||
12049 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
12050 | { |
12051 | if (strcmp (r->old_name, name) == 0) | |
12052 | return r->new_name; | |
12053 | } | |
e0001a05 NC |
12054 | |
12055 | return name; | |
12056 | } |