Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
fb227da0 | 2 | Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
77cba8a3 | 82 | unsigned xtensa_num_pipe_stages; |
d77b99c9 | 83 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
84 | |
85 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
86 | ||
87 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 88 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
89 | back end. */ |
90 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
91 | |
92 | /* Flags for properties of the last instruction in a segment. */ | |
93 | #define FLAG_IS_A0_WRITER 0x1 | |
94 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
95 | ||
96 | ||
97 | /* We define a special segment names ".literal" to place literals | |
98 | into. The .fini and .init sections are special because they | |
99 | contain code that is moved together by the linker. We give them | |
100 | their own special .fini.literal and .init.literal sections. */ | |
101 | ||
102 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 103 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 104 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 105 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
106 | |
107 | ||
43cd72b9 | 108 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
109 | state of the literal collection pools. If lit_prefix is set, it is |
110 | used to determine the literal section names; otherwise, the literal | |
111 | sections are determined based on the current text section. The | |
112 | lit_seg and lit4_seg fields cache these literal sections, with the | |
113 | current_text_seg field used a tag to indicate whether the cached | |
114 | values are valid. */ | |
e0001a05 NC |
115 | |
116 | typedef struct lit_state_struct | |
117 | { | |
74869ac7 BW |
118 | char *lit_prefix; |
119 | segT current_text_seg; | |
e0001a05 | 120 | segT lit_seg; |
43cd72b9 | 121 | segT lit4_seg; |
e0001a05 NC |
122 | } lit_state; |
123 | ||
124 | static lit_state default_lit_sections; | |
125 | ||
126 | ||
74869ac7 BW |
127 | /* We keep a list of literal segments. The seg_list type is the node |
128 | for this list. The literal_head pointer is the head of the list, | |
129 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
130 | |
131 | typedef struct seg_list_struct | |
132 | { | |
133 | struct seg_list_struct *next; | |
134 | segT seg; | |
135 | } seg_list; | |
136 | ||
137 | static seg_list literal_head_h; | |
138 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
139 | |
140 | ||
82e7541d BW |
141 | /* Lists of symbols. We keep a list of symbols that label the current |
142 | instruction, so that we can adjust the symbols when inserting alignment | |
143 | for various instructions. We also keep a list of all the symbols on | |
144 | literals, so that we can fix up those symbols when the literals are | |
145 | later moved into the text sections. */ | |
146 | ||
147 | typedef struct sym_list_struct | |
148 | { | |
149 | struct sym_list_struct *next; | |
150 | symbolS *sym; | |
151 | } sym_list; | |
152 | ||
153 | static sym_list *insn_labels = NULL; | |
154 | static sym_list *free_insn_labels = NULL; | |
155 | static sym_list *saved_insn_labels = NULL; | |
156 | ||
157 | static sym_list *literal_syms; | |
158 | ||
159 | ||
43cd72b9 BW |
160 | /* Flags to determine whether to prefer const16 or l32r |
161 | if both options are available. */ | |
162 | int prefer_const16 = 0; | |
163 | int prefer_l32r = 0; | |
164 | ||
e0001a05 NC |
165 | /* Global flag to indicate when we are emitting literals. */ |
166 | int generating_literals = 0; | |
167 | ||
43cd72b9 BW |
168 | /* The following PROPERTY table definitions are copied from |
169 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
170 | ||
171 | /* Flags in the property tables to specify whether blocks of memory | |
172 | are literals, instructions, data, or unreachable. For | |
173 | instructions, blocks that begin loop targets and branch targets are | |
174 | designated. Blocks that do not allow density, instruction | |
175 | reordering or transformation are also specified. Finally, for | |
176 | branch targets, branch target alignment priority is included. | |
177 | Alignment of the next block is specified in the current block | |
178 | and the size of the current block does not include any fill required | |
179 | to align to the next block. */ | |
180 | ||
181 | #define XTENSA_PROP_LITERAL 0x00000001 | |
182 | #define XTENSA_PROP_INSN 0x00000002 | |
183 | #define XTENSA_PROP_DATA 0x00000004 | |
184 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
185 | /* Instruction only properties at beginning of code. */ | |
186 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
187 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
188 | /* Instruction only properties about code. */ | |
189 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
190 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
191 | /* Historically, NO_TRANSFORM was a property of instructions, |
192 | but it should apply to literals under certain circumstances. */ | |
193 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
194 | |
195 | /* Branch target alignment information. This transmits information | |
196 | to the linker optimization about the priority of aligning a | |
197 | particular block for branch target alignment: None, low priority, | |
198 | high priority, or required. These only need to be checked in | |
199 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
200 | Common usage is | |
201 | ||
202 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
203 | case XTENSA_PROP_BT_ALIGN_NONE: | |
204 | case XTENSA_PROP_BT_ALIGN_LOW: | |
205 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
206 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
207 | */ | |
208 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
209 | ||
210 | /* No branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
212 | /* Low priority branch target alignment. */ | |
213 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
214 | /* High priority branch target alignment. */ | |
215 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
216 | /* Required branch target alignment. */ | |
217 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
218 | ||
219 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
220 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
221 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
222 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
223 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
224 | ||
225 | ||
226 | /* Alignment is specified in the block BEFORE the one that needs | |
227 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
228 | get the required alignment specified as a power of 2. Use | |
229 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
230 | alignment. Be careful of side effects since the SET will evaluate | |
231 | flags twice. Also, note that the SIZE of a block in the property | |
232 | table does not include the alignment size, so the alignment fill | |
233 | must be calculated to determine if two blocks are contiguous. | |
234 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
235 | possible future implementation. */ | |
236 | ||
237 | #define XTENSA_PROP_ALIGN 0x00000800 | |
238 | ||
239 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
240 | ||
241 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
242 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
243 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
244 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
245 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
246 | ||
247 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
248 | ||
249 | ||
250 | /* Structure for saving instruction and alignment per-fragment data | |
251 | that will be written to the object file. This structure is | |
252 | equivalent to the actual data that will be written out to the file | |
253 | but is easier to use. We provide a conversion to file flags | |
254 | in frag_flags_to_number. */ | |
255 | ||
256 | typedef struct frag_flags_struct frag_flags; | |
257 | ||
258 | struct frag_flags_struct | |
259 | { | |
260 | /* is_literal should only be used after xtensa_move_literals. | |
261 | If you need to check if you are generating a literal fragment, | |
262 | then use the generating_literals global. */ | |
263 | ||
264 | unsigned is_literal : 1; | |
265 | unsigned is_insn : 1; | |
266 | unsigned is_data : 1; | |
267 | unsigned is_unreachable : 1; | |
268 | ||
99ded152 BW |
269 | /* is_specific_opcode implies no_transform. */ |
270 | unsigned is_no_transform : 1; | |
271 | ||
43cd72b9 BW |
272 | struct |
273 | { | |
274 | unsigned is_loop_target : 1; | |
275 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
276 | unsigned bt_align_priority : 2; | |
277 | ||
278 | unsigned is_no_density : 1; | |
279 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
280 | |
281 | unsigned is_no_reorder : 1; | |
282 | ||
283 | /* Uses absolute literal addressing for l32r. */ | |
284 | unsigned is_abslit : 1; | |
285 | } insn; | |
286 | unsigned is_align : 1; | |
287 | unsigned alignment : 5; | |
288 | }; | |
289 | ||
290 | ||
291 | /* Structure for saving information about a block of property data | |
292 | for frags that have the same flags. */ | |
293 | struct xtensa_block_info_struct | |
294 | { | |
295 | segT sec; | |
296 | bfd_vma offset; | |
297 | size_t size; | |
298 | frag_flags flags; | |
299 | struct xtensa_block_info_struct *next; | |
300 | }; | |
301 | ||
e0001a05 NC |
302 | |
303 | /* Structure for saving the current state before emitting literals. */ | |
304 | typedef struct emit_state_struct | |
305 | { | |
306 | const char *name; | |
307 | segT now_seg; | |
308 | subsegT now_subseg; | |
309 | int generating_literals; | |
310 | } emit_state; | |
311 | ||
312 | ||
43cd72b9 BW |
313 | /* Opcode placement information */ |
314 | ||
315 | typedef unsigned long long bitfield; | |
316 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
317 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
318 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
319 | ||
320 | #define MAX_FORMATS 32 | |
321 | ||
322 | typedef struct op_placement_info_struct | |
323 | { | |
324 | int num_formats; | |
325 | /* A number describing how restrictive the issue is for this | |
326 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 327 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 328 | only one format but many slots in that format. The most |
c138bc38 | 329 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
330 | format. */ |
331 | int issuef; | |
43cd72b9 | 332 | xtensa_format narrowest; |
43cd72b9 | 333 | char narrowest_size; |
b2d179be | 334 | char narrowest_slot; |
43cd72b9 BW |
335 | |
336 | /* formats is a bitfield with the Nth bit set | |
337 | if the opcode fits in the Nth xtensa_format. */ | |
338 | bitfield formats; | |
339 | ||
340 | /* slots[N]'s Mth bit is set if the op fits in the | |
341 | Mth slot of the Nth xtensa_format. */ | |
342 | bitfield slots[MAX_FORMATS]; | |
343 | ||
344 | /* A count of the number of slots in a given format | |
345 | an op can fit (i.e., the bitcount of the slot field above). */ | |
346 | char slots_in_format[MAX_FORMATS]; | |
347 | ||
348 | } op_placement_info, *op_placement_info_table; | |
349 | ||
350 | op_placement_info_table op_placement_table; | |
351 | ||
352 | ||
353 | /* Extra expression types. */ | |
354 | ||
355 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
356 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
357 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 358 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
43cd72b9 | 359 | |
bbdd25a8 BW |
360 | struct suffix_reloc_map |
361 | { | |
362 | char *suffix; | |
363 | int length; | |
364 | bfd_reloc_code_real_type reloc; | |
365 | unsigned char operator; | |
366 | }; | |
367 | ||
368 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
369 | ||
370 | static struct suffix_reloc_map suffix_relocs[] = | |
371 | { | |
372 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
373 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
374 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 375 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
bbdd25a8 BW |
376 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } |
377 | }; | |
378 | ||
43cd72b9 | 379 | |
e0001a05 NC |
380 | /* Directives. */ |
381 | ||
382 | typedef enum | |
383 | { | |
384 | directive_none = 0, | |
385 | directive_literal, | |
386 | directive_density, | |
43cd72b9 | 387 | directive_transform, |
e0001a05 NC |
388 | directive_freeregs, |
389 | directive_longcalls, | |
43cd72b9 BW |
390 | directive_literal_prefix, |
391 | directive_schedule, | |
392 | directive_absolute_literals, | |
393 | directive_last_directive | |
e0001a05 NC |
394 | } directiveE; |
395 | ||
396 | typedef struct | |
397 | { | |
398 | const char *name; | |
399 | bfd_boolean can_be_negated; | |
400 | } directive_infoS; | |
401 | ||
402 | const directive_infoS directive_info[] = | |
403 | { | |
43cd72b9 BW |
404 | { "none", FALSE }, |
405 | { "literal", FALSE }, | |
406 | { "density", TRUE }, | |
407 | { "transform", TRUE }, | |
408 | { "freeregs", FALSE }, | |
409 | { "longcalls", TRUE }, | |
410 | { "literal_prefix", FALSE }, | |
411 | { "schedule", TRUE }, | |
412 | { "absolute-literals", TRUE } | |
e0001a05 NC |
413 | }; |
414 | ||
415 | bfd_boolean directive_state[] = | |
416 | { | |
417 | FALSE, /* none */ | |
418 | FALSE, /* literal */ | |
43cd72b9 | 419 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
420 | FALSE, /* density */ |
421 | #else | |
422 | TRUE, /* density */ | |
423 | #endif | |
43cd72b9 | 424 | TRUE, /* transform */ |
e0001a05 NC |
425 | FALSE, /* freeregs */ |
426 | FALSE, /* longcalls */ | |
43cd72b9 | 427 | FALSE, /* literal_prefix */ |
2caa7ca0 | 428 | FALSE, /* schedule */ |
43cd72b9 BW |
429 | #if XSHAL_USE_ABSOLUTE_LITERALS |
430 | TRUE /* absolute_literals */ | |
431 | #else | |
432 | FALSE /* absolute_literals */ | |
433 | #endif | |
e0001a05 NC |
434 | }; |
435 | ||
e0001a05 NC |
436 | |
437 | /* Directive functions. */ | |
438 | ||
7fa3d080 BW |
439 | static void xtensa_begin_directive (int); |
440 | static void xtensa_end_directive (int); | |
74869ac7 | 441 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
442 | static void xtensa_literal_position (int); |
443 | static void xtensa_literal_pseudo (int); | |
444 | static void xtensa_frequency_pseudo (int); | |
445 | static void xtensa_elf_cons (int); | |
fb227da0 | 446 | static void xtensa_leb128 (int); |
e0001a05 | 447 | |
7fa3d080 | 448 | /* Parsing and Idiom Translation. */ |
e0001a05 | 449 | |
7fa3d080 | 450 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 451 | |
e0001a05 NC |
452 | /* Various Other Internal Functions. */ |
453 | ||
84b08ed9 BW |
454 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
455 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
456 | static void xtensa_mark_literal_pool_location (void); |
457 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
458 | static fragS *get_literal_pool_location (segT); | |
459 | static void set_literal_pool_location (segT, fragS *); | |
460 | static void xtensa_set_frag_assembly_state (fragS *); | |
461 | static void finish_vinsn (vliw_insn *); | |
462 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 463 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
464 | |
465 | /* Alignment Functions. */ | |
466 | ||
d77b99c9 BW |
467 | static int get_text_align_power (unsigned); |
468 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 469 | static int branch_align_power (segT); |
e0001a05 NC |
470 | |
471 | /* Helpers for xtensa_relax_frag(). */ | |
472 | ||
7fa3d080 | 473 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 474 | |
b08b5071 | 475 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 476 | |
7fa3d080 BW |
477 | static unsigned get_last_insn_flags (segT, subsegT); |
478 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
479 | static float get_subseg_total_freq (segT, subsegT); |
480 | static float get_subseg_target_freq (segT, subsegT); | |
481 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
482 | |
483 | /* Segment list functions. */ | |
484 | ||
7fa3d080 BW |
485 | static void xtensa_move_literals (void); |
486 | static void xtensa_reorder_segments (void); | |
487 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
488 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
489 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
490 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 491 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 492 | |
e0001a05 | 493 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 494 | |
74869ac7 | 495 | extern asection *xtensa_get_property_section (asection *, const char *); |
e0001a05 | 496 | |
43cd72b9 BW |
497 | /* op_placement_info functions. */ |
498 | ||
7fa3d080 BW |
499 | static void init_op_placement_info_table (void); |
500 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
501 | static int xg_get_single_size (xtensa_opcode); | |
502 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 503 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 504 | |
e0001a05 | 505 | /* TInsn and IStack functions. */ |
43cd72b9 | 506 | |
7fa3d080 BW |
507 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
508 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
509 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
510 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
511 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
512 | static void tinsn_from_chars (TInsn *, char *, int); | |
513 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
514 | static int get_num_stack_text_bytes (IStack *); | |
515 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 516 | |
43cd72b9 BW |
517 | /* vliw_insn functions. */ |
518 | ||
7fa3d080 BW |
519 | static void xg_init_vinsn (vliw_insn *); |
520 | static void xg_clear_vinsn (vliw_insn *); | |
521 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
522 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 523 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
524 | (vliw_insn *, char *, fragS *, bfd_boolean); |
525 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 526 | |
e0001a05 | 527 | /* Expression Utilities. */ |
43cd72b9 | 528 | |
7fa3d080 BW |
529 | bfd_boolean expr_is_const (const expressionS *); |
530 | offsetT get_expr_const (const expressionS *); | |
531 | void set_expr_const (expressionS *, offsetT); | |
532 | bfd_boolean expr_is_register (const expressionS *); | |
533 | offsetT get_expr_register (const expressionS *); | |
534 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
535 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
536 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 537 | |
9456465c BW |
538 | /* Section renaming. */ |
539 | ||
7fa3d080 | 540 | static void build_section_rename (const char *); |
e0001a05 | 541 | |
e0001a05 NC |
542 | |
543 | /* ISA imported from bfd. */ | |
544 | extern xtensa_isa xtensa_default_isa; | |
545 | ||
546 | extern int target_big_endian; | |
547 | ||
548 | static xtensa_opcode xtensa_addi_opcode; | |
549 | static xtensa_opcode xtensa_addmi_opcode; | |
550 | static xtensa_opcode xtensa_call0_opcode; | |
551 | static xtensa_opcode xtensa_call4_opcode; | |
552 | static xtensa_opcode xtensa_call8_opcode; | |
553 | static xtensa_opcode xtensa_call12_opcode; | |
554 | static xtensa_opcode xtensa_callx0_opcode; | |
555 | static xtensa_opcode xtensa_callx4_opcode; | |
556 | static xtensa_opcode xtensa_callx8_opcode; | |
557 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 558 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 559 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 560 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
561 | static xtensa_opcode xtensa_movi_opcode; |
562 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 563 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 564 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 565 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
566 | static xtensa_opcode xtensa_loop_opcode; |
567 | static xtensa_opcode xtensa_loopnez_opcode; | |
568 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 569 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
570 | static xtensa_opcode xtensa_nop_n_opcode; |
571 | static xtensa_opcode xtensa_or_opcode; | |
572 | static xtensa_opcode xtensa_ret_opcode; | |
573 | static xtensa_opcode xtensa_ret_n_opcode; | |
574 | static xtensa_opcode xtensa_retw_opcode; | |
575 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 576 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
577 | static xtensa_opcode xtensa_waiti_opcode; |
578 | ||
579 | \f | |
580 | /* Command-line Options. */ | |
581 | ||
582 | bfd_boolean use_literal_section = TRUE; | |
583 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 584 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 585 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
586 | static bfd_boolean workaround_a0_b_retw = FALSE; |
587 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
588 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 589 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 590 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 591 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 592 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 593 | |
43cd72b9 BW |
594 | /* When workaround_short_loops is TRUE, all loops with early exits must |
595 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
596 | to the workaround_short_loop flag. In addition to the | |
597 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
598 | must have at least 3 instructions. */ | |
e0001a05 | 599 | |
43cd72b9 | 600 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 601 | |
7fa3d080 BW |
602 | |
603 | static void | |
604 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
605 | { | |
606 | if (earliest > latest) | |
607 | as_fatal (_("illegal range of target hardware versions")); | |
608 | ||
609 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
610 | if (earliest < 105000 || latest < 105000) | |
611 | { | |
612 | workaround_a0_b_retw |= TRUE; | |
613 | workaround_b_j_loop_end |= TRUE; | |
614 | workaround_short_loop |= TRUE; | |
615 | workaround_close_loop_end |= TRUE; | |
616 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 617 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
618 | } |
619 | } | |
620 | ||
621 | ||
e0001a05 NC |
622 | enum |
623 | { | |
624 | option_density = OPTION_MD_BASE, | |
625 | option_no_density, | |
626 | ||
627 | option_relax, | |
628 | option_no_relax, | |
629 | ||
43cd72b9 BW |
630 | option_link_relax, |
631 | option_no_link_relax, | |
632 | ||
e0001a05 NC |
633 | option_generics, |
634 | option_no_generics, | |
635 | ||
43cd72b9 BW |
636 | option_transform, |
637 | option_no_transform, | |
638 | ||
e0001a05 NC |
639 | option_text_section_literals, |
640 | option_no_text_section_literals, | |
641 | ||
43cd72b9 BW |
642 | option_absolute_literals, |
643 | option_no_absolute_literals, | |
644 | ||
e0001a05 NC |
645 | option_align_targets, |
646 | option_no_align_targets, | |
647 | ||
43cd72b9 | 648 | option_warn_unaligned_targets, |
e0001a05 NC |
649 | |
650 | option_longcalls, | |
651 | option_no_longcalls, | |
652 | ||
653 | option_workaround_a0_b_retw, | |
654 | option_no_workaround_a0_b_retw, | |
655 | ||
656 | option_workaround_b_j_loop_end, | |
657 | option_no_workaround_b_j_loop_end, | |
658 | ||
659 | option_workaround_short_loop, | |
660 | option_no_workaround_short_loop, | |
661 | ||
662 | option_workaround_all_short_loops, | |
663 | option_no_workaround_all_short_loops, | |
664 | ||
665 | option_workaround_close_loop_end, | |
666 | option_no_workaround_close_loop_end, | |
667 | ||
668 | option_no_workarounds, | |
669 | ||
e0001a05 | 670 | option_rename_section_name, |
e0001a05 | 671 | |
43cd72b9 BW |
672 | option_prefer_l32r, |
673 | option_prefer_const16, | |
674 | ||
675 | option_target_hardware | |
e0001a05 NC |
676 | }; |
677 | ||
678 | const char *md_shortopts = ""; | |
679 | ||
680 | struct option md_longopts[] = | |
681 | { | |
43cd72b9 BW |
682 | { "density", no_argument, NULL, option_density }, |
683 | { "no-density", no_argument, NULL, option_no_density }, | |
684 | ||
685 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
686 | to the "transform" option. */ | |
687 | { "relax", no_argument, NULL, option_relax }, | |
688 | { "no-relax", no_argument, NULL, option_no_relax }, | |
689 | { "generics", no_argument, NULL, option_generics }, | |
690 | { "no-generics", no_argument, NULL, option_no_generics }, | |
691 | ||
692 | { "transform", no_argument, NULL, option_transform }, | |
693 | { "no-transform", no_argument, NULL, option_no_transform }, | |
694 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
695 | { "no-text-section-literals", no_argument, NULL, | |
696 | option_no_text_section_literals }, | |
697 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
698 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
699 | /* This option was changed from -align-target to -target-align |
700 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 701 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
702 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
703 | { "warn-unaligned-targets", no_argument, NULL, | |
704 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
705 | { "longcalls", no_argument, NULL, option_longcalls }, |
706 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
707 | ||
708 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
709 | option_no_workaround_a0_b_retw }, | |
710 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 711 | |
43cd72b9 BW |
712 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
713 | option_no_workaround_b_j_loop_end }, | |
714 | { "workaround-b-j-loop-end", no_argument, NULL, | |
715 | option_workaround_b_j_loop_end }, | |
e0001a05 | 716 | |
43cd72b9 BW |
717 | { "no-workaround-short-loops", no_argument, NULL, |
718 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
719 | { "workaround-short-loops", no_argument, NULL, |
720 | option_workaround_short_loop }, | |
e0001a05 | 721 | |
43cd72b9 BW |
722 | { "no-workaround-all-short-loops", no_argument, NULL, |
723 | option_no_workaround_all_short_loops }, | |
724 | { "workaround-all-short-loop", no_argument, NULL, | |
725 | option_workaround_all_short_loops }, | |
726 | ||
727 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
728 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
729 | ||
730 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
731 | ||
732 | { "no-workaround-close-loop-end", no_argument, NULL, | |
733 | option_no_workaround_close_loop_end }, | |
734 | { "workaround-close-loop-end", no_argument, NULL, | |
735 | option_workaround_close_loop_end }, | |
e0001a05 | 736 | |
7fa3d080 | 737 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 738 | |
43cd72b9 BW |
739 | { "link-relax", no_argument, NULL, option_link_relax }, |
740 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
741 | ||
742 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
743 | ||
744 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
745 | }; |
746 | ||
747 | size_t md_longopts_size = sizeof md_longopts; | |
748 | ||
749 | ||
750 | int | |
7fa3d080 | 751 | md_parse_option (int c, char *arg) |
e0001a05 NC |
752 | { |
753 | switch (c) | |
754 | { | |
755 | case option_density: | |
43cd72b9 | 756 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
757 | return 1; |
758 | case option_no_density: | |
43cd72b9 | 759 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 760 | return 1; |
43cd72b9 BW |
761 | case option_link_relax: |
762 | linkrelax = 1; | |
e0001a05 | 763 | return 1; |
43cd72b9 BW |
764 | case option_no_link_relax: |
765 | linkrelax = 0; | |
e0001a05 | 766 | return 1; |
43cd72b9 BW |
767 | case option_generics: |
768 | as_warn (_("--generics is deprecated; use --transform instead")); | |
769 | return md_parse_option (option_transform, arg); | |
770 | case option_no_generics: | |
771 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
772 | return md_parse_option (option_no_transform, arg); | |
773 | case option_relax: | |
774 | as_warn (_("--relax is deprecated; use --transform instead")); | |
775 | return md_parse_option (option_transform, arg); | |
776 | case option_no_relax: | |
777 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
778 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
779 | case option_longcalls: |
780 | directive_state[directive_longcalls] = TRUE; | |
781 | return 1; | |
782 | case option_no_longcalls: | |
783 | directive_state[directive_longcalls] = FALSE; | |
784 | return 1; | |
785 | case option_text_section_literals: | |
786 | use_literal_section = FALSE; | |
787 | return 1; | |
788 | case option_no_text_section_literals: | |
789 | use_literal_section = TRUE; | |
790 | return 1; | |
43cd72b9 BW |
791 | case option_absolute_literals: |
792 | if (!absolute_literals_supported) | |
793 | { | |
794 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
795 | return 0; | |
796 | } | |
797 | directive_state[directive_absolute_literals] = TRUE; | |
798 | return 1; | |
799 | case option_no_absolute_literals: | |
800 | directive_state[directive_absolute_literals] = FALSE; | |
801 | return 1; | |
802 | ||
e0001a05 NC |
803 | case option_workaround_a0_b_retw: |
804 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
805 | return 1; |
806 | case option_no_workaround_a0_b_retw: | |
807 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
808 | return 1; |
809 | case option_workaround_b_j_loop_end: | |
810 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
811 | return 1; |
812 | case option_no_workaround_b_j_loop_end: | |
813 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
814 | return 1; |
815 | ||
816 | case option_workaround_short_loop: | |
817 | workaround_short_loop = TRUE; | |
e0001a05 NC |
818 | return 1; |
819 | case option_no_workaround_short_loop: | |
820 | workaround_short_loop = FALSE; | |
e0001a05 NC |
821 | return 1; |
822 | ||
823 | case option_workaround_all_short_loops: | |
824 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
825 | return 1; |
826 | case option_no_workaround_all_short_loops: | |
827 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
828 | return 1; |
829 | ||
830 | case option_workaround_close_loop_end: | |
831 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
832 | return 1; |
833 | case option_no_workaround_close_loop_end: | |
834 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
835 | return 1; |
836 | ||
837 | case option_no_workarounds: | |
838 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 839 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 840 | workaround_short_loop = FALSE; |
e0001a05 | 841 | workaround_all_short_loops = FALSE; |
e0001a05 | 842 | workaround_close_loop_end = FALSE; |
e0001a05 | 843 | return 1; |
43cd72b9 | 844 | |
e0001a05 NC |
845 | case option_align_targets: |
846 | align_targets = TRUE; | |
847 | return 1; | |
848 | case option_no_align_targets: | |
849 | align_targets = FALSE; | |
850 | return 1; | |
851 | ||
43cd72b9 BW |
852 | case option_warn_unaligned_targets: |
853 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
854 | return 1; |
855 | ||
e0001a05 NC |
856 | case option_rename_section_name: |
857 | build_section_rename (arg); | |
858 | return 1; | |
e0001a05 NC |
859 | |
860 | case 'Q': | |
861 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
862 | should be emitted or not. FIXME: Not implemented. */ | |
863 | return 1; | |
c138bc38 | 864 | |
43cd72b9 BW |
865 | case option_prefer_l32r: |
866 | if (prefer_const16) | |
867 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
868 | prefer_l32r = 1; | |
869 | return 1; | |
870 | ||
871 | case option_prefer_const16: | |
872 | if (prefer_l32r) | |
873 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
874 | prefer_const16 = 1; | |
875 | return 1; | |
876 | ||
c138bc38 | 877 | case option_target_hardware: |
43cd72b9 BW |
878 | { |
879 | int earliest, latest = 0; | |
880 | if (*arg == 0 || *arg == '-') | |
881 | as_fatal (_("invalid target hardware version")); | |
882 | ||
883 | earliest = strtol (arg, &arg, 0); | |
884 | ||
885 | if (*arg == 0) | |
886 | latest = earliest; | |
887 | else if (*arg == '-') | |
888 | { | |
889 | if (*++arg == 0) | |
890 | as_fatal (_("invalid target hardware version")); | |
891 | latest = strtol (arg, &arg, 0); | |
892 | } | |
893 | if (*arg != 0) | |
894 | as_fatal (_("invalid target hardware version")); | |
895 | ||
896 | xtensa_setup_hw_workarounds (earliest, latest); | |
897 | return 1; | |
898 | } | |
899 | ||
900 | case option_transform: | |
901 | /* This option has no affect other than to use the defaults, | |
902 | which are already set. */ | |
903 | return 1; | |
904 | ||
905 | case option_no_transform: | |
906 | /* This option turns off all transformations of any kind. | |
907 | However, because we want to preserve the state of other | |
908 | directives, we only change its own field. Thus, before | |
909 | you perform any transformation, always check if transform | |
910 | is available. If you use the functions we provide for this | |
911 | purpose, you will be ok. */ | |
912 | directive_state[directive_transform] = FALSE; | |
913 | return 1; | |
914 | ||
e0001a05 NC |
915 | default: |
916 | return 0; | |
917 | } | |
918 | } | |
919 | ||
920 | ||
921 | void | |
7fa3d080 | 922 | md_show_usage (FILE *stream) |
e0001a05 | 923 | { |
43cd72b9 BW |
924 | fputs ("\n\ |
925 | Xtensa options:\n\ | |
9456465c BW |
926 | --[no-]text-section-literals\n\ |
927 | [Do not] put literals in the text section\n\ | |
928 | --[no-]absolute-literals\n\ | |
929 | [Do not] default to use non-PC-relative literals\n\ | |
930 | --[no-]target-align [Do not] try to align branch targets\n\ | |
931 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
932 | --[no-]transform [Do not] transform instructions\n\ | |
933 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
934 | } |
935 | ||
7fa3d080 BW |
936 | \f |
937 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
938 | |
939 | static void | |
7fa3d080 | 940 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 941 | { |
7fa3d080 | 942 | sym_list *l; |
43cd72b9 | 943 | |
7fa3d080 BW |
944 | if (!free_insn_labels) |
945 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
946 | else | |
43cd72b9 | 947 | { |
7fa3d080 BW |
948 | l = free_insn_labels; |
949 | free_insn_labels = l->next; | |
950 | } | |
951 | ||
952 | l->sym = sym; | |
953 | l->next = insn_labels; | |
954 | insn_labels = l; | |
955 | } | |
956 | ||
957 | ||
958 | static void | |
959 | xtensa_clear_insn_labels (void) | |
960 | { | |
961 | sym_list **pl; | |
962 | ||
963 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
964 | ; | |
965 | *pl = insn_labels; | |
966 | insn_labels = NULL; | |
967 | } | |
968 | ||
969 | ||
7fa3d080 | 970 | static void |
c3ea6048 | 971 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
972 | { |
973 | sym_list *lit; | |
974 | ||
975 | for (lit = insn_labels; lit; lit = lit->next) | |
976 | { | |
977 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
978 | S_SET_VALUE (lit_sym, new_offset); |
979 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
980 | } |
981 | } | |
982 | ||
e0001a05 NC |
983 | \f |
984 | /* Directive data and functions. */ | |
985 | ||
986 | typedef struct state_stackS_struct | |
987 | { | |
988 | directiveE directive; | |
989 | bfd_boolean negated; | |
990 | bfd_boolean old_state; | |
991 | const char *file; | |
992 | unsigned int line; | |
993 | const void *datum; | |
994 | struct state_stackS_struct *prev; | |
995 | } state_stackS; | |
996 | ||
997 | state_stackS *directive_state_stack; | |
998 | ||
999 | const pseudo_typeS md_pseudo_table[] = | |
1000 | { | |
43cd72b9 BW |
1001 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1002 | { "literal_position", xtensa_literal_position, 0 }, | |
1003 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1004 | { "long", xtensa_elf_cons, 4 }, | |
1005 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1006 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1007 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1008 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1009 | { "sleb128", xtensa_leb128, 1}, |
1010 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1011 | { "begin", xtensa_begin_directive, 0 }, |
1012 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1013 | { "literal", xtensa_literal_pseudo, 0 }, |
1014 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1015 | { NULL, 0, 0 }, | |
e0001a05 NC |
1016 | }; |
1017 | ||
1018 | ||
7fa3d080 BW |
1019 | static bfd_boolean |
1020 | use_transform (void) | |
e0001a05 | 1021 | { |
43cd72b9 BW |
1022 | /* After md_end, you should be checking frag by frag, rather |
1023 | than state directives. */ | |
1024 | assert (!past_xtensa_end); | |
1025 | return directive_state[directive_transform]; | |
e0001a05 NC |
1026 | } |
1027 | ||
1028 | ||
7fa3d080 BW |
1029 | static bfd_boolean |
1030 | do_align_targets (void) | |
e0001a05 | 1031 | { |
7b1cc377 BW |
1032 | /* Do not use this function after md_end; just look at align_targets |
1033 | instead. There is no target-align directive, so alignment is either | |
1034 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1035 | assert (!past_xtensa_end); |
1036 | return align_targets && use_transform (); | |
e0001a05 NC |
1037 | } |
1038 | ||
1039 | ||
1040 | static void | |
7fa3d080 | 1041 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1042 | { |
1043 | char *file; | |
1044 | unsigned int line; | |
1045 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1046 | ||
1047 | as_where (&file, &line); | |
1048 | ||
1049 | stack->directive = directive; | |
1050 | stack->negated = negated; | |
1051 | stack->old_state = directive_state[directive]; | |
1052 | stack->file = file; | |
1053 | stack->line = line; | |
1054 | stack->datum = datum; | |
1055 | stack->prev = directive_state_stack; | |
1056 | directive_state_stack = stack; | |
1057 | ||
1058 | directive_state[directive] = !negated; | |
1059 | } | |
1060 | ||
7fa3d080 | 1061 | |
e0001a05 | 1062 | static void |
7fa3d080 BW |
1063 | directive_pop (directiveE *directive, |
1064 | bfd_boolean *negated, | |
1065 | const char **file, | |
1066 | unsigned int *line, | |
1067 | const void **datum) | |
e0001a05 NC |
1068 | { |
1069 | state_stackS *top = directive_state_stack; | |
1070 | ||
1071 | if (!directive_state_stack) | |
1072 | { | |
1073 | as_bad (_("unmatched end directive")); | |
1074 | *directive = directive_none; | |
1075 | return; | |
1076 | } | |
1077 | ||
1078 | directive_state[directive_state_stack->directive] = top->old_state; | |
1079 | *directive = top->directive; | |
1080 | *negated = top->negated; | |
1081 | *file = top->file; | |
1082 | *line = top->line; | |
1083 | *datum = top->datum; | |
1084 | directive_state_stack = top->prev; | |
1085 | free (top); | |
1086 | } | |
1087 | ||
1088 | ||
1089 | static void | |
7fa3d080 | 1090 | directive_balance (void) |
e0001a05 NC |
1091 | { |
1092 | while (directive_state_stack) | |
1093 | { | |
1094 | directiveE directive; | |
1095 | bfd_boolean negated; | |
1096 | const char *file; | |
1097 | unsigned int line; | |
1098 | const void *datum; | |
1099 | ||
1100 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1101 | as_warn_where ((char *) file, line, | |
1102 | _(".begin directive with no matching .end directive")); | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | ||
1107 | static bfd_boolean | |
7fa3d080 | 1108 | inside_directive (directiveE dir) |
e0001a05 NC |
1109 | { |
1110 | state_stackS *top = directive_state_stack; | |
1111 | ||
1112 | while (top && top->directive != dir) | |
1113 | top = top->prev; | |
1114 | ||
1115 | return (top != NULL); | |
1116 | } | |
1117 | ||
1118 | ||
1119 | static void | |
7fa3d080 | 1120 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1121 | { |
1122 | int len; | |
1123 | unsigned i; | |
43cd72b9 | 1124 | char *directive_string; |
e0001a05 NC |
1125 | |
1126 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1127 | *negated = FALSE; | |
1128 | else | |
1129 | { | |
1130 | *negated = TRUE; | |
1131 | input_line_pointer += 3; | |
1132 | } | |
1133 | ||
1134 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1135 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1136 | ||
1137 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1138 | equivalent to .begin [no-]transform. We should remove it when | |
1139 | we stop accepting those options. */ | |
c138bc38 | 1140 | |
43cd72b9 BW |
1141 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1142 | { | |
1143 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1144 | directive_string = "transform"; | |
1145 | } | |
1146 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1147 | { | |
1148 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1149 | directive_string = "transform"; | |
c138bc38 | 1150 | } |
43cd72b9 BW |
1151 | else |
1152 | directive_string = input_line_pointer; | |
e0001a05 NC |
1153 | |
1154 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1155 | { | |
43cd72b9 | 1156 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1157 | { |
1158 | input_line_pointer += len; | |
1159 | *directive = (directiveE) i; | |
1160 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1161 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1162 | directive_info[i].name); |
1163 | return; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | as_bad (_("unknown directive")); | |
1168 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1169 | } | |
1170 | ||
1171 | ||
1172 | static void | |
7fa3d080 | 1173 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1174 | { |
1175 | directiveE directive; | |
1176 | bfd_boolean negated; | |
1177 | emit_state *state; | |
e0001a05 NC |
1178 | lit_state *ls; |
1179 | ||
1180 | get_directive (&directive, &negated); | |
1181 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1182 | { | |
1183 | discard_rest_of_line (); | |
1184 | return; | |
1185 | } | |
1186 | ||
43cd72b9 BW |
1187 | if (cur_vinsn.inside_bundle) |
1188 | as_bad (_("directives are not valid inside bundles")); | |
1189 | ||
e0001a05 NC |
1190 | switch (directive) |
1191 | { | |
1192 | case directive_literal: | |
82e7541d BW |
1193 | if (!inside_directive (directive_literal)) |
1194 | { | |
1195 | /* Previous labels go with whatever follows this directive, not with | |
1196 | the literal, so save them now. */ | |
1197 | saved_insn_labels = insn_labels; | |
1198 | insn_labels = NULL; | |
1199 | } | |
43cd72b9 | 1200 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1201 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1202 | xtensa_switch_to_literal_fragment (state); | |
1203 | directive_push (directive_literal, negated, state); | |
1204 | break; | |
1205 | ||
1206 | case directive_literal_prefix: | |
c138bc38 | 1207 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1208 | might produce a literal. */ |
1209 | md_flush_pending_output (); | |
e0001a05 NC |
1210 | /* Check to see if the current fragment is a literal |
1211 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1212 | if (generating_literals) |
e0001a05 NC |
1213 | { |
1214 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1215 | return; | |
1216 | } | |
1217 | ||
1218 | /* Allocate the literal state for this section and push | |
1219 | onto the directive stack. */ | |
1220 | ls = xmalloc (sizeof (lit_state)); | |
1221 | assert (ls); | |
1222 | ||
1223 | *ls = default_lit_sections; | |
e0001a05 NC |
1224 | directive_push (directive_literal_prefix, negated, ls); |
1225 | ||
e0001a05 | 1226 | /* Process the new prefix. */ |
74869ac7 | 1227 | xtensa_literal_prefix (); |
e0001a05 NC |
1228 | break; |
1229 | ||
1230 | case directive_freeregs: | |
1231 | /* This information is currently unused, but we'll accept the statement | |
1232 | and just discard the rest of the line. This won't check the syntax, | |
1233 | but it will accept every correct freeregs directive. */ | |
1234 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1235 | directive_push (directive_freeregs, negated, 0); | |
1236 | break; | |
1237 | ||
43cd72b9 BW |
1238 | case directive_schedule: |
1239 | md_flush_pending_output (); | |
1240 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1241 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1242 | directive_push (directive_schedule, negated, 0); | |
1243 | xtensa_set_frag_assembly_state (frag_now); | |
1244 | break; | |
1245 | ||
e0001a05 | 1246 | case directive_density: |
43cd72b9 BW |
1247 | as_warn (_(".begin [no-]density is ignored")); |
1248 | break; | |
1249 | ||
1250 | case directive_absolute_literals: | |
1251 | md_flush_pending_output (); | |
1252 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1253 | { |
43cd72b9 | 1254 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1255 | break; |
1256 | } | |
43cd72b9 BW |
1257 | xtensa_set_frag_assembly_state (frag_now); |
1258 | directive_push (directive, negated, 0); | |
1259 | break; | |
e0001a05 NC |
1260 | |
1261 | default: | |
43cd72b9 BW |
1262 | md_flush_pending_output (); |
1263 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1264 | directive_push (directive, negated, 0); |
1265 | break; | |
1266 | } | |
1267 | ||
1268 | demand_empty_rest_of_line (); | |
1269 | } | |
1270 | ||
1271 | ||
1272 | static void | |
7fa3d080 | 1273 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1274 | { |
1275 | directiveE begin_directive, end_directive; | |
1276 | bfd_boolean begin_negated, end_negated; | |
1277 | const char *file; | |
1278 | unsigned int line; | |
1279 | emit_state *state; | |
43cd72b9 | 1280 | emit_state **state_ptr; |
e0001a05 NC |
1281 | lit_state *s; |
1282 | ||
43cd72b9 BW |
1283 | if (cur_vinsn.inside_bundle) |
1284 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1285 | |
e0001a05 | 1286 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1287 | |
1288 | md_flush_pending_output (); | |
1289 | ||
1290 | switch (end_directive) | |
e0001a05 | 1291 | { |
43cd72b9 | 1292 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1293 | discard_rest_of_line (); |
1294 | return; | |
e0001a05 | 1295 | |
43cd72b9 BW |
1296 | case directive_density: |
1297 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1298 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1299 | break; |
1300 | ||
1301 | case directive_absolute_literals: | |
1302 | if (!absolute_literals_supported && !end_negated) | |
1303 | { | |
1304 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1305 | demand_empty_rest_of_line (); | |
1306 | return; | |
1307 | } | |
1308 | break; | |
1309 | ||
1310 | default: | |
1311 | break; | |
e0001a05 NC |
1312 | } |
1313 | ||
43cd72b9 | 1314 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1315 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1316 | (const void **) state_ptr); |
e0001a05 NC |
1317 | |
1318 | if (begin_directive != directive_none) | |
1319 | { | |
1320 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1321 | { | |
1322 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1323 | begin_negated ? "no-" : "", | |
1324 | directive_info[begin_directive].name, file, line); | |
1325 | } | |
1326 | else | |
1327 | { | |
1328 | switch (end_directive) | |
1329 | { | |
1330 | case directive_literal: | |
1331 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1332 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1333 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1334 | free (state); |
82e7541d BW |
1335 | if (!inside_directive (directive_literal)) |
1336 | { | |
1337 | /* Restore the list of current labels. */ | |
1338 | xtensa_clear_insn_labels (); | |
1339 | insn_labels = saved_insn_labels; | |
1340 | } | |
e0001a05 NC |
1341 | break; |
1342 | ||
e0001a05 NC |
1343 | case directive_literal_prefix: |
1344 | /* Restore the default collection sections from saved state. */ | |
1345 | s = (lit_state *) state; | |
1346 | assert (s); | |
e8247da7 | 1347 | default_lit_sections = *s; |
e0001a05 | 1348 | |
74869ac7 BW |
1349 | /* Free the state storage. */ |
1350 | free (s->lit_prefix); | |
e0001a05 NC |
1351 | free (s); |
1352 | break; | |
1353 | ||
43cd72b9 BW |
1354 | case directive_schedule: |
1355 | case directive_freeregs: | |
1356 | break; | |
1357 | ||
e0001a05 | 1358 | default: |
43cd72b9 | 1359 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1360 | break; |
1361 | } | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | demand_empty_rest_of_line (); | |
1366 | } | |
1367 | ||
1368 | ||
1369 | /* Place an aligned literal fragment at the current location. */ | |
1370 | ||
1371 | static void | |
7fa3d080 | 1372 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1373 | { |
43cd72b9 BW |
1374 | md_flush_pending_output (); |
1375 | ||
e0001a05 NC |
1376 | if (inside_directive (directive_literal)) |
1377 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1378 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1379 | |
1380 | demand_empty_rest_of_line (); | |
82e7541d | 1381 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1382 | } |
1383 | ||
1384 | ||
43cd72b9 | 1385 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1386 | |
1387 | static void | |
7fa3d080 | 1388 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1389 | { |
1390 | emit_state state; | |
1745fcba | 1391 | char *p, *base_name; |
e0001a05 | 1392 | char c; |
e0001a05 NC |
1393 | segT dest_seg; |
1394 | ||
82e7541d BW |
1395 | if (inside_directive (directive_literal)) |
1396 | { | |
1397 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1398 | ignore_rest_of_line (); | |
1399 | return; | |
1400 | } | |
1401 | ||
43cd72b9 BW |
1402 | md_flush_pending_output (); |
1403 | ||
82e7541d BW |
1404 | /* Previous labels go with whatever follows this directive, not with |
1405 | the literal, so save them now. */ | |
1406 | saved_insn_labels = insn_labels; | |
1407 | insn_labels = NULL; | |
1408 | ||
e0001a05 NC |
1409 | /* If we are using text-section literals, then this is the right value... */ |
1410 | dest_seg = now_seg; | |
1411 | ||
1412 | base_name = input_line_pointer; | |
1413 | ||
1414 | xtensa_switch_to_literal_fragment (&state); | |
1415 | ||
43cd72b9 | 1416 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1417 | need to put them in the section we just switched to. */ |
43cd72b9 | 1418 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1419 | dest_seg = now_seg; |
1420 | ||
43cd72b9 BW |
1421 | /* All literals are aligned to four-byte boundaries. */ |
1422 | frag_align (2, 0, 0); | |
1423 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1424 | |
1425 | c = get_symbol_end (); | |
1426 | /* Just after name is now '\0'. */ | |
1427 | p = input_line_pointer; | |
1428 | *p = c; | |
1429 | SKIP_WHITESPACE (); | |
1430 | ||
1431 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1432 | { | |
1433 | as_bad (_("expected comma or colon after symbol name; " | |
1434 | "rest of line ignored")); | |
1435 | ignore_rest_of_line (); | |
1436 | xtensa_restore_emit_state (&state); | |
1437 | return; | |
1438 | } | |
1439 | *p = 0; | |
1440 | ||
e0001a05 | 1441 | colon (base_name); |
e0001a05 | 1442 | |
e0001a05 | 1443 | *p = c; |
43cd72b9 | 1444 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1445 | |
43cd72b9 | 1446 | xtensa_elf_cons (4); |
e0001a05 NC |
1447 | |
1448 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1449 | |
1450 | /* Restore the list of current labels. */ | |
1451 | xtensa_clear_insn_labels (); | |
1452 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1453 | } |
1454 | ||
1455 | ||
1456 | static void | |
74869ac7 | 1457 | xtensa_literal_prefix (void) |
e0001a05 | 1458 | { |
74869ac7 BW |
1459 | char *name; |
1460 | int len; | |
1461 | ||
1462 | /* Parse the new prefix from the input_line_pointer. */ | |
1463 | SKIP_WHITESPACE (); | |
1464 | len = strspn (input_line_pointer, | |
1465 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1466 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1467 | |
1468 | /* Get a null-terminated copy of the name. */ | |
1469 | name = xmalloc (len + 1); | |
1470 | assert (name); | |
74869ac7 | 1471 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1472 | name[len] = 0; |
1473 | ||
74869ac7 BW |
1474 | /* Skip the name in the input line. */ |
1475 | input_line_pointer += len; | |
43cd72b9 | 1476 | |
74869ac7 | 1477 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1478 | |
74869ac7 | 1479 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1480 | default_lit_sections.lit_seg = NULL; |
1481 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1482 | } |
1483 | ||
1484 | ||
1485 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1486 | ||
1487 | static void | |
7fa3d080 | 1488 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1489 | { |
1490 | float fall_through_f, target_f; | |
43cd72b9 BW |
1491 | |
1492 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1493 | if (fall_through_f < 0) | |
1494 | { | |
1495 | as_bad (_("fall through frequency must be greater than 0")); | |
1496 | ignore_rest_of_line (); | |
1497 | return; | |
1498 | } | |
1499 | ||
1500 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1501 | if (target_f < 0) | |
1502 | { | |
1503 | as_bad (_("branch target frequency must be greater than 0")); | |
1504 | ignore_rest_of_line (); | |
1505 | return; | |
1506 | } | |
1507 | ||
b08b5071 | 1508 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1509 | |
1510 | demand_empty_rest_of_line (); | |
1511 | } | |
1512 | ||
1513 | ||
1514 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1515 | Clobbers input_line_pointer, checks end-of-line. */ | |
1516 | ||
1517 | static void | |
7fa3d080 | 1518 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1519 | { |
1520 | expressionS exp; | |
1521 | bfd_reloc_code_real_type reloc; | |
1522 | ||
1523 | md_flush_pending_output (); | |
1524 | ||
1525 | if (cur_vinsn.inside_bundle) | |
1526 | as_bad (_("directives are not valid inside bundles")); | |
1527 | ||
1528 | if (is_it_end_of_statement ()) | |
1529 | { | |
1530 | demand_empty_rest_of_line (); | |
1531 | return; | |
1532 | } | |
1533 | ||
1534 | do | |
1535 | { | |
1536 | expression (&exp); | |
1537 | if (exp.X_op == O_symbol | |
1538 | && *input_line_pointer == '@' | |
1539 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1540 | != BFD_RELOC_NONE)) | |
1541 | { | |
1542 | reloc_howto_type *reloc_howto = | |
1543 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1544 | ||
1545 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1546 | as_bad (_("unsupported relocation")); | |
1547 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1548 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1549 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1550 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1551 | as_bad (_("opcode-specific %s relocation used outside " | |
1552 | "an instruction"), reloc_howto->name); | |
1553 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1554 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1555 | reloc_howto->name, nbytes); | |
1556 | else | |
1557 | { | |
1558 | char *p = frag_more ((int) nbytes); | |
1559 | xtensa_set_frag_assembly_state (frag_now); | |
1560 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1561 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1562 | } |
1563 | } | |
1564 | else | |
1f7efbae BW |
1565 | { |
1566 | xtensa_set_frag_assembly_state (frag_now); | |
1567 | emit_expr (&exp, (unsigned int) nbytes); | |
1568 | } | |
43cd72b9 BW |
1569 | } |
1570 | while (*input_line_pointer++ == ','); | |
1571 | ||
1572 | input_line_pointer--; /* Put terminator back into stream. */ | |
1573 | demand_empty_rest_of_line (); | |
1574 | } | |
1575 | ||
fb227da0 BW |
1576 | static bfd_boolean is_leb128_expr; |
1577 | ||
1578 | static void | |
1579 | xtensa_leb128 (int sign) | |
1580 | { | |
1581 | is_leb128_expr = TRUE; | |
1582 | s_leb128 (sign); | |
1583 | is_leb128_expr = FALSE; | |
1584 | } | |
1585 | ||
7fa3d080 BW |
1586 | \f |
1587 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1588 | |
1589 | /* Parse @plt, etc. and return the desired relocation. */ | |
1590 | static bfd_reloc_code_real_type | |
7fa3d080 | 1591 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1592 | { |
43cd72b9 BW |
1593 | char ident[20]; |
1594 | char *str = *str_p; | |
1595 | char *str2; | |
1596 | int ch; | |
1597 | int len; | |
bbdd25a8 | 1598 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1599 | |
1600 | if (*str++ != '@') | |
1601 | return BFD_RELOC_NONE; | |
1602 | ||
1603 | for (ch = *str, str2 = ident; | |
1604 | (str2 < ident + sizeof (ident) - 1 | |
1605 | && (ISALNUM (ch) || ch == '@')); | |
1606 | ch = *++str) | |
1607 | { | |
1608 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1609 | } | |
1610 | ||
1611 | *str2 = '\0'; | |
1612 | len = str2 - ident; | |
1613 | ||
1614 | ch = ident[0]; | |
bbdd25a8 BW |
1615 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1616 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1617 | && len == ptr->length |
bbdd25a8 | 1618 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1619 | { |
1620 | /* Now check for "identifier@suffix+constant". */ | |
1621 | if (*str == '-' || *str == '+') | |
1622 | { | |
1623 | char *orig_line = input_line_pointer; | |
1624 | expressionS new_exp; | |
1625 | ||
1626 | input_line_pointer = str; | |
1627 | expression (&new_exp); | |
1628 | if (new_exp.X_op == O_constant) | |
1629 | { | |
1630 | exp_p->X_add_number += new_exp.X_add_number; | |
1631 | str = input_line_pointer; | |
1632 | } | |
1633 | ||
1634 | if (&input_line_pointer != str_p) | |
1635 | input_line_pointer = orig_line; | |
1636 | } | |
1637 | ||
1638 | *str_p = str; | |
1639 | return ptr->reloc; | |
1640 | } | |
1641 | ||
1642 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1643 | } |
1644 | ||
e0001a05 | 1645 | |
bbdd25a8 BW |
1646 | /* Find the matching operator type. */ |
1647 | static unsigned char | |
1648 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1649 | { | |
1650 | struct suffix_reloc_map *sfx; | |
1651 | unsigned char operator = (unsigned char) -1; | |
1652 | ||
1653 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1654 | { | |
1655 | if (sfx->reloc == reloc) | |
1656 | { | |
1657 | operator = sfx->operator; | |
1658 | break; | |
1659 | } | |
1660 | } | |
1661 | assert (operator != (unsigned char) -1); | |
1662 | return operator; | |
1663 | } | |
1664 | ||
1665 | ||
1666 | /* Find the matching reloc type. */ | |
1667 | static bfd_reloc_code_real_type | |
1668 | map_operator_to_reloc (unsigned char operator) | |
1669 | { | |
1670 | struct suffix_reloc_map *sfx; | |
1671 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1672 | ||
1673 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1674 | { | |
1675 | if (sfx->operator == operator) | |
1676 | { | |
1677 | reloc = sfx->reloc; | |
1678 | break; | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | if (reloc == BFD_RELOC_UNUSED) | |
1683 | return BFD_RELOC_32; | |
1684 | ||
1685 | return reloc; | |
1686 | } | |
1687 | ||
1688 | ||
e0001a05 | 1689 | static const char * |
7fa3d080 | 1690 | expression_end (const char *name) |
e0001a05 NC |
1691 | { |
1692 | while (1) | |
1693 | { | |
1694 | switch (*name) | |
1695 | { | |
43cd72b9 | 1696 | case '}': |
e0001a05 NC |
1697 | case ';': |
1698 | case '\0': | |
1699 | case ',': | |
43cd72b9 | 1700 | case ':': |
e0001a05 NC |
1701 | return name; |
1702 | case ' ': | |
1703 | case '\t': | |
1704 | ++name; | |
1705 | continue; | |
1706 | default: | |
1707 | return 0; | |
1708 | } | |
1709 | } | |
1710 | } | |
1711 | ||
1712 | ||
1713 | #define ERROR_REG_NUM ((unsigned) -1) | |
1714 | ||
1715 | static unsigned | |
7fa3d080 | 1716 | tc_get_register (const char *prefix) |
e0001a05 NC |
1717 | { |
1718 | unsigned reg; | |
1719 | const char *next_expr; | |
1720 | const char *old_line_pointer; | |
1721 | ||
1722 | SKIP_WHITESPACE (); | |
1723 | old_line_pointer = input_line_pointer; | |
1724 | ||
1725 | if (*input_line_pointer == '$') | |
1726 | ++input_line_pointer; | |
1727 | ||
1728 | /* Accept "sp" as a synonym for "a1". */ | |
1729 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1730 | && expression_end (input_line_pointer + 2)) | |
1731 | { | |
1732 | input_line_pointer += 2; | |
1733 | return 1; /* AR[1] */ | |
1734 | } | |
1735 | ||
1736 | while (*input_line_pointer++ == *prefix++) | |
1737 | ; | |
1738 | --input_line_pointer; | |
1739 | --prefix; | |
1740 | ||
1741 | if (*prefix) | |
1742 | { | |
1743 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1744 | return ERROR_REG_NUM; | |
1745 | } | |
1746 | ||
1747 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1748 | { | |
1749 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1750 | return ERROR_REG_NUM; | |
1751 | } | |
1752 | ||
1753 | reg = 0; | |
1754 | ||
1755 | while (ISDIGIT ((int) *input_line_pointer)) | |
1756 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1757 | ||
1758 | if (!(next_expr = expression_end (input_line_pointer))) | |
1759 | { | |
1760 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1761 | return ERROR_REG_NUM; | |
1762 | } | |
1763 | ||
1764 | input_line_pointer = (char *) next_expr; | |
1765 | ||
1766 | return reg; | |
1767 | } | |
1768 | ||
1769 | ||
e0001a05 | 1770 | static void |
7fa3d080 | 1771 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1772 | { |
43cd72b9 | 1773 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1774 | |
43cd72b9 BW |
1775 | /* Check if this is an immediate operand. */ |
1776 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1777 | { |
43cd72b9 | 1778 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1779 | segT t = expression (tok); |
43cd72b9 BW |
1780 | if (t == absolute_section |
1781 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1782 | { |
1783 | assert (tok->X_op == O_constant); | |
1784 | tok->X_op = O_symbol; | |
1785 | tok->X_add_symbol = &abs_symbol; | |
1786 | } | |
43cd72b9 BW |
1787 | |
1788 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1789 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1790 | != BFD_RELOC_NONE)) | |
e0001a05 | 1791 | { |
1bbb5f21 | 1792 | switch (reloc) |
43cd72b9 | 1793 | { |
1bbb5f21 BW |
1794 | case BFD_RELOC_LO16: |
1795 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1796 | { |
43cd72b9 | 1797 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1798 | return; |
1bbb5f21 BW |
1799 | } |
1800 | break; | |
1801 | case BFD_RELOC_HI16: | |
1802 | if (tok->X_op == O_constant) | |
1803 | { | |
43cd72b9 | 1804 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1805 | return; |
bbdd25a8 | 1806 | } |
1bbb5f21 BW |
1807 | break; |
1808 | case BFD_RELOC_UNUSED: | |
1809 | as_bad (_("unsupported relocation")); | |
1810 | return; | |
1811 | case BFD_RELOC_32_PCREL: | |
1812 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1813 | return; | |
1814 | default: | |
1815 | break; | |
43cd72b9 | 1816 | } |
bbdd25a8 | 1817 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1818 | } |
e0001a05 NC |
1819 | } |
1820 | else | |
1821 | { | |
43cd72b9 BW |
1822 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1823 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1824 | |
1825 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1826 | { | |
1827 | uint32 buf = reg; | |
43cd72b9 | 1828 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1829 | as_bad (_("register number out of range")); |
1830 | } | |
1831 | ||
1832 | tok->X_op = O_register; | |
1833 | tok->X_add_symbol = 0; | |
1834 | tok->X_add_number = reg; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | ||
1839 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1840 | ||
1841 | static int | |
7fa3d080 | 1842 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1843 | { |
1844 | char *old_input_line_pointer; | |
1845 | bfd_boolean saw_comma = FALSE; | |
1846 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1847 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1848 | int num_args = 0; |
1849 | char *arg_end, *arg; | |
1850 | int arg_len; | |
43cd72b9 BW |
1851 | |
1852 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1853 | old_input_line_pointer = input_line_pointer; |
1854 | input_line_pointer = str; | |
1855 | ||
1856 | while (*input_line_pointer) | |
1857 | { | |
1858 | SKIP_WHITESPACE (); | |
1859 | switch (*input_line_pointer) | |
1860 | { | |
1861 | case '\0': | |
43cd72b9 | 1862 | case '}': |
e0001a05 NC |
1863 | goto fini; |
1864 | ||
43cd72b9 BW |
1865 | case ':': |
1866 | input_line_pointer++; | |
1867 | if (saw_comma || saw_colon || !saw_arg) | |
1868 | goto err; | |
1869 | saw_colon = TRUE; | |
1870 | break; | |
1871 | ||
e0001a05 NC |
1872 | case ',': |
1873 | input_line_pointer++; | |
43cd72b9 | 1874 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1875 | goto err; |
1876 | saw_comma = TRUE; | |
1877 | break; | |
1878 | ||
1879 | default: | |
43cd72b9 | 1880 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1881 | goto err; |
1882 | ||
1883 | arg_end = input_line_pointer + 1; | |
1884 | while (!expression_end (arg_end)) | |
1885 | arg_end += 1; | |
43cd72b9 | 1886 | |
e0001a05 | 1887 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1888 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1889 | args[num_args] = arg; |
1890 | ||
43cd72b9 BW |
1891 | if (saw_colon) |
1892 | *arg++ = ':'; | |
e0001a05 NC |
1893 | strncpy (arg, input_line_pointer, arg_len); |
1894 | arg[arg_len] = '\0'; | |
43cd72b9 | 1895 | |
e0001a05 NC |
1896 | input_line_pointer = arg_end; |
1897 | num_args += 1; | |
c138bc38 | 1898 | saw_comma = FALSE; |
43cd72b9 | 1899 | saw_colon = FALSE; |
c138bc38 | 1900 | saw_arg = TRUE; |
e0001a05 NC |
1901 | break; |
1902 | } | |
1903 | } | |
1904 | ||
1905 | fini: | |
43cd72b9 | 1906 | if (saw_comma || saw_colon) |
e0001a05 NC |
1907 | goto err; |
1908 | input_line_pointer = old_input_line_pointer; | |
1909 | return num_args; | |
1910 | ||
1911 | err: | |
43cd72b9 BW |
1912 | if (saw_comma) |
1913 | as_bad (_("extra comma")); | |
1914 | else if (saw_colon) | |
1915 | as_bad (_("extra colon")); | |
1916 | else if (!saw_arg) | |
c138bc38 | 1917 | as_bad (_("missing argument")); |
43cd72b9 BW |
1918 | else |
1919 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1920 | input_line_pointer = old_input_line_pointer; |
1921 | return -1; | |
1922 | } | |
1923 | ||
1924 | ||
43cd72b9 | 1925 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1926 | |
1927 | static bfd_boolean | |
7fa3d080 | 1928 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1929 | { |
43cd72b9 | 1930 | expressionS *tok, *last_tok; |
e0001a05 NC |
1931 | xtensa_opcode opcode = insn->opcode; |
1932 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1933 | xtensa_isa isa = xtensa_default_isa; |
1934 | int n, num_regs = 0; | |
e0001a05 | 1935 | int opcode_operand_count; |
43cd72b9 BW |
1936 | int opnd_cnt, last_opnd_cnt; |
1937 | unsigned int next_reg = 0; | |
e0001a05 NC |
1938 | char *old_input_line_pointer; |
1939 | ||
1940 | if (insn->insn_type == ITYPE_LITERAL) | |
1941 | opcode_operand_count = 1; | |
1942 | else | |
43cd72b9 | 1943 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1944 | |
43cd72b9 | 1945 | tok = insn->tok; |
e0001a05 NC |
1946 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1947 | ||
1948 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1949 | old_input_line_pointer = input_line_pointer; |
1950 | ||
1951 | last_tok = 0; | |
1952 | last_opnd_cnt = -1; | |
1953 | opnd_cnt = 0; | |
1954 | ||
1955 | /* Skip invisible operands. */ | |
1956 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1957 | { | |
1958 | opnd_cnt += 1; | |
1959 | tok++; | |
1960 | } | |
e0001a05 NC |
1961 | |
1962 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1963 | { |
e0001a05 | 1964 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1965 | if (*input_line_pointer == ':') |
1966 | { | |
1967 | xtensa_regfile opnd_rf; | |
1968 | input_line_pointer++; | |
1969 | if (num_regs == 0) | |
1970 | goto err; | |
1971 | assert (opnd_cnt > 0); | |
1972 | num_regs--; | |
1973 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1974 | if (next_reg | |
1975 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1976 | as_warn (_("incorrect register number, ignoring")); | |
1977 | next_reg++; | |
1978 | } | |
1979 | else | |
1980 | { | |
1981 | if (opnd_cnt >= opcode_operand_count) | |
1982 | { | |
1983 | as_warn (_("too many arguments")); | |
1984 | goto err; | |
1985 | } | |
1986 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1987 | ||
1988 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1989 | next_reg = tok->X_add_number + 1; | |
1990 | ||
1991 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1992 | goto err; | |
1993 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1994 | { | |
1995 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1996 | /* minus 1 because we are seeing one right now */ | |
1997 | } | |
1998 | else | |
1999 | num_regs = 0; | |
e0001a05 | 2000 | |
43cd72b9 BW |
2001 | last_tok = tok; |
2002 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 2003 | |
43cd72b9 BW |
2004 | do |
2005 | { | |
2006 | opnd_cnt += 1; | |
2007 | tok++; | |
2008 | } | |
2009 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2010 | } | |
2011 | } | |
e0001a05 | 2012 | |
43cd72b9 BW |
2013 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2014 | goto err; | |
e0001a05 NC |
2015 | |
2016 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2017 | had_error = FALSE; |
e0001a05 NC |
2018 | |
2019 | err: | |
43cd72b9 | 2020 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2021 | return had_error; |
2022 | } | |
2023 | ||
2024 | ||
43cd72b9 | 2025 | static int |
7fa3d080 | 2026 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2027 | { |
2028 | xtensa_isa isa = xtensa_default_isa; | |
2029 | static xtensa_insnbuf slotbuf = NULL; | |
2030 | xtensa_format fmt; | |
2031 | xtensa_opcode opc = insn->opcode; | |
2032 | int slot, opnd, fmt_found; | |
2033 | unsigned val; | |
2034 | ||
2035 | if (!slotbuf) | |
2036 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2037 | ||
2038 | /* Find format/slot where this can be encoded. */ | |
2039 | fmt_found = 0; | |
2040 | slot = 0; | |
2041 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2042 | { | |
2043 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2044 | { | |
2045 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2046 | { | |
2047 | fmt_found = 1; | |
2048 | break; | |
2049 | } | |
2050 | } | |
2051 | if (fmt_found) break; | |
2052 | } | |
2053 | ||
2054 | if (!fmt_found) | |
2055 | { | |
2056 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2057 | return -1; | |
2058 | } | |
2059 | ||
2060 | /* First encode all the visible operands | |
2061 | (to deal with shared field operands). */ | |
2062 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2063 | { | |
2064 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2065 | && (insn->tok[opnd].X_op == O_register | |
2066 | || insn->tok[opnd].X_op == O_constant)) | |
2067 | { | |
2068 | val = insn->tok[opnd].X_add_number; | |
2069 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2070 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2071 | } | |
2072 | } | |
2073 | ||
2074 | /* Then pull out the values for the invisible ones. */ | |
2075 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2076 | { | |
2077 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2078 | { | |
2079 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2080 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2081 | insn->tok[opnd].X_add_number = val; | |
2082 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2083 | insn->tok[opnd].X_op = O_register; | |
2084 | else | |
2085 | insn->tok[opnd].X_op = O_constant; | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
2092 | ||
e0001a05 | 2093 | static void |
7fa3d080 | 2094 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2095 | { |
2096 | char *cnt_arg, *new_arg; | |
2097 | cnt_arg = *cnt_argp; | |
2098 | ||
2099 | /* replace the argument with "31-(argument)" */ | |
2100 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2101 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2102 | ||
2103 | free (cnt_arg); | |
2104 | *cnt_argp = new_arg; | |
2105 | } | |
2106 | ||
2107 | ||
2108 | /* If "arg" is a constant expression, return non-zero with the value | |
2109 | in *valp. */ | |
2110 | ||
2111 | static int | |
7fa3d080 | 2112 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2113 | { |
2114 | expressionS exp; | |
2115 | char *save_ptr = input_line_pointer; | |
2116 | ||
2117 | input_line_pointer = arg; | |
2118 | expression (&exp); | |
2119 | input_line_pointer = save_ptr; | |
2120 | ||
2121 | if (exp.X_op == O_constant) | |
2122 | { | |
2123 | *valp = exp.X_add_number; | |
2124 | return 1; | |
2125 | } | |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | ||
2131 | static void | |
7fa3d080 | 2132 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2133 | { |
2134 | free (*popname); | |
2135 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2136 | strcpy (*popname, newop); | |
2137 | } | |
2138 | ||
2139 | ||
2140 | static int | |
7fa3d080 BW |
2141 | xg_check_num_args (int *pnum_args, |
2142 | int expected_num, | |
2143 | char *opname, | |
2144 | char **arg_strings) | |
e0001a05 NC |
2145 | { |
2146 | int num_args = *pnum_args; | |
2147 | ||
43cd72b9 | 2148 | if (num_args < expected_num) |
e0001a05 NC |
2149 | { |
2150 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2151 | num_args, opname, expected_num); | |
2152 | return -1; | |
2153 | } | |
2154 | ||
2155 | if (num_args > expected_num) | |
2156 | { | |
2157 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2158 | num_args, opname, expected_num); | |
2159 | while (num_args-- > expected_num) | |
2160 | { | |
2161 | free (arg_strings[num_args]); | |
2162 | arg_strings[num_args] = 0; | |
2163 | } | |
2164 | *pnum_args = expected_num; | |
2165 | return -1; | |
2166 | } | |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | ||
43cd72b9 BW |
2172 | /* If the register is not specified as part of the opcode, |
2173 | then get it from the operand and move it to the opcode. */ | |
2174 | ||
e0001a05 | 2175 | static int |
7fa3d080 | 2176 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2177 | { |
43cd72b9 BW |
2178 | xtensa_isa isa = xtensa_default_isa; |
2179 | xtensa_sysreg sr; | |
e0001a05 | 2180 | char *opname, *new_opname; |
43cd72b9 BW |
2181 | const char *sr_name; |
2182 | int is_user, is_write; | |
e0001a05 NC |
2183 | |
2184 | opname = *popname; | |
2185 | if (*opname == '_') | |
80ca4e2c | 2186 | opname += 1; |
43cd72b9 BW |
2187 | is_user = (opname[1] == 'u'); |
2188 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2189 | |
43cd72b9 | 2190 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2191 | |
43cd72b9 BW |
2192 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2193 | return -1; | |
e0001a05 | 2194 | |
43cd72b9 BW |
2195 | /* Check if the argument is a symbolic register name. */ |
2196 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2197 | /* Handle WSR to "INTSET" as a special case. */ | |
2198 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2199 | && !strcasecmp (arg_strings[1], "intset")) | |
2200 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2201 | if (sr == XTENSA_UNDEFINED | |
2202 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2203 | { | |
2204 | /* Maybe it's a register number.... */ | |
2205 | offsetT val; | |
e0001a05 NC |
2206 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2207 | { | |
43cd72b9 BW |
2208 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2209 | arg_strings[1], opname); | |
e0001a05 NC |
2210 | return -1; |
2211 | } | |
43cd72b9 BW |
2212 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2213 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2214 | { |
43cd72b9 | 2215 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2216 | (long) val, opname); |
e0001a05 NC |
2217 | return -1; |
2218 | } | |
43cd72b9 | 2219 | } |
e0001a05 | 2220 | |
43cd72b9 BW |
2221 | /* Remove the last argument, which is now part of the opcode. */ |
2222 | free (arg_strings[1]); | |
2223 | arg_strings[1] = 0; | |
2224 | *pnum_args = 1; | |
2225 | ||
2226 | /* Translate the opcode. */ | |
2227 | sr_name = xtensa_sysreg_name (isa, sr); | |
2228 | /* Another special case for "WSR.INTSET".... */ | |
2229 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2230 | sr_name = "intset"; | |
2231 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2232 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2233 | free (*popname); |
2234 | *popname = new_opname; | |
2235 | ||
2236 | return 0; | |
2237 | } | |
2238 | ||
2239 | ||
2240 | static int | |
7fa3d080 | 2241 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2242 | { |
2243 | xtensa_isa isa = xtensa_default_isa; | |
2244 | xtensa_sysreg sr; | |
2245 | char *opname, *new_opname; | |
2246 | const char *sr_name; | |
2247 | bfd_boolean has_underbar = FALSE; | |
2248 | ||
2249 | opname = *popname; | |
2250 | if (opname[0] == '_') | |
2251 | { | |
2252 | has_underbar = TRUE; | |
2253 | opname += 1; | |
2254 | } | |
2255 | ||
2256 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2257 | if (sr != XTENSA_UNDEFINED) | |
2258 | { | |
2259 | /* The new default name ("nnn") is different from the old default | |
2260 | name ("URnnn"). The old default is handled below, and we don't | |
2261 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2262 | default. */ | |
2263 | static char namebuf[10]; | |
2264 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2265 | if (strcmp (namebuf, opname + 1) == 0) | |
2266 | return 0; | |
2267 | } | |
2268 | else | |
2269 | { | |
2270 | offsetT val; | |
2271 | char *end; | |
2272 | ||
2273 | /* Only continue if the reg name is "URnnn". */ | |
2274 | if (opname[1] != 'u' || opname[2] != 'r') | |
2275 | return 0; | |
2276 | val = strtoul (opname + 3, &end, 10); | |
2277 | if (*end != '\0') | |
2278 | return 0; | |
2279 | ||
2280 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2281 | if (sr == XTENSA_UNDEFINED) | |
2282 | { | |
2283 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2284 | (long) val, opname); |
43cd72b9 BW |
2285 | return -1; |
2286 | } | |
2287 | } | |
2288 | ||
2289 | /* Translate the opcode. */ | |
2290 | sr_name = xtensa_sysreg_name (isa, sr); | |
2291 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2292 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2293 | opname[0], sr_name); | |
2294 | free (*popname); | |
2295 | *popname = new_opname; | |
2296 | ||
2297 | return 0; | |
2298 | } | |
2299 | ||
2300 | ||
2301 | static int | |
7fa3d080 BW |
2302 | xtensa_translate_zero_immed (char *old_op, |
2303 | char *new_op, | |
2304 | char **popname, | |
2305 | int *pnum_args, | |
2306 | char **arg_strings) | |
43cd72b9 BW |
2307 | { |
2308 | char *opname; | |
2309 | offsetT val; | |
2310 | ||
2311 | opname = *popname; | |
2312 | assert (opname[0] != '_'); | |
2313 | ||
2314 | if (strcmp (opname, old_op) != 0) | |
2315 | return 0; | |
e0001a05 | 2316 | |
43cd72b9 BW |
2317 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2318 | return -1; | |
2319 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2320 | { | |
2321 | xg_replace_opname (popname, new_op); | |
2322 | free (arg_strings[1]); | |
2323 | arg_strings[1] = arg_strings[2]; | |
2324 | arg_strings[2] = 0; | |
2325 | *pnum_args = 2; | |
e0001a05 NC |
2326 | } |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
2331 | ||
2332 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2333 | Returns non-zero if an error was found. */ | |
2334 | ||
2335 | static int | |
7fa3d080 | 2336 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2337 | { |
2338 | char *opname = *popname; | |
2339 | bfd_boolean has_underbar = FALSE; | |
2340 | ||
2341 | if (*opname == '_') | |
2342 | { | |
2343 | has_underbar = TRUE; | |
2344 | opname += 1; | |
2345 | } | |
2346 | ||
2347 | if (strcmp (opname, "mov") == 0) | |
2348 | { | |
43cd72b9 | 2349 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2350 | xg_replace_opname (popname, "mov.n"); |
2351 | else | |
2352 | { | |
2353 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2354 | return -1; | |
2355 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2356 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2357 | strcpy (arg_strings[2], arg_strings[1]); | |
2358 | *pnum_args = 3; | |
2359 | } | |
2360 | return 0; | |
2361 | } | |
2362 | ||
2363 | if (strcmp (opname, "bbsi.l") == 0) | |
2364 | { | |
2365 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2366 | return -1; | |
2367 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2368 | if (target_big_endian) | |
2369 | xg_reverse_shift_count (&arg_strings[1]); | |
2370 | return 0; | |
2371 | } | |
2372 | ||
2373 | if (strcmp (opname, "bbci.l") == 0) | |
2374 | { | |
2375 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2376 | return -1; | |
2377 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2378 | if (target_big_endian) | |
2379 | xg_reverse_shift_count (&arg_strings[1]); | |
2380 | return 0; | |
2381 | } | |
2382 | ||
eb6d9dce BW |
2383 | /* Don't do anything special with NOPs inside FLIX instructions. They |
2384 | are handled elsewhere. Real NOP instructions are always available | |
2385 | in configurations with FLIX, so this should never be an issue but | |
2386 | check for it anyway. */ | |
2387 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2388 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2389 | { |
43cd72b9 | 2390 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2391 | xg_replace_opname (popname, "nop.n"); |
2392 | else | |
2393 | { | |
2394 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2395 | return -1; | |
2396 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2397 | arg_strings[0] = (char *) xmalloc (3); | |
2398 | arg_strings[1] = (char *) xmalloc (3); | |
2399 | arg_strings[2] = (char *) xmalloc (3); | |
2400 | strcpy (arg_strings[0], "a1"); | |
2401 | strcpy (arg_strings[1], "a1"); | |
2402 | strcpy (arg_strings[2], "a1"); | |
2403 | *pnum_args = 3; | |
2404 | } | |
2405 | return 0; | |
2406 | } | |
2407 | ||
43cd72b9 BW |
2408 | /* Recognize [RW]UR and [RWX]SR. */ |
2409 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2410 | && (opname[1] == 'u' || opname[1] == 's')) | |
2411 | || (opname[0] == 'x' && opname[1] == 's')) | |
2412 | && opname[2] == 'r' | |
2413 | && opname[3] == '\0') | |
e0001a05 NC |
2414 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2415 | ||
43cd72b9 BW |
2416 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2417 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2418 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2419 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2420 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2421 | |
43cd72b9 BW |
2422 | /* Relax branches that don't allow comparisons against an immediate value |
2423 | of zero to the corresponding branches with implicit zero immediates. */ | |
2424 | if (!has_underbar && use_transform ()) | |
2425 | { | |
2426 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2427 | pnum_args, arg_strings)) | |
2428 | return -1; | |
e0001a05 | 2429 | |
43cd72b9 BW |
2430 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2431 | pnum_args, arg_strings)) | |
2432 | return -1; | |
e0001a05 | 2433 | |
43cd72b9 BW |
2434 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2435 | pnum_args, arg_strings)) | |
2436 | return -1; | |
e0001a05 | 2437 | |
43cd72b9 BW |
2438 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2439 | pnum_args, arg_strings)) | |
2440 | return -1; | |
2441 | } | |
e0001a05 | 2442 | |
43cd72b9 BW |
2443 | return 0; |
2444 | } | |
e0001a05 | 2445 | |
43cd72b9 BW |
2446 | \f |
2447 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2448 | |
43cd72b9 BW |
2449 | /* Currently the assembler only allows us to use a single target per |
2450 | fragment. Because of this, only one operand for a given | |
2451 | instruction may be symbolic. If there is a PC-relative operand, | |
2452 | the last one is chosen. Otherwise, the result is the number of the | |
2453 | last immediate operand, and if there are none of those, we fail and | |
2454 | return -1. */ | |
e0001a05 | 2455 | |
7fa3d080 BW |
2456 | static int |
2457 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2458 | { |
2459 | int last_immed = -1; | |
2460 | int noperands, opi; | |
e0001a05 | 2461 | |
43cd72b9 BW |
2462 | if (opcode == XTENSA_UNDEFINED) |
2463 | return -1; | |
e0001a05 | 2464 | |
43cd72b9 BW |
2465 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2466 | for (opi = noperands - 1; opi >= 0; opi--) | |
2467 | { | |
2468 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2469 | continue; | |
2470 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2471 | return opi; | |
2472 | if (last_immed == -1 | |
2473 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2474 | last_immed = opi; | |
e0001a05 | 2475 | } |
43cd72b9 | 2476 | return last_immed; |
e0001a05 NC |
2477 | } |
2478 | ||
e0001a05 | 2479 | |
43cd72b9 | 2480 | static xtensa_opcode |
7fa3d080 | 2481 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2482 | { |
43cd72b9 BW |
2483 | static xtensa_insnbuf insnbuf = NULL; |
2484 | static xtensa_insnbuf slotbuf = NULL; | |
2485 | xtensa_isa isa = xtensa_default_isa; | |
2486 | xtensa_format fmt; | |
2487 | ||
2488 | if (!insnbuf) | |
e0001a05 | 2489 | { |
43cd72b9 BW |
2490 | insnbuf = xtensa_insnbuf_alloc (isa); |
2491 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2492 | } |
e0001a05 | 2493 | |
d77b99c9 | 2494 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2495 | fmt = xtensa_format_decode (isa, insnbuf); |
2496 | if (fmt == XTENSA_UNDEFINED) | |
2497 | return XTENSA_UNDEFINED; | |
e0001a05 | 2498 | |
43cd72b9 BW |
2499 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2500 | return XTENSA_UNDEFINED; | |
e0001a05 | 2501 | |
43cd72b9 BW |
2502 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2503 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2504 | } |
2505 | ||
2506 | ||
43cd72b9 | 2507 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2508 | |
43cd72b9 | 2509 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2510 | |
7fa3d080 BW |
2511 | static void |
2512 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2513 | { |
2514 | int num_opcodes, num_operands; | |
2515 | xtensa_opcode opcode; | |
2516 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2517 | |
43cd72b9 BW |
2518 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2519 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2520 | { |
43cd72b9 BW |
2521 | int opn; |
2522 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2523 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2524 | for (opn = 0; opn < num_operands; opn++) | |
2525 | { | |
2526 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2527 | continue; | |
2528 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2529 | { | |
2530 | xtensa_regfile opnd_rf = | |
2531 | xtensa_operand_regfile (isa, opcode, opn); | |
2532 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2533 | } | |
2534 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2535 | fputs ("[lLr] ", stderr); | |
2536 | else | |
2537 | fputs ("i ", stderr); | |
2538 | } | |
2539 | fprintf (stderr, "\n"); | |
e0001a05 | 2540 | } |
e0001a05 NC |
2541 | } |
2542 | ||
2543 | ||
43cd72b9 | 2544 | static void |
7fa3d080 | 2545 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2546 | { |
e0001a05 | 2547 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2548 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2549 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2550 | int op; | |
e0001a05 | 2551 | |
43cd72b9 | 2552 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2553 | |
43cd72b9 BW |
2554 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2555 | { | |
2556 | xtensa_opcode opcode; | |
2557 | const char *opname; | |
2558 | int operands; | |
2559 | ||
2560 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2561 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2562 | opname = xtensa_opcode_name (isa, opcode); | |
2563 | ||
2564 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2565 | fprintf (stderr, " operands = "); | |
2566 | for (operands = 0; | |
2567 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2568 | operands++) | |
2569 | { | |
2570 | unsigned int val; | |
2571 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2572 | continue; | |
2573 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2574 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2575 | fprintf (stderr, "%d ", val); | |
2576 | } | |
2577 | fprintf (stderr, "\n"); | |
2578 | } | |
2579 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2580 | } |
2581 | ||
43cd72b9 BW |
2582 | #endif /* TENSILICA_DEBUG */ |
2583 | ||
e0001a05 NC |
2584 | |
2585 | static bfd_boolean | |
7fa3d080 | 2586 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2587 | { |
43cd72b9 BW |
2588 | xtensa_isa isa = xtensa_default_isa; |
2589 | int n, num_operands; | |
e0001a05 | 2590 | |
64b607e6 | 2591 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2592 | return FALSE; |
2593 | ||
43cd72b9 BW |
2594 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2595 | for (n = 0; n < num_operands; n++) | |
2596 | { | |
2597 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2598 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2599 | return TRUE; | |
2600 | } | |
2601 | return FALSE; | |
e0001a05 NC |
2602 | } |
2603 | ||
2604 | ||
43cd72b9 BW |
2605 | /* Convert from BFD relocation type code to slot and operand number. |
2606 | Returns non-zero on failure. */ | |
e0001a05 | 2607 | |
43cd72b9 | 2608 | static int |
7fa3d080 | 2609 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2610 | { |
43cd72b9 BW |
2611 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2612 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2613 | { |
43cd72b9 BW |
2614 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2615 | *is_alt = FALSE; | |
e0001a05 | 2616 | } |
43cd72b9 BW |
2617 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2618 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2619 | { |
43cd72b9 BW |
2620 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2621 | *is_alt = TRUE; | |
e0001a05 | 2622 | } |
43cd72b9 BW |
2623 | else |
2624 | return -1; | |
2625 | ||
2626 | return 0; | |
e0001a05 NC |
2627 | } |
2628 | ||
2629 | ||
43cd72b9 BW |
2630 | /* Convert from slot number to BFD relocation type code for the |
2631 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2632 | failure. */ | |
e0001a05 | 2633 | |
43cd72b9 | 2634 | static bfd_reloc_code_real_type |
7fa3d080 | 2635 | encode_reloc (int slot) |
e0001a05 | 2636 | { |
43cd72b9 BW |
2637 | if (slot < 0 || slot > 14) |
2638 | return BFD_RELOC_NONE; | |
2639 | ||
2640 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2641 | } |
2642 | ||
2643 | ||
43cd72b9 BW |
2644 | /* Convert from slot numbers to BFD relocation type code for the |
2645 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2646 | |
43cd72b9 | 2647 | static bfd_reloc_code_real_type |
7fa3d080 | 2648 | encode_alt_reloc (int slot) |
e0001a05 | 2649 | { |
43cd72b9 BW |
2650 | if (slot < 0 || slot > 14) |
2651 | return BFD_RELOC_NONE; | |
2652 | ||
2653 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2654 | } |
2655 | ||
2656 | ||
2657 | static void | |
7fa3d080 BW |
2658 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2659 | xtensa_format fmt, | |
2660 | int slot, | |
2661 | xtensa_opcode opcode, | |
2662 | int operand, | |
2663 | uint32 value, | |
2664 | const char *file, | |
2665 | unsigned int line) | |
e0001a05 | 2666 | { |
e0001a05 NC |
2667 | uint32 valbuf = value; |
2668 | ||
43cd72b9 | 2669 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2670 | { |
43cd72b9 BW |
2671 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2672 | == 1) | |
2673 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2674 | _("operand %d of '%s' has out of range value '%u'"), |
2675 | operand + 1, | |
2676 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2677 | value); | |
43cd72b9 BW |
2678 | else |
2679 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2680 | _("operand %d of '%s' has invalid value '%u'"), |
2681 | operand + 1, | |
2682 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2683 | value); | |
43cd72b9 | 2684 | return; |
e0001a05 NC |
2685 | } |
2686 | ||
43cd72b9 BW |
2687 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2688 | slotbuf, valbuf); | |
e0001a05 NC |
2689 | } |
2690 | ||
2691 | ||
2692 | static uint32 | |
7fa3d080 BW |
2693 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2694 | xtensa_format fmt, | |
2695 | int slot, | |
2696 | xtensa_opcode opcode, | |
2697 | int opnum) | |
e0001a05 | 2698 | { |
43cd72b9 BW |
2699 | uint32 val = 0; |
2700 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2701 | fmt, slot, slotbuf, &val); | |
2702 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2703 | return val; | |
e0001a05 NC |
2704 | } |
2705 | ||
e0001a05 | 2706 | \f |
7fa3d080 | 2707 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2708 | |
7fa3d080 BW |
2709 | /* The routine xg_instruction_matches_option_term must return TRUE |
2710 | when a given option term is true. The meaning of all of the option | |
2711 | terms is given interpretation by this function. This is needed when | |
2712 | an option depends on the state of a directive, but there are no such | |
2713 | options in use right now. */ | |
e0001a05 | 2714 | |
7fa3d080 BW |
2715 | static bfd_boolean |
2716 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2717 | const ReqOrOption *option) | |
e0001a05 | 2718 | { |
7fa3d080 BW |
2719 | if (strcmp (option->option_name, "realnop") == 0 |
2720 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2721 | { | |
2722 | /* These conditions were evaluated statically when building the | |
2723 | relaxation table. There's no need to reevaluate them now. */ | |
2724 | return TRUE; | |
2725 | } | |
2726 | else | |
2727 | { | |
2728 | as_fatal (_("internal error: unknown option name '%s'"), | |
2729 | option->option_name); | |
2730 | } | |
e0001a05 NC |
2731 | } |
2732 | ||
2733 | ||
7fa3d080 BW |
2734 | static bfd_boolean |
2735 | xg_instruction_matches_or_options (TInsn *insn, | |
2736 | const ReqOrOptionList *or_option) | |
e0001a05 | 2737 | { |
7fa3d080 BW |
2738 | const ReqOrOption *option; |
2739 | /* Must match each of the AND terms. */ | |
2740 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2741 | { |
7fa3d080 BW |
2742 | if (xg_instruction_matches_option_term (insn, option)) |
2743 | return TRUE; | |
e0001a05 | 2744 | } |
7fa3d080 | 2745 | return FALSE; |
e0001a05 NC |
2746 | } |
2747 | ||
2748 | ||
7fa3d080 BW |
2749 | static bfd_boolean |
2750 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2751 | { |
7fa3d080 BW |
2752 | const ReqOption *req_options; |
2753 | /* Must match each of the AND terms. */ | |
2754 | for (req_options = options; | |
2755 | req_options != NULL; | |
2756 | req_options = req_options->next) | |
e0001a05 | 2757 | { |
7fa3d080 BW |
2758 | /* Must match one of the OR clauses. */ |
2759 | if (!xg_instruction_matches_or_options (insn, | |
2760 | req_options->or_option_terms)) | |
2761 | return FALSE; | |
e0001a05 | 2762 | } |
7fa3d080 | 2763 | return TRUE; |
e0001a05 NC |
2764 | } |
2765 | ||
2766 | ||
7fa3d080 | 2767 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2768 | |
7fa3d080 BW |
2769 | static bfd_boolean |
2770 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2771 | { |
7fa3d080 | 2772 | PreconditionList *condition_l; |
e0001a05 | 2773 | |
7fa3d080 BW |
2774 | if (rule->opcode != insn->opcode) |
2775 | return FALSE; | |
e0001a05 | 2776 | |
7fa3d080 BW |
2777 | for (condition_l = rule->conditions; |
2778 | condition_l != NULL; | |
2779 | condition_l = condition_l->next) | |
e0001a05 | 2780 | { |
7fa3d080 BW |
2781 | expressionS *exp1; |
2782 | expressionS *exp2; | |
2783 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2784 | |
7fa3d080 | 2785 | switch (cond->typ) |
e0001a05 | 2786 | { |
7fa3d080 BW |
2787 | case OP_CONSTANT: |
2788 | /* The expression must be the constant. */ | |
2789 | assert (cond->op_num < insn->ntok); | |
2790 | exp1 = &insn->tok[cond->op_num]; | |
2791 | if (expr_is_const (exp1)) | |
2792 | { | |
2793 | switch (cond->cmp) | |
2794 | { | |
2795 | case OP_EQUAL: | |
2796 | if (get_expr_const (exp1) != cond->op_data) | |
2797 | return FALSE; | |
2798 | break; | |
2799 | case OP_NOTEQUAL: | |
2800 | if (get_expr_const (exp1) == cond->op_data) | |
2801 | return FALSE; | |
2802 | break; | |
2803 | default: | |
2804 | return FALSE; | |
2805 | } | |
2806 | } | |
2807 | else if (expr_is_register (exp1)) | |
2808 | { | |
2809 | switch (cond->cmp) | |
2810 | { | |
2811 | case OP_EQUAL: | |
2812 | if (get_expr_register (exp1) != cond->op_data) | |
2813 | return FALSE; | |
2814 | break; | |
2815 | case OP_NOTEQUAL: | |
2816 | if (get_expr_register (exp1) == cond->op_data) | |
2817 | return FALSE; | |
2818 | break; | |
2819 | default: | |
2820 | return FALSE; | |
2821 | } | |
2822 | } | |
2823 | else | |
2824 | return FALSE; | |
2825 | break; | |
2826 | ||
2827 | case OP_OPERAND: | |
2828 | assert (cond->op_num < insn->ntok); | |
2829 | assert (cond->op_data < insn->ntok); | |
2830 | exp1 = &insn->tok[cond->op_num]; | |
2831 | exp2 = &insn->tok[cond->op_data]; | |
2832 | ||
2833 | switch (cond->cmp) | |
2834 | { | |
2835 | case OP_EQUAL: | |
2836 | if (!expr_is_equal (exp1, exp2)) | |
2837 | return FALSE; | |
2838 | break; | |
2839 | case OP_NOTEQUAL: | |
2840 | if (expr_is_equal (exp1, exp2)) | |
2841 | return FALSE; | |
2842 | break; | |
2843 | } | |
2844 | break; | |
2845 | ||
2846 | case OP_LITERAL: | |
2847 | case OP_LABEL: | |
2848 | default: | |
2849 | return FALSE; | |
2850 | } | |
2851 | } | |
2852 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2853 | return FALSE; | |
2854 | ||
2855 | return TRUE; | |
2856 | } | |
2857 | ||
2858 | ||
2859 | static int | |
2860 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2861 | { | |
2862 | bfd_boolean a_greater = FALSE; | |
2863 | bfd_boolean b_greater = FALSE; | |
2864 | ||
2865 | ReqOptionList *l_a = a->options; | |
2866 | ReqOptionList *l_b = b->options; | |
2867 | ||
2868 | /* We only care if they both are the same except for | |
2869 | a const16 vs. an l32r. */ | |
2870 | ||
2871 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2872 | { | |
2873 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2874 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2875 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2876 | { | |
2877 | if (l_or_a->is_true != l_or_b->is_true) | |
2878 | return 0; | |
2879 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2880 | { | |
2881 | /* This is the case we care about. */ | |
2882 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2883 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2884 | { | |
2885 | if (prefer_const16) | |
2886 | a_greater = TRUE; | |
2887 | else | |
2888 | b_greater = TRUE; | |
2889 | } | |
2890 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2891 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2892 | { | |
2893 | if (prefer_const16) | |
2894 | b_greater = TRUE; | |
2895 | else | |
2896 | a_greater = TRUE; | |
2897 | } | |
2898 | else | |
2899 | return 0; | |
2900 | } | |
2901 | l_or_a = l_or_a->next; | |
2902 | l_or_b = l_or_b->next; | |
2903 | } | |
2904 | if (l_or_a || l_or_b) | |
2905 | return 0; | |
2906 | ||
2907 | l_a = l_a->next; | |
2908 | l_b = l_b->next; | |
2909 | } | |
2910 | if (l_a || l_b) | |
2911 | return 0; | |
2912 | ||
2913 | /* Incomparable if the substitution was used differently in two cases. */ | |
2914 | if (a_greater && b_greater) | |
2915 | return 0; | |
2916 | ||
2917 | if (b_greater) | |
2918 | return 1; | |
2919 | if (a_greater) | |
2920 | return -1; | |
2921 | ||
2922 | return 0; | |
2923 | } | |
2924 | ||
2925 | ||
2926 | static TransitionRule * | |
2927 | xg_instruction_match (TInsn *insn) | |
2928 | { | |
2929 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2930 | TransitionList *l; | |
2931 | assert (insn->opcode < table->num_opcodes); | |
2932 | ||
2933 | /* Walk through all of the possible transitions. */ | |
2934 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2935 | { | |
2936 | TransitionRule *rule = l->rule; | |
2937 | if (xg_instruction_matches_rule (insn, rule)) | |
2938 | return rule; | |
2939 | } | |
2940 | return NULL; | |
2941 | } | |
2942 | ||
2943 | \f | |
2944 | /* Various Other Internal Functions. */ | |
2945 | ||
2946 | static bfd_boolean | |
2947 | is_unique_insn_expansion (TransitionRule *r) | |
2948 | { | |
2949 | if (!r->to_instr || r->to_instr->next != NULL) | |
2950 | return FALSE; | |
2951 | if (r->to_instr->typ != INSTR_INSTR) | |
2952 | return FALSE; | |
2953 | return TRUE; | |
2954 | } | |
2955 | ||
2956 | ||
84b08ed9 BW |
2957 | /* Check if there is exactly one relaxation for INSN that converts it to |
2958 | another instruction of equal or larger size. If so, and if TARG is | |
2959 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2960 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2961 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2962 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2963 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2964 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2965 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2966 | |
84b08ed9 BW |
2967 | bfd_boolean |
2968 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2969 | { |
2970 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2971 | TransitionList *l; | |
84b08ed9 | 2972 | TransitionRule *match = 0; |
7fa3d080 | 2973 | |
7fa3d080 BW |
2974 | assert (insn->insn_type == ITYPE_INSN); |
2975 | assert (insn->opcode < table->num_opcodes); | |
2976 | ||
2977 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2978 | { | |
2979 | TransitionRule *rule = l->rule; | |
2980 | ||
2981 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2982 | && is_unique_insn_expansion (rule) |
2983 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2984 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2985 | { |
84b08ed9 BW |
2986 | if (match) |
2987 | return FALSE; | |
2988 | match = rule; | |
7fa3d080 BW |
2989 | } |
2990 | } | |
84b08ed9 BW |
2991 | if (!match) |
2992 | return FALSE; | |
2993 | ||
2994 | if (targ) | |
2995 | xg_build_to_insn (targ, insn, match->to_instr); | |
2996 | return TRUE; | |
7fa3d080 BW |
2997 | } |
2998 | ||
2999 | ||
3000 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3001 | ||
3002 | static int | |
3003 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3004 | { | |
3005 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3006 | TransitionList *l; | |
3007 | int max_size = xg_get_single_size (opcode); | |
3008 | ||
3009 | assert (opcode < table->num_opcodes); | |
3010 | ||
3011 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3012 | { | |
3013 | TransitionRule *rule = l->rule; | |
3014 | BuildInstr *build_list; | |
3015 | int this_size = 0; | |
3016 | ||
3017 | if (!rule) | |
3018 | continue; | |
3019 | build_list = rule->to_instr; | |
3020 | if (is_unique_insn_expansion (rule)) | |
3021 | { | |
3022 | assert (build_list->typ == INSTR_INSTR); | |
3023 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3024 | } | |
3025 | else | |
3026 | for (; build_list != NULL; build_list = build_list->next) | |
3027 | { | |
3028 | switch (build_list->typ) | |
3029 | { | |
3030 | case INSTR_INSTR: | |
3031 | this_size += xg_get_single_size (build_list->opcode); | |
3032 | break; | |
3033 | case INSTR_LITERAL_DEF: | |
3034 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3035 | default: |
3036 | break; | |
3037 | } | |
3038 | } | |
3039 | if (this_size > max_size) | |
3040 | max_size = this_size; | |
3041 | } | |
3042 | return max_size; | |
3043 | } | |
3044 | ||
3045 | ||
3046 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3047 | ||
7fa3d080 BW |
3048 | static int |
3049 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3050 | { |
43cd72b9 | 3051 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3052 | TransitionList *l; |
3053 | int max_size = 0; | |
3054 | ||
3055 | assert (opcode < table->num_opcodes); | |
3056 | ||
3057 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3058 | { | |
3059 | TransitionRule *rule = l->rule; | |
3060 | BuildInstr *build_list; | |
3061 | int this_size = 0; | |
3062 | ||
3063 | if (!rule) | |
3064 | continue; | |
3065 | build_list = rule->to_instr; | |
3066 | if (is_unique_insn_expansion (rule)) | |
3067 | { | |
3068 | assert (build_list->typ == INSTR_INSTR); | |
3069 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3070 | } | |
3071 | else | |
3072 | for (; build_list != NULL; build_list = build_list->next) | |
3073 | { | |
3074 | switch (build_list->typ) | |
3075 | { | |
3076 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3077 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3078 | this_size += 4; |
3079 | break; | |
3080 | case INSTR_INSTR: | |
3081 | case INSTR_LABEL_DEF: | |
3082 | default: | |
3083 | break; | |
3084 | } | |
3085 | } | |
3086 | if (this_size > max_size) | |
3087 | max_size = this_size; | |
3088 | } | |
3089 | return max_size; | |
3090 | } | |
3091 | ||
3092 | ||
7fa3d080 BW |
3093 | static bfd_boolean |
3094 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3095 | { | |
3096 | int steps_taken = 0; | |
3097 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3098 | TransitionList *l; | |
3099 | ||
3100 | assert (insn->insn_type == ITYPE_INSN); | |
3101 | assert (insn->opcode < table->num_opcodes); | |
3102 | ||
3103 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3104 | { | |
3105 | TransitionRule *rule = l->rule; | |
3106 | ||
3107 | if (xg_instruction_matches_rule (insn, rule)) | |
3108 | { | |
3109 | if (steps_taken == lateral_steps) | |
3110 | return TRUE; | |
3111 | steps_taken++; | |
3112 | } | |
3113 | } | |
3114 | return FALSE; | |
3115 | } | |
3116 | ||
3117 | ||
3118 | static symbolS * | |
3119 | get_special_literal_symbol (void) | |
3120 | { | |
3121 | static symbolS *sym = NULL; | |
3122 | ||
3123 | if (sym == NULL) | |
3124 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3125 | return sym; | |
3126 | } | |
3127 | ||
3128 | ||
3129 | static symbolS * | |
3130 | get_special_label_symbol (void) | |
3131 | { | |
3132 | static symbolS *sym = NULL; | |
3133 | ||
3134 | if (sym == NULL) | |
3135 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3136 | return sym; | |
3137 | } | |
3138 | ||
3139 | ||
3140 | static bfd_boolean | |
3141 | xg_valid_literal_expression (const expressionS *exp) | |
3142 | { | |
3143 | switch (exp->X_op) | |
3144 | { | |
3145 | case O_constant: | |
3146 | case O_symbol: | |
3147 | case O_big: | |
3148 | case O_uminus: | |
3149 | case O_subtract: | |
3150 | case O_pltrel: | |
1bbb5f21 | 3151 | case O_pcrel: |
7fa3d080 BW |
3152 | return TRUE; |
3153 | default: | |
3154 | return FALSE; | |
3155 | } | |
3156 | } | |
3157 | ||
3158 | ||
3159 | /* This will check to see if the value can be converted into the | |
3160 | operand type. It will return TRUE if it does not fit. */ | |
3161 | ||
3162 | static bfd_boolean | |
3163 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3164 | { | |
3165 | uint32 valbuf = value; | |
3166 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3167 | return TRUE; | |
3168 | return FALSE; | |
3169 | } | |
3170 | ||
3171 | ||
3172 | /* Assumes: All immeds are constants. Check that all constants fit | |
3173 | into their immeds; return FALSE if not. */ | |
3174 | ||
3175 | static bfd_boolean | |
3176 | xg_immeds_fit (const TInsn *insn) | |
3177 | { | |
3178 | xtensa_isa isa = xtensa_default_isa; | |
3179 | int i; | |
3180 | ||
3181 | int n = insn->ntok; | |
3182 | assert (insn->insn_type == ITYPE_INSN); | |
3183 | for (i = 0; i < n; ++i) | |
3184 | { | |
3185 | const expressionS *expr = &insn->tok[i]; | |
3186 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3187 | continue; | |
3188 | ||
3189 | switch (expr->X_op) | |
3190 | { | |
3191 | case O_register: | |
3192 | case O_constant: | |
3193 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3194 | return FALSE; | |
3195 | break; | |
3196 | ||
3197 | default: | |
3198 | /* The symbol should have a fixup associated with it. */ | |
3199 | assert (FALSE); | |
3200 | break; | |
3201 | } | |
3202 | } | |
3203 | return TRUE; | |
3204 | } | |
3205 | ||
3206 | ||
3207 | /* This should only be called after we have an initial | |
3208 | estimate of the addresses. */ | |
3209 | ||
3210 | static bfd_boolean | |
3211 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3212 | segT pc_seg, | |
3213 | fragS *pc_frag, | |
3214 | offsetT pc_offset, | |
3215 | long stretch) | |
e0001a05 | 3216 | { |
7fa3d080 BW |
3217 | xtensa_isa isa = xtensa_default_isa; |
3218 | symbolS *symbolP; | |
3219 | fragS *sym_frag; | |
3220 | offsetT target, pc; | |
3221 | uint32 new_offset; | |
3222 | int i; | |
3223 | int n = insn->ntok; | |
e0001a05 NC |
3224 | |
3225 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3226 | |
7fa3d080 | 3227 | for (i = 0; i < n; ++i) |
e0001a05 | 3228 | { |
7fa3d080 BW |
3229 | const expressionS *expr = &insn->tok[i]; |
3230 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3231 | continue; | |
e0001a05 | 3232 | |
7fa3d080 | 3233 | switch (expr->X_op) |
e0001a05 | 3234 | { |
7fa3d080 BW |
3235 | case O_register: |
3236 | case O_constant: | |
3237 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3238 | return FALSE; | |
3239 | break; | |
e0001a05 | 3240 | |
7fa3d080 BW |
3241 | case O_lo16: |
3242 | case O_hi16: | |
3243 | /* Check for the worst case. */ | |
3244 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3245 | return FALSE; | |
3246 | break; | |
e0001a05 | 3247 | |
7fa3d080 | 3248 | case O_symbol: |
7c834684 | 3249 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3250 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3251 | if (pc_frag == 0 |
3252 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3253 | return FALSE; |
e0001a05 | 3254 | |
8e6bc631 BW |
3255 | /* If it is a weak symbol or a symbol in a different section, |
3256 | it cannot be known to fit at assembly time. */ | |
3257 | if (S_IS_WEAK (expr->X_add_symbol) | |
3258 | || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7c834684 | 3259 | { |
8e6bc631 | 3260 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3261 | assume it will be in range. If the symbol is weak and |
3262 | undefined, it may remain undefined at link-time, in which | |
3263 | case it will have a zero value and almost certainly be out | |
3264 | of range for a direct call; thus, relax for undefined weak | |
3265 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3266 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f BW |
3267 | && ! pc_frag->tc_frag_data.use_longcalls |
3268 | && (! S_IS_WEAK (expr->X_add_symbol) | |
3269 | || S_IS_DEFINED (expr->X_add_symbol))) | |
7c834684 | 3270 | return TRUE; |
7c834684 | 3271 | |
8e6bc631 BW |
3272 | return FALSE; |
3273 | } | |
e0001a05 | 3274 | |
7fa3d080 BW |
3275 | symbolP = expr->X_add_symbol; |
3276 | sym_frag = symbol_get_frag (symbolP); | |
3277 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3278 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3279 | |
7fa3d080 BW |
3280 | /* If frag has yet to be reached on this pass, assume it |
3281 | will move by STRETCH just as we did. If this is not so, | |
3282 | it will be because some frag between grows, and that will | |
3283 | force another pass. Beware zero-length frags. There | |
3284 | should be a faster way to do this. */ | |
3285 | ||
3286 | if (stretch != 0 | |
3287 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3288 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3289 | { | |
3290 | target += stretch; | |
3291 | } | |
c138bc38 | 3292 | |
7fa3d080 BW |
3293 | new_offset = target; |
3294 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3295 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3296 | return FALSE; | |
3297 | break; | |
3298 | ||
3299 | default: | |
3300 | /* The symbol should have a fixup associated with it. */ | |
3301 | return FALSE; | |
3302 | } | |
3303 | } | |
3304 | ||
3305 | return TRUE; | |
e0001a05 NC |
3306 | } |
3307 | ||
3308 | ||
43cd72b9 | 3309 | /* Return TRUE on success. */ |
e0001a05 | 3310 | |
7fa3d080 BW |
3311 | static bfd_boolean |
3312 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3313 | { |
3314 | BuildOp *op; | |
3315 | symbolS *sym; | |
3316 | ||
60242db2 | 3317 | tinsn_init (targ); |
b224e962 BW |
3318 | targ->debug_line = insn->debug_line; |
3319 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3320 | switch (bi->typ) |
3321 | { | |
3322 | case INSTR_INSTR: | |
3323 | op = bi->ops; | |
3324 | targ->opcode = bi->opcode; | |
3325 | targ->insn_type = ITYPE_INSN; | |
3326 | targ->is_specific_opcode = FALSE; | |
3327 | ||
3328 | for (; op != NULL; op = op->next) | |
3329 | { | |
3330 | int op_num = op->op_num; | |
3331 | int op_data = op->op_data; | |
3332 | ||
3333 | assert (op->op_num < MAX_INSN_ARGS); | |
3334 | ||
3335 | if (targ->ntok <= op_num) | |
3336 | targ->ntok = op_num + 1; | |
3337 | ||
3338 | switch (op->typ) | |
3339 | { | |
3340 | case OP_CONSTANT: | |
3341 | set_expr_const (&targ->tok[op_num], op_data); | |
3342 | break; | |
3343 | case OP_OPERAND: | |
3344 | assert (op_data < insn->ntok); | |
3345 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3346 | break; | |
3347 | case OP_LITERAL: | |
3348 | sym = get_special_literal_symbol (); | |
3349 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3350 | break; | |
3351 | case OP_LABEL: | |
3352 | sym = get_special_label_symbol (); | |
3353 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3354 | break; | |
43cd72b9 BW |
3355 | case OP_OPERAND_HI16U: |
3356 | case OP_OPERAND_LOW16U: | |
3357 | assert (op_data < insn->ntok); | |
3358 | if (expr_is_const (&insn->tok[op_data])) | |
3359 | { | |
3360 | long val; | |
3361 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3362 | val = xg_apply_userdef_op_fn (op->typ, | |
3363 | targ->tok[op_num]. | |
3364 | X_add_number); | |
3365 | targ->tok[op_num].X_add_number = val; | |
3366 | } | |
3367 | else | |
3368 | { | |
3369 | /* For const16 we can create relocations for these. */ | |
3370 | if (targ->opcode == XTENSA_UNDEFINED | |
3371 | || (targ->opcode != xtensa_const16_opcode)) | |
3372 | return FALSE; | |
3373 | assert (op_data < insn->ntok); | |
3374 | /* Need to build a O_lo16 or O_hi16. */ | |
3375 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3376 | if (targ->tok[op_num].X_op == O_symbol) | |
3377 | { | |
3378 | if (op->typ == OP_OPERAND_HI16U) | |
3379 | targ->tok[op_num].X_op = O_hi16; | |
3380 | else if (op->typ == OP_OPERAND_LOW16U) | |
3381 | targ->tok[op_num].X_op = O_lo16; | |
3382 | else | |
3383 | return FALSE; | |
3384 | } | |
3385 | } | |
3386 | break; | |
e0001a05 NC |
3387 | default: |
3388 | /* currently handles: | |
3389 | OP_OPERAND_LOW8 | |
3390 | OP_OPERAND_HI24S | |
3391 | OP_OPERAND_F32MINUS */ | |
3392 | if (xg_has_userdef_op_fn (op->typ)) | |
3393 | { | |
3394 | assert (op_data < insn->ntok); | |
3395 | if (expr_is_const (&insn->tok[op_data])) | |
3396 | { | |
3397 | long val; | |
3398 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3399 | val = xg_apply_userdef_op_fn (op->typ, | |
3400 | targ->tok[op_num]. | |
3401 | X_add_number); | |
3402 | targ->tok[op_num].X_add_number = val; | |
3403 | } | |
3404 | else | |
3405 | return FALSE; /* We cannot use a relocation for this. */ | |
3406 | break; | |
3407 | } | |
3408 | assert (0); | |
3409 | break; | |
3410 | } | |
3411 | } | |
3412 | break; | |
3413 | ||
3414 | case INSTR_LITERAL_DEF: | |
3415 | op = bi->ops; | |
3416 | targ->opcode = XTENSA_UNDEFINED; | |
3417 | targ->insn_type = ITYPE_LITERAL; | |
3418 | targ->is_specific_opcode = FALSE; | |
3419 | for (; op != NULL; op = op->next) | |
3420 | { | |
3421 | int op_num = op->op_num; | |
3422 | int op_data = op->op_data; | |
3423 | assert (op->op_num < MAX_INSN_ARGS); | |
3424 | ||
3425 | if (targ->ntok <= op_num) | |
3426 | targ->ntok = op_num + 1; | |
3427 | ||
3428 | switch (op->typ) | |
3429 | { | |
3430 | case OP_OPERAND: | |
3431 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3432 | /* We can only pass resolvable literals through. */ |
3433 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3434 | return FALSE; | |
e0001a05 NC |
3435 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3436 | break; | |
3437 | case OP_LITERAL: | |
3438 | case OP_CONSTANT: | |
3439 | case OP_LABEL: | |
3440 | default: | |
3441 | assert (0); | |
3442 | break; | |
3443 | } | |
3444 | } | |
3445 | break; | |
3446 | ||
3447 | case INSTR_LABEL_DEF: | |
3448 | op = bi->ops; | |
3449 | targ->opcode = XTENSA_UNDEFINED; | |
3450 | targ->insn_type = ITYPE_LABEL; | |
3451 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3452 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3453 | assert (op == NULL); |
3454 | break; | |
3455 | ||
3456 | default: | |
3457 | assert (0); | |
3458 | } | |
3459 | ||
3460 | return TRUE; | |
3461 | } | |
3462 | ||
3463 | ||
43cd72b9 | 3464 | /* Return TRUE on success. */ |
e0001a05 | 3465 | |
7fa3d080 BW |
3466 | static bfd_boolean |
3467 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3468 | { |
3469 | for (; bi != NULL; bi = bi->next) | |
3470 | { | |
3471 | TInsn *next_insn = istack_push_space (istack); | |
3472 | ||
3473 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3474 | return FALSE; | |
3475 | } | |
3476 | return TRUE; | |
3477 | } | |
3478 | ||
3479 | ||
43cd72b9 | 3480 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3481 | |
7fa3d080 BW |
3482 | static bfd_boolean |
3483 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3484 | { |
3485 | int stack_size = istack->ninsn; | |
3486 | int steps_taken = 0; | |
43cd72b9 | 3487 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3488 | TransitionList *l; |
3489 | ||
3490 | assert (insn->insn_type == ITYPE_INSN); | |
3491 | assert (insn->opcode < table->num_opcodes); | |
3492 | ||
3493 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3494 | { | |
3495 | TransitionRule *rule = l->rule; | |
3496 | ||
3497 | if (xg_instruction_matches_rule (insn, rule)) | |
3498 | { | |
3499 | if (lateral_steps == steps_taken) | |
3500 | { | |
3501 | int i; | |
3502 | ||
3503 | /* This is it. Expand the rule to the stack. */ | |
3504 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3505 | return FALSE; | |
3506 | ||
3507 | /* Check to see if it fits. */ | |
3508 | for (i = stack_size; i < istack->ninsn; i++) | |
3509 | { | |
3510 | TInsn *insn = &istack->insn[i]; | |
3511 | ||
3512 | if (insn->insn_type == ITYPE_INSN | |
3513 | && !tinsn_has_symbolic_operands (insn) | |
3514 | && !xg_immeds_fit (insn)) | |
3515 | { | |
3516 | istack->ninsn = stack_size; | |
3517 | return FALSE; | |
3518 | } | |
3519 | } | |
3520 | return TRUE; | |
3521 | } | |
3522 | steps_taken++; | |
3523 | } | |
3524 | } | |
3525 | return FALSE; | |
3526 | } | |
3527 | ||
43cd72b9 | 3528 | \f |
43cd72b9 | 3529 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3530 | Return the number of steps taken. |
3531 | ||
3532 | For relaxation to correctly terminate, every relaxation chain must | |
3533 | terminate in one of two ways: | |
3534 | ||
3535 | 1. If the chain from one instruction to the next consists entirely of | |
3536 | single instructions, then the chain *must* handle all possible | |
3537 | immediates without failing. It must not ever fail because an | |
3538 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3539 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3540 | immediate larger than 32 bits, so it satisfies this condition. | |
3541 | Single instruction relaxation chains are as defined by | |
3542 | xg_is_single_relaxable_instruction. | |
3543 | ||
3544 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3545 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3546 | ||
3547 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3548 | -- in particular when the last two instructions have the same single | |
3549 | size. But nevertheless, you should guarantee the above two conditions. | |
3550 | ||
3551 | We could fix this so that single-instruction expansions correctly | |
3552 | terminate when they can't handle the range, but the error messages are | |
3553 | worse, and it actually turns out that in every case but one (18-bit wide | |
3554 | branches), you need a multi-instruction expansion to get the full range | |
3555 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3556 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3557 | |
7fa3d080 BW |
3558 | static int |
3559 | xg_assembly_relax (IStack *istack, | |
3560 | TInsn *insn, | |
3561 | segT pc_seg, | |
3562 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3563 | offsetT pc_offset, /* offset in fragment */ | |
3564 | int min_steps, /* minimum conversion steps */ | |
3565 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3566 | { |
3567 | int steps_taken = 0; | |
3568 | ||
b81bf389 BW |
3569 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3570 | This may go through a couple of stages of single instruction | |
3571 | transformations before we get there. */ | |
e0001a05 NC |
3572 | |
3573 | TInsn single_target; | |
3574 | TInsn current_insn; | |
3575 | int lateral_steps = 0; | |
3576 | int istack_size = istack->ninsn; | |
3577 | ||
3578 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3579 | && steps_taken >= min_steps) | |
3580 | { | |
3581 | istack_push (istack, insn); | |
3582 | return steps_taken; | |
3583 | } | |
43cd72b9 | 3584 | current_insn = *insn; |
e0001a05 | 3585 | |
7c834684 | 3586 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3587 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3588 | { |
21af2bbd | 3589 | steps_taken++; |
e0001a05 NC |
3590 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3591 | stretch)) | |
3592 | { | |
e0001a05 NC |
3593 | if (steps_taken >= min_steps) |
3594 | { | |
3595 | istack_push (istack, &single_target); | |
3596 | return steps_taken; | |
3597 | } | |
3598 | } | |
43cd72b9 | 3599 | current_insn = single_target; |
e0001a05 NC |
3600 | } |
3601 | ||
3602 | /* Now check for a multi-instruction expansion. */ | |
3603 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3604 | { | |
3605 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3606 | stretch)) | |
3607 | { | |
3608 | if (steps_taken >= min_steps) | |
3609 | { | |
3610 | istack_push (istack, ¤t_insn); | |
3611 | return steps_taken; | |
3612 | } | |
3613 | } | |
3614 | steps_taken++; | |
3615 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3616 | { | |
3617 | if (steps_taken >= min_steps) | |
3618 | return steps_taken; | |
3619 | } | |
3620 | lateral_steps++; | |
3621 | istack->ninsn = istack_size; | |
3622 | } | |
3623 | ||
3624 | /* It's not going to work -- use the original. */ | |
3625 | istack_push (istack, insn); | |
3626 | return steps_taken; | |
3627 | } | |
3628 | ||
3629 | ||
7fa3d080 BW |
3630 | static void |
3631 | xg_finish_frag (char *last_insn, | |
3632 | enum xtensa_relax_statesE frag_state, | |
3633 | enum xtensa_relax_statesE slot0_state, | |
3634 | int max_growth, | |
3635 | bfd_boolean is_insn) | |
e0001a05 NC |
3636 | { |
3637 | /* Finish off this fragment so that it has at LEAST the desired | |
3638 | max_growth. If it doesn't fit in this fragment, close this one | |
3639 | and start a new one. In either case, return a pointer to the | |
3640 | beginning of the growth area. */ | |
3641 | ||
3642 | fragS *old_frag; | |
43cd72b9 | 3643 | |
542f8b94 | 3644 | frag_grow (max_growth); |
e0001a05 NC |
3645 | old_frag = frag_now; |
3646 | ||
3647 | frag_now->fr_opcode = last_insn; | |
3648 | if (is_insn) | |
3649 | frag_now->tc_frag_data.is_insn = TRUE; | |
3650 | ||
3651 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3652 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3653 | ||
3654 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3655 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3656 | |
3657 | /* Just to make sure that we did not split it up. */ | |
3658 | assert (old_frag->fr_next == frag_now); | |
3659 | } | |
3660 | ||
3661 | ||
7fa3d080 BW |
3662 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3663 | ||
3664 | static bfd_boolean | |
3665 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3666 | { | |
3667 | if (fragP == NULL) | |
3668 | return FALSE; | |
3669 | ||
3670 | for (; fragP; fragP = fragP->fr_next) | |
3671 | { | |
3672 | if (fragP == target) | |
3673 | return TRUE; | |
3674 | if (fragP->fr_fix != 0) | |
3675 | return FALSE; | |
3676 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3677 | return FALSE; | |
3678 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3679 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3680 | return FALSE; | |
3681 | if (fragP->fr_type == rs_space) | |
3682 | return FALSE; | |
3683 | } | |
3684 | return FALSE; | |
3685 | } | |
3686 | ||
3687 | ||
e0001a05 | 3688 | static bfd_boolean |
7fa3d080 | 3689 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3690 | { |
3691 | xtensa_isa isa = xtensa_default_isa; | |
3692 | int i; | |
43cd72b9 | 3693 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3694 | int target_op = -1; |
3695 | symbolS *sym; | |
3696 | fragS *target_frag; | |
3697 | ||
64b607e6 BW |
3698 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3699 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3700 | return FALSE; |
3701 | ||
3702 | for (i = 0; i < num_ops; i++) | |
3703 | { | |
43cd72b9 | 3704 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3705 | { |
3706 | target_op = i; | |
3707 | break; | |
3708 | } | |
3709 | } | |
3710 | if (target_op == -1) | |
3711 | return FALSE; | |
3712 | ||
3713 | if (insn->ntok <= target_op) | |
3714 | return FALSE; | |
3715 | ||
3716 | if (insn->tok[target_op].X_op != O_symbol) | |
3717 | return FALSE; | |
3718 | ||
3719 | sym = insn->tok[target_op].X_add_symbol; | |
3720 | if (sym == NULL) | |
3721 | return FALSE; | |
3722 | ||
3723 | if (insn->tok[target_op].X_add_number != 0) | |
3724 | return FALSE; | |
3725 | ||
3726 | target_frag = symbol_get_frag (sym); | |
3727 | if (target_frag == NULL) | |
3728 | return FALSE; | |
3729 | ||
c138bc38 | 3730 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3731 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3732 | return TRUE; | |
3733 | ||
3734 | return FALSE; | |
3735 | } | |
3736 | ||
3737 | ||
3738 | static void | |
7fa3d080 | 3739 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3740 | { |
3741 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3742 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3743 | |
7fa3d080 BW |
3744 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3745 | { | |
3746 | int i = 1; | |
3747 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3748 | && insn->tok[i].X_op == O_symbol) | |
3749 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3750 | return; | |
3751 | } | |
e0001a05 | 3752 | |
7fa3d080 BW |
3753 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3754 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3755 | { |
7fa3d080 BW |
3756 | int i; |
3757 | ||
3758 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3759 | { | |
3760 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3761 | && insn->tok[i].X_op == O_symbol) | |
3762 | { | |
3763 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3764 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3765 | if (S_IS_DEFINED (sym)) | |
3766 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3767 | } | |
3768 | } | |
e0001a05 | 3769 | } |
e0001a05 NC |
3770 | } |
3771 | ||
3772 | ||
43cd72b9 | 3773 | /* Return FALSE if no error. */ |
e0001a05 | 3774 | |
7fa3d080 BW |
3775 | static bfd_boolean |
3776 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3777 | { |
3778 | int num_ops = 0; | |
3779 | BuildOp *b_op; | |
3780 | ||
3781 | switch (instr_spec->typ) | |
3782 | { | |
3783 | case INSTR_INSTR: | |
3784 | new_insn->insn_type = ITYPE_INSN; | |
3785 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3786 | break; |
3787 | case INSTR_LITERAL_DEF: | |
3788 | new_insn->insn_type = ITYPE_LITERAL; | |
3789 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3790 | break; |
3791 | case INSTR_LABEL_DEF: | |
b224e962 | 3792 | abort (); |
e0001a05 | 3793 | } |
b224e962 BW |
3794 | new_insn->is_specific_opcode = FALSE; |
3795 | new_insn->debug_line = old_insn->debug_line; | |
3796 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3797 | |
3798 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3799 | { | |
3800 | expressionS *exp; | |
3801 | const expressionS *src_exp; | |
3802 | ||
3803 | num_ops++; | |
3804 | switch (b_op->typ) | |
3805 | { | |
3806 | case OP_CONSTANT: | |
3807 | /* The expression must be the constant. */ | |
3808 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3809 | exp = &new_insn->tok[b_op->op_num]; | |
3810 | set_expr_const (exp, b_op->op_data); | |
3811 | break; | |
3812 | ||
3813 | case OP_OPERAND: | |
3814 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3815 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3816 | src_exp = &old_insn->tok[b_op->op_data]; | |
3817 | exp = &new_insn->tok[b_op->op_num]; | |
3818 | copy_expr (exp, src_exp); | |
3819 | break; | |
3820 | ||
3821 | case OP_LITERAL: | |
3822 | case OP_LABEL: | |
3823 | as_bad (_("can't handle generation of literal/labels yet")); | |
3824 | assert (0); | |
3825 | ||
3826 | default: | |
3827 | as_bad (_("can't handle undefined OP TYPE")); | |
3828 | assert (0); | |
3829 | } | |
3830 | } | |
3831 | ||
3832 | new_insn->ntok = num_ops; | |
3833 | return FALSE; | |
3834 | } | |
3835 | ||
3836 | ||
43cd72b9 | 3837 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3838 | |
7fa3d080 BW |
3839 | static bfd_boolean |
3840 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3841 | { |
43cd72b9 | 3842 | TransitionRule *rule; |
e0001a05 | 3843 | BuildInstr *insn_spec; |
43cd72b9 BW |
3844 | |
3845 | if (old_insn->is_specific_opcode || !density_supported) | |
3846 | return FALSE; | |
3847 | ||
3848 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3849 | if (rule == NULL) |
3850 | return FALSE; | |
3851 | ||
3852 | insn_spec = rule->to_instr; | |
3853 | /* There should only be one. */ | |
3854 | assert (insn_spec != NULL); | |
3855 | assert (insn_spec->next == NULL); | |
3856 | if (insn_spec->next != NULL) | |
3857 | return FALSE; | |
3858 | ||
3859 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3860 | ||
3861 | return TRUE; | |
3862 | } | |
3863 | ||
3864 | ||
3865 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3866 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3867 | tokens into the stack or relax it and place multiple |
3868 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3869 | |
3870 | static bfd_boolean | |
7fa3d080 | 3871 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3872 | { |
3873 | int noperands; | |
3874 | TInsn new_insn; | |
7c834684 BW |
3875 | bfd_boolean do_expand; |
3876 | ||
60242db2 | 3877 | tinsn_init (&new_insn); |
e0001a05 | 3878 | |
43cd72b9 BW |
3879 | /* Narrow it if we can. xg_simplify_insn now does all the |
3880 | appropriate checking (e.g., for the density option). */ | |
3881 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3882 | orig_insn = &new_insn; | |
e0001a05 | 3883 | |
43cd72b9 BW |
3884 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3885 | orig_insn->opcode); | |
e0001a05 NC |
3886 | if (orig_insn->ntok < noperands) |
3887 | { | |
3888 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3889 | orig_insn->ntok, | |
3890 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3891 | noperands); | |
3892 | return TRUE; | |
3893 | } | |
3894 | if (orig_insn->ntok > noperands) | |
3895 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3896 | orig_insn->ntok, | |
3897 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3898 | noperands); | |
3899 | ||
43cd72b9 | 3900 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3901 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3902 | orig_insn->ntok = noperands; |
3903 | ||
e0001a05 NC |
3904 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3905 | return TRUE; | |
3906 | ||
d12f9798 BW |
3907 | /* Special case for extui opcode which has constraints not handled |
3908 | by the ordinary operand encoding checks. The number of operands | |
3909 | and related syntax issues have already been checked. */ | |
3910 | if (orig_insn->opcode == xtensa_extui_opcode) | |
3911 | { | |
3912 | int shiftimm = orig_insn->tok[2].X_add_number; | |
3913 | int maskimm = orig_insn->tok[3].X_add_number; | |
3914 | if (shiftimm + maskimm > 32) | |
3915 | { | |
3916 | as_bad (_("immediate operands sum to greater than 32")); | |
3917 | return TRUE; | |
3918 | } | |
3919 | } | |
3920 | ||
7c834684 BW |
3921 | /* If the instruction will definitely need to be relaxed, it is better |
3922 | to expand it now for better scheduling. Decide whether to expand | |
3923 | now.... */ | |
3924 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3925 | ||
3926 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3927 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3928 | adjacent. */ | |
3929 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3930 | do_expand = FALSE; | |
e0001a05 NC |
3931 | |
3932 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3933 | { | |
7c834684 BW |
3934 | /* The values of symbolic operands are not known yet, so only expand |
3935 | now if an operand is "complex" (e.g., difference of symbols) and | |
3936 | will have to be stored as a literal regardless of the value. */ | |
3937 | if (!tinsn_has_complex_operands (orig_insn)) | |
3938 | do_expand = FALSE; | |
e0001a05 | 3939 | } |
7c834684 BW |
3940 | else if (xg_immeds_fit (orig_insn)) |
3941 | do_expand = FALSE; | |
3942 | ||
3943 | if (do_expand) | |
3944 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3945 | else |
7c834684 | 3946 | istack_push (istack, orig_insn); |
e0001a05 | 3947 | |
e0001a05 NC |
3948 | return FALSE; |
3949 | } | |
3950 | ||
3951 | ||
7fa3d080 | 3952 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
3953 | or the name is .gnu.linkonce.*. */ |
3954 | ||
3955 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
3956 | |
3957 | static bfd_boolean | |
3958 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3959 | { | |
3960 | flagword flags, link_once_flags; | |
3961 | ||
3962 | flags = bfd_get_section_flags (abfd, sec); | |
3963 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3964 | ||
3965 | /* Flags might not be set yet. */ | |
74869ac7 BW |
3966 | if (!link_once_flags |
3967 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
3968 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 3969 | |
7fa3d080 BW |
3970 | return (link_once_flags != 0); |
3971 | } | |
3972 | ||
3973 | ||
3974 | static void | |
3975 | xtensa_add_literal_sym (symbolS *sym) | |
3976 | { | |
3977 | sym_list *l; | |
3978 | ||
3979 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3980 | l->sym = sym; | |
3981 | l->next = literal_syms; | |
3982 | literal_syms = l; | |
3983 | } | |
3984 | ||
3985 | ||
3986 | static symbolS * | |
3987 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3988 | { | |
3989 | static int lit_num = 0; | |
3990 | static char name[256]; | |
3991 | symbolS *symbolP; | |
3992 | ||
3993 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3994 | ||
3995 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3996 | be careful to make sure that if it is used in a relocation that the | |
3997 | symbol will be in the output file. */ | |
3998 | if (get_is_linkonce_section (stdoutput, sec)) | |
3999 | { | |
4000 | symbolP = symbol_new (name, sec, 0, frag); | |
4001 | S_CLEAR_EXTERNAL (symbolP); | |
4002 | /* symbolP->local = 1; */ | |
4003 | } | |
4004 | else | |
4005 | symbolP = symbol_new (name, sec, 0, frag); | |
4006 | ||
4007 | xtensa_add_literal_sym (symbolP); | |
4008 | ||
7fa3d080 BW |
4009 | lit_num++; |
4010 | return symbolP; | |
4011 | } | |
4012 | ||
4013 | ||
e0001a05 NC |
4014 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4015 | ||
7fa3d080 BW |
4016 | static symbolS * |
4017 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4018 | { |
4019 | emit_state state; | |
4020 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4021 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4022 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4023 | char *p; |
e0001a05 NC |
4024 | |
4025 | /* size = 4 for L32R. It could easily be larger when we move to | |
4026 | larger constants. Add a parameter later. */ | |
4027 | offsetT litsize = 4; | |
4028 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4029 | expressionS saved_loc; | |
43cd72b9 BW |
4030 | expressionS * emit_val; |
4031 | ||
e0001a05 NC |
4032 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4033 | ||
4034 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4035 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4036 | |
4037 | xtensa_switch_to_literal_fragment (&state); | |
4038 | ||
43cd72b9 BW |
4039 | emit_val = &insn->tok[0]; |
4040 | if (emit_val->X_op == O_big) | |
4041 | { | |
4042 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4043 | if (size > litsize) | |
4044 | { | |
4045 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4046 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4047 | _("invalid immediate")); |
4048 | xtensa_restore_emit_state (&state); | |
4049 | return NULL; | |
4050 | } | |
4051 | } | |
4052 | ||
e0001a05 NC |
4053 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4054 | literals done with this function have a frag to themselves. That's | |
4055 | important for the way text section literals work. */ | |
4056 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4057 | record_alignment (now_seg, litalign); |
e0001a05 | 4058 | |
bbdd25a8 | 4059 | switch (emit_val->X_op) |
43cd72b9 | 4060 | { |
1bbb5f21 BW |
4061 | case O_pcrel: |
4062 | pcrel = TRUE; | |
4063 | /* fall through */ | |
bbdd25a8 BW |
4064 | case O_pltrel: |
4065 | p = frag_more (litsize); | |
43cd72b9 | 4066 | xtensa_set_frag_assembly_state (frag_now); |
bbdd25a8 | 4067 | reloc = map_operator_to_reloc (emit_val->X_op); |
43cd72b9 BW |
4068 | if (emit_val->X_add_symbol) |
4069 | emit_val->X_op = O_symbol; | |
4070 | else | |
4071 | emit_val->X_op = O_constant; | |
4072 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4073 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4074 | break; |
4075 | ||
4076 | default: | |
4077 | emit_expr (emit_val, litsize); | |
4078 | break; | |
43cd72b9 | 4079 | } |
e0001a05 NC |
4080 | |
4081 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4082 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4083 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4084 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4085 | |
4086 | /* Go back. */ | |
4087 | xtensa_restore_emit_state (&state); | |
4088 | return lit_sym; | |
4089 | } | |
4090 | ||
4091 | ||
4092 | static void | |
7fa3d080 | 4093 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4094 | { |
4095 | emit_state state; | |
43cd72b9 | 4096 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4097 | takes effect if something is placed here. */ |
4098 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4099 | fragS *lit_saved_frag; | |
4100 | ||
e0001a05 | 4101 | assert (size % 4 == 0); |
e0001a05 NC |
4102 | |
4103 | xtensa_switch_to_literal_fragment (&state); | |
4104 | ||
4105 | /* Force a 4-byte align here. */ | |
4106 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4107 | record_alignment (now_seg, litalign); |
e0001a05 | 4108 | |
542f8b94 | 4109 | frag_grow (size); |
e0001a05 NC |
4110 | |
4111 | lit_saved_frag = frag_now; | |
4112 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4113 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4114 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4115 | |
4116 | /* Go back. */ | |
4117 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4118 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4119 | } |
4120 | ||
4121 | ||
e0001a05 | 4122 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4123 | Return TRUE on success. */ |
e0001a05 | 4124 | |
7fa3d080 BW |
4125 | static bfd_boolean |
4126 | xg_add_opcode_fix (TInsn *tinsn, | |
4127 | int opnum, | |
4128 | xtensa_format fmt, | |
4129 | int slot, | |
4130 | expressionS *expr, | |
4131 | fragS *fragP, | |
4132 | offsetT offset) | |
43cd72b9 BW |
4133 | { |
4134 | xtensa_opcode opcode = tinsn->opcode; | |
4135 | bfd_reloc_code_real_type reloc; | |
4136 | reloc_howto_type *howto; | |
4137 | int fmt_length; | |
e0001a05 NC |
4138 | fixS *the_fix; |
4139 | ||
43cd72b9 BW |
4140 | reloc = BFD_RELOC_NONE; |
4141 | ||
4142 | /* First try the special cases for "alternate" relocs. */ | |
4143 | if (opcode == xtensa_l32r_opcode) | |
4144 | { | |
4145 | if (fragP->tc_frag_data.use_absolute_literals) | |
4146 | reloc = encode_alt_reloc (slot); | |
4147 | } | |
4148 | else if (opcode == xtensa_const16_opcode) | |
4149 | { | |
4150 | if (expr->X_op == O_lo16) | |
4151 | { | |
4152 | reloc = encode_reloc (slot); | |
4153 | expr->X_op = O_symbol; | |
4154 | } | |
4155 | else if (expr->X_op == O_hi16) | |
4156 | { | |
4157 | reloc = encode_alt_reloc (slot); | |
4158 | expr->X_op = O_symbol; | |
4159 | } | |
4160 | } | |
4161 | ||
4162 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4163 | { |
43cd72b9 | 4164 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4165 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4166 | return FALSE; |
4167 | } | |
4168 | ||
43cd72b9 BW |
4169 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4170 | into the symbol table where the generic portions of the assembler | |
4171 | won't know what to do with them. */ | |
4172 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4173 | { | |
4174 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4175 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4176 | return FALSE; |
4177 | } | |
4178 | ||
4179 | /* Next try the generic relocs. */ | |
4180 | if (reloc == BFD_RELOC_NONE) | |
4181 | reloc = encode_reloc (slot); | |
4182 | if (reloc == BFD_RELOC_NONE) | |
4183 | { | |
4184 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4185 | return FALSE; | |
4186 | } | |
e0001a05 | 4187 | |
43cd72b9 | 4188 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4189 | if (!howto) |
4190 | { | |
43cd72b9 | 4191 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4192 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4193 | return FALSE; | |
4194 | } | |
4195 | ||
43cd72b9 BW |
4196 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4197 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4198 | howto->pc_relative, reloc); |
d9740523 | 4199 | the_fix->fx_no_overflow = 1; |
7fa3d080 BW |
4200 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; |
4201 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4202 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4203 | |
7fa3d080 BW |
4204 | return TRUE; |
4205 | } | |
4206 | ||
4207 | ||
4208 | static bfd_boolean | |
4209 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4210 | char *buf, |
4211 | fragS *fragP, | |
4212 | offsetT offset, | |
4213 | bfd_boolean build_fix) | |
4214 | { | |
4215 | static xtensa_insnbuf insnbuf = NULL; | |
4216 | bfd_boolean has_symbolic_immed = FALSE; | |
4217 | bfd_boolean ok = TRUE; | |
b2d179be | 4218 | |
7fa3d080 BW |
4219 | if (!insnbuf) |
4220 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4221 | ||
4222 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4223 | if (has_symbolic_immed && build_fix) | |
4224 | { | |
4225 | /* Add a fixup. */ | |
b2d179be BW |
4226 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4227 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4228 | int opnum = get_relaxable_immed (tinsn->opcode); |
4229 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4230 | |
b2d179be | 4231 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4232 | ok = FALSE; |
4233 | } | |
4234 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4235 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4236 | (unsigned char *) buf, 0); | |
7fa3d080 | 4237 | return ok; |
e0001a05 NC |
4238 | } |
4239 | ||
4240 | ||
7fa3d080 BW |
4241 | static void |
4242 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4243 | { |
4244 | symbolS *sym = get_special_literal_symbol (); | |
4245 | int i; | |
4246 | if (lit_sym == 0) | |
4247 | return; | |
4248 | assert (insn->insn_type == ITYPE_INSN); | |
4249 | for (i = 0; i < insn->ntok; i++) | |
4250 | if (insn->tok[i].X_add_symbol == sym) | |
4251 | insn->tok[i].X_add_symbol = lit_sym; | |
4252 | ||
4253 | } | |
4254 | ||
4255 | ||
7fa3d080 BW |
4256 | static void |
4257 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4258 | { |
4259 | symbolS *sym = get_special_label_symbol (); | |
4260 | int i; | |
e0001a05 NC |
4261 | for (i = 0; i < insn->ntok; i++) |
4262 | if (insn->tok[i].X_add_symbol == sym) | |
4263 | insn->tok[i].X_add_symbol = label_sym; | |
4264 | ||
4265 | } | |
4266 | ||
4267 | ||
43cd72b9 | 4268 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4269 | integer register. */ |
4270 | ||
4271 | static bfd_boolean | |
7fa3d080 | 4272 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4273 | { |
4274 | int i; | |
4275 | int num_ops; | |
4276 | xtensa_isa isa = xtensa_default_isa; | |
4277 | ||
43cd72b9 | 4278 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4279 | |
4280 | for (i = 0; i < num_ops; i++) | |
4281 | { | |
43cd72b9 BW |
4282 | char inout; |
4283 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4284 | if ((inout == 'o' || inout == 'm') | |
4285 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4286 | { |
43cd72b9 BW |
4287 | xtensa_regfile opnd_rf = |
4288 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4289 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4290 | { |
4291 | if ((insn->tok[i].X_op == O_register) | |
4292 | && (insn->tok[i].X_add_number == regnum)) | |
4293 | return TRUE; | |
4294 | } | |
4295 | } | |
4296 | } | |
4297 | return FALSE; | |
4298 | } | |
4299 | ||
4300 | ||
4301 | static bfd_boolean | |
7fa3d080 | 4302 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4303 | { |
4304 | xtensa_opcode opcode = tinsn->opcode; | |
4305 | ||
4306 | if (opcode == XTENSA_UNDEFINED) | |
4307 | return FALSE; | |
4308 | ||
4309 | if (opcode == xtensa_call0_opcode | |
4310 | || opcode == xtensa_callx0_opcode | |
4311 | || opcode == xtensa_call4_opcode | |
4312 | || opcode == xtensa_callx4_opcode | |
4313 | || opcode == xtensa_call8_opcode | |
4314 | || opcode == xtensa_callx8_opcode | |
4315 | || opcode == xtensa_call12_opcode | |
4316 | || opcode == xtensa_callx12_opcode | |
4317 | || opcode == xtensa_isync_opcode | |
4318 | || opcode == xtensa_ret_opcode | |
4319 | || opcode == xtensa_ret_n_opcode | |
4320 | || opcode == xtensa_retw_opcode | |
4321 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4322 | || opcode == xtensa_waiti_opcode |
4323 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4324 | return TRUE; |
c138bc38 | 4325 | |
e0001a05 NC |
4326 | return FALSE; |
4327 | } | |
4328 | ||
4329 | ||
4330 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4331 | This allows the debugger to add unaligned labels. | |
4332 | Also, the assembler generates stabs labels that need | |
4333 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4334 | ||
7fa3d080 BW |
4335 | static bfd_boolean |
4336 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4337 | { |
4338 | const char *name = S_GET_NAME (sym); | |
4339 | static size_t fake_size = 0; | |
4340 | ||
4341 | if (name | |
4342 | && name[0] == '.' | |
4343 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4344 | return TRUE; | |
4345 | ||
4346 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4347 | if (fake_size == 0) | |
4348 | fake_size = strlen (FAKE_LABEL_NAME); | |
4349 | ||
43cd72b9 | 4350 | if (name |
e0001a05 NC |
4351 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4352 | && (name[fake_size] == 'F' | |
4353 | || name[fake_size] == 'L' | |
4354 | || (name[fake_size] == 'e' | |
4355 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4356 | return TRUE; | |
4357 | ||
4358 | return FALSE; | |
4359 | } | |
4360 | ||
4361 | ||
7fa3d080 BW |
4362 | static fragS * |
4363 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4364 | { |
4365 | fragS *next_fragP = fragP->fr_next; | |
4366 | ||
c138bc38 | 4367 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4368 | So we have to skip until we find something legit. */ |
4369 | while (next_fragP && next_fragP->fr_fix == 0) | |
4370 | next_fragP = next_fragP->fr_next; | |
4371 | ||
4372 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4373 | return NULL; | |
4374 | ||
4375 | return next_fragP; | |
4376 | } | |
4377 | ||
4378 | ||
43cd72b9 | 4379 | static bfd_boolean |
7fa3d080 | 4380 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4381 | { |
4382 | xtensa_opcode out_opcode; | |
4383 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4384 | ||
4385 | if (next_fragP == NULL) | |
4386 | return FALSE; | |
4387 | ||
4388 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4389 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4390 | { | |
4391 | *opcode = out_opcode; | |
4392 | return TRUE; | |
4393 | } | |
4394 | return FALSE; | |
4395 | } | |
4396 | ||
4397 | ||
4398 | static int | |
7fa3d080 | 4399 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4400 | { |
e0001a05 NC |
4401 | static xtensa_insnbuf insnbuf = NULL; |
4402 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4403 | xtensa_format fmt; |
c138bc38 | 4404 | int fmt_size; |
e0001a05 NC |
4405 | |
4406 | if (!insnbuf) | |
4407 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4408 | ||
43cd72b9 BW |
4409 | if (fragP == NULL) |
4410 | return XTENSA_UNDEFINED; | |
4411 | ||
d77b99c9 BW |
4412 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4413 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4414 | |
4415 | fmt = xtensa_format_decode (isa, insnbuf); | |
4416 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4417 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4418 | fmt_size = xtensa_format_length (isa, fmt); |
4419 | ||
4420 | /* If the next format won't be changing due to relaxation, just | |
4421 | return the length of the first format. */ | |
4422 | if (fragP->fr_opcode != fragP->fr_literal) | |
4423 | return fmt_size; | |
4424 | ||
c138bc38 | 4425 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4426 | multi-slot instruction, we will return the more conservative |
4427 | number. This works because alignment on bigger instructions | |
4428 | is more restrictive than alignment on smaller instructions. | |
4429 | This is more conservative than we would like, but it happens | |
4430 | infrequently. */ | |
4431 | ||
4432 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4433 | return fmt_size; | |
4434 | ||
4435 | /* If we aren't doing one of our own relaxations or it isn't | |
4436 | slot-based, then the insn size won't change. */ | |
4437 | if (fragP->fr_type != rs_machine_dependent) | |
4438 | return fmt_size; | |
4439 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4440 | return fmt_size; | |
4441 | ||
4442 | /* If an instruction is about to grow, return the longer size. */ | |
4443 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4444 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4445 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4446 | { |
4447 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4448 | instruction in the relaxed version is of length 3. (The case | |
4449 | where we have to pull the instruction out of a FLIX bundle | |
4450 | is handled conservatively above.) However, frags with opcodes | |
4451 | that are expanding to wide branches end up having formats that | |
4452 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4453 | we can't tell directly what format the relaxer picked. This | |
4454 | is a wart in the design of the relaxer that should someday be | |
4455 | fixed, but would require major changes, or at least should | |
4456 | be accompanied by major changes to make use of that data. | |
4457 | ||
4458 | In any event, we can tell that we are expanding from a single-slot | |
4459 | three-byte format to a wider one with the logic below. */ | |
4460 | ||
4461 | if (fmt_size <= 3 && fragP->tc_frag_data.text_expansion[0] != 3) | |
4462 | return 3 + fragP->tc_frag_data.text_expansion[0]; | |
4463 | else | |
4464 | return 3; | |
4465 | } | |
c138bc38 | 4466 | |
43cd72b9 BW |
4467 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4468 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4469 | |
43cd72b9 | 4470 | return fmt_size; |
e0001a05 NC |
4471 | } |
4472 | ||
4473 | ||
7fa3d080 BW |
4474 | static int |
4475 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4476 | { |
7fa3d080 BW |
4477 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4478 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4479 | } |
4480 | ||
4481 | ||
03aaa593 BW |
4482 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4483 | required two-byte instructions to be treated as three-byte instructions | |
4484 | for loop instruction alignment. This restriction was removed beginning | |
4485 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4486 | is that the first instruction of the loop must appear at an address that | |
4487 | does not cross a fetch boundary. */ | |
4488 | ||
4489 | static int | |
4490 | get_loop_align_size (int insn_size) | |
4491 | { | |
4492 | if (insn_size == XTENSA_UNDEFINED) | |
4493 | return xtensa_fetch_width; | |
4494 | ||
4495 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4496 | return 3; | |
4497 | ||
4498 | return insn_size; | |
4499 | } | |
4500 | ||
4501 | ||
e0001a05 NC |
4502 | /* If the next legit fragment is an end-of-loop marker, |
4503 | switch its state so it will instantiate a NOP. */ | |
4504 | ||
4505 | static void | |
1d19a770 | 4506 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4507 | { |
4508 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4509 | fragS *new_target = NULL; |
e0001a05 | 4510 | |
7b1cc377 | 4511 | if (align_targets) |
43cd72b9 BW |
4512 | { |
4513 | /* We are guaranteed there will be one of these... */ | |
4514 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4515 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4516 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4517 | next_fragP = next_fragP->fr_next; | |
4518 | ||
4519 | assert (next_fragP->fr_type == rs_machine_dependent | |
4520 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4521 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4522 | ||
4523 | /* ...and one of these. */ | |
4524 | new_target = next_fragP->fr_next; | |
4525 | while (!(new_target->fr_type == rs_machine_dependent | |
4526 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4527 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4528 | new_target = new_target->fr_next; | |
4529 | ||
4530 | assert (new_target->fr_type == rs_machine_dependent | |
4531 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4532 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4533 | } | |
43cd72b9 | 4534 | |
1d19a770 | 4535 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4536 | { |
1d19a770 BW |
4537 | if (next_fragP->fr_type == rs_machine_dependent |
4538 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4539 | { |
1d19a770 BW |
4540 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4541 | return; | |
e0001a05 | 4542 | } |
1d19a770 BW |
4543 | |
4544 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4545 | } |
4546 | } | |
4547 | ||
4548 | ||
4549 | static bfd_boolean | |
7fa3d080 | 4550 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4551 | { |
43cd72b9 | 4552 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4553 | so we have to skip until we find something legit. */ |
4554 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4555 | { | |
4556 | if (fragP->tc_frag_data.is_branch_target) | |
4557 | return TRUE; | |
4558 | if (fragP->fr_fix != 0) | |
4559 | break; | |
4560 | } | |
4561 | return FALSE; | |
4562 | } | |
4563 | ||
4564 | ||
4565 | static bfd_boolean | |
7fa3d080 | 4566 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4567 | { |
c138bc38 | 4568 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4569 | So we have to skip until we find something legit. */ |
4570 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4571 | { | |
4572 | if (fragP->tc_frag_data.is_loop_target) | |
4573 | return TRUE; | |
4574 | if (fragP->fr_fix != 0) | |
4575 | break; | |
4576 | } | |
4577 | return FALSE; | |
4578 | } | |
4579 | ||
4580 | ||
4581 | static addressT | |
7fa3d080 | 4582 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4583 | { |
4584 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4585 | xtensa_opcode next_opcode; |
e0001a05 | 4586 | |
43cd72b9 | 4587 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4588 | return 0; |
4589 | ||
43cd72b9 BW |
4590 | /* Sometimes an empty will end up here due to storage allocation issues, |
4591 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4592 | while (next_fragp->fr_fix == 0) |
4593 | next_fragp = next_fragp->fr_next; | |
4594 | ||
4595 | if (next_fragp->fr_type != rs_machine_dependent) | |
4596 | return 0; | |
4597 | ||
4598 | /* There is some implicit knowledge encoded in here. | |
4599 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4600 | been relaxed. Note that we can assume that the LOOP |
4601 | instruction is in slot 0 because loops aren't bundleable. */ | |
4602 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4603 | return get_expanded_loop_offset (next_opcode); |
4604 | ||
4605 | return 0; | |
4606 | } | |
4607 | ||
4608 | ||
4609 | /* Mark a location where we can later insert literal frags. Update | |
4610 | the section's literal_pool_loc, so subsequent literals can be | |
4611 | placed nearest to their use. */ | |
4612 | ||
4613 | static void | |
7fa3d080 | 4614 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4615 | { |
4616 | /* Any labels pointing to the current location need | |
4617 | to be adjusted to after the literal pool. */ | |
4618 | emit_state s; | |
e0001a05 | 4619 | fragS *pool_location; |
e0001a05 | 4620 | |
1f2a7e38 | 4621 | if (use_literal_section) |
43cd72b9 BW |
4622 | return; |
4623 | ||
dd49a749 BW |
4624 | /* We stash info in these frags so we can later move the literal's |
4625 | fixes into this frchain's fix list. */ | |
e0001a05 | 4626 | pool_location = frag_now; |
dd49a749 | 4627 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4628 | frag_now->tc_frag_data.literal_frag = frag_now; |
dd49a749 | 4629 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4630 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4631 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4632 | frag_now->tc_frag_data.lit_seg = now_seg; |
4633 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4634 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4635 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4636 | |
4637 | /* Now put a frag into the literal pool that points to this location. */ | |
4638 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4639 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4640 | frag_align (2, 0, 0); | |
4641 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4642 | |
4643 | /* Close whatever frag is there. */ | |
4644 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4645 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4646 | frag_now->tc_frag_data.literal_frag = pool_location; |
4647 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4648 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4649 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4650 | } |
4651 | ||
4652 | ||
43cd72b9 BW |
4653 | /* Build a nop of the correct size into tinsn. */ |
4654 | ||
4655 | static void | |
7fa3d080 | 4656 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4657 | { |
4658 | tinsn_init (tinsn); | |
4659 | switch (size) | |
4660 | { | |
4661 | case 2: | |
4662 | tinsn->opcode = xtensa_nop_n_opcode; | |
4663 | tinsn->ntok = 0; | |
4664 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4665 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4666 | break; | |
4667 | ||
4668 | case 3: | |
4669 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4670 | { | |
4671 | tinsn->opcode = xtensa_or_opcode; | |
4672 | set_expr_const (&tinsn->tok[0], 1); | |
4673 | set_expr_const (&tinsn->tok[1], 1); | |
4674 | set_expr_const (&tinsn->tok[2], 1); | |
4675 | tinsn->ntok = 3; | |
4676 | } | |
4677 | else | |
4678 | tinsn->opcode = xtensa_nop_opcode; | |
4679 | ||
4680 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4681 | } | |
4682 | } | |
4683 | ||
4684 | ||
e0001a05 NC |
4685 | /* Assemble a NOP of the requested size in the buffer. User must have |
4686 | allocated "buf" with at least "size" bytes. */ | |
4687 | ||
7fa3d080 | 4688 | static void |
d77b99c9 | 4689 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4690 | { |
4691 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4692 | TInsn tinsn; |
e0001a05 | 4693 | |
43cd72b9 | 4694 | build_nop (&tinsn, size); |
e0001a05 | 4695 | |
43cd72b9 BW |
4696 | if (!insnbuf) |
4697 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4698 | |
43cd72b9 | 4699 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4700 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4701 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4702 | } |
4703 | ||
4704 | ||
4705 | /* Return the number of bytes for the offset of the expanded loop | |
4706 | instruction. This should be incorporated into the relaxation | |
4707 | specification but is hard-coded here. This is used to auto-align | |
4708 | the loop instruction. It is invalid to call this function if the | |
4709 | configuration does not have loops or if the opcode is not a loop | |
4710 | opcode. */ | |
4711 | ||
4712 | static addressT | |
7fa3d080 | 4713 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4714 | { |
4715 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4716 | This MUST correspond directly to the specification of the loop | |
4717 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4718 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4719 | if (opcode == xtensa_loop_opcode) |
4720 | return 0; | |
4721 | if (opcode == xtensa_loopnez_opcode) | |
4722 | return 3; | |
4723 | if (opcode == xtensa_loopgtz_opcode) | |
4724 | return 6; | |
4725 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4726 | return 0; | |
4727 | } | |
4728 | ||
4729 | ||
7fa3d080 BW |
4730 | static fragS * |
4731 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4732 | { |
4733 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4734 | } | |
4735 | ||
4736 | ||
4737 | static void | |
7fa3d080 | 4738 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4739 | { |
4740 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4741 | } | |
4742 | ||
43cd72b9 BW |
4743 | |
4744 | /* Set frag assembly state should be called when a new frag is | |
4745 | opened and after a frag has been closed. */ | |
4746 | ||
7fa3d080 BW |
4747 | static void |
4748 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4749 | { |
4750 | if (!density_supported) | |
4751 | fragP->tc_frag_data.is_no_density = TRUE; | |
4752 | ||
4753 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4754 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4755 | "use_schedule" here. */ |
4756 | if (!directive_state[directive_transform]) | |
4757 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4758 | if (directive_state[directive_longcalls]) |
4759 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4760 | fragP->tc_frag_data.use_absolute_literals = |
4761 | directive_state[directive_absolute_literals]; | |
4762 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4763 | } | |
4764 | ||
4765 | ||
7fa3d080 BW |
4766 | static bfd_boolean |
4767 | relaxable_section (asection *sec) | |
43cd72b9 | 4768 | { |
11ac2671 BW |
4769 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4770 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4771 | } |
4772 | ||
4773 | ||
99ded152 BW |
4774 | static void |
4775 | xtensa_mark_frags_for_org (void) | |
4776 | { | |
4777 | segT *seclist; | |
4778 | ||
4779 | /* Walk over each fragment of all of the current segments. If we find | |
4780 | a .org frag in any of the segments, mark all frags prior to it as | |
4781 | "no transform", which will prevent linker optimizations from messing | |
4782 | up the .org distance. This should be done after | |
4783 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4784 | about that function trashing the data we save here. */ | |
4785 | ||
4786 | for (seclist = &stdoutput->sections; | |
4787 | seclist && *seclist; | |
4788 | seclist = &(*seclist)->next) | |
4789 | { | |
4790 | segT sec = *seclist; | |
4791 | segment_info_type *seginfo; | |
4792 | fragS *fragP; | |
4793 | flagword flags; | |
4794 | flags = bfd_get_section_flags (stdoutput, sec); | |
4795 | if (flags & SEC_DEBUGGING) | |
4796 | continue; | |
4797 | if (!(flags & SEC_ALLOC)) | |
4798 | continue; | |
4799 | ||
4800 | seginfo = seg_info (sec); | |
4801 | if (seginfo && seginfo->frchainP) | |
4802 | { | |
4803 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4804 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4805 | fragP = fragP->fr_next) | |
4806 | { | |
4807 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4808 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4809 | if (fragP->fr_subtype == RELAX_ORG) | |
4810 | { | |
4811 | while (last_fragP != fragP->fr_next) | |
4812 | { | |
4813 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4814 | last_fragP = last_fragP->fr_next; | |
4815 | } | |
4816 | } | |
4817 | } | |
4818 | } | |
4819 | } | |
4820 | } | |
4821 | ||
4822 | ||
43cd72b9 | 4823 | static void |
7fa3d080 | 4824 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4825 | { |
4826 | segT *seclist; | |
4827 | ||
4828 | /* Walk over each fragment of all of the current segments. For each | |
4829 | unmarked fragment, mark it with the same info as the previous | |
4830 | fragment. */ | |
4831 | for (seclist = &stdoutput->sections; | |
4832 | seclist && *seclist; | |
4833 | seclist = &(*seclist)->next) | |
4834 | { | |
4835 | segT sec = *seclist; | |
4836 | segment_info_type *seginfo; | |
4837 | fragS *fragP; | |
4838 | flagword flags; | |
4839 | flags = bfd_get_section_flags (stdoutput, sec); | |
4840 | if (flags & SEC_DEBUGGING) | |
4841 | continue; | |
4842 | if (!(flags & SEC_ALLOC)) | |
4843 | continue; | |
4844 | ||
4845 | seginfo = seg_info (sec); | |
4846 | if (seginfo && seginfo->frchainP) | |
4847 | { | |
4848 | fragS *last_fragP = 0; | |
4849 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4850 | fragP = fragP->fr_next) | |
4851 | { | |
4852 | if (fragP->fr_fix != 0 | |
4853 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4854 | { | |
4855 | if (last_fragP == 0) | |
4856 | { | |
4857 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4858 | _("assembly state not set for first frag in section %s"), | |
4859 | sec->name); | |
4860 | } | |
4861 | else | |
4862 | { | |
4863 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4864 | fragP->tc_frag_data.is_no_density = | |
4865 | last_fragP->tc_frag_data.is_no_density; | |
4866 | fragP->tc_frag_data.is_no_transform = | |
4867 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4868 | fragP->tc_frag_data.use_longcalls = |
4869 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4870 | fragP->tc_frag_data.use_absolute_literals = |
4871 | last_fragP->tc_frag_data.use_absolute_literals; | |
4872 | } | |
4873 | } | |
4874 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4875 | last_fragP = fragP; | |
4876 | } | |
4877 | } | |
4878 | } | |
4879 | } | |
4880 | ||
4881 | ||
4882 | static void | |
7fa3d080 BW |
4883 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4884 | asection *sec, | |
4885 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4886 | { |
4887 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4888 | segment_info_type *seginfo = seg_info (sec); | |
4889 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4890 | |
43cd72b9 | 4891 | if (flags & SEC_CODE) |
c138bc38 | 4892 | { |
43cd72b9 BW |
4893 | xtensa_isa isa = xtensa_default_isa; |
4894 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4895 | while (frag != NULL) | |
4896 | { | |
4897 | if (frag->tc_frag_data.is_branch_target) | |
4898 | { | |
4899 | int op_size; | |
664df4e4 | 4900 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4901 | xtensa_format fmt; |
4902 | ||
d77b99c9 BW |
4903 | xtensa_insnbuf_from_chars |
4904 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4905 | fmt = xtensa_format_decode (isa, insnbuf); |
4906 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4907 | branch_align = 1 << branch_align_power (sec); |
4908 | frag_addr = frag->fr_address % branch_align; | |
4909 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4910 | as_warn_where (frag->fr_file, frag->fr_line, |
4911 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4912 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4913 | } |
4914 | frag = frag->fr_next; | |
4915 | } | |
4916 | xtensa_insnbuf_free (isa, insnbuf); | |
4917 | } | |
4918 | } | |
4919 | ||
4920 | ||
4921 | static void | |
7fa3d080 BW |
4922 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4923 | asection *sec, | |
4924 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4925 | { |
4926 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4927 | segment_info_type *seginfo = seg_info (sec); | |
4928 | fragS *frag = seginfo->frchainP->frch_root; | |
4929 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4930 | |
43cd72b9 | 4931 | if (flags & SEC_CODE) |
c138bc38 | 4932 | { |
43cd72b9 BW |
4933 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4934 | while (frag != NULL) | |
4935 | { | |
4936 | if (frag->tc_frag_data.is_first_loop_insn) | |
4937 | { | |
4938 | int op_size; | |
d77b99c9 | 4939 | addressT frag_addr; |
43cd72b9 BW |
4940 | xtensa_format fmt; |
4941 | ||
d77b99c9 BW |
4942 | xtensa_insnbuf_from_chars |
4943 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4944 | fmt = xtensa_format_decode (isa, insnbuf); |
4945 | op_size = xtensa_format_length (isa, fmt); | |
4946 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4947 | ||
d77b99c9 | 4948 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4949 | as_warn_where (frag->fr_file, frag->fr_line, |
4950 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4951 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4952 | } |
4953 | frag = frag->fr_next; | |
4954 | } | |
4955 | xtensa_insnbuf_free (isa, insnbuf); | |
4956 | } | |
4957 | } | |
4958 | ||
4959 | ||
30f725a1 BW |
4960 | static int |
4961 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4962 | { |
4963 | xtensa_isa isa = xtensa_default_isa; | |
4964 | static xtensa_insnbuf insnbuf = NULL; | |
4965 | static xtensa_insnbuf slotbuf = NULL; | |
4966 | xtensa_format fmt; | |
4967 | int slot; | |
4968 | bfd_boolean alt_reloc; | |
4969 | xtensa_opcode opcode; | |
4970 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4971 | ||
4972 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4973 | if (alt_reloc) | |
4974 | as_fatal (_("unexpected fix")); | |
4975 | ||
4976 | if (!insnbuf) | |
4977 | { | |
4978 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4979 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4980 | } | |
4981 | ||
d77b99c9 | 4982 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4983 | fmt = xtensa_format_decode (isa, insnbuf); |
4984 | if (fmt == XTENSA_UNDEFINED) | |
4985 | as_fatal (_("undecodable fix")); | |
4986 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4987 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4988 | if (opcode == XTENSA_UNDEFINED) | |
4989 | as_fatal (_("undecodable fix")); | |
4990 | ||
4991 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4992 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4993 | of a CONST16 operand. */ |
43cd72b9 | 4994 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4995 | return 0; |
43cd72b9 BW |
4996 | |
4997 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4998 | get_relaxable_immed (opcode), val, | |
4999 | fixP->fx_file, fixP->fx_line); | |
5000 | ||
5001 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5002 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5003 | |
5004 | return 1; | |
43cd72b9 BW |
5005 | } |
5006 | ||
e0001a05 NC |
5007 | \f |
5008 | /* External Functions and Other GAS Hooks. */ | |
5009 | ||
5010 | const char * | |
7fa3d080 | 5011 | xtensa_target_format (void) |
e0001a05 NC |
5012 | { |
5013 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5014 | } | |
5015 | ||
5016 | ||
5017 | void | |
7fa3d080 | 5018 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5019 | { |
5020 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5021 | } | |
5022 | ||
5023 | ||
5024 | void | |
7fa3d080 | 5025 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5026 | { |
5027 | if (target_big_endian) | |
5028 | number_to_chars_bigendian (buf, val, n); | |
5029 | else | |
5030 | number_to_chars_littleendian (buf, val, n); | |
5031 | } | |
5032 | ||
5033 | ||
5034 | /* This function is called once, at assembler startup time. It should | |
5035 | set up all the tables, etc. that the MD part of the assembler will | |
5036 | need. */ | |
5037 | ||
5038 | void | |
7fa3d080 | 5039 | md_begin (void) |
e0001a05 NC |
5040 | { |
5041 | segT current_section = now_seg; | |
5042 | int current_subsec = now_subseg; | |
5043 | xtensa_isa isa; | |
5044 | ||
43cd72b9 | 5045 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5046 | isa = xtensa_default_isa; |
e0001a05 | 5047 | |
43cd72b9 BW |
5048 | linkrelax = 1; |
5049 | ||
74869ac7 | 5050 | /* Set up the literal sections. */ |
e0001a05 | 5051 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5052 | |
5053 | subseg_set (current_section, current_subsec); | |
5054 | ||
43cd72b9 BW |
5055 | xg_init_vinsn (&cur_vinsn); |
5056 | ||
e0001a05 NC |
5057 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
5058 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5059 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5060 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5061 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5062 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5063 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5064 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5065 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5066 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5067 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5068 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5069 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5070 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5071 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5072 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 5073 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5074 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5075 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5076 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5077 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5078 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5079 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5080 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5081 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5082 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5083 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5084 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5085 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5086 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5087 | |
77cba8a3 BW |
5088 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5089 | ||
43cd72b9 BW |
5090 | init_op_placement_info_table (); |
5091 | ||
5092 | /* Set up the assembly state. */ | |
5093 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5094 | xtensa_set_frag_assembly_state (frag_now); | |
5095 | } | |
5096 | ||
5097 | ||
5098 | /* TC_INIT_FIX_DATA hook */ | |
5099 | ||
5100 | void | |
7fa3d080 | 5101 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5102 | { |
5103 | x->tc_fix_data.slot = 0; | |
5104 | x->tc_fix_data.X_add_symbol = NULL; | |
5105 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5106 | } |
5107 | ||
5108 | ||
5109 | /* tc_frob_label hook */ | |
5110 | ||
5111 | void | |
7fa3d080 | 5112 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5113 | { |
3ea38ac2 BW |
5114 | float freq; |
5115 | ||
5116 | if (cur_vinsn.inside_bundle) | |
5117 | { | |
5118 | as_bad (_("labels are not valid inside bundles")); | |
5119 | return; | |
5120 | } | |
5121 | ||
5122 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5123 | |
43cd72b9 BW |
5124 | /* Since the label was already attached to a frag associated with the |
5125 | previous basic block, it now needs to be reset to the current frag. */ | |
5126 | symbol_set_frag (sym, frag_now); | |
5127 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5128 | ||
82e7541d BW |
5129 | if (generating_literals) |
5130 | xtensa_add_literal_sym (sym); | |
5131 | else | |
5132 | xtensa_add_insn_label (sym); | |
5133 | ||
7b1cc377 BW |
5134 | if (symbol_get_tc (sym)->is_loop_target) |
5135 | { | |
5136 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5137 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5138 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5139 | ||
5140 | xtensa_set_frag_assembly_state (frag_now); | |
5141 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5142 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5143 | ||
5144 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5145 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5146 | } |
e0001a05 NC |
5147 | |
5148 | /* No target aligning in the absolute section. */ | |
61846f28 | 5149 | if (now_seg != absolute_section |
43cd72b9 | 5150 | && do_align_targets () |
61846f28 | 5151 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5152 | && !generating_literals) |
5153 | { | |
43cd72b9 BW |
5154 | xtensa_set_frag_assembly_state (frag_now); |
5155 | ||
43cd72b9 | 5156 | frag_var (rs_machine_dependent, |
7b1cc377 | 5157 | 0, (int) freq, |
e0001a05 NC |
5158 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5159 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5160 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5161 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5162 | } |
5163 | ||
5164 | /* We need to mark the following properties even if we aren't aligning. */ | |
5165 | ||
5166 | /* If the label is already known to be a branch target, i.e., a | |
5167 | forward branch, mark the frag accordingly. Backward branches | |
5168 | are handled by xg_add_branch_and_loop_targets. */ | |
5169 | if (symbol_get_tc (sym)->is_branch_target) | |
5170 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5171 | ||
5172 | /* Loops only go forward, so they can be identified here. */ | |
5173 | if (symbol_get_tc (sym)->is_loop_target) | |
5174 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5175 | |
5176 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5177 | } |
5178 | ||
5179 | ||
5180 | /* tc_unrecognized_line hook */ | |
5181 | ||
5182 | int | |
7fa3d080 | 5183 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5184 | { |
5185 | switch (ch) | |
5186 | { | |
5187 | case '{' : | |
5188 | if (cur_vinsn.inside_bundle == 0) | |
5189 | { | |
5190 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5191 | when using --gstabs. Temporarily disable debug info. */ | |
5192 | generate_lineno_debug (); | |
5193 | if (debug_type == DEBUG_STABS) | |
5194 | { | |
5195 | xt_saved_debug_type = debug_type; | |
5196 | debug_type = DEBUG_NONE; | |
5197 | } | |
82e7541d | 5198 | |
43cd72b9 BW |
5199 | cur_vinsn.inside_bundle = 1; |
5200 | } | |
5201 | else | |
5202 | { | |
5203 | as_bad (_("extra opening brace")); | |
5204 | return 0; | |
5205 | } | |
5206 | break; | |
82e7541d | 5207 | |
43cd72b9 BW |
5208 | case '}' : |
5209 | if (cur_vinsn.inside_bundle) | |
5210 | finish_vinsn (&cur_vinsn); | |
5211 | else | |
5212 | { | |
5213 | as_bad (_("extra closing brace")); | |
5214 | return 0; | |
5215 | } | |
5216 | break; | |
5217 | default: | |
5218 | as_bad (_("syntax error")); | |
5219 | return 0; | |
e0001a05 | 5220 | } |
43cd72b9 | 5221 | return 1; |
e0001a05 NC |
5222 | } |
5223 | ||
5224 | ||
5225 | /* md_flush_pending_output hook */ | |
5226 | ||
5227 | void | |
7fa3d080 | 5228 | xtensa_flush_pending_output (void) |
e0001a05 | 5229 | { |
a3582eee BW |
5230 | /* This line fixes a bug where automatically generated gstabs info |
5231 | separates a function label from its entry instruction, ending up | |
5232 | with the literal position between the function label and the entry | |
5233 | instruction and crashing code. It only happens with --gstabs and | |
5234 | --text-section-literals, and when several other obscure relaxation | |
5235 | conditions are met. */ | |
5236 | if (outputting_stabs_line_debug) | |
5237 | return; | |
5238 | ||
43cd72b9 BW |
5239 | if (cur_vinsn.inside_bundle) |
5240 | as_bad (_("missing closing brace")); | |
5241 | ||
e0001a05 NC |
5242 | /* If there is a non-zero instruction fragment, close it. */ |
5243 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5244 | { | |
5245 | frag_wane (frag_now); | |
5246 | frag_new (0); | |
43cd72b9 | 5247 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5248 | } |
5249 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5250 | |
5251 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5252 | } |
5253 | ||
5254 | ||
43cd72b9 BW |
5255 | /* We had an error while parsing an instruction. The string might look |
5256 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5257 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5258 | and the num_slots field will grow past the end of the array of slots, | |
5259 | and bad things happen. */ | |
5260 | ||
5261 | static void | |
7fa3d080 | 5262 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5263 | { |
5264 | if (cur_vinsn.inside_bundle) | |
5265 | { | |
5266 | if (*input_line_pointer == '}' | |
5267 | || *(input_line_pointer - 1) == '}' | |
5268 | || *(input_line_pointer - 2) == '}') | |
5269 | xg_clear_vinsn (&cur_vinsn); | |
5270 | } | |
5271 | } | |
5272 | ||
5273 | ||
e0001a05 | 5274 | void |
7fa3d080 | 5275 | md_assemble (char *str) |
e0001a05 NC |
5276 | { |
5277 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5278 | char *opname; |
e0001a05 NC |
5279 | unsigned opnamelen; |
5280 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5281 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5282 | int num_args; |
e0001a05 | 5283 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5284 | |
e0001a05 NC |
5285 | tinsn_init (&orig_insn); |
5286 | ||
5287 | /* Split off the opcode. */ | |
5288 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5289 | opname = xmalloc (opnamelen + 1); | |
5290 | memcpy (opname, str, opnamelen); | |
5291 | opname[opnamelen] = '\0'; | |
5292 | ||
5293 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5294 | if (num_args == -1) | |
5295 | { | |
5296 | as_bad (_("syntax error")); | |
5297 | return; | |
5298 | } | |
5299 | ||
5300 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5301 | return; | |
5302 | ||
5303 | /* Check for an underbar prefix. */ | |
5304 | if (*opname == '_') | |
5305 | { | |
5306 | has_underbar = TRUE; | |
5307 | opname += 1; | |
5308 | } | |
5309 | ||
5310 | orig_insn.insn_type = ITYPE_INSN; | |
5311 | orig_insn.ntok = 0; | |
43cd72b9 | 5312 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5313 | |
5314 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5315 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5316 | { | |
43cd72b9 BW |
5317 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5318 | if (fmt == XTENSA_UNDEFINED) | |
5319 | { | |
5320 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5321 | error_reset_cur_vinsn (); | |
5322 | return; | |
5323 | } | |
5324 | if (!cur_vinsn.inside_bundle) | |
5325 | { | |
5326 | as_bad (_("format names only valid inside bundles")); | |
5327 | error_reset_cur_vinsn (); | |
5328 | return; | |
5329 | } | |
5330 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5331 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5332 | opname); | |
5333 | cur_vinsn.format = fmt; | |
5334 | free (has_underbar ? opname - 1 : opname); | |
5335 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5336 | return; |
5337 | } | |
5338 | ||
e0001a05 NC |
5339 | /* Parse the arguments. */ |
5340 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5341 | { | |
5342 | as_bad (_("syntax error")); | |
43cd72b9 | 5343 | error_reset_cur_vinsn (); |
e0001a05 NC |
5344 | return; |
5345 | } | |
5346 | ||
5347 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5348 | free (has_underbar ? opname - 1 : opname); | |
5349 | opname = 0; | |
5350 | while (num_args-- > 0) | |
5351 | free (arg_strings[num_args]); | |
5352 | ||
43cd72b9 BW |
5353 | /* Get expressions for invisible operands. */ |
5354 | if (get_invisible_operands (&orig_insn)) | |
5355 | { | |
5356 | error_reset_cur_vinsn (); | |
5357 | return; | |
5358 | } | |
5359 | ||
e0001a05 NC |
5360 | /* Check for the right number and type of arguments. */ |
5361 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5362 | { |
43cd72b9 BW |
5363 | error_reset_cur_vinsn (); |
5364 | return; | |
e0001a05 NC |
5365 | } |
5366 | ||
b224e962 BW |
5367 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5368 | spread across multiple input lines and individual instructions may be | |
5369 | moved around in some cases. */ | |
5370 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5371 | dwarf2_where (&orig_insn.debug_line); | |
5372 | dwarf2_consume_line_info (); | |
c138bc38 | 5373 | |
43cd72b9 BW |
5374 | xg_add_branch_and_loop_targets (&orig_insn); |
5375 | ||
431ad2d0 BW |
5376 | /* Check that immediate value for ENTRY is >= 16. */ |
5377 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5378 | { |
431ad2d0 BW |
5379 | expressionS *exp = &orig_insn.tok[2]; |
5380 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5381 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5382 | } |
5383 | ||
e0001a05 | 5384 | /* Finish it off: |
43cd72b9 BW |
5385 | assemble_tokens (opcode, tok, ntok); |
5386 | expand the tokens from the orig_insn into the | |
5387 | stack of instructions that will not expand | |
e0001a05 | 5388 | unless required at relaxation time. */ |
e0001a05 | 5389 | |
43cd72b9 BW |
5390 | if (!cur_vinsn.inside_bundle) |
5391 | emit_single_op (&orig_insn); | |
5392 | else /* We are inside a bundle. */ | |
e0001a05 | 5393 | { |
43cd72b9 BW |
5394 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5395 | cur_vinsn.num_slots++; | |
5396 | if (*input_line_pointer == '}' | |
5397 | || *(input_line_pointer - 1) == '}' | |
5398 | || *(input_line_pointer - 2) == '}') | |
5399 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5400 | } |
5401 | ||
43cd72b9 BW |
5402 | /* We've just emitted a new instruction so clear the list of labels. */ |
5403 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5404 | } |
5405 | ||
5406 | ||
43cd72b9 | 5407 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5408 | |
43cd72b9 BW |
5409 | /* For a .align directive, we mark the previous block with the alignment |
5410 | information. This will be placed in the object file in the | |
5411 | property section corresponding to this section. */ | |
e0001a05 | 5412 | |
43cd72b9 | 5413 | void |
7fa3d080 | 5414 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5415 | { |
5416 | if (linkrelax | |
b08b5071 | 5417 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5418 | && (fragP->fr_type == rs_align |
5419 | || fragP->fr_type == rs_align_code) | |
5420 | && fragP->fr_address + fragP->fr_fix > 0 | |
5421 | && fragP->fr_offset > 0 | |
5422 | && now_seg != bss_section) | |
e0001a05 | 5423 | { |
43cd72b9 BW |
5424 | fragP->tc_frag_data.is_align = TRUE; |
5425 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5426 | } |
5427 | ||
43cd72b9 | 5428 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5429 | { |
43cd72b9 BW |
5430 | int count; |
5431 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5432 | if (count != 0) | |
c138bc38 | 5433 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5434 | _("unaligned entry instruction")); |
e0001a05 | 5435 | } |
99ded152 BW |
5436 | |
5437 | if (linkrelax && fragP->fr_type == rs_org) | |
5438 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5439 | } |
43cd72b9 | 5440 | |
e0001a05 NC |
5441 | |
5442 | /* TC_FRAG_INIT hook */ | |
5443 | ||
5444 | void | |
7fa3d080 | 5445 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5446 | { |
43cd72b9 | 5447 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5448 | } |
5449 | ||
5450 | ||
5451 | symbolS * | |
7fa3d080 | 5452 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5453 | { |
5454 | return NULL; | |
5455 | } | |
5456 | ||
5457 | ||
5458 | /* Round up a section size to the appropriate boundary. */ | |
5459 | ||
5460 | valueT | |
7fa3d080 | 5461 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5462 | { |
5463 | return size; /* Byte alignment is fine. */ | |
5464 | } | |
5465 | ||
5466 | ||
5467 | long | |
7fa3d080 | 5468 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5469 | { |
5470 | char *insn_p; | |
5471 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5472 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5473 | int opnum; |
43cd72b9 | 5474 | uint32 opnd_value; |
e0001a05 | 5475 | xtensa_opcode opcode; |
43cd72b9 BW |
5476 | xtensa_format fmt; |
5477 | int slot; | |
e0001a05 NC |
5478 | xtensa_isa isa = xtensa_default_isa; |
5479 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5480 | bfd_boolean alt_reloc; |
e0001a05 | 5481 | |
e0001a05 | 5482 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5483 | return 0; |
e0001a05 | 5484 | |
1bbb5f21 BW |
5485 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5486 | return addr; | |
5487 | ||
e0001a05 | 5488 | if (!insnbuf) |
43cd72b9 BW |
5489 | { |
5490 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5491 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5492 | } | |
e0001a05 NC |
5493 | |
5494 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5495 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5496 | fmt = xtensa_format_decode (isa, insnbuf); |
5497 | ||
5498 | if (fmt == XTENSA_UNDEFINED) | |
5499 | as_fatal (_("bad instruction format")); | |
5500 | ||
5501 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5502 | as_fatal (_("invalid relocation")); | |
5503 | ||
5504 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5505 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5506 | ||
30f725a1 BW |
5507 | /* Check for "alternate" relocations (operand not specified). None |
5508 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5509 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5510 | { | |
5511 | if (opcode != xtensa_l32r_opcode | |
5512 | && opcode != xtensa_const16_opcode) | |
5513 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5514 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5515 | return 0; |
e0001a05 NC |
5516 | } |
5517 | ||
43cd72b9 BW |
5518 | opnum = get_relaxable_immed (opcode); |
5519 | opnd_value = 0; | |
5520 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5521 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5522 | { |
5523 | as_bad_where (fixP->fx_file, | |
5524 | fixP->fx_line, | |
5525 | _("invalid relocation for operand %d of '%s'"), | |
5526 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5527 | return 0; |
e0001a05 | 5528 | } |
43cd72b9 BW |
5529 | return 0 - opnd_value; |
5530 | } | |
5531 | ||
5532 | ||
5533 | /* TC_FORCE_RELOCATION hook */ | |
5534 | ||
5535 | int | |
7fa3d080 | 5536 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5537 | { |
5538 | switch (fix->fx_r_type) | |
30f725a1 BW |
5539 | { |
5540 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5541 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5542 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5543 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5544 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5545 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5546 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5547 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5548 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5549 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5550 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5551 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5552 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5553 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5554 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5555 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5556 | return 1; |
5557 | default: | |
5558 | break; | |
e0001a05 NC |
5559 | } |
5560 | ||
43cd72b9 BW |
5561 | if (linkrelax && fix->fx_addsy |
5562 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5563 | return 1; | |
5564 | ||
5565 | return generic_force_reloc (fix); | |
5566 | } | |
5567 | ||
5568 | ||
30f725a1 BW |
5569 | /* TC_VALIDATE_FIX_SUB hook */ |
5570 | ||
5571 | int | |
5572 | xtensa_validate_fix_sub (fixS *fix) | |
5573 | { | |
5574 | segT add_symbol_segment, sub_symbol_segment; | |
5575 | ||
5576 | /* The difference of two symbols should be resolved by the assembler when | |
5577 | linkrelax is not set. If the linker may relax the section containing | |
5578 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5579 | the linker knows to adjust the difference value. */ | |
5580 | if (!linkrelax || fix->fx_addsy == NULL) | |
5581 | return 0; | |
5582 | ||
5583 | /* Make sure both symbols are in the same segment, and that segment is | |
5584 | "normal" and relaxable. If the segment is not "normal", then the | |
5585 | fix is not valid. If the segment is not "relaxable", then the fix | |
5586 | should have been handled earlier. */ | |
5587 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5588 | if (! SEG_NORMAL (add_symbol_segment) || | |
5589 | ! relaxable_section (add_symbol_segment)) | |
5590 | return 0; | |
5591 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5592 | return (sub_symbol_segment == add_symbol_segment); | |
5593 | } | |
5594 | ||
5595 | ||
43cd72b9 BW |
5596 | /* NO_PSEUDO_DOT hook */ |
5597 | ||
5598 | /* This function has nothing to do with pseudo dots, but this is the | |
5599 | nearest macro to where the check needs to take place. FIXME: This | |
5600 | seems wrong. */ | |
5601 | ||
5602 | bfd_boolean | |
7fa3d080 | 5603 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5604 | { |
5605 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5606 | as_bad (_("directives are not valid inside bundles")); | |
5607 | ||
5608 | /* This function must always return FALSE because it is called via a | |
5609 | macro that has nothing to do with bundling. */ | |
5610 | return FALSE; | |
e0001a05 NC |
5611 | } |
5612 | ||
5613 | ||
43cd72b9 | 5614 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5615 | |
5616 | void | |
7fa3d080 | 5617 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5618 | { |
43cd72b9 BW |
5619 | /* Set up the assembly state. */ |
5620 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5621 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5622 | } |
5623 | ||
5624 | ||
5625 | /* tc_fix_adjustable hook */ | |
5626 | ||
5627 | bfd_boolean | |
7fa3d080 | 5628 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5629 | { |
43cd72b9 BW |
5630 | /* An offset is not allowed in combination with the difference of two |
5631 | symbols, but that cannot be easily detected after a local symbol | |
5632 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5633 | an fix will not be adjusted. */ | |
5634 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5635 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5636 | return 0; | |
5637 | ||
e0001a05 NC |
5638 | /* We need the symbol name for the VTABLE entries. */ |
5639 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5640 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5641 | return 0; | |
5642 | ||
5643 | return 1; | |
5644 | } | |
5645 | ||
5646 | ||
6a7eedfe BW |
5647 | /* tc_symbol_new_hook */ |
5648 | ||
5649 | symbolS *expr_symbols = NULL; | |
5650 | ||
5651 | void | |
5652 | xtensa_symbol_new_hook (symbolS *sym) | |
5653 | { | |
fb227da0 | 5654 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5655 | { |
5656 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5657 | expr_symbols = sym; | |
5658 | } | |
5659 | } | |
5660 | ||
5661 | ||
e0001a05 | 5662 | void |
55cf6793 | 5663 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5664 | { |
30f725a1 | 5665 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5666 | valueT val = 0; |
30f725a1 | 5667 | |
e7da6241 BW |
5668 | /* Subtracted symbols are only allowed for a few relocation types, and |
5669 | unless linkrelax is enabled, they should not make it to this point. */ | |
5670 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5671 | || fixP->fx_r_type == BFD_RELOC_16 | |
5672 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5673 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5674 | ||
30f725a1 | 5675 | switch (fixP->fx_r_type) |
e0001a05 | 5676 | { |
1bbb5f21 | 5677 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5678 | case BFD_RELOC_32: |
5679 | case BFD_RELOC_16: | |
5680 | case BFD_RELOC_8: | |
e7da6241 | 5681 | if (fixP->fx_subsy) |
30f725a1 BW |
5682 | { |
5683 | switch (fixP->fx_r_type) | |
5684 | { | |
5685 | case BFD_RELOC_8: | |
5686 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5687 | break; | |
5688 | case BFD_RELOC_16: | |
5689 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5690 | break; | |
5691 | case BFD_RELOC_32: | |
5692 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5693 | break; | |
5694 | default: | |
5695 | break; | |
5696 | } | |
e0001a05 | 5697 | |
30f725a1 BW |
5698 | /* An offset is only allowed when it results from adjusting a |
5699 | local symbol into a section-relative offset. If the offset | |
5700 | came from the original expression, tc_fix_adjustable will have | |
5701 | prevented the fix from being converted to a section-relative | |
5702 | form so that we can flag the error here. */ | |
5703 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5704 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5705 | _("cannot represent subtraction with an offset")); | |
5706 | ||
5707 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5708 | - S_GET_VALUE (fixP->fx_subsy)); | |
5709 | ||
5710 | /* The difference value gets written out, and the DIFF reloc | |
5711 | identifies the address of the subtracted symbol (i.e., the one | |
5712 | with the lowest address). */ | |
5713 | *valP = val; | |
5714 | fixP->fx_offset -= val; | |
5715 | fixP->fx_subsy = NULL; | |
5716 | } | |
5717 | else if (! fixP->fx_addsy) | |
e0001a05 | 5718 | { |
30f725a1 | 5719 | val = *valP; |
e0001a05 | 5720 | fixP->fx_done = 1; |
30f725a1 | 5721 | } |
d47d412e BW |
5722 | /* fall through */ |
5723 | ||
5724 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5725 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5726 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5727 | break; | |
e0001a05 | 5728 | |
30f725a1 BW |
5729 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5730 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5731 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5732 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5733 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5734 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5735 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5736 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5737 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5738 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5739 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5740 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5741 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5742 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5743 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5744 | if (linkrelax) | |
5745 | { | |
5746 | /* Write the tentative value of a PC-relative relocation to a | |
5747 | local symbol into the instruction. The value will be ignored | |
5748 | by the linker, and it makes the object file disassembly | |
5749 | readable when all branch targets are encoded in relocations. */ | |
5750 | ||
5751 | assert (fixP->fx_addsy); | |
20ee54e8 | 5752 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5753 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5754 | { | |
5755 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5756 | - md_pcrel_from (fixP)); | |
5757 | (void) xg_apply_fix_value (fixP, val); | |
5758 | } | |
5759 | } | |
5760 | else if (! fixP->fx_addsy) | |
5761 | { | |
5762 | val = *valP; | |
5763 | if (xg_apply_fix_value (fixP, val)) | |
5764 | fixP->fx_done = 1; | |
5765 | } | |
5766 | break; | |
e0001a05 | 5767 | |
30f725a1 BW |
5768 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5769 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5770 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5771 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5772 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5773 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5774 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5775 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5776 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5777 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5778 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5779 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5780 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5781 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5782 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5783 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5784 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5785 | break; | |
e0001a05 | 5786 | |
30f725a1 BW |
5787 | case BFD_RELOC_VTABLE_INHERIT: |
5788 | case BFD_RELOC_VTABLE_ENTRY: | |
5789 | fixP->fx_done = 0; | |
5790 | break; | |
e0001a05 | 5791 | |
30f725a1 BW |
5792 | default: |
5793 | as_bad (_("unhandled local relocation fix %s"), | |
5794 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5795 | } |
5796 | } | |
5797 | ||
5798 | ||
5799 | char * | |
7fa3d080 | 5800 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 5801 | { |
499ac353 | 5802 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
5803 | } |
5804 | ||
5805 | ||
5806 | int | |
7fa3d080 | 5807 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5808 | { |
34e41783 | 5809 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5810 | } |
5811 | ||
5812 | ||
5813 | /* Translate internal representation of relocation info to BFD target | |
5814 | format. */ | |
5815 | ||
5816 | arelent * | |
30f725a1 | 5817 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5818 | { |
5819 | arelent *reloc; | |
5820 | ||
5821 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5822 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5823 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5824 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5825 | ||
5826 | /* Make sure none of our internal relocations make it this far. | |
5827 | They'd better have been fully resolved by this point. */ | |
5828 | assert ((int) fixp->fx_r_type > 0); | |
5829 | ||
30f725a1 | 5830 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5831 | |
e0001a05 NC |
5832 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5833 | if (reloc->howto == NULL) | |
5834 | { | |
5835 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5836 | _("cannot represent `%s' relocation in object file"), | |
5837 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5838 | free (reloc->sym_ptr_ptr); |
5839 | free (reloc); | |
e0001a05 NC |
5840 | return NULL; |
5841 | } | |
5842 | ||
5843 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 5844 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 5845 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 5846 | |
e0001a05 NC |
5847 | return reloc; |
5848 | } | |
5849 | ||
7fa3d080 BW |
5850 | \f |
5851 | /* Checks for resource conflicts between instructions. */ | |
5852 | ||
c138bc38 BW |
5853 | /* The func unit stuff could be implemented as bit-vectors rather |
5854 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5855 | slow, we will switch it. */ |
5856 | ||
c138bc38 | 5857 | resource_table * |
7fa3d080 BW |
5858 | new_resource_table (void *data, |
5859 | int cycles, | |
5860 | int nu, | |
5861 | unit_num_copies_func uncf, | |
5862 | opcode_num_units_func onuf, | |
5863 | opcode_funcUnit_use_unit_func ouuf, | |
5864 | opcode_funcUnit_use_stage_func ousf) | |
5865 | { | |
5866 | int i; | |
5867 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5868 | rt->data = data; | |
5869 | rt->cycles = cycles; | |
5870 | rt->allocated_cycles = cycles; | |
5871 | rt->num_units = nu; | |
5872 | rt->unit_num_copies = uncf; | |
5873 | rt->opcode_num_units = onuf; | |
5874 | rt->opcode_unit_use = ouuf; | |
5875 | rt->opcode_unit_stage = ousf; | |
5876 | ||
0bf60745 | 5877 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5878 | for (i = 0; i < cycles; i++) |
0bf60745 | 5879 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5880 | |
5881 | return rt; | |
5882 | } | |
5883 | ||
5884 | ||
c138bc38 | 5885 | void |
7fa3d080 BW |
5886 | clear_resource_table (resource_table *rt) |
5887 | { | |
5888 | int i, j; | |
5889 | for (i = 0; i < rt->allocated_cycles; i++) | |
5890 | for (j = 0; j < rt->num_units; j++) | |
5891 | rt->units[i][j] = 0; | |
5892 | } | |
5893 | ||
5894 | ||
5895 | /* We never shrink it, just fake it into thinking so. */ | |
5896 | ||
c138bc38 | 5897 | void |
7fa3d080 BW |
5898 | resize_resource_table (resource_table *rt, int cycles) |
5899 | { | |
5900 | int i, old_cycles; | |
5901 | ||
5902 | rt->cycles = cycles; | |
5903 | if (cycles <= rt->allocated_cycles) | |
5904 | return; | |
5905 | ||
5906 | old_cycles = rt->allocated_cycles; | |
5907 | rt->allocated_cycles = cycles; | |
5908 | ||
0bf60745 BW |
5909 | rt->units = xrealloc (rt->units, |
5910 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5911 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5912 | rt->units[i] = xrealloc (rt->units[i], |
5913 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5914 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5915 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5916 | } |
5917 | ||
5918 | ||
c138bc38 | 5919 | bfd_boolean |
7fa3d080 BW |
5920 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5921 | { | |
5922 | int i; | |
5923 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5924 | ||
c138bc38 | 5925 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5926 | { |
5927 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5928 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5929 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5930 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5931 | if (copies_in_use >= copies) | |
5932 | return FALSE; | |
5933 | } | |
5934 | return TRUE; | |
5935 | } | |
7fa3d080 | 5936 | |
c138bc38 BW |
5937 | |
5938 | void | |
7fa3d080 BW |
5939 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5940 | { | |
5941 | int i; | |
5942 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5943 | ||
c138bc38 | 5944 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5945 | { |
5946 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5947 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5948 | /* Note that this allows resources to be oversubscribed. That's |
5949 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5950 | resources_available reports when a resource is over-subscribed, |
5951 | so it's easy to tell. */ | |
5952 | rt->units[stage + cycle][unit]++; | |
5953 | } | |
5954 | } | |
5955 | ||
5956 | ||
c138bc38 | 5957 | void |
7fa3d080 BW |
5958 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5959 | { | |
5960 | int i; | |
5961 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5962 | ||
c138bc38 | 5963 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5964 | { |
5965 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5966 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5967 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5968 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5969 | } |
5970 | } | |
c138bc38 | 5971 | |
7fa3d080 BW |
5972 | |
5973 | /* Wrapper functions make parameterized resource reservation | |
5974 | more convenient. */ | |
5975 | ||
c138bc38 | 5976 | int |
7fa3d080 BW |
5977 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5978 | { | |
5979 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5980 | return use->unit; |
7fa3d080 BW |
5981 | } |
5982 | ||
5983 | ||
c138bc38 | 5984 | int |
7fa3d080 BW |
5985 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5986 | { | |
5987 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5988 | return use->stage; | |
5989 | } | |
5990 | ||
5991 | ||
5992 | /* Note that this function does not check issue constraints, but | |
5993 | solely whether the hardware is available to execute the given | |
c138bc38 | 5994 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5995 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5996 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5997 | |
5998 | static bfd_boolean | |
5999 | resources_conflict (vliw_insn *vinsn) | |
6000 | { | |
6001 | int i; | |
6002 | static resource_table *rt = NULL; | |
6003 | ||
6004 | /* This is the most common case by far. Optimize it. */ | |
6005 | if (vinsn->num_slots == 1) | |
6006 | return FALSE; | |
43cd72b9 | 6007 | |
c138bc38 | 6008 | if (rt == NULL) |
7fa3d080 BW |
6009 | { |
6010 | xtensa_isa isa = xtensa_default_isa; | |
6011 | rt = new_resource_table | |
77cba8a3 | 6012 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6013 | xtensa_isa_num_funcUnits (isa), |
6014 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6015 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6016 | opcode_funcUnit_use_unit, | |
6017 | opcode_funcUnit_use_stage); | |
6018 | } | |
43cd72b9 | 6019 | |
7fa3d080 | 6020 | clear_resource_table (rt); |
43cd72b9 | 6021 | |
7fa3d080 BW |
6022 | for (i = 0; i < vinsn->num_slots; i++) |
6023 | { | |
6024 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6025 | return TRUE; | |
6026 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6027 | } | |
e0001a05 | 6028 | |
7fa3d080 BW |
6029 | return FALSE; |
6030 | } | |
e0001a05 | 6031 | |
7fa3d080 BW |
6032 | \f |
6033 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6034 | |
7fa3d080 BW |
6035 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6036 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6037 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6038 | |
6039 | ||
43cd72b9 BW |
6040 | /* We have reached the end of a bundle; emit into the frag. */ |
6041 | ||
e0001a05 | 6042 | static void |
7fa3d080 | 6043 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6044 | { |
43cd72b9 BW |
6045 | IStack slotstack; |
6046 | int i; | |
6047 | char *file_name; | |
d77b99c9 | 6048 | unsigned line; |
e0001a05 | 6049 | |
43cd72b9 | 6050 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6051 | { |
6052 | xg_clear_vinsn (vinsn); | |
6053 | return; | |
6054 | } | |
43cd72b9 BW |
6055 | |
6056 | /* First, find a format that works. */ | |
6057 | if (vinsn->format == XTENSA_UNDEFINED) | |
6058 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6059 | ||
6060 | if (vinsn->format == XTENSA_UNDEFINED) | |
6061 | { | |
6062 | as_where (&file_name, &line); | |
6063 | as_bad_where (file_name, line, | |
6064 | _("couldn't find a valid instruction format")); | |
6065 | fprintf (stderr, _(" ops were: ")); | |
6066 | for (i = 0; i < vinsn->num_slots; i++) | |
6067 | fprintf (stderr, _(" %s;"), | |
6068 | xtensa_opcode_name (xtensa_default_isa, | |
6069 | vinsn->slots[i].opcode)); | |
6070 | fprintf (stderr, _("\n")); | |
6071 | xg_clear_vinsn (vinsn); | |
6072 | return; | |
6073 | } | |
6074 | ||
6075 | if (vinsn->num_slots | |
6076 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6077 | { |
43cd72b9 BW |
6078 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6079 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6080 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6081 | vinsn->num_slots); | |
6082 | xg_clear_vinsn (vinsn); | |
6083 | return; | |
6084 | } | |
e0001a05 | 6085 | |
c138bc38 | 6086 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6087 | { |
6088 | as_where (&file_name, &line); | |
6089 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6090 | fprintf (stderr, " ops were: "); | |
6091 | for (i = 0; i < vinsn->num_slots; i++) | |
6092 | fprintf (stderr, " %s;", | |
6093 | xtensa_opcode_name (xtensa_default_isa, | |
6094 | vinsn->slots[i].opcode)); | |
6095 | fprintf (stderr, "\n"); | |
6096 | xg_clear_vinsn (vinsn); | |
6097 | return; | |
6098 | } | |
6099 | ||
6100 | for (i = 0; i < vinsn->num_slots; i++) | |
6101 | { | |
6102 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6103 | { |
43cd72b9 BW |
6104 | symbolS *lit_sym = NULL; |
6105 | int j; | |
6106 | bfd_boolean e = FALSE; | |
6107 | bfd_boolean saved_density = density_supported; | |
6108 | ||
6109 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6110 | if (vinsn->num_slots > 1) | |
6111 | density_supported = FALSE; | |
6112 | ||
6113 | istack_init (&slotstack); | |
6114 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6115 | { |
43cd72b9 BW |
6116 | vinsn->slots[i].opcode = |
6117 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6118 | vinsn->format, i); | |
6119 | vinsn->slots[i].ntok = 0; | |
6120 | } | |
e0001a05 | 6121 | |
43cd72b9 BW |
6122 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6123 | { | |
6124 | e = TRUE; | |
6125 | continue; | |
e0001a05 | 6126 | } |
e0001a05 | 6127 | |
43cd72b9 | 6128 | density_supported = saved_density; |
e0001a05 | 6129 | |
43cd72b9 BW |
6130 | if (e) |
6131 | { | |
6132 | xg_clear_vinsn (vinsn); | |
6133 | return; | |
6134 | } | |
e0001a05 | 6135 | |
0fa77c95 | 6136 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6137 | { |
6138 | TInsn *insn = &slotstack.insn[j]; | |
6139 | if (insn->insn_type == ITYPE_LITERAL) | |
6140 | { | |
6141 | assert (lit_sym == NULL); | |
6142 | lit_sym = xg_assemble_literal (insn); | |
6143 | } | |
6144 | else | |
6145 | { | |
0fa77c95 | 6146 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6147 | if (lit_sym) |
6148 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6149 | if (j != slotstack.ninsn - 1) |
6150 | emit_single_op (insn); | |
43cd72b9 BW |
6151 | } |
6152 | } | |
6153 | ||
6154 | if (vinsn->num_slots > 1) | |
6155 | { | |
6156 | if (opcode_fits_format_slot | |
6157 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6158 | vinsn->format, i)) | |
6159 | { | |
6160 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6161 | } | |
6162 | else | |
6163 | { | |
b2d179be | 6164 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6165 | if (vinsn->format == XTENSA_UNDEFINED) |
6166 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6167 | else | |
c138bc38 | 6168 | vinsn->slots[i].opcode |
43cd72b9 BW |
6169 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6170 | vinsn->format, i); | |
6171 | ||
6172 | vinsn->slots[i].ntok = 0; | |
6173 | } | |
6174 | } | |
6175 | else | |
6176 | { | |
6177 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6178 | vinsn->format = XTENSA_UNDEFINED; | |
6179 | } | |
6180 | } | |
6181 | } | |
6182 | ||
6183 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6184 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6185 | { |
6186 | as_where (&file_name, &line); | |
6187 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6188 | fprintf (stderr, " ops were: "); | |
6189 | for (i = 0; i < vinsn->num_slots; i++) | |
6190 | fprintf (stderr, " %s;", | |
6191 | xtensa_opcode_name (xtensa_default_isa, | |
6192 | vinsn->slots[i].opcode)); | |
6193 | fprintf (stderr, "\n"); | |
6194 | xg_clear_vinsn (vinsn); | |
6195 | return; | |
6196 | } | |
6197 | ||
6198 | /* First, find a format that works. */ | |
6199 | if (vinsn->format == XTENSA_UNDEFINED) | |
6200 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6201 | ||
6202 | xg_assemble_vliw_tokens (vinsn); | |
6203 | ||
6204 | xg_clear_vinsn (vinsn); | |
6205 | } | |
6206 | ||
6207 | ||
6208 | /* Given an vliw instruction, what conflicts are there in register | |
6209 | usage and in writes to states and queues? | |
6210 | ||
6211 | This function does two things: | |
6212 | 1. Reports an error when a vinsn contains illegal combinations | |
6213 | of writes to registers states or queues. | |
6214 | 2. Marks individual tinsns as not relaxable if the combination | |
6215 | contains antidependencies. | |
6216 | ||
6217 | Job 2 handles things like swap semantics in instructions that need | |
6218 | to be relaxed. For example, | |
6219 | ||
6220 | addi a0, a1, 100000 | |
6221 | ||
6222 | normally would be relaxed to | |
6223 | ||
6224 | l32r a0, some_label | |
6225 | add a0, a1, a0 | |
6226 | ||
6227 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6228 | ||
6229 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6230 | ||
6231 | then we can't relax it into | |
6232 | ||
6233 | l32r a0, some_label | |
6234 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6235 | ||
6236 | because the value of a0 is trashed before the second add can read it. */ | |
6237 | ||
7fa3d080 BW |
6238 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6239 | ||
43cd72b9 | 6240 | static bfd_boolean |
7fa3d080 | 6241 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6242 | { |
6243 | int i, j; | |
6244 | int branches = 0; | |
6245 | xtensa_isa isa = xtensa_default_isa; | |
6246 | ||
6247 | assert (!past_xtensa_end); | |
6248 | ||
6249 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6250 | { | |
6251 | TInsn *op1 = &vinsn->slots[i]; | |
6252 | if (op1->is_specific_opcode) | |
6253 | op1->keep_wide = TRUE; | |
6254 | else | |
6255 | op1->keep_wide = FALSE; | |
6256 | } | |
6257 | ||
6258 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6259 | { | |
6260 | TInsn *op1 = &vinsn->slots[i]; | |
6261 | ||
6262 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6263 | branches++; | |
6264 | ||
6265 | for (j = 0; j < vinsn->num_slots; j++) | |
6266 | { | |
6267 | if (i != j) | |
6268 | { | |
6269 | TInsn *op2 = &vinsn->slots[j]; | |
6270 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6271 | switch (conflict_type) | |
6272 | { | |
6273 | case 'c': | |
6274 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6275 | xtensa_opcode_name (isa, op1->opcode), i, | |
6276 | xtensa_opcode_name (isa, op2->opcode), j); | |
6277 | return TRUE; | |
6278 | case 'd': | |
6279 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6280 | xtensa_opcode_name (isa, op1->opcode), i, | |
6281 | xtensa_opcode_name (isa, op2->opcode), j); | |
6282 | return TRUE; | |
6283 | case 'e': | |
53dfbcc7 | 6284 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6285 | xtensa_opcode_name (isa, op1->opcode), i, |
6286 | xtensa_opcode_name (isa, op2->opcode), j); | |
6287 | return TRUE; | |
6288 | case 'f': | |
53dfbcc7 | 6289 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6290 | xtensa_opcode_name (isa, op1->opcode), i, |
6291 | xtensa_opcode_name (isa, op2->opcode), j); | |
6292 | return TRUE; | |
6293 | default: | |
6294 | /* Everything is OK. */ | |
6295 | break; | |
6296 | } | |
6297 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6298 | || conflict_type == 'a'); | |
6299 | } | |
6300 | } | |
6301 | } | |
6302 | ||
6303 | if (branches > 1) | |
6304 | { | |
6305 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6306 | return TRUE; | |
6307 | } | |
6308 | ||
6309 | return FALSE; | |
6310 | } | |
6311 | ||
6312 | ||
a1ace8d8 | 6313 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6314 | Cases found are: |
6315 | ||
6316 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6317 | case B: no relationship between what is read and written (both could | |
6318 | read the same reg though) | |
c138bc38 | 6319 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6320 | bundle) |
6321 | case D: t1 writes a state that t2 also writes | |
6322 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6323 | case F: two volatile queue accesses |
43cd72b9 BW |
6324 | */ |
6325 | ||
6326 | static char | |
7fa3d080 | 6327 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6328 | { |
6329 | xtensa_isa isa = xtensa_default_isa; | |
6330 | xtensa_regfile t1_regfile, t2_regfile; | |
6331 | int t1_reg, t2_reg; | |
6332 | int t1_base_reg, t1_last_reg; | |
6333 | int t2_base_reg, t2_last_reg; | |
6334 | char t1_inout, t2_inout; | |
6335 | int i, j; | |
6336 | char conflict = 'b'; | |
6337 | int t1_states; | |
6338 | int t2_states; | |
6339 | int t1_interfaces; | |
6340 | int t2_interfaces; | |
6341 | bfd_boolean t1_volatile = FALSE; | |
6342 | bfd_boolean t2_volatile = FALSE; | |
6343 | ||
6344 | /* Check registers. */ | |
6345 | for (j = 0; j < t2->ntok; j++) | |
6346 | { | |
6347 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6348 | continue; | |
6349 | ||
6350 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6351 | t2_base_reg = t2->tok[j].X_add_number; | |
6352 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6353 | ||
6354 | for (i = 0; i < t1->ntok; i++) | |
6355 | { | |
6356 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6357 | continue; | |
6358 | ||
6359 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6360 | ||
6361 | if (t1_regfile != t2_regfile) | |
6362 | continue; | |
6363 | ||
6364 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6365 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6366 | ||
6367 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6368 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6369 | { | |
6370 | if (t1_inout == 'm' || t1_inout == 'o' | |
6371 | || t2_inout == 'm' || t2_inout == 'o') | |
6372 | { | |
6373 | conflict = 'a'; | |
6374 | continue; | |
6375 | } | |
6376 | } | |
6377 | ||
6378 | t1_base_reg = t1->tok[i].X_add_number; | |
6379 | t1_last_reg = (t1_base_reg | |
6380 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6381 | ||
6382 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6383 | { | |
6384 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6385 | { | |
6386 | if (t1_reg != t2_reg) | |
6387 | continue; | |
6388 | ||
6389 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6390 | { |
6391 | conflict = 'a'; | |
6392 | continue; | |
6393 | } | |
43cd72b9 | 6394 | |
7fa3d080 BW |
6395 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6396 | { | |
6397 | conflict = 'a'; | |
6398 | continue; | |
6399 | } | |
43cd72b9 | 6400 | |
7fa3d080 BW |
6401 | if (t1_inout != 'i' && t2_inout != 'i') |
6402 | return 'c'; | |
6403 | } | |
6404 | } | |
6405 | } | |
6406 | } | |
43cd72b9 | 6407 | |
7fa3d080 BW |
6408 | /* Check states. */ |
6409 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6410 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6411 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6412 | { |
7fa3d080 BW |
6413 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6414 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6415 | for (i = 0; i < t1_states; i++) | |
6416 | { | |
6417 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6418 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6419 | if (t1_so != t2_so) |
7fa3d080 | 6420 | continue; |
43cd72b9 | 6421 | |
7fa3d080 BW |
6422 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6423 | { | |
6424 | conflict = 'a'; | |
6425 | continue; | |
6426 | } | |
c138bc38 | 6427 | |
7fa3d080 BW |
6428 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6429 | { | |
6430 | conflict = 'a'; | |
6431 | continue; | |
6432 | } | |
c138bc38 | 6433 | |
7fa3d080 BW |
6434 | if (t1_inout != 'i' && t2_inout != 'i') |
6435 | return 'd'; | |
c138bc38 | 6436 | } |
7fa3d080 | 6437 | } |
43cd72b9 | 6438 | |
7fa3d080 BW |
6439 | /* Check tieports. */ |
6440 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6441 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6442 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6443 | { |
7fa3d080 BW |
6444 | xtensa_interface t2_int |
6445 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6446 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6447 | ||
53dfbcc7 | 6448 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6449 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6450 | t2_volatile = TRUE; |
a1ace8d8 | 6451 | |
7fa3d080 BW |
6452 | for (i = 0; i < t1_interfaces; i++) |
6453 | { | |
6454 | xtensa_interface t1_int | |
6455 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6456 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6457 | |
53dfbcc7 | 6458 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6459 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6460 | t1_volatile = TRUE; |
a1ace8d8 BW |
6461 | |
6462 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6463 | return 'f'; | |
c138bc38 | 6464 | |
7fa3d080 BW |
6465 | if (t1_int != t2_int) |
6466 | continue; | |
c138bc38 | 6467 | |
7fa3d080 BW |
6468 | if (t2_inout == 'i' && t1_inout == 'o') |
6469 | { | |
6470 | conflict = 'a'; | |
6471 | continue; | |
6472 | } | |
c138bc38 | 6473 | |
7fa3d080 BW |
6474 | if (t1_inout == 'i' && t2_inout == 'o') |
6475 | { | |
6476 | conflict = 'a'; | |
6477 | continue; | |
6478 | } | |
c138bc38 | 6479 | |
7fa3d080 BW |
6480 | if (t1_inout != 'i' && t2_inout != 'i') |
6481 | return 'e'; | |
6482 | } | |
43cd72b9 | 6483 | } |
c138bc38 | 6484 | |
7fa3d080 | 6485 | return conflict; |
43cd72b9 BW |
6486 | } |
6487 | ||
6488 | ||
6489 | static xtensa_format | |
7fa3d080 | 6490 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6491 | { |
6492 | /* Right now we assume that the ops within the vinsn are properly | |
6493 | ordered for the slots that the programmer wanted them in. In | |
6494 | other words, we don't rearrange the ops in hopes of finding a | |
6495 | better format. The scheduler handles that. */ | |
6496 | ||
6497 | xtensa_isa isa = xtensa_default_isa; | |
6498 | xtensa_format format; | |
6499 | vliw_insn v_copy = *vinsn; | |
6500 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6501 | ||
65738a7d BW |
6502 | if (vinsn->num_slots == 1) |
6503 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6504 | ||
43cd72b9 BW |
6505 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6506 | { | |
6507 | v_copy = *vinsn; | |
6508 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6509 | { | |
6510 | int slot; | |
6511 | int fit = 0; | |
6512 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6513 | { | |
6514 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6515 | { | |
6516 | v_copy.slots[slot].opcode = | |
6517 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6518 | v_copy.slots[slot].ntok = 0; | |
6519 | } | |
6520 | ||
6521 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6522 | format, slot)) | |
6523 | fit++; | |
7fa3d080 | 6524 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6525 | { |
7fa3d080 BW |
6526 | TInsn widened; |
6527 | /* Try the widened version. */ | |
6528 | if (!v_copy.slots[slot].keep_wide | |
6529 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6530 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6531 | &widened, TRUE) | |
7fa3d080 BW |
6532 | && opcode_fits_format_slot (widened.opcode, |
6533 | format, slot)) | |
43cd72b9 | 6534 | { |
7fa3d080 BW |
6535 | v_copy.slots[slot] = widened; |
6536 | fit++; | |
43cd72b9 BW |
6537 | } |
6538 | } | |
6539 | } | |
6540 | if (fit == v_copy.num_slots) | |
6541 | { | |
6542 | *vinsn = v_copy; | |
6543 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6544 | vinsn->format = format; | |
6545 | break; | |
6546 | } | |
6547 | } | |
6548 | } | |
6549 | ||
6550 | if (format == xtensa_isa_num_formats (isa)) | |
6551 | return XTENSA_UNDEFINED; | |
6552 | ||
6553 | return format; | |
6554 | } | |
6555 | ||
6556 | ||
6557 | /* Return the additional space needed in a frag | |
6558 | for possible relaxations of any ops in a VLIW insn. | |
6559 | Also fill out the relaxations that might be required of | |
6560 | each tinsn in the vinsn. */ | |
6561 | ||
6562 | static int | |
e7da6241 | 6563 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6564 | { |
e7da6241 | 6565 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6566 | int extra_space = 0; |
6567 | int slot; | |
6568 | ||
6569 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6570 | { | |
6571 | TInsn *tinsn = &vinsn->slots[slot]; | |
6572 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6573 | { | |
6574 | /* A narrow instruction could be widened later to help | |
6575 | alignment issues. */ | |
84b08ed9 | 6576 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6577 | && !tinsn->is_specific_opcode |
6578 | && vinsn->num_slots == 1) | |
6579 | { | |
6580 | /* Difference in bytes between narrow and wide insns... */ | |
6581 | extra_space += 1; | |
6582 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6583 | } |
6584 | } | |
6585 | else | |
6586 | { | |
b08b5071 BW |
6587 | if (workaround_b_j_loop_end |
6588 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6589 | && use_transform ()) |
6590 | { | |
6591 | /* Add 2 of these. */ | |
6592 | extra_space += 3; /* for the nop size */ | |
6593 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6594 | } | |
c138bc38 | 6595 | |
43cd72b9 BW |
6596 | /* Need to assemble it with space for the relocation. */ |
6597 | if (xg_is_relaxable_insn (tinsn, 0) | |
6598 | && !tinsn->is_specific_opcode) | |
6599 | { | |
6600 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6601 | int max_literal_size = | |
6602 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6603 | |
43cd72b9 | 6604 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6605 | |
43cd72b9 | 6606 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6607 | extra_space += max_size; |
6608 | } | |
6609 | else | |
6610 | { | |
e7da6241 BW |
6611 | /* A fix record will be added for this instruction prior |
6612 | to relaxation, so make it end the frag. */ | |
6613 | finish_frag = TRUE; | |
43cd72b9 BW |
6614 | } |
6615 | } | |
6616 | } | |
e7da6241 | 6617 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6618 | return extra_space; |
6619 | } | |
6620 | ||
6621 | ||
6622 | static void | |
b2d179be | 6623 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6624 | { |
6625 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6626 | int slot, chosen_slot; |
43cd72b9 | 6627 | |
b2d179be BW |
6628 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6629 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6630 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6631 | |
b2d179be BW |
6632 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6633 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6634 | { |
b2d179be BW |
6635 | if (slot == chosen_slot) |
6636 | vinsn->slots[slot] = *tinsn; | |
6637 | else | |
6638 | { | |
6639 | vinsn->slots[slot].opcode = | |
6640 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6641 | vinsn->slots[slot].ntok = 0; | |
6642 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6643 | } | |
43cd72b9 | 6644 | } |
43cd72b9 BW |
6645 | } |
6646 | ||
6647 | ||
6648 | static bfd_boolean | |
7fa3d080 | 6649 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6650 | { |
6651 | int i; | |
6652 | IStack istack; /* put instructions into here */ | |
6653 | symbolS *lit_sym = NULL; | |
6654 | symbolS *label_sym = NULL; | |
6655 | ||
6656 | istack_init (&istack); | |
6657 | ||
6658 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6659 | Because the scheduling and bundling characteristics of movi and |
6660 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6661 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6662 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6663 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6664 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6665 | && (orig_insn->tok[1].X_op == O_symbol |
482fd9f9 BW |
6666 | || orig_insn->tok[1].X_op == O_pltrel) |
6667 | && !orig_insn->is_specific_opcode && use_transform ()) | |
43cd72b9 BW |
6668 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6669 | else | |
6670 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6671 | return TRUE; | |
6672 | ||
6673 | for (i = 0; i < istack.ninsn; i++) | |
6674 | { | |
6675 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6676 | switch (insn->insn_type) |
43cd72b9 BW |
6677 | { |
6678 | case ITYPE_LITERAL: | |
6679 | assert (lit_sym == NULL); | |
6680 | lit_sym = xg_assemble_literal (insn); | |
6681 | break; | |
6682 | case ITYPE_LABEL: | |
6683 | { | |
6684 | static int relaxed_sym_idx = 0; | |
6685 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6686 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6687 | colon (label); | |
6688 | assert (label_sym == NULL); | |
6689 | label_sym = symbol_find_or_make (label); | |
6690 | assert (label_sym); | |
6691 | free (label); | |
6692 | } | |
6693 | break; | |
6694 | case ITYPE_INSN: | |
b2d179be BW |
6695 | { |
6696 | vliw_insn v; | |
6697 | if (lit_sym) | |
6698 | xg_resolve_literals (insn, lit_sym); | |
6699 | if (label_sym) | |
6700 | xg_resolve_labels (insn, label_sym); | |
6701 | xg_init_vinsn (&v); | |
6702 | bundle_tinsn (insn, &v); | |
6703 | finish_vinsn (&v); | |
6704 | xg_free_vinsn (&v); | |
6705 | } | |
43cd72b9 BW |
6706 | break; |
6707 | default: | |
6708 | assert (0); | |
6709 | break; | |
6710 | } | |
6711 | } | |
6712 | return FALSE; | |
6713 | } | |
6714 | ||
6715 | ||
34e41783 BW |
6716 | static int |
6717 | total_frag_text_expansion (fragS *fragP) | |
6718 | { | |
6719 | int slot; | |
6720 | int total_expansion = 0; | |
6721 | ||
6722 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6723 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6724 | ||
6725 | return total_expansion; | |
6726 | } | |
6727 | ||
6728 | ||
43cd72b9 BW |
6729 | /* Emit a vliw instruction to the current fragment. */ |
6730 | ||
7fa3d080 BW |
6731 | static void |
6732 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6733 | { |
e7da6241 | 6734 | bfd_boolean finish_frag; |
43cd72b9 BW |
6735 | bfd_boolean is_jump = FALSE; |
6736 | bfd_boolean is_branch = FALSE; | |
6737 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
6738 | int insn_size; |
6739 | int extra_space; | |
6740 | char *f = NULL; | |
6741 | int slot; | |
b224e962 BW |
6742 | struct dwarf2_line_info debug_line; |
6743 | bfd_boolean loc_directive_seen = FALSE; | |
6744 | TInsn *tinsn; | |
43cd72b9 | 6745 | |
b224e962 | 6746 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
6747 | |
6748 | if (generating_literals) | |
6749 | { | |
6750 | static int reported = 0; | |
6751 | if (reported < 4) | |
6752 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6753 | _("cannot assemble into a literal fragment")); | |
6754 | if (reported == 3) | |
6755 | as_bad (_("...")); | |
6756 | reported++; | |
6757 | return; | |
6758 | } | |
6759 | ||
6760 | if (frag_now_fix () != 0 | |
b08b5071 | 6761 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6762 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6763 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6764 | || (directive_state[directive_longcalls] |
6765 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6766 | || (directive_state[directive_absolute_literals] |
6767 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6768 | { | |
6769 | frag_wane (frag_now); | |
6770 | frag_new (0); | |
6771 | xtensa_set_frag_assembly_state (frag_now); | |
6772 | } | |
6773 | ||
6774 | if (workaround_a0_b_retw | |
6775 | && vinsn->num_slots == 1 | |
6776 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6777 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6778 | && use_transform ()) | |
6779 | { | |
6780 | has_a0_b_retw = TRUE; | |
6781 | ||
6782 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6783 | After the first assembly pass we will check all of them and | |
6784 | add a nop if needed. */ | |
6785 | frag_now->tc_frag_data.is_insn = TRUE; | |
6786 | frag_var (rs_machine_dependent, 4, 4, | |
6787 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6788 | frag_now->fr_symbol, | |
6789 | frag_now->fr_offset, | |
6790 | NULL); | |
6791 | xtensa_set_frag_assembly_state (frag_now); | |
6792 | frag_now->tc_frag_data.is_insn = TRUE; | |
6793 | frag_var (rs_machine_dependent, 4, 4, | |
6794 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6795 | frag_now->fr_symbol, | |
6796 | frag_now->fr_offset, | |
6797 | NULL); | |
6798 | xtensa_set_frag_assembly_state (frag_now); | |
6799 | } | |
6800 | ||
b224e962 | 6801 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 6802 | { |
b224e962 BW |
6803 | tinsn = &vinsn->slots[slot]; |
6804 | ||
43cd72b9 | 6805 | /* See if the instruction implies an aligned section. */ |
b224e962 | 6806 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 6807 | record_alignment (now_seg, 2); |
c138bc38 | 6808 | |
b224e962 BW |
6809 | /* Determine the best line number for debug info. */ |
6810 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
6811 | && (tinsn->debug_line.filenum != debug_line.filenum | |
6812 | || tinsn->debug_line.line < debug_line.line | |
6813 | || tinsn->debug_line.column < debug_line.column)) | |
6814 | debug_line = tinsn->debug_line; | |
6815 | if (tinsn->loc_directive_seen) | |
6816 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
6817 | } |
6818 | ||
6819 | /* Special cases for instructions that force an alignment... */ | |
6820 | /* None of these opcodes are bundle-able. */ | |
6821 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6822 | { | |
d77b99c9 | 6823 | int max_fill; |
c138bc38 | 6824 | |
05d58145 BW |
6825 | /* Remember the symbol that marks the end of the loop in the frag |
6826 | that marks the start of the loop. This way we can easily find | |
6827 | the end of the loop at the beginning, without adding special code | |
6828 | to mark the loop instructions themselves. */ | |
6829 | symbolS *target_sym = NULL; | |
6830 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6831 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6832 | ||
43cd72b9 BW |
6833 | xtensa_set_frag_assembly_state (frag_now); |
6834 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6835 | |
43cd72b9 BW |
6836 | max_fill = get_text_align_max_fill_size |
6837 | (get_text_align_power (xtensa_fetch_width), | |
6838 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6839 | ||
6840 | if (use_transform ()) | |
6841 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6842 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6843 | else |
c138bc38 | 6844 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6845 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6846 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
6847 | } |
6848 | ||
b08b5071 | 6849 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6850 | && !vinsn->slots[0].is_specific_opcode) |
6851 | { | |
6852 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 6853 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
6854 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
6855 | } | |
6856 | ||
6857 | if (vinsn->num_slots == 1) | |
6858 | { | |
6859 | if (workaround_a0_b_retw && use_transform ()) | |
6860 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6861 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6862 | ||
6863 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6864 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6865 | } | |
6866 | else | |
6867 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6868 | ||
6869 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6870 | ||
e7da6241 | 6871 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6872 | |
6873 | /* vinsn_to_insnbuf will produce the error. */ | |
6874 | if (vinsn->format != XTENSA_UNDEFINED) | |
6875 | { | |
d77b99c9 | 6876 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6877 | xtensa_set_frag_assembly_state (frag_now); |
6878 | frag_now->tc_frag_data.is_insn = TRUE; | |
6879 | } | |
6880 | ||
e7da6241 | 6881 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6882 | if (vinsn->format == XTENSA_UNDEFINED) |
6883 | return; | |
6884 | ||
d77b99c9 | 6885 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6886 | |
b224e962 BW |
6887 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
6888 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
6889 | &debug_line); | |
43cd72b9 BW |
6890 | |
6891 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6892 | { | |
b224e962 | 6893 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 6894 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 6895 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6896 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6897 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6898 | if (tinsn->literal_space != 0) | |
6899 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6900 | ||
6901 | if (tinsn->subtype == RELAX_NARROW) | |
6902 | assert (vinsn->num_slots == 1); | |
6903 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6904 | is_jump = TRUE; | |
6905 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6906 | is_branch = TRUE; | |
6907 | ||
e7da6241 BW |
6908 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6909 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6910 | finish_frag = TRUE; |
6911 | } | |
6912 | ||
6913 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6914 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6915 | |
6916 | if (finish_frag) | |
6917 | { | |
6918 | frag_variant (rs_machine_dependent, | |
6919 | extra_space, extra_space, RELAX_SLOTS, | |
6920 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6921 | xtensa_set_frag_assembly_state (frag_now); | |
6922 | } | |
6923 | ||
6924 | /* Special cases for loops: | |
6925 | close_loop_end should be inserted AFTER short_loop. | |
6926 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6927 | when converting them. */ | |
6928 | ||
6929 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 6930 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
6931 | && !vinsn->slots[0].is_specific_opcode) |
6932 | { | |
6933 | if (workaround_short_loop && use_transform ()) | |
6934 | { | |
6935 | maybe_has_short_loop = TRUE; | |
6936 | frag_now->tc_frag_data.is_insn = TRUE; | |
6937 | frag_var (rs_machine_dependent, 4, 4, | |
6938 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6939 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6940 | frag_now->tc_frag_data.is_insn = TRUE; | |
6941 | frag_var (rs_machine_dependent, 4, 4, | |
6942 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6943 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6944 | } | |
6945 | ||
6946 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6947 | loop at least 12 bytes away from another loop's end. */ | |
6948 | if (workaround_close_loop_end && use_transform ()) | |
6949 | { | |
6950 | maybe_has_close_loop_end = TRUE; | |
6951 | frag_now->tc_frag_data.is_insn = TRUE; | |
6952 | frag_var (rs_machine_dependent, 12, 12, | |
6953 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6954 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6955 | } | |
6956 | } | |
6957 | ||
6958 | if (use_transform ()) | |
6959 | { | |
6960 | if (is_jump) | |
6961 | { | |
6962 | assert (finish_frag); | |
6963 | frag_var (rs_machine_dependent, | |
6964 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6965 | RELAX_UNREACHABLE, | |
6966 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6967 | xtensa_set_frag_assembly_state (frag_now); | |
6968 | } | |
7b1cc377 | 6969 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6970 | { |
6971 | assert (finish_frag); | |
6972 | frag_var (rs_machine_dependent, | |
6973 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6974 | RELAX_MAYBE_UNREACHABLE, | |
6975 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6976 | xtensa_set_frag_assembly_state (frag_now); | |
6977 | frag_var (rs_machine_dependent, | |
6978 | 0, 0, | |
6979 | RELAX_MAYBE_DESIRE_ALIGN, | |
6980 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6981 | xtensa_set_frag_assembly_state (frag_now); | |
6982 | } | |
6983 | } | |
6984 | ||
6985 | /* Now, if the original opcode was a call... */ | |
6986 | if (do_align_targets () | |
6987 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6988 | { | |
b08b5071 | 6989 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6990 | frag_now->tc_frag_data.is_insn = TRUE; |
6991 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6992 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6993 | xtensa_set_frag_assembly_state (frag_now); | |
6994 | } | |
6995 | ||
6996 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6997 | { | |
6998 | frag_wane (frag_now); | |
6999 | frag_new (0); | |
7000 | xtensa_set_frag_assembly_state (frag_now); | |
7001 | } | |
7002 | } | |
7003 | ||
7004 | \f | |
7fa3d080 BW |
7005 | /* xtensa_end and helper functions. */ |
7006 | ||
7007 | static void xtensa_cleanup_align_frags (void); | |
7008 | static void xtensa_fix_target_frags (void); | |
7009 | static void xtensa_mark_narrow_branches (void); | |
7010 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7011 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7012 | static void xtensa_fix_a0_b_retw_frags (void); |
7013 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7014 | static void xtensa_fix_close_loop_end_frags (void); | |
7015 | static void xtensa_fix_short_loop_frags (void); | |
7016 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7017 | static void xtensa_add_config_info (void); |
7fa3d080 | 7018 | |
43cd72b9 | 7019 | void |
7fa3d080 | 7020 | xtensa_end (void) |
43cd72b9 BW |
7021 | { |
7022 | directive_balance (); | |
7023 | xtensa_flush_pending_output (); | |
7024 | ||
7025 | past_xtensa_end = TRUE; | |
7026 | ||
7027 | xtensa_move_literals (); | |
7028 | ||
7029 | xtensa_reorder_segments (); | |
7030 | xtensa_cleanup_align_frags (); | |
7031 | xtensa_fix_target_frags (); | |
7032 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7033 | xtensa_fix_a0_b_retw_frags (); | |
7034 | if (workaround_b_j_loop_end) | |
7035 | xtensa_fix_b_j_loop_end_frags (); | |
7036 | ||
7037 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7038 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7039 | xtensa_fix_close_loop_end_frags (); | |
7040 | ||
7041 | if (workaround_short_loop && maybe_has_short_loop) | |
7042 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7043 | if (align_targets) |
7044 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7045 | xtensa_mark_zcl_first_insns (); |
7046 | ||
7047 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7048 | |
7049 | xtensa_add_config_info (); | |
43cd72b9 BW |
7050 | } |
7051 | ||
7052 | ||
7053 | static void | |
7fa3d080 | 7054 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7055 | { |
7056 | frchainS *frchP; | |
c9049d30 | 7057 | asection *s; |
43cd72b9 | 7058 | |
c9049d30 AM |
7059 | for (s = stdoutput->sections; s; s = s->next) |
7060 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7061 | { | |
7062 | fragS *fragP; | |
7063 | /* Walk over all of the fragments in a subsection. */ | |
7064 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7065 | { | |
7066 | if ((fragP->fr_type == rs_align | |
7067 | || fragP->fr_type == rs_align_code | |
7068 | || (fragP->fr_type == rs_machine_dependent | |
7069 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7070 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7071 | && fragP->fr_fix == 0) | |
7072 | { | |
7073 | fragS *next = fragP->fr_next; | |
7074 | ||
7075 | while (next | |
7076 | && next->fr_fix == 0 | |
7077 | && next->fr_type == rs_machine_dependent | |
7078 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7079 | { | |
7080 | frag_wane (next); | |
7081 | next = next->fr_next; | |
7082 | } | |
7083 | } | |
7084 | /* If we don't widen branch targets, then they | |
7085 | will be easier to align. */ | |
7086 | if (fragP->tc_frag_data.is_branch_target | |
7087 | && fragP->fr_opcode == fragP->fr_literal | |
7088 | && fragP->fr_type == rs_machine_dependent | |
7089 | && fragP->fr_subtype == RELAX_SLOTS | |
7090 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7091 | frag_wane (fragP); | |
7092 | if (fragP->fr_type == rs_machine_dependent | |
7093 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7094 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7095 | } | |
7096 | } | |
43cd72b9 BW |
7097 | } |
7098 | ||
7099 | ||
7100 | /* Re-process all of the fragments looking to convert all of the | |
7101 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7102 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7103 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7104 | |
43cd72b9 | 7105 | static void |
7fa3d080 | 7106 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7107 | { |
7108 | frchainS *frchP; | |
c9049d30 | 7109 | asection *s; |
e0001a05 NC |
7110 | |
7111 | /* When this routine is called, all of the subsections are still intact | |
7112 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7113 | for (s = stdoutput->sections; s; s = s->next) |
7114 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7115 | { | |
7116 | fragS *fragP; | |
e0001a05 | 7117 | |
c9049d30 AM |
7118 | /* Walk over all of the fragments in a subsection. */ |
7119 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7120 | { | |
7121 | if (fragP->fr_type == rs_machine_dependent | |
7122 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7123 | { | |
7124 | if (next_frag_is_branch_target (fragP)) | |
7125 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7126 | else | |
7127 | frag_wane (fragP); | |
7128 | } | |
7129 | } | |
7130 | } | |
e0001a05 NC |
7131 | } |
7132 | ||
7133 | ||
7fa3d080 BW |
7134 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7135 | ||
43cd72b9 | 7136 | static void |
7fa3d080 | 7137 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7138 | { |
7139 | frchainS *frchP; | |
c9049d30 | 7140 | asection *s; |
43cd72b9 | 7141 | |
c9049d30 AM |
7142 | for (s = stdoutput->sections; s; s = s->next) |
7143 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7144 | { | |
7145 | fragS *fragP; | |
7146 | /* Walk over all of the fragments in a subsection. */ | |
7147 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7148 | { | |
7149 | if (fragP->fr_type == rs_machine_dependent | |
7150 | && fragP->fr_subtype == RELAX_SLOTS | |
7151 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7152 | { | |
7153 | vliw_insn vinsn; | |
7154 | ||
7155 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7156 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7157 | ||
7158 | if (vinsn.num_slots == 1 | |
7159 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7160 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7161 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7162 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7163 | &vinsn.slots[0])) | |
7164 | { | |
7165 | fragP->fr_subtype = RELAX_SLOTS; | |
7166 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7167 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7168 | } | |
7169 | } | |
7170 | } | |
7171 | } | |
43cd72b9 BW |
7172 | } |
7173 | ||
7174 | ||
7175 | /* A branch is typically widened only when its target is out of | |
7176 | range. However, we would like to widen them to align a subsequent | |
7177 | branch target when possible. | |
7178 | ||
7179 | Because the branch relaxation code is so convoluted, the optimal solution | |
7180 | (combining the two cases) is difficult to get right in all circumstances. | |
7181 | We therefore go with an "almost as good" solution, where we only | |
7182 | use for alignment narrow branches that definitely will not expand to a | |
7183 | jump and a branch. These functions find and mark these cases. */ | |
7184 | ||
a67517f4 BW |
7185 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7186 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7187 | We start counting beginning with the frag after the 2-byte branch, so the | |
7188 | maximum offset is (4 - 2) + 63 = 65. */ | |
7189 | #define MAX_IMMED6 65 | |
43cd72b9 | 7190 | |
d77b99c9 | 7191 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7192 | |
43cd72b9 | 7193 | static bfd_boolean |
7fa3d080 | 7194 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7195 | { |
7196 | const expressionS *expr = &tinsn->tok[1]; | |
7197 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7198 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7199 | fragS *target_frag; |
7200 | ||
7201 | if (expr->X_op != O_symbol) | |
7202 | return FALSE; | |
7203 | ||
7204 | target_frag = symbol_get_frag (symbolP); | |
7205 | ||
43cd72b9 BW |
7206 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7207 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7208 | return FALSE; | |
7209 | ||
7210 | /* The branch doesn't branch over it's own frag, | |
7211 | but over the subsequent ones. */ | |
7212 | fragP = fragP->fr_next; | |
7213 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7214 | { | |
7215 | max_distance += unrelaxed_frag_max_size (fragP); | |
7216 | fragP = fragP->fr_next; | |
7217 | } | |
7218 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7219 | return TRUE; | |
e0001a05 NC |
7220 | return FALSE; |
7221 | } | |
7222 | ||
7223 | ||
43cd72b9 | 7224 | static void |
7fa3d080 | 7225 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7226 | { |
7227 | frchainS *frchP; | |
c9049d30 | 7228 | asection *s; |
43cd72b9 | 7229 | |
c9049d30 AM |
7230 | for (s = stdoutput->sections; s; s = s->next) |
7231 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7232 | { | |
7233 | fragS *fragP; | |
7234 | /* Walk over all of the fragments in a subsection. */ | |
7235 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7236 | { | |
7237 | if (fragP->fr_type == rs_machine_dependent | |
7238 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7239 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7240 | { | |
7241 | /* Find the loop frag. */ | |
7242 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7243 | /* Find the first insn frag. */ | |
7244 | targ_frag = next_non_empty_frag (targ_frag); | |
7245 | ||
7246 | /* Of course, sometimes (mostly for toy test cases) a | |
7247 | zero-cost loop instruction is the last in a section. */ | |
7248 | if (targ_frag) | |
7249 | { | |
7250 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7251 | /* Do not widen a frag that is the first instruction of a | |
7252 | zero-cost loop. It makes that loop harder to align. */ | |
7253 | if (targ_frag->fr_type == rs_machine_dependent | |
7254 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7255 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7256 | == RELAX_NARROW)) | |
7257 | { | |
7258 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7259 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7260 | else | |
7261 | { | |
7262 | frag_wane (targ_frag); | |
7263 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7264 | } | |
7265 | } | |
7266 | } | |
7267 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7268 | frag_wane (fragP); | |
7269 | } | |
7270 | } | |
7271 | } | |
43cd72b9 BW |
7272 | } |
7273 | ||
7274 | ||
fb227da0 BW |
7275 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
7276 | sleb128 value, the linker is unable to adjust that value to account for | |
7277 | link-time relaxation. Mark all the code between such symbols so that | |
7278 | its size cannot be changed by linker relaxation. */ | |
7279 | ||
6a7eedfe BW |
7280 | static void |
7281 | xtensa_mark_difference_of_two_symbols (void) | |
7282 | { | |
7283 | symbolS *expr_sym; | |
7284 | ||
7285 | for (expr_sym = expr_symbols; expr_sym; | |
7286 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) | |
7287 | { | |
7288 | expressionS *expr = symbol_get_value_expression (expr_sym); | |
7289 | ||
7290 | if (expr->X_op == O_subtract) | |
7291 | { | |
7292 | symbolS *left = expr->X_add_symbol; | |
7293 | symbolS *right = expr->X_op_symbol; | |
7294 | ||
7295 | /* Difference of two symbols not in the same section | |
7296 | are handled with relocations in the linker. */ | |
7297 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7298 | { | |
7299 | fragS *start; | |
7300 | fragS *end; | |
7301 | ||
7302 | if (symbol_get_frag (left)->fr_address | |
7303 | <= symbol_get_frag (right)->fr_address) | |
7304 | { | |
7305 | start = symbol_get_frag (left); | |
7306 | end = symbol_get_frag (right); | |
7307 | } | |
7308 | else | |
7309 | { | |
7310 | start = symbol_get_frag (right); | |
7311 | end = symbol_get_frag (left); | |
7312 | } | |
7313 | do | |
7314 | { | |
7315 | start->tc_frag_data.is_no_transform = 1; | |
7316 | start = start->fr_next; | |
7317 | } | |
7318 | while (start && start->fr_address < end->fr_address); | |
7319 | } | |
7320 | } | |
7321 | } | |
7322 | } | |
7323 | ||
7324 | ||
e0001a05 NC |
7325 | /* Re-process all of the fragments looking to convert all of the |
7326 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7327 | conditional branch or a retw/retw.n, convert this frag to one that | |
7328 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7329 | ||
7fa3d080 BW |
7330 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7331 | ||
e0001a05 | 7332 | static void |
7fa3d080 | 7333 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7334 | { |
7335 | frchainS *frchP; | |
c9049d30 | 7336 | asection *s; |
e0001a05 NC |
7337 | |
7338 | /* When this routine is called, all of the subsections are still intact | |
7339 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7340 | for (s = stdoutput->sections; s; s = s->next) |
7341 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7342 | { | |
7343 | fragS *fragP; | |
e0001a05 | 7344 | |
c9049d30 AM |
7345 | /* Walk over all of the fragments in a subsection. */ |
7346 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7347 | { | |
7348 | if (fragP->fr_type == rs_machine_dependent | |
7349 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7350 | { | |
7351 | if (next_instrs_are_b_retw (fragP)) | |
7352 | { | |
7353 | if (fragP->tc_frag_data.is_no_transform) | |
7354 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7355 | else | |
7356 | relax_frag_add_nop (fragP); | |
7357 | } | |
7358 | frag_wane (fragP); | |
7359 | } | |
7360 | } | |
7361 | } | |
e0001a05 NC |
7362 | } |
7363 | ||
7364 | ||
7fa3d080 BW |
7365 | static bfd_boolean |
7366 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7367 | { |
7368 | xtensa_opcode opcode; | |
43cd72b9 | 7369 | xtensa_format fmt; |
e0001a05 NC |
7370 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7371 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7372 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7373 | xtensa_isa isa = xtensa_default_isa; |
7374 | int offset = 0; | |
43cd72b9 BW |
7375 | int slot; |
7376 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7377 | |
7378 | if (!insnbuf) | |
43cd72b9 BW |
7379 | { |
7380 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7381 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7382 | } | |
e0001a05 NC |
7383 | |
7384 | if (next_fragP == NULL) | |
7385 | return FALSE; | |
7386 | ||
7387 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7388 | xtensa_insnbuf_from_chars |
7389 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7390 | fmt = xtensa_format_decode (isa, insnbuf); |
7391 | if (fmt == XTENSA_UNDEFINED) | |
7392 | return FALSE; | |
7393 | ||
7394 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7395 | { | |
7396 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7397 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7398 | ||
7399 | branch_seen = (branch_seen | |
7400 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7401 | } | |
e0001a05 | 7402 | |
43cd72b9 | 7403 | if (!branch_seen) |
e0001a05 NC |
7404 | return FALSE; |
7405 | ||
43cd72b9 | 7406 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7407 | if (offset == next_fragP->fr_fix) |
7408 | { | |
7409 | next_fragP = next_non_empty_frag (next_fragP); | |
7410 | offset = 0; | |
7411 | } | |
43cd72b9 | 7412 | |
e0001a05 NC |
7413 | if (next_fragP == NULL) |
7414 | return FALSE; | |
7415 | ||
7416 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7417 | xtensa_insnbuf_from_chars |
7418 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7419 | fmt = xtensa_format_decode (isa, insnbuf); |
7420 | ||
7421 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7422 | have no problems. */ | |
7423 | if (fmt == XTENSA_UNDEFINED | |
7424 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7425 | return FALSE; | |
7426 | ||
7427 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7428 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7429 | |
b08b5071 | 7430 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7431 | return TRUE; |
43cd72b9 | 7432 | |
e0001a05 NC |
7433 | return FALSE; |
7434 | } | |
7435 | ||
7436 | ||
7437 | /* Re-process all of the fragments looking to convert all of the | |
7438 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7439 | loop end label, convert this frag to one that will generate a NOP. | |
7440 | In any case close it off with a .fill 0. */ | |
7441 | ||
7fa3d080 BW |
7442 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7443 | ||
e0001a05 | 7444 | static void |
7fa3d080 | 7445 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7446 | { |
7447 | frchainS *frchP; | |
c9049d30 | 7448 | asection *s; |
e0001a05 NC |
7449 | |
7450 | /* When this routine is called, all of the subsections are still intact | |
7451 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7452 | for (s = stdoutput->sections; s; s = s->next) |
7453 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7454 | { | |
7455 | fragS *fragP; | |
e0001a05 | 7456 | |
c9049d30 AM |
7457 | /* Walk over all of the fragments in a subsection. */ |
7458 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7459 | { | |
7460 | if (fragP->fr_type == rs_machine_dependent | |
7461 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7462 | { | |
7463 | if (next_instr_is_loop_end (fragP)) | |
7464 | { | |
7465 | if (fragP->tc_frag_data.is_no_transform) | |
7466 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7467 | else | |
7468 | relax_frag_add_nop (fragP); | |
7469 | } | |
7470 | frag_wane (fragP); | |
7471 | } | |
7472 | } | |
7473 | } | |
e0001a05 NC |
7474 | } |
7475 | ||
7476 | ||
7fa3d080 BW |
7477 | static bfd_boolean |
7478 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7479 | { |
7480 | const fragS *next_fragP; | |
7481 | ||
7482 | if (next_frag_is_loop_target (fragP)) | |
7483 | return FALSE; | |
7484 | ||
7485 | next_fragP = next_non_empty_frag (fragP); | |
7486 | if (next_fragP == NULL) | |
7487 | return FALSE; | |
7488 | ||
7489 | if (!next_frag_is_loop_target (next_fragP)) | |
7490 | return FALSE; | |
7491 | ||
7492 | /* If the size is >= 3 then there is more than one instruction here. | |
7493 | The hardware bug will not fire. */ | |
7494 | if (next_fragP->fr_fix > 3) | |
7495 | return FALSE; | |
7496 | ||
7497 | return TRUE; | |
7498 | } | |
7499 | ||
7500 | ||
7501 | /* Re-process all of the fragments looking to convert all of the | |
7502 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7503 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7504 | make it at least 12 bytes away. In any case close it off with a | |
7505 | .fill 0. */ | |
7506 | ||
d77b99c9 | 7507 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7508 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7509 | |
e0001a05 | 7510 | static void |
7fa3d080 | 7511 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7512 | { |
7513 | frchainS *frchP; | |
c9049d30 | 7514 | asection *s; |
e0001a05 NC |
7515 | |
7516 | /* When this routine is called, all of the subsections are still intact | |
7517 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7518 | for (s = stdoutput->sections; s; s = s->next) |
7519 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7520 | { | |
7521 | fragS *fragP; | |
e0001a05 | 7522 | |
c9049d30 | 7523 | fragS *current_target = NULL; |
e0001a05 | 7524 | |
c9049d30 AM |
7525 | /* Walk over all of the fragments in a subsection. */ |
7526 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7527 | { | |
7528 | if (fragP->fr_type == rs_machine_dependent | |
7529 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7530 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7531 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7532 | |
c9049d30 AM |
7533 | if (current_target |
7534 | && fragP->fr_type == rs_machine_dependent | |
7535 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7536 | { | |
7537 | offsetT min_bytes; | |
7538 | int bytes_added = 0; | |
e0001a05 NC |
7539 | |
7540 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7541 | /* Max out at 12. */ |
7542 | min_bytes = min_bytes_to_other_loop_end | |
7543 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7544 | ||
7545 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7546 | { | |
7547 | if (fragP->tc_frag_data.is_no_transform) | |
7548 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7549 | else | |
7550 | { | |
7551 | while (min_bytes + bytes_added | |
7552 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7553 | { | |
7554 | int length = 3; | |
7555 | ||
7556 | if (fragP->fr_var < length) | |
7557 | as_fatal (_("fr_var %lu < length %d"), | |
7558 | (long) fragP->fr_var, length); | |
7559 | else | |
7560 | { | |
7561 | assemble_nop (length, | |
7562 | fragP->fr_literal + fragP->fr_fix); | |
7563 | fragP->fr_fix += length; | |
7564 | fragP->fr_var -= length; | |
7565 | } | |
7566 | bytes_added += length; | |
7567 | } | |
7568 | } | |
7569 | } | |
7570 | frag_wane (fragP); | |
7571 | } | |
7572 | assert (fragP->fr_type != rs_machine_dependent | |
7573 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7574 | } | |
7575 | } | |
e0001a05 NC |
7576 | } |
7577 | ||
7578 | ||
d77b99c9 | 7579 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7580 | |
d77b99c9 | 7581 | static offsetT |
7fa3d080 BW |
7582 | min_bytes_to_other_loop_end (fragS *fragP, |
7583 | fragS *current_target, | |
d77b99c9 | 7584 | offsetT max_size) |
e0001a05 | 7585 | { |
d77b99c9 | 7586 | offsetT offset = 0; |
e0001a05 NC |
7587 | fragS *current_fragP; |
7588 | ||
7589 | for (current_fragP = fragP; | |
7590 | current_fragP; | |
7591 | current_fragP = current_fragP->fr_next) | |
7592 | { | |
7593 | if (current_fragP->tc_frag_data.is_loop_target | |
7594 | && current_fragP != current_target) | |
05d58145 | 7595 | return offset; |
e0001a05 NC |
7596 | |
7597 | offset += unrelaxed_frag_min_size (current_fragP); | |
7598 | ||
05d58145 | 7599 | if (offset >= max_size) |
e0001a05 NC |
7600 | return max_size; |
7601 | } | |
7602 | return max_size; | |
7603 | } | |
7604 | ||
7605 | ||
d77b99c9 | 7606 | static offsetT |
7fa3d080 | 7607 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7608 | { |
d77b99c9 | 7609 | offsetT size = fragP->fr_fix; |
e0001a05 | 7610 | |
d77b99c9 | 7611 | /* Add fill size. */ |
e0001a05 NC |
7612 | if (fragP->fr_type == rs_fill) |
7613 | size += fragP->fr_offset; | |
7614 | ||
7615 | return size; | |
7616 | } | |
7617 | ||
7618 | ||
d77b99c9 | 7619 | static offsetT |
7fa3d080 | 7620 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7621 | { |
d77b99c9 | 7622 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7623 | switch (fragP->fr_type) |
7624 | { | |
7625 | case 0: | |
c138bc38 | 7626 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7627 | end up with type 0. */ |
7628 | break; | |
7629 | case rs_fill: | |
7630 | case rs_org: | |
7631 | case rs_space: | |
7632 | size += fragP->fr_offset; | |
7633 | break; | |
7634 | case rs_align: | |
7635 | case rs_align_code: | |
7636 | case rs_align_test: | |
7637 | case rs_leb128: | |
7638 | case rs_cfa: | |
7639 | case rs_dwarf2dbg: | |
7640 | /* No further adjustments needed. */ | |
7641 | break; | |
7642 | case rs_machine_dependent: | |
7643 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7644 | size += fragP->fr_var; | |
7645 | break; | |
7646 | default: | |
7647 | /* We had darn well better know how big it is. */ | |
7648 | assert (0); | |
7649 | break; | |
7650 | } | |
7651 | ||
7652 | return size; | |
7653 | } | |
7654 | ||
7655 | ||
e0001a05 NC |
7656 | /* Re-process all of the fragments looking to convert all |
7657 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7658 | ||
7659 | A) | |
7660 | 1) the instruction size count to the loop end label | |
7661 | is too short (<= 2 instructions), | |
7662 | 2) loop has a jump or branch in it | |
7663 | ||
7664 | or B) | |
43cd72b9 | 7665 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7666 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7667 | 3) the instruction size count to the loop end label is too short | |
7668 | (<= 2 instructions) | |
7669 | then convert this frag (and maybe the next one) to generate a NOP. | |
7670 | In any case close it off with a .fill 0. */ | |
7671 | ||
d77b99c9 | 7672 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7673 | static bfd_boolean branch_before_loop_end (fragS *); |
7674 | ||
e0001a05 | 7675 | static void |
7fa3d080 | 7676 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7677 | { |
7678 | frchainS *frchP; | |
c9049d30 | 7679 | asection *s; |
e0001a05 NC |
7680 | |
7681 | /* When this routine is called, all of the subsections are still intact | |
7682 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7683 | for (s = stdoutput->sections; s; s = s->next) |
7684 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7685 | { | |
7686 | fragS *fragP; | |
7687 | fragS *current_target = NULL; | |
7688 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7689 | |
c9049d30 AM |
7690 | /* Walk over all of the fragments in a subsection. */ |
7691 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7692 | { | |
7693 | if (fragP->fr_type == rs_machine_dependent | |
7694 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7695 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7696 | { | |
7697 | TInsn t_insn; | |
7698 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7699 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7700 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7701 | current_opcode = t_insn.opcode; | |
7702 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7703 | current_opcode) == 1); |
c9049d30 | 7704 | } |
e0001a05 | 7705 | |
c9049d30 AM |
7706 | if (fragP->fr_type == rs_machine_dependent |
7707 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7708 | { | |
7709 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7710 | && (branch_before_loop_end (fragP->fr_next) | |
7711 | || (workaround_all_short_loops | |
7712 | && current_opcode != XTENSA_UNDEFINED | |
7713 | && current_opcode != xtensa_loop_opcode))) | |
7714 | { | |
7715 | if (fragP->tc_frag_data.is_no_transform) | |
7716 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7717 | else | |
7718 | relax_frag_add_nop (fragP); | |
7719 | } | |
7720 | frag_wane (fragP); | |
7721 | } | |
7722 | } | |
7723 | } | |
e0001a05 NC |
7724 | } |
7725 | ||
7726 | ||
d77b99c9 | 7727 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7728 | |
d77b99c9 | 7729 | static int |
7fa3d080 BW |
7730 | count_insns_to_loop_end (fragS *base_fragP, |
7731 | bfd_boolean count_relax_add, | |
d77b99c9 | 7732 | int max_count) |
e0001a05 NC |
7733 | { |
7734 | fragS *fragP = NULL; | |
d77b99c9 | 7735 | int insn_count = 0; |
e0001a05 NC |
7736 | |
7737 | fragP = base_fragP; | |
7738 | ||
7739 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7740 | { | |
7741 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7742 | if (insn_count >= max_count) | |
7743 | return max_count; | |
7744 | ||
7745 | if (count_relax_add) | |
7746 | { | |
7747 | if (fragP->fr_type == rs_machine_dependent | |
7748 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7749 | { | |
7750 | /* In order to add the appropriate number of | |
7751 | NOPs, we count an instruction for downstream | |
7752 | occurrences. */ | |
7753 | insn_count++; | |
7754 | if (insn_count >= max_count) | |
7755 | return max_count; | |
7756 | } | |
7757 | } | |
7758 | } | |
7759 | return insn_count; | |
7760 | } | |
7761 | ||
7762 | ||
d77b99c9 | 7763 | static int |
7fa3d080 | 7764 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7765 | { |
43cd72b9 BW |
7766 | xtensa_isa isa = xtensa_default_isa; |
7767 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7768 | int insn_count = 0; |
e0001a05 NC |
7769 | int offset = 0; |
7770 | ||
7771 | if (!fragP->tc_frag_data.is_insn) | |
7772 | return insn_count; | |
7773 | ||
43cd72b9 BW |
7774 | if (!insnbuf) |
7775 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7776 | ||
e0001a05 NC |
7777 | /* Decode the fixed instructions. */ |
7778 | while (offset < fragP->fr_fix) | |
7779 | { | |
43cd72b9 BW |
7780 | xtensa_format fmt; |
7781 | ||
d77b99c9 BW |
7782 | xtensa_insnbuf_from_chars |
7783 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7784 | fmt = xtensa_format_decode (isa, insnbuf); |
7785 | ||
7786 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7787 | { |
7788 | as_fatal (_("undecodable instruction in instruction frag")); | |
7789 | return insn_count; | |
7790 | } | |
43cd72b9 | 7791 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7792 | insn_count++; |
7793 | } | |
7794 | ||
7795 | return insn_count; | |
7796 | } | |
7797 | ||
7798 | ||
7fa3d080 BW |
7799 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7800 | ||
43cd72b9 | 7801 | static bfd_boolean |
7fa3d080 | 7802 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7803 | { |
7804 | fragS *fragP; | |
7805 | ||
7806 | for (fragP = base_fragP; | |
7807 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7808 | fragP = fragP->fr_next) | |
7809 | { | |
7810 | if (unrelaxed_frag_has_b_j (fragP)) | |
7811 | return TRUE; | |
7812 | } | |
7813 | return FALSE; | |
7814 | } | |
7815 | ||
7816 | ||
43cd72b9 | 7817 | static bfd_boolean |
7fa3d080 | 7818 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7819 | { |
43cd72b9 BW |
7820 | static xtensa_insnbuf insnbuf = NULL; |
7821 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7822 | int offset = 0; |
7823 | ||
7824 | if (!fragP->tc_frag_data.is_insn) | |
7825 | return FALSE; | |
7826 | ||
43cd72b9 BW |
7827 | if (!insnbuf) |
7828 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7829 | ||
e0001a05 NC |
7830 | /* Decode the fixed instructions. */ |
7831 | while (offset < fragP->fr_fix) | |
7832 | { | |
43cd72b9 BW |
7833 | xtensa_format fmt; |
7834 | int slot; | |
7835 | ||
d77b99c9 BW |
7836 | xtensa_insnbuf_from_chars |
7837 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7838 | fmt = xtensa_format_decode (isa, insnbuf); |
7839 | if (fmt == XTENSA_UNDEFINED) | |
7840 | return FALSE; | |
7841 | ||
7842 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7843 | { |
43cd72b9 BW |
7844 | xtensa_opcode opcode = |
7845 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7846 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7847 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7848 | return TRUE; | |
e0001a05 | 7849 | } |
43cd72b9 | 7850 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7851 | } |
7852 | return FALSE; | |
7853 | } | |
7854 | ||
7855 | ||
7856 | /* Checks to be made after initial assembly but before relaxation. */ | |
7857 | ||
7fa3d080 BW |
7858 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7859 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7860 | ||
e0001a05 | 7861 | static void |
7fa3d080 | 7862 | xtensa_sanity_check (void) |
e0001a05 NC |
7863 | { |
7864 | char *file_name; | |
d77b99c9 | 7865 | unsigned line; |
e0001a05 | 7866 | frchainS *frchP; |
c9049d30 | 7867 | asection *s; |
e0001a05 NC |
7868 | |
7869 | as_where (&file_name, &line); | |
c9049d30 AM |
7870 | for (s = stdoutput->sections; s; s = s->next) |
7871 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7872 | { | |
7873 | fragS *fragP; | |
e0001a05 | 7874 | |
c9049d30 AM |
7875 | /* Walk over all of the fragments in a subsection. */ |
7876 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7877 | { | |
c9049d30 | 7878 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
7879 | && fragP->fr_subtype == RELAX_SLOTS |
7880 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
7881 | { |
7882 | static xtensa_insnbuf insnbuf = NULL; | |
7883 | TInsn t_insn; | |
7884 | ||
7885 | if (fragP->fr_opcode != NULL) | |
7886 | { | |
7887 | if (!insnbuf) | |
7888 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7889 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7890 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
7891 | ||
7892 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7893 | t_insn.opcode) == 1) | |
7894 | { | |
7895 | if (is_empty_loop (&t_insn, fragP)) | |
7896 | { | |
7897 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7898 | as_bad (_("invalid empty loop")); | |
7899 | } | |
7900 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7901 | { | |
7902 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7903 | as_bad (_("loop target does not follow " | |
7904 | "loop instruction in section")); | |
7905 | } | |
7906 | } | |
7907 | } | |
7908 | } | |
7909 | } | |
7910 | } | |
e0001a05 NC |
7911 | new_logical_line (file_name, line); |
7912 | } | |
7913 | ||
7914 | ||
7915 | #define LOOP_IMMED_OPN 1 | |
7916 | ||
43cd72b9 | 7917 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7918 | |
7fa3d080 BW |
7919 | static bfd_boolean |
7920 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7921 | { |
7922 | const expressionS *expr; | |
7923 | symbolS *symbolP; | |
7924 | fragS *next_fragP; | |
7925 | ||
7926 | if (insn->insn_type != ITYPE_INSN) | |
7927 | return FALSE; | |
7928 | ||
43cd72b9 | 7929 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7930 | return FALSE; |
7931 | ||
7932 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7933 | return FALSE; | |
7934 | ||
7935 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7936 | ||
7937 | if (expr->X_op != O_symbol) | |
7938 | return FALSE; | |
7939 | ||
7940 | symbolP = expr->X_add_symbol; | |
7941 | if (!symbolP) | |
7942 | return FALSE; | |
7943 | ||
7944 | if (symbol_get_frag (symbolP) == NULL) | |
7945 | return FALSE; | |
7946 | ||
7947 | if (S_GET_VALUE (symbolP) != 0) | |
7948 | return FALSE; | |
7949 | ||
7950 | /* Walk through the zero-size fragments from this one. If we find | |
7951 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7952 | |
e0001a05 NC |
7953 | for (next_fragP = fragP->fr_next; |
7954 | next_fragP != NULL; | |
7955 | next_fragP = next_fragP->fr_next) | |
7956 | { | |
7957 | if (next_fragP == symbol_get_frag (symbolP)) | |
7958 | return TRUE; | |
7959 | if (next_fragP->fr_fix != 0) | |
7960 | return FALSE; | |
7961 | } | |
7962 | return FALSE; | |
7963 | } | |
7964 | ||
7965 | ||
7fa3d080 BW |
7966 | static bfd_boolean |
7967 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7968 | { |
7969 | const expressionS *expr; | |
7970 | symbolS *symbolP; | |
7971 | fragS *next_fragP; | |
7972 | ||
7973 | if (insn->insn_type != ITYPE_INSN) | |
7974 | return FALSE; | |
7975 | ||
64b607e6 | 7976 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7977 | return FALSE; |
7978 | ||
7979 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7980 | return FALSE; | |
7981 | ||
7982 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7983 | ||
7984 | if (expr->X_op != O_symbol) | |
7985 | return FALSE; | |
7986 | ||
7987 | symbolP = expr->X_add_symbol; | |
7988 | if (!symbolP) | |
7989 | return FALSE; | |
7990 | ||
7991 | if (symbol_get_frag (symbolP) == NULL) | |
7992 | return FALSE; | |
7993 | ||
7994 | /* Walk through fragments until we find the target. | |
7995 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7996 | |
e0001a05 NC |
7997 | for (next_fragP = fragP->fr_next; |
7998 | next_fragP != NULL; | |
7999 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8000 | { |
8001 | if (next_fragP == symbol_get_frag (symbolP)) | |
8002 | return TRUE; | |
8003 | } | |
e0001a05 NC |
8004 | |
8005 | return FALSE; | |
8006 | } | |
8007 | ||
2caa7ca0 BW |
8008 | |
8009 | #define XTINFO_NAME "Xtensa_Info" | |
8010 | #define XTINFO_NAMESZ 12 | |
8011 | #define XTINFO_TYPE 1 | |
8012 | ||
8013 | static void | |
8014 | xtensa_add_config_info (void) | |
8015 | { | |
8016 | asection *info_sec; | |
8017 | char *data, *p; | |
8018 | int sz; | |
8019 | ||
8020 | info_sec = subseg_new (".xtensa.info", 0); | |
8021 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8022 | ||
8023 | data = xmalloc (100); | |
8024 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
8025 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8026 | sz = strlen (data) + 1; | |
8027 | ||
8028 | /* Add enough null terminators to pad to a word boundary. */ | |
8029 | do | |
8030 | data[sz++] = 0; | |
8031 | while ((sz & 3) != 0); | |
8032 | ||
8033 | /* Follow the standard note section layout: | |
8034 | First write the length of the name string. */ | |
8035 | p = frag_more (4); | |
8036 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8037 | ||
8038 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8039 | p = frag_more (4); | |
8040 | md_number_to_chars (p, (valueT) sz, 4); | |
8041 | ||
8042 | /* Write the note type. */ | |
8043 | p = frag_more (4); | |
8044 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8045 | ||
8046 | /* Write the name field. */ | |
8047 | p = frag_more (XTINFO_NAMESZ); | |
8048 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8049 | ||
8050 | /* Finally, write the descriptor. */ | |
8051 | p = frag_more (sz); | |
8052 | memcpy (p, data, sz); | |
8053 | ||
8054 | free (data); | |
8055 | } | |
8056 | ||
e0001a05 NC |
8057 | \f |
8058 | /* Alignment Functions. */ | |
8059 | ||
d77b99c9 BW |
8060 | static int |
8061 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8062 | { |
03aaa593 BW |
8063 | if (target_size <= 4) |
8064 | return 2; | |
8065 | assert (target_size == 8); | |
8066 | return 3; | |
e0001a05 NC |
8067 | } |
8068 | ||
8069 | ||
d77b99c9 | 8070 | static int |
7fa3d080 BW |
8071 | get_text_align_max_fill_size (int align_pow, |
8072 | bfd_boolean use_nops, | |
8073 | bfd_boolean use_no_density) | |
e0001a05 NC |
8074 | { |
8075 | if (!use_nops) | |
8076 | return (1 << align_pow); | |
8077 | if (use_no_density) | |
8078 | return 3 * (1 << align_pow); | |
8079 | ||
8080 | return 1 + (1 << align_pow); | |
8081 | } | |
8082 | ||
8083 | ||
d77b99c9 BW |
8084 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8085 | target instruction of size "target_size" so that it does not cross a | |
8086 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8087 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8088 | be filled by NOP instructions. */ | |
e0001a05 | 8089 | |
d77b99c9 | 8090 | static int |
7fa3d080 BW |
8091 | get_text_align_fill_size (addressT address, |
8092 | int align_pow, | |
8093 | int target_size, | |
8094 | bfd_boolean use_nops, | |
8095 | bfd_boolean use_no_density) | |
e0001a05 | 8096 | { |
d77b99c9 BW |
8097 | addressT alignment, fill, fill_limit, fill_step; |
8098 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8099 | |
d77b99c9 BW |
8100 | alignment = (1 << align_pow); |
8101 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 8102 | |
e0001a05 NC |
8103 | if (!use_nops) |
8104 | { | |
d77b99c9 BW |
8105 | fill_limit = alignment; |
8106 | fill_step = 1; | |
e0001a05 | 8107 | } |
d77b99c9 | 8108 | else if (!use_no_density) |
e0001a05 | 8109 | { |
d77b99c9 BW |
8110 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8111 | fill_limit = alignment * 2; | |
8112 | fill_step = 1; | |
8113 | skip_one = TRUE; | |
e0001a05 NC |
8114 | } |
8115 | else | |
8116 | { | |
d77b99c9 BW |
8117 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8118 | fill_limit = alignment * 3; | |
8119 | fill_step = 3; | |
8120 | } | |
e0001a05 | 8121 | |
d77b99c9 BW |
8122 | /* Try all fill sizes until finding one that works. */ |
8123 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8124 | { | |
8125 | if (skip_one && fill == 1) | |
8126 | continue; | |
8127 | if ((address + fill) >> align_pow | |
8128 | == (address + fill + target_size - 1) >> align_pow) | |
8129 | return fill; | |
e0001a05 NC |
8130 | } |
8131 | assert (0); | |
8132 | return 0; | |
8133 | } | |
8134 | ||
8135 | ||
664df4e4 BW |
8136 | static int |
8137 | branch_align_power (segT sec) | |
8138 | { | |
8139 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8140 | is aligned to at least an 8-byte boundary, then a branch target need | |
8141 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8142 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8143 | (which may be insufficient, e.g., if the section has no alignment, but | |
8144 | it's good enough). */ | |
8145 | if (xtensa_fetch_width == 8) | |
8146 | { | |
8147 | if (get_recorded_alignment (sec) >= 3) | |
8148 | return 3; | |
8149 | } | |
8150 | else | |
8151 | assert (xtensa_fetch_width == 4); | |
8152 | ||
8153 | return 2; | |
8154 | } | |
8155 | ||
8156 | ||
e0001a05 NC |
8157 | /* This will assert if it is not possible. */ |
8158 | ||
d77b99c9 BW |
8159 | static int |
8160 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8161 | { |
d77b99c9 BW |
8162 | int count = 0; |
8163 | ||
e0001a05 NC |
8164 | if (use_no_density) |
8165 | { | |
8166 | assert (fill_size % 3 == 0); | |
8167 | return (fill_size / 3); | |
8168 | } | |
8169 | ||
8170 | assert (fill_size != 1); /* Bad argument. */ | |
8171 | ||
8172 | while (fill_size > 1) | |
8173 | { | |
d77b99c9 | 8174 | int insn_size = 3; |
e0001a05 NC |
8175 | if (fill_size == 2 || fill_size == 4) |
8176 | insn_size = 2; | |
8177 | fill_size -= insn_size; | |
8178 | count++; | |
8179 | } | |
8180 | assert (fill_size != 1); /* Bad algorithm. */ | |
8181 | return count; | |
8182 | } | |
8183 | ||
8184 | ||
d77b99c9 BW |
8185 | static int |
8186 | get_text_align_nth_nop_size (offsetT fill_size, | |
8187 | int n, | |
7fa3d080 | 8188 | bfd_boolean use_no_density) |
e0001a05 | 8189 | { |
d77b99c9 | 8190 | int count = 0; |
e0001a05 NC |
8191 | |
8192 | if (use_no_density) | |
8193 | return 3; | |
8194 | ||
d77b99c9 BW |
8195 | assert (fill_size != 1); /* Bad argument. */ |
8196 | ||
e0001a05 NC |
8197 | while (fill_size > 1) |
8198 | { | |
d77b99c9 | 8199 | int insn_size = 3; |
e0001a05 NC |
8200 | if (fill_size == 2 || fill_size == 4) |
8201 | insn_size = 2; | |
8202 | fill_size -= insn_size; | |
8203 | count++; | |
8204 | if (n + 1 == count) | |
8205 | return insn_size; | |
8206 | } | |
8207 | assert (0); | |
8208 | return 0; | |
8209 | } | |
8210 | ||
8211 | ||
8212 | /* For the given fragment, find the appropriate address | |
8213 | for it to begin at if we are using NOPs to align it. */ | |
8214 | ||
8215 | static addressT | |
7fa3d080 | 8216 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8217 | { |
43cd72b9 BW |
8218 | /* The rule is: get next fragment's FIRST instruction. Find |
8219 | the smallest number of bytes that need to be added to | |
8220 | ensure that the next fragment's FIRST instruction will fit | |
8221 | in a single word. | |
c138bc38 | 8222 | |
43cd72b9 BW |
8223 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8224 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8225 | |
43cd72b9 BW |
8226 | If the FIRST instruction MIGHT be relaxed, |
8227 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8228 | |
43cd72b9 BW |
8229 | Note again here that LOOP instructions are not bundleable, |
8230 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8231 | |
d77b99c9 | 8232 | int fill_size = 0; |
43cd72b9 BW |
8233 | int first_insn_size; |
8234 | int loop_insn_size; | |
8235 | addressT pre_opcode_bytes; | |
d77b99c9 | 8236 | int align_power; |
43cd72b9 BW |
8237 | fragS *first_insn; |
8238 | xtensa_opcode opcode; | |
8239 | bfd_boolean is_loop; | |
e0001a05 | 8240 | |
43cd72b9 BW |
8241 | assert (fragP->fr_type == rs_machine_dependent); |
8242 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8243 | |
43cd72b9 BW |
8244 | /* Find the loop frag. */ |
8245 | first_insn = next_non_empty_frag (fragP); | |
8246 | /* Now find the first insn frag. */ | |
8247 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8248 | |
43cd72b9 BW |
8249 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8250 | assert (is_loop); | |
8251 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8252 | |
43cd72b9 BW |
8253 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8254 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8255 | |
43cd72b9 BW |
8256 | /* For loops, the alignment depends on the size of the |
8257 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8258 | |
43cd72b9 | 8259 | if (first_insn == NULL) |
03aaa593 BW |
8260 | first_insn_size = xtensa_fetch_width; |
8261 | else | |
8262 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8263 | |
43cd72b9 | 8264 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8265 | align_power = get_text_align_power (first_insn_size); |
8266 | record_alignment (now_seg, align_power); | |
c138bc38 | 8267 | |
43cd72b9 | 8268 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8269 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8270 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8271 | |
8272 | return address + fill_size; | |
8273 | } | |
8274 | ||
8275 | ||
43cd72b9 BW |
8276 | /* 3 mechanisms for relaxing an alignment: |
8277 | ||
8278 | Align to a power of 2. | |
8279 | Align so the next fragment's instruction does not cross a word boundary. | |
8280 | Align the current instruction so that if the next instruction | |
8281 | were 3 bytes, it would not cross a word boundary. | |
8282 | ||
e0001a05 NC |
8283 | We can align with: |
8284 | ||
43cd72b9 BW |
8285 | zeros - This is easy; always insert zeros. |
8286 | nops - 3-byte and 2-byte instructions | |
8287 | 2 - 2-byte nop | |
8288 | 3 - 3-byte nop | |
8289 | 4 - 2 2-byte nops | |
8290 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8291 | widening - widen previous instructions. */ |
8292 | ||
d77b99c9 BW |
8293 | static offsetT |
8294 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8295 | { |
43cd72b9 BW |
8296 | addressT target_address, loop_insn_offset; |
8297 | int target_size; | |
8298 | xtensa_opcode loop_opcode; | |
8299 | bfd_boolean is_loop; | |
d77b99c9 BW |
8300 | int align_power; |
8301 | offsetT opt_diff; | |
5f9084e9 | 8302 | offsetT branch_align; |
def13efb | 8303 | fragS *loop_frag; |
e0001a05 | 8304 | |
43cd72b9 BW |
8305 | assert (fragP->fr_type == rs_machine_dependent); |
8306 | switch (fragP->fr_subtype) | |
e0001a05 | 8307 | { |
43cd72b9 BW |
8308 | case RELAX_DESIRE_ALIGN: |
8309 | target_size = next_frag_format_size (fragP); | |
8310 | if (target_size == XTENSA_UNDEFINED) | |
8311 | target_size = 3; | |
664df4e4 BW |
8312 | align_power = branch_align_power (now_seg); |
8313 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8314 | /* Don't count on the section alignment being as large as the target. */ |
8315 | if (target_size > branch_align) | |
8316 | target_size = branch_align; | |
d77b99c9 | 8317 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8318 | target_size, FALSE, FALSE); |
8319 | ||
664df4e4 BW |
8320 | *max_diff = (opt_diff + branch_align |
8321 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8322 | assert (*max_diff >= opt_diff); |
8323 | return opt_diff; | |
e0001a05 | 8324 | |
43cd72b9 | 8325 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
8326 | /* The next non-empty frag after this one holds the LOOP instruction |
8327 | that needs to be aligned. The required alignment depends on the | |
8328 | size of the next non-empty frag after the loop frag, i.e., the | |
8329 | first instruction in the loop. */ | |
8330 | loop_frag = next_non_empty_frag (fragP); | |
8331 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
8332 | loop_insn_offset = 0; |
8333 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8334 | assert (is_loop); | |
8335 | ||
8336 | /* If the loop has been expanded then the LOOP instruction | |
8337 | could be at an offset from this fragment. */ | |
def13efb | 8338 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
8339 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
8340 | ||
43cd72b9 BW |
8341 | /* In an ideal world, which is what we are shooting for here, |
8342 | we wouldn't need to use any NOPs immediately prior to the | |
8343 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8344 | will call get_noop_aligned_address. */ | |
8345 | target_address = | |
8346 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 8347 | align_power = get_text_align_power (target_size); |
d77b99c9 | 8348 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
8349 | target_size, FALSE, FALSE); |
8350 | ||
8351 | *max_diff = xtensa_fetch_width | |
8352 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8353 | - target_size + opt_diff; | |
8354 | assert (*max_diff >= opt_diff); | |
8355 | return opt_diff; | |
e0001a05 | 8356 | |
43cd72b9 BW |
8357 | default: |
8358 | break; | |
e0001a05 | 8359 | } |
43cd72b9 BW |
8360 | assert (0); |
8361 | return 0; | |
e0001a05 NC |
8362 | } |
8363 | ||
8364 | \f | |
8365 | /* md_relax_frag Hook and Helper Functions. */ | |
8366 | ||
7fa3d080 BW |
8367 | static long relax_frag_loop_align (fragS *, long); |
8368 | static long relax_frag_for_align (fragS *, long); | |
8369 | static long relax_frag_immed | |
8370 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8371 | ||
8372 | ||
e0001a05 NC |
8373 | /* Return the number of bytes added to this fragment, given that the |
8374 | input has been stretched already by "stretch". */ | |
8375 | ||
8376 | long | |
7fa3d080 | 8377 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8378 | { |
43cd72b9 | 8379 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8380 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8381 | long new_stretch = 0; | |
8382 | char *file_name; | |
d77b99c9 BW |
8383 | unsigned line; |
8384 | int lit_size; | |
43cd72b9 BW |
8385 | static xtensa_insnbuf vbuf = NULL; |
8386 | int slot, num_slots; | |
8387 | xtensa_format fmt; | |
e0001a05 NC |
8388 | |
8389 | as_where (&file_name, &line); | |
8390 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8391 | ||
8392 | fragP->tc_frag_data.unreported_expansion = 0; | |
8393 | ||
8394 | switch (fragP->fr_subtype) | |
8395 | { | |
8396 | case RELAX_ALIGN_NEXT_OPCODE: | |
8397 | /* Always convert. */ | |
43cd72b9 BW |
8398 | if (fragP->tc_frag_data.relax_seen) |
8399 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8400 | break; |
8401 | ||
8402 | case RELAX_LOOP_END: | |
8403 | /* Do nothing. */ | |
8404 | break; | |
8405 | ||
8406 | case RELAX_LOOP_END_ADD_NOP: | |
8407 | /* Add a NOP and switch to .fill 0. */ | |
8408 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8409 | frag_wane (fragP); |
e0001a05 NC |
8410 | break; |
8411 | ||
8412 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8413 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8414 | it or not. */ |
8415 | break; | |
8416 | ||
8417 | case RELAX_LITERAL: | |
8418 | case RELAX_LITERAL_FINAL: | |
8419 | return 0; | |
8420 | ||
8421 | case RELAX_LITERAL_NR: | |
8422 | lit_size = 4; | |
8423 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8424 | assert (unreported == lit_size); | |
8425 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8426 | fragP->fr_var -= lit_size; | |
8427 | fragP->fr_fix += lit_size; | |
8428 | new_stretch = 4; | |
8429 | break; | |
8430 | ||
43cd72b9 BW |
8431 | case RELAX_SLOTS: |
8432 | if (vbuf == NULL) | |
8433 | vbuf = xtensa_insnbuf_alloc (isa); | |
8434 | ||
d77b99c9 BW |
8435 | xtensa_insnbuf_from_chars |
8436 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8437 | fmt = xtensa_format_decode (isa, vbuf); |
8438 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8439 | |
43cd72b9 BW |
8440 | for (slot = 0; slot < num_slots; slot++) |
8441 | { | |
8442 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8443 | { | |
8444 | case RELAX_NARROW: | |
8445 | if (fragP->tc_frag_data.relax_seen) | |
8446 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8447 | break; | |
8448 | ||
8449 | case RELAX_IMMED: | |
8450 | case RELAX_IMMED_STEP1: | |
8451 | case RELAX_IMMED_STEP2: | |
b81bf389 | 8452 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
8453 | /* Place the immediate. */ |
8454 | new_stretch += relax_frag_immed | |
8455 | (now_seg, fragP, stretch, | |
8456 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8457 | fmt, slot, stretched_p, FALSE); | |
8458 | break; | |
8459 | ||
8460 | default: | |
8461 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8462 | break; | |
8463 | } | |
8464 | } | |
e0001a05 NC |
8465 | break; |
8466 | ||
8467 | case RELAX_LITERAL_POOL_BEGIN: | |
8468 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8469 | case RELAX_MAYBE_UNREACHABLE: |
8470 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8471 | /* No relaxation required. */ |
8472 | break; | |
8473 | ||
43cd72b9 BW |
8474 | case RELAX_FILL_NOP: |
8475 | case RELAX_UNREACHABLE: | |
8476 | if (fragP->tc_frag_data.relax_seen) | |
8477 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8478 | break; | |
8479 | ||
e0001a05 NC |
8480 | default: |
8481 | as_bad (_("bad relaxation state")); | |
8482 | } | |
8483 | ||
43cd72b9 | 8484 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8485 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8486 | { |
8487 | fragP->tc_frag_data.relax_seen = TRUE; | |
8488 | *stretched_p = 1; | |
8489 | } | |
8490 | ||
e0001a05 NC |
8491 | new_logical_line (file_name, line); |
8492 | return new_stretch; | |
8493 | } | |
8494 | ||
8495 | ||
8496 | static long | |
7fa3d080 | 8497 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8498 | { |
8499 | addressT old_address, old_next_address, old_size; | |
8500 | addressT new_address, new_next_address, new_size; | |
8501 | addressT growth; | |
8502 | ||
43cd72b9 BW |
8503 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8504 | section have been done, hopefully eliminating the need for a NOP here. | |
8505 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8506 | |
8507 | /* Calculate the old address of this fragment and the next fragment. */ | |
8508 | old_address = fragP->fr_address - stretch; | |
8509 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8510 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8511 | old_size = old_next_address - old_address; |
8512 | ||
8513 | /* Calculate the new address of this fragment and the next fragment. */ | |
8514 | new_address = fragP->fr_address; | |
8515 | new_next_address = | |
8516 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8517 | new_size = new_next_address - new_address; | |
8518 | ||
8519 | growth = new_size - old_size; | |
8520 | ||
8521 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8522 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8523 | return growth; |
8524 | } | |
8525 | ||
8526 | ||
43cd72b9 | 8527 | /* Add a NOP instruction. */ |
e0001a05 NC |
8528 | |
8529 | static long | |
7fa3d080 | 8530 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8531 | { |
e0001a05 | 8532 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8533 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8534 | assemble_nop (length, nop_buf); | |
e0001a05 | 8535 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8536 | |
e0001a05 NC |
8537 | if (fragP->fr_var < length) |
8538 | { | |
dd49a749 | 8539 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8540 | return 0; |
8541 | } | |
8542 | ||
8543 | fragP->fr_fix += length; | |
8544 | fragP->fr_var -= length; | |
e0001a05 NC |
8545 | return length; |
8546 | } | |
8547 | ||
8548 | ||
7fa3d080 BW |
8549 | static long future_alignment_required (fragS *, long); |
8550 | ||
e0001a05 | 8551 | static long |
7fa3d080 | 8552 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8553 | { |
43cd72b9 BW |
8554 | /* Overview of the relaxation procedure for alignment: |
8555 | We can widen with NOPs or by widening instructions or by filling | |
8556 | bytes after jump instructions. Find the opportune places and widen | |
8557 | them if necessary. */ | |
8558 | ||
8559 | long stretch_me; | |
8560 | long diff; | |
e0001a05 | 8561 | |
43cd72b9 BW |
8562 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8563 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8564 | || (fragP->fr_subtype == RELAX_SLOTS | |
8565 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8566 | ||
8567 | stretch_me = future_alignment_required (fragP, stretch); | |
8568 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8569 | if (diff == 0) | |
8570 | return 0; | |
e0001a05 | 8571 | |
43cd72b9 | 8572 | if (diff < 0) |
e0001a05 | 8573 | { |
43cd72b9 BW |
8574 | /* We expanded on a previous pass. Can we shrink now? */ |
8575 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8576 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8577 | { |
43cd72b9 BW |
8578 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8579 | return -shrink; | |
e0001a05 NC |
8580 | } |
8581 | return 0; | |
8582 | } | |
8583 | ||
43cd72b9 BW |
8584 | /* Below here, diff > 0. */ |
8585 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8586 | |
43cd72b9 | 8587 | return diff; |
e0001a05 NC |
8588 | } |
8589 | ||
8590 | ||
43cd72b9 BW |
8591 | /* Return the address of the next frag that should be aligned. |
8592 | ||
8593 | By "address" we mean the address it _would_ be at if there | |
8594 | is no action taken to align it between here and the target frag. | |
8595 | In other words, if no narrows and no fill nops are used between | |
8596 | here and the frag to align, _even_if_ some of the frags we use | |
8597 | to align targets have already expanded on a previous relaxation | |
8598 | pass. | |
8599 | ||
8600 | Also, count each frag that may be used to help align the target. | |
8601 | ||
8602 | Return 0 if there are no frags left in the chain that need to be | |
8603 | aligned. */ | |
8604 | ||
8605 | static addressT | |
7fa3d080 BW |
8606 | find_address_of_next_align_frag (fragS **fragPP, |
8607 | int *wide_nops, | |
8608 | int *narrow_nops, | |
8609 | int *widens, | |
8610 | bfd_boolean *paddable) | |
e0001a05 | 8611 | { |
43cd72b9 BW |
8612 | fragS *fragP = *fragPP; |
8613 | addressT address = fragP->fr_address; | |
8614 | ||
8615 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8616 | |
8617 | while (fragP) | |
8618 | { | |
8619 | /* Limit this to a small search. */ | |
b5e4a23d | 8620 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8621 | { |
8622 | *fragPP = fragP; | |
8623 | return 0; | |
8624 | } | |
e0001a05 NC |
8625 | address += fragP->fr_fix; |
8626 | ||
43cd72b9 BW |
8627 | if (fragP->fr_type == rs_fill) |
8628 | address += fragP->fr_offset * fragP->fr_var; | |
8629 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8630 | { |
e0001a05 NC |
8631 | switch (fragP->fr_subtype) |
8632 | { | |
43cd72b9 BW |
8633 | case RELAX_UNREACHABLE: |
8634 | *paddable = TRUE; | |
8635 | break; | |
8636 | ||
8637 | case RELAX_FILL_NOP: | |
8638 | (*wide_nops)++; | |
8639 | if (!fragP->tc_frag_data.is_no_density) | |
8640 | (*narrow_nops)++; | |
8641 | break; | |
8642 | ||
8643 | case RELAX_SLOTS: | |
8644 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8645 | { | |
8646 | (*widens)++; | |
8647 | break; | |
8648 | } | |
34e41783 | 8649 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8650 | break; |
8651 | ||
8652 | case RELAX_IMMED: | |
43cd72b9 | 8653 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8654 | break; |
8655 | ||
8656 | case RELAX_ALIGN_NEXT_OPCODE: | |
8657 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8658 | *fragPP = fragP; |
8659 | return address; | |
8660 | ||
8661 | case RELAX_MAYBE_UNREACHABLE: | |
8662 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8663 | /* Do nothing. */ | |
e0001a05 NC |
8664 | break; |
8665 | ||
8666 | default: | |
43cd72b9 BW |
8667 | /* Just punt if we don't know the type. */ |
8668 | *fragPP = fragP; | |
8669 | return 0; | |
e0001a05 | 8670 | } |
43cd72b9 | 8671 | } |
c138bc38 | 8672 | else |
43cd72b9 BW |
8673 | { |
8674 | /* Just punt if we don't know the type. */ | |
8675 | *fragPP = fragP; | |
8676 | return 0; | |
8677 | } | |
8678 | fragP = fragP->fr_next; | |
8679 | } | |
8680 | ||
8681 | *fragPP = fragP; | |
8682 | return 0; | |
8683 | } | |
8684 | ||
8685 | ||
7fa3d080 BW |
8686 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8687 | ||
43cd72b9 | 8688 | static long |
7fa3d080 | 8689 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8690 | { |
8691 | fragS *this_frag = fragP; | |
8692 | long address; | |
8693 | int num_widens = 0; | |
8694 | int wide_nops = 0; | |
8695 | int narrow_nops = 0; | |
8696 | bfd_boolean paddable = FALSE; | |
8697 | offsetT local_opt_diff; | |
8698 | offsetT opt_diff; | |
8699 | offsetT max_diff; | |
8700 | int stretch_amount = 0; | |
8701 | int local_stretch_amount; | |
8702 | int global_stretch_amount; | |
8703 | ||
7fa3d080 BW |
8704 | address = find_address_of_next_align_frag |
8705 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8706 | |
b5e4a23d BW |
8707 | if (!address) |
8708 | { | |
8709 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8710 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8711 | else | |
8712 | frag_wane (this_frag); | |
8713 | } | |
8714 | else | |
43cd72b9 BW |
8715 | { |
8716 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8717 | opt_diff = local_opt_diff; | |
8718 | assert (opt_diff >= 0); | |
8719 | assert (max_diff >= opt_diff); | |
c138bc38 | 8720 | if (max_diff == 0) |
43cd72b9 | 8721 | return 0; |
d2a033cd | 8722 | |
43cd72b9 BW |
8723 | if (fragP) |
8724 | fragP = fragP->fr_next; | |
8725 | ||
8726 | while (fragP && opt_diff < max_diff && address) | |
8727 | { | |
8728 | /* We only use these to determine if we can exit early | |
c138bc38 | 8729 | because there will be plenty of ways to align future |
43cd72b9 | 8730 | align frags. */ |
d77b99c9 | 8731 | int glob_widens = 0; |
43cd72b9 BW |
8732 | int dnn = 0; |
8733 | int dw = 0; | |
8734 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8735 | address = find_address_of_next_align_frag |
8736 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8737 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8738 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8739 | address = 0; |
43cd72b9 | 8740 | |
c138bc38 | 8741 | if (address) |
43cd72b9 BW |
8742 | { |
8743 | offsetT next_m_diff; | |
8744 | offsetT next_o_diff; | |
8745 | ||
8746 | /* Downrange frags haven't had stretch added to them yet. */ | |
8747 | address += stretch; | |
8748 | ||
8749 | /* The address also includes any text expansion from this | |
8750 | frag in a previous pass, but we don't want that. */ | |
8751 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8752 | ||
8753 | /* Assume we are going to move at least opt_diff. In | |
8754 | reality, we might not be able to, but assuming that | |
8755 | we will helps catch cases where moving opt_diff pushes | |
8756 | the next target from aligned to unaligned. */ | |
8757 | address += opt_diff; | |
8758 | ||
8759 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8760 | ||
8761 | /* Now cleanup for the adjustments to address. */ | |
8762 | next_o_diff += opt_diff; | |
8763 | next_m_diff += opt_diff; | |
8764 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8765 | opt_diff = next_o_diff; | |
8766 | if (next_m_diff < max_diff) | |
8767 | max_diff = next_m_diff; | |
8768 | fragP = fragP->fr_next; | |
8769 | } | |
8770 | } | |
d2a033cd | 8771 | |
43cd72b9 BW |
8772 | /* If there are enough wideners in between, do it. */ |
8773 | if (paddable) | |
8774 | { | |
8775 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8776 | { | |
8777 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8778 | return opt_diff; | |
8779 | } | |
8780 | return 0; | |
8781 | } | |
c138bc38 | 8782 | local_stretch_amount |
43cd72b9 BW |
8783 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8784 | num_widens, local_opt_diff); | |
c138bc38 BW |
8785 | global_stretch_amount |
8786 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8787 | num_widens, opt_diff); |
c138bc38 BW |
8788 | /* If the condition below is true, then the frag couldn't |
8789 | stretch the correct amount for the global case, so we just | |
8790 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8791 | the correct alignment in the global case. */ |
8792 | if (global_stretch_amount < local_stretch_amount) | |
8793 | stretch_amount = local_stretch_amount; | |
8794 | else | |
8795 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8796 | |
43cd72b9 BW |
8797 | if (this_frag->fr_subtype == RELAX_SLOTS |
8798 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8799 | assert (stretch_amount <= 1); | |
8800 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8801 | { | |
8802 | if (this_frag->tc_frag_data.is_no_density) | |
8803 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8804 | else | |
8805 | assert (stretch_amount <= 3); | |
8806 | } | |
8807 | } | |
8808 | return stretch_amount; | |
8809 | } | |
8810 | ||
8811 | ||
8812 | /* The idea: widen everything you can to get a target or loop aligned, | |
8813 | then start using NOPs. | |
8814 | ||
8815 | When we must have a NOP, here is a table of how we decide | |
8816 | (so you don't have to fight through the control flow below): | |
8817 | ||
8818 | wide_nops = the number of wide NOPs available for aligning | |
8819 | narrow_nops = the number of narrow NOPs available for aligning | |
8820 | (a subset of wide_nops) | |
8821 | widens = the number of narrow instructions that should be widened | |
8822 | ||
8823 | Desired wide narrow | |
8824 | Diff nop nop widens | |
8825 | 1 0 0 1 | |
8826 | 2 0 1 0 | |
8827 | 3a 1 0 0 | |
8828 | b 0 1 1 (case 3a makes this case unnecessary) | |
8829 | 4a 1 0 1 | |
8830 | b 0 2 0 | |
8831 | c 0 1 2 (case 4a makes this case unnecessary) | |
8832 | 5a 1 0 2 | |
8833 | b 1 1 0 | |
8834 | c 0 2 1 (case 5b makes this case unnecessary) | |
8835 | 6a 2 0 0 | |
8836 | b 1 0 3 | |
708587a4 | 8837 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8838 | d 1 1 1 (case 6a makes this case unnecessary) |
8839 | e 0 2 2 (case 6a makes this case unnecessary) | |
8840 | f 0 3 0 (case 6a makes this case unnecessary) | |
8841 | 7a 1 0 4 | |
8842 | b 2 0 1 | |
8843 | c 1 1 2 (case 7b makes this case unnecessary) | |
8844 | d 0 1 5 (case 7a makes this case unnecessary) | |
8845 | e 0 2 3 (case 7b makes this case unnecessary) | |
8846 | f 0 3 1 (case 7b makes this case unnecessary) | |
8847 | g 1 2 1 (case 7b makes this case unnecessary) | |
8848 | */ | |
8849 | ||
8850 | static long | |
7fa3d080 BW |
8851 | bytes_to_stretch (fragS *this_frag, |
8852 | int wide_nops, | |
8853 | int narrow_nops, | |
8854 | int num_widens, | |
8855 | int desired_diff) | |
43cd72b9 BW |
8856 | { |
8857 | int bytes_short = desired_diff - num_widens; | |
8858 | ||
8859 | assert (desired_diff >= 0 && desired_diff < 8); | |
8860 | if (desired_diff == 0) | |
8861 | return 0; | |
c138bc38 | 8862 | |
43cd72b9 | 8863 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8864 | |
43cd72b9 BW |
8865 | /* Always prefer widening to NOP-filling. */ |
8866 | if (bytes_short < 0) | |
8867 | { | |
8868 | /* There are enough RELAX_NARROW frags after this one | |
8869 | to align the target without widening this frag in any way. */ | |
8870 | return 0; | |
8871 | } | |
c138bc38 | 8872 | |
43cd72b9 BW |
8873 | if (bytes_short == 0) |
8874 | { | |
8875 | /* Widen every narrow between here and the align target | |
8876 | and the align target will be properly aligned. */ | |
8877 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8878 | return 0; | |
8879 | else | |
8880 | return 1; | |
8881 | } | |
c138bc38 | 8882 | |
43cd72b9 BW |
8883 | /* From here we will need at least one NOP to get an alignment. |
8884 | However, we may not be able to align at all, in which case, | |
8885 | don't widen. */ | |
8886 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8887 | { | |
8888 | switch (desired_diff) | |
8889 | { | |
8890 | case 1: | |
8891 | return 0; | |
8892 | case 2: | |
8893 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8894 | return 2; /* case 2 */ | |
8895 | return 0; | |
c138bc38 | 8896 | case 3: |
43cd72b9 BW |
8897 | if (wide_nops > 1) |
8898 | return 0; | |
8899 | else | |
8900 | return 3; /* case 3a */ | |
8901 | case 4: | |
8902 | if (num_widens >= 1 && wide_nops == 1) | |
8903 | return 3; /* case 4a */ | |
8904 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8905 | return 2; /* case 4b */ | |
8906 | return 0; | |
8907 | case 5: | |
8908 | if (num_widens >= 2 && wide_nops == 1) | |
8909 | return 3; /* case 5a */ | |
c138bc38 | 8910 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8911 | between here and the align target? */ |
8912 | if (wide_nops < 2 || narrow_nops == 0) | |
8913 | return 0; | |
8914 | /* Are there other nops closer that can serve instead? */ | |
8915 | if (wide_nops > 2 && narrow_nops > 1) | |
8916 | return 0; | |
8917 | /* Take the density one first, because there might not be | |
8918 | another density one available. */ | |
8919 | if (!this_frag->tc_frag_data.is_no_density) | |
8920 | return 2; /* case 5b narrow */ | |
8921 | else | |
8922 | return 3; /* case 5b wide */ | |
8923 | return 0; | |
8924 | case 6: | |
8925 | if (wide_nops == 2) | |
8926 | return 3; /* case 6a */ | |
8927 | else if (num_widens >= 3 && wide_nops == 1) | |
8928 | return 3; /* case 6b */ | |
8929 | return 0; | |
8930 | case 7: | |
8931 | if (wide_nops == 1 && num_widens >= 4) | |
8932 | return 3; /* case 7a */ | |
8933 | else if (wide_nops == 2 && num_widens >= 1) | |
8934 | return 3; /* case 7b */ | |
8935 | return 0; | |
e0001a05 | 8936 | default: |
43cd72b9 | 8937 | assert (0); |
e0001a05 | 8938 | } |
e0001a05 | 8939 | } |
43cd72b9 BW |
8940 | else |
8941 | { | |
c138bc38 | 8942 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8943 | this instruction to help? |
e0001a05 | 8944 | |
03aaa593 | 8945 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8946 | switch (desired_diff) |
8947 | { | |
8948 | case 1: | |
8949 | assert (0); | |
8950 | return 0; | |
8951 | case 2: | |
8952 | case 3: | |
8953 | return 0; | |
8954 | case 4: | |
8955 | if (wide_nops >= 1 && num_widens == 1) | |
8956 | return 1; /* case 4a */ | |
8957 | return 0; | |
8958 | case 5: | |
8959 | if (wide_nops >= 1 && num_widens == 2) | |
8960 | return 1; /* case 5a */ | |
8961 | return 0; | |
8962 | case 6: | |
8963 | if (wide_nops >= 2) | |
8964 | return 0; /* case 6a */ | |
8965 | else if (wide_nops >= 1 && num_widens == 3) | |
8966 | return 1; /* case 6b */ | |
8967 | return 0; | |
8968 | case 7: | |
8969 | if (wide_nops >= 1 && num_widens == 4) | |
8970 | return 1; /* case 7a */ | |
8971 | else if (wide_nops >= 2 && num_widens == 1) | |
8972 | return 1; /* case 7b */ | |
8973 | return 0; | |
8974 | default: | |
8975 | assert (0); | |
8976 | return 0; | |
8977 | } | |
8978 | } | |
8979 | assert (0); | |
8980 | return 0; | |
e0001a05 NC |
8981 | } |
8982 | ||
8983 | ||
8984 | static long | |
7fa3d080 BW |
8985 | relax_frag_immed (segT segP, |
8986 | fragS *fragP, | |
8987 | long stretch, | |
8988 | int min_steps, | |
8989 | xtensa_format fmt, | |
8990 | int slot, | |
8991 | int *stretched_p, | |
8992 | bfd_boolean estimate_only) | |
e0001a05 | 8993 | { |
43cd72b9 | 8994 | TInsn tinsn; |
e0001a05 NC |
8995 | int old_size; |
8996 | bfd_boolean negatable_branch = FALSE; | |
8997 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 8998 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 8999 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9000 | IStack istack; |
9001 | offsetT frag_offset; | |
9002 | int num_steps; | |
e0001a05 | 9003 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 9004 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 NC |
9005 | |
9006 | assert (fragP->fr_opcode != NULL); | |
9007 | ||
b5e4a23d BW |
9008 | xg_clear_vinsn (&cur_vinsn); |
9009 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 9010 | if (cur_vinsn.num_slots > 1) |
def13efb | 9011 | from_wide_insn = TRUE; |
43cd72b9 | 9012 | |
b5e4a23d | 9013 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 9014 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 9015 | |
64b607e6 | 9016 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 9017 | return 0; |
e0001a05 | 9018 | |
b08b5071 | 9019 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9020 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 9021 | |
43cd72b9 | 9022 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 9023 | |
43cd72b9 | 9024 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9025 | |
9026 | /* Special case: replace a branch to the next instruction with a NOP. | |
9027 | This is required to work around a hardware bug in T1040.0 and also | |
9028 | serves as an optimization. */ | |
9029 | ||
9030 | if (branch_jmp_to_next | |
9031 | && ((old_size == 2) || (old_size == 3)) | |
9032 | && !next_frag_is_loop_target (fragP)) | |
9033 | return 0; | |
9034 | ||
9035 | /* Here is the fun stuff: Get the immediate field from this | |
9036 | instruction. If it fits, we are done. If not, find the next | |
9037 | instruction sequence that fits. */ | |
9038 | ||
9039 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9040 | istack_init (&istack); | |
43cd72b9 | 9041 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 9042 | min_steps, stretch); |
2276bc20 | 9043 | assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 9044 | |
43cd72b9 | 9045 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
9046 | |
9047 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 9048 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
9049 | literal_diff |
9050 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 9051 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
9052 | |
9053 | if (from_wide_insn) | |
43cd72b9 | 9054 | { |
2276bc20 BW |
9055 | int first = 0; |
9056 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
9057 | first++; | |
9058 | ||
43cd72b9 BW |
9059 | num_text_bytes += old_size; |
9060 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
9061 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
9062 | else |
9063 | { | |
9064 | /* The first instruction in the relaxed sequence will go after | |
9065 | the current wide instruction, and thus its symbolic immediates | |
9066 | might not fit. */ | |
9067 | ||
9068 | istack_init (&istack); | |
9069 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, | |
9070 | frag_offset + old_size, | |
9071 | min_steps, stretch + old_size); | |
9072 | assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); | |
9073 | ||
9074 | fragP->tc_frag_data.slot_subtypes[slot] | |
9075 | = (int) RELAX_IMMED + num_steps; | |
9076 | ||
9077 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
9078 | literal_diff | |
9079 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
9080 | ||
9081 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; | |
9082 | } | |
43cd72b9 | 9083 | } |
def13efb | 9084 | |
43cd72b9 BW |
9085 | total_text_diff = num_text_bytes - old_size; |
9086 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
9087 | |
9088 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
9089 | assert (num_text_bytes >= 0); |
9090 | assert (literal_diff >= 0); | |
9091 | assert (total_text_diff >= 0); | |
e0001a05 | 9092 | |
43cd72b9 BW |
9093 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
9094 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9095 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
9096 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
9097 | |
9098 | /* Find the associated expandable literal for this. */ | |
9099 | if (literal_diff != 0) | |
9100 | { | |
2276bc20 | 9101 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9102 | if (lit_fragP) |
9103 | { | |
9104 | assert (literal_diff == 4); | |
9105 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
9106 | ||
9107 | /* We expect that the literal section state has NOT been | |
9108 | modified yet. */ | |
9109 | assert (lit_fragP->fr_type == rs_machine_dependent | |
9110 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
9111 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
9112 | ||
9113 | /* We need to mark this section for another iteration | |
9114 | of relaxation. */ | |
9115 | (*stretched_p)++; | |
9116 | } | |
9117 | } | |
9118 | ||
43cd72b9 | 9119 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 9120 | update_next_frag_state (fragP); |
e0001a05 | 9121 | |
43cd72b9 | 9122 | return this_text_diff; |
e0001a05 NC |
9123 | } |
9124 | ||
9125 | \f | |
9126 | /* md_convert_frag Hook and Helper Functions. */ | |
9127 | ||
7fa3d080 BW |
9128 | static void convert_frag_align_next_opcode (fragS *); |
9129 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
9130 | static void convert_frag_fill_nop (fragS *); | |
9131 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
9132 | ||
e0001a05 | 9133 | void |
7fa3d080 | 9134 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9135 | { |
43cd72b9 BW |
9136 | static xtensa_insnbuf vbuf = NULL; |
9137 | xtensa_isa isa = xtensa_default_isa; | |
9138 | int slot; | |
9139 | int num_slots; | |
9140 | xtensa_format fmt; | |
e0001a05 | 9141 | char *file_name; |
d77b99c9 | 9142 | unsigned line; |
e0001a05 NC |
9143 | |
9144 | as_where (&file_name, &line); | |
9145 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9146 | ||
9147 | switch (fragp->fr_subtype) | |
9148 | { | |
9149 | case RELAX_ALIGN_NEXT_OPCODE: | |
9150 | /* Always convert. */ | |
9151 | convert_frag_align_next_opcode (fragp); | |
9152 | break; | |
9153 | ||
9154 | case RELAX_DESIRE_ALIGN: | |
9155 | /* Do nothing. If not aligned already, too bad. */ | |
9156 | break; | |
9157 | ||
43cd72b9 BW |
9158 | case RELAX_LITERAL: |
9159 | case RELAX_LITERAL_FINAL: | |
9160 | break; | |
9161 | ||
9162 | case RELAX_SLOTS: | |
9163 | if (vbuf == NULL) | |
9164 | vbuf = xtensa_insnbuf_alloc (isa); | |
9165 | ||
d77b99c9 BW |
9166 | xtensa_insnbuf_from_chars |
9167 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9168 | fmt = xtensa_format_decode (isa, vbuf); |
9169 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9170 | ||
9171 | for (slot = 0; slot < num_slots; slot++) | |
9172 | { | |
9173 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9174 | { | |
9175 | case RELAX_NARROW: | |
9176 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9177 | break; | |
9178 | ||
9179 | case RELAX_IMMED: | |
9180 | case RELAX_IMMED_STEP1: | |
9181 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9182 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9183 | /* Place the immediate. */ |
9184 | convert_frag_immed | |
9185 | (sec, fragp, | |
9186 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9187 | fmt, slot); | |
9188 | break; | |
9189 | ||
9190 | default: | |
9191 | /* This is OK because some slots could have | |
9192 | relaxations and others have none. */ | |
9193 | break; | |
9194 | } | |
9195 | } | |
9196 | break; | |
9197 | ||
9198 | case RELAX_UNREACHABLE: | |
9199 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9200 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9201 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9202 | frag_wane (fragp); | |
e0001a05 NC |
9203 | break; |
9204 | ||
43cd72b9 BW |
9205 | case RELAX_MAYBE_UNREACHABLE: |
9206 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9207 | frag_wane (fragp); | |
e0001a05 NC |
9208 | break; |
9209 | ||
43cd72b9 BW |
9210 | case RELAX_FILL_NOP: |
9211 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9212 | break; |
9213 | ||
9214 | case RELAX_LITERAL_NR: | |
9215 | if (use_literal_section) | |
9216 | { | |
9217 | /* This should have been handled during relaxation. When | |
9218 | relaxing a code segment, literals sometimes need to be | |
9219 | added to the corresponding literal segment. If that | |
9220 | literal segment has already been relaxed, then we end up | |
9221 | in this situation. Marking the literal segments as data | |
9222 | would make this happen less often (since GAS always relaxes | |
9223 | code before data), but we could still get into trouble if | |
9224 | there are instructions in a segment that is not marked as | |
9225 | containing code. Until we can implement a better solution, | |
9226 | cheat and adjust the addresses of all the following frags. | |
9227 | This could break subsequent alignments, but the linker's | |
9228 | literal coalescing will do that anyway. */ | |
9229 | ||
9230 | fragS *f; | |
9231 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9232 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9233 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9234 | fragp->fr_var -= 4; | |
9235 | fragp->fr_fix += 4; | |
9236 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9237 | f->fr_address += 4; | |
9238 | } | |
9239 | else | |
9240 | as_bad (_("invalid relaxation fragment result")); | |
9241 | break; | |
9242 | } | |
9243 | ||
9244 | fragp->fr_var = 0; | |
9245 | new_logical_line (file_name, line); | |
9246 | } | |
9247 | ||
9248 | ||
7fa3d080 BW |
9249 | static void |
9250 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9251 | { |
9252 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9253 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9254 | addressT aligned_address; | |
d77b99c9 BW |
9255 | offsetT fill_size; |
9256 | int nop, nop_count; | |
e0001a05 NC |
9257 | |
9258 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9259 | fragp->fr_fix); | |
9260 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9261 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9262 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9263 | ||
d77b99c9 | 9264 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9265 | { |
d77b99c9 BW |
9266 | int nop_size; |
9267 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9268 | |
9269 | assemble_nop (nop_size, nop_buf); | |
9270 | nop_buf += nop_size; | |
9271 | } | |
9272 | ||
9273 | fragp->fr_fix += fill_size; | |
9274 | fragp->fr_var -= fill_size; | |
9275 | } | |
9276 | ||
9277 | ||
9278 | static void | |
7fa3d080 | 9279 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9280 | { |
43cd72b9 | 9281 | TInsn tinsn, single_target; |
84b08ed9 | 9282 | int size, old_size, diff; |
e0001a05 NC |
9283 | offsetT frag_offset; |
9284 | ||
43cd72b9 BW |
9285 | assert (slot == 0); |
9286 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9287 | ||
b5e4a23d | 9288 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9289 | { |
9290 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9291 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9292 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9293 | fmt, slot); | |
9294 | return; | |
9295 | } | |
9296 | ||
9297 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9298 | { |
9299 | /* No conversion. */ | |
9300 | fragP->fr_var = 0; | |
9301 | return; | |
9302 | } | |
9303 | ||
9304 | assert (fragP->fr_opcode != NULL); | |
9305 | ||
43cd72b9 BW |
9306 | /* Frags in this relaxation state should only contain |
9307 | single instruction bundles. */ | |
9308 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9309 | |
9310 | /* Just convert it to a wide form.... */ | |
9311 | size = 0; | |
43cd72b9 | 9312 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9313 | |
9314 | tinsn_init (&single_target); | |
9315 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9316 | ||
84b08ed9 | 9317 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9318 | { |
9319 | as_bad (_("unable to widen instruction")); | |
9320 | return; | |
9321 | } | |
9322 | ||
9323 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9324 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9325 | frag_offset, TRUE); | |
e0001a05 NC |
9326 | |
9327 | diff = size - old_size; | |
9328 | assert (diff >= 0); | |
9329 | assert (diff <= fragP->fr_var); | |
9330 | fragP->fr_var -= diff; | |
9331 | fragP->fr_fix += diff; | |
9332 | ||
9333 | /* clean it up */ | |
9334 | fragP->fr_var = 0; | |
9335 | } | |
9336 | ||
9337 | ||
9338 | static void | |
7fa3d080 | 9339 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9340 | { |
9341 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9342 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9343 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9344 | - fragP->fr_address - fragP->fr_fix)); | |
9345 | if (size == 0) | |
9346 | { | |
9347 | /* No conversion. */ | |
9348 | fragP->fr_var = 0; | |
9349 | return; | |
9350 | } | |
9351 | assemble_nop (size, loc); | |
9352 | fragP->tc_frag_data.is_insn = TRUE; | |
9353 | fragP->fr_var -= size; | |
9354 | fragP->fr_fix += size; | |
9355 | frag_wane (fragP); | |
9356 | } | |
9357 | ||
9358 | ||
7fa3d080 BW |
9359 | static fixS *fix_new_exp_in_seg |
9360 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9361 | bfd_reloc_code_real_type); | |
9362 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9363 | ||
43cd72b9 | 9364 | static void |
7fa3d080 BW |
9365 | convert_frag_immed (segT segP, |
9366 | fragS *fragP, | |
9367 | int min_steps, | |
9368 | xtensa_format fmt, | |
9369 | int slot) | |
e0001a05 NC |
9370 | { |
9371 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9372 | TInsn orig_tinsn; |
e0001a05 | 9373 | bfd_boolean expanded = FALSE; |
e0001a05 | 9374 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9375 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 9376 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 9377 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
9378 | int bytes; |
9379 | bfd_boolean is_loop; | |
e0001a05 | 9380 | |
43cd72b9 | 9381 | assert (fr_opcode != NULL); |
e0001a05 | 9382 | |
b5e4a23d | 9383 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9384 | |
b5e4a23d | 9385 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9386 | if (cur_vinsn.num_slots > 1) |
def13efb | 9387 | from_wide_insn = TRUE; |
e0001a05 | 9388 | |
b5e4a23d | 9389 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9390 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9391 | ||
9392 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9393 | |
b08b5071 | 9394 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9395 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9396 | |
9397 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9398 | { | |
9399 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9400 | bytes = xtensa_format_length (isa, fmt); |
9401 | if (bytes >= 4) | |
9402 | { | |
b5e4a23d BW |
9403 | cur_vinsn.slots[slot].opcode = |
9404 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9405 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9406 | } |
9407 | else | |
9408 | { | |
9409 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9410 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9411 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9412 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9413 | } | |
e7da6241 | 9414 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9415 | xtensa_insnbuf_to_chars |
b5e4a23d | 9416 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9417 | fragP->fr_var = 0; |
9418 | } | |
7c834684 | 9419 | else |
e0001a05 | 9420 | { |
43cd72b9 BW |
9421 | /* Here is the fun stuff: Get the immediate field from this |
9422 | instruction. If it fits, we're done. If not, find the next | |
9423 | instruction sequence that fits. */ | |
9424 | ||
e0001a05 NC |
9425 | IStack istack; |
9426 | int i; | |
9427 | symbolS *lit_sym = NULL; | |
9428 | int total_size = 0; | |
43cd72b9 | 9429 | int target_offset = 0; |
e0001a05 NC |
9430 | int old_size; |
9431 | int diff; | |
9432 | symbolS *gen_label = NULL; | |
9433 | offsetT frag_offset; | |
43cd72b9 BW |
9434 | bfd_boolean first = TRUE; |
9435 | bfd_boolean last_is_jump; | |
e0001a05 | 9436 | |
43cd72b9 | 9437 | /* It does not fit. Find something that does and |
e0001a05 | 9438 | convert immediately. */ |
43cd72b9 | 9439 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9440 | istack_init (&istack); |
43cd72b9 | 9441 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9442 | segP, fragP, frag_offset, min_steps, 0); |
9443 | ||
43cd72b9 | 9444 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9445 | |
9446 | /* Assemble this right inline. */ | |
9447 | ||
9448 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9449 | target_offset = 0; |
e0001a05 NC |
9450 | for (i = 0; i < istack.ninsn; i++) |
9451 | { | |
43cd72b9 | 9452 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9453 | fragS *lit_frag; |
9454 | ||
43cd72b9 | 9455 | switch (tinsn->insn_type) |
e0001a05 NC |
9456 | { |
9457 | case ITYPE_LITERAL: | |
9458 | if (lit_sym != NULL) | |
9459 | as_bad (_("multiple literals in expansion")); | |
9460 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9461 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9462 | if (lit_frag == NULL) |
9463 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9464 | if (tinsn->ntok != 1) |
e0001a05 NC |
9465 | as_bad (_("number of literal tokens != 1")); |
9466 | ||
9467 | /* Set the literal symbol and add a fixup. */ | |
9468 | lit_sym = lit_frag->fr_symbol; | |
9469 | break; | |
9470 | ||
9471 | case ITYPE_LABEL: | |
43cd72b9 BW |
9472 | if (align_targets && !is_loop) |
9473 | { | |
9474 | fragS *unreach = fragP->fr_next; | |
9475 | while (!(unreach->fr_type == rs_machine_dependent | |
9476 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9477 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9478 | { | |
9479 | unreach = unreach->fr_next; | |
9480 | } | |
9481 | ||
9482 | assert (unreach->fr_type == rs_machine_dependent | |
9483 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9484 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9485 | ||
9486 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9487 | } | |
e0001a05 NC |
9488 | assert (gen_label == NULL); |
9489 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9490 | fr_opcode - fragP->fr_literal |
9491 | + target_offset, fragP); | |
e0001a05 NC |
9492 | break; |
9493 | ||
9494 | case ITYPE_INSN: | |
def13efb | 9495 | if (first && from_wide_insn) |
43cd72b9 BW |
9496 | { |
9497 | target_offset += xtensa_format_length (isa, fmt); | |
9498 | first = FALSE; | |
9499 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9500 | target_offset += xg_get_single_size (tinsn->opcode); | |
9501 | } | |
9502 | else | |
9503 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9504 | break; |
9505 | } | |
9506 | } | |
9507 | ||
9508 | total_size = 0; | |
43cd72b9 BW |
9509 | first = TRUE; |
9510 | last_is_jump = FALSE; | |
e0001a05 NC |
9511 | for (i = 0; i < istack.ninsn; i++) |
9512 | { | |
43cd72b9 | 9513 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9514 | fragS *lit_frag; |
9515 | int size; | |
9516 | segT target_seg; | |
43cd72b9 | 9517 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9518 | |
43cd72b9 | 9519 | switch (tinsn->insn_type) |
e0001a05 NC |
9520 | { |
9521 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9522 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9523 | /* Already checked. */ | |
e0001a05 NC |
9524 | assert (lit_frag != NULL); |
9525 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9526 | assert (tinsn->ntok == 1); |
9527 | /* Add a fixup. */ | |
e0001a05 NC |
9528 | target_seg = S_GET_SEGMENT (lit_sym); |
9529 | assert (target_seg); | |
bbdd25a8 | 9530 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op); |
e0001a05 | 9531 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9532 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9533 | break; |
9534 | ||
9535 | case ITYPE_LABEL: | |
9536 | break; | |
9537 | ||
9538 | case ITYPE_INSN: | |
43cd72b9 BW |
9539 | xg_resolve_labels (tinsn, gen_label); |
9540 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 9541 | if (from_wide_insn && first) |
43cd72b9 BW |
9542 | { |
9543 | first = FALSE; | |
9544 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9545 | { | |
b5e4a23d | 9546 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9547 | } |
9548 | else | |
9549 | { | |
b5e4a23d | 9550 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9551 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9552 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9553 | } |
b5e4a23d BW |
9554 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9555 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9556 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9557 | fragP->tc_frag_data.is_insn = TRUE; |
9558 | size = xtensa_format_length (isa, fmt); | |
9559 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9560 | { | |
43cd72b9 | 9561 | xg_emit_insn_to_buf |
b2d179be | 9562 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9563 | immed_instr - fragP->fr_literal + size, TRUE); |
9564 | size += xg_get_single_size (tinsn->opcode); | |
9565 | } | |
9566 | } | |
9567 | else | |
9568 | { | |
43cd72b9 | 9569 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9570 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9571 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9572 | } |
e0001a05 | 9573 | immed_instr += size; |
43cd72b9 | 9574 | total_size += size; |
e0001a05 NC |
9575 | break; |
9576 | } | |
9577 | } | |
9578 | ||
9579 | diff = total_size - old_size; | |
9580 | assert (diff >= 0); | |
9581 | if (diff != 0) | |
9582 | expanded = TRUE; | |
9583 | assert (diff <= fragP->fr_var); | |
9584 | fragP->fr_var -= diff; | |
9585 | fragP->fr_fix += diff; | |
9586 | } | |
9587 | ||
e0001a05 | 9588 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9589 | if (is_loop) |
e0001a05 NC |
9590 | { |
9591 | symbolS *sym; | |
43cd72b9 | 9592 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9593 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9594 | { | |
9595 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9596 | return; | |
9597 | } | |
43cd72b9 | 9598 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9599 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9600 | { | |
9601 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9602 | return; | |
9603 | } | |
9604 | } | |
9605 | ||
43cd72b9 BW |
9606 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9607 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9608 | |
43cd72b9 | 9609 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9610 | { |
9611 | /* Add an expansion note on the expanded instruction. */ | |
9612 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9613 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9614 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9615 | } |
9616 | } | |
9617 | ||
9618 | ||
9619 | /* Add a new fix expression into the desired segment. We have to | |
9620 | switch to that segment to do this. */ | |
9621 | ||
9622 | static fixS * | |
7fa3d080 BW |
9623 | fix_new_exp_in_seg (segT new_seg, |
9624 | subsegT new_subseg, | |
9625 | fragS *frag, | |
9626 | int where, | |
9627 | int size, | |
9628 | expressionS *exp, | |
9629 | int pcrel, | |
9630 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9631 | { |
9632 | fixS *new_fix; | |
9633 | segT seg = now_seg; | |
9634 | subsegT subseg = now_subseg; | |
43cd72b9 | 9635 | |
e0001a05 NC |
9636 | assert (new_seg != 0); |
9637 | subseg_set (new_seg, new_subseg); | |
9638 | ||
e0001a05 NC |
9639 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9640 | subseg_set (seg, subseg); | |
9641 | return new_fix; | |
9642 | } | |
9643 | ||
9644 | ||
43cd72b9 BW |
9645 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9646 | ||
9647 | loop as, .L1 | |
9648 | .L0: | |
9649 | rsr as, LEND | |
9650 | wsr as, LBEG | |
9651 | addi as, as, lo8 (label-.L1) | |
9652 | addmi as, as, mid8 (label-.L1) | |
9653 | wsr as, LEND | |
9654 | isync | |
9655 | rsr as, LCOUNT | |
9656 | addi as, as, 1 | |
9657 | .L1: | |
9658 | <<body>> | |
9659 | label: | |
9660 | */ | |
e0001a05 NC |
9661 | |
9662 | static void | |
7fa3d080 | 9663 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9664 | { |
9665 | TInsn loop_insn; | |
9666 | TInsn addi_insn; | |
9667 | TInsn addmi_insn; | |
9668 | unsigned long target; | |
9669 | static xtensa_insnbuf insnbuf = NULL; | |
9670 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9671 | xtensa_isa isa = xtensa_default_isa; | |
9672 | addressT loop_offset; | |
9673 | addressT addi_offset = 9; | |
9674 | addressT addmi_offset = 12; | |
43cd72b9 | 9675 | fragS *next_fragP; |
d77b99c9 | 9676 | int target_count; |
e0001a05 NC |
9677 | |
9678 | if (!insnbuf) | |
9679 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9680 | ||
9681 | /* Get the loop offset. */ | |
43cd72b9 | 9682 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9683 | |
43cd72b9 BW |
9684 | /* Validate that there really is a LOOP at the loop_offset. Because |
9685 | loops are not bundleable, we can assume that the instruction will be | |
9686 | in slot 0. */ | |
9687 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9688 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9689 | ||
9690 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9691 | addi_offset += loop_offset; |
9692 | addmi_offset += loop_offset; | |
9693 | ||
43cd72b9 | 9694 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9695 | if (tinsn->tok[1].X_op == O_constant) |
9696 | target = tinsn->tok[1].X_add_number; | |
9697 | else if (tinsn->tok[1].X_op == O_symbol) | |
9698 | { | |
9699 | /* Find the fragment. */ | |
9700 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9701 | assert (S_GET_SEGMENT (sym) == segP | |
9702 | || S_GET_SEGMENT (sym) == absolute_section); | |
9703 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9704 | } | |
9705 | else | |
9706 | { | |
9707 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9708 | target = 0; | |
9709 | } | |
e0001a05 | 9710 | |
e0001a05 NC |
9711 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
9712 | loop_length_hi = loop_length & ~0x0ff; | |
9713 | loop_length_lo = loop_length & 0x0ff; | |
9714 | if (loop_length_lo >= 128) | |
9715 | { | |
9716 | loop_length_lo -= 256; | |
9717 | loop_length_hi += 256; | |
9718 | } | |
9719 | ||
43cd72b9 | 9720 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9721 | 32512. If the loop is larger than that, then we just fail. */ |
9722 | if (loop_length_hi > 32512) | |
9723 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9724 | _("loop too long for LOOP instruction")); | |
9725 | ||
43cd72b9 | 9726 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9727 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9728 | ||
43cd72b9 | 9729 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9730 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9731 | ||
9732 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9733 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9734 | |
e0001a05 | 9735 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9736 | xtensa_insnbuf_to_chars |
9737 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9738 | |
9739 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9740 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9741 | xtensa_insnbuf_to_chars |
9742 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9743 | |
9744 | /* Walk through all of the frags from here to the loop end | |
9745 | and mark them as no_transform to keep them from being modified | |
9746 | by the linker. If we ever have a relocation for the | |
9747 | addi/addmi of the difference of two symbols we can remove this. */ | |
9748 | ||
9749 | target_count = 0; | |
9750 | for (next_fragP = fragP; next_fragP != NULL; | |
9751 | next_fragP = next_fragP->fr_next) | |
9752 | { | |
b08b5071 | 9753 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9754 | if (next_fragP->tc_frag_data.is_loop_target) |
9755 | target_count++; | |
9756 | if (target_count == 2) | |
9757 | break; | |
9758 | } | |
e0001a05 NC |
9759 | } |
9760 | ||
b08b5071 BW |
9761 | \f |
9762 | /* A map that keeps information on a per-subsegment basis. This is | |
9763 | maintained during initial assembly, but is invalid once the | |
9764 | subsegments are smashed together. I.E., it cannot be used during | |
9765 | the relaxation. */ | |
e0001a05 | 9766 | |
b08b5071 | 9767 | typedef struct subseg_map_struct |
e0001a05 | 9768 | { |
b08b5071 BW |
9769 | /* the key */ |
9770 | segT seg; | |
9771 | subsegT subseg; | |
e0001a05 | 9772 | |
b08b5071 BW |
9773 | /* the data */ |
9774 | unsigned flags; | |
9775 | float total_freq; /* fall-through + branch target frequency */ | |
9776 | float target_freq; /* branch target frequency alone */ | |
9777 | ||
9778 | struct subseg_map_struct *next; | |
9779 | } subseg_map; | |
e0001a05 | 9780 | |
e0001a05 | 9781 | |
e0001a05 NC |
9782 | static subseg_map *sseg_map = NULL; |
9783 | ||
43cd72b9 | 9784 | static subseg_map * |
7fa3d080 | 9785 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9786 | { |
9787 | subseg_map *subseg_e; | |
9788 | ||
9789 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9790 | { |
43cd72b9 | 9791 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9792 | break; |
e0001a05 | 9793 | } |
b08b5071 BW |
9794 | return subseg_e; |
9795 | } | |
9796 | ||
9797 | ||
9798 | static subseg_map * | |
9799 | add_subseg_info (segT seg, subsegT subseg) | |
9800 | { | |
9801 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9802 | memset (subseg_e, 0, sizeof (subseg_map)); |
9803 | subseg_e->seg = seg; | |
9804 | subseg_e->subseg = subseg; | |
9805 | subseg_e->flags = 0; | |
9806 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9807 | subseg_e->target_freq = 1.0; |
9808 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9809 | subseg_e->next = sseg_map; |
9810 | sseg_map = subseg_e; | |
43cd72b9 BW |
9811 | return subseg_e; |
9812 | } | |
e0001a05 | 9813 | |
7fa3d080 BW |
9814 | |
9815 | static unsigned | |
9816 | get_last_insn_flags (segT seg, subsegT subseg) | |
9817 | { | |
9818 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9819 | if (subseg_e) |
9820 | return subseg_e->flags; | |
9821 | return 0; | |
7fa3d080 BW |
9822 | } |
9823 | ||
9824 | ||
43cd72b9 | 9825 | static void |
7fa3d080 BW |
9826 | set_last_insn_flags (segT seg, |
9827 | subsegT subseg, | |
9828 | unsigned fl, | |
9829 | bfd_boolean val) | |
43cd72b9 BW |
9830 | { |
9831 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9832 | if (! subseg_e) |
9833 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9834 | if (val) |
9835 | subseg_e->flags |= fl; | |
9836 | else | |
9837 | subseg_e->flags &= ~fl; | |
9838 | } | |
9839 | ||
b08b5071 BW |
9840 | |
9841 | static float | |
9842 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9843 | { | |
9844 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9845 | if (subseg_e) | |
9846 | return subseg_e->total_freq; | |
9847 | return 1.0; | |
9848 | } | |
9849 | ||
9850 | ||
9851 | static float | |
9852 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9853 | { | |
9854 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9855 | if (subseg_e) | |
9856 | return subseg_e->target_freq; | |
9857 | return 1.0; | |
9858 | } | |
9859 | ||
9860 | ||
9861 | static void | |
9862 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9863 | { | |
9864 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9865 | if (! subseg_e) | |
9866 | subseg_e = add_subseg_info (seg, subseg); | |
9867 | subseg_e->total_freq = total_f; | |
9868 | subseg_e->target_freq = target_f; | |
9869 | } | |
9870 | ||
e0001a05 NC |
9871 | \f |
9872 | /* Segment Lists and emit_state Stuff. */ | |
9873 | ||
e0001a05 | 9874 | static void |
7fa3d080 | 9875 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9876 | { |
9877 | head = head->next; | |
9878 | while (head) | |
9879 | { | |
9880 | segT literal_section = head->seg; | |
9881 | ||
9882 | /* Move the literal section to the front of the section list. */ | |
9883 | assert (literal_section); | |
69852798 AM |
9884 | if (literal_section != stdoutput->sections) |
9885 | { | |
9886 | bfd_section_list_remove (stdoutput, literal_section); | |
9887 | bfd_section_list_prepend (stdoutput, literal_section); | |
9888 | } | |
e0001a05 NC |
9889 | head = head->next; |
9890 | } | |
9891 | } | |
9892 | ||
9893 | ||
7fa3d080 BW |
9894 | static void mark_literal_frags (seg_list *); |
9895 | ||
9896 | static void | |
9897 | xtensa_move_literals (void) | |
e0001a05 NC |
9898 | { |
9899 | seg_list *segment; | |
9900 | frchainS *frchain_from, *frchain_to; | |
9901 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9902 | fragS **frag_splice; | |
9903 | emit_state state; | |
9904 | segT dest_seg; | |
9905 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9906 | sym_list *lit; |
e0001a05 | 9907 | |
a7877748 | 9908 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
9909 | |
9910 | if (use_literal_section) | |
9911 | return; | |
9912 | ||
74869ac7 | 9913 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 9914 | { |
74869ac7 BW |
9915 | /* Keep the literals for .init and .fini in separate sections. */ |
9916 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
9917 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
9918 | continue; | |
9919 | ||
e0001a05 NC |
9920 | frchain_from = seg_info (segment->seg)->frchainP; |
9921 | search_frag = frchain_from->frch_root; | |
9922 | literal_pool = NULL; | |
9923 | frchain_to = NULL; | |
9924 | frag_splice = &(frchain_from->frch_root); | |
9925 | ||
9926 | while (!search_frag->tc_frag_data.literal_frag) | |
9927 | { | |
9928 | assert (search_frag->fr_fix == 0 | |
9929 | || search_frag->fr_type == rs_align); | |
9930 | search_frag = search_frag->fr_next; | |
9931 | } | |
9932 | ||
9933 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9934 | == RELAX_LITERAL_POOL_BEGIN); | |
9935 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9936 | ||
9937 | /* Make sure that all the frags in this series are closed, and | |
9938 | that there is at least one left over of zero-size. This | |
9939 | prevents us from making a segment with an frchain without any | |
9940 | frags in it. */ | |
9941 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9942 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9943 | last_frag = frag_now; |
9944 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9945 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9946 | |
43cd72b9 | 9947 | while (search_frag != frag_now) |
e0001a05 NC |
9948 | { |
9949 | next_frag = search_frag->fr_next; | |
9950 | ||
43cd72b9 | 9951 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9952 | to the appropriate place. */ |
9953 | if (search_frag->tc_frag_data.literal_frag) | |
9954 | { | |
9955 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9956 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9957 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9958 | assert (frchain_to); | |
e0001a05 | 9959 | } |
c48aaca0 | 9960 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 9961 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9962 | |
e0001a05 NC |
9963 | *frag_splice = next_frag; |
9964 | search_frag->fr_next = insert_after->fr_next; | |
9965 | insert_after->fr_next = search_frag; | |
9966 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 9967 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
9968 | |
9969 | /* Now move any fixups associated with this frag to the | |
9970 | right section. */ | |
9971 | fix = frchain_from->fix_root; | |
9972 | fix_splice = &(frchain_from->fix_root); | |
9973 | while (fix) | |
9974 | { | |
9975 | next_fix = fix->fx_next; | |
9976 | if (fix->fx_frag == search_frag) | |
9977 | { | |
9978 | *fix_splice = next_fix; | |
9979 | fix->fx_next = frchain_to->fix_root; | |
9980 | frchain_to->fix_root = fix; | |
9981 | if (frchain_to->fix_tail == NULL) | |
9982 | frchain_to->fix_tail = fix; | |
9983 | } | |
9984 | else | |
9985 | fix_splice = &(fix->fx_next); | |
9986 | fix = next_fix; | |
9987 | } | |
9988 | search_frag = next_frag; | |
9989 | } | |
9990 | ||
9991 | if (frchain_from->fix_root != NULL) | |
9992 | { | |
9993 | frchain_from = seg_info (segment->seg)->frchainP; | |
9994 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9995 | ||
9996 | assert (frchain_from->fix_root == NULL); | |
9997 | } | |
9998 | frchain_from->fix_tail = NULL; | |
9999 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
10000 | } |
10001 | ||
82e7541d BW |
10002 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
10003 | for (lit = literal_syms; lit; lit = lit->next) | |
10004 | { | |
10005 | symbolS *lit_sym = lit->sym; | |
10006 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
10007 | if (dest_seg) |
10008 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 10009 | } |
e0001a05 NC |
10010 | } |
10011 | ||
10012 | ||
a7877748 BW |
10013 | /* Walk over all the frags for segments in a list and mark them as |
10014 | containing literals. As clunky as this is, we can't rely on frag_var | |
10015 | and frag_variant to get called in all situations. */ | |
10016 | ||
10017 | static void | |
7fa3d080 | 10018 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
10019 | { |
10020 | frchainS *frchain_from; | |
10021 | fragS *search_frag; | |
10022 | ||
10023 | while (segment) | |
10024 | { | |
10025 | frchain_from = seg_info (segment->seg)->frchainP; | |
10026 | search_frag = frchain_from->frch_root; | |
c138bc38 | 10027 | while (search_frag) |
a7877748 BW |
10028 | { |
10029 | search_frag->tc_frag_data.is_literal = TRUE; | |
10030 | search_frag = search_frag->fr_next; | |
10031 | } | |
10032 | segment = segment->next; | |
10033 | } | |
10034 | } | |
10035 | ||
10036 | ||
e0001a05 | 10037 | static void |
7fa3d080 | 10038 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
10039 | { |
10040 | /* Move all of the sections in the section list to come | |
10041 | after "after" in the gnu segment list. */ | |
10042 | ||
10043 | head = head->next; | |
10044 | while (head) | |
10045 | { | |
10046 | segT literal_section = head->seg; | |
10047 | ||
10048 | /* Move the literal section after "after". */ | |
10049 | assert (literal_section); | |
10050 | if (literal_section != after) | |
10051 | { | |
69852798 AM |
10052 | bfd_section_list_remove (stdoutput, literal_section); |
10053 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
10054 | } |
10055 | ||
10056 | head = head->next; | |
10057 | } | |
10058 | } | |
10059 | ||
10060 | ||
10061 | /* Push all the literal segments to the end of the gnu list. */ | |
10062 | ||
7fa3d080 BW |
10063 | static void |
10064 | xtensa_reorder_segments (void) | |
e0001a05 NC |
10065 | { |
10066 | segT sec; | |
b08b5071 | 10067 | segT last_sec = 0; |
e0001a05 NC |
10068 | int old_count = 0; |
10069 | int new_count = 0; | |
10070 | ||
10071 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
10072 | { |
10073 | last_sec = sec; | |
10074 | old_count++; | |
10075 | } | |
e0001a05 NC |
10076 | |
10077 | /* Now that we have the last section, push all the literal | |
10078 | sections to the end. */ | |
e0001a05 | 10079 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
10080 | |
10081 | /* Now perform the final error check. */ | |
10082 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10083 | new_count++; | |
10084 | assert (new_count == old_count); | |
10085 | } | |
10086 | ||
10087 | ||
e0001a05 NC |
10088 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10089 | correct location. Return a emit_state which can be passed to | |
10090 | xtensa_restore_emit_state to return to current fragment. */ | |
10091 | ||
7fa3d080 BW |
10092 | static void |
10093 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10094 | { |
10095 | if (directive_state[directive_absolute_literals]) | |
10096 | { | |
74869ac7 BW |
10097 | segT lit4_seg = cache_literal_section (TRUE); |
10098 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
10099 | } |
10100 | else | |
10101 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10102 | ||
10103 | /* Do a 4-byte align here. */ | |
10104 | frag_align (2, 0, 0); | |
10105 | record_alignment (now_seg, 2); | |
10106 | } | |
10107 | ||
10108 | ||
7fa3d080 BW |
10109 | static void |
10110 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 10111 | { |
e0001a05 NC |
10112 | static bfd_boolean recursive = FALSE; |
10113 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 10114 | segT lit_seg; |
c138bc38 | 10115 | bfd_boolean is_init = |
e0001a05 | 10116 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 10117 | bfd_boolean is_fini = |
e0001a05 | 10118 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 10119 | |
43cd72b9 BW |
10120 | if (pool_location == NULL |
10121 | && !use_literal_section | |
e0001a05 NC |
10122 | && !recursive |
10123 | && !is_init && ! is_fini) | |
10124 | { | |
43cd72b9 | 10125 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
10126 | |
10127 | /* When we mark a literal pool location, we want to put a frag in | |
10128 | the literal pool that points to it. But to do that, we want to | |
10129 | switch_to_literal_fragment. But literal sections don't have | |
10130 | literal pools, so their location is always null, so we would | |
10131 | recurse forever. This is kind of hacky, but it works. */ | |
10132 | ||
e0001a05 | 10133 | recursive = TRUE; |
61846f28 | 10134 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10135 | recursive = FALSE; |
10136 | } | |
10137 | ||
74869ac7 BW |
10138 | lit_seg = cache_literal_section (FALSE); |
10139 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 10140 | |
43cd72b9 BW |
10141 | if (!use_literal_section |
10142 | && !is_init && !is_fini | |
10143 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10144 | { |
10145 | /* Close whatever frag is there. */ | |
10146 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10147 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10148 | frag_now->tc_frag_data.literal_frag = pool_location; |
10149 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10150 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10151 | } |
e0001a05 NC |
10152 | } |
10153 | ||
10154 | ||
10155 | /* Call this function before emitting data into the literal section. | |
10156 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10157 | This is similar to a .section new_now_seg subseg. */ | |
10158 | ||
7fa3d080 BW |
10159 | static void |
10160 | xtensa_switch_section_emit_state (emit_state *state, | |
10161 | segT new_now_seg, | |
10162 | subsegT new_now_subseg) | |
e0001a05 NC |
10163 | { |
10164 | state->name = now_seg->name; | |
10165 | state->now_seg = now_seg; | |
10166 | state->now_subseg = now_subseg; | |
10167 | state->generating_literals = generating_literals; | |
10168 | generating_literals++; | |
2b0210eb | 10169 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10170 | } |
10171 | ||
10172 | ||
10173 | /* Use to restore the emitting into the normal place. */ | |
10174 | ||
7fa3d080 BW |
10175 | static void |
10176 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10177 | { |
10178 | generating_literals = state->generating_literals; | |
2b0210eb | 10179 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10180 | } |
10181 | ||
10182 | ||
74869ac7 | 10183 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10184 | |
74869ac7 BW |
10185 | static bfd_boolean |
10186 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10187 | { |
74869ac7 BW |
10188 | const char *gname = inf; |
10189 | const char *group_name = elf_group_name (sec); | |
10190 | ||
10191 | return (group_name == gname | |
10192 | || (group_name != NULL | |
10193 | && gname != NULL | |
10194 | && strcmp (group_name, gname) == 0)); | |
10195 | } | |
e0001a05 | 10196 | |
e0001a05 | 10197 | |
74869ac7 BW |
10198 | /* Get the literal section to be used for the current text section. |
10199 | The result may be cached in the default_lit_sections structure. */ | |
10200 | ||
10201 | static segT | |
10202 | cache_literal_section (bfd_boolean use_abs_literals) | |
10203 | { | |
10204 | const char *text_name, *group_name = 0; | |
10205 | char *base_name, *name, *suffix; | |
10206 | segT *pcached; | |
10207 | segT seg, current_section; | |
10208 | int current_subsec; | |
10209 | bfd_boolean linkonce = FALSE; | |
10210 | ||
10211 | /* Save the current section/subsection. */ | |
10212 | current_section = now_seg; | |
10213 | current_subsec = now_subseg; | |
10214 | ||
10215 | /* Clear the cached values if they are no longer valid. */ | |
10216 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10217 | { |
74869ac7 BW |
10218 | default_lit_sections.current_text_seg = now_seg; |
10219 | default_lit_sections.lit_seg = NULL; | |
10220 | default_lit_sections.lit4_seg = NULL; | |
10221 | } | |
10222 | ||
10223 | /* Check if the literal section is already cached. */ | |
10224 | if (use_abs_literals) | |
10225 | pcached = &default_lit_sections.lit4_seg; | |
10226 | else | |
10227 | pcached = &default_lit_sections.lit_seg; | |
10228 | ||
10229 | if (*pcached) | |
10230 | return *pcached; | |
10231 | ||
10232 | text_name = default_lit_sections.lit_prefix; | |
10233 | if (! text_name || ! *text_name) | |
10234 | { | |
10235 | text_name = segment_name (current_section); | |
10236 | group_name = elf_group_name (current_section); | |
10237 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10238 | } | |
10239 | ||
10240 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10241 | if (group_name) | |
10242 | { | |
10243 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10244 | sprintf (name, "%s.%s", base_name, group_name); | |
10245 | } | |
10246 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10247 | { | |
10248 | suffix = strchr (text_name + linkonce_len, '.'); | |
10249 | ||
10250 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10251 | + (suffix ? strlen (suffix) : 0)); | |
10252 | strcpy (name, ".gnu.linkonce"); | |
10253 | strcat (name, base_name); | |
10254 | if (suffix) | |
10255 | strcat (name, suffix); | |
10256 | linkonce = TRUE; | |
10257 | } | |
10258 | else | |
10259 | { | |
10260 | /* If the section name ends with ".text", then replace that suffix | |
10261 | instead of appending an additional suffix. */ | |
10262 | size_t len = strlen (text_name); | |
10263 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10264 | len -= 5; | |
10265 | ||
10266 | name = xmalloc (len + strlen (base_name) + 1); | |
10267 | strcpy (name, text_name); | |
10268 | strcpy (name + len, base_name); | |
b08b5071 | 10269 | } |
e0001a05 | 10270 | |
74869ac7 BW |
10271 | /* Canonicalize section names to allow renaming literal sections. |
10272 | The group name, if any, came from the current text section and | |
10273 | has already been canonicalized. */ | |
10274 | name = tc_canonicalize_symbol_name (name); | |
10275 | ||
10276 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10277 | (void *) group_name); | |
10278 | if (! seg) | |
e0001a05 | 10279 | { |
74869ac7 BW |
10280 | flagword flags; |
10281 | ||
10282 | seg = subseg_force_new (name, 0); | |
10283 | ||
10284 | if (! use_abs_literals) | |
b08b5071 | 10285 | { |
74869ac7 | 10286 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10287 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10288 | n->seg = seg; | |
74869ac7 BW |
10289 | n->next = literal_head->next; |
10290 | literal_head->next = n; | |
b08b5071 | 10291 | } |
74869ac7 BW |
10292 | |
10293 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10294 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10295 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10296 | ||
10297 | elf_group_name (seg) = group_name; | |
10298 | ||
10299 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10300 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10301 | } |
10302 | ||
74869ac7 | 10303 | *pcached = seg; |
b08b5071 | 10304 | subseg_set (current_section, current_subsec); |
74869ac7 | 10305 | return seg; |
e0001a05 NC |
10306 | } |
10307 | ||
43cd72b9 BW |
10308 | \f |
10309 | /* Property Tables Stuff. */ | |
10310 | ||
7fa3d080 BW |
10311 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10312 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10313 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10314 | ||
10315 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10316 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10317 | ||
b08b5071 | 10318 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10319 | static void xtensa_create_property_segments |
10320 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10321 | static void xtensa_create_xproperty_segments | |
10322 | (frag_flags_fn, const char *, xt_section_type); | |
7fa3d080 BW |
10323 | static bfd_boolean section_has_property (segT, frag_predicate); |
10324 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10325 | static void add_xt_block_frags | |
542f8b94 | 10326 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
10327 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
10328 | static void xtensa_frag_flags_init (frag_flags *); | |
10329 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10330 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
542f8b94 | 10331 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
10332 | |
10333 | /* Set up property tables after relaxation. */ | |
10334 | ||
10335 | void | |
10336 | xtensa_post_relax_hook (void) | |
10337 | { | |
10338 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10339 | |
10340 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 10341 | xtensa_mark_frags_for_org (); |
6a7eedfe | 10342 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 10343 | |
b29757dc BW |
10344 | xtensa_create_property_segments (get_frag_is_literal, |
10345 | NULL, | |
10346 | XTENSA_LIT_SEC_NAME, | |
10347 | xt_literal_sec); | |
7fa3d080 BW |
10348 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10349 | XTENSA_PROP_SEC_NAME, | |
10350 | xt_prop_sec); | |
10351 | ||
10352 | if (warn_unaligned_branch_targets) | |
10353 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10354 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10355 | } | |
10356 | ||
10357 | ||
43cd72b9 BW |
10358 | /* This function is only meaningful after xtensa_move_literals. */ |
10359 | ||
10360 | static bfd_boolean | |
7fa3d080 | 10361 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10362 | { |
10363 | assert (fragP != NULL); | |
10364 | return fragP->tc_frag_data.is_literal; | |
10365 | } | |
10366 | ||
10367 | ||
43cd72b9 | 10368 | static void |
7fa3d080 BW |
10369 | xtensa_create_property_segments (frag_predicate property_function, |
10370 | frag_predicate end_property_function, | |
10371 | const char *section_name_base, | |
10372 | xt_section_type sec_type) | |
43cd72b9 BW |
10373 | { |
10374 | segT *seclist; | |
10375 | ||
10376 | /* Walk over all of the current segments. | |
10377 | Walk over each fragment | |
10378 | For each non-empty fragment, | |
10379 | Build a property record (append where possible). */ | |
10380 | ||
10381 | for (seclist = &stdoutput->sections; | |
10382 | seclist && *seclist; | |
10383 | seclist = &(*seclist)->next) | |
10384 | { | |
10385 | segT sec = *seclist; | |
10386 | flagword flags; | |
10387 | ||
10388 | flags = bfd_get_section_flags (stdoutput, sec); | |
10389 | if (flags & SEC_DEBUGGING) | |
10390 | continue; | |
10391 | if (!(flags & SEC_ALLOC)) | |
10392 | continue; | |
10393 | ||
10394 | if (section_has_property (sec, property_function)) | |
10395 | { | |
542f8b94 BW |
10396 | segment_info_type *xt_seg_info; |
10397 | xtensa_block_info **xt_blocks; | |
10398 | segT prop_sec = xtensa_get_property_section (sec, section_name_base); | |
10399 | ||
10400 | prop_sec->output_section = prop_sec; | |
10401 | subseg_set (prop_sec, 0); | |
10402 | xt_seg_info = seg_info (prop_sec); | |
10403 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10404 | ||
43cd72b9 | 10405 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10406 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
10407 | end_property_function); |
10408 | } | |
10409 | } | |
10410 | ||
10411 | /* Now we fill them out.... */ | |
10412 | ||
10413 | for (seclist = &stdoutput->sections; | |
10414 | seclist && *seclist; | |
10415 | seclist = &(*seclist)->next) | |
10416 | { | |
10417 | segment_info_type *seginfo; | |
10418 | xtensa_block_info *block; | |
10419 | segT sec = *seclist; | |
10420 | ||
10421 | seginfo = seg_info (sec); | |
10422 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10423 | ||
10424 | if (block) | |
10425 | { | |
10426 | xtensa_block_info *cur_block; | |
43cd72b9 | 10427 | int num_recs = 0; |
d77b99c9 | 10428 | bfd_size_type rec_size; |
43cd72b9 BW |
10429 | |
10430 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10431 | num_recs++; | |
10432 | ||
10433 | rec_size = num_recs * 8; | |
10434 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10435 | ||
43cd72b9 BW |
10436 | if (num_recs) |
10437 | { | |
43cd72b9 | 10438 | char *frag_data; |
542f8b94 | 10439 | int i; |
43cd72b9 | 10440 | |
542f8b94 BW |
10441 | subseg_set (sec, 0); |
10442 | frag_data = frag_more (rec_size); | |
43cd72b9 | 10443 | cur_block = block; |
43cd72b9 BW |
10444 | for (i = 0; i < num_recs; i++) |
10445 | { | |
542f8b94 | 10446 | fixS *fix; |
e0001a05 | 10447 | |
43cd72b9 | 10448 | /* Write the fixup. */ |
542f8b94 BW |
10449 | assert (cur_block); |
10450 | fix = fix_new (frag_now, i * 8, 4, | |
10451 | section_symbol (cur_block->sec), | |
10452 | cur_block->offset, | |
10453 | FALSE, BFD_RELOC_32); | |
10454 | fix->fx_file = "<internal>"; | |
43cd72b9 | 10455 | fix->fx_line = 0; |
e0001a05 | 10456 | |
43cd72b9 | 10457 | /* Write the length. */ |
542f8b94 | 10458 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
10459 | cur_block->size, 4); |
10460 | cur_block = cur_block->next; | |
10461 | } | |
542f8b94 BW |
10462 | frag_wane (frag_now); |
10463 | frag_new (0); | |
10464 | frag_wane (frag_now); | |
43cd72b9 BW |
10465 | } |
10466 | } | |
10467 | } | |
e0001a05 NC |
10468 | } |
10469 | ||
10470 | ||
7fa3d080 BW |
10471 | static void |
10472 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10473 | const char *section_name_base, | |
10474 | xt_section_type sec_type) | |
e0001a05 NC |
10475 | { |
10476 | segT *seclist; | |
10477 | ||
10478 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10479 | Walk over each fragment. |
10480 | For each fragment that has instructions, | |
10481 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10482 | |
10483 | for (seclist = &stdoutput->sections; | |
10484 | seclist && *seclist; | |
10485 | seclist = &(*seclist)->next) | |
10486 | { | |
10487 | segT sec = *seclist; | |
43cd72b9 BW |
10488 | flagword flags; |
10489 | ||
10490 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10491 | if ((flags & SEC_DEBUGGING) |
10492 | || !(flags & SEC_ALLOC) | |
10493 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10494 | continue; |
10495 | ||
10496 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10497 | { |
542f8b94 BW |
10498 | segment_info_type *xt_seg_info; |
10499 | xtensa_block_info **xt_blocks; | |
10500 | segT prop_sec = xtensa_get_property_section (sec, section_name_base); | |
10501 | ||
10502 | prop_sec->output_section = prop_sec; | |
10503 | subseg_set (prop_sec, 0); | |
10504 | xt_seg_info = seg_info (prop_sec); | |
10505 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10506 | ||
e0001a05 | 10507 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10508 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
10509 | } |
10510 | } | |
10511 | ||
10512 | /* Now we fill them out.... */ | |
10513 | ||
10514 | for (seclist = &stdoutput->sections; | |
10515 | seclist && *seclist; | |
10516 | seclist = &(*seclist)->next) | |
10517 | { | |
10518 | segment_info_type *seginfo; | |
10519 | xtensa_block_info *block; | |
10520 | segT sec = *seclist; | |
43cd72b9 | 10521 | |
e0001a05 NC |
10522 | seginfo = seg_info (sec); |
10523 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10524 | ||
10525 | if (block) | |
10526 | { | |
10527 | xtensa_block_info *cur_block; | |
43cd72b9 | 10528 | int num_recs = 0; |
d77b99c9 | 10529 | bfd_size_type rec_size; |
e0001a05 NC |
10530 | |
10531 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10532 | num_recs++; | |
10533 | ||
43cd72b9 | 10534 | rec_size = num_recs * (8 + 4); |
e0001a05 | 10535 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
10536 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10537 | ||
e0001a05 NC |
10538 | if (num_recs) |
10539 | { | |
e0001a05 | 10540 | char *frag_data; |
542f8b94 | 10541 | int i; |
e0001a05 | 10542 | |
542f8b94 BW |
10543 | subseg_set (sec, 0); |
10544 | frag_data = frag_more (rec_size); | |
e0001a05 | 10545 | cur_block = block; |
e0001a05 NC |
10546 | for (i = 0; i < num_recs; i++) |
10547 | { | |
542f8b94 | 10548 | fixS *fix; |
e0001a05 NC |
10549 | |
10550 | /* Write the fixup. */ | |
542f8b94 BW |
10551 | assert (cur_block); |
10552 | fix = fix_new (frag_now, i * 12, 4, | |
10553 | section_symbol (cur_block->sec), | |
10554 | cur_block->offset, | |
10555 | FALSE, BFD_RELOC_32); | |
10556 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
10557 | fix->fx_line = 0; |
10558 | ||
10559 | /* Write the length. */ | |
542f8b94 | 10560 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 10561 | cur_block->size, 4); |
542f8b94 | 10562 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 BW |
10563 | frag_flags_to_number (&cur_block->flags), |
10564 | 4); | |
e0001a05 NC |
10565 | cur_block = cur_block->next; |
10566 | } | |
542f8b94 BW |
10567 | frag_wane (frag_now); |
10568 | frag_new (0); | |
10569 | frag_wane (frag_now); | |
e0001a05 NC |
10570 | } |
10571 | } | |
10572 | } | |
10573 | } | |
10574 | ||
10575 | ||
7fa3d080 BW |
10576 | static bfd_boolean |
10577 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10578 | { |
10579 | segment_info_type *seginfo = seg_info (sec); | |
10580 | fragS *fragP; | |
10581 | ||
10582 | if (seginfo && seginfo->frchainP) | |
10583 | { | |
10584 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10585 | { | |
10586 | if (property_function (fragP) | |
10587 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10588 | return TRUE; | |
10589 | } | |
10590 | } | |
10591 | return FALSE; | |
10592 | } | |
10593 | ||
10594 | ||
7fa3d080 BW |
10595 | static bfd_boolean |
10596 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10597 | { |
10598 | segment_info_type *seginfo = seg_info (sec); | |
10599 | fragS *fragP; | |
10600 | ||
10601 | if (seginfo && seginfo->frchainP) | |
10602 | { | |
10603 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10604 | { | |
10605 | frag_flags prop_flags; | |
10606 | property_function (fragP, &prop_flags); | |
10607 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10608 | return TRUE; | |
10609 | } | |
10610 | } | |
10611 | return FALSE; | |
10612 | } | |
10613 | ||
10614 | ||
e0001a05 NC |
10615 | /* Two types of block sections exist right now: literal and insns. */ |
10616 | ||
7fa3d080 BW |
10617 | static void |
10618 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
10619 | xtensa_block_info **xt_block, |
10620 | frag_predicate property_function, | |
10621 | frag_predicate end_property_function) | |
e0001a05 | 10622 | { |
e0001a05 NC |
10623 | bfd_vma seg_offset; |
10624 | fragS *fragP; | |
10625 | ||
e0001a05 NC |
10626 | /* Build it if needed. */ |
10627 | while (*xt_block != NULL) | |
10628 | xt_block = &(*xt_block)->next; | |
10629 | /* We are either at NULL at the beginning or at the end. */ | |
10630 | ||
10631 | /* Walk through the frags. */ | |
10632 | seg_offset = 0; | |
10633 | ||
542f8b94 | 10634 | if (seg_info (sec)->frchainP) |
e0001a05 | 10635 | { |
542f8b94 | 10636 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
10637 | fragP; |
10638 | fragP = fragP->fr_next) | |
10639 | { | |
10640 | if (property_function (fragP) | |
10641 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10642 | { | |
10643 | if (*xt_block != NULL) | |
10644 | { | |
10645 | if ((*xt_block)->offset + (*xt_block)->size | |
10646 | == fragP->fr_address) | |
10647 | (*xt_block)->size += fragP->fr_fix; | |
10648 | else | |
10649 | xt_block = &((*xt_block)->next); | |
10650 | } | |
10651 | if (*xt_block == NULL) | |
10652 | { | |
43cd72b9 BW |
10653 | xtensa_block_info *new_block = (xtensa_block_info *) |
10654 | xmalloc (sizeof (xtensa_block_info)); | |
10655 | new_block->sec = sec; | |
10656 | new_block->offset = fragP->fr_address; | |
10657 | new_block->size = fragP->fr_fix; | |
10658 | new_block->next = NULL; | |
10659 | xtensa_frag_flags_init (&new_block->flags); | |
10660 | *xt_block = new_block; | |
10661 | } | |
10662 | if (end_property_function | |
10663 | && end_property_function (fragP)) | |
10664 | { | |
10665 | xt_block = &((*xt_block)->next); | |
10666 | } | |
10667 | } | |
10668 | } | |
10669 | } | |
10670 | } | |
10671 | ||
10672 | ||
10673 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10674 | ||
7fa3d080 BW |
10675 | static bfd_boolean |
10676 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10677 | { |
10678 | if (prop_flags->is_literal | |
10679 | || prop_flags->is_insn | |
10680 | || prop_flags->is_data | |
10681 | || prop_flags->is_unreachable) | |
10682 | return FALSE; | |
10683 | return TRUE; | |
10684 | } | |
10685 | ||
10686 | ||
7fa3d080 BW |
10687 | static void |
10688 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10689 | { |
10690 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10691 | } | |
10692 | ||
10693 | ||
7fa3d080 BW |
10694 | static void |
10695 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10696 | { |
10697 | xtensa_frag_flags_init (prop_flags); | |
10698 | if (fragP->tc_frag_data.is_literal) | |
10699 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
10700 | if (fragP->tc_frag_data.is_specific_opcode |
10701 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
10702 | { |
10703 | prop_flags->is_no_transform = TRUE; | |
10704 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10705 | prop_flags->is_data = TRUE; | |
10706 | } | |
43cd72b9 | 10707 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 10708 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10709 | else if (fragP->tc_frag_data.is_insn) |
10710 | { | |
10711 | prop_flags->is_insn = TRUE; | |
10712 | if (fragP->tc_frag_data.is_loop_target) | |
10713 | prop_flags->insn.is_loop_target = TRUE; | |
10714 | if (fragP->tc_frag_data.is_branch_target) | |
10715 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
10716 | if (fragP->tc_frag_data.is_no_density) |
10717 | prop_flags->insn.is_no_density = TRUE; | |
10718 | if (fragP->tc_frag_data.use_absolute_literals) | |
10719 | prop_flags->insn.is_abslit = TRUE; | |
10720 | } | |
10721 | if (fragP->tc_frag_data.is_align) | |
10722 | { | |
10723 | prop_flags->is_align = TRUE; | |
10724 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10725 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10726 | prop_flags->is_data = TRUE; | |
10727 | } | |
10728 | } | |
10729 | ||
10730 | ||
7fa3d080 BW |
10731 | static bfd_vma |
10732 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10733 | { |
10734 | bfd_vma num = 0; | |
10735 | if (prop_flags->is_literal) | |
10736 | num |= XTENSA_PROP_LITERAL; | |
10737 | if (prop_flags->is_insn) | |
10738 | num |= XTENSA_PROP_INSN; | |
10739 | if (prop_flags->is_data) | |
10740 | num |= XTENSA_PROP_DATA; | |
10741 | if (prop_flags->is_unreachable) | |
10742 | num |= XTENSA_PROP_UNREACHABLE; | |
10743 | if (prop_flags->insn.is_loop_target) | |
10744 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10745 | if (prop_flags->insn.is_branch_target) | |
10746 | { | |
10747 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10748 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10749 | } | |
10750 | ||
10751 | if (prop_flags->insn.is_no_density) | |
10752 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
10753 | if (prop_flags->is_no_transform) |
10754 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
10755 | if (prop_flags->insn.is_no_reorder) |
10756 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10757 | if (prop_flags->insn.is_abslit) | |
10758 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10759 | ||
10760 | if (prop_flags->is_align) | |
10761 | { | |
10762 | num |= XTENSA_PROP_ALIGN; | |
10763 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10764 | } | |
10765 | ||
10766 | return num; | |
10767 | } | |
10768 | ||
10769 | ||
10770 | static bfd_boolean | |
7fa3d080 BW |
10771 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10772 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10773 | { |
10774 | /* Cannot combine with an end marker. */ | |
10775 | ||
10776 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10777 | return FALSE; | |
10778 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10779 | return FALSE; | |
10780 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10781 | return FALSE; | |
10782 | ||
10783 | if (prop_flags_1->is_insn) | |
10784 | { | |
10785 | /* Properties of the beginning of the frag. */ | |
10786 | if (prop_flags_2->insn.is_loop_target) | |
10787 | return FALSE; | |
10788 | if (prop_flags_2->insn.is_branch_target) | |
10789 | return FALSE; | |
10790 | if (prop_flags_1->insn.is_no_density != | |
10791 | prop_flags_2->insn.is_no_density) | |
10792 | return FALSE; | |
99ded152 BW |
10793 | if (prop_flags_1->is_no_transform != |
10794 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
10795 | return FALSE; |
10796 | if (prop_flags_1->insn.is_no_reorder != | |
10797 | prop_flags_2->insn.is_no_reorder) | |
10798 | return FALSE; | |
10799 | if (prop_flags_1->insn.is_abslit != | |
10800 | prop_flags_2->insn.is_abslit) | |
10801 | return FALSE; | |
10802 | } | |
10803 | ||
10804 | if (prop_flags_1->is_align) | |
10805 | return FALSE; | |
10806 | ||
10807 | return TRUE; | |
10808 | } | |
10809 | ||
10810 | ||
7fa3d080 BW |
10811 | static bfd_vma |
10812 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10813 | { |
10814 | bfd_vma end_addr; | |
d77b99c9 | 10815 | unsigned align_bits; |
43cd72b9 BW |
10816 | |
10817 | if (!xt_block->flags.is_align) | |
10818 | return xt_block->size; | |
10819 | ||
10820 | end_addr = xt_block->offset + xt_block->size; | |
10821 | align_bits = xt_block->flags.alignment; | |
10822 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10823 | return end_addr - xt_block->offset; | |
10824 | } | |
10825 | ||
10826 | ||
10827 | static bfd_boolean | |
7fa3d080 BW |
10828 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10829 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10830 | { |
10831 | if (xt_block->sec != xt_block_2->sec) | |
10832 | return FALSE; | |
10833 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10834 | != xt_block_2->offset) | |
10835 | return FALSE; | |
10836 | ||
10837 | if (xt_block_2->size == 0 | |
10838 | && (!xt_block_2->flags.is_unreachable | |
10839 | || xt_block->flags.is_unreachable)) | |
10840 | { | |
10841 | if (xt_block_2->flags.is_align | |
10842 | && xt_block->flags.is_align) | |
10843 | { | |
10844 | /* Nothing needed. */ | |
10845 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10846 | return TRUE; | |
10847 | } | |
10848 | else | |
10849 | { | |
10850 | if (xt_block_2->flags.is_align) | |
10851 | { | |
10852 | /* Push alignment to previous entry. */ | |
10853 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10854 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10855 | } | |
10856 | return TRUE; | |
10857 | } | |
10858 | } | |
10859 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10860 | &xt_block_2->flags)) | |
10861 | return FALSE; | |
10862 | ||
10863 | xt_block->size += xt_block_2->size; | |
10864 | ||
10865 | if (xt_block_2->flags.is_align) | |
10866 | { | |
10867 | xt_block->flags.is_align = TRUE; | |
10868 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10869 | } | |
10870 | ||
10871 | return TRUE; | |
10872 | } | |
10873 | ||
10874 | ||
7fa3d080 BW |
10875 | static void |
10876 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
10877 | xtensa_block_info **xt_block, |
10878 | frag_flags_fn property_function) | |
43cd72b9 | 10879 | { |
43cd72b9 BW |
10880 | bfd_vma seg_offset; |
10881 | fragS *fragP; | |
10882 | ||
43cd72b9 BW |
10883 | /* Build it if needed. */ |
10884 | while (*xt_block != NULL) | |
10885 | { | |
10886 | xt_block = &(*xt_block)->next; | |
10887 | } | |
10888 | /* We are either at NULL at the beginning or at the end. */ | |
10889 | ||
10890 | /* Walk through the frags. */ | |
10891 | seg_offset = 0; | |
10892 | ||
542f8b94 | 10893 | if (seg_info (sec)->frchainP) |
43cd72b9 | 10894 | { |
542f8b94 | 10895 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
10896 | fragP = fragP->fr_next) |
10897 | { | |
10898 | xtensa_block_info tmp_block; | |
10899 | tmp_block.sec = sec; | |
10900 | tmp_block.offset = fragP->fr_address; | |
10901 | tmp_block.size = fragP->fr_fix; | |
10902 | tmp_block.next = NULL; | |
10903 | property_function (fragP, &tmp_block.flags); | |
10904 | ||
10905 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10906 | /* && fragP->fr_fix != 0) */ | |
10907 | { | |
10908 | if ((*xt_block) == NULL | |
10909 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10910 | { | |
10911 | xtensa_block_info *new_block; | |
10912 | if ((*xt_block) != NULL) | |
10913 | xt_block = &(*xt_block)->next; | |
10914 | new_block = (xtensa_block_info *) | |
10915 | xmalloc (sizeof (xtensa_block_info)); | |
10916 | *new_block = tmp_block; | |
10917 | *xt_block = new_block; | |
10918 | } | |
10919 | } | |
10920 | } | |
10921 | } | |
10922 | } | |
10923 | ||
10924 | \f | |
10925 | /* op_placement_info_table */ | |
10926 | ||
10927 | /* op_placement_info makes it easier to determine which | |
10928 | ops can go in which slots. */ | |
10929 | ||
10930 | static void | |
7fa3d080 | 10931 | init_op_placement_info_table (void) |
43cd72b9 BW |
10932 | { |
10933 | xtensa_isa isa = xtensa_default_isa; | |
10934 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10935 | xtensa_opcode opcode; | |
10936 | xtensa_format fmt; | |
10937 | int slot; | |
10938 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10939 | ||
10940 | op_placement_table = (op_placement_info_table) | |
10941 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10942 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10943 | ||
10944 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10945 | { | |
10946 | op_placement_info *opi = &op_placement_table[opcode]; | |
10947 | /* FIXME: Make tinsn allocation dynamic. */ | |
10948 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10949 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10950 | opi->narrowest = XTENSA_UNDEFINED; |
10951 | opi->narrowest_size = 0x7F; | |
b2d179be | 10952 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10953 | opi->formats = 0; |
10954 | opi->num_formats = 0; | |
10955 | opi->issuef = 0; | |
10956 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10957 | { | |
10958 | opi->slots[fmt] = 0; | |
10959 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10960 | { | |
10961 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10962 | { | |
10963 | int fmt_length = xtensa_format_length (isa, fmt); | |
10964 | opi->issuef++; | |
10965 | set_bit (fmt, opi->formats); | |
10966 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
10967 | if (fmt_length < opi->narrowest_size |
10968 | || (fmt_length == opi->narrowest_size | |
10969 | && (xtensa_format_num_slots (isa, fmt) | |
10970 | < xtensa_format_num_slots (isa, | |
10971 | opi->narrowest)))) | |
43cd72b9 BW |
10972 | { |
10973 | opi->narrowest = fmt; | |
10974 | opi->narrowest_size = fmt_length; | |
b2d179be | 10975 | opi->narrowest_slot = slot; |
43cd72b9 | 10976 | } |
e0001a05 NC |
10977 | } |
10978 | } | |
43cd72b9 BW |
10979 | if (opi->formats) |
10980 | opi->num_formats++; | |
e0001a05 NC |
10981 | } |
10982 | } | |
43cd72b9 BW |
10983 | xtensa_insnbuf_free (isa, ibuf); |
10984 | } | |
10985 | ||
10986 | ||
10987 | bfd_boolean | |
7fa3d080 | 10988 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
10989 | { |
10990 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
10991 | } | |
10992 | ||
10993 | ||
10994 | /* If the opcode is available in a single slot format, return its size. */ | |
10995 | ||
7fa3d080 BW |
10996 | static int |
10997 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 10998 | { |
b2d179be | 10999 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
11000 | } |
11001 | ||
11002 | ||
7fa3d080 BW |
11003 | static xtensa_format |
11004 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 11005 | { |
b2d179be BW |
11006 | return op_placement_table[opcode].narrowest; |
11007 | } | |
11008 | ||
11009 | ||
11010 | static int | |
11011 | xg_get_single_slot (xtensa_opcode opcode) | |
11012 | { | |
11013 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
11014 | } |
11015 | ||
11016 | \f | |
11017 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
11018 | ||
11019 | void | |
7fa3d080 | 11020 | istack_init (IStack *stack) |
e0001a05 NC |
11021 | { |
11022 | memset (stack, 0, sizeof (IStack)); | |
11023 | stack->ninsn = 0; | |
11024 | } | |
11025 | ||
11026 | ||
11027 | bfd_boolean | |
7fa3d080 | 11028 | istack_empty (IStack *stack) |
e0001a05 NC |
11029 | { |
11030 | return (stack->ninsn == 0); | |
11031 | } | |
11032 | ||
11033 | ||
11034 | bfd_boolean | |
7fa3d080 | 11035 | istack_full (IStack *stack) |
e0001a05 NC |
11036 | { |
11037 | return (stack->ninsn == MAX_ISTACK); | |
11038 | } | |
11039 | ||
11040 | ||
11041 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 11042 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
11043 | |
11044 | TInsn * | |
7fa3d080 | 11045 | istack_top (IStack *stack) |
e0001a05 NC |
11046 | { |
11047 | int rec = stack->ninsn - 1; | |
11048 | assert (!istack_empty (stack)); | |
11049 | return &stack->insn[rec]; | |
11050 | } | |
11051 | ||
11052 | ||
11053 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 11054 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11055 | |
11056 | void | |
7fa3d080 | 11057 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
11058 | { |
11059 | int rec = stack->ninsn; | |
11060 | assert (!istack_full (stack)); | |
43cd72b9 | 11061 | stack->insn[rec] = *insn; |
e0001a05 NC |
11062 | stack->ninsn++; |
11063 | } | |
11064 | ||
11065 | ||
11066 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11067 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11068 | |
11069 | TInsn * | |
7fa3d080 | 11070 | istack_push_space (IStack *stack) |
e0001a05 NC |
11071 | { |
11072 | int rec = stack->ninsn; | |
11073 | TInsn *insn; | |
11074 | assert (!istack_full (stack)); | |
11075 | insn = &stack->insn[rec]; | |
60242db2 | 11076 | tinsn_init (insn); |
e0001a05 NC |
11077 | stack->ninsn++; |
11078 | return insn; | |
11079 | } | |
11080 | ||
11081 | ||
11082 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11083 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11084 | |
11085 | void | |
7fa3d080 | 11086 | istack_pop (IStack *stack) |
e0001a05 NC |
11087 | { |
11088 | int rec = stack->ninsn - 1; | |
11089 | assert (!istack_empty (stack)); | |
11090 | stack->ninsn--; | |
60242db2 | 11091 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11092 | } |
11093 | ||
11094 | \f | |
11095 | /* TInsn functions. */ | |
11096 | ||
11097 | void | |
7fa3d080 | 11098 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11099 | { |
11100 | memset (dst, 0, sizeof (TInsn)); | |
11101 | } | |
11102 | ||
11103 | ||
43cd72b9 | 11104 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11105 | |
11106 | static bfd_boolean | |
7fa3d080 | 11107 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11108 | { |
11109 | int i; | |
11110 | int n = insn->ntok; | |
11111 | ||
11112 | assert (insn->insn_type == ITYPE_INSN); | |
11113 | ||
11114 | for (i = 0; i < n; ++i) | |
11115 | { | |
11116 | switch (insn->tok[i].X_op) | |
11117 | { | |
11118 | case O_register: | |
11119 | case O_constant: | |
11120 | break; | |
11121 | default: | |
11122 | return TRUE; | |
11123 | } | |
11124 | } | |
11125 | return FALSE; | |
11126 | } | |
11127 | ||
11128 | ||
11129 | bfd_boolean | |
7fa3d080 | 11130 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11131 | { |
43cd72b9 | 11132 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11133 | int i; |
11134 | int n = insn->ntok; | |
11135 | ||
11136 | assert (insn->insn_type == ITYPE_INSN); | |
11137 | ||
11138 | for (i = 0; i < n; ++i) | |
11139 | { | |
11140 | switch (insn->tok[i].X_op) | |
11141 | { | |
11142 | case O_register: | |
11143 | case O_constant: | |
11144 | break; | |
43cd72b9 BW |
11145 | case O_big: |
11146 | case O_illegal: | |
11147 | case O_absent: | |
11148 | /* Errors for these types are caught later. */ | |
11149 | break; | |
11150 | case O_hi16: | |
11151 | case O_lo16: | |
e0001a05 | 11152 | default: |
43cd72b9 BW |
11153 | /* Symbolic immediates are only allowed on the last immediate |
11154 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11155 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11156 | if (i != get_relaxable_immed (insn->opcode) |
11157 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11158 | && insn->opcode != xtensa_const16_opcode)) | |
11159 | { | |
431ad2d0 | 11160 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11161 | return TRUE; |
11162 | } | |
e0001a05 NC |
11163 | } |
11164 | } | |
11165 | return FALSE; | |
11166 | } | |
11167 | ||
11168 | ||
11169 | /* For assembly code with complex expressions (e.g. subtraction), | |
11170 | we have to build them in the literal pool so that | |
11171 | their results are calculated correctly after relaxation. | |
11172 | The relaxation only handles expressions that | |
11173 | boil down to SYMBOL + OFFSET. */ | |
11174 | ||
11175 | static bfd_boolean | |
7fa3d080 | 11176 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11177 | { |
11178 | int i; | |
11179 | int n = insn->ntok; | |
11180 | assert (insn->insn_type == ITYPE_INSN); | |
11181 | for (i = 0; i < n; ++i) | |
11182 | { | |
11183 | switch (insn->tok[i].X_op) | |
11184 | { | |
11185 | case O_register: | |
11186 | case O_constant: | |
11187 | case O_symbol: | |
43cd72b9 BW |
11188 | case O_lo16: |
11189 | case O_hi16: | |
e0001a05 NC |
11190 | break; |
11191 | default: | |
11192 | return TRUE; | |
11193 | } | |
11194 | } | |
11195 | return FALSE; | |
11196 | } | |
11197 | ||
11198 | ||
b2d179be BW |
11199 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11200 | Return TRUE if there is a symbol in the immediate field. This | |
11201 | function assumes that: | |
11202 | 1) The number of operands are correct. | |
11203 | 2) The insn_type is ITYPE_INSN. | |
11204 | 3) The opcode can be encoded in the specified format and slot. | |
11205 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11206 | |
11207 | static bfd_boolean | |
7fa3d080 BW |
11208 | tinsn_to_slotbuf (xtensa_format fmt, |
11209 | int slot, | |
11210 | TInsn *tinsn, | |
11211 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11212 | { |
11213 | xtensa_isa isa = xtensa_default_isa; | |
11214 | xtensa_opcode opcode = tinsn->opcode; | |
11215 | bfd_boolean has_fixup = FALSE; | |
11216 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11217 | int i; | |
11218 | ||
43cd72b9 BW |
11219 | assert (tinsn->insn_type == ITYPE_INSN); |
11220 | if (noperands != tinsn->ntok) | |
11221 | as_fatal (_("operand number mismatch")); | |
11222 | ||
11223 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11224 | { | |
11225 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11226 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11227 | return FALSE; | |
11228 | } | |
11229 | ||
11230 | for (i = 0; i < noperands; i++) | |
11231 | { | |
11232 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11233 | int rc; |
11234 | unsigned line; | |
43cd72b9 BW |
11235 | char *file_name; |
11236 | uint32 opnd_value; | |
11237 | ||
11238 | switch (expr->X_op) | |
11239 | { | |
11240 | case O_register: | |
11241 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11242 | break; | |
11243 | /* The register number has already been checked in | |
11244 | expression_maybe_register, so we don't need to check here. */ | |
11245 | opnd_value = expr->X_add_number; | |
11246 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11247 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11248 | opnd_value); | |
11249 | if (rc != 0) | |
11250 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11251 | break; | |
11252 | ||
11253 | case O_constant: | |
11254 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11255 | break; | |
11256 | as_where (&file_name, &line); | |
11257 | /* It is a constant and we called this function | |
11258 | then we have to try to fit it. */ | |
11259 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11260 | expr->X_add_number, file_name, line); |
11261 | break; | |
11262 | ||
e0001a05 NC |
11263 | default: |
11264 | has_fixup = TRUE; | |
11265 | break; | |
11266 | } | |
11267 | } | |
43cd72b9 | 11268 | |
e0001a05 NC |
11269 | return has_fixup; |
11270 | } | |
11271 | ||
11272 | ||
b2d179be BW |
11273 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11274 | into a multi-slot instruction, fill the other slots with NOPs. | |
11275 | Return TRUE if there is a symbol in the immediate field. See also the | |
11276 | assumptions listed for tinsn_to_slotbuf. */ | |
11277 | ||
11278 | static bfd_boolean | |
11279 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11280 | { | |
11281 | static xtensa_insnbuf slotbuf = 0; | |
11282 | static vliw_insn vinsn; | |
11283 | xtensa_isa isa = xtensa_default_isa; | |
11284 | bfd_boolean has_fixup = FALSE; | |
11285 | int i; | |
11286 | ||
11287 | if (!slotbuf) | |
11288 | { | |
11289 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11290 | xg_init_vinsn (&vinsn); | |
11291 | } | |
11292 | ||
11293 | xg_clear_vinsn (&vinsn); | |
11294 | ||
11295 | bundle_tinsn (tinsn, &vinsn); | |
11296 | ||
11297 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11298 | ||
11299 | for (i = 0; i < vinsn.num_slots; i++) | |
11300 | { | |
11301 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11302 | has_fixup |= | |
11303 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11304 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11305 | } | |
11306 | ||
11307 | return has_fixup; | |
11308 | } | |
11309 | ||
11310 | ||
43cd72b9 | 11311 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11312 | |
7fa3d080 BW |
11313 | static bfd_boolean |
11314 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11315 | { |
11316 | xtensa_isa isa = xtensa_default_isa; | |
11317 | xtensa_opcode opcode = insn->opcode; | |
11318 | ||
11319 | if (opcode == XTENSA_UNDEFINED) | |
11320 | { | |
11321 | as_bad (_("invalid opcode")); | |
11322 | return TRUE; | |
11323 | } | |
11324 | ||
43cd72b9 | 11325 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11326 | { |
11327 | as_bad (_("too few operands")); | |
11328 | return TRUE; | |
11329 | } | |
11330 | ||
43cd72b9 | 11331 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11332 | { |
11333 | as_bad (_("too many operands")); | |
11334 | return TRUE; | |
11335 | } | |
11336 | return FALSE; | |
11337 | } | |
11338 | ||
11339 | ||
11340 | /* Load an instruction from its encoded form. */ | |
11341 | ||
11342 | static void | |
7fa3d080 | 11343 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11344 | { |
43cd72b9 | 11345 | vliw_insn vinsn; |
e0001a05 | 11346 | |
43cd72b9 BW |
11347 | xg_init_vinsn (&vinsn); |
11348 | vinsn_from_chars (&vinsn, f); | |
11349 | ||
11350 | *tinsn = vinsn.slots[slot]; | |
11351 | xg_free_vinsn (&vinsn); | |
11352 | } | |
e0001a05 | 11353 | |
43cd72b9 BW |
11354 | |
11355 | static void | |
7fa3d080 BW |
11356 | tinsn_from_insnbuf (TInsn *tinsn, |
11357 | xtensa_insnbuf slotbuf, | |
11358 | xtensa_format fmt, | |
11359 | int slot) | |
43cd72b9 BW |
11360 | { |
11361 | int i; | |
11362 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11363 | |
11364 | /* Find the immed. */ | |
43cd72b9 BW |
11365 | tinsn_init (tinsn); |
11366 | tinsn->insn_type = ITYPE_INSN; | |
11367 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11368 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11369 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11370 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11371 | { |
43cd72b9 BW |
11372 | set_expr_const (&tinsn->tok[i], |
11373 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11374 | tinsn->opcode, i)); | |
e0001a05 NC |
11375 | } |
11376 | } | |
11377 | ||
11378 | ||
11379 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11380 | ||
11381 | static void | |
7fa3d080 | 11382 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11383 | { |
43cd72b9 | 11384 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11385 | int opnum; |
11386 | ||
43cd72b9 | 11387 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11388 | { |
11389 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11390 | assert (opnum >= 0); |
e7da6241 BW |
11391 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11392 | fragP->tc_frag_data.slot_symbols[slot], | |
11393 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11394 | } |
11395 | } | |
11396 | ||
11397 | ||
11398 | static int | |
7fa3d080 | 11399 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11400 | { |
11401 | int i; | |
11402 | int text_bytes = 0; | |
11403 | ||
11404 | for (i = 0; i < istack->ninsn; i++) | |
11405 | { | |
43cd72b9 BW |
11406 | TInsn *tinsn = &istack->insn[i]; |
11407 | if (tinsn->insn_type == ITYPE_INSN) | |
11408 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11409 | } |
11410 | return text_bytes; | |
11411 | } | |
11412 | ||
11413 | ||
11414 | static int | |
7fa3d080 | 11415 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11416 | { |
11417 | int i; | |
11418 | int lit_bytes = 0; | |
11419 | ||
11420 | for (i = 0; i < istack->ninsn; i++) | |
11421 | { | |
43cd72b9 BW |
11422 | TInsn *tinsn = &istack->insn[i]; |
11423 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11424 | lit_bytes += 4; |
11425 | } | |
11426 | return lit_bytes; | |
11427 | } | |
11428 | ||
43cd72b9 BW |
11429 | \f |
11430 | /* vliw_insn functions. */ | |
11431 | ||
7fa3d080 BW |
11432 | static void |
11433 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11434 | { |
11435 | int i; | |
11436 | xtensa_isa isa = xtensa_default_isa; | |
11437 | ||
11438 | xg_clear_vinsn (v); | |
11439 | ||
11440 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11441 | if (v->insnbuf == NULL) | |
11442 | as_fatal (_("out of memory")); | |
11443 | ||
11444 | for (i = 0; i < MAX_SLOTS; i++) | |
11445 | { | |
43cd72b9 BW |
11446 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11447 | if (v->slotbuf[i] == NULL) | |
11448 | as_fatal (_("out of memory")); | |
11449 | } | |
11450 | } | |
11451 | ||
11452 | ||
7fa3d080 BW |
11453 | static void |
11454 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11455 | { |
11456 | int i; | |
65738a7d BW |
11457 | |
11458 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11459 | ||
43cd72b9 BW |
11460 | v->format = XTENSA_UNDEFINED; |
11461 | v->num_slots = 0; | |
11462 | v->inside_bundle = FALSE; | |
11463 | ||
11464 | if (xt_saved_debug_type != DEBUG_NONE) | |
11465 | debug_type = xt_saved_debug_type; | |
11466 | ||
11467 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11468 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11469 | } |
11470 | ||
11471 | ||
7fa3d080 BW |
11472 | static bfd_boolean |
11473 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11474 | { |
11475 | int i; | |
c138bc38 | 11476 | |
43cd72b9 BW |
11477 | for (i = 0; i < v->num_slots; i++) |
11478 | { | |
11479 | if (v->slots[i].is_specific_opcode) | |
11480 | return TRUE; | |
11481 | } | |
11482 | return FALSE; | |
11483 | } | |
11484 | ||
11485 | ||
7fa3d080 BW |
11486 | static void |
11487 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11488 | { |
11489 | int i; | |
11490 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11491 | for (i = 0; i < MAX_SLOTS; i++) | |
11492 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11493 | } | |
11494 | ||
11495 | ||
e7da6241 BW |
11496 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11497 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11498 | |
11499 | static bfd_boolean | |
7fa3d080 BW |
11500 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11501 | char *frag_offset, | |
11502 | fragS *fragP, | |
11503 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11504 | { |
11505 | xtensa_isa isa = xtensa_default_isa; | |
11506 | xtensa_format fmt = vinsn->format; | |
11507 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11508 | int slot; | |
11509 | bfd_boolean has_fixup = FALSE; | |
11510 | ||
11511 | xtensa_format_encode (isa, fmt, insnbuf); | |
11512 | ||
11513 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11514 | { | |
11515 | TInsn *tinsn = &vinsn->slots[slot]; | |
11516 | bfd_boolean tinsn_has_fixup = | |
11517 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11518 | vinsn->slotbuf[slot]); | |
11519 | ||
11520 | xtensa_format_set_slot (isa, fmt, slot, | |
11521 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11522 | if (tinsn_has_fixup) |
43cd72b9 BW |
11523 | { |
11524 | int i; | |
11525 | xtensa_opcode opcode = tinsn->opcode; | |
11526 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11527 | has_fixup = TRUE; | |
11528 | ||
11529 | for (i = 0; i < noperands; i++) | |
11530 | { | |
11531 | expressionS* expr = &tinsn->tok[i]; | |
11532 | switch (expr->X_op) | |
11533 | { | |
11534 | case O_symbol: | |
11535 | case O_lo16: | |
11536 | case O_hi16: | |
11537 | if (get_relaxable_immed (opcode) == i) | |
11538 | { | |
e7da6241 BW |
11539 | /* Add a fix record for the instruction, except if this |
11540 | function is being called prior to relaxation, i.e., | |
11541 | if record_fixup is false, and the instruction might | |
11542 | be relaxed later. */ | |
11543 | if (record_fixup | |
11544 | || tinsn->is_specific_opcode | |
11545 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11546 | { |
e7da6241 BW |
11547 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11548 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11549 | } |
11550 | else | |
11551 | { | |
e7da6241 BW |
11552 | if (expr->X_op != O_symbol) |
11553 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11554 | tinsn->symbol = expr->X_add_symbol; |
11555 | tinsn->offset = expr->X_add_number; | |
11556 | } | |
11557 | } | |
11558 | else | |
e7da6241 | 11559 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11560 | break; |
11561 | ||
11562 | case O_constant: | |
11563 | case O_register: | |
11564 | break; | |
11565 | ||
43cd72b9 | 11566 | default: |
e7da6241 | 11567 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11568 | break; |
11569 | } | |
11570 | } | |
11571 | } | |
11572 | } | |
11573 | ||
11574 | return has_fixup; | |
11575 | } | |
11576 | ||
11577 | ||
11578 | static void | |
7fa3d080 | 11579 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11580 | { |
11581 | static xtensa_insnbuf insnbuf = NULL; | |
11582 | static xtensa_insnbuf slotbuf = NULL; | |
11583 | int i; | |
11584 | xtensa_format fmt; | |
11585 | xtensa_isa isa = xtensa_default_isa; | |
11586 | ||
11587 | if (!insnbuf) | |
11588 | { | |
11589 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11590 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11591 | } | |
11592 | ||
d77b99c9 | 11593 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11594 | fmt = xtensa_format_decode (isa, insnbuf); |
11595 | if (fmt == XTENSA_UNDEFINED) | |
11596 | as_fatal (_("cannot decode instruction format")); | |
11597 | vinsn->format = fmt; | |
11598 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11599 | ||
11600 | for (i = 0; i < vinsn->num_slots; i++) | |
11601 | { | |
11602 | TInsn *tinsn = &vinsn->slots[i]; | |
11603 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11604 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11605 | } | |
11606 | } | |
11607 | ||
e0001a05 NC |
11608 | \f |
11609 | /* Expression utilities. */ | |
11610 | ||
43cd72b9 | 11611 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11612 | |
11613 | bfd_boolean | |
7fa3d080 | 11614 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11615 | { |
11616 | return (s->X_op == O_constant); | |
11617 | } | |
11618 | ||
11619 | ||
11620 | /* Get the expression constant. | |
43cd72b9 | 11621 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11622 | |
11623 | offsetT | |
7fa3d080 | 11624 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11625 | { |
11626 | assert (expr_is_const (s)); | |
11627 | return s->X_add_number; | |
11628 | } | |
11629 | ||
11630 | ||
11631 | /* Set the expression to a constant value. */ | |
11632 | ||
11633 | void | |
7fa3d080 | 11634 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11635 | { |
11636 | s->X_op = O_constant; | |
11637 | s->X_add_number = val; | |
11638 | s->X_add_symbol = NULL; | |
11639 | s->X_op_symbol = NULL; | |
11640 | } | |
11641 | ||
11642 | ||
43cd72b9 | 11643 | bfd_boolean |
7fa3d080 | 11644 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11645 | { |
11646 | return (s->X_op == O_register); | |
11647 | } | |
11648 | ||
11649 | ||
11650 | /* Get the expression constant. | |
11651 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11652 | ||
11653 | offsetT | |
7fa3d080 | 11654 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11655 | { |
11656 | assert (expr_is_register (s)); | |
11657 | return s->X_add_number; | |
11658 | } | |
11659 | ||
11660 | ||
e0001a05 NC |
11661 | /* Set the expression to a symbol + constant offset. */ |
11662 | ||
11663 | void | |
7fa3d080 | 11664 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11665 | { |
11666 | s->X_op = O_symbol; | |
11667 | s->X_add_symbol = sym; | |
11668 | s->X_op_symbol = NULL; /* unused */ | |
11669 | s->X_add_number = offset; | |
11670 | } | |
11671 | ||
11672 | ||
43cd72b9 BW |
11673 | /* Return TRUE if the two expressions are equal. */ |
11674 | ||
e0001a05 | 11675 | bfd_boolean |
7fa3d080 | 11676 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11677 | { |
11678 | if (s1->X_op != s2->X_op) | |
11679 | return FALSE; | |
11680 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11681 | return FALSE; | |
11682 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11683 | return FALSE; | |
11684 | if (s1->X_add_number != s2->X_add_number) | |
11685 | return FALSE; | |
11686 | return TRUE; | |
11687 | } | |
11688 | ||
11689 | ||
11690 | static void | |
7fa3d080 | 11691 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11692 | { |
11693 | memcpy (dst, src, sizeof (expressionS)); | |
11694 | } | |
11695 | ||
11696 | \f | |
9456465c | 11697 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11698 | |
11699 | struct rename_section_struct | |
11700 | { | |
11701 | char *old_name; | |
11702 | char *new_name; | |
11703 | struct rename_section_struct *next; | |
11704 | }; | |
11705 | ||
11706 | static struct rename_section_struct *section_rename; | |
11707 | ||
11708 | ||
9456465c BW |
11709 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11710 | entries to the section_rename list. Note: Specifying multiple | |
11711 | renamings separated by colons is not documented and is retained only | |
11712 | for backward compatibility. */ | |
e0001a05 | 11713 | |
7fa3d080 BW |
11714 | static void |
11715 | build_section_rename (const char *arg) | |
e0001a05 | 11716 | { |
9456465c | 11717 | struct rename_section_struct *r; |
e0001a05 NC |
11718 | char *this_arg = NULL; |
11719 | char *next_arg = NULL; | |
11720 | ||
9456465c | 11721 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11722 | { |
9456465c BW |
11723 | char *old_name, *new_name; |
11724 | ||
e0001a05 NC |
11725 | if (this_arg) |
11726 | { | |
11727 | next_arg = strchr (this_arg, ':'); | |
11728 | if (next_arg) | |
11729 | { | |
11730 | *next_arg = '\0'; | |
11731 | next_arg++; | |
11732 | } | |
11733 | } | |
e0001a05 | 11734 | |
9456465c BW |
11735 | old_name = this_arg; |
11736 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11737 | |
9456465c BW |
11738 | if (*old_name == '\0') |
11739 | { | |
11740 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11741 | continue; | |
11742 | } | |
11743 | if (!new_name || new_name[1] == '\0') | |
11744 | { | |
11745 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11746 | old_name); | |
11747 | continue; | |
11748 | } | |
11749 | *new_name = '\0'; | |
11750 | new_name++; | |
e0001a05 | 11751 | |
9456465c BW |
11752 | /* Check for invalid section renaming. */ |
11753 | for (r = section_rename; r != NULL; r = r->next) | |
11754 | { | |
11755 | if (strcmp (r->old_name, old_name) == 0) | |
11756 | as_bad (_("section %s renamed multiple times"), old_name); | |
11757 | if (strcmp (r->new_name, new_name) == 0) | |
11758 | as_bad (_("multiple sections remapped to output section %s"), | |
11759 | new_name); | |
11760 | } | |
e0001a05 | 11761 | |
9456465c BW |
11762 | /* Now add it. */ |
11763 | r = (struct rename_section_struct *) | |
11764 | xmalloc (sizeof (struct rename_section_struct)); | |
11765 | r->old_name = xstrdup (old_name); | |
11766 | r->new_name = xstrdup (new_name); | |
11767 | r->next = section_rename; | |
11768 | section_rename = r; | |
e0001a05 | 11769 | } |
e0001a05 NC |
11770 | } |
11771 | ||
11772 | ||
9456465c BW |
11773 | char * |
11774 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11775 | { |
11776 | struct rename_section_struct *r = section_rename; | |
11777 | ||
11778 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11779 | { |
11780 | if (strcmp (r->old_name, name) == 0) | |
11781 | return r->new_name; | |
11782 | } | |
e0001a05 NC |
11783 | |
11784 | return name; | |
11785 | } |