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[deliverable/binutils-gdb.git] / gas / config / tc-xtensa.c
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e0001a05 1/* tc-xtensa.c -- Assemble Xtensa instructions.
43cd72b9 2 Copyright 2003, 2004 Free Software Foundation, Inc.
e0001a05
NC		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
43cd72b9 18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
e0001a05
NC		 19 MA 02111-1307, USA. */
20
21#include <string.h>
43cd72b9 22#include <limits.h>
e0001a05
NC		 23#include "as.h"
24#include "sb.h"
25#include "safe-ctype.h"
26#include "tc-xtensa.h"
27#include "frags.h"
28#include "subsegs.h"
29#include "xtensa-relax.h"
30#include "xtensa-istack.h"
cda2eb9e 31#include "dwarf2dbg.h"
e0001a05
NC		 32#include "struc-symbol.h"
33#include "xtensa-config.h"
34
35#ifndef uint32
36#define uint32 unsigned int
37#endif
38#ifndef int32
39#define int32 signed int
40#endif
41
42/* Notes:
43
e0001a05
NC		 44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
47
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
58
59
60/* Define characters with special meanings to GAS. */
61const char comment_chars[] = "#";
62const char line_comment_chars[] = "#";
63const char line_separator_chars[] = ";";
64const char EXP_CHARS[] = "eE";
65const char FLT_CHARS[] = "rRsSfFdDxXpP";
66
67
43cd72b9
BW		 68/* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
e0001a05 70
e0001a05 71bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
43cd72b9
BW		 72bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
73
74/* Maximum width we would pad an unreachable frag to get alignment. */
75#define UNREACHABLE_MAX_WIDTH 8
e0001a05 76
43cd72b9
BW		 77static vliw_insn cur_vinsn;
78
79size_t xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
80
81static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
82
83/* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
85 back end. */
86static bfd_boolean past_xtensa_end = FALSE;
e0001a05
NC		 87
88/* Flags for properties of the last instruction in a segment. */
89#define FLAG_IS_A0_WRITER 0x1
90#define FLAG_IS_BAD_LOOPEND 0x2
91
92
93/* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
97
98#define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
43cd72b9 99#define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
e0001a05
NC		 100#define FINI_SECTION_NAME xtensa_section_rename (".fini")
101#define INIT_SECTION_NAME xtensa_section_rename (".init")
102#define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103#define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
104
105
43cd72b9 106/* This type is used for the directive_stack to keep track of the
e0001a05
NC		 107 state of the literal collection pools. */
108
109typedef struct lit_state_struct
110{
111 const char *lit_seg_name;
43cd72b9 112 const char *lit4_seg_name;
e0001a05
NC		 113 const char *init_lit_seg_name;
114 const char *fini_lit_seg_name;
115 segT lit_seg;
43cd72b9 116 segT lit4_seg;
e0001a05
NC		 117 segT init_lit_seg;
118 segT fini_lit_seg;
119} lit_state;
120
121static lit_state default_lit_sections;
122
123
124/* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
127
128typedef struct seg_list_struct
129{
130 struct seg_list_struct *next;
131 segT seg;
132} seg_list;
133
134static seg_list literal_head_h;
135static seg_list *literal_head = &literal_head_h;
136static seg_list init_literal_head_h;
137static seg_list *init_literal_head = &init_literal_head_h;
138static seg_list fini_literal_head_h;
139static seg_list *fini_literal_head = &fini_literal_head_h;
140
141
82e7541d
BW		 142/* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
147
148typedef struct sym_list_struct
149{
150 struct sym_list_struct *next;
151 symbolS *sym;
152} sym_list;
153
154static sym_list *insn_labels = NULL;
155static sym_list *free_insn_labels = NULL;
156static sym_list *saved_insn_labels = NULL;
157
158static sym_list *literal_syms;
159
160
43cd72b9
BW		 161/* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163int prefer_const16 = 0;
164int prefer_l32r = 0;
165
e0001a05
NC		 166/* Global flag to indicate when we are emitting literals. */
167int generating_literals = 0;
168
43cd72b9
BW		 169/* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
171
172/* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
181
182#define XTENSA_PROP_LITERAL 0x00000001
183#define XTENSA_PROP_INSN 0x00000002
184#define XTENSA_PROP_DATA 0x00000004
185#define XTENSA_PROP_UNREACHABLE 0x00000008
186/* Instruction only properties at beginning of code. */
187#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189/* Instruction only properties about code. */
190#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192#define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
193
194/* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 Common usage is
200
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206*/
207#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208
209/* No branch target alignment. */
210#define XTENSA_PROP_BT_ALIGN_NONE 0x0
211/* Low priority branch target alignment. */
212#define XTENSA_PROP_BT_ALIGN_LOW 0x1
213/* High priority branch target alignment. */
214#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215/* Required branch target alignment. */
216#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217
218#define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223
224
225/* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
235
236#define XTENSA_PROP_ALIGN 0x00000800
237
238#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239
240#define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245
246#define XTENSA_PROP_INSN_ABSLIT 0x00020000
247
248
249/* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
254
255typedef struct frag_flags_struct frag_flags;
256
257struct frag_flags_struct
258{
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
262
263 unsigned is_literal : 1;
264 unsigned is_insn : 1;
265 unsigned is_data : 1;
266 unsigned is_unreachable : 1;
267
268 struct
269 {
270 unsigned is_loop_target : 1;
271 unsigned is_branch_target : 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority : 2;
273
274 unsigned is_no_density : 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform : 1;
278
279 unsigned is_no_reorder : 1;
280
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit : 1;
283 } insn;
284 unsigned is_align : 1;
285 unsigned alignment : 5;
286};
287
288
289/* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291struct xtensa_block_info_struct
292{
293 segT sec;
294 bfd_vma offset;
295 size_t size;
296 frag_flags flags;
297 struct xtensa_block_info_struct *next;
298};
299
e0001a05
NC		 300
301/* Structure for saving the current state before emitting literals. */
302typedef struct emit_state_struct
303{
304 const char *name;
305 segT now_seg;
306 subsegT now_subseg;
307 int generating_literals;
308} emit_state;
309
310
43cd72b9
BW		 311/* Opcode placement information */
312
313typedef unsigned long long bitfield;
314#define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315#define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316#define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317
318#define MAX_FORMATS 32
319
320typedef struct op_placement_info_struct
321{
322 int num_formats;
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
328 format. */
329 int issuef;
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
332 and their sizes: */
333 xtensa_format single;
334 xtensa_format narrowest;
335 xtensa_format widest;
336 char narrowest_size;
337 char widest_size;
338 char single_size;
339
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
342 bitfield formats;
343
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots[MAX_FORMATS];
347
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format[MAX_FORMATS];
351
352} op_placement_info, *op_placement_info_table;
353
354op_placement_info_table op_placement_table;
355
356
357/* Extra expression types. */
358
359#define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360#define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361#define O_lo16 O_md3 /* use low 16 bits of symbolic value */
362
363
e0001a05
NC		 364/* Directives. */
365
366typedef enum
367{
368 directive_none = 0,
369 directive_literal,
370 directive_density,
43cd72b9 371 directive_transform,
e0001a05
NC		 372 directive_freeregs,
373 directive_longcalls,
43cd72b9
BW		 374 directive_literal_prefix,
375 directive_schedule,
376 directive_absolute_literals,
377 directive_last_directive
e0001a05
NC		 378} directiveE;
379
380typedef struct
381{
382 const char *name;
383 bfd_boolean can_be_negated;
384} directive_infoS;
385
386const directive_infoS directive_info[] =
387{
43cd72b9
BW		 388 { "none", FALSE },
389 { "literal", FALSE },
390 { "density", TRUE },
391 { "transform", TRUE },
392 { "freeregs", FALSE },
393 { "longcalls", TRUE },
394 { "literal_prefix", FALSE },
395 { "schedule", TRUE },
396 { "absolute-literals", TRUE }
e0001a05
NC		 397};
398
399bfd_boolean directive_state[] =
400{
401 FALSE, /* none */
402 FALSE, /* literal */
43cd72b9 403#if !XCHAL_HAVE_DENSITY
e0001a05
NC		 404 FALSE, /* density */
405#else
406 TRUE, /* density */
407#endif
43cd72b9 408 TRUE, /* transform */
e0001a05
NC		 409 FALSE, /* freeregs */
410 FALSE, /* longcalls */
43cd72b9
BW		 411 FALSE, /* literal_prefix */
412 TRUE, /* schedule */
413#if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE /* absolute_literals */
415#else
416 FALSE /* absolute_literals */
417#endif
e0001a05
NC		 418};
419
e0001a05
NC		 420
421/* Directive functions. */
422
7fa3d080
BW		 423static void xtensa_begin_directive (int);
424static void xtensa_end_directive (int);
425static void xtensa_dwarf2_directive_loc (int);
426static void xtensa_literal_prefix (char const *, int);
427static void xtensa_literal_position (int);
428static void xtensa_literal_pseudo (int);
429static void xtensa_frequency_pseudo (int);
430static void xtensa_elf_cons (int);
e0001a05 431
7fa3d080 432/* Parsing and Idiom Translation. */
e0001a05 433
7fa3d080 434static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
e0001a05 435
e0001a05
NC		 436/* Various Other Internal Functions. */
437
7fa3d080
BW		 438static void xtensa_mark_literal_pool_location (void);
439static addressT get_expanded_loop_offset (xtensa_opcode);
440static fragS *get_literal_pool_location (segT);
441static void set_literal_pool_location (segT, fragS *);
442static void xtensa_set_frag_assembly_state (fragS *);
443static void finish_vinsn (vliw_insn *);
444static bfd_boolean emit_single_op (TInsn *);
34e41783 445static int total_frag_text_expansion (fragS *);
e0001a05
NC		 446
447/* Alignment Functions. */
448
7fa3d080
BW		 449static size_t get_text_align_power (int);
450static addressT get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
e0001a05
NC		 451
452/* Helpers for xtensa_relax_frag(). */
453
7fa3d080 454static long relax_frag_add_nop (fragS *);
e0001a05 455
b08b5071 456/* Accessors for additional per-subsegment information. */
e0001a05 457
7fa3d080
BW		 458static unsigned get_last_insn_flags (segT, subsegT);
459static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
b08b5071
BW		 460static float get_subseg_total_freq (segT, subsegT);
461static float get_subseg_target_freq (segT, subsegT);
462static void set_subseg_freq (segT, subsegT, float, float);
e0001a05
NC		 463
464/* Segment list functions. */
465
7fa3d080
BW		 466static void xtensa_move_literals (void);
467static void xtensa_reorder_segments (void);
468static void xtensa_switch_to_literal_fragment (emit_state *);
469static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
470static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
471static void xtensa_restore_emit_state (emit_state *);
e0001a05 472static void cache_literal_section
7fa3d080 473 (seg_list *, const char *, segT *, bfd_boolean);
e0001a05 474
e0001a05 475/* Import from elf32-xtensa.c in BFD library. */
43cd72b9 476
7fa3d080 477extern char *xtensa_get_property_section_name (asection *, const char *);
e0001a05 478
43cd72b9
BW		 479/* op_placement_info functions. */
480
7fa3d080
BW		 481static void init_op_placement_info_table (void);
482extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
483static int xg_get_single_size (xtensa_opcode);
484static xtensa_format xg_get_single_format (xtensa_opcode);
43cd72b9 485
e0001a05 486/* TInsn and IStack functions. */
43cd72b9 487
7fa3d080
BW		 488static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
489static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
490static bfd_boolean tinsn_has_complex_operands (const TInsn *);
491static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
492static bfd_boolean tinsn_check_arguments (const TInsn *);
493static void tinsn_from_chars (TInsn *, char *, int);
494static void tinsn_immed_from_frag (TInsn *, fragS *, int);
495static int get_num_stack_text_bytes (IStack *);
496static int get_num_stack_literal_bytes (IStack *);
e0001a05 497
43cd72b9
BW		 498/* vliw_insn functions. */
499
7fa3d080
BW		 500static void xg_init_vinsn (vliw_insn *);
501static void xg_clear_vinsn (vliw_insn *);
502static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
503static void xg_free_vinsn (vliw_insn *);
43cd72b9 504static bfd_boolean vinsn_to_insnbuf
7fa3d080
BW		 505 (vliw_insn *, char *, fragS *, bfd_boolean);
506static void vinsn_from_chars (vliw_insn *, char *);
43cd72b9 507
e0001a05 508/* Expression Utilities. */
43cd72b9 509
7fa3d080
BW		 510bfd_boolean expr_is_const (const expressionS *);
511offsetT get_expr_const (const expressionS *);
512void set_expr_const (expressionS *, offsetT);
513bfd_boolean expr_is_register (const expressionS *);
514offsetT get_expr_register (const expressionS *);
515void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
43cd72b9 516static void set_expr_symbol_offset_diff
7fa3d080
BW		 517 (expressionS *, symbolS *, symbolS *, offsetT);
518bfd_boolean expr_is_equal (expressionS *, expressionS *);
519static void copy_expr (expressionS *, const expressionS *);
e0001a05 520
9456465c
BW		 521/* Section renaming. */
522
7fa3d080 523static void build_section_rename (const char *);
e0001a05 524
e0001a05
NC		 525
526/* ISA imported from bfd. */
527extern xtensa_isa xtensa_default_isa;
528
529extern int target_big_endian;
530
531static xtensa_opcode xtensa_addi_opcode;
532static xtensa_opcode xtensa_addmi_opcode;
533static xtensa_opcode xtensa_call0_opcode;
534static xtensa_opcode xtensa_call4_opcode;
535static xtensa_opcode xtensa_call8_opcode;
536static xtensa_opcode xtensa_call12_opcode;
537static xtensa_opcode xtensa_callx0_opcode;
538static xtensa_opcode xtensa_callx4_opcode;
539static xtensa_opcode xtensa_callx8_opcode;
540static xtensa_opcode xtensa_callx12_opcode;
43cd72b9 541static xtensa_opcode xtensa_const16_opcode;
e0001a05 542static xtensa_opcode xtensa_entry_opcode;
43cd72b9
BW		 543static xtensa_opcode xtensa_movi_opcode;
544static xtensa_opcode xtensa_movi_n_opcode;
e0001a05 545static xtensa_opcode xtensa_isync_opcode;
e0001a05 546static xtensa_opcode xtensa_jx_opcode;
43cd72b9 547static xtensa_opcode xtensa_l32r_opcode;
e0001a05
NC		 548static xtensa_opcode xtensa_loop_opcode;
549static xtensa_opcode xtensa_loopnez_opcode;
550static xtensa_opcode xtensa_loopgtz_opcode;
43cd72b9 551static xtensa_opcode xtensa_nop_opcode;
e0001a05
NC		 552static xtensa_opcode xtensa_nop_n_opcode;
553static xtensa_opcode xtensa_or_opcode;
554static xtensa_opcode xtensa_ret_opcode;
555static xtensa_opcode xtensa_ret_n_opcode;
556static xtensa_opcode xtensa_retw_opcode;
557static xtensa_opcode xtensa_retw_n_opcode;
43cd72b9 558static xtensa_opcode xtensa_rsr_lcount_opcode;
e0001a05
NC		 559static xtensa_opcode xtensa_waiti_opcode;
560
561\f
562/* Command-line Options. */
563
564bfd_boolean use_literal_section = TRUE;
565static bfd_boolean align_targets = TRUE;
43cd72b9 566static bfd_boolean warn_unaligned_branch_targets = FALSE;
e0001a05 567static bfd_boolean has_a0_b_retw = FALSE;
43cd72b9
BW		 568static bfd_boolean workaround_a0_b_retw = FALSE;
569static bfd_boolean workaround_b_j_loop_end = FALSE;
570static bfd_boolean workaround_short_loop = FALSE;
e0001a05 571static bfd_boolean maybe_has_short_loop = FALSE;
43cd72b9 572static bfd_boolean workaround_close_loop_end = FALSE;
e0001a05
NC		 573static bfd_boolean maybe_has_close_loop_end = FALSE;
574
43cd72b9
BW		 575/* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
e0001a05 580
43cd72b9 581static bfd_boolean workaround_all_short_loops = FALSE;
e0001a05 582
7fa3d080
BW		 583
584static void
585xtensa_setup_hw_workarounds (int earliest, int latest)
586{
587 if (earliest > latest)
588 as_fatal (_("illegal range of target hardware versions"));
589
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest < 105000 || latest < 105000)
592 {
593 workaround_a0_b_retw |= TRUE;
594 workaround_b_j_loop_end |= TRUE;
595 workaround_short_loop |= TRUE;
596 workaround_close_loop_end |= TRUE;
597 workaround_all_short_loops |= TRUE;
598 }
599}
600
601
e0001a05
NC		 602enum
603{
604 option_density = OPTION_MD_BASE,
605 option_no_density,
606
607 option_relax,
608 option_no_relax,
609
43cd72b9
BW		 610 option_link_relax,
611 option_no_link_relax,
612
e0001a05
NC		 613 option_generics,
614 option_no_generics,
615
43cd72b9
BW		 616 option_transform,
617 option_no_transform,
618
e0001a05
NC		 619 option_text_section_literals,
620 option_no_text_section_literals,
621
43cd72b9
BW		 622 option_absolute_literals,
623 option_no_absolute_literals,
624
e0001a05
NC		 625 option_align_targets,
626 option_no_align_targets,
627
43cd72b9 628 option_warn_unaligned_targets,
e0001a05
NC		 629
630 option_longcalls,
631 option_no_longcalls,
632
633 option_workaround_a0_b_retw,
634 option_no_workaround_a0_b_retw,
635
636 option_workaround_b_j_loop_end,
637 option_no_workaround_b_j_loop_end,
638
639 option_workaround_short_loop,
640 option_no_workaround_short_loop,
641
642 option_workaround_all_short_loops,
643 option_no_workaround_all_short_loops,
644
645 option_workaround_close_loop_end,
646 option_no_workaround_close_loop_end,
647
648 option_no_workarounds,
649
e0001a05 650 option_rename_section_name,
e0001a05 651
43cd72b9
BW		 652 option_prefer_l32r,
653 option_prefer_const16,
654
655 option_target_hardware
e0001a05
NC		 656};
657
658const char *md_shortopts = "";
659
660struct option md_longopts[] =
661{
43cd72b9
BW		 662 { "density", no_argument, NULL, option_density },
663 { "no-density", no_argument, NULL, option_no_density },
664
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument, NULL, option_relax },
668 { "no-relax", no_argument, NULL, option_no_relax },
669 { "generics", no_argument, NULL, option_generics },
670 { "no-generics", no_argument, NULL, option_no_generics },
671
672 { "transform", no_argument, NULL, option_transform },
673 { "no-transform", no_argument, NULL, option_no_transform },
674 { "text-section-literals", no_argument, NULL, option_text_section_literals },
675 { "no-text-section-literals", no_argument, NULL,
676 option_no_text_section_literals },
677 { "absolute-literals", no_argument, NULL, option_absolute_literals },
678 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
e0001a05
NC		 679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
43cd72b9 681 { "target-align", no_argument, NULL, option_align_targets },
7fa3d080
BW		 682 { "no-target-align", no_argument, NULL, option_no_align_targets },
683 { "warn-unaligned-targets", no_argument, NULL,
684 option_warn_unaligned_targets },
43cd72b9
BW		 685 { "longcalls", no_argument, NULL, option_longcalls },
686 { "no-longcalls", no_argument, NULL, option_no_longcalls },
687
688 { "no-workaround-a0-b-retw", no_argument, NULL,
689 option_no_workaround_a0_b_retw },
690 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
e0001a05 691
43cd72b9
BW		 692 { "no-workaround-b-j-loop-end", no_argument, NULL,
693 option_no_workaround_b_j_loop_end },
694 { "workaround-b-j-loop-end", no_argument, NULL,
695 option_workaround_b_j_loop_end },
e0001a05 696
43cd72b9
BW		 697 { "no-workaround-short-loops", no_argument, NULL,
698 option_no_workaround_short_loop },
7fa3d080
BW		 699 { "workaround-short-loops", no_argument, NULL,
700 option_workaround_short_loop },
e0001a05 701
43cd72b9
BW		 702 { "no-workaround-all-short-loops", no_argument, NULL,
703 option_no_workaround_all_short_loops },
704 { "workaround-all-short-loop", no_argument, NULL,
705 option_workaround_all_short_loops },
706
707 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
708 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
709
710 { "no-workarounds", no_argument, NULL, option_no_workarounds },
711
712 { "no-workaround-close-loop-end", no_argument, NULL,
713 option_no_workaround_close_loop_end },
714 { "workaround-close-loop-end", no_argument, NULL,
715 option_workaround_close_loop_end },
e0001a05 716
7fa3d080 717 { "rename-section", required_argument, NULL, option_rename_section_name },
e0001a05 718
43cd72b9
BW		 719 { "link-relax", no_argument, NULL, option_link_relax },
720 { "no-link-relax", no_argument, NULL, option_no_link_relax },
721
722 { "target-hardware", required_argument, NULL, option_target_hardware },
723
724 { NULL, no_argument, NULL, 0 }
e0001a05
NC		 725};
726
727size_t md_longopts_size = sizeof md_longopts;
728
729
730int
7fa3d080 731md_parse_option (int c, char *arg)
e0001a05
NC		 732{
733 switch (c)
734 {
735 case option_density:
43cd72b9 736 as_warn (_("--density option is ignored"));
e0001a05
NC		 737 return 1;
738 case option_no_density:
43cd72b9 739 as_warn (_("--no-density option is ignored"));
e0001a05 740 return 1;
43cd72b9
BW		 741 case option_link_relax:
742 linkrelax = 1;
e0001a05 743 return 1;
43cd72b9
BW		 744 case option_no_link_relax:
745 linkrelax = 0;
e0001a05 746 return 1;
43cd72b9
BW		 747 case option_generics:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform, arg);
750 case option_no_generics:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform, arg);
753 case option_relax:
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform, arg);
756 case option_no_relax:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform, arg);
e0001a05
NC		 759 case option_longcalls:
760 directive_state[directive_longcalls] = TRUE;
761 return 1;
762 case option_no_longcalls:
763 directive_state[directive_longcalls] = FALSE;
764 return 1;
765 case option_text_section_literals:
766 use_literal_section = FALSE;
767 return 1;
768 case option_no_text_section_literals:
769 use_literal_section = TRUE;
770 return 1;
43cd72b9
BW		 771 case option_absolute_literals:
772 if (!absolute_literals_supported)
773 {
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
775 return 0;
776 }
777 directive_state[directive_absolute_literals] = TRUE;
778 return 1;
779 case option_no_absolute_literals:
780 directive_state[directive_absolute_literals] = FALSE;
781 return 1;
782
e0001a05
NC		 783 case option_workaround_a0_b_retw:
784 workaround_a0_b_retw = TRUE;
e0001a05
NC		 785 return 1;
786 case option_no_workaround_a0_b_retw:
787 workaround_a0_b_retw = FALSE;
e0001a05
NC		 788 return 1;
789 case option_workaround_b_j_loop_end:
790 workaround_b_j_loop_end = TRUE;
e0001a05
NC		 791 return 1;
792 case option_no_workaround_b_j_loop_end:
793 workaround_b_j_loop_end = FALSE;
e0001a05
NC		 794 return 1;
795
796 case option_workaround_short_loop:
797 workaround_short_loop = TRUE;
e0001a05
NC		 798 return 1;
799 case option_no_workaround_short_loop:
800 workaround_short_loop = FALSE;
e0001a05
NC		 801 return 1;
802
803 case option_workaround_all_short_loops:
804 workaround_all_short_loops = TRUE;
e0001a05
NC		 805 return 1;
806 case option_no_workaround_all_short_loops:
807 workaround_all_short_loops = FALSE;
e0001a05
NC		 808 return 1;
809
810 case option_workaround_close_loop_end:
811 workaround_close_loop_end = TRUE;
e0001a05
NC		 812 return 1;
813 case option_no_workaround_close_loop_end:
814 workaround_close_loop_end = FALSE;
e0001a05
NC		 815 return 1;
816
817 case option_no_workarounds:
818 workaround_a0_b_retw = FALSE;
e0001a05 819 workaround_b_j_loop_end = FALSE;
e0001a05 820 workaround_short_loop = FALSE;
e0001a05 821 workaround_all_short_loops = FALSE;
e0001a05 822 workaround_close_loop_end = FALSE;
e0001a05 823 return 1;
43cd72b9 824
e0001a05
NC		 825 case option_align_targets:
826 align_targets = TRUE;
827 return 1;
828 case option_no_align_targets:
829 align_targets = FALSE;
830 return 1;
831
43cd72b9
BW		 832 case option_warn_unaligned_targets:
833 warn_unaligned_branch_targets = TRUE;
e0001a05
NC		 834 return 1;
835
e0001a05
NC		 836 case option_rename_section_name:
837 build_section_rename (arg);
838 return 1;
e0001a05
NC		 839
840 case 'Q':
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
843 return 1;
844
43cd72b9
BW		 845 case option_prefer_l32r:
846 if (prefer_const16)
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
848 prefer_l32r = 1;
849 return 1;
850
851 case option_prefer_const16:
852 if (prefer_l32r)
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
854 prefer_const16 = 1;
855 return 1;
856
857 case option_target_hardware:
858 {
859 int earliest, latest = 0;
860 if (*arg == 0 || *arg == '-')
861 as_fatal (_("invalid target hardware version"));
862
863 earliest = strtol (arg, &arg, 0);
864
865 if (*arg == 0)
866 latest = earliest;
867 else if (*arg == '-')
868 {
869 if (*++arg == 0)
870 as_fatal (_("invalid target hardware version"));
871 latest = strtol (arg, &arg, 0);
872 }
873 if (*arg != 0)
874 as_fatal (_("invalid target hardware version"));
875
876 xtensa_setup_hw_workarounds (earliest, latest);
877 return 1;
878 }
879
880 case option_transform:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
883 return 1;
884
885 case option_no_transform:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state[directive_transform] = FALSE;
893 return 1;
894
e0001a05
NC		 895 default:
896 return 0;
897 }
898}
899
900
901void
7fa3d080 902md_show_usage (FILE *stream)
e0001a05 903{
43cd72b9
BW		 904 fputs ("\n\
905Xtensa options:\n\
9456465c
BW		 906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream);
e0001a05
NC		 914}
915
7fa3d080
BW		 916\f
917/* Functions related to the list of current label symbols. */
43cd72b9
BW		 918
919static void
7fa3d080 920xtensa_add_insn_label (symbolS *sym)
43cd72b9 921{
7fa3d080 922 sym_list *l;
43cd72b9 923
7fa3d080
BW		 924 if (!free_insn_labels)
925 l = (sym_list *) xmalloc (sizeof (sym_list));
926 else
43cd72b9 927 {
7fa3d080
BW		 928 l = free_insn_labels;
929 free_insn_labels = l->next;
930 }
931
932 l->sym = sym;
933 l->next = insn_labels;
934 insn_labels = l;
935}
936
937
938static void
939xtensa_clear_insn_labels (void)
940{
941 sym_list **pl;
942
943 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
944 ;
945 *pl = insn_labels;
946 insn_labels = NULL;
947}
948
949
950/* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
953
954 loop a0, loopend
955 <loop1 body>
956 loopend:
957
958 loop a2, loopend2
959 <loop2 body>
960
961 would become:
962
963 loop a0, loopend
964 <loop1 body>
965 nop.n <===== bad!
966 loopend:
967
968 loop a2, loopend2
969 <loop2 body>
970
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
973
974static void
975xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
976{
977 sym_list *lit;
978
979 for (lit = insn_labels; lit; lit = lit->next)
980 {
981 symbolS *lit_sym = lit->sym;
982 if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
983 {
984 S_SET_VALUE (lit_sym, new_offset);
985 symbol_set_frag (lit_sym, new_frag);
986 }
43cd72b9
BW		 987 }
988}
989
e0001a05
NC		 990\f
991/* Directive data and functions. */
992
993typedef struct state_stackS_struct
994{
995 directiveE directive;
996 bfd_boolean negated;
997 bfd_boolean old_state;
998 const char *file;
999 unsigned int line;
1000 const void *datum;
1001 struct state_stackS_struct *prev;
1002} state_stackS;
1003
1004state_stackS *directive_state_stack;
1005
1006const pseudo_typeS md_pseudo_table[] =
1007{
43cd72b9
BW		 1008 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position, 0 },
1010 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons, 4 },
1012 { "word", xtensa_elf_cons, 4 },
1013 { "short", xtensa_elf_cons, 2 },
1014 { "begin", xtensa_begin_directive, 0 },
1015 { "end", xtensa_end_directive, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc, 0 },
1017 { "literal", xtensa_literal_pseudo, 0 },
1018 { "frequency", xtensa_frequency_pseudo, 0 },
1019 { NULL, 0, 0 },
e0001a05
NC		 1020};
1021
1022
7fa3d080
BW		 1023static bfd_boolean
1024use_transform (void)
e0001a05 1025{
43cd72b9
BW		 1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end);
1029 return directive_state[directive_transform];
e0001a05
NC		 1030}
1031
1032
7fa3d080
BW		 1033static bfd_boolean
1034use_longcalls (void)
e0001a05 1035{
43cd72b9
BW		 1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end);
1039 return directive_state[directive_longcalls] && use_transform ();
e0001a05
NC		 1040}
1041
1042
7fa3d080
BW		 1043static bfd_boolean
1044do_align_targets (void)
e0001a05 1045{
43cd72b9
BW		 1046 /* After md_end, you should be checking frag by frag, rather
1047 than state directives. */
1048 assert (!past_xtensa_end);
1049 return align_targets && use_transform ();
e0001a05
NC		 1050}
1051
1052
1053static void
7fa3d080 1054directive_push (directiveE directive, bfd_boolean negated, const void *datum)
e0001a05
NC		 1055{
1056 char *file;
1057 unsigned int line;
1058 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1059
1060 as_where (&file, &line);
1061
1062 stack->directive = directive;
1063 stack->negated = negated;
1064 stack->old_state = directive_state[directive];
1065 stack->file = file;
1066 stack->line = line;
1067 stack->datum = datum;
1068 stack->prev = directive_state_stack;
1069 directive_state_stack = stack;
1070
1071 directive_state[directive] = !negated;
1072}
1073
7fa3d080 1074
e0001a05 1075static void
7fa3d080
BW		 1076directive_pop (directiveE *directive,
1077 bfd_boolean *negated,
1078 const char **file,
1079 unsigned int *line,
1080 const void **datum)
e0001a05
NC		 1081{
1082 state_stackS *top = directive_state_stack;
1083
1084 if (!directive_state_stack)
1085 {
1086 as_bad (_("unmatched end directive"));
1087 *directive = directive_none;
1088 return;
1089 }
1090
1091 directive_state[directive_state_stack->directive] = top->old_state;
1092 *directive = top->directive;
1093 *negated = top->negated;
1094 *file = top->file;
1095 *line = top->line;
1096 *datum = top->datum;
1097 directive_state_stack = top->prev;
1098 free (top);
1099}
1100
1101
1102static void
7fa3d080 1103directive_balance (void)
e0001a05
NC		 1104{
1105 while (directive_state_stack)
1106 {
1107 directiveE directive;
1108 bfd_boolean negated;
1109 const char *file;
1110 unsigned int line;
1111 const void *datum;
1112
1113 directive_pop (&directive, &negated, &file, &line, &datum);
1114 as_warn_where ((char *) file, line,
1115 _(".begin directive with no matching .end directive"));
1116 }
1117}
1118
1119
1120static bfd_boolean
7fa3d080 1121inside_directive (directiveE dir)
e0001a05
NC		 1122{
1123 state_stackS *top = directive_state_stack;
1124
1125 while (top && top->directive != dir)
1126 top = top->prev;
1127
1128 return (top != NULL);
1129}
1130
1131
1132static void
7fa3d080 1133get_directive (directiveE *directive, bfd_boolean *negated)
e0001a05
NC		 1134{
1135 int len;
1136 unsigned i;
43cd72b9 1137 char *directive_string;
e0001a05
NC		 1138
1139 if (strncmp (input_line_pointer, "no-", 3) != 0)
1140 *negated = FALSE;
1141 else
1142 {
1143 *negated = TRUE;
1144 input_line_pointer += 3;
1145 }
1146
1147 len = strspn (input_line_pointer,
43cd72b9
BW		 1148 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1149
1150 /* This code is a hack to make .begin [no-][generics|relax] exactly
1151 equivalent to .begin [no-]transform. We should remove it when
1152 we stop accepting those options. */
1153
1154 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1155 {
1156 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1157 directive_string = "transform";
1158 }
1159 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1160 {
1161 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1162 directive_string = "transform";
1163 }
1164 else
1165 directive_string = input_line_pointer;
e0001a05
NC		 1166
1167 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1168 {
43cd72b9 1169 if (strncmp (directive_string, directive_info[i].name, len) == 0)
e0001a05
NC		 1170 {
1171 input_line_pointer += len;
1172 *directive = (directiveE) i;
1173 if (*negated && !directive_info[i].can_be_negated)
43cd72b9 1174 as_bad (_("directive %s cannot be negated"),
e0001a05
NC		 1175 directive_info[i].name);
1176 return;
1177 }
1178 }
1179
1180 as_bad (_("unknown directive"));
1181 *directive = (directiveE) XTENSA_UNDEFINED;
1182}
1183
1184
1185static void
7fa3d080 1186xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
e0001a05
NC		 1187{
1188 directiveE directive;
1189 bfd_boolean negated;
1190 emit_state *state;
1191 int len;
1192 lit_state *ls;
1193
1194 get_directive (&directive, &negated);
1195 if (directive == (directiveE) XTENSA_UNDEFINED)
1196 {
1197 discard_rest_of_line ();
1198 return;
1199 }
1200
43cd72b9
BW		 1201 if (cur_vinsn.inside_bundle)
1202 as_bad (_("directives are not valid inside bundles"));
1203
e0001a05
NC		 1204 switch (directive)
1205 {
1206 case directive_literal:
82e7541d
BW		 1207 if (!inside_directive (directive_literal))
1208 {
1209 /* Previous labels go with whatever follows this directive, not with
1210 the literal, so save them now. */
1211 saved_insn_labels = insn_labels;
1212 insn_labels = NULL;
1213 }
43cd72b9 1214 as_warn (_(".begin literal is deprecated; use .literal instead"));
e0001a05
NC		 1215 state = (emit_state *) xmalloc (sizeof (emit_state));
1216 xtensa_switch_to_literal_fragment (state);
1217 directive_push (directive_literal, negated, state);
1218 break;
1219
1220 case directive_literal_prefix:
43cd72b9
BW		 1221 /* Have to flush pending output because a movi relaxed to an l32r
1222 might produce a literal. */
1223 md_flush_pending_output ();
e0001a05
NC		 1224 /* Check to see if the current fragment is a literal
1225 fragment. If it is, then this operation is not allowed. */
43cd72b9 1226 if (generating_literals)
e0001a05
NC		 1227 {
1228 as_bad (_("cannot set literal_prefix inside literal fragment"));
1229 return;
1230 }
1231
1232 /* Allocate the literal state for this section and push
1233 onto the directive stack. */
1234 ls = xmalloc (sizeof (lit_state));
1235 assert (ls);
1236
1237 *ls = default_lit_sections;
1238
1239 directive_push (directive_literal_prefix, negated, ls);
1240
1241 /* Parse the new prefix from the input_line_pointer. */
1242 SKIP_WHITESPACE ();
1243 len = strspn (input_line_pointer,
1244 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1245 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1246
1247 /* Process the new prefix. */
1248 xtensa_literal_prefix (input_line_pointer, len);
1249
1250 /* Skip the name in the input line. */
1251 input_line_pointer += len;
1252 break;
1253
1254 case directive_freeregs:
1255 /* This information is currently unused, but we'll accept the statement
1256 and just discard the rest of the line. This won't check the syntax,
1257 but it will accept every correct freeregs directive. */
1258 input_line_pointer += strcspn (input_line_pointer, "\n");
1259 directive_push (directive_freeregs, negated, 0);
1260 break;
1261
43cd72b9
BW		 1262 case directive_schedule:
1263 md_flush_pending_output ();
1264 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1265 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1266 directive_push (directive_schedule, negated, 0);
1267 xtensa_set_frag_assembly_state (frag_now);
1268 break;
1269
e0001a05 1270 case directive_density:
43cd72b9
BW		 1271 as_warn (_(".begin [no-]density is ignored"));
1272 break;
1273
1274 case directive_absolute_literals:
1275 md_flush_pending_output ();
1276 if (!absolute_literals_supported && !negated)
e0001a05 1277 {
43cd72b9 1278 as_warn (_("Xtensa absolute literals option not supported; ignored"));
e0001a05
NC		 1279 break;
1280 }
43cd72b9
BW		 1281 xtensa_set_frag_assembly_state (frag_now);
1282 directive_push (directive, negated, 0);
1283 break;
e0001a05
NC		 1284
1285 default:
43cd72b9
BW		 1286 md_flush_pending_output ();
1287 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1288 directive_push (directive, negated, 0);
1289 break;
1290 }
1291
1292 demand_empty_rest_of_line ();
1293}
1294
1295
1296static void
7fa3d080 1297xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
e0001a05
NC		 1298{
1299 directiveE begin_directive, end_directive;
1300 bfd_boolean begin_negated, end_negated;
1301 const char *file;
1302 unsigned int line;
1303 emit_state *state;
43cd72b9 1304 emit_state **state_ptr;
e0001a05
NC		 1305 lit_state *s;
1306
43cd72b9
BW		 1307 if (cur_vinsn.inside_bundle)
1308 as_bad (_("directives are not valid inside bundles"));
82e7541d 1309
e0001a05 1310 get_directive (&end_directive, &end_negated);
43cd72b9
BW		 1311
1312 md_flush_pending_output ();
1313
1314 switch (end_directive)
e0001a05 1315 {
43cd72b9 1316 case (directiveE) XTENSA_UNDEFINED:
e0001a05
NC		 1317 discard_rest_of_line ();
1318 return;
e0001a05 1319
43cd72b9
BW		 1320 case directive_density:
1321 as_warn (_(".end [no-]density is ignored"));
e0001a05 1322 demand_empty_rest_of_line ();
43cd72b9
BW		 1323 break;
1324
1325 case directive_absolute_literals:
1326 if (!absolute_literals_supported && !end_negated)
1327 {
1328 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1329 demand_empty_rest_of_line ();
1330 return;
1331 }
1332 break;
1333
1334 default:
1335 break;
e0001a05
NC		 1336 }
1337
43cd72b9 1338 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
e0001a05 1339 directive_pop (&begin_directive, &begin_negated, &file, &line,
43cd72b9 1340 (const void **) state_ptr);
e0001a05
NC		 1341
1342 if (begin_directive != directive_none)
1343 {
1344 if (begin_directive != end_directive || begin_negated != end_negated)
1345 {
1346 as_bad (_("does not match begin %s%s at %s:%d"),
1347 begin_negated ? "no-" : "",
1348 directive_info[begin_directive].name, file, line);
1349 }
1350 else
1351 {
1352 switch (end_directive)
1353 {
1354 case directive_literal:
1355 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1356 xtensa_restore_emit_state (state);
43cd72b9 1357 xtensa_set_frag_assembly_state (frag_now);
e0001a05 1358 free (state);
82e7541d
BW		 1359 if (!inside_directive (directive_literal))
1360 {
1361 /* Restore the list of current labels. */
1362 xtensa_clear_insn_labels ();
1363 insn_labels = saved_insn_labels;
1364 }
e0001a05
NC		 1365 break;
1366
e0001a05
NC		 1367 case directive_literal_prefix:
1368 /* Restore the default collection sections from saved state. */
1369 s = (lit_state *) state;
1370 assert (s);
1371
1372 if (use_literal_section)
1373 default_lit_sections = *s;
1374
1375 /* free the state storage */
1376 free (s);
1377 break;
1378
43cd72b9
BW		 1379 case directive_schedule:
1380 case directive_freeregs:
1381 break;
1382
e0001a05 1383 default:
43cd72b9 1384 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1385 break;
1386 }
1387 }
1388 }
1389
1390 demand_empty_rest_of_line ();
1391}
1392
1393
43cd72b9
BW		 1394/* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1395
1396static bfd_boolean xtensa_loc_directive_seen = FALSE;
1397
1398static void
7fa3d080 1399xtensa_dwarf2_directive_loc (int x)
43cd72b9
BW		 1400{
1401 xtensa_loc_directive_seen = TRUE;
1402 dwarf2_directive_loc (x);
1403}
1404
1405
1406static void
7fa3d080 1407xtensa_dwarf2_emit_insn (int size, struct dwarf2_line_info *loc)
43cd72b9
BW		 1408{
1409 if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen)
1410 return;
1411 xtensa_loc_directive_seen = FALSE;
1412 dwarf2_gen_line_info (frag_now_fix () - size, loc);
1413}
1414
1415
e0001a05
NC		 1416/* Place an aligned literal fragment at the current location. */
1417
1418static void
7fa3d080 1419xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
e0001a05 1420{
43cd72b9
BW		 1421 md_flush_pending_output ();
1422
e0001a05
NC		 1423 if (inside_directive (directive_literal))
1424 as_warn (_(".literal_position inside literal directive; ignoring"));
43cd72b9 1425 xtensa_mark_literal_pool_location ();
e0001a05
NC		 1426
1427 demand_empty_rest_of_line ();
82e7541d 1428 xtensa_clear_insn_labels ();
e0001a05
NC		 1429}
1430
1431
43cd72b9 1432/* Support .literal label, expr, ... */
e0001a05
NC		 1433
1434static void
7fa3d080 1435xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
e0001a05
NC		 1436{
1437 emit_state state;
1745fcba 1438 char *p, *base_name;
e0001a05 1439 char c;
e0001a05
NC		 1440 segT dest_seg;
1441
82e7541d
BW		 1442 if (inside_directive (directive_literal))
1443 {
1444 as_bad (_(".literal not allowed inside .begin literal region"));
1445 ignore_rest_of_line ();
1446 return;
1447 }
1448
43cd72b9
BW		 1449 md_flush_pending_output ();
1450
82e7541d
BW		 1451 /* Previous labels go with whatever follows this directive, not with
1452 the literal, so save them now. */
1453 saved_insn_labels = insn_labels;
1454 insn_labels = NULL;
1455
e0001a05
NC		 1456 /* If we are using text-section literals, then this is the right value... */
1457 dest_seg = now_seg;
1458
1459 base_name = input_line_pointer;
1460
1461 xtensa_switch_to_literal_fragment (&state);
1462
43cd72b9 1463 /* ...but if we aren't using text-section-literals, then we
e0001a05 1464 need to put them in the section we just switched to. */
43cd72b9 1465 if (use_literal_section || directive_state[directive_absolute_literals])
e0001a05
NC		 1466 dest_seg = now_seg;
1467
43cd72b9
BW		 1468 /* All literals are aligned to four-byte boundaries. */
1469 frag_align (2, 0, 0);
1470 record_alignment (now_seg, 2);
e0001a05
NC		 1471
1472 c = get_symbol_end ();
1473 /* Just after name is now '\0'. */
1474 p = input_line_pointer;
1475 *p = c;
1476 SKIP_WHITESPACE ();
1477
1478 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1479 {
1480 as_bad (_("expected comma or colon after symbol name; "
1481 "rest of line ignored"));
1482 ignore_rest_of_line ();
1483 xtensa_restore_emit_state (&state);
1484 return;
1485 }
1486 *p = 0;
1487
e0001a05 1488 colon (base_name);
e0001a05 1489
e0001a05 1490 *p = c;
43cd72b9 1491 input_line_pointer++; /* skip ',' or ':' */
e0001a05 1492
43cd72b9 1493 xtensa_elf_cons (4);
e0001a05
NC		 1494
1495 xtensa_restore_emit_state (&state);
82e7541d
BW		 1496
1497 /* Restore the list of current labels. */
1498 xtensa_clear_insn_labels ();
1499 insn_labels = saved_insn_labels;
e0001a05
NC		 1500}
1501
1502
1503static void
7fa3d080 1504xtensa_literal_prefix (char const *start, int len)
e0001a05 1505{
43cd72b9
BW		 1506 char *name, *linkonce_suffix;
1507 char *newname, *newname4;
1508 size_t linkonce_len;
e0001a05
NC		 1509
1510 /* Get a null-terminated copy of the name. */
1511 name = xmalloc (len + 1);
1512 assert (name);
1513
1514 strncpy (name, start, len);
1515 name[len] = 0;
1516
1517 /* Allocate the sections (interesting note: the memory pointing to
1518 the name is actually used for the name by the new section). */
43cd72b9 1519
e0001a05 1520 newname = xmalloc (len + strlen (".literal") + 1);
43cd72b9 1521 newname4 = xmalloc (len + strlen (".lit4") + 1);
e0001a05 1522
43cd72b9
BW		 1523 linkonce_len = sizeof (".gnu.linkonce.") - 1;
1524 if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
1525 && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
1526 {
1527 strcpy (newname, ".gnu.linkonce.literal");
1528 strcpy (newname4, ".gnu.linkonce.lit4");
e0001a05 1529
43cd72b9
BW		 1530 strcat (newname, linkonce_suffix);
1531 strcat (newname4, linkonce_suffix);
1532 }
1533 else
1534 {
1535 int suffix_pos = len;
1536
1537 /* If the section name ends with ".text", then replace that suffix
1538 instead of appending an additional suffix. */
1539 if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
1540 suffix_pos -= 5;
1541
1542 strcpy (newname, name);
1543 strcpy (newname4, name);
1544
1545 strcpy (newname + suffix_pos, ".literal");
1546 strcpy (newname4 + suffix_pos, ".lit4");
1547 }
1548
b08b5071 1549 /* Note that cache_literal_section does not create a segment if
43cd72b9
BW		 1550 it already exists. */
1551 default_lit_sections.lit_seg = NULL;
1552 default_lit_sections.lit4_seg = NULL;
1553
1554 /* Canonicalizing section names allows renaming literal
e0001a05 1555 sections to occur correctly. */
43cd72b9
BW		 1556 default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
1557 default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
e0001a05
NC		 1558
1559 free (name);
43cd72b9
BW		 1560}
1561
1562
1563/* Support ".frequency branch_target_frequency fall_through_frequency". */
1564
1565static void
7fa3d080 1566xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
43cd72b9
BW		 1567{
1568 float fall_through_f, target_f;
43cd72b9
BW		 1569
1570 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1571 if (fall_through_f < 0)
1572 {
1573 as_bad (_("fall through frequency must be greater than 0"));
1574 ignore_rest_of_line ();
1575 return;
1576 }
1577
1578 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1579 if (target_f < 0)
1580 {
1581 as_bad (_("branch target frequency must be greater than 0"));
1582 ignore_rest_of_line ();
1583 return;
1584 }
1585
b08b5071 1586 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
43cd72b9
BW		 1587
1588 demand_empty_rest_of_line ();
1589}
1590
1591
1592/* Like normal .long/.short/.word, except support @plt, etc.
1593 Clobbers input_line_pointer, checks end-of-line. */
1594
1595static void
7fa3d080 1596xtensa_elf_cons (int nbytes)
43cd72b9
BW		 1597{
1598 expressionS exp;
1599 bfd_reloc_code_real_type reloc;
1600
1601 md_flush_pending_output ();
1602
1603 if (cur_vinsn.inside_bundle)
1604 as_bad (_("directives are not valid inside bundles"));
1605
1606 if (is_it_end_of_statement ())
1607 {
1608 demand_empty_rest_of_line ();
1609 return;
1610 }
1611
1612 do
1613 {
1614 expression (&exp);
1615 if (exp.X_op == O_symbol
1616 && *input_line_pointer == '@'
1617 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1618 != BFD_RELOC_NONE))
1619 {
1620 reloc_howto_type *reloc_howto =
1621 bfd_reloc_type_lookup (stdoutput, reloc);
1622
1623 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1624 as_bad (_("unsupported relocation"));
1625 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1626 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1627 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1628 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1629 as_bad (_("opcode-specific %s relocation used outside "
1630 "an instruction"), reloc_howto->name);
1631 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1632 as_bad (_("%s relocations do not fit in %d bytes"),
1633 reloc_howto->name, nbytes);
1634 else
1635 {
1636 char *p = frag_more ((int) nbytes);
1637 xtensa_set_frag_assembly_state (frag_now);
1638 fix_new_exp (frag_now, p - frag_now->fr_literal,
1639 nbytes, &exp, 0, reloc);
1640 }
1641 }
1642 else
1643 emit_expr (&exp, (unsigned int) nbytes);
1644 }
1645 while (*input_line_pointer++ == ',');
1646
1647 input_line_pointer--; /* Put terminator back into stream. */
1648 demand_empty_rest_of_line ();
1649}
1650
7fa3d080
BW		 1651\f
1652/* Parsing and Idiom Translation. */
43cd72b9
BW		 1653
1654/* Parse @plt, etc. and return the desired relocation. */
1655static bfd_reloc_code_real_type
7fa3d080 1656xtensa_elf_suffix (char **str_p, expressionS *exp_p)
43cd72b9
BW		 1657{
1658 struct map_bfd
1659 {
1660 char *string;
1661 int length;
1662 bfd_reloc_code_real_type reloc;
1663 };
1664
1665 char ident[20];
1666 char *str = *str_p;
1667 char *str2;
1668 int ch;
1669 int len;
1670 struct map_bfd *ptr;
1671
1672#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
e0001a05 1673
43cd72b9
BW		 1674 static struct map_bfd mapping[] =
1675 {
1676 MAP ("l", BFD_RELOC_LO16),
1677 MAP ("h", BFD_RELOC_HI16),
1678 MAP ("plt", BFD_RELOC_XTENSA_PLT),
1679 { (char *) 0, 0, BFD_RELOC_UNUSED }
1680 };
1681
1682 if (*str++ != '@')
1683 return BFD_RELOC_NONE;
1684
1685 for (ch = *str, str2 = ident;
1686 (str2 < ident + sizeof (ident) - 1
1687 && (ISALNUM (ch) || ch == '@'));
1688 ch = *++str)
1689 {
1690 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1691 }
1692
1693 *str2 = '\0';
1694 len = str2 - ident;
1695
1696 ch = ident[0];
1697 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
1698 if (ch == ptr->string[0]
1699 && len == ptr->length
1700 && memcmp (ident, ptr->string, ptr->length) == 0)
1701 {
1702 /* Now check for "identifier@suffix+constant". */
1703 if (*str == '-' || *str == '+')
1704 {
1705 char *orig_line = input_line_pointer;
1706 expressionS new_exp;
1707
1708 input_line_pointer = str;
1709 expression (&new_exp);
1710 if (new_exp.X_op == O_constant)
1711 {
1712 exp_p->X_add_number += new_exp.X_add_number;
1713 str = input_line_pointer;
1714 }
1715
1716 if (&input_line_pointer != str_p)
1717 input_line_pointer = orig_line;
1718 }
1719
1720 *str_p = str;
1721 return ptr->reloc;
1722 }
1723
1724 return BFD_RELOC_UNUSED;
e0001a05
NC		 1725}
1726
e0001a05
NC		 1727
1728static const char *
7fa3d080 1729expression_end (const char *name)
e0001a05
NC		 1730{
1731 while (1)
1732 {
1733 switch (*name)
1734 {
43cd72b9 1735 case '}':
e0001a05
NC		 1736 case ';':
1737 case '\0':
1738 case ',':
43cd72b9 1739 case ':':
e0001a05
NC		 1740 return name;
1741 case ' ':
1742 case '\t':
1743 ++name;
1744 continue;
1745 default:
1746 return 0;
1747 }
1748 }
1749}
1750
1751
1752#define ERROR_REG_NUM ((unsigned) -1)
1753
1754static unsigned
7fa3d080 1755tc_get_register (const char *prefix)
e0001a05
NC		 1756{
1757 unsigned reg;
1758 const char *next_expr;
1759 const char *old_line_pointer;
1760
1761 SKIP_WHITESPACE ();
1762 old_line_pointer = input_line_pointer;
1763
1764 if (*input_line_pointer == '$')
1765 ++input_line_pointer;
1766
1767 /* Accept "sp" as a synonym for "a1". */
1768 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1769 && expression_end (input_line_pointer + 2))
1770 {
1771 input_line_pointer += 2;
1772 return 1; /* AR[1] */
1773 }
1774
1775 while (*input_line_pointer++ == *prefix++)
1776 ;
1777 --input_line_pointer;
1778 --prefix;
1779
1780 if (*prefix)
1781 {
1782 as_bad (_("bad register name: %s"), old_line_pointer);
1783 return ERROR_REG_NUM;
1784 }
1785
1786 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1787 {
1788 as_bad (_("bad register number: %s"), input_line_pointer);
1789 return ERROR_REG_NUM;
1790 }
1791
1792 reg = 0;
1793
1794 while (ISDIGIT ((int) *input_line_pointer))
1795 reg = reg * 10 + *input_line_pointer++ - '0';
1796
1797 if (!(next_expr = expression_end (input_line_pointer)))
1798 {
1799 as_bad (_("bad register name: %s"), old_line_pointer);
1800 return ERROR_REG_NUM;
1801 }
1802
1803 input_line_pointer = (char *) next_expr;
1804
1805 return reg;
1806}
1807
1808
e0001a05 1809static void
7fa3d080 1810expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
e0001a05 1811{
43cd72b9 1812 xtensa_isa isa = xtensa_default_isa;
e0001a05 1813
43cd72b9
BW		 1814 /* Check if this is an immediate operand. */
1815 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
e0001a05 1816 {
43cd72b9 1817 bfd_reloc_code_real_type reloc;
e0001a05 1818 segT t = expression (tok);
43cd72b9
BW		 1819 if (t == absolute_section
1820 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
e0001a05
NC		 1821 {
1822 assert (tok->X_op == O_constant);
1823 tok->X_op = O_symbol;
1824 tok->X_add_symbol = &abs_symbol;
1825 }
43cd72b9
BW		 1826
1827 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1828 && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1829 && (reloc != BFD_RELOC_NONE))
e0001a05 1830 {
43cd72b9
BW		 1831 switch (reloc)
1832 {
1833 default:
1834 case BFD_RELOC_UNUSED:
1835 as_bad (_("unsupported relocation"));
1836 break;
1837
1838 case BFD_RELOC_XTENSA_PLT:
1839 tok->X_op = O_pltrel;
1840 break;
1841
1842 case BFD_RELOC_LO16:
1843 if (tok->X_op == O_constant)
1844 tok->X_add_number &= 0xffff;
1845 else
1846 tok->X_op = O_lo16;
1847 break;
1848
1849 case BFD_RELOC_HI16:
1850 if (tok->X_op == O_constant)
1851 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1852 else
1853 tok->X_op = O_hi16;
1854 break;
1855 }
e0001a05 1856 }
e0001a05
NC		 1857 }
1858 else
1859 {
43cd72b9
BW		 1860 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1861 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
e0001a05
NC		 1862
1863 if (reg != ERROR_REG_NUM) /* Already errored */
1864 {
1865 uint32 buf = reg;
43cd72b9 1866 if (xtensa_operand_encode (isa, opc, opnd, &buf))
e0001a05
NC		 1867 as_bad (_("register number out of range"));
1868 }
1869
1870 tok->X_op = O_register;
1871 tok->X_add_symbol = 0;
1872 tok->X_add_number = reg;
1873 }
1874}
1875
1876
1877/* Split up the arguments for an opcode or pseudo-op. */
1878
1879static int
7fa3d080 1880tokenize_arguments (char **args, char *str)
e0001a05
NC		 1881{
1882 char *old_input_line_pointer;
1883 bfd_boolean saw_comma = FALSE;
1884 bfd_boolean saw_arg = FALSE;
43cd72b9 1885 bfd_boolean saw_colon = FALSE;
e0001a05
NC		 1886 int num_args = 0;
1887 char *arg_end, *arg;
1888 int arg_len;
43cd72b9
BW		 1889
1890 /* Save and restore input_line_pointer around this function. */
e0001a05
NC		 1891 old_input_line_pointer = input_line_pointer;
1892 input_line_pointer = str;
1893
1894 while (*input_line_pointer)
1895 {
1896 SKIP_WHITESPACE ();
1897 switch (*input_line_pointer)
1898 {
1899 case '\0':
43cd72b9 1900 case '}':
e0001a05
NC		 1901 goto fini;
1902
43cd72b9
BW		 1903 case ':':
1904 input_line_pointer++;
1905 if (saw_comma || saw_colon || !saw_arg)
1906 goto err;
1907 saw_colon = TRUE;
1908 break;
1909
e0001a05
NC		 1910 case ',':
1911 input_line_pointer++;
43cd72b9 1912 if (saw_comma || saw_colon || !saw_arg)
e0001a05
NC		 1913 goto err;
1914 saw_comma = TRUE;
1915 break;
1916
1917 default:
43cd72b9 1918 if (!saw_comma && !saw_colon && saw_arg)
e0001a05
NC		 1919 goto err;
1920
1921 arg_end = input_line_pointer + 1;
1922 while (!expression_end (arg_end))
1923 arg_end += 1;
43cd72b9 1924
e0001a05 1925 arg_len = arg_end - input_line_pointer;
43cd72b9 1926 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
e0001a05
NC		 1927 args[num_args] = arg;
1928
43cd72b9
BW		 1929 if (saw_colon)
1930 *arg++ = ':';
e0001a05
NC		 1931 strncpy (arg, input_line_pointer, arg_len);
1932 arg[arg_len] = '\0';
43cd72b9 1933
e0001a05
NC		 1934 input_line_pointer = arg_end;
1935 num_args += 1;
1936 saw_comma = FALSE;
43cd72b9 1937 saw_colon = FALSE;
e0001a05
NC		 1938 saw_arg = TRUE;
1939 break;
1940 }
1941 }
1942
1943fini:
43cd72b9 1944 if (saw_comma || saw_colon)
e0001a05
NC		 1945 goto err;
1946 input_line_pointer = old_input_line_pointer;
1947 return num_args;
1948
1949err:
43cd72b9
BW		 1950 if (saw_comma)
1951 as_bad (_("extra comma"));
1952 else if (saw_colon)
1953 as_bad (_("extra colon"));
1954 else if (!saw_arg)
1955 as_bad (_("missing argument"));
1956 else
1957 as_bad (_("missing comma or colon"));
e0001a05
NC		 1958 input_line_pointer = old_input_line_pointer;
1959 return -1;
1960}
1961
1962
43cd72b9 1963/* Parse the arguments to an opcode. Return TRUE on error. */
e0001a05
NC		 1964
1965static bfd_boolean
7fa3d080 1966parse_arguments (TInsn *insn, int num_args, char **arg_strings)
e0001a05 1967{
43cd72b9 1968 expressionS *tok, *last_tok;
e0001a05
NC		 1969 xtensa_opcode opcode = insn->opcode;
1970 bfd_boolean had_error = TRUE;
43cd72b9
BW		 1971 xtensa_isa isa = xtensa_default_isa;
1972 int n, num_regs = 0;
e0001a05 1973 int opcode_operand_count;
43cd72b9
BW		 1974 int opnd_cnt, last_opnd_cnt;
1975 unsigned int next_reg = 0;
e0001a05
NC		 1976 char *old_input_line_pointer;
1977
1978 if (insn->insn_type == ITYPE_LITERAL)
1979 opcode_operand_count = 1;
1980 else
43cd72b9 1981 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
e0001a05 1982
43cd72b9 1983 tok = insn->tok;
e0001a05
NC		 1984 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
1985
1986 /* Save and restore input_line_pointer around this function. */
43cd72b9
BW		 1987 old_input_line_pointer = input_line_pointer;
1988
1989 last_tok = 0;
1990 last_opnd_cnt = -1;
1991 opnd_cnt = 0;
1992
1993 /* Skip invisible operands. */
1994 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
1995 {
1996 opnd_cnt += 1;
1997 tok++;
1998 }
e0001a05
NC		 1999
2000 for (n = 0; n < num_args; n++)
43cd72b9 2001 {
e0001a05 2002 input_line_pointer = arg_strings[n];
43cd72b9
BW		 2003 if (*input_line_pointer == ':')
2004 {
2005 xtensa_regfile opnd_rf;
2006 input_line_pointer++;
2007 if (num_regs == 0)
2008 goto err;
2009 assert (opnd_cnt > 0);
2010 num_regs--;
2011 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2012 if (next_reg
2013 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2014 as_warn (_("incorrect register number, ignoring"));
2015 next_reg++;
2016 }
2017 else
2018 {
2019 if (opnd_cnt >= opcode_operand_count)
2020 {
2021 as_warn (_("too many arguments"));
2022 goto err;
2023 }
2024 assert (opnd_cnt < MAX_INSN_ARGS);
2025
2026 expression_maybe_register (opcode, opnd_cnt, tok);
2027 next_reg = tok->X_add_number + 1;
2028
2029 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2030 goto err;
2031 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2032 {
2033 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2034 /* minus 1 because we are seeing one right now */
2035 }
2036 else
2037 num_regs = 0;
e0001a05 2038
43cd72b9
BW		 2039 last_tok = tok;
2040 last_opnd_cnt = opnd_cnt;
e0001a05 2041
43cd72b9
BW		 2042 do
2043 {
2044 opnd_cnt += 1;
2045 tok++;
2046 }
2047 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2048 }
2049 }
e0001a05 2050
43cd72b9
BW		 2051 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2052 goto err;
e0001a05
NC		 2053
2054 insn->ntok = tok - insn->tok;
2055 had_error = FALSE;
2056
2057 err:
43cd72b9 2058 input_line_pointer = old_input_line_pointer;
e0001a05
NC		 2059 return had_error;
2060}
2061
2062
43cd72b9 2063static int
7fa3d080 2064get_invisible_operands (TInsn *insn)
43cd72b9
BW		 2065{
2066 xtensa_isa isa = xtensa_default_isa;
2067 static xtensa_insnbuf slotbuf = NULL;
2068 xtensa_format fmt;
2069 xtensa_opcode opc = insn->opcode;
2070 int slot, opnd, fmt_found;
2071 unsigned val;
2072
2073 if (!slotbuf)
2074 slotbuf = xtensa_insnbuf_alloc (isa);
2075
2076 /* Find format/slot where this can be encoded. */
2077 fmt_found = 0;
2078 slot = 0;
2079 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2080 {
2081 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2082 {
2083 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2084 {
2085 fmt_found = 1;
2086 break;
2087 }
2088 }
2089 if (fmt_found) break;
2090 }
2091
2092 if (!fmt_found)
2093 {
2094 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2095 return -1;
2096 }
2097
2098 /* First encode all the visible operands
2099 (to deal with shared field operands). */
2100 for (opnd = 0; opnd < insn->ntok; opnd++)
2101 {
2102 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2103 && (insn->tok[opnd].X_op == O_register
2104 || insn->tok[opnd].X_op == O_constant))
2105 {
2106 val = insn->tok[opnd].X_add_number;
2107 xtensa_operand_encode (isa, opc, opnd, &val);
2108 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2109 }
2110 }
2111
2112 /* Then pull out the values for the invisible ones. */
2113 for (opnd = 0; opnd < insn->ntok; opnd++)
2114 {
2115 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2116 {
2117 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2118 xtensa_operand_decode (isa, opc, opnd, &val);
2119 insn->tok[opnd].X_add_number = val;
2120 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2121 insn->tok[opnd].X_op = O_register;
2122 else
2123 insn->tok[opnd].X_op = O_constant;
2124 }
2125 }
2126
2127 return 0;
2128}
2129
2130
e0001a05 2131static void
7fa3d080 2132xg_reverse_shift_count (char **cnt_argp)
e0001a05
NC		 2133{
2134 char *cnt_arg, *new_arg;
2135 cnt_arg = *cnt_argp;
2136
2137 /* replace the argument with "31-(argument)" */
2138 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2139 sprintf (new_arg, "31-(%s)", cnt_arg);
2140
2141 free (cnt_arg);
2142 *cnt_argp = new_arg;
2143}
2144
2145
2146/* If "arg" is a constant expression, return non-zero with the value
2147 in *valp. */
2148
2149static int
7fa3d080 2150xg_arg_is_constant (char *arg, offsetT *valp)
e0001a05
NC		 2151{
2152 expressionS exp;
2153 char *save_ptr = input_line_pointer;
2154
2155 input_line_pointer = arg;
2156 expression (&exp);
2157 input_line_pointer = save_ptr;
2158
2159 if (exp.X_op == O_constant)
2160 {
2161 *valp = exp.X_add_number;
2162 return 1;
2163 }
2164
2165 return 0;
2166}
2167
2168
2169static void
7fa3d080 2170xg_replace_opname (char **popname, char *newop)
e0001a05
NC		 2171{
2172 free (*popname);
2173 *popname = (char *) xmalloc (strlen (newop) + 1);
2174 strcpy (*popname, newop);
2175}
2176
2177
2178static int
7fa3d080
BW		 2179xg_check_num_args (int *pnum_args,
2180 int expected_num,
2181 char *opname,
2182 char **arg_strings)
e0001a05
NC		 2183{
2184 int num_args = *pnum_args;
2185
43cd72b9 2186 if (num_args < expected_num)
e0001a05
NC		 2187 {
2188 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2189 num_args, opname, expected_num);
2190 return -1;
2191 }
2192
2193 if (num_args > expected_num)
2194 {
2195 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2196 num_args, opname, expected_num);
2197 while (num_args-- > expected_num)
2198 {
2199 free (arg_strings[num_args]);
2200 arg_strings[num_args] = 0;
2201 }
2202 *pnum_args = expected_num;
2203 return -1;
2204 }
2205
2206 return 0;
2207}
2208
2209
43cd72b9
BW		 2210/* If the register is not specified as part of the opcode,
2211 then get it from the operand and move it to the opcode. */
2212
e0001a05 2213static int
7fa3d080 2214xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
e0001a05 2215{
43cd72b9
BW		 2216 xtensa_isa isa = xtensa_default_isa;
2217 xtensa_sysreg sr;
e0001a05 2218 char *opname, *new_opname;
43cd72b9
BW		 2219 const char *sr_name;
2220 int is_user, is_write;
e0001a05
NC		 2221 bfd_boolean has_underbar = FALSE;
2222
2223 opname = *popname;
2224 if (*opname == '_')
2225 {
2226 has_underbar = TRUE;
2227 opname += 1;
2228 }
43cd72b9
BW		 2229 is_user = (opname[1] == 'u');
2230 is_write = (opname[0] == 'w');
e0001a05 2231
43cd72b9 2232 /* Opname == [rw]ur or [rwx]sr... */
e0001a05 2233
43cd72b9
BW		 2234 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2235 return -1;
e0001a05 2236
43cd72b9
BW		 2237 /* Check if the argument is a symbolic register name. */
2238 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2239 /* Handle WSR to "INTSET" as a special case. */
2240 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2241 && !strcasecmp (arg_strings[1], "intset"))
2242 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2243 if (sr == XTENSA_UNDEFINED
2244 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2245 {
2246 /* Maybe it's a register number.... */
2247 offsetT val;
e0001a05
NC		 2248 if (!xg_arg_is_constant (arg_strings[1], &val))
2249 {
43cd72b9
BW		 2250 as_bad (_("invalid register '%s' for '%s' instruction"),
2251 arg_strings[1], opname);
e0001a05
NC		 2252 return -1;
2253 }
43cd72b9
BW		 2254 sr = xtensa_sysreg_lookup (isa, val, is_user);
2255 if (sr == XTENSA_UNDEFINED)
e0001a05 2256 {
43cd72b9 2257 as_bad (_("invalid register number (%ld) for '%s' instruction"),
e0001a05
NC		 2258 val, opname);
2259 return -1;
2260 }
43cd72b9 2261 }
e0001a05 2262
43cd72b9
BW		 2263 /* Remove the last argument, which is now part of the opcode. */
2264 free (arg_strings[1]);
2265 arg_strings[1] = 0;
2266 *pnum_args = 1;
2267
2268 /* Translate the opcode. */
2269 sr_name = xtensa_sysreg_name (isa, sr);
2270 /* Another special case for "WSR.INTSET".... */
2271 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2272 sr_name = "intset";
2273 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2274 sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""),
2275 *popname, sr_name);
2276 free (*popname);
2277 *popname = new_opname;
2278
2279 return 0;
2280}
2281
2282
2283static int
7fa3d080 2284xtensa_translate_old_userreg_ops (char **popname)
43cd72b9
BW		 2285{
2286 xtensa_isa isa = xtensa_default_isa;
2287 xtensa_sysreg sr;
2288 char *opname, *new_opname;
2289 const char *sr_name;
2290 bfd_boolean has_underbar = FALSE;
2291
2292 opname = *popname;
2293 if (opname[0] == '_')
2294 {
2295 has_underbar = TRUE;
2296 opname += 1;
2297 }
2298
2299 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2300 if (sr != XTENSA_UNDEFINED)
2301 {
2302 /* The new default name ("nnn") is different from the old default
2303 name ("URnnn"). The old default is handled below, and we don't
2304 want to recognize [RW]nnn, so do nothing if the name is the (new)
2305 default. */
2306 static char namebuf[10];
2307 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2308 if (strcmp (namebuf, opname + 1) == 0)
2309 return 0;
2310 }
2311 else
2312 {
2313 offsetT val;
2314 char *end;
2315
2316 /* Only continue if the reg name is "URnnn". */
2317 if (opname[1] != 'u' || opname[2] != 'r')
2318 return 0;
2319 val = strtoul (opname + 3, &end, 10);
2320 if (*end != '\0')
2321 return 0;
2322
2323 sr = xtensa_sysreg_lookup (isa, val, 1);
2324 if (sr == XTENSA_UNDEFINED)
2325 {
2326 as_bad (_("invalid register number (%ld) for '%s'"),
2327 val, opname);
2328 return -1;
2329 }
2330 }
2331
2332 /* Translate the opcode. */
2333 sr_name = xtensa_sysreg_name (isa, sr);
2334 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2335 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2336 opname[0], sr_name);
2337 free (*popname);
2338 *popname = new_opname;
2339
2340 return 0;
2341}
2342
2343
2344static int
7fa3d080
BW		 2345xtensa_translate_zero_immed (char *old_op,
2346 char *new_op,
2347 char **popname,
2348 int *pnum_args,
2349 char **arg_strings)
43cd72b9
BW		 2350{
2351 char *opname;
2352 offsetT val;
2353
2354 opname = *popname;
2355 assert (opname[0] != '_');
2356
2357 if (strcmp (opname, old_op) != 0)
2358 return 0;
e0001a05 2359
43cd72b9
BW		 2360 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2361 return -1;
2362 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2363 {
2364 xg_replace_opname (popname, new_op);
2365 free (arg_strings[1]);
2366 arg_strings[1] = arg_strings[2];
2367 arg_strings[2] = 0;
2368 *pnum_args = 2;
e0001a05
NC		 2369 }
2370
2371 return 0;
2372}
2373
2374
2375/* If the instruction is an idiom (i.e., a built-in macro), translate it.
2376 Returns non-zero if an error was found. */
2377
2378static int
7fa3d080 2379xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
e0001a05
NC		 2380{
2381 char *opname = *popname;
2382 bfd_boolean has_underbar = FALSE;
2383
43cd72b9
BW		 2384 if (cur_vinsn.inside_bundle)
2385 return 0;
2386
e0001a05
NC		 2387 if (*opname == '_')
2388 {
2389 has_underbar = TRUE;
2390 opname += 1;
2391 }
2392
2393 if (strcmp (opname, "mov") == 0)
2394 {
43cd72b9 2395 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2396 xg_replace_opname (popname, "mov.n");
2397 else
2398 {
2399 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2400 return -1;
2401 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2402 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2403 strcpy (arg_strings[2], arg_strings[1]);
2404 *pnum_args = 3;
2405 }
2406 return 0;
2407 }
2408
2409 if (strcmp (opname, "bbsi.l") == 0)
2410 {
2411 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2412 return -1;
2413 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2414 if (target_big_endian)
2415 xg_reverse_shift_count (&arg_strings[1]);
2416 return 0;
2417 }
2418
2419 if (strcmp (opname, "bbci.l") == 0)
2420 {
2421 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2422 return -1;
2423 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2424 if (target_big_endian)
2425 xg_reverse_shift_count (&arg_strings[1]);
2426 return 0;
2427 }
2428
43cd72b9
BW		 2429 if (xtensa_nop_opcode == XTENSA_UNDEFINED
2430 && strcmp (opname, "nop") == 0)
e0001a05 2431 {
43cd72b9 2432 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2433 xg_replace_opname (popname, "nop.n");
2434 else
2435 {
2436 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2437 return -1;
2438 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2439 arg_strings[0] = (char *) xmalloc (3);
2440 arg_strings[1] = (char *) xmalloc (3);
2441 arg_strings[2] = (char *) xmalloc (3);
2442 strcpy (arg_strings[0], "a1");
2443 strcpy (arg_strings[1], "a1");
2444 strcpy (arg_strings[2], "a1");
2445 *pnum_args = 3;
2446 }
2447 return 0;
2448 }
2449
43cd72b9
BW		 2450 /* Recognize [RW]UR and [RWX]SR. */
2451 if ((((opname[0] == 'r' || opname[0] == 'w')
2452 && (opname[1] == 'u' || opname[1] == 's'))
2453 || (opname[0] == 'x' && opname[1] == 's'))
2454 && opname[2] == 'r'
2455 && opname[3] == '\0')
e0001a05
NC		 2456 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2457
43cd72b9
BW		 2458 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2459 [RW]<name> if <name> is the non-default name of a user register. */
2460 if ((opname[0] == 'r' || opname[0] == 'w')
2461 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2462 return xtensa_translate_old_userreg_ops (popname);
e0001a05 2463
43cd72b9
BW		 2464 /* Relax branches that don't allow comparisons against an immediate value
2465 of zero to the corresponding branches with implicit zero immediates. */
2466 if (!has_underbar && use_transform ())
2467 {
2468 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2469 pnum_args, arg_strings))
2470 return -1;
e0001a05 2471
43cd72b9
BW		 2472 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2473 pnum_args, arg_strings))
2474 return -1;
e0001a05 2475
43cd72b9
BW		 2476 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2477 pnum_args, arg_strings))
2478 return -1;
e0001a05 2479
43cd72b9
BW		 2480 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2481 pnum_args, arg_strings))
2482 return -1;
2483 }
e0001a05 2484
43cd72b9
BW		 2485 return 0;
2486}
e0001a05 2487
43cd72b9
BW		 2488\f
2489/* Functions for dealing with the Xtensa ISA. */
e0001a05 2490
43cd72b9
BW		 2491/* Currently the assembler only allows us to use a single target per
2492 fragment. Because of this, only one operand for a given
2493 instruction may be symbolic. If there is a PC-relative operand,
2494 the last one is chosen. Otherwise, the result is the number of the
2495 last immediate operand, and if there are none of those, we fail and
2496 return -1. */
e0001a05 2497
7fa3d080
BW		 2498static int
2499get_relaxable_immed (xtensa_opcode opcode)
43cd72b9
BW		 2500{
2501 int last_immed = -1;
2502 int noperands, opi;
e0001a05 2503
43cd72b9
BW		 2504 if (opcode == XTENSA_UNDEFINED)
2505 return -1;
e0001a05 2506
43cd72b9
BW		 2507 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2508 for (opi = noperands - 1; opi >= 0; opi--)
2509 {
2510 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2511 continue;
2512 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2513 return opi;
2514 if (last_immed == -1
2515 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2516 last_immed = opi;
e0001a05 2517 }
43cd72b9 2518 return last_immed;
e0001a05
NC		 2519}
2520
e0001a05 2521
43cd72b9 2522static xtensa_opcode
7fa3d080 2523get_opcode_from_buf (const char *buf, int slot)
e0001a05 2524{
43cd72b9
BW		 2525 static xtensa_insnbuf insnbuf = NULL;
2526 static xtensa_insnbuf slotbuf = NULL;
2527 xtensa_isa isa = xtensa_default_isa;
2528 xtensa_format fmt;
2529
2530 if (!insnbuf)
e0001a05 2531 {
43cd72b9
BW		 2532 insnbuf = xtensa_insnbuf_alloc (isa);
2533 slotbuf = xtensa_insnbuf_alloc (isa);
e0001a05 2534 }
e0001a05 2535
43cd72b9
BW		 2536 xtensa_insnbuf_from_chars (isa, insnbuf, buf, 0);
2537 fmt = xtensa_format_decode (isa, insnbuf);
2538 if (fmt == XTENSA_UNDEFINED)
2539 return XTENSA_UNDEFINED;
e0001a05 2540
43cd72b9
BW		 2541 if (slot >= xtensa_format_num_slots (isa, fmt))
2542 return XTENSA_UNDEFINED;
e0001a05 2543
43cd72b9
BW		 2544 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2545 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
e0001a05
NC		 2546}
2547
2548
43cd72b9 2549#ifdef TENSILICA_DEBUG
e0001a05 2550
43cd72b9 2551/* For debugging, print out the mapping of opcode numbers to opcodes. */
e0001a05 2552
7fa3d080
BW		 2553static void
2554xtensa_print_insn_table (void)
43cd72b9
BW		 2555{
2556 int num_opcodes, num_operands;
2557 xtensa_opcode opcode;
2558 xtensa_isa isa = xtensa_default_isa;
e0001a05 2559
43cd72b9
BW		 2560 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2561 for (opcode = 0; opcode < num_opcodes; opcode++)
e0001a05 2562 {
43cd72b9
BW		 2563 int opn;
2564 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2565 num_operands = xtensa_opcode_num_operands (isa, opcode);
2566 for (opn = 0; opn < num_operands; opn++)
2567 {
2568 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2569 continue;
2570 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2571 {
2572 xtensa_regfile opnd_rf =
2573 xtensa_operand_regfile (isa, opcode, opn);
2574 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2575 }
2576 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2577 fputs ("[lLr] ", stderr);
2578 else
2579 fputs ("i ", stderr);
2580 }
2581 fprintf (stderr, "\n");
e0001a05 2582 }
e0001a05
NC		 2583}
2584
2585
43cd72b9 2586static void
7fa3d080 2587print_vliw_insn (xtensa_insnbuf vbuf)
e0001a05 2588{
e0001a05 2589 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 2590 xtensa_format f = xtensa_format_decode (isa, vbuf);
2591 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2592 int op;
e0001a05 2593
43cd72b9 2594 fprintf (stderr, "format = %d\n", f);
e0001a05 2595
43cd72b9
BW		 2596 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2597 {
2598 xtensa_opcode opcode;
2599 const char *opname;
2600 int operands;
2601
2602 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2603 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2604 opname = xtensa_opcode_name (isa, opcode);
2605
2606 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2607 fprintf (stderr, " operands = ");
2608 for (operands = 0;
2609 operands < xtensa_opcode_num_operands (isa, opcode);
2610 operands++)
2611 {
2612 unsigned int val;
2613 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2614 continue;
2615 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2616 xtensa_operand_decode (isa, opcode, operands, &val);
2617 fprintf (stderr, "%d ", val);
2618 }
2619 fprintf (stderr, "\n");
2620 }
2621 xtensa_insnbuf_free (isa, sbuf);
e0001a05
NC		 2622}
2623
43cd72b9
BW		 2624#endif /* TENSILICA_DEBUG */
2625
e0001a05
NC		 2626
2627static bfd_boolean
7fa3d080 2628is_direct_call_opcode (xtensa_opcode opcode)
e0001a05 2629{
43cd72b9
BW		 2630 xtensa_isa isa = xtensa_default_isa;
2631 int n, num_operands;
e0001a05 2632
43cd72b9 2633 if (xtensa_opcode_is_call (isa, opcode) == 0)
e0001a05
NC		 2634 return FALSE;
2635
43cd72b9
BW		 2636 num_operands = xtensa_opcode_num_operands (isa, opcode);
2637 for (n = 0; n < num_operands; n++)
2638 {
2639 if (xtensa_operand_is_register (isa, opcode, n) == 0
2640 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2641 return TRUE;
2642 }
2643 return FALSE;
e0001a05
NC		 2644}
2645
2646
43cd72b9
BW		 2647/* Convert from BFD relocation type code to slot and operand number.
2648 Returns non-zero on failure. */
e0001a05 2649
43cd72b9 2650static int
7fa3d080 2651decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
e0001a05 2652{
43cd72b9
BW		 2653 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2654 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
e0001a05 2655 {
43cd72b9
BW		 2656 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2657 *is_alt = FALSE;
e0001a05 2658 }
43cd72b9
BW		 2659 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2660 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
e0001a05 2661 {
43cd72b9
BW		 2662 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2663 *is_alt = TRUE;
e0001a05 2664 }
43cd72b9
BW		 2665 else
2666 return -1;
2667
2668 return 0;
e0001a05
NC		 2669}
2670
2671
43cd72b9
BW		 2672/* Convert from slot number to BFD relocation type code for the
2673 standard PC-relative relocations. Return BFD_RELOC_NONE on
2674 failure. */
e0001a05 2675
43cd72b9 2676static bfd_reloc_code_real_type
7fa3d080 2677encode_reloc (int slot)
e0001a05 2678{
43cd72b9
BW		 2679 if (slot < 0 || slot > 14)
2680 return BFD_RELOC_NONE;
2681
2682 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
e0001a05
NC		 2683}
2684
2685
43cd72b9
BW		 2686/* Convert from slot numbers to BFD relocation type code for the
2687 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
e0001a05 2688
43cd72b9 2689static bfd_reloc_code_real_type
7fa3d080 2690encode_alt_reloc (int slot)
e0001a05 2691{
43cd72b9
BW		 2692 if (slot < 0 || slot > 14)
2693 return BFD_RELOC_NONE;
2694
2695 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
e0001a05
NC		 2696}
2697
2698
2699static void
7fa3d080
BW		 2700xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2701 xtensa_format fmt,
2702 int slot,
2703 xtensa_opcode opcode,
2704 int operand,
2705 uint32 value,
2706 const char *file,
2707 unsigned int line)
e0001a05 2708{
e0001a05
NC		 2709 uint32 valbuf = value;
2710
43cd72b9 2711 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
e0001a05 2712 {
43cd72b9
BW		 2713 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2714 == 1)
2715 as_bad_where ((char *) file, line,
2716 _("operand %u is out of range for '%s'"), value,
2717 xtensa_opcode_name (xtensa_default_isa, opcode));
2718 else
2719 as_bad_where ((char *) file, line,
2720 _("operand %u is invalid for '%s'"), value,
2721 xtensa_opcode_name (xtensa_default_isa, opcode));
2722 return;
e0001a05
NC		 2723 }
2724
43cd72b9
BW		 2725 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2726 slotbuf, valbuf);
e0001a05
NC		 2727}
2728
2729
2730static uint32
7fa3d080
BW		 2731xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2732 xtensa_format fmt,
2733 int slot,
2734 xtensa_opcode opcode,
2735 int opnum)
e0001a05 2736{
43cd72b9
BW		 2737 uint32 val = 0;
2738 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2739 fmt, slot, slotbuf, &val);
2740 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2741 return val;
e0001a05
NC		 2742}
2743
e0001a05 2744\f
7fa3d080 2745/* Checks for rules from xtensa-relax tables. */
e0001a05 2746
7fa3d080
BW		 2747/* The routine xg_instruction_matches_option_term must return TRUE
2748 when a given option term is true. The meaning of all of the option
2749 terms is given interpretation by this function. This is needed when
2750 an option depends on the state of a directive, but there are no such
2751 options in use right now. */
e0001a05 2752
7fa3d080
BW		 2753static bfd_boolean
2754xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
2755 const ReqOrOption *option)
e0001a05 2756{
7fa3d080
BW		 2757 if (strcmp (option->option_name, "realnop") == 0
2758 || strncmp (option->option_name, "IsaUse", 6) == 0)
2759 {
2760 /* These conditions were evaluated statically when building the
2761 relaxation table. There's no need to reevaluate them now. */
2762 return TRUE;
2763 }
2764 else
2765 {
2766 as_fatal (_("internal error: unknown option name '%s'"),
2767 option->option_name);
2768 }
e0001a05
NC		 2769}
2770
2771
7fa3d080
BW		 2772static bfd_boolean
2773xg_instruction_matches_or_options (TInsn *insn,
2774 const ReqOrOptionList *or_option)
e0001a05 2775{
7fa3d080
BW		 2776 const ReqOrOption *option;
2777 /* Must match each of the AND terms. */
2778 for (option = or_option; option != NULL; option = option->next)
e0001a05 2779 {
7fa3d080
BW		 2780 if (xg_instruction_matches_option_term (insn, option))
2781 return TRUE;
e0001a05 2782 }
7fa3d080 2783 return FALSE;
e0001a05
NC		 2784}
2785
2786
7fa3d080
BW		 2787static bfd_boolean
2788xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
e0001a05 2789{
7fa3d080
BW		 2790 const ReqOption *req_options;
2791 /* Must match each of the AND terms. */
2792 for (req_options = options;
2793 req_options != NULL;
2794 req_options = req_options->next)
e0001a05 2795 {
7fa3d080
BW		 2796 /* Must match one of the OR clauses. */
2797 if (!xg_instruction_matches_or_options (insn,
2798 req_options->or_option_terms))
2799 return FALSE;
e0001a05 2800 }
7fa3d080 2801 return TRUE;
e0001a05
NC		 2802}
2803
2804
7fa3d080 2805/* Return the transition rule that matches or NULL if none matches. */
e0001a05 2806
7fa3d080
BW		 2807static bfd_boolean
2808xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
e0001a05 2809{
7fa3d080 2810 PreconditionList *condition_l;
e0001a05 2811
7fa3d080
BW		 2812 if (rule->opcode != insn->opcode)
2813 return FALSE;
e0001a05 2814
7fa3d080
BW		 2815 for (condition_l = rule->conditions;
2816 condition_l != NULL;
2817 condition_l = condition_l->next)
e0001a05 2818 {
7fa3d080
BW		 2819 expressionS *exp1;
2820 expressionS *exp2;
2821 Precondition *cond = condition_l->precond;
e0001a05 2822
7fa3d080 2823 switch (cond->typ)
e0001a05 2824 {
7fa3d080
BW		 2825 case OP_CONSTANT:
2826 /* The expression must be the constant. */
2827 assert (cond->op_num < insn->ntok);
2828 exp1 = &insn->tok[cond->op_num];
2829 if (expr_is_const (exp1))
2830 {
2831 switch (cond->cmp)
2832 {
2833 case OP_EQUAL:
2834 if (get_expr_const (exp1) != cond->op_data)
2835 return FALSE;
2836 break;
2837 case OP_NOTEQUAL:
2838 if (get_expr_const (exp1) == cond->op_data)
2839 return FALSE;
2840 break;
2841 default:
2842 return FALSE;
2843 }
2844 }
2845 else if (expr_is_register (exp1))
2846 {
2847 switch (cond->cmp)
2848 {
2849 case OP_EQUAL:
2850 if (get_expr_register (exp1) != cond->op_data)
2851 return FALSE;
2852 break;
2853 case OP_NOTEQUAL:
2854 if (get_expr_register (exp1) == cond->op_data)
2855 return FALSE;
2856 break;
2857 default:
2858 return FALSE;
2859 }
2860 }
2861 else
2862 return FALSE;
2863 break;
2864
2865 case OP_OPERAND:
2866 assert (cond->op_num < insn->ntok);
2867 assert (cond->op_data < insn->ntok);
2868 exp1 = &insn->tok[cond->op_num];
2869 exp2 = &insn->tok[cond->op_data];
2870
2871 switch (cond->cmp)
2872 {
2873 case OP_EQUAL:
2874 if (!expr_is_equal (exp1, exp2))
2875 return FALSE;
2876 break;
2877 case OP_NOTEQUAL:
2878 if (expr_is_equal (exp1, exp2))
2879 return FALSE;
2880 break;
2881 }
2882 break;
2883
2884 case OP_LITERAL:
2885 case OP_LABEL:
2886 default:
2887 return FALSE;
2888 }
2889 }
2890 if (!xg_instruction_matches_options (insn, rule->options))
2891 return FALSE;
2892
2893 return TRUE;
2894}
2895
2896
2897static int
2898transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2899{
2900 bfd_boolean a_greater = FALSE;
2901 bfd_boolean b_greater = FALSE;
2902
2903 ReqOptionList *l_a = a->options;
2904 ReqOptionList *l_b = b->options;
2905
2906 /* We only care if they both are the same except for
2907 a const16 vs. an l32r. */
2908
2909 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2910 {
2911 ReqOrOptionList *l_or_a = l_a->or_option_terms;
2912 ReqOrOptionList *l_or_b = l_b->or_option_terms;
2913 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2914 {
2915 if (l_or_a->is_true != l_or_b->is_true)
2916 return 0;
2917 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
2918 {
2919 /* This is the case we care about. */
2920 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
2921 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
2922 {
2923 if (prefer_const16)
2924 a_greater = TRUE;
2925 else
2926 b_greater = TRUE;
2927 }
2928 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
2929 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
2930 {
2931 if (prefer_const16)
2932 b_greater = TRUE;
2933 else
2934 a_greater = TRUE;
2935 }
2936 else
2937 return 0;
2938 }
2939 l_or_a = l_or_a->next;
2940 l_or_b = l_or_b->next;
2941 }
2942 if (l_or_a || l_or_b)
2943 return 0;
2944
2945 l_a = l_a->next;
2946 l_b = l_b->next;
2947 }
2948 if (l_a || l_b)
2949 return 0;
2950
2951 /* Incomparable if the substitution was used differently in two cases. */
2952 if (a_greater && b_greater)
2953 return 0;
2954
2955 if (b_greater)
2956 return 1;
2957 if (a_greater)
2958 return -1;
2959
2960 return 0;
2961}
2962
2963
2964static TransitionRule *
2965xg_instruction_match (TInsn *insn)
2966{
2967 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
2968 TransitionList *l;
2969 assert (insn->opcode < table->num_opcodes);
2970
2971 /* Walk through all of the possible transitions. */
2972 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2973 {
2974 TransitionRule *rule = l->rule;
2975 if (xg_instruction_matches_rule (insn, rule))
2976 return rule;
2977 }
2978 return NULL;
2979}
2980
2981\f
2982/* Various Other Internal Functions. */
2983
2984static bfd_boolean
2985is_unique_insn_expansion (TransitionRule *r)
2986{
2987 if (!r->to_instr || r->to_instr->next != NULL)
2988 return FALSE;
2989 if (r->to_instr->typ != INSTR_INSTR)
2990 return FALSE;
2991 return TRUE;
2992}
2993
2994
2995static int
2996xg_get_build_instr_size (BuildInstr *insn)
2997{
2998 assert (insn->typ == INSTR_INSTR);
2999 return xg_get_single_size (insn->opcode);
3000}
3001
3002
3003static bfd_boolean
3004xg_is_narrow_insn (TInsn *insn)
3005{
3006 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3007 TransitionList *l;
3008 int num_match = 0;
3009 assert (insn->insn_type == ITYPE_INSN);
3010 assert (insn->opcode < table->num_opcodes);
3011
3012 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3013 {
3014 TransitionRule *rule = l->rule;
3015
3016 if (xg_instruction_matches_rule (insn, rule)
3017 && is_unique_insn_expansion (rule))
3018 {
3019 /* It only generates one instruction... */
3020 assert (insn->insn_type == ITYPE_INSN);
3021 /* ...and it is a larger instruction. */
3022 if (xg_get_single_size (insn->opcode)
3023 < xg_get_build_instr_size (rule->to_instr))
3024 {
3025 num_match++;
3026 if (num_match > 1)
3027 return FALSE;
3028 }
3029 }
3030 }
3031 return (num_match == 1);
3032}
3033
3034
3035static bfd_boolean
3036xg_is_single_relaxable_insn (TInsn *insn)
3037{
3038 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3039 TransitionList *l;
3040 int num_match = 0;
3041 assert (insn->insn_type == ITYPE_INSN);
3042 assert (insn->opcode < table->num_opcodes);
3043
3044 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3045 {
3046 TransitionRule *rule = l->rule;
3047
3048 if (xg_instruction_matches_rule (insn, rule)
3049 && is_unique_insn_expansion (rule))
3050 {
3051 /* It only generates one instruction... */
3052 assert (insn->insn_type == ITYPE_INSN);
3053 /* ... and it is a larger instruction. */
3054 if (xg_get_single_size (insn->opcode)
3055 <= xg_get_build_instr_size (rule->to_instr))
3056 {
3057 num_match++;
3058 if (num_match > 1)
3059 return FALSE;
3060 }
3061 }
3062 }
3063 return (num_match == 1);
3064}
3065
3066
3067/* Return the maximum number of bytes this opcode can expand to. */
3068
3069static int
3070xg_get_max_insn_widen_size (xtensa_opcode opcode)
3071{
3072 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3073 TransitionList *l;
3074 int max_size = xg_get_single_size (opcode);
3075
3076 assert (opcode < table->num_opcodes);
3077
3078 for (l = table->table[opcode]; l != NULL; l = l->next)
3079 {
3080 TransitionRule *rule = l->rule;
3081 BuildInstr *build_list;
3082 int this_size = 0;
3083
3084 if (!rule)
3085 continue;
3086 build_list = rule->to_instr;
3087 if (is_unique_insn_expansion (rule))
3088 {
3089 assert (build_list->typ == INSTR_INSTR);
3090 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3091 }
3092 else
3093 for (; build_list != NULL; build_list = build_list->next)
3094 {
3095 switch (build_list->typ)
3096 {
3097 case INSTR_INSTR:
3098 this_size += xg_get_single_size (build_list->opcode);
3099 break;
3100 case INSTR_LITERAL_DEF:
3101 case INSTR_LABEL_DEF:
e0001a05
NC		 3102 default:
3103 break;
3104 }
3105 }
3106 if (this_size > max_size)
3107 max_size = this_size;
3108 }
3109 return max_size;
3110}
3111
3112
3113/* Return the maximum number of literal bytes this opcode can generate. */
3114
7fa3d080
BW		 3115static int
3116xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
e0001a05 3117{
43cd72b9 3118 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3119 TransitionList *l;
3120 int max_size = 0;
3121
3122 assert (opcode < table->num_opcodes);
3123
3124 for (l = table->table[opcode]; l != NULL; l = l->next)
3125 {
3126 TransitionRule *rule = l->rule;
3127 BuildInstr *build_list;
3128 int this_size = 0;
3129
3130 if (!rule)
3131 continue;
3132 build_list = rule->to_instr;
3133 if (is_unique_insn_expansion (rule))
3134 {
3135 assert (build_list->typ == INSTR_INSTR);
3136 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3137 }
3138 else
3139 for (; build_list != NULL; build_list = build_list->next)
3140 {
3141 switch (build_list->typ)
3142 {
3143 case INSTR_LITERAL_DEF:
43cd72b9 3144 /* Hard-coded 4-byte literal. */
e0001a05
NC		 3145 this_size += 4;
3146 break;
3147 case INSTR_INSTR:
3148 case INSTR_LABEL_DEF:
3149 default:
3150 break;
3151 }
3152 }
3153 if (this_size > max_size)
3154 max_size = this_size;
3155 }
3156 return max_size;
3157}
3158
3159
7fa3d080
BW		 3160static bfd_boolean
3161xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3162{
3163 int steps_taken = 0;
3164 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3165 TransitionList *l;
3166
3167 assert (insn->insn_type == ITYPE_INSN);
3168 assert (insn->opcode < table->num_opcodes);
3169
3170 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3171 {
3172 TransitionRule *rule = l->rule;
3173
3174 if (xg_instruction_matches_rule (insn, rule))
3175 {
3176 if (steps_taken == lateral_steps)
3177 return TRUE;
3178 steps_taken++;
3179 }
3180 }
3181 return FALSE;
3182}
3183
3184
3185static symbolS *
3186get_special_literal_symbol (void)
3187{
3188 static symbolS *sym = NULL;
3189
3190 if (sym == NULL)
3191 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3192 return sym;
3193}
3194
3195
3196static symbolS *
3197get_special_label_symbol (void)
3198{
3199 static symbolS *sym = NULL;
3200
3201 if (sym == NULL)
3202 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3203 return sym;
3204}
3205
3206
3207static bfd_boolean
3208xg_valid_literal_expression (const expressionS *exp)
3209{
3210 switch (exp->X_op)
3211 {
3212 case O_constant:
3213 case O_symbol:
3214 case O_big:
3215 case O_uminus:
3216 case O_subtract:
3217 case O_pltrel:
3218 return TRUE;
3219 default:
3220 return FALSE;
3221 }
3222}
3223
3224
3225/* This will check to see if the value can be converted into the
3226 operand type. It will return TRUE if it does not fit. */
3227
3228static bfd_boolean
3229xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3230{
3231 uint32 valbuf = value;
3232 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3233 return TRUE;
3234 return FALSE;
3235}
3236
3237
3238/* Assumes: All immeds are constants. Check that all constants fit
3239 into their immeds; return FALSE if not. */
3240
3241static bfd_boolean
3242xg_immeds_fit (const TInsn *insn)
3243{
3244 xtensa_isa isa = xtensa_default_isa;
3245 int i;
3246
3247 int n = insn->ntok;
3248 assert (insn->insn_type == ITYPE_INSN);
3249 for (i = 0; i < n; ++i)
3250 {
3251 const expressionS *expr = &insn->tok[i];
3252 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3253 continue;
3254
3255 switch (expr->X_op)
3256 {
3257 case O_register:
3258 case O_constant:
3259 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3260 return FALSE;
3261 break;
3262
3263 default:
3264 /* The symbol should have a fixup associated with it. */
3265 assert (FALSE);
3266 break;
3267 }
3268 }
3269 return TRUE;
3270}
3271
3272
3273/* This should only be called after we have an initial
3274 estimate of the addresses. */
3275
3276static bfd_boolean
3277xg_symbolic_immeds_fit (const TInsn *insn,
3278 segT pc_seg,
3279 fragS *pc_frag,
3280 offsetT pc_offset,
3281 long stretch)
e0001a05 3282{
7fa3d080
BW		 3283 xtensa_isa isa = xtensa_default_isa;
3284 symbolS *symbolP;
3285 fragS *sym_frag;
3286 offsetT target, pc;
3287 uint32 new_offset;
3288 int i;
3289 int n = insn->ntok;
e0001a05
NC		 3290
3291 assert (insn->insn_type == ITYPE_INSN);
e0001a05 3292
7fa3d080 3293 for (i = 0; i < n; ++i)
e0001a05 3294 {
7fa3d080
BW		 3295 const expressionS *expr = &insn->tok[i];
3296 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3297 continue;
e0001a05 3298
7fa3d080 3299 switch (expr->X_op)
e0001a05 3300 {
7fa3d080
BW		 3301 case O_register:
3302 case O_constant:
3303 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3304 return FALSE;
3305 break;
e0001a05 3306
7fa3d080
BW		 3307 case O_lo16:
3308 case O_hi16:
3309 /* Check for the worst case. */
3310 if (xg_check_operand (0xffff, insn->opcode, i))
3311 return FALSE;
3312 break;
e0001a05 3313
7fa3d080
BW		 3314 case O_symbol:
3315 /* We only allow symbols for pc-relative stuff.
3316 If pc_frag == 0, then we don't have frag locations yet. */
3317 if (pc_frag == 0)
3318 return FALSE;
e0001a05 3319
7fa3d080
BW		 3320 /* If it is PC-relative and the symbol is not in the same
3321 segment as the PC.... */
3322 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0
3323 || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3324 return FALSE;
e0001a05 3325
7fa3d080
BW		 3326 /* If it is a weak symbol, then assume it won't reach. This will
3327 only affect calls when longcalls are enabled, because if
3328 longcalls are disabled, then the call is marked as a specific
3329 opcode. */
3330 if (S_IS_WEAK (expr->X_add_symbol))
3331 return FALSE;
e0001a05 3332
7fa3d080
BW		 3333 symbolP = expr->X_add_symbol;
3334 sym_frag = symbol_get_frag (symbolP);
3335 target = S_GET_VALUE (symbolP) + expr->X_add_number;
3336 pc = pc_frag->fr_address + pc_offset;
e0001a05 3337
7fa3d080
BW		 3338 /* If frag has yet to be reached on this pass, assume it
3339 will move by STRETCH just as we did. If this is not so,
3340 it will be because some frag between grows, and that will
3341 force another pass. Beware zero-length frags. There
3342 should be a faster way to do this. */
3343
3344 if (stretch != 0
3345 && sym_frag->relax_marker != pc_frag->relax_marker
3346 && S_GET_SEGMENT (symbolP) == pc_seg)
3347 {
3348 target += stretch;
3349 }
3350
3351 new_offset = target;
3352 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3353 if (xg_check_operand (new_offset, insn->opcode, i))
3354 return FALSE;
3355 break;
3356
3357 default:
3358 /* The symbol should have a fixup associated with it. */
3359 return FALSE;
3360 }
3361 }
3362
3363 return TRUE;
e0001a05
NC		 3364}
3365
3366
43cd72b9 3367/* Return TRUE on success. */
e0001a05 3368
7fa3d080
BW		 3369static bfd_boolean
3370xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
e0001a05
NC		 3371{
3372 BuildOp *op;
3373 symbolS *sym;
3374
3375 memset (targ, 0, sizeof (TInsn));
43cd72b9 3376 targ->loc = insn->loc;
e0001a05
NC		 3377 switch (bi->typ)
3378 {
3379 case INSTR_INSTR:
3380 op = bi->ops;
3381 targ->opcode = bi->opcode;
3382 targ->insn_type = ITYPE_INSN;
3383 targ->is_specific_opcode = FALSE;
3384
3385 for (; op != NULL; op = op->next)
3386 {
3387 int op_num = op->op_num;
3388 int op_data = op->op_data;
3389
3390 assert (op->op_num < MAX_INSN_ARGS);
3391
3392 if (targ->ntok <= op_num)
3393 targ->ntok = op_num + 1;
3394
3395 switch (op->typ)
3396 {
3397 case OP_CONSTANT:
3398 set_expr_const (&targ->tok[op_num], op_data);
3399 break;
3400 case OP_OPERAND:
3401 assert (op_data < insn->ntok);
3402 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3403 break;
3404 case OP_LITERAL:
3405 sym = get_special_literal_symbol ();
3406 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3407 break;
3408 case OP_LABEL:
3409 sym = get_special_label_symbol ();
3410 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3411 break;
43cd72b9
BW		 3412 case OP_OPERAND_HI16U:
3413 case OP_OPERAND_LOW16U:
3414 assert (op_data < insn->ntok);
3415 if (expr_is_const (&insn->tok[op_data]))
3416 {
3417 long val;
3418 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3419 val = xg_apply_userdef_op_fn (op->typ,
3420 targ->tok[op_num].
3421 X_add_number);
3422 targ->tok[op_num].X_add_number = val;
3423 }
3424 else
3425 {
3426 /* For const16 we can create relocations for these. */
3427 if (targ->opcode == XTENSA_UNDEFINED
3428 || (targ->opcode != xtensa_const16_opcode))
3429 return FALSE;
3430 assert (op_data < insn->ntok);
3431 /* Need to build a O_lo16 or O_hi16. */
3432 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3433 if (targ->tok[op_num].X_op == O_symbol)
3434 {
3435 if (op->typ == OP_OPERAND_HI16U)
3436 targ->tok[op_num].X_op = O_hi16;
3437 else if (op->typ == OP_OPERAND_LOW16U)
3438 targ->tok[op_num].X_op = O_lo16;
3439 else
3440 return FALSE;
3441 }
3442 }
3443 break;
e0001a05
NC		 3444 default:
3445 /* currently handles:
3446 OP_OPERAND_LOW8
3447 OP_OPERAND_HI24S
3448 OP_OPERAND_F32MINUS */
3449 if (xg_has_userdef_op_fn (op->typ))
3450 {
3451 assert (op_data < insn->ntok);
3452 if (expr_is_const (&insn->tok[op_data]))
3453 {
3454 long val;
3455 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3456 val = xg_apply_userdef_op_fn (op->typ,
3457 targ->tok[op_num].
3458 X_add_number);
3459 targ->tok[op_num].X_add_number = val;
3460 }
3461 else
3462 return FALSE; /* We cannot use a relocation for this. */
3463 break;
3464 }
3465 assert (0);
3466 break;
3467 }
3468 }
3469 break;
3470
3471 case INSTR_LITERAL_DEF:
3472 op = bi->ops;
3473 targ->opcode = XTENSA_UNDEFINED;
3474 targ->insn_type = ITYPE_LITERAL;
3475 targ->is_specific_opcode = FALSE;
3476 for (; op != NULL; op = op->next)
3477 {
3478 int op_num = op->op_num;
3479 int op_data = op->op_data;
3480 assert (op->op_num < MAX_INSN_ARGS);
3481
3482 if (targ->ntok <= op_num)
3483 targ->ntok = op_num + 1;
3484
3485 switch (op->typ)
3486 {
3487 case OP_OPERAND:
3488 assert (op_data < insn->ntok);
43cd72b9
BW		 3489 /* We can only pass resolvable literals through. */
3490 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3491 return FALSE;
e0001a05
NC		 3492 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3493 break;
3494 case OP_LITERAL:
3495 case OP_CONSTANT:
3496 case OP_LABEL:
3497 default:
3498 assert (0);
3499 break;
3500 }
3501 }
3502 break;
3503
3504 case INSTR_LABEL_DEF:
3505 op = bi->ops;
3506 targ->opcode = XTENSA_UNDEFINED;
3507 targ->insn_type = ITYPE_LABEL;
3508 targ->is_specific_opcode = FALSE;
43cd72b9 3509 /* Literal with no ops is a label? */
e0001a05
NC		 3510 assert (op == NULL);
3511 break;
3512
3513 default:
3514 assert (0);
3515 }
3516
3517 return TRUE;
3518}
3519
3520
43cd72b9 3521/* Return TRUE on success. */
e0001a05 3522
7fa3d080
BW		 3523static bfd_boolean
3524xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
e0001a05
NC		 3525{
3526 for (; bi != NULL; bi = bi->next)
3527 {
3528 TInsn *next_insn = istack_push_space (istack);
3529
3530 if (!xg_build_to_insn (next_insn, insn, bi))
3531 return FALSE;
3532 }
3533 return TRUE;
3534}
3535
3536
43cd72b9 3537/* Return TRUE on valid expansion. */
e0001a05 3538
7fa3d080
BW		 3539static bfd_boolean
3540xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
e0001a05
NC		 3541{
3542 int stack_size = istack->ninsn;
3543 int steps_taken = 0;
43cd72b9 3544 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3545 TransitionList *l;
3546
3547 assert (insn->insn_type == ITYPE_INSN);
3548 assert (insn->opcode < table->num_opcodes);
3549
3550 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3551 {
3552 TransitionRule *rule = l->rule;
3553
3554 if (xg_instruction_matches_rule (insn, rule))
3555 {
3556 if (lateral_steps == steps_taken)
3557 {
3558 int i;
3559
3560 /* This is it. Expand the rule to the stack. */
3561 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3562 return FALSE;
3563
3564 /* Check to see if it fits. */
3565 for (i = stack_size; i < istack->ninsn; i++)
3566 {
3567 TInsn *insn = &istack->insn[i];
3568
3569 if (insn->insn_type == ITYPE_INSN
3570 && !tinsn_has_symbolic_operands (insn)
3571 && !xg_immeds_fit (insn))
3572 {
3573 istack->ninsn = stack_size;
3574 return FALSE;
3575 }
3576 }
3577 return TRUE;
3578 }
3579 steps_taken++;
3580 }
3581 }
3582 return FALSE;
3583}
3584
3585
7fa3d080
BW		 3586static bfd_boolean
3587xg_expand_narrow (TInsn *targ, TInsn *insn)
e0001a05 3588{
43cd72b9 3589 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3590 TransitionList *l;
3591
3592 assert (insn->insn_type == ITYPE_INSN);
3593 assert (insn->opcode < table->num_opcodes);
3594
3595 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3596 {
3597 TransitionRule *rule = l->rule;
3598 if (xg_instruction_matches_rule (insn, rule)
3599 && is_unique_insn_expansion (rule))
3600 {
3601 /* Is it a larger instruction? */
43cd72b9 3602 if (xg_get_single_size (insn->opcode)
e0001a05
NC		 3603 <= xg_get_build_instr_size (rule->to_instr))
3604 {
3605 xg_build_to_insn (targ, insn, rule->to_instr);
3606 return FALSE;
3607 }
3608 }
3609 }
3610 return TRUE;
3611}
3612
43cd72b9 3613\f
43cd72b9
BW		 3614/* Relax the assembly instruction at least "min_steps".
3615 Return the number of steps taken. */
e0001a05 3616
7fa3d080
BW		 3617static int
3618xg_assembly_relax (IStack *istack,
3619 TInsn *insn,
3620 segT pc_seg,
3621 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3622 offsetT pc_offset, /* offset in fragment */
3623 int min_steps, /* minimum conversion steps */
3624 long stretch) /* number of bytes stretched so far */
e0001a05
NC		 3625{
3626 int steps_taken = 0;
3627
3628 /* assert (has no symbolic operands)
3629 Some of its immeds don't fit.
3630 Try to build a relaxed version.
3631 This may go through a couple of stages
3632 of single instruction transformations before
3633 we get there. */
3634
3635 TInsn single_target;
3636 TInsn current_insn;
3637 int lateral_steps = 0;
3638 int istack_size = istack->ninsn;
3639
3640 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3641 && steps_taken >= min_steps)
3642 {
3643 istack_push (istack, insn);
3644 return steps_taken;
3645 }
43cd72b9 3646 current_insn = *insn;
e0001a05
NC		 3647
3648 /* Walk through all of the single instruction expansions. */
3649 while (xg_is_single_relaxable_insn (&current_insn))
3650 {
3651 int error_val = xg_expand_narrow (&single_target, &current_insn);
3652
3653 assert (!error_val);
3654
3655 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3656 stretch))
3657 {
3658 steps_taken++;
3659 if (steps_taken >= min_steps)
3660 {
3661 istack_push (istack, &single_target);
3662 return steps_taken;
3663 }
3664 }
43cd72b9 3665 current_insn = single_target;
e0001a05
NC		 3666 }
3667
3668 /* Now check for a multi-instruction expansion. */
3669 while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3670 {
3671 if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3672 stretch))
3673 {
3674 if (steps_taken >= min_steps)
3675 {
3676 istack_push (istack, &current_insn);
3677 return steps_taken;
3678 }
3679 }
3680 steps_taken++;
3681 if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3682 {
3683 if (steps_taken >= min_steps)
3684 return steps_taken;
3685 }
3686 lateral_steps++;
3687 istack->ninsn = istack_size;
3688 }
3689
3690 /* It's not going to work -- use the original. */
3691 istack_push (istack, insn);
3692 return steps_taken;
3693}
3694
3695
3696static void
7fa3d080 3697xg_force_frag_space (int size)
e0001a05
NC		 3698{
3699 /* This may have the side effect of creating a new fragment for the
3700 space to go into. I just do not like the name of the "frag"
3701 functions. */
3702 frag_grow (size);
3703}
3704
3705
7fa3d080
BW		 3706static void
3707xg_finish_frag (char *last_insn,
3708 enum xtensa_relax_statesE frag_state,
3709 enum xtensa_relax_statesE slot0_state,
3710 int max_growth,
3711 bfd_boolean is_insn)
e0001a05
NC		 3712{
3713 /* Finish off this fragment so that it has at LEAST the desired
3714 max_growth. If it doesn't fit in this fragment, close this one
3715 and start a new one. In either case, return a pointer to the
3716 beginning of the growth area. */
3717
3718 fragS *old_frag;
43cd72b9 3719
e0001a05
NC		 3720 xg_force_frag_space (max_growth);
3721
3722 old_frag = frag_now;
3723
3724 frag_now->fr_opcode = last_insn;
3725 if (is_insn)
3726 frag_now->tc_frag_data.is_insn = TRUE;
3727
3728 frag_var (rs_machine_dependent, max_growth, max_growth,
43cd72b9
BW		 3729 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3730
3731 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3732 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 3733
3734 /* Just to make sure that we did not split it up. */
3735 assert (old_frag->fr_next == frag_now);
3736}
3737
3738
7fa3d080
BW		 3739/* Return TRUE if the target frag is one of the next non-empty frags. */
3740
3741static bfd_boolean
3742is_next_frag_target (const fragS *fragP, const fragS *target)
3743{
3744 if (fragP == NULL)
3745 return FALSE;
3746
3747 for (; fragP; fragP = fragP->fr_next)
3748 {
3749 if (fragP == target)
3750 return TRUE;
3751 if (fragP->fr_fix != 0)
3752 return FALSE;
3753 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3754 return FALSE;
3755 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3756 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3757 return FALSE;
3758 if (fragP->fr_type == rs_space)
3759 return FALSE;
3760 }
3761 return FALSE;
3762}
3763
3764
e0001a05 3765static bfd_boolean
7fa3d080 3766is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
e0001a05
NC		 3767{
3768 xtensa_isa isa = xtensa_default_isa;
3769 int i;
43cd72b9 3770 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 3771 int target_op = -1;
3772 symbolS *sym;
3773 fragS *target_frag;
3774
43cd72b9
BW		 3775 if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
3776 && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
e0001a05
NC		 3777 return FALSE;
3778
3779 for (i = 0; i < num_ops; i++)
3780 {
43cd72b9 3781 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
e0001a05
NC		 3782 {
3783 target_op = i;
3784 break;
3785 }
3786 }
3787 if (target_op == -1)
3788 return FALSE;
3789
3790 if (insn->ntok <= target_op)
3791 return FALSE;
3792
3793 if (insn->tok[target_op].X_op != O_symbol)
3794 return FALSE;
3795
3796 sym = insn->tok[target_op].X_add_symbol;
3797 if (sym == NULL)
3798 return FALSE;
3799
3800 if (insn->tok[target_op].X_add_number != 0)
3801 return FALSE;
3802
3803 target_frag = symbol_get_frag (sym);
3804 if (target_frag == NULL)
3805 return FALSE;
3806
3807 if (is_next_frag_target (fragP->fr_next, target_frag)
3808 && S_GET_VALUE (sym) == target_frag->fr_address)
3809 return TRUE;
3810
3811 return FALSE;
3812}
3813
3814
3815static void
7fa3d080 3816xg_add_branch_and_loop_targets (TInsn *insn)
e0001a05
NC		 3817{
3818 xtensa_isa isa = xtensa_default_isa;
7fa3d080 3819 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
43cd72b9 3820
7fa3d080
BW		 3821 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3822 {
3823 int i = 1;
3824 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3825 && insn->tok[i].X_op == O_symbol)
3826 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3827 return;
3828 }
e0001a05 3829
7fa3d080
BW		 3830 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3831 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
e0001a05 3832 {
7fa3d080
BW		 3833 int i;
3834
3835 for (i = 0; i < insn->ntok && i < num_ops; i++)
3836 {
3837 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3838 && insn->tok[i].X_op == O_symbol)
3839 {
3840 symbolS *sym = insn->tok[i].X_add_symbol;
3841 symbol_get_tc (sym)->is_branch_target = TRUE;
3842 if (S_IS_DEFINED (sym))
3843 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3844 }
3845 }
e0001a05 3846 }
e0001a05
NC		 3847}
3848
3849
43cd72b9 3850/* Return FALSE if no error. */
e0001a05 3851
7fa3d080
BW		 3852static bfd_boolean
3853xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
e0001a05
NC		 3854{
3855 int num_ops = 0;
3856 BuildOp *b_op;
3857
3858 switch (instr_spec->typ)
3859 {
3860 case INSTR_INSTR:
3861 new_insn->insn_type = ITYPE_INSN;
3862 new_insn->opcode = instr_spec->opcode;
3863 new_insn->is_specific_opcode = FALSE;
43cd72b9 3864 new_insn->loc = old_insn->loc;
e0001a05
NC		 3865 break;
3866 case INSTR_LITERAL_DEF:
3867 new_insn->insn_type = ITYPE_LITERAL;
3868 new_insn->opcode = XTENSA_UNDEFINED;
3869 new_insn->is_specific_opcode = FALSE;
43cd72b9 3870 new_insn->loc = old_insn->loc;
e0001a05
NC		 3871 break;
3872 case INSTR_LABEL_DEF:
3873 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3874 break;
3875 }
3876
3877 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3878 {
3879 expressionS *exp;
3880 const expressionS *src_exp;
3881
3882 num_ops++;
3883 switch (b_op->typ)
3884 {
3885 case OP_CONSTANT:
3886 /* The expression must be the constant. */
3887 assert (b_op->op_num < MAX_INSN_ARGS);
3888 exp = &new_insn->tok[b_op->op_num];
3889 set_expr_const (exp, b_op->op_data);
3890 break;
3891
3892 case OP_OPERAND:
3893 assert (b_op->op_num < MAX_INSN_ARGS);
3894 assert (b_op->op_data < (unsigned) old_insn->ntok);
3895 src_exp = &old_insn->tok[b_op->op_data];
3896 exp = &new_insn->tok[b_op->op_num];
3897 copy_expr (exp, src_exp);
3898 break;
3899
3900 case OP_LITERAL:
3901 case OP_LABEL:
3902 as_bad (_("can't handle generation of literal/labels yet"));
3903 assert (0);
3904
3905 default:
3906 as_bad (_("can't handle undefined OP TYPE"));
3907 assert (0);
3908 }
3909 }
3910
3911 new_insn->ntok = num_ops;
3912 return FALSE;
3913}
3914
3915
43cd72b9 3916/* Return TRUE if it was simplified. */
e0001a05 3917
7fa3d080
BW		 3918static bfd_boolean
3919xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
e0001a05 3920{
43cd72b9 3921 TransitionRule *rule;
e0001a05 3922 BuildInstr *insn_spec;
43cd72b9
BW		 3923
3924 if (old_insn->is_specific_opcode || !density_supported)
3925 return FALSE;
3926
3927 rule = xg_instruction_match (old_insn);
e0001a05
NC		 3928 if (rule == NULL)
3929 return FALSE;
3930
3931 insn_spec = rule->to_instr;
3932 /* There should only be one. */
3933 assert (insn_spec != NULL);
3934 assert (insn_spec->next == NULL);
3935 if (insn_spec->next != NULL)
3936 return FALSE;
3937
3938 xg_build_token_insn (insn_spec, old_insn, new_insn);
3939
3940 return TRUE;
3941}
3942
3943
3944/* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3945 l32i.n. (2) Check the number of operands. (3) Place the instruction
3946 tokens into the stack or if we can relax it at assembly time, place
43cd72b9 3947 multiple instructions/literals onto the stack. Return FALSE if no
e0001a05
NC		 3948 error. */
3949
3950static bfd_boolean
7fa3d080 3951xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
e0001a05
NC		 3952{
3953 int noperands;
3954 TInsn new_insn;
3955 memset (&new_insn, 0, sizeof (TInsn));
3956
43cd72b9
BW		 3957 /* Narrow it if we can. xg_simplify_insn now does all the
3958 appropriate checking (e.g., for the density option). */
3959 if (xg_simplify_insn (orig_insn, &new_insn))
3960 orig_insn = &new_insn;
e0001a05 3961
43cd72b9
BW		 3962 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
3963 orig_insn->opcode);
e0001a05
NC		 3964 if (orig_insn->ntok < noperands)
3965 {
3966 as_bad (_("found %d operands for '%s': Expected %d"),
3967 orig_insn->ntok,
3968 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3969 noperands);
3970 return TRUE;
3971 }
3972 if (orig_insn->ntok > noperands)
3973 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3974 orig_insn->ntok,
3975 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3976 noperands);
3977
43cd72b9 3978 /* If there are not enough operands, we will assert above. If there
e0001a05
NC		 3979 are too many, just cut out the extras here. */
3980
3981 orig_insn->ntok = noperands;
3982
43cd72b9 3983 /* Cases:
e0001a05
NC		 3984
3985 Instructions with all constant immeds:
3986 Assemble them and relax the instruction if possible.
3987 Give error if not possible; no fixup needed.
3988
3989 Instructions with symbolic immeds:
3990 Assemble them with a Fix up (that may cause instruction expansion).
43cd72b9
BW		 3991 Also close out the fragment if the fixup may cause instruction expansion.
3992
e0001a05
NC		 3993 There are some other special cases where we need alignment.
3994 1) before certain instructions with required alignment (OPCODE_ALIGN)
3995 2) before labels that have jumps (LABEL_ALIGN)
3996 3) after call instructions (RETURN_ALIGN)
43cd72b9
BW		 3997 Multiple of these may be possible on the same fragment.
3998 If so, make sure to satisfy the required alignment.
e0001a05
NC		 3999 Then try to get the desired alignment. */
4000
4001 if (tinsn_has_invalid_symbolic_operands (orig_insn))
4002 return TRUE;
4003
43cd72b9 4004 if (orig_insn->is_specific_opcode || !use_transform ())
e0001a05
NC		 4005 {
4006 istack_push (istack, orig_insn);
4007 return FALSE;
4008 }
4009
4010 if (tinsn_has_symbolic_operands (orig_insn))
4011 {
4012 if (tinsn_has_complex_operands (orig_insn))
4013 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4014 else
4015 istack_push (istack, orig_insn);
4016 }
4017 else
4018 {
4019 if (xg_immeds_fit (orig_insn))
4020 istack_push (istack, orig_insn);
4021 else
4022 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4023 }
4024
e0001a05
NC		 4025 return FALSE;
4026}
4027
4028
7fa3d080
BW		 4029/* Return TRUE if the section flags are marked linkonce
4030 or the name is .gnu.linkonce*. */
4031
4032static bfd_boolean
4033get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4034{
4035 flagword flags, link_once_flags;
4036
4037 flags = bfd_get_section_flags (abfd, sec);
4038 link_once_flags = (flags & SEC_LINK_ONCE);
4039
4040 /* Flags might not be set yet. */
4041 if (!link_once_flags)
4042 {
4043 static size_t len = sizeof ".gnu.linkonce.t.";
4044
4045 if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
4046 link_once_flags = SEC_LINK_ONCE;
4047 }
4048 return (link_once_flags != 0);
4049}
4050
4051
4052static void
4053xtensa_add_literal_sym (symbolS *sym)
4054{
4055 sym_list *l;
4056
4057 l = (sym_list *) xmalloc (sizeof (sym_list));
4058 l->sym = sym;
4059 l->next = literal_syms;
4060 literal_syms = l;
4061}
4062
4063
4064static symbolS *
4065xtensa_create_literal_symbol (segT sec, fragS *frag)
4066{
4067 static int lit_num = 0;
4068 static char name[256];
4069 symbolS *symbolP;
4070
4071 sprintf (name, ".L_lit_sym%d", lit_num);
4072
4073 /* Create a local symbol. If it is in a linkonce section, we have to
4074 be careful to make sure that if it is used in a relocation that the
4075 symbol will be in the output file. */
4076 if (get_is_linkonce_section (stdoutput, sec))
4077 {
4078 symbolP = symbol_new (name, sec, 0, frag);
4079 S_CLEAR_EXTERNAL (symbolP);
4080 /* symbolP->local = 1; */
4081 }
4082 else
4083 symbolP = symbol_new (name, sec, 0, frag);
4084
4085 xtensa_add_literal_sym (symbolP);
4086
4087 frag->tc_frag_data.is_literal = TRUE;
4088 lit_num++;
4089 return symbolP;
4090}
4091
4092
e0001a05
NC		 4093/* Currently all literals that are generated here are 32-bit L32R targets. */
4094
7fa3d080
BW		 4095static symbolS *
4096xg_assemble_literal (/* const */ TInsn *insn)
e0001a05
NC		 4097{
4098 emit_state state;
4099 symbolS *lit_sym = NULL;
4100
4101 /* size = 4 for L32R. It could easily be larger when we move to
4102 larger constants. Add a parameter later. */
4103 offsetT litsize = 4;
4104 offsetT litalign = 2; /* 2^2 = 4 */
4105 expressionS saved_loc;
43cd72b9
BW		 4106 expressionS * emit_val;
4107
e0001a05
NC		 4108 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4109
4110 assert (insn->insn_type == ITYPE_LITERAL);
77cd6497 4111 assert (insn->ntok == 1); /* must be only one token here */
e0001a05
NC		 4112
4113 xtensa_switch_to_literal_fragment (&state);
4114
43cd72b9
BW		 4115 emit_val = &insn->tok[0];
4116 if (emit_val->X_op == O_big)
4117 {
4118 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4119 if (size > litsize)
4120 {
4121 /* This happens when someone writes a "movi a2, big_number". */
4122 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4123 _("invalid immediate"));
4124 xtensa_restore_emit_state (&state);
4125 return NULL;
4126 }
4127 }
4128
e0001a05
NC		 4129 /* Force a 4-byte align here. Note that this opens a new frag, so all
4130 literals done with this function have a frag to themselves. That's
4131 important for the way text section literals work. */
4132 frag_align (litalign, 0, 0);
43cd72b9 4133 record_alignment (now_seg, litalign);
e0001a05 4134
43cd72b9
BW		 4135 if (emit_val->X_op == O_pltrel)
4136 {
4137 char *p = frag_more (litsize);
4138 xtensa_set_frag_assembly_state (frag_now);
4139 if (emit_val->X_add_symbol)
4140 emit_val->X_op = O_symbol;
4141 else
4142 emit_val->X_op = O_constant;
4143 fix_new_exp (frag_now, p - frag_now->fr_literal,
4144 litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
4145 }
4146 else
4147 emit_expr (emit_val, litsize);
e0001a05
NC		 4148
4149 assert (frag_now->tc_frag_data.literal_frag == NULL);
4150 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4151 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4152 lit_sym = frag_now->fr_symbol;
4153 frag_now->tc_frag_data.is_literal = TRUE;
4154
4155 /* Go back. */
4156 xtensa_restore_emit_state (&state);
4157 return lit_sym;
4158}
4159
4160
4161static void
7fa3d080 4162xg_assemble_literal_space (/* const */ int size, int slot)
e0001a05
NC		 4163{
4164 emit_state state;
43cd72b9 4165 /* We might have to do something about this alignment. It only
e0001a05
NC		 4166 takes effect if something is placed here. */
4167 offsetT litalign = 2; /* 2^2 = 4 */
4168 fragS *lit_saved_frag;
4169
e0001a05 4170 assert (size % 4 == 0);
e0001a05
NC		 4171
4172 xtensa_switch_to_literal_fragment (&state);
4173
4174 /* Force a 4-byte align here. */
4175 frag_align (litalign, 0, 0);
43cd72b9 4176 record_alignment (now_seg, litalign);
e0001a05
NC		 4177
4178 xg_force_frag_space (size);
4179
4180 lit_saved_frag = frag_now;
4181 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4182 frag_now->tc_frag_data.is_literal = TRUE;
4183 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
43cd72b9 4184 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
e0001a05
NC		 4185
4186 /* Go back. */
4187 xtensa_restore_emit_state (&state);
43cd72b9 4188 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
e0001a05
NC		 4189}
4190
4191
e0001a05 4192/* Put in a fixup record based on the opcode.
43cd72b9 4193 Return TRUE on success. */
e0001a05 4194
7fa3d080
BW		 4195static bfd_boolean
4196xg_add_opcode_fix (TInsn *tinsn,
4197 int opnum,
4198 xtensa_format fmt,
4199 int slot,
4200 expressionS *expr,
4201 fragS *fragP,
4202 offsetT offset)
43cd72b9
BW		 4203{
4204 xtensa_opcode opcode = tinsn->opcode;
4205 bfd_reloc_code_real_type reloc;
4206 reloc_howto_type *howto;
4207 int fmt_length;
e0001a05
NC		 4208 fixS *the_fix;
4209
43cd72b9
BW		 4210 reloc = BFD_RELOC_NONE;
4211
4212 /* First try the special cases for "alternate" relocs. */
4213 if (opcode == xtensa_l32r_opcode)
4214 {
4215 if (fragP->tc_frag_data.use_absolute_literals)
4216 reloc = encode_alt_reloc (slot);
4217 }
4218 else if (opcode == xtensa_const16_opcode)
4219 {
4220 if (expr->X_op == O_lo16)
4221 {
4222 reloc = encode_reloc (slot);
4223 expr->X_op = O_symbol;
4224 }
4225 else if (expr->X_op == O_hi16)
4226 {
4227 reloc = encode_alt_reloc (slot);
4228 expr->X_op = O_symbol;
4229 }
4230 }
4231
4232 if (opnum != get_relaxable_immed (opcode))
e0001a05 4233 {
43cd72b9 4234 as_bad (_("invalid relocation for operand %i of '%s'"),
e0001a05
NC		 4235 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4236 return FALSE;
4237 }
4238
43cd72b9
BW		 4239 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4240 into the symbol table where the generic portions of the assembler
4241 won't know what to do with them. */
4242 if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4243 {
4244 as_bad (_("invalid expression for operand %i of '%s'"),
4245 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4246 return FALSE;
4247 }
4248
4249 /* Next try the generic relocs. */
4250 if (reloc == BFD_RELOC_NONE)
4251 reloc = encode_reloc (slot);
4252 if (reloc == BFD_RELOC_NONE)
4253 {
4254 as_bad (_("invalid relocation in instruction slot %i"), slot);
4255 return FALSE;
4256 }
e0001a05 4257
43cd72b9 4258 howto = bfd_reloc_type_lookup (stdoutput, reloc);
e0001a05
NC		 4259 if (!howto)
4260 {
43cd72b9 4261 as_bad (_("undefined symbol for opcode \"%s\""),
e0001a05
NC		 4262 xtensa_opcode_name (xtensa_default_isa, opcode));
4263 return FALSE;
4264 }
4265
43cd72b9
BW		 4266 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4267 the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
e0001a05 4268 howto->pc_relative, reloc);
d9740523 4269 the_fix->fx_no_overflow = 1;
e0001a05 4270
7fa3d080
BW		 4271 if (expr->X_add_symbol
4272 && (S_IS_EXTERNAL (expr->X_add_symbol)
4273 || S_IS_WEAK (expr->X_add_symbol)))
4274 the_fix->fx_plt = TRUE;
4275
4276 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4277 the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4278 the_fix->tc_fix_data.slot = slot;
4279
4280 return TRUE;
4281}
4282
4283
4284static bfd_boolean
4285xg_emit_insn_to_buf (TInsn *tinsn,
4286 xtensa_format fmt,
4287 char *buf,
4288 fragS *fragP,
4289 offsetT offset,
4290 bfd_boolean build_fix)
4291{
4292 static xtensa_insnbuf insnbuf = NULL;
4293 bfd_boolean has_symbolic_immed = FALSE;
4294 bfd_boolean ok = TRUE;
4295 if (!insnbuf)
4296 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4297
4298 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4299 if (has_symbolic_immed && build_fix)
4300 {
4301 /* Add a fixup. */
4302 int opnum = get_relaxable_immed (tinsn->opcode);
4303 expressionS *exp = &tinsn->tok[opnum];
43cd72b9 4304
7fa3d080
BW		 4305 if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset))
4306 ok = FALSE;
4307 }
4308 fragP->tc_frag_data.is_insn = TRUE;
4309 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
4310 return ok;
e0001a05
NC		 4311}
4312
4313
7fa3d080
BW		 4314static void
4315xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
e0001a05
NC		 4316{
4317 symbolS *sym = get_special_literal_symbol ();
4318 int i;
4319 if (lit_sym == 0)
4320 return;
4321 assert (insn->insn_type == ITYPE_INSN);
4322 for (i = 0; i < insn->ntok; i++)
4323 if (insn->tok[i].X_add_symbol == sym)
4324 insn->tok[i].X_add_symbol = lit_sym;
4325
4326}
4327
4328
7fa3d080
BW		 4329static void
4330xg_resolve_labels (TInsn *insn, symbolS *label_sym)
e0001a05
NC		 4331{
4332 symbolS *sym = get_special_label_symbol ();
4333 int i;
43cd72b9 4334 /* assert (!insn->is_literal); */
e0001a05
NC		 4335 for (i = 0; i < insn->ntok; i++)
4336 if (insn->tok[i].X_add_symbol == sym)
4337 insn->tok[i].X_add_symbol = label_sym;
4338
4339}
4340
4341
43cd72b9 4342/* Return TRUE if the instruction can write to the specified
e0001a05
NC		 4343 integer register. */
4344
4345static bfd_boolean
7fa3d080 4346is_register_writer (const TInsn *insn, const char *regset, int regnum)
e0001a05
NC		 4347{
4348 int i;
4349 int num_ops;
4350 xtensa_isa isa = xtensa_default_isa;
4351
43cd72b9 4352 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 4353
4354 for (i = 0; i < num_ops; i++)
4355 {
43cd72b9
BW		 4356 char inout;
4357 inout = xtensa_operand_inout (isa, insn->opcode, i);
4358 if ((inout == 'o' || inout == 'm')
4359 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
e0001a05 4360 {
43cd72b9
BW		 4361 xtensa_regfile opnd_rf =
4362 xtensa_operand_regfile (isa, insn->opcode, i);
4363 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
e0001a05
NC		 4364 {
4365 if ((insn->tok[i].X_op == O_register)
4366 && (insn->tok[i].X_add_number == regnum))
4367 return TRUE;
4368 }
4369 }
4370 }
4371 return FALSE;
4372}
4373
4374
4375static bfd_boolean
7fa3d080 4376is_bad_loopend_opcode (const TInsn *tinsn)
e0001a05
NC		 4377{
4378 xtensa_opcode opcode = tinsn->opcode;
4379
4380 if (opcode == XTENSA_UNDEFINED)
4381 return FALSE;
4382
4383 if (opcode == xtensa_call0_opcode
4384 || opcode == xtensa_callx0_opcode
4385 || opcode == xtensa_call4_opcode
4386 || opcode == xtensa_callx4_opcode
4387 || opcode == xtensa_call8_opcode
4388 || opcode == xtensa_callx8_opcode
4389 || opcode == xtensa_call12_opcode
4390 || opcode == xtensa_callx12_opcode
4391 || opcode == xtensa_isync_opcode
4392 || opcode == xtensa_ret_opcode
4393 || opcode == xtensa_ret_n_opcode
4394 || opcode == xtensa_retw_opcode
4395 || opcode == xtensa_retw_n_opcode
43cd72b9
BW		 4396 || opcode == xtensa_waiti_opcode
4397 || opcode == xtensa_rsr_lcount_opcode)
e0001a05
NC		 4398 return TRUE;
4399
e0001a05
NC		 4400 return FALSE;
4401}
4402
4403
4404/* Labels that begin with ".Ln" or ".LM" are unaligned.
4405 This allows the debugger to add unaligned labels.
4406 Also, the assembler generates stabs labels that need
4407 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4408
7fa3d080
BW		 4409static bfd_boolean
4410is_unaligned_label (symbolS *sym)
e0001a05
NC		 4411{
4412 const char *name = S_GET_NAME (sym);
4413 static size_t fake_size = 0;
4414
4415 if (name
4416 && name[0] == '.'
4417 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4418 return TRUE;
4419
4420 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4421 if (fake_size == 0)
4422 fake_size = strlen (FAKE_LABEL_NAME);
4423
43cd72b9 4424 if (name
e0001a05
NC		 4425 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4426 && (name[fake_size] == 'F'
4427 || name[fake_size] == 'L'
4428 || (name[fake_size] == 'e'
4429 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4430 return TRUE;
4431
4432 return FALSE;
4433}
4434
4435
7fa3d080
BW		 4436static fragS *
4437next_non_empty_frag (const fragS *fragP)
e0001a05
NC		 4438{
4439 fragS *next_fragP = fragP->fr_next;
4440
4441 /* Sometimes an empty will end up here due storage allocation issues.
4442 So we have to skip until we find something legit. */
4443 while (next_fragP && next_fragP->fr_fix == 0)
4444 next_fragP = next_fragP->fr_next;
4445
4446 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4447 return NULL;
4448
4449 return next_fragP;
4450}
4451
4452
43cd72b9 4453static bfd_boolean
7fa3d080 4454next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
43cd72b9
BW		 4455{
4456 xtensa_opcode out_opcode;
4457 const fragS *next_fragP = next_non_empty_frag (fragP);
4458
4459 if (next_fragP == NULL)
4460 return FALSE;
4461
4462 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4463 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4464 {
4465 *opcode = out_opcode;
4466 return TRUE;
4467 }
4468 return FALSE;
4469}
4470
4471
4472static int
7fa3d080 4473frag_format_size (const fragS *fragP)
43cd72b9 4474{
e0001a05
NC		 4475 static xtensa_insnbuf insnbuf = NULL;
4476 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 4477 xtensa_format fmt;
4478 int fmt_size;
e0001a05
NC		 4479
4480 if (!insnbuf)
4481 insnbuf = xtensa_insnbuf_alloc (isa);
4482
43cd72b9
BW		 4483 if (fragP == NULL)
4484 return XTENSA_UNDEFINED;
4485
4486 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal, 0);
4487
4488 fmt = xtensa_format_decode (isa, insnbuf);
4489 if (fmt == XTENSA_UNDEFINED)
e0001a05 4490 return XTENSA_UNDEFINED;
43cd72b9
BW		 4491 fmt_size = xtensa_format_length (isa, fmt);
4492
4493 /* If the next format won't be changing due to relaxation, just
4494 return the length of the first format. */
4495 if (fragP->fr_opcode != fragP->fr_literal)
4496 return fmt_size;
4497
4498 /* If during relaxation we have to pull an instruction out of a
4499 multi-slot instruction, we will return the more conservative
4500 number. This works because alignment on bigger instructions
4501 is more restrictive than alignment on smaller instructions.
4502 This is more conservative than we would like, but it happens
4503 infrequently. */
4504
4505 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4506 return fmt_size;
4507
4508 /* If we aren't doing one of our own relaxations or it isn't
4509 slot-based, then the insn size won't change. */
4510 if (fragP->fr_type != rs_machine_dependent)
4511 return fmt_size;
4512 if (fragP->fr_subtype != RELAX_SLOTS)
4513 return fmt_size;
4514
4515 /* If an instruction is about to grow, return the longer size. */
4516 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4517 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
4518 return 3;
4519
4520 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4521 return 2 + fragP->tc_frag_data.text_expansion[0];
e0001a05 4522
43cd72b9 4523 return fmt_size;
e0001a05
NC		 4524}
4525
4526
7fa3d080
BW		 4527static int
4528next_frag_format_size (const fragS *fragP)
e0001a05 4529{
7fa3d080
BW		 4530 const fragS *next_fragP = next_non_empty_frag (fragP);
4531 return frag_format_size (next_fragP);
e0001a05
NC		 4532}
4533
4534
4535/* If the next legit fragment is an end-of-loop marker,
4536 switch its state so it will instantiate a NOP. */
4537
4538static void
1d19a770 4539update_next_frag_state (fragS *fragP)
e0001a05
NC		 4540{
4541 fragS *next_fragP = fragP->fr_next;
43cd72b9 4542 fragS *new_target = NULL;
e0001a05 4543
43cd72b9
BW		 4544 if (align_targets)
4545 {
4546 /* We are guaranteed there will be one of these... */
4547 while (!(next_fragP->fr_type == rs_machine_dependent
4548 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4549 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4550 next_fragP = next_fragP->fr_next;
4551
4552 assert (next_fragP->fr_type == rs_machine_dependent
4553 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4554 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4555
4556 /* ...and one of these. */
4557 new_target = next_fragP->fr_next;
4558 while (!(new_target->fr_type == rs_machine_dependent
4559 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4560 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4561 new_target = new_target->fr_next;
4562
4563 assert (new_target->fr_type == rs_machine_dependent
4564 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4565 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4566 }
43cd72b9 4567
1d19a770 4568 while (next_fragP && next_fragP->fr_fix == 0)
43cd72b9 4569 {
1d19a770
BW		 4570 if (next_fragP->fr_type == rs_machine_dependent
4571 && next_fragP->fr_subtype == RELAX_LOOP_END)
43cd72b9 4572 {
1d19a770
BW		 4573 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4574 return;
e0001a05 4575 }
1d19a770
BW		 4576
4577 next_fragP = next_fragP->fr_next;
e0001a05
NC		 4578 }
4579}
4580
4581
4582static bfd_boolean
7fa3d080 4583next_frag_is_branch_target (const fragS *fragP)
e0001a05 4584{
43cd72b9 4585 /* Sometimes an empty will end up here due to storage allocation issues,
e0001a05
NC		 4586 so we have to skip until we find something legit. */
4587 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4588 {
4589 if (fragP->tc_frag_data.is_branch_target)
4590 return TRUE;
4591 if (fragP->fr_fix != 0)
4592 break;
4593 }
4594 return FALSE;
4595}
4596
4597
4598static bfd_boolean
7fa3d080 4599next_frag_is_loop_target (const fragS *fragP)
e0001a05
NC		 4600{
4601 /* Sometimes an empty will end up here due storage allocation issues.
4602 So we have to skip until we find something legit. */
4603 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4604 {
4605 if (fragP->tc_frag_data.is_loop_target)
4606 return TRUE;
4607 if (fragP->fr_fix != 0)
4608 break;
4609 }
4610 return FALSE;
4611}
4612
4613
4614static addressT
7fa3d080 4615next_frag_pre_opcode_bytes (const fragS *fragp)
e0001a05
NC		 4616{
4617 const fragS *next_fragp = fragp->fr_next;
43cd72b9 4618 xtensa_opcode next_opcode;
e0001a05 4619
43cd72b9 4620 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
e0001a05
NC		 4621 return 0;
4622
43cd72b9
BW		 4623 /* Sometimes an empty will end up here due to storage allocation issues,
4624 so we have to skip until we find something legit. */
e0001a05
NC		 4625 while (next_fragp->fr_fix == 0)
4626 next_fragp = next_fragp->fr_next;
4627
4628 if (next_fragp->fr_type != rs_machine_dependent)
4629 return 0;
4630
4631 /* There is some implicit knowledge encoded in here.
4632 The LOOP instructions that are NOT RELAX_IMMED have
43cd72b9
BW		 4633 been relaxed. Note that we can assume that the LOOP
4634 instruction is in slot 0 because loops aren't bundleable. */
4635 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
e0001a05
NC		 4636 return get_expanded_loop_offset (next_opcode);
4637
4638 return 0;
4639}
4640
4641
4642/* Mark a location where we can later insert literal frags. Update
4643 the section's literal_pool_loc, so subsequent literals can be
4644 placed nearest to their use. */
4645
4646static void
7fa3d080 4647xtensa_mark_literal_pool_location (void)
e0001a05
NC		 4648{
4649 /* Any labels pointing to the current location need
4650 to be adjusted to after the literal pool. */
4651 emit_state s;
e0001a05 4652 fragS *pool_location;
e0001a05 4653
43cd72b9
BW		 4654 if (use_literal_section && !directive_state[directive_absolute_literals])
4655 return;
4656
e0001a05 4657 frag_align (2, 0, 0);
43cd72b9 4658 record_alignment (now_seg, 2);
e0001a05
NC		 4659
4660 /* We stash info in the fr_var of these frags
43cd72b9 4661 so we can later move the literal's fixes into this
e0001a05
NC		 4662 frchain's fix list. We can use fr_var because fr_var's
4663 interpretation depends solely on the fr_type and subtype. */
4664 pool_location = frag_now;
43cd72b9 4665 frag_variant (rs_machine_dependent, 0, (int) frchain_now,
e0001a05 4666 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
43cd72b9
BW		 4667 xtensa_set_frag_assembly_state (frag_now);
4668 frag_variant (rs_machine_dependent, 0, (int) now_seg,
e0001a05 4669 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
43cd72b9 4670 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4671
4672 /* Now put a frag into the literal pool that points to this location. */
4673 set_literal_pool_location (now_seg, pool_location);
43cd72b9
BW		 4674 xtensa_switch_to_non_abs_literal_fragment (&s);
4675 frag_align (2, 0, 0);
4676 record_alignment (now_seg, 2);
e0001a05
NC		 4677
4678 /* Close whatever frag is there. */
4679 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 4680 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4681 frag_now->tc_frag_data.literal_frag = pool_location;
4682 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4683 xtensa_restore_emit_state (&s);
43cd72b9 4684 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4685}
4686
4687
43cd72b9
BW		 4688/* Build a nop of the correct size into tinsn. */
4689
4690static void
7fa3d080 4691build_nop (TInsn *tinsn, int size)
43cd72b9
BW		 4692{
4693 tinsn_init (tinsn);
4694 switch (size)
4695 {
4696 case 2:
4697 tinsn->opcode = xtensa_nop_n_opcode;
4698 tinsn->ntok = 0;
4699 if (tinsn->opcode == XTENSA_UNDEFINED)
4700 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4701 break;
4702
4703 case 3:
4704 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4705 {
4706 tinsn->opcode = xtensa_or_opcode;
4707 set_expr_const (&tinsn->tok[0], 1);
4708 set_expr_const (&tinsn->tok[1], 1);
4709 set_expr_const (&tinsn->tok[2], 1);
4710 tinsn->ntok = 3;
4711 }
4712 else
4713 tinsn->opcode = xtensa_nop_opcode;
4714
4715 assert (tinsn->opcode != XTENSA_UNDEFINED);
4716 }
4717}
4718
4719
e0001a05
NC		 4720/* Assemble a NOP of the requested size in the buffer. User must have
4721 allocated "buf" with at least "size" bytes. */
4722
7fa3d080
BW		 4723static void
4724assemble_nop (size_t size, char *buf)
e0001a05
NC		 4725{
4726 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 4727 TInsn tinsn;
e0001a05 4728
43cd72b9 4729 build_nop (&tinsn, size);
e0001a05 4730
43cd72b9
BW		 4731 if (!insnbuf)
4732 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
e0001a05 4733
43cd72b9
BW		 4734 tinsn_to_insnbuf (&tinsn, insnbuf);
4735 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
e0001a05
NC		 4736}
4737
4738
4739/* Return the number of bytes for the offset of the expanded loop
4740 instruction. This should be incorporated into the relaxation
4741 specification but is hard-coded here. This is used to auto-align
4742 the loop instruction. It is invalid to call this function if the
4743 configuration does not have loops or if the opcode is not a loop
4744 opcode. */
4745
4746static addressT
7fa3d080 4747get_expanded_loop_offset (xtensa_opcode opcode)
e0001a05
NC		 4748{
4749 /* This is the OFFSET of the loop instruction in the expanded loop.
4750 This MUST correspond directly to the specification of the loop
4751 expansion. It will be validated on fragment conversion. */
43cd72b9 4752 assert (opcode != XTENSA_UNDEFINED);
e0001a05
NC		 4753 if (opcode == xtensa_loop_opcode)
4754 return 0;
4755 if (opcode == xtensa_loopnez_opcode)
4756 return 3;
4757 if (opcode == xtensa_loopgtz_opcode)
4758 return 6;
4759 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4760 return 0;
4761}
4762
4763
7fa3d080
BW		 4764static fragS *
4765get_literal_pool_location (segT seg)
e0001a05
NC		 4766{
4767 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4768}
4769
4770
4771static void
7fa3d080 4772set_literal_pool_location (segT seg, fragS *literal_pool_loc)
e0001a05
NC		 4773{
4774 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4775}
4776
43cd72b9
BW		 4777
4778/* Set frag assembly state should be called when a new frag is
4779 opened and after a frag has been closed. */
4780
7fa3d080
BW		 4781static void
4782xtensa_set_frag_assembly_state (fragS *fragP)
43cd72b9
BW		 4783{
4784 if (!density_supported)
4785 fragP->tc_frag_data.is_no_density = TRUE;
4786
4787 /* This function is called from subsegs_finish, which is called
4788 after xtensa_end, so we can't use "use_transform" or
4789 "use_schedule" here. */
4790 if (!directive_state[directive_transform])
4791 fragP->tc_frag_data.is_no_transform = TRUE;
4792 fragP->tc_frag_data.use_absolute_literals =
4793 directive_state[directive_absolute_literals];
4794 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4795}
4796
4797
7fa3d080
BW		 4798static bfd_boolean
4799relaxable_section (asection *sec)
43cd72b9
BW		 4800{
4801 return (sec->flags & SEC_DEBUGGING) == 0;
4802}
4803
4804
4805static void
7fa3d080 4806xtensa_find_unmarked_state_frags (void)
43cd72b9
BW		 4807{
4808 segT *seclist;
4809
4810 /* Walk over each fragment of all of the current segments. For each
4811 unmarked fragment, mark it with the same info as the previous
4812 fragment. */
4813 for (seclist = &stdoutput->sections;
4814 seclist && *seclist;
4815 seclist = &(*seclist)->next)
4816 {
4817 segT sec = *seclist;
4818 segment_info_type *seginfo;
4819 fragS *fragP;
4820 flagword flags;
4821 flags = bfd_get_section_flags (stdoutput, sec);
4822 if (flags & SEC_DEBUGGING)
4823 continue;
4824 if (!(flags & SEC_ALLOC))
4825 continue;
4826
4827 seginfo = seg_info (sec);
4828 if (seginfo && seginfo->frchainP)
4829 {
4830 fragS *last_fragP = 0;
4831 for (fragP = seginfo->frchainP->frch_root; fragP;
4832 fragP = fragP->fr_next)
4833 {
4834 if (fragP->fr_fix != 0
4835 && !fragP->tc_frag_data.is_assembly_state_set)
4836 {
4837 if (last_fragP == 0)
4838 {
4839 as_warn_where (fragP->fr_file, fragP->fr_line,
4840 _("assembly state not set for first frag in section %s"),
4841 sec->name);
4842 }
4843 else
4844 {
4845 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4846 fragP->tc_frag_data.is_no_density =
4847 last_fragP->tc_frag_data.is_no_density;
4848 fragP->tc_frag_data.is_no_transform =
4849 last_fragP->tc_frag_data.is_no_transform;
4850 fragP->tc_frag_data.use_absolute_literals =
4851 last_fragP->tc_frag_data.use_absolute_literals;
4852 }
4853 }
4854 if (fragP->tc_frag_data.is_assembly_state_set)
4855 last_fragP = fragP;
4856 }
4857 }
4858 }
4859}
4860
4861
4862static void
7fa3d080
BW		 4863xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4864 asection *sec,
4865 void *unused ATTRIBUTE_UNUSED)
43cd72b9
BW		 4866{
4867 flagword flags = bfd_get_section_flags (abfd, sec);
4868 segment_info_type *seginfo = seg_info (sec);
4869 fragS *frag = seginfo->frchainP->frch_root;
4870
4871 if (flags & SEC_CODE)
4872 {
4873 xtensa_isa isa = xtensa_default_isa;
4874 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4875 while (frag != NULL)
4876 {
4877 if (frag->tc_frag_data.is_branch_target)
4878 {
4879 int op_size;
4880 int frag_addr;
4881 xtensa_format fmt;
4882
4883 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
4884 fmt = xtensa_format_decode (isa, insnbuf);
4885 op_size = xtensa_format_length (isa, fmt);
4886 frag_addr = frag->fr_address % xtensa_fetch_width;
4887 if (frag_addr + op_size > (int) xtensa_fetch_width)
4888 as_warn_where (frag->fr_file, frag->fr_line,
4889 _("unaligned branch target: %d bytes at 0x%lx"),
4890 op_size, frag->fr_address);
4891 }
4892 frag = frag->fr_next;
4893 }
4894 xtensa_insnbuf_free (isa, insnbuf);
4895 }
4896}
4897
4898
4899static void
7fa3d080
BW		 4900xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
4901 asection *sec,
4902 void *unused ATTRIBUTE_UNUSED)
43cd72b9
BW		 4903{
4904 flagword flags = bfd_get_section_flags (abfd, sec);
4905 segment_info_type *seginfo = seg_info (sec);
4906 fragS *frag = seginfo->frchainP->frch_root;
4907 xtensa_isa isa = xtensa_default_isa;
4908
4909 if (flags & SEC_CODE)
4910 {
4911 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4912 while (frag != NULL)
4913 {
4914 if (frag->tc_frag_data.is_first_loop_insn)
4915 {
4916 int op_size;
4917 int frag_addr;
4918 xtensa_format fmt;
4919
4920 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
4921 fmt = xtensa_format_decode (isa, insnbuf);
4922 op_size = xtensa_format_length (isa, fmt);
4923 frag_addr = frag->fr_address % xtensa_fetch_width;
4924
4925 if (frag_addr + op_size > (signed) xtensa_fetch_width)
4926 as_warn_where (frag->fr_file, frag->fr_line,
4927 _("unaligned loop: %d bytes at 0x%lx"),
4928 op_size, frag->fr_address);
4929 }
4930 frag = frag->fr_next;
4931 }
4932 xtensa_insnbuf_free (isa, insnbuf);
4933 }
4934}
4935
4936
7fa3d080
BW		 4937static void
4938xg_apply_tentative_value (fixS *fixP, valueT val)
43cd72b9
BW		 4939{
4940 xtensa_isa isa = xtensa_default_isa;
4941 static xtensa_insnbuf insnbuf = NULL;
4942 static xtensa_insnbuf slotbuf = NULL;
4943 xtensa_format fmt;
4944 int slot;
4945 bfd_boolean alt_reloc;
4946 xtensa_opcode opcode;
4947 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
4948
4949 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
4950 if (alt_reloc)
4951 as_fatal (_("unexpected fix"));
4952
4953 if (!insnbuf)
4954 {
4955 insnbuf = xtensa_insnbuf_alloc (isa);
4956 slotbuf = xtensa_insnbuf_alloc (isa);
4957 }
4958
4959 xtensa_insnbuf_from_chars (isa, insnbuf, fixpos, 0);
4960 fmt = xtensa_format_decode (isa, insnbuf);
4961 if (fmt == XTENSA_UNDEFINED)
4962 as_fatal (_("undecodable fix"));
4963 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
4964 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
4965 if (opcode == XTENSA_UNDEFINED)
4966 as_fatal (_("undecodable fix"));
4967
4968 /* CONST16 immediates are not PC-relative, despite the fact that we
4969 reuse the normal PC-relative operand relocations for the low part
4970 of a CONST16 operand. The code in tc_gen_reloc does not decode
4971 the opcodes so it is more convenient to detect this special case
4972 here. */
4973 if (opcode == xtensa_const16_opcode)
4974 return;
4975
4976 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
4977 get_relaxable_immed (opcode), val,
4978 fixP->fx_file, fixP->fx_line);
4979
4980 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
4981 xtensa_insnbuf_to_chars (isa, insnbuf, fixpos, 0);
4982}
4983
e0001a05
NC		 4984\f
4985/* External Functions and Other GAS Hooks. */
4986
4987const char *
7fa3d080 4988xtensa_target_format (void)
e0001a05
NC		 4989{
4990 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
4991}
4992
4993
4994void
7fa3d080 4995xtensa_file_arch_init (bfd *abfd)
e0001a05
NC		 4996{
4997 bfd_set_private_flags (abfd, 0x100 | 0x200);
4998}
4999
5000
5001void
7fa3d080 5002md_number_to_chars (char *buf, valueT val, int n)
e0001a05
NC		 5003{
5004 if (target_big_endian)
5005 number_to_chars_bigendian (buf, val, n);
5006 else
5007 number_to_chars_littleendian (buf, val, n);
5008}
5009
5010
5011/* This function is called once, at assembler startup time. It should
5012 set up all the tables, etc. that the MD part of the assembler will
5013 need. */
5014
5015void
7fa3d080 5016md_begin (void)
e0001a05
NC		 5017{
5018 segT current_section = now_seg;
5019 int current_subsec = now_subseg;
5020 xtensa_isa isa;
5021
43cd72b9 5022 xtensa_default_isa = xtensa_isa_init (0, 0);
e0001a05 5023 isa = xtensa_default_isa;
e0001a05 5024
43cd72b9
BW		 5025 linkrelax = 1;
5026
5027 /* Set up the .literal, .fini.literal and .init.literal sections. */
e0001a05
NC		 5028 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5029 default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
5030 default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
5031 default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
43cd72b9 5032 default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
e0001a05
NC		 5033
5034 subseg_set (current_section, current_subsec);
5035
43cd72b9
BW		 5036 xg_init_vinsn (&cur_vinsn);
5037
e0001a05
NC		 5038 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5039 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5040 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5041 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5042 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5043 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5044 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5045 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5046 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5047 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
43cd72b9 5048 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
e0001a05 5049 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
43cd72b9
BW		 5050 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5051 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
e0001a05 5052 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
e0001a05 5053 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
43cd72b9 5054 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
e0001a05
NC		 5055 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5056 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5057 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
43cd72b9 5058 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
e0001a05
NC		 5059 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5060 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5061 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5062 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5063 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5064 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
43cd72b9 5065 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
e0001a05 5066 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
43cd72b9
BW		 5067
5068 init_op_placement_info_table ();
5069
5070 /* Set up the assembly state. */
5071 if (!frag_now->tc_frag_data.is_assembly_state_set)
5072 xtensa_set_frag_assembly_state (frag_now);
5073}
5074
5075
5076/* TC_INIT_FIX_DATA hook */
5077
5078void
7fa3d080 5079xtensa_init_fix_data (fixS *x)
43cd72b9
BW		 5080{
5081 x->tc_fix_data.slot = 0;
5082 x->tc_fix_data.X_add_symbol = NULL;
5083 x->tc_fix_data.X_add_number = 0;
e0001a05
NC		 5084}
5085
5086
5087/* tc_frob_label hook */
5088
5089void
7fa3d080 5090xtensa_frob_label (symbolS *sym)
e0001a05 5091{
43cd72b9
BW		 5092 /* Since the label was already attached to a frag associated with the
5093 previous basic block, it now needs to be reset to the current frag. */
5094 symbol_set_frag (sym, frag_now);
5095 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5096
82e7541d
BW		 5097 if (generating_literals)
5098 xtensa_add_literal_sym (sym);
5099 else
5100 xtensa_add_insn_label (sym);
5101
5102 if (symbol_get_tc (sym)->is_loop_target
e0001a05
NC		 5103 && (get_last_insn_flags (now_seg, now_subseg)
5104 & FLAG_IS_BAD_LOOPEND) != 0)
5105 as_bad (_("invalid last instruction for a zero-overhead loop"));
5106
5107 /* No target aligning in the absolute section. */
61846f28 5108 if (now_seg != absolute_section
43cd72b9 5109 && do_align_targets ()
61846f28 5110 && !is_unaligned_label (sym)
43cd72b9
BW		 5111 && !generating_literals)
5112 {
b08b5071 5113 float freq = get_subseg_target_freq (now_seg, now_subseg);
43cd72b9
BW		 5114 xtensa_set_frag_assembly_state (frag_now);
5115
5116 /* The only time this type of frag grows is when there is a
5117 negatable branch that needs to be relaxed as the last
5118 instruction in a zero-overhead loop. Because alignment frags
5119 are so common, marking them all as possibly growing four
5120 bytes makes any worst-case analysis appear much worse than it
5121 is. So, we make fr_var not actually reflect the amount of
5122 memory allocated at the end of this frag, but rather the
5123 amount of memory this frag might grow. The "4, 0" below
5124 allocates four bytes at the end of the frag for room to grow
5125 if we need to relax a loop end with a NOP. Frags prior to
5126 this one might grow to align this one, but the frag itself
5127 won't grow unless it meets the condition above. */
5128
5129#define RELAX_LOOP_END_BYTES 4
5130
5131 frag_var (rs_machine_dependent,
5132 RELAX_LOOP_END_BYTES, (int) freq,
e0001a05
NC		 5133 RELAX_DESIRE_ALIGN_IF_TARGET,
5134 frag_now->fr_symbol, frag_now->fr_offset, NULL);
43cd72b9 5135 xtensa_set_frag_assembly_state (frag_now);
82e7541d 5136 xtensa_move_labels (frag_now, 0, TRUE);
43cd72b9
BW		 5137 }
5138
5139 /* We need to mark the following properties even if we aren't aligning. */
5140
5141 /* If the label is already known to be a branch target, i.e., a
5142 forward branch, mark the frag accordingly. Backward branches
5143 are handled by xg_add_branch_and_loop_targets. */
5144 if (symbol_get_tc (sym)->is_branch_target)
5145 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5146
5147 /* Loops only go forward, so they can be identified here. */
5148 if (symbol_get_tc (sym)->is_loop_target)
5149 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5150}
5151
5152
5153/* tc_unrecognized_line hook */
5154
5155int
7fa3d080 5156xtensa_unrecognized_line (int ch)
43cd72b9
BW		 5157{
5158 switch (ch)
5159 {
5160 case '{' :
5161 if (cur_vinsn.inside_bundle == 0)
5162 {
5163 /* PR8110: Cannot emit line number info inside a FLIX bundle
5164 when using --gstabs. Temporarily disable debug info. */
5165 generate_lineno_debug ();
5166 if (debug_type == DEBUG_STABS)
5167 {
5168 xt_saved_debug_type = debug_type;
5169 debug_type = DEBUG_NONE;
5170 }
82e7541d 5171
43cd72b9
BW		 5172 cur_vinsn.inside_bundle = 1;
5173 }
5174 else
5175 {
5176 as_bad (_("extra opening brace"));
5177 return 0;
5178 }
5179 break;
82e7541d 5180
43cd72b9
BW		 5181 case '}' :
5182 if (cur_vinsn.inside_bundle)
5183 finish_vinsn (&cur_vinsn);
5184 else
5185 {
5186 as_bad (_("extra closing brace"));
5187 return 0;
5188 }
5189 break;
5190 default:
5191 as_bad (_("syntax error"));
5192 return 0;
e0001a05 5193 }
43cd72b9 5194 return 1;
e0001a05
NC		 5195}
5196
5197
5198/* md_flush_pending_output hook */
5199
5200void
7fa3d080 5201xtensa_flush_pending_output (void)
e0001a05 5202{
43cd72b9
BW		 5203 if (cur_vinsn.inside_bundle)
5204 as_bad (_("missing closing brace"));
5205
e0001a05
NC		 5206 /* If there is a non-zero instruction fragment, close it. */
5207 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5208 {
5209 frag_wane (frag_now);
5210 frag_new (0);
43cd72b9 5211 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5212 }
5213 frag_now->tc_frag_data.is_insn = FALSE;
82e7541d
BW		 5214
5215 xtensa_clear_insn_labels ();
e0001a05
NC		 5216}
5217
5218
43cd72b9
BW		 5219/* We had an error while parsing an instruction. The string might look
5220 like this: "insn arg1, arg2 }". If so, we need to see the closing
5221 brace and reset some fields. Otherwise, the vinsn never gets closed
5222 and the num_slots field will grow past the end of the array of slots,
5223 and bad things happen. */
5224
5225static void
7fa3d080 5226error_reset_cur_vinsn (void)
43cd72b9
BW		 5227{
5228 if (cur_vinsn.inside_bundle)
5229 {
5230 if (*input_line_pointer == '}'
5231 || *(input_line_pointer - 1) == '}'
5232 || *(input_line_pointer - 2) == '}')
5233 xg_clear_vinsn (&cur_vinsn);
5234 }
5235}
5236
5237
e0001a05 5238void
7fa3d080 5239md_assemble (char *str)
e0001a05
NC		 5240{
5241 xtensa_isa isa = xtensa_default_isa;
5242 char *opname;
5243 unsigned opnamelen;
5244 bfd_boolean has_underbar = FALSE;
43cd72b9 5245 char *arg_strings[MAX_INSN_ARGS];
e0001a05 5246 int num_args;
e0001a05 5247 TInsn orig_insn; /* Original instruction from the input. */
e0001a05 5248
e0001a05
NC		 5249 tinsn_init (&orig_insn);
5250
5251 /* Split off the opcode. */
5252 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5253 opname = xmalloc (opnamelen + 1);
5254 memcpy (opname, str, opnamelen);
5255 opname[opnamelen] = '\0';
5256
5257 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5258 if (num_args == -1)
5259 {
5260 as_bad (_("syntax error"));
5261 return;
5262 }
5263
5264 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5265 return;
5266
5267 /* Check for an underbar prefix. */
5268 if (*opname == '_')
5269 {
5270 has_underbar = TRUE;
5271 opname += 1;
5272 }
5273
5274 orig_insn.insn_type = ITYPE_INSN;
5275 orig_insn.ntok = 0;
43cd72b9 5276 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
e0001a05
NC		 5277
5278 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5279 if (orig_insn.opcode == XTENSA_UNDEFINED)
5280 {
43cd72b9
BW		 5281 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5282 if (fmt == XTENSA_UNDEFINED)
5283 {
5284 as_bad (_("unknown opcode or format name '%s'"), opname);
5285 error_reset_cur_vinsn ();
5286 return;
5287 }
5288 if (!cur_vinsn.inside_bundle)
5289 {
5290 as_bad (_("format names only valid inside bundles"));
5291 error_reset_cur_vinsn ();
5292 return;
5293 }
5294 if (cur_vinsn.format != XTENSA_UNDEFINED)
5295 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5296 opname);
5297 cur_vinsn.format = fmt;
5298 free (has_underbar ? opname - 1 : opname);
5299 error_reset_cur_vinsn ();
e0001a05
NC		 5300 return;
5301 }
5302
e0001a05
NC		 5303 /* Special case: The call instructions should be marked "specific opcode"
5304 to keep them from expanding. */
5305 if (!use_longcalls () && is_direct_call_opcode (orig_insn.opcode))
5306 orig_insn.is_specific_opcode = TRUE;
5307
5308 /* Parse the arguments. */
5309 if (parse_arguments (&orig_insn, num_args, arg_strings))
5310 {
5311 as_bad (_("syntax error"));
43cd72b9 5312 error_reset_cur_vinsn ();
e0001a05
NC		 5313 return;
5314 }
5315
5316 /* Free the opcode and argument strings, now that they've been parsed. */
5317 free (has_underbar ? opname - 1 : opname);
5318 opname = 0;
5319 while (num_args-- > 0)
5320 free (arg_strings[num_args]);
5321
43cd72b9
BW		 5322 /* Get expressions for invisible operands. */
5323 if (get_invisible_operands (&orig_insn))
5324 {
5325 error_reset_cur_vinsn ();
5326 return;
5327 }
5328
e0001a05
NC		 5329 /* Check for the right number and type of arguments. */
5330 if (tinsn_check_arguments (&orig_insn))
e0001a05 5331 {
43cd72b9
BW		 5332 error_reset_cur_vinsn ();
5333 return;
e0001a05
NC		 5334 }
5335
43cd72b9
BW		 5336 dwarf2_where (&orig_insn.loc);
5337
5338 xg_add_branch_and_loop_targets (&orig_insn);
5339
61846f28 5340 /* Special-case for "entry" instruction. */
b08b5071 5341 if (orig_insn.opcode == xtensa_entry_opcode)
e0001a05 5342 {
43cd72b9
BW		 5343 /* Check that the third opcode (#2) is >= 16. */
5344 if (orig_insn.ntok >= 3)
e0001a05 5345 {
43cd72b9 5346 expressionS *exp = &orig_insn.tok[2];
e0001a05
NC		 5347 switch (exp->X_op)
5348 {
5349 case O_constant:
5350 if (exp->X_add_number < 16)
5351 as_warn (_("entry instruction with stack decrement < 16"));
5352 break;
5353
5354 default:
5355 as_warn (_("entry instruction with non-constant decrement"));
5356 }
5357 }
e0001a05
NC		 5358 }
5359
e0001a05 5360 /* Finish it off:
43cd72b9
BW		 5361 assemble_tokens (opcode, tok, ntok);
5362 expand the tokens from the orig_insn into the
5363 stack of instructions that will not expand
e0001a05 5364 unless required at relaxation time. */
e0001a05 5365
43cd72b9
BW		 5366 if (!cur_vinsn.inside_bundle)
5367 emit_single_op (&orig_insn);
5368 else /* We are inside a bundle. */
e0001a05 5369 {
43cd72b9
BW		 5370 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5371 cur_vinsn.num_slots++;
5372 if (*input_line_pointer == '}'
5373 || *(input_line_pointer - 1) == '}'
5374 || *(input_line_pointer - 2) == '}')
5375 finish_vinsn (&cur_vinsn);
e0001a05
NC		 5376 }
5377
43cd72b9
BW		 5378 /* We've just emitted a new instruction so clear the list of labels. */
5379 xtensa_clear_insn_labels ();
e0001a05
NC		 5380}
5381
5382
43cd72b9 5383/* HANDLE_ALIGN hook */
e0001a05 5384
43cd72b9
BW		 5385/* For a .align directive, we mark the previous block with the alignment
5386 information. This will be placed in the object file in the
5387 property section corresponding to this section. */
e0001a05 5388
43cd72b9 5389void
7fa3d080 5390xtensa_handle_align (fragS *fragP)
43cd72b9
BW		 5391{
5392 if (linkrelax
b08b5071 5393 && ! fragP->tc_frag_data.is_literal
43cd72b9
BW		 5394 && (fragP->fr_type == rs_align
5395 || fragP->fr_type == rs_align_code)
5396 && fragP->fr_address + fragP->fr_fix > 0
5397 && fragP->fr_offset > 0
5398 && now_seg != bss_section)
e0001a05 5399 {
43cd72b9
BW		 5400 fragP->tc_frag_data.is_align = TRUE;
5401 fragP->tc_frag_data.alignment = fragP->fr_offset;
e0001a05
NC		 5402 }
5403
43cd72b9 5404 if (fragP->fr_type == rs_align_test)
e0001a05 5405 {
43cd72b9
BW		 5406 int count;
5407 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5408 if (count != 0)
5409 as_bad_where (fragP->fr_file, fragP->fr_line,
5410 _("unaligned entry instruction"));
e0001a05 5411 }
e0001a05 5412}
43cd72b9 5413
e0001a05
NC		 5414
5415/* TC_FRAG_INIT hook */
5416
5417void
7fa3d080 5418xtensa_frag_init (fragS *frag)
e0001a05 5419{
43cd72b9 5420 xtensa_set_frag_assembly_state (frag);
e0001a05
NC		 5421}
5422
5423
5424symbolS *
7fa3d080 5425md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
e0001a05
NC		 5426{
5427 return NULL;
5428}
5429
5430
5431/* Round up a section size to the appropriate boundary. */
5432
5433valueT
7fa3d080 5434md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
e0001a05
NC		 5435{
5436 return size; /* Byte alignment is fine. */
5437}
5438
5439
5440long
7fa3d080 5441md_pcrel_from (fixS *fixP)
e0001a05
NC		 5442{
5443 char *insn_p;
5444 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 5445 static xtensa_insnbuf slotbuf = NULL;
e0001a05 5446 int opnum;
43cd72b9 5447 uint32 opnd_value;
e0001a05 5448 xtensa_opcode opcode;
43cd72b9
BW		 5449 xtensa_format fmt;
5450 int slot;
e0001a05
NC		 5451 xtensa_isa isa = xtensa_default_isa;
5452 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
43cd72b9 5453 bfd_boolean alt_reloc;
e0001a05
NC		 5454
5455 if (fixP->fx_done)
5456 return addr;
5457
5458 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5459 return addr;
5460
5461 if (!insnbuf)
43cd72b9
BW		 5462 {
5463 insnbuf = xtensa_insnbuf_alloc (isa);
5464 slotbuf = xtensa_insnbuf_alloc (isa);
5465 }
e0001a05
NC		 5466
5467 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
43cd72b9
BW		 5468 xtensa_insnbuf_from_chars (isa, insnbuf, insn_p, 0);
5469 fmt = xtensa_format_decode (isa, insnbuf);
5470
5471 if (fmt == XTENSA_UNDEFINED)
5472 as_fatal (_("bad instruction format"));
5473
5474 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5475 as_fatal (_("invalid relocation"));
5476
5477 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5478 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5479
5480 /* Check for "alternate" relocation (operand not specified). */
5481 if (alt_reloc || opcode == xtensa_const16_opcode)
5482 {
5483 if (opcode != xtensa_l32r_opcode
5484 && opcode != xtensa_const16_opcode)
5485 as_fatal (_("invalid relocation for '%s' instruction"),
5486 xtensa_opcode_name (isa, opcode));
e0001a05
NC		 5487 return addr;
5488 }
5489
43cd72b9
BW		 5490 opnum = get_relaxable_immed (opcode);
5491 opnd_value = 0;
5492 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5493 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
e0001a05
NC		 5494 {
5495 as_bad_where (fixP->fx_file,
5496 fixP->fx_line,
5497 _("invalid relocation for operand %d of '%s'"),
5498 opnum, xtensa_opcode_name (isa, opcode));
5499 return addr;
5500 }
43cd72b9
BW		 5501 return 0 - opnd_value;
5502}
5503
5504
5505/* TC_FORCE_RELOCATION hook */
5506
5507int
7fa3d080 5508xtensa_force_relocation (fixS *fix)
43cd72b9
BW		 5509{
5510 switch (fix->fx_r_type)
5511 {
5512 case BFD_RELOC_XTENSA_SLOT0_ALT:
5513 case BFD_RELOC_XTENSA_SLOT1_ALT:
5514 case BFD_RELOC_XTENSA_SLOT2_ALT:
5515 case BFD_RELOC_XTENSA_SLOT3_ALT:
5516 case BFD_RELOC_XTENSA_SLOT4_ALT:
5517 case BFD_RELOC_XTENSA_SLOT5_ALT:
5518 case BFD_RELOC_XTENSA_SLOT6_ALT:
5519 case BFD_RELOC_XTENSA_SLOT7_ALT:
5520 case BFD_RELOC_XTENSA_SLOT8_ALT:
5521 case BFD_RELOC_XTENSA_SLOT9_ALT:
5522 case BFD_RELOC_XTENSA_SLOT10_ALT:
5523 case BFD_RELOC_XTENSA_SLOT11_ALT:
5524 case BFD_RELOC_XTENSA_SLOT12_ALT:
5525 case BFD_RELOC_XTENSA_SLOT13_ALT:
5526 case BFD_RELOC_XTENSA_SLOT14_ALT:
5527 case BFD_RELOC_VTABLE_INHERIT:
5528 case BFD_RELOC_VTABLE_ENTRY:
5529 return 1;
5530 default:
5531 break;
e0001a05
NC		 5532 }
5533
43cd72b9
BW		 5534 if (linkrelax && fix->fx_addsy
5535 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5536 return 1;
5537
5538 return generic_force_reloc (fix);
5539}
5540
5541
5542/* NO_PSEUDO_DOT hook */
5543
5544/* This function has nothing to do with pseudo dots, but this is the
5545 nearest macro to where the check needs to take place. FIXME: This
5546 seems wrong. */
5547
5548bfd_boolean
7fa3d080 5549xtensa_check_inside_bundle (void)
43cd72b9
BW		 5550{
5551 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5552 as_bad (_("directives are not valid inside bundles"));
5553
5554 /* This function must always return FALSE because it is called via a
5555 macro that has nothing to do with bundling. */
5556 return FALSE;
e0001a05
NC		 5557}
5558
5559
43cd72b9 5560/* md_elf_section_change_hook */
e0001a05
NC		 5561
5562void
7fa3d080 5563xtensa_elf_section_change_hook (void)
e0001a05 5564{
43cd72b9
BW		 5565 /* Set up the assembly state. */
5566 if (!frag_now->tc_frag_data.is_assembly_state_set)
5567 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5568}
5569
5570
5571/* tc_fix_adjustable hook */
5572
5573bfd_boolean
7fa3d080 5574xtensa_fix_adjustable (fixS *fixP)
e0001a05 5575{
43cd72b9
BW		 5576 /* An offset is not allowed in combination with the difference of two
5577 symbols, but that cannot be easily detected after a local symbol
5578 has been adjusted to a (section+offset) form. Return 0 so that such
5579 an fix will not be adjusted. */
5580 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
5581 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
5582 return 0;
5583
e0001a05
NC		 5584 /* We need the symbol name for the VTABLE entries. */
5585 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5586 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5587 return 0;
5588
43cd72b9
BW		 5589 if (fixP->fx_addsy
5590 && (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
5591 return 0;
5592
e0001a05
NC		 5593 return 1;
5594}
5595
5596
5597void
7fa3d080 5598md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
e0001a05
NC		 5599{
5600 if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
5601 {
e0001a05 5602 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
e0001a05
NC		 5603
5604 switch (fixP->fx_r_type)
5605 {
5606 case BFD_RELOC_XTENSA_ASM_EXPAND:
5607 fixP->fx_done = 1;
5608 break;
5609
5610 case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
5611 as_bad (_("unhandled local relocation fix %s"),
5612 bfd_get_reloc_code_name (fixP->fx_r_type));
5613 break;
5614
5615 case BFD_RELOC_32:
5616 case BFD_RELOC_16:
5617 case BFD_RELOC_8:
5618 /* The only one we support that isn't an instruction field. */
5619 md_number_to_chars (fixpos, *valP, fixP->fx_size);
5620 fixP->fx_done = 1;
5621 break;
5622
e0001a05
NC		 5623 case BFD_RELOC_VTABLE_INHERIT:
5624 case BFD_RELOC_VTABLE_ENTRY:
5625 fixP->fx_done = 0;
5626 break;
5627
5628 default:
5629 as_bad (_("unhandled local relocation fix %s"),
5630 bfd_get_reloc_code_name (fixP->fx_r_type));
5631 }
5632 }
5633}
5634
5635
5636char *
7fa3d080 5637md_atof (int type, char *litP, int *sizeP)
e0001a05
NC		 5638{
5639 int prec;
5640 LITTLENUM_TYPE words[4];
5641 char *t;
5642 int i;
5643
5644 switch (type)
5645 {
5646 case 'f':
5647 prec = 2;
5648 break;
5649
5650 case 'd':
5651 prec = 4;
5652 break;
5653
5654 default:
5655 *sizeP = 0;
5656 return "bad call to md_atof";
5657 }
5658
5659 t = atof_ieee (input_line_pointer, type, words);
5660 if (t)
5661 input_line_pointer = t;
5662
5663 *sizeP = prec * 2;
5664
5665 for (i = prec - 1; i >= 0; i--)
5666 {
5667 int idx = i;
5668 if (target_big_endian)
5669 idx = (prec - 1 - i);
5670
5671 md_number_to_chars (litP, (valueT) words[idx], 2);
5672 litP += 2;
5673 }
5674
5675 return NULL;
5676}
5677
5678
5679int
7fa3d080 5680md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
e0001a05 5681{
34e41783 5682 return total_frag_text_expansion (fragP);
e0001a05
NC		 5683}
5684
5685
5686/* Translate internal representation of relocation info to BFD target
5687 format. */
5688
5689arelent *
7fa3d080 5690tc_gen_reloc (asection *section, fixS *fixp)
e0001a05
NC		 5691{
5692 arelent *reloc;
43cd72b9 5693 bfd_boolean apply_tentative_value = FALSE;
e0001a05
NC		 5694
5695 reloc = (arelent *) xmalloc (sizeof (arelent));
5696 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5697 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5698 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5699
5700 /* Make sure none of our internal relocations make it this far.
5701 They'd better have been fully resolved by this point. */
5702 assert ((int) fixp->fx_r_type > 0);
5703
43cd72b9
BW		 5704 if (linkrelax && fixp->fx_subsy
5705 && (fixp->fx_r_type == BFD_RELOC_8
5706 || fixp->fx_r_type == BFD_RELOC_16
5707 || fixp->fx_r_type == BFD_RELOC_32))
5708 {
5709 int diff_size = 0;
5710 bfd_vma diff_value, diff_mask = 0;
5711
5712 switch (fixp->fx_r_type)
5713 {
5714 case BFD_RELOC_8:
5715 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5716 diff_size = 1;
5717 diff_mask = 0xff;
5718 break;
5719 case BFD_RELOC_16:
5720 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5721 diff_size = 2;
5722 diff_mask = 0xffff;
5723 break;
5724 case BFD_RELOC_32:
5725 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5726 diff_size = 4;
5727 diff_mask = 0xffffffff;
5728 break;
5729 default:
5730 break;
5731 }
5732
5733 /* An offset is only allowed when it results from adjusting a local
5734 symbol into a section-relative offset. If the offset came from the
5735 original expression, tc_fix_adjustable will have prevented the fix
5736 from being converted to a section-relative form so that we can flag
5737 the error here. */
5738 if (fixp->fx_offset != 0 && !symbol_section_p (fixp->fx_addsy))
5739 {
5740 as_bad_where (fixp->fx_file, fixp->fx_line,
5741 _("cannot represent subtraction with an offset"));
5742 free (reloc->sym_ptr_ptr);
5743 free (reloc);
5744 return NULL;
5745 }
5746
5747 assert (S_GET_SEGMENT (fixp->fx_addsy)
5748 == S_GET_SEGMENT (fixp->fx_subsy));
5749
5750 diff_value = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
5751 - S_GET_VALUE (fixp->fx_subsy));
5752
5753 /* Check for overflow. */
5754 if ((diff_value & ~diff_mask) != 0)
5755 {
5756 as_bad_where (fixp->fx_file, fixp->fx_line,
5757 _("value of %ld too large"), diff_value);
5758 free (reloc->sym_ptr_ptr);
5759 free (reloc);
5760 return NULL;
5761 }
5762
5763 md_number_to_chars (fixp->fx_frag->fr_literal + fixp->fx_where,
5764 diff_value, diff_size);
5765 reloc->addend = fixp->fx_offset - diff_value;
5766 }
5767 else
5768 {
5769 reloc->addend = fixp->fx_offset;
5770
5771 switch (fixp->fx_r_type)
5772 {
5773 case BFD_RELOC_XTENSA_SLOT0_OP:
5774 case BFD_RELOC_XTENSA_SLOT1_OP:
5775 case BFD_RELOC_XTENSA_SLOT2_OP:
5776 case BFD_RELOC_XTENSA_SLOT3_OP:
5777 case BFD_RELOC_XTENSA_SLOT4_OP:
5778 case BFD_RELOC_XTENSA_SLOT5_OP:
5779 case BFD_RELOC_XTENSA_SLOT6_OP:
5780 case BFD_RELOC_XTENSA_SLOT7_OP:
5781 case BFD_RELOC_XTENSA_SLOT8_OP:
5782 case BFD_RELOC_XTENSA_SLOT9_OP:
5783 case BFD_RELOC_XTENSA_SLOT10_OP:
5784 case BFD_RELOC_XTENSA_SLOT11_OP:
5785 case BFD_RELOC_XTENSA_SLOT12_OP:
5786 case BFD_RELOC_XTENSA_SLOT13_OP:
5787 case BFD_RELOC_XTENSA_SLOT14_OP:
5788 /* As a special case, the immediate value for a CONST16 opcode
5789 should not be applied, since this kind of relocation is
5790 handled specially for CONST16 and is not really PC-relative.
5791 Rather than decode the opcode here, just wait and handle it
5792 in xg_apply_tentative_value. */
5793 apply_tentative_value = TRUE;
5794 break;
5795
5796 case BFD_RELOC_XTENSA_SLOT0_ALT:
5797 case BFD_RELOC_XTENSA_SLOT1_ALT:
5798 case BFD_RELOC_XTENSA_SLOT2_ALT:
5799 case BFD_RELOC_XTENSA_SLOT3_ALT:
5800 case BFD_RELOC_XTENSA_SLOT4_ALT:
5801 case BFD_RELOC_XTENSA_SLOT5_ALT:
5802 case BFD_RELOC_XTENSA_SLOT6_ALT:
5803 case BFD_RELOC_XTENSA_SLOT7_ALT:
5804 case BFD_RELOC_XTENSA_SLOT8_ALT:
5805 case BFD_RELOC_XTENSA_SLOT9_ALT:
5806 case BFD_RELOC_XTENSA_SLOT10_ALT:
5807 case BFD_RELOC_XTENSA_SLOT11_ALT:
5808 case BFD_RELOC_XTENSA_SLOT12_ALT:
5809 case BFD_RELOC_XTENSA_SLOT13_ALT:
5810 case BFD_RELOC_XTENSA_SLOT14_ALT:
5811 case BFD_RELOC_XTENSA_ASM_EXPAND:
5812 case BFD_RELOC_32:
5813 case BFD_RELOC_XTENSA_PLT:
5814 case BFD_RELOC_VTABLE_INHERIT:
5815 case BFD_RELOC_VTABLE_ENTRY:
5816 break;
5817
5818 case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
5819 as_warn (_("emitting simplification relocation"));
5820 break;
5821
5822 default:
5823 as_warn (_("emitting unknown relocation"));
5824 }
5825 }
5826
e0001a05
NC		 5827 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5828 if (reloc->howto == NULL)
5829 {
5830 as_bad_where (fixp->fx_file, fixp->fx_line,
5831 _("cannot represent `%s' relocation in object file"),
5832 bfd_get_reloc_code_name (fixp->fx_r_type));
43cd72b9
BW		 5833 free (reloc->sym_ptr_ptr);
5834 free (reloc);
e0001a05
NC		 5835 return NULL;
5836 }
5837
5838 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
43cd72b9
BW		 5839 as_fatal (_("internal error? cannot generate `%s' relocation"),
5840 bfd_get_reloc_code_name (fixp->fx_r_type));
e0001a05 5841
43cd72b9
BW		 5842 /* Write the tentative value of a PC-relative relocation to a local symbol
5843 into the instruction. The value will be ignored by the linker, and it
5844 makes the object file disassembly readable when the linkrelax flag is
5845 set and all branch targets are encoded in relocations. */
e0001a05 5846
43cd72b9 5847 if (linkrelax && apply_tentative_value && fixp->fx_pcrel)
e0001a05 5848 {
43cd72b9
BW		 5849 valueT val;
5850 assert (fixp->fx_addsy);
5851 if (S_GET_SEGMENT (fixp->fx_addsy) == section && !fixp->fx_plt
5852 && !S_FORCE_RELOC (fixp->fx_addsy, 1))
5853 {
5854 val = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
5855 - md_pcrel_from (fixp));
5856 xg_apply_tentative_value (fixp, val);
5857 }
e0001a05
NC		 5858 }
5859
5860 return reloc;
5861}
5862
7fa3d080
BW		 5863\f
5864/* Checks for resource conflicts between instructions. */
5865
5866/* The func unit stuff could be implemented as bit-vectors rather
5867 than the iterative approach here. If it ends up being too
5868 slow, we will switch it. */
5869
5870resource_table *
5871new_resource_table (void *data,
5872 int cycles,
5873 int nu,
5874 unit_num_copies_func uncf,
5875 opcode_num_units_func onuf,
5876 opcode_funcUnit_use_unit_func ouuf,
5877 opcode_funcUnit_use_stage_func ousf)
5878{
5879 int i;
5880 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
5881 rt->data = data;
5882 rt->cycles = cycles;
5883 rt->allocated_cycles = cycles;
5884 rt->num_units = nu;
5885 rt->unit_num_copies = uncf;
5886 rt->opcode_num_units = onuf;
5887 rt->opcode_unit_use = ouuf;
5888 rt->opcode_unit_stage = ousf;
5889
5890 rt->units = (char **) xcalloc (cycles, sizeof (char *));
5891 for (i = 0; i < cycles; i++)
5892 rt->units[i] = (char *) xcalloc (nu, sizeof (char));
5893
5894 return rt;
5895}
5896
5897
5898void
5899clear_resource_table (resource_table *rt)
5900{
5901 int i, j;
5902 for (i = 0; i < rt->allocated_cycles; i++)
5903 for (j = 0; j < rt->num_units; j++)
5904 rt->units[i][j] = 0;
5905}
5906
5907
5908/* We never shrink it, just fake it into thinking so. */
5909
5910void
5911resize_resource_table (resource_table *rt, int cycles)
5912{
5913 int i, old_cycles;
5914
5915 rt->cycles = cycles;
5916 if (cycles <= rt->allocated_cycles)
5917 return;
5918
5919 old_cycles = rt->allocated_cycles;
5920 rt->allocated_cycles = cycles;
5921
5922 rt->units = xrealloc (rt->units, sizeof (char *) * rt->allocated_cycles);
5923 for (i = 0; i < old_cycles; i++)
5924 rt->units[i] = xrealloc (rt->units[i], sizeof (char) * rt->num_units);
5925 for (i = old_cycles; i < cycles; i++)
5926 rt->units[i] = xcalloc (rt->num_units, sizeof (char));
5927}
5928
5929
5930bfd_boolean
5931resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
5932{
5933 int i;
5934 int uses = (rt->opcode_num_units) (rt->data, opcode);
5935
5936 for (i = 0; i < uses; i++)
5937 {
5938 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5939 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5940 int copies_in_use = rt->units[stage + cycle][unit];
5941 int copies = (rt->unit_num_copies) (rt->data, unit);
5942 if (copies_in_use >= copies)
5943 return FALSE;
5944 }
5945 return TRUE;
5946}
5947
5948
5949void
5950reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5951{
5952 int i;
5953 int uses = (rt->opcode_num_units) (rt->data, opcode);
5954
5955 for (i = 0; i < uses; i++)
5956 {
5957 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5958 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5959 /* Note that this allows resources to be oversubscribed. That's
5960 essential to the way the optional scheduler works.
5961 resources_available reports when a resource is over-subscribed,
5962 so it's easy to tell. */
5963 rt->units[stage + cycle][unit]++;
5964 }
5965}
5966
5967
5968void
5969release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5970{
5971 int i;
5972 int uses = (rt->opcode_num_units) (rt->data, opcode);
5973
5974 for (i = 0; i < uses; i++)
5975 {
5976 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5977 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5978 rt->units[stage + cycle][unit]--;
5979 assert (rt->units[stage + cycle][unit] >= 0);
5980 }
5981}
5982
5983
5984/* Wrapper functions make parameterized resource reservation
5985 more convenient. */
5986
5987int
5988opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
5989{
5990 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5991 return use->unit;
5992}
5993
5994
5995int
5996opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
5997{
5998 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5999 return use->stage;
6000}
6001
6002
6003/* Note that this function does not check issue constraints, but
6004 solely whether the hardware is available to execute the given
6005 instructions together. It also doesn't check if the tinsns
6006 write the same state, or access the same tieports. That is
a1ace8d8 6007 checked by check_t1_t2_reads_and_writes. */
7fa3d080
BW		 6008
6009static bfd_boolean
6010resources_conflict (vliw_insn *vinsn)
6011{
6012 int i;
6013 static resource_table *rt = NULL;
6014
6015 /* This is the most common case by far. Optimize it. */
6016 if (vinsn->num_slots == 1)
6017 return FALSE;
43cd72b9 6018
7fa3d080
BW		 6019 if (rt == NULL)
6020 {
6021 xtensa_isa isa = xtensa_default_isa;
6022 rt = new_resource_table
6023 (isa, xtensa_isa_num_pipe_stages (isa),
6024 xtensa_isa_num_funcUnits (isa),
6025 (unit_num_copies_func) xtensa_funcUnit_num_copies,
6026 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6027 opcode_funcUnit_use_unit,
6028 opcode_funcUnit_use_stage);
6029 }
43cd72b9 6030
7fa3d080 6031 clear_resource_table (rt);
43cd72b9 6032
7fa3d080
BW		 6033 for (i = 0; i < vinsn->num_slots; i++)
6034 {
6035 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6036 return TRUE;
6037 reserve_resources (rt, vinsn->slots[i].opcode, 0);
6038 }
e0001a05 6039
7fa3d080
BW		 6040 return FALSE;
6041}
e0001a05 6042
7fa3d080
BW		 6043\f
6044/* finish_vinsn, emit_single_op and helper functions. */
e0001a05 6045
7fa3d080
BW		 6046static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6047static xtensa_format xg_find_narrowest_format (vliw_insn *);
6048static void bundle_single_op (TInsn *);
6049static void xg_assemble_vliw_tokens (vliw_insn *);
e0001a05
NC		 6050
6051
43cd72b9
BW		 6052/* We have reached the end of a bundle; emit into the frag. */
6053
e0001a05 6054static void
7fa3d080 6055finish_vinsn (vliw_insn *vinsn)
e0001a05 6056{
43cd72b9
BW		 6057 IStack slotstack;
6058 int i;
6059 char *file_name;
6060 int line;
e0001a05 6061
43cd72b9 6062 if (find_vinsn_conflicts (vinsn))
a1ace8d8
BW		 6063 {
6064 xg_clear_vinsn (vinsn);
6065 return;
6066 }
43cd72b9
BW		 6067
6068 /* First, find a format that works. */
6069 if (vinsn->format == XTENSA_UNDEFINED)
6070 vinsn->format = xg_find_narrowest_format (vinsn);
6071
6072 if (vinsn->format == XTENSA_UNDEFINED)
6073 {
6074 as_where (&file_name, &line);
6075 as_bad_where (file_name, line,
6076 _("couldn't find a valid instruction format"));
6077 fprintf (stderr, _(" ops were: "));
6078 for (i = 0; i < vinsn->num_slots; i++)
6079 fprintf (stderr, _(" %s;"),
6080 xtensa_opcode_name (xtensa_default_isa,
6081 vinsn->slots[i].opcode));
6082 fprintf (stderr, _("\n"));
6083 xg_clear_vinsn (vinsn);
6084 return;
6085 }
6086
6087 if (vinsn->num_slots
6088 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
e0001a05 6089 {
43cd72b9
BW		 6090 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6091 xtensa_format_name (xtensa_default_isa, vinsn->format),
6092 xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6093 vinsn->num_slots);
6094 xg_clear_vinsn (vinsn);
6095 return;
6096 }
e0001a05 6097
43cd72b9
BW		 6098 if (resources_conflict (vinsn))
6099 {
6100 as_where (&file_name, &line);
6101 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6102 fprintf (stderr, " ops were: ");
6103 for (i = 0; i < vinsn->num_slots; i++)
6104 fprintf (stderr, " %s;",
6105 xtensa_opcode_name (xtensa_default_isa,
6106 vinsn->slots[i].opcode));
6107 fprintf (stderr, "\n");
6108 xg_clear_vinsn (vinsn);
6109 return;
6110 }
6111
6112 for (i = 0; i < vinsn->num_slots; i++)
6113 {
6114 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
e0001a05 6115 {
43cd72b9
BW		 6116 symbolS *lit_sym = NULL;
6117 int j;
6118 bfd_boolean e = FALSE;
6119 bfd_boolean saved_density = density_supported;
6120
6121 /* We don't want to narrow ops inside multi-slot bundles. */
6122 if (vinsn->num_slots > 1)
6123 density_supported = FALSE;
6124
6125 istack_init (&slotstack);
6126 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
e0001a05 6127 {
43cd72b9
BW		 6128 vinsn->slots[i].opcode =
6129 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6130 vinsn->format, i);
6131 vinsn->slots[i].ntok = 0;
6132 }
e0001a05 6133
43cd72b9
BW		 6134 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6135 {
6136 e = TRUE;
6137 continue;
e0001a05 6138 }
e0001a05 6139
43cd72b9 6140 density_supported = saved_density;
e0001a05 6141
43cd72b9
BW		 6142 if (e)
6143 {
6144 xg_clear_vinsn (vinsn);
6145 return;
6146 }
e0001a05 6147
43cd72b9
BW		 6148 for (j = 0; j < slotstack.ninsn - 1; j++)
6149 {
6150 TInsn *insn = &slotstack.insn[j];
6151 if (insn->insn_type == ITYPE_LITERAL)
6152 {
6153 assert (lit_sym == NULL);
6154 lit_sym = xg_assemble_literal (insn);
6155 }
6156 else
6157 {
6158 if (lit_sym)
6159 xg_resolve_literals (insn, lit_sym);
6160 emit_single_op (insn);
6161 }
6162 }
6163
6164 if (vinsn->num_slots > 1)
6165 {
6166 if (opcode_fits_format_slot
6167 (slotstack.insn[slotstack.ninsn - 1].opcode,
6168 vinsn->format, i))
6169 {
6170 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6171 }
6172 else
6173 {
6174 bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6175 if (vinsn->format == XTENSA_UNDEFINED)
6176 vinsn->slots[i].opcode = xtensa_nop_opcode;
6177 else
6178 vinsn->slots[i].opcode
6179 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6180 vinsn->format, i);
6181
6182 vinsn->slots[i].ntok = 0;
6183 }
6184 }
6185 else
6186 {
6187 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6188 vinsn->format = XTENSA_UNDEFINED;
6189 }
6190 }
6191 }
6192
6193 /* Now check resource conflicts on the modified bundle. */
6194 if (resources_conflict (vinsn))
6195 {
6196 as_where (&file_name, &line);
6197 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6198 fprintf (stderr, " ops were: ");
6199 for (i = 0; i < vinsn->num_slots; i++)
6200 fprintf (stderr, " %s;",
6201 xtensa_opcode_name (xtensa_default_isa,
6202 vinsn->slots[i].opcode));
6203 fprintf (stderr, "\n");
6204 xg_clear_vinsn (vinsn);
6205 return;
6206 }
6207
6208 /* First, find a format that works. */
6209 if (vinsn->format == XTENSA_UNDEFINED)
6210 vinsn->format = xg_find_narrowest_format (vinsn);
6211
6212 xg_assemble_vliw_tokens (vinsn);
6213
6214 xg_clear_vinsn (vinsn);
6215}
6216
6217
6218/* Given an vliw instruction, what conflicts are there in register
6219 usage and in writes to states and queues?
6220
6221 This function does two things:
6222 1. Reports an error when a vinsn contains illegal combinations
6223 of writes to registers states or queues.
6224 2. Marks individual tinsns as not relaxable if the combination
6225 contains antidependencies.
6226
6227 Job 2 handles things like swap semantics in instructions that need
6228 to be relaxed. For example,
6229
6230 addi a0, a1, 100000
6231
6232 normally would be relaxed to
6233
6234 l32r a0, some_label
6235 add a0, a1, a0
6236
6237 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6238
6239 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6240
6241 then we can't relax it into
6242
6243 l32r a0, some_label
6244 { add a0, a1, a0 ; add a2, a0, a4 ; }
6245
6246 because the value of a0 is trashed before the second add can read it. */
6247
7fa3d080
BW		 6248static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6249
43cd72b9 6250static bfd_boolean
7fa3d080 6251find_vinsn_conflicts (vliw_insn *vinsn)
43cd72b9
BW		 6252{
6253 int i, j;
6254 int branches = 0;
6255 xtensa_isa isa = xtensa_default_isa;
6256
6257 assert (!past_xtensa_end);
6258
6259 for (i = 0 ; i < vinsn->num_slots; i++)
6260 {
6261 TInsn *op1 = &vinsn->slots[i];
6262 if (op1->is_specific_opcode)
6263 op1->keep_wide = TRUE;
6264 else
6265 op1->keep_wide = FALSE;
6266 }
6267
6268 for (i = 0 ; i < vinsn->num_slots; i++)
6269 {
6270 TInsn *op1 = &vinsn->slots[i];
6271
6272 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6273 branches++;
6274
6275 for (j = 0; j < vinsn->num_slots; j++)
6276 {
6277 if (i != j)
6278 {
6279 TInsn *op2 = &vinsn->slots[j];
6280 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6281 switch (conflict_type)
6282 {
6283 case 'c':
6284 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6285 xtensa_opcode_name (isa, op1->opcode), i,
6286 xtensa_opcode_name (isa, op2->opcode), j);
6287 return TRUE;
6288 case 'd':
6289 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6290 xtensa_opcode_name (isa, op1->opcode), i,
6291 xtensa_opcode_name (isa, op2->opcode), j);
6292 return TRUE;
6293 case 'e':
6294 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6295 xtensa_opcode_name (isa, op1->opcode), i,
6296 xtensa_opcode_name (isa, op2->opcode), j);
6297 return TRUE;
6298 case 'f':
6299 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6300 xtensa_opcode_name (isa, op1->opcode), i,
6301 xtensa_opcode_name (isa, op2->opcode), j);
6302 return TRUE;
6303 default:
6304 /* Everything is OK. */
6305 break;
6306 }
6307 op2->is_specific_opcode = (op2->is_specific_opcode
6308 || conflict_type == 'a');
6309 }
6310 }
6311 }
6312
6313 if (branches > 1)
6314 {
6315 as_bad (_("multiple branches or jumps in the same bundle"));
6316 return TRUE;
6317 }
6318
6319 return FALSE;
6320}
6321
6322
a1ace8d8 6323/* Check how the state used by t1 and t2 relate.
43cd72b9
BW		 6324 Cases found are:
6325
6326 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6327 case B: no relationship between what is read and written (both could
6328 read the same reg though)
6329 case C: t1 writes a register t2 writes (a register conflict within a
6330 bundle)
6331 case D: t1 writes a state that t2 also writes
6332 case E: t1 writes a tie queue that t2 also writes
a1ace8d8 6333 case F: two volatile queue accesses
43cd72b9
BW		 6334*/
6335
6336static char
7fa3d080 6337check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
43cd72b9
BW		 6338{
6339 xtensa_isa isa = xtensa_default_isa;
6340 xtensa_regfile t1_regfile, t2_regfile;
6341 int t1_reg, t2_reg;
6342 int t1_base_reg, t1_last_reg;
6343 int t2_base_reg, t2_last_reg;
6344 char t1_inout, t2_inout;
6345 int i, j;
6346 char conflict = 'b';
6347 int t1_states;
6348 int t2_states;
6349 int t1_interfaces;
6350 int t2_interfaces;
6351 bfd_boolean t1_volatile = FALSE;
6352 bfd_boolean t2_volatile = FALSE;
6353
6354 /* Check registers. */
6355 for (j = 0; j < t2->ntok; j++)
6356 {
6357 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6358 continue;
6359
6360 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6361 t2_base_reg = t2->tok[j].X_add_number;
6362 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6363
6364 for (i = 0; i < t1->ntok; i++)
6365 {
6366 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6367 continue;
6368
6369 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6370
6371 if (t1_regfile != t2_regfile)
6372 continue;
6373
6374 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6375 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6376
6377 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6378 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6379 {
6380 if (t1_inout == 'm' || t1_inout == 'o'
6381 || t2_inout == 'm' || t2_inout == 'o')
6382 {
6383 conflict = 'a';
6384 continue;
6385 }
6386 }
6387
6388 t1_base_reg = t1->tok[i].X_add_number;
6389 t1_last_reg = (t1_base_reg
6390 + xtensa_operand_num_regs (isa, t1->opcode, i));
6391
6392 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6393 {
6394 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6395 {
6396 if (t1_reg != t2_reg)
6397 continue;
6398
6399 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
7fa3d080
BW		 6400 {
6401 conflict = 'a';
6402 continue;
6403 }
43cd72b9 6404
7fa3d080
BW		 6405 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6406 {
6407 conflict = 'a';
6408 continue;
6409 }
43cd72b9 6410
7fa3d080
BW		 6411 if (t1_inout != 'i' && t2_inout != 'i')
6412 return 'c';
6413 }
6414 }
6415 }
6416 }
43cd72b9 6417
7fa3d080
BW		 6418 /* Check states. */
6419 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6420 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6421 for (j = 0; j < t2_states; j++)
43cd72b9 6422 {
7fa3d080
BW		 6423 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6424 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6425 for (i = 0; i < t1_states; i++)
6426 {
6427 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6428 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6429 if (t1_so != t2_so)
6430 continue;
43cd72b9 6431
7fa3d080
BW		 6432 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6433 {
6434 conflict = 'a';
6435 continue;
6436 }
6437
6438 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6439 {
6440 conflict = 'a';
6441 continue;
6442 }
6443
6444 if (t1_inout != 'i' && t2_inout != 'i')
6445 return 'd';
6446 }
6447 }
43cd72b9 6448
7fa3d080
BW		 6449 /* Check tieports. */
6450 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6451 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6452 for (j = 0; j < t2_interfaces; j++)
43cd72b9 6453 {
7fa3d080
BW		 6454 xtensa_interface t2_int
6455 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
a1ace8d8
BW		 6456 int t2_class = xtensa_interface_class_id (isa, t2_int);
6457
7fa3d080 6458 t2_inout = xtensa_interface_inout (isa, j);
a1ace8d8 6459 if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
7fa3d080 6460 t2_volatile = TRUE;
a1ace8d8 6461
7fa3d080
BW		 6462 for (i = 0; i < t1_interfaces; i++)
6463 {
6464 xtensa_interface t1_int
6465 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
a1ace8d8
BW		 6466 int t1_class = xtensa_interface_class_id (isa, t2_int);
6467
7fa3d080 6468 t1_inout = xtensa_interface_inout (isa, i);
a1ace8d8 6469 if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
7fa3d080 6470 t1_volatile = TRUE;
a1ace8d8
BW		 6471
6472 if (t1_volatile && t2_volatile && (t1_class == t2_class))
6473 return 'f';
7fa3d080
BW		 6474
6475 if (t1_int != t2_int)
6476 continue;
6477
6478 if (t2_inout == 'i' && t1_inout == 'o')
6479 {
6480 conflict = 'a';
6481 continue;
6482 }
6483
6484 if (t1_inout == 'i' && t2_inout == 'o')
6485 {
6486 conflict = 'a';
6487 continue;
6488 }
6489
6490 if (t1_inout != 'i' && t2_inout != 'i')
6491 return 'e';
6492 }
43cd72b9 6493 }
7fa3d080
BW		 6494
6495 return conflict;
43cd72b9
BW		 6496}
6497
6498
6499static xtensa_format
7fa3d080 6500xg_find_narrowest_format (vliw_insn *vinsn)
43cd72b9
BW		 6501{
6502 /* Right now we assume that the ops within the vinsn are properly
6503 ordered for the slots that the programmer wanted them in. In
6504 other words, we don't rearrange the ops in hopes of finding a
6505 better format. The scheduler handles that. */
6506
6507 xtensa_isa isa = xtensa_default_isa;
6508 xtensa_format format;
6509 vliw_insn v_copy = *vinsn;
6510 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6511
6512 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6513 {
6514 v_copy = *vinsn;
6515 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6516 {
6517 int slot;
6518 int fit = 0;
6519 for (slot = 0; slot < v_copy.num_slots; slot++)
6520 {
6521 if (v_copy.slots[slot].opcode == nop_opcode)
6522 {
6523 v_copy.slots[slot].opcode =
6524 xtensa_format_slot_nop_opcode (isa, format, slot);
6525 v_copy.slots[slot].ntok = 0;
6526 }
6527
6528 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6529 format, slot))
6530 fit++;
7fa3d080 6531 else if (v_copy.num_slots > 1)
43cd72b9 6532 {
7fa3d080
BW		 6533 TInsn widened;
6534 /* Try the widened version. */
6535 if (!v_copy.slots[slot].keep_wide
6536 && !v_copy.slots[slot].is_specific_opcode
6537 && xg_is_narrow_insn (&v_copy.slots[slot])
6538 && !xg_expand_narrow (&widened, &v_copy.slots[slot])
6539 && opcode_fits_format_slot (widened.opcode,
6540 format, slot))
43cd72b9 6541 {
7fa3d080 6542 /* The xg_is_narrow clause requires some explanation:
43cd72b9 6543
7fa3d080
BW		 6544 addi can be "widened" to an addmi, which is then
6545 expanded to an addmi/addi pair if the immediate
6546 requires it, but here we must have a single widen
6547 only.
43cd72b9 6548
7fa3d080
BW		 6549 xg_is_narrow tells us that addi isn't really
6550 narrow. The widen_spec_list says that there are
6551 other cases. */
43cd72b9 6552
7fa3d080
BW		 6553 v_copy.slots[slot] = widened;
6554 fit++;
43cd72b9
BW		 6555 }
6556 }
6557 }
6558 if (fit == v_copy.num_slots)
6559 {
6560 *vinsn = v_copy;
6561 xtensa_format_encode (isa, format, vinsn->insnbuf);
6562 vinsn->format = format;
6563 break;
6564 }
6565 }
6566 }
6567
6568 if (format == xtensa_isa_num_formats (isa))
6569 return XTENSA_UNDEFINED;
6570
6571 return format;
6572}
6573
6574
6575/* Return the additional space needed in a frag
6576 for possible relaxations of any ops in a VLIW insn.
6577 Also fill out the relaxations that might be required of
6578 each tinsn in the vinsn. */
6579
6580static int
7fa3d080 6581relaxation_requirements (vliw_insn *vinsn)
43cd72b9
BW		 6582{
6583 int extra_space = 0;
6584 int slot;
6585
6586 for (slot = 0; slot < vinsn->num_slots; slot++)
6587 {
6588 TInsn *tinsn = &vinsn->slots[slot];
6589 if (!tinsn_has_symbolic_operands (tinsn))
6590 {
6591 /* A narrow instruction could be widened later to help
6592 alignment issues. */
6593 if (xg_is_narrow_insn (tinsn)
6594 && !tinsn->is_specific_opcode
6595 && vinsn->num_slots == 1)
6596 {
6597 /* Difference in bytes between narrow and wide insns... */
6598 extra_space += 1;
6599 tinsn->subtype = RELAX_NARROW;
6600 tinsn->record_fix = TRUE;
6601 break;
6602 }
6603 else
6604 {
6605 tinsn->record_fix = FALSE;
6606 /* No extra_space needed. */
6607 }
6608 }
6609 else
6610 {
b08b5071
BW		 6611 if (workaround_b_j_loop_end
6612 && tinsn->opcode == xtensa_jx_opcode
43cd72b9
BW		 6613 && use_transform ())
6614 {
6615 /* Add 2 of these. */
6616 extra_space += 3; /* for the nop size */
6617 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6618 }
6619
6620 /* Need to assemble it with space for the relocation. */
6621 if (xg_is_relaxable_insn (tinsn, 0)
6622 && !tinsn->is_specific_opcode)
6623 {
6624 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6625 int max_literal_size =
6626 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6627
6628 tinsn->literal_space = max_literal_size;
6629
6630 tinsn->subtype = RELAX_IMMED;
6631 tinsn->record_fix = FALSE;
6632 extra_space += max_size;
6633 }
6634 else
6635 {
6636 tinsn->record_fix = TRUE;
6637 /* No extra space needed. */
6638 }
6639 }
6640 }
6641 return extra_space;
6642}
6643
6644
6645static void
7fa3d080 6646bundle_single_op (TInsn *orig_insn)
43cd72b9
BW		 6647{
6648 xtensa_isa isa = xtensa_default_isa;
6649 vliw_insn v;
6650 int slot;
6651
6652 xg_init_vinsn (&v);
6653 v.format = op_placement_table[orig_insn->opcode].narrowest;
6654 assert (v.format != XTENSA_UNDEFINED);
6655 v.num_slots = xtensa_format_num_slots (isa, v.format);
6656
6657 for (slot = 0;
6658 !opcode_fits_format_slot (orig_insn->opcode, v.format, slot);
6659 slot++)
6660 {
6661 v.slots[slot].opcode =
6662 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6663 v.slots[slot].ntok = 0;
6664 v.slots[slot].insn_type = ITYPE_INSN;
6665 }
6666
6667 v.slots[slot] = *orig_insn;
6668 slot++;
6669
6670 for ( ; slot < v.num_slots; slot++)
6671 {
6672 v.slots[slot].opcode =
6673 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6674 v.slots[slot].ntok = 0;
6675 v.slots[slot].insn_type = ITYPE_INSN;
6676 }
6677
6678 finish_vinsn (&v);
6679 xg_free_vinsn (&v);
6680}
6681
6682
6683static bfd_boolean
7fa3d080 6684emit_single_op (TInsn *orig_insn)
43cd72b9
BW		 6685{
6686 int i;
6687 IStack istack; /* put instructions into here */
6688 symbolS *lit_sym = NULL;
6689 symbolS *label_sym = NULL;
6690
6691 istack_init (&istack);
6692
6693 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6694 Because the scheduling and bundling characteristics of movi and
6695 l32r or const16 are so different, we can do much better if we relax
6696 it prior to scheduling and bundling, rather than after. */
b08b5071
BW		 6697 if ((orig_insn->opcode == xtensa_movi_opcode
6698 || orig_insn->opcode == xtensa_movi_n_opcode)
6699 && !cur_vinsn.inside_bundle
43cd72b9
BW		 6700 && (orig_insn->tok[1].X_op == O_symbol
6701 || orig_insn->tok[1].X_op == O_pltrel))
6702 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6703 else
6704 if (xg_expand_assembly_insn (&istack, orig_insn))
6705 return TRUE;
6706
6707 for (i = 0; i < istack.ninsn; i++)
6708 {
6709 TInsn *insn = &istack.insn[i];
6710 switch (insn->insn_type)
6711 {
6712 case ITYPE_LITERAL:
6713 assert (lit_sym == NULL);
6714 lit_sym = xg_assemble_literal (insn);
6715 break;
6716 case ITYPE_LABEL:
6717 {
6718 static int relaxed_sym_idx = 0;
6719 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6720 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6721 colon (label);
6722 assert (label_sym == NULL);
6723 label_sym = symbol_find_or_make (label);
6724 assert (label_sym);
6725 free (label);
6726 }
6727 break;
6728 case ITYPE_INSN:
6729 if (lit_sym)
6730 xg_resolve_literals (insn, lit_sym);
6731 if (label_sym)
6732 xg_resolve_labels (insn, label_sym);
6733 bundle_single_op (insn);
6734 break;
6735 default:
6736 assert (0);
6737 break;
6738 }
6739 }
6740 return FALSE;
6741}
6742
6743
34e41783
BW		 6744static int
6745total_frag_text_expansion (fragS *fragP)
6746{
6747 int slot;
6748 int total_expansion = 0;
6749
6750 for (slot = 0; slot < MAX_SLOTS; slot++)
6751 total_expansion += fragP->tc_frag_data.text_expansion[slot];
6752
6753 return total_expansion;
6754}
6755
6756
43cd72b9
BW		 6757/* Emit a vliw instruction to the current fragment. */
6758
7fa3d080
BW		 6759static void
6760xg_assemble_vliw_tokens (vliw_insn *vinsn)
43cd72b9
BW		 6761{
6762 bfd_boolean finish_frag = FALSE;
6763 bfd_boolean is_jump = FALSE;
6764 bfd_boolean is_branch = FALSE;
6765 xtensa_isa isa = xtensa_default_isa;
6766 int i;
6767 int insn_size;
6768 int extra_space;
6769 char *f = NULL;
6770 int slot;
6771 struct dwarf2_line_info best_loc;
6772
6773 best_loc.line = INT_MAX;
6774
6775 if (generating_literals)
6776 {
6777 static int reported = 0;
6778 if (reported < 4)
6779 as_bad_where (frag_now->fr_file, frag_now->fr_line,
6780 _("cannot assemble into a literal fragment"));
6781 if (reported == 3)
6782 as_bad (_("..."));
6783 reported++;
6784 return;
6785 }
6786
6787 if (frag_now_fix () != 0
b08b5071 6788 && (! frag_now->tc_frag_data.is_insn
43cd72b9 6789 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
b08b5071 6790 || !use_transform () != frag_now->tc_frag_data.is_no_transform
43cd72b9
BW		 6791 || (directive_state[directive_absolute_literals]
6792 != frag_now->tc_frag_data.use_absolute_literals)))
6793 {
6794 frag_wane (frag_now);
6795 frag_new (0);
6796 xtensa_set_frag_assembly_state (frag_now);
6797 }
6798
6799 if (workaround_a0_b_retw
6800 && vinsn->num_slots == 1
6801 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6802 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6803 && use_transform ())
6804 {
6805 has_a0_b_retw = TRUE;
6806
6807 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6808 After the first assembly pass we will check all of them and
6809 add a nop if needed. */
6810 frag_now->tc_frag_data.is_insn = TRUE;
6811 frag_var (rs_machine_dependent, 4, 4,
6812 RELAX_ADD_NOP_IF_A0_B_RETW,
6813 frag_now->fr_symbol,
6814 frag_now->fr_offset,
6815 NULL);
6816 xtensa_set_frag_assembly_state (frag_now);
6817 frag_now->tc_frag_data.is_insn = TRUE;
6818 frag_var (rs_machine_dependent, 4, 4,
6819 RELAX_ADD_NOP_IF_A0_B_RETW,
6820 frag_now->fr_symbol,
6821 frag_now->fr_offset,
6822 NULL);
6823 xtensa_set_frag_assembly_state (frag_now);
6824 }
6825
6826 for (i = 0; i < vinsn->num_slots; i++)
6827 {
6828 /* See if the instruction implies an aligned section. */
6829 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
6830 record_alignment (now_seg, 2);
6831
6832 /* Also determine the best line number for debug info. */
6833 best_loc = vinsn->slots[i].loc.line < best_loc.line
6834 ? vinsn->slots[i].loc : best_loc;
6835 }
6836
6837 /* Special cases for instructions that force an alignment... */
6838 /* None of these opcodes are bundle-able. */
6839 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6840 {
6841 size_t max_fill;
6842
6843 xtensa_set_frag_assembly_state (frag_now);
6844 frag_now->tc_frag_data.is_insn = TRUE;
6845
6846 max_fill = get_text_align_max_fill_size
6847 (get_text_align_power (xtensa_fetch_width),
6848 TRUE, frag_now->tc_frag_data.is_no_density);
6849
6850 if (use_transform ())
6851 frag_var (rs_machine_dependent, max_fill, max_fill,
6852 RELAX_ALIGN_NEXT_OPCODE,
6853 frag_now->fr_symbol,
6854 frag_now->fr_offset,
6855 NULL);
6856 else
6857 frag_var (rs_machine_dependent, 0, 0,
6858 RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
6859 xtensa_set_frag_assembly_state (frag_now);
6860
6861 xtensa_move_labels (frag_now, 0, FALSE);
6862 }
6863
b08b5071 6864 if (vinsn->slots[0].opcode == xtensa_entry_opcode
43cd72b9
BW		 6865 && !vinsn->slots[0].is_specific_opcode)
6866 {
6867 xtensa_mark_literal_pool_location ();
6868 xtensa_move_labels (frag_now, 0, TRUE);
6869 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
6870 }
6871
6872 if (vinsn->num_slots == 1)
6873 {
6874 if (workaround_a0_b_retw && use_transform ())
6875 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
6876 is_register_writer (&vinsn->slots[0], "a", 0));
6877
6878 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
6879 is_bad_loopend_opcode (&vinsn->slots[0]));
6880 }
6881 else
6882 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
6883
6884 insn_size = xtensa_format_length (isa, vinsn->format);
6885
6886 extra_space = relaxation_requirements (vinsn);
6887
6888 /* vinsn_to_insnbuf will produce the error. */
6889 if (vinsn->format != XTENSA_UNDEFINED)
6890 {
6891 f = (char *) frag_more (insn_size + extra_space);
6892 xtensa_set_frag_assembly_state (frag_now);
6893 frag_now->tc_frag_data.is_insn = TRUE;
6894 }
6895
6896 vinsn_to_insnbuf (vinsn, f, frag_now, TRUE);
6897 if (vinsn->format == XTENSA_UNDEFINED)
6898 return;
6899
6900 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, f, 0);
6901
6902 xtensa_dwarf2_emit_insn (insn_size - extra_space, &best_loc);
6903
6904 for (slot = 0; slot < vinsn->num_slots; slot++)
6905 {
6906 TInsn *tinsn = &vinsn->slots[slot];
6907 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
6908 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
6909 frag_now->tc_frag_data.slot_sub_symbols[slot] = tinsn->sub_symbol;
6910 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
6911 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
6912 if (tinsn->literal_space != 0)
6913 xg_assemble_literal_space (tinsn->literal_space, slot);
6914
6915 if (tinsn->subtype == RELAX_NARROW)
6916 assert (vinsn->num_slots == 1);
6917 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
6918 is_jump = TRUE;
6919 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
6920 is_branch = TRUE;
6921
6922 if (tinsn->subtype || tinsn->symbol || tinsn->record_fix
6923 || tinsn->offset || tinsn->literal_frag || is_jump || is_branch)
6924 finish_frag = TRUE;
6925 }
6926
6927 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
b08b5071 6928 frag_now->tc_frag_data.is_specific_opcode = TRUE;
43cd72b9
BW		 6929
6930 if (finish_frag)
6931 {
6932 frag_variant (rs_machine_dependent,
6933 extra_space, extra_space, RELAX_SLOTS,
6934 frag_now->fr_symbol, frag_now->fr_offset, f);
6935 xtensa_set_frag_assembly_state (frag_now);
6936 }
6937
6938 /* Special cases for loops:
6939 close_loop_end should be inserted AFTER short_loop.
6940 Make sure that CLOSE loops are processed BEFORE short_loops
6941 when converting them. */
6942
6943 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6944 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
6945 && !vinsn->slots[0].is_specific_opcode)
6946 {
6947 if (workaround_short_loop && use_transform ())
6948 {
6949 maybe_has_short_loop = TRUE;
6950 frag_now->tc_frag_data.is_insn = TRUE;
6951 frag_var (rs_machine_dependent, 4, 4,
6952 RELAX_ADD_NOP_IF_SHORT_LOOP,
6953 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6954 frag_now->tc_frag_data.is_insn = TRUE;
6955 frag_var (rs_machine_dependent, 4, 4,
6956 RELAX_ADD_NOP_IF_SHORT_LOOP,
6957 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6958 }
6959
6960 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6961 loop at least 12 bytes away from another loop's end. */
6962 if (workaround_close_loop_end && use_transform ())
6963 {
6964 maybe_has_close_loop_end = TRUE;
6965 frag_now->tc_frag_data.is_insn = TRUE;
6966 frag_var (rs_machine_dependent, 12, 12,
6967 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
6968 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6969 }
6970 }
6971
6972 if (use_transform ())
6973 {
6974 if (is_jump)
6975 {
6976 assert (finish_frag);
6977 frag_var (rs_machine_dependent,
6978 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6979 RELAX_UNREACHABLE,
6980 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6981 xtensa_set_frag_assembly_state (frag_now);
6982 }
6983 else if (is_branch && align_targets)
6984 {
6985 assert (finish_frag);
6986 frag_var (rs_machine_dependent,
6987 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6988 RELAX_MAYBE_UNREACHABLE,
6989 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6990 xtensa_set_frag_assembly_state (frag_now);
6991 frag_var (rs_machine_dependent,
6992 0, 0,
6993 RELAX_MAYBE_DESIRE_ALIGN,
6994 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6995 xtensa_set_frag_assembly_state (frag_now);
6996 }
6997 }
6998
6999 /* Now, if the original opcode was a call... */
7000 if (do_align_targets ()
7001 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7002 {
b08b5071 7003 float freq = get_subseg_total_freq (now_seg, now_subseg);
43cd72b9
BW		 7004 frag_now->tc_frag_data.is_insn = TRUE;
7005 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7006 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7007 xtensa_set_frag_assembly_state (frag_now);
7008 }
7009
7010 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7011 {
7012 frag_wane (frag_now);
7013 frag_new (0);
7014 xtensa_set_frag_assembly_state (frag_now);
7015 }
7016}
7017
7018\f
7fa3d080
BW		 7019/* xtensa_end and helper functions. */
7020
7021static void xtensa_cleanup_align_frags (void);
7022static void xtensa_fix_target_frags (void);
7023static void xtensa_mark_narrow_branches (void);
7024static void xtensa_mark_zcl_first_insns (void);
7025static void xtensa_fix_a0_b_retw_frags (void);
7026static void xtensa_fix_b_j_loop_end_frags (void);
7027static void xtensa_fix_close_loop_end_frags (void);
7028static void xtensa_fix_short_loop_frags (void);
7029static void xtensa_sanity_check (void);
7030
43cd72b9 7031void
7fa3d080 7032xtensa_end (void)
43cd72b9
BW		 7033{
7034 directive_balance ();
7035 xtensa_flush_pending_output ();
7036
7037 past_xtensa_end = TRUE;
7038
7039 xtensa_move_literals ();
7040
7041 xtensa_reorder_segments ();
7042 xtensa_cleanup_align_frags ();
7043 xtensa_fix_target_frags ();
7044 if (workaround_a0_b_retw && has_a0_b_retw)
7045 xtensa_fix_a0_b_retw_frags ();
7046 if (workaround_b_j_loop_end)
7047 xtensa_fix_b_j_loop_end_frags ();
7048
7049 /* "close_loop_end" should be processed BEFORE "short_loop". */
7050 if (workaround_close_loop_end && maybe_has_close_loop_end)
7051 xtensa_fix_close_loop_end_frags ();
7052
7053 if (workaround_short_loop && maybe_has_short_loop)
7054 xtensa_fix_short_loop_frags ();
7055 xtensa_mark_narrow_branches ();
7056 xtensa_mark_zcl_first_insns ();
7057
7058 xtensa_sanity_check ();
7059}
7060
7061
7062static void
7fa3d080 7063xtensa_cleanup_align_frags (void)
43cd72b9
BW		 7064{
7065 frchainS *frchP;
7066
7067 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7068 {
7069 fragS *fragP;
7070 /* Walk over all of the fragments in a subsection. */
7071 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7072 {
7073 if ((fragP->fr_type == rs_align
7074 || fragP->fr_type == rs_align_code
7075 || (fragP->fr_type == rs_machine_dependent
7076 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7077 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7078 && fragP->fr_fix == 0)
7079 {
7080 fragS *next = fragP->fr_next;
7081
7082 while (next
7083 && next->fr_fix == 0
7084 && next->fr_type == rs_machine_dependent
7085 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7086 {
7087 frag_wane (next);
7088 next = next->fr_next;
7089 }
7090 }
7091 /* If we don't widen branch targets, then they
7092 will be easier to align. */
7093 if (fragP->tc_frag_data.is_branch_target
7094 && fragP->fr_opcode == fragP->fr_literal
7095 && fragP->fr_type == rs_machine_dependent
7096 && fragP->fr_subtype == RELAX_SLOTS
7097 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7098 frag_wane (fragP);
7099 if (fragP->fr_type == rs_machine_dependent
7100 && fragP->fr_subtype == RELAX_UNREACHABLE)
7101 fragP->tc_frag_data.is_unreachable = TRUE;
7102 }
7103 }
7104}
7105
7106
7107/* Re-process all of the fragments looking to convert all of the
7108 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7109 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7110 If the next fragment starts with a loop target, AND the previous
7111 fragment can be expanded to negate the branch, convert this to a
7112 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7113
7fa3d080
BW		 7114static bfd_boolean frag_can_negate_branch (fragS *);
7115
43cd72b9 7116static void
7fa3d080 7117xtensa_fix_target_frags (void)
e0001a05
NC		 7118{
7119 frchainS *frchP;
7120
7121 /* When this routine is called, all of the subsections are still intact
7122 so we walk over subsections instead of sections. */
7123 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7124 {
7125 bfd_boolean prev_frag_can_negate_branch = FALSE;
7126 fragS *fragP;
7127
7128 /* Walk over all of the fragments in a subsection. */
7129 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7130 {
7131 if (fragP->fr_type == rs_machine_dependent
7132 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7133 {
7134 if (next_frag_is_loop_target (fragP))
7135 {
7136 if (prev_frag_can_negate_branch)
43cd72b9
BW		 7137 {
7138 fragP->fr_subtype = RELAX_LOOP_END;
7139 /* See the comment near the frag_var with a
7140 RELAX_DESIRE_ALIGN to see why we do this. */
7141 fragP->fr_var = RELAX_LOOP_END_BYTES;
7142 }
e0001a05
NC		 7143 else
7144 {
43cd72b9 7145 if (next_frag_is_branch_target (fragP))
e0001a05
NC		 7146 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7147 else
7148 frag_wane (fragP);
7149 }
7150 }
43cd72b9 7151 else if (next_frag_is_branch_target (fragP))
e0001a05
NC		 7152 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7153 else
7154 frag_wane (fragP);
7155 }
7156 if (fragP->fr_fix != 0)
7157 prev_frag_can_negate_branch = FALSE;
7158 if (frag_can_negate_branch (fragP))
7159 prev_frag_can_negate_branch = TRUE;
7160 }
7161 }
7162}
7163
7164
7165static bfd_boolean
7fa3d080 7166frag_can_negate_branch (fragS *fragP)
e0001a05 7167{
43cd72b9
BW		 7168 xtensa_isa isa = xtensa_default_isa;
7169 vliw_insn vinsn;
7170 int slot;
7171
7172 if (fragP->fr_type != rs_machine_dependent
7173 || fragP->fr_subtype != RELAX_SLOTS)
7174 return FALSE;
7175
7176 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7177
7178 for (slot = 0; slot < xtensa_format_num_slots (isa, vinsn.format); slot++)
e0001a05 7179 {
43cd72b9
BW		 7180 if ((fragP->tc_frag_data.slot_subtypes[slot] == RELAX_IMMED)
7181 && xtensa_opcode_is_branch (isa, vinsn.slots[slot].opcode) == 1)
e0001a05
NC		 7182 return TRUE;
7183 }
43cd72b9
BW		 7184
7185 return FALSE;
7186}
7187
7188
7fa3d080
BW		 7189static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7190
43cd72b9 7191static void
7fa3d080 7192xtensa_mark_narrow_branches (void)
43cd72b9
BW		 7193{
7194 frchainS *frchP;
7195
7196 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7197 {
7198 fragS *fragP;
7199 /* Walk over all of the fragments in a subsection. */
7200 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7201 {
7202 if (fragP->fr_type == rs_machine_dependent
7203 && fragP->fr_subtype == RELAX_SLOTS
7204 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7205 {
7206 vliw_insn vinsn;
7207 const expressionS *expr;
7208 symbolS *symbolP;
7209
7210 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7211 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7212
7213 expr = &vinsn.slots[0].tok[1];
7214 symbolP = expr->X_add_symbol;
7215
7216 if (vinsn.num_slots == 1
7217 && xtensa_opcode_is_branch (xtensa_default_isa,
7218 vinsn.slots[0].opcode)
7219 && xg_get_single_size (vinsn.slots[0].opcode) == 2
7220 && is_narrow_branch_guaranteed_in_range (fragP,
7221 &vinsn.slots[0]))
7222 {
7223 fragP->fr_subtype = RELAX_SLOTS;
7224 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7225 }
7226 }
7227 }
7228 }
7229}
7230
7231
7232/* A branch is typically widened only when its target is out of
7233 range. However, we would like to widen them to align a subsequent
7234 branch target when possible.
7235
7236 Because the branch relaxation code is so convoluted, the optimal solution
7237 (combining the two cases) is difficult to get right in all circumstances.
7238 We therefore go with an "almost as good" solution, where we only
7239 use for alignment narrow branches that definitely will not expand to a
7240 jump and a branch. These functions find and mark these cases. */
7241
a67517f4
BW		 7242/* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7243 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7244 We start counting beginning with the frag after the 2-byte branch, so the
7245 maximum offset is (4 - 2) + 63 = 65. */
7246#define MAX_IMMED6 65
43cd72b9 7247
7fa3d080
BW		 7248static size_t unrelaxed_frag_max_size (fragS *);
7249
43cd72b9 7250static bfd_boolean
7fa3d080 7251is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
43cd72b9
BW		 7252{
7253 const expressionS *expr = &tinsn->tok[1];
7254 symbolS *symbolP = expr->X_add_symbol;
7255 fragS *target_frag = symbol_get_frag (symbolP);
7256 size_t max_distance = expr->X_add_number;
7257 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7258 if (is_branch_jmp_to_next (tinsn, fragP))
7259 return FALSE;
7260
7261 /* The branch doesn't branch over it's own frag,
7262 but over the subsequent ones. */
7263 fragP = fragP->fr_next;
7264 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7265 {
7266 max_distance += unrelaxed_frag_max_size (fragP);
7267 fragP = fragP->fr_next;
7268 }
7269 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7270 return TRUE;
e0001a05
NC		 7271 return FALSE;
7272}
7273
7274
43cd72b9 7275static void
7fa3d080 7276xtensa_mark_zcl_first_insns (void)
43cd72b9
BW		 7277{
7278 frchainS *frchP;
7279
7280 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7281 {
7282 fragS *fragP;
7283 /* Walk over all of the fragments in a subsection. */
7284 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7285 {
7286 if (fragP->fr_type == rs_machine_dependent
7287 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7288 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7289 {
7290 /* Find the loop frag. */
7291 fragS *targ_frag = next_non_empty_frag (fragP);
7292 /* Find the first insn frag. */
7293 targ_frag = next_non_empty_frag (targ_frag);
7294
7295 /* Of course, sometimes (mostly for toy test cases) a
7296 zero-cost loop instruction is the last in a section. */
7297 if (targ_frag)
7298 {
7299 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7300 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7301 frag_wane (fragP);
7302 }
7303 }
7304 }
7305 }
7306}
7307
7308
e0001a05
NC		 7309/* Re-process all of the fragments looking to convert all of the
7310 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7311 conditional branch or a retw/retw.n, convert this frag to one that
7312 will generate a NOP. In any case close it off with a .fill 0. */
7313
7fa3d080
BW		 7314static bfd_boolean next_instrs_are_b_retw (fragS *);
7315
e0001a05 7316static void
7fa3d080 7317xtensa_fix_a0_b_retw_frags (void)
e0001a05
NC		 7318{
7319 frchainS *frchP;
7320
7321 /* When this routine is called, all of the subsections are still intact
7322 so we walk over subsections instead of sections. */
7323 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7324 {
7325 fragS *fragP;
7326
7327 /* Walk over all of the fragments in a subsection. */
7328 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7329 {
7330 if (fragP->fr_type == rs_machine_dependent
7331 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7332 {
7333 if (next_instrs_are_b_retw (fragP))
43cd72b9 7334 {
b08b5071 7335 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7336 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7337 else
7338 relax_frag_add_nop (fragP);
7339 }
7340 frag_wane (fragP);
e0001a05
NC		 7341 }
7342 }
7343 }
7344}
7345
7346
7fa3d080
BW		 7347static bfd_boolean
7348next_instrs_are_b_retw (fragS *fragP)
e0001a05
NC		 7349{
7350 xtensa_opcode opcode;
43cd72b9 7351 xtensa_format fmt;
e0001a05
NC		 7352 const fragS *next_fragP = next_non_empty_frag (fragP);
7353 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 7354 static xtensa_insnbuf slotbuf = NULL;
e0001a05
NC		 7355 xtensa_isa isa = xtensa_default_isa;
7356 int offset = 0;
43cd72b9
BW		 7357 int slot;
7358 bfd_boolean branch_seen = FALSE;
e0001a05
NC		 7359
7360 if (!insnbuf)
43cd72b9
BW		 7361 {
7362 insnbuf = xtensa_insnbuf_alloc (isa);
7363 slotbuf = xtensa_insnbuf_alloc (isa);
7364 }
e0001a05
NC		 7365
7366 if (next_fragP == NULL)
7367 return FALSE;
7368
7369 /* Check for the conditional branch. */
43cd72b9
BW		 7370 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7371 fmt = xtensa_format_decode (isa, insnbuf);
7372 if (fmt == XTENSA_UNDEFINED)
7373 return FALSE;
7374
7375 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7376 {
7377 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7378 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7379
7380 branch_seen = (branch_seen
7381 || xtensa_opcode_is_branch (isa, opcode) == 1);
7382 }
e0001a05 7383
43cd72b9 7384 if (!branch_seen)
e0001a05
NC		 7385 return FALSE;
7386
43cd72b9 7387 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7388 if (offset == next_fragP->fr_fix)
7389 {
7390 next_fragP = next_non_empty_frag (next_fragP);
7391 offset = 0;
7392 }
43cd72b9 7393
e0001a05
NC		 7394 if (next_fragP == NULL)
7395 return FALSE;
7396
7397 /* Check for the retw/retw.n. */
43cd72b9
BW		 7398 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7399 fmt = xtensa_format_decode (isa, insnbuf);
7400
7401 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7402 have no problems. */
7403 if (fmt == XTENSA_UNDEFINED
7404 || xtensa_format_num_slots (isa, fmt) != 1)
7405 return FALSE;
7406
7407 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7408 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
e0001a05 7409
b08b5071 7410 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
e0001a05 7411 return TRUE;
43cd72b9 7412
e0001a05
NC		 7413 return FALSE;
7414}
7415
7416
7417/* Re-process all of the fragments looking to convert all of the
7418 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7419 loop end label, convert this frag to one that will generate a NOP.
7420 In any case close it off with a .fill 0. */
7421
7fa3d080
BW		 7422static bfd_boolean next_instr_is_loop_end (fragS *);
7423
e0001a05 7424static void
7fa3d080 7425xtensa_fix_b_j_loop_end_frags (void)
e0001a05
NC		 7426{
7427 frchainS *frchP;
7428
7429 /* When this routine is called, all of the subsections are still intact
7430 so we walk over subsections instead of sections. */
7431 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7432 {
7433 fragS *fragP;
7434
7435 /* Walk over all of the fragments in a subsection. */
7436 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7437 {
7438 if (fragP->fr_type == rs_machine_dependent
7439 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7440 {
7441 if (next_instr_is_loop_end (fragP))
43cd72b9 7442 {
b08b5071 7443 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7444 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7445 else
7446 relax_frag_add_nop (fragP);
7447 }
7448 frag_wane (fragP);
e0001a05
NC		 7449 }
7450 }
7451 }
7452}
7453
7454
7fa3d080
BW		 7455static bfd_boolean
7456next_instr_is_loop_end (fragS *fragP)
e0001a05
NC		 7457{
7458 const fragS *next_fragP;
7459
7460 if (next_frag_is_loop_target (fragP))
7461 return FALSE;
7462
7463 next_fragP = next_non_empty_frag (fragP);
7464 if (next_fragP == NULL)
7465 return FALSE;
7466
7467 if (!next_frag_is_loop_target (next_fragP))
7468 return FALSE;
7469
7470 /* If the size is >= 3 then there is more than one instruction here.
7471 The hardware bug will not fire. */
7472 if (next_fragP->fr_fix > 3)
7473 return FALSE;
7474
7475 return TRUE;
7476}
7477
7478
7479/* Re-process all of the fragments looking to convert all of the
7480 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7481 not MY loop's loop end within 12 bytes, add enough nops here to
7482 make it at least 12 bytes away. In any case close it off with a
7483 .fill 0. */
7484
7fa3d080
BW		 7485static size_t min_bytes_to_other_loop_end (fragS *, fragS *, offsetT, size_t);
7486
e0001a05 7487static void
7fa3d080 7488xtensa_fix_close_loop_end_frags (void)
e0001a05
NC		 7489{
7490 frchainS *frchP;
7491
7492 /* When this routine is called, all of the subsections are still intact
7493 so we walk over subsections instead of sections. */
7494 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7495 {
7496 fragS *fragP;
7497
7498 fragS *current_target = NULL;
7499 offsetT current_offset = 0;
7500
7501 /* Walk over all of the fragments in a subsection. */
7502 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7503 {
7504 if (fragP->fr_type == rs_machine_dependent
43cd72b9
BW		 7505 && ((fragP->fr_subtype == RELAX_IMMED)
7506 || ((fragP->fr_subtype == RELAX_SLOTS)
7507 && (fragP->tc_frag_data.slot_subtypes[0]
7508 == RELAX_IMMED))))
e0001a05
NC		 7509 {
7510 /* Read it. If the instruction is a loop, get the target. */
43cd72b9
BW		 7511 TInsn t_insn;
7512 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7513 if (xtensa_opcode_is_loop (xtensa_default_isa,
7514 t_insn.opcode) == 1)
e0001a05 7515 {
e0001a05 7516 /* Get the current fragment target. */
43cd72b9 7517 if (fragP->tc_frag_data.slot_symbols[0])
e0001a05 7518 {
43cd72b9
BW		 7519 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7520 current_target = symbol_get_frag (sym);
e0001a05
NC		 7521 current_offset = fragP->fr_offset;
7522 }
7523 }
7524 }
7525
7526 if (current_target
7527 && fragP->fr_type == rs_machine_dependent
7528 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7529 {
7530 size_t min_bytes;
7531 size_t bytes_added = 0;
7532
7533#define REQUIRED_LOOP_DIVIDING_BYTES 12
7534 /* Max out at 12. */
7535 min_bytes = min_bytes_to_other_loop_end
7536 (fragP->fr_next, current_target, current_offset,
7537 REQUIRED_LOOP_DIVIDING_BYTES);
7538
7539 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7540 {
b08b5071 7541 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7542 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7543 else
e0001a05 7544 {
43cd72b9
BW		 7545 while (min_bytes + bytes_added
7546 < REQUIRED_LOOP_DIVIDING_BYTES)
e0001a05 7547 {
43cd72b9
BW		 7548 int length = 3;
7549
7550 if (fragP->fr_var < length)
7551 as_fatal (_("fr_var %lu < length %d"),
7552 fragP->fr_var, length);
7553 else
7554 {
7555 assemble_nop (length,
7556 fragP->fr_literal + fragP->fr_fix);
7557 fragP->fr_fix += length;
7558 fragP->fr_var -= length;
7559 }
7560 bytes_added += length;
e0001a05 7561 }
e0001a05
NC		 7562 }
7563 }
7564 frag_wane (fragP);
7565 }
43cd72b9
BW		 7566 assert (fragP->fr_type != rs_machine_dependent
7567 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
e0001a05
NC		 7568 }
7569 }
7570}
7571
7572
7fa3d080
BW		 7573static size_t unrelaxed_frag_min_size (fragS *);
7574
43cd72b9 7575static size_t
7fa3d080
BW		 7576min_bytes_to_other_loop_end (fragS *fragP,
7577 fragS *current_target,
7578 offsetT current_offset,
7579 size_t max_size)
e0001a05
NC		 7580{
7581 size_t offset = 0;
7582 fragS *current_fragP;
7583
7584 for (current_fragP = fragP;
7585 current_fragP;
7586 current_fragP = current_fragP->fr_next)
7587 {
7588 if (current_fragP->tc_frag_data.is_loop_target
7589 && current_fragP != current_target)
7590 return offset + current_offset;
7591
7592 offset += unrelaxed_frag_min_size (current_fragP);
7593
7594 if (offset + current_offset >= max_size)
7595 return max_size;
7596 }
7597 return max_size;
7598}
7599
7600
43cd72b9 7601static size_t
7fa3d080 7602unrelaxed_frag_min_size (fragS *fragP)
e0001a05
NC		 7603{
7604 size_t size = fragP->fr_fix;
7605
7606 /* add fill size */
7607 if (fragP->fr_type == rs_fill)
7608 size += fragP->fr_offset;
7609
7610 return size;
7611}
7612
7613
43cd72b9 7614static size_t
7fa3d080 7615unrelaxed_frag_max_size (fragS *fragP)
43cd72b9
BW		 7616{
7617 size_t size = fragP->fr_fix;
7618 switch (fragP->fr_type)
7619 {
7620 case 0:
7621 /* Empty frags created by the obstack allocation scheme
7622 end up with type 0. */
7623 break;
7624 case rs_fill:
7625 case rs_org:
7626 case rs_space:
7627 size += fragP->fr_offset;
7628 break;
7629 case rs_align:
7630 case rs_align_code:
7631 case rs_align_test:
7632 case rs_leb128:
7633 case rs_cfa:
7634 case rs_dwarf2dbg:
7635 /* No further adjustments needed. */
7636 break;
7637 case rs_machine_dependent:
7638 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7639 size += fragP->fr_var;
7640 break;
7641 default:
7642 /* We had darn well better know how big it is. */
7643 assert (0);
7644 break;
7645 }
7646
7647 return size;
7648}
7649
7650
e0001a05
NC		 7651/* Re-process all of the fragments looking to convert all
7652 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7653
7654 A)
7655 1) the instruction size count to the loop end label
7656 is too short (<= 2 instructions),
7657 2) loop has a jump or branch in it
7658
7659 or B)
43cd72b9 7660 1) workaround_all_short_loops is TRUE
e0001a05
NC		 7661 2) The generating loop was a 'loopgtz' or 'loopnez'
7662 3) the instruction size count to the loop end label is too short
7663 (<= 2 instructions)
7664 then convert this frag (and maybe the next one) to generate a NOP.
7665 In any case close it off with a .fill 0. */
7666
7fa3d080
BW		 7667static size_t count_insns_to_loop_end (fragS *, bfd_boolean, size_t);
7668static bfd_boolean branch_before_loop_end (fragS *);
7669
e0001a05 7670static void
7fa3d080 7671xtensa_fix_short_loop_frags (void)
e0001a05
NC		 7672{
7673 frchainS *frchP;
7674
7675 /* When this routine is called, all of the subsections are still intact
7676 so we walk over subsections instead of sections. */
7677 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7678 {
7679 fragS *fragP;
7680 fragS *current_target = NULL;
7681 offsetT current_offset = 0;
7682 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
7683
7684 /* Walk over all of the fragments in a subsection. */
7685 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7686 {
43cd72b9 7687 /* Check on the current loop. */
e0001a05 7688 if (fragP->fr_type == rs_machine_dependent
43cd72b9
BW		 7689 && ((fragP->fr_subtype == RELAX_IMMED)
7690 || ((fragP->fr_subtype == RELAX_SLOTS)
7691 && (fragP->tc_frag_data.slot_subtypes[0]
7692 == RELAX_IMMED))))
e0001a05 7693 {
43cd72b9
BW		 7694 TInsn t_insn;
7695
e0001a05 7696 /* Read it. If the instruction is a loop, get the target. */
43cd72b9
BW		 7697 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7698 if (xtensa_opcode_is_loop (xtensa_default_isa,
7699 t_insn.opcode) == 1)
e0001a05 7700 {
e0001a05 7701 /* Get the current fragment target. */
43cd72b9 7702 if (fragP->tc_frag_data.slot_symbols[0])
e0001a05 7703 {
43cd72b9
BW		 7704 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7705 current_target = symbol_get_frag (sym);
e0001a05 7706 current_offset = fragP->fr_offset;
43cd72b9 7707 current_opcode = t_insn.opcode;
e0001a05
NC		 7708 }
7709 }
7710 }
7711
7712 if (fragP->fr_type == rs_machine_dependent
7713 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7714 {
7715 size_t insn_count =
7716 count_insns_to_loop_end (fragP->fr_next, TRUE, 3);
7717 if (insn_count < 3
7718 && (branch_before_loop_end (fragP->fr_next)
43cd72b9 7719 || (workaround_all_short_loops
e0001a05 7720 && current_opcode != XTENSA_UNDEFINED
b08b5071 7721 && current_opcode != xtensa_loop_opcode)))
43cd72b9 7722 {
b08b5071 7723 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7724 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7725 else
7726 relax_frag_add_nop (fragP);
7727 }
7728 frag_wane (fragP);
e0001a05
NC		 7729 }
7730 }
7731 }
7732}
7733
7734
7fa3d080
BW		 7735static size_t unrelaxed_frag_min_insn_count (fragS *);
7736
43cd72b9 7737static size_t
7fa3d080
BW		 7738count_insns_to_loop_end (fragS *base_fragP,
7739 bfd_boolean count_relax_add,
7740 size_t max_count)
e0001a05
NC		 7741{
7742 fragS *fragP = NULL;
7743 size_t insn_count = 0;
7744
7745 fragP = base_fragP;
7746
7747 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7748 {
7749 insn_count += unrelaxed_frag_min_insn_count (fragP);
7750 if (insn_count >= max_count)
7751 return max_count;
7752
7753 if (count_relax_add)
7754 {
7755 if (fragP->fr_type == rs_machine_dependent
7756 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7757 {
7758 /* In order to add the appropriate number of
7759 NOPs, we count an instruction for downstream
7760 occurrences. */
7761 insn_count++;
7762 if (insn_count >= max_count)
7763 return max_count;
7764 }
7765 }
7766 }
7767 return insn_count;
7768}
7769
7770
43cd72b9 7771static size_t
7fa3d080 7772unrelaxed_frag_min_insn_count (fragS *fragP)
e0001a05 7773{
43cd72b9
BW		 7774 xtensa_isa isa = xtensa_default_isa;
7775 static xtensa_insnbuf insnbuf = NULL;
e0001a05
NC		 7776 size_t insn_count = 0;
7777 int offset = 0;
7778
7779 if (!fragP->tc_frag_data.is_insn)
7780 return insn_count;
7781
43cd72b9
BW		 7782 if (!insnbuf)
7783 insnbuf = xtensa_insnbuf_alloc (isa);
7784
e0001a05
NC		 7785 /* Decode the fixed instructions. */
7786 while (offset < fragP->fr_fix)
7787 {
43cd72b9
BW		 7788 xtensa_format fmt;
7789
7790 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7791 fmt = xtensa_format_decode (isa, insnbuf);
7792
7793 if (fmt == XTENSA_UNDEFINED)
e0001a05
NC		 7794 {
7795 as_fatal (_("undecodable instruction in instruction frag"));
7796 return insn_count;
7797 }
43cd72b9 7798 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7799 insn_count++;
7800 }
7801
7802 return insn_count;
7803}
7804
7805
7fa3d080
BW		 7806static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7807
43cd72b9 7808static bfd_boolean
7fa3d080 7809branch_before_loop_end (fragS *base_fragP)
e0001a05
NC		 7810{
7811 fragS *fragP;
7812
7813 for (fragP = base_fragP;
7814 fragP && !fragP->tc_frag_data.is_loop_target;
7815 fragP = fragP->fr_next)
7816 {
7817 if (unrelaxed_frag_has_b_j (fragP))
7818 return TRUE;
7819 }
7820 return FALSE;
7821}
7822
7823
43cd72b9 7824static bfd_boolean
7fa3d080 7825unrelaxed_frag_has_b_j (fragS *fragP)
e0001a05 7826{
43cd72b9
BW		 7827 static xtensa_insnbuf insnbuf = NULL;
7828 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 7829 int offset = 0;
7830
7831 if (!fragP->tc_frag_data.is_insn)
7832 return FALSE;
7833
43cd72b9
BW		 7834 if (!insnbuf)
7835 insnbuf = xtensa_insnbuf_alloc (isa);
7836
e0001a05
NC		 7837 /* Decode the fixed instructions. */
7838 while (offset < fragP->fr_fix)
7839 {
43cd72b9
BW		 7840 xtensa_format fmt;
7841 int slot;
7842
7843 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7844 fmt = xtensa_format_decode (isa, insnbuf);
7845 if (fmt == XTENSA_UNDEFINED)
7846 return FALSE;
7847
7848 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
e0001a05 7849 {
43cd72b9
BW		 7850 xtensa_opcode opcode =
7851 get_opcode_from_buf (fragP->fr_literal + offset, slot);
7852 if (xtensa_opcode_is_branch (isa, opcode) == 1
7853 || xtensa_opcode_is_jump (isa, opcode) == 1)
7854 return TRUE;
e0001a05 7855 }
43cd72b9 7856 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7857 }
7858 return FALSE;
7859}
7860
7861
7862/* Checks to be made after initial assembly but before relaxation. */
7863
7fa3d080
BW		 7864static bfd_boolean is_empty_loop (const TInsn *, fragS *);
7865static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
7866
e0001a05 7867static void
7fa3d080 7868xtensa_sanity_check (void)
e0001a05
NC		 7869{
7870 char *file_name;
7871 int line;
7872
7873 frchainS *frchP;
7874
7875 as_where (&file_name, &line);
7876 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7877 {
7878 fragS *fragP;
7879
7880 /* Walk over all of the fragments in a subsection. */
7881 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7882 {
7883 /* Currently we only check for empty loops here. */
7884 if (fragP->fr_type == rs_machine_dependent
7885 && fragP->fr_subtype == RELAX_IMMED)
7886 {
7887 static xtensa_insnbuf insnbuf = NULL;
7888 TInsn t_insn;
7889
7890 if (fragP->fr_opcode != NULL)
7891 {
7892 if (!insnbuf)
7893 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
43cd72b9
BW		 7894 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7895 tinsn_immed_from_frag (&t_insn, fragP, 0);
e0001a05 7896
43cd72b9
BW		 7897 if (xtensa_opcode_is_loop (xtensa_default_isa,
7898 t_insn.opcode) == 1)
e0001a05
NC		 7899 {
7900 if (is_empty_loop (&t_insn, fragP))
7901 {
7902 new_logical_line (fragP->fr_file, fragP->fr_line);
7903 as_bad (_("invalid empty loop"));
7904 }
7905 if (!is_local_forward_loop (&t_insn, fragP))
7906 {
7907 new_logical_line (fragP->fr_file, fragP->fr_line);
7908 as_bad (_("loop target does not follow "
7909 "loop instruction in section"));
7910 }
7911 }
7912 }
7913 }
7914 }
7915 }
7916 new_logical_line (file_name, line);
7917}
7918
7919
7920#define LOOP_IMMED_OPN 1
7921
43cd72b9 7922/* Return TRUE if the loop target is the next non-zero fragment. */
e0001a05 7923
7fa3d080
BW		 7924static bfd_boolean
7925is_empty_loop (const TInsn *insn, fragS *fragP)
e0001a05
NC		 7926{
7927 const expressionS *expr;
7928 symbolS *symbolP;
7929 fragS *next_fragP;
7930
7931 if (insn->insn_type != ITYPE_INSN)
7932 return FALSE;
7933
43cd72b9 7934 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
e0001a05
NC		 7935 return FALSE;
7936
7937 if (insn->ntok <= LOOP_IMMED_OPN)
7938 return FALSE;
7939
7940 expr = &insn->tok[LOOP_IMMED_OPN];
7941
7942 if (expr->X_op != O_symbol)
7943 return FALSE;
7944
7945 symbolP = expr->X_add_symbol;
7946 if (!symbolP)
7947 return FALSE;
7948
7949 if (symbol_get_frag (symbolP) == NULL)
7950 return FALSE;
7951
7952 if (S_GET_VALUE (symbolP) != 0)
7953 return FALSE;
7954
7955 /* Walk through the zero-size fragments from this one. If we find
7956 the target fragment, then this is a zero-size loop. */
43cd72b9 7957
e0001a05
NC		 7958 for (next_fragP = fragP->fr_next;
7959 next_fragP != NULL;
7960 next_fragP = next_fragP->fr_next)
7961 {
7962 if (next_fragP == symbol_get_frag (symbolP))
7963 return TRUE;
7964 if (next_fragP->fr_fix != 0)
7965 return FALSE;
7966 }
7967 return FALSE;
7968}
7969
7970
7fa3d080
BW		 7971static bfd_boolean
7972is_local_forward_loop (const TInsn *insn, fragS *fragP)
e0001a05
NC		 7973{
7974 const expressionS *expr;
7975 symbolS *symbolP;
7976 fragS *next_fragP;
7977
7978 if (insn->insn_type != ITYPE_INSN)
7979 return FALSE;
7980
43cd72b9 7981 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
e0001a05
NC		 7982 return FALSE;
7983
7984 if (insn->ntok <= LOOP_IMMED_OPN)
7985 return FALSE;
7986
7987 expr = &insn->tok[LOOP_IMMED_OPN];
7988
7989 if (expr->X_op != O_symbol)
7990 return FALSE;
7991
7992 symbolP = expr->X_add_symbol;
7993 if (!symbolP)
7994 return FALSE;
7995
7996 if (symbol_get_frag (symbolP) == NULL)
7997 return FALSE;
7998
7999 /* Walk through fragments until we find the target.
8000 If we do not find the target, then this is an invalid loop. */
43cd72b9 8001
e0001a05
NC		 8002 for (next_fragP = fragP->fr_next;
8003 next_fragP != NULL;
8004 next_fragP = next_fragP->fr_next)
43cd72b9
BW		 8005 {
8006 if (next_fragP == symbol_get_frag (symbolP))
8007 return TRUE;
8008 }
e0001a05
NC		 8009
8010 return FALSE;
8011}
8012
8013\f
8014/* Alignment Functions. */
8015
43cd72b9 8016static size_t
7fa3d080 8017get_text_align_power (int target_size)
e0001a05
NC		 8018{
8019 size_t i = 0;
8020 for (i = 0; i < sizeof (size_t); i++)
8021 {
8022 if (target_size <= (1 << i))
8023 return i;
8024 }
43cd72b9 8025 assert (0);
e0001a05
NC		 8026 return 0;
8027}
8028
8029
43cd72b9 8030static addressT
7fa3d080
BW		 8031get_text_align_max_fill_size (int align_pow,
8032 bfd_boolean use_nops,
8033 bfd_boolean use_no_density)
e0001a05
NC		 8034{
8035 if (!use_nops)
8036 return (1 << align_pow);
8037 if (use_no_density)
8038 return 3 * (1 << align_pow);
8039
8040 return 1 + (1 << align_pow);
8041}
8042
8043
8044/* get_text_align_fill_size ()
43cd72b9 8045
e0001a05
NC		 8046 Desired alignments:
8047 give the address
8048 target_size = size of next instruction
8049 align_pow = get_text_align_power (target_size).
8050 use_nops = 0
8051 use_no_density = 0;
8052 Loop alignments:
8053 address = current address + loop instruction size;
8054 target_size = 3 (for 2 or 3 byte target)
43cd72b9 8055 = 4 (for 4 byte target)
e0001a05
NC		 8056 = 8 (for 8 byte target)
8057 align_pow = get_text_align_power (target_size);
8058 use_nops = 1
8059 use_no_density = set appropriately
8060 Text alignments:
8061 address = current address + loop instruction size;
8062 target_size = 0
8063 align_pow = get_text_align_power (target_size);
8064 use_nops = 0
8065 use_no_density = 0. */
8066
43cd72b9 8067static addressT
7fa3d080
BW		 8068get_text_align_fill_size (addressT address,
8069 int align_pow,
8070 int target_size,
8071 bfd_boolean use_nops,
8072 bfd_boolean use_no_density)
e0001a05
NC		 8073{
8074 /* Input arguments:
8075
8076 align_pow: log2 (required alignment).
8077
8078 target_size: alignment must allow the new_address and
8079 new_address+target_size-1.
8080
43cd72b9 8081 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
e0001a05
NC		 8082
8083 use_no_density: if use_nops and use_no_density, we can only use
8084 3-byte nops.
8085
43cd72b9
BW		 8086 Usually the align_pow is the power of 2 that is greater than
8087 or equal to the target_size. This handles the 2-byte, 3-byte
8088 and 8-byte instructions.
8089
8090 Two cases:
8091
8092 (1) aligning an instruction properly, but without using NOPs.
8093 E.G.: a 3-byte instruction can go on any address where address mod 4
8094 is zero or one. The aligner uses this case to find the optimal
8095 number of fill bytes for relax_frag_for_align.
8096
8097 (2) aligning an instruction properly, but where we might need to use
8098 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8099 or similar to get the optimal location. */
e0001a05
NC		 8100
8101 size_t alignment = (1 << align_pow);
43cd72b9
BW		 8102
8103 assert (target_size != 0);
8104
e0001a05
NC		 8105 if (!use_nops)
8106 {
43cd72b9
BW		 8107 unsigned fill_bytes;
8108 for (fill_bytes = 0; fill_bytes < alignment; fill_bytes++)
8109 {
8110 addressT end_address = address + target_size - 1 + fill_bytes;
8111 addressT start_address = address + fill_bytes;
8112 if ((end_address >> align_pow) == (start_address >> align_pow))
8113 return fill_bytes;
8114 }
8115 assert (0);
e0001a05
NC		 8116 }
8117
8118 /* This is the slightly harder case. */
8119 assert ((int) alignment >= target_size);
8120 assert (target_size > 0);
8121 if (!use_no_density)
8122 {
8123 size_t i;
8124 for (i = 0; i < alignment * 2; i++)
8125 {
8126 if (i == 1)
8127 continue;
43cd72b9
BW		 8128 if ((address + i) >> align_pow
8129 == (address + i + target_size - 1) >> align_pow)
e0001a05
NC		 8130 return i;
8131 }
8132 }
8133 else
8134 {
8135 size_t i;
8136
8137 /* Can only fill multiples of 3. */
8138 for (i = 0; i <= alignment * 3; i += 3)
8139 {
43cd72b9
BW		 8140 if ((address + i) >> align_pow
8141 == (address + i + target_size - 1) >> align_pow)
e0001a05
NC		 8142 return i;
8143 }
8144 }
8145 assert (0);
8146 return 0;
8147}
8148
8149
8150/* This will assert if it is not possible. */
8151
7fa3d080
BW		 8152static size_t
8153get_text_align_nop_count (size_t fill_size, bfd_boolean use_no_density)
e0001a05
NC		 8154{
8155 size_t count = 0;
8156 if (use_no_density)
8157 {
8158 assert (fill_size % 3 == 0);
8159 return (fill_size / 3);
8160 }
8161
8162 assert (fill_size != 1); /* Bad argument. */
8163
8164 while (fill_size > 1)
8165 {
8166 size_t insn_size = 3;
8167 if (fill_size == 2 || fill_size == 4)
8168 insn_size = 2;
8169 fill_size -= insn_size;
8170 count++;
8171 }
8172 assert (fill_size != 1); /* Bad algorithm. */
8173 return count;
8174}
8175
8176
7fa3d080
BW		 8177static size_t
8178get_text_align_nth_nop_size (size_t fill_size,
8179 size_t n,
8180 bfd_boolean use_no_density)
e0001a05
NC		 8181{
8182 size_t count = 0;
8183
8184 assert (get_text_align_nop_count (fill_size, use_no_density) > n);
8185
8186 if (use_no_density)
8187 return 3;
8188
8189 while (fill_size > 1)
8190 {
8191 size_t insn_size = 3;
8192 if (fill_size == 2 || fill_size == 4)
8193 insn_size = 2;
8194 fill_size -= insn_size;
8195 count++;
8196 if (n + 1 == count)
8197 return insn_size;
8198 }
8199 assert (0);
8200 return 0;
8201}
8202
8203
8204/* For the given fragment, find the appropriate address
8205 for it to begin at if we are using NOPs to align it. */
8206
8207static addressT
7fa3d080 8208get_noop_aligned_address (fragS *fragP, addressT address)
e0001a05 8209{
43cd72b9
BW		 8210 /* The rule is: get next fragment's FIRST instruction. Find
8211 the smallest number of bytes that need to be added to
8212 ensure that the next fragment's FIRST instruction will fit
8213 in a single word.
8214
8215 E.G., 2 bytes : 0, 1, 2 mod 4
8216 3 bytes: 0, 1 mod 4
8217
8218 If the FIRST instruction MIGHT be relaxed,
8219 assume that it will become a 3-byte instruction.
8220
8221 Note again here that LOOP instructions are not bundleable,
8222 and this relaxation only applies to LOOP opcodes. */
8223
e0001a05 8224 size_t fill_size = 0;
43cd72b9
BW		 8225 int first_insn_size;
8226 int loop_insn_size;
8227 addressT pre_opcode_bytes;
8228 size_t alignment;
8229 fragS *first_insn;
8230 xtensa_opcode opcode;
8231 bfd_boolean is_loop;
e0001a05 8232
43cd72b9
BW		 8233 assert (fragP->fr_type == rs_machine_dependent);
8234 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
e0001a05 8235
43cd72b9
BW		 8236 /* Find the loop frag. */
8237 first_insn = next_non_empty_frag (fragP);
8238 /* Now find the first insn frag. */
8239 first_insn = next_non_empty_frag (first_insn);
e0001a05 8240
43cd72b9
BW		 8241 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8242 assert (is_loop);
8243 loop_insn_size = xg_get_single_size (opcode);
e0001a05 8244
43cd72b9
BW		 8245 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8246 pre_opcode_bytes += loop_insn_size;
e0001a05 8247
43cd72b9
BW		 8248 /* For loops, the alignment depends on the size of the
8249 instruction following the loop, not the LOOP instruction. */
e0001a05 8250
43cd72b9
BW		 8251 if (first_insn == NULL)
8252 return address;
e0001a05 8253
43cd72b9 8254 assert (first_insn->tc_frag_data.is_first_loop_insn);
e0001a05 8255
43cd72b9 8256 first_insn_size = frag_format_size (first_insn);
e0001a05 8257
43cd72b9
BW		 8258 if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED)
8259 first_insn_size = 3; /* ISA specifies this */
e0001a05 8260
43cd72b9
BW		 8261 /* If it was 8, then we'll need a larger alignment for the section. */
8262 alignment = get_text_align_power (first_insn_size);
e0001a05 8263
43cd72b9
BW		 8264 /* Is now_seg valid? */
8265 record_alignment (now_seg, alignment);
8266
8267 fill_size = get_text_align_fill_size
8268 (address + pre_opcode_bytes,
8269 get_text_align_power (first_insn_size),
8270 first_insn_size, TRUE, fragP->tc_frag_data.is_no_density);
e0001a05
NC		 8271
8272 return address + fill_size;
8273}
8274
8275
43cd72b9
BW		 8276/* 3 mechanisms for relaxing an alignment:
8277
8278 Align to a power of 2.
8279 Align so the next fragment's instruction does not cross a word boundary.
8280 Align the current instruction so that if the next instruction
8281 were 3 bytes, it would not cross a word boundary.
8282
e0001a05
NC		 8283 We can align with:
8284
43cd72b9
BW		 8285 zeros - This is easy; always insert zeros.
8286 nops - 3-byte and 2-byte instructions
8287 2 - 2-byte nop
8288 3 - 3-byte nop
8289 4 - 2 2-byte nops
8290 >=5 : 3-byte instruction + fn (n-3)
e0001a05
NC		 8291 widening - widen previous instructions. */
8292
8293static addressT
7fa3d080 8294get_aligned_diff (fragS *fragP, addressT address, addressT *max_diff)
e0001a05 8295{
43cd72b9
BW		 8296 addressT target_address, loop_insn_offset;
8297 int target_size;
8298 xtensa_opcode loop_opcode;
8299 bfd_boolean is_loop;
8300 int text_align_power;
8301 addressT opt_diff;
e0001a05 8302
43cd72b9
BW		 8303 assert (fragP->fr_type == rs_machine_dependent);
8304 switch (fragP->fr_subtype)
e0001a05 8305 {
43cd72b9
BW		 8306 case RELAX_DESIRE_ALIGN:
8307 target_size = next_frag_format_size (fragP);
8308 if (target_size == XTENSA_UNDEFINED)
8309 target_size = 3;
8310 text_align_power = get_text_align_power (xtensa_fetch_width);
8311 opt_diff = get_text_align_fill_size (address, text_align_power,
8312 target_size, FALSE, FALSE);
8313
8314 *max_diff = opt_diff + xtensa_fetch_width
8315 - (target_size + ((address + opt_diff) % xtensa_fetch_width));
8316 assert (*max_diff >= opt_diff);
8317 return opt_diff;
e0001a05 8318
43cd72b9
BW		 8319 case RELAX_ALIGN_NEXT_OPCODE:
8320 target_size = next_frag_format_size (fragP);
8321 loop_insn_offset = 0;
8322 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8323 assert (is_loop);
8324
8325 /* If the loop has been expanded then the LOOP instruction
8326 could be at an offset from this fragment. */
8327 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
8328 != RELAX_IMMED)
8329 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8330
8331 if (target_size == 2)
8332 target_size = 3; /* ISA specifies this */
8333
8334 /* In an ideal world, which is what we are shooting for here,
8335 we wouldn't need to use any NOPs immediately prior to the
8336 LOOP instruction. If this approach fails, relax_frag_loop_align
8337 will call get_noop_aligned_address. */
8338 target_address =
8339 address + loop_insn_offset + xg_get_single_size (loop_opcode);
8340 text_align_power = get_text_align_power (target_size),
8341 opt_diff = get_text_align_fill_size (target_address, text_align_power,
8342 target_size, FALSE, FALSE);
8343
8344 *max_diff = xtensa_fetch_width
8345 - ((target_address + opt_diff) % xtensa_fetch_width)
8346 - target_size + opt_diff;
8347 assert (*max_diff >= opt_diff);
8348 return opt_diff;
e0001a05 8349
43cd72b9
BW		 8350 default:
8351 break;
e0001a05 8352 }
43cd72b9
BW		 8353 assert (0);
8354 return 0;
e0001a05
NC		 8355}
8356
8357\f
8358/* md_relax_frag Hook and Helper Functions. */
8359
7fa3d080
BW		 8360static long relax_frag_loop_align (fragS *, long);
8361static long relax_frag_for_align (fragS *, long);
8362static long relax_frag_immed
8363 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8364
8365
e0001a05
NC		 8366/* Return the number of bytes added to this fragment, given that the
8367 input has been stretched already by "stretch". */
8368
8369long
7fa3d080 8370xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
e0001a05 8371{
43cd72b9 8372 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 8373 int unreported = fragP->tc_frag_data.unreported_expansion;
8374 long new_stretch = 0;
8375 char *file_name;
8376 int line, lit_size;
43cd72b9
BW		 8377 static xtensa_insnbuf vbuf = NULL;
8378 int slot, num_slots;
8379 xtensa_format fmt;
e0001a05
NC		 8380
8381 as_where (&file_name, &line);
8382 new_logical_line (fragP->fr_file, fragP->fr_line);
8383
8384 fragP->tc_frag_data.unreported_expansion = 0;
8385
8386 switch (fragP->fr_subtype)
8387 {
8388 case RELAX_ALIGN_NEXT_OPCODE:
8389 /* Always convert. */
43cd72b9
BW		 8390 if (fragP->tc_frag_data.relax_seen)
8391 new_stretch = relax_frag_loop_align (fragP, stretch);
e0001a05
NC		 8392 break;
8393
8394 case RELAX_LOOP_END:
8395 /* Do nothing. */
8396 break;
8397
8398 case RELAX_LOOP_END_ADD_NOP:
8399 /* Add a NOP and switch to .fill 0. */
8400 new_stretch = relax_frag_add_nop (fragP);
43cd72b9 8401 frag_wane (fragP);
e0001a05
NC		 8402 break;
8403
8404 case RELAX_DESIRE_ALIGN:
43cd72b9 8405 /* Do nothing. The narrowing before this frag will either align
e0001a05
NC		 8406 it or not. */
8407 break;
8408
8409 case RELAX_LITERAL:
8410 case RELAX_LITERAL_FINAL:
8411 return 0;
8412
8413 case RELAX_LITERAL_NR:
8414 lit_size = 4;
8415 fragP->fr_subtype = RELAX_LITERAL_FINAL;
8416 assert (unreported == lit_size);
8417 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8418 fragP->fr_var -= lit_size;
8419 fragP->fr_fix += lit_size;
8420 new_stretch = 4;
8421 break;
8422
43cd72b9
BW		 8423 case RELAX_SLOTS:
8424 if (vbuf == NULL)
8425 vbuf = xtensa_insnbuf_alloc (isa);
8426
8427 xtensa_insnbuf_from_chars (isa, vbuf, fragP->fr_opcode, 0);
8428 fmt = xtensa_format_decode (isa, vbuf);
8429 num_slots = xtensa_format_num_slots (isa, fmt);
e0001a05 8430
43cd72b9
BW		 8431 for (slot = 0; slot < num_slots; slot++)
8432 {
8433 switch (fragP->tc_frag_data.slot_subtypes[slot])
8434 {
8435 case RELAX_NARROW:
8436 if (fragP->tc_frag_data.relax_seen)
8437 new_stretch += relax_frag_for_align (fragP, stretch);
8438 break;
8439
8440 case RELAX_IMMED:
8441 case RELAX_IMMED_STEP1:
8442 case RELAX_IMMED_STEP2:
8443 /* Place the immediate. */
8444 new_stretch += relax_frag_immed
8445 (now_seg, fragP, stretch,
8446 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8447 fmt, slot, stretched_p, FALSE);
8448 break;
8449
8450 default:
8451 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8452 break;
8453 }
8454 }
e0001a05
NC		 8455 break;
8456
8457 case RELAX_LITERAL_POOL_BEGIN:
8458 case RELAX_LITERAL_POOL_END:
43cd72b9
BW		 8459 case RELAX_MAYBE_UNREACHABLE:
8460 case RELAX_MAYBE_DESIRE_ALIGN:
e0001a05
NC		 8461 /* No relaxation required. */
8462 break;
8463
43cd72b9
BW		 8464 case RELAX_FILL_NOP:
8465 case RELAX_UNREACHABLE:
8466 if (fragP->tc_frag_data.relax_seen)
8467 new_stretch += relax_frag_for_align (fragP, stretch);
8468 break;
8469
e0001a05
NC		 8470 default:
8471 as_bad (_("bad relaxation state"));
8472 }
8473
43cd72b9
BW		 8474 /* Tell gas we need another relaxation pass. */
8475 if (! fragP->tc_frag_data.relax_seen)
8476 {
8477 fragP->tc_frag_data.relax_seen = TRUE;
8478 *stretched_p = 1;
8479 }
8480
e0001a05
NC		 8481 new_logical_line (file_name, line);
8482 return new_stretch;
8483}
8484
8485
8486static long
7fa3d080 8487relax_frag_loop_align (fragS *fragP, long stretch)
e0001a05
NC		 8488{
8489 addressT old_address, old_next_address, old_size;
8490 addressT new_address, new_next_address, new_size;
8491 addressT growth;
8492
43cd72b9
BW		 8493 /* All the frags with relax_frag_for_alignment prior to this one in the
8494 section have been done, hopefully eliminating the need for a NOP here.
8495 But, this will put it in if necessary. */
e0001a05
NC		 8496
8497 /* Calculate the old address of this fragment and the next fragment. */
8498 old_address = fragP->fr_address - stretch;
8499 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
43cd72b9 8500 fragP->tc_frag_data.text_expansion[0]);
e0001a05
NC		 8501 old_size = old_next_address - old_address;
8502
8503 /* Calculate the new address of this fragment and the next fragment. */
8504 new_address = fragP->fr_address;
8505 new_next_address =
8506 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8507 new_size = new_next_address - new_address;
8508
8509 growth = new_size - old_size;
8510
8511 /* Fix up the text_expansion field and return the new growth. */
43cd72b9 8512 fragP->tc_frag_data.text_expansion[0] += growth;
e0001a05
NC		 8513 return growth;
8514}
8515
8516
43cd72b9 8517/* Add a NOP instruction. */
e0001a05
NC		 8518
8519static long
7fa3d080 8520relax_frag_add_nop (fragS *fragP)
e0001a05 8521{
e0001a05 8522 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
43cd72b9
BW		 8523 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8524 assemble_nop (length, nop_buf);
e0001a05 8525 fragP->tc_frag_data.is_insn = TRUE;
e0001a05 8526
e0001a05
NC		 8527 if (fragP->fr_var < length)
8528 {
43cd72b9 8529 as_fatal (_("fr_var (%ld) < length (%d)"), fragP->fr_var, length);
e0001a05
NC		 8530 return 0;
8531 }
8532
8533 fragP->fr_fix += length;
8534 fragP->fr_var -= length;
e0001a05
NC		 8535 return length;
8536}
8537
8538
7fa3d080
BW		 8539static long future_alignment_required (fragS *, long);
8540
e0001a05 8541static long
7fa3d080 8542relax_frag_for_align (fragS *fragP, long stretch)
e0001a05 8543{
43cd72b9
BW		 8544 /* Overview of the relaxation procedure for alignment:
8545 We can widen with NOPs or by widening instructions or by filling
8546 bytes after jump instructions. Find the opportune places and widen
8547 them if necessary. */
8548
8549 long stretch_me;
8550 long diff;
e0001a05 8551
43cd72b9
BW		 8552 assert (fragP->fr_subtype == RELAX_FILL_NOP
8553 || fragP->fr_subtype == RELAX_UNREACHABLE
8554 || (fragP->fr_subtype == RELAX_SLOTS
8555 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8556
8557 stretch_me = future_alignment_required (fragP, stretch);
8558 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8559 if (diff == 0)
8560 return 0;
e0001a05 8561
43cd72b9 8562 if (diff < 0)
e0001a05 8563 {
43cd72b9
BW		 8564 /* We expanded on a previous pass. Can we shrink now? */
8565 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8566 if (shrink <= stretch && stretch > 0)
e0001a05 8567 {
43cd72b9
BW		 8568 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8569 return -shrink;
e0001a05
NC		 8570 }
8571 return 0;
8572 }
8573
43cd72b9
BW		 8574 /* Below here, diff > 0. */
8575 fragP->tc_frag_data.text_expansion[0] = stretch_me;
e0001a05 8576
43cd72b9 8577 return diff;
e0001a05
NC		 8578}
8579
8580
43cd72b9
BW		 8581/* Return the address of the next frag that should be aligned.
8582
8583 By "address" we mean the address it _would_ be at if there
8584 is no action taken to align it between here and the target frag.
8585 In other words, if no narrows and no fill nops are used between
8586 here and the frag to align, _even_if_ some of the frags we use
8587 to align targets have already expanded on a previous relaxation
8588 pass.
8589
8590 Also, count each frag that may be used to help align the target.
8591
8592 Return 0 if there are no frags left in the chain that need to be
8593 aligned. */
8594
8595static addressT
7fa3d080
BW		 8596find_address_of_next_align_frag (fragS **fragPP,
8597 int *wide_nops,
8598 int *narrow_nops,
8599 int *widens,
8600 bfd_boolean *paddable)
e0001a05 8601{
43cd72b9
BW		 8602 fragS *fragP = *fragPP;
8603 addressT address = fragP->fr_address;
8604
8605 /* Do not reset the counts to 0. */
e0001a05
NC		 8606
8607 while (fragP)
8608 {
8609 /* Limit this to a small search. */
43cd72b9
BW		 8610 if (*widens > 8)
8611 {
8612 *fragPP = fragP;
8613 return 0;
8614 }
e0001a05
NC		 8615 address += fragP->fr_fix;
8616
43cd72b9
BW		 8617 if (fragP->fr_type == rs_fill)
8618 address += fragP->fr_offset * fragP->fr_var;
8619 else if (fragP->fr_type == rs_machine_dependent)
e0001a05 8620 {
e0001a05
NC		 8621 switch (fragP->fr_subtype)
8622 {
43cd72b9
BW		 8623 case RELAX_UNREACHABLE:
8624 *paddable = TRUE;
8625 break;
8626
8627 case RELAX_FILL_NOP:
8628 (*wide_nops)++;
8629 if (!fragP->tc_frag_data.is_no_density)
8630 (*narrow_nops)++;
8631 break;
8632
8633 case RELAX_SLOTS:
8634 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8635 {
8636 (*widens)++;
8637 break;
8638 }
34e41783 8639 address += total_frag_text_expansion (fragP);;
e0001a05
NC		 8640 break;
8641
8642 case RELAX_IMMED:
43cd72b9 8643 address += fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 8644 break;
8645
8646 case RELAX_ALIGN_NEXT_OPCODE:
8647 case RELAX_DESIRE_ALIGN:
43cd72b9
BW		 8648 *fragPP = fragP;
8649 return address;
8650
8651 case RELAX_MAYBE_UNREACHABLE:
8652 case RELAX_MAYBE_DESIRE_ALIGN:
8653 /* Do nothing. */
e0001a05
NC		 8654 break;
8655
8656 default:
43cd72b9
BW		 8657 /* Just punt if we don't know the type. */
8658 *fragPP = fragP;
8659 return 0;
e0001a05 8660 }
43cd72b9
BW		 8661 }
8662 else
8663 {
8664 /* Just punt if we don't know the type. */
8665 *fragPP = fragP;
8666 return 0;
8667 }
8668 fragP = fragP->fr_next;
8669 }
8670
8671 *fragPP = fragP;
8672 return 0;
8673}
8674
8675
7fa3d080
BW		 8676static long bytes_to_stretch (fragS *, int, int, int, int);
8677
43cd72b9
BW		 8678/* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8679 I'll leave this in until I am more confident this works. */
8680
8681#define LOOKAHEAD_ALIGNER 1
8682
8683static long
7fa3d080 8684future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
43cd72b9
BW		 8685{
8686 fragS *this_frag = fragP;
8687 long address;
8688 int num_widens = 0;
8689 int wide_nops = 0;
8690 int narrow_nops = 0;
8691 bfd_boolean paddable = FALSE;
8692 offsetT local_opt_diff;
8693 offsetT opt_diff;
8694 offsetT max_diff;
8695 int stretch_amount = 0;
8696 int local_stretch_amount;
8697 int global_stretch_amount;
8698
7fa3d080
BW		 8699 address = find_address_of_next_align_frag
8700 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
43cd72b9
BW		 8701
8702 if (address)
8703 {
8704 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8705 opt_diff = local_opt_diff;
8706 assert (opt_diff >= 0);
8707 assert (max_diff >= opt_diff);
8708 if (max_diff == 0)
8709 return 0;
8710#ifdef LOOKAHEAD_ALIGNER
8711 if (fragP)
8712 fragP = fragP->fr_next;
8713
8714 while (fragP && opt_diff < max_diff && address)
8715 {
8716 /* We only use these to determine if we can exit early
8717 because there will be plenty of ways to align future
8718 align frags. */
8719 unsigned int glob_widens = 0;
8720 int dnn = 0;
8721 int dw = 0;
8722 bfd_boolean glob_pad = 0;
7fa3d080
BW		 8723 address = find_address_of_next_align_frag
8724 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
43cd72b9
BW		 8725 /* If there is a padable portion, then skip. */
8726 if (glob_pad || (glob_widens >= xtensa_fetch_width))
8727 break;
8728
8729 if (address)
8730 {
8731 offsetT next_m_diff;
8732 offsetT next_o_diff;
8733
8734 /* Downrange frags haven't had stretch added to them yet. */
8735 address += stretch;
8736
8737 /* The address also includes any text expansion from this
8738 frag in a previous pass, but we don't want that. */
8739 address -= this_frag->tc_frag_data.text_expansion[0];
8740
8741 /* Assume we are going to move at least opt_diff. In
8742 reality, we might not be able to, but assuming that
8743 we will helps catch cases where moving opt_diff pushes
8744 the next target from aligned to unaligned. */
8745 address += opt_diff;
8746
8747 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8748
8749 /* Now cleanup for the adjustments to address. */
8750 next_o_diff += opt_diff;
8751 next_m_diff += opt_diff;
8752 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8753 opt_diff = next_o_diff;
8754 if (next_m_diff < max_diff)
8755 max_diff = next_m_diff;
8756 fragP = fragP->fr_next;
8757 }
8758 }
8759#endif /* LOOKAHEAD_ALIGNER */
8760 /* If there are enough wideners in between, do it. */
8761 if (paddable)
8762 {
8763 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8764 {
8765 assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8766 return opt_diff;
8767 }
8768 return 0;
8769 }
8770 local_stretch_amount
8771 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8772 num_widens, local_opt_diff);
8773#ifdef LOOKAHEAD_ALIGNER
8774 global_stretch_amount
8775 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8776 num_widens, opt_diff);
8777 /* If the condition below is true, then the frag couldn't
8778 stretch the correct amount for the global case, so we just
8779 optimize locally. We'll rely on the subsequent frags to get
8780 the correct alignment in the global case. */
8781 if (global_stretch_amount < local_stretch_amount)
8782 stretch_amount = local_stretch_amount;
8783 else
8784 stretch_amount = global_stretch_amount;
8785#else /* ! LOOKAHEAD_ALIGNER */
8786 stretch_amount = local_stretch_amount;
8787#endif /* ! LOOKAHEAD_ALIGNER */
8788 if (this_frag->fr_subtype == RELAX_SLOTS
8789 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8790 assert (stretch_amount <= 1);
8791 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8792 {
8793 if (this_frag->tc_frag_data.is_no_density)
8794 assert (stretch_amount == 3 || stretch_amount == 0);
8795 else
8796 assert (stretch_amount <= 3);
8797 }
8798 }
8799 return stretch_amount;
8800}
8801
8802
8803/* The idea: widen everything you can to get a target or loop aligned,
8804 then start using NOPs.
8805
8806 When we must have a NOP, here is a table of how we decide
8807 (so you don't have to fight through the control flow below):
8808
8809 wide_nops = the number of wide NOPs available for aligning
8810 narrow_nops = the number of narrow NOPs available for aligning
8811 (a subset of wide_nops)
8812 widens = the number of narrow instructions that should be widened
8813
8814 Desired wide narrow
8815 Diff nop nop widens
8816 1 0 0 1
8817 2 0 1 0
8818 3a 1 0 0
8819 b 0 1 1 (case 3a makes this case unnecessary)
8820 4a 1 0 1
8821 b 0 2 0
8822 c 0 1 2 (case 4a makes this case unnecessary)
8823 5a 1 0 2
8824 b 1 1 0
8825 c 0 2 1 (case 5b makes this case unnecessary)
8826 6a 2 0 0
8827 b 1 0 3
8828 c 0 1 4 (case 6b makes this case unneccesary)
8829 d 1 1 1 (case 6a makes this case unnecessary)
8830 e 0 2 2 (case 6a makes this case unnecessary)
8831 f 0 3 0 (case 6a makes this case unnecessary)
8832 7a 1 0 4
8833 b 2 0 1
8834 c 1 1 2 (case 7b makes this case unnecessary)
8835 d 0 1 5 (case 7a makes this case unnecessary)
8836 e 0 2 3 (case 7b makes this case unnecessary)
8837 f 0 3 1 (case 7b makes this case unnecessary)
8838 g 1 2 1 (case 7b makes this case unnecessary)
8839*/
8840
8841static long
7fa3d080
BW		 8842bytes_to_stretch (fragS *this_frag,
8843 int wide_nops,
8844 int narrow_nops,
8845 int num_widens,
8846 int desired_diff)
43cd72b9
BW		 8847{
8848 int bytes_short = desired_diff - num_widens;
8849
8850 assert (desired_diff >= 0 && desired_diff < 8);
8851 if (desired_diff == 0)
8852 return 0;
8853
8854 assert (wide_nops > 0 || num_widens > 0);
e0001a05 8855
43cd72b9
BW		 8856 /* Always prefer widening to NOP-filling. */
8857 if (bytes_short < 0)
8858 {
8859 /* There are enough RELAX_NARROW frags after this one
8860 to align the target without widening this frag in any way. */
8861 return 0;
8862 }
8863
8864 if (bytes_short == 0)
8865 {
8866 /* Widen every narrow between here and the align target
8867 and the align target will be properly aligned. */
8868 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8869 return 0;
8870 else
8871 return 1;
8872 }
8873
8874 /* From here we will need at least one NOP to get an alignment.
8875 However, we may not be able to align at all, in which case,
8876 don't widen. */
8877 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8878 {
8879 switch (desired_diff)
8880 {
8881 case 1:
8882 return 0;
8883 case 2:
8884 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
8885 return 2; /* case 2 */
8886 return 0;
8887 case 3:
8888 if (wide_nops > 1)
8889 return 0;
8890 else
8891 return 3; /* case 3a */
8892 case 4:
8893 if (num_widens >= 1 && wide_nops == 1)
8894 return 3; /* case 4a */
8895 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
8896 return 2; /* case 4b */
8897 return 0;
8898 case 5:
8899 if (num_widens >= 2 && wide_nops == 1)
8900 return 3; /* case 5a */
8901 /* We will need two nops. Are there enough nops
8902 between here and the align target? */
8903 if (wide_nops < 2 || narrow_nops == 0)
8904 return 0;
8905 /* Are there other nops closer that can serve instead? */
8906 if (wide_nops > 2 && narrow_nops > 1)
8907 return 0;
8908 /* Take the density one first, because there might not be
8909 another density one available. */
8910 if (!this_frag->tc_frag_data.is_no_density)
8911 return 2; /* case 5b narrow */
8912 else
8913 return 3; /* case 5b wide */
8914 return 0;
8915 case 6:
8916 if (wide_nops == 2)
8917 return 3; /* case 6a */
8918 else if (num_widens >= 3 && wide_nops == 1)
8919 return 3; /* case 6b */
8920 return 0;
8921 case 7:
8922 if (wide_nops == 1 && num_widens >= 4)
8923 return 3; /* case 7a */
8924 else if (wide_nops == 2 && num_widens >= 1)
8925 return 3; /* case 7b */
8926 return 0;
e0001a05 8927 default:
43cd72b9 8928 assert (0);
e0001a05 8929 }
e0001a05 8930 }
43cd72b9
BW		 8931 else
8932 {
8933 /* We will need a NOP no matter what, but should we widen
8934 this instruction to help?
e0001a05 8935
43cd72b9
BW		 8936 This is a RELAX_FRAG_NARROW frag. */
8937 switch (desired_diff)
8938 {
8939 case 1:
8940 assert (0);
8941 return 0;
8942 case 2:
8943 case 3:
8944 return 0;
8945 case 4:
8946 if (wide_nops >= 1 && num_widens == 1)
8947 return 1; /* case 4a */
8948 return 0;
8949 case 5:
8950 if (wide_nops >= 1 && num_widens == 2)
8951 return 1; /* case 5a */
8952 return 0;
8953 case 6:
8954 if (wide_nops >= 2)
8955 return 0; /* case 6a */
8956 else if (wide_nops >= 1 && num_widens == 3)
8957 return 1; /* case 6b */
8958 return 0;
8959 case 7:
8960 if (wide_nops >= 1 && num_widens == 4)
8961 return 1; /* case 7a */
8962 else if (wide_nops >= 2 && num_widens == 1)
8963 return 1; /* case 7b */
8964 return 0;
8965 default:
8966 assert (0);
8967 return 0;
8968 }
8969 }
8970 assert (0);
8971 return 0;
e0001a05
NC		 8972}
8973
8974
8975static long
7fa3d080
BW		 8976relax_frag_immed (segT segP,
8977 fragS *fragP,
8978 long stretch,
8979 int min_steps,
8980 xtensa_format fmt,
8981 int slot,
8982 int *stretched_p,
8983 bfd_boolean estimate_only)
e0001a05 8984{
43cd72b9
BW		 8985 TInsn tinsn;
8986 vliw_insn orig_vinsn;
e0001a05
NC		 8987 int old_size;
8988 bfd_boolean negatable_branch = FALSE;
8989 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 8990 bfd_boolean wide_insn = FALSE;
8991 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 8992 IStack istack;
8993 offsetT frag_offset;
8994 int num_steps;
8995 fragS *lit_fragP;
8996 int num_text_bytes, num_literal_bytes;
43cd72b9 8997 int literal_diff, total_text_diff, this_text_diff, first;
e0001a05
NC		 8998
8999 assert (fragP->fr_opcode != NULL);
9000
43cd72b9
BW		 9001 xg_init_vinsn (&orig_vinsn);
9002 vinsn_from_chars (&orig_vinsn, fragP->fr_opcode);
9003 if (xtensa_format_num_slots (isa, fmt) > 1)
9004 wide_insn = TRUE;
9005
9006 tinsn = orig_vinsn.slots[slot];
9007 tinsn_immed_from_frag (&tinsn, fragP, slot);
e0001a05 9008
43cd72b9
BW		 9009 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
9010 return 0;
e0001a05 9011
b08b5071 9012 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
43cd72b9 9013 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
e0001a05 9014
43cd72b9 9015 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
e0001a05 9016
43cd72b9 9017 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 9018
9019 /* Special case: replace a branch to the next instruction with a NOP.
9020 This is required to work around a hardware bug in T1040.0 and also
9021 serves as an optimization. */
9022
9023 if (branch_jmp_to_next
9024 && ((old_size == 2) || (old_size == 3))
9025 && !next_frag_is_loop_target (fragP))
9026 return 0;
9027
9028 /* Here is the fun stuff: Get the immediate field from this
9029 instruction. If it fits, we are done. If not, find the next
9030 instruction sequence that fits. */
9031
9032 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9033 istack_init (&istack);
43cd72b9 9034 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
e0001a05
NC		 9035 min_steps, stretch);
9036 if (num_steps < min_steps)
9037 {
9038 as_fatal (_("internal error: relaxation failed"));
9039 return 0;
9040 }
9041
9042 if (num_steps > RELAX_IMMED_MAXSTEPS)
9043 {
9044 as_fatal (_("internal error: relaxation requires too many steps"));
9045 return 0;
9046 }
9047
43cd72b9 9048 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
e0001a05
NC		 9049
9050 /* Figure out the number of bytes needed. */
9051 lit_fragP = 0;
e0001a05 9052 num_literal_bytes = get_num_stack_literal_bytes (&istack);
43cd72b9
BW		 9053 literal_diff =
9054 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9055 first = 0;
9056 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9057 first++;
9058 num_text_bytes = get_num_stack_text_bytes (&istack);
9059 if (wide_insn)
9060 {
9061 num_text_bytes += old_size;
9062 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9063 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9064 }
9065 total_text_diff = num_text_bytes - old_size;
9066 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
e0001a05
NC		 9067
9068 /* It MUST get larger. If not, we could get an infinite loop. */
43cd72b9
BW		 9069 assert (num_text_bytes >= 0);
9070 assert (literal_diff >= 0);
9071 assert (total_text_diff >= 0);
e0001a05 9072
43cd72b9
BW		 9073 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9074 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9075 assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9076 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
e0001a05
NC		 9077
9078 /* Find the associated expandable literal for this. */
9079 if (literal_diff != 0)
9080 {
43cd72b9 9081 lit_fragP = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9082 if (lit_fragP)
9083 {
9084 assert (literal_diff == 4);
9085 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9086
9087 /* We expect that the literal section state has NOT been
9088 modified yet. */
9089 assert (lit_fragP->fr_type == rs_machine_dependent
9090 && lit_fragP->fr_subtype == RELAX_LITERAL);
9091 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9092
9093 /* We need to mark this section for another iteration
9094 of relaxation. */
9095 (*stretched_p)++;
9096 }
9097 }
9098
43cd72b9 9099 if (negatable_branch && istack.ninsn > 1)
1d19a770 9100 update_next_frag_state (fragP);
e0001a05 9101
43cd72b9 9102 return this_text_diff;
e0001a05
NC		 9103}
9104
9105\f
9106/* md_convert_frag Hook and Helper Functions. */
9107
7fa3d080
BW		 9108static void convert_frag_align_next_opcode (fragS *);
9109static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
9110static void convert_frag_fill_nop (fragS *);
9111static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
9112
e0001a05 9113void
7fa3d080 9114md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
e0001a05 9115{
43cd72b9
BW		 9116 static xtensa_insnbuf vbuf = NULL;
9117 xtensa_isa isa = xtensa_default_isa;
9118 int slot;
9119 int num_slots;
9120 xtensa_format fmt;
e0001a05
NC		 9121 char *file_name;
9122 int line;
9123
9124 as_where (&file_name, &line);
9125 new_logical_line (fragp->fr_file, fragp->fr_line);
9126
9127 switch (fragp->fr_subtype)
9128 {
9129 case RELAX_ALIGN_NEXT_OPCODE:
9130 /* Always convert. */
9131 convert_frag_align_next_opcode (fragp);
9132 break;
9133
9134 case RELAX_DESIRE_ALIGN:
9135 /* Do nothing. If not aligned already, too bad. */
9136 break;
9137
43cd72b9
BW		 9138 case RELAX_LITERAL:
9139 case RELAX_LITERAL_FINAL:
9140 break;
9141
9142 case RELAX_SLOTS:
9143 if (vbuf == NULL)
9144 vbuf = xtensa_insnbuf_alloc (isa);
9145
9146 xtensa_insnbuf_from_chars (isa, vbuf, fragp->fr_opcode, 0);
9147 fmt = xtensa_format_decode (isa, vbuf);
9148 num_slots = xtensa_format_num_slots (isa, fmt);
9149
9150 for (slot = 0; slot < num_slots; slot++)
9151 {
9152 switch (fragp->tc_frag_data.slot_subtypes[slot])
9153 {
9154 case RELAX_NARROW:
9155 convert_frag_narrow (sec, fragp, fmt, slot);
9156 break;
9157
9158 case RELAX_IMMED:
9159 case RELAX_IMMED_STEP1:
9160 case RELAX_IMMED_STEP2:
9161 /* Place the immediate. */
9162 convert_frag_immed
9163 (sec, fragp,
9164 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9165 fmt, slot);
9166 break;
9167
9168 default:
9169 /* This is OK because some slots could have
9170 relaxations and others have none. */
9171 break;
9172 }
9173 }
9174 break;
9175
9176 case RELAX_UNREACHABLE:
9177 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9178 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9179 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9180 frag_wane (fragp);
e0001a05
NC		 9181 break;
9182
43cd72b9
BW		 9183 case RELAX_MAYBE_UNREACHABLE:
9184 case RELAX_MAYBE_DESIRE_ALIGN:
9185 frag_wane (fragp);
e0001a05
NC		 9186 break;
9187
43cd72b9
BW		 9188 case RELAX_FILL_NOP:
9189 convert_frag_fill_nop (fragp);
e0001a05
NC		 9190 break;
9191
9192 case RELAX_LITERAL_NR:
9193 if (use_literal_section)
9194 {
9195 /* This should have been handled during relaxation. When
9196 relaxing a code segment, literals sometimes need to be
9197 added to the corresponding literal segment. If that
9198 literal segment has already been relaxed, then we end up
9199 in this situation. Marking the literal segments as data
9200 would make this happen less often (since GAS always relaxes
9201 code before data), but we could still get into trouble if
9202 there are instructions in a segment that is not marked as
9203 containing code. Until we can implement a better solution,
9204 cheat and adjust the addresses of all the following frags.
9205 This could break subsequent alignments, but the linker's
9206 literal coalescing will do that anyway. */
9207
9208 fragS *f;
9209 fragp->fr_subtype = RELAX_LITERAL_FINAL;
9210 assert (fragp->tc_frag_data.unreported_expansion == 4);
9211 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9212 fragp->fr_var -= 4;
9213 fragp->fr_fix += 4;
9214 for (f = fragp->fr_next; f; f = f->fr_next)
9215 f->fr_address += 4;
9216 }
9217 else
9218 as_bad (_("invalid relaxation fragment result"));
9219 break;
9220 }
9221
9222 fragp->fr_var = 0;
9223 new_logical_line (file_name, line);
9224}
9225
9226
7fa3d080
BW		 9227static void
9228convert_frag_align_next_opcode (fragS *fragp)
e0001a05
NC		 9229{
9230 char *nop_buf; /* Location for Writing. */
9231 size_t i;
9232
9233 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9234 addressT aligned_address;
9235 size_t fill_size, nop_count;
9236
9237 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9238 fragp->fr_fix);
9239 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9240 nop_count = get_text_align_nop_count (fill_size, use_no_density);
9241 nop_buf = fragp->fr_literal + fragp->fr_fix;
9242
9243 for (i = 0; i < nop_count; i++)
9244 {
9245 size_t nop_size;
9246 nop_size = get_text_align_nth_nop_size (fill_size, i, use_no_density);
9247
9248 assemble_nop (nop_size, nop_buf);
9249 nop_buf += nop_size;
9250 }
9251
9252 fragp->fr_fix += fill_size;
9253 fragp->fr_var -= fill_size;
9254}
9255
9256
9257static void
7fa3d080 9258convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
e0001a05 9259{
43cd72b9
BW		 9260 TInsn tinsn, single_target;
9261 xtensa_format single_fmt;
e0001a05
NC		 9262 int size, old_size, diff, error_val;
9263 offsetT frag_offset;
9264
43cd72b9
BW		 9265 assert (slot == 0);
9266 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9267
9268 if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1)
9269 {
9270 assert (fragP->tc_frag_data.text_expansion[0] == 1
9271 || fragP->tc_frag_data.text_expansion[0] == 0);
9272 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9273 fmt, slot);
9274 return;
9275 }
9276
9277 if (fragP->tc_frag_data.text_expansion[0] == 0)
e0001a05
NC		 9278 {
9279 /* No conversion. */
9280 fragP->fr_var = 0;
9281 return;
9282 }
9283
9284 assert (fragP->fr_opcode != NULL);
9285
43cd72b9
BW		 9286 /* Frags in this relaxation state should only contain
9287 single instruction bundles. */
9288 tinsn_immed_from_frag (&tinsn, fragP, 0);
e0001a05
NC		 9289
9290 /* Just convert it to a wide form.... */
9291 size = 0;
43cd72b9 9292 old_size = xg_get_single_size (tinsn.opcode);
e0001a05
NC		 9293
9294 tinsn_init (&single_target);
9295 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9296
43cd72b9 9297 error_val = xg_expand_narrow (&single_target, &tinsn);
e0001a05 9298 if (error_val)
43cd72b9
BW		 9299 {
9300 as_bad (_("unable to widen instruction"));
9301 return;
9302 }
9303
9304 size = xg_get_single_size (single_target.opcode);
9305 single_fmt = xg_get_single_format (single_target.opcode);
e0001a05 9306
43cd72b9 9307 xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode,
e0001a05
NC		 9308 fragP, frag_offset, TRUE);
9309
9310 diff = size - old_size;
9311 assert (diff >= 0);
9312 assert (diff <= fragP->fr_var);
9313 fragP->fr_var -= diff;
9314 fragP->fr_fix += diff;
9315
9316 /* clean it up */
9317 fragP->fr_var = 0;
9318}
9319
9320
9321static void
7fa3d080 9322convert_frag_fill_nop (fragS *fragP)
43cd72b9
BW		 9323{
9324 char *loc = &fragP->fr_literal[fragP->fr_fix];
9325 int size = fragP->tc_frag_data.text_expansion[0];
9326 assert ((unsigned) size == (fragP->fr_next->fr_address
9327 - fragP->fr_address - fragP->fr_fix));
9328 if (size == 0)
9329 {
9330 /* No conversion. */
9331 fragP->fr_var = 0;
9332 return;
9333 }
9334 assemble_nop (size, loc);
9335 fragP->tc_frag_data.is_insn = TRUE;
9336 fragP->fr_var -= size;
9337 fragP->fr_fix += size;
9338 frag_wane (fragP);
9339}
9340
9341
7fa3d080
BW		 9342static fixS *fix_new_exp_in_seg
9343 (segT, subsegT, fragS *, int, int, expressionS *, int,
9344 bfd_reloc_code_real_type);
9345static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9346
43cd72b9 9347static void
7fa3d080
BW		 9348convert_frag_immed (segT segP,
9349 fragS *fragP,
9350 int min_steps,
9351 xtensa_format fmt,
9352 int slot)
e0001a05
NC		 9353{
9354 char *immed_instr = fragP->fr_opcode;
43cd72b9 9355 TInsn orig_tinsn;
e0001a05 9356 bfd_boolean expanded = FALSE;
e0001a05 9357 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 9358 char *fr_opcode = fragP->fr_opcode;
9359 vliw_insn orig_vinsn;
9360 xtensa_isa isa = xtensa_default_isa;
9361 bfd_boolean wide_insn = FALSE;
9362 int bytes;
9363 bfd_boolean is_loop;
e0001a05 9364
43cd72b9 9365 assert (fr_opcode != NULL);
e0001a05 9366
43cd72b9 9367 xg_init_vinsn (&orig_vinsn);
e0001a05 9368
43cd72b9
BW		 9369 vinsn_from_chars (&orig_vinsn, fr_opcode);
9370 if (xtensa_format_num_slots (isa, fmt) > 1)
9371 wide_insn = TRUE;
e0001a05 9372
43cd72b9
BW		 9373 orig_tinsn = orig_vinsn.slots[slot];
9374 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9375
9376 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
e0001a05 9377
b08b5071 9378 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
43cd72b9 9379 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
e0001a05
NC		 9380
9381 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9382 {
9383 /* Conversion just inserts a NOP and marks the fix as completed. */
43cd72b9
BW		 9384 bytes = xtensa_format_length (isa, fmt);
9385 if (bytes >= 4)
9386 {
9387 orig_vinsn.slots[slot].opcode =
9388 xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot);
9389 orig_vinsn.slots[slot].ntok = 0;
9390 }
9391 else
9392 {
9393 bytes += fragP->tc_frag_data.text_expansion[0];
9394 assert (bytes == 2 || bytes == 3);
9395 build_nop (&orig_vinsn.slots[0], bytes);
9396 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9397 }
9398 vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE);
9399 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf, fr_opcode, 0);
e0001a05
NC		 9400 fragP->fr_var = 0;
9401 }
43cd72b9 9402 else if (!orig_tinsn.is_specific_opcode)
e0001a05 9403 {
43cd72b9
BW		 9404 /* Here is the fun stuff: Get the immediate field from this
9405 instruction. If it fits, we're done. If not, find the next
9406 instruction sequence that fits. */
9407
e0001a05
NC		 9408 IStack istack;
9409 int i;
9410 symbolS *lit_sym = NULL;
9411 int total_size = 0;
43cd72b9 9412 int target_offset = 0;
e0001a05
NC		 9413 int old_size;
9414 int diff;
9415 symbolS *gen_label = NULL;
9416 offsetT frag_offset;
43cd72b9
BW		 9417 bfd_boolean first = TRUE;
9418 bfd_boolean last_is_jump;
e0001a05 9419
43cd72b9 9420 /* It does not fit. Find something that does and
e0001a05 9421 convert immediately. */
43cd72b9 9422 frag_offset = fr_opcode - fragP->fr_literal;
e0001a05 9423 istack_init (&istack);
43cd72b9 9424 xg_assembly_relax (&istack, &orig_tinsn,
e0001a05
NC		 9425 segP, fragP, frag_offset, min_steps, 0);
9426
43cd72b9 9427 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 9428
9429 /* Assemble this right inline. */
9430
9431 /* First, create the mapping from a label name to the REAL label. */
43cd72b9 9432 target_offset = 0;
e0001a05
NC		 9433 for (i = 0; i < istack.ninsn; i++)
9434 {
43cd72b9 9435 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 9436 fragS *lit_frag;
9437
43cd72b9 9438 switch (tinsn->insn_type)
e0001a05
NC		 9439 {
9440 case ITYPE_LITERAL:
9441 if (lit_sym != NULL)
9442 as_bad (_("multiple literals in expansion"));
9443 /* First find the appropriate space in the literal pool. */
43cd72b9 9444 lit_frag = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9445 if (lit_frag == NULL)
9446 as_bad (_("no registered fragment for literal"));
43cd72b9 9447 if (tinsn->ntok != 1)
e0001a05
NC		 9448 as_bad (_("number of literal tokens != 1"));
9449
9450 /* Set the literal symbol and add a fixup. */
9451 lit_sym = lit_frag->fr_symbol;
9452 break;
9453
9454 case ITYPE_LABEL:
43cd72b9
BW		 9455 if (align_targets && !is_loop)
9456 {
9457 fragS *unreach = fragP->fr_next;
9458 while (!(unreach->fr_type == rs_machine_dependent
9459 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9460 || unreach->fr_subtype == RELAX_UNREACHABLE)))
9461 {
9462 unreach = unreach->fr_next;
9463 }
9464
9465 assert (unreach->fr_type == rs_machine_dependent
9466 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9467 || unreach->fr_subtype == RELAX_UNREACHABLE));
9468
9469 target_offset += unreach->tc_frag_data.text_expansion[0];
9470 }
e0001a05
NC		 9471 assert (gen_label == NULL);
9472 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
43cd72b9
BW		 9473 fr_opcode - fragP->fr_literal
9474 + target_offset, fragP);
e0001a05
NC		 9475 break;
9476
9477 case ITYPE_INSN:
43cd72b9
BW		 9478 if (first && wide_insn)
9479 {
9480 target_offset += xtensa_format_length (isa, fmt);
9481 first = FALSE;
9482 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9483 target_offset += xg_get_single_size (tinsn->opcode);
9484 }
9485 else
9486 target_offset += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 9487 break;
9488 }
9489 }
9490
9491 total_size = 0;
43cd72b9
BW		 9492 first = TRUE;
9493 last_is_jump = FALSE;
e0001a05
NC		 9494 for (i = 0; i < istack.ninsn; i++)
9495 {
43cd72b9 9496 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 9497 fragS *lit_frag;
9498 int size;
9499 segT target_seg;
43cd72b9 9500 bfd_reloc_code_real_type reloc_type;
e0001a05 9501
43cd72b9 9502 switch (tinsn->insn_type)
e0001a05
NC		 9503 {
9504 case ITYPE_LITERAL:
43cd72b9
BW		 9505 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9506 /* Already checked. */
e0001a05
NC		 9507 assert (lit_frag != NULL);
9508 assert (lit_sym != NULL);
43cd72b9
BW		 9509 assert (tinsn->ntok == 1);
9510 /* Add a fixup. */
e0001a05
NC		 9511 target_seg = S_GET_SEGMENT (lit_sym);
9512 assert (target_seg);
43cd72b9
BW		 9513 if (tinsn->tok[0].X_op == O_pltrel)
9514 reloc_type = BFD_RELOC_XTENSA_PLT;
9515 else
9516 reloc_type = BFD_RELOC_32;
e0001a05 9517 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
43cd72b9 9518 &tinsn->tok[0], FALSE, reloc_type);
e0001a05
NC		 9519 break;
9520
9521 case ITYPE_LABEL:
9522 break;
9523
9524 case ITYPE_INSN:
43cd72b9
BW		 9525 xg_resolve_labels (tinsn, gen_label);
9526 xg_resolve_literals (tinsn, lit_sym);
9527 if (wide_insn && first)
9528 {
9529 first = FALSE;
9530 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9531 {
9532 tinsn->record_fix = TRUE;
9533 orig_vinsn.slots[slot] = *tinsn;
9534 }
9535 else
9536 {
9537 orig_vinsn.slots[slot].opcode =
9538 xtensa_format_slot_nop_opcode (isa, fmt, slot);
9539 orig_vinsn.slots[slot].ntok = 0;
9540 orig_vinsn.slots[slot].record_fix = FALSE;
9541 }
9542 vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE);
9543 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf,
9544 immed_instr, 0);
9545 fragP->tc_frag_data.is_insn = TRUE;
9546 size = xtensa_format_length (isa, fmt);
9547 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9548 {
9549 xtensa_format single_fmt =
9550 xg_get_single_format (tinsn->opcode);
9551
9552 xg_emit_insn_to_buf
9553 (tinsn, single_fmt, immed_instr + size, fragP,
9554 immed_instr - fragP->fr_literal + size, TRUE);
9555 size += xg_get_single_size (tinsn->opcode);
9556 }
9557 }
9558 else
9559 {
9560 xtensa_format single_format;
9561 size = xg_get_single_size (tinsn->opcode);
9562 single_format = xg_get_single_format (tinsn->opcode);
9563 xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
9564 fragP,
9565 immed_instr - fragP->fr_literal, TRUE);
43cd72b9 9566 }
e0001a05 9567 immed_instr += size;
43cd72b9 9568 total_size += size;
e0001a05
NC		 9569 break;
9570 }
9571 }
9572
9573 diff = total_size - old_size;
9574 assert (diff >= 0);
9575 if (diff != 0)
9576 expanded = TRUE;
9577 assert (diff <= fragP->fr_var);
9578 fragP->fr_var -= diff;
9579 fragP->fr_fix += diff;
9580 }
9581
9582 /* Clean it up. */
43cd72b9 9583 xg_free_vinsn (&orig_vinsn);
e0001a05
NC		 9584
9585 /* Check for undefined immediates in LOOP instructions. */
43cd72b9 9586 if (is_loop)
e0001a05
NC		 9587 {
9588 symbolS *sym;
43cd72b9 9589 sym = orig_tinsn.tok[1].X_add_symbol;
e0001a05
NC		 9590 if (sym != NULL && !S_IS_DEFINED (sym))
9591 {
9592 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9593 return;
9594 }
43cd72b9 9595 sym = orig_tinsn.tok[1].X_op_symbol;
e0001a05
NC		 9596 if (sym != NULL && !S_IS_DEFINED (sym))
9597 {
9598 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9599 return;
9600 }
9601 }
9602
43cd72b9
BW		 9603 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9604 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
e0001a05 9605
43cd72b9 9606 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
e0001a05
NC		 9607 {
9608 /* Add an expansion note on the expanded instruction. */
9609 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
43cd72b9 9610 &orig_tinsn.tok[0], TRUE,
e0001a05 9611 BFD_RELOC_XTENSA_ASM_EXPAND);
e0001a05
NC		 9612 }
9613}
9614
9615
9616/* Add a new fix expression into the desired segment. We have to
9617 switch to that segment to do this. */
9618
9619static fixS *
7fa3d080
BW		 9620fix_new_exp_in_seg (segT new_seg,
9621 subsegT new_subseg,
9622 fragS *frag,
9623 int where,
9624 int size,
9625 expressionS *exp,
9626 int pcrel,
9627 bfd_reloc_code_real_type r_type)
e0001a05
NC		 9628{
9629 fixS *new_fix;
9630 segT seg = now_seg;
9631 subsegT subseg = now_subseg;
43cd72b9 9632
e0001a05
NC		 9633 assert (new_seg != 0);
9634 subseg_set (new_seg, new_subseg);
9635
e0001a05
NC		 9636 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9637 subseg_set (seg, subseg);
9638 return new_fix;
9639}
9640
9641
43cd72b9
BW		 9642/* Relax a loop instruction so that it can span loop >256 bytes.
9643
9644 loop as, .L1
9645 .L0:
9646 rsr as, LEND
9647 wsr as, LBEG
9648 addi as, as, lo8 (label-.L1)
9649 addmi as, as, mid8 (label-.L1)
9650 wsr as, LEND
9651 isync
9652 rsr as, LCOUNT
9653 addi as, as, 1
9654 .L1:
9655 <<body>>
9656 label:
9657*/
e0001a05
NC		 9658
9659static void
7fa3d080 9660convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
e0001a05
NC		 9661{
9662 TInsn loop_insn;
9663 TInsn addi_insn;
9664 TInsn addmi_insn;
9665 unsigned long target;
9666 static xtensa_insnbuf insnbuf = NULL;
9667 unsigned int loop_length, loop_length_hi, loop_length_lo;
9668 xtensa_isa isa = xtensa_default_isa;
9669 addressT loop_offset;
9670 addressT addi_offset = 9;
9671 addressT addmi_offset = 12;
43cd72b9
BW		 9672 fragS *next_fragP;
9673 size_t target_count;
e0001a05
NC		 9674
9675 if (!insnbuf)
9676 insnbuf = xtensa_insnbuf_alloc (isa);
9677
9678 /* Get the loop offset. */
43cd72b9 9679 loop_offset = get_expanded_loop_offset (tinsn->opcode);
e0001a05 9680
43cd72b9
BW		 9681 /* Validate that there really is a LOOP at the loop_offset. Because
9682 loops are not bundleable, we can assume that the instruction will be
9683 in slot 0. */
9684 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9685 tinsn_immed_from_frag (&loop_insn, fragP, 0);
9686
9687 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
e0001a05
NC		 9688 addi_offset += loop_offset;
9689 addmi_offset += loop_offset;
9690
43cd72b9 9691 assert (tinsn->ntok == 2);
b08b5071
BW		 9692 if (tinsn->tok[1].X_op == O_constant)
9693 target = tinsn->tok[1].X_add_number;
9694 else if (tinsn->tok[1].X_op == O_symbol)
9695 {
9696 /* Find the fragment. */
9697 symbolS *sym = tinsn->tok[1].X_add_symbol;
9698 assert (S_GET_SEGMENT (sym) == segP
9699 || S_GET_SEGMENT (sym) == absolute_section);
9700 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
9701 }
9702 else
9703 {
9704 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
9705 target = 0;
9706 }
e0001a05
NC		 9707
9708 know (symbolP);
9709 know (symbolP->sy_frag);
9710 know (!(S_GET_SEGMENT (symbolP) == absolute_section)
9711 || symbol_get_frag (symbolP) == &zero_address_frag);
9712
9713 loop_length = target - (fragP->fr_address + fragP->fr_fix);
9714 loop_length_hi = loop_length & ~0x0ff;
9715 loop_length_lo = loop_length & 0x0ff;
9716 if (loop_length_lo >= 128)
9717 {
9718 loop_length_lo -= 256;
9719 loop_length_hi += 256;
9720 }
9721
43cd72b9 9722 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
e0001a05
NC		 9723 32512. If the loop is larger than that, then we just fail. */
9724 if (loop_length_hi > 32512)
9725 as_bad_where (fragP->fr_file, fragP->fr_line,
9726 _("loop too long for LOOP instruction"));
9727
43cd72b9 9728 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 9729 assert (addi_insn.opcode == xtensa_addi_opcode);
9730
43cd72b9 9731 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
e0001a05
NC		 9732 assert (addmi_insn.opcode == xtensa_addmi_opcode);
9733
9734 set_expr_const (&addi_insn.tok[2], loop_length_lo);
9735 tinsn_to_insnbuf (&addi_insn, insnbuf);
43cd72b9 9736
e0001a05 9737 fragP->tc_frag_data.is_insn = TRUE;
43cd72b9 9738 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 9739
9740 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9741 tinsn_to_insnbuf (&addmi_insn, insnbuf);
43cd72b9
BW		 9742 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addmi_offset, 0);
9743
9744 /* Walk through all of the frags from here to the loop end
9745 and mark them as no_transform to keep them from being modified
9746 by the linker. If we ever have a relocation for the
9747 addi/addmi of the difference of two symbols we can remove this. */
9748
9749 target_count = 0;
9750 for (next_fragP = fragP; next_fragP != NULL;
9751 next_fragP = next_fragP->fr_next)
9752 {
b08b5071 9753 next_fragP->tc_frag_data.is_no_transform = TRUE;
43cd72b9
BW		 9754 if (next_fragP->tc_frag_data.is_loop_target)
9755 target_count++;
9756 if (target_count == 2)
9757 break;
9758 }
e0001a05
NC		 9759}
9760
b08b5071
BW		 9761\f
9762/* A map that keeps information on a per-subsegment basis. This is
9763 maintained during initial assembly, but is invalid once the
9764 subsegments are smashed together. I.E., it cannot be used during
9765 the relaxation. */
e0001a05 9766
b08b5071 9767typedef struct subseg_map_struct
e0001a05 9768{
b08b5071
BW		 9769 /* the key */
9770 segT seg;
9771 subsegT subseg;
e0001a05 9772
b08b5071
BW		 9773 /* the data */
9774 unsigned flags;
9775 float total_freq; /* fall-through + branch target frequency */
9776 float target_freq; /* branch target frequency alone */
9777
9778 struct subseg_map_struct *next;
9779} subseg_map;
e0001a05 9780
e0001a05 9781
e0001a05
NC		 9782static subseg_map *sseg_map = NULL;
9783
43cd72b9 9784static subseg_map *
7fa3d080 9785get_subseg_info (segT seg, subsegT subseg)
e0001a05
NC		 9786{
9787 subseg_map *subseg_e;
9788
9789 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
e0001a05 9790 {
43cd72b9 9791 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
b08b5071 9792 break;
e0001a05 9793 }
b08b5071
BW		 9794 return subseg_e;
9795}
9796
9797
9798static subseg_map *
9799add_subseg_info (segT seg, subsegT subseg)
9800{
9801 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
43cd72b9
BW		 9802 memset (subseg_e, 0, sizeof (subseg_map));
9803 subseg_e->seg = seg;
9804 subseg_e->subseg = subseg;
9805 subseg_e->flags = 0;
9806 /* Start off considering every branch target very important. */
b08b5071
BW		 9807 subseg_e->target_freq = 1.0;
9808 subseg_e->total_freq = 1.0;
43cd72b9
BW		 9809 subseg_e->next = sseg_map;
9810 sseg_map = subseg_e;
43cd72b9
BW		 9811 return subseg_e;
9812}
e0001a05 9813
7fa3d080
BW		 9814
9815static unsigned
9816get_last_insn_flags (segT seg, subsegT subseg)
9817{
9818 subseg_map *subseg_e = get_subseg_info (seg, subseg);
b08b5071
BW		 9819 if (subseg_e)
9820 return subseg_e->flags;
9821 return 0;
7fa3d080
BW		 9822}
9823
9824
43cd72b9 9825static void
7fa3d080
BW		 9826set_last_insn_flags (segT seg,
9827 subsegT subseg,
9828 unsigned fl,
9829 bfd_boolean val)
43cd72b9
BW		 9830{
9831 subseg_map *subseg_e = get_subseg_info (seg, subseg);
b08b5071
BW		 9832 if (! subseg_e)
9833 subseg_e = add_subseg_info (seg, subseg);
e0001a05
NC		 9834 if (val)
9835 subseg_e->flags |= fl;
9836 else
9837 subseg_e->flags &= ~fl;
9838}
9839
b08b5071
BW		 9840
9841static float
9842get_subseg_total_freq (segT seg, subsegT subseg)
9843{
9844 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9845 if (subseg_e)
9846 return subseg_e->total_freq;
9847 return 1.0;
9848}
9849
9850
9851static float
9852get_subseg_target_freq (segT seg, subsegT subseg)
9853{
9854 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9855 if (subseg_e)
9856 return subseg_e->target_freq;
9857 return 1.0;
9858}
9859
9860
9861static void
9862set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
9863{
9864 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9865 if (! subseg_e)
9866 subseg_e = add_subseg_info (seg, subseg);
9867 subseg_e->total_freq = total_f;
9868 subseg_e->target_freq = target_f;
9869}
9870
e0001a05
NC		 9871\f
9872/* Segment Lists and emit_state Stuff. */
9873
9874/* Remove the segment from the global sections list. */
9875
9876static void
7fa3d080 9877xtensa_remove_section (segT sec)
e0001a05
NC		 9878{
9879 /* Handle brain-dead bfd_section_list_remove macro, which
9880 expect the address of the prior section's "next" field, not
9881 just the address of the section to remove. */
9882
9883 segT *ps_next_ptr = &stdoutput->sections;
9884 while (*ps_next_ptr != sec && *ps_next_ptr != NULL)
9885 ps_next_ptr = &(*ps_next_ptr)->next;
9886
9887 assert (*ps_next_ptr != NULL);
9888
9889 bfd_section_list_remove (stdoutput, ps_next_ptr);
9890}
9891
9892
9893static void
7fa3d080 9894xtensa_insert_section (segT after_sec, segT sec)
e0001a05
NC		 9895{
9896 segT *after_sec_next;
9897 if (after_sec == NULL)
9898 after_sec_next = &stdoutput->sections;
9899 else
9900 after_sec_next = &after_sec->next;
9901
9902 bfd_section_list_insert (stdoutput, after_sec_next, sec);
9903}
9904
9905
9906static void
7fa3d080 9907xtensa_move_seg_list_to_beginning (seg_list *head)
e0001a05
NC		 9908{
9909 head = head->next;
9910 while (head)
9911 {
9912 segT literal_section = head->seg;
9913
9914 /* Move the literal section to the front of the section list. */
9915 assert (literal_section);
9916 xtensa_remove_section (literal_section);
9917 xtensa_insert_section (NULL, literal_section);
9918
9919 head = head->next;
9920 }
9921}
9922
9923
7fa3d080
BW		 9924static void mark_literal_frags (seg_list *);
9925
9926static void
9927xtensa_move_literals (void)
e0001a05
NC		 9928{
9929 seg_list *segment;
9930 frchainS *frchain_from, *frchain_to;
9931 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
9932 fragS **frag_splice;
9933 emit_state state;
9934 segT dest_seg;
9935 fixS *fix, *next_fix, **fix_splice;
82e7541d 9936 sym_list *lit;
e0001a05 9937
a7877748
BW		 9938 mark_literal_frags (literal_head->next);
9939 mark_literal_frags (init_literal_head->next);
9940 mark_literal_frags (fini_literal_head->next);
e0001a05
NC		 9941
9942 if (use_literal_section)
9943 return;
9944
9945 segment = literal_head->next;
9946 while (segment)
9947 {
9948 frchain_from = seg_info (segment->seg)->frchainP;
9949 search_frag = frchain_from->frch_root;
9950 literal_pool = NULL;
9951 frchain_to = NULL;
9952 frag_splice = &(frchain_from->frch_root);
9953
9954 while (!search_frag->tc_frag_data.literal_frag)
9955 {
9956 assert (search_frag->fr_fix == 0
9957 || search_frag->fr_type == rs_align);
9958 search_frag = search_frag->fr_next;
9959 }
9960
9961 assert (search_frag->tc_frag_data.literal_frag->fr_subtype
9962 == RELAX_LITERAL_POOL_BEGIN);
9963 xtensa_switch_section_emit_state (&state, segment->seg, 0);
9964
9965 /* Make sure that all the frags in this series are closed, and
9966 that there is at least one left over of zero-size. This
9967 prevents us from making a segment with an frchain without any
9968 frags in it. */
9969 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 9970 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 9971 last_frag = frag_now;
9972 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 9973 xtensa_set_frag_assembly_state (frag_now);
e0001a05 9974
43cd72b9 9975 while (search_frag != frag_now)
e0001a05
NC		 9976 {
9977 next_frag = search_frag->fr_next;
9978
43cd72b9 9979 /* First, move the frag out of the literal section and
e0001a05
NC		 9980 to the appropriate place. */
9981 if (search_frag->tc_frag_data.literal_frag)
9982 {
9983 literal_pool = search_frag->tc_frag_data.literal_frag;
9984 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
43cd72b9 9985 /* Note that we set this fr_var to be a fix
e0001a05
NC		 9986 chain when we created the literal pool location
9987 as RELAX_LITERAL_POOL_BEGIN. */
9988 frchain_to = (frchainS *) literal_pool->fr_var;
9989 }
9990 insert_after = literal_pool;
43cd72b9 9991
e0001a05
NC		 9992 while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
9993 insert_after = insert_after->fr_next;
9994
9995 dest_seg = (segT) insert_after->fr_next->fr_var;
43cd72b9 9996
e0001a05
NC		 9997 *frag_splice = next_frag;
9998 search_frag->fr_next = insert_after->fr_next;
9999 insert_after->fr_next = search_frag;
10000 search_frag->tc_frag_data.lit_seg = dest_seg;
10001
10002 /* Now move any fixups associated with this frag to the
10003 right section. */
10004 fix = frchain_from->fix_root;
10005 fix_splice = &(frchain_from->fix_root);
10006 while (fix)
10007 {
10008 next_fix = fix->fx_next;
10009 if (fix->fx_frag == search_frag)
10010 {
10011 *fix_splice = next_fix;
10012 fix->fx_next = frchain_to->fix_root;
10013 frchain_to->fix_root = fix;
10014 if (frchain_to->fix_tail == NULL)
10015 frchain_to->fix_tail = fix;
10016 }
10017 else
10018 fix_splice = &(fix->fx_next);
10019 fix = next_fix;
10020 }
10021 search_frag = next_frag;
10022 }
10023
10024 if (frchain_from->fix_root != NULL)
10025 {
10026 frchain_from = seg_info (segment->seg)->frchainP;
10027 as_warn (_("fixes not all moved from %s"), segment->seg->name);
10028
10029 assert (frchain_from->fix_root == NULL);
10030 }
10031 frchain_from->fix_tail = NULL;
10032 xtensa_restore_emit_state (&state);
10033 segment = segment->next;
10034 }
10035
82e7541d
BW		 10036 /* Now fix up the SEGMENT value for all the literal symbols. */
10037 for (lit = literal_syms; lit; lit = lit->next)
10038 {
10039 symbolS *lit_sym = lit->sym;
10040 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
43cd72b9
BW		 10041 if (dest_seg)
10042 S_SET_SEGMENT (lit_sym, dest_seg);
82e7541d 10043 }
e0001a05
NC		 10044}
10045
10046
a7877748
BW		 10047/* Walk over all the frags for segments in a list and mark them as
10048 containing literals. As clunky as this is, we can't rely on frag_var
10049 and frag_variant to get called in all situations. */
10050
10051static void
7fa3d080 10052mark_literal_frags (seg_list *segment)
a7877748
BW		 10053{
10054 frchainS *frchain_from;
10055 fragS *search_frag;
10056
10057 while (segment)
10058 {
10059 frchain_from = seg_info (segment->seg)->frchainP;
10060 search_frag = frchain_from->frch_root;
10061 while (search_frag)
10062 {
10063 search_frag->tc_frag_data.is_literal = TRUE;
10064 search_frag = search_frag->fr_next;
10065 }
10066 segment = segment->next;
10067 }
10068}
10069
10070
e0001a05 10071static void
7fa3d080 10072xtensa_reorder_seg_list (seg_list *head, segT after)
e0001a05
NC		 10073{
10074 /* Move all of the sections in the section list to come
10075 after "after" in the gnu segment list. */
10076
10077 head = head->next;
10078 while (head)
10079 {
10080 segT literal_section = head->seg;
10081
10082 /* Move the literal section after "after". */
10083 assert (literal_section);
10084 if (literal_section != after)
10085 {
10086 xtensa_remove_section (literal_section);
10087 xtensa_insert_section (after, literal_section);
10088 }
10089
10090 head = head->next;
10091 }
10092}
10093
10094
10095/* Push all the literal segments to the end of the gnu list. */
10096
7fa3d080
BW		 10097static void
10098xtensa_reorder_segments (void)
e0001a05
NC		 10099{
10100 segT sec;
b08b5071 10101 segT last_sec = 0;
e0001a05
NC		 10102 int old_count = 0;
10103 int new_count = 0;
10104
10105 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
b08b5071
BW		 10106 {
10107 last_sec = sec;
10108 old_count++;
10109 }
e0001a05
NC		 10110
10111 /* Now that we have the last section, push all the literal
10112 sections to the end. */
e0001a05
NC		 10113 xtensa_reorder_seg_list (literal_head, last_sec);
10114 xtensa_reorder_seg_list (init_literal_head, last_sec);
10115 xtensa_reorder_seg_list (fini_literal_head, last_sec);
10116
10117 /* Now perform the final error check. */
10118 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10119 new_count++;
10120 assert (new_count == old_count);
10121}
10122
10123
e0001a05
NC		 10124/* Change the emit state (seg, subseg, and frag related stuff) to the
10125 correct location. Return a emit_state which can be passed to
10126 xtensa_restore_emit_state to return to current fragment. */
10127
7fa3d080
BW		 10128static void
10129xtensa_switch_to_literal_fragment (emit_state *result)
43cd72b9
BW		 10130{
10131 if (directive_state[directive_absolute_literals])
10132 {
10133 cache_literal_section (0, default_lit_sections.lit4_seg_name,
10134 &default_lit_sections.lit4_seg, FALSE);
10135 xtensa_switch_section_emit_state (result,
10136 default_lit_sections.lit4_seg, 0);
10137 }
10138 else
10139 xtensa_switch_to_non_abs_literal_fragment (result);
10140
10141 /* Do a 4-byte align here. */
10142 frag_align (2, 0, 0);
10143 record_alignment (now_seg, 2);
10144}
10145
10146
7fa3d080
BW		 10147static void
10148xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
e0001a05
NC		 10149{
10150 /* When we mark a literal pool location, we want to put a frag in
10151 the literal pool that points to it. But to do that, we want to
10152 switch_to_literal_fragment. But literal sections don't have
10153 literal pools, so their location is always null, so we would
10154 recurse forever. This is kind of hacky, but it works. */
10155
10156 static bfd_boolean recursive = FALSE;
10157 fragS *pool_location = get_literal_pool_location (now_seg);
10158 bfd_boolean is_init =
10159 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
10160
10161 bfd_boolean is_fini =
10162 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
e0001a05 10163
43cd72b9
BW		 10164 if (pool_location == NULL
10165 && !use_literal_section
e0001a05
NC		 10166 && !recursive
10167 && !is_init && ! is_fini)
10168 {
43cd72b9 10169 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
e0001a05 10170 recursive = TRUE;
61846f28 10171 xtensa_mark_literal_pool_location ();
e0001a05
NC		 10172 recursive = FALSE;
10173 }
10174
10175 /* Special case: If we are in the ".fini" or ".init" section, then
10176 we will ALWAYS be generating to the ".fini.literal" and
10177 ".init.literal" sections. */
10178
10179 if (is_init)
10180 {
10181 cache_literal_section (init_literal_head,
10182 default_lit_sections.init_lit_seg_name,
43cd72b9 10183 &default_lit_sections.init_lit_seg, TRUE);
e0001a05
NC		 10184 xtensa_switch_section_emit_state (result,
10185 default_lit_sections.init_lit_seg, 0);
10186 }
10187 else if (is_fini)
10188 {
10189 cache_literal_section (fini_literal_head,
10190 default_lit_sections.fini_lit_seg_name,
43cd72b9 10191 &default_lit_sections.fini_lit_seg, TRUE);
e0001a05
NC		 10192 xtensa_switch_section_emit_state (result,
10193 default_lit_sections.fini_lit_seg, 0);
10194 }
43cd72b9 10195 else
e0001a05
NC		 10196 {
10197 cache_literal_section (literal_head,
10198 default_lit_sections.lit_seg_name,
43cd72b9 10199 &default_lit_sections.lit_seg, TRUE);
e0001a05
NC		 10200 xtensa_switch_section_emit_state (result,
10201 default_lit_sections.lit_seg, 0);
10202 }
10203
43cd72b9
BW		 10204 if (!use_literal_section
10205 && !is_init && !is_fini
10206 && get_literal_pool_location (now_seg) != pool_location)
e0001a05
NC		 10207 {
10208 /* Close whatever frag is there. */
10209 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10210 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 10211 frag_now->tc_frag_data.literal_frag = pool_location;
10212 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10213 xtensa_set_frag_assembly_state (frag_now);
e0001a05 10214 }
e0001a05
NC		 10215}
10216
10217
10218/* Call this function before emitting data into the literal section.
10219 This is a helper function for xtensa_switch_to_literal_fragment.
10220 This is similar to a .section new_now_seg subseg. */
10221
7fa3d080
BW		 10222static void
10223xtensa_switch_section_emit_state (emit_state *state,
10224 segT new_now_seg,
10225 subsegT new_now_subseg)
e0001a05
NC		 10226{
10227 state->name = now_seg->name;
10228 state->now_seg = now_seg;
10229 state->now_subseg = now_subseg;
10230 state->generating_literals = generating_literals;
10231 generating_literals++;
2b0210eb 10232 subseg_set (new_now_seg, new_now_subseg);
e0001a05
NC		 10233}
10234
10235
10236/* Use to restore the emitting into the normal place. */
10237
7fa3d080
BW		 10238static void
10239xtensa_restore_emit_state (emit_state *state)
e0001a05
NC		 10240{
10241 generating_literals = state->generating_literals;
2b0210eb 10242 subseg_set (state->now_seg, state->now_subseg);
e0001a05
NC		 10243}
10244
10245
10246/* Get a segment of a given name. If the segment is already
10247 present, return it; otherwise, create a new one. */
10248
10249static void
7fa3d080
BW		 10250cache_literal_section (seg_list *head,
10251 const char *name,
b08b5071 10252 segT *pseg,
7fa3d080 10253 bfd_boolean is_code)
e0001a05
NC		 10254{
10255 segT current_section = now_seg;
10256 int current_subsec = now_subseg;
b08b5071 10257 segT seg;
e0001a05 10258
b08b5071 10259 if (*pseg != 0)
e0001a05 10260 return;
e0001a05 10261
b08b5071
BW		 10262 /* Check if the named section exists. */
10263 for (seg = stdoutput->sections; seg; seg = seg->next)
10264 {
10265 if (!strcmp (segment_name (seg), name))
10266 break;
10267 }
e0001a05 10268
b08b5071 10269 if (!seg)
e0001a05 10270 {
b08b5071
BW		 10271 /* Create a new literal section. */
10272 seg = subseg_new (name, (subsegT) 0);
43cd72b9 10273 if (head)
b08b5071
BW		 10274 {
10275 /* Add the newly created literal segment to the specified list. */
10276 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
10277 n->seg = seg;
10278 n->next = head->next;
10279 head->next = n;
10280 }
10281 bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS |
43cd72b9
BW		 10282 SEC_READONLY | SEC_ALLOC | SEC_LOAD
10283 | (is_code ? SEC_CODE : SEC_DATA));
b08b5071 10284 bfd_set_section_alignment (stdoutput, seg, 2);
e0001a05
NC		 10285 }
10286
b08b5071
BW		 10287 *pseg = seg;
10288 subseg_set (current_section, current_subsec);
e0001a05
NC		 10289}
10290
43cd72b9
BW		 10291\f
10292/* Property Tables Stuff. */
10293
7fa3d080
BW		 10294#define XTENSA_INSN_SEC_NAME ".xt.insn"
10295#define XTENSA_LIT_SEC_NAME ".xt.lit"
10296#define XTENSA_PROP_SEC_NAME ".xt.prop"
10297
10298typedef bfd_boolean (*frag_predicate) (const fragS *);
10299typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10300
b08b5071 10301static bfd_boolean get_frag_is_literal (const fragS *);
7fa3d080
BW		 10302static void xtensa_create_property_segments
10303 (frag_predicate, frag_predicate, const char *, xt_section_type);
10304static void xtensa_create_xproperty_segments
10305 (frag_flags_fn, const char *, xt_section_type);
10306static segment_info_type *retrieve_segment_info (segT);
10307static segT retrieve_xtensa_section (char *);
10308static bfd_boolean section_has_property (segT, frag_predicate);
10309static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10310static void add_xt_block_frags
10311 (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
10312static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10313static void xtensa_frag_flags_init (frag_flags *);
10314static void get_frag_property_flags (const fragS *, frag_flags *);
10315static bfd_vma frag_flags_to_number (const frag_flags *);
10316static void add_xt_prop_frags
10317 (segT, segT, xtensa_block_info **, frag_flags_fn);
10318
10319/* Set up property tables after relaxation. */
10320
10321void
10322xtensa_post_relax_hook (void)
10323{
10324 xtensa_move_seg_list_to_beginning (literal_head);
10325 xtensa_move_seg_list_to_beginning (init_literal_head);
10326 xtensa_move_seg_list_to_beginning (fini_literal_head);
10327
10328 xtensa_find_unmarked_state_frags ();
10329
10330 if (use_literal_section)
10331 xtensa_create_property_segments (get_frag_is_literal,
10332 NULL,
10333 XTENSA_LIT_SEC_NAME,
10334 xt_literal_sec);
10335 xtensa_create_xproperty_segments (get_frag_property_flags,
10336 XTENSA_PROP_SEC_NAME,
10337 xt_prop_sec);
10338
10339 if (warn_unaligned_branch_targets)
10340 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10341 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10342}
10343
10344
43cd72b9
BW		 10345/* This function is only meaningful after xtensa_move_literals. */
10346
10347static bfd_boolean
7fa3d080 10348get_frag_is_literal (const fragS *fragP)
43cd72b9
BW		 10349{
10350 assert (fragP != NULL);
10351 return fragP->tc_frag_data.is_literal;
10352}
10353
10354
43cd72b9 10355static void
7fa3d080
BW		 10356xtensa_create_property_segments (frag_predicate property_function,
10357 frag_predicate end_property_function,
10358 const char *section_name_base,
10359 xt_section_type sec_type)
43cd72b9
BW		 10360{
10361 segT *seclist;
10362
10363 /* Walk over all of the current segments.
10364 Walk over each fragment
10365 For each non-empty fragment,
10366 Build a property record (append where possible). */
10367
10368 for (seclist = &stdoutput->sections;
10369 seclist && *seclist;
10370 seclist = &(*seclist)->next)
10371 {
10372 segT sec = *seclist;
10373 flagword flags;
10374
10375 flags = bfd_get_section_flags (stdoutput, sec);
10376 if (flags & SEC_DEBUGGING)
10377 continue;
10378 if (!(flags & SEC_ALLOC))
10379 continue;
10380
10381 if (section_has_property (sec, property_function))
10382 {
10383 char *property_section_name =
10384 xtensa_get_property_section_name (sec, section_name_base);
10385 segT insn_sec = retrieve_xtensa_section (property_section_name);
10386 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10387 xtensa_block_info **xt_blocks =
10388 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10389 /* Walk over all of the frchains here and add new sections. */
10390 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
10391 end_property_function);
10392 }
10393 }
10394
10395 /* Now we fill them out.... */
10396
10397 for (seclist = &stdoutput->sections;
10398 seclist && *seclist;
10399 seclist = &(*seclist)->next)
10400 {
10401 segment_info_type *seginfo;
10402 xtensa_block_info *block;
10403 segT sec = *seclist;
10404
10405 seginfo = seg_info (sec);
10406 block = seginfo->tc_segment_info_data.blocks[sec_type];
10407
10408 if (block)
10409 {
10410 xtensa_block_info *cur_block;
10411 /* This is a section with some data. */
10412 int num_recs = 0;
10413 size_t rec_size;
10414
10415 for (cur_block = block; cur_block; cur_block = cur_block->next)
10416 num_recs++;
10417
10418 rec_size = num_recs * 8;
10419 bfd_set_section_size (stdoutput, sec, rec_size);
10420
10421 /* In order to make this work with the assembler, we have to
10422 build some frags and then build the "fixups" for it. It
10423 would be easier to just set the contents then set the
10424 arlents. */
10425
10426 if (num_recs)
10427 {
10428 /* Allocate a fragment and leak it. */
10429 fragS *fragP;
10430 size_t frag_size;
10431 fixS *fixes;
10432 frchainS *frchainP;
10433 int i;
10434 char *frag_data;
10435
10436 frag_size = sizeof (fragS) + rec_size;
10437 fragP = (fragS *) xmalloc (frag_size);
e0001a05 10438
43cd72b9
BW		 10439 memset (fragP, 0, frag_size);
10440 fragP->fr_address = 0;
10441 fragP->fr_next = NULL;
10442 fragP->fr_fix = rec_size;
10443 fragP->fr_var = 0;
10444 fragP->fr_type = rs_fill;
10445 /* The rest are zeros. */
e0001a05 10446
43cd72b9
BW		 10447 frchainP = seginfo->frchainP;
10448 frchainP->frch_root = fragP;
10449 frchainP->frch_last = fragP;
e0001a05 10450
43cd72b9
BW		 10451 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10452 memset (fixes, 0, sizeof (fixS) * num_recs);
e0001a05 10453
43cd72b9
BW		 10454 seginfo->fix_root = fixes;
10455 seginfo->fix_tail = &fixes[num_recs - 1];
10456 cur_block = block;
10457 frag_data = &fragP->fr_literal[0];
10458 for (i = 0; i < num_recs; i++)
10459 {
10460 fixS *fix = &fixes[i];
10461 assert (cur_block);
e0001a05 10462
43cd72b9
BW		 10463 /* Write the fixup. */
10464 if (i != num_recs - 1)
10465 fix->fx_next = &fixes[i + 1];
10466 else
10467 fix->fx_next = NULL;
10468 fix->fx_size = 4;
10469 fix->fx_done = 0;
10470 fix->fx_frag = fragP;
10471 fix->fx_where = i * 8;
10472 fix->fx_addsy = section_symbol (cur_block->sec);
10473 fix->fx_offset = cur_block->offset;
10474 fix->fx_r_type = BFD_RELOC_32;
10475 fix->fx_file = "Internal Assembly";
10476 fix->fx_line = 0;
e0001a05 10477
43cd72b9
BW		 10478 /* Write the length. */
10479 md_number_to_chars (&frag_data[4 + 8 * i],
10480 cur_block->size, 4);
10481 cur_block = cur_block->next;
10482 }
10483 }
10484 }
10485 }
e0001a05
NC		 10486}
10487
10488
7fa3d080
BW		 10489static void
10490xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10491 const char *section_name_base,
10492 xt_section_type sec_type)
e0001a05
NC		 10493{
10494 segT *seclist;
10495
10496 /* Walk over all of the current segments.
43cd72b9
BW		 10497 Walk over each fragment.
10498 For each fragment that has instructions,
10499 build an instruction record (append where possible). */
e0001a05
NC		 10500
10501 for (seclist = &stdoutput->sections;
10502 seclist && *seclist;
10503 seclist = &(*seclist)->next)
10504 {
10505 segT sec = *seclist;
43cd72b9
BW		 10506 flagword flags;
10507
10508 flags = bfd_get_section_flags (stdoutput, sec);
10509 if (flags & SEC_DEBUGGING)
10510 continue;
10511 if (!(flags & SEC_ALLOC))
10512 continue;
10513
10514 if (section_has_xproperty (sec, flag_fn))
e0001a05 10515 {
b614a702
BW		 10516 char *property_section_name =
10517 xtensa_get_property_section_name (sec, section_name_base);
e0001a05
NC		 10518 segT insn_sec = retrieve_xtensa_section (property_section_name);
10519 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
43cd72b9 10520 xtensa_block_info **xt_blocks =
e0001a05
NC		 10521 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10522 /* Walk over all of the frchains here and add new sections. */
43cd72b9 10523 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
e0001a05
NC		 10524 }
10525 }
10526
10527 /* Now we fill them out.... */
10528
10529 for (seclist = &stdoutput->sections;
10530 seclist && *seclist;
10531 seclist = &(*seclist)->next)
10532 {
10533 segment_info_type *seginfo;
10534 xtensa_block_info *block;
10535 segT sec = *seclist;
43cd72b9 10536
e0001a05
NC		 10537 seginfo = seg_info (sec);
10538 block = seginfo->tc_segment_info_data.blocks[sec_type];
10539
10540 if (block)
10541 {
10542 xtensa_block_info *cur_block;
10543 /* This is a section with some data. */
43cd72b9 10544 int num_recs = 0;
e0001a05
NC		 10545 size_t rec_size;
10546
10547 for (cur_block = block; cur_block; cur_block = cur_block->next)
10548 num_recs++;
10549
43cd72b9 10550 rec_size = num_recs * (8 + 4);
e0001a05
NC		 10551 bfd_set_section_size (stdoutput, sec, rec_size);
10552
43cd72b9
BW		 10553 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10554
10555 /* In order to make this work with the assembler, we have to build
10556 some frags then build the "fixups" for it. It would be easier to
10557 just set the contents then set the arlents. */
e0001a05
NC		 10558
10559 if (num_recs)
10560 {
43cd72b9 10561 /* Allocate a fragment and (unfortunately) leak it. */
e0001a05
NC		 10562 fragS *fragP;
10563 size_t frag_size;
10564 fixS *fixes;
10565 frchainS *frchainP;
43cd72b9 10566 int i;
e0001a05
NC		 10567 char *frag_data;
10568
10569 frag_size = sizeof (fragS) + rec_size;
10570 fragP = (fragS *) xmalloc (frag_size);
10571
10572 memset (fragP, 0, frag_size);
10573 fragP->fr_address = 0;
10574 fragP->fr_next = NULL;
10575 fragP->fr_fix = rec_size;
10576 fragP->fr_var = 0;
10577 fragP->fr_type = rs_fill;
43cd72b9 10578 /* The rest are zeros. */
e0001a05
NC		 10579
10580 frchainP = seginfo->frchainP;
10581 frchainP->frch_root = fragP;
10582 frchainP->frch_last = fragP;
10583
10584 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10585 memset (fixes, 0, sizeof (fixS) * num_recs);
10586
10587 seginfo->fix_root = fixes;
10588 seginfo->fix_tail = &fixes[num_recs - 1];
10589 cur_block = block;
10590 frag_data = &fragP->fr_literal[0];
10591 for (i = 0; i < num_recs; i++)
10592 {
10593 fixS *fix = &fixes[i];
10594 assert (cur_block);
10595
10596 /* Write the fixup. */
10597 if (i != num_recs - 1)
10598 fix->fx_next = &fixes[i + 1];
10599 else
10600 fix->fx_next = NULL;
10601 fix->fx_size = 4;
10602 fix->fx_done = 0;
10603 fix->fx_frag = fragP;
43cd72b9 10604 fix->fx_where = i * (8 + 4);
e0001a05
NC		 10605 fix->fx_addsy = section_symbol (cur_block->sec);
10606 fix->fx_offset = cur_block->offset;
10607 fix->fx_r_type = BFD_RELOC_32;
10608 fix->fx_file = "Internal Assembly";
10609 fix->fx_line = 0;
10610
10611 /* Write the length. */
43cd72b9 10612 md_number_to_chars (&frag_data[4 + (8+4) * i],
e0001a05 10613 cur_block->size, 4);
43cd72b9
BW		 10614 md_number_to_chars (&frag_data[8 + (8+4) * i],
10615 frag_flags_to_number (&cur_block->flags),
10616 4);
e0001a05
NC		 10617 cur_block = cur_block->next;
10618 }
10619 }
10620 }
10621 }
10622}
10623
10624
7fa3d080
BW		 10625static segment_info_type *
10626retrieve_segment_info (segT seg)
e0001a05
NC		 10627{
10628 segment_info_type *seginfo;
10629 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
10630 if (!seginfo)
10631 {
10632 frchainS *frchainP;
10633
10634 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
7fa3d080 10635 memset ((void *) seginfo, 0, sizeof (*seginfo));
e0001a05
NC		 10636 seginfo->fix_root = NULL;
10637 seginfo->fix_tail = NULL;
10638 seginfo->bfd_section = seg;
10639 seginfo->sym = 0;
10640 /* We will not be dealing with these, only our special ones. */
65ec77d2 10641 bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
e0001a05
NC		 10642
10643 frchainP = (frchainS *) xmalloc (sizeof (frchainS));
10644 frchainP->frch_root = NULL;
10645 frchainP->frch_last = NULL;
10646 frchainP->frch_next = NULL;
10647 frchainP->frch_seg = seg;
10648 frchainP->frch_subseg = 0;
10649 frchainP->fix_root = NULL;
10650 frchainP->fix_tail = NULL;
10651 /* Do not init the objstack. */
10652 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10653 /* frchainP->frch_frag_now = fragP; */
10654 frchainP->frch_frag_now = NULL;
10655
10656 seginfo->frchainP = frchainP;
10657 }
10658
10659 return seginfo;
10660}
10661
10662
7fa3d080
BW		 10663static segT
10664retrieve_xtensa_section (char *sec_name)
e0001a05
NC		 10665{
10666 bfd *abfd = stdoutput;
10667 flagword flags, out_flags, link_once_flags;
10668 segT s;
10669
10670 flags = bfd_get_section_flags (abfd, now_seg);
10671 link_once_flags = (flags & SEC_LINK_ONCE);
10672 if (link_once_flags)
10673 link_once_flags |= (flags & SEC_LINK_DUPLICATES);
10674 out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
10675
10676 s = bfd_make_section_old_way (abfd, sec_name);
10677 if (s == NULL)
10678 as_bad (_("could not create section %s"), sec_name);
10679 if (!bfd_set_section_flags (abfd, s, out_flags))
10680 as_bad (_("invalid flag combination on section %s"), sec_name);
10681
10682 return s;
10683}
10684
10685
7fa3d080
BW		 10686static bfd_boolean
10687section_has_property (segT sec, frag_predicate property_function)
e0001a05
NC		 10688{
10689 segment_info_type *seginfo = seg_info (sec);
10690 fragS *fragP;
10691
10692 if (seginfo && seginfo->frchainP)
10693 {
10694 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10695 {
10696 if (property_function (fragP)
10697 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10698 return TRUE;
10699 }
10700 }
10701 return FALSE;
10702}
10703
10704
7fa3d080
BW		 10705static bfd_boolean
10706section_has_xproperty (segT sec, frag_flags_fn property_function)
43cd72b9
BW		 10707{
10708 segment_info_type *seginfo = seg_info (sec);
10709 fragS *fragP;
10710
10711 if (seginfo && seginfo->frchainP)
10712 {
10713 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10714 {
10715 frag_flags prop_flags;
10716 property_function (fragP, &prop_flags);
10717 if (!xtensa_frag_flags_is_empty (&prop_flags))
10718 return TRUE;
10719 }
10720 }
10721 return FALSE;
10722}
10723
10724
e0001a05
NC		 10725/* Two types of block sections exist right now: literal and insns. */
10726
7fa3d080
BW		 10727static void
10728add_xt_block_frags (segT sec,
10729 segT xt_block_sec,
10730 xtensa_block_info **xt_block,
10731 frag_predicate property_function,
10732 frag_predicate end_property_function)
e0001a05
NC		 10733{
10734 segment_info_type *seg_info;
10735 segment_info_type *xt_seg_info;
10736 bfd_vma seg_offset;
10737 fragS *fragP;
10738
10739 xt_seg_info = retrieve_segment_info (xt_block_sec);
10740 seg_info = retrieve_segment_info (sec);
10741
10742 /* Build it if needed. */
10743 while (*xt_block != NULL)
10744 xt_block = &(*xt_block)->next;
10745 /* We are either at NULL at the beginning or at the end. */
10746
10747 /* Walk through the frags. */
10748 seg_offset = 0;
10749
10750 if (seg_info->frchainP)
10751 {
10752 for (fragP = seg_info->frchainP->frch_root;
10753 fragP;
10754 fragP = fragP->fr_next)
10755 {
10756 if (property_function (fragP)
10757 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10758 {
10759 if (*xt_block != NULL)
10760 {
10761 if ((*xt_block)->offset + (*xt_block)->size
10762 == fragP->fr_address)
10763 (*xt_block)->size += fragP->fr_fix;
10764 else
10765 xt_block = &((*xt_block)->next);
10766 }
10767 if (*xt_block == NULL)
10768 {
43cd72b9
BW		 10769 xtensa_block_info *new_block = (xtensa_block_info *)
10770 xmalloc (sizeof (xtensa_block_info));
10771 new_block->sec = sec;
10772 new_block->offset = fragP->fr_address;
10773 new_block->size = fragP->fr_fix;
10774 new_block->next = NULL;
10775 xtensa_frag_flags_init (&new_block->flags);
10776 *xt_block = new_block;
10777 }
10778 if (end_property_function
10779 && end_property_function (fragP))
10780 {
10781 xt_block = &((*xt_block)->next);
10782 }
10783 }
10784 }
10785 }
10786}
10787
10788
10789/* Break the encapsulation of add_xt_prop_frags here. */
10790
7fa3d080
BW		 10791static bfd_boolean
10792xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
43cd72b9
BW		 10793{
10794 if (prop_flags->is_literal
10795 || prop_flags->is_insn
10796 || prop_flags->is_data
10797 || prop_flags->is_unreachable)
10798 return FALSE;
10799 return TRUE;
10800}
10801
10802
7fa3d080
BW		 10803static void
10804xtensa_frag_flags_init (frag_flags *prop_flags)
43cd72b9
BW		 10805{
10806 memset (prop_flags, 0, sizeof (frag_flags));
10807}
10808
10809
7fa3d080
BW		 10810static void
10811get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
43cd72b9
BW		 10812{
10813 xtensa_frag_flags_init (prop_flags);
10814 if (fragP->tc_frag_data.is_literal)
10815 prop_flags->is_literal = TRUE;
10816 if (fragP->tc_frag_data.is_unreachable)
7fa3d080 10817 prop_flags->is_unreachable = TRUE;
43cd72b9
BW		 10818 else if (fragP->tc_frag_data.is_insn)
10819 {
10820 prop_flags->is_insn = TRUE;
10821 if (fragP->tc_frag_data.is_loop_target)
10822 prop_flags->insn.is_loop_target = TRUE;
10823 if (fragP->tc_frag_data.is_branch_target)
10824 prop_flags->insn.is_branch_target = TRUE;
10825 if (fragP->tc_frag_data.is_specific_opcode
10826 || fragP->tc_frag_data.is_no_transform)
10827 prop_flags->insn.is_no_transform = TRUE;
10828 if (fragP->tc_frag_data.is_no_density)
10829 prop_flags->insn.is_no_density = TRUE;
10830 if (fragP->tc_frag_data.use_absolute_literals)
10831 prop_flags->insn.is_abslit = TRUE;
10832 }
10833 if (fragP->tc_frag_data.is_align)
10834 {
10835 prop_flags->is_align = TRUE;
10836 prop_flags->alignment = fragP->tc_frag_data.alignment;
10837 if (xtensa_frag_flags_is_empty (prop_flags))
10838 prop_flags->is_data = TRUE;
10839 }
10840}
10841
10842
7fa3d080
BW		 10843static bfd_vma
10844frag_flags_to_number (const frag_flags *prop_flags)
43cd72b9
BW		 10845{
10846 bfd_vma num = 0;
10847 if (prop_flags->is_literal)
10848 num |= XTENSA_PROP_LITERAL;
10849 if (prop_flags->is_insn)
10850 num |= XTENSA_PROP_INSN;
10851 if (prop_flags->is_data)
10852 num |= XTENSA_PROP_DATA;
10853 if (prop_flags->is_unreachable)
10854 num |= XTENSA_PROP_UNREACHABLE;
10855 if (prop_flags->insn.is_loop_target)
10856 num |= XTENSA_PROP_INSN_LOOP_TARGET;
10857 if (prop_flags->insn.is_branch_target)
10858 {
10859 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
10860 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
10861 }
10862
10863 if (prop_flags->insn.is_no_density)
10864 num |= XTENSA_PROP_INSN_NO_DENSITY;
10865 if (prop_flags->insn.is_no_transform)
10866 num |= XTENSA_PROP_INSN_NO_TRANSFORM;
10867 if (prop_flags->insn.is_no_reorder)
10868 num |= XTENSA_PROP_INSN_NO_REORDER;
10869 if (prop_flags->insn.is_abslit)
10870 num |= XTENSA_PROP_INSN_ABSLIT;
10871
10872 if (prop_flags->is_align)
10873 {
10874 num |= XTENSA_PROP_ALIGN;
10875 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
10876 }
10877
10878 return num;
10879}
10880
10881
10882static bfd_boolean
7fa3d080
BW		 10883xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
10884 const frag_flags *prop_flags_2)
43cd72b9
BW		 10885{
10886 /* Cannot combine with an end marker. */
10887
10888 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
10889 return FALSE;
10890 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
10891 return FALSE;
10892 if (prop_flags_1->is_data != prop_flags_2->is_data)
10893 return FALSE;
10894
10895 if (prop_flags_1->is_insn)
10896 {
10897 /* Properties of the beginning of the frag. */
10898 if (prop_flags_2->insn.is_loop_target)
10899 return FALSE;
10900 if (prop_flags_2->insn.is_branch_target)
10901 return FALSE;
10902 if (prop_flags_1->insn.is_no_density !=
10903 prop_flags_2->insn.is_no_density)
10904 return FALSE;
10905 if (prop_flags_1->insn.is_no_transform !=
10906 prop_flags_2->insn.is_no_transform)
10907 return FALSE;
10908 if (prop_flags_1->insn.is_no_reorder !=
10909 prop_flags_2->insn.is_no_reorder)
10910 return FALSE;
10911 if (prop_flags_1->insn.is_abslit !=
10912 prop_flags_2->insn.is_abslit)
10913 return FALSE;
10914 }
10915
10916 if (prop_flags_1->is_align)
10917 return FALSE;
10918
10919 return TRUE;
10920}
10921
10922
7fa3d080
BW		 10923static bfd_vma
10924xt_block_aligned_size (const xtensa_block_info *xt_block)
43cd72b9
BW		 10925{
10926 bfd_vma end_addr;
10927 size_t align_bits;
10928
10929 if (!xt_block->flags.is_align)
10930 return xt_block->size;
10931
10932 end_addr = xt_block->offset + xt_block->size;
10933 align_bits = xt_block->flags.alignment;
10934 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
10935 return end_addr - xt_block->offset;
10936}
10937
10938
10939static bfd_boolean
7fa3d080
BW		 10940xtensa_xt_block_combine (xtensa_block_info *xt_block,
10941 const xtensa_block_info *xt_block_2)
43cd72b9
BW		 10942{
10943 if (xt_block->sec != xt_block_2->sec)
10944 return FALSE;
10945 if (xt_block->offset + xt_block_aligned_size (xt_block)
10946 != xt_block_2->offset)
10947 return FALSE;
10948
10949 if (xt_block_2->size == 0
10950 && (!xt_block_2->flags.is_unreachable
10951 || xt_block->flags.is_unreachable))
10952 {
10953 if (xt_block_2->flags.is_align
10954 && xt_block->flags.is_align)
10955 {
10956 /* Nothing needed. */
10957 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
10958 return TRUE;
10959 }
10960 else
10961 {
10962 if (xt_block_2->flags.is_align)
10963 {
10964 /* Push alignment to previous entry. */
10965 xt_block->flags.is_align = xt_block_2->flags.is_align;
10966 xt_block->flags.alignment = xt_block_2->flags.alignment;
10967 }
10968 return TRUE;
10969 }
10970 }
10971 if (!xtensa_frag_flags_combinable (&xt_block->flags,
10972 &xt_block_2->flags))
10973 return FALSE;
10974
10975 xt_block->size += xt_block_2->size;
10976
10977 if (xt_block_2->flags.is_align)
10978 {
10979 xt_block->flags.is_align = TRUE;
10980 xt_block->flags.alignment = xt_block_2->flags.alignment;
10981 }
10982
10983 return TRUE;
10984}
10985
10986
7fa3d080
BW		 10987static void
10988add_xt_prop_frags (segT sec,
10989 segT xt_block_sec,
10990 xtensa_block_info **xt_block,
10991 frag_flags_fn property_function)
43cd72b9
BW		 10992{
10993 segment_info_type *seg_info;
10994 segment_info_type *xt_seg_info;
10995 bfd_vma seg_offset;
10996 fragS *fragP;
10997
10998 xt_seg_info = retrieve_segment_info (xt_block_sec);
10999 seg_info = retrieve_segment_info (sec);
11000 /* Build it if needed. */
11001 while (*xt_block != NULL)
11002 {
11003 xt_block = &(*xt_block)->next;
11004 }
11005 /* We are either at NULL at the beginning or at the end. */
11006
11007 /* Walk through the frags. */
11008 seg_offset = 0;
11009
11010 if (seg_info->frchainP)
11011 {
11012 for (fragP = seg_info->frchainP->frch_root; fragP;
11013 fragP = fragP->fr_next)
11014 {
11015 xtensa_block_info tmp_block;
11016 tmp_block.sec = sec;
11017 tmp_block.offset = fragP->fr_address;
11018 tmp_block.size = fragP->fr_fix;
11019 tmp_block.next = NULL;
11020 property_function (fragP, &tmp_block.flags);
11021
11022 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
11023 /* && fragP->fr_fix != 0) */
11024 {
11025 if ((*xt_block) == NULL
11026 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
11027 {
11028 xtensa_block_info *new_block;
11029 if ((*xt_block) != NULL)
11030 xt_block = &(*xt_block)->next;
11031 new_block = (xtensa_block_info *)
11032 xmalloc (sizeof (xtensa_block_info));
11033 *new_block = tmp_block;
11034 *xt_block = new_block;
11035 }
11036 }
11037 }
11038 }
11039}
11040
11041\f
11042/* op_placement_info_table */
11043
11044/* op_placement_info makes it easier to determine which
11045 ops can go in which slots. */
11046
11047static void
7fa3d080 11048init_op_placement_info_table (void)
43cd72b9
BW		 11049{
11050 xtensa_isa isa = xtensa_default_isa;
11051 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
11052 xtensa_opcode opcode;
11053 xtensa_format fmt;
11054 int slot;
11055 int num_opcodes = xtensa_isa_num_opcodes (isa);
11056
11057 op_placement_table = (op_placement_info_table)
11058 xmalloc (sizeof (op_placement_info) * num_opcodes);
11059 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
11060
11061 for (opcode = 0; opcode < num_opcodes; opcode++)
11062 {
11063 op_placement_info *opi = &op_placement_table[opcode];
11064 /* FIXME: Make tinsn allocation dynamic. */
11065 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
11066 as_fatal (_("too many operands in instruction"));
11067 opi->single = XTENSA_UNDEFINED;
11068 opi->single_size = 0;
11069 opi->widest = XTENSA_UNDEFINED;
11070 opi->widest_size = 0;
11071 opi->narrowest = XTENSA_UNDEFINED;
11072 opi->narrowest_size = 0x7F;
11073 opi->formats = 0;
11074 opi->num_formats = 0;
11075 opi->issuef = 0;
11076 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
11077 {
11078 opi->slots[fmt] = 0;
11079 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
11080 {
11081 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11082 {
11083 int fmt_length = xtensa_format_length (isa, fmt);
11084 opi->issuef++;
11085 set_bit (fmt, opi->formats);
11086 set_bit (slot, opi->slots[fmt]);
11087 /* opi->slot_count[fmt]++; */
11088 if (fmt_length < opi->narrowest_size)
11089 {
11090 opi->narrowest = fmt;
11091 opi->narrowest_size = fmt_length;
11092 }
11093 if (fmt_length > opi->widest_size)
11094 {
11095 opi->widest = fmt;
11096 opi->widest_size = fmt_length;
11097 }
11098 if (xtensa_format_num_slots (isa, fmt) == 1)
11099 {
11100 if (opi->single_size == 0
11101 || fmt_length < opi->single_size)
11102 {
11103 opi->single = fmt;
11104 opi->single_size = fmt_length;
11105 }
11106 }
e0001a05
NC		 11107 }
11108 }
43cd72b9
BW		 11109 if (opi->formats)
11110 opi->num_formats++;
e0001a05
NC		 11111 }
11112 }
43cd72b9
BW		 11113 xtensa_insnbuf_free (isa, ibuf);
11114}
11115
11116
11117bfd_boolean
7fa3d080 11118opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
43cd72b9
BW		 11119{
11120 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11121}
11122
11123
11124/* If the opcode is available in a single slot format, return its size. */
11125
7fa3d080
BW		 11126static int
11127xg_get_single_size (xtensa_opcode opcode)
43cd72b9
BW		 11128{
11129 assert (op_placement_table[opcode].single != XTENSA_UNDEFINED);
11130 return op_placement_table[opcode].single_size;
11131}
11132
11133
7fa3d080
BW		 11134static xtensa_format
11135xg_get_single_format (xtensa_opcode opcode)
43cd72b9
BW		 11136{
11137 return op_placement_table[opcode].single;
e0001a05
NC		 11138}
11139
11140\f
11141/* Instruction Stack Functions (from "xtensa-istack.h"). */
11142
11143void
7fa3d080 11144istack_init (IStack *stack)
e0001a05
NC		 11145{
11146 memset (stack, 0, sizeof (IStack));
11147 stack->ninsn = 0;
11148}
11149
11150
11151bfd_boolean
7fa3d080 11152istack_empty (IStack *stack)
e0001a05
NC		 11153{
11154 return (stack->ninsn == 0);
11155}
11156
11157
11158bfd_boolean
7fa3d080 11159istack_full (IStack *stack)
e0001a05
NC		 11160{
11161 return (stack->ninsn == MAX_ISTACK);
11162}
11163
11164
11165/* Return a pointer to the top IStack entry.
43cd72b9 11166 It is an error to call this if istack_empty () is TRUE. */
e0001a05
NC		 11167
11168TInsn *
7fa3d080 11169istack_top (IStack *stack)
e0001a05
NC		 11170{
11171 int rec = stack->ninsn - 1;
11172 assert (!istack_empty (stack));
11173 return &stack->insn[rec];
11174}
11175
11176
11177/* Add a new TInsn to an IStack.
43cd72b9 11178 It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 11179
11180void
7fa3d080 11181istack_push (IStack *stack, TInsn *insn)
e0001a05
NC		 11182{
11183 int rec = stack->ninsn;
11184 assert (!istack_full (stack));
43cd72b9 11185 stack->insn[rec] = *insn;
e0001a05
NC		 11186 stack->ninsn++;
11187}
11188
11189
11190/* Clear space for the next TInsn on the IStack and return a pointer
43cd72b9 11191 to it. It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 11192
11193TInsn *
7fa3d080 11194istack_push_space (IStack *stack)
e0001a05
NC		 11195{
11196 int rec = stack->ninsn;
11197 TInsn *insn;
11198 assert (!istack_full (stack));
11199 insn = &stack->insn[rec];
11200 memset (insn, 0, sizeof (TInsn));
11201 stack->ninsn++;
11202 return insn;
11203}
11204
11205
11206/* Remove the last pushed instruction. It is an error to call this if
43cd72b9 11207 istack_empty () returns TRUE. */
e0001a05
NC		 11208
11209void
7fa3d080 11210istack_pop (IStack *stack)
e0001a05
NC		 11211{
11212 int rec = stack->ninsn - 1;
11213 assert (!istack_empty (stack));
11214 stack->ninsn--;
11215 memset (&stack->insn[rec], 0, sizeof (TInsn));
11216}
11217
11218\f
11219/* TInsn functions. */
11220
11221void
7fa3d080 11222tinsn_init (TInsn *dst)
e0001a05
NC		 11223{
11224 memset (dst, 0, sizeof (TInsn));
11225}
11226
11227
e0001a05
NC		 11228/* Get the ``num''th token of the TInsn.
11229 It is illegal to call this if num > insn->ntoks. */
11230
11231expressionS *
7fa3d080 11232tinsn_get_tok (TInsn *insn, int num)
e0001a05
NC		 11233{
11234 assert (num < insn->ntok);
11235 return &insn->tok[num];
11236}
11237
11238
43cd72b9 11239/* Return TRUE if ANY of the operands in the insn are symbolic. */
e0001a05
NC		 11240
11241static bfd_boolean
7fa3d080 11242tinsn_has_symbolic_operands (const TInsn *insn)
e0001a05
NC		 11243{
11244 int i;
11245 int n = insn->ntok;
11246
11247 assert (insn->insn_type == ITYPE_INSN);
11248
11249 for (i = 0; i < n; ++i)
11250 {
11251 switch (insn->tok[i].X_op)
11252 {
11253 case O_register:
11254 case O_constant:
11255 break;
11256 default:
11257 return TRUE;
11258 }
11259 }
11260 return FALSE;
11261}
11262
11263
11264bfd_boolean
7fa3d080 11265tinsn_has_invalid_symbolic_operands (const TInsn *insn)
e0001a05 11266{
43cd72b9 11267 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 11268 int i;
11269 int n = insn->ntok;
11270
11271 assert (insn->insn_type == ITYPE_INSN);
11272
11273 for (i = 0; i < n; ++i)
11274 {
11275 switch (insn->tok[i].X_op)
11276 {
11277 case O_register:
11278 case O_constant:
11279 break;
43cd72b9
BW		 11280 case O_big:
11281 case O_illegal:
11282 case O_absent:
11283 /* Errors for these types are caught later. */
11284 break;
11285 case O_hi16:
11286 case O_lo16:
e0001a05 11287 default:
43cd72b9
BW		 11288 /* Symbolic immediates are only allowed on the last immediate
11289 operand. At this time, CONST16 is the only opcode where we
11290 support non-PC-relative relocations. (It isn't necessary
11291 to complain about non-PC-relative relocations here, but
11292 otherwise, no error is reported until the relocations are
11293 generated, and the assembler won't get that far if there
11294 are any other errors. It's nice to see all the problems
11295 at once.) */
11296 if (i != get_relaxable_immed (insn->opcode)
11297 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11298 && insn->opcode != xtensa_const16_opcode))
11299 {
11300 as_bad (_("invalid symbolic operand %d on '%s'"),
11301 i, xtensa_opcode_name (isa, insn->opcode));
11302 return TRUE;
11303 }
e0001a05
NC		 11304 }
11305 }
11306 return FALSE;
11307}
11308
11309
11310/* For assembly code with complex expressions (e.g. subtraction),
11311 we have to build them in the literal pool so that
11312 their results are calculated correctly after relaxation.
11313 The relaxation only handles expressions that
11314 boil down to SYMBOL + OFFSET. */
11315
11316static bfd_boolean
7fa3d080 11317tinsn_has_complex_operands (const TInsn *insn)
e0001a05
NC		 11318{
11319 int i;
11320 int n = insn->ntok;
11321 assert (insn->insn_type == ITYPE_INSN);
11322 for (i = 0; i < n; ++i)
11323 {
11324 switch (insn->tok[i].X_op)
11325 {
11326 case O_register:
11327 case O_constant:
11328 case O_symbol:
43cd72b9
BW		 11329 case O_lo16:
11330 case O_hi16:
e0001a05
NC		 11331 break;
11332 default:
11333 return TRUE;
11334 }
11335 }
11336 return FALSE;
11337}
11338
11339
43cd72b9
BW		 11340/* Convert the constant operands in the tinsn to insnbuf.
11341 Return TRUE if there is a symbol in the immediate field.
e0001a05 11342
43cd72b9 11343 Before this is called,
e0001a05 11344 1) the number of operands are correct
43cd72b9 11345 2) the tinsn is a ITYPE_INSN
e0001a05
NC		 11346 3) ONLY the relaxable_ is built
11347 4) All operands are O_constant, O_symbol. All constants fit
11348 The return value tells whether there are any remaining O_symbols. */
11349
11350static bfd_boolean
7fa3d080 11351tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
e0001a05 11352{
43cd72b9 11353 static xtensa_insnbuf slotbuf = 0;
e0001a05 11354 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 11355 xtensa_opcode opcode = tinsn->opcode;
11356 xtensa_format fmt = xg_get_single_format (opcode);
e0001a05 11357 bfd_boolean has_fixup = FALSE;
43cd72b9 11358 int noperands = xtensa_opcode_num_operands (isa, opcode);
e0001a05
NC		 11359 int i;
11360 uint32 opnd_value;
11361 char *file_name;
11362 int line;
11363
43cd72b9
BW		 11364 if (!slotbuf)
11365 slotbuf = xtensa_insnbuf_alloc (isa);
11366
11367 assert (tinsn->insn_type == ITYPE_INSN);
11368 if (noperands != tinsn->ntok)
e0001a05
NC		 11369 as_fatal (_("operand number mismatch"));
11370
43cd72b9
BW		 11371 if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode))
11372 as_fatal (_("cannot encode opcode"));
e0001a05
NC		 11373
11374 for (i = 0; i < noperands; ++i)
11375 {
43cd72b9 11376 expressionS *expr = &tinsn->tok[i];
e0001a05
NC		 11377 switch (expr->X_op)
11378 {
11379 case O_register:
43cd72b9
BW		 11380 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11381 break;
11382 /* The register number has already been checked in
e0001a05
NC		 11383 expression_maybe_register, so we don't need to check here. */
11384 opnd_value = expr->X_add_number;
43cd72b9
BW		 11385 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11386 xtensa_operand_set_field (isa, opcode, i, fmt, 0,
11387 slotbuf, opnd_value);
e0001a05
NC		 11388 break;
11389
11390 case O_constant:
43cd72b9
BW		 11391 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11392 break;
e0001a05
NC		 11393 as_where (&file_name, &line);
11394 /* It is a constant and we called this function,
11395 then we have to try to fit it. */
43cd72b9
BW		 11396 xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i,
11397 expr->X_add_number, file_name, line);
11398 break;
11399
11400 default:
11401 has_fixup = TRUE;
11402 break;
11403 }
11404 }
11405
11406 xtensa_format_encode (isa, fmt, insnbuf);
11407 xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf);
11408
11409 return has_fixup;
11410}
11411
11412
11413/* Convert the constant operands in the tinsn to slotbuf.
11414 Return TRUE if there is a symbol in the immediate field.
11415 (Eventually this should replace tinsn_to_insnbuf.) */
11416
11417/* Before this is called,
11418 1) the number of operands are correct
11419 2) the tinsn is a ITYPE_INSN
11420 3) ONLY the relaxable_ is built
11421 4) All operands are
11422 O_constant, O_symbol
11423 All constants fit
11424
11425 The return value tells whether there are any remaining O_symbols. */
11426
11427static bfd_boolean
7fa3d080
BW		 11428tinsn_to_slotbuf (xtensa_format fmt,
11429 int slot,
11430 TInsn *tinsn,
11431 xtensa_insnbuf slotbuf)
43cd72b9
BW		 11432{
11433 xtensa_isa isa = xtensa_default_isa;
11434 xtensa_opcode opcode = tinsn->opcode;
11435 bfd_boolean has_fixup = FALSE;
11436 int noperands = xtensa_opcode_num_operands (isa, opcode);
11437 int i;
11438
11439 *((int *) &slotbuf[0]) = 0;
11440 *((int *) &slotbuf[1]) = 0;
11441 assert (tinsn->insn_type == ITYPE_INSN);
11442 if (noperands != tinsn->ntok)
11443 as_fatal (_("operand number mismatch"));
11444
11445 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11446 {
11447 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11448 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11449 return FALSE;
11450 }
11451
11452 for (i = 0; i < noperands; i++)
11453 {
11454 expressionS *expr = &tinsn->tok[i];
11455 int rc, line;
11456 char *file_name;
11457 uint32 opnd_value;
11458
11459 switch (expr->X_op)
11460 {
11461 case O_register:
11462 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11463 break;
11464 /* The register number has already been checked in
11465 expression_maybe_register, so we don't need to check here. */
11466 opnd_value = expr->X_add_number;
11467 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11468 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11469 opnd_value);
11470 if (rc != 0)
11471 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11472 break;
11473
11474 case O_constant:
11475 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11476 break;
11477 as_where (&file_name, &line);
11478 /* It is a constant and we called this function
11479 then we have to try to fit it. */
11480 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
e0001a05
NC		 11481 expr->X_add_number, file_name, line);
11482 break;
11483
e0001a05
NC		 11484 default:
11485 has_fixup = TRUE;
11486 break;
11487 }
11488 }
43cd72b9 11489
e0001a05
NC		 11490 return has_fixup;
11491}
11492
11493
43cd72b9 11494/* Check the instruction arguments. Return TRUE on failure. */
e0001a05 11495
7fa3d080
BW		 11496static bfd_boolean
11497tinsn_check_arguments (const TInsn *insn)
e0001a05
NC		 11498{
11499 xtensa_isa isa = xtensa_default_isa;
11500 xtensa_opcode opcode = insn->opcode;
11501
11502 if (opcode == XTENSA_UNDEFINED)
11503 {
11504 as_bad (_("invalid opcode"));
11505 return TRUE;
11506 }
11507
43cd72b9 11508 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
e0001a05
NC		 11509 {
11510 as_bad (_("too few operands"));
11511 return TRUE;
11512 }
11513
43cd72b9 11514 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
e0001a05
NC		 11515 {
11516 as_bad (_("too many operands"));
11517 return TRUE;
11518 }
11519 return FALSE;
11520}
11521
11522
11523/* Load an instruction from its encoded form. */
11524
11525static void
7fa3d080 11526tinsn_from_chars (TInsn *tinsn, char *f, int slot)
e0001a05 11527{
43cd72b9 11528 vliw_insn vinsn;
e0001a05 11529
43cd72b9
BW		 11530 xg_init_vinsn (&vinsn);
11531 vinsn_from_chars (&vinsn, f);
11532
11533 *tinsn = vinsn.slots[slot];
11534 xg_free_vinsn (&vinsn);
11535}
e0001a05 11536
43cd72b9
BW		 11537
11538static void
7fa3d080
BW		 11539tinsn_from_insnbuf (TInsn *tinsn,
11540 xtensa_insnbuf slotbuf,
11541 xtensa_format fmt,
11542 int slot)
43cd72b9
BW		 11543{
11544 int i;
11545 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 11546
11547 /* Find the immed. */
43cd72b9
BW		 11548 tinsn_init (tinsn);
11549 tinsn->insn_type = ITYPE_INSN;
11550 tinsn->is_specific_opcode = FALSE; /* must not be specific */
11551 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11552 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11553 for (i = 0; i < tinsn->ntok; i++)
e0001a05 11554 {
43cd72b9
BW		 11555 set_expr_const (&tinsn->tok[i],
11556 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11557 tinsn->opcode, i));
e0001a05
NC		 11558 }
11559}
11560
11561
11562/* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11563
11564static void
7fa3d080 11565tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
e0001a05 11566{
43cd72b9 11567 xtensa_opcode opcode = tinsn->opcode;
e0001a05
NC		 11568 int opnum;
11569
43cd72b9 11570 if (fragP->tc_frag_data.slot_symbols[slot])
e0001a05
NC		 11571 {
11572 opnum = get_relaxable_immed (opcode);
43cd72b9
BW		 11573 assert (opnum >= 0);
11574 if (fragP->tc_frag_data.slot_sub_symbols[slot])
11575 {
11576 set_expr_symbol_offset_diff
11577 (&tinsn->tok[opnum],
11578 fragP->tc_frag_data.slot_symbols[slot],
11579 fragP->tc_frag_data.slot_sub_symbols[slot],
11580 fragP->tc_frag_data.slot_offsets[slot]);
11581 }
11582 else
11583 {
11584 set_expr_symbol_offset
11585 (&tinsn->tok[opnum],
11586 fragP->tc_frag_data.slot_symbols[slot],
11587 fragP->tc_frag_data.slot_offsets[slot]);
11588 }
e0001a05
NC		 11589 }
11590}
11591
11592
11593static int
7fa3d080 11594get_num_stack_text_bytes (IStack *istack)
e0001a05
NC		 11595{
11596 int i;
11597 int text_bytes = 0;
11598
11599 for (i = 0; i < istack->ninsn; i++)
11600 {
43cd72b9
BW		 11601 TInsn *tinsn = &istack->insn[i];
11602 if (tinsn->insn_type == ITYPE_INSN)
11603 text_bytes += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 11604 }
11605 return text_bytes;
11606}
11607
11608
11609static int
7fa3d080 11610get_num_stack_literal_bytes (IStack *istack)
e0001a05
NC		 11611{
11612 int i;
11613 int lit_bytes = 0;
11614
11615 for (i = 0; i < istack->ninsn; i++)
11616 {
43cd72b9
BW		 11617 TInsn *tinsn = &istack->insn[i];
11618 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
e0001a05
NC		 11619 lit_bytes += 4;
11620 }
11621 return lit_bytes;
11622}
11623
43cd72b9
BW		 11624\f
11625/* vliw_insn functions. */
11626
7fa3d080
BW		 11627static void
11628xg_init_vinsn (vliw_insn *v)
43cd72b9
BW		 11629{
11630 int i;
11631 xtensa_isa isa = xtensa_default_isa;
11632
11633 xg_clear_vinsn (v);
11634
11635 v->insnbuf = xtensa_insnbuf_alloc (isa);
11636 if (v->insnbuf == NULL)
11637 as_fatal (_("out of memory"));
11638
11639 for (i = 0; i < MAX_SLOTS; i++)
11640 {
11641 tinsn_init (&v->slots[i]);
11642 v->slots[i].opcode = XTENSA_UNDEFINED;
11643 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11644 if (v->slotbuf[i] == NULL)
11645 as_fatal (_("out of memory"));
11646 }
11647}
11648
11649
7fa3d080
BW		 11650static void
11651xg_clear_vinsn (vliw_insn *v)
43cd72b9
BW		 11652{
11653 int i;
11654 v->format = XTENSA_UNDEFINED;
11655 v->num_slots = 0;
11656 v->inside_bundle = FALSE;
11657
11658 if (xt_saved_debug_type != DEBUG_NONE)
11659 debug_type = xt_saved_debug_type;
11660
11661 for (i = 0; i < MAX_SLOTS; i++)
11662 {
11663 memset (&v->slots[i], 0, sizeof (TInsn));
11664 v->slots[i].opcode = XTENSA_UNDEFINED;
11665 }
11666}
11667
11668
7fa3d080
BW		 11669static bfd_boolean
11670vinsn_has_specific_opcodes (vliw_insn *v)
43cd72b9
BW		 11671{
11672 int i;
11673
11674 for (i = 0; i < v->num_slots; i++)
11675 {
11676 if (v->slots[i].is_specific_opcode)
11677 return TRUE;
11678 }
11679 return FALSE;
11680}
11681
11682
7fa3d080
BW		 11683static void
11684xg_free_vinsn (vliw_insn *v)
43cd72b9
BW		 11685{
11686 int i;
11687 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11688 for (i = 0; i < MAX_SLOTS; i++)
11689 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11690}
11691
11692
11693/* Before this is called, we should have
11694 filled out the following fields:
11695
11696 1) the number of operands for each opcode are correct
11697 2) the tinsn in the slots are ITYPE_INSN
11698 3) ONLY the relaxable_ is built
11699 4) All operands are
11700 O_constant, O_symbol
11701 All constants fit
11702
11703 The return value tells whether there are any remaining O_symbols. */
11704
11705static bfd_boolean
7fa3d080
BW		 11706vinsn_to_insnbuf (vliw_insn *vinsn,
11707 char *frag_offset,
11708 fragS *fragP,
11709 bfd_boolean record_fixup)
43cd72b9
BW		 11710{
11711 xtensa_isa isa = xtensa_default_isa;
11712 xtensa_format fmt = vinsn->format;
11713 xtensa_insnbuf insnbuf = vinsn->insnbuf;
11714 int slot;
11715 bfd_boolean has_fixup = FALSE;
11716
11717 xtensa_format_encode (isa, fmt, insnbuf);
11718
11719 for (slot = 0; slot < vinsn->num_slots; slot++)
11720 {
11721 TInsn *tinsn = &vinsn->slots[slot];
11722 bfd_boolean tinsn_has_fixup =
11723 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11724 vinsn->slotbuf[slot]);
11725
11726 xtensa_format_set_slot (isa, fmt, slot,
11727 insnbuf, vinsn->slotbuf[slot]);
11728 /* tinsn_has_fixup tracks if there is a fixup at all.
11729 record_fixup controls globally. I.E., we use this
11730 function from several places, some of which are after
11731 fixups have already been recorded. Finally,
11732 tinsn->record_fixup controls based on the individual ops,
11733 which may or may not need it based on the relaxation
11734 requirements. */
11735 if (tinsn_has_fixup && record_fixup)
11736 {
11737 int i;
11738 xtensa_opcode opcode = tinsn->opcode;
11739 int noperands = xtensa_opcode_num_operands (isa, opcode);
11740 has_fixup = TRUE;
11741
11742 for (i = 0; i < noperands; i++)
11743 {
11744 expressionS* expr = &tinsn->tok[i];
11745 switch (expr->X_op)
11746 {
11747 case O_symbol:
11748 case O_lo16:
11749 case O_hi16:
11750 if (get_relaxable_immed (opcode) == i)
11751 {
11752 if (tinsn->record_fix || expr->X_op != O_symbol)
11753 {
11754 if (!xg_add_opcode_fix
11755 (tinsn, i, fmt, slot, expr, fragP,
11756 frag_offset - fragP->fr_literal))
11757 as_bad (_("instruction with constant operands does not fit"));
11758 }
11759 else
11760 {
11761 tinsn->symbol = expr->X_add_symbol;
11762 tinsn->offset = expr->X_add_number;
11763 }
11764 }
11765 else
11766 as_bad (_("invalid operand %d on '%s'"),
11767 i, xtensa_opcode_name (isa, opcode));
11768 break;
11769
11770 case O_constant:
11771 case O_register:
11772 break;
11773
11774 case O_subtract:
11775 if (get_relaxable_immed (opcode) == i)
11776 {
11777 if (tinsn->record_fix)
11778 as_bad (_("invalid subtract operand"));
11779 else
11780 {
11781 tinsn->symbol = expr->X_add_symbol;
11782 tinsn->sub_symbol = expr->X_op_symbol;
11783 tinsn->offset = expr->X_add_number;
11784 }
11785 }
11786 else
11787 as_bad (_("invalid operand %d on '%s'"),
11788 i, xtensa_opcode_name (isa, opcode));
11789 break;
11790
11791 default:
11792 as_bad (_("invalid expression for operand %d on '%s'"),
11793 i, xtensa_opcode_name (isa, opcode));
11794 break;
11795 }
11796 }
11797 }
11798 }
11799
11800 return has_fixup;
11801}
11802
11803
11804static void
7fa3d080 11805vinsn_from_chars (vliw_insn *vinsn, char *f)
43cd72b9
BW		 11806{
11807 static xtensa_insnbuf insnbuf = NULL;
11808 static xtensa_insnbuf slotbuf = NULL;
11809 int i;
11810 xtensa_format fmt;
11811 xtensa_isa isa = xtensa_default_isa;
11812
11813 if (!insnbuf)
11814 {
11815 insnbuf = xtensa_insnbuf_alloc (isa);
11816 slotbuf = xtensa_insnbuf_alloc (isa);
11817 }
11818
11819 xtensa_insnbuf_from_chars (isa, insnbuf, f, 0);
11820 fmt = xtensa_format_decode (isa, insnbuf);
11821 if (fmt == XTENSA_UNDEFINED)
11822 as_fatal (_("cannot decode instruction format"));
11823 vinsn->format = fmt;
11824 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11825
11826 for (i = 0; i < vinsn->num_slots; i++)
11827 {
11828 TInsn *tinsn = &vinsn->slots[i];
11829 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
11830 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
11831 }
11832}
11833
e0001a05
NC		 11834\f
11835/* Expression utilities. */
11836
43cd72b9 11837/* Return TRUE if the expression is an integer constant. */
e0001a05
NC		 11838
11839bfd_boolean
7fa3d080 11840expr_is_const (const expressionS *s)
e0001a05
NC		 11841{
11842 return (s->X_op == O_constant);
11843}
11844
11845
11846/* Get the expression constant.
43cd72b9 11847 Calling this is illegal if expr_is_const () returns TRUE. */
e0001a05
NC		 11848
11849offsetT
7fa3d080 11850get_expr_const (const expressionS *s)
e0001a05
NC		 11851{
11852 assert (expr_is_const (s));
11853 return s->X_add_number;
11854}
11855
11856
11857/* Set the expression to a constant value. */
11858
11859void
7fa3d080 11860set_expr_const (expressionS *s, offsetT val)
e0001a05
NC		 11861{
11862 s->X_op = O_constant;
11863 s->X_add_number = val;
11864 s->X_add_symbol = NULL;
11865 s->X_op_symbol = NULL;
11866}
11867
11868
43cd72b9 11869bfd_boolean
7fa3d080 11870expr_is_register (const expressionS *s)
43cd72b9
BW		 11871{
11872 return (s->X_op == O_register);
11873}
11874
11875
11876/* Get the expression constant.
11877 Calling this is illegal if expr_is_const () returns TRUE. */
11878
11879offsetT
7fa3d080 11880get_expr_register (const expressionS *s)
43cd72b9
BW		 11881{
11882 assert (expr_is_register (s));
11883 return s->X_add_number;
11884}
11885
11886
e0001a05
NC		 11887/* Set the expression to a symbol + constant offset. */
11888
11889void
7fa3d080 11890set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
e0001a05
NC		 11891{
11892 s->X_op = O_symbol;
11893 s->X_add_symbol = sym;
11894 s->X_op_symbol = NULL; /* unused */
11895 s->X_add_number = offset;
11896}
11897
11898
43cd72b9
BW		 11899/* Set the expression to symbol - minus_sym + offset. */
11900
7fa3d080
BW		 11901static void
11902set_expr_symbol_offset_diff (expressionS *s,
11903 symbolS *sym,
11904 symbolS *minus_sym,
11905 offsetT offset)
43cd72b9
BW		 11906{
11907 s->X_op = O_subtract;
11908 s->X_add_symbol = sym;
11909 s->X_op_symbol = minus_sym; /* unused */
11910 s->X_add_number = offset;
11911}
11912
11913
11914/* Return TRUE if the two expressions are equal. */
11915
e0001a05 11916bfd_boolean
7fa3d080 11917expr_is_equal (expressionS *s1, expressionS *s2)
e0001a05
NC		 11918{
11919 if (s1->X_op != s2->X_op)
11920 return FALSE;
11921 if (s1->X_add_symbol != s2->X_add_symbol)
11922 return FALSE;
11923 if (s1->X_op_symbol != s2->X_op_symbol)
11924 return FALSE;
11925 if (s1->X_add_number != s2->X_add_number)
11926 return FALSE;
11927 return TRUE;
11928}
11929
11930
11931static void
7fa3d080 11932copy_expr (expressionS *dst, const expressionS *src)
e0001a05
NC		 11933{
11934 memcpy (dst, src, sizeof (expressionS));
11935}
11936
11937\f
9456465c 11938/* Support for the "--rename-section" option. */
e0001a05
NC		 11939
11940struct rename_section_struct
11941{
11942 char *old_name;
11943 char *new_name;
11944 struct rename_section_struct *next;
11945};
11946
11947static struct rename_section_struct *section_rename;
11948
11949
9456465c
BW		 11950/* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11951 entries to the section_rename list. Note: Specifying multiple
11952 renamings separated by colons is not documented and is retained only
11953 for backward compatibility. */
e0001a05 11954
7fa3d080
BW		 11955static void
11956build_section_rename (const char *arg)
e0001a05 11957{
9456465c 11958 struct rename_section_struct *r;
e0001a05
NC		 11959 char *this_arg = NULL;
11960 char *next_arg = NULL;
11961
9456465c 11962 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
e0001a05 11963 {
9456465c
BW		 11964 char *old_name, *new_name;
11965
e0001a05
NC		 11966 if (this_arg)
11967 {
11968 next_arg = strchr (this_arg, ':');
11969 if (next_arg)
11970 {
11971 *next_arg = '\0';
11972 next_arg++;
11973 }
11974 }
e0001a05 11975
9456465c
BW		 11976 old_name = this_arg;
11977 new_name = strchr (this_arg, '=');
e0001a05 11978
9456465c
BW		 11979 if (*old_name == '\0')
11980 {
11981 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11982 continue;
11983 }
11984 if (!new_name || new_name[1] == '\0')
11985 {
11986 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11987 old_name);
11988 continue;
11989 }
11990 *new_name = '\0';
11991 new_name++;
e0001a05 11992
9456465c
BW		 11993 /* Check for invalid section renaming. */
11994 for (r = section_rename; r != NULL; r = r->next)
11995 {
11996 if (strcmp (r->old_name, old_name) == 0)
11997 as_bad (_("section %s renamed multiple times"), old_name);
11998 if (strcmp (r->new_name, new_name) == 0)
11999 as_bad (_("multiple sections remapped to output section %s"),
12000 new_name);
12001 }
e0001a05 12002
9456465c
BW		 12003 /* Now add it. */
12004 r = (struct rename_section_struct *)
12005 xmalloc (sizeof (struct rename_section_struct));
12006 r->old_name = xstrdup (old_name);
12007 r->new_name = xstrdup (new_name);
12008 r->next = section_rename;
12009 section_rename = r;
e0001a05 12010 }
e0001a05
NC		 12011}
12012
12013
9456465c
BW		 12014char *
12015xtensa_section_rename (char *name)
e0001a05
NC		 12016{
12017 struct rename_section_struct *r = section_rename;
12018
12019 for (r = section_rename; r != NULL; r = r->next)
43cd72b9
BW		 12020 {
12021 if (strcmp (r->old_name, name) == 0)
12022 return r->new_name;
12023 }
e0001a05
NC		 12024
12025 return name;
12026}
GDB Binutils - Deliverables
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