Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
250d07de | 2 | Copyright (C) 2003-2021 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
e0001a05 | 21 | #include "as.h" |
df7b86aa | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "sb.h" |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 | 30 | #include "xtensa-config.h" |
b0b79343 | 31 | #include "elf/xtensa.h" |
e0001a05 | 32 | |
2caa7ca0 | 33 | /* Provide default values for new configuration settings. */ |
7a77f1ac MF |
34 | #ifndef XTHAL_ABI_WINDOWED |
35 | #define XTHAL_ABI_WINDOWED 0 | |
36 | #endif | |
37 | ||
38 | #ifndef XTHAL_ABI_CALL0 | |
39 | #define XTHAL_ABI_CALL0 1 | |
2caa7ca0 BW |
40 | #endif |
41 | ||
935f1f4b MF |
42 | #ifndef XTENSA_MARCH_EARLIEST |
43 | #define XTENSA_MARCH_EARLIEST 0 | |
44 | #endif | |
45 | ||
e0001a05 NC |
46 | #ifndef uint32 |
47 | #define uint32 unsigned int | |
48 | #endif | |
49 | #ifndef int32 | |
50 | #define int32 signed int | |
51 | #endif | |
52 | ||
53 | /* Notes: | |
54 | ||
e0001a05 NC |
55 | Naming conventions (used somewhat inconsistently): |
56 | The xtensa_ functions are exported | |
57 | The xg_ functions are internal | |
58 | ||
59 | We also have a couple of different extensibility mechanisms. | |
60 | 1) The idiom replacement: | |
61 | This is used when a line is first parsed to | |
62 | replace an instruction pattern with another instruction | |
63 | It is currently limited to replacements of instructions | |
64 | with constant operands. | |
65 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
66 | replacement patterns. When an instruction's immediate field | |
67 | does not fit the next instruction sequence is attempted. | |
68 | In addition, "narrow" opcodes are supported this way. */ | |
69 | ||
70 | ||
71 | /* Define characters with special meanings to GAS. */ | |
72 | const char comment_chars[] = "#"; | |
73 | const char line_comment_chars[] = "#"; | |
74 | const char line_separator_chars[] = ";"; | |
75 | const char EXP_CHARS[] = "eE"; | |
76 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
77 | ||
78 | ||
43cd72b9 BW |
79 | /* Flags to indicate whether the hardware supports the density and |
80 | absolute literals options. */ | |
e0001a05 | 81 | |
f7e16c2a MF |
82 | bfd_boolean density_supported; |
83 | bfd_boolean absolute_literals_supported; | |
43cd72b9 | 84 | |
935f1f4b MF |
85 | static unsigned microarch_earliest; |
86 | ||
43cd72b9 BW |
87 | static vliw_insn cur_vinsn; |
88 | ||
77cba8a3 | 89 | unsigned xtensa_num_pipe_stages; |
f7e16c2a | 90 | unsigned xtensa_fetch_width; |
43cd72b9 BW |
91 | |
92 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
93 | ||
94 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 95 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
96 | back end. */ |
97 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
98 | |
99 | /* Flags for properties of the last instruction in a segment. */ | |
100 | #define FLAG_IS_A0_WRITER 0x1 | |
101 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
102 | ||
103 | ||
104 | /* We define a special segment names ".literal" to place literals | |
105 | into. The .fini and .init sections are special because they | |
106 | contain code that is moved together by the linker. We give them | |
107 | their own special .fini.literal and .init.literal sections. */ | |
108 | ||
109 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 110 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 111 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 112 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
113 | |
114 | ||
43cd72b9 | 115 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
116 | state of the literal collection pools. If lit_prefix is set, it is |
117 | used to determine the literal section names; otherwise, the literal | |
118 | sections are determined based on the current text section. The | |
119 | lit_seg and lit4_seg fields cache these literal sections, with the | |
120 | current_text_seg field used a tag to indicate whether the cached | |
121 | values are valid. */ | |
e0001a05 NC |
122 | |
123 | typedef struct lit_state_struct | |
124 | { | |
74869ac7 BW |
125 | char *lit_prefix; |
126 | segT current_text_seg; | |
e0001a05 | 127 | segT lit_seg; |
43cd72b9 | 128 | segT lit4_seg; |
e0001a05 NC |
129 | } lit_state; |
130 | ||
131 | static lit_state default_lit_sections; | |
132 | ||
133 | ||
74869ac7 BW |
134 | /* We keep a list of literal segments. The seg_list type is the node |
135 | for this list. The literal_head pointer is the head of the list, | |
136 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
137 | |
138 | typedef struct seg_list_struct | |
139 | { | |
140 | struct seg_list_struct *next; | |
141 | segT seg; | |
142 | } seg_list; | |
143 | ||
144 | static seg_list literal_head_h; | |
145 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
146 | |
147 | ||
82e7541d BW |
148 | /* Lists of symbols. We keep a list of symbols that label the current |
149 | instruction, so that we can adjust the symbols when inserting alignment | |
150 | for various instructions. We also keep a list of all the symbols on | |
151 | literals, so that we can fix up those symbols when the literals are | |
152 | later moved into the text sections. */ | |
153 | ||
154 | typedef struct sym_list_struct | |
155 | { | |
156 | struct sym_list_struct *next; | |
157 | symbolS *sym; | |
158 | } sym_list; | |
159 | ||
160 | static sym_list *insn_labels = NULL; | |
161 | static sym_list *free_insn_labels = NULL; | |
162 | static sym_list *saved_insn_labels = NULL; | |
163 | ||
164 | static sym_list *literal_syms; | |
165 | ||
166 | ||
43cd72b9 BW |
167 | /* Flags to determine whether to prefer const16 or l32r |
168 | if both options are available. */ | |
169 | int prefer_const16 = 0; | |
170 | int prefer_l32r = 0; | |
171 | ||
e0001a05 NC |
172 | /* Global flag to indicate when we are emitting literals. */ |
173 | int generating_literals = 0; | |
174 | ||
43cd72b9 BW |
175 | /* The following PROPERTY table definitions are copied from |
176 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
177 | ||
178 | /* Flags in the property tables to specify whether blocks of memory | |
179 | are literals, instructions, data, or unreachable. For | |
180 | instructions, blocks that begin loop targets and branch targets are | |
181 | designated. Blocks that do not allow density, instruction | |
182 | reordering or transformation are also specified. Finally, for | |
183 | branch targets, branch target alignment priority is included. | |
184 | Alignment of the next block is specified in the current block | |
185 | and the size of the current block does not include any fill required | |
186 | to align to the next block. */ | |
187 | ||
188 | #define XTENSA_PROP_LITERAL 0x00000001 | |
189 | #define XTENSA_PROP_INSN 0x00000002 | |
190 | #define XTENSA_PROP_DATA 0x00000004 | |
191 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
192 | /* Instruction only properties at beginning of code. */ | |
193 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
194 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
195 | /* Instruction only properties about code. */ | |
196 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
197 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
198 | /* Historically, NO_TRANSFORM was a property of instructions, |
199 | but it should apply to literals under certain circumstances. */ | |
200 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
201 | |
202 | /* Branch target alignment information. This transmits information | |
203 | to the linker optimization about the priority of aligning a | |
204 | particular block for branch target alignment: None, low priority, | |
205 | high priority, or required. These only need to be checked in | |
206 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
207 | Common usage is | |
208 | ||
209 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
210 | case XTENSA_PROP_BT_ALIGN_NONE: | |
211 | case XTENSA_PROP_BT_ALIGN_LOW: | |
212 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
213 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
214 | */ | |
215 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
216 | ||
217 | /* No branch target alignment. */ | |
218 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
219 | /* Low priority branch target alignment. */ | |
220 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
221 | /* High priority branch target alignment. */ | |
222 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
223 | /* Required branch target alignment. */ | |
224 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
225 | ||
43cd72b9 BW |
226 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ |
227 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
228 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
229 | ||
230 | ||
231 | /* Alignment is specified in the block BEFORE the one that needs | |
232 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
233 | get the required alignment specified as a power of 2. Use | |
234 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
235 | alignment. Be careful of side effects since the SET will evaluate | |
236 | flags twice. Also, note that the SIZE of a block in the property | |
237 | table does not include the alignment size, so the alignment fill | |
238 | must be calculated to determine if two blocks are contiguous. | |
239 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
240 | possible future implementation. */ | |
241 | ||
242 | #define XTENSA_PROP_ALIGN 0x00000800 | |
243 | ||
244 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
245 | ||
43cd72b9 BW |
246 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ |
247 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
248 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
249 | ||
250 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
251 | ||
252 | ||
253 | /* Structure for saving instruction and alignment per-fragment data | |
254 | that will be written to the object file. This structure is | |
255 | equivalent to the actual data that will be written out to the file | |
256 | but is easier to use. We provide a conversion to file flags | |
257 | in frag_flags_to_number. */ | |
258 | ||
259 | typedef struct frag_flags_struct frag_flags; | |
260 | ||
261 | struct frag_flags_struct | |
262 | { | |
263 | /* is_literal should only be used after xtensa_move_literals. | |
264 | If you need to check if you are generating a literal fragment, | |
265 | then use the generating_literals global. */ | |
266 | ||
267 | unsigned is_literal : 1; | |
268 | unsigned is_insn : 1; | |
269 | unsigned is_data : 1; | |
270 | unsigned is_unreachable : 1; | |
271 | ||
99ded152 BW |
272 | /* is_specific_opcode implies no_transform. */ |
273 | unsigned is_no_transform : 1; | |
274 | ||
43cd72b9 BW |
275 | struct |
276 | { | |
277 | unsigned is_loop_target : 1; | |
278 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
279 | unsigned bt_align_priority : 2; | |
280 | ||
281 | unsigned is_no_density : 1; | |
282 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
283 | |
284 | unsigned is_no_reorder : 1; | |
285 | ||
286 | /* Uses absolute literal addressing for l32r. */ | |
287 | unsigned is_abslit : 1; | |
288 | } insn; | |
289 | unsigned is_align : 1; | |
290 | unsigned alignment : 5; | |
291 | }; | |
292 | ||
293 | ||
294 | /* Structure for saving information about a block of property data | |
295 | for frags that have the same flags. */ | |
296 | struct xtensa_block_info_struct | |
297 | { | |
298 | segT sec; | |
299 | bfd_vma offset; | |
300 | size_t size; | |
301 | frag_flags flags; | |
302 | struct xtensa_block_info_struct *next; | |
303 | }; | |
304 | ||
e0001a05 NC |
305 | |
306 | /* Structure for saving the current state before emitting literals. */ | |
307 | typedef struct emit_state_struct | |
308 | { | |
309 | const char *name; | |
310 | segT now_seg; | |
311 | subsegT now_subseg; | |
312 | int generating_literals; | |
313 | } emit_state; | |
314 | ||
315 | ||
43cd72b9 BW |
316 | /* Opcode placement information */ |
317 | ||
318 | typedef unsigned long long bitfield; | |
319 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
320 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
321 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
322 | ||
323 | #define MAX_FORMATS 32 | |
324 | ||
325 | typedef struct op_placement_info_struct | |
326 | { | |
327 | int num_formats; | |
328 | /* A number describing how restrictive the issue is for this | |
329 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 330 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 331 | only one format but many slots in that format. The most |
c138bc38 | 332 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
333 | format. */ |
334 | int issuef; | |
43cd72b9 | 335 | xtensa_format narrowest; |
43cd72b9 | 336 | char narrowest_size; |
b2d179be | 337 | char narrowest_slot; |
43cd72b9 BW |
338 | |
339 | /* formats is a bitfield with the Nth bit set | |
340 | if the opcode fits in the Nth xtensa_format. */ | |
341 | bitfield formats; | |
342 | ||
343 | /* slots[N]'s Mth bit is set if the op fits in the | |
344 | Mth slot of the Nth xtensa_format. */ | |
345 | bitfield slots[MAX_FORMATS]; | |
346 | ||
347 | /* A count of the number of slots in a given format | |
348 | an op can fit (i.e., the bitcount of the slot field above). */ | |
349 | char slots_in_format[MAX_FORMATS]; | |
350 | ||
351 | } op_placement_info, *op_placement_info_table; | |
352 | ||
353 | op_placement_info_table op_placement_table; | |
354 | ||
355 | ||
356 | /* Extra expression types. */ | |
357 | ||
358 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
359 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
360 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 361 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
362 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
363 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
364 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
365 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
366 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 367 | |
bbdd25a8 BW |
368 | struct suffix_reloc_map |
369 | { | |
b9bb4a93 | 370 | const char *suffix; |
bbdd25a8 BW |
371 | int length; |
372 | bfd_reloc_code_real_type reloc; | |
cc34adb2 | 373 | operatorT operator; |
bbdd25a8 BW |
374 | }; |
375 | ||
376 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
377 | ||
378 | static struct suffix_reloc_map suffix_relocs[] = | |
379 | { | |
380 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
381 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
382 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 383 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
384 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
385 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
386 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
387 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
388 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
389 | }; |
390 | ||
43cd72b9 | 391 | |
e0001a05 NC |
392 | /* Directives. */ |
393 | ||
394 | typedef enum | |
395 | { | |
396 | directive_none = 0, | |
397 | directive_literal, | |
398 | directive_density, | |
43cd72b9 | 399 | directive_transform, |
e0001a05 NC |
400 | directive_freeregs, |
401 | directive_longcalls, | |
43cd72b9 BW |
402 | directive_literal_prefix, |
403 | directive_schedule, | |
404 | directive_absolute_literals, | |
405 | directive_last_directive | |
e0001a05 NC |
406 | } directiveE; |
407 | ||
408 | typedef struct | |
409 | { | |
410 | const char *name; | |
411 | bfd_boolean can_be_negated; | |
412 | } directive_infoS; | |
413 | ||
414 | const directive_infoS directive_info[] = | |
415 | { | |
43cd72b9 BW |
416 | { "none", FALSE }, |
417 | { "literal", FALSE }, | |
418 | { "density", TRUE }, | |
419 | { "transform", TRUE }, | |
420 | { "freeregs", FALSE }, | |
421 | { "longcalls", TRUE }, | |
422 | { "literal_prefix", FALSE }, | |
423 | { "schedule", TRUE }, | |
424 | { "absolute-literals", TRUE } | |
e0001a05 NC |
425 | }; |
426 | ||
427 | bfd_boolean directive_state[] = | |
428 | { | |
429 | FALSE, /* none */ | |
430 | FALSE, /* literal */ | |
e0001a05 | 431 | FALSE, /* density */ |
43cd72b9 | 432 | TRUE, /* transform */ |
e0001a05 NC |
433 | FALSE, /* freeregs */ |
434 | FALSE, /* longcalls */ | |
43cd72b9 | 435 | FALSE, /* literal_prefix */ |
2caa7ca0 | 436 | FALSE, /* schedule */ |
43cd72b9 | 437 | FALSE /* absolute_literals */ |
e0001a05 NC |
438 | }; |
439 | ||
b46824bd MF |
440 | /* A circular list of all potential and actual literal pool locations |
441 | in a segment. */ | |
442 | struct litpool_frag | |
443 | { | |
444 | struct litpool_frag *next; | |
445 | struct litpool_frag *prev; | |
446 | fragS *fragP; | |
447 | addressT addr; | |
448 | short priority; /* 1, 2, or 3 -- 1 is highest */ | |
449 | short original_priority; | |
cd665a94 | 450 | int literal_count; |
b46824bd MF |
451 | }; |
452 | ||
453 | /* Map a segment to its litpool_frag list. */ | |
454 | struct litpool_seg | |
455 | { | |
456 | struct litpool_seg *next; | |
457 | asection *seg; | |
458 | struct litpool_frag frag_list; | |
459 | int frag_count; /* since last litpool location */ | |
460 | }; | |
461 | ||
462 | static struct litpool_seg litpool_seg_list; | |
463 | ||
cd665a94 MF |
464 | /* Limit maximal size of auto litpool by half of the j range. */ |
465 | #define MAX_AUTO_POOL_LITERALS 16384 | |
466 | ||
467 | /* Limit maximal size of explicit literal pool by l32r range. */ | |
468 | #define MAX_EXPLICIT_POOL_LITERALS 65536 | |
469 | ||
470 | #define MAX_POOL_LITERALS \ | |
471 | (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS) | |
e0001a05 NC |
472 | |
473 | /* Directive functions. */ | |
474 | ||
7fa3d080 BW |
475 | static void xtensa_begin_directive (int); |
476 | static void xtensa_end_directive (int); | |
74869ac7 | 477 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
478 | static void xtensa_literal_position (int); |
479 | static void xtensa_literal_pseudo (int); | |
480 | static void xtensa_frequency_pseudo (int); | |
481 | static void xtensa_elf_cons (int); | |
fb227da0 | 482 | static void xtensa_leb128 (int); |
e0001a05 | 483 | |
7fa3d080 | 484 | /* Parsing and Idiom Translation. */ |
e0001a05 | 485 | |
7fa3d080 | 486 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 487 | |
e0001a05 NC |
488 | /* Various Other Internal Functions. */ |
489 | ||
84b08ed9 BW |
490 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
491 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
492 | static void xtensa_mark_literal_pool_location (void); |
493 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
494 | static fragS *get_literal_pool_location (segT); | |
495 | static void set_literal_pool_location (segT, fragS *); | |
496 | static void xtensa_set_frag_assembly_state (fragS *); | |
497 | static void finish_vinsn (vliw_insn *); | |
498 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 499 | static int total_frag_text_expansion (fragS *); |
a82c7d90 DW |
500 | static bfd_boolean use_trampolines = TRUE; |
501 | static void xtensa_check_frag_count (void); | |
502 | static void xtensa_create_trampoline_frag (bfd_boolean); | |
503 | static void xtensa_maybe_create_trampoline_frag (void); | |
504 | struct trampoline_frag; | |
46888d71 MF |
505 | static int init_trampoline_frag (fragS *); |
506 | static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset); | |
b46824bd MF |
507 | static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean); |
508 | static bfd_boolean auto_litpools = FALSE; | |
cd665a94 | 509 | static int auto_litpool_limit = 0; |
54879176 | 510 | static bfd_boolean xtensa_is_init_fini (segT seg); |
e0001a05 NC |
511 | |
512 | /* Alignment Functions. */ | |
513 | ||
d77b99c9 BW |
514 | static int get_text_align_power (unsigned); |
515 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 516 | static int branch_align_power (segT); |
e0001a05 NC |
517 | |
518 | /* Helpers for xtensa_relax_frag(). */ | |
519 | ||
7fa3d080 | 520 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 521 | |
b08b5071 | 522 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 523 | |
7fa3d080 BW |
524 | static unsigned get_last_insn_flags (segT, subsegT); |
525 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
526 | static float get_subseg_total_freq (segT, subsegT); |
527 | static float get_subseg_target_freq (segT, subsegT); | |
528 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
529 | |
530 | /* Segment list functions. */ | |
531 | ||
7fa3d080 BW |
532 | static void xtensa_move_literals (void); |
533 | static void xtensa_reorder_segments (void); | |
534 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
535 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
536 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
537 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 538 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 539 | |
43cd72b9 BW |
540 | /* op_placement_info functions. */ |
541 | ||
7fa3d080 BW |
542 | static void init_op_placement_info_table (void); |
543 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
544 | static int xg_get_single_size (xtensa_opcode); | |
545 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 546 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 547 | |
e0001a05 | 548 | /* TInsn and IStack functions. */ |
43cd72b9 | 549 | |
7fa3d080 BW |
550 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
551 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
552 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
553 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
554 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
555 | static void tinsn_from_chars (TInsn *, char *, int); | |
556 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
557 | static int get_num_stack_text_bytes (IStack *); | |
558 | static int get_num_stack_literal_bytes (IStack *); | |
a82c7d90 | 559 | static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); |
e0001a05 | 560 | |
43cd72b9 BW |
561 | /* vliw_insn functions. */ |
562 | ||
7fa3d080 | 563 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 564 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 BW |
565 | static void xg_clear_vinsn (vliw_insn *); |
566 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
567 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 568 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
569 | (vliw_insn *, char *, fragS *, bfd_boolean); |
570 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 571 | |
e0001a05 | 572 | /* Expression Utilities. */ |
43cd72b9 | 573 | |
7fa3d080 BW |
574 | bfd_boolean expr_is_const (const expressionS *); |
575 | offsetT get_expr_const (const expressionS *); | |
576 | void set_expr_const (expressionS *, offsetT); | |
577 | bfd_boolean expr_is_register (const expressionS *); | |
578 | offsetT get_expr_register (const expressionS *); | |
579 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
580 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
581 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 582 | |
9456465c BW |
583 | /* Section renaming. */ |
584 | ||
7fa3d080 | 585 | static void build_section_rename (const char *); |
e0001a05 | 586 | |
e0001a05 NC |
587 | |
588 | /* ISA imported from bfd. */ | |
589 | extern xtensa_isa xtensa_default_isa; | |
590 | ||
591 | extern int target_big_endian; | |
592 | ||
593 | static xtensa_opcode xtensa_addi_opcode; | |
594 | static xtensa_opcode xtensa_addmi_opcode; | |
595 | static xtensa_opcode xtensa_call0_opcode; | |
596 | static xtensa_opcode xtensa_call4_opcode; | |
597 | static xtensa_opcode xtensa_call8_opcode; | |
598 | static xtensa_opcode xtensa_call12_opcode; | |
599 | static xtensa_opcode xtensa_callx0_opcode; | |
600 | static xtensa_opcode xtensa_callx4_opcode; | |
601 | static xtensa_opcode xtensa_callx8_opcode; | |
602 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 603 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 604 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 605 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
606 | static xtensa_opcode xtensa_movi_opcode; |
607 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 608 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 609 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 610 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 611 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
612 | static xtensa_opcode xtensa_loop_opcode; |
613 | static xtensa_opcode xtensa_loopnez_opcode; | |
614 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 615 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
616 | static xtensa_opcode xtensa_nop_n_opcode; |
617 | static xtensa_opcode xtensa_or_opcode; | |
618 | static xtensa_opcode xtensa_ret_opcode; | |
619 | static xtensa_opcode xtensa_ret_n_opcode; | |
620 | static xtensa_opcode xtensa_retw_opcode; | |
621 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 622 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 623 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 624 | static int config_max_slots = 0; |
e0001a05 NC |
625 | |
626 | \f | |
627 | /* Command-line Options. */ | |
628 | ||
629 | bfd_boolean use_literal_section = TRUE; | |
19fc3723 | 630 | enum flix_level produce_flix = FLIX_ALL; |
e0001a05 | 631 | static bfd_boolean align_targets = TRUE; |
43cd72b9 | 632 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 633 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
634 | static bfd_boolean workaround_a0_b_retw = FALSE; |
635 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
636 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 637 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 638 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 639 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 640 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
9632a526 | 641 | static bfd_boolean opt_linkrelax = TRUE; |
e0001a05 | 642 | |
43cd72b9 BW |
643 | /* When workaround_short_loops is TRUE, all loops with early exits must |
644 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
645 | to the workaround_short_loop flag. In addition to the | |
646 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
647 | must have at least 3 instructions. */ | |
e0001a05 | 648 | |
43cd72b9 | 649 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 650 | |
8255c61b MF |
651 | /* Generate individual property section for every section. |
652 | This option is defined in BDF library. */ | |
653 | extern bfd_boolean elf32xtensa_separate_props; | |
7fa3d080 | 654 | |
7a77f1ac MF |
655 | /* Xtensa ABI. |
656 | This option is defined in BDF library. */ | |
657 | extern int elf32xtensa_abi; | |
658 | ||
7fa3d080 BW |
659 | static void |
660 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
661 | { | |
662 | if (earliest > latest) | |
663 | as_fatal (_("illegal range of target hardware versions")); | |
664 | ||
665 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
666 | if (earliest < 105000 || latest < 105000) | |
667 | { | |
668 | workaround_a0_b_retw |= TRUE; | |
669 | workaround_b_j_loop_end |= TRUE; | |
670 | workaround_short_loop |= TRUE; | |
671 | workaround_close_loop_end |= TRUE; | |
672 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 673 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
674 | } |
675 | } | |
676 | ||
677 | ||
e0001a05 NC |
678 | enum |
679 | { | |
680 | option_density = OPTION_MD_BASE, | |
681 | option_no_density, | |
682 | ||
19fc3723 SA |
683 | option_flix, |
684 | option_no_generate_flix, | |
685 | option_no_flix, | |
686 | ||
e0001a05 NC |
687 | option_relax, |
688 | option_no_relax, | |
689 | ||
43cd72b9 BW |
690 | option_link_relax, |
691 | option_no_link_relax, | |
692 | ||
e0001a05 NC |
693 | option_generics, |
694 | option_no_generics, | |
695 | ||
43cd72b9 BW |
696 | option_transform, |
697 | option_no_transform, | |
698 | ||
e0001a05 NC |
699 | option_text_section_literals, |
700 | option_no_text_section_literals, | |
701 | ||
43cd72b9 BW |
702 | option_absolute_literals, |
703 | option_no_absolute_literals, | |
704 | ||
e0001a05 NC |
705 | option_align_targets, |
706 | option_no_align_targets, | |
707 | ||
43cd72b9 | 708 | option_warn_unaligned_targets, |
e0001a05 NC |
709 | |
710 | option_longcalls, | |
711 | option_no_longcalls, | |
712 | ||
713 | option_workaround_a0_b_retw, | |
714 | option_no_workaround_a0_b_retw, | |
715 | ||
716 | option_workaround_b_j_loop_end, | |
717 | option_no_workaround_b_j_loop_end, | |
718 | ||
719 | option_workaround_short_loop, | |
720 | option_no_workaround_short_loop, | |
721 | ||
722 | option_workaround_all_short_loops, | |
723 | option_no_workaround_all_short_loops, | |
724 | ||
725 | option_workaround_close_loop_end, | |
726 | option_no_workaround_close_loop_end, | |
727 | ||
728 | option_no_workarounds, | |
729 | ||
e0001a05 | 730 | option_rename_section_name, |
e0001a05 | 731 | |
43cd72b9 BW |
732 | option_prefer_l32r, |
733 | option_prefer_const16, | |
734 | ||
a82c7d90 DW |
735 | option_target_hardware, |
736 | ||
737 | option_trampolines, | |
738 | option_no_trampolines, | |
b46824bd MF |
739 | |
740 | option_auto_litpools, | |
741 | option_no_auto_litpools, | |
742 | option_auto_litpool_limit, | |
8255c61b MF |
743 | |
744 | option_separate_props, | |
745 | option_no_separate_props, | |
7a77f1ac MF |
746 | |
747 | option_abi_windowed, | |
748 | option_abi_call0, | |
e0001a05 NC |
749 | }; |
750 | ||
751 | const char *md_shortopts = ""; | |
752 | ||
753 | struct option md_longopts[] = | |
754 | { | |
43cd72b9 BW |
755 | { "density", no_argument, NULL, option_density }, |
756 | { "no-density", no_argument, NULL, option_no_density }, | |
757 | ||
19fc3723 SA |
758 | { "flix", no_argument, NULL, option_flix }, |
759 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
760 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
761 | ||
43cd72b9 BW |
762 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
763 | to the "transform" option. */ | |
764 | { "relax", no_argument, NULL, option_relax }, | |
765 | { "no-relax", no_argument, NULL, option_no_relax }, | |
766 | { "generics", no_argument, NULL, option_generics }, | |
767 | { "no-generics", no_argument, NULL, option_no_generics }, | |
768 | ||
769 | { "transform", no_argument, NULL, option_transform }, | |
770 | { "no-transform", no_argument, NULL, option_no_transform }, | |
771 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
772 | { "no-text-section-literals", no_argument, NULL, | |
773 | option_no_text_section_literals }, | |
774 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
775 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
776 | /* This option was changed from -align-target to -target-align |
777 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 778 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
779 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
780 | { "warn-unaligned-targets", no_argument, NULL, | |
781 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
782 | { "longcalls", no_argument, NULL, option_longcalls }, |
783 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
784 | ||
785 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
786 | option_no_workaround_a0_b_retw }, | |
787 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 788 | |
43cd72b9 BW |
789 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
790 | option_no_workaround_b_j_loop_end }, | |
791 | { "workaround-b-j-loop-end", no_argument, NULL, | |
792 | option_workaround_b_j_loop_end }, | |
e0001a05 | 793 | |
43cd72b9 BW |
794 | { "no-workaround-short-loops", no_argument, NULL, |
795 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
796 | { "workaround-short-loops", no_argument, NULL, |
797 | option_workaround_short_loop }, | |
e0001a05 | 798 | |
43cd72b9 BW |
799 | { "no-workaround-all-short-loops", no_argument, NULL, |
800 | option_no_workaround_all_short_loops }, | |
801 | { "workaround-all-short-loop", no_argument, NULL, | |
802 | option_workaround_all_short_loops }, | |
803 | ||
804 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
805 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
806 | ||
807 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
808 | ||
809 | { "no-workaround-close-loop-end", no_argument, NULL, | |
810 | option_no_workaround_close_loop_end }, | |
811 | { "workaround-close-loop-end", no_argument, NULL, | |
812 | option_workaround_close_loop_end }, | |
e0001a05 | 813 | |
7fa3d080 | 814 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 815 | |
43cd72b9 BW |
816 | { "link-relax", no_argument, NULL, option_link_relax }, |
817 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
818 | ||
819 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
820 | ||
a82c7d90 DW |
821 | { "trampolines", no_argument, NULL, option_trampolines }, |
822 | { "no-trampolines", no_argument, NULL, option_no_trampolines }, | |
823 | ||
b46824bd MF |
824 | { "auto-litpools", no_argument, NULL, option_auto_litpools }, |
825 | { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools }, | |
826 | { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit }, | |
827 | ||
8255c61b MF |
828 | { "separate-prop-tables", no_argument, NULL, option_separate_props }, |
829 | ||
7a77f1ac MF |
830 | { "abi-windowed", no_argument, NULL, option_abi_windowed }, |
831 | { "abi-call0", no_argument, NULL, option_abi_call0 }, | |
832 | ||
43cd72b9 | 833 | { NULL, no_argument, NULL, 0 } |
e0001a05 NC |
834 | }; |
835 | ||
836 | size_t md_longopts_size = sizeof md_longopts; | |
837 | ||
838 | ||
839 | int | |
17b9d67d | 840 | md_parse_option (int c, const char *arg) |
e0001a05 NC |
841 | { |
842 | switch (c) | |
843 | { | |
844 | case option_density: | |
43cd72b9 | 845 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
846 | return 1; |
847 | case option_no_density: | |
43cd72b9 | 848 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 849 | return 1; |
43cd72b9 | 850 | case option_link_relax: |
9632a526 | 851 | opt_linkrelax = TRUE; |
e0001a05 | 852 | return 1; |
43cd72b9 | 853 | case option_no_link_relax: |
9632a526 | 854 | opt_linkrelax = FALSE; |
e0001a05 | 855 | return 1; |
19fc3723 SA |
856 | case option_flix: |
857 | produce_flix = FLIX_ALL; | |
858 | return 1; | |
859 | case option_no_generate_flix: | |
860 | produce_flix = FLIX_NO_GENERATE; | |
861 | return 1; | |
862 | case option_no_flix: | |
863 | produce_flix = FLIX_NONE; | |
864 | return 1; | |
43cd72b9 BW |
865 | case option_generics: |
866 | as_warn (_("--generics is deprecated; use --transform instead")); | |
867 | return md_parse_option (option_transform, arg); | |
868 | case option_no_generics: | |
869 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
870 | return md_parse_option (option_no_transform, arg); | |
871 | case option_relax: | |
872 | as_warn (_("--relax is deprecated; use --transform instead")); | |
873 | return md_parse_option (option_transform, arg); | |
874 | case option_no_relax: | |
875 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
876 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
877 | case option_longcalls: |
878 | directive_state[directive_longcalls] = TRUE; | |
879 | return 1; | |
880 | case option_no_longcalls: | |
881 | directive_state[directive_longcalls] = FALSE; | |
882 | return 1; | |
883 | case option_text_section_literals: | |
884 | use_literal_section = FALSE; | |
885 | return 1; | |
886 | case option_no_text_section_literals: | |
887 | use_literal_section = TRUE; | |
888 | return 1; | |
43cd72b9 BW |
889 | case option_absolute_literals: |
890 | if (!absolute_literals_supported) | |
891 | { | |
892 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
893 | return 0; | |
894 | } | |
895 | directive_state[directive_absolute_literals] = TRUE; | |
896 | return 1; | |
897 | case option_no_absolute_literals: | |
898 | directive_state[directive_absolute_literals] = FALSE; | |
899 | return 1; | |
900 | ||
e0001a05 NC |
901 | case option_workaround_a0_b_retw: |
902 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
903 | return 1; |
904 | case option_no_workaround_a0_b_retw: | |
905 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
906 | return 1; |
907 | case option_workaround_b_j_loop_end: | |
908 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
909 | return 1; |
910 | case option_no_workaround_b_j_loop_end: | |
911 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
912 | return 1; |
913 | ||
914 | case option_workaround_short_loop: | |
915 | workaround_short_loop = TRUE; | |
e0001a05 NC |
916 | return 1; |
917 | case option_no_workaround_short_loop: | |
918 | workaround_short_loop = FALSE; | |
e0001a05 NC |
919 | return 1; |
920 | ||
921 | case option_workaround_all_short_loops: | |
922 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
923 | return 1; |
924 | case option_no_workaround_all_short_loops: | |
925 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
926 | return 1; |
927 | ||
928 | case option_workaround_close_loop_end: | |
929 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
930 | return 1; |
931 | case option_no_workaround_close_loop_end: | |
932 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
933 | return 1; |
934 | ||
935 | case option_no_workarounds: | |
936 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 937 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 938 | workaround_short_loop = FALSE; |
e0001a05 | 939 | workaround_all_short_loops = FALSE; |
e0001a05 | 940 | workaround_close_loop_end = FALSE; |
e0001a05 | 941 | return 1; |
43cd72b9 | 942 | |
e0001a05 NC |
943 | case option_align_targets: |
944 | align_targets = TRUE; | |
945 | return 1; | |
946 | case option_no_align_targets: | |
947 | align_targets = FALSE; | |
948 | return 1; | |
949 | ||
43cd72b9 BW |
950 | case option_warn_unaligned_targets: |
951 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
952 | return 1; |
953 | ||
e0001a05 NC |
954 | case option_rename_section_name: |
955 | build_section_rename (arg); | |
956 | return 1; | |
e0001a05 NC |
957 | |
958 | case 'Q': | |
959 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
960 | should be emitted or not. FIXME: Not implemented. */ | |
961 | return 1; | |
c138bc38 | 962 | |
43cd72b9 BW |
963 | case option_prefer_l32r: |
964 | if (prefer_const16) | |
965 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
966 | prefer_l32r = 1; | |
967 | return 1; | |
968 | ||
969 | case option_prefer_const16: | |
970 | if (prefer_l32r) | |
971 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
972 | prefer_const16 = 1; | |
973 | return 1; | |
974 | ||
c138bc38 | 975 | case option_target_hardware: |
43cd72b9 BW |
976 | { |
977 | int earliest, latest = 0; | |
17b9d67d | 978 | char *end; |
43cd72b9 BW |
979 | if (*arg == 0 || *arg == '-') |
980 | as_fatal (_("invalid target hardware version")); | |
981 | ||
17b9d67d | 982 | earliest = strtol (arg, &end, 0); |
43cd72b9 | 983 | |
17b9d67d | 984 | if (*end == 0) |
43cd72b9 | 985 | latest = earliest; |
17b9d67d | 986 | else if (*end == '-') |
43cd72b9 | 987 | { |
17b9d67d | 988 | if (*++end == 0) |
43cd72b9 | 989 | as_fatal (_("invalid target hardware version")); |
17b9d67d | 990 | latest = strtol (end, &end, 0); |
43cd72b9 | 991 | } |
17b9d67d | 992 | if (*end != 0) |
43cd72b9 BW |
993 | as_fatal (_("invalid target hardware version")); |
994 | ||
995 | xtensa_setup_hw_workarounds (earliest, latest); | |
996 | return 1; | |
997 | } | |
998 | ||
999 | case option_transform: | |
1000 | /* This option has no affect other than to use the defaults, | |
1001 | which are already set. */ | |
1002 | return 1; | |
1003 | ||
1004 | case option_no_transform: | |
1005 | /* This option turns off all transformations of any kind. | |
1006 | However, because we want to preserve the state of other | |
1007 | directives, we only change its own field. Thus, before | |
1008 | you perform any transformation, always check if transform | |
1009 | is available. If you use the functions we provide for this | |
1010 | purpose, you will be ok. */ | |
1011 | directive_state[directive_transform] = FALSE; | |
1012 | return 1; | |
1013 | ||
a82c7d90 DW |
1014 | case option_trampolines: |
1015 | use_trampolines = TRUE; | |
1016 | return 1; | |
1017 | ||
1018 | case option_no_trampolines: | |
1019 | use_trampolines = FALSE; | |
1020 | return 1; | |
1021 | ||
b46824bd MF |
1022 | case option_auto_litpools: |
1023 | auto_litpools = TRUE; | |
1024 | use_literal_section = FALSE; | |
cd665a94 MF |
1025 | if (auto_litpool_limit <= 0) |
1026 | auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2; | |
b46824bd MF |
1027 | return 1; |
1028 | ||
1029 | case option_no_auto_litpools: | |
1030 | auto_litpools = FALSE; | |
1031 | auto_litpool_limit = -1; | |
1032 | return 1; | |
1033 | ||
1034 | case option_auto_litpool_limit: | |
1035 | { | |
1036 | int value = 0; | |
17b9d67d | 1037 | char *end; |
b46824bd MF |
1038 | if (auto_litpool_limit < 0) |
1039 | as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit")); | |
1040 | if (*arg == 0 || *arg == '-') | |
1041 | as_fatal (_("invalid auto-litpool-limit argument")); | |
17b9d67d TS |
1042 | value = strtol (arg, &end, 10); |
1043 | if (*end != 0) | |
b46824bd MF |
1044 | as_fatal (_("invalid auto-litpool-limit argument")); |
1045 | if (value < 100 || value > 10000) | |
1046 | as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)")); | |
1047 | auto_litpool_limit = value; | |
1048 | auto_litpools = TRUE; | |
1049 | use_literal_section = FALSE; | |
1050 | return 1; | |
1051 | } | |
1052 | ||
8255c61b MF |
1053 | case option_separate_props: |
1054 | elf32xtensa_separate_props = TRUE; | |
1055 | return 1; | |
1056 | ||
1057 | case option_no_separate_props: | |
1058 | elf32xtensa_separate_props = FALSE; | |
1059 | return 1; | |
1060 | ||
7a77f1ac MF |
1061 | case option_abi_windowed: |
1062 | elf32xtensa_abi = XTHAL_ABI_WINDOWED; | |
1063 | return 1; | |
1064 | ||
1065 | case option_abi_call0: | |
1066 | elf32xtensa_abi = XTHAL_ABI_CALL0; | |
1067 | return 1; | |
1068 | ||
e0001a05 NC |
1069 | default: |
1070 | return 0; | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | ||
1075 | void | |
7fa3d080 | 1076 | md_show_usage (FILE *stream) |
e0001a05 | 1077 | { |
43cd72b9 BW |
1078 | fputs ("\n\ |
1079 | Xtensa options:\n\ | |
9456465c BW |
1080 | --[no-]text-section-literals\n\ |
1081 | [Do not] put literals in the text section\n\ | |
1082 | --[no-]absolute-literals\n\ | |
1083 | [Do not] default to use non-PC-relative literals\n\ | |
1084 | --[no-]target-align [Do not] try to align branch targets\n\ | |
1085 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
1086 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
1087 | --flix both allow hand-written and generate flix bundles\n\ |
1088 | --no-generate-flix allow hand-written but do not generate\n\ | |
1089 | flix bundles\n\ | |
1090 | --no-allow-flix neither allow hand-written nor generate\n\ | |
1091 | flix bundles\n\ | |
a82c7d90 DW |
1092 | --rename-section old=new Rename section 'old' to 'new'\n\ |
1093 | --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ | |
b46824bd MF |
1094 | when jumps do not reach their targets\n\ |
1095 | --[no-]auto-litpools [Do not] automatically create literal pools\n\ | |
1096 | --auto-litpool-limit=<value>\n\ | |
1097 | (range 100-10000) Maximum number of blocks of\n\ | |
1098 | instructions to emit between literal pool\n\ | |
8255c61b MF |
1099 | locations; implies --auto-litpools flag\n\ |
1100 | --[no-]separate-prop-tables\n\ | |
1101 | [Do not] place Xtensa property records into\n\ | |
1102 | individual property sections for each section.\n\ | |
1103 | Default is to generate single property section.\n", stream); | |
e0001a05 NC |
1104 | } |
1105 | ||
7fa3d080 BW |
1106 | \f |
1107 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
1108 | |
1109 | static void | |
7fa3d080 | 1110 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 1111 | { |
7fa3d080 | 1112 | sym_list *l; |
43cd72b9 | 1113 | |
7fa3d080 | 1114 | if (!free_insn_labels) |
325801bd | 1115 | l = XNEW (sym_list); |
7fa3d080 | 1116 | else |
43cd72b9 | 1117 | { |
7fa3d080 BW |
1118 | l = free_insn_labels; |
1119 | free_insn_labels = l->next; | |
1120 | } | |
1121 | ||
1122 | l->sym = sym; | |
1123 | l->next = insn_labels; | |
1124 | insn_labels = l; | |
1125 | } | |
1126 | ||
1127 | ||
1128 | static void | |
1129 | xtensa_clear_insn_labels (void) | |
1130 | { | |
1131 | sym_list **pl; | |
1132 | ||
1133 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1134 | ; | |
1135 | *pl = insn_labels; | |
1136 | insn_labels = NULL; | |
1137 | } | |
1138 | ||
1139 | ||
7fa3d080 | 1140 | static void |
c3ea6048 | 1141 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1142 | { |
1143 | sym_list *lit; | |
1144 | ||
1145 | for (lit = insn_labels; lit; lit = lit->next) | |
1146 | { | |
1147 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1148 | S_SET_VALUE (lit_sym, new_offset); |
1149 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1150 | } |
1151 | } | |
1152 | ||
e0001a05 NC |
1153 | \f |
1154 | /* Directive data and functions. */ | |
1155 | ||
1156 | typedef struct state_stackS_struct | |
1157 | { | |
1158 | directiveE directive; | |
1159 | bfd_boolean negated; | |
1160 | bfd_boolean old_state; | |
1161 | const char *file; | |
1162 | unsigned int line; | |
1163 | const void *datum; | |
1164 | struct state_stackS_struct *prev; | |
1165 | } state_stackS; | |
1166 | ||
1167 | state_stackS *directive_state_stack; | |
1168 | ||
1169 | const pseudo_typeS md_pseudo_table[] = | |
1170 | { | |
43cd72b9 BW |
1171 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1172 | { "literal_position", xtensa_literal_position, 0 }, | |
1173 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1174 | { "long", xtensa_elf_cons, 4 }, | |
1175 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1176 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1177 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1178 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1179 | { "sleb128", xtensa_leb128, 1}, |
1180 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1181 | { "begin", xtensa_begin_directive, 0 }, |
1182 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1183 | { "literal", xtensa_literal_pseudo, 0 }, |
1184 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1185 | { NULL, 0, 0 }, | |
e0001a05 NC |
1186 | }; |
1187 | ||
1188 | ||
7fa3d080 BW |
1189 | static bfd_boolean |
1190 | use_transform (void) | |
e0001a05 | 1191 | { |
43cd72b9 BW |
1192 | /* After md_end, you should be checking frag by frag, rather |
1193 | than state directives. */ | |
9c2799c2 | 1194 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1195 | return directive_state[directive_transform]; |
e0001a05 NC |
1196 | } |
1197 | ||
1198 | ||
7fa3d080 BW |
1199 | static bfd_boolean |
1200 | do_align_targets (void) | |
e0001a05 | 1201 | { |
7b1cc377 BW |
1202 | /* Do not use this function after md_end; just look at align_targets |
1203 | instead. There is no target-align directive, so alignment is either | |
1204 | enabled for all frags or not done at all. */ | |
9c2799c2 | 1205 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1206 | return align_targets && use_transform (); |
e0001a05 NC |
1207 | } |
1208 | ||
1209 | ||
1210 | static void | |
7fa3d080 | 1211 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 | 1212 | { |
3b4dbbbf | 1213 | const char *file; |
e0001a05 | 1214 | unsigned int line; |
325801bd | 1215 | state_stackS *stack = XNEW (state_stackS); |
e0001a05 | 1216 | |
3b4dbbbf | 1217 | file = as_where (&line); |
e0001a05 NC |
1218 | |
1219 | stack->directive = directive; | |
1220 | stack->negated = negated; | |
1221 | stack->old_state = directive_state[directive]; | |
1222 | stack->file = file; | |
1223 | stack->line = line; | |
1224 | stack->datum = datum; | |
1225 | stack->prev = directive_state_stack; | |
1226 | directive_state_stack = stack; | |
1227 | ||
1228 | directive_state[directive] = !negated; | |
1229 | } | |
1230 | ||
7fa3d080 | 1231 | |
e0001a05 | 1232 | static void |
7fa3d080 BW |
1233 | directive_pop (directiveE *directive, |
1234 | bfd_boolean *negated, | |
1235 | const char **file, | |
1236 | unsigned int *line, | |
1237 | const void **datum) | |
e0001a05 NC |
1238 | { |
1239 | state_stackS *top = directive_state_stack; | |
1240 | ||
1241 | if (!directive_state_stack) | |
1242 | { | |
33eaf5de | 1243 | as_bad (_("unmatched .end directive")); |
e0001a05 NC |
1244 | *directive = directive_none; |
1245 | return; | |
1246 | } | |
1247 | ||
1248 | directive_state[directive_state_stack->directive] = top->old_state; | |
1249 | *directive = top->directive; | |
1250 | *negated = top->negated; | |
1251 | *file = top->file; | |
1252 | *line = top->line; | |
1253 | *datum = top->datum; | |
1254 | directive_state_stack = top->prev; | |
1255 | free (top); | |
1256 | } | |
1257 | ||
1258 | ||
1259 | static void | |
7fa3d080 | 1260 | directive_balance (void) |
e0001a05 NC |
1261 | { |
1262 | while (directive_state_stack) | |
1263 | { | |
1264 | directiveE directive; | |
1265 | bfd_boolean negated; | |
1266 | const char *file; | |
1267 | unsigned int line; | |
1268 | const void *datum; | |
1269 | ||
1270 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1271 | as_warn_where ((char *) file, line, | |
1272 | _(".begin directive with no matching .end directive")); | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | ||
1277 | static bfd_boolean | |
7fa3d080 | 1278 | inside_directive (directiveE dir) |
e0001a05 NC |
1279 | { |
1280 | state_stackS *top = directive_state_stack; | |
1281 | ||
1282 | while (top && top->directive != dir) | |
1283 | top = top->prev; | |
1284 | ||
1285 | return (top != NULL); | |
1286 | } | |
1287 | ||
1288 | ||
1289 | static void | |
7fa3d080 | 1290 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1291 | { |
1292 | int len; | |
1293 | unsigned i; | |
b9bb4a93 | 1294 | const char *directive_string; |
e0001a05 NC |
1295 | |
1296 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1297 | *negated = FALSE; | |
1298 | else | |
1299 | { | |
1300 | *negated = TRUE; | |
1301 | input_line_pointer += 3; | |
1302 | } | |
1303 | ||
1304 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1305 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1306 | ||
1307 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1308 | equivalent to .begin [no-]transform. We should remove it when | |
1309 | we stop accepting those options. */ | |
c138bc38 | 1310 | |
43cd72b9 BW |
1311 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1312 | { | |
1313 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1314 | directive_string = "transform"; | |
1315 | } | |
1316 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1317 | { | |
1318 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1319 | directive_string = "transform"; | |
c138bc38 | 1320 | } |
43cd72b9 BW |
1321 | else |
1322 | directive_string = input_line_pointer; | |
e0001a05 NC |
1323 | |
1324 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1325 | { | |
43cd72b9 | 1326 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1327 | { |
1328 | input_line_pointer += len; | |
1329 | *directive = (directiveE) i; | |
1330 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1331 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1332 | directive_info[i].name); |
1333 | return; | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | as_bad (_("unknown directive")); | |
1338 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1339 | } | |
1340 | ||
1341 | ||
1342 | static void | |
7fa3d080 | 1343 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1344 | { |
1345 | directiveE directive; | |
1346 | bfd_boolean negated; | |
1347 | emit_state *state; | |
e0001a05 NC |
1348 | lit_state *ls; |
1349 | ||
1350 | get_directive (&directive, &negated); | |
1351 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1352 | { | |
1353 | discard_rest_of_line (); | |
1354 | return; | |
1355 | } | |
1356 | ||
43cd72b9 BW |
1357 | if (cur_vinsn.inside_bundle) |
1358 | as_bad (_("directives are not valid inside bundles")); | |
1359 | ||
e0001a05 NC |
1360 | switch (directive) |
1361 | { | |
1362 | case directive_literal: | |
82e7541d BW |
1363 | if (!inside_directive (directive_literal)) |
1364 | { | |
1365 | /* Previous labels go with whatever follows this directive, not with | |
1366 | the literal, so save them now. */ | |
1367 | saved_insn_labels = insn_labels; | |
1368 | insn_labels = NULL; | |
1369 | } | |
43cd72b9 | 1370 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
325801bd | 1371 | state = XNEW (emit_state); |
e0001a05 NC |
1372 | xtensa_switch_to_literal_fragment (state); |
1373 | directive_push (directive_literal, negated, state); | |
1374 | break; | |
1375 | ||
1376 | case directive_literal_prefix: | |
c138bc38 | 1377 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1378 | might produce a literal. */ |
1379 | md_flush_pending_output (); | |
e0001a05 NC |
1380 | /* Check to see if the current fragment is a literal |
1381 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1382 | if (generating_literals) |
e0001a05 NC |
1383 | { |
1384 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1385 | return; | |
1386 | } | |
1387 | ||
1388 | /* Allocate the literal state for this section and push | |
1389 | onto the directive stack. */ | |
325801bd | 1390 | ls = XNEW (lit_state); |
9c2799c2 | 1391 | gas_assert (ls); |
e0001a05 NC |
1392 | |
1393 | *ls = default_lit_sections; | |
e0001a05 NC |
1394 | directive_push (directive_literal_prefix, negated, ls); |
1395 | ||
e0001a05 | 1396 | /* Process the new prefix. */ |
74869ac7 | 1397 | xtensa_literal_prefix (); |
e0001a05 NC |
1398 | break; |
1399 | ||
1400 | case directive_freeregs: | |
1401 | /* This information is currently unused, but we'll accept the statement | |
1402 | and just discard the rest of the line. This won't check the syntax, | |
1403 | but it will accept every correct freeregs directive. */ | |
1404 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1405 | directive_push (directive_freeregs, negated, 0); | |
1406 | break; | |
1407 | ||
43cd72b9 BW |
1408 | case directive_schedule: |
1409 | md_flush_pending_output (); | |
1410 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1411 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1412 | directive_push (directive_schedule, negated, 0); | |
1413 | xtensa_set_frag_assembly_state (frag_now); | |
1414 | break; | |
1415 | ||
e0001a05 | 1416 | case directive_density: |
43cd72b9 BW |
1417 | as_warn (_(".begin [no-]density is ignored")); |
1418 | break; | |
1419 | ||
1420 | case directive_absolute_literals: | |
1421 | md_flush_pending_output (); | |
1422 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1423 | { |
43cd72b9 | 1424 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1425 | break; |
1426 | } | |
43cd72b9 BW |
1427 | xtensa_set_frag_assembly_state (frag_now); |
1428 | directive_push (directive, negated, 0); | |
1429 | break; | |
e0001a05 NC |
1430 | |
1431 | default: | |
43cd72b9 BW |
1432 | md_flush_pending_output (); |
1433 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1434 | directive_push (directive, negated, 0); |
1435 | break; | |
1436 | } | |
1437 | ||
1438 | demand_empty_rest_of_line (); | |
1439 | } | |
1440 | ||
1441 | ||
1442 | static void | |
7fa3d080 | 1443 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1444 | { |
1445 | directiveE begin_directive, end_directive; | |
1446 | bfd_boolean begin_negated, end_negated; | |
1447 | const char *file; | |
1448 | unsigned int line; | |
1449 | emit_state *state; | |
43cd72b9 | 1450 | emit_state **state_ptr; |
e0001a05 NC |
1451 | lit_state *s; |
1452 | ||
43cd72b9 BW |
1453 | if (cur_vinsn.inside_bundle) |
1454 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1455 | |
e0001a05 | 1456 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1457 | |
1458 | md_flush_pending_output (); | |
1459 | ||
87975d2a | 1460 | switch ((int) end_directive) |
e0001a05 | 1461 | { |
87975d2a | 1462 | case XTENSA_UNDEFINED: |
e0001a05 NC |
1463 | discard_rest_of_line (); |
1464 | return; | |
e0001a05 | 1465 | |
87975d2a | 1466 | case (int) directive_density: |
43cd72b9 | 1467 | as_warn (_(".end [no-]density is ignored")); |
e0001a05 | 1468 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1469 | break; |
1470 | ||
87975d2a | 1471 | case (int) directive_absolute_literals: |
43cd72b9 BW |
1472 | if (!absolute_literals_supported && !end_negated) |
1473 | { | |
1474 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1475 | demand_empty_rest_of_line (); | |
1476 | return; | |
1477 | } | |
1478 | break; | |
1479 | ||
1480 | default: | |
1481 | break; | |
e0001a05 NC |
1482 | } |
1483 | ||
43cd72b9 | 1484 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1485 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1486 | (const void **) state_ptr); |
e0001a05 NC |
1487 | |
1488 | if (begin_directive != directive_none) | |
1489 | { | |
1490 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1491 | { | |
1492 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1493 | begin_negated ? "no-" : "", | |
1494 | directive_info[begin_directive].name, file, line); | |
1495 | } | |
1496 | else | |
1497 | { | |
1498 | switch (end_directive) | |
1499 | { | |
1500 | case directive_literal: | |
1501 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1502 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1503 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1504 | free (state); |
82e7541d BW |
1505 | if (!inside_directive (directive_literal)) |
1506 | { | |
1507 | /* Restore the list of current labels. */ | |
1508 | xtensa_clear_insn_labels (); | |
1509 | insn_labels = saved_insn_labels; | |
1510 | } | |
e0001a05 NC |
1511 | break; |
1512 | ||
e0001a05 NC |
1513 | case directive_literal_prefix: |
1514 | /* Restore the default collection sections from saved state. */ | |
1515 | s = (lit_state *) state; | |
9c2799c2 | 1516 | gas_assert (s); |
e8247da7 | 1517 | default_lit_sections = *s; |
e0001a05 | 1518 | |
74869ac7 BW |
1519 | /* Free the state storage. */ |
1520 | free (s->lit_prefix); | |
e0001a05 NC |
1521 | free (s); |
1522 | break; | |
1523 | ||
43cd72b9 BW |
1524 | case directive_schedule: |
1525 | case directive_freeregs: | |
1526 | break; | |
1527 | ||
e0001a05 | 1528 | default: |
43cd72b9 | 1529 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1530 | break; |
1531 | } | |
1532 | } | |
1533 | } | |
1534 | ||
1535 | demand_empty_rest_of_line (); | |
1536 | } | |
1537 | ||
1538 | ||
1539 | /* Place an aligned literal fragment at the current location. */ | |
1540 | ||
1541 | static void | |
7fa3d080 | 1542 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1543 | { |
43cd72b9 BW |
1544 | md_flush_pending_output (); |
1545 | ||
e0001a05 NC |
1546 | if (inside_directive (directive_literal)) |
1547 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1548 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1549 | |
1550 | demand_empty_rest_of_line (); | |
82e7541d | 1551 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1552 | } |
1553 | ||
1554 | ||
43cd72b9 | 1555 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1556 | |
1557 | static void | |
7fa3d080 | 1558 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1559 | { |
1560 | emit_state state; | |
1745fcba | 1561 | char *p, *base_name; |
e0001a05 | 1562 | char c; |
e0001a05 | 1563 | |
82e7541d BW |
1564 | if (inside_directive (directive_literal)) |
1565 | { | |
1566 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1567 | ignore_rest_of_line (); | |
1568 | return; | |
1569 | } | |
1570 | ||
43cd72b9 BW |
1571 | md_flush_pending_output (); |
1572 | ||
82e7541d BW |
1573 | /* Previous labels go with whatever follows this directive, not with |
1574 | the literal, so save them now. */ | |
1575 | saved_insn_labels = insn_labels; | |
1576 | insn_labels = NULL; | |
1577 | ||
e0001a05 NC |
1578 | base_name = input_line_pointer; |
1579 | ||
1580 | xtensa_switch_to_literal_fragment (&state); | |
1581 | ||
43cd72b9 BW |
1582 | /* All literals are aligned to four-byte boundaries. */ |
1583 | frag_align (2, 0, 0); | |
1584 | record_alignment (now_seg, 2); | |
e0001a05 | 1585 | |
d02603dc | 1586 | c = get_symbol_name (&base_name); |
e0001a05 NC |
1587 | /* Just after name is now '\0'. */ |
1588 | p = input_line_pointer; | |
1589 | *p = c; | |
d02603dc | 1590 | SKIP_WHITESPACE_AFTER_NAME (); |
e0001a05 NC |
1591 | |
1592 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1593 | { | |
1594 | as_bad (_("expected comma or colon after symbol name; " | |
1595 | "rest of line ignored")); | |
1596 | ignore_rest_of_line (); | |
1597 | xtensa_restore_emit_state (&state); | |
1598 | return; | |
1599 | } | |
e0001a05 | 1600 | |
d02603dc | 1601 | *p = 0; |
e0001a05 | 1602 | colon (base_name); |
e0001a05 | 1603 | *p = c; |
d02603dc | 1604 | |
43cd72b9 | 1605 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1606 | |
43cd72b9 | 1607 | xtensa_elf_cons (4); |
e0001a05 NC |
1608 | |
1609 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1610 | |
1611 | /* Restore the list of current labels. */ | |
1612 | xtensa_clear_insn_labels (); | |
1613 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1614 | } |
1615 | ||
1616 | ||
1617 | static void | |
74869ac7 | 1618 | xtensa_literal_prefix (void) |
e0001a05 | 1619 | { |
74869ac7 BW |
1620 | char *name; |
1621 | int len; | |
1622 | ||
1623 | /* Parse the new prefix from the input_line_pointer. */ | |
1624 | SKIP_WHITESPACE (); | |
1625 | len = strspn (input_line_pointer, | |
1626 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1627 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1628 | |
1629 | /* Get a null-terminated copy of the name. */ | |
29a2809e | 1630 | name = xmemdup0 (input_line_pointer, len); |
e0001a05 | 1631 | |
74869ac7 BW |
1632 | /* Skip the name in the input line. */ |
1633 | input_line_pointer += len; | |
43cd72b9 | 1634 | |
74869ac7 | 1635 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1636 | |
74869ac7 | 1637 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1638 | default_lit_sections.lit_seg = NULL; |
1639 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1640 | } |
1641 | ||
1642 | ||
1643 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1644 | ||
1645 | static void | |
7fa3d080 | 1646 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1647 | { |
1648 | float fall_through_f, target_f; | |
43cd72b9 BW |
1649 | |
1650 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1651 | if (fall_through_f < 0) | |
1652 | { | |
1653 | as_bad (_("fall through frequency must be greater than 0")); | |
1654 | ignore_rest_of_line (); | |
1655 | return; | |
1656 | } | |
1657 | ||
1658 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1659 | if (target_f < 0) | |
1660 | { | |
1661 | as_bad (_("branch target frequency must be greater than 0")); | |
1662 | ignore_rest_of_line (); | |
1663 | return; | |
1664 | } | |
1665 | ||
b08b5071 | 1666 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1667 | |
1668 | demand_empty_rest_of_line (); | |
1669 | } | |
1670 | ||
1671 | ||
1672 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1673 | Clobbers input_line_pointer, checks end-of-line. */ | |
1674 | ||
1675 | static void | |
7fa3d080 | 1676 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1677 | { |
1678 | expressionS exp; | |
1679 | bfd_reloc_code_real_type reloc; | |
1680 | ||
1681 | md_flush_pending_output (); | |
1682 | ||
1683 | if (cur_vinsn.inside_bundle) | |
1684 | as_bad (_("directives are not valid inside bundles")); | |
1685 | ||
1686 | if (is_it_end_of_statement ()) | |
1687 | { | |
1688 | demand_empty_rest_of_line (); | |
1689 | return; | |
1690 | } | |
1691 | ||
1692 | do | |
1693 | { | |
1694 | expression (&exp); | |
1695 | if (exp.X_op == O_symbol | |
1696 | && *input_line_pointer == '@' | |
1697 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1698 | != BFD_RELOC_NONE)) | |
1699 | { | |
1700 | reloc_howto_type *reloc_howto = | |
1701 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1702 | ||
1703 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1704 | as_bad (_("unsupported relocation")); | |
1705 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1706 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1707 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1708 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1709 | as_bad (_("opcode-specific %s relocation used outside " | |
1710 | "an instruction"), reloc_howto->name); | |
1711 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
992a06ee AM |
1712 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
1713 | "%s relocations do not fit in %d bytes", | |
1714 | nbytes), | |
43cd72b9 | 1715 | reloc_howto->name, nbytes); |
28dbbc02 BW |
1716 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1717 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1718 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1719 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1720 | else |
1721 | { | |
1722 | char *p = frag_more ((int) nbytes); | |
1723 | xtensa_set_frag_assembly_state (frag_now); | |
1724 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1725 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1726 | } |
1727 | } | |
1728 | else | |
1f7efbae BW |
1729 | { |
1730 | xtensa_set_frag_assembly_state (frag_now); | |
1731 | emit_expr (&exp, (unsigned int) nbytes); | |
1732 | } | |
43cd72b9 BW |
1733 | } |
1734 | while (*input_line_pointer++ == ','); | |
1735 | ||
1736 | input_line_pointer--; /* Put terminator back into stream. */ | |
1737 | demand_empty_rest_of_line (); | |
1738 | } | |
1739 | ||
fb227da0 BW |
1740 | static bfd_boolean is_leb128_expr; |
1741 | ||
1742 | static void | |
1743 | xtensa_leb128 (int sign) | |
1744 | { | |
1745 | is_leb128_expr = TRUE; | |
1746 | s_leb128 (sign); | |
1747 | is_leb128_expr = FALSE; | |
1748 | } | |
1749 | ||
7fa3d080 BW |
1750 | \f |
1751 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1752 | |
1753 | /* Parse @plt, etc. and return the desired relocation. */ | |
1754 | static bfd_reloc_code_real_type | |
7fa3d080 | 1755 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1756 | { |
43cd72b9 BW |
1757 | char ident[20]; |
1758 | char *str = *str_p; | |
1759 | char *str2; | |
1760 | int ch; | |
1761 | int len; | |
e066bf5f | 1762 | unsigned int i; |
43cd72b9 BW |
1763 | |
1764 | if (*str++ != '@') | |
1765 | return BFD_RELOC_NONE; | |
1766 | ||
1767 | for (ch = *str, str2 = ident; | |
1768 | (str2 < ident + sizeof (ident) - 1 | |
1769 | && (ISALNUM (ch) || ch == '@')); | |
1770 | ch = *++str) | |
1771 | { | |
1772 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1773 | } | |
1774 | ||
1775 | *str2 = '\0'; | |
1776 | len = str2 - ident; | |
1777 | ||
1778 | ch = ident[0]; | |
e066bf5f TS |
1779 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
1780 | if (ch == suffix_relocs[i].suffix[0] | |
1781 | && len == suffix_relocs[i].length | |
1782 | && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0) | |
43cd72b9 BW |
1783 | { |
1784 | /* Now check for "identifier@suffix+constant". */ | |
1785 | if (*str == '-' || *str == '+') | |
1786 | { | |
1787 | char *orig_line = input_line_pointer; | |
1788 | expressionS new_exp; | |
1789 | ||
1790 | input_line_pointer = str; | |
1791 | expression (&new_exp); | |
1792 | if (new_exp.X_op == O_constant) | |
1793 | { | |
1794 | exp_p->X_add_number += new_exp.X_add_number; | |
1795 | str = input_line_pointer; | |
1796 | } | |
1797 | ||
1798 | if (&input_line_pointer != str_p) | |
1799 | input_line_pointer = orig_line; | |
1800 | } | |
1801 | ||
1802 | *str_p = str; | |
e066bf5f | 1803 | return suffix_relocs[i].reloc; |
43cd72b9 BW |
1804 | } |
1805 | ||
1806 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1807 | } |
1808 | ||
e0001a05 | 1809 | |
bbdd25a8 | 1810 | /* Find the matching operator type. */ |
cc34adb2 | 1811 | static operatorT |
bbdd25a8 BW |
1812 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) |
1813 | { | |
cc34adb2 | 1814 | operatorT operator = O_illegal; |
e066bf5f | 1815 | unsigned int i; |
3739860c | 1816 | |
e066bf5f | 1817 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1818 | { |
e066bf5f | 1819 | if (suffix_relocs[i].reloc == reloc) |
bbdd25a8 | 1820 | { |
e066bf5f | 1821 | operator = suffix_relocs[i].operator; |
bbdd25a8 BW |
1822 | break; |
1823 | } | |
1824 | } | |
cc34adb2 | 1825 | gas_assert (operator != O_illegal); |
bbdd25a8 BW |
1826 | return operator; |
1827 | } | |
1828 | ||
1829 | ||
1830 | /* Find the matching reloc type. */ | |
1831 | static bfd_reloc_code_real_type | |
28dbbc02 | 1832 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 | 1833 | { |
e066bf5f | 1834 | unsigned int i; |
bbdd25a8 BW |
1835 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; |
1836 | ||
e066bf5f | 1837 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1838 | { |
e066bf5f | 1839 | if (suffix_relocs[i].operator == operator) |
bbdd25a8 | 1840 | { |
e066bf5f | 1841 | reloc = suffix_relocs[i].reloc; |
bbdd25a8 BW |
1842 | break; |
1843 | } | |
1844 | } | |
1845 | ||
28dbbc02 BW |
1846 | if (is_literal) |
1847 | { | |
1848 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1849 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1850 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1851 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1852 | } | |
1853 | ||
bbdd25a8 BW |
1854 | if (reloc == BFD_RELOC_UNUSED) |
1855 | return BFD_RELOC_32; | |
1856 | ||
1857 | return reloc; | |
1858 | } | |
1859 | ||
1860 | ||
e0001a05 | 1861 | static const char * |
7fa3d080 | 1862 | expression_end (const char *name) |
e0001a05 NC |
1863 | { |
1864 | while (1) | |
1865 | { | |
1866 | switch (*name) | |
1867 | { | |
43cd72b9 | 1868 | case '}': |
e0001a05 NC |
1869 | case ';': |
1870 | case '\0': | |
1871 | case ',': | |
43cd72b9 | 1872 | case ':': |
e0001a05 NC |
1873 | return name; |
1874 | case ' ': | |
1875 | case '\t': | |
1876 | ++name; | |
1877 | continue; | |
1878 | default: | |
1879 | return 0; | |
1880 | } | |
1881 | } | |
1882 | } | |
1883 | ||
1884 | ||
1885 | #define ERROR_REG_NUM ((unsigned) -1) | |
1886 | ||
1887 | static unsigned | |
7fa3d080 | 1888 | tc_get_register (const char *prefix) |
e0001a05 NC |
1889 | { |
1890 | unsigned reg; | |
1891 | const char *next_expr; | |
1892 | const char *old_line_pointer; | |
1893 | ||
1894 | SKIP_WHITESPACE (); | |
1895 | old_line_pointer = input_line_pointer; | |
1896 | ||
1897 | if (*input_line_pointer == '$') | |
1898 | ++input_line_pointer; | |
1899 | ||
1900 | /* Accept "sp" as a synonym for "a1". */ | |
1901 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1902 | && expression_end (input_line_pointer + 2)) | |
1903 | { | |
1904 | input_line_pointer += 2; | |
1905 | return 1; /* AR[1] */ | |
1906 | } | |
1907 | ||
1908 | while (*input_line_pointer++ == *prefix++) | |
1909 | ; | |
1910 | --input_line_pointer; | |
1911 | --prefix; | |
1912 | ||
1913 | if (*prefix) | |
1914 | { | |
1915 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1916 | return ERROR_REG_NUM; | |
1917 | } | |
1918 | ||
1919 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1920 | { | |
1921 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1922 | return ERROR_REG_NUM; | |
1923 | } | |
1924 | ||
1925 | reg = 0; | |
1926 | ||
1927 | while (ISDIGIT ((int) *input_line_pointer)) | |
1928 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1929 | ||
1930 | if (!(next_expr = expression_end (input_line_pointer))) | |
1931 | { | |
1932 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1933 | return ERROR_REG_NUM; | |
1934 | } | |
1935 | ||
1936 | input_line_pointer = (char *) next_expr; | |
1937 | ||
1938 | return reg; | |
1939 | } | |
1940 | ||
1941 | ||
e0001a05 | 1942 | static void |
7fa3d080 | 1943 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1944 | { |
43cd72b9 | 1945 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1946 | |
43cd72b9 BW |
1947 | /* Check if this is an immediate operand. */ |
1948 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1949 | { |
43cd72b9 | 1950 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1951 | segT t = expression (tok); |
91d6fa6a | 1952 | |
43cd72b9 BW |
1953 | if (t == absolute_section |
1954 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1955 | { |
9c2799c2 | 1956 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1957 | tok->X_op = O_symbol; |
1958 | tok->X_add_symbol = &abs_symbol; | |
1959 | } | |
43cd72b9 BW |
1960 | |
1961 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1962 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1963 | != BFD_RELOC_NONE)) | |
e0001a05 | 1964 | { |
1bbb5f21 | 1965 | switch (reloc) |
43cd72b9 | 1966 | { |
1bbb5f21 BW |
1967 | case BFD_RELOC_LO16: |
1968 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1969 | { |
43cd72b9 | 1970 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1971 | return; |
1bbb5f21 BW |
1972 | } |
1973 | break; | |
1974 | case BFD_RELOC_HI16: | |
1975 | if (tok->X_op == O_constant) | |
1976 | { | |
43cd72b9 | 1977 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1978 | return; |
bbdd25a8 | 1979 | } |
1bbb5f21 BW |
1980 | break; |
1981 | case BFD_RELOC_UNUSED: | |
1982 | as_bad (_("unsupported relocation")); | |
1983 | return; | |
1984 | case BFD_RELOC_32_PCREL: | |
1985 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1986 | return; | |
1987 | default: | |
1988 | break; | |
43cd72b9 | 1989 | } |
bbdd25a8 | 1990 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1991 | } |
e0001a05 NC |
1992 | } |
1993 | else | |
1994 | { | |
43cd72b9 BW |
1995 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1996 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1997 | |
1998 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1999 | { | |
2000 | uint32 buf = reg; | |
43cd72b9 | 2001 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
2002 | as_bad (_("register number out of range")); |
2003 | } | |
2004 | ||
2005 | tok->X_op = O_register; | |
2006 | tok->X_add_symbol = 0; | |
2007 | tok->X_add_number = reg; | |
2008 | } | |
2009 | } | |
2010 | ||
2011 | ||
2012 | /* Split up the arguments for an opcode or pseudo-op. */ | |
2013 | ||
2014 | static int | |
7fa3d080 | 2015 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
2016 | { |
2017 | char *old_input_line_pointer; | |
2018 | bfd_boolean saw_comma = FALSE; | |
2019 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 2020 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
2021 | int num_args = 0; |
2022 | char *arg_end, *arg; | |
2023 | int arg_len; | |
43cd72b9 BW |
2024 | |
2025 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
2026 | old_input_line_pointer = input_line_pointer; |
2027 | input_line_pointer = str; | |
2028 | ||
2029 | while (*input_line_pointer) | |
2030 | { | |
2031 | SKIP_WHITESPACE (); | |
2032 | switch (*input_line_pointer) | |
2033 | { | |
2034 | case '\0': | |
43cd72b9 | 2035 | case '}': |
e0001a05 NC |
2036 | goto fini; |
2037 | ||
43cd72b9 BW |
2038 | case ':': |
2039 | input_line_pointer++; | |
2040 | if (saw_comma || saw_colon || !saw_arg) | |
2041 | goto err; | |
2042 | saw_colon = TRUE; | |
2043 | break; | |
2044 | ||
e0001a05 NC |
2045 | case ',': |
2046 | input_line_pointer++; | |
43cd72b9 | 2047 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
2048 | goto err; |
2049 | saw_comma = TRUE; | |
2050 | break; | |
2051 | ||
2052 | default: | |
43cd72b9 | 2053 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
2054 | goto err; |
2055 | ||
2056 | arg_end = input_line_pointer + 1; | |
2057 | while (!expression_end (arg_end)) | |
2058 | arg_end += 1; | |
43cd72b9 | 2059 | |
e0001a05 | 2060 | arg_len = arg_end - input_line_pointer; |
325801bd | 2061 | arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
2062 | args[num_args] = arg; |
2063 | ||
43cd72b9 BW |
2064 | if (saw_colon) |
2065 | *arg++ = ':'; | |
e0001a05 NC |
2066 | strncpy (arg, input_line_pointer, arg_len); |
2067 | arg[arg_len] = '\0'; | |
43cd72b9 | 2068 | |
e0001a05 NC |
2069 | input_line_pointer = arg_end; |
2070 | num_args += 1; | |
c138bc38 | 2071 | saw_comma = FALSE; |
43cd72b9 | 2072 | saw_colon = FALSE; |
c138bc38 | 2073 | saw_arg = TRUE; |
e0001a05 NC |
2074 | break; |
2075 | } | |
2076 | } | |
2077 | ||
dc1e8a47 | 2078 | fini: |
43cd72b9 | 2079 | if (saw_comma || saw_colon) |
e0001a05 NC |
2080 | goto err; |
2081 | input_line_pointer = old_input_line_pointer; | |
2082 | return num_args; | |
2083 | ||
dc1e8a47 | 2084 | err: |
43cd72b9 BW |
2085 | if (saw_comma) |
2086 | as_bad (_("extra comma")); | |
2087 | else if (saw_colon) | |
2088 | as_bad (_("extra colon")); | |
2089 | else if (!saw_arg) | |
c138bc38 | 2090 | as_bad (_("missing argument")); |
43cd72b9 BW |
2091 | else |
2092 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
2093 | input_line_pointer = old_input_line_pointer; |
2094 | return -1; | |
2095 | } | |
2096 | ||
2097 | ||
43cd72b9 | 2098 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
2099 | |
2100 | static bfd_boolean | |
7fa3d080 | 2101 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 2102 | { |
43cd72b9 | 2103 | expressionS *tok, *last_tok; |
e0001a05 NC |
2104 | xtensa_opcode opcode = insn->opcode; |
2105 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
2106 | xtensa_isa isa = xtensa_default_isa; |
2107 | int n, num_regs = 0; | |
e0001a05 | 2108 | int opcode_operand_count; |
43cd72b9 BW |
2109 | int opnd_cnt, last_opnd_cnt; |
2110 | unsigned int next_reg = 0; | |
e0001a05 NC |
2111 | char *old_input_line_pointer; |
2112 | ||
2113 | if (insn->insn_type == ITYPE_LITERAL) | |
2114 | opcode_operand_count = 1; | |
2115 | else | |
43cd72b9 | 2116 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 2117 | |
43cd72b9 | 2118 | tok = insn->tok; |
e0001a05 NC |
2119 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
2120 | ||
2121 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
2122 | old_input_line_pointer = input_line_pointer; |
2123 | ||
2124 | last_tok = 0; | |
2125 | last_opnd_cnt = -1; | |
2126 | opnd_cnt = 0; | |
2127 | ||
2128 | /* Skip invisible operands. */ | |
2129 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2130 | { | |
2131 | opnd_cnt += 1; | |
2132 | tok++; | |
2133 | } | |
e0001a05 NC |
2134 | |
2135 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2136 | { |
e0001a05 | 2137 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2138 | if (*input_line_pointer == ':') |
2139 | { | |
2140 | xtensa_regfile opnd_rf; | |
2141 | input_line_pointer++; | |
2142 | if (num_regs == 0) | |
2143 | goto err; | |
9c2799c2 | 2144 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2145 | num_regs--; |
2146 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2147 | if (next_reg | |
2148 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2149 | as_warn (_("incorrect register number, ignoring")); | |
2150 | next_reg++; | |
2151 | } | |
2152 | else | |
2153 | { | |
2154 | if (opnd_cnt >= opcode_operand_count) | |
2155 | { | |
2156 | as_warn (_("too many arguments")); | |
2157 | goto err; | |
2158 | } | |
9c2799c2 | 2159 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2160 | |
2161 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2162 | next_reg = tok->X_add_number + 1; | |
2163 | ||
2164 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2165 | goto err; | |
2166 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2167 | { | |
2168 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2169 | /* minus 1 because we are seeing one right now */ | |
2170 | } | |
2171 | else | |
2172 | num_regs = 0; | |
e0001a05 | 2173 | |
43cd72b9 BW |
2174 | last_tok = tok; |
2175 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2176 | demand_empty_rest_of_line (); |
e0001a05 | 2177 | |
43cd72b9 BW |
2178 | do |
2179 | { | |
2180 | opnd_cnt += 1; | |
2181 | tok++; | |
2182 | } | |
2183 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2184 | } | |
2185 | } | |
e0001a05 | 2186 | |
43cd72b9 BW |
2187 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2188 | goto err; | |
e0001a05 NC |
2189 | |
2190 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2191 | had_error = FALSE; |
e0001a05 NC |
2192 | |
2193 | err: | |
43cd72b9 | 2194 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2195 | return had_error; |
2196 | } | |
2197 | ||
2198 | ||
43cd72b9 | 2199 | static int |
7fa3d080 | 2200 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2201 | { |
2202 | xtensa_isa isa = xtensa_default_isa; | |
2203 | static xtensa_insnbuf slotbuf = NULL; | |
2204 | xtensa_format fmt; | |
2205 | xtensa_opcode opc = insn->opcode; | |
2206 | int slot, opnd, fmt_found; | |
2207 | unsigned val; | |
2208 | ||
2209 | if (!slotbuf) | |
2210 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2211 | ||
2212 | /* Find format/slot where this can be encoded. */ | |
2213 | fmt_found = 0; | |
2214 | slot = 0; | |
2215 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2216 | { | |
2217 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2218 | { | |
2219 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2220 | { | |
2221 | fmt_found = 1; | |
2222 | break; | |
2223 | } | |
2224 | } | |
2225 | if (fmt_found) break; | |
2226 | } | |
2227 | ||
2228 | if (!fmt_found) | |
2229 | { | |
2230 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2231 | return -1; | |
2232 | } | |
2233 | ||
2234 | /* First encode all the visible operands | |
2235 | (to deal with shared field operands). */ | |
2236 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2237 | { | |
2238 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2239 | && (insn->tok[opnd].X_op == O_register | |
2240 | || insn->tok[opnd].X_op == O_constant)) | |
2241 | { | |
2242 | val = insn->tok[opnd].X_add_number; | |
2243 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2244 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | /* Then pull out the values for the invisible ones. */ | |
2249 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2250 | { | |
2251 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2252 | { | |
2253 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2254 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2255 | insn->tok[opnd].X_add_number = val; | |
2256 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2257 | insn->tok[opnd].X_op = O_register; | |
2258 | else | |
2259 | insn->tok[opnd].X_op = O_constant; | |
2260 | } | |
2261 | } | |
2262 | ||
2263 | return 0; | |
2264 | } | |
2265 | ||
2266 | ||
e0001a05 | 2267 | static void |
7fa3d080 | 2268 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2269 | { |
2270 | char *cnt_arg, *new_arg; | |
2271 | cnt_arg = *cnt_argp; | |
2272 | ||
2273 | /* replace the argument with "31-(argument)" */ | |
78fb7e37 | 2274 | new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); |
e0001a05 NC |
2275 | |
2276 | free (cnt_arg); | |
2277 | *cnt_argp = new_arg; | |
2278 | } | |
2279 | ||
2280 | ||
2281 | /* If "arg" is a constant expression, return non-zero with the value | |
2282 | in *valp. */ | |
2283 | ||
2284 | static int | |
7fa3d080 | 2285 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2286 | { |
2287 | expressionS exp; | |
2288 | char *save_ptr = input_line_pointer; | |
2289 | ||
2290 | input_line_pointer = arg; | |
2291 | expression (&exp); | |
2292 | input_line_pointer = save_ptr; | |
2293 | ||
2294 | if (exp.X_op == O_constant) | |
2295 | { | |
2296 | *valp = exp.X_add_number; | |
2297 | return 1; | |
2298 | } | |
2299 | ||
2300 | return 0; | |
2301 | } | |
2302 | ||
2303 | ||
2304 | static void | |
b9bb4a93 | 2305 | xg_replace_opname (char **popname, const char *newop) |
e0001a05 NC |
2306 | { |
2307 | free (*popname); | |
4ec9d7d5 | 2308 | *popname = xstrdup (newop); |
e0001a05 NC |
2309 | } |
2310 | ||
2311 | ||
2312 | static int | |
7fa3d080 BW |
2313 | xg_check_num_args (int *pnum_args, |
2314 | int expected_num, | |
2315 | char *opname, | |
2316 | char **arg_strings) | |
e0001a05 NC |
2317 | { |
2318 | int num_args = *pnum_args; | |
2319 | ||
43cd72b9 | 2320 | if (num_args < expected_num) |
e0001a05 NC |
2321 | { |
2322 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2323 | num_args, opname, expected_num); | |
2324 | return -1; | |
2325 | } | |
2326 | ||
2327 | if (num_args > expected_num) | |
2328 | { | |
2329 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2330 | num_args, opname, expected_num); | |
2331 | while (num_args-- > expected_num) | |
2332 | { | |
2333 | free (arg_strings[num_args]); | |
2334 | arg_strings[num_args] = 0; | |
2335 | } | |
2336 | *pnum_args = expected_num; | |
2337 | return -1; | |
2338 | } | |
2339 | ||
2340 | return 0; | |
2341 | } | |
2342 | ||
2343 | ||
43cd72b9 BW |
2344 | /* If the register is not specified as part of the opcode, |
2345 | then get it from the operand and move it to the opcode. */ | |
2346 | ||
e0001a05 | 2347 | static int |
7fa3d080 | 2348 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2349 | { |
43cd72b9 BW |
2350 | xtensa_isa isa = xtensa_default_isa; |
2351 | xtensa_sysreg sr; | |
e0001a05 | 2352 | char *opname, *new_opname; |
43cd72b9 BW |
2353 | const char *sr_name; |
2354 | int is_user, is_write; | |
e0001a05 NC |
2355 | |
2356 | opname = *popname; | |
2357 | if (*opname == '_') | |
80ca4e2c | 2358 | opname += 1; |
43cd72b9 BW |
2359 | is_user = (opname[1] == 'u'); |
2360 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2361 | |
43cd72b9 | 2362 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2363 | |
43cd72b9 BW |
2364 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2365 | return -1; | |
e0001a05 | 2366 | |
43cd72b9 BW |
2367 | /* Check if the argument is a symbolic register name. */ |
2368 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2369 | /* Handle WSR to "INTSET" as a special case. */ | |
2370 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2371 | && !strcasecmp (arg_strings[1], "intset")) | |
2372 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2373 | if (sr == XTENSA_UNDEFINED | |
2374 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2375 | { | |
2376 | /* Maybe it's a register number.... */ | |
2377 | offsetT val; | |
e0001a05 NC |
2378 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2379 | { | |
43cd72b9 BW |
2380 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2381 | arg_strings[1], opname); | |
e0001a05 NC |
2382 | return -1; |
2383 | } | |
43cd72b9 BW |
2384 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2385 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2386 | { |
43cd72b9 | 2387 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2388 | (long) val, opname); |
e0001a05 NC |
2389 | return -1; |
2390 | } | |
43cd72b9 | 2391 | } |
e0001a05 | 2392 | |
43cd72b9 BW |
2393 | /* Remove the last argument, which is now part of the opcode. */ |
2394 | free (arg_strings[1]); | |
2395 | arg_strings[1] = 0; | |
2396 | *pnum_args = 1; | |
2397 | ||
2398 | /* Translate the opcode. */ | |
2399 | sr_name = xtensa_sysreg_name (isa, sr); | |
2400 | /* Another special case for "WSR.INTSET".... */ | |
2401 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2402 | sr_name = "intset"; | |
4ec9d7d5 | 2403 | new_opname = concat (*popname, ".", sr_name, (char *) NULL); |
43cd72b9 BW |
2404 | free (*popname); |
2405 | *popname = new_opname; | |
2406 | ||
2407 | return 0; | |
2408 | } | |
2409 | ||
2410 | ||
2411 | static int | |
7fa3d080 | 2412 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2413 | { |
2414 | xtensa_isa isa = xtensa_default_isa; | |
2415 | xtensa_sysreg sr; | |
2416 | char *opname, *new_opname; | |
2417 | const char *sr_name; | |
2418 | bfd_boolean has_underbar = FALSE; | |
2419 | ||
2420 | opname = *popname; | |
2421 | if (opname[0] == '_') | |
2422 | { | |
2423 | has_underbar = TRUE; | |
2424 | opname += 1; | |
2425 | } | |
2426 | ||
2427 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2428 | if (sr != XTENSA_UNDEFINED) | |
2429 | { | |
2430 | /* The new default name ("nnn") is different from the old default | |
2431 | name ("URnnn"). The old default is handled below, and we don't | |
2432 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2433 | default. */ | |
2434 | static char namebuf[10]; | |
2435 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2436 | if (strcmp (namebuf, opname + 1) == 0) | |
2437 | return 0; | |
2438 | } | |
2439 | else | |
2440 | { | |
2441 | offsetT val; | |
2442 | char *end; | |
2443 | ||
2444 | /* Only continue if the reg name is "URnnn". */ | |
2445 | if (opname[1] != 'u' || opname[2] != 'r') | |
2446 | return 0; | |
2447 | val = strtoul (opname + 3, &end, 10); | |
2448 | if (*end != '\0') | |
2449 | return 0; | |
2450 | ||
2451 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2452 | if (sr == XTENSA_UNDEFINED) | |
2453 | { | |
2454 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2455 | (long) val, opname); |
43cd72b9 BW |
2456 | return -1; |
2457 | } | |
2458 | } | |
2459 | ||
2460 | /* Translate the opcode. */ | |
2461 | sr_name = xtensa_sysreg_name (isa, sr); | |
add39d23 | 2462 | new_opname = XNEWVEC (char, strlen (sr_name) + 6); |
43cd72b9 BW |
2463 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), |
2464 | opname[0], sr_name); | |
2465 | free (*popname); | |
2466 | *popname = new_opname; | |
2467 | ||
2468 | return 0; | |
2469 | } | |
2470 | ||
2471 | ||
2472 | static int | |
b9bb4a93 TS |
2473 | xtensa_translate_zero_immed (const char *old_op, |
2474 | const char *new_op, | |
7fa3d080 BW |
2475 | char **popname, |
2476 | int *pnum_args, | |
2477 | char **arg_strings) | |
43cd72b9 BW |
2478 | { |
2479 | char *opname; | |
2480 | offsetT val; | |
2481 | ||
2482 | opname = *popname; | |
9c2799c2 | 2483 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2484 | |
2485 | if (strcmp (opname, old_op) != 0) | |
2486 | return 0; | |
e0001a05 | 2487 | |
43cd72b9 BW |
2488 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2489 | return -1; | |
2490 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2491 | { | |
2492 | xg_replace_opname (popname, new_op); | |
2493 | free (arg_strings[1]); | |
2494 | arg_strings[1] = arg_strings[2]; | |
2495 | arg_strings[2] = 0; | |
2496 | *pnum_args = 2; | |
e0001a05 NC |
2497 | } |
2498 | ||
2499 | return 0; | |
2500 | } | |
2501 | ||
2502 | ||
2503 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2504 | Returns non-zero if an error was found. */ | |
2505 | ||
2506 | static int | |
7fa3d080 | 2507 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2508 | { |
2509 | char *opname = *popname; | |
2510 | bfd_boolean has_underbar = FALSE; | |
2511 | ||
2512 | if (*opname == '_') | |
2513 | { | |
2514 | has_underbar = TRUE; | |
2515 | opname += 1; | |
2516 | } | |
2517 | ||
2518 | if (strcmp (opname, "mov") == 0) | |
2519 | { | |
43cd72b9 | 2520 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2521 | xg_replace_opname (popname, "mov.n"); |
2522 | else | |
2523 | { | |
2524 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2525 | return -1; | |
2526 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 | 2527 | arg_strings[2] = xstrdup (arg_strings[1]); |
e0001a05 NC |
2528 | *pnum_args = 3; |
2529 | } | |
2530 | return 0; | |
2531 | } | |
2532 | ||
935f1f4b MF |
2533 | /* Without an operand, this is given a default immediate operand of 0. */ |
2534 | if ((strcmp (opname, "simcall") == 0 && microarch_earliest >= 280000)) | |
2535 | { | |
2536 | if (*pnum_args == 0) | |
2537 | { | |
2538 | arg_strings[0] = (char *) xmalloc (2); | |
2539 | strcpy (arg_strings[0], "0"); | |
2540 | *pnum_args = 1; | |
2541 | } | |
2542 | return 0; | |
2543 | } | |
2544 | ||
e0001a05 NC |
2545 | if (strcmp (opname, "bbsi.l") == 0) |
2546 | { | |
2547 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2548 | return -1; | |
2549 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2550 | if (target_big_endian) | |
2551 | xg_reverse_shift_count (&arg_strings[1]); | |
2552 | return 0; | |
2553 | } | |
2554 | ||
2555 | if (strcmp (opname, "bbci.l") == 0) | |
2556 | { | |
2557 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2558 | return -1; | |
2559 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2560 | if (target_big_endian) | |
2561 | xg_reverse_shift_count (&arg_strings[1]); | |
2562 | return 0; | |
2563 | } | |
2564 | ||
eb6d9dce | 2565 | /* Don't do anything special with NOPs inside FLIX instructions. They |
3739860c | 2566 | are handled elsewhere. Real NOP instructions are always available |
eb6d9dce BW |
2567 | in configurations with FLIX, so this should never be an issue but |
2568 | check for it anyway. */ | |
2569 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2570 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2571 | { |
43cd72b9 | 2572 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2573 | xg_replace_opname (popname, "nop.n"); |
2574 | else | |
2575 | { | |
2576 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2577 | return -1; | |
2578 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 TS |
2579 | arg_strings[0] = xstrdup ("a1"); |
2580 | arg_strings[1] = xstrdup ("a1"); | |
2581 | arg_strings[2] = xstrdup ("a1"); | |
e0001a05 NC |
2582 | *pnum_args = 3; |
2583 | } | |
2584 | return 0; | |
2585 | } | |
2586 | ||
43cd72b9 BW |
2587 | /* Recognize [RW]UR and [RWX]SR. */ |
2588 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2589 | && (opname[1] == 'u' || opname[1] == 's')) | |
2590 | || (opname[0] == 'x' && opname[1] == 's')) | |
2591 | && opname[2] == 'r' | |
2592 | && opname[3] == '\0') | |
e0001a05 NC |
2593 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2594 | ||
43cd72b9 BW |
2595 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2596 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2597 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2598 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2599 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2600 | |
43cd72b9 BW |
2601 | /* Relax branches that don't allow comparisons against an immediate value |
2602 | of zero to the corresponding branches with implicit zero immediates. */ | |
2603 | if (!has_underbar && use_transform ()) | |
2604 | { | |
2605 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2606 | pnum_args, arg_strings)) | |
2607 | return -1; | |
e0001a05 | 2608 | |
43cd72b9 BW |
2609 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2610 | pnum_args, arg_strings)) | |
2611 | return -1; | |
e0001a05 | 2612 | |
43cd72b9 BW |
2613 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2614 | pnum_args, arg_strings)) | |
2615 | return -1; | |
e0001a05 | 2616 | |
43cd72b9 BW |
2617 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2618 | pnum_args, arg_strings)) | |
2619 | return -1; | |
2620 | } | |
e0001a05 | 2621 | |
43cd72b9 BW |
2622 | return 0; |
2623 | } | |
e0001a05 | 2624 | |
43cd72b9 BW |
2625 | \f |
2626 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2627 | |
43cd72b9 BW |
2628 | /* Currently the assembler only allows us to use a single target per |
2629 | fragment. Because of this, only one operand for a given | |
2630 | instruction may be symbolic. If there is a PC-relative operand, | |
2631 | the last one is chosen. Otherwise, the result is the number of the | |
2632 | last immediate operand, and if there are none of those, we fail and | |
2633 | return -1. */ | |
e0001a05 | 2634 | |
7fa3d080 BW |
2635 | static int |
2636 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2637 | { |
2638 | int last_immed = -1; | |
2639 | int noperands, opi; | |
e0001a05 | 2640 | |
43cd72b9 BW |
2641 | if (opcode == XTENSA_UNDEFINED) |
2642 | return -1; | |
e0001a05 | 2643 | |
43cd72b9 BW |
2644 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2645 | for (opi = noperands - 1; opi >= 0; opi--) | |
2646 | { | |
2647 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2648 | continue; | |
2649 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2650 | return opi; | |
2651 | if (last_immed == -1 | |
2652 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2653 | last_immed = opi; | |
e0001a05 | 2654 | } |
43cd72b9 | 2655 | return last_immed; |
e0001a05 NC |
2656 | } |
2657 | ||
e0001a05 | 2658 | |
43cd72b9 | 2659 | static xtensa_opcode |
7fa3d080 | 2660 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2661 | { |
43cd72b9 BW |
2662 | static xtensa_insnbuf insnbuf = NULL; |
2663 | static xtensa_insnbuf slotbuf = NULL; | |
2664 | xtensa_isa isa = xtensa_default_isa; | |
2665 | xtensa_format fmt; | |
2666 | ||
2667 | if (!insnbuf) | |
e0001a05 | 2668 | { |
43cd72b9 BW |
2669 | insnbuf = xtensa_insnbuf_alloc (isa); |
2670 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2671 | } |
e0001a05 | 2672 | |
d77b99c9 | 2673 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2674 | fmt = xtensa_format_decode (isa, insnbuf); |
2675 | if (fmt == XTENSA_UNDEFINED) | |
2676 | return XTENSA_UNDEFINED; | |
e0001a05 | 2677 | |
43cd72b9 BW |
2678 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2679 | return XTENSA_UNDEFINED; | |
e0001a05 | 2680 | |
43cd72b9 BW |
2681 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2682 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2683 | } |
2684 | ||
2685 | ||
43cd72b9 | 2686 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2687 | |
43cd72b9 | 2688 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2689 | |
7fa3d080 BW |
2690 | static void |
2691 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2692 | { |
2693 | int num_opcodes, num_operands; | |
2694 | xtensa_opcode opcode; | |
2695 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2696 | |
43cd72b9 BW |
2697 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2698 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2699 | { |
43cd72b9 BW |
2700 | int opn; |
2701 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2702 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2703 | for (opn = 0; opn < num_operands; opn++) | |
2704 | { | |
2705 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2706 | continue; | |
2707 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2708 | { | |
2709 | xtensa_regfile opnd_rf = | |
2710 | xtensa_operand_regfile (isa, opcode, opn); | |
2711 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2712 | } | |
2713 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2714 | fputs ("[lLr] ", stderr); | |
2715 | else | |
2716 | fputs ("i ", stderr); | |
2717 | } | |
2718 | fprintf (stderr, "\n"); | |
e0001a05 | 2719 | } |
e0001a05 NC |
2720 | } |
2721 | ||
2722 | ||
43cd72b9 | 2723 | static void |
7fa3d080 | 2724 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2725 | { |
e0001a05 | 2726 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2727 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2728 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2729 | int op; | |
e0001a05 | 2730 | |
43cd72b9 | 2731 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2732 | |
43cd72b9 BW |
2733 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2734 | { | |
2735 | xtensa_opcode opcode; | |
2736 | const char *opname; | |
2737 | int operands; | |
2738 | ||
2739 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2740 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2741 | opname = xtensa_opcode_name (isa, opcode); | |
2742 | ||
2743 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2744 | fprintf (stderr, " operands = "); | |
2745 | for (operands = 0; | |
2746 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2747 | operands++) | |
2748 | { | |
2749 | unsigned int val; | |
2750 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2751 | continue; | |
2752 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2753 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2754 | fprintf (stderr, "%d ", val); | |
2755 | } | |
2756 | fprintf (stderr, "\n"); | |
2757 | } | |
2758 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2759 | } |
2760 | ||
43cd72b9 BW |
2761 | #endif /* TENSILICA_DEBUG */ |
2762 | ||
e0001a05 NC |
2763 | |
2764 | static bfd_boolean | |
7fa3d080 | 2765 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2766 | { |
43cd72b9 BW |
2767 | xtensa_isa isa = xtensa_default_isa; |
2768 | int n, num_operands; | |
e0001a05 | 2769 | |
64b607e6 | 2770 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2771 | return FALSE; |
2772 | ||
43cd72b9 BW |
2773 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2774 | for (n = 0; n < num_operands; n++) | |
2775 | { | |
2776 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2777 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2778 | return TRUE; | |
2779 | } | |
2780 | return FALSE; | |
e0001a05 NC |
2781 | } |
2782 | ||
2783 | ||
43cd72b9 BW |
2784 | /* Convert from BFD relocation type code to slot and operand number. |
2785 | Returns non-zero on failure. */ | |
e0001a05 | 2786 | |
43cd72b9 | 2787 | static int |
7fa3d080 | 2788 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2789 | { |
43cd72b9 BW |
2790 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2791 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2792 | { |
43cd72b9 BW |
2793 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2794 | *is_alt = FALSE; | |
e0001a05 | 2795 | } |
43cd72b9 BW |
2796 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2797 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2798 | { |
43cd72b9 BW |
2799 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2800 | *is_alt = TRUE; | |
e0001a05 | 2801 | } |
43cd72b9 BW |
2802 | else |
2803 | return -1; | |
2804 | ||
2805 | return 0; | |
e0001a05 NC |
2806 | } |
2807 | ||
2808 | ||
43cd72b9 BW |
2809 | /* Convert from slot number to BFD relocation type code for the |
2810 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2811 | failure. */ | |
e0001a05 | 2812 | |
43cd72b9 | 2813 | static bfd_reloc_code_real_type |
7fa3d080 | 2814 | encode_reloc (int slot) |
e0001a05 | 2815 | { |
43cd72b9 BW |
2816 | if (slot < 0 || slot > 14) |
2817 | return BFD_RELOC_NONE; | |
2818 | ||
2819 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2820 | } |
2821 | ||
2822 | ||
43cd72b9 BW |
2823 | /* Convert from slot numbers to BFD relocation type code for the |
2824 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2825 | |
43cd72b9 | 2826 | static bfd_reloc_code_real_type |
7fa3d080 | 2827 | encode_alt_reloc (int slot) |
e0001a05 | 2828 | { |
43cd72b9 BW |
2829 | if (slot < 0 || slot > 14) |
2830 | return BFD_RELOC_NONE; | |
2831 | ||
2832 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2833 | } |
2834 | ||
2835 | ||
2836 | static void | |
7fa3d080 BW |
2837 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2838 | xtensa_format fmt, | |
2839 | int slot, | |
2840 | xtensa_opcode opcode, | |
2841 | int operand, | |
2842 | uint32 value, | |
2843 | const char *file, | |
2844 | unsigned int line) | |
e0001a05 | 2845 | { |
e0001a05 NC |
2846 | uint32 valbuf = value; |
2847 | ||
43cd72b9 | 2848 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2849 | { |
43cd72b9 BW |
2850 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2851 | == 1) | |
2852 | as_bad_where ((char *) file, line, | |
3739860c | 2853 | _("operand %d of '%s' has out of range value '%u'"), |
d7c531cd BW |
2854 | operand + 1, |
2855 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2856 | value); | |
43cd72b9 BW |
2857 | else |
2858 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2859 | _("operand %d of '%s' has invalid value '%u'"), |
2860 | operand + 1, | |
2861 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2862 | value); | |
43cd72b9 | 2863 | return; |
e0001a05 NC |
2864 | } |
2865 | ||
43cd72b9 BW |
2866 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2867 | slotbuf, valbuf); | |
e0001a05 NC |
2868 | } |
2869 | ||
2870 | ||
2871 | static uint32 | |
7fa3d080 BW |
2872 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2873 | xtensa_format fmt, | |
2874 | int slot, | |
2875 | xtensa_opcode opcode, | |
2876 | int opnum) | |
e0001a05 | 2877 | { |
43cd72b9 BW |
2878 | uint32 val = 0; |
2879 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2880 | fmt, slot, slotbuf, &val); | |
2881 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2882 | return val; | |
e0001a05 NC |
2883 | } |
2884 | ||
e0001a05 | 2885 | \f |
7fa3d080 | 2886 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2887 | |
7fa3d080 BW |
2888 | /* The routine xg_instruction_matches_option_term must return TRUE |
2889 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2890 | terms is given interpretation by this function. */ |
e0001a05 | 2891 | |
7fa3d080 | 2892 | static bfd_boolean |
19e8f41a | 2893 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2894 | { |
7fa3d080 BW |
2895 | if (strcmp (option->option_name, "realnop") == 0 |
2896 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2897 | { | |
2898 | /* These conditions were evaluated statically when building the | |
2899 | relaxation table. There's no need to reevaluate them now. */ | |
2900 | return TRUE; | |
2901 | } | |
19e8f41a BW |
2902 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2903 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2904 | else |
2905 | { | |
2906 | as_fatal (_("internal error: unknown option name '%s'"), | |
2907 | option->option_name); | |
2908 | } | |
e0001a05 NC |
2909 | } |
2910 | ||
2911 | ||
7fa3d080 BW |
2912 | static bfd_boolean |
2913 | xg_instruction_matches_or_options (TInsn *insn, | |
2914 | const ReqOrOptionList *or_option) | |
e0001a05 | 2915 | { |
7fa3d080 BW |
2916 | const ReqOrOption *option; |
2917 | /* Must match each of the AND terms. */ | |
2918 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2919 | { |
7fa3d080 BW |
2920 | if (xg_instruction_matches_option_term (insn, option)) |
2921 | return TRUE; | |
e0001a05 | 2922 | } |
7fa3d080 | 2923 | return FALSE; |
e0001a05 NC |
2924 | } |
2925 | ||
2926 | ||
7fa3d080 BW |
2927 | static bfd_boolean |
2928 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2929 | { |
7fa3d080 BW |
2930 | const ReqOption *req_options; |
2931 | /* Must match each of the AND terms. */ | |
2932 | for (req_options = options; | |
2933 | req_options != NULL; | |
2934 | req_options = req_options->next) | |
e0001a05 | 2935 | { |
7fa3d080 BW |
2936 | /* Must match one of the OR clauses. */ |
2937 | if (!xg_instruction_matches_or_options (insn, | |
2938 | req_options->or_option_terms)) | |
2939 | return FALSE; | |
e0001a05 | 2940 | } |
7fa3d080 | 2941 | return TRUE; |
e0001a05 NC |
2942 | } |
2943 | ||
2944 | ||
7fa3d080 | 2945 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2946 | |
7fa3d080 BW |
2947 | static bfd_boolean |
2948 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2949 | { |
7fa3d080 | 2950 | PreconditionList *condition_l; |
e0001a05 | 2951 | |
7fa3d080 BW |
2952 | if (rule->opcode != insn->opcode) |
2953 | return FALSE; | |
e0001a05 | 2954 | |
7fa3d080 BW |
2955 | for (condition_l = rule->conditions; |
2956 | condition_l != NULL; | |
2957 | condition_l = condition_l->next) | |
e0001a05 | 2958 | { |
7fa3d080 BW |
2959 | expressionS *exp1; |
2960 | expressionS *exp2; | |
2961 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2962 | |
7fa3d080 | 2963 | switch (cond->typ) |
e0001a05 | 2964 | { |
7fa3d080 BW |
2965 | case OP_CONSTANT: |
2966 | /* The expression must be the constant. */ | |
9c2799c2 | 2967 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2968 | exp1 = &insn->tok[cond->op_num]; |
2969 | if (expr_is_const (exp1)) | |
2970 | { | |
2971 | switch (cond->cmp) | |
2972 | { | |
2973 | case OP_EQUAL: | |
2974 | if (get_expr_const (exp1) != cond->op_data) | |
2975 | return FALSE; | |
2976 | break; | |
2977 | case OP_NOTEQUAL: | |
2978 | if (get_expr_const (exp1) == cond->op_data) | |
2979 | return FALSE; | |
2980 | break; | |
2981 | default: | |
2982 | return FALSE; | |
2983 | } | |
2984 | } | |
2985 | else if (expr_is_register (exp1)) | |
2986 | { | |
2987 | switch (cond->cmp) | |
2988 | { | |
2989 | case OP_EQUAL: | |
2990 | if (get_expr_register (exp1) != cond->op_data) | |
2991 | return FALSE; | |
2992 | break; | |
2993 | case OP_NOTEQUAL: | |
2994 | if (get_expr_register (exp1) == cond->op_data) | |
2995 | return FALSE; | |
2996 | break; | |
2997 | default: | |
2998 | return FALSE; | |
2999 | } | |
3000 | } | |
3001 | else | |
3002 | return FALSE; | |
3003 | break; | |
3004 | ||
3005 | case OP_OPERAND: | |
9c2799c2 NC |
3006 | gas_assert (cond->op_num < insn->ntok); |
3007 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
3008 | exp1 = &insn->tok[cond->op_num]; |
3009 | exp2 = &insn->tok[cond->op_data]; | |
3010 | ||
3011 | switch (cond->cmp) | |
3012 | { | |
3013 | case OP_EQUAL: | |
3014 | if (!expr_is_equal (exp1, exp2)) | |
3015 | return FALSE; | |
3016 | break; | |
3017 | case OP_NOTEQUAL: | |
3018 | if (expr_is_equal (exp1, exp2)) | |
3019 | return FALSE; | |
3020 | break; | |
3021 | } | |
3022 | break; | |
3023 | ||
3024 | case OP_LITERAL: | |
3025 | case OP_LABEL: | |
3026 | default: | |
3027 | return FALSE; | |
3028 | } | |
3029 | } | |
3030 | if (!xg_instruction_matches_options (insn, rule->options)) | |
3031 | return FALSE; | |
3032 | ||
3033 | return TRUE; | |
3034 | } | |
3035 | ||
3036 | ||
3037 | static int | |
3038 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
3039 | { | |
3040 | bfd_boolean a_greater = FALSE; | |
3041 | bfd_boolean b_greater = FALSE; | |
3042 | ||
3043 | ReqOptionList *l_a = a->options; | |
3044 | ReqOptionList *l_b = b->options; | |
3045 | ||
3046 | /* We only care if they both are the same except for | |
3047 | a const16 vs. an l32r. */ | |
3048 | ||
3049 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
3050 | { | |
3051 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
3052 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
3053 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
3054 | { | |
3055 | if (l_or_a->is_true != l_or_b->is_true) | |
3056 | return 0; | |
3057 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
3058 | { | |
3059 | /* This is the case we care about. */ | |
3060 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
3061 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
3062 | { | |
3063 | if (prefer_const16) | |
3064 | a_greater = TRUE; | |
3065 | else | |
3066 | b_greater = TRUE; | |
3067 | } | |
3068 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
3069 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
3070 | { | |
3071 | if (prefer_const16) | |
3072 | b_greater = TRUE; | |
3073 | else | |
3074 | a_greater = TRUE; | |
3075 | } | |
3076 | else | |
3077 | return 0; | |
3078 | } | |
3079 | l_or_a = l_or_a->next; | |
3080 | l_or_b = l_or_b->next; | |
3081 | } | |
3082 | if (l_or_a || l_or_b) | |
3083 | return 0; | |
3084 | ||
3085 | l_a = l_a->next; | |
3086 | l_b = l_b->next; | |
3087 | } | |
3088 | if (l_a || l_b) | |
3089 | return 0; | |
3090 | ||
3091 | /* Incomparable if the substitution was used differently in two cases. */ | |
3092 | if (a_greater && b_greater) | |
3093 | return 0; | |
3094 | ||
3095 | if (b_greater) | |
3096 | return 1; | |
3097 | if (a_greater) | |
3098 | return -1; | |
3099 | ||
3100 | return 0; | |
3101 | } | |
3102 | ||
3103 | ||
3104 | static TransitionRule * | |
3105 | xg_instruction_match (TInsn *insn) | |
3106 | { | |
3107 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
3108 | TransitionList *l; | |
9c2799c2 | 3109 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
3110 | |
3111 | /* Walk through all of the possible transitions. */ | |
3112 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3113 | { | |
3114 | TransitionRule *rule = l->rule; | |
3115 | if (xg_instruction_matches_rule (insn, rule)) | |
3116 | return rule; | |
3117 | } | |
3118 | return NULL; | |
3119 | } | |
3120 | ||
3121 | \f | |
3122 | /* Various Other Internal Functions. */ | |
3123 | ||
3124 | static bfd_boolean | |
3125 | is_unique_insn_expansion (TransitionRule *r) | |
3126 | { | |
3127 | if (!r->to_instr || r->to_instr->next != NULL) | |
3128 | return FALSE; | |
3129 | if (r->to_instr->typ != INSTR_INSTR) | |
3130 | return FALSE; | |
3131 | return TRUE; | |
3132 | } | |
3133 | ||
3134 | ||
84b08ed9 BW |
3135 | /* Check if there is exactly one relaxation for INSN that converts it to |
3136 | another instruction of equal or larger size. If so, and if TARG is | |
3137 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3138 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3139 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3140 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3141 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3142 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3143 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3144 | |
84b08ed9 BW |
3145 | bfd_boolean |
3146 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
3147 | { |
3148 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3149 | TransitionList *l; | |
84b08ed9 | 3150 | TransitionRule *match = 0; |
7fa3d080 | 3151 | |
9c2799c2 NC |
3152 | gas_assert (insn->insn_type == ITYPE_INSN); |
3153 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3154 | |
3155 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3156 | { | |
3157 | TransitionRule *rule = l->rule; | |
3158 | ||
3159 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3160 | && is_unique_insn_expansion (rule) |
3161 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3162 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3163 | { |
84b08ed9 BW |
3164 | if (match) |
3165 | return FALSE; | |
3166 | match = rule; | |
7fa3d080 BW |
3167 | } |
3168 | } | |
84b08ed9 BW |
3169 | if (!match) |
3170 | return FALSE; | |
3171 | ||
3172 | if (targ) | |
3173 | xg_build_to_insn (targ, insn, match->to_instr); | |
3174 | return TRUE; | |
7fa3d080 BW |
3175 | } |
3176 | ||
3177 | ||
3178 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3179 | ||
3180 | static int | |
3181 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3182 | { | |
3183 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3184 | TransitionList *l; | |
3185 | int max_size = xg_get_single_size (opcode); | |
3186 | ||
9c2799c2 | 3187 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3188 | |
3189 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3190 | { | |
3191 | TransitionRule *rule = l->rule; | |
3192 | BuildInstr *build_list; | |
3193 | int this_size = 0; | |
3194 | ||
3195 | if (!rule) | |
3196 | continue; | |
3197 | build_list = rule->to_instr; | |
3198 | if (is_unique_insn_expansion (rule)) | |
3199 | { | |
9c2799c2 | 3200 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3201 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3202 | } | |
3203 | else | |
3204 | for (; build_list != NULL; build_list = build_list->next) | |
3205 | { | |
3206 | switch (build_list->typ) | |
3207 | { | |
3208 | case INSTR_INSTR: | |
3209 | this_size += xg_get_single_size (build_list->opcode); | |
3210 | break; | |
3211 | case INSTR_LITERAL_DEF: | |
3212 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3213 | default: |
3214 | break; | |
3215 | } | |
3216 | } | |
3217 | if (this_size > max_size) | |
3218 | max_size = this_size; | |
3219 | } | |
3220 | return max_size; | |
3221 | } | |
3222 | ||
3223 | ||
3224 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3225 | ||
7fa3d080 BW |
3226 | static int |
3227 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3228 | { |
43cd72b9 | 3229 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3230 | TransitionList *l; |
3231 | int max_size = 0; | |
3232 | ||
9c2799c2 | 3233 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3234 | |
3235 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3236 | { | |
3237 | TransitionRule *rule = l->rule; | |
3238 | BuildInstr *build_list; | |
3239 | int this_size = 0; | |
3240 | ||
3241 | if (!rule) | |
3242 | continue; | |
3243 | build_list = rule->to_instr; | |
3244 | if (is_unique_insn_expansion (rule)) | |
3245 | { | |
9c2799c2 | 3246 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3247 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3248 | } | |
3249 | else | |
3250 | for (; build_list != NULL; build_list = build_list->next) | |
3251 | { | |
3252 | switch (build_list->typ) | |
3253 | { | |
3254 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3255 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3256 | this_size += 4; |
3257 | break; | |
3258 | case INSTR_INSTR: | |
3259 | case INSTR_LABEL_DEF: | |
3260 | default: | |
3261 | break; | |
3262 | } | |
3263 | } | |
3264 | if (this_size > max_size) | |
3265 | max_size = this_size; | |
3266 | } | |
3267 | return max_size; | |
3268 | } | |
3269 | ||
3270 | ||
7fa3d080 BW |
3271 | static bfd_boolean |
3272 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3273 | { | |
3274 | int steps_taken = 0; | |
3275 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3276 | TransitionList *l; | |
3277 | ||
9c2799c2 NC |
3278 | gas_assert (insn->insn_type == ITYPE_INSN); |
3279 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3280 | |
3281 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3282 | { | |
3283 | TransitionRule *rule = l->rule; | |
3284 | ||
3285 | if (xg_instruction_matches_rule (insn, rule)) | |
3286 | { | |
3287 | if (steps_taken == lateral_steps) | |
3288 | return TRUE; | |
3289 | steps_taken++; | |
3290 | } | |
3291 | } | |
3292 | return FALSE; | |
3293 | } | |
3294 | ||
3295 | ||
3296 | static symbolS * | |
3297 | get_special_literal_symbol (void) | |
3298 | { | |
3299 | static symbolS *sym = NULL; | |
3300 | ||
3301 | if (sym == NULL) | |
3302 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3303 | return sym; | |
3304 | } | |
3305 | ||
3306 | ||
3307 | static symbolS * | |
3308 | get_special_label_symbol (void) | |
3309 | { | |
3310 | static symbolS *sym = NULL; | |
3311 | ||
3312 | if (sym == NULL) | |
3313 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3314 | return sym; | |
3315 | } | |
3316 | ||
3317 | ||
3318 | static bfd_boolean | |
3319 | xg_valid_literal_expression (const expressionS *exp) | |
3320 | { | |
3321 | switch (exp->X_op) | |
3322 | { | |
3323 | case O_constant: | |
3324 | case O_symbol: | |
3325 | case O_big: | |
3326 | case O_uminus: | |
3327 | case O_subtract: | |
3328 | case O_pltrel: | |
1bbb5f21 | 3329 | case O_pcrel: |
28dbbc02 BW |
3330 | case O_tlsfunc: |
3331 | case O_tlsarg: | |
3332 | case O_tpoff: | |
3333 | case O_dtpoff: | |
7fa3d080 BW |
3334 | return TRUE; |
3335 | default: | |
3336 | return FALSE; | |
3337 | } | |
3338 | } | |
3339 | ||
3340 | ||
3341 | /* This will check to see if the value can be converted into the | |
3342 | operand type. It will return TRUE if it does not fit. */ | |
3343 | ||
3344 | static bfd_boolean | |
3345 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3346 | { | |
3347 | uint32 valbuf = value; | |
3348 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3349 | return TRUE; | |
3350 | return FALSE; | |
3351 | } | |
3352 | ||
3353 | ||
3354 | /* Assumes: All immeds are constants. Check that all constants fit | |
3355 | into their immeds; return FALSE if not. */ | |
3356 | ||
3357 | static bfd_boolean | |
3358 | xg_immeds_fit (const TInsn *insn) | |
3359 | { | |
3360 | xtensa_isa isa = xtensa_default_isa; | |
3361 | int i; | |
3362 | ||
3363 | int n = insn->ntok; | |
9c2799c2 | 3364 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3365 | for (i = 0; i < n; ++i) |
3366 | { | |
91d6fa6a NC |
3367 | const expressionS *exp = &insn->tok[i]; |
3368 | ||
7fa3d080 BW |
3369 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3370 | continue; | |
3371 | ||
91d6fa6a | 3372 | switch (exp->X_op) |
7fa3d080 BW |
3373 | { |
3374 | case O_register: | |
3375 | case O_constant: | |
91d6fa6a | 3376 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3377 | return FALSE; |
3378 | break; | |
3379 | ||
3380 | default: | |
3381 | /* The symbol should have a fixup associated with it. */ | |
9c2799c2 | 3382 | gas_assert (FALSE); |
7fa3d080 BW |
3383 | break; |
3384 | } | |
3385 | } | |
3386 | return TRUE; | |
3387 | } | |
3388 | ||
3389 | ||
3390 | /* This should only be called after we have an initial | |
3391 | estimate of the addresses. */ | |
3392 | ||
3393 | static bfd_boolean | |
3394 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3395 | segT pc_seg, | |
3396 | fragS *pc_frag, | |
3397 | offsetT pc_offset, | |
3398 | long stretch) | |
e0001a05 | 3399 | { |
7fa3d080 BW |
3400 | xtensa_isa isa = xtensa_default_isa; |
3401 | symbolS *symbolP; | |
3402 | fragS *sym_frag; | |
3403 | offsetT target, pc; | |
3404 | uint32 new_offset; | |
3405 | int i; | |
3406 | int n = insn->ntok; | |
e0001a05 | 3407 | |
9c2799c2 | 3408 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3409 | |
7fa3d080 | 3410 | for (i = 0; i < n; ++i) |
e0001a05 | 3411 | { |
91d6fa6a NC |
3412 | const expressionS *exp = &insn->tok[i]; |
3413 | ||
7fa3d080 BW |
3414 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3415 | continue; | |
e0001a05 | 3416 | |
91d6fa6a | 3417 | switch (exp->X_op) |
e0001a05 | 3418 | { |
7fa3d080 BW |
3419 | case O_register: |
3420 | case O_constant: | |
91d6fa6a | 3421 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3422 | return FALSE; |
3423 | break; | |
e0001a05 | 3424 | |
7fa3d080 BW |
3425 | case O_lo16: |
3426 | case O_hi16: | |
3427 | /* Check for the worst case. */ | |
3428 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3429 | return FALSE; | |
3430 | break; | |
e0001a05 | 3431 | |
7fa3d080 | 3432 | case O_symbol: |
7c834684 | 3433 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3434 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3435 | if (pc_frag == 0 |
3436 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3437 | return FALSE; |
e0001a05 | 3438 | |
8e6bc631 BW |
3439 | /* If it is a weak symbol or a symbol in a different section, |
3440 | it cannot be known to fit at assembly time. */ | |
91d6fa6a NC |
3441 | if (S_IS_WEAK (exp->X_add_symbol) |
3442 | || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) | |
7c834684 | 3443 | { |
8e6bc631 | 3444 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3445 | assume it will be in range. If the symbol is weak and |
3446 | undefined, it may remain undefined at link-time, in which | |
3447 | case it will have a zero value and almost certainly be out | |
3448 | of range for a direct call; thus, relax for undefined weak | |
3449 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3450 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f | 3451 | && ! pc_frag->tc_frag_data.use_longcalls |
91d6fa6a NC |
3452 | && (! S_IS_WEAK (exp->X_add_symbol) |
3453 | || S_IS_DEFINED (exp->X_add_symbol))) | |
7c834684 | 3454 | return TRUE; |
7c834684 | 3455 | |
8e6bc631 BW |
3456 | return FALSE; |
3457 | } | |
e0001a05 | 3458 | |
91d6fa6a | 3459 | symbolP = exp->X_add_symbol; |
7fa3d080 | 3460 | sym_frag = symbol_get_frag (symbolP); |
91d6fa6a | 3461 | target = S_GET_VALUE (symbolP) + exp->X_add_number; |
7fa3d080 | 3462 | pc = pc_frag->fr_address + pc_offset; |
e0001a05 | 3463 | |
7fa3d080 BW |
3464 | /* If frag has yet to be reached on this pass, assume it |
3465 | will move by STRETCH just as we did. If this is not so, | |
3466 | it will be because some frag between grows, and that will | |
3467 | force another pass. Beware zero-length frags. There | |
3468 | should be a faster way to do this. */ | |
3469 | ||
3470 | if (stretch != 0 | |
3471 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3472 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3473 | { | |
3474 | target += stretch; | |
3475 | } | |
c138bc38 | 3476 | |
7fa3d080 BW |
3477 | new_offset = target; |
3478 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3479 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3480 | return FALSE; | |
3481 | break; | |
3482 | ||
3483 | default: | |
3484 | /* The symbol should have a fixup associated with it. */ | |
3485 | return FALSE; | |
3486 | } | |
3487 | } | |
3488 | ||
3489 | return TRUE; | |
e0001a05 NC |
3490 | } |
3491 | ||
3492 | ||
43cd72b9 | 3493 | /* Return TRUE on success. */ |
e0001a05 | 3494 | |
7fa3d080 BW |
3495 | static bfd_boolean |
3496 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3497 | { |
3498 | BuildOp *op; | |
3499 | symbolS *sym; | |
3500 | ||
60242db2 | 3501 | tinsn_init (targ); |
b224e962 BW |
3502 | targ->debug_line = insn->debug_line; |
3503 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3504 | switch (bi->typ) |
3505 | { | |
3506 | case INSTR_INSTR: | |
3507 | op = bi->ops; | |
3508 | targ->opcode = bi->opcode; | |
3509 | targ->insn_type = ITYPE_INSN; | |
3510 | targ->is_specific_opcode = FALSE; | |
3511 | ||
3512 | for (; op != NULL; op = op->next) | |
3513 | { | |
3514 | int op_num = op->op_num; | |
3515 | int op_data = op->op_data; | |
3516 | ||
9c2799c2 | 3517 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3518 | |
3519 | if (targ->ntok <= op_num) | |
3520 | targ->ntok = op_num + 1; | |
3521 | ||
3522 | switch (op->typ) | |
3523 | { | |
3524 | case OP_CONSTANT: | |
3525 | set_expr_const (&targ->tok[op_num], op_data); | |
3526 | break; | |
3527 | case OP_OPERAND: | |
9c2799c2 | 3528 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3529 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3530 | break; | |
19e8f41a BW |
3531 | case OP_FREEREG: |
3532 | if (insn->extra_arg.X_op != O_register) | |
3533 | return FALSE; | |
3534 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3535 | break; | |
e0001a05 NC |
3536 | case OP_LITERAL: |
3537 | sym = get_special_literal_symbol (); | |
3538 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3539 | if (insn->tok[op_data].X_op == O_tlsfunc |
3540 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3541 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3542 | break; |
3543 | case OP_LABEL: | |
3544 | sym = get_special_label_symbol (); | |
3545 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3546 | break; | |
43cd72b9 BW |
3547 | case OP_OPERAND_HI16U: |
3548 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3549 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3550 | if (expr_is_const (&insn->tok[op_data])) |
3551 | { | |
3552 | long val; | |
3553 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3554 | val = xg_apply_userdef_op_fn (op->typ, | |
3555 | targ->tok[op_num]. | |
3556 | X_add_number); | |
3557 | targ->tok[op_num].X_add_number = val; | |
3558 | } | |
3559 | else | |
3560 | { | |
3561 | /* For const16 we can create relocations for these. */ | |
3562 | if (targ->opcode == XTENSA_UNDEFINED | |
3563 | || (targ->opcode != xtensa_const16_opcode)) | |
3564 | return FALSE; | |
9c2799c2 | 3565 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3566 | /* Need to build a O_lo16 or O_hi16. */ |
3567 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3568 | if (targ->tok[op_num].X_op == O_symbol) | |
3569 | { | |
3570 | if (op->typ == OP_OPERAND_HI16U) | |
3571 | targ->tok[op_num].X_op = O_hi16; | |
3572 | else if (op->typ == OP_OPERAND_LOW16U) | |
3573 | targ->tok[op_num].X_op = O_lo16; | |
3574 | else | |
3575 | return FALSE; | |
3576 | } | |
3577 | } | |
3578 | break; | |
e0001a05 NC |
3579 | default: |
3580 | /* currently handles: | |
3581 | OP_OPERAND_LOW8 | |
3582 | OP_OPERAND_HI24S | |
3583 | OP_OPERAND_F32MINUS */ | |
3584 | if (xg_has_userdef_op_fn (op->typ)) | |
3585 | { | |
9c2799c2 | 3586 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3587 | if (expr_is_const (&insn->tok[op_data])) |
3588 | { | |
3589 | long val; | |
3590 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3591 | val = xg_apply_userdef_op_fn (op->typ, | |
3592 | targ->tok[op_num]. | |
3593 | X_add_number); | |
3594 | targ->tok[op_num].X_add_number = val; | |
3595 | } | |
3596 | else | |
3597 | return FALSE; /* We cannot use a relocation for this. */ | |
3598 | break; | |
3599 | } | |
9c2799c2 | 3600 | gas_assert (0); |
e0001a05 NC |
3601 | break; |
3602 | } | |
3603 | } | |
3604 | break; | |
3605 | ||
3606 | case INSTR_LITERAL_DEF: | |
3607 | op = bi->ops; | |
3608 | targ->opcode = XTENSA_UNDEFINED; | |
3609 | targ->insn_type = ITYPE_LITERAL; | |
3610 | targ->is_specific_opcode = FALSE; | |
3611 | for (; op != NULL; op = op->next) | |
3612 | { | |
3613 | int op_num = op->op_num; | |
3614 | int op_data = op->op_data; | |
9c2799c2 | 3615 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3616 | |
3617 | if (targ->ntok <= op_num) | |
3618 | targ->ntok = op_num + 1; | |
3619 | ||
3620 | switch (op->typ) | |
3621 | { | |
3622 | case OP_OPERAND: | |
9c2799c2 | 3623 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3624 | /* We can only pass resolvable literals through. */ |
3625 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3626 | return FALSE; | |
e0001a05 NC |
3627 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3628 | break; | |
3629 | case OP_LITERAL: | |
3630 | case OP_CONSTANT: | |
3631 | case OP_LABEL: | |
3632 | default: | |
9c2799c2 | 3633 | gas_assert (0); |
e0001a05 NC |
3634 | break; |
3635 | } | |
3636 | } | |
3637 | break; | |
3638 | ||
3639 | case INSTR_LABEL_DEF: | |
3640 | op = bi->ops; | |
3641 | targ->opcode = XTENSA_UNDEFINED; | |
3642 | targ->insn_type = ITYPE_LABEL; | |
3643 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3644 | /* Literal with no ops is a label? */ |
9c2799c2 | 3645 | gas_assert (op == NULL); |
e0001a05 NC |
3646 | break; |
3647 | ||
3648 | default: | |
9c2799c2 | 3649 | gas_assert (0); |
e0001a05 NC |
3650 | } |
3651 | ||
3652 | return TRUE; | |
3653 | } | |
3654 | ||
3655 | ||
43cd72b9 | 3656 | /* Return TRUE on success. */ |
e0001a05 | 3657 | |
7fa3d080 BW |
3658 | static bfd_boolean |
3659 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3660 | { |
3661 | for (; bi != NULL; bi = bi->next) | |
3662 | { | |
3663 | TInsn *next_insn = istack_push_space (istack); | |
3664 | ||
3665 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3666 | return FALSE; | |
3667 | } | |
3668 | return TRUE; | |
3669 | } | |
3670 | ||
3671 | ||
43cd72b9 | 3672 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3673 | |
7fa3d080 BW |
3674 | static bfd_boolean |
3675 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3676 | { |
3677 | int stack_size = istack->ninsn; | |
3678 | int steps_taken = 0; | |
43cd72b9 | 3679 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3680 | TransitionList *l; |
3681 | ||
9c2799c2 NC |
3682 | gas_assert (insn->insn_type == ITYPE_INSN); |
3683 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3684 | |
3685 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3686 | { | |
3687 | TransitionRule *rule = l->rule; | |
3688 | ||
3689 | if (xg_instruction_matches_rule (insn, rule)) | |
3690 | { | |
3691 | if (lateral_steps == steps_taken) | |
3692 | { | |
3693 | int i; | |
3694 | ||
3695 | /* This is it. Expand the rule to the stack. */ | |
3696 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3697 | return FALSE; | |
3698 | ||
3699 | /* Check to see if it fits. */ | |
3700 | for (i = stack_size; i < istack->ninsn; i++) | |
3701 | { | |
91d6fa6a | 3702 | TInsn *tinsn = &istack->insn[i]; |
e0001a05 | 3703 | |
91d6fa6a NC |
3704 | if (tinsn->insn_type == ITYPE_INSN |
3705 | && !tinsn_has_symbolic_operands (tinsn) | |
3706 | && !xg_immeds_fit (tinsn)) | |
e0001a05 NC |
3707 | { |
3708 | istack->ninsn = stack_size; | |
3709 | return FALSE; | |
3710 | } | |
3711 | } | |
3712 | return TRUE; | |
3713 | } | |
3714 | steps_taken++; | |
3715 | } | |
3716 | } | |
3717 | return FALSE; | |
3718 | } | |
3719 | ||
43cd72b9 | 3720 | \f |
43cd72b9 | 3721 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3722 | Return the number of steps taken. |
3723 | ||
3724 | For relaxation to correctly terminate, every relaxation chain must | |
3725 | terminate in one of two ways: | |
3726 | ||
3727 | 1. If the chain from one instruction to the next consists entirely of | |
3728 | single instructions, then the chain *must* handle all possible | |
3729 | immediates without failing. It must not ever fail because an | |
3730 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3731 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3732 | immediate larger than 32 bits, so it satisfies this condition. | |
3733 | Single instruction relaxation chains are as defined by | |
3734 | xg_is_single_relaxable_instruction. | |
3735 | ||
3736 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3737 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3738 | ||
3739 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3740 | -- in particular when the last two instructions have the same single | |
3741 | size. But nevertheless, you should guarantee the above two conditions. | |
3742 | ||
3743 | We could fix this so that single-instruction expansions correctly | |
3744 | terminate when they can't handle the range, but the error messages are | |
3745 | worse, and it actually turns out that in every case but one (18-bit wide | |
3746 | branches), you need a multi-instruction expansion to get the full range | |
3747 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3748 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3749 | |
7fa3d080 BW |
3750 | static int |
3751 | xg_assembly_relax (IStack *istack, | |
3752 | TInsn *insn, | |
3753 | segT pc_seg, | |
3754 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3755 | offsetT pc_offset, /* offset in fragment */ | |
3756 | int min_steps, /* minimum conversion steps */ | |
3757 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3758 | { |
3759 | int steps_taken = 0; | |
3760 | ||
b81bf389 BW |
3761 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3762 | This may go through a couple of stages of single instruction | |
3763 | transformations before we get there. */ | |
e0001a05 NC |
3764 | |
3765 | TInsn single_target; | |
3766 | TInsn current_insn; | |
3767 | int lateral_steps = 0; | |
3768 | int istack_size = istack->ninsn; | |
3769 | ||
3770 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3771 | && steps_taken >= min_steps) | |
3772 | { | |
3773 | istack_push (istack, insn); | |
3774 | return steps_taken; | |
3775 | } | |
43cd72b9 | 3776 | current_insn = *insn; |
e0001a05 | 3777 | |
7c834684 | 3778 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3779 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3780 | { |
21af2bbd | 3781 | steps_taken++; |
e0001a05 NC |
3782 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3783 | stretch)) | |
3784 | { | |
e0001a05 NC |
3785 | if (steps_taken >= min_steps) |
3786 | { | |
3787 | istack_push (istack, &single_target); | |
3788 | return steps_taken; | |
3789 | } | |
3790 | } | |
43cd72b9 | 3791 | current_insn = single_target; |
e0001a05 NC |
3792 | } |
3793 | ||
3794 | /* Now check for a multi-instruction expansion. */ | |
3795 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3796 | { | |
3797 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3798 | stretch)) | |
3799 | { | |
3800 | if (steps_taken >= min_steps) | |
3801 | { | |
3802 | istack_push (istack, ¤t_insn); | |
3803 | return steps_taken; | |
3804 | } | |
3805 | } | |
3806 | steps_taken++; | |
3807 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3808 | { | |
3809 | if (steps_taken >= min_steps) | |
3810 | return steps_taken; | |
3811 | } | |
3812 | lateral_steps++; | |
3813 | istack->ninsn = istack_size; | |
3814 | } | |
3815 | ||
3816 | /* It's not going to work -- use the original. */ | |
3817 | istack_push (istack, insn); | |
3818 | return steps_taken; | |
3819 | } | |
3820 | ||
3821 | ||
7fa3d080 BW |
3822 | static void |
3823 | xg_finish_frag (char *last_insn, | |
3824 | enum xtensa_relax_statesE frag_state, | |
3825 | enum xtensa_relax_statesE slot0_state, | |
3826 | int max_growth, | |
3827 | bfd_boolean is_insn) | |
e0001a05 NC |
3828 | { |
3829 | /* Finish off this fragment so that it has at LEAST the desired | |
3830 | max_growth. If it doesn't fit in this fragment, close this one | |
3831 | and start a new one. In either case, return a pointer to the | |
3832 | beginning of the growth area. */ | |
3833 | ||
3834 | fragS *old_frag; | |
43cd72b9 | 3835 | |
542f8b94 | 3836 | frag_grow (max_growth); |
e0001a05 NC |
3837 | old_frag = frag_now; |
3838 | ||
3839 | frag_now->fr_opcode = last_insn; | |
3840 | if (is_insn) | |
3841 | frag_now->tc_frag_data.is_insn = TRUE; | |
3842 | ||
3843 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3844 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3845 | ||
3846 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3847 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3848 | |
3849 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3850 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3851 | } |
3852 | ||
3853 | ||
7fa3d080 BW |
3854 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3855 | ||
3856 | static bfd_boolean | |
3857 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3858 | { | |
3859 | if (fragP == NULL) | |
3860 | return FALSE; | |
3861 | ||
3862 | for (; fragP; fragP = fragP->fr_next) | |
3863 | { | |
3864 | if (fragP == target) | |
3865 | return TRUE; | |
3866 | if (fragP->fr_fix != 0) | |
3867 | return FALSE; | |
3868 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3869 | return FALSE; | |
3870 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3871 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3872 | return FALSE; | |
3873 | if (fragP->fr_type == rs_space) | |
3874 | return FALSE; | |
3875 | } | |
3876 | return FALSE; | |
3877 | } | |
3878 | ||
3879 | ||
e0001a05 | 3880 | static bfd_boolean |
7fa3d080 | 3881 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3882 | { |
3883 | xtensa_isa isa = xtensa_default_isa; | |
3884 | int i; | |
43cd72b9 | 3885 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3886 | int target_op = -1; |
3887 | symbolS *sym; | |
3888 | fragS *target_frag; | |
3889 | ||
64b607e6 BW |
3890 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3891 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3892 | return FALSE; |
3893 | ||
3894 | for (i = 0; i < num_ops; i++) | |
3895 | { | |
43cd72b9 | 3896 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3897 | { |
3898 | target_op = i; | |
3899 | break; | |
3900 | } | |
3901 | } | |
3902 | if (target_op == -1) | |
3903 | return FALSE; | |
3904 | ||
3905 | if (insn->ntok <= target_op) | |
3906 | return FALSE; | |
3907 | ||
3908 | if (insn->tok[target_op].X_op != O_symbol) | |
3909 | return FALSE; | |
3910 | ||
3911 | sym = insn->tok[target_op].X_add_symbol; | |
3912 | if (sym == NULL) | |
3913 | return FALSE; | |
3914 | ||
3915 | if (insn->tok[target_op].X_add_number != 0) | |
3916 | return FALSE; | |
3917 | ||
3918 | target_frag = symbol_get_frag (sym); | |
3919 | if (target_frag == NULL) | |
3920 | return FALSE; | |
3921 | ||
c138bc38 | 3922 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3923 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3924 | return TRUE; | |
3925 | ||
3926 | return FALSE; | |
3927 | } | |
3928 | ||
3929 | ||
3930 | static void | |
7fa3d080 | 3931 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3932 | { |
3933 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3934 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3935 | |
7fa3d080 BW |
3936 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3937 | { | |
3938 | int i = 1; | |
3939 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3940 | && insn->tok[i].X_op == O_symbol) | |
3941 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3942 | return; | |
3943 | } | |
e0001a05 | 3944 | |
7fa3d080 BW |
3945 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3946 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3947 | { |
7fa3d080 BW |
3948 | int i; |
3949 | ||
3950 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3951 | { | |
3952 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3953 | && insn->tok[i].X_op == O_symbol) | |
3954 | { | |
3955 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3956 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3957 | if (S_IS_DEFINED (sym)) | |
3958 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3959 | } | |
3960 | } | |
e0001a05 | 3961 | } |
e0001a05 NC |
3962 | } |
3963 | ||
3964 | ||
43cd72b9 | 3965 | /* Return FALSE if no error. */ |
e0001a05 | 3966 | |
7fa3d080 BW |
3967 | static bfd_boolean |
3968 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3969 | { |
3970 | int num_ops = 0; | |
3971 | BuildOp *b_op; | |
3972 | ||
3973 | switch (instr_spec->typ) | |
3974 | { | |
3975 | case INSTR_INSTR: | |
3976 | new_insn->insn_type = ITYPE_INSN; | |
3977 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3978 | break; |
3979 | case INSTR_LITERAL_DEF: | |
3980 | new_insn->insn_type = ITYPE_LITERAL; | |
3981 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3982 | break; |
3983 | case INSTR_LABEL_DEF: | |
b224e962 | 3984 | abort (); |
e0001a05 | 3985 | } |
b224e962 BW |
3986 | new_insn->is_specific_opcode = FALSE; |
3987 | new_insn->debug_line = old_insn->debug_line; | |
3988 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3989 | |
3990 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3991 | { | |
3992 | expressionS *exp; | |
3993 | const expressionS *src_exp; | |
3994 | ||
3995 | num_ops++; | |
3996 | switch (b_op->typ) | |
3997 | { | |
3998 | case OP_CONSTANT: | |
3999 | /* The expression must be the constant. */ | |
9c2799c2 | 4000 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
4001 | exp = &new_insn->tok[b_op->op_num]; |
4002 | set_expr_const (exp, b_op->op_data); | |
4003 | break; | |
4004 | ||
4005 | case OP_OPERAND: | |
9c2799c2 NC |
4006 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
4007 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
4008 | src_exp = &old_insn->tok[b_op->op_data]; |
4009 | exp = &new_insn->tok[b_op->op_num]; | |
4010 | copy_expr (exp, src_exp); | |
4011 | break; | |
4012 | ||
4013 | case OP_LITERAL: | |
4014 | case OP_LABEL: | |
4015 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 4016 | gas_assert (0); |
e0001a05 NC |
4017 | |
4018 | default: | |
4019 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 4020 | gas_assert (0); |
e0001a05 NC |
4021 | } |
4022 | } | |
4023 | ||
4024 | new_insn->ntok = num_ops; | |
4025 | return FALSE; | |
4026 | } | |
4027 | ||
4028 | ||
43cd72b9 | 4029 | /* Return TRUE if it was simplified. */ |
e0001a05 | 4030 | |
7fa3d080 BW |
4031 | static bfd_boolean |
4032 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 4033 | { |
43cd72b9 | 4034 | TransitionRule *rule; |
e0001a05 | 4035 | BuildInstr *insn_spec; |
43cd72b9 BW |
4036 | |
4037 | if (old_insn->is_specific_opcode || !density_supported) | |
4038 | return FALSE; | |
4039 | ||
4040 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
4041 | if (rule == NULL) |
4042 | return FALSE; | |
4043 | ||
4044 | insn_spec = rule->to_instr; | |
4045 | /* There should only be one. */ | |
9c2799c2 NC |
4046 | gas_assert (insn_spec != NULL); |
4047 | gas_assert (insn_spec->next == NULL); | |
e0001a05 NC |
4048 | if (insn_spec->next != NULL) |
4049 | return FALSE; | |
4050 | ||
4051 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
4052 | ||
4053 | return TRUE; | |
4054 | } | |
4055 | ||
4056 | ||
4057 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
4058 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
4059 | tokens into the stack or relax it and place multiple |
4060 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
4061 | |
4062 | static bfd_boolean | |
7fa3d080 | 4063 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
4064 | { |
4065 | int noperands; | |
4066 | TInsn new_insn; | |
7c834684 BW |
4067 | bfd_boolean do_expand; |
4068 | ||
60242db2 | 4069 | tinsn_init (&new_insn); |
e0001a05 | 4070 | |
43cd72b9 BW |
4071 | /* Narrow it if we can. xg_simplify_insn now does all the |
4072 | appropriate checking (e.g., for the density option). */ | |
4073 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
4074 | orig_insn = &new_insn; | |
e0001a05 | 4075 | |
43cd72b9 BW |
4076 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
4077 | orig_insn->opcode); | |
e0001a05 NC |
4078 | if (orig_insn->ntok < noperands) |
4079 | { | |
992a06ee AM |
4080 | as_bad (ngettext ("found %d operand for '%s': Expected %d", |
4081 | "found %d operands for '%s': Expected %d", | |
4082 | orig_insn->ntok), | |
e0001a05 NC |
4083 | orig_insn->ntok, |
4084 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4085 | noperands); | |
4086 | return TRUE; | |
4087 | } | |
4088 | if (orig_insn->ntok > noperands) | |
992a06ee AM |
4089 | as_warn (ngettext ("found %d operand for '%s': Expected %d", |
4090 | "found %d operands for '%s': Expected %d", | |
4091 | orig_insn->ntok), | |
e0001a05 NC |
4092 | orig_insn->ntok, |
4093 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4094 | noperands); | |
4095 | ||
43cd72b9 | 4096 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 4097 | are too many, just cut out the extras here. */ |
e0001a05 NC |
4098 | orig_insn->ntok = noperands; |
4099 | ||
e0001a05 NC |
4100 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
4101 | return TRUE; | |
4102 | ||
d12f9798 BW |
4103 | /* Special case for extui opcode which has constraints not handled |
4104 | by the ordinary operand encoding checks. The number of operands | |
4105 | and related syntax issues have already been checked. */ | |
4106 | if (orig_insn->opcode == xtensa_extui_opcode) | |
4107 | { | |
4108 | int shiftimm = orig_insn->tok[2].X_add_number; | |
4109 | int maskimm = orig_insn->tok[3].X_add_number; | |
4110 | if (shiftimm + maskimm > 32) | |
4111 | { | |
4112 | as_bad (_("immediate operands sum to greater than 32")); | |
4113 | return TRUE; | |
4114 | } | |
4115 | } | |
4116 | ||
7c834684 BW |
4117 | /* If the instruction will definitely need to be relaxed, it is better |
4118 | to expand it now for better scheduling. Decide whether to expand | |
4119 | now.... */ | |
4120 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
4121 | ||
4122 | /* Calls should be expanded to longcalls only in the backend relaxation | |
4123 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
4124 | adjacent. */ | |
4125 | if (is_direct_call_opcode (orig_insn->opcode)) | |
4126 | do_expand = FALSE; | |
e0001a05 NC |
4127 | |
4128 | if (tinsn_has_symbolic_operands (orig_insn)) | |
4129 | { | |
7c834684 BW |
4130 | /* The values of symbolic operands are not known yet, so only expand |
4131 | now if an operand is "complex" (e.g., difference of symbols) and | |
4132 | will have to be stored as a literal regardless of the value. */ | |
4133 | if (!tinsn_has_complex_operands (orig_insn)) | |
4134 | do_expand = FALSE; | |
e0001a05 | 4135 | } |
7c834684 BW |
4136 | else if (xg_immeds_fit (orig_insn)) |
4137 | do_expand = FALSE; | |
4138 | ||
4139 | if (do_expand) | |
4140 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4141 | else |
7c834684 | 4142 | istack_push (istack, orig_insn); |
e0001a05 | 4143 | |
e0001a05 NC |
4144 | return FALSE; |
4145 | } | |
4146 | ||
4147 | ||
7fa3d080 | 4148 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4149 | or the name is .gnu.linkonce.*. */ |
4150 | ||
4151 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
4152 | |
4153 | static bfd_boolean | |
4154 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4155 | { | |
4156 | flagword flags, link_once_flags; | |
4157 | ||
fd361982 | 4158 | flags = bfd_section_flags (sec); |
7fa3d080 BW |
4159 | link_once_flags = (flags & SEC_LINK_ONCE); |
4160 | ||
4161 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4162 | if (!link_once_flags |
4163 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4164 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4165 | |
7fa3d080 BW |
4166 | return (link_once_flags != 0); |
4167 | } | |
4168 | ||
4169 | ||
4170 | static void | |
4171 | xtensa_add_literal_sym (symbolS *sym) | |
4172 | { | |
4173 | sym_list *l; | |
4174 | ||
325801bd | 4175 | l = XNEW (sym_list); |
7fa3d080 BW |
4176 | l->sym = sym; |
4177 | l->next = literal_syms; | |
4178 | literal_syms = l; | |
4179 | } | |
4180 | ||
4181 | ||
4182 | static symbolS * | |
4183 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4184 | { | |
4185 | static int lit_num = 0; | |
4186 | static char name[256]; | |
4187 | symbolS *symbolP; | |
4188 | ||
4189 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4190 | ||
4191 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4192 | be careful to make sure that if it is used in a relocation that the | |
4193 | symbol will be in the output file. */ | |
4194 | if (get_is_linkonce_section (stdoutput, sec)) | |
4195 | { | |
e01e1cee | 4196 | symbolP = symbol_new (name, sec, frag, 0); |
7fa3d080 BW |
4197 | S_CLEAR_EXTERNAL (symbolP); |
4198 | /* symbolP->local = 1; */ | |
4199 | } | |
4200 | else | |
e01e1cee | 4201 | symbolP = symbol_new (name, sec, frag, 0); |
7fa3d080 BW |
4202 | |
4203 | xtensa_add_literal_sym (symbolP); | |
4204 | ||
7fa3d080 BW |
4205 | lit_num++; |
4206 | return symbolP; | |
4207 | } | |
4208 | ||
4209 | ||
e0001a05 NC |
4210 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4211 | ||
7fa3d080 BW |
4212 | static symbolS * |
4213 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4214 | { |
4215 | emit_state state; | |
4216 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4217 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4218 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4219 | char *p; |
e0001a05 NC |
4220 | |
4221 | /* size = 4 for L32R. It could easily be larger when we move to | |
4222 | larger constants. Add a parameter later. */ | |
4223 | offsetT litsize = 4; | |
4224 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4225 | expressionS saved_loc; | |
43cd72b9 BW |
4226 | expressionS * emit_val; |
4227 | ||
e0001a05 NC |
4228 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4229 | ||
9c2799c2 NC |
4230 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4231 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4232 | |
4233 | xtensa_switch_to_literal_fragment (&state); | |
4234 | ||
43cd72b9 BW |
4235 | emit_val = &insn->tok[0]; |
4236 | if (emit_val->X_op == O_big) | |
4237 | { | |
4238 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4239 | if (size > litsize) | |
4240 | { | |
4241 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4242 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4243 | _("invalid immediate")); |
4244 | xtensa_restore_emit_state (&state); | |
4245 | return NULL; | |
4246 | } | |
4247 | } | |
4248 | ||
e0001a05 NC |
4249 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4250 | literals done with this function have a frag to themselves. That's | |
4251 | important for the way text section literals work. */ | |
4252 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4253 | record_alignment (now_seg, litalign); |
e0001a05 | 4254 | |
bbdd25a8 | 4255 | switch (emit_val->X_op) |
43cd72b9 | 4256 | { |
1bbb5f21 BW |
4257 | case O_pcrel: |
4258 | pcrel = TRUE; | |
4259 | /* fall through */ | |
bbdd25a8 | 4260 | case O_pltrel: |
28dbbc02 BW |
4261 | case O_tlsfunc: |
4262 | case O_tlsarg: | |
4263 | case O_tpoff: | |
4264 | case O_dtpoff: | |
bbdd25a8 | 4265 | p = frag_more (litsize); |
43cd72b9 | 4266 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4267 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4268 | if (emit_val->X_add_symbol) |
4269 | emit_val->X_op = O_symbol; | |
4270 | else | |
4271 | emit_val->X_op = O_constant; | |
4272 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4273 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4274 | break; |
4275 | ||
4276 | default: | |
4277 | emit_expr (emit_val, litsize); | |
4278 | break; | |
43cd72b9 | 4279 | } |
e0001a05 | 4280 | |
9c2799c2 | 4281 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4282 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4283 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4284 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4285 | |
4286 | /* Go back. */ | |
4287 | xtensa_restore_emit_state (&state); | |
4288 | return lit_sym; | |
4289 | } | |
4290 | ||
4291 | ||
4292 | static void | |
7fa3d080 | 4293 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4294 | { |
4295 | emit_state state; | |
43cd72b9 | 4296 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4297 | takes effect if something is placed here. */ |
4298 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4299 | fragS *lit_saved_frag; | |
4300 | ||
9c2799c2 | 4301 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4302 | |
4303 | xtensa_switch_to_literal_fragment (&state); | |
4304 | ||
4305 | /* Force a 4-byte align here. */ | |
4306 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4307 | record_alignment (now_seg, litalign); |
e0001a05 | 4308 | |
542f8b94 | 4309 | frag_grow (size); |
e0001a05 NC |
4310 | |
4311 | lit_saved_frag = frag_now; | |
4312 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4313 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4314 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4315 | |
4316 | /* Go back. */ | |
4317 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4318 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4319 | } |
4320 | ||
4321 | ||
e0001a05 | 4322 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4323 | Return TRUE on success. */ |
e0001a05 | 4324 | |
7fa3d080 BW |
4325 | static bfd_boolean |
4326 | xg_add_opcode_fix (TInsn *tinsn, | |
4327 | int opnum, | |
4328 | xtensa_format fmt, | |
4329 | int slot, | |
91d6fa6a | 4330 | expressionS *exp, |
7fa3d080 BW |
4331 | fragS *fragP, |
4332 | offsetT offset) | |
43cd72b9 BW |
4333 | { |
4334 | xtensa_opcode opcode = tinsn->opcode; | |
4335 | bfd_reloc_code_real_type reloc; | |
4336 | reloc_howto_type *howto; | |
4337 | int fmt_length; | |
e0001a05 NC |
4338 | fixS *the_fix; |
4339 | ||
43cd72b9 BW |
4340 | reloc = BFD_RELOC_NONE; |
4341 | ||
4342 | /* First try the special cases for "alternate" relocs. */ | |
4343 | if (opcode == xtensa_l32r_opcode) | |
4344 | { | |
4345 | if (fragP->tc_frag_data.use_absolute_literals) | |
4346 | reloc = encode_alt_reloc (slot); | |
4347 | } | |
4348 | else if (opcode == xtensa_const16_opcode) | |
4349 | { | |
91d6fa6a | 4350 | if (exp->X_op == O_lo16) |
43cd72b9 BW |
4351 | { |
4352 | reloc = encode_reloc (slot); | |
91d6fa6a | 4353 | exp->X_op = O_symbol; |
43cd72b9 | 4354 | } |
91d6fa6a | 4355 | else if (exp->X_op == O_hi16) |
43cd72b9 BW |
4356 | { |
4357 | reloc = encode_alt_reloc (slot); | |
91d6fa6a | 4358 | exp->X_op = O_symbol; |
43cd72b9 BW |
4359 | } |
4360 | } | |
4361 | ||
4362 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4363 | { |
43cd72b9 | 4364 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4365 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4366 | return FALSE; |
4367 | } | |
4368 | ||
43cd72b9 BW |
4369 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4370 | into the symbol table where the generic portions of the assembler | |
4371 | won't know what to do with them. */ | |
91d6fa6a | 4372 | if (exp->X_op == O_lo16 || exp->X_op == O_hi16) |
43cd72b9 BW |
4373 | { |
4374 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4375 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4376 | return FALSE; |
4377 | } | |
4378 | ||
4379 | /* Next try the generic relocs. */ | |
4380 | if (reloc == BFD_RELOC_NONE) | |
4381 | reloc = encode_reloc (slot); | |
4382 | if (reloc == BFD_RELOC_NONE) | |
4383 | { | |
4384 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4385 | return FALSE; | |
4386 | } | |
e0001a05 | 4387 | |
43cd72b9 | 4388 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4389 | if (!howto) |
4390 | { | |
43cd72b9 | 4391 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4392 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4393 | return FALSE; | |
4394 | } | |
4395 | ||
43cd72b9 | 4396 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
91d6fa6a | 4397 | the_fix = fix_new_exp (fragP, offset, fmt_length, exp, |
e0001a05 | 4398 | howto->pc_relative, reloc); |
d9740523 | 4399 | the_fix->fx_no_overflow = 1; |
91d6fa6a NC |
4400 | the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; |
4401 | the_fix->tc_fix_data.X_add_number = exp->X_add_number; | |
7fa3d080 | 4402 | the_fix->tc_fix_data.slot = slot; |
c138bc38 | 4403 | |
7fa3d080 BW |
4404 | return TRUE; |
4405 | } | |
4406 | ||
4407 | ||
4408 | static bfd_boolean | |
4409 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4410 | char *buf, |
4411 | fragS *fragP, | |
4412 | offsetT offset, | |
4413 | bfd_boolean build_fix) | |
4414 | { | |
4415 | static xtensa_insnbuf insnbuf = NULL; | |
4416 | bfd_boolean has_symbolic_immed = FALSE; | |
4417 | bfd_boolean ok = TRUE; | |
b2d179be | 4418 | |
7fa3d080 BW |
4419 | if (!insnbuf) |
4420 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4421 | ||
4422 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4423 | if (has_symbolic_immed && build_fix) | |
4424 | { | |
4425 | /* Add a fixup. */ | |
b2d179be BW |
4426 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4427 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4428 | int opnum = get_relaxable_immed (tinsn->opcode); |
4429 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4430 | |
b2d179be | 4431 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4432 | ok = FALSE; |
4433 | } | |
4434 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4435 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4436 | (unsigned char *) buf, 0); | |
7fa3d080 | 4437 | return ok; |
e0001a05 NC |
4438 | } |
4439 | ||
4440 | ||
7fa3d080 BW |
4441 | static void |
4442 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4443 | { |
4444 | symbolS *sym = get_special_literal_symbol (); | |
4445 | int i; | |
4446 | if (lit_sym == 0) | |
4447 | return; | |
9c2799c2 | 4448 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4449 | for (i = 0; i < insn->ntok; i++) |
4450 | if (insn->tok[i].X_add_symbol == sym) | |
4451 | insn->tok[i].X_add_symbol = lit_sym; | |
4452 | ||
4453 | } | |
4454 | ||
4455 | ||
7fa3d080 BW |
4456 | static void |
4457 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4458 | { |
4459 | symbolS *sym = get_special_label_symbol (); | |
4460 | int i; | |
e0001a05 NC |
4461 | for (i = 0; i < insn->ntok; i++) |
4462 | if (insn->tok[i].X_add_symbol == sym) | |
4463 | insn->tok[i].X_add_symbol = label_sym; | |
4464 | ||
4465 | } | |
4466 | ||
4467 | ||
43cd72b9 | 4468 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4469 | integer register. */ |
4470 | ||
4471 | static bfd_boolean | |
7fa3d080 | 4472 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4473 | { |
4474 | int i; | |
4475 | int num_ops; | |
4476 | xtensa_isa isa = xtensa_default_isa; | |
4477 | ||
43cd72b9 | 4478 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4479 | |
4480 | for (i = 0; i < num_ops; i++) | |
4481 | { | |
43cd72b9 BW |
4482 | char inout; |
4483 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4484 | if ((inout == 'o' || inout == 'm') | |
4485 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4486 | { |
43cd72b9 BW |
4487 | xtensa_regfile opnd_rf = |
4488 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4489 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4490 | { |
4491 | if ((insn->tok[i].X_op == O_register) | |
4492 | && (insn->tok[i].X_add_number == regnum)) | |
4493 | return TRUE; | |
4494 | } | |
4495 | } | |
4496 | } | |
4497 | return FALSE; | |
4498 | } | |
4499 | ||
4500 | ||
4501 | static bfd_boolean | |
7fa3d080 | 4502 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4503 | { |
4504 | xtensa_opcode opcode = tinsn->opcode; | |
4505 | ||
4506 | if (opcode == XTENSA_UNDEFINED) | |
4507 | return FALSE; | |
4508 | ||
4509 | if (opcode == xtensa_call0_opcode | |
4510 | || opcode == xtensa_callx0_opcode | |
4511 | || opcode == xtensa_call4_opcode | |
4512 | || opcode == xtensa_callx4_opcode | |
4513 | || opcode == xtensa_call8_opcode | |
4514 | || opcode == xtensa_callx8_opcode | |
4515 | || opcode == xtensa_call12_opcode | |
4516 | || opcode == xtensa_callx12_opcode | |
4517 | || opcode == xtensa_isync_opcode | |
4518 | || opcode == xtensa_ret_opcode | |
4519 | || opcode == xtensa_ret_n_opcode | |
4520 | || opcode == xtensa_retw_opcode | |
4521 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4522 | || opcode == xtensa_waiti_opcode |
4523 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4524 | return TRUE; |
c138bc38 | 4525 | |
e0001a05 NC |
4526 | return FALSE; |
4527 | } | |
4528 | ||
4529 | ||
4530 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4531 | This allows the debugger to add unaligned labels. | |
4532 | Also, the assembler generates stabs labels that need | |
4533 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4534 | ||
7fa3d080 BW |
4535 | static bfd_boolean |
4536 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4537 | { |
4538 | const char *name = S_GET_NAME (sym); | |
4539 | static size_t fake_size = 0; | |
4540 | ||
4541 | if (name | |
4542 | && name[0] == '.' | |
4543 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4544 | return TRUE; | |
4545 | ||
4546 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4547 | if (fake_size == 0) | |
4548 | fake_size = strlen (FAKE_LABEL_NAME); | |
4549 | ||
43cd72b9 | 4550 | if (name |
e0001a05 NC |
4551 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4552 | && (name[fake_size] == 'F' | |
4553 | || name[fake_size] == 'L' | |
4554 | || (name[fake_size] == 'e' | |
4555 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4556 | return TRUE; | |
4557 | ||
4558 | return FALSE; | |
4559 | } | |
4560 | ||
4561 | ||
7fa3d080 BW |
4562 | static fragS * |
4563 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4564 | { |
4565 | fragS *next_fragP = fragP->fr_next; | |
4566 | ||
c138bc38 | 4567 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4568 | So we have to skip until we find something legit. */ |
4569 | while (next_fragP && next_fragP->fr_fix == 0) | |
4570 | next_fragP = next_fragP->fr_next; | |
4571 | ||
4572 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4573 | return NULL; | |
4574 | ||
4575 | return next_fragP; | |
4576 | } | |
4577 | ||
4578 | ||
43cd72b9 | 4579 | static bfd_boolean |
7fa3d080 | 4580 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4581 | { |
4582 | xtensa_opcode out_opcode; | |
4583 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4584 | ||
4585 | if (next_fragP == NULL) | |
4586 | return FALSE; | |
4587 | ||
4588 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4589 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4590 | { | |
4591 | *opcode = out_opcode; | |
4592 | return TRUE; | |
4593 | } | |
4594 | return FALSE; | |
4595 | } | |
4596 | ||
4597 | ||
4598 | static int | |
7fa3d080 | 4599 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4600 | { |
e0001a05 NC |
4601 | static xtensa_insnbuf insnbuf = NULL; |
4602 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4603 | xtensa_format fmt; |
c138bc38 | 4604 | int fmt_size; |
e0001a05 NC |
4605 | |
4606 | if (!insnbuf) | |
4607 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4608 | ||
43cd72b9 BW |
4609 | if (fragP == NULL) |
4610 | return XTENSA_UNDEFINED; | |
4611 | ||
d77b99c9 BW |
4612 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4613 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4614 | |
4615 | fmt = xtensa_format_decode (isa, insnbuf); | |
4616 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4617 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4618 | fmt_size = xtensa_format_length (isa, fmt); |
4619 | ||
4620 | /* If the next format won't be changing due to relaxation, just | |
4621 | return the length of the first format. */ | |
4622 | if (fragP->fr_opcode != fragP->fr_literal) | |
4623 | return fmt_size; | |
4624 | ||
c138bc38 | 4625 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4626 | multi-slot instruction, we will return the more conservative |
4627 | number. This works because alignment on bigger instructions | |
4628 | is more restrictive than alignment on smaller instructions. | |
4629 | This is more conservative than we would like, but it happens | |
4630 | infrequently. */ | |
4631 | ||
4632 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4633 | return fmt_size; | |
4634 | ||
4635 | /* If we aren't doing one of our own relaxations or it isn't | |
4636 | slot-based, then the insn size won't change. */ | |
4637 | if (fragP->fr_type != rs_machine_dependent) | |
4638 | return fmt_size; | |
4639 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4640 | return fmt_size; | |
4641 | ||
4642 | /* If an instruction is about to grow, return the longer size. */ | |
4643 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4644 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4645 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4646 | { |
4647 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4648 | instruction in the relaxed version is of length 3. (The case | |
4649 | where we have to pull the instruction out of a FLIX bundle | |
4650 | is handled conservatively above.) However, frags with opcodes | |
4651 | that are expanding to wide branches end up having formats that | |
4652 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4653 | we can't tell directly what format the relaxer picked. This | |
4654 | is a wart in the design of the relaxer that should someday be | |
4655 | fixed, but would require major changes, or at least should | |
4656 | be accompanied by major changes to make use of that data. | |
4657 | ||
4658 | In any event, we can tell that we are expanding from a single-slot | |
19ef5f3d | 4659 | format to a wider one with the logic below. */ |
def13efb | 4660 | |
19ef5f3d SA |
4661 | int i; |
4662 | int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; | |
4663 | ||
4664 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) | |
4665 | { | |
4666 | if (relaxed_size == xtensa_format_length (isa, i)) | |
4667 | return relaxed_size; | |
4668 | } | |
4669 | ||
4670 | return 3; | |
def13efb | 4671 | } |
c138bc38 | 4672 | |
43cd72b9 BW |
4673 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4674 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4675 | |
43cd72b9 | 4676 | return fmt_size; |
e0001a05 NC |
4677 | } |
4678 | ||
4679 | ||
7fa3d080 BW |
4680 | static int |
4681 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4682 | { |
7fa3d080 BW |
4683 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4684 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4685 | } |
4686 | ||
4687 | ||
03aaa593 BW |
4688 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4689 | required two-byte instructions to be treated as three-byte instructions | |
4690 | for loop instruction alignment. This restriction was removed beginning | |
4691 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4692 | is that the first instruction of the loop must appear at an address that | |
4693 | does not cross a fetch boundary. */ | |
4694 | ||
4695 | static int | |
4696 | get_loop_align_size (int insn_size) | |
4697 | { | |
4698 | if (insn_size == XTENSA_UNDEFINED) | |
4699 | return xtensa_fetch_width; | |
4700 | ||
4701 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4702 | return 3; | |
4703 | ||
4704 | return insn_size; | |
4705 | } | |
4706 | ||
4707 | ||
e0001a05 NC |
4708 | /* If the next legit fragment is an end-of-loop marker, |
4709 | switch its state so it will instantiate a NOP. */ | |
4710 | ||
4711 | static void | |
1d19a770 | 4712 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4713 | { |
4714 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4715 | fragS *new_target = NULL; |
e0001a05 | 4716 | |
7b1cc377 | 4717 | if (align_targets) |
43cd72b9 BW |
4718 | { |
4719 | /* We are guaranteed there will be one of these... */ | |
4720 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4721 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4722 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4723 | next_fragP = next_fragP->fr_next; | |
4724 | ||
9c2799c2 | 4725 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4726 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4727 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4728 | ||
4729 | /* ...and one of these. */ | |
4730 | new_target = next_fragP->fr_next; | |
4731 | while (!(new_target->fr_type == rs_machine_dependent | |
4732 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4733 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4734 | new_target = new_target->fr_next; | |
4735 | ||
9c2799c2 | 4736 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4737 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4738 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4739 | } | |
43cd72b9 | 4740 | |
1d19a770 | 4741 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4742 | { |
1d19a770 BW |
4743 | if (next_fragP->fr_type == rs_machine_dependent |
4744 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4745 | { |
1d19a770 BW |
4746 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4747 | return; | |
e0001a05 | 4748 | } |
1d19a770 BW |
4749 | |
4750 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4751 | } |
4752 | } | |
4753 | ||
4754 | ||
4755 | static bfd_boolean | |
7fa3d080 | 4756 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4757 | { |
43cd72b9 | 4758 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4759 | so we have to skip until we find something legit. */ |
4760 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4761 | { | |
4762 | if (fragP->tc_frag_data.is_branch_target) | |
4763 | return TRUE; | |
4764 | if (fragP->fr_fix != 0) | |
4765 | break; | |
4766 | } | |
4767 | return FALSE; | |
4768 | } | |
4769 | ||
4770 | ||
4771 | static bfd_boolean | |
7fa3d080 | 4772 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4773 | { |
c138bc38 | 4774 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4775 | So we have to skip until we find something legit. */ |
4776 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4777 | { | |
4778 | if (fragP->tc_frag_data.is_loop_target) | |
4779 | return TRUE; | |
4780 | if (fragP->fr_fix != 0) | |
4781 | break; | |
4782 | } | |
4783 | return FALSE; | |
4784 | } | |
4785 | ||
4786 | ||
3a1e9c4a SA |
4787 | /* As specified in the relaxation table, when a loop instruction is |
4788 | relaxed, there are 24 bytes between the loop instruction itself and | |
4789 | the first instruction in the loop. */ | |
4790 | ||
4791 | #define RELAXED_LOOP_INSN_BYTES 24 | |
4792 | ||
e0001a05 | 4793 | static addressT |
7fa3d080 | 4794 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4795 | { |
4796 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4797 | xtensa_opcode next_opcode; |
e0001a05 | 4798 | |
43cd72b9 | 4799 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4800 | return 0; |
4801 | ||
43cd72b9 BW |
4802 | /* Sometimes an empty will end up here due to storage allocation issues, |
4803 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4804 | while (next_fragp->fr_fix == 0) |
4805 | next_fragp = next_fragp->fr_next; | |
4806 | ||
4807 | if (next_fragp->fr_type != rs_machine_dependent) | |
4808 | return 0; | |
4809 | ||
4810 | /* There is some implicit knowledge encoded in here. | |
4811 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4812 | been relaxed. Note that we can assume that the LOOP |
4813 | instruction is in slot 0 because loops aren't bundleable. */ | |
4814 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
3a1e9c4a | 4815 | return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; |
e0001a05 NC |
4816 | |
4817 | return 0; | |
4818 | } | |
4819 | ||
4820 | ||
4821 | /* Mark a location where we can later insert literal frags. Update | |
4822 | the section's literal_pool_loc, so subsequent literals can be | |
4823 | placed nearest to their use. */ | |
4824 | ||
4825 | static void | |
7fa3d080 | 4826 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4827 | { |
4828 | /* Any labels pointing to the current location need | |
4829 | to be adjusted to after the literal pool. */ | |
e0001a05 | 4830 | fragS *pool_location; |
e0001a05 | 4831 | |
1f2a7e38 | 4832 | if (use_literal_section) |
43cd72b9 BW |
4833 | return; |
4834 | ||
dd49a749 BW |
4835 | /* We stash info in these frags so we can later move the literal's |
4836 | fixes into this frchain's fix list. */ | |
e0001a05 | 4837 | pool_location = frag_now; |
dd49a749 | 4838 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4839 | frag_now->tc_frag_data.literal_frag = frag_now; |
b46824bd MF |
4840 | /* Just record this frag. */ |
4841 | xtensa_maybe_create_literal_pool_frag (FALSE, FALSE); | |
dd49a749 | 4842 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4843 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4844 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4845 | frag_now->tc_frag_data.lit_seg = now_seg; |
4846 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4847 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4848 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 4849 | |
e0001a05 | 4850 | set_literal_pool_location (now_seg, pool_location); |
e0001a05 NC |
4851 | } |
4852 | ||
4853 | ||
43cd72b9 BW |
4854 | /* Build a nop of the correct size into tinsn. */ |
4855 | ||
4856 | static void | |
7fa3d080 | 4857 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4858 | { |
4859 | tinsn_init (tinsn); | |
4860 | switch (size) | |
4861 | { | |
4862 | case 2: | |
4863 | tinsn->opcode = xtensa_nop_n_opcode; | |
4864 | tinsn->ntok = 0; | |
4865 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4866 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4867 | break; | |
4868 | ||
4869 | case 3: | |
4870 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4871 | { | |
4872 | tinsn->opcode = xtensa_or_opcode; | |
4873 | set_expr_const (&tinsn->tok[0], 1); | |
4874 | set_expr_const (&tinsn->tok[1], 1); | |
4875 | set_expr_const (&tinsn->tok[2], 1); | |
4876 | tinsn->ntok = 3; | |
4877 | } | |
4878 | else | |
4879 | tinsn->opcode = xtensa_nop_opcode; | |
4880 | ||
9c2799c2 | 4881 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4882 | } |
4883 | } | |
4884 | ||
4885 | ||
e0001a05 NC |
4886 | /* Assemble a NOP of the requested size in the buffer. User must have |
4887 | allocated "buf" with at least "size" bytes. */ | |
4888 | ||
7fa3d080 | 4889 | static void |
d77b99c9 | 4890 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4891 | { |
4892 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4893 | TInsn tinsn; |
e0001a05 | 4894 | |
43cd72b9 | 4895 | build_nop (&tinsn, size); |
e0001a05 | 4896 | |
43cd72b9 BW |
4897 | if (!insnbuf) |
4898 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4899 | |
43cd72b9 | 4900 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4901 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4902 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4903 | } |
4904 | ||
4905 | ||
4906 | /* Return the number of bytes for the offset of the expanded loop | |
4907 | instruction. This should be incorporated into the relaxation | |
4908 | specification but is hard-coded here. This is used to auto-align | |
4909 | the loop instruction. It is invalid to call this function if the | |
4910 | configuration does not have loops or if the opcode is not a loop | |
4911 | opcode. */ | |
4912 | ||
4913 | static addressT | |
7fa3d080 | 4914 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4915 | { |
4916 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4917 | This MUST correspond directly to the specification of the loop | |
4918 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4919 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4920 | if (opcode == xtensa_loop_opcode) |
4921 | return 0; | |
4922 | if (opcode == xtensa_loopnez_opcode) | |
4923 | return 3; | |
4924 | if (opcode == xtensa_loopgtz_opcode) | |
4925 | return 6; | |
4926 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4927 | return 0; | |
4928 | } | |
4929 | ||
4930 | ||
7fa3d080 BW |
4931 | static fragS * |
4932 | get_literal_pool_location (segT seg) | |
e0001a05 | 4933 | { |
f8aecf3c | 4934 | if (auto_litpools) |
b46824bd | 4935 | { |
f8aecf3c MF |
4936 | struct litpool_seg *lps = litpool_seg_list.next; |
4937 | struct litpool_frag *lpf; | |
4938 | for ( ; lps && lps->seg->id != seg->id; lps = lps->next) | |
4939 | ; | |
4940 | if (lps) | |
b46824bd | 4941 | { |
f8aecf3c MF |
4942 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) |
4943 | { /* Skip "candidates" for now. */ | |
4944 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
4945 | lpf->priority == 1) | |
4946 | return lpf->fragP; | |
4947 | } | |
4948 | /* Must convert a lower-priority pool. */ | |
4949 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4950 | { | |
4951 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
4952 | return lpf->fragP; | |
4953 | } | |
4954 | /* Still no match -- try for a low priority pool. */ | |
4955 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4956 | { | |
4957 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
4958 | return lpf->fragP; | |
4959 | } | |
b46824bd MF |
4960 | } |
4961 | } | |
e0001a05 NC |
4962 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; |
4963 | } | |
4964 | ||
4965 | ||
4966 | static void | |
7fa3d080 | 4967 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4968 | { |
4969 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4970 | } | |
4971 | ||
43cd72b9 BW |
4972 | |
4973 | /* Set frag assembly state should be called when a new frag is | |
4974 | opened and after a frag has been closed. */ | |
4975 | ||
7fa3d080 BW |
4976 | static void |
4977 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4978 | { |
4979 | if (!density_supported) | |
4980 | fragP->tc_frag_data.is_no_density = TRUE; | |
4981 | ||
4982 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4983 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4984 | "use_schedule" here. */ |
4985 | if (!directive_state[directive_transform]) | |
4986 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4987 | if (directive_state[directive_longcalls]) |
4988 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4989 | fragP->tc_frag_data.use_absolute_literals = |
4990 | directive_state[directive_absolute_literals]; | |
4991 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4992 | } | |
4993 | ||
4994 | ||
7fa3d080 BW |
4995 | static bfd_boolean |
4996 | relaxable_section (asection *sec) | |
43cd72b9 | 4997 | { |
11ac2671 BW |
4998 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4999 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
5000 | } |
5001 | ||
5002 | ||
99ded152 BW |
5003 | static void |
5004 | xtensa_mark_frags_for_org (void) | |
5005 | { | |
5006 | segT *seclist; | |
5007 | ||
5008 | /* Walk over each fragment of all of the current segments. If we find | |
5009 | a .org frag in any of the segments, mark all frags prior to it as | |
5010 | "no transform", which will prevent linker optimizations from messing | |
5011 | up the .org distance. This should be done after | |
5012 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
5013 | about that function trashing the data we save here. */ | |
5014 | ||
5015 | for (seclist = &stdoutput->sections; | |
5016 | seclist && *seclist; | |
5017 | seclist = &(*seclist)->next) | |
5018 | { | |
5019 | segT sec = *seclist; | |
5020 | segment_info_type *seginfo; | |
5021 | fragS *fragP; | |
5022 | flagword flags; | |
fd361982 | 5023 | flags = bfd_section_flags (sec); |
99ded152 BW |
5024 | if (flags & SEC_DEBUGGING) |
5025 | continue; | |
5026 | if (!(flags & SEC_ALLOC)) | |
5027 | continue; | |
5028 | ||
5029 | seginfo = seg_info (sec); | |
5030 | if (seginfo && seginfo->frchainP) | |
5031 | { | |
5032 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
5033 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5034 | fragP = fragP->fr_next) | |
5035 | { | |
5036 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
5037 | rs_fill, so use the value as cached in rs_subtype here. */ | |
5038 | if (fragP->fr_subtype == RELAX_ORG) | |
5039 | { | |
5040 | while (last_fragP != fragP->fr_next) | |
5041 | { | |
5042 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
5043 | last_fragP = last_fragP->fr_next; | |
5044 | } | |
5045 | } | |
5046 | } | |
5047 | } | |
5048 | } | |
5049 | } | |
5050 | ||
5051 | ||
43cd72b9 | 5052 | static void |
7fa3d080 | 5053 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
5054 | { |
5055 | segT *seclist; | |
5056 | ||
5057 | /* Walk over each fragment of all of the current segments. For each | |
5058 | unmarked fragment, mark it with the same info as the previous | |
5059 | fragment. */ | |
5060 | for (seclist = &stdoutput->sections; | |
5061 | seclist && *seclist; | |
5062 | seclist = &(*seclist)->next) | |
5063 | { | |
5064 | segT sec = *seclist; | |
5065 | segment_info_type *seginfo; | |
5066 | fragS *fragP; | |
5067 | flagword flags; | |
fd361982 | 5068 | flags = bfd_section_flags (sec); |
43cd72b9 BW |
5069 | if (flags & SEC_DEBUGGING) |
5070 | continue; | |
5071 | if (!(flags & SEC_ALLOC)) | |
5072 | continue; | |
5073 | ||
5074 | seginfo = seg_info (sec); | |
5075 | if (seginfo && seginfo->frchainP) | |
5076 | { | |
5077 | fragS *last_fragP = 0; | |
5078 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5079 | fragP = fragP->fr_next) | |
5080 | { | |
5081 | if (fragP->fr_fix != 0 | |
5082 | && !fragP->tc_frag_data.is_assembly_state_set) | |
5083 | { | |
5084 | if (last_fragP == 0) | |
5085 | { | |
5086 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
5087 | _("assembly state not set for first frag in section %s"), | |
5088 | sec->name); | |
5089 | } | |
5090 | else | |
5091 | { | |
5092 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
5093 | fragP->tc_frag_data.is_no_density = | |
5094 | last_fragP->tc_frag_data.is_no_density; | |
5095 | fragP->tc_frag_data.is_no_transform = | |
5096 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
5097 | fragP->tc_frag_data.use_longcalls = |
5098 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
5099 | fragP->tc_frag_data.use_absolute_literals = |
5100 | last_fragP->tc_frag_data.use_absolute_literals; | |
5101 | } | |
5102 | } | |
5103 | if (fragP->tc_frag_data.is_assembly_state_set) | |
5104 | last_fragP = fragP; | |
5105 | } | |
5106 | } | |
5107 | } | |
5108 | } | |
5109 | ||
5110 | ||
5111 | static void | |
7fa3d080 BW |
5112 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
5113 | asection *sec, | |
5114 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 | 5115 | { |
fd361982 | 5116 | flagword flags = bfd_section_flags (sec); |
43cd72b9 BW |
5117 | segment_info_type *seginfo = seg_info (sec); |
5118 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 5119 | |
43cd72b9 | 5120 | if (flags & SEC_CODE) |
c138bc38 | 5121 | { |
43cd72b9 BW |
5122 | xtensa_isa isa = xtensa_default_isa; |
5123 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
5124 | while (frag != NULL) | |
5125 | { | |
5126 | if (frag->tc_frag_data.is_branch_target) | |
5127 | { | |
5128 | int op_size; | |
664df4e4 | 5129 | addressT branch_align, frag_addr; |
43cd72b9 BW |
5130 | xtensa_format fmt; |
5131 | ||
d77b99c9 BW |
5132 | xtensa_insnbuf_from_chars |
5133 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5134 | fmt = xtensa_format_decode (isa, insnbuf); |
5135 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
5136 | branch_align = 1 << branch_align_power (sec); |
5137 | frag_addr = frag->fr_address % branch_align; | |
5138 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
5139 | as_warn_where (frag->fr_file, frag->fr_line, |
5140 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 5141 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5142 | } |
5143 | frag = frag->fr_next; | |
5144 | } | |
5145 | xtensa_insnbuf_free (isa, insnbuf); | |
5146 | } | |
5147 | } | |
5148 | ||
5149 | ||
5150 | static void | |
7fa3d080 BW |
5151 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
5152 | asection *sec, | |
5153 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 | 5154 | { |
fd361982 | 5155 | flagword flags = bfd_section_flags (sec); |
43cd72b9 BW |
5156 | segment_info_type *seginfo = seg_info (sec); |
5157 | fragS *frag = seginfo->frchainP->frch_root; | |
5158 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 5159 | |
43cd72b9 | 5160 | if (flags & SEC_CODE) |
c138bc38 | 5161 | { |
43cd72b9 BW |
5162 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
5163 | while (frag != NULL) | |
5164 | { | |
5165 | if (frag->tc_frag_data.is_first_loop_insn) | |
5166 | { | |
5167 | int op_size; | |
d77b99c9 | 5168 | addressT frag_addr; |
43cd72b9 BW |
5169 | xtensa_format fmt; |
5170 | ||
3c83b96e SA |
5171 | if (frag->fr_fix == 0) |
5172 | frag = next_non_empty_frag (frag); | |
3739860c | 5173 | |
3c83b96e SA |
5174 | if (frag) |
5175 | { | |
5176 | xtensa_insnbuf_from_chars | |
5177 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
5178 | fmt = xtensa_format_decode (isa, insnbuf); | |
5179 | op_size = xtensa_format_length (isa, fmt); | |
5180 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
3739860c | 5181 | |
3c83b96e SA |
5182 | if (frag_addr + op_size > xtensa_fetch_width) |
5183 | as_warn_where (frag->fr_file, frag->fr_line, | |
5184 | _("unaligned loop: %d bytes at 0x%lx"), | |
5185 | op_size, (long) frag->fr_address); | |
5186 | } | |
43cd72b9 BW |
5187 | } |
5188 | frag = frag->fr_next; | |
5189 | } | |
5190 | xtensa_insnbuf_free (isa, insnbuf); | |
5191 | } | |
5192 | } | |
5193 | ||
5194 | ||
30f725a1 BW |
5195 | static int |
5196 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5197 | { |
5198 | xtensa_isa isa = xtensa_default_isa; | |
5199 | static xtensa_insnbuf insnbuf = NULL; | |
5200 | static xtensa_insnbuf slotbuf = NULL; | |
5201 | xtensa_format fmt; | |
5202 | int slot; | |
5203 | bfd_boolean alt_reloc; | |
5204 | xtensa_opcode opcode; | |
5205 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5206 | ||
1b6e95c2 BW |
5207 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5208 | || alt_reloc) | |
43cd72b9 BW |
5209 | as_fatal (_("unexpected fix")); |
5210 | ||
5211 | if (!insnbuf) | |
5212 | { | |
5213 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5214 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5215 | } | |
5216 | ||
d77b99c9 | 5217 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5218 | fmt = xtensa_format_decode (isa, insnbuf); |
5219 | if (fmt == XTENSA_UNDEFINED) | |
5220 | as_fatal (_("undecodable fix")); | |
5221 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5222 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5223 | if (opcode == XTENSA_UNDEFINED) | |
5224 | as_fatal (_("undecodable fix")); | |
5225 | ||
5226 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5227 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5228 | of a CONST16 operand. */ |
43cd72b9 | 5229 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5230 | return 0; |
43cd72b9 BW |
5231 | |
5232 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5233 | get_relaxable_immed (opcode), val, | |
5234 | fixP->fx_file, fixP->fx_line); | |
5235 | ||
5236 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5237 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5238 | |
5239 | return 1; | |
43cd72b9 BW |
5240 | } |
5241 | ||
e0001a05 NC |
5242 | \f |
5243 | /* External Functions and Other GAS Hooks. */ | |
5244 | ||
5245 | const char * | |
7fa3d080 | 5246 | xtensa_target_format (void) |
e0001a05 NC |
5247 | { |
5248 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5249 | } | |
5250 | ||
5251 | ||
5252 | void | |
7fa3d080 | 5253 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5254 | { |
5255 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5256 | } | |
5257 | ||
5258 | ||
5259 | void | |
7fa3d080 | 5260 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5261 | { |
5262 | if (target_big_endian) | |
5263 | number_to_chars_bigendian (buf, val, n); | |
5264 | else | |
5265 | number_to_chars_littleendian (buf, val, n); | |
5266 | } | |
5267 | ||
f7e16c2a MF |
5268 | static void |
5269 | xg_init_global_config (void) | |
5270 | { | |
5271 | target_big_endian = XCHAL_HAVE_BE; | |
5272 | ||
5273 | density_supported = XCHAL_HAVE_DENSITY; | |
5274 | absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; | |
5275 | xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; | |
5276 | ||
5277 | directive_state[directive_density] = XCHAL_HAVE_DENSITY; | |
5278 | directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS; | |
935f1f4b MF |
5279 | |
5280 | microarch_earliest = XTENSA_MARCH_EARLIEST; | |
f7e16c2a MF |
5281 | } |
5282 | ||
5283 | void | |
5284 | xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) | |
5285 | { | |
5286 | xg_init_global_config (); | |
5287 | } | |
e0001a05 NC |
5288 | |
5289 | /* This function is called once, at assembler startup time. It should | |
5290 | set up all the tables, etc. that the MD part of the assembler will | |
5291 | need. */ | |
5292 | ||
5293 | void | |
7fa3d080 | 5294 | md_begin (void) |
e0001a05 NC |
5295 | { |
5296 | segT current_section = now_seg; | |
5297 | int current_subsec = now_subseg; | |
5298 | xtensa_isa isa; | |
62af60e2 | 5299 | int i; |
e0001a05 | 5300 | |
43cd72b9 | 5301 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5302 | isa = xtensa_default_isa; |
e0001a05 | 5303 | |
9632a526 | 5304 | linkrelax = opt_linkrelax; |
43cd72b9 | 5305 | |
74869ac7 | 5306 | /* Set up the literal sections. */ |
e0001a05 | 5307 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5308 | |
5309 | subseg_set (current_section, current_subsec); | |
5310 | ||
5311 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5312 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5313 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5314 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5315 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5316 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5317 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5318 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5319 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5320 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5321 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5322 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5323 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5324 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5325 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5326 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5327 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5328 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5329 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5330 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5331 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5332 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5333 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5334 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5335 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5336 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5337 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5338 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5339 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5340 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5341 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5342 | |
3739860c | 5343 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
62af60e2 SA |
5344 | { |
5345 | int format_slots = xtensa_format_num_slots (isa, i); | |
5346 | if (format_slots > config_max_slots) | |
5347 | config_max_slots = format_slots; | |
5348 | } | |
5349 | ||
5350 | xg_init_vinsn (&cur_vinsn); | |
5351 | ||
77cba8a3 BW |
5352 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5353 | ||
43cd72b9 BW |
5354 | init_op_placement_info_table (); |
5355 | ||
5356 | /* Set up the assembly state. */ | |
5357 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5358 | xtensa_set_frag_assembly_state (frag_now); | |
54879176 MF |
5359 | |
5360 | if (!use_literal_section) | |
5361 | xtensa_mark_literal_pool_location (); | |
43cd72b9 BW |
5362 | } |
5363 | ||
5364 | ||
5365 | /* TC_INIT_FIX_DATA hook */ | |
5366 | ||
5367 | void | |
7fa3d080 | 5368 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5369 | { |
5370 | x->tc_fix_data.slot = 0; | |
5371 | x->tc_fix_data.X_add_symbol = NULL; | |
5372 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5373 | } |
5374 | ||
5375 | ||
5376 | /* tc_frob_label hook */ | |
5377 | ||
5378 | void | |
7fa3d080 | 5379 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5380 | { |
3ea38ac2 BW |
5381 | float freq; |
5382 | ||
5383 | if (cur_vinsn.inside_bundle) | |
5384 | { | |
5385 | as_bad (_("labels are not valid inside bundles")); | |
5386 | return; | |
5387 | } | |
5388 | ||
5389 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5390 | |
43cd72b9 BW |
5391 | /* Since the label was already attached to a frag associated with the |
5392 | previous basic block, it now needs to be reset to the current frag. */ | |
5393 | symbol_set_frag (sym, frag_now); | |
5394 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5395 | ||
82e7541d BW |
5396 | if (generating_literals) |
5397 | xtensa_add_literal_sym (sym); | |
5398 | else | |
5399 | xtensa_add_insn_label (sym); | |
5400 | ||
7b1cc377 BW |
5401 | if (symbol_get_tc (sym)->is_loop_target) |
5402 | { | |
5403 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5404 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5405 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5406 | ||
5407 | xtensa_set_frag_assembly_state (frag_now); | |
5408 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5409 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5410 | ||
5411 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5412 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5413 | } |
e0001a05 NC |
5414 | |
5415 | /* No target aligning in the absolute section. */ | |
61846f28 | 5416 | if (now_seg != absolute_section |
61846f28 | 5417 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5418 | && !generating_literals) |
5419 | { | |
43cd72b9 BW |
5420 | xtensa_set_frag_assembly_state (frag_now); |
5421 | ||
b7afdeef SA |
5422 | if (do_align_targets ()) |
5423 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5424 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5425 | frag_now->fr_offset, NULL); | |
5426 | else | |
5427 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5428 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5429 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5430 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5431 | } |
5432 | ||
5433 | /* We need to mark the following properties even if we aren't aligning. */ | |
5434 | ||
5435 | /* If the label is already known to be a branch target, i.e., a | |
5436 | forward branch, mark the frag accordingly. Backward branches | |
5437 | are handled by xg_add_branch_and_loop_targets. */ | |
5438 | if (symbol_get_tc (sym)->is_branch_target) | |
5439 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5440 | ||
5441 | /* Loops only go forward, so they can be identified here. */ | |
5442 | if (symbol_get_tc (sym)->is_loop_target) | |
5443 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5444 | |
5445 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5446 | } |
5447 | ||
5448 | ||
5449 | /* tc_unrecognized_line hook */ | |
5450 | ||
5451 | int | |
7fa3d080 | 5452 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5453 | { |
5454 | switch (ch) | |
5455 | { | |
5456 | case '{' : | |
5457 | if (cur_vinsn.inside_bundle == 0) | |
5458 | { | |
5459 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5460 | when using --gstabs. Temporarily disable debug info. */ | |
5461 | generate_lineno_debug (); | |
5462 | if (debug_type == DEBUG_STABS) | |
5463 | { | |
5464 | xt_saved_debug_type = debug_type; | |
5465 | debug_type = DEBUG_NONE; | |
5466 | } | |
82e7541d | 5467 | |
43cd72b9 BW |
5468 | cur_vinsn.inside_bundle = 1; |
5469 | } | |
5470 | else | |
5471 | { | |
5472 | as_bad (_("extra opening brace")); | |
5473 | return 0; | |
5474 | } | |
5475 | break; | |
82e7541d | 5476 | |
43cd72b9 BW |
5477 | case '}' : |
5478 | if (cur_vinsn.inside_bundle) | |
5479 | finish_vinsn (&cur_vinsn); | |
5480 | else | |
5481 | { | |
5482 | as_bad (_("extra closing brace")); | |
5483 | return 0; | |
5484 | } | |
5485 | break; | |
5486 | default: | |
5487 | as_bad (_("syntax error")); | |
5488 | return 0; | |
e0001a05 | 5489 | } |
43cd72b9 | 5490 | return 1; |
e0001a05 NC |
5491 | } |
5492 | ||
5493 | ||
5494 | /* md_flush_pending_output hook */ | |
5495 | ||
5496 | void | |
7fa3d080 | 5497 | xtensa_flush_pending_output (void) |
e0001a05 | 5498 | { |
a3582eee BW |
5499 | /* This line fixes a bug where automatically generated gstabs info |
5500 | separates a function label from its entry instruction, ending up | |
5501 | with the literal position between the function label and the entry | |
5502 | instruction and crashing code. It only happens with --gstabs and | |
5503 | --text-section-literals, and when several other obscure relaxation | |
5504 | conditions are met. */ | |
5505 | if (outputting_stabs_line_debug) | |
5506 | return; | |
5507 | ||
43cd72b9 BW |
5508 | if (cur_vinsn.inside_bundle) |
5509 | as_bad (_("missing closing brace")); | |
5510 | ||
e0001a05 NC |
5511 | /* If there is a non-zero instruction fragment, close it. */ |
5512 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5513 | { | |
5514 | frag_wane (frag_now); | |
5515 | frag_new (0); | |
43cd72b9 | 5516 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5517 | } |
5518 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5519 | |
5520 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5521 | } |
5522 | ||
5523 | ||
43cd72b9 BW |
5524 | /* We had an error while parsing an instruction. The string might look |
5525 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5526 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5527 | and the num_slots field will grow past the end of the array of slots, | |
5528 | and bad things happen. */ | |
5529 | ||
5530 | static void | |
7fa3d080 | 5531 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5532 | { |
5533 | if (cur_vinsn.inside_bundle) | |
5534 | { | |
5535 | if (*input_line_pointer == '}' | |
5536 | || *(input_line_pointer - 1) == '}' | |
5537 | || *(input_line_pointer - 2) == '}') | |
5538 | xg_clear_vinsn (&cur_vinsn); | |
5539 | } | |
5540 | } | |
5541 | ||
5542 | ||
e0001a05 | 5543 | void |
7fa3d080 | 5544 | md_assemble (char *str) |
e0001a05 NC |
5545 | { |
5546 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5547 | char *opname; |
e0001a05 NC |
5548 | unsigned opnamelen; |
5549 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5550 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5551 | int num_args; |
e0001a05 | 5552 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5553 | |
e0001a05 NC |
5554 | tinsn_init (&orig_insn); |
5555 | ||
5556 | /* Split off the opcode. */ | |
5557 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
4ec9d7d5 | 5558 | opname = xstrndup (str, opnamelen); |
e0001a05 NC |
5559 | |
5560 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5561 | if (num_args == -1) | |
5562 | { | |
5563 | as_bad (_("syntax error")); | |
5564 | return; | |
5565 | } | |
5566 | ||
5567 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5568 | return; | |
5569 | ||
5570 | /* Check for an underbar prefix. */ | |
5571 | if (*opname == '_') | |
5572 | { | |
5573 | has_underbar = TRUE; | |
5574 | opname += 1; | |
5575 | } | |
5576 | ||
5577 | orig_insn.insn_type = ITYPE_INSN; | |
5578 | orig_insn.ntok = 0; | |
43cd72b9 | 5579 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5580 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 | 5581 | |
2b0f3761 | 5582 | /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its |
28dbbc02 BW |
5583 | extra argument and set the opcode to "CALLXn". */ |
5584 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5585 | && strncasecmp (opname, "callx", 5) == 0) | |
5586 | { | |
5587 | unsigned long window_size; | |
5588 | char *suffix; | |
5589 | ||
5590 | window_size = strtoul (opname + 5, &suffix, 10); | |
5591 | if (suffix != opname + 5 | |
5592 | && (window_size == 0 | |
5593 | || window_size == 4 | |
5594 | || window_size == 8 | |
5595 | || window_size == 12) | |
5596 | && strcasecmp (suffix, ".tls") == 0) | |
5597 | { | |
5598 | switch (window_size) | |
5599 | { | |
5600 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5601 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5602 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5603 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5604 | } | |
5605 | ||
5606 | if (num_args != 2) | |
5607 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5608 | else | |
5609 | { | |
5610 | bfd_reloc_code_real_type reloc; | |
5611 | char *old_input_line_pointer; | |
19e8f41a | 5612 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5613 | |
5614 | old_input_line_pointer = input_line_pointer; | |
5615 | input_line_pointer = arg_strings[num_args - 1]; | |
5616 | ||
87975d2a | 5617 | expression (tok); |
28dbbc02 BW |
5618 | if (tok->X_op == O_symbol |
5619 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5620 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5621 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5622 | else | |
5623 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5624 | ||
5625 | input_line_pointer = old_input_line_pointer; | |
5626 | num_args -= 1; | |
5627 | } | |
5628 | } | |
5629 | } | |
5630 | ||
2b0f3761 | 5631 | /* Special case: Check for "j.l" pseudo op. */ |
19e8f41a BW |
5632 | if (orig_insn.opcode == XTENSA_UNDEFINED |
5633 | && strncasecmp (opname, "j.l", 3) == 0) | |
5634 | { | |
5635 | if (num_args != 2) | |
5636 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5637 | else | |
5638 | { | |
5639 | char *old_input_line_pointer; | |
5640 | expressionS *tok = &orig_insn.extra_arg; | |
5641 | ||
5642 | old_input_line_pointer = input_line_pointer; | |
5643 | input_line_pointer = arg_strings[num_args - 1]; | |
5644 | ||
5645 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5646 | input_line_pointer = old_input_line_pointer; | |
5647 | ||
5648 | num_args -= 1; | |
5649 | orig_insn.opcode = xtensa_j_opcode; | |
5650 | } | |
5651 | } | |
5652 | ||
e0001a05 NC |
5653 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5654 | { | |
43cd72b9 BW |
5655 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5656 | if (fmt == XTENSA_UNDEFINED) | |
5657 | { | |
5658 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5659 | error_reset_cur_vinsn (); | |
5660 | return; | |
5661 | } | |
5662 | if (!cur_vinsn.inside_bundle) | |
5663 | { | |
5664 | as_bad (_("format names only valid inside bundles")); | |
5665 | error_reset_cur_vinsn (); | |
5666 | return; | |
5667 | } | |
5668 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5669 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5670 | opname); | |
5671 | cur_vinsn.format = fmt; | |
5672 | free (has_underbar ? opname - 1 : opname); | |
5673 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5674 | return; |
5675 | } | |
5676 | ||
e0001a05 NC |
5677 | /* Parse the arguments. */ |
5678 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5679 | { | |
5680 | as_bad (_("syntax error")); | |
43cd72b9 | 5681 | error_reset_cur_vinsn (); |
e0001a05 NC |
5682 | return; |
5683 | } | |
5684 | ||
5685 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5686 | free (has_underbar ? opname - 1 : opname); | |
5687 | opname = 0; | |
5688 | while (num_args-- > 0) | |
5689 | free (arg_strings[num_args]); | |
5690 | ||
43cd72b9 BW |
5691 | /* Get expressions for invisible operands. */ |
5692 | if (get_invisible_operands (&orig_insn)) | |
5693 | { | |
5694 | error_reset_cur_vinsn (); | |
5695 | return; | |
5696 | } | |
5697 | ||
e0001a05 NC |
5698 | /* Check for the right number and type of arguments. */ |
5699 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5700 | { |
43cd72b9 BW |
5701 | error_reset_cur_vinsn (); |
5702 | return; | |
e0001a05 NC |
5703 | } |
5704 | ||
b224e962 BW |
5705 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5706 | spread across multiple input lines and individual instructions may be | |
5707 | moved around in some cases. */ | |
5708 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5709 | dwarf2_where (&orig_insn.debug_line); | |
5710 | dwarf2_consume_line_info (); | |
c138bc38 | 5711 | |
43cd72b9 BW |
5712 | xg_add_branch_and_loop_targets (&orig_insn); |
5713 | ||
431ad2d0 BW |
5714 | /* Check that immediate value for ENTRY is >= 16. */ |
5715 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5716 | { |
431ad2d0 BW |
5717 | expressionS *exp = &orig_insn.tok[2]; |
5718 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5719 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5720 | } |
5721 | ||
e0001a05 | 5722 | /* Finish it off: |
43cd72b9 BW |
5723 | assemble_tokens (opcode, tok, ntok); |
5724 | expand the tokens from the orig_insn into the | |
5725 | stack of instructions that will not expand | |
e0001a05 | 5726 | unless required at relaxation time. */ |
e0001a05 | 5727 | |
43cd72b9 BW |
5728 | if (!cur_vinsn.inside_bundle) |
5729 | emit_single_op (&orig_insn); | |
5730 | else /* We are inside a bundle. */ | |
e0001a05 | 5731 | { |
43cd72b9 BW |
5732 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5733 | cur_vinsn.num_slots++; | |
5734 | if (*input_line_pointer == '}' | |
5735 | || *(input_line_pointer - 1) == '}' | |
5736 | || *(input_line_pointer - 2) == '}') | |
5737 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5738 | } |
5739 | ||
43cd72b9 BW |
5740 | /* We've just emitted a new instruction so clear the list of labels. */ |
5741 | xtensa_clear_insn_labels (); | |
a82c7d90 DW |
5742 | |
5743 | xtensa_check_frag_count (); | |
e0001a05 NC |
5744 | } |
5745 | ||
5746 | ||
43cd72b9 | 5747 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5748 | |
43cd72b9 BW |
5749 | /* For a .align directive, we mark the previous block with the alignment |
5750 | information. This will be placed in the object file in the | |
5751 | property section corresponding to this section. */ | |
e0001a05 | 5752 | |
43cd72b9 | 5753 | void |
7fa3d080 | 5754 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5755 | { |
5756 | if (linkrelax | |
b08b5071 | 5757 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5758 | && (fragP->fr_type == rs_align |
5759 | || fragP->fr_type == rs_align_code) | |
43cd72b9 BW |
5760 | && fragP->fr_offset > 0 |
5761 | && now_seg != bss_section) | |
e0001a05 | 5762 | { |
43cd72b9 BW |
5763 | fragP->tc_frag_data.is_align = TRUE; |
5764 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5765 | } |
5766 | ||
43cd72b9 | 5767 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5768 | { |
43cd72b9 BW |
5769 | int count; |
5770 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5771 | if (count != 0) | |
c138bc38 | 5772 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5773 | _("unaligned entry instruction")); |
e0001a05 | 5774 | } |
99ded152 BW |
5775 | |
5776 | if (linkrelax && fragP->fr_type == rs_org) | |
5777 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5778 | } |
43cd72b9 | 5779 | |
e0001a05 NC |
5780 | |
5781 | /* TC_FRAG_INIT hook */ | |
5782 | ||
5783 | void | |
7fa3d080 | 5784 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5785 | { |
43cd72b9 | 5786 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5787 | } |
5788 | ||
5789 | ||
5790 | symbolS * | |
7fa3d080 | 5791 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5792 | { |
5793 | return NULL; | |
5794 | } | |
5795 | ||
5796 | ||
5797 | /* Round up a section size to the appropriate boundary. */ | |
5798 | ||
5799 | valueT | |
7fa3d080 | 5800 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5801 | { |
5802 | return size; /* Byte alignment is fine. */ | |
5803 | } | |
5804 | ||
5805 | ||
5806 | long | |
7fa3d080 | 5807 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5808 | { |
5809 | char *insn_p; | |
5810 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5811 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5812 | int opnum; |
43cd72b9 | 5813 | uint32 opnd_value; |
e0001a05 | 5814 | xtensa_opcode opcode; |
43cd72b9 BW |
5815 | xtensa_format fmt; |
5816 | int slot; | |
e0001a05 NC |
5817 | xtensa_isa isa = xtensa_default_isa; |
5818 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5819 | bfd_boolean alt_reloc; |
e0001a05 | 5820 | |
e0001a05 | 5821 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5822 | return 0; |
e0001a05 | 5823 | |
1bbb5f21 BW |
5824 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5825 | return addr; | |
5826 | ||
e0001a05 | 5827 | if (!insnbuf) |
43cd72b9 BW |
5828 | { |
5829 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5830 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5831 | } | |
e0001a05 NC |
5832 | |
5833 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5834 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5835 | fmt = xtensa_format_decode (isa, insnbuf); |
5836 | ||
5837 | if (fmt == XTENSA_UNDEFINED) | |
5838 | as_fatal (_("bad instruction format")); | |
5839 | ||
5840 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5841 | as_fatal (_("invalid relocation")); | |
5842 | ||
5843 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5844 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5845 | ||
30f725a1 BW |
5846 | /* Check for "alternate" relocations (operand not specified). None |
5847 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5848 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5849 | { | |
5850 | if (opcode != xtensa_l32r_opcode | |
5851 | && opcode != xtensa_const16_opcode) | |
5852 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5853 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5854 | return 0; |
e0001a05 NC |
5855 | } |
5856 | ||
43cd72b9 BW |
5857 | opnum = get_relaxable_immed (opcode); |
5858 | opnd_value = 0; | |
5859 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5860 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5861 | { |
5862 | as_bad_where (fixP->fx_file, | |
5863 | fixP->fx_line, | |
5864 | _("invalid relocation for operand %d of '%s'"), | |
5865 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5866 | return 0; |
e0001a05 | 5867 | } |
43cd72b9 BW |
5868 | return 0 - opnd_value; |
5869 | } | |
5870 | ||
5871 | ||
5872 | /* TC_FORCE_RELOCATION hook */ | |
5873 | ||
5874 | int | |
7fa3d080 | 5875 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5876 | { |
5877 | switch (fix->fx_r_type) | |
30f725a1 BW |
5878 | { |
5879 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5880 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5881 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5882 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5883 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5884 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5885 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5886 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5887 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5888 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5889 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5890 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5891 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5892 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5893 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5894 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5895 | return 1; |
5896 | default: | |
5897 | break; | |
e0001a05 NC |
5898 | } |
5899 | ||
43cd72b9 BW |
5900 | if (linkrelax && fix->fx_addsy |
5901 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5902 | return 1; | |
5903 | ||
5904 | return generic_force_reloc (fix); | |
5905 | } | |
5906 | ||
5907 | ||
30f725a1 BW |
5908 | /* TC_VALIDATE_FIX_SUB hook */ |
5909 | ||
5910 | int | |
5911 | xtensa_validate_fix_sub (fixS *fix) | |
5912 | { | |
5913 | segT add_symbol_segment, sub_symbol_segment; | |
5914 | ||
5915 | /* The difference of two symbols should be resolved by the assembler when | |
5916 | linkrelax is not set. If the linker may relax the section containing | |
5917 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5918 | the linker knows to adjust the difference value. */ | |
5919 | if (!linkrelax || fix->fx_addsy == NULL) | |
5920 | return 0; | |
5921 | ||
5922 | /* Make sure both symbols are in the same segment, and that segment is | |
5923 | "normal" and relaxable. If the segment is not "normal", then the | |
5924 | fix is not valid. If the segment is not "relaxable", then the fix | |
5925 | should have been handled earlier. */ | |
5926 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5927 | if (! SEG_NORMAL (add_symbol_segment) || | |
5928 | ! relaxable_section (add_symbol_segment)) | |
5929 | return 0; | |
5930 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5931 | return (sub_symbol_segment == add_symbol_segment); | |
5932 | } | |
5933 | ||
5934 | ||
43cd72b9 BW |
5935 | /* NO_PSEUDO_DOT hook */ |
5936 | ||
5937 | /* This function has nothing to do with pseudo dots, but this is the | |
5938 | nearest macro to where the check needs to take place. FIXME: This | |
5939 | seems wrong. */ | |
5940 | ||
5941 | bfd_boolean | |
7fa3d080 | 5942 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5943 | { |
5944 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5945 | as_bad (_("directives are not valid inside bundles")); | |
5946 | ||
5947 | /* This function must always return FALSE because it is called via a | |
5948 | macro that has nothing to do with bundling. */ | |
5949 | return FALSE; | |
e0001a05 NC |
5950 | } |
5951 | ||
5952 | ||
43cd72b9 | 5953 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5954 | |
5955 | void | |
7fa3d080 | 5956 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5957 | { |
43cd72b9 BW |
5958 | /* Set up the assembly state. */ |
5959 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5960 | xtensa_set_frag_assembly_state (frag_now); | |
54879176 MF |
5961 | |
5962 | if (!use_literal_section | |
5963 | && seg_info (now_seg)->tc_segment_info_data.literal_pool_loc == NULL | |
5964 | && !xtensa_is_init_fini (now_seg)) | |
5965 | xtensa_mark_literal_pool_location (); | |
e0001a05 NC |
5966 | } |
5967 | ||
5968 | ||
5969 | /* tc_fix_adjustable hook */ | |
5970 | ||
5971 | bfd_boolean | |
7fa3d080 | 5972 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 NC |
5973 | { |
5974 | /* We need the symbol name for the VTABLE entries. */ | |
5975 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5976 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5977 | return 0; | |
5978 | ||
5979 | return 1; | |
5980 | } | |
5981 | ||
5982 | ||
6a7eedfe BW |
5983 | /* tc_symbol_new_hook */ |
5984 | ||
5985 | symbolS *expr_symbols = NULL; | |
5986 | ||
3739860c | 5987 | void |
6a7eedfe BW |
5988 | xtensa_symbol_new_hook (symbolS *sym) |
5989 | { | |
fb227da0 | 5990 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5991 | { |
5992 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5993 | expr_symbols = sym; | |
5994 | } | |
5995 | } | |
5996 | ||
5997 | ||
e0001a05 | 5998 | void |
55cf6793 | 5999 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 6000 | { |
30f725a1 | 6001 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 6002 | valueT val = 0; |
30f725a1 | 6003 | |
e7da6241 BW |
6004 | /* Subtracted symbols are only allowed for a few relocation types, and |
6005 | unless linkrelax is enabled, they should not make it to this point. */ | |
6006 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
6007 | || fixP->fx_r_type == BFD_RELOC_16 | |
6008 | || fixP->fx_r_type == BFD_RELOC_8))) | |
6009 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
6010 | ||
30f725a1 | 6011 | switch (fixP->fx_r_type) |
e0001a05 | 6012 | { |
1bbb5f21 | 6013 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
6014 | case BFD_RELOC_32: |
6015 | case BFD_RELOC_16: | |
6016 | case BFD_RELOC_8: | |
e7da6241 | 6017 | if (fixP->fx_subsy) |
30f725a1 | 6018 | { |
30ce8e47 MF |
6019 | bfd_boolean neg = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
6020 | < S_GET_VALUE (fixP->fx_subsy); | |
6021 | ||
30f725a1 BW |
6022 | switch (fixP->fx_r_type) |
6023 | { | |
6024 | case BFD_RELOC_8: | |
30ce8e47 MF |
6025 | fixP->fx_r_type = neg |
6026 | ? BFD_RELOC_XTENSA_NDIFF8 : BFD_RELOC_XTENSA_PDIFF8; | |
ea173078 | 6027 | fixP->fx_signed = 0; |
30f725a1 BW |
6028 | break; |
6029 | case BFD_RELOC_16: | |
30ce8e47 MF |
6030 | fixP->fx_r_type = neg |
6031 | ? BFD_RELOC_XTENSA_NDIFF16 : BFD_RELOC_XTENSA_PDIFF16; | |
ea173078 | 6032 | fixP->fx_signed = 0; |
30f725a1 BW |
6033 | break; |
6034 | case BFD_RELOC_32: | |
30ce8e47 MF |
6035 | fixP->fx_r_type = neg |
6036 | ? BFD_RELOC_XTENSA_NDIFF32 : BFD_RELOC_XTENSA_PDIFF32; | |
ea173078 | 6037 | fixP->fx_signed = 0; |
30f725a1 BW |
6038 | break; |
6039 | default: | |
6040 | break; | |
6041 | } | |
e0001a05 | 6042 | |
30f725a1 BW |
6043 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
6044 | - S_GET_VALUE (fixP->fx_subsy)); | |
6045 | ||
6046 | /* The difference value gets written out, and the DIFF reloc | |
6047 | identifies the address of the subtracted symbol (i.e., the one | |
6048 | with the lowest address). */ | |
6049 | *valP = val; | |
6050 | fixP->fx_offset -= val; | |
6051 | fixP->fx_subsy = NULL; | |
6052 | } | |
6053 | else if (! fixP->fx_addsy) | |
e0001a05 | 6054 | { |
30f725a1 | 6055 | val = *valP; |
e0001a05 | 6056 | fixP->fx_done = 1; |
30f725a1 | 6057 | } |
75c1c971 MF |
6058 | else if (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section) |
6059 | { | |
6060 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
6061 | *valP = val; | |
6062 | fixP->fx_done = 1; | |
6063 | } | |
d47d412e BW |
6064 | /* fall through */ |
6065 | ||
6066 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
6067 | md_number_to_chars (fixpos, val, fixP->fx_size); |
6068 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6069 | break; | |
e0001a05 | 6070 | |
28dbbc02 BW |
6071 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
6072 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
6073 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
6074 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
6075 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6076 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
6077 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6078 | break; | |
6079 | ||
30f725a1 BW |
6080 | case BFD_RELOC_XTENSA_SLOT0_OP: |
6081 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
6082 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
6083 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
6084 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
6085 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
6086 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
6087 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
6088 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
6089 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
6090 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
6091 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
6092 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
6093 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
6094 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
6095 | if (linkrelax) | |
6096 | { | |
6097 | /* Write the tentative value of a PC-relative relocation to a | |
6098 | local symbol into the instruction. The value will be ignored | |
6099 | by the linker, and it makes the object file disassembly | |
6100 | readable when all branch targets are encoded in relocations. */ | |
6101 | ||
9c2799c2 | 6102 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 6103 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
6104 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
6105 | { | |
6106 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
6107 | - md_pcrel_from (fixP)); | |
6108 | (void) xg_apply_fix_value (fixP, val); | |
6109 | } | |
6110 | } | |
6111 | else if (! fixP->fx_addsy) | |
6112 | { | |
6113 | val = *valP; | |
6114 | if (xg_apply_fix_value (fixP, val)) | |
6115 | fixP->fx_done = 1; | |
6116 | } | |
6117 | break; | |
e0001a05 | 6118 | |
30f725a1 | 6119 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
6120 | case BFD_RELOC_XTENSA_TLS_FUNC: |
6121 | case BFD_RELOC_XTENSA_TLS_ARG: | |
6122 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
6123 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
6124 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
6125 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
6126 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
6127 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
6128 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
6129 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
6130 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
6131 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
6132 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
6133 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
6134 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
6135 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
6136 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
6137 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
6138 | /* These all need to be resolved at link-time. Do nothing now. */ | |
6139 | break; | |
e0001a05 | 6140 | |
30f725a1 BW |
6141 | case BFD_RELOC_VTABLE_INHERIT: |
6142 | case BFD_RELOC_VTABLE_ENTRY: | |
6143 | fixP->fx_done = 0; | |
6144 | break; | |
e0001a05 | 6145 | |
30f725a1 BW |
6146 | default: |
6147 | as_bad (_("unhandled local relocation fix %s"), | |
6148 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
6149 | } |
6150 | } | |
6151 | ||
6152 | ||
6d4af3c2 | 6153 | const char * |
7fa3d080 | 6154 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 6155 | { |
499ac353 | 6156 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
6157 | } |
6158 | ||
6159 | ||
6160 | int | |
7fa3d080 | 6161 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 6162 | { |
34e41783 | 6163 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
6164 | } |
6165 | ||
6166 | ||
6167 | /* Translate internal representation of relocation info to BFD target | |
6168 | format. */ | |
6169 | ||
6170 | arelent * | |
30f725a1 | 6171 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
6172 | { |
6173 | arelent *reloc; | |
6174 | ||
325801bd TS |
6175 | reloc = XNEW (arelent); |
6176 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
e0001a05 NC |
6177 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
6178 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6179 | ||
6180 | /* Make sure none of our internal relocations make it this far. | |
6181 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 6182 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 6183 | |
30f725a1 | 6184 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 6185 | |
e0001a05 NC |
6186 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
6187 | if (reloc->howto == NULL) | |
6188 | { | |
6189 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6190 | _("cannot represent `%s' relocation in object file"), | |
6191 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
6192 | free (reloc->sym_ptr_ptr); |
6193 | free (reloc); | |
e0001a05 NC |
6194 | return NULL; |
6195 | } | |
6196 | ||
6197 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 6198 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 6199 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 6200 | |
e0001a05 NC |
6201 | return reloc; |
6202 | } | |
6203 | ||
7fa3d080 BW |
6204 | \f |
6205 | /* Checks for resource conflicts between instructions. */ | |
6206 | ||
c138bc38 BW |
6207 | /* The func unit stuff could be implemented as bit-vectors rather |
6208 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6209 | slow, we will switch it. */ |
6210 | ||
c138bc38 | 6211 | resource_table * |
7fa3d080 BW |
6212 | new_resource_table (void *data, |
6213 | int cycles, | |
6214 | int nu, | |
6215 | unit_num_copies_func uncf, | |
6216 | opcode_num_units_func onuf, | |
6217 | opcode_funcUnit_use_unit_func ouuf, | |
6218 | opcode_funcUnit_use_stage_func ousf) | |
6219 | { | |
6220 | int i; | |
325801bd | 6221 | resource_table *rt = XNEW (resource_table); |
7fa3d080 BW |
6222 | rt->data = data; |
6223 | rt->cycles = cycles; | |
6224 | rt->allocated_cycles = cycles; | |
6225 | rt->num_units = nu; | |
6226 | rt->unit_num_copies = uncf; | |
6227 | rt->opcode_num_units = onuf; | |
6228 | rt->opcode_unit_use = ouuf; | |
6229 | rt->opcode_unit_stage = ousf; | |
6230 | ||
add39d23 | 6231 | rt->units = XCNEWVEC (unsigned char *, cycles); |
7fa3d080 | 6232 | for (i = 0; i < cycles; i++) |
add39d23 | 6233 | rt->units[i] = XCNEWVEC (unsigned char, nu); |
7fa3d080 BW |
6234 | |
6235 | return rt; | |
6236 | } | |
6237 | ||
6238 | ||
c138bc38 | 6239 | void |
7fa3d080 BW |
6240 | clear_resource_table (resource_table *rt) |
6241 | { | |
6242 | int i, j; | |
6243 | for (i = 0; i < rt->allocated_cycles; i++) | |
6244 | for (j = 0; j < rt->num_units; j++) | |
6245 | rt->units[i][j] = 0; | |
6246 | } | |
6247 | ||
6248 | ||
6249 | /* We never shrink it, just fake it into thinking so. */ | |
6250 | ||
c138bc38 | 6251 | void |
7fa3d080 BW |
6252 | resize_resource_table (resource_table *rt, int cycles) |
6253 | { | |
6254 | int i, old_cycles; | |
6255 | ||
6256 | rt->cycles = cycles; | |
6257 | if (cycles <= rt->allocated_cycles) | |
6258 | return; | |
6259 | ||
6260 | old_cycles = rt->allocated_cycles; | |
6261 | rt->allocated_cycles = cycles; | |
6262 | ||
325801bd | 6263 | rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles); |
7fa3d080 | 6264 | for (i = 0; i < old_cycles; i++) |
325801bd | 6265 | rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units); |
7fa3d080 | 6266 | for (i = old_cycles; i < cycles; i++) |
add39d23 | 6267 | rt->units[i] = XCNEWVEC (unsigned char, rt->num_units); |
7fa3d080 BW |
6268 | } |
6269 | ||
6270 | ||
c138bc38 | 6271 | bfd_boolean |
7fa3d080 BW |
6272 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6273 | { | |
6274 | int i; | |
6275 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6276 | ||
c138bc38 | 6277 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6278 | { |
6279 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6280 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6281 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6282 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6283 | if (copies_in_use >= copies) | |
6284 | return FALSE; | |
6285 | } | |
6286 | return TRUE; | |
6287 | } | |
7fa3d080 | 6288 | |
c138bc38 BW |
6289 | |
6290 | void | |
7fa3d080 BW |
6291 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6292 | { | |
6293 | int i; | |
6294 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6295 | ||
c138bc38 | 6296 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6297 | { |
6298 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6299 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6300 | /* Note that this allows resources to be oversubscribed. That's |
6301 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6302 | resources_available reports when a resource is over-subscribed, |
6303 | so it's easy to tell. */ | |
6304 | rt->units[stage + cycle][unit]++; | |
6305 | } | |
6306 | } | |
6307 | ||
6308 | ||
c138bc38 | 6309 | void |
7fa3d080 BW |
6310 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6311 | { | |
6312 | int i; | |
6313 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6314 | ||
c138bc38 | 6315 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6316 | { |
6317 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6318 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6319 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6320 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6321 | } |
6322 | } | |
c138bc38 | 6323 | |
7fa3d080 BW |
6324 | |
6325 | /* Wrapper functions make parameterized resource reservation | |
6326 | more convenient. */ | |
6327 | ||
c138bc38 | 6328 | int |
7fa3d080 BW |
6329 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6330 | { | |
6331 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6332 | return use->unit; |
7fa3d080 BW |
6333 | } |
6334 | ||
6335 | ||
c138bc38 | 6336 | int |
7fa3d080 BW |
6337 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6338 | { | |
6339 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6340 | return use->stage; | |
6341 | } | |
6342 | ||
6343 | ||
6344 | /* Note that this function does not check issue constraints, but | |
6345 | solely whether the hardware is available to execute the given | |
c138bc38 | 6346 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6347 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6348 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6349 | |
6350 | static bfd_boolean | |
6351 | resources_conflict (vliw_insn *vinsn) | |
6352 | { | |
6353 | int i; | |
6354 | static resource_table *rt = NULL; | |
6355 | ||
6356 | /* This is the most common case by far. Optimize it. */ | |
6357 | if (vinsn->num_slots == 1) | |
6358 | return FALSE; | |
43cd72b9 | 6359 | |
c138bc38 | 6360 | if (rt == NULL) |
7fa3d080 BW |
6361 | { |
6362 | xtensa_isa isa = xtensa_default_isa; | |
6363 | rt = new_resource_table | |
77cba8a3 | 6364 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6365 | xtensa_isa_num_funcUnits (isa), |
6366 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6367 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6368 | opcode_funcUnit_use_unit, | |
6369 | opcode_funcUnit_use_stage); | |
6370 | } | |
43cd72b9 | 6371 | |
7fa3d080 | 6372 | clear_resource_table (rt); |
43cd72b9 | 6373 | |
7fa3d080 BW |
6374 | for (i = 0; i < vinsn->num_slots; i++) |
6375 | { | |
6376 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6377 | return TRUE; | |
6378 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6379 | } | |
e0001a05 | 6380 | |
7fa3d080 BW |
6381 | return FALSE; |
6382 | } | |
e0001a05 | 6383 | |
7fa3d080 BW |
6384 | \f |
6385 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6386 | |
7fa3d080 BW |
6387 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6388 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6389 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6390 | |
6391 | ||
43cd72b9 BW |
6392 | /* We have reached the end of a bundle; emit into the frag. */ |
6393 | ||
e0001a05 | 6394 | static void |
7fa3d080 | 6395 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6396 | { |
43cd72b9 BW |
6397 | IStack slotstack; |
6398 | int i; | |
bf3d1399 | 6399 | int slots; |
e0001a05 | 6400 | |
43cd72b9 | 6401 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6402 | { |
6403 | xg_clear_vinsn (vinsn); | |
6404 | return; | |
6405 | } | |
43cd72b9 BW |
6406 | |
6407 | /* First, find a format that works. */ | |
6408 | if (vinsn->format == XTENSA_UNDEFINED) | |
6409 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6410 | ||
bf3d1399 AM |
6411 | slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format); |
6412 | if (slots > 1 | |
19fc3723 SA |
6413 | && produce_flix == FLIX_NONE) |
6414 | { | |
6415 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6416 | xg_clear_vinsn (vinsn); | |
6417 | return; | |
6418 | } | |
6419 | ||
43cd72b9 BW |
6420 | if (vinsn->format == XTENSA_UNDEFINED) |
6421 | { | |
3b4dbbbf | 6422 | as_bad (_("couldn't find a valid instruction format")); |
43cd72b9 BW |
6423 | fprintf (stderr, _(" ops were: ")); |
6424 | for (i = 0; i < vinsn->num_slots; i++) | |
6425 | fprintf (stderr, _(" %s;"), | |
6426 | xtensa_opcode_name (xtensa_default_isa, | |
6427 | vinsn->slots[i].opcode)); | |
6428 | fprintf (stderr, _("\n")); | |
6429 | xg_clear_vinsn (vinsn); | |
6430 | return; | |
6431 | } | |
6432 | ||
bf3d1399 | 6433 | if (vinsn->num_slots != slots) |
e0001a05 | 6434 | { |
bf3d1399 AM |
6435 | as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"), |
6436 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6e98b342 | 6437 | slots, vinsn->num_slots); |
43cd72b9 BW |
6438 | xg_clear_vinsn (vinsn); |
6439 | return; | |
6440 | } | |
e0001a05 | 6441 | |
c138bc38 | 6442 | if (resources_conflict (vinsn)) |
43cd72b9 | 6443 | { |
3b4dbbbf | 6444 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6445 | fprintf (stderr, " ops were: "); |
6446 | for (i = 0; i < vinsn->num_slots; i++) | |
6447 | fprintf (stderr, " %s;", | |
6448 | xtensa_opcode_name (xtensa_default_isa, | |
6449 | vinsn->slots[i].opcode)); | |
6450 | fprintf (stderr, "\n"); | |
6451 | xg_clear_vinsn (vinsn); | |
6452 | return; | |
6453 | } | |
6454 | ||
6455 | for (i = 0; i < vinsn->num_slots; i++) | |
6456 | { | |
6457 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6458 | { |
43cd72b9 BW |
6459 | symbolS *lit_sym = NULL; |
6460 | int j; | |
6461 | bfd_boolean e = FALSE; | |
6462 | bfd_boolean saved_density = density_supported; | |
6463 | ||
6464 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6465 | if (vinsn->num_slots > 1) | |
6466 | density_supported = FALSE; | |
6467 | ||
6468 | istack_init (&slotstack); | |
6469 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6470 | { |
43cd72b9 BW |
6471 | vinsn->slots[i].opcode = |
6472 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6473 | vinsn->format, i); | |
6474 | vinsn->slots[i].ntok = 0; | |
6475 | } | |
e0001a05 | 6476 | |
43cd72b9 BW |
6477 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6478 | { | |
6479 | e = TRUE; | |
6480 | continue; | |
e0001a05 | 6481 | } |
e0001a05 | 6482 | |
43cd72b9 | 6483 | density_supported = saved_density; |
e0001a05 | 6484 | |
43cd72b9 BW |
6485 | if (e) |
6486 | { | |
6487 | xg_clear_vinsn (vinsn); | |
6488 | return; | |
6489 | } | |
e0001a05 | 6490 | |
0fa77c95 | 6491 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6492 | { |
6493 | TInsn *insn = &slotstack.insn[j]; | |
6494 | if (insn->insn_type == ITYPE_LITERAL) | |
6495 | { | |
9c2799c2 | 6496 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6497 | lit_sym = xg_assemble_literal (insn); |
6498 | } | |
6499 | else | |
6500 | { | |
9c2799c2 | 6501 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6502 | if (lit_sym) |
6503 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6504 | if (j != slotstack.ninsn - 1) |
6505 | emit_single_op (insn); | |
43cd72b9 BW |
6506 | } |
6507 | } | |
6508 | ||
6509 | if (vinsn->num_slots > 1) | |
6510 | { | |
6511 | if (opcode_fits_format_slot | |
6512 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6513 | vinsn->format, i)) | |
6514 | { | |
6515 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6516 | } | |
6517 | else | |
6518 | { | |
b2d179be | 6519 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6520 | if (vinsn->format == XTENSA_UNDEFINED) |
6521 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6522 | else | |
c138bc38 | 6523 | vinsn->slots[i].opcode |
43cd72b9 BW |
6524 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6525 | vinsn->format, i); | |
6526 | ||
6527 | vinsn->slots[i].ntok = 0; | |
6528 | } | |
6529 | } | |
6530 | else | |
6531 | { | |
6532 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6533 | vinsn->format = XTENSA_UNDEFINED; | |
6534 | } | |
6535 | } | |
6536 | } | |
6537 | ||
6538 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6539 | if (resources_conflict (vinsn)) |
43cd72b9 | 6540 | { |
3b4dbbbf | 6541 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6542 | fprintf (stderr, " ops were: "); |
6543 | for (i = 0; i < vinsn->num_slots; i++) | |
6544 | fprintf (stderr, " %s;", | |
6545 | xtensa_opcode_name (xtensa_default_isa, | |
6546 | vinsn->slots[i].opcode)); | |
6547 | fprintf (stderr, "\n"); | |
6548 | xg_clear_vinsn (vinsn); | |
6549 | return; | |
6550 | } | |
6551 | ||
6552 | /* First, find a format that works. */ | |
6553 | if (vinsn->format == XTENSA_UNDEFINED) | |
6554 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6555 | ||
6556 | xg_assemble_vliw_tokens (vinsn); | |
6557 | ||
6558 | xg_clear_vinsn (vinsn); | |
a82c7d90 DW |
6559 | |
6560 | xtensa_check_frag_count (); | |
43cd72b9 BW |
6561 | } |
6562 | ||
6563 | ||
6564 | /* Given an vliw instruction, what conflicts are there in register | |
6565 | usage and in writes to states and queues? | |
6566 | ||
6567 | This function does two things: | |
6568 | 1. Reports an error when a vinsn contains illegal combinations | |
6569 | of writes to registers states or queues. | |
6570 | 2. Marks individual tinsns as not relaxable if the combination | |
6571 | contains antidependencies. | |
6572 | ||
6573 | Job 2 handles things like swap semantics in instructions that need | |
6574 | to be relaxed. For example, | |
6575 | ||
6576 | addi a0, a1, 100000 | |
6577 | ||
6578 | normally would be relaxed to | |
6579 | ||
6580 | l32r a0, some_label | |
6581 | add a0, a1, a0 | |
6582 | ||
6583 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6584 | ||
6585 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6586 | ||
6587 | then we can't relax it into | |
6588 | ||
6589 | l32r a0, some_label | |
6590 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6591 | ||
6592 | because the value of a0 is trashed before the second add can read it. */ | |
6593 | ||
7fa3d080 BW |
6594 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6595 | ||
43cd72b9 | 6596 | static bfd_boolean |
7fa3d080 | 6597 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6598 | { |
6599 | int i, j; | |
6600 | int branches = 0; | |
6601 | xtensa_isa isa = xtensa_default_isa; | |
6602 | ||
9c2799c2 | 6603 | gas_assert (!past_xtensa_end); |
43cd72b9 BW |
6604 | |
6605 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6606 | { | |
6607 | TInsn *op1 = &vinsn->slots[i]; | |
6608 | if (op1->is_specific_opcode) | |
6609 | op1->keep_wide = TRUE; | |
6610 | else | |
6611 | op1->keep_wide = FALSE; | |
6612 | } | |
6613 | ||
6614 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6615 | { | |
6616 | TInsn *op1 = &vinsn->slots[i]; | |
6617 | ||
6618 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6619 | branches++; | |
6620 | ||
6621 | for (j = 0; j < vinsn->num_slots; j++) | |
6622 | { | |
6623 | if (i != j) | |
6624 | { | |
6625 | TInsn *op2 = &vinsn->slots[j]; | |
6626 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6627 | switch (conflict_type) | |
6628 | { | |
6629 | case 'c': | |
6630 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6631 | xtensa_opcode_name (isa, op1->opcode), i, | |
6632 | xtensa_opcode_name (isa, op2->opcode), j); | |
6633 | return TRUE; | |
6634 | case 'd': | |
6635 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6636 | xtensa_opcode_name (isa, op1->opcode), i, | |
6637 | xtensa_opcode_name (isa, op2->opcode), j); | |
6638 | return TRUE; | |
6639 | case 'e': | |
53dfbcc7 | 6640 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6641 | xtensa_opcode_name (isa, op1->opcode), i, |
6642 | xtensa_opcode_name (isa, op2->opcode), j); | |
6643 | return TRUE; | |
6644 | case 'f': | |
53dfbcc7 | 6645 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6646 | xtensa_opcode_name (isa, op1->opcode), i, |
6647 | xtensa_opcode_name (isa, op2->opcode), j); | |
6648 | return TRUE; | |
6649 | default: | |
6650 | /* Everything is OK. */ | |
6651 | break; | |
6652 | } | |
6653 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6654 | || conflict_type == 'a'); | |
6655 | } | |
6656 | } | |
6657 | } | |
6658 | ||
6659 | if (branches > 1) | |
6660 | { | |
6661 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6662 | return TRUE; | |
6663 | } | |
6664 | ||
6665 | return FALSE; | |
6666 | } | |
6667 | ||
6668 | ||
a1ace8d8 | 6669 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6670 | Cases found are: |
6671 | ||
6672 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6673 | case B: no relationship between what is read and written (both could | |
6674 | read the same reg though) | |
c138bc38 | 6675 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6676 | bundle) |
6677 | case D: t1 writes a state that t2 also writes | |
6678 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6679 | case F: two volatile queue accesses |
43cd72b9 BW |
6680 | */ |
6681 | ||
6682 | static char | |
7fa3d080 | 6683 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6684 | { |
6685 | xtensa_isa isa = xtensa_default_isa; | |
6686 | xtensa_regfile t1_regfile, t2_regfile; | |
6687 | int t1_reg, t2_reg; | |
6688 | int t1_base_reg, t1_last_reg; | |
6689 | int t2_base_reg, t2_last_reg; | |
6690 | char t1_inout, t2_inout; | |
6691 | int i, j; | |
6692 | char conflict = 'b'; | |
6693 | int t1_states; | |
6694 | int t2_states; | |
6695 | int t1_interfaces; | |
6696 | int t2_interfaces; | |
6697 | bfd_boolean t1_volatile = FALSE; | |
6698 | bfd_boolean t2_volatile = FALSE; | |
6699 | ||
6700 | /* Check registers. */ | |
6701 | for (j = 0; j < t2->ntok; j++) | |
6702 | { | |
6703 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6704 | continue; | |
6705 | ||
6706 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6707 | t2_base_reg = t2->tok[j].X_add_number; | |
6708 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6709 | ||
6710 | for (i = 0; i < t1->ntok; i++) | |
6711 | { | |
6712 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6713 | continue; | |
6714 | ||
6715 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6716 | ||
6717 | if (t1_regfile != t2_regfile) | |
6718 | continue; | |
6719 | ||
6720 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6721 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6722 | ||
6723 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6724 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6725 | { | |
6726 | if (t1_inout == 'm' || t1_inout == 'o' | |
6727 | || t2_inout == 'm' || t2_inout == 'o') | |
6728 | { | |
6729 | conflict = 'a'; | |
6730 | continue; | |
6731 | } | |
6732 | } | |
6733 | ||
6734 | t1_base_reg = t1->tok[i].X_add_number; | |
6735 | t1_last_reg = (t1_base_reg | |
6736 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6737 | ||
6738 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6739 | { | |
6740 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6741 | { | |
6742 | if (t1_reg != t2_reg) | |
6743 | continue; | |
6744 | ||
6745 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6746 | { |
6747 | conflict = 'a'; | |
6748 | continue; | |
6749 | } | |
43cd72b9 | 6750 | |
7fa3d080 BW |
6751 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6752 | { | |
6753 | conflict = 'a'; | |
6754 | continue; | |
6755 | } | |
43cd72b9 | 6756 | |
7fa3d080 BW |
6757 | if (t1_inout != 'i' && t2_inout != 'i') |
6758 | return 'c'; | |
6759 | } | |
6760 | } | |
6761 | } | |
6762 | } | |
43cd72b9 | 6763 | |
7fa3d080 BW |
6764 | /* Check states. */ |
6765 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6766 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6767 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6768 | { |
7fa3d080 BW |
6769 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6770 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6771 | for (i = 0; i < t1_states; i++) | |
6772 | { | |
6773 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6774 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6775 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6776 | continue; |
43cd72b9 | 6777 | |
7fa3d080 BW |
6778 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6779 | { | |
6780 | conflict = 'a'; | |
6781 | continue; | |
6782 | } | |
c138bc38 | 6783 | |
7fa3d080 BW |
6784 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6785 | { | |
6786 | conflict = 'a'; | |
6787 | continue; | |
6788 | } | |
c138bc38 | 6789 | |
7fa3d080 BW |
6790 | if (t1_inout != 'i' && t2_inout != 'i') |
6791 | return 'd'; | |
c138bc38 | 6792 | } |
7fa3d080 | 6793 | } |
43cd72b9 | 6794 | |
7fa3d080 BW |
6795 | /* Check tieports. */ |
6796 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6797 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6798 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6799 | { |
7fa3d080 BW |
6800 | xtensa_interface t2_int |
6801 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6802 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6803 | ||
53dfbcc7 | 6804 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6805 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6806 | t2_volatile = TRUE; |
a1ace8d8 | 6807 | |
7fa3d080 BW |
6808 | for (i = 0; i < t1_interfaces; i++) |
6809 | { | |
6810 | xtensa_interface t1_int | |
6811 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6812 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6813 | |
53dfbcc7 | 6814 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6815 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6816 | t1_volatile = TRUE; |
a1ace8d8 BW |
6817 | |
6818 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6819 | return 'f'; | |
c138bc38 | 6820 | |
7fa3d080 BW |
6821 | if (t1_int != t2_int) |
6822 | continue; | |
c138bc38 | 6823 | |
7fa3d080 BW |
6824 | if (t2_inout == 'i' && t1_inout == 'o') |
6825 | { | |
6826 | conflict = 'a'; | |
6827 | continue; | |
6828 | } | |
c138bc38 | 6829 | |
7fa3d080 BW |
6830 | if (t1_inout == 'i' && t2_inout == 'o') |
6831 | { | |
6832 | conflict = 'a'; | |
6833 | continue; | |
6834 | } | |
c138bc38 | 6835 | |
7fa3d080 BW |
6836 | if (t1_inout != 'i' && t2_inout != 'i') |
6837 | return 'e'; | |
6838 | } | |
43cd72b9 | 6839 | } |
c138bc38 | 6840 | |
7fa3d080 | 6841 | return conflict; |
43cd72b9 BW |
6842 | } |
6843 | ||
6844 | ||
6845 | static xtensa_format | |
7fa3d080 | 6846 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6847 | { |
6848 | /* Right now we assume that the ops within the vinsn are properly | |
6849 | ordered for the slots that the programmer wanted them in. In | |
6850 | other words, we don't rearrange the ops in hopes of finding a | |
6851 | better format. The scheduler handles that. */ | |
6852 | ||
6853 | xtensa_isa isa = xtensa_default_isa; | |
6854 | xtensa_format format; | |
43cd72b9 BW |
6855 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6856 | ||
65738a7d BW |
6857 | if (vinsn->num_slots == 1) |
6858 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6859 | ||
43cd72b9 BW |
6860 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6861 | { | |
d8392fd9 SA |
6862 | vliw_insn v_copy; |
6863 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6864 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6865 | { | |
6866 | int slot; | |
6867 | int fit = 0; | |
6868 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6869 | { | |
6870 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6871 | { | |
6872 | v_copy.slots[slot].opcode = | |
6873 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6874 | v_copy.slots[slot].ntok = 0; | |
6875 | } | |
6876 | ||
6877 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6878 | format, slot)) | |
6879 | fit++; | |
7fa3d080 | 6880 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6881 | { |
7fa3d080 BW |
6882 | TInsn widened; |
6883 | /* Try the widened version. */ | |
6884 | if (!v_copy.slots[slot].keep_wide | |
6885 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6886 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6887 | &widened, TRUE) | |
7fa3d080 BW |
6888 | && opcode_fits_format_slot (widened.opcode, |
6889 | format, slot)) | |
43cd72b9 | 6890 | { |
7fa3d080 BW |
6891 | v_copy.slots[slot] = widened; |
6892 | fit++; | |
43cd72b9 BW |
6893 | } |
6894 | } | |
6895 | } | |
6896 | if (fit == v_copy.num_slots) | |
6897 | { | |
d8392fd9 | 6898 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6899 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6900 | vinsn->format = format; | |
6901 | break; | |
6902 | } | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | if (format == xtensa_isa_num_formats (isa)) | |
6907 | return XTENSA_UNDEFINED; | |
6908 | ||
6909 | return format; | |
6910 | } | |
6911 | ||
6912 | ||
6913 | /* Return the additional space needed in a frag | |
6914 | for possible relaxations of any ops in a VLIW insn. | |
6915 | Also fill out the relaxations that might be required of | |
6916 | each tinsn in the vinsn. */ | |
6917 | ||
6918 | static int | |
e7da6241 | 6919 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6920 | { |
e7da6241 | 6921 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6922 | int extra_space = 0; |
6923 | int slot; | |
6924 | ||
6925 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6926 | { | |
6927 | TInsn *tinsn = &vinsn->slots[slot]; | |
6928 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6929 | { | |
6930 | /* A narrow instruction could be widened later to help | |
6931 | alignment issues. */ | |
84b08ed9 | 6932 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6933 | && !tinsn->is_specific_opcode |
6934 | && vinsn->num_slots == 1) | |
6935 | { | |
6936 | /* Difference in bytes between narrow and wide insns... */ | |
6937 | extra_space += 1; | |
6938 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6939 | } |
6940 | } | |
6941 | else | |
6942 | { | |
b08b5071 BW |
6943 | if (workaround_b_j_loop_end |
6944 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6945 | && use_transform ()) |
6946 | { | |
6947 | /* Add 2 of these. */ | |
6948 | extra_space += 3; /* for the nop size */ | |
6949 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6950 | } | |
c138bc38 | 6951 | |
43cd72b9 BW |
6952 | /* Need to assemble it with space for the relocation. */ |
6953 | if (xg_is_relaxable_insn (tinsn, 0) | |
6954 | && !tinsn->is_specific_opcode) | |
6955 | { | |
6956 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6957 | int max_literal_size = | |
6958 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6959 | |
43cd72b9 | 6960 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6961 | |
43cd72b9 | 6962 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6963 | extra_space += max_size; |
6964 | } | |
6965 | else | |
6966 | { | |
e7da6241 BW |
6967 | /* A fix record will be added for this instruction prior |
6968 | to relaxation, so make it end the frag. */ | |
6969 | finish_frag = TRUE; | |
43cd72b9 BW |
6970 | } |
6971 | } | |
6972 | } | |
e7da6241 | 6973 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6974 | return extra_space; |
6975 | } | |
6976 | ||
6977 | ||
6978 | static void | |
b2d179be | 6979 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6980 | { |
6981 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6982 | int slot, chosen_slot; |
43cd72b9 | 6983 | |
b2d179be | 6984 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6985 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6986 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6987 | |
b2d179be BW |
6988 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6989 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6990 | { |
b2d179be BW |
6991 | if (slot == chosen_slot) |
6992 | vinsn->slots[slot] = *tinsn; | |
6993 | else | |
6994 | { | |
6995 | vinsn->slots[slot].opcode = | |
6996 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6997 | vinsn->slots[slot].ntok = 0; | |
6998 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6999 | } | |
43cd72b9 | 7000 | } |
43cd72b9 BW |
7001 | } |
7002 | ||
7003 | ||
7004 | static bfd_boolean | |
7fa3d080 | 7005 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
7006 | { |
7007 | int i; | |
7008 | IStack istack; /* put instructions into here */ | |
7009 | symbolS *lit_sym = NULL; | |
7010 | symbolS *label_sym = NULL; | |
7011 | ||
7012 | istack_init (&istack); | |
7013 | ||
7014 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
7015 | Because the scheduling and bundling characteristics of movi and |
7016 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 7017 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 7018 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
7019 | || orig_insn->opcode == xtensa_movi_n_opcode) |
7020 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 7021 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
7022 | || orig_insn->tok[1].X_op == O_pltrel |
7023 | || orig_insn->tok[1].X_op == O_tlsfunc | |
7024 | || orig_insn->tok[1].X_op == O_tlsarg | |
7025 | || orig_insn->tok[1].X_op == O_tpoff | |
7026 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 7027 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
7028 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
7029 | else | |
7030 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
7031 | return TRUE; | |
7032 | ||
7033 | for (i = 0; i < istack.ninsn; i++) | |
7034 | { | |
7035 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 7036 | switch (insn->insn_type) |
43cd72b9 BW |
7037 | { |
7038 | case ITYPE_LITERAL: | |
9c2799c2 | 7039 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
7040 | lit_sym = xg_assemble_literal (insn); |
7041 | break; | |
7042 | case ITYPE_LABEL: | |
7043 | { | |
7044 | static int relaxed_sym_idx = 0; | |
325801bd | 7045 | char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12); |
43cd72b9 BW |
7046 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); |
7047 | colon (label); | |
9c2799c2 | 7048 | gas_assert (label_sym == NULL); |
43cd72b9 | 7049 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 7050 | gas_assert (label_sym); |
43cd72b9 BW |
7051 | free (label); |
7052 | } | |
7053 | break; | |
7054 | case ITYPE_INSN: | |
b2d179be BW |
7055 | { |
7056 | vliw_insn v; | |
7057 | if (lit_sym) | |
7058 | xg_resolve_literals (insn, lit_sym); | |
7059 | if (label_sym) | |
7060 | xg_resolve_labels (insn, label_sym); | |
7061 | xg_init_vinsn (&v); | |
7062 | bundle_tinsn (insn, &v); | |
7063 | finish_vinsn (&v); | |
7064 | xg_free_vinsn (&v); | |
7065 | } | |
43cd72b9 BW |
7066 | break; |
7067 | default: | |
9c2799c2 | 7068 | gas_assert (0); |
43cd72b9 BW |
7069 | break; |
7070 | } | |
7071 | } | |
7072 | return FALSE; | |
7073 | } | |
7074 | ||
7075 | ||
34e41783 BW |
7076 | static int |
7077 | total_frag_text_expansion (fragS *fragP) | |
7078 | { | |
7079 | int slot; | |
7080 | int total_expansion = 0; | |
7081 | ||
62af60e2 | 7082 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
7083 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
7084 | ||
7085 | return total_expansion; | |
7086 | } | |
7087 | ||
7088 | ||
43cd72b9 BW |
7089 | /* Emit a vliw instruction to the current fragment. */ |
7090 | ||
7fa3d080 BW |
7091 | static void |
7092 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 7093 | { |
e7da6241 | 7094 | bfd_boolean finish_frag; |
43cd72b9 BW |
7095 | bfd_boolean is_jump = FALSE; |
7096 | bfd_boolean is_branch = FALSE; | |
7097 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
7098 | int insn_size; |
7099 | int extra_space; | |
7100 | char *f = NULL; | |
7101 | int slot; | |
b224e962 BW |
7102 | struct dwarf2_line_info debug_line; |
7103 | bfd_boolean loc_directive_seen = FALSE; | |
7104 | TInsn *tinsn; | |
43cd72b9 | 7105 | |
b224e962 | 7106 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
7107 | |
7108 | if (generating_literals) | |
7109 | { | |
7110 | static int reported = 0; | |
7111 | if (reported < 4) | |
7112 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
7113 | _("cannot assemble into a literal fragment")); | |
7114 | if (reported == 3) | |
7115 | as_bad (_("...")); | |
7116 | reported++; | |
7117 | return; | |
7118 | } | |
7119 | ||
7120 | if (frag_now_fix () != 0 | |
b08b5071 | 7121 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 7122 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
28a0da39 | 7123 | || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
7124 | || (directive_state[directive_longcalls] |
7125 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
7126 | || (directive_state[directive_absolute_literals] |
7127 | != frag_now->tc_frag_data.use_absolute_literals))) | |
7128 | { | |
7129 | frag_wane (frag_now); | |
7130 | frag_new (0); | |
7131 | xtensa_set_frag_assembly_state (frag_now); | |
7132 | } | |
7133 | ||
7134 | if (workaround_a0_b_retw | |
7135 | && vinsn->num_slots == 1 | |
7136 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
7137 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
7138 | && use_transform ()) | |
7139 | { | |
7140 | has_a0_b_retw = TRUE; | |
7141 | ||
7142 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
7143 | After the first assembly pass we will check all of them and | |
7144 | add a nop if needed. */ | |
7145 | frag_now->tc_frag_data.is_insn = TRUE; | |
7146 | frag_var (rs_machine_dependent, 4, 4, | |
7147 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7148 | frag_now->fr_symbol, | |
7149 | frag_now->fr_offset, | |
7150 | NULL); | |
7151 | xtensa_set_frag_assembly_state (frag_now); | |
7152 | frag_now->tc_frag_data.is_insn = TRUE; | |
7153 | frag_var (rs_machine_dependent, 4, 4, | |
7154 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7155 | frag_now->fr_symbol, | |
7156 | frag_now->fr_offset, | |
7157 | NULL); | |
7158 | xtensa_set_frag_assembly_state (frag_now); | |
7159 | } | |
7160 | ||
b224e962 | 7161 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 7162 | { |
b224e962 BW |
7163 | tinsn = &vinsn->slots[slot]; |
7164 | ||
43cd72b9 | 7165 | /* See if the instruction implies an aligned section. */ |
b224e962 | 7166 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 7167 | record_alignment (now_seg, 2); |
c138bc38 | 7168 | |
b224e962 BW |
7169 | /* Determine the best line number for debug info. */ |
7170 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
7171 | && (tinsn->debug_line.filenum != debug_line.filenum | |
7172 | || tinsn->debug_line.line < debug_line.line | |
7173 | || tinsn->debug_line.column < debug_line.column)) | |
7174 | debug_line = tinsn->debug_line; | |
7175 | if (tinsn->loc_directive_seen) | |
7176 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
7177 | } |
7178 | ||
7179 | /* Special cases for instructions that force an alignment... */ | |
7180 | /* None of these opcodes are bundle-able. */ | |
7181 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
7182 | { | |
d77b99c9 | 7183 | int max_fill; |
c138bc38 | 7184 | |
05d58145 BW |
7185 | /* Remember the symbol that marks the end of the loop in the frag |
7186 | that marks the start of the loop. This way we can easily find | |
7187 | the end of the loop at the beginning, without adding special code | |
7188 | to mark the loop instructions themselves. */ | |
7189 | symbolS *target_sym = NULL; | |
7190 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
7191 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
7192 | ||
43cd72b9 BW |
7193 | xtensa_set_frag_assembly_state (frag_now); |
7194 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 7195 | |
43cd72b9 BW |
7196 | max_fill = get_text_align_max_fill_size |
7197 | (get_text_align_power (xtensa_fetch_width), | |
7198 | TRUE, frag_now->tc_frag_data.is_no_density); | |
7199 | ||
7200 | if (use_transform ()) | |
7201 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7202 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7203 | else |
c138bc38 | 7204 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7205 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7206 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7207 | } |
7208 | ||
b08b5071 | 7209 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7210 | && !vinsn->slots[0].is_specific_opcode) |
7211 | { | |
7212 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7213 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7214 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7215 | } | |
7216 | ||
7217 | if (vinsn->num_slots == 1) | |
7218 | { | |
7219 | if (workaround_a0_b_retw && use_transform ()) | |
7220 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7221 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7222 | ||
7223 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7224 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7225 | } | |
7226 | else | |
7227 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
7228 | ||
7229 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7230 | ||
e7da6241 | 7231 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7232 | |
7233 | /* vinsn_to_insnbuf will produce the error. */ | |
7234 | if (vinsn->format != XTENSA_UNDEFINED) | |
7235 | { | |
d77b99c9 | 7236 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7237 | xtensa_set_frag_assembly_state (frag_now); |
7238 | frag_now->tc_frag_data.is_insn = TRUE; | |
7239 | } | |
7240 | ||
e7da6241 | 7241 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7242 | if (vinsn->format == XTENSA_UNDEFINED) |
7243 | return; | |
7244 | ||
d77b99c9 | 7245 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7246 | |
b224e962 BW |
7247 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7248 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7249 | &debug_line); | |
43cd72b9 BW |
7250 | |
7251 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7252 | { | |
b224e962 | 7253 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7254 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7255 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7256 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 | 7257 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
b46824bd | 7258 | if (tinsn->opcode == xtensa_l32r_opcode) |
8d1015a8 AM |
7259 | frag_now->tc_frag_data.literal_frags[slot] |
7260 | = symbol_get_frag (tinsn->tok[1].X_add_symbol); | |
43cd72b9 BW |
7261 | if (tinsn->literal_space != 0) |
7262 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7263 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7264 | |
7265 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7266 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 BW |
7267 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
7268 | is_jump = TRUE; | |
7269 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7270 | is_branch = TRUE; | |
7271 | ||
e7da6241 BW |
7272 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7273 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7274 | finish_frag = TRUE; |
7275 | } | |
7276 | ||
7277 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7278 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7279 | |
7280 | if (finish_frag) | |
7281 | { | |
7282 | frag_variant (rs_machine_dependent, | |
7283 | extra_space, extra_space, RELAX_SLOTS, | |
7284 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7285 | xtensa_set_frag_assembly_state (frag_now); | |
7286 | } | |
7287 | ||
7288 | /* Special cases for loops: | |
7289 | close_loop_end should be inserted AFTER short_loop. | |
7290 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7291 | when converting them. */ | |
7292 | ||
7293 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7294 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7295 | && !vinsn->slots[0].is_specific_opcode) |
7296 | { | |
7297 | if (workaround_short_loop && use_transform ()) | |
7298 | { | |
7299 | maybe_has_short_loop = TRUE; | |
7300 | frag_now->tc_frag_data.is_insn = TRUE; | |
7301 | frag_var (rs_machine_dependent, 4, 4, | |
7302 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7303 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7304 | frag_now->tc_frag_data.is_insn = TRUE; | |
7305 | frag_var (rs_machine_dependent, 4, 4, | |
7306 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7307 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7308 | } | |
7309 | ||
7310 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7311 | loop at least 12 bytes away from another loop's end. */ | |
7312 | if (workaround_close_loop_end && use_transform ()) | |
7313 | { | |
7314 | maybe_has_close_loop_end = TRUE; | |
7315 | frag_now->tc_frag_data.is_insn = TRUE; | |
7316 | frag_var (rs_machine_dependent, 12, 12, | |
7317 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7318 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7319 | } | |
7320 | } | |
7321 | ||
7322 | if (use_transform ()) | |
7323 | { | |
7324 | if (is_jump) | |
7325 | { | |
9c2799c2 | 7326 | gas_assert (finish_frag); |
43cd72b9 | 7327 | frag_var (rs_machine_dependent, |
1beeb686 | 7328 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7329 | RELAX_UNREACHABLE, |
7330 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7331 | xtensa_set_frag_assembly_state (frag_now); | |
a82c7d90 | 7332 | xtensa_maybe_create_trampoline_frag (); |
b46824bd MF |
7333 | /* Always create one here. */ |
7334 | xtensa_maybe_create_literal_pool_frag (TRUE, FALSE); | |
43cd72b9 | 7335 | } |
7b1cc377 | 7336 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7337 | { |
9c2799c2 | 7338 | gas_assert (finish_frag); |
43cd72b9 | 7339 | frag_var (rs_machine_dependent, |
1beeb686 | 7340 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7341 | RELAX_MAYBE_UNREACHABLE, |
7342 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7343 | xtensa_set_frag_assembly_state (frag_now); | |
7344 | frag_var (rs_machine_dependent, | |
7345 | 0, 0, | |
7346 | RELAX_MAYBE_DESIRE_ALIGN, | |
7347 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7348 | xtensa_set_frag_assembly_state (frag_now); | |
7349 | } | |
7350 | } | |
7351 | ||
7352 | /* Now, if the original opcode was a call... */ | |
7353 | if (do_align_targets () | |
7354 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7355 | { | |
b08b5071 | 7356 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7357 | frag_now->tc_frag_data.is_insn = TRUE; |
7358 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7359 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7360 | xtensa_set_frag_assembly_state (frag_now); | |
7361 | } | |
7362 | ||
7363 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7364 | { | |
7365 | frag_wane (frag_now); | |
7366 | frag_new (0); | |
7367 | xtensa_set_frag_assembly_state (frag_now); | |
7368 | } | |
7369 | } | |
7370 | ||
7371 | \f | |
7fa3d080 BW |
7372 | /* xtensa_end and helper functions. */ |
7373 | ||
7374 | static void xtensa_cleanup_align_frags (void); | |
7375 | static void xtensa_fix_target_frags (void); | |
7376 | static void xtensa_mark_narrow_branches (void); | |
7377 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7378 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7379 | static void xtensa_fix_a0_b_retw_frags (void); |
7380 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7381 | static void xtensa_fix_close_loop_end_frags (void); | |
7382 | static void xtensa_fix_short_loop_frags (void); | |
7383 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7384 | static void xtensa_add_config_info (void); |
7fa3d080 | 7385 | |
43cd72b9 | 7386 | void |
7fa3d080 | 7387 | xtensa_end (void) |
43cd72b9 BW |
7388 | { |
7389 | directive_balance (); | |
7390 | xtensa_flush_pending_output (); | |
7391 | ||
7392 | past_xtensa_end = TRUE; | |
7393 | ||
7394 | xtensa_move_literals (); | |
7395 | ||
7396 | xtensa_reorder_segments (); | |
7397 | xtensa_cleanup_align_frags (); | |
7398 | xtensa_fix_target_frags (); | |
7399 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7400 | xtensa_fix_a0_b_retw_frags (); | |
7401 | if (workaround_b_j_loop_end) | |
7402 | xtensa_fix_b_j_loop_end_frags (); | |
7403 | ||
7404 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7405 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7406 | xtensa_fix_close_loop_end_frags (); | |
7407 | ||
7408 | if (workaround_short_loop && maybe_has_short_loop) | |
7409 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7410 | if (align_targets) |
7411 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7412 | xtensa_mark_zcl_first_insns (); |
7413 | ||
7414 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7415 | |
7416 | xtensa_add_config_info (); | |
a82c7d90 DW |
7417 | |
7418 | xtensa_check_frag_count (); | |
43cd72b9 BW |
7419 | } |
7420 | ||
148d6384 MF |
7421 | struct trampoline_chain_entry |
7422 | { | |
7423 | symbolS *sym; | |
7424 | addressT offset; | |
7425 | }; | |
7426 | ||
7427 | /* Trampoline chain for a given (sym, offset) pair is a sorted array | |
7428 | of locations of trampoline jumps leading there. Jumps are represented | |
7429 | as pairs (sym, offset): trampoline frag symbol and offset of the jump | |
7430 | inside the frag. */ | |
7431 | struct trampoline_chain | |
7432 | { | |
7433 | struct trampoline_chain_entry target; | |
7434 | struct trampoline_chain_entry *entry; | |
7435 | size_t n_entries; | |
7436 | size_t n_max; | |
7437 | bfd_boolean needs_sorting; | |
7438 | }; | |
7439 | ||
7440 | struct trampoline_chain_index | |
7441 | { | |
7442 | struct trampoline_chain *entry; | |
7443 | size_t n_entries; | |
7444 | size_t n_max; | |
7445 | bfd_boolean needs_sorting; | |
7446 | }; | |
7447 | ||
fe6c2f1b MF |
7448 | struct trampoline_index |
7449 | { | |
7450 | fragS **entry; | |
7451 | size_t n_entries; | |
7452 | size_t n_max; | |
7453 | }; | |
43cd72b9 | 7454 | |
a82c7d90 DW |
7455 | struct trampoline_seg |
7456 | { | |
7457 | struct trampoline_seg *next; | |
7458 | asection *seg; | |
148d6384 | 7459 | /* Trampolines ordered by their frag fr_address */ |
fe6c2f1b | 7460 | struct trampoline_index index; |
148d6384 MF |
7461 | /* Known trampoline chains ordered by (sym, offset) pair */ |
7462 | struct trampoline_chain_index chain_index; | |
a82c7d90 DW |
7463 | }; |
7464 | ||
7465 | static struct trampoline_seg trampoline_seg_list; | |
7466 | #define J_RANGE (128 * 1024) | |
fe6c2f1b | 7467 | #define J_MARGIN 4096 |
a82c7d90 DW |
7468 | |
7469 | static int unreachable_count = 0; | |
7470 | ||
7471 | ||
7472 | static void | |
7473 | xtensa_maybe_create_trampoline_frag (void) | |
7474 | { | |
7475 | if (!use_trampolines) | |
7476 | return; | |
7477 | ||
7478 | /* We create an area for possible trampolines every 10 unreachable frags. | |
7479 | These are preferred over the ones not preceded by an unreachable frag, | |
7480 | because we don't have to jump around them. This function is called after | |
7481 | each RELAX_UNREACHABLE frag is created. */ | |
7482 | ||
7483 | if (++unreachable_count > 10) | |
7484 | { | |
7485 | xtensa_create_trampoline_frag (FALSE); | |
7486 | clear_frag_count (); | |
7487 | unreachable_count = 0; | |
7488 | } | |
7489 | } | |
7490 | ||
7491 | static void | |
7492 | xtensa_check_frag_count (void) | |
7493 | { | |
7494 | if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) | |
7495 | return; | |
7496 | ||
7497 | /* We create an area for possible trampolines every 8000 frags or so. This | |
7498 | is an estimate based on the max range of a "j" insn (+/-128K) divided | |
7499 | by a typical frag byte count (16), minus a few for safety. This function | |
7500 | is called after each source line is processed. */ | |
7501 | ||
7502 | if (get_frag_count () > 8000) | |
7503 | { | |
7504 | xtensa_create_trampoline_frag (TRUE); | |
7505 | clear_frag_count (); | |
7506 | unreachable_count = 0; | |
7507 | } | |
b46824bd MF |
7508 | |
7509 | /* We create an area for a possible literal pool every N (default 5000) | |
7510 | frags or so. */ | |
7511 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); | |
a82c7d90 DW |
7512 | } |
7513 | ||
7514 | static xtensa_insnbuf trampoline_buf = NULL; | |
7515 | static xtensa_insnbuf trampoline_slotbuf = NULL; | |
7516 | ||
b46824bd MF |
7517 | static xtensa_insnbuf litpool_buf = NULL; |
7518 | static xtensa_insnbuf litpool_slotbuf = NULL; | |
7519 | ||
a82c7d90 DW |
7520 | #define TRAMPOLINE_FRAG_SIZE 3000 |
7521 | ||
1c2649f5 MF |
7522 | static struct trampoline_seg * |
7523 | find_trampoline_seg (asection *seg) | |
7524 | { | |
7525 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
407e1140 MF |
7526 | static struct trampoline_seg *mr; |
7527 | ||
7528 | if (mr && mr->seg == seg) | |
7529 | return mr; | |
1c2649f5 MF |
7530 | |
7531 | for ( ; ts; ts = ts->next) | |
7532 | { | |
7533 | if (ts->seg == seg) | |
407e1140 MF |
7534 | { |
7535 | mr = ts; | |
7536 | return ts; | |
7537 | } | |
1c2649f5 MF |
7538 | } |
7539 | ||
7540 | return NULL; | |
7541 | } | |
7542 | ||
fe6c2f1b MF |
7543 | static size_t xg_find_trampoline (const struct trampoline_index *idx, |
7544 | addressT addr) | |
7545 | { | |
7546 | size_t a = 0; | |
7547 | size_t b = idx->n_entries; | |
7548 | ||
7549 | while (b - a > 1) | |
7550 | { | |
7551 | size_t c = (a + b) / 2; | |
7552 | ||
7553 | if (idx->entry[c]->fr_address <= addr) | |
7554 | a = c; | |
7555 | else | |
7556 | b = c; | |
7557 | } | |
7558 | return a; | |
7559 | } | |
7560 | ||
7561 | static void xg_add_trampoline_to_index (struct trampoline_index *idx, | |
7562 | fragS *fragP) | |
7563 | { | |
7564 | if (idx->n_entries == idx->n_max) | |
7565 | { | |
7566 | idx->n_max = (idx->n_entries + 1) * 2; | |
7567 | idx->entry = xrealloc (idx->entry, | |
7568 | sizeof (*idx->entry) * idx->n_max); | |
7569 | } | |
7570 | idx->entry[idx->n_entries] = fragP; | |
7571 | ++idx->n_entries; | |
7572 | } | |
7573 | ||
7574 | static void xg_remove_trampoline_from_index (struct trampoline_index *idx, | |
7575 | size_t i) | |
7576 | { | |
7577 | gas_assert (i < idx->n_entries); | |
7578 | memmove (idx->entry + i, idx->entry + i + 1, | |
7579 | (idx->n_entries - i - 1) * sizeof (*idx->entry)); | |
7580 | --idx->n_entries; | |
7581 | } | |
7582 | ||
7583 | static void xg_add_trampoline_to_seg (struct trampoline_seg *ts, | |
7584 | fragS *fragP) | |
7585 | { | |
7586 | xg_add_trampoline_to_index (&ts->index, fragP); | |
7587 | } | |
1c2649f5 | 7588 | |
a82c7d90 DW |
7589 | static void |
7590 | xtensa_create_trampoline_frag (bfd_boolean needs_jump_around) | |
7591 | { | |
7592 | /* Emit a frag where we can place intermediate jump instructions, | |
7593 | in case we need to jump farther than 128K bytes. | |
7594 | Each jump instruction takes three bytes. | |
7595 | We allocate enough for 1000 trampolines in each frag. | |
7596 | If that's not enough, oh well. */ | |
7597 | ||
1c2649f5 | 7598 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
a82c7d90 DW |
7599 | char *varP; |
7600 | fragS *fragP; | |
7601 | int size = TRAMPOLINE_FRAG_SIZE; | |
7602 | ||
a82c7d90 DW |
7603 | if (ts == NULL) |
7604 | { | |
add39d23 | 7605 | ts = XCNEW(struct trampoline_seg); |
a82c7d90 DW |
7606 | ts->next = trampoline_seg_list.next; |
7607 | trampoline_seg_list.next = ts; | |
7608 | ts->seg = now_seg; | |
7609 | } | |
7610 | ||
7611 | frag_wane (frag_now); | |
7612 | frag_new (0); | |
7613 | xtensa_set_frag_assembly_state (frag_now); | |
7614 | varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); | |
7615 | fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); | |
7616 | if (trampoline_buf == NULL) | |
7617 | { | |
7618 | trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7619 | trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7620 | } | |
46888d71 | 7621 | fragP->tc_frag_data.needs_jump_around = needs_jump_around; |
fe6c2f1b | 7622 | xg_add_trampoline_to_seg (ts, fragP); |
a82c7d90 DW |
7623 | } |
7624 | ||
fe6c2f1b MF |
7625 | static bfd_boolean xg_is_trampoline_frag_full (const fragS *fragP) |
7626 | { | |
7627 | return fragP->fr_var < 3; | |
7628 | } | |
a82c7d90 | 7629 | |
148d6384 MF |
7630 | static int xg_order_trampoline_chain_entry (const void *a, const void *b) |
7631 | { | |
7632 | const struct trampoline_chain_entry *pa = a; | |
7633 | const struct trampoline_chain_entry *pb = b; | |
7634 | ||
8ef6decb AM |
7635 | if (pa->sym != pb->sym) |
7636 | { | |
7637 | valueT aval = S_GET_VALUE (pa->sym); | |
7638 | valueT bval = S_GET_VALUE (pb->sym); | |
7639 | ||
7640 | if (aval != bval) | |
7641 | return aval < bval ? -1 : 1; | |
7642 | } | |
7643 | if (pa->offset != pb->offset) | |
7644 | return pa->offset < pb->offset ? -1 : 1; | |
7645 | return 0; | |
148d6384 MF |
7646 | } |
7647 | ||
7648 | static void xg_sort_trampoline_chain (struct trampoline_chain *tc) | |
7649 | { | |
7650 | qsort (tc->entry, tc->n_entries, sizeof (*tc->entry), | |
7651 | xg_order_trampoline_chain_entry); | |
7652 | tc->needs_sorting = FALSE; | |
7653 | } | |
7654 | ||
7655 | /* Find entry index in the given chain with maximal address <= source. */ | |
7656 | static size_t xg_find_chain_entry (struct trampoline_chain *tc, | |
7657 | addressT source) | |
7658 | { | |
7659 | size_t a = 0; | |
7660 | size_t b = tc->n_entries; | |
7661 | ||
7662 | if (tc->needs_sorting) | |
7663 | xg_sort_trampoline_chain (tc); | |
7664 | ||
7665 | while (b - a > 1) | |
7666 | { | |
7667 | size_t c = (a + b) / 2; | |
7668 | struct trampoline_chain_entry *e = tc->entry + c; | |
7669 | ||
7670 | if (S_GET_VALUE(e->sym) + e->offset <= source) | |
7671 | a = c; | |
7672 | else | |
7673 | b = c; | |
7674 | } | |
7675 | return a; | |
7676 | } | |
7677 | ||
7678 | /* Find the best jump target for the source in the given trampoline chain. | |
7679 | The best jump target is the one that results in the shortest path to the | |
7680 | final target, it's the location of the jump closest to the final target, | |
7681 | but within the J_RANGE - J_MARGIN from the source. */ | |
7682 | static struct trampoline_chain_entry * | |
7683 | xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source) | |
7684 | { | |
7685 | addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset; | |
7686 | size_t i = xg_find_chain_entry (tc, source); | |
7687 | struct trampoline_chain_entry *e = tc->entry + i; | |
7688 | int step = target < source ? -1 : 1; | |
7689 | addressT chained_target; | |
7690 | offsetT off; | |
7691 | ||
7692 | if (target > source && | |
7693 | S_GET_VALUE(e->sym) + e->offset <= source && | |
7694 | i + 1 < tc->n_entries) | |
7695 | ++i; | |
7696 | ||
7697 | while (i + step < tc->n_entries) | |
7698 | { | |
7699 | struct trampoline_chain_entry *next = tc->entry + i + step; | |
7700 | ||
7701 | chained_target = S_GET_VALUE(next->sym) + next->offset; | |
7702 | off = source - chained_target; | |
7703 | ||
7704 | if (labs (off) >= J_RANGE - J_MARGIN) | |
7705 | break; | |
7706 | ||
7707 | i += step; | |
7708 | } | |
7709 | ||
7710 | e = tc->entry + i; | |
7711 | chained_target = S_GET_VALUE(e->sym) + e->offset; | |
7712 | off = source - chained_target; | |
7713 | ||
7714 | if (labs (off) < J_MARGIN || | |
7715 | labs (off) >= J_RANGE - J_MARGIN) | |
7716 | return &tc->target; | |
7717 | return tc->entry + i; | |
7718 | } | |
7719 | ||
7720 | static int xg_order_trampoline_chain (const void *a, const void *b) | |
7721 | { | |
10af2a65 MF |
7722 | const struct trampoline_chain *_pa = a; |
7723 | const struct trampoline_chain *_pb = b; | |
7724 | const struct trampoline_chain_entry *pa = &_pa->target; | |
7725 | const struct trampoline_chain_entry *pb = &_pb->target; | |
7726 | symbolS *s1 = pa->sym; | |
7727 | symbolS *s2 = pb->sym; | |
7728 | ||
8ef6decb AM |
7729 | if (s1 != s2) |
7730 | { | |
7731 | symbolS *tmp = symbol_symbolS (s1); | |
7732 | if (tmp) | |
7733 | s1 = tmp; | |
10af2a65 | 7734 | |
8ef6decb AM |
7735 | tmp = symbol_symbolS (s2); |
7736 | if (tmp) | |
7737 | s2 = tmp; | |
10af2a65 | 7738 | |
8ef6decb AM |
7739 | if (s1 != s2) |
7740 | return s1 < s2 ? -1 : 1; | |
7741 | } | |
7742 | ||
7743 | if (pa->offset != pb->offset) | |
7744 | return pa->offset < pb->offset ? -1 : 1; | |
7745 | return 0; | |
148d6384 MF |
7746 | } |
7747 | ||
7748 | static struct trampoline_chain * | |
7749 | xg_get_trampoline_chain (struct trampoline_seg *ts, | |
7750 | symbolS *sym, | |
7751 | addressT offset) | |
7752 | { | |
7753 | struct trampoline_chain_index *idx = &ts->chain_index; | |
7754 | struct trampoline_chain c; | |
7755 | ||
e637b7ba AM |
7756 | if (idx->n_entries == 0) |
7757 | return NULL; | |
7758 | ||
148d6384 MF |
7759 | if (idx->needs_sorting) |
7760 | { | |
7761 | qsort (idx->entry, idx->n_entries, sizeof (*idx->entry), | |
7762 | xg_order_trampoline_chain); | |
7763 | idx->needs_sorting = FALSE; | |
7764 | } | |
7765 | c.target.sym = sym; | |
7766 | c.target.offset = offset; | |
7767 | return bsearch (&c, idx->entry, idx->n_entries, | |
7768 | sizeof (struct trampoline_chain), | |
7769 | xg_order_trampoline_chain); | |
7770 | } | |
7771 | ||
7772 | /* Find trampoline chain in the given trampoline segment that is going | |
7773 | to the *sym + *offset. If found, replace *sym and *offset with the | |
7774 | best jump target in that chain. */ | |
7775 | static struct trampoline_chain * | |
7776 | xg_find_best_eq_target (struct trampoline_seg *ts, | |
7777 | addressT source, symbolS **sym, | |
7778 | addressT *offset) | |
7779 | { | |
7780 | struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset); | |
7781 | ||
7782 | if (tc) | |
7783 | { | |
7784 | struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source); | |
7785 | ||
7786 | *sym = e->sym; | |
7787 | *offset = e->offset; | |
7788 | } | |
7789 | return tc; | |
7790 | } | |
7791 | ||
7792 | static void xg_add_location_to_chain (struct trampoline_chain *tc, | |
7793 | symbolS *sym, addressT offset) | |
7794 | { | |
7795 | struct trampoline_chain_entry *e; | |
7796 | ||
7797 | if (tc->n_entries == tc->n_max) | |
7798 | { | |
7799 | tc->n_max = (tc->n_max + 1) * 2; | |
7800 | tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max); | |
7801 | } | |
7802 | e = tc->entry + tc->n_entries; | |
7803 | e->sym = sym; | |
7804 | e->offset = offset; | |
7805 | ++tc->n_entries; | |
7806 | tc->needs_sorting = TRUE; | |
7807 | } | |
7808 | ||
7809 | static struct trampoline_chain * | |
7810 | xg_create_trampoline_chain (struct trampoline_seg *ts, | |
7811 | symbolS *sym, addressT offset) | |
7812 | { | |
7813 | struct trampoline_chain_index *idx = &ts->chain_index; | |
7814 | struct trampoline_chain *tc; | |
7815 | ||
7816 | if (idx->n_entries == idx->n_max) | |
7817 | { | |
7818 | idx->n_max = (idx->n_max + 1) * 2; | |
7819 | idx->entry = xrealloc (idx->entry, | |
7820 | sizeof (*idx->entry) * idx->n_max); | |
7821 | } | |
7822 | ||
7823 | tc = idx->entry + idx->n_entries; | |
7824 | tc->target.sym = sym; | |
7825 | tc->target.offset = offset; | |
7826 | tc->entry = NULL; | |
7827 | tc->n_entries = 0; | |
7828 | tc->n_max = 0; | |
7829 | xg_add_location_to_chain (tc, sym, offset); | |
7830 | ||
7831 | ++idx->n_entries; | |
7832 | idx->needs_sorting = TRUE; | |
7833 | ||
7834 | return tc; | |
7835 | } | |
7836 | ||
a82c7d90 DW |
7837 | void dump_trampolines (void); |
7838 | ||
7839 | void | |
7840 | dump_trampolines (void) | |
7841 | { | |
7842 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7843 | ||
7844 | for ( ; ts; ts = ts->next) | |
7845 | { | |
fe6c2f1b | 7846 | size_t i; |
a82c7d90 DW |
7847 | asection *seg = ts->seg; |
7848 | ||
7849 | if (seg == NULL) | |
7850 | continue; | |
7851 | fprintf(stderr, "SECTION %s\n", seg->name); | |
fe6c2f1b MF |
7852 | |
7853 | for (i = 0; i < ts->index.n_entries; ++i) | |
a82c7d90 | 7854 | { |
fe6c2f1b MF |
7855 | fragS *tf = ts->index.entry[i]; |
7856 | ||
a82c7d90 | 7857 | fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", |
46888d71 MF |
7858 | (int)tf->fr_address, (int)tf->fr_fix, |
7859 | tf->tc_frag_data.needs_jump_around ? "T" : "F"); | |
a82c7d90 DW |
7860 | } |
7861 | } | |
7862 | } | |
7863 | ||
b46824bd MF |
7864 | static void dump_litpools (void) __attribute__ ((unused)); |
7865 | ||
7866 | static void | |
7867 | dump_litpools (void) | |
7868 | { | |
7869 | struct litpool_seg *lps = litpool_seg_list.next; | |
7870 | struct litpool_frag *lpf; | |
7871 | ||
7872 | for ( ; lps ; lps = lps->next ) | |
7873 | { | |
7874 | printf("litpool seg %s\n", lps->seg->name); | |
7875 | for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next ) | |
7876 | { | |
7877 | fragS *litfrag = lpf->fragP->fr_next; | |
7878 | int count = 0; | |
7879 | while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END) | |
7880 | { | |
7881 | if (litfrag->fr_fix == 4) | |
7882 | count++; | |
7883 | litfrag = litfrag->fr_next; | |
7884 | } | |
7885 | printf(" %ld <%d:%d> (%d) [%d]: ", | |
7886 | lpf->addr, lpf->priority, lpf->original_priority, | |
7887 | lpf->fragP->fr_line, count); | |
279edac5 | 7888 | /* dump_frag(lpf->fragP); */ |
b46824bd MF |
7889 | } |
7890 | } | |
7891 | } | |
7892 | ||
7893 | static void | |
7894 | xtensa_maybe_create_literal_pool_frag (bfd_boolean create, | |
7895 | bfd_boolean only_if_needed) | |
7896 | { | |
7897 | struct litpool_seg *lps = litpool_seg_list.next; | |
7898 | fragS *fragP; | |
7899 | struct litpool_frag *lpf; | |
7900 | bfd_boolean needed = FALSE; | |
7901 | ||
7902 | if (use_literal_section || !auto_litpools) | |
7903 | return; | |
7904 | ||
7905 | for ( ; lps ; lps = lps->next ) | |
7906 | { | |
7907 | if (lps->seg == now_seg) | |
7908 | break; | |
7909 | } | |
7910 | ||
7911 | if (lps == NULL) | |
7912 | { | |
add39d23 | 7913 | lps = XCNEW (struct litpool_seg); |
b46824bd MF |
7914 | lps->next = litpool_seg_list.next; |
7915 | litpool_seg_list.next = lps; | |
7916 | lps->seg = now_seg; | |
7917 | lps->frag_list.next = &lps->frag_list; | |
7918 | lps->frag_list.prev = &lps->frag_list; | |
947fa914 MF |
7919 | /* Put candidate literal pool at the beginning of every section, |
7920 | so that even when section starts with literal load there's a | |
7921 | literal pool available. */ | |
7922 | lps->frag_count = auto_litpool_limit; | |
b46824bd MF |
7923 | } |
7924 | ||
7925 | lps->frag_count++; | |
7926 | ||
7927 | if (create) | |
7928 | { | |
7929 | if (only_if_needed) | |
7930 | { | |
7931 | if (past_xtensa_end || !use_transform() || | |
7932 | frag_now->tc_frag_data.is_no_transform) | |
7933 | { | |
7934 | return; | |
7935 | } | |
7936 | if (auto_litpool_limit <= 0) | |
7937 | { | |
7938 | /* Don't create a litpool based only on frag count. */ | |
7939 | return; | |
7940 | } | |
7941 | else if (lps->frag_count > auto_litpool_limit) | |
7942 | { | |
7943 | needed = TRUE; | |
7944 | } | |
7945 | else | |
7946 | { | |
7947 | return; | |
7948 | } | |
7949 | } | |
7950 | else | |
7951 | { | |
7952 | needed = TRUE; | |
7953 | } | |
7954 | } | |
7955 | ||
7956 | if (needed) | |
7957 | { | |
7958 | int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */ | |
7959 | /* Create a potential site for a literal pool. */ | |
7960 | frag_wane (frag_now); | |
7961 | frag_new (0); | |
7962 | xtensa_set_frag_assembly_state (frag_now); | |
7963 | fragP = frag_now; | |
7964 | fragP->tc_frag_data.lit_frchain = frchain_now; | |
7965 | fragP->tc_frag_data.literal_frag = fragP; | |
7966 | frag_var (rs_machine_dependent, size, size, | |
7967 | (only_if_needed) ? | |
7968 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN : | |
7969 | RELAX_LITERAL_POOL_BEGIN, | |
7970 | NULL, 0, NULL); | |
7971 | frag_now->tc_frag_data.lit_seg = now_seg; | |
7972 | frag_variant (rs_machine_dependent, 0, 0, | |
7973 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); | |
7974 | xtensa_set_frag_assembly_state (frag_now); | |
7975 | } | |
7976 | else | |
7977 | { | |
7978 | /* RELAX_LITERAL_POOL_BEGIN frag is being created; | |
7979 | just record it here. */ | |
7980 | fragP = frag_now; | |
7981 | } | |
7982 | ||
325801bd | 7983 | lpf = XNEW (struct litpool_frag); |
b46824bd MF |
7984 | /* Insert at tail of circular list. */ |
7985 | lpf->addr = 0; | |
7986 | lps->frag_list.prev->next = lpf; | |
7987 | lpf->next = &lps->frag_list; | |
7988 | lpf->prev = lps->frag_list.prev; | |
7989 | lps->frag_list.prev = lpf; | |
7990 | lpf->fragP = fragP; | |
7991 | lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1; | |
7992 | lpf->original_priority = lpf->priority; | |
cd665a94 | 7993 | lpf->literal_count = 0; |
b46824bd MF |
7994 | |
7995 | lps->frag_count = 0; | |
7996 | } | |
7997 | ||
43cd72b9 | 7998 | static void |
7fa3d080 | 7999 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
8000 | { |
8001 | frchainS *frchP; | |
c9049d30 | 8002 | asection *s; |
43cd72b9 | 8003 | |
c9049d30 AM |
8004 | for (s = stdoutput->sections; s; s = s->next) |
8005 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8006 | { | |
8007 | fragS *fragP; | |
8008 | /* Walk over all of the fragments in a subsection. */ | |
8009 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8010 | { | |
8011 | if ((fragP->fr_type == rs_align | |
8012 | || fragP->fr_type == rs_align_code | |
8013 | || (fragP->fr_type == rs_machine_dependent | |
8014 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
8015 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
8016 | && fragP->fr_fix == 0) | |
8017 | { | |
8018 | fragS *next = fragP->fr_next; | |
8019 | ||
8020 | while (next | |
8021 | && next->fr_fix == 0 | |
8022 | && next->fr_type == rs_machine_dependent | |
8023 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
8024 | { | |
8025 | frag_wane (next); | |
8026 | next = next->fr_next; | |
8027 | } | |
8028 | } | |
8029 | /* If we don't widen branch targets, then they | |
8030 | will be easier to align. */ | |
8031 | if (fragP->tc_frag_data.is_branch_target | |
8032 | && fragP->fr_opcode == fragP->fr_literal | |
8033 | && fragP->fr_type == rs_machine_dependent | |
8034 | && fragP->fr_subtype == RELAX_SLOTS | |
8035 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8036 | frag_wane (fragP); | |
8037 | if (fragP->fr_type == rs_machine_dependent | |
8038 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
8039 | fragP->tc_frag_data.is_unreachable = TRUE; | |
8040 | } | |
8041 | } | |
43cd72b9 BW |
8042 | } |
8043 | ||
8044 | ||
8045 | /* Re-process all of the fragments looking to convert all of the | |
8046 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
8047 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 8048 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 8049 | |
43cd72b9 | 8050 | static void |
7fa3d080 | 8051 | xtensa_fix_target_frags (void) |
e0001a05 NC |
8052 | { |
8053 | frchainS *frchP; | |
c9049d30 | 8054 | asection *s; |
e0001a05 NC |
8055 | |
8056 | /* When this routine is called, all of the subsections are still intact | |
8057 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8058 | for (s = stdoutput->sections; s; s = s->next) |
8059 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8060 | { | |
8061 | fragS *fragP; | |
e0001a05 | 8062 | |
c9049d30 AM |
8063 | /* Walk over all of the fragments in a subsection. */ |
8064 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8065 | { | |
8066 | if (fragP->fr_type == rs_machine_dependent | |
8067 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
8068 | { | |
8069 | if (next_frag_is_branch_target (fragP)) | |
8070 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
8071 | else | |
8072 | frag_wane (fragP); | |
8073 | } | |
8074 | } | |
8075 | } | |
e0001a05 NC |
8076 | } |
8077 | ||
8078 | ||
7fa3d080 BW |
8079 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
8080 | ||
43cd72b9 | 8081 | static void |
7fa3d080 | 8082 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
8083 | { |
8084 | frchainS *frchP; | |
c9049d30 | 8085 | asection *s; |
43cd72b9 | 8086 | |
c9049d30 AM |
8087 | for (s = stdoutput->sections; s; s = s->next) |
8088 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8089 | { | |
8090 | fragS *fragP; | |
8091 | /* Walk over all of the fragments in a subsection. */ | |
8092 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8093 | { | |
8094 | if (fragP->fr_type == rs_machine_dependent | |
8095 | && fragP->fr_subtype == RELAX_SLOTS | |
8096 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
8097 | { | |
8098 | vliw_insn vinsn; | |
8099 | ||
8100 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
8101 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
8102 | ||
8103 | if (vinsn.num_slots == 1 | |
8104 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 8105 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
8106 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
8107 | && is_narrow_branch_guaranteed_in_range (fragP, | |
8108 | &vinsn.slots[0])) | |
8109 | { | |
8110 | fragP->fr_subtype = RELAX_SLOTS; | |
8111 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
8112 | fragP->tc_frag_data.is_aligning_branch = 1; | |
8113 | } | |
8114 | } | |
8115 | } | |
8116 | } | |
43cd72b9 BW |
8117 | } |
8118 | ||
8119 | ||
8120 | /* A branch is typically widened only when its target is out of | |
8121 | range. However, we would like to widen them to align a subsequent | |
8122 | branch target when possible. | |
8123 | ||
8124 | Because the branch relaxation code is so convoluted, the optimal solution | |
8125 | (combining the two cases) is difficult to get right in all circumstances. | |
8126 | We therefore go with an "almost as good" solution, where we only | |
8127 | use for alignment narrow branches that definitely will not expand to a | |
8128 | jump and a branch. These functions find and mark these cases. */ | |
8129 | ||
a67517f4 BW |
8130 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
8131 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
8132 | We start counting beginning with the frag after the 2-byte branch, so the | |
8133 | maximum offset is (4 - 2) + 63 = 65. */ | |
8134 | #define MAX_IMMED6 65 | |
43cd72b9 | 8135 | |
d77b99c9 | 8136 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 8137 | |
43cd72b9 | 8138 | static bfd_boolean |
7fa3d080 | 8139 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 | 8140 | { |
91d6fa6a NC |
8141 | const expressionS *exp = &tinsn->tok[1]; |
8142 | symbolS *symbolP = exp->X_add_symbol; | |
8143 | offsetT max_distance = exp->X_add_number; | |
e7da6241 BW |
8144 | fragS *target_frag; |
8145 | ||
91d6fa6a | 8146 | if (exp->X_op != O_symbol) |
e7da6241 BW |
8147 | return FALSE; |
8148 | ||
8149 | target_frag = symbol_get_frag (symbolP); | |
8150 | ||
43cd72b9 BW |
8151 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
8152 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
8153 | return FALSE; | |
8154 | ||
8155 | /* The branch doesn't branch over it's own frag, | |
8156 | but over the subsequent ones. */ | |
8157 | fragP = fragP->fr_next; | |
8158 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
8159 | { | |
8160 | max_distance += unrelaxed_frag_max_size (fragP); | |
8161 | fragP = fragP->fr_next; | |
8162 | } | |
8163 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
8164 | return TRUE; | |
e0001a05 NC |
8165 | return FALSE; |
8166 | } | |
8167 | ||
8168 | ||
43cd72b9 | 8169 | static void |
7fa3d080 | 8170 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
8171 | { |
8172 | frchainS *frchP; | |
c9049d30 | 8173 | asection *s; |
43cd72b9 | 8174 | |
c9049d30 AM |
8175 | for (s = stdoutput->sections; s; s = s->next) |
8176 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8177 | { | |
8178 | fragS *fragP; | |
8179 | /* Walk over all of the fragments in a subsection. */ | |
8180 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8181 | { | |
8182 | if (fragP->fr_type == rs_machine_dependent | |
8183 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
8184 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
8185 | { | |
8186 | /* Find the loop frag. */ | |
3a1e9c4a | 8187 | fragS *loop_frag = next_non_empty_frag (fragP); |
c9049d30 | 8188 | /* Find the first insn frag. */ |
3a1e9c4a SA |
8189 | fragS *targ_frag = next_non_empty_frag (loop_frag); |
8190 | ||
8191 | /* Handle a corner case that comes up in hardware | |
8192 | diagnostics. The original assembly looks like this: | |
3739860c | 8193 | |
3a1e9c4a SA |
8194 | loop aX, LabelA |
8195 | <empty_frag>--not found by next_non_empty_frag | |
8196 | loop aY, LabelB | |
8197 | ||
8198 | Depending on the start address, the assembler may or | |
8199 | may not change it to look something like this: | |
8200 | ||
8201 | loop aX, LabelA | |
8202 | nop--frag isn't empty anymore | |
8203 | loop aY, LabelB | |
8204 | ||
8205 | So set up to check the alignment of the nop if it | |
8206 | exists */ | |
8207 | while (loop_frag != targ_frag) | |
8208 | { | |
8209 | if (loop_frag->fr_type == rs_machine_dependent | |
8210 | && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
3739860c | 8211 | || loop_frag->fr_subtype |
3a1e9c4a SA |
8212 | == RELAX_CHECK_ALIGN_NEXT_OPCODE)) |
8213 | targ_frag = loop_frag; | |
8214 | else | |
8215 | loop_frag = loop_frag->fr_next; | |
8216 | } | |
c9049d30 AM |
8217 | |
8218 | /* Of course, sometimes (mostly for toy test cases) a | |
8219 | zero-cost loop instruction is the last in a section. */ | |
8220 | if (targ_frag) | |
8221 | { | |
8222 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
8223 | /* Do not widen a frag that is the first instruction of a | |
8224 | zero-cost loop. It makes that loop harder to align. */ | |
8225 | if (targ_frag->fr_type == rs_machine_dependent | |
8226 | && targ_frag->fr_subtype == RELAX_SLOTS | |
8227 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
8228 | == RELAX_NARROW)) | |
8229 | { | |
8230 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
8231 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8232 | else | |
8233 | { | |
8234 | frag_wane (targ_frag); | |
8235 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
8236 | } | |
8237 | } | |
8238 | } | |
8239 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
8240 | frag_wane (fragP); | |
8241 | } | |
8242 | } | |
8243 | } | |
43cd72b9 BW |
8244 | } |
8245 | ||
8246 | ||
fb227da0 BW |
8247 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
8248 | sleb128 value, the linker is unable to adjust that value to account for | |
8249 | link-time relaxation. Mark all the code between such symbols so that | |
8250 | its size cannot be changed by linker relaxation. */ | |
3739860c | 8251 | |
6a7eedfe BW |
8252 | static void |
8253 | xtensa_mark_difference_of_two_symbols (void) | |
8254 | { | |
8255 | symbolS *expr_sym; | |
8256 | ||
3739860c | 8257 | for (expr_sym = expr_symbols; expr_sym; |
6a7eedfe BW |
8258 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) |
8259 | { | |
91d6fa6a | 8260 | expressionS *exp = symbol_get_value_expression (expr_sym); |
6a7eedfe | 8261 | |
91d6fa6a | 8262 | if (exp->X_op == O_subtract) |
6a7eedfe | 8263 | { |
91d6fa6a NC |
8264 | symbolS *left = exp->X_add_symbol; |
8265 | symbolS *right = exp->X_op_symbol; | |
3739860c | 8266 | |
6a7eedfe BW |
8267 | /* Difference of two symbols not in the same section |
8268 | are handled with relocations in the linker. */ | |
8269 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
8270 | { | |
8271 | fragS *start; | |
8272 | fragS *end; | |
983f90e3 | 8273 | fragS *walk; |
6a7eedfe | 8274 | |
3739860c | 8275 | if (symbol_get_frag (left)->fr_address |
6a7eedfe BW |
8276 | <= symbol_get_frag (right)->fr_address) |
8277 | { | |
8278 | start = symbol_get_frag (left); | |
8279 | end = symbol_get_frag (right); | |
8280 | } | |
8281 | else | |
8282 | { | |
8283 | start = symbol_get_frag (right); | |
8284 | end = symbol_get_frag (left); | |
8285 | } | |
983f90e3 SA |
8286 | |
8287 | if (start->tc_frag_data.no_transform_end != NULL) | |
8288 | walk = start->tc_frag_data.no_transform_end; | |
8289 | else | |
8290 | walk = start; | |
3739860c | 8291 | do |
6a7eedfe | 8292 | { |
983f90e3 SA |
8293 | walk->tc_frag_data.is_no_transform = 1; |
8294 | walk = walk->fr_next; | |
6a7eedfe | 8295 | } |
983f90e3 SA |
8296 | while (walk && walk->fr_address < end->fr_address); |
8297 | ||
8298 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
8299 | } |
8300 | } | |
8301 | } | |
8302 | } | |
8303 | ||
8304 | ||
e0001a05 NC |
8305 | /* Re-process all of the fragments looking to convert all of the |
8306 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
8307 | conditional branch or a retw/retw.n, convert this frag to one that | |
8308 | will generate a NOP. In any case close it off with a .fill 0. */ | |
8309 | ||
7fa3d080 BW |
8310 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
8311 | ||
e0001a05 | 8312 | static void |
7fa3d080 | 8313 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
8314 | { |
8315 | frchainS *frchP; | |
c9049d30 | 8316 | asection *s; |
e0001a05 NC |
8317 | |
8318 | /* When this routine is called, all of the subsections are still intact | |
8319 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8320 | for (s = stdoutput->sections; s; s = s->next) |
8321 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8322 | { | |
8323 | fragS *fragP; | |
e0001a05 | 8324 | |
c9049d30 AM |
8325 | /* Walk over all of the fragments in a subsection. */ |
8326 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8327 | { | |
8328 | if (fragP->fr_type == rs_machine_dependent | |
8329 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
8330 | { | |
8331 | if (next_instrs_are_b_retw (fragP)) | |
8332 | { | |
8333 | if (fragP->tc_frag_data.is_no_transform) | |
8334 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
8335 | else | |
8336 | relax_frag_add_nop (fragP); | |
8337 | } | |
8338 | frag_wane (fragP); | |
8339 | } | |
8340 | } | |
8341 | } | |
e0001a05 NC |
8342 | } |
8343 | ||
8344 | ||
7fa3d080 BW |
8345 | static bfd_boolean |
8346 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
8347 | { |
8348 | xtensa_opcode opcode; | |
43cd72b9 | 8349 | xtensa_format fmt; |
e0001a05 NC |
8350 | const fragS *next_fragP = next_non_empty_frag (fragP); |
8351 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 8352 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 8353 | xtensa_isa isa = xtensa_default_isa; |
871a6bd2 | 8354 | unsigned int offset = 0; |
43cd72b9 BW |
8355 | int slot; |
8356 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
8357 | |
8358 | if (!insnbuf) | |
43cd72b9 BW |
8359 | { |
8360 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8361 | slotbuf = xtensa_insnbuf_alloc (isa); | |
8362 | } | |
e0001a05 NC |
8363 | |
8364 | if (next_fragP == NULL) | |
8365 | return FALSE; | |
8366 | ||
8367 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
8368 | xtensa_insnbuf_from_chars |
8369 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8370 | fmt = xtensa_format_decode (isa, insnbuf); |
8371 | if (fmt == XTENSA_UNDEFINED) | |
8372 | return FALSE; | |
8373 | ||
8374 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
8375 | { | |
8376 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
8377 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
8378 | ||
8379 | branch_seen = (branch_seen | |
8380 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
8381 | } | |
e0001a05 | 8382 | |
43cd72b9 | 8383 | if (!branch_seen) |
e0001a05 NC |
8384 | return FALSE; |
8385 | ||
43cd72b9 | 8386 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8387 | if (offset == next_fragP->fr_fix) |
8388 | { | |
8389 | next_fragP = next_non_empty_frag (next_fragP); | |
8390 | offset = 0; | |
8391 | } | |
43cd72b9 | 8392 | |
e0001a05 NC |
8393 | if (next_fragP == NULL) |
8394 | return FALSE; | |
8395 | ||
8396 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
8397 | xtensa_insnbuf_from_chars |
8398 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8399 | fmt = xtensa_format_decode (isa, insnbuf); |
8400 | ||
8401 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
8402 | have no problems. */ | |
8403 | if (fmt == XTENSA_UNDEFINED | |
8404 | || xtensa_format_num_slots (isa, fmt) != 1) | |
8405 | return FALSE; | |
8406 | ||
8407 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
8408 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 8409 | |
b08b5071 | 8410 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 8411 | return TRUE; |
43cd72b9 | 8412 | |
e0001a05 NC |
8413 | return FALSE; |
8414 | } | |
8415 | ||
8416 | ||
8417 | /* Re-process all of the fragments looking to convert all of the | |
8418 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
8419 | loop end label, convert this frag to one that will generate a NOP. | |
8420 | In any case close it off with a .fill 0. */ | |
8421 | ||
7fa3d080 BW |
8422 | static bfd_boolean next_instr_is_loop_end (fragS *); |
8423 | ||
e0001a05 | 8424 | static void |
7fa3d080 | 8425 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
8426 | { |
8427 | frchainS *frchP; | |
c9049d30 | 8428 | asection *s; |
e0001a05 NC |
8429 | |
8430 | /* When this routine is called, all of the subsections are still intact | |
8431 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8432 | for (s = stdoutput->sections; s; s = s->next) |
8433 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8434 | { | |
8435 | fragS *fragP; | |
e0001a05 | 8436 | |
c9049d30 AM |
8437 | /* Walk over all of the fragments in a subsection. */ |
8438 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8439 | { | |
8440 | if (fragP->fr_type == rs_machine_dependent | |
8441 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
8442 | { | |
8443 | if (next_instr_is_loop_end (fragP)) | |
8444 | { | |
8445 | if (fragP->tc_frag_data.is_no_transform) | |
8446 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
8447 | else | |
8448 | relax_frag_add_nop (fragP); | |
8449 | } | |
8450 | frag_wane (fragP); | |
8451 | } | |
8452 | } | |
8453 | } | |
e0001a05 NC |
8454 | } |
8455 | ||
8456 | ||
7fa3d080 BW |
8457 | static bfd_boolean |
8458 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
8459 | { |
8460 | const fragS *next_fragP; | |
8461 | ||
8462 | if (next_frag_is_loop_target (fragP)) | |
8463 | return FALSE; | |
8464 | ||
8465 | next_fragP = next_non_empty_frag (fragP); | |
8466 | if (next_fragP == NULL) | |
8467 | return FALSE; | |
8468 | ||
8469 | if (!next_frag_is_loop_target (next_fragP)) | |
8470 | return FALSE; | |
8471 | ||
8472 | /* If the size is >= 3 then there is more than one instruction here. | |
8473 | The hardware bug will not fire. */ | |
8474 | if (next_fragP->fr_fix > 3) | |
8475 | return FALSE; | |
8476 | ||
8477 | return TRUE; | |
8478 | } | |
8479 | ||
8480 | ||
8481 | /* Re-process all of the fragments looking to convert all of the | |
8482 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
8483 | not MY loop's loop end within 12 bytes, add enough nops here to | |
8484 | make it at least 12 bytes away. In any case close it off with a | |
8485 | .fill 0. */ | |
8486 | ||
d77b99c9 | 8487 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 8488 | (fragS *, fragS *, offsetT); |
7fa3d080 | 8489 | |
e0001a05 | 8490 | static void |
7fa3d080 | 8491 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
8492 | { |
8493 | frchainS *frchP; | |
c9049d30 | 8494 | asection *s; |
e0001a05 NC |
8495 | |
8496 | /* When this routine is called, all of the subsections are still intact | |
8497 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8498 | for (s = stdoutput->sections; s; s = s->next) |
8499 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8500 | { | |
8501 | fragS *fragP; | |
e0001a05 | 8502 | |
c9049d30 | 8503 | fragS *current_target = NULL; |
e0001a05 | 8504 | |
c9049d30 AM |
8505 | /* Walk over all of the fragments in a subsection. */ |
8506 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8507 | { | |
8508 | if (fragP->fr_type == rs_machine_dependent | |
8509 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8510 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 8511 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 8512 | |
c9049d30 AM |
8513 | if (current_target |
8514 | && fragP->fr_type == rs_machine_dependent | |
8515 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
8516 | { | |
8517 | offsetT min_bytes; | |
8518 | int bytes_added = 0; | |
e0001a05 NC |
8519 | |
8520 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
8521 | /* Max out at 12. */ |
8522 | min_bytes = min_bytes_to_other_loop_end | |
8523 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
8524 | ||
8525 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
8526 | { | |
8527 | if (fragP->tc_frag_data.is_no_transform) | |
8528 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
8529 | else | |
8530 | { | |
8531 | while (min_bytes + bytes_added | |
8532 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
8533 | { | |
8534 | int length = 3; | |
8535 | ||
8536 | if (fragP->fr_var < length) | |
8537 | as_fatal (_("fr_var %lu < length %d"), | |
8538 | (long) fragP->fr_var, length); | |
8539 | else | |
8540 | { | |
8541 | assemble_nop (length, | |
8542 | fragP->fr_literal + fragP->fr_fix); | |
8543 | fragP->fr_fix += length; | |
8544 | fragP->fr_var -= length; | |
8545 | } | |
8546 | bytes_added += length; | |
8547 | } | |
8548 | } | |
8549 | } | |
8550 | frag_wane (fragP); | |
8551 | } | |
9c2799c2 | 8552 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
8553 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
8554 | } | |
8555 | } | |
e0001a05 NC |
8556 | } |
8557 | ||
8558 | ||
d77b99c9 | 8559 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 8560 | |
d77b99c9 | 8561 | static offsetT |
7fa3d080 BW |
8562 | min_bytes_to_other_loop_end (fragS *fragP, |
8563 | fragS *current_target, | |
d77b99c9 | 8564 | offsetT max_size) |
e0001a05 | 8565 | { |
d77b99c9 | 8566 | offsetT offset = 0; |
e0001a05 NC |
8567 | fragS *current_fragP; |
8568 | ||
8569 | for (current_fragP = fragP; | |
8570 | current_fragP; | |
8571 | current_fragP = current_fragP->fr_next) | |
8572 | { | |
8573 | if (current_fragP->tc_frag_data.is_loop_target | |
8574 | && current_fragP != current_target) | |
05d58145 | 8575 | return offset; |
e0001a05 NC |
8576 | |
8577 | offset += unrelaxed_frag_min_size (current_fragP); | |
8578 | ||
05d58145 | 8579 | if (offset >= max_size) |
e0001a05 NC |
8580 | return max_size; |
8581 | } | |
8582 | return max_size; | |
8583 | } | |
8584 | ||
8585 | ||
d77b99c9 | 8586 | static offsetT |
7fa3d080 | 8587 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 8588 | { |
d77b99c9 | 8589 | offsetT size = fragP->fr_fix; |
e0001a05 | 8590 | |
d77b99c9 | 8591 | /* Add fill size. */ |
e0001a05 NC |
8592 | if (fragP->fr_type == rs_fill) |
8593 | size += fragP->fr_offset; | |
8594 | ||
8595 | return size; | |
8596 | } | |
8597 | ||
8598 | ||
d77b99c9 | 8599 | static offsetT |
7fa3d080 | 8600 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 8601 | { |
d77b99c9 | 8602 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
8603 | switch (fragP->fr_type) |
8604 | { | |
8605 | case 0: | |
c138bc38 | 8606 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
8607 | end up with type 0. */ |
8608 | break; | |
8609 | case rs_fill: | |
8610 | case rs_org: | |
8611 | case rs_space: | |
8612 | size += fragP->fr_offset; | |
8613 | break; | |
8614 | case rs_align: | |
8615 | case rs_align_code: | |
8616 | case rs_align_test: | |
8617 | case rs_leb128: | |
8618 | case rs_cfa: | |
8619 | case rs_dwarf2dbg: | |
8620 | /* No further adjustments needed. */ | |
8621 | break; | |
8622 | case rs_machine_dependent: | |
8623 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
8624 | size += fragP->fr_var; | |
8625 | break; | |
8626 | default: | |
8627 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 8628 | gas_assert (0); |
43cd72b9 BW |
8629 | break; |
8630 | } | |
8631 | ||
8632 | return size; | |
8633 | } | |
8634 | ||
8635 | ||
e0001a05 NC |
8636 | /* Re-process all of the fragments looking to convert all |
8637 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
8638 | ||
8639 | A) | |
8640 | 1) the instruction size count to the loop end label | |
8641 | is too short (<= 2 instructions), | |
8642 | 2) loop has a jump or branch in it | |
8643 | ||
8644 | or B) | |
43cd72b9 | 8645 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
8646 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
8647 | 3) the instruction size count to the loop end label is too short | |
8648 | (<= 2 instructions) | |
8649 | then convert this frag (and maybe the next one) to generate a NOP. | |
8650 | In any case close it off with a .fill 0. */ | |
8651 | ||
d77b99c9 | 8652 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
8653 | static bfd_boolean branch_before_loop_end (fragS *); |
8654 | ||
e0001a05 | 8655 | static void |
7fa3d080 | 8656 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
8657 | { |
8658 | frchainS *frchP; | |
c9049d30 | 8659 | asection *s; |
e0001a05 NC |
8660 | |
8661 | /* When this routine is called, all of the subsections are still intact | |
8662 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8663 | for (s = stdoutput->sections; s; s = s->next) |
8664 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8665 | { | |
8666 | fragS *fragP; | |
c9049d30 | 8667 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; |
e0001a05 | 8668 | |
c9049d30 AM |
8669 | /* Walk over all of the fragments in a subsection. */ |
8670 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8671 | { | |
8672 | if (fragP->fr_type == rs_machine_dependent | |
8673 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8674 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
8675 | { | |
8676 | TInsn t_insn; | |
8677 | fragS *loop_frag = next_non_empty_frag (fragP); | |
8678 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
c9049d30 | 8679 | current_opcode = t_insn.opcode; |
9c2799c2 | 8680 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 8681 | current_opcode) == 1); |
c9049d30 | 8682 | } |
e0001a05 | 8683 | |
c9049d30 AM |
8684 | if (fragP->fr_type == rs_machine_dependent |
8685 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8686 | { | |
8687 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
8688 | && (branch_before_loop_end (fragP->fr_next) | |
8689 | || (workaround_all_short_loops | |
8690 | && current_opcode != XTENSA_UNDEFINED | |
8691 | && current_opcode != xtensa_loop_opcode))) | |
8692 | { | |
8693 | if (fragP->tc_frag_data.is_no_transform) | |
8694 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
8695 | else | |
8696 | relax_frag_add_nop (fragP); | |
8697 | } | |
8698 | frag_wane (fragP); | |
8699 | } | |
8700 | } | |
8701 | } | |
e0001a05 NC |
8702 | } |
8703 | ||
8704 | ||
d77b99c9 | 8705 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 8706 | |
d77b99c9 | 8707 | static int |
7fa3d080 BW |
8708 | count_insns_to_loop_end (fragS *base_fragP, |
8709 | bfd_boolean count_relax_add, | |
d77b99c9 | 8710 | int max_count) |
e0001a05 NC |
8711 | { |
8712 | fragS *fragP = NULL; | |
d77b99c9 | 8713 | int insn_count = 0; |
e0001a05 NC |
8714 | |
8715 | fragP = base_fragP; | |
8716 | ||
8717 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
8718 | { | |
8719 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
8720 | if (insn_count >= max_count) | |
8721 | return max_count; | |
8722 | ||
8723 | if (count_relax_add) | |
8724 | { | |
8725 | if (fragP->fr_type == rs_machine_dependent | |
8726 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8727 | { | |
8728 | /* In order to add the appropriate number of | |
8729 | NOPs, we count an instruction for downstream | |
8730 | occurrences. */ | |
8731 | insn_count++; | |
8732 | if (insn_count >= max_count) | |
8733 | return max_count; | |
8734 | } | |
8735 | } | |
8736 | } | |
8737 | return insn_count; | |
8738 | } | |
8739 | ||
8740 | ||
d77b99c9 | 8741 | static int |
7fa3d080 | 8742 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 8743 | { |
43cd72b9 BW |
8744 | xtensa_isa isa = xtensa_default_isa; |
8745 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 8746 | int insn_count = 0; |
871a6bd2 | 8747 | unsigned int offset = 0; |
e0001a05 NC |
8748 | |
8749 | if (!fragP->tc_frag_data.is_insn) | |
8750 | return insn_count; | |
8751 | ||
43cd72b9 BW |
8752 | if (!insnbuf) |
8753 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8754 | ||
e0001a05 NC |
8755 | /* Decode the fixed instructions. */ |
8756 | while (offset < fragP->fr_fix) | |
8757 | { | |
43cd72b9 BW |
8758 | xtensa_format fmt; |
8759 | ||
d77b99c9 BW |
8760 | xtensa_insnbuf_from_chars |
8761 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8762 | fmt = xtensa_format_decode (isa, insnbuf); |
8763 | ||
8764 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
8765 | { |
8766 | as_fatal (_("undecodable instruction in instruction frag")); | |
8767 | return insn_count; | |
8768 | } | |
43cd72b9 | 8769 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8770 | insn_count++; |
8771 | } | |
8772 | ||
8773 | return insn_count; | |
8774 | } | |
8775 | ||
8776 | ||
7fa3d080 BW |
8777 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
8778 | ||
43cd72b9 | 8779 | static bfd_boolean |
7fa3d080 | 8780 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
8781 | { |
8782 | fragS *fragP; | |
8783 | ||
8784 | for (fragP = base_fragP; | |
8785 | fragP && !fragP->tc_frag_data.is_loop_target; | |
8786 | fragP = fragP->fr_next) | |
8787 | { | |
8788 | if (unrelaxed_frag_has_b_j (fragP)) | |
8789 | return TRUE; | |
8790 | } | |
8791 | return FALSE; | |
8792 | } | |
8793 | ||
8794 | ||
43cd72b9 | 8795 | static bfd_boolean |
7fa3d080 | 8796 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 8797 | { |
43cd72b9 BW |
8798 | static xtensa_insnbuf insnbuf = NULL; |
8799 | xtensa_isa isa = xtensa_default_isa; | |
871a6bd2 | 8800 | unsigned int offset = 0; |
e0001a05 NC |
8801 | |
8802 | if (!fragP->tc_frag_data.is_insn) | |
8803 | return FALSE; | |
8804 | ||
43cd72b9 BW |
8805 | if (!insnbuf) |
8806 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8807 | ||
e0001a05 NC |
8808 | /* Decode the fixed instructions. */ |
8809 | while (offset < fragP->fr_fix) | |
8810 | { | |
43cd72b9 BW |
8811 | xtensa_format fmt; |
8812 | int slot; | |
8813 | ||
d77b99c9 BW |
8814 | xtensa_insnbuf_from_chars |
8815 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8816 | fmt = xtensa_format_decode (isa, insnbuf); |
8817 | if (fmt == XTENSA_UNDEFINED) | |
8818 | return FALSE; | |
8819 | ||
8820 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8821 | { |
43cd72b9 BW |
8822 | xtensa_opcode opcode = |
8823 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8824 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8825 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
8826 | return TRUE; | |
e0001a05 | 8827 | } |
43cd72b9 | 8828 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8829 | } |
8830 | return FALSE; | |
8831 | } | |
8832 | ||
8833 | ||
8834 | /* Checks to be made after initial assembly but before relaxation. */ | |
8835 | ||
7fa3d080 BW |
8836 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
8837 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
8838 | ||
e0001a05 | 8839 | static void |
7fa3d080 | 8840 | xtensa_sanity_check (void) |
e0001a05 | 8841 | { |
3b4dbbbf | 8842 | const char *file_name; |
d77b99c9 | 8843 | unsigned line; |
e0001a05 | 8844 | frchainS *frchP; |
c9049d30 | 8845 | asection *s; |
e0001a05 | 8846 | |
3b4dbbbf | 8847 | file_name = as_where (&line); |
c9049d30 AM |
8848 | for (s = stdoutput->sections; s; s = s->next) |
8849 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8850 | { | |
8851 | fragS *fragP; | |
e0001a05 | 8852 | |
c9049d30 AM |
8853 | /* Walk over all of the fragments in a subsection. */ |
8854 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8855 | { | |
c9049d30 | 8856 | if (fragP->fr_type == rs_machine_dependent |
3739860c | 8857 | && fragP->fr_subtype == RELAX_SLOTS |
a7284bf1 | 8858 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) |
c9049d30 AM |
8859 | { |
8860 | static xtensa_insnbuf insnbuf = NULL; | |
8861 | TInsn t_insn; | |
8862 | ||
8863 | if (fragP->fr_opcode != NULL) | |
8864 | { | |
8865 | if (!insnbuf) | |
8866 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8867 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8868 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8869 | ||
8870 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8871 | t_insn.opcode) == 1) | |
8872 | { | |
8873 | if (is_empty_loop (&t_insn, fragP)) | |
8874 | { | |
8875 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8876 | as_bad (_("invalid empty loop")); | |
8877 | } | |
8878 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8879 | { | |
8880 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8881 | as_bad (_("loop target does not follow " | |
8882 | "loop instruction in section")); | |
8883 | } | |
8884 | } | |
8885 | } | |
8886 | } | |
8887 | } | |
8888 | } | |
e0001a05 NC |
8889 | new_logical_line (file_name, line); |
8890 | } | |
8891 | ||
8892 | ||
8893 | #define LOOP_IMMED_OPN 1 | |
8894 | ||
43cd72b9 | 8895 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8896 | |
7fa3d080 BW |
8897 | static bfd_boolean |
8898 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8899 | { |
91d6fa6a | 8900 | const expressionS *exp; |
e0001a05 NC |
8901 | symbolS *symbolP; |
8902 | fragS *next_fragP; | |
8903 | ||
8904 | if (insn->insn_type != ITYPE_INSN) | |
8905 | return FALSE; | |
8906 | ||
43cd72b9 | 8907 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8908 | return FALSE; |
8909 | ||
8910 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8911 | return FALSE; | |
8912 | ||
91d6fa6a | 8913 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8914 | |
91d6fa6a | 8915 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8916 | return FALSE; |
8917 | ||
91d6fa6a | 8918 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8919 | if (!symbolP) |
8920 | return FALSE; | |
8921 | ||
8922 | if (symbol_get_frag (symbolP) == NULL) | |
8923 | return FALSE; | |
8924 | ||
8925 | if (S_GET_VALUE (symbolP) != 0) | |
8926 | return FALSE; | |
8927 | ||
8928 | /* Walk through the zero-size fragments from this one. If we find | |
8929 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8930 | |
e0001a05 NC |
8931 | for (next_fragP = fragP->fr_next; |
8932 | next_fragP != NULL; | |
8933 | next_fragP = next_fragP->fr_next) | |
8934 | { | |
8935 | if (next_fragP == symbol_get_frag (symbolP)) | |
8936 | return TRUE; | |
8937 | if (next_fragP->fr_fix != 0) | |
8938 | return FALSE; | |
8939 | } | |
8940 | return FALSE; | |
8941 | } | |
8942 | ||
8943 | ||
7fa3d080 BW |
8944 | static bfd_boolean |
8945 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8946 | { |
91d6fa6a | 8947 | const expressionS *exp; |
e0001a05 NC |
8948 | symbolS *symbolP; |
8949 | fragS *next_fragP; | |
8950 | ||
8951 | if (insn->insn_type != ITYPE_INSN) | |
8952 | return FALSE; | |
8953 | ||
64b607e6 | 8954 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8955 | return FALSE; |
8956 | ||
8957 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8958 | return FALSE; | |
8959 | ||
91d6fa6a | 8960 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8961 | |
91d6fa6a | 8962 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8963 | return FALSE; |
8964 | ||
91d6fa6a | 8965 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8966 | if (!symbolP) |
8967 | return FALSE; | |
8968 | ||
8969 | if (symbol_get_frag (symbolP) == NULL) | |
8970 | return FALSE; | |
8971 | ||
8972 | /* Walk through fragments until we find the target. | |
8973 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8974 | |
e0001a05 NC |
8975 | for (next_fragP = fragP->fr_next; |
8976 | next_fragP != NULL; | |
8977 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8978 | { |
8979 | if (next_fragP == symbol_get_frag (symbolP)) | |
8980 | return TRUE; | |
8981 | } | |
e0001a05 NC |
8982 | |
8983 | return FALSE; | |
8984 | } | |
8985 | ||
2caa7ca0 BW |
8986 | #define XTINFO_NAME "Xtensa_Info" |
8987 | #define XTINFO_NAMESZ 12 | |
8988 | #define XTINFO_TYPE 1 | |
8989 | ||
8990 | static void | |
8991 | xtensa_add_config_info (void) | |
8992 | { | |
8993 | asection *info_sec; | |
8994 | char *data, *p; | |
8995 | int sz; | |
8996 | ||
8997 | info_sec = subseg_new (".xtensa.info", 0); | |
fd361982 | 8998 | bfd_set_section_flags (info_sec, SEC_HAS_CONTENTS | SEC_READONLY); |
2caa7ca0 | 8999 | |
325801bd | 9000 | data = XNEWVEC (char, 100); |
2caa7ca0 | 9001 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", |
7a77f1ac | 9002 | XSHAL_USE_ABSOLUTE_LITERALS, xtensa_abi_choice ()); |
2caa7ca0 BW |
9003 | sz = strlen (data) + 1; |
9004 | ||
9005 | /* Add enough null terminators to pad to a word boundary. */ | |
9006 | do | |
9007 | data[sz++] = 0; | |
9008 | while ((sz & 3) != 0); | |
9009 | ||
9010 | /* Follow the standard note section layout: | |
9011 | First write the length of the name string. */ | |
9012 | p = frag_more (4); | |
9013 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
9014 | ||
9015 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
9016 | p = frag_more (4); | |
9017 | md_number_to_chars (p, (valueT) sz, 4); | |
9018 | ||
9019 | /* Write the note type. */ | |
9020 | p = frag_more (4); | |
9021 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
9022 | ||
9023 | /* Write the name field. */ | |
9024 | p = frag_more (XTINFO_NAMESZ); | |
9025 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
9026 | ||
9027 | /* Finally, write the descriptor. */ | |
9028 | p = frag_more (sz); | |
9029 | memcpy (p, data, sz); | |
9030 | ||
9031 | free (data); | |
9032 | } | |
9033 | ||
e0001a05 NC |
9034 | \f |
9035 | /* Alignment Functions. */ | |
9036 | ||
d77b99c9 BW |
9037 | static int |
9038 | get_text_align_power (unsigned target_size) | |
e0001a05 | 9039 | { |
03aaa593 BW |
9040 | if (target_size <= 4) |
9041 | return 2; | |
19ef5f3d SA |
9042 | |
9043 | if (target_size <= 8) | |
9044 | return 3; | |
9045 | ||
9046 | if (target_size <= 16) | |
9047 | return 4; | |
9048 | ||
9049 | if (target_size <= 32) | |
9050 | return 5; | |
9051 | ||
9052 | if (target_size <= 64) | |
9053 | return 6; | |
9054 | ||
9055 | if (target_size <= 128) | |
9056 | return 7; | |
9057 | ||
9058 | if (target_size <= 256) | |
9059 | return 8; | |
9060 | ||
9061 | if (target_size <= 512) | |
9062 | return 9; | |
9063 | ||
9064 | if (target_size <= 1024) | |
9065 | return 10; | |
9066 | ||
9067 | gas_assert (0); | |
9068 | return 0; | |
e0001a05 NC |
9069 | } |
9070 | ||
9071 | ||
d77b99c9 | 9072 | static int |
7fa3d080 BW |
9073 | get_text_align_max_fill_size (int align_pow, |
9074 | bfd_boolean use_nops, | |
9075 | bfd_boolean use_no_density) | |
e0001a05 NC |
9076 | { |
9077 | if (!use_nops) | |
9078 | return (1 << align_pow); | |
9079 | if (use_no_density) | |
9080 | return 3 * (1 << align_pow); | |
9081 | ||
9082 | return 1 + (1 << align_pow); | |
9083 | } | |
9084 | ||
9085 | ||
d77b99c9 BW |
9086 | /* Calculate the minimum bytes of fill needed at "address" to align a |
9087 | target instruction of size "target_size" so that it does not cross a | |
9088 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
9089 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
9090 | be filled by NOP instructions. */ | |
e0001a05 | 9091 | |
d77b99c9 | 9092 | static int |
7fa3d080 BW |
9093 | get_text_align_fill_size (addressT address, |
9094 | int align_pow, | |
9095 | int target_size, | |
9096 | bfd_boolean use_nops, | |
9097 | bfd_boolean use_no_density) | |
e0001a05 | 9098 | { |
d77b99c9 BW |
9099 | addressT alignment, fill, fill_limit, fill_step; |
9100 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 9101 | |
d77b99c9 | 9102 | alignment = (1 << align_pow); |
9c2799c2 | 9103 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 9104 | |
e0001a05 NC |
9105 | if (!use_nops) |
9106 | { | |
d77b99c9 BW |
9107 | fill_limit = alignment; |
9108 | fill_step = 1; | |
e0001a05 | 9109 | } |
d77b99c9 | 9110 | else if (!use_no_density) |
e0001a05 | 9111 | { |
d77b99c9 BW |
9112 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
9113 | fill_limit = alignment * 2; | |
9114 | fill_step = 1; | |
9115 | skip_one = TRUE; | |
e0001a05 NC |
9116 | } |
9117 | else | |
9118 | { | |
d77b99c9 BW |
9119 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
9120 | fill_limit = alignment * 3; | |
9121 | fill_step = 3; | |
9122 | } | |
e0001a05 | 9123 | |
d77b99c9 BW |
9124 | /* Try all fill sizes until finding one that works. */ |
9125 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
9126 | { | |
9127 | if (skip_one && fill == 1) | |
9128 | continue; | |
9129 | if ((address + fill) >> align_pow | |
9130 | == (address + fill + target_size - 1) >> align_pow) | |
9131 | return fill; | |
e0001a05 | 9132 | } |
9c2799c2 | 9133 | gas_assert (0); |
e0001a05 NC |
9134 | return 0; |
9135 | } | |
9136 | ||
9137 | ||
664df4e4 BW |
9138 | static int |
9139 | branch_align_power (segT sec) | |
9140 | { | |
19ef5f3d SA |
9141 | /* If the Xtensa processor has a fetch width of X, and |
9142 | the section is aligned to at least that boundary, then a branch | |
9143 | target need only fit within that aligned block of memory to avoid | |
9144 | a stall. Otherwise, try to fit branch targets within 4-byte | |
9145 | aligned blocks (which may be insufficient, e.g., if the section | |
9146 | has no alignment, but it's good enough). */ | |
9147 | int fetch_align = get_text_align_power(xtensa_fetch_width); | |
9148 | int sec_align = get_recorded_alignment (sec); | |
9149 | ||
9150 | if (sec_align >= fetch_align) | |
9151 | return fetch_align; | |
664df4e4 BW |
9152 | |
9153 | return 2; | |
9154 | } | |
9155 | ||
9156 | ||
e0001a05 NC |
9157 | /* This will assert if it is not possible. */ |
9158 | ||
d77b99c9 BW |
9159 | static int |
9160 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 9161 | { |
d77b99c9 BW |
9162 | int count = 0; |
9163 | ||
e0001a05 NC |
9164 | if (use_no_density) |
9165 | { | |
9c2799c2 | 9166 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
9167 | return (fill_size / 3); |
9168 | } | |
9169 | ||
9c2799c2 | 9170 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
9171 | |
9172 | while (fill_size > 1) | |
9173 | { | |
d77b99c9 | 9174 | int insn_size = 3; |
e0001a05 NC |
9175 | if (fill_size == 2 || fill_size == 4) |
9176 | insn_size = 2; | |
9177 | fill_size -= insn_size; | |
9178 | count++; | |
9179 | } | |
9c2799c2 | 9180 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
9181 | return count; |
9182 | } | |
9183 | ||
9184 | ||
d77b99c9 BW |
9185 | static int |
9186 | get_text_align_nth_nop_size (offsetT fill_size, | |
9187 | int n, | |
7fa3d080 | 9188 | bfd_boolean use_no_density) |
e0001a05 | 9189 | { |
d77b99c9 | 9190 | int count = 0; |
e0001a05 NC |
9191 | |
9192 | if (use_no_density) | |
9193 | return 3; | |
9194 | ||
9c2799c2 | 9195 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 9196 | |
e0001a05 NC |
9197 | while (fill_size > 1) |
9198 | { | |
d77b99c9 | 9199 | int insn_size = 3; |
e0001a05 NC |
9200 | if (fill_size == 2 || fill_size == 4) |
9201 | insn_size = 2; | |
9202 | fill_size -= insn_size; | |
9203 | count++; | |
9204 | if (n + 1 == count) | |
9205 | return insn_size; | |
9206 | } | |
9c2799c2 | 9207 | gas_assert (0); |
e0001a05 NC |
9208 | return 0; |
9209 | } | |
9210 | ||
9211 | ||
9212 | /* For the given fragment, find the appropriate address | |
9213 | for it to begin at if we are using NOPs to align it. */ | |
9214 | ||
9215 | static addressT | |
7fa3d080 | 9216 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 9217 | { |
43cd72b9 BW |
9218 | /* The rule is: get next fragment's FIRST instruction. Find |
9219 | the smallest number of bytes that need to be added to | |
9220 | ensure that the next fragment's FIRST instruction will fit | |
9221 | in a single word. | |
c138bc38 | 9222 | |
43cd72b9 BW |
9223 | E.G., 2 bytes : 0, 1, 2 mod 4 |
9224 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 9225 | |
43cd72b9 BW |
9226 | If the FIRST instruction MIGHT be relaxed, |
9227 | assume that it will become a 3-byte instruction. | |
c138bc38 | 9228 | |
43cd72b9 BW |
9229 | Note again here that LOOP instructions are not bundleable, |
9230 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 9231 | |
d77b99c9 | 9232 | int fill_size = 0; |
43cd72b9 BW |
9233 | int first_insn_size; |
9234 | int loop_insn_size; | |
9235 | addressT pre_opcode_bytes; | |
d77b99c9 | 9236 | int align_power; |
43cd72b9 BW |
9237 | fragS *first_insn; |
9238 | xtensa_opcode opcode; | |
9239 | bfd_boolean is_loop; | |
e0001a05 | 9240 | |
9c2799c2 NC |
9241 | gas_assert (fragP->fr_type == rs_machine_dependent); |
9242 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 9243 | |
43cd72b9 BW |
9244 | /* Find the loop frag. */ |
9245 | first_insn = next_non_empty_frag (fragP); | |
9246 | /* Now find the first insn frag. */ | |
9247 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 9248 | |
43cd72b9 | 9249 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 9250 | gas_assert (is_loop); |
43cd72b9 | 9251 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 9252 | |
43cd72b9 BW |
9253 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
9254 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 9255 | |
43cd72b9 BW |
9256 | /* For loops, the alignment depends on the size of the |
9257 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 9258 | |
43cd72b9 | 9259 | if (first_insn == NULL) |
03aaa593 BW |
9260 | first_insn_size = xtensa_fetch_width; |
9261 | else | |
9262 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 9263 | |
43cd72b9 | 9264 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
9265 | align_power = get_text_align_power (first_insn_size); |
9266 | record_alignment (now_seg, align_power); | |
c138bc38 | 9267 | |
43cd72b9 | 9268 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
9269 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
9270 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
9271 | |
9272 | return address + fill_size; | |
9273 | } | |
9274 | ||
9275 | ||
43cd72b9 BW |
9276 | /* 3 mechanisms for relaxing an alignment: |
9277 | ||
9278 | Align to a power of 2. | |
9279 | Align so the next fragment's instruction does not cross a word boundary. | |
9280 | Align the current instruction so that if the next instruction | |
9281 | were 3 bytes, it would not cross a word boundary. | |
9282 | ||
e0001a05 NC |
9283 | We can align with: |
9284 | ||
43cd72b9 BW |
9285 | zeros - This is easy; always insert zeros. |
9286 | nops - 3-byte and 2-byte instructions | |
9287 | 2 - 2-byte nop | |
9288 | 3 - 3-byte nop | |
9289 | 4 - 2 2-byte nops | |
9290 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
9291 | widening - widen previous instructions. */ |
9292 | ||
d77b99c9 BW |
9293 | static offsetT |
9294 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 9295 | { |
43cd72b9 BW |
9296 | addressT target_address, loop_insn_offset; |
9297 | int target_size; | |
9298 | xtensa_opcode loop_opcode; | |
9299 | bfd_boolean is_loop; | |
d77b99c9 BW |
9300 | int align_power; |
9301 | offsetT opt_diff; | |
5f9084e9 | 9302 | offsetT branch_align; |
def13efb | 9303 | fragS *loop_frag; |
e0001a05 | 9304 | |
9c2799c2 | 9305 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 9306 | switch (fragP->fr_subtype) |
e0001a05 | 9307 | { |
43cd72b9 BW |
9308 | case RELAX_DESIRE_ALIGN: |
9309 | target_size = next_frag_format_size (fragP); | |
9310 | if (target_size == XTENSA_UNDEFINED) | |
9311 | target_size = 3; | |
664df4e4 BW |
9312 | align_power = branch_align_power (now_seg); |
9313 | branch_align = 1 << align_power; | |
0e5cd789 BW |
9314 | /* Don't count on the section alignment being as large as the target. */ |
9315 | if (target_size > branch_align) | |
9316 | target_size = branch_align; | |
d77b99c9 | 9317 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
9318 | target_size, FALSE, FALSE); |
9319 | ||
664df4e4 BW |
9320 | *max_diff = (opt_diff + branch_align |
9321 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 9322 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9323 | return opt_diff; |
e0001a05 | 9324 | |
43cd72b9 | 9325 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
9326 | /* The next non-empty frag after this one holds the LOOP instruction |
9327 | that needs to be aligned. The required alignment depends on the | |
9328 | size of the next non-empty frag after the loop frag, i.e., the | |
9329 | first instruction in the loop. */ | |
9330 | loop_frag = next_non_empty_frag (fragP); | |
9331 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
9332 | loop_insn_offset = 0; |
9333 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 9334 | gas_assert (is_loop); |
43cd72b9 BW |
9335 | |
9336 | /* If the loop has been expanded then the LOOP instruction | |
9337 | could be at an offset from this fragment. */ | |
def13efb | 9338 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
9339 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
9340 | ||
43cd72b9 BW |
9341 | /* In an ideal world, which is what we are shooting for here, |
9342 | we wouldn't need to use any NOPs immediately prior to the | |
9343 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
9344 | will call get_noop_aligned_address. */ | |
9345 | target_address = | |
9346 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 9347 | align_power = get_text_align_power (target_size); |
d77b99c9 | 9348 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
9349 | target_size, FALSE, FALSE); |
9350 | ||
9351 | *max_diff = xtensa_fetch_width | |
9352 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
9353 | - target_size + opt_diff; | |
9c2799c2 | 9354 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9355 | return opt_diff; |
e0001a05 | 9356 | |
43cd72b9 BW |
9357 | default: |
9358 | break; | |
e0001a05 | 9359 | } |
9c2799c2 | 9360 | gas_assert (0); |
43cd72b9 | 9361 | return 0; |
e0001a05 NC |
9362 | } |
9363 | ||
9364 | \f | |
9365 | /* md_relax_frag Hook and Helper Functions. */ | |
9366 | ||
7fa3d080 BW |
9367 | static long relax_frag_loop_align (fragS *, long); |
9368 | static long relax_frag_for_align (fragS *, long); | |
9369 | static long relax_frag_immed | |
9370 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
9371 | ||
fe6c2f1b MF |
9372 | /* Get projected address for the first fulcrum on a path from source to |
9373 | target. */ | |
9374 | static addressT xg_get_fulcrum (addressT source, addressT target) | |
b76f99d7 | 9375 | { |
fe6c2f1b MF |
9376 | offsetT delta = target - source; |
9377 | int n; | |
b76f99d7 | 9378 | |
fe6c2f1b MF |
9379 | n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN); |
9380 | return source + delta / n; | |
9381 | } | |
b76f99d7 | 9382 | |
fe6c2f1b MF |
9383 | /* Given trampoline index, source and target of a jump find the best |
9384 | candidate trampoline for the first fulcrum. The best trampoline is | |
9385 | the one in the reach of "j' instruction from the source, closest to | |
9386 | the projected fulcrum address, and preferrably w/o a jump around or | |
9387 | with already initialized jump around. */ | |
9388 | static size_t xg_find_best_trampoline (struct trampoline_index *idx, | |
9389 | addressT source, addressT target) | |
b76f99d7 | 9390 | { |
fe6c2f1b MF |
9391 | addressT fulcrum = xg_get_fulcrum (source, target); |
9392 | size_t dist = 0; | |
9393 | size_t best = -1; | |
9394 | size_t base_tr = xg_find_trampoline (idx, fulcrum); | |
9395 | int checked = 1; | |
b76f99d7 | 9396 | |
fe6c2f1b MF |
9397 | /* Check trampoline frags around the base_tr to find the best. */ |
9398 | for (dist = 0; checked; ++dist) | |
b76f99d7 | 9399 | { |
fe6c2f1b MF |
9400 | int i; |
9401 | size_t tr = base_tr - dist; | |
9402 | ||
9403 | checked = 0; | |
9404 | ||
9405 | /* Trampolines are checked in the following order: | |
9406 | base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */ | |
9407 | for (i = 0; i < 2; ++i, tr = base_tr + dist + 1) | |
9408 | if (tr < idx->n_entries) | |
9409 | { | |
9410 | fragS *trampoline_frag = idx->entry[tr]; | |
9411 | offsetT off; | |
9412 | ||
9413 | /* Don't check trampolines outside source - target interval. */ | |
9414 | if ((trampoline_frag->fr_address < source && | |
9415 | trampoline_frag->fr_address < target) || | |
9416 | (trampoline_frag->fr_address > source && | |
9417 | trampoline_frag->fr_address > target)) | |
9418 | continue; | |
9419 | ||
db5d5ad1 MF |
9420 | /* Don't choose trampoline that contains the source. */ |
9421 | if (source >= trampoline_frag->fr_address | |
9422 | && source <= trampoline_frag->fr_address + | |
9423 | trampoline_frag->fr_fix) | |
9424 | continue; | |
9425 | ||
fe6c2f1b MF |
9426 | off = trampoline_frag->fr_address - fulcrum; |
9427 | /* Stop if some trampoline is found and the search is more than | |
9428 | J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump | |
9429 | around is nice, but it shouldn't have much overhead. */ | |
9430 | if (best < idx->n_entries && labs (off) > J_RANGE / 4) | |
9431 | return best; | |
9432 | ||
9433 | off = trampoline_frag->fr_address - source; | |
9434 | if (labs (off) < J_RANGE - J_MARGIN) | |
9435 | { | |
9436 | ++checked; | |
9437 | /* Stop if a trampoline w/o jump around is found or initialized | |
9438 | trampoline with jump around is found. */ | |
9439 | if (!trampoline_frag->tc_frag_data.needs_jump_around || | |
9440 | trampoline_frag->fr_fix) | |
9441 | return tr; | |
9442 | else if (best >= idx->n_entries) | |
9443 | best = tr; | |
9444 | } | |
9445 | } | |
b76f99d7 | 9446 | } |
fe6c2f1b MF |
9447 | |
9448 | if (best < idx->n_entries) | |
9449 | return best; | |
9450 | else | |
9451 | as_fatal (_("cannot find suitable trampoline")); | |
b76f99d7 MF |
9452 | } |
9453 | ||
fe6c2f1b MF |
9454 | static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP) |
9455 | { | |
9456 | symbolS *s = fixP->fx_addsy; | |
9457 | addressT source = fixP->fx_frag->fr_address; | |
9458 | addressT target = S_GET_VALUE (s) + fixP->fx_offset; | |
9459 | size_t tr = xg_find_best_trampoline (idx, source, target); | |
9460 | fragS *trampoline_frag = idx->entry[tr]; | |
9461 | fixS *newfixP; | |
9462 | ||
9463 | init_trampoline_frag (trampoline_frag); | |
9464 | newfixP = xg_append_jump (trampoline_frag, | |
9465 | fixP->fx_addsy, fixP->fx_offset); | |
9466 | ||
9467 | /* Adjust the fixup for the original "j" instruction to | |
9468 | point to the newly added jump. */ | |
9469 | fixP->fx_addsy = trampoline_frag->fr_symbol; | |
9470 | fixP->fx_offset = trampoline_frag->fr_fix - 3; | |
9471 | fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol; | |
9472 | fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3; | |
9473 | ||
9474 | trampoline_frag->tc_frag_data.relax_seen = FALSE; | |
9475 | ||
9476 | if (xg_is_trampoline_frag_full (trampoline_frag)) | |
9477 | xg_remove_trampoline_from_index (idx, tr); | |
9478 | ||
9479 | return newfixP; | |
9480 | } | |
9481 | ||
9482 | static bfd_boolean xg_is_relaxable_fixup (fixS *fixP) | |
b76f99d7 MF |
9483 | { |
9484 | xtensa_isa isa = xtensa_default_isa; | |
fe6c2f1b MF |
9485 | addressT addr = fixP->fx_frag->fr_address; |
9486 | addressT target; | |
9487 | offsetT delta; | |
b76f99d7 MF |
9488 | symbolS *s = fixP->fx_addsy; |
9489 | int slot; | |
9490 | xtensa_format fmt; | |
9491 | xtensa_opcode opcode; | |
9492 | ||
9493 | if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || | |
9494 | fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) | |
9495 | return FALSE; | |
fe6c2f1b MF |
9496 | |
9497 | target = S_GET_VALUE (s) + fixP->fx_offset; | |
b76f99d7 MF |
9498 | delta = target - addr; |
9499 | ||
fe6c2f1b | 9500 | if (labs (delta) < J_RANGE - J_MARGIN) |
b76f99d7 MF |
9501 | return FALSE; |
9502 | ||
9503 | xtensa_insnbuf_from_chars (isa, trampoline_buf, | |
9504 | (unsigned char *) fixP->fx_frag->fr_literal + | |
9505 | fixP->fx_where, 0); | |
9506 | fmt = xtensa_format_decode (isa, trampoline_buf); | |
9507 | gas_assert (fmt != XTENSA_UNDEFINED); | |
9508 | slot = fixP->tc_fix_data.slot; | |
9509 | xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); | |
9510 | opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); | |
fe6c2f1b | 9511 | return opcode == xtensa_j_opcode; |
b76f99d7 MF |
9512 | } |
9513 | ||
fe6c2f1b | 9514 | static void xg_relax_fixups (struct trampoline_seg *ts) |
b76f99d7 | 9515 | { |
fe6c2f1b MF |
9516 | struct trampoline_index *idx = &ts->index; |
9517 | segment_info_type *seginfo = seg_info (now_seg); | |
9518 | fixS *fx; | |
b76f99d7 | 9519 | |
fe6c2f1b | 9520 | for (fx = seginfo->fix_root; fx; fx = fx->fx_next) |
b76f99d7 | 9521 | { |
fe6c2f1b | 9522 | fixS *fixP = fx; |
148d6384 MF |
9523 | struct trampoline_chain *tc = NULL; |
9524 | ||
9525 | if (xg_is_relaxable_fixup (fixP)) | |
9526 | { | |
9527 | tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address, | |
9528 | &fixP->fx_addsy, &fixP->fx_offset); | |
9529 | if (!tc) | |
9530 | tc = xg_create_trampoline_chain (ts, fixP->fx_addsy, | |
9531 | fixP->fx_offset); | |
9532 | gas_assert (tc); | |
9533 | } | |
b76f99d7 | 9534 | |
fe6c2f1b | 9535 | while (xg_is_relaxable_fixup (fixP)) |
148d6384 MF |
9536 | { |
9537 | fixP = xg_relax_fixup (idx, fixP); | |
9538 | xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, | |
9539 | fixP->fx_where); | |
9540 | } | |
b76f99d7 | 9541 | } |
b76f99d7 | 9542 | } |
7fa3d080 | 9543 | |
fe6c2f1b MF |
9544 | /* Given a trampoline frag relax all jumps that might want to use this |
9545 | trampoline. Only do real work once per relaxation cycle, when | |
9546 | xg_relax_trampoline is called for the first trampoline in the now_seg. | |
9547 | Don't use stretch, don't update new_stretch: place fulcrums with a | |
9548 | slack to tolerate code movement. In the worst case if a jump between | |
9549 | two trampolines wouldn't reach the next relaxation pass will fix it. */ | |
9550 | static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED, | |
9551 | long *new_stretch ATTRIBUTE_UNUSED) | |
120bc8b8 | 9552 | { |
fe6c2f1b | 9553 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
120bc8b8 | 9554 | |
fe6c2f1b MF |
9555 | if (ts->index.n_entries && ts->index.entry[0] == fragP) |
9556 | xg_relax_fixups (ts); | |
120bc8b8 MF |
9557 | } |
9558 | ||
e0001a05 NC |
9559 | /* Return the number of bytes added to this fragment, given that the |
9560 | input has been stretched already by "stretch". */ | |
9561 | ||
9562 | long | |
7fa3d080 | 9563 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 9564 | { |
43cd72b9 | 9565 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9566 | int unreported = fragP->tc_frag_data.unreported_expansion; |
9567 | long new_stretch = 0; | |
3b4dbbbf | 9568 | const char *file_name; |
d77b99c9 BW |
9569 | unsigned line; |
9570 | int lit_size; | |
43cd72b9 BW |
9571 | static xtensa_insnbuf vbuf = NULL; |
9572 | int slot, num_slots; | |
9573 | xtensa_format fmt; | |
e0001a05 | 9574 | |
3b4dbbbf | 9575 | file_name = as_where (&line); |
e0001a05 NC |
9576 | new_logical_line (fragP->fr_file, fragP->fr_line); |
9577 | ||
9578 | fragP->tc_frag_data.unreported_expansion = 0; | |
9579 | ||
9580 | switch (fragP->fr_subtype) | |
9581 | { | |
9582 | case RELAX_ALIGN_NEXT_OPCODE: | |
9583 | /* Always convert. */ | |
43cd72b9 BW |
9584 | if (fragP->tc_frag_data.relax_seen) |
9585 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
9586 | break; |
9587 | ||
9588 | case RELAX_LOOP_END: | |
9589 | /* Do nothing. */ | |
9590 | break; | |
9591 | ||
9592 | case RELAX_LOOP_END_ADD_NOP: | |
9593 | /* Add a NOP and switch to .fill 0. */ | |
9594 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 9595 | frag_wane (fragP); |
e0001a05 NC |
9596 | break; |
9597 | ||
9598 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 9599 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
9600 | it or not. */ |
9601 | break; | |
9602 | ||
9603 | case RELAX_LITERAL: | |
9604 | case RELAX_LITERAL_FINAL: | |
9605 | return 0; | |
9606 | ||
9607 | case RELAX_LITERAL_NR: | |
9608 | lit_size = 4; | |
9609 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9610 | gas_assert (unreported == lit_size); |
e0001a05 NC |
9611 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
9612 | fragP->fr_var -= lit_size; | |
9613 | fragP->fr_fix += lit_size; | |
9614 | new_stretch = 4; | |
9615 | break; | |
9616 | ||
43cd72b9 BW |
9617 | case RELAX_SLOTS: |
9618 | if (vbuf == NULL) | |
9619 | vbuf = xtensa_insnbuf_alloc (isa); | |
9620 | ||
d77b99c9 BW |
9621 | xtensa_insnbuf_from_chars |
9622 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
9623 | fmt = xtensa_format_decode (isa, vbuf); |
9624 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 9625 | |
43cd72b9 BW |
9626 | for (slot = 0; slot < num_slots; slot++) |
9627 | { | |
9628 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
9629 | { | |
9630 | case RELAX_NARROW: | |
9631 | if (fragP->tc_frag_data.relax_seen) | |
9632 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9633 | break; | |
9634 | ||
9635 | case RELAX_IMMED: | |
9636 | case RELAX_IMMED_STEP1: | |
9637 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9638 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9639 | /* Place the immediate. */ |
9640 | new_stretch += relax_frag_immed | |
9641 | (now_seg, fragP, stretch, | |
9642 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9643 | fmt, slot, stretched_p, FALSE); | |
9644 | break; | |
9645 | ||
9646 | default: | |
9647 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
9648 | break; | |
9649 | } | |
9650 | } | |
e0001a05 NC |
9651 | break; |
9652 | ||
9653 | case RELAX_LITERAL_POOL_BEGIN: | |
b46824bd MF |
9654 | if (fragP->fr_var != 0) |
9655 | { | |
9656 | /* We have a converted "candidate" literal pool; | |
9657 | assemble a jump around it. */ | |
9658 | TInsn insn; | |
9659 | if (!litpool_slotbuf) | |
9660 | { | |
9661 | litpool_buf = xtensa_insnbuf_alloc (isa); | |
9662 | litpool_slotbuf = xtensa_insnbuf_alloc (isa); | |
9663 | } | |
9664 | new_stretch += 3; | |
9665 | fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ | |
9666 | fragP->tc_frag_data.is_insn = TRUE; | |
9667 | tinsn_init (&insn); | |
9668 | insn.insn_type = ITYPE_INSN; | |
9669 | insn.opcode = xtensa_j_opcode; | |
9670 | insn.ntok = 1; | |
9671 | set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol, | |
9672 | fragP->fr_fix); | |
9673 | fmt = xg_get_single_format (xtensa_j_opcode); | |
9674 | tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf); | |
9675 | xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf); | |
9676 | xtensa_insnbuf_to_chars (isa, litpool_buf, | |
9677 | (unsigned char *)fragP->fr_literal + | |
9678 | fragP->fr_fix, 3); | |
9679 | fragP->fr_fix += 3; | |
9680 | fragP->fr_var -= 3; | |
9681 | /* Add a fix-up. */ | |
9682 | fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE, | |
9683 | BFD_RELOC_XTENSA_SLOT0_OP); | |
9684 | } | |
9685 | break; | |
9686 | ||
e0001a05 | 9687 | case RELAX_LITERAL_POOL_END: |
b46824bd | 9688 | case RELAX_LITERAL_POOL_CANDIDATE_BEGIN: |
43cd72b9 BW |
9689 | case RELAX_MAYBE_UNREACHABLE: |
9690 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
9691 | /* No relaxation required. */ |
9692 | break; | |
9693 | ||
43cd72b9 BW |
9694 | case RELAX_FILL_NOP: |
9695 | case RELAX_UNREACHABLE: | |
9696 | if (fragP->tc_frag_data.relax_seen) | |
9697 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9698 | break; | |
9699 | ||
a82c7d90 DW |
9700 | case RELAX_TRAMPOLINE: |
9701 | if (fragP->tc_frag_data.relax_seen) | |
120bc8b8 | 9702 | xg_relax_trampoline (fragP, stretch, &new_stretch); |
a82c7d90 DW |
9703 | break; |
9704 | ||
e0001a05 NC |
9705 | default: |
9706 | as_bad (_("bad relaxation state")); | |
9707 | } | |
9708 | ||
43cd72b9 | 9709 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 9710 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
9711 | { |
9712 | fragP->tc_frag_data.relax_seen = TRUE; | |
9713 | *stretched_p = 1; | |
9714 | } | |
9715 | ||
e0001a05 NC |
9716 | new_logical_line (file_name, line); |
9717 | return new_stretch; | |
9718 | } | |
9719 | ||
9720 | ||
9721 | static long | |
7fa3d080 | 9722 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
9723 | { |
9724 | addressT old_address, old_next_address, old_size; | |
9725 | addressT new_address, new_next_address, new_size; | |
9726 | addressT growth; | |
9727 | ||
43cd72b9 BW |
9728 | /* All the frags with relax_frag_for_alignment prior to this one in the |
9729 | section have been done, hopefully eliminating the need for a NOP here. | |
9730 | But, this will put it in if necessary. */ | |
e0001a05 NC |
9731 | |
9732 | /* Calculate the old address of this fragment and the next fragment. */ | |
9733 | old_address = fragP->fr_address - stretch; | |
9734 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 9735 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
9736 | old_size = old_next_address - old_address; |
9737 | ||
9738 | /* Calculate the new address of this fragment and the next fragment. */ | |
9739 | new_address = fragP->fr_address; | |
9740 | new_next_address = | |
9741 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
9742 | new_size = new_next_address - new_address; | |
9743 | ||
9744 | growth = new_size - old_size; | |
9745 | ||
9746 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 9747 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
9748 | return growth; |
9749 | } | |
9750 | ||
9751 | ||
43cd72b9 | 9752 | /* Add a NOP instruction. */ |
e0001a05 NC |
9753 | |
9754 | static long | |
7fa3d080 | 9755 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 9756 | { |
e0001a05 | 9757 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
9758 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
9759 | assemble_nop (length, nop_buf); | |
e0001a05 | 9760 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 9761 | |
e0001a05 NC |
9762 | if (fragP->fr_var < length) |
9763 | { | |
dd49a749 | 9764 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
9765 | return 0; |
9766 | } | |
9767 | ||
9768 | fragP->fr_fix += length; | |
9769 | fragP->fr_var -= length; | |
e0001a05 NC |
9770 | return length; |
9771 | } | |
9772 | ||
9773 | ||
7fa3d080 BW |
9774 | static long future_alignment_required (fragS *, long); |
9775 | ||
e0001a05 | 9776 | static long |
7fa3d080 | 9777 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 9778 | { |
43cd72b9 BW |
9779 | /* Overview of the relaxation procedure for alignment: |
9780 | We can widen with NOPs or by widening instructions or by filling | |
9781 | bytes after jump instructions. Find the opportune places and widen | |
9782 | them if necessary. */ | |
9783 | ||
9784 | long stretch_me; | |
9785 | long diff; | |
e0001a05 | 9786 | |
9c2799c2 | 9787 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
9788 | || fragP->fr_subtype == RELAX_UNREACHABLE |
9789 | || (fragP->fr_subtype == RELAX_SLOTS | |
9790 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
9791 | ||
9792 | stretch_me = future_alignment_required (fragP, stretch); | |
9793 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
9794 | if (diff == 0) | |
9795 | return 0; | |
e0001a05 | 9796 | |
43cd72b9 | 9797 | if (diff < 0) |
e0001a05 | 9798 | { |
43cd72b9 BW |
9799 | /* We expanded on a previous pass. Can we shrink now? */ |
9800 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
9801 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 9802 | { |
43cd72b9 BW |
9803 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
9804 | return -shrink; | |
e0001a05 NC |
9805 | } |
9806 | return 0; | |
9807 | } | |
9808 | ||
43cd72b9 BW |
9809 | /* Below here, diff > 0. */ |
9810 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 9811 | |
43cd72b9 | 9812 | return diff; |
e0001a05 NC |
9813 | } |
9814 | ||
9815 | ||
43cd72b9 BW |
9816 | /* Return the address of the next frag that should be aligned. |
9817 | ||
9818 | By "address" we mean the address it _would_ be at if there | |
9819 | is no action taken to align it between here and the target frag. | |
9820 | In other words, if no narrows and no fill nops are used between | |
9821 | here and the frag to align, _even_if_ some of the frags we use | |
9822 | to align targets have already expanded on a previous relaxation | |
9823 | pass. | |
9824 | ||
9825 | Also, count each frag that may be used to help align the target. | |
9826 | ||
9827 | Return 0 if there are no frags left in the chain that need to be | |
9828 | aligned. */ | |
9829 | ||
9830 | static addressT | |
7fa3d080 BW |
9831 | find_address_of_next_align_frag (fragS **fragPP, |
9832 | int *wide_nops, | |
9833 | int *narrow_nops, | |
9834 | int *widens, | |
9835 | bfd_boolean *paddable) | |
e0001a05 | 9836 | { |
43cd72b9 BW |
9837 | fragS *fragP = *fragPP; |
9838 | addressT address = fragP->fr_address; | |
9839 | ||
9840 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
9841 | |
9842 | while (fragP) | |
9843 | { | |
9844 | /* Limit this to a small search. */ | |
b5e4a23d | 9845 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
9846 | { |
9847 | *fragPP = fragP; | |
9848 | return 0; | |
9849 | } | |
e0001a05 NC |
9850 | address += fragP->fr_fix; |
9851 | ||
43cd72b9 BW |
9852 | if (fragP->fr_type == rs_fill) |
9853 | address += fragP->fr_offset * fragP->fr_var; | |
9854 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 9855 | { |
e0001a05 NC |
9856 | switch (fragP->fr_subtype) |
9857 | { | |
43cd72b9 BW |
9858 | case RELAX_UNREACHABLE: |
9859 | *paddable = TRUE; | |
9860 | break; | |
9861 | ||
9862 | case RELAX_FILL_NOP: | |
9863 | (*wide_nops)++; | |
9864 | if (!fragP->tc_frag_data.is_no_density) | |
9865 | (*narrow_nops)++; | |
9866 | break; | |
9867 | ||
9868 | case RELAX_SLOTS: | |
9869 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9870 | { | |
9871 | (*widens)++; | |
9872 | break; | |
9873 | } | |
5bb3703f | 9874 | address += total_frag_text_expansion (fragP); |
e0001a05 NC |
9875 | break; |
9876 | ||
9877 | case RELAX_IMMED: | |
43cd72b9 | 9878 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
9879 | break; |
9880 | ||
9881 | case RELAX_ALIGN_NEXT_OPCODE: | |
9882 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
9883 | *fragPP = fragP; |
9884 | return address; | |
9885 | ||
9886 | case RELAX_MAYBE_UNREACHABLE: | |
9887 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9888 | /* Do nothing. */ | |
e0001a05 NC |
9889 | break; |
9890 | ||
9891 | default: | |
43cd72b9 BW |
9892 | /* Just punt if we don't know the type. */ |
9893 | *fragPP = fragP; | |
9894 | return 0; | |
e0001a05 | 9895 | } |
43cd72b9 | 9896 | } |
c138bc38 | 9897 | else |
43cd72b9 BW |
9898 | { |
9899 | /* Just punt if we don't know the type. */ | |
9900 | *fragPP = fragP; | |
9901 | return 0; | |
9902 | } | |
9903 | fragP = fragP->fr_next; | |
9904 | } | |
9905 | ||
9906 | *fragPP = fragP; | |
9907 | return 0; | |
9908 | } | |
9909 | ||
9910 | ||
7fa3d080 BW |
9911 | static long bytes_to_stretch (fragS *, int, int, int, int); |
9912 | ||
43cd72b9 | 9913 | static long |
7fa3d080 | 9914 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
9915 | { |
9916 | fragS *this_frag = fragP; | |
9917 | long address; | |
9918 | int num_widens = 0; | |
9919 | int wide_nops = 0; | |
9920 | int narrow_nops = 0; | |
9921 | bfd_boolean paddable = FALSE; | |
9922 | offsetT local_opt_diff; | |
9923 | offsetT opt_diff; | |
9924 | offsetT max_diff; | |
9925 | int stretch_amount = 0; | |
9926 | int local_stretch_amount; | |
9927 | int global_stretch_amount; | |
9928 | ||
7fa3d080 BW |
9929 | address = find_address_of_next_align_frag |
9930 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 9931 | |
b5e4a23d BW |
9932 | if (!address) |
9933 | { | |
9934 | if (this_frag->tc_frag_data.is_aligning_branch) | |
9935 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
9936 | else | |
9937 | frag_wane (this_frag); | |
9938 | } | |
9939 | else | |
43cd72b9 BW |
9940 | { |
9941 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
9942 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
9943 | gas_assert (opt_diff >= 0); |
9944 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 9945 | if (max_diff == 0) |
43cd72b9 | 9946 | return 0; |
d2a033cd | 9947 | |
43cd72b9 BW |
9948 | if (fragP) |
9949 | fragP = fragP->fr_next; | |
9950 | ||
9951 | while (fragP && opt_diff < max_diff && address) | |
9952 | { | |
9953 | /* We only use these to determine if we can exit early | |
c138bc38 | 9954 | because there will be plenty of ways to align future |
43cd72b9 | 9955 | align frags. */ |
d77b99c9 | 9956 | int glob_widens = 0; |
43cd72b9 BW |
9957 | int dnn = 0; |
9958 | int dw = 0; | |
9959 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
9960 | address = find_address_of_next_align_frag |
9961 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 9962 | /* If there is a padable portion, then skip. */ |
664df4e4 | 9963 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 9964 | address = 0; |
43cd72b9 | 9965 | |
c138bc38 | 9966 | if (address) |
43cd72b9 BW |
9967 | { |
9968 | offsetT next_m_diff; | |
9969 | offsetT next_o_diff; | |
9970 | ||
9971 | /* Downrange frags haven't had stretch added to them yet. */ | |
9972 | address += stretch; | |
9973 | ||
9974 | /* The address also includes any text expansion from this | |
9975 | frag in a previous pass, but we don't want that. */ | |
9976 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
9977 | ||
9978 | /* Assume we are going to move at least opt_diff. In | |
9979 | reality, we might not be able to, but assuming that | |
9980 | we will helps catch cases where moving opt_diff pushes | |
9981 | the next target from aligned to unaligned. */ | |
9982 | address += opt_diff; | |
9983 | ||
9984 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
9985 | ||
9986 | /* Now cleanup for the adjustments to address. */ | |
9987 | next_o_diff += opt_diff; | |
9988 | next_m_diff += opt_diff; | |
9989 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
9990 | opt_diff = next_o_diff; | |
9991 | if (next_m_diff < max_diff) | |
9992 | max_diff = next_m_diff; | |
9993 | fragP = fragP->fr_next; | |
9994 | } | |
9995 | } | |
d2a033cd | 9996 | |
43cd72b9 BW |
9997 | /* If there are enough wideners in between, do it. */ |
9998 | if (paddable) | |
9999 | { | |
10000 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
10001 | { | |
1beeb686 | 10002 | gas_assert (opt_diff <= (signed) xtensa_fetch_width); |
43cd72b9 BW |
10003 | return opt_diff; |
10004 | } | |
10005 | return 0; | |
10006 | } | |
c138bc38 | 10007 | local_stretch_amount |
43cd72b9 BW |
10008 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
10009 | num_widens, local_opt_diff); | |
c138bc38 BW |
10010 | global_stretch_amount |
10011 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 10012 | num_widens, opt_diff); |
c138bc38 BW |
10013 | /* If the condition below is true, then the frag couldn't |
10014 | stretch the correct amount for the global case, so we just | |
10015 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
10016 | the correct alignment in the global case. */ |
10017 | if (global_stretch_amount < local_stretch_amount) | |
10018 | stretch_amount = local_stretch_amount; | |
10019 | else | |
10020 | stretch_amount = global_stretch_amount; | |
d2a033cd | 10021 | |
43cd72b9 BW |
10022 | if (this_frag->fr_subtype == RELAX_SLOTS |
10023 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 10024 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
10025 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10026 | { | |
10027 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 10028 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 10029 | else |
9c2799c2 | 10030 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
10031 | } |
10032 | } | |
10033 | return stretch_amount; | |
10034 | } | |
10035 | ||
10036 | ||
10037 | /* The idea: widen everything you can to get a target or loop aligned, | |
10038 | then start using NOPs. | |
10039 | ||
43cd72b9 BW |
10040 | wide_nops = the number of wide NOPs available for aligning |
10041 | narrow_nops = the number of narrow NOPs available for aligning | |
10042 | (a subset of wide_nops) | |
10043 | widens = the number of narrow instructions that should be widened | |
10044 | ||
43cd72b9 BW |
10045 | */ |
10046 | ||
10047 | static long | |
7fa3d080 BW |
10048 | bytes_to_stretch (fragS *this_frag, |
10049 | int wide_nops, | |
10050 | int narrow_nops, | |
10051 | int num_widens, | |
10052 | int desired_diff) | |
43cd72b9 | 10053 | { |
19ef5f3d SA |
10054 | int nops_needed; |
10055 | int nop_bytes; | |
10056 | int extra_bytes; | |
43cd72b9 BW |
10057 | int bytes_short = desired_diff - num_widens; |
10058 | ||
3739860c | 10059 | gas_assert (desired_diff >= 0 |
1beeb686 | 10060 | && desired_diff < (signed) xtensa_fetch_width); |
43cd72b9 BW |
10061 | if (desired_diff == 0) |
10062 | return 0; | |
c138bc38 | 10063 | |
9c2799c2 | 10064 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 10065 | |
43cd72b9 BW |
10066 | /* Always prefer widening to NOP-filling. */ |
10067 | if (bytes_short < 0) | |
10068 | { | |
10069 | /* There are enough RELAX_NARROW frags after this one | |
10070 | to align the target without widening this frag in any way. */ | |
10071 | return 0; | |
10072 | } | |
c138bc38 | 10073 | |
43cd72b9 BW |
10074 | if (bytes_short == 0) |
10075 | { | |
10076 | /* Widen every narrow between here and the align target | |
10077 | and the align target will be properly aligned. */ | |
10078 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
10079 | return 0; | |
10080 | else | |
10081 | return 1; | |
10082 | } | |
c138bc38 | 10083 | |
43cd72b9 BW |
10084 | /* From here we will need at least one NOP to get an alignment. |
10085 | However, we may not be able to align at all, in which case, | |
10086 | don't widen. */ | |
19ef5f3d SA |
10087 | nops_needed = desired_diff / 3; |
10088 | ||
10089 | /* If there aren't enough nops, don't widen. */ | |
10090 | if (nops_needed > wide_nops) | |
10091 | return 0; | |
10092 | ||
10093 | /* First try it with all wide nops. */ | |
10094 | nop_bytes = nops_needed * 3; | |
10095 | extra_bytes = desired_diff - nop_bytes; | |
10096 | ||
10097 | if (nop_bytes + num_widens >= desired_diff) | |
43cd72b9 | 10098 | { |
19ef5f3d SA |
10099 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10100 | return 3; | |
10101 | else if (num_widens == extra_bytes) | |
10102 | return 1; | |
10103 | return 0; | |
e0001a05 | 10104 | } |
19ef5f3d SA |
10105 | |
10106 | /* Add a narrow nop. */ | |
10107 | nops_needed++; | |
10108 | nop_bytes += 2; | |
10109 | extra_bytes -= 2; | |
10110 | if (narrow_nops == 0 || nops_needed > wide_nops) | |
10111 | return 0; | |
10112 | ||
10113 | if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) | |
43cd72b9 | 10114 | { |
19ef5f3d SA |
10115 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10116 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
10117 | else if (num_widens == extra_bytes) | |
10118 | return 1; | |
10119 | return 0; | |
10120 | } | |
e0001a05 | 10121 | |
19ef5f3d SA |
10122 | /* Replace a wide nop with a narrow nop--we can get here if |
10123 | extra_bytes was negative in the previous conditional. */ | |
10124 | if (narrow_nops == 1) | |
10125 | return 0; | |
10126 | nop_bytes--; | |
10127 | extra_bytes++; | |
10128 | if (nop_bytes + num_widens >= desired_diff) | |
10129 | { | |
10130 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
10131 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
10132 | else if (num_widens == extra_bytes) | |
10133 | return 1; | |
10134 | return 0; | |
43cd72b9 | 10135 | } |
19ef5f3d SA |
10136 | |
10137 | /* If we can't satisfy any of the above cases, then we can't align | |
10138 | using padding or fill nops. */ | |
43cd72b9 | 10139 | return 0; |
e0001a05 NC |
10140 | } |
10141 | ||
10142 | ||
46888d71 | 10143 | static fragS * |
76a493ab | 10144 | xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP) |
a82c7d90 | 10145 | { |
76a493ab MF |
10146 | symbolS *sym = tinsn->tok[0].X_add_symbol; |
10147 | addressT source = fragP->fr_address; | |
10148 | addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; | |
a82c7d90 | 10149 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
fe6c2f1b | 10150 | size_t i; |
a82c7d90 | 10151 | |
76a493ab MF |
10152 | if (!ts || !ts->index.n_entries) |
10153 | return NULL; | |
a82c7d90 | 10154 | |
76a493ab | 10155 | i = xg_find_best_trampoline (&ts->index, source, target); |
a82c7d90 | 10156 | |
76a493ab | 10157 | return ts->index.entry[i]; |
a82c7d90 DW |
10158 | } |
10159 | ||
10160 | ||
fe6c2f1b MF |
10161 | /* Append jump to sym + offset to the end of the trampoline frag fragP. |
10162 | Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var | |
10163 | and finish the frag if it's full (but don't remove it from the trampoline | |
10164 | frag index). Return fixup for the newly created jump. */ | |
46888d71 | 10165 | static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset) |
fec68fb1 MF |
10166 | { |
10167 | fixS *fixP; | |
10168 | TInsn insn; | |
10169 | xtensa_format fmt; | |
10170 | xtensa_isa isa = xtensa_default_isa; | |
10171 | ||
10172 | gas_assert (fragP->fr_var >= 3); | |
10173 | tinsn_init (&insn); | |
10174 | insn.insn_type = ITYPE_INSN; | |
10175 | insn.opcode = xtensa_j_opcode; | |
10176 | insn.ntok = 1; | |
10177 | set_expr_symbol_offset (&insn.tok[0], sym, offset); | |
10178 | fmt = xg_get_single_format (xtensa_j_opcode); | |
10179 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
10180 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
10181 | xtensa_insnbuf_to_chars (isa, trampoline_buf, | |
10182 | (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3); | |
10183 | fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, TRUE, | |
10184 | BFD_RELOC_XTENSA_SLOT0_OP); | |
10185 | fixP->tc_fix_data.slot = 0; | |
10186 | ||
10187 | fragP->fr_fix += 3; | |
10188 | fragP->fr_var -= 3; | |
10189 | ||
10190 | /* Adjust the jump around this trampoline (if present). */ | |
46888d71 MF |
10191 | if (fragP->tc_frag_data.jump_around_fix) |
10192 | fragP->tc_frag_data.jump_around_fix->fx_offset += 3; | |
fec68fb1 | 10193 | |
fe6c2f1b MF |
10194 | /* Do we have room for more? */ |
10195 | if (xg_is_trampoline_frag_full (fragP)) | |
10196 | { | |
10197 | frag_wane (fragP); | |
10198 | fragP->fr_subtype = 0; | |
10199 | } | |
10200 | ||
fec68fb1 MF |
10201 | return fixP; |
10202 | } | |
10203 | ||
a82c7d90 DW |
10204 | |
10205 | static int | |
46888d71 | 10206 | init_trampoline_frag (fragS *fp) |
a82c7d90 | 10207 | { |
a82c7d90 DW |
10208 | int growth = 0; |
10209 | ||
10210 | if (fp->fr_fix == 0) | |
10211 | { | |
10212 | symbolS *lsym; | |
10213 | char label[10 + 2 * sizeof(fp)]; | |
a82c7d90 | 10214 | |
fec68fb1 | 10215 | sprintf (label, ".L0_TR_%p", fp); |
e01e1cee | 10216 | lsym = (symbolS *) local_symbol_make (label, now_seg, fp, 0); |
a82c7d90 | 10217 | fp->fr_symbol = lsym; |
46888d71 | 10218 | if (fp->tc_frag_data.needs_jump_around) |
a82c7d90 | 10219 | { |
46888d71 | 10220 | fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3); |
a82c7d90 | 10221 | growth = 3; |
a82c7d90 DW |
10222 | } |
10223 | } | |
10224 | return growth; | |
10225 | } | |
10226 | ||
a82c7d90 | 10227 | static int |
148d6384 | 10228 | xg_get_single_symbol_slot (fragS *fragP) |
a82c7d90 | 10229 | { |
148d6384 MF |
10230 | int i; |
10231 | int slot = -1; | |
24e5b4e6 MF |
10232 | |
10233 | for (i = 0; i < MAX_SLOTS; ++i) | |
148d6384 | 10234 | if (fragP->tc_frag_data.slot_symbols[i]) |
24e5b4e6 MF |
10235 | { |
10236 | gas_assert (slot == -1); | |
10237 | slot = i; | |
10238 | } | |
10239 | ||
10240 | gas_assert (slot >= 0 && slot < MAX_SLOTS); | |
a82c7d90 | 10241 | |
148d6384 MF |
10242 | return slot; |
10243 | } | |
10244 | ||
10245 | static fixS * | |
10246 | add_jump_to_trampoline (fragS *tramp, fragS *origfrag) | |
10247 | { | |
10248 | int slot = xg_get_single_symbol_slot (origfrag); | |
10249 | fixS *fixP; | |
10250 | ||
a82c7d90 | 10251 | /* Assemble a jump to the target label in the trampoline frag. */ |
148d6384 MF |
10252 | fixP = xg_append_jump (tramp, |
10253 | origfrag->tc_frag_data.slot_symbols[slot], | |
10254 | origfrag->tc_frag_data.slot_offsets[slot]); | |
fec68fb1 | 10255 | |
a82c7d90 | 10256 | /* Modify the original j to point here. */ |
fec68fb1 | 10257 | origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol; |
24e5b4e6 | 10258 | origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3; |
fec68fb1 | 10259 | |
a82c7d90 | 10260 | /* If trampoline is full, remove it from the list. */ |
fe6c2f1b MF |
10261 | if (xg_is_trampoline_frag_full (tramp)) |
10262 | { | |
10263 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
10264 | size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address); | |
10265 | ||
10266 | gas_assert (ts->index.entry[tr] == tramp); | |
10267 | xg_remove_trampoline_from_index (&ts->index, tr); | |
10268 | } | |
a82c7d90 | 10269 | |
148d6384 | 10270 | return fixP; |
a82c7d90 DW |
10271 | } |
10272 | ||
10273 | ||
e0001a05 | 10274 | static long |
7fa3d080 BW |
10275 | relax_frag_immed (segT segP, |
10276 | fragS *fragP, | |
10277 | long stretch, | |
10278 | int min_steps, | |
10279 | xtensa_format fmt, | |
10280 | int slot, | |
10281 | int *stretched_p, | |
10282 | bfd_boolean estimate_only) | |
e0001a05 | 10283 | { |
43cd72b9 | 10284 | TInsn tinsn; |
e0001a05 NC |
10285 | int old_size; |
10286 | bfd_boolean negatable_branch = FALSE; | |
10287 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 10288 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 10289 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
10290 | IStack istack; |
10291 | offsetT frag_offset; | |
10292 | int num_steps; | |
e0001a05 | 10293 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 10294 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 10295 | |
9c2799c2 | 10296 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10297 | |
b5e4a23d BW |
10298 | xg_clear_vinsn (&cur_vinsn); |
10299 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 10300 | if (cur_vinsn.num_slots > 1) |
def13efb | 10301 | from_wide_insn = TRUE; |
43cd72b9 | 10302 | |
b5e4a23d | 10303 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 10304 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 10305 | |
64b607e6 | 10306 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 10307 | return 0; |
e0001a05 | 10308 | |
b08b5071 | 10309 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10310 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 10311 | |
43cd72b9 | 10312 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 10313 | |
43cd72b9 | 10314 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10315 | |
10316 | /* Special case: replace a branch to the next instruction with a NOP. | |
10317 | This is required to work around a hardware bug in T1040.0 and also | |
10318 | serves as an optimization. */ | |
10319 | ||
10320 | if (branch_jmp_to_next | |
10321 | && ((old_size == 2) || (old_size == 3)) | |
10322 | && !next_frag_is_loop_target (fragP)) | |
10323 | return 0; | |
10324 | ||
10325 | /* Here is the fun stuff: Get the immediate field from this | |
10326 | instruction. If it fits, we are done. If not, find the next | |
10327 | instruction sequence that fits. */ | |
10328 | ||
10329 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10330 | istack_init (&istack); | |
43cd72b9 | 10331 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 10332 | min_steps, stretch); |
9c2799c2 | 10333 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 10334 | |
43cd72b9 | 10335 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
10336 | |
10337 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 10338 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
10339 | literal_diff |
10340 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 10341 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
10342 | |
10343 | if (from_wide_insn) | |
43cd72b9 | 10344 | { |
2276bc20 BW |
10345 | int first = 0; |
10346 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
10347 | first++; | |
10348 | ||
43cd72b9 BW |
10349 | num_text_bytes += old_size; |
10350 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
10351 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
10352 | else |
10353 | { | |
10354 | /* The first instruction in the relaxed sequence will go after | |
10355 | the current wide instruction, and thus its symbolic immediates | |
10356 | might not fit. */ | |
3739860c | 10357 | |
2276bc20 | 10358 | istack_init (&istack); |
3739860c | 10359 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, |
2276bc20 BW |
10360 | frag_offset + old_size, |
10361 | min_steps, stretch + old_size); | |
9c2799c2 | 10362 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 | 10363 | |
3739860c | 10364 | fragP->tc_frag_data.slot_subtypes[slot] |
2276bc20 BW |
10365 | = (int) RELAX_IMMED + num_steps; |
10366 | ||
10367 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
3739860c | 10368 | literal_diff |
2276bc20 | 10369 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; |
3739860c | 10370 | |
2276bc20 BW |
10371 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; |
10372 | } | |
43cd72b9 | 10373 | } |
def13efb | 10374 | |
43cd72b9 BW |
10375 | total_text_diff = num_text_bytes - old_size; |
10376 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
10377 | |
10378 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
10379 | gas_assert (num_text_bytes >= 0); |
10380 | gas_assert (literal_diff >= 0); | |
10381 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 10382 | |
43cd72b9 BW |
10383 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
10384 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
10385 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
10386 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
10387 | |
10388 | /* Find the associated expandable literal for this. */ | |
10389 | if (literal_diff != 0) | |
10390 | { | |
2276bc20 | 10391 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10392 | if (lit_fragP) |
10393 | { | |
9c2799c2 | 10394 | gas_assert (literal_diff == 4); |
e0001a05 NC |
10395 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
10396 | ||
10397 | /* We expect that the literal section state has NOT been | |
10398 | modified yet. */ | |
9c2799c2 | 10399 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
10400 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
10401 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
10402 | ||
10403 | /* We need to mark this section for another iteration | |
10404 | of relaxation. */ | |
10405 | (*stretched_p)++; | |
10406 | } | |
10407 | } | |
10408 | ||
43cd72b9 | 10409 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 10410 | update_next_frag_state (fragP); |
e0001a05 | 10411 | |
a82c7d90 DW |
10412 | /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ |
10413 | if (istack.ninsn > 2 && | |
10414 | istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && | |
10415 | istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && | |
10416 | istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) | |
10417 | { | |
10418 | TInsn *jinsn = &istack.insn[istack.ninsn - 2]; | |
148d6384 MF |
10419 | struct trampoline_seg *ts = find_trampoline_seg (segP); |
10420 | struct trampoline_chain *tc = NULL; | |
10421 | ||
10422 | if (ts && | |
10423 | !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, | |
10424 | total_text_diff)) | |
10425 | { | |
10426 | int s = xg_get_single_symbol_slot (fragP); | |
10427 | addressT offset = fragP->tc_frag_data.slot_offsets[s]; | |
10428 | ||
10429 | tc = xg_find_best_eq_target (ts, fragP->fr_address, | |
10430 | &fragP->tc_frag_data.slot_symbols[s], | |
10431 | &offset); | |
10432 | ||
10433 | if (!tc) | |
10434 | tc = xg_create_trampoline_chain (ts, | |
10435 | fragP->tc_frag_data.slot_symbols[s], | |
10436 | offset); | |
10437 | fragP->tc_frag_data.slot_offsets[s] = offset; | |
10438 | tinsn_immed_from_frag (jinsn, fragP, s); | |
10439 | } | |
a82c7d90 | 10440 | |
148d6384 MF |
10441 | if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, |
10442 | total_text_diff)) | |
a82c7d90 | 10443 | { |
76a493ab | 10444 | fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP); |
a82c7d90 DW |
10445 | |
10446 | if (tf) | |
10447 | { | |
148d6384 MF |
10448 | fixS *fixP; |
10449 | ||
10450 | this_text_diff += init_trampoline_frag (tf) + 3; | |
10451 | fixP = add_jump_to_trampoline (tf, fragP); | |
10452 | xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, | |
10453 | fixP->fx_where); | |
10454 | fragP->tc_frag_data.relax_seen = FALSE; | |
a82c7d90 DW |
10455 | } |
10456 | else | |
10457 | { | |
10458 | /* If target symbol is undefined, assume it will reach once linked. */ | |
10459 | expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; | |
10460 | ||
10461 | if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) | |
10462 | { | |
10463 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10464 | _("jump target out of range; no usable trampoline found")); | |
10465 | } | |
10466 | } | |
10467 | } | |
10468 | } | |
10469 | ||
43cd72b9 | 10470 | return this_text_diff; |
e0001a05 NC |
10471 | } |
10472 | ||
10473 | \f | |
10474 | /* md_convert_frag Hook and Helper Functions. */ | |
10475 | ||
7fa3d080 BW |
10476 | static void convert_frag_align_next_opcode (fragS *); |
10477 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
10478 | static void convert_frag_fill_nop (fragS *); | |
10479 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
10480 | ||
e0001a05 | 10481 | void |
7fa3d080 | 10482 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 10483 | { |
43cd72b9 BW |
10484 | static xtensa_insnbuf vbuf = NULL; |
10485 | xtensa_isa isa = xtensa_default_isa; | |
10486 | int slot; | |
10487 | int num_slots; | |
10488 | xtensa_format fmt; | |
3b4dbbbf | 10489 | const char *file_name; |
d77b99c9 | 10490 | unsigned line; |
e0001a05 | 10491 | |
3b4dbbbf | 10492 | file_name = as_where (&line); |
e0001a05 NC |
10493 | new_logical_line (fragp->fr_file, fragp->fr_line); |
10494 | ||
10495 | switch (fragp->fr_subtype) | |
10496 | { | |
10497 | case RELAX_ALIGN_NEXT_OPCODE: | |
10498 | /* Always convert. */ | |
10499 | convert_frag_align_next_opcode (fragp); | |
10500 | break; | |
10501 | ||
10502 | case RELAX_DESIRE_ALIGN: | |
10503 | /* Do nothing. If not aligned already, too bad. */ | |
10504 | break; | |
10505 | ||
43cd72b9 BW |
10506 | case RELAX_LITERAL: |
10507 | case RELAX_LITERAL_FINAL: | |
10508 | break; | |
10509 | ||
10510 | case RELAX_SLOTS: | |
10511 | if (vbuf == NULL) | |
10512 | vbuf = xtensa_insnbuf_alloc (isa); | |
10513 | ||
d77b99c9 BW |
10514 | xtensa_insnbuf_from_chars |
10515 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
10516 | fmt = xtensa_format_decode (isa, vbuf); |
10517 | num_slots = xtensa_format_num_slots (isa, fmt); | |
10518 | ||
10519 | for (slot = 0; slot < num_slots; slot++) | |
10520 | { | |
10521 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
10522 | { | |
10523 | case RELAX_NARROW: | |
10524 | convert_frag_narrow (sec, fragp, fmt, slot); | |
10525 | break; | |
10526 | ||
10527 | case RELAX_IMMED: | |
10528 | case RELAX_IMMED_STEP1: | |
10529 | case RELAX_IMMED_STEP2: | |
b81bf389 | 10530 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
10531 | /* Place the immediate. */ |
10532 | convert_frag_immed | |
10533 | (sec, fragp, | |
10534 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
10535 | fmt, slot); | |
10536 | break; | |
10537 | ||
10538 | default: | |
10539 | /* This is OK because some slots could have | |
10540 | relaxations and others have none. */ | |
10541 | break; | |
10542 | } | |
10543 | } | |
10544 | break; | |
10545 | ||
10546 | case RELAX_UNREACHABLE: | |
10547 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
10548 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
10549 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
10550 | frag_wane (fragp); | |
e0001a05 NC |
10551 | break; |
10552 | ||
43cd72b9 BW |
10553 | case RELAX_MAYBE_UNREACHABLE: |
10554 | case RELAX_MAYBE_DESIRE_ALIGN: | |
10555 | frag_wane (fragp); | |
e0001a05 NC |
10556 | break; |
10557 | ||
43cd72b9 BW |
10558 | case RELAX_FILL_NOP: |
10559 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
10560 | break; |
10561 | ||
10562 | case RELAX_LITERAL_NR: | |
10563 | if (use_literal_section) | |
10564 | { | |
10565 | /* This should have been handled during relaxation. When | |
10566 | relaxing a code segment, literals sometimes need to be | |
10567 | added to the corresponding literal segment. If that | |
10568 | literal segment has already been relaxed, then we end up | |
10569 | in this situation. Marking the literal segments as data | |
10570 | would make this happen less often (since GAS always relaxes | |
10571 | code before data), but we could still get into trouble if | |
10572 | there are instructions in a segment that is not marked as | |
10573 | containing code. Until we can implement a better solution, | |
10574 | cheat and adjust the addresses of all the following frags. | |
10575 | This could break subsequent alignments, but the linker's | |
10576 | literal coalescing will do that anyway. */ | |
10577 | ||
10578 | fragS *f; | |
10579 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 10580 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
10581 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
10582 | fragp->fr_var -= 4; | |
10583 | fragp->fr_fix += 4; | |
10584 | for (f = fragp->fr_next; f; f = f->fr_next) | |
10585 | f->fr_address += 4; | |
10586 | } | |
10587 | else | |
10588 | as_bad (_("invalid relaxation fragment result")); | |
10589 | break; | |
a82c7d90 DW |
10590 | |
10591 | case RELAX_TRAMPOLINE: | |
10592 | break; | |
e0001a05 NC |
10593 | } |
10594 | ||
10595 | fragp->fr_var = 0; | |
10596 | new_logical_line (file_name, line); | |
10597 | } | |
10598 | ||
10599 | ||
7fa3d080 BW |
10600 | static void |
10601 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
10602 | { |
10603 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
10604 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
10605 | addressT aligned_address; | |
d77b99c9 BW |
10606 | offsetT fill_size; |
10607 | int nop, nop_count; | |
e0001a05 NC |
10608 | |
10609 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
10610 | fragp->fr_fix); | |
10611 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
10612 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
10613 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
10614 | ||
d77b99c9 | 10615 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 10616 | { |
d77b99c9 BW |
10617 | int nop_size; |
10618 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
10619 | |
10620 | assemble_nop (nop_size, nop_buf); | |
10621 | nop_buf += nop_size; | |
10622 | } | |
10623 | ||
10624 | fragp->fr_fix += fill_size; | |
10625 | fragp->fr_var -= fill_size; | |
10626 | } | |
10627 | ||
10628 | ||
10629 | static void | |
7fa3d080 | 10630 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 10631 | { |
43cd72b9 | 10632 | TInsn tinsn, single_target; |
84b08ed9 | 10633 | int size, old_size, diff; |
e0001a05 NC |
10634 | offsetT frag_offset; |
10635 | ||
9c2799c2 | 10636 | gas_assert (slot == 0); |
43cd72b9 BW |
10637 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
10638 | ||
b5e4a23d | 10639 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 10640 | { |
9c2799c2 | 10641 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
10642 | || fragP->tc_frag_data.text_expansion[0] == 0); |
10643 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
10644 | fmt, slot); | |
10645 | return; | |
10646 | } | |
10647 | ||
10648 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
10649 | { |
10650 | /* No conversion. */ | |
10651 | fragP->fr_var = 0; | |
10652 | return; | |
10653 | } | |
10654 | ||
9c2799c2 | 10655 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10656 | |
43cd72b9 BW |
10657 | /* Frags in this relaxation state should only contain |
10658 | single instruction bundles. */ | |
10659 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
10660 | |
10661 | /* Just convert it to a wide form.... */ | |
10662 | size = 0; | |
43cd72b9 | 10663 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
10664 | |
10665 | tinsn_init (&single_target); | |
10666 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10667 | ||
84b08ed9 | 10668 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
10669 | { |
10670 | as_bad (_("unable to widen instruction")); | |
10671 | return; | |
10672 | } | |
10673 | ||
10674 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
10675 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
10676 | frag_offset, TRUE); | |
e0001a05 NC |
10677 | |
10678 | diff = size - old_size; | |
9c2799c2 NC |
10679 | gas_assert (diff >= 0); |
10680 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
10681 | fragP->fr_var -= diff; |
10682 | fragP->fr_fix += diff; | |
10683 | ||
10684 | /* clean it up */ | |
10685 | fragP->fr_var = 0; | |
10686 | } | |
10687 | ||
10688 | ||
10689 | static void | |
7fa3d080 | 10690 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
10691 | { |
10692 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
10693 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10694 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
10695 | - fragP->fr_address - fragP->fr_fix)); |
10696 | if (size == 0) | |
10697 | { | |
10698 | /* No conversion. */ | |
10699 | fragP->fr_var = 0; | |
10700 | return; | |
10701 | } | |
10702 | assemble_nop (size, loc); | |
10703 | fragP->tc_frag_data.is_insn = TRUE; | |
10704 | fragP->fr_var -= size; | |
10705 | fragP->fr_fix += size; | |
10706 | frag_wane (fragP); | |
10707 | } | |
10708 | ||
10709 | ||
7fa3d080 BW |
10710 | static fixS *fix_new_exp_in_seg |
10711 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
10712 | bfd_reloc_code_real_type); | |
7fa3d080 | 10713 | |
43cd72b9 | 10714 | static void |
7fa3d080 BW |
10715 | convert_frag_immed (segT segP, |
10716 | fragS *fragP, | |
10717 | int min_steps, | |
10718 | xtensa_format fmt, | |
10719 | int slot) | |
e0001a05 NC |
10720 | { |
10721 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 10722 | TInsn orig_tinsn; |
e0001a05 | 10723 | bfd_boolean expanded = FALSE; |
e0001a05 | 10724 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 10725 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 10726 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 10727 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
10728 | int bytes; |
10729 | bfd_boolean is_loop; | |
e0001a05 | 10730 | |
9c2799c2 | 10731 | gas_assert (fr_opcode != NULL); |
e0001a05 | 10732 | |
b5e4a23d | 10733 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 10734 | |
b5e4a23d | 10735 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 10736 | if (cur_vinsn.num_slots > 1) |
def13efb | 10737 | from_wide_insn = TRUE; |
e0001a05 | 10738 | |
b5e4a23d | 10739 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
10740 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
10741 | ||
10742 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 10743 | |
b08b5071 | 10744 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10745 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
10746 | |
10747 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
10748 | { | |
10749 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
10750 | bytes = xtensa_format_length (isa, fmt); |
10751 | if (bytes >= 4) | |
10752 | { | |
b5e4a23d BW |
10753 | cur_vinsn.slots[slot].opcode = |
10754 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
10755 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
10756 | } |
10757 | else | |
10758 | { | |
10759 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10760 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 10761 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
10762 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
10763 | } | |
e7da6241 | 10764 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 10765 | xtensa_insnbuf_to_chars |
b5e4a23d | 10766 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
10767 | fragP->fr_var = 0; |
10768 | } | |
7c834684 | 10769 | else |
e0001a05 | 10770 | { |
43cd72b9 BW |
10771 | /* Here is the fun stuff: Get the immediate field from this |
10772 | instruction. If it fits, we're done. If not, find the next | |
10773 | instruction sequence that fits. */ | |
10774 | ||
e0001a05 NC |
10775 | IStack istack; |
10776 | int i; | |
10777 | symbolS *lit_sym = NULL; | |
10778 | int total_size = 0; | |
43cd72b9 | 10779 | int target_offset = 0; |
e0001a05 NC |
10780 | int old_size; |
10781 | int diff; | |
10782 | symbolS *gen_label = NULL; | |
10783 | offsetT frag_offset; | |
43cd72b9 | 10784 | bfd_boolean first = TRUE; |
e0001a05 | 10785 | |
43cd72b9 | 10786 | /* It does not fit. Find something that does and |
e0001a05 | 10787 | convert immediately. */ |
43cd72b9 | 10788 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 10789 | istack_init (&istack); |
43cd72b9 | 10790 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
10791 | segP, fragP, frag_offset, min_steps, 0); |
10792 | ||
43cd72b9 | 10793 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10794 | |
10795 | /* Assemble this right inline. */ | |
10796 | ||
10797 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 10798 | target_offset = 0; |
e0001a05 NC |
10799 | for (i = 0; i < istack.ninsn; i++) |
10800 | { | |
43cd72b9 | 10801 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10802 | fragS *lit_frag; |
10803 | ||
43cd72b9 | 10804 | switch (tinsn->insn_type) |
e0001a05 NC |
10805 | { |
10806 | case ITYPE_LITERAL: | |
10807 | if (lit_sym != NULL) | |
10808 | as_bad (_("multiple literals in expansion")); | |
10809 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 10810 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10811 | if (lit_frag == NULL) |
10812 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 10813 | if (tinsn->ntok != 1) |
e0001a05 NC |
10814 | as_bad (_("number of literal tokens != 1")); |
10815 | ||
10816 | /* Set the literal symbol and add a fixup. */ | |
10817 | lit_sym = lit_frag->fr_symbol; | |
10818 | break; | |
10819 | ||
10820 | case ITYPE_LABEL: | |
43cd72b9 BW |
10821 | if (align_targets && !is_loop) |
10822 | { | |
10823 | fragS *unreach = fragP->fr_next; | |
10824 | while (!(unreach->fr_type == rs_machine_dependent | |
10825 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
10826 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
10827 | { | |
10828 | unreach = unreach->fr_next; | |
10829 | } | |
10830 | ||
9c2799c2 | 10831 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
10832 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
10833 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
10834 | ||
10835 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
10836 | } | |
9c2799c2 | 10837 | gas_assert (gen_label == NULL); |
e01e1cee | 10838 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, fragP, |
43cd72b9 | 10839 | fr_opcode - fragP->fr_literal |
e01e1cee | 10840 | + target_offset); |
e0001a05 NC |
10841 | break; |
10842 | ||
10843 | case ITYPE_INSN: | |
def13efb | 10844 | if (first && from_wide_insn) |
43cd72b9 BW |
10845 | { |
10846 | target_offset += xtensa_format_length (isa, fmt); | |
10847 | first = FALSE; | |
10848 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10849 | target_offset += xg_get_single_size (tinsn->opcode); | |
10850 | } | |
10851 | else | |
10852 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
10853 | break; |
10854 | } | |
10855 | } | |
10856 | ||
10857 | total_size = 0; | |
43cd72b9 | 10858 | first = TRUE; |
e0001a05 NC |
10859 | for (i = 0; i < istack.ninsn; i++) |
10860 | { | |
43cd72b9 | 10861 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10862 | fragS *lit_frag; |
10863 | int size; | |
10864 | segT target_seg; | |
43cd72b9 | 10865 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 10866 | |
43cd72b9 | 10867 | switch (tinsn->insn_type) |
e0001a05 NC |
10868 | { |
10869 | case ITYPE_LITERAL: | |
43cd72b9 BW |
10870 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
10871 | /* Already checked. */ | |
9c2799c2 NC |
10872 | gas_assert (lit_frag != NULL); |
10873 | gas_assert (lit_sym != NULL); | |
10874 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 10875 | /* Add a fixup. */ |
e0001a05 | 10876 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 10877 | gas_assert (target_seg); |
28dbbc02 | 10878 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 10879 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 10880 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
10881 | break; |
10882 | ||
10883 | case ITYPE_LABEL: | |
10884 | break; | |
10885 | ||
10886 | case ITYPE_INSN: | |
43cd72b9 BW |
10887 | xg_resolve_labels (tinsn, gen_label); |
10888 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 10889 | if (from_wide_insn && first) |
43cd72b9 BW |
10890 | { |
10891 | first = FALSE; | |
10892 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10893 | { | |
b5e4a23d | 10894 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
10895 | } |
10896 | else | |
10897 | { | |
b5e4a23d | 10898 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 10899 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 10900 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 10901 | } |
b5e4a23d BW |
10902 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
10903 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 10904 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
10905 | fragP->tc_frag_data.is_insn = TRUE; |
10906 | size = xtensa_format_length (isa, fmt); | |
10907 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10908 | { | |
43cd72b9 | 10909 | xg_emit_insn_to_buf |
b2d179be | 10910 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
10911 | immed_instr - fragP->fr_literal + size, TRUE); |
10912 | size += xg_get_single_size (tinsn->opcode); | |
10913 | } | |
10914 | } | |
10915 | else | |
10916 | { | |
43cd72b9 | 10917 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 10918 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 10919 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 10920 | } |
e0001a05 | 10921 | immed_instr += size; |
43cd72b9 | 10922 | total_size += size; |
e0001a05 NC |
10923 | break; |
10924 | } | |
10925 | } | |
10926 | ||
10927 | diff = total_size - old_size; | |
9c2799c2 | 10928 | gas_assert (diff >= 0); |
e0001a05 NC |
10929 | if (diff != 0) |
10930 | expanded = TRUE; | |
9c2799c2 | 10931 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
10932 | fragP->fr_var -= diff; |
10933 | fragP->fr_fix += diff; | |
10934 | } | |
10935 | ||
e0001a05 | 10936 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 10937 | if (is_loop) |
e0001a05 NC |
10938 | { |
10939 | symbolS *sym; | |
43cd72b9 | 10940 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
10941 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10942 | { | |
10943 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10944 | return; | |
10945 | } | |
43cd72b9 | 10946 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
10947 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10948 | { | |
10949 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10950 | return; | |
10951 | } | |
10952 | } | |
10953 | ||
43cd72b9 | 10954 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
10955 | { |
10956 | /* Add an expansion note on the expanded instruction. */ | |
10957 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 10958 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 10959 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
10960 | } |
10961 | } | |
10962 | ||
10963 | ||
10964 | /* Add a new fix expression into the desired segment. We have to | |
10965 | switch to that segment to do this. */ | |
10966 | ||
10967 | static fixS * | |
7fa3d080 BW |
10968 | fix_new_exp_in_seg (segT new_seg, |
10969 | subsegT new_subseg, | |
10970 | fragS *frag, | |
10971 | int where, | |
10972 | int size, | |
10973 | expressionS *exp, | |
10974 | int pcrel, | |
10975 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
10976 | { |
10977 | fixS *new_fix; | |
10978 | segT seg = now_seg; | |
10979 | subsegT subseg = now_subseg; | |
43cd72b9 | 10980 | |
9c2799c2 | 10981 | gas_assert (new_seg != 0); |
e0001a05 NC |
10982 | subseg_set (new_seg, new_subseg); |
10983 | ||
e0001a05 NC |
10984 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
10985 | subseg_set (seg, subseg); | |
10986 | return new_fix; | |
10987 | } | |
10988 | ||
10989 | ||
b08b5071 BW |
10990 | \f |
10991 | /* A map that keeps information on a per-subsegment basis. This is | |
10992 | maintained during initial assembly, but is invalid once the | |
10993 | subsegments are smashed together. I.E., it cannot be used during | |
10994 | the relaxation. */ | |
e0001a05 | 10995 | |
b08b5071 | 10996 | typedef struct subseg_map_struct |
e0001a05 | 10997 | { |
b08b5071 BW |
10998 | /* the key */ |
10999 | segT seg; | |
11000 | subsegT subseg; | |
e0001a05 | 11001 | |
b08b5071 BW |
11002 | /* the data */ |
11003 | unsigned flags; | |
11004 | float total_freq; /* fall-through + branch target frequency */ | |
11005 | float target_freq; /* branch target frequency alone */ | |
11006 | ||
11007 | struct subseg_map_struct *next; | |
11008 | } subseg_map; | |
e0001a05 | 11009 | |
e0001a05 | 11010 | |
e0001a05 NC |
11011 | static subseg_map *sseg_map = NULL; |
11012 | ||
43cd72b9 | 11013 | static subseg_map * |
7fa3d080 | 11014 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
11015 | { |
11016 | subseg_map *subseg_e; | |
11017 | ||
11018 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 11019 | { |
43cd72b9 | 11020 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 11021 | break; |
e0001a05 | 11022 | } |
b08b5071 BW |
11023 | return subseg_e; |
11024 | } | |
11025 | ||
11026 | ||
11027 | static subseg_map * | |
11028 | add_subseg_info (segT seg, subsegT subseg) | |
11029 | { | |
325801bd | 11030 | subseg_map *subseg_e = XNEW (subseg_map); |
43cd72b9 BW |
11031 | memset (subseg_e, 0, sizeof (subseg_map)); |
11032 | subseg_e->seg = seg; | |
11033 | subseg_e->subseg = subseg; | |
11034 | subseg_e->flags = 0; | |
11035 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
11036 | subseg_e->target_freq = 1.0; |
11037 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
11038 | subseg_e->next = sseg_map; |
11039 | sseg_map = subseg_e; | |
43cd72b9 BW |
11040 | return subseg_e; |
11041 | } | |
e0001a05 | 11042 | |
7fa3d080 BW |
11043 | |
11044 | static unsigned | |
11045 | get_last_insn_flags (segT seg, subsegT subseg) | |
11046 | { | |
11047 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11048 | if (subseg_e) |
11049 | return subseg_e->flags; | |
11050 | return 0; | |
7fa3d080 BW |
11051 | } |
11052 | ||
11053 | ||
43cd72b9 | 11054 | static void |
7fa3d080 BW |
11055 | set_last_insn_flags (segT seg, |
11056 | subsegT subseg, | |
11057 | unsigned fl, | |
11058 | bfd_boolean val) | |
43cd72b9 BW |
11059 | { |
11060 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11061 | if (! subseg_e) |
11062 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
11063 | if (val) |
11064 | subseg_e->flags |= fl; | |
11065 | else | |
11066 | subseg_e->flags &= ~fl; | |
11067 | } | |
11068 | ||
b08b5071 BW |
11069 | |
11070 | static float | |
11071 | get_subseg_total_freq (segT seg, subsegT subseg) | |
11072 | { | |
11073 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11074 | if (subseg_e) | |
11075 | return subseg_e->total_freq; | |
11076 | return 1.0; | |
11077 | } | |
11078 | ||
11079 | ||
11080 | static float | |
11081 | get_subseg_target_freq (segT seg, subsegT subseg) | |
11082 | { | |
11083 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11084 | if (subseg_e) | |
11085 | return subseg_e->target_freq; | |
11086 | return 1.0; | |
11087 | } | |
11088 | ||
11089 | ||
11090 | static void | |
11091 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
11092 | { | |
11093 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11094 | if (! subseg_e) | |
11095 | subseg_e = add_subseg_info (seg, subseg); | |
11096 | subseg_e->total_freq = total_f; | |
11097 | subseg_e->target_freq = target_f; | |
11098 | } | |
11099 | ||
e0001a05 NC |
11100 | \f |
11101 | /* Segment Lists and emit_state Stuff. */ | |
11102 | ||
e0001a05 | 11103 | static void |
7fa3d080 | 11104 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
11105 | { |
11106 | head = head->next; | |
11107 | while (head) | |
11108 | { | |
11109 | segT literal_section = head->seg; | |
11110 | ||
11111 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 11112 | gas_assert (literal_section); |
69852798 AM |
11113 | if (literal_section != stdoutput->sections) |
11114 | { | |
11115 | bfd_section_list_remove (stdoutput, literal_section); | |
11116 | bfd_section_list_prepend (stdoutput, literal_section); | |
11117 | } | |
e0001a05 NC |
11118 | head = head->next; |
11119 | } | |
11120 | } | |
11121 | ||
11122 | ||
7fa3d080 BW |
11123 | static void mark_literal_frags (seg_list *); |
11124 | ||
947fa914 MF |
11125 | static void |
11126 | xg_promote_candidate_litpool (struct litpool_seg *lps, | |
11127 | struct litpool_frag *lp) | |
11128 | { | |
11129 | fragS *poolbeg; | |
11130 | fragS *poolend; | |
11131 | symbolS *lsym; | |
11132 | char label[10 + 2 * sizeof (fragS *)]; | |
11133 | ||
11134 | poolbeg = lp->fragP; | |
11135 | lp->priority = 1; | |
11136 | poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN; | |
11137 | poolend = poolbeg->fr_next; | |
11138 | gas_assert (poolend->fr_type == rs_machine_dependent && | |
11139 | poolend->fr_subtype == RELAX_LITERAL_POOL_END); | |
11140 | /* Create a local symbol pointing to the | |
11141 | end of the pool. */ | |
11142 | sprintf (label, ".L0_LT_%p", poolbeg); | |
e01e1cee | 11143 | lsym = (symbolS *) local_symbol_make (label, lps->seg, poolend, 0); |
947fa914 MF |
11144 | poolbeg->fr_symbol = lsym; |
11145 | /* Rest is done in xtensa_relax_frag. */ | |
11146 | } | |
11147 | ||
cd665a94 MF |
11148 | static struct litpool_frag *xg_find_litpool (struct litpool_seg *lps, |
11149 | struct litpool_frag *lpf, | |
11150 | addressT addr) | |
11151 | { | |
11152 | struct litpool_frag *lp = lpf->prev; | |
11153 | ||
11154 | gas_assert (lp->fragP); | |
11155 | ||
11156 | while (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11157 | { | |
11158 | lp = lp->prev; | |
11159 | if (lp->fragP == NULL) | |
11160 | { | |
11161 | /* End of list; have to bite the bullet. | |
11162 | Take the nearest. */ | |
11163 | lp = lpf->prev; | |
11164 | break; | |
11165 | } | |
11166 | /* Does it (conservatively) reach? */ | |
11167 | if (addr - lp->addr <= 128 * 1024) | |
11168 | { | |
11169 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
11170 | lp->literal_count < MAX_POOL_LITERALS) | |
11171 | { | |
11172 | /* Found a good one. */ | |
11173 | break; | |
11174 | } | |
11175 | else if (lp->prev->fragP && | |
11176 | addr - lp->prev->addr > 128 * 1024 && | |
11177 | lp->prev->literal_count < MAX_POOL_LITERALS) | |
11178 | { | |
11179 | /* This is still a "candidate" but the next one | |
11180 | will be too far away, so revert to the nearest | |
11181 | one, convert it and add the jump around. */ | |
11182 | lp = lpf->prev; | |
11183 | break; | |
11184 | } | |
11185 | } | |
11186 | } | |
11187 | ||
11188 | if (lp->literal_count >= MAX_POOL_LITERALS) | |
11189 | { | |
11190 | lp = lpf->prev; | |
11191 | while (lp && lp->fragP && lp->literal_count >= MAX_POOL_LITERALS) | |
11192 | { | |
11193 | lp = lp->prev; | |
11194 | } | |
11195 | gas_assert (lp); | |
11196 | } | |
11197 | ||
11198 | gas_assert (lp && lp->fragP && lp->literal_count < MAX_POOL_LITERALS); | |
11199 | ++lp->literal_count; | |
11200 | ||
11201 | /* Convert candidate and add the jump around. */ | |
11202 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11203 | xg_promote_candidate_litpool (lps, lp); | |
11204 | ||
11205 | return lp; | |
11206 | } | |
11207 | ||
d0ad159d MF |
11208 | static bfd_boolean xtensa_is_init_fini (segT seg) |
11209 | { | |
11210 | if (!seg) | |
11211 | return 0; | |
11212 | return strcmp (segment_name (seg), INIT_SECTION_NAME) == 0 | |
11213 | || strcmp (segment_name (seg), FINI_SECTION_NAME) == 0; | |
11214 | } | |
11215 | ||
7fa3d080 | 11216 | static void |
f8aecf3c | 11217 | xtensa_assign_litpool_addresses (void) |
e0001a05 | 11218 | { |
b46824bd | 11219 | struct litpool_seg *lps; |
b46824bd MF |
11220 | |
11221 | for (lps = litpool_seg_list.next; lps; lps = lps->next) | |
11222 | { | |
11223 | frchainS *frchP = seg_info (lps->seg)->frchainP; | |
11224 | struct litpool_frag *lpf = lps->frag_list.next; | |
11225 | addressT addr = 0; | |
11226 | ||
d0ad159d MF |
11227 | if (xtensa_is_init_fini (lps->seg)) |
11228 | continue; | |
11229 | ||
b46824bd MF |
11230 | for ( ; frchP; frchP = frchP->frch_next) |
11231 | { | |
11232 | fragS *fragP; | |
11233 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
11234 | { | |
11235 | if (lpf && fragP == lpf->fragP) | |
11236 | { | |
11237 | gas_assert(fragP->fr_type == rs_machine_dependent && | |
11238 | (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN || | |
11239 | fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)); | |
11240 | /* Found a litpool location. */ | |
11241 | lpf->addr = addr; | |
11242 | lpf = lpf->next; | |
11243 | } | |
11244 | if (fragP->fr_type == rs_machine_dependent && | |
11245 | fragP->fr_subtype == RELAX_SLOTS) | |
11246 | { | |
11247 | int slot; | |
11248 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
11249 | { | |
d0ad159d MF |
11250 | fragS *litfrag = fragP->tc_frag_data.literal_frags[slot]; |
11251 | ||
11252 | if (litfrag | |
11253 | && litfrag->tc_frag_data.is_literal | |
11254 | && !litfrag->tc_frag_data.literal_frag) | |
b46824bd | 11255 | { |
d0ad159d MF |
11256 | /* L32R referring .literal or generated as a result |
11257 | of relaxation. Point its literal to the nearest | |
11258 | litpool preferring non-"candidate" positions to | |
11259 | avoid the jump-around. */ | |
11260 | ||
11261 | struct litpool_frag *lp; | |
11262 | ||
11263 | lp = xg_find_litpool (lps, lpf, addr); | |
11264 | /* Take earliest use of this literal to avoid | |
11265 | forward refs. */ | |
11266 | litfrag->tc_frag_data.literal_frag = lp->fragP; | |
b46824bd MF |
11267 | } |
11268 | } | |
11269 | } | |
11270 | addr += fragP->fr_fix; | |
11271 | if (fragP->fr_type == rs_fill) | |
11272 | addr += fragP->fr_offset; | |
11273 | } | |
11274 | } | |
11275 | } | |
f8aecf3c | 11276 | } |
b46824bd | 11277 | |
f8aecf3c MF |
11278 | static void |
11279 | xtensa_move_literals (void) | |
11280 | { | |
11281 | seg_list *segment; | |
11282 | frchainS *frchain_from, *frchain_to; | |
11283 | fragS *search_frag, *next_frag, *literal_pool, *insert_after; | |
11284 | fragS **frag_splice; | |
11285 | emit_state state; | |
11286 | segT dest_seg; | |
11287 | fixS *fix, *next_fix, **fix_splice; | |
11288 | sym_list *lit; | |
11289 | const char *init_name = INIT_SECTION_NAME; | |
11290 | const char *fini_name = FINI_SECTION_NAME; | |
11291 | int init_name_len = strlen(init_name); | |
11292 | int fini_name_len = strlen(fini_name); | |
11293 | ||
11294 | mark_literal_frags (literal_head->next); | |
11295 | ||
11296 | if (use_literal_section) | |
11297 | return; | |
11298 | ||
11299 | /* Assign addresses (rough estimates) to the potential literal pool locations | |
11300 | and create new ones if the gaps are too large. */ | |
11301 | ||
11302 | xtensa_assign_litpool_addresses (); | |
11303 | ||
11304 | /* Walk through the literal segments. */ | |
74869ac7 | 11305 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 11306 | { |
4111950f MF |
11307 | const char *seg_name = segment_name (segment->seg); |
11308 | ||
74869ac7 | 11309 | /* Keep the literals for .init and .fini in separate sections. */ |
4111950f MF |
11310 | if ((!memcmp (seg_name, init_name, init_name_len) && |
11311 | !strcmp (seg_name + init_name_len, ".literal")) || | |
11312 | (!memcmp (seg_name, fini_name, fini_name_len) && | |
11313 | !strcmp (seg_name + fini_name_len, ".literal"))) | |
74869ac7 BW |
11314 | continue; |
11315 | ||
e0001a05 NC |
11316 | frchain_from = seg_info (segment->seg)->frchainP; |
11317 | search_frag = frchain_from->frch_root; | |
11318 | literal_pool = NULL; | |
11319 | frchain_to = NULL; | |
11320 | frag_splice = &(frchain_from->frch_root); | |
11321 | ||
4de0562a | 11322 | while (search_frag && !search_frag->tc_frag_data.literal_frag) |
e0001a05 | 11323 | { |
9c2799c2 | 11324 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
11325 | || search_frag->fr_type == rs_align); |
11326 | search_frag = search_frag->fr_next; | |
11327 | } | |
11328 | ||
4de0562a | 11329 | if (!search_frag) |
f8aecf3c | 11330 | continue; |
4de0562a | 11331 | |
9c2799c2 | 11332 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
11333 | == RELAX_LITERAL_POOL_BEGIN); |
11334 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
11335 | ||
11336 | /* Make sure that all the frags in this series are closed, and | |
11337 | that there is at least one left over of zero-size. This | |
11338 | prevents us from making a segment with an frchain without any | |
11339 | frags in it. */ | |
11340 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11341 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11342 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); |
43cd72b9 | 11343 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11344 | |
43cd72b9 | 11345 | while (search_frag != frag_now) |
e0001a05 NC |
11346 | { |
11347 | next_frag = search_frag->fr_next; | |
e0001a05 NC |
11348 | if (search_frag->tc_frag_data.literal_frag) |
11349 | { | |
11350 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 11351 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 11352 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 11353 | gas_assert (frchain_to); |
e0001a05 | 11354 | } |
b46824bd MF |
11355 | |
11356 | if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0) | |
11357 | { | |
11358 | /* Skip empty fill frags. */ | |
11359 | *frag_splice = next_frag; | |
11360 | search_frag = next_frag; | |
11361 | continue; | |
11362 | } | |
11363 | ||
11364 | if (search_frag->fr_type == rs_align) | |
11365 | { | |
11366 | /* Skip alignment frags, because the pool as a whole will be | |
11367 | aligned if used, and we don't want to force alignment if the | |
11368 | pool is unused. */ | |
11369 | *frag_splice = next_frag; | |
11370 | search_frag = next_frag; | |
11371 | continue; | |
11372 | } | |
11373 | ||
11374 | /* First, move the frag out of the literal section and | |
11375 | to the appropriate place. */ | |
11376 | ||
33eaf5de | 11377 | /* Insert an alignment frag at start of pool. */ |
b46824bd MF |
11378 | if (literal_pool->fr_next->fr_type == rs_machine_dependent && |
11379 | literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END) | |
11380 | { | |
11381 | segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg; | |
11382 | emit_state prev_state; | |
11383 | fragS *prev_frag; | |
11384 | fragS *align_frag; | |
11385 | xtensa_switch_section_emit_state (&prev_state, pool_seg, 0); | |
11386 | prev_frag = frag_now; | |
11387 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
11388 | align_frag = frag_now; | |
11389 | frag_align (2, 0, 0); | |
11390 | /* Splice it into the right place. */ | |
11391 | prev_frag->fr_next = align_frag->fr_next; | |
11392 | align_frag->fr_next = literal_pool->fr_next; | |
11393 | literal_pool->fr_next = align_frag; | |
11394 | /* Insert after this one. */ | |
11395 | literal_pool->tc_frag_data.literal_frag = align_frag; | |
11396 | xtensa_restore_emit_state (&prev_state); | |
11397 | } | |
c48aaca0 | 11398 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 11399 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
b46824bd MF |
11400 | /* Skip align frag. */ |
11401 | if (insert_after->fr_next->fr_type == rs_align) | |
11402 | { | |
11403 | insert_after = insert_after->fr_next; | |
11404 | } | |
43cd72b9 | 11405 | |
e0001a05 NC |
11406 | *frag_splice = next_frag; |
11407 | search_frag->fr_next = insert_after->fr_next; | |
11408 | insert_after->fr_next = search_frag; | |
11409 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 11410 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
11411 | |
11412 | /* Now move any fixups associated with this frag to the | |
11413 | right section. */ | |
11414 | fix = frchain_from->fix_root; | |
11415 | fix_splice = &(frchain_from->fix_root); | |
11416 | while (fix) | |
11417 | { | |
11418 | next_fix = fix->fx_next; | |
11419 | if (fix->fx_frag == search_frag) | |
11420 | { | |
11421 | *fix_splice = next_fix; | |
11422 | fix->fx_next = frchain_to->fix_root; | |
11423 | frchain_to->fix_root = fix; | |
11424 | if (frchain_to->fix_tail == NULL) | |
11425 | frchain_to->fix_tail = fix; | |
11426 | } | |
11427 | else | |
11428 | fix_splice = &(fix->fx_next); | |
11429 | fix = next_fix; | |
11430 | } | |
11431 | search_frag = next_frag; | |
11432 | } | |
11433 | ||
11434 | if (frchain_from->fix_root != NULL) | |
11435 | { | |
11436 | frchain_from = seg_info (segment->seg)->frchainP; | |
11437 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
11438 | ||
9c2799c2 | 11439 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
11440 | } |
11441 | frchain_from->fix_tail = NULL; | |
11442 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
11443 | } |
11444 | ||
82e7541d BW |
11445 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
11446 | for (lit = literal_syms; lit; lit = lit->next) | |
11447 | { | |
11448 | symbolS *lit_sym = lit->sym; | |
91d6fa6a NC |
11449 | segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; |
11450 | if (dseg) | |
11451 | S_SET_SEGMENT (lit_sym, dseg); | |
82e7541d | 11452 | } |
e0001a05 NC |
11453 | } |
11454 | ||
11455 | ||
a7877748 BW |
11456 | /* Walk over all the frags for segments in a list and mark them as |
11457 | containing literals. As clunky as this is, we can't rely on frag_var | |
11458 | and frag_variant to get called in all situations. */ | |
11459 | ||
11460 | static void | |
7fa3d080 | 11461 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
11462 | { |
11463 | frchainS *frchain_from; | |
11464 | fragS *search_frag; | |
11465 | ||
11466 | while (segment) | |
11467 | { | |
11468 | frchain_from = seg_info (segment->seg)->frchainP; | |
11469 | search_frag = frchain_from->frch_root; | |
c138bc38 | 11470 | while (search_frag) |
a7877748 BW |
11471 | { |
11472 | search_frag->tc_frag_data.is_literal = TRUE; | |
11473 | search_frag = search_frag->fr_next; | |
11474 | } | |
11475 | segment = segment->next; | |
11476 | } | |
11477 | } | |
11478 | ||
11479 | ||
e0001a05 | 11480 | static void |
7fa3d080 | 11481 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
11482 | { |
11483 | /* Move all of the sections in the section list to come | |
11484 | after "after" in the gnu segment list. */ | |
11485 | ||
11486 | head = head->next; | |
11487 | while (head) | |
11488 | { | |
11489 | segT literal_section = head->seg; | |
11490 | ||
11491 | /* Move the literal section after "after". */ | |
9c2799c2 | 11492 | gas_assert (literal_section); |
e0001a05 NC |
11493 | if (literal_section != after) |
11494 | { | |
69852798 AM |
11495 | bfd_section_list_remove (stdoutput, literal_section); |
11496 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
11497 | } |
11498 | ||
11499 | head = head->next; | |
11500 | } | |
11501 | } | |
11502 | ||
11503 | ||
11504 | /* Push all the literal segments to the end of the gnu list. */ | |
11505 | ||
7fa3d080 BW |
11506 | static void |
11507 | xtensa_reorder_segments (void) | |
e0001a05 NC |
11508 | { |
11509 | segT sec; | |
b08b5071 | 11510 | segT last_sec = 0; |
e0001a05 NC |
11511 | int old_count = 0; |
11512 | int new_count = 0; | |
11513 | ||
11514 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
11515 | { |
11516 | last_sec = sec; | |
11517 | old_count++; | |
11518 | } | |
e0001a05 NC |
11519 | |
11520 | /* Now that we have the last section, push all the literal | |
11521 | sections to the end. */ | |
e0001a05 | 11522 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
11523 | |
11524 | /* Now perform the final error check. */ | |
11525 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
11526 | new_count++; | |
9c2799c2 | 11527 | gas_assert (new_count == old_count); |
e0001a05 NC |
11528 | } |
11529 | ||
11530 | ||
e0001a05 NC |
11531 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
11532 | correct location. Return a emit_state which can be passed to | |
11533 | xtensa_restore_emit_state to return to current fragment. */ | |
11534 | ||
7fa3d080 BW |
11535 | static void |
11536 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
11537 | { |
11538 | if (directive_state[directive_absolute_literals]) | |
11539 | { | |
74869ac7 BW |
11540 | segT lit4_seg = cache_literal_section (TRUE); |
11541 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
11542 | } |
11543 | else | |
11544 | xtensa_switch_to_non_abs_literal_fragment (result); | |
11545 | ||
11546 | /* Do a 4-byte align here. */ | |
11547 | frag_align (2, 0, 0); | |
11548 | record_alignment (now_seg, 2); | |
11549 | } | |
11550 | ||
11551 | ||
7fa3d080 BW |
11552 | static void |
11553 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 11554 | { |
e0001a05 | 11555 | fragS *pool_location = get_literal_pool_location (now_seg); |
74869ac7 | 11556 | segT lit_seg; |
d0ad159d | 11557 | bfd_boolean is_init_fini = xtensa_is_init_fini (now_seg); |
e0001a05 | 11558 | |
43cd72b9 BW |
11559 | if (pool_location == NULL |
11560 | && !use_literal_section | |
d0ad159d | 11561 | && !is_init_fini) |
e0001a05 | 11562 | { |
b46824bd MF |
11563 | if (!auto_litpools) |
11564 | { | |
11565 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); | |
11566 | } | |
947fa914 MF |
11567 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); |
11568 | pool_location = get_literal_pool_location (now_seg); | |
e0001a05 NC |
11569 | } |
11570 | ||
74869ac7 BW |
11571 | lit_seg = cache_literal_section (FALSE); |
11572 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 11573 | |
43cd72b9 | 11574 | if (!use_literal_section |
d0ad159d | 11575 | && !is_init_fini |
43cd72b9 | 11576 | && get_literal_pool_location (now_seg) != pool_location) |
e0001a05 NC |
11577 | { |
11578 | /* Close whatever frag is there. */ | |
11579 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11580 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
11581 | frag_now->tc_frag_data.literal_frag = pool_location; |
11582 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11583 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11584 | } |
e0001a05 NC |
11585 | } |
11586 | ||
11587 | ||
11588 | /* Call this function before emitting data into the literal section. | |
11589 | This is a helper function for xtensa_switch_to_literal_fragment. | |
11590 | This is similar to a .section new_now_seg subseg. */ | |
11591 | ||
7fa3d080 BW |
11592 | static void |
11593 | xtensa_switch_section_emit_state (emit_state *state, | |
11594 | segT new_now_seg, | |
11595 | subsegT new_now_subseg) | |
e0001a05 NC |
11596 | { |
11597 | state->name = now_seg->name; | |
11598 | state->now_seg = now_seg; | |
11599 | state->now_subseg = now_subseg; | |
11600 | state->generating_literals = generating_literals; | |
11601 | generating_literals++; | |
2b0210eb | 11602 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
11603 | } |
11604 | ||
11605 | ||
11606 | /* Use to restore the emitting into the normal place. */ | |
11607 | ||
7fa3d080 BW |
11608 | static void |
11609 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
11610 | { |
11611 | generating_literals = state->generating_literals; | |
2b0210eb | 11612 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
11613 | } |
11614 | ||
11615 | ||
74869ac7 | 11616 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 11617 | |
74869ac7 BW |
11618 | static bfd_boolean |
11619 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 11620 | { |
74869ac7 BW |
11621 | const char *gname = inf; |
11622 | const char *group_name = elf_group_name (sec); | |
3739860c | 11623 | |
74869ac7 BW |
11624 | return (group_name == gname |
11625 | || (group_name != NULL | |
11626 | && gname != NULL | |
11627 | && strcmp (group_name, gname) == 0)); | |
11628 | } | |
e0001a05 | 11629 | |
e0001a05 | 11630 | |
74869ac7 BW |
11631 | /* Get the literal section to be used for the current text section. |
11632 | The result may be cached in the default_lit_sections structure. */ | |
11633 | ||
11634 | static segT | |
11635 | cache_literal_section (bfd_boolean use_abs_literals) | |
11636 | { | |
11637 | const char *text_name, *group_name = 0; | |
b9bb4a93 TS |
11638 | const char *base_name, *suffix; |
11639 | char *name; | |
74869ac7 BW |
11640 | segT *pcached; |
11641 | segT seg, current_section; | |
11642 | int current_subsec; | |
11643 | bfd_boolean linkonce = FALSE; | |
11644 | ||
11645 | /* Save the current section/subsection. */ | |
11646 | current_section = now_seg; | |
11647 | current_subsec = now_subseg; | |
11648 | ||
11649 | /* Clear the cached values if they are no longer valid. */ | |
11650 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 11651 | { |
74869ac7 BW |
11652 | default_lit_sections.current_text_seg = now_seg; |
11653 | default_lit_sections.lit_seg = NULL; | |
11654 | default_lit_sections.lit4_seg = NULL; | |
11655 | } | |
11656 | ||
11657 | /* Check if the literal section is already cached. */ | |
11658 | if (use_abs_literals) | |
11659 | pcached = &default_lit_sections.lit4_seg; | |
11660 | else | |
11661 | pcached = &default_lit_sections.lit_seg; | |
11662 | ||
11663 | if (*pcached) | |
11664 | return *pcached; | |
3739860c | 11665 | |
74869ac7 BW |
11666 | text_name = default_lit_sections.lit_prefix; |
11667 | if (! text_name || ! *text_name) | |
11668 | { | |
11669 | text_name = segment_name (current_section); | |
11670 | group_name = elf_group_name (current_section); | |
11671 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
11672 | } | |
11673 | ||
11674 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
11675 | if (group_name) | |
11676 | { | |
4ec9d7d5 | 11677 | name = concat (base_name, ".", group_name, (char *) NULL); |
74869ac7 BW |
11678 | } |
11679 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
11680 | { | |
11681 | suffix = strchr (text_name + linkonce_len, '.'); | |
11682 | ||
4ec9d7d5 TS |
11683 | name = concat (".gnu.linkonce", base_name, suffix ? suffix : "", |
11684 | (char *) NULL); | |
74869ac7 BW |
11685 | linkonce = TRUE; |
11686 | } | |
11687 | else | |
11688 | { | |
a89c407e SA |
11689 | /* If the section name begins or ends with ".text", then replace |
11690 | that portion instead of appending an additional suffix. */ | |
74869ac7 | 11691 | size_t len = strlen (text_name); |
a89c407e SA |
11692 | if (len >= 5 |
11693 | && (strcmp (text_name + len - 5, ".text") == 0 | |
11694 | || strncmp (text_name, ".text", 5) == 0)) | |
74869ac7 BW |
11695 | len -= 5; |
11696 | ||
add39d23 | 11697 | name = XNEWVEC (char, len + strlen (base_name) + 1); |
a89c407e SA |
11698 | if (strncmp (text_name, ".text", 5) == 0) |
11699 | { | |
11700 | strcpy (name, base_name); | |
11701 | strcat (name, text_name + 5); | |
11702 | } | |
11703 | else | |
11704 | { | |
11705 | strcpy (name, text_name); | |
11706 | strcpy (name + len, base_name); | |
11707 | } | |
b08b5071 | 11708 | } |
e0001a05 | 11709 | |
74869ac7 BW |
11710 | /* Canonicalize section names to allow renaming literal sections. |
11711 | The group name, if any, came from the current text section and | |
11712 | has already been canonicalized. */ | |
11713 | name = tc_canonicalize_symbol_name (name); | |
11714 | ||
11715 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
11716 | (void *) group_name); | |
11717 | if (! seg) | |
e0001a05 | 11718 | { |
74869ac7 BW |
11719 | flagword flags; |
11720 | ||
11721 | seg = subseg_force_new (name, 0); | |
11722 | ||
11723 | if (! use_abs_literals) | |
b08b5071 | 11724 | { |
74869ac7 | 11725 | /* Add the newly created literal segment to the list. */ |
325801bd | 11726 | seg_list *n = XNEW (seg_list); |
b08b5071 | 11727 | n->seg = seg; |
74869ac7 BW |
11728 | n->next = literal_head->next; |
11729 | literal_head->next = n; | |
b08b5071 | 11730 | } |
74869ac7 BW |
11731 | |
11732 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
11733 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
11734 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
11735 | ||
11736 | elf_group_name (seg) = group_name; | |
11737 | ||
fd361982 AM |
11738 | bfd_set_section_flags (seg, flags); |
11739 | bfd_set_section_alignment (seg, 2); | |
e0001a05 NC |
11740 | } |
11741 | ||
74869ac7 | 11742 | *pcached = seg; |
b08b5071 | 11743 | subseg_set (current_section, current_subsec); |
74869ac7 | 11744 | return seg; |
e0001a05 NC |
11745 | } |
11746 | ||
43cd72b9 BW |
11747 | \f |
11748 | /* Property Tables Stuff. */ | |
11749 | ||
7fa3d080 BW |
11750 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
11751 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
11752 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
11753 | ||
11754 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
11755 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
11756 | ||
b08b5071 | 11757 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
11758 | static void xtensa_create_property_segments |
11759 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
11760 | static void xtensa_create_xproperty_segments | |
11761 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 11762 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
11763 | static bfd_boolean section_has_property (segT, frag_predicate); |
11764 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
11765 | static void add_xt_block_frags | |
542f8b94 | 11766 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
11767 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
11768 | static void xtensa_frag_flags_init (frag_flags *); | |
11769 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 11770 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 11771 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
11772 | |
11773 | /* Set up property tables after relaxation. */ | |
11774 | ||
11775 | void | |
11776 | xtensa_post_relax_hook (void) | |
11777 | { | |
11778 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
11779 | |
11780 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 11781 | xtensa_mark_frags_for_org (); |
6a7eedfe | 11782 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 11783 | |
b29757dc BW |
11784 | xtensa_create_property_segments (get_frag_is_literal, |
11785 | NULL, | |
11786 | XTENSA_LIT_SEC_NAME, | |
11787 | xt_literal_sec); | |
7fa3d080 BW |
11788 | xtensa_create_xproperty_segments (get_frag_property_flags, |
11789 | XTENSA_PROP_SEC_NAME, | |
11790 | xt_prop_sec); | |
11791 | ||
11792 | if (warn_unaligned_branch_targets) | |
11793 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
11794 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
11795 | } | |
11796 | ||
11797 | ||
43cd72b9 BW |
11798 | /* This function is only meaningful after xtensa_move_literals. */ |
11799 | ||
11800 | static bfd_boolean | |
7fa3d080 | 11801 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 11802 | { |
9c2799c2 | 11803 | gas_assert (fragP != NULL); |
43cd72b9 BW |
11804 | return fragP->tc_frag_data.is_literal; |
11805 | } | |
11806 | ||
11807 | ||
43cd72b9 | 11808 | static void |
7fa3d080 BW |
11809 | xtensa_create_property_segments (frag_predicate property_function, |
11810 | frag_predicate end_property_function, | |
11811 | const char *section_name_base, | |
11812 | xt_section_type sec_type) | |
43cd72b9 BW |
11813 | { |
11814 | segT *seclist; | |
11815 | ||
11816 | /* Walk over all of the current segments. | |
11817 | Walk over each fragment | |
11818 | For each non-empty fragment, | |
11819 | Build a property record (append where possible). */ | |
11820 | ||
11821 | for (seclist = &stdoutput->sections; | |
11822 | seclist && *seclist; | |
11823 | seclist = &(*seclist)->next) | |
11824 | { | |
11825 | segT sec = *seclist; | |
43cd72b9 | 11826 | |
532f93bd | 11827 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11828 | continue; |
11829 | ||
11830 | if (section_has_property (sec, property_function)) | |
11831 | { | |
542f8b94 BW |
11832 | segment_info_type *xt_seg_info; |
11833 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11834 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11835 | |
11836 | prop_sec->output_section = prop_sec; | |
11837 | subseg_set (prop_sec, 0); | |
11838 | xt_seg_info = seg_info (prop_sec); | |
11839 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11840 | ||
43cd72b9 | 11841 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11842 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
11843 | end_property_function); |
11844 | } | |
11845 | } | |
11846 | ||
11847 | /* Now we fill them out.... */ | |
11848 | ||
11849 | for (seclist = &stdoutput->sections; | |
11850 | seclist && *seclist; | |
11851 | seclist = &(*seclist)->next) | |
11852 | { | |
11853 | segment_info_type *seginfo; | |
11854 | xtensa_block_info *block; | |
11855 | segT sec = *seclist; | |
11856 | ||
11857 | seginfo = seg_info (sec); | |
11858 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11859 | ||
11860 | if (block) | |
11861 | { | |
11862 | xtensa_block_info *cur_block; | |
43cd72b9 | 11863 | int num_recs = 0; |
d77b99c9 | 11864 | bfd_size_type rec_size; |
43cd72b9 BW |
11865 | |
11866 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11867 | num_recs++; | |
11868 | ||
11869 | rec_size = num_recs * 8; | |
fd361982 | 11870 | bfd_set_section_size (sec, rec_size); |
43cd72b9 | 11871 | |
43cd72b9 BW |
11872 | if (num_recs) |
11873 | { | |
43cd72b9 | 11874 | char *frag_data; |
542f8b94 | 11875 | int i; |
43cd72b9 | 11876 | |
542f8b94 BW |
11877 | subseg_set (sec, 0); |
11878 | frag_data = frag_more (rec_size); | |
43cd72b9 | 11879 | cur_block = block; |
43cd72b9 BW |
11880 | for (i = 0; i < num_recs; i++) |
11881 | { | |
542f8b94 | 11882 | fixS *fix; |
e0001a05 | 11883 | |
43cd72b9 | 11884 | /* Write the fixup. */ |
9c2799c2 | 11885 | gas_assert (cur_block); |
542f8b94 BW |
11886 | fix = fix_new (frag_now, i * 8, 4, |
11887 | section_symbol (cur_block->sec), | |
11888 | cur_block->offset, | |
11889 | FALSE, BFD_RELOC_32); | |
11890 | fix->fx_file = "<internal>"; | |
43cd72b9 | 11891 | fix->fx_line = 0; |
e0001a05 | 11892 | |
43cd72b9 | 11893 | /* Write the length. */ |
542f8b94 | 11894 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
11895 | cur_block->size, 4); |
11896 | cur_block = cur_block->next; | |
11897 | } | |
542f8b94 BW |
11898 | frag_wane (frag_now); |
11899 | frag_new (0); | |
11900 | frag_wane (frag_now); | |
43cd72b9 BW |
11901 | } |
11902 | } | |
11903 | } | |
e0001a05 NC |
11904 | } |
11905 | ||
11906 | ||
7fa3d080 BW |
11907 | static void |
11908 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
11909 | const char *section_name_base, | |
11910 | xt_section_type sec_type) | |
e0001a05 NC |
11911 | { |
11912 | segT *seclist; | |
11913 | ||
11914 | /* Walk over all of the current segments. | |
43cd72b9 BW |
11915 | Walk over each fragment. |
11916 | For each fragment that has instructions, | |
11917 | build an instruction record (append where possible). */ | |
e0001a05 NC |
11918 | |
11919 | for (seclist = &stdoutput->sections; | |
11920 | seclist && *seclist; | |
11921 | seclist = &(*seclist)->next) | |
11922 | { | |
11923 | segT sec = *seclist; | |
43cd72b9 | 11924 | |
532f93bd | 11925 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11926 | continue; |
11927 | ||
11928 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 11929 | { |
542f8b94 BW |
11930 | segment_info_type *xt_seg_info; |
11931 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11932 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11933 | |
11934 | prop_sec->output_section = prop_sec; | |
11935 | subseg_set (prop_sec, 0); | |
11936 | xt_seg_info = seg_info (prop_sec); | |
11937 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11938 | ||
e0001a05 | 11939 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11940 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
11941 | } |
11942 | } | |
11943 | ||
11944 | /* Now we fill them out.... */ | |
11945 | ||
11946 | for (seclist = &stdoutput->sections; | |
11947 | seclist && *seclist; | |
11948 | seclist = &(*seclist)->next) | |
11949 | { | |
11950 | segment_info_type *seginfo; | |
11951 | xtensa_block_info *block; | |
11952 | segT sec = *seclist; | |
43cd72b9 | 11953 | |
e0001a05 NC |
11954 | seginfo = seg_info (sec); |
11955 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11956 | ||
11957 | if (block) | |
11958 | { | |
11959 | xtensa_block_info *cur_block; | |
43cd72b9 | 11960 | int num_recs = 0; |
d77b99c9 | 11961 | bfd_size_type rec_size; |
e0001a05 NC |
11962 | |
11963 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11964 | num_recs++; | |
11965 | ||
43cd72b9 | 11966 | rec_size = num_recs * (8 + 4); |
fd361982 | 11967 | bfd_set_section_size (sec, rec_size); |
43cd72b9 BW |
11968 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
11969 | ||
e0001a05 NC |
11970 | if (num_recs) |
11971 | { | |
e0001a05 | 11972 | char *frag_data; |
542f8b94 | 11973 | int i; |
e0001a05 | 11974 | |
542f8b94 BW |
11975 | subseg_set (sec, 0); |
11976 | frag_data = frag_more (rec_size); | |
e0001a05 | 11977 | cur_block = block; |
e0001a05 NC |
11978 | for (i = 0; i < num_recs; i++) |
11979 | { | |
542f8b94 | 11980 | fixS *fix; |
e0001a05 NC |
11981 | |
11982 | /* Write the fixup. */ | |
9c2799c2 | 11983 | gas_assert (cur_block); |
542f8b94 BW |
11984 | fix = fix_new (frag_now, i * 12, 4, |
11985 | section_symbol (cur_block->sec), | |
11986 | cur_block->offset, | |
11987 | FALSE, BFD_RELOC_32); | |
11988 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
11989 | fix->fx_line = 0; |
11990 | ||
11991 | /* Write the length. */ | |
542f8b94 | 11992 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 11993 | cur_block->size, 4); |
542f8b94 | 11994 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 11995 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 11996 | sizeof (flagword)); |
e0001a05 NC |
11997 | cur_block = cur_block->next; |
11998 | } | |
542f8b94 BW |
11999 | frag_wane (frag_now); |
12000 | frag_new (0); | |
12001 | frag_wane (frag_now); | |
e0001a05 NC |
12002 | } |
12003 | } | |
12004 | } | |
12005 | } | |
12006 | ||
12007 | ||
532f93bd BW |
12008 | static bfd_boolean |
12009 | exclude_section_from_property_tables (segT sec) | |
12010 | { | |
fd361982 | 12011 | flagword flags = bfd_section_flags (sec); |
532f93bd BW |
12012 | |
12013 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
12014 | if ((flags & SEC_DEBUGGING) | |
12015 | || !(flags & SEC_ALLOC) | |
12016 | || (flags & SEC_MERGE)) | |
12017 | return TRUE; | |
12018 | ||
12019 | /* Linker cie and fde optimizations mess up property entries for | |
12020 | eh_frame sections, but there is nothing inside them relevant to | |
12021 | property tables anyway. */ | |
12022 | if (strcmp (sec->name, ".eh_frame") == 0) | |
12023 | return TRUE; | |
12024 | ||
12025 | return FALSE; | |
12026 | } | |
12027 | ||
12028 | ||
7fa3d080 BW |
12029 | static bfd_boolean |
12030 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
12031 | { |
12032 | segment_info_type *seginfo = seg_info (sec); | |
12033 | fragS *fragP; | |
12034 | ||
12035 | if (seginfo && seginfo->frchainP) | |
12036 | { | |
12037 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
12038 | { | |
12039 | if (property_function (fragP) | |
12040 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
12041 | return TRUE; | |
12042 | } | |
12043 | } | |
12044 | return FALSE; | |
12045 | } | |
12046 | ||
12047 | ||
7fa3d080 BW |
12048 | static bfd_boolean |
12049 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
12050 | { |
12051 | segment_info_type *seginfo = seg_info (sec); | |
12052 | fragS *fragP; | |
12053 | ||
12054 | if (seginfo && seginfo->frchainP) | |
12055 | { | |
12056 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
12057 | { | |
12058 | frag_flags prop_flags; | |
12059 | property_function (fragP, &prop_flags); | |
12060 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
12061 | return TRUE; | |
12062 | } | |
12063 | } | |
12064 | return FALSE; | |
12065 | } | |
12066 | ||
12067 | ||
e0001a05 NC |
12068 | /* Two types of block sections exist right now: literal and insns. */ |
12069 | ||
7fa3d080 BW |
12070 | static void |
12071 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
12072 | xtensa_block_info **xt_block, |
12073 | frag_predicate property_function, | |
12074 | frag_predicate end_property_function) | |
e0001a05 | 12075 | { |
e0001a05 NC |
12076 | fragS *fragP; |
12077 | ||
e0001a05 NC |
12078 | /* Build it if needed. */ |
12079 | while (*xt_block != NULL) | |
12080 | xt_block = &(*xt_block)->next; | |
12081 | /* We are either at NULL at the beginning or at the end. */ | |
12082 | ||
12083 | /* Walk through the frags. */ | |
542f8b94 | 12084 | if (seg_info (sec)->frchainP) |
e0001a05 | 12085 | { |
542f8b94 | 12086 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
12087 | fragP; |
12088 | fragP = fragP->fr_next) | |
12089 | { | |
12090 | if (property_function (fragP) | |
12091 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
12092 | { | |
12093 | if (*xt_block != NULL) | |
12094 | { | |
12095 | if ((*xt_block)->offset + (*xt_block)->size | |
12096 | == fragP->fr_address) | |
12097 | (*xt_block)->size += fragP->fr_fix; | |
12098 | else | |
12099 | xt_block = &((*xt_block)->next); | |
12100 | } | |
12101 | if (*xt_block == NULL) | |
12102 | { | |
325801bd | 12103 | xtensa_block_info *new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12104 | new_block->sec = sec; |
12105 | new_block->offset = fragP->fr_address; | |
12106 | new_block->size = fragP->fr_fix; | |
12107 | new_block->next = NULL; | |
12108 | xtensa_frag_flags_init (&new_block->flags); | |
12109 | *xt_block = new_block; | |
12110 | } | |
12111 | if (end_property_function | |
12112 | && end_property_function (fragP)) | |
12113 | { | |
12114 | xt_block = &((*xt_block)->next); | |
12115 | } | |
12116 | } | |
12117 | } | |
12118 | } | |
12119 | } | |
12120 | ||
12121 | ||
12122 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
12123 | ||
7fa3d080 BW |
12124 | static bfd_boolean |
12125 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
12126 | { |
12127 | if (prop_flags->is_literal | |
12128 | || prop_flags->is_insn | |
12129 | || prop_flags->is_data | |
12130 | || prop_flags->is_unreachable) | |
12131 | return FALSE; | |
12132 | return TRUE; | |
12133 | } | |
12134 | ||
12135 | ||
7fa3d080 BW |
12136 | static void |
12137 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
12138 | { |
12139 | memset (prop_flags, 0, sizeof (frag_flags)); | |
12140 | } | |
12141 | ||
12142 | ||
7fa3d080 BW |
12143 | static void |
12144 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
12145 | { |
12146 | xtensa_frag_flags_init (prop_flags); | |
12147 | if (fragP->tc_frag_data.is_literal) | |
12148 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
12149 | if (fragP->tc_frag_data.is_specific_opcode |
12150 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
12151 | { |
12152 | prop_flags->is_no_transform = TRUE; | |
12153 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12154 | prop_flags->is_data = TRUE; | |
12155 | } | |
43cd72b9 | 12156 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 12157 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
12158 | else if (fragP->tc_frag_data.is_insn) |
12159 | { | |
12160 | prop_flags->is_insn = TRUE; | |
12161 | if (fragP->tc_frag_data.is_loop_target) | |
12162 | prop_flags->insn.is_loop_target = TRUE; | |
12163 | if (fragP->tc_frag_data.is_branch_target) | |
12164 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
12165 | if (fragP->tc_frag_data.is_no_density) |
12166 | prop_flags->insn.is_no_density = TRUE; | |
12167 | if (fragP->tc_frag_data.use_absolute_literals) | |
12168 | prop_flags->insn.is_abslit = TRUE; | |
12169 | } | |
12170 | if (fragP->tc_frag_data.is_align) | |
12171 | { | |
12172 | prop_flags->is_align = TRUE; | |
12173 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
12174 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12175 | prop_flags->is_data = TRUE; | |
12176 | } | |
12177 | } | |
12178 | ||
12179 | ||
2f1bf5c1 | 12180 | static flagword |
7fa3d080 | 12181 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 12182 | { |
2f1bf5c1 | 12183 | flagword num = 0; |
43cd72b9 BW |
12184 | if (prop_flags->is_literal) |
12185 | num |= XTENSA_PROP_LITERAL; | |
12186 | if (prop_flags->is_insn) | |
12187 | num |= XTENSA_PROP_INSN; | |
12188 | if (prop_flags->is_data) | |
12189 | num |= XTENSA_PROP_DATA; | |
12190 | if (prop_flags->is_unreachable) | |
12191 | num |= XTENSA_PROP_UNREACHABLE; | |
12192 | if (prop_flags->insn.is_loop_target) | |
12193 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
12194 | if (prop_flags->insn.is_branch_target) | |
12195 | { | |
12196 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
12197 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
12198 | } | |
12199 | ||
12200 | if (prop_flags->insn.is_no_density) | |
12201 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
12202 | if (prop_flags->is_no_transform) |
12203 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
12204 | if (prop_flags->insn.is_no_reorder) |
12205 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
12206 | if (prop_flags->insn.is_abslit) | |
12207 | num |= XTENSA_PROP_INSN_ABSLIT; | |
12208 | ||
12209 | if (prop_flags->is_align) | |
12210 | { | |
12211 | num |= XTENSA_PROP_ALIGN; | |
12212 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
12213 | } | |
12214 | ||
12215 | return num; | |
12216 | } | |
12217 | ||
12218 | ||
12219 | static bfd_boolean | |
7fa3d080 BW |
12220 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
12221 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
12222 | { |
12223 | /* Cannot combine with an end marker. */ | |
12224 | ||
12225 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
12226 | return FALSE; | |
12227 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
12228 | return FALSE; | |
12229 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
12230 | return FALSE; | |
12231 | ||
12232 | if (prop_flags_1->is_insn) | |
12233 | { | |
12234 | /* Properties of the beginning of the frag. */ | |
12235 | if (prop_flags_2->insn.is_loop_target) | |
12236 | return FALSE; | |
12237 | if (prop_flags_2->insn.is_branch_target) | |
12238 | return FALSE; | |
12239 | if (prop_flags_1->insn.is_no_density != | |
12240 | prop_flags_2->insn.is_no_density) | |
12241 | return FALSE; | |
99ded152 BW |
12242 | if (prop_flags_1->is_no_transform != |
12243 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
12244 | return FALSE; |
12245 | if (prop_flags_1->insn.is_no_reorder != | |
12246 | prop_flags_2->insn.is_no_reorder) | |
12247 | return FALSE; | |
12248 | if (prop_flags_1->insn.is_abslit != | |
12249 | prop_flags_2->insn.is_abslit) | |
12250 | return FALSE; | |
12251 | } | |
12252 | ||
12253 | if (prop_flags_1->is_align) | |
12254 | return FALSE; | |
12255 | ||
12256 | return TRUE; | |
12257 | } | |
12258 | ||
12259 | ||
7fa3d080 BW |
12260 | static bfd_vma |
12261 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
12262 | { |
12263 | bfd_vma end_addr; | |
d77b99c9 | 12264 | unsigned align_bits; |
43cd72b9 BW |
12265 | |
12266 | if (!xt_block->flags.is_align) | |
12267 | return xt_block->size; | |
12268 | ||
12269 | end_addr = xt_block->offset + xt_block->size; | |
12270 | align_bits = xt_block->flags.alignment; | |
12271 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
12272 | return end_addr - xt_block->offset; | |
12273 | } | |
12274 | ||
12275 | ||
12276 | static bfd_boolean | |
7fa3d080 BW |
12277 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
12278 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
12279 | { |
12280 | if (xt_block->sec != xt_block_2->sec) | |
12281 | return FALSE; | |
12282 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
12283 | != xt_block_2->offset) | |
12284 | return FALSE; | |
12285 | ||
12286 | if (xt_block_2->size == 0 | |
12287 | && (!xt_block_2->flags.is_unreachable | |
12288 | || xt_block->flags.is_unreachable)) | |
12289 | { | |
12290 | if (xt_block_2->flags.is_align | |
12291 | && xt_block->flags.is_align) | |
12292 | { | |
12293 | /* Nothing needed. */ | |
12294 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
12295 | return TRUE; | |
12296 | } | |
12297 | else | |
12298 | { | |
12299 | if (xt_block_2->flags.is_align) | |
12300 | { | |
12301 | /* Push alignment to previous entry. */ | |
12302 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
12303 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12304 | } | |
12305 | return TRUE; | |
12306 | } | |
12307 | } | |
12308 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
12309 | &xt_block_2->flags)) | |
12310 | return FALSE; | |
12311 | ||
12312 | xt_block->size += xt_block_2->size; | |
12313 | ||
12314 | if (xt_block_2->flags.is_align) | |
12315 | { | |
12316 | xt_block->flags.is_align = TRUE; | |
12317 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12318 | } | |
12319 | ||
12320 | return TRUE; | |
12321 | } | |
12322 | ||
12323 | ||
7fa3d080 BW |
12324 | static void |
12325 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
12326 | xtensa_block_info **xt_block, |
12327 | frag_flags_fn property_function) | |
43cd72b9 | 12328 | { |
43cd72b9 BW |
12329 | fragS *fragP; |
12330 | ||
43cd72b9 BW |
12331 | /* Build it if needed. */ |
12332 | while (*xt_block != NULL) | |
12333 | { | |
12334 | xt_block = &(*xt_block)->next; | |
12335 | } | |
12336 | /* We are either at NULL at the beginning or at the end. */ | |
12337 | ||
12338 | /* Walk through the frags. */ | |
542f8b94 | 12339 | if (seg_info (sec)->frchainP) |
43cd72b9 | 12340 | { |
542f8b94 | 12341 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
12342 | fragP = fragP->fr_next) |
12343 | { | |
12344 | xtensa_block_info tmp_block; | |
12345 | tmp_block.sec = sec; | |
12346 | tmp_block.offset = fragP->fr_address; | |
12347 | tmp_block.size = fragP->fr_fix; | |
12348 | tmp_block.next = NULL; | |
12349 | property_function (fragP, &tmp_block.flags); | |
12350 | ||
12351 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
12352 | /* && fragP->fr_fix != 0) */ | |
12353 | { | |
12354 | if ((*xt_block) == NULL | |
12355 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
12356 | { | |
12357 | xtensa_block_info *new_block; | |
12358 | if ((*xt_block) != NULL) | |
12359 | xt_block = &(*xt_block)->next; | |
325801bd | 12360 | new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12361 | *new_block = tmp_block; |
12362 | *xt_block = new_block; | |
12363 | } | |
12364 | } | |
12365 | } | |
12366 | } | |
12367 | } | |
12368 | ||
12369 | \f | |
12370 | /* op_placement_info_table */ | |
12371 | ||
12372 | /* op_placement_info makes it easier to determine which | |
12373 | ops can go in which slots. */ | |
12374 | ||
12375 | static void | |
7fa3d080 | 12376 | init_op_placement_info_table (void) |
43cd72b9 BW |
12377 | { |
12378 | xtensa_isa isa = xtensa_default_isa; | |
12379 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
12380 | xtensa_opcode opcode; | |
12381 | xtensa_format fmt; | |
12382 | int slot; | |
12383 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
12384 | ||
325801bd | 12385 | op_placement_table = XNEWVEC (op_placement_info, num_opcodes); |
9c2799c2 | 12386 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
12387 | |
12388 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
12389 | { | |
12390 | op_placement_info *opi = &op_placement_table[opcode]; | |
12391 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 12392 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 12393 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
12394 | opi->narrowest = XTENSA_UNDEFINED; |
12395 | opi->narrowest_size = 0x7F; | |
b2d179be | 12396 | opi->narrowest_slot = 0; |
43cd72b9 BW |
12397 | opi->formats = 0; |
12398 | opi->num_formats = 0; | |
12399 | opi->issuef = 0; | |
12400 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
12401 | { | |
12402 | opi->slots[fmt] = 0; | |
12403 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
12404 | { | |
12405 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
12406 | { | |
12407 | int fmt_length = xtensa_format_length (isa, fmt); | |
12408 | opi->issuef++; | |
12409 | set_bit (fmt, opi->formats); | |
12410 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
12411 | if (fmt_length < opi->narrowest_size |
12412 | || (fmt_length == opi->narrowest_size | |
12413 | && (xtensa_format_num_slots (isa, fmt) | |
12414 | < xtensa_format_num_slots (isa, | |
12415 | opi->narrowest)))) | |
43cd72b9 BW |
12416 | { |
12417 | opi->narrowest = fmt; | |
12418 | opi->narrowest_size = fmt_length; | |
b2d179be | 12419 | opi->narrowest_slot = slot; |
43cd72b9 | 12420 | } |
e0001a05 NC |
12421 | } |
12422 | } | |
43cd72b9 BW |
12423 | if (opi->formats) |
12424 | opi->num_formats++; | |
e0001a05 NC |
12425 | } |
12426 | } | |
43cd72b9 BW |
12427 | xtensa_insnbuf_free (isa, ibuf); |
12428 | } | |
12429 | ||
12430 | ||
12431 | bfd_boolean | |
7fa3d080 | 12432 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
12433 | { |
12434 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
12435 | } | |
12436 | ||
12437 | ||
12438 | /* If the opcode is available in a single slot format, return its size. */ | |
12439 | ||
7fa3d080 BW |
12440 | static int |
12441 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 12442 | { |
b2d179be | 12443 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
12444 | } |
12445 | ||
12446 | ||
7fa3d080 BW |
12447 | static xtensa_format |
12448 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 12449 | { |
b2d179be BW |
12450 | return op_placement_table[opcode].narrowest; |
12451 | } | |
12452 | ||
12453 | ||
12454 | static int | |
12455 | xg_get_single_slot (xtensa_opcode opcode) | |
12456 | { | |
12457 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
12458 | } |
12459 | ||
12460 | \f | |
12461 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
12462 | ||
12463 | void | |
7fa3d080 | 12464 | istack_init (IStack *stack) |
e0001a05 | 12465 | { |
e0001a05 NC |
12466 | stack->ninsn = 0; |
12467 | } | |
12468 | ||
12469 | ||
12470 | bfd_boolean | |
7fa3d080 | 12471 | istack_empty (IStack *stack) |
e0001a05 NC |
12472 | { |
12473 | return (stack->ninsn == 0); | |
12474 | } | |
12475 | ||
12476 | ||
12477 | bfd_boolean | |
7fa3d080 | 12478 | istack_full (IStack *stack) |
e0001a05 NC |
12479 | { |
12480 | return (stack->ninsn == MAX_ISTACK); | |
12481 | } | |
12482 | ||
12483 | ||
12484 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 12485 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
12486 | |
12487 | TInsn * | |
7fa3d080 | 12488 | istack_top (IStack *stack) |
e0001a05 NC |
12489 | { |
12490 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12491 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
12492 | return &stack->insn[rec]; |
12493 | } | |
12494 | ||
12495 | ||
12496 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 12497 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12498 | |
12499 | void | |
7fa3d080 | 12500 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
12501 | { |
12502 | int rec = stack->ninsn; | |
9c2799c2 | 12503 | gas_assert (!istack_full (stack)); |
43cd72b9 | 12504 | stack->insn[rec] = *insn; |
e0001a05 NC |
12505 | stack->ninsn++; |
12506 | } | |
12507 | ||
12508 | ||
12509 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 12510 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12511 | |
12512 | TInsn * | |
7fa3d080 | 12513 | istack_push_space (IStack *stack) |
e0001a05 NC |
12514 | { |
12515 | int rec = stack->ninsn; | |
12516 | TInsn *insn; | |
9c2799c2 | 12517 | gas_assert (!istack_full (stack)); |
e0001a05 | 12518 | insn = &stack->insn[rec]; |
60242db2 | 12519 | tinsn_init (insn); |
e0001a05 NC |
12520 | stack->ninsn++; |
12521 | return insn; | |
12522 | } | |
12523 | ||
12524 | ||
12525 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 12526 | istack_empty () returns TRUE. */ |
e0001a05 NC |
12527 | |
12528 | void | |
7fa3d080 | 12529 | istack_pop (IStack *stack) |
e0001a05 NC |
12530 | { |
12531 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12532 | gas_assert (!istack_empty (stack)); |
e0001a05 | 12533 | stack->ninsn--; |
60242db2 | 12534 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
12535 | } |
12536 | ||
12537 | \f | |
12538 | /* TInsn functions. */ | |
12539 | ||
12540 | void | |
7fa3d080 | 12541 | tinsn_init (TInsn *dst) |
e0001a05 NC |
12542 | { |
12543 | memset (dst, 0, sizeof (TInsn)); | |
12544 | } | |
12545 | ||
12546 | ||
43cd72b9 | 12547 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
12548 | |
12549 | static bfd_boolean | |
7fa3d080 | 12550 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
12551 | { |
12552 | int i; | |
12553 | int n = insn->ntok; | |
12554 | ||
9c2799c2 | 12555 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12556 | |
12557 | for (i = 0; i < n; ++i) | |
12558 | { | |
12559 | switch (insn->tok[i].X_op) | |
12560 | { | |
12561 | case O_register: | |
12562 | case O_constant: | |
12563 | break; | |
12564 | default: | |
12565 | return TRUE; | |
12566 | } | |
12567 | } | |
12568 | return FALSE; | |
12569 | } | |
12570 | ||
12571 | ||
12572 | bfd_boolean | |
7fa3d080 | 12573 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 12574 | { |
43cd72b9 | 12575 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
12576 | int i; |
12577 | int n = insn->ntok; | |
12578 | ||
9c2799c2 | 12579 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12580 | |
12581 | for (i = 0; i < n; ++i) | |
12582 | { | |
12583 | switch (insn->tok[i].X_op) | |
12584 | { | |
12585 | case O_register: | |
12586 | case O_constant: | |
12587 | break; | |
43cd72b9 BW |
12588 | case O_big: |
12589 | case O_illegal: | |
12590 | case O_absent: | |
12591 | /* Errors for these types are caught later. */ | |
12592 | break; | |
12593 | case O_hi16: | |
12594 | case O_lo16: | |
e0001a05 | 12595 | default: |
43cd72b9 BW |
12596 | /* Symbolic immediates are only allowed on the last immediate |
12597 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 12598 | support non-PC-relative relocations. */ |
43cd72b9 BW |
12599 | if (i != get_relaxable_immed (insn->opcode) |
12600 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
12601 | && insn->opcode != xtensa_const16_opcode)) | |
12602 | { | |
431ad2d0 | 12603 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
12604 | return TRUE; |
12605 | } | |
e0001a05 NC |
12606 | } |
12607 | } | |
12608 | return FALSE; | |
12609 | } | |
12610 | ||
12611 | ||
12612 | /* For assembly code with complex expressions (e.g. subtraction), | |
12613 | we have to build them in the literal pool so that | |
12614 | their results are calculated correctly after relaxation. | |
12615 | The relaxation only handles expressions that | |
12616 | boil down to SYMBOL + OFFSET. */ | |
12617 | ||
12618 | static bfd_boolean | |
7fa3d080 | 12619 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
12620 | { |
12621 | int i; | |
12622 | int n = insn->ntok; | |
9c2799c2 | 12623 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12624 | for (i = 0; i < n; ++i) |
12625 | { | |
12626 | switch (insn->tok[i].X_op) | |
12627 | { | |
12628 | case O_register: | |
12629 | case O_constant: | |
12630 | case O_symbol: | |
43cd72b9 BW |
12631 | case O_lo16: |
12632 | case O_hi16: | |
e0001a05 NC |
12633 | break; |
12634 | default: | |
12635 | return TRUE; | |
12636 | } | |
12637 | } | |
12638 | return FALSE; | |
12639 | } | |
12640 | ||
12641 | ||
b2d179be BW |
12642 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
12643 | Return TRUE if there is a symbol in the immediate field. This | |
12644 | function assumes that: | |
12645 | 1) The number of operands are correct. | |
12646 | 2) The insn_type is ITYPE_INSN. | |
12647 | 3) The opcode can be encoded in the specified format and slot. | |
12648 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
12649 | |
12650 | static bfd_boolean | |
7fa3d080 BW |
12651 | tinsn_to_slotbuf (xtensa_format fmt, |
12652 | int slot, | |
12653 | TInsn *tinsn, | |
12654 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
12655 | { |
12656 | xtensa_isa isa = xtensa_default_isa; | |
12657 | xtensa_opcode opcode = tinsn->opcode; | |
12658 | bfd_boolean has_fixup = FALSE; | |
12659 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
12660 | int i; | |
12661 | ||
9c2799c2 | 12662 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
12663 | if (noperands != tinsn->ntok) |
12664 | as_fatal (_("operand number mismatch")); | |
12665 | ||
12666 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
12667 | { | |
12668 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
12669 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
12670 | return FALSE; | |
12671 | } | |
12672 | ||
12673 | for (i = 0; i < noperands; i++) | |
12674 | { | |
91d6fa6a | 12675 | expressionS *exp = &tinsn->tok[i]; |
d77b99c9 BW |
12676 | int rc; |
12677 | unsigned line; | |
3b4dbbbf | 12678 | const char *file_name; |
43cd72b9 BW |
12679 | uint32 opnd_value; |
12680 | ||
91d6fa6a | 12681 | switch (exp->X_op) |
43cd72b9 BW |
12682 | { |
12683 | case O_register: | |
12684 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12685 | break; | |
12686 | /* The register number has already been checked in | |
12687 | expression_maybe_register, so we don't need to check here. */ | |
91d6fa6a | 12688 | opnd_value = exp->X_add_number; |
43cd72b9 BW |
12689 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
12690 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
12691 | opnd_value); | |
12692 | if (rc != 0) | |
12693 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
12694 | break; | |
12695 | ||
12696 | case O_constant: | |
12697 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12698 | break; | |
3b4dbbbf | 12699 | file_name = as_where (&line); |
43cd72b9 BW |
12700 | /* It is a constant and we called this function |
12701 | then we have to try to fit it. */ | |
12702 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
91d6fa6a | 12703 | exp->X_add_number, file_name, line); |
e0001a05 NC |
12704 | break; |
12705 | ||
e0001a05 NC |
12706 | default: |
12707 | has_fixup = TRUE; | |
12708 | break; | |
12709 | } | |
12710 | } | |
43cd72b9 | 12711 | |
e0001a05 NC |
12712 | return has_fixup; |
12713 | } | |
12714 | ||
12715 | ||
b2d179be BW |
12716 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
12717 | into a multi-slot instruction, fill the other slots with NOPs. | |
12718 | Return TRUE if there is a symbol in the immediate field. See also the | |
12719 | assumptions listed for tinsn_to_slotbuf. */ | |
12720 | ||
12721 | static bfd_boolean | |
12722 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
12723 | { | |
12724 | static xtensa_insnbuf slotbuf = 0; | |
12725 | static vliw_insn vinsn; | |
12726 | xtensa_isa isa = xtensa_default_isa; | |
12727 | bfd_boolean has_fixup = FALSE; | |
12728 | int i; | |
12729 | ||
12730 | if (!slotbuf) | |
12731 | { | |
12732 | slotbuf = xtensa_insnbuf_alloc (isa); | |
12733 | xg_init_vinsn (&vinsn); | |
12734 | } | |
12735 | ||
12736 | xg_clear_vinsn (&vinsn); | |
12737 | ||
12738 | bundle_tinsn (tinsn, &vinsn); | |
12739 | ||
12740 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
12741 | ||
12742 | for (i = 0; i < vinsn.num_slots; i++) | |
12743 | { | |
12744 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
12745 | has_fixup |= | |
12746 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
12747 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
12748 | } | |
12749 | ||
12750 | return has_fixup; | |
12751 | } | |
12752 | ||
12753 | ||
43cd72b9 | 12754 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 12755 | |
7fa3d080 BW |
12756 | static bfd_boolean |
12757 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
12758 | { |
12759 | xtensa_isa isa = xtensa_default_isa; | |
12760 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
12761 | xtensa_regfile t1_regfile, t2_regfile; |
12762 | int t1_reg, t2_reg; | |
12763 | int t1_base_reg, t1_last_reg; | |
12764 | int t2_base_reg, t2_last_reg; | |
12765 | char t1_inout, t2_inout; | |
12766 | int i, j; | |
e0001a05 NC |
12767 | |
12768 | if (opcode == XTENSA_UNDEFINED) | |
12769 | { | |
12770 | as_bad (_("invalid opcode")); | |
12771 | return TRUE; | |
12772 | } | |
12773 | ||
43cd72b9 | 12774 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
12775 | { |
12776 | as_bad (_("too few operands")); | |
12777 | return TRUE; | |
12778 | } | |
12779 | ||
43cd72b9 | 12780 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
12781 | { |
12782 | as_bad (_("too many operands")); | |
12783 | return TRUE; | |
12784 | } | |
6dc6b655 BW |
12785 | |
12786 | /* Check registers. */ | |
12787 | for (j = 0; j < insn->ntok; j++) | |
12788 | { | |
12789 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
12790 | continue; | |
12791 | ||
12792 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
12793 | t2_base_reg = insn->tok[j].X_add_number; | |
12794 | t2_last_reg | |
12795 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
12796 | ||
12797 | for (i = 0; i < insn->ntok; i++) | |
12798 | { | |
12799 | if (i == j) | |
12800 | continue; | |
12801 | ||
12802 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
12803 | continue; | |
12804 | ||
12805 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
12806 | ||
12807 | if (t1_regfile != t2_regfile) | |
12808 | continue; | |
12809 | ||
12810 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
12811 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
12812 | ||
12813 | t1_base_reg = insn->tok[i].X_add_number; | |
12814 | t1_last_reg = (t1_base_reg | |
12815 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
12816 | ||
12817 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
12818 | { | |
12819 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
12820 | { | |
12821 | if (t1_reg != t2_reg) | |
12822 | continue; | |
12823 | ||
12824 | if (t1_inout != 'i' && t2_inout != 'i') | |
12825 | { | |
12826 | as_bad (_("multiple writes to the same register")); | |
12827 | return TRUE; | |
12828 | } | |
12829 | } | |
12830 | } | |
12831 | } | |
12832 | } | |
e0001a05 NC |
12833 | return FALSE; |
12834 | } | |
12835 | ||
12836 | ||
12837 | /* Load an instruction from its encoded form. */ | |
12838 | ||
12839 | static void | |
7fa3d080 | 12840 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 12841 | { |
43cd72b9 | 12842 | vliw_insn vinsn; |
e0001a05 | 12843 | |
43cd72b9 BW |
12844 | xg_init_vinsn (&vinsn); |
12845 | vinsn_from_chars (&vinsn, f); | |
12846 | ||
12847 | *tinsn = vinsn.slots[slot]; | |
12848 | xg_free_vinsn (&vinsn); | |
12849 | } | |
e0001a05 | 12850 | |
43cd72b9 BW |
12851 | |
12852 | static void | |
7fa3d080 BW |
12853 | tinsn_from_insnbuf (TInsn *tinsn, |
12854 | xtensa_insnbuf slotbuf, | |
12855 | xtensa_format fmt, | |
12856 | int slot) | |
43cd72b9 BW |
12857 | { |
12858 | int i; | |
12859 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
12860 | |
12861 | /* Find the immed. */ | |
43cd72b9 BW |
12862 | tinsn_init (tinsn); |
12863 | tinsn->insn_type = ITYPE_INSN; | |
12864 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
12865 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
12866 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
12867 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 12868 | { |
43cd72b9 BW |
12869 | set_expr_const (&tinsn->tok[i], |
12870 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
12871 | tinsn->opcode, i)); | |
e0001a05 NC |
12872 | } |
12873 | } | |
12874 | ||
12875 | ||
12876 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
12877 | ||
12878 | static void | |
7fa3d080 | 12879 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 12880 | { |
43cd72b9 | 12881 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
12882 | int opnum; |
12883 | ||
43cd72b9 | 12884 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
12885 | { |
12886 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 12887 | gas_assert (opnum >= 0); |
e7da6241 BW |
12888 | set_expr_symbol_offset (&tinsn->tok[opnum], |
12889 | fragP->tc_frag_data.slot_symbols[slot], | |
12890 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 12891 | } |
19e8f41a | 12892 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
12893 | } |
12894 | ||
12895 | ||
12896 | static int | |
7fa3d080 | 12897 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
12898 | { |
12899 | int i; | |
12900 | int text_bytes = 0; | |
12901 | ||
12902 | for (i = 0; i < istack->ninsn; i++) | |
12903 | { | |
43cd72b9 BW |
12904 | TInsn *tinsn = &istack->insn[i]; |
12905 | if (tinsn->insn_type == ITYPE_INSN) | |
12906 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
12907 | } |
12908 | return text_bytes; | |
12909 | } | |
12910 | ||
12911 | ||
12912 | static int | |
7fa3d080 | 12913 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
12914 | { |
12915 | int i; | |
12916 | int lit_bytes = 0; | |
12917 | ||
12918 | for (i = 0; i < istack->ninsn; i++) | |
12919 | { | |
43cd72b9 BW |
12920 | TInsn *tinsn = &istack->insn[i]; |
12921 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
12922 | lit_bytes += 4; |
12923 | } | |
12924 | return lit_bytes; | |
12925 | } | |
12926 | ||
43cd72b9 BW |
12927 | \f |
12928 | /* vliw_insn functions. */ | |
12929 | ||
7fa3d080 BW |
12930 | static void |
12931 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12932 | { |
12933 | int i; | |
12934 | xtensa_isa isa = xtensa_default_isa; | |
12935 | ||
12936 | xg_clear_vinsn (v); | |
12937 | ||
12938 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
12939 | if (v->insnbuf == NULL) | |
12940 | as_fatal (_("out of memory")); | |
12941 | ||
62af60e2 | 12942 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 12943 | { |
43cd72b9 BW |
12944 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
12945 | if (v->slotbuf[i] == NULL) | |
12946 | as_fatal (_("out of memory")); | |
12947 | } | |
12948 | } | |
12949 | ||
12950 | ||
7fa3d080 BW |
12951 | static void |
12952 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12953 | { |
12954 | int i; | |
65738a7d | 12955 | |
3739860c | 12956 | memset (v, 0, offsetof (vliw_insn, slots) |
62af60e2 | 12957 | + sizeof(TInsn) * config_max_slots); |
65738a7d | 12958 | |
43cd72b9 BW |
12959 | v->format = XTENSA_UNDEFINED; |
12960 | v->num_slots = 0; | |
12961 | v->inside_bundle = FALSE; | |
12962 | ||
12963 | if (xt_saved_debug_type != DEBUG_NONE) | |
12964 | debug_type = xt_saved_debug_type; | |
12965 | ||
62af60e2 | 12966 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 12967 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
12968 | } |
12969 | ||
12970 | ||
d8392fd9 SA |
12971 | static void |
12972 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
12973 | { | |
3739860c | 12974 | memcpy (dst, src, |
d8392fd9 SA |
12975 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); |
12976 | dst->insnbuf = src->insnbuf; | |
12977 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
12978 | } | |
12979 | ||
12980 | ||
7fa3d080 BW |
12981 | static bfd_boolean |
12982 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
12983 | { |
12984 | int i; | |
c138bc38 | 12985 | |
43cd72b9 BW |
12986 | for (i = 0; i < v->num_slots; i++) |
12987 | { | |
12988 | if (v->slots[i].is_specific_opcode) | |
12989 | return TRUE; | |
12990 | } | |
12991 | return FALSE; | |
12992 | } | |
12993 | ||
12994 | ||
7fa3d080 BW |
12995 | static void |
12996 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12997 | { |
12998 | int i; | |
12999 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 13000 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
13001 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
13002 | } | |
13003 | ||
13004 | ||
e7da6241 BW |
13005 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
13006 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
13007 | |
13008 | static bfd_boolean | |
7fa3d080 BW |
13009 | vinsn_to_insnbuf (vliw_insn *vinsn, |
13010 | char *frag_offset, | |
13011 | fragS *fragP, | |
13012 | bfd_boolean record_fixup) | |
43cd72b9 BW |
13013 | { |
13014 | xtensa_isa isa = xtensa_default_isa; | |
13015 | xtensa_format fmt = vinsn->format; | |
13016 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
13017 | int slot; | |
13018 | bfd_boolean has_fixup = FALSE; | |
13019 | ||
13020 | xtensa_format_encode (isa, fmt, insnbuf); | |
13021 | ||
13022 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
13023 | { | |
13024 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 13025 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
13026 | bfd_boolean tinsn_has_fixup = |
13027 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
13028 | vinsn->slotbuf[slot]); | |
13029 | ||
13030 | xtensa_format_set_slot (isa, fmt, slot, | |
13031 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 13032 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
13033 | { |
13034 | if (vinsn->num_slots != 1) | |
13035 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
13036 | else if (record_fixup) | |
13037 | /* Instructions that generate TLS relocations should always be | |
13038 | relaxed in the front-end. If "record_fixup" is set, then this | |
13039 | function is being called during back-end relaxation, so flag | |
13040 | the unexpected behavior as an error. */ | |
13041 | as_bad (_("unexpected TLS relocation")); | |
13042 | else | |
13043 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
13044 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
13045 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
13046 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 13047 | } |
e7da6241 | 13048 | if (tinsn_has_fixup) |
43cd72b9 BW |
13049 | { |
13050 | int i; | |
13051 | xtensa_opcode opcode = tinsn->opcode; | |
13052 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
13053 | has_fixup = TRUE; | |
13054 | ||
13055 | for (i = 0; i < noperands; i++) | |
13056 | { | |
91d6fa6a NC |
13057 | expressionS* exp = &tinsn->tok[i]; |
13058 | switch (exp->X_op) | |
43cd72b9 BW |
13059 | { |
13060 | case O_symbol: | |
13061 | case O_lo16: | |
13062 | case O_hi16: | |
13063 | if (get_relaxable_immed (opcode) == i) | |
13064 | { | |
e7da6241 BW |
13065 | /* Add a fix record for the instruction, except if this |
13066 | function is being called prior to relaxation, i.e., | |
13067 | if record_fixup is false, and the instruction might | |
13068 | be relaxed later. */ | |
13069 | if (record_fixup | |
13070 | || tinsn->is_specific_opcode | |
13071 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 13072 | { |
91d6fa6a | 13073 | xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, |
e7da6241 | 13074 | frag_offset - fragP->fr_literal); |
43cd72b9 BW |
13075 | } |
13076 | else | |
13077 | { | |
91d6fa6a | 13078 | if (exp->X_op != O_symbol) |
e7da6241 | 13079 | as_bad (_("invalid operand")); |
91d6fa6a NC |
13080 | tinsn->symbol = exp->X_add_symbol; |
13081 | tinsn->offset = exp->X_add_number; | |
43cd72b9 BW |
13082 | } |
13083 | } | |
13084 | else | |
e7da6241 | 13085 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
13086 | break; |
13087 | ||
13088 | case O_constant: | |
13089 | case O_register: | |
13090 | break; | |
13091 | ||
43cd72b9 | 13092 | default: |
e7da6241 | 13093 | as_bad (_("expression too complex")); |
43cd72b9 BW |
13094 | break; |
13095 | } | |
13096 | } | |
13097 | } | |
13098 | } | |
13099 | ||
13100 | return has_fixup; | |
13101 | } | |
13102 | ||
13103 | ||
13104 | static void | |
7fa3d080 | 13105 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
13106 | { |
13107 | static xtensa_insnbuf insnbuf = NULL; | |
13108 | static xtensa_insnbuf slotbuf = NULL; | |
13109 | int i; | |
13110 | xtensa_format fmt; | |
13111 | xtensa_isa isa = xtensa_default_isa; | |
13112 | ||
13113 | if (!insnbuf) | |
13114 | { | |
13115 | insnbuf = xtensa_insnbuf_alloc (isa); | |
13116 | slotbuf = xtensa_insnbuf_alloc (isa); | |
13117 | } | |
13118 | ||
d77b99c9 | 13119 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
13120 | fmt = xtensa_format_decode (isa, insnbuf); |
13121 | if (fmt == XTENSA_UNDEFINED) | |
13122 | as_fatal (_("cannot decode instruction format")); | |
13123 | vinsn->format = fmt; | |
13124 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
13125 | ||
13126 | for (i = 0; i < vinsn->num_slots; i++) | |
13127 | { | |
13128 | TInsn *tinsn = &vinsn->slots[i]; | |
13129 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
13130 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
13131 | } | |
13132 | } | |
13133 | ||
e0001a05 NC |
13134 | \f |
13135 | /* Expression utilities. */ | |
13136 | ||
43cd72b9 | 13137 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
13138 | |
13139 | bfd_boolean | |
7fa3d080 | 13140 | expr_is_const (const expressionS *s) |
e0001a05 NC |
13141 | { |
13142 | return (s->X_op == O_constant); | |
13143 | } | |
13144 | ||
13145 | ||
13146 | /* Get the expression constant. | |
43cd72b9 | 13147 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
13148 | |
13149 | offsetT | |
7fa3d080 | 13150 | get_expr_const (const expressionS *s) |
e0001a05 | 13151 | { |
9c2799c2 | 13152 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
13153 | return s->X_add_number; |
13154 | } | |
13155 | ||
13156 | ||
13157 | /* Set the expression to a constant value. */ | |
13158 | ||
13159 | void | |
7fa3d080 | 13160 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
13161 | { |
13162 | s->X_op = O_constant; | |
13163 | s->X_add_number = val; | |
13164 | s->X_add_symbol = NULL; | |
13165 | s->X_op_symbol = NULL; | |
13166 | } | |
13167 | ||
13168 | ||
43cd72b9 | 13169 | bfd_boolean |
7fa3d080 | 13170 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
13171 | { |
13172 | return (s->X_op == O_register); | |
13173 | } | |
13174 | ||
13175 | ||
13176 | /* Get the expression constant. | |
13177 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
13178 | ||
13179 | offsetT | |
7fa3d080 | 13180 | get_expr_register (const expressionS *s) |
43cd72b9 | 13181 | { |
9c2799c2 | 13182 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
13183 | return s->X_add_number; |
13184 | } | |
13185 | ||
13186 | ||
e0001a05 NC |
13187 | /* Set the expression to a symbol + constant offset. */ |
13188 | ||
13189 | void | |
7fa3d080 | 13190 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
13191 | { |
13192 | s->X_op = O_symbol; | |
13193 | s->X_add_symbol = sym; | |
13194 | s->X_op_symbol = NULL; /* unused */ | |
13195 | s->X_add_number = offset; | |
13196 | } | |
13197 | ||
13198 | ||
43cd72b9 BW |
13199 | /* Return TRUE if the two expressions are equal. */ |
13200 | ||
e0001a05 | 13201 | bfd_boolean |
7fa3d080 | 13202 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
13203 | { |
13204 | if (s1->X_op != s2->X_op) | |
13205 | return FALSE; | |
13206 | if (s1->X_add_symbol != s2->X_add_symbol) | |
13207 | return FALSE; | |
13208 | if (s1->X_op_symbol != s2->X_op_symbol) | |
13209 | return FALSE; | |
13210 | if (s1->X_add_number != s2->X_add_number) | |
13211 | return FALSE; | |
13212 | return TRUE; | |
13213 | } | |
13214 | ||
13215 | ||
13216 | static void | |
7fa3d080 | 13217 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
13218 | { |
13219 | memcpy (dst, src, sizeof (expressionS)); | |
13220 | } | |
13221 | ||
13222 | \f | |
9456465c | 13223 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
13224 | |
13225 | struct rename_section_struct | |
13226 | { | |
e4a0c708 | 13227 | const char *old_name; |
e0001a05 NC |
13228 | char *new_name; |
13229 | struct rename_section_struct *next; | |
13230 | }; | |
13231 | ||
13232 | static struct rename_section_struct *section_rename; | |
13233 | ||
13234 | ||
9456465c BW |
13235 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
13236 | entries to the section_rename list. Note: Specifying multiple | |
13237 | renamings separated by colons is not documented and is retained only | |
13238 | for backward compatibility. */ | |
e0001a05 | 13239 | |
7fa3d080 BW |
13240 | static void |
13241 | build_section_rename (const char *arg) | |
e0001a05 | 13242 | { |
9456465c | 13243 | struct rename_section_struct *r; |
e0001a05 NC |
13244 | char *this_arg = NULL; |
13245 | char *next_arg = NULL; | |
13246 | ||
9456465c | 13247 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 13248 | { |
9456465c BW |
13249 | char *old_name, *new_name; |
13250 | ||
e0001a05 NC |
13251 | if (this_arg) |
13252 | { | |
13253 | next_arg = strchr (this_arg, ':'); | |
13254 | if (next_arg) | |
13255 | { | |
13256 | *next_arg = '\0'; | |
13257 | next_arg++; | |
13258 | } | |
13259 | } | |
e0001a05 | 13260 | |
9456465c BW |
13261 | old_name = this_arg; |
13262 | new_name = strchr (this_arg, '='); | |
e0001a05 | 13263 | |
9456465c BW |
13264 | if (*old_name == '\0') |
13265 | { | |
13266 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
13267 | continue; | |
13268 | } | |
13269 | if (!new_name || new_name[1] == '\0') | |
13270 | { | |
13271 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
13272 | old_name); | |
13273 | continue; | |
13274 | } | |
13275 | *new_name = '\0'; | |
13276 | new_name++; | |
e0001a05 | 13277 | |
9456465c BW |
13278 | /* Check for invalid section renaming. */ |
13279 | for (r = section_rename; r != NULL; r = r->next) | |
13280 | { | |
13281 | if (strcmp (r->old_name, old_name) == 0) | |
13282 | as_bad (_("section %s renamed multiple times"), old_name); | |
13283 | if (strcmp (r->new_name, new_name) == 0) | |
13284 | as_bad (_("multiple sections remapped to output section %s"), | |
13285 | new_name); | |
13286 | } | |
e0001a05 | 13287 | |
9456465c | 13288 | /* Now add it. */ |
325801bd | 13289 | r = XNEW (struct rename_section_struct); |
9456465c BW |
13290 | r->old_name = xstrdup (old_name); |
13291 | r->new_name = xstrdup (new_name); | |
13292 | r->next = section_rename; | |
13293 | section_rename = r; | |
e0001a05 | 13294 | } |
e0001a05 NC |
13295 | } |
13296 | ||
13297 | ||
9456465c | 13298 | char * |
e4a0c708 | 13299 | xtensa_section_rename (const char *name) |
e0001a05 NC |
13300 | { |
13301 | struct rename_section_struct *r = section_rename; | |
13302 | ||
13303 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
13304 | { |
13305 | if (strcmp (r->old_name, name) == 0) | |
13306 | return r->new_name; | |
13307 | } | |
e0001a05 | 13308 | |
e4a0c708 | 13309 | return (char *) name; |
e0001a05 | 13310 | } |