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[deliverable/binutils-gdb.git] / gas / config / tc-xtensa.c
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e0001a05 1/* tc-xtensa.c -- Assemble Xtensa instructions.
43cd72b9 2 Copyright 2003, 2004 Free Software Foundation, Inc.
e0001a05
NC		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
43cd72b9 18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
e0001a05
NC		 19 MA 02111-1307, USA. */
20
21#include <string.h>
43cd72b9 22#include <limits.h>
e0001a05
NC		 23#include "as.h"
24#include "sb.h"
25#include "safe-ctype.h"
26#include "tc-xtensa.h"
27#include "frags.h"
28#include "subsegs.h"
29#include "xtensa-relax.h"
30#include "xtensa-istack.h"
cda2eb9e 31#include "dwarf2dbg.h"
e0001a05
NC		 32#include "struc-symbol.h"
33#include "xtensa-config.h"
34
35#ifndef uint32
36#define uint32 unsigned int
37#endif
38#ifndef int32
39#define int32 signed int
40#endif
41
42/* Notes:
43
e0001a05
NC		 44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
47
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
58
59
60/* Define characters with special meanings to GAS. */
61const char comment_chars[] = "#";
62const char line_comment_chars[] = "#";
63const char line_separator_chars[] = ";";
64const char EXP_CHARS[] = "eE";
65const char FLT_CHARS[] = "rRsSfFdDxXpP";
66
67
43cd72b9
BW		 68/* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
e0001a05 70
e0001a05 71bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
43cd72b9
BW		 72bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
73
74/* Maximum width we would pad an unreachable frag to get alignment. */
75#define UNREACHABLE_MAX_WIDTH 8
e0001a05 76
43cd72b9
BW		 77static void error_reset_cur_vinsn PARAMS ((void));
78static vliw_insn cur_vinsn;
79
80size_t xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
81
82static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
83
84/* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
86 back end. */
87static bfd_boolean past_xtensa_end = FALSE;
e0001a05
NC		 88
89/* Flags for properties of the last instruction in a segment. */
90#define FLAG_IS_A0_WRITER 0x1
91#define FLAG_IS_BAD_LOOPEND 0x2
92
93
94/* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
98
99#define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
43cd72b9 100#define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
e0001a05
NC		 101#define FINI_SECTION_NAME xtensa_section_rename (".fini")
102#define INIT_SECTION_NAME xtensa_section_rename (".init")
103#define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
104#define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
105
106
43cd72b9 107/* This type is used for the directive_stack to keep track of the
e0001a05
NC		 108 state of the literal collection pools. */
109
110typedef struct lit_state_struct
111{
112 const char *lit_seg_name;
43cd72b9 113 const char *lit4_seg_name;
e0001a05
NC		 114 const char *init_lit_seg_name;
115 const char *fini_lit_seg_name;
116 segT lit_seg;
43cd72b9 117 segT lit4_seg;
e0001a05
NC		 118 segT init_lit_seg;
119 segT fini_lit_seg;
120} lit_state;
121
122static lit_state default_lit_sections;
123
124
125/* We keep lists of literal segments. The seg_list type is the node
126 for such a list. The *_literal_head locals are the heads of the
127 various lists. All of these lists have a dummy node at the start. */
128
129typedef struct seg_list_struct
130{
131 struct seg_list_struct *next;
132 segT seg;
133} seg_list;
134
135static seg_list literal_head_h;
136static seg_list *literal_head = &literal_head_h;
137static seg_list init_literal_head_h;
138static seg_list *init_literal_head = &init_literal_head_h;
139static seg_list fini_literal_head_h;
140static seg_list *fini_literal_head = &fini_literal_head_h;
141
142
82e7541d
BW		 143/* Lists of symbols. We keep a list of symbols that label the current
144 instruction, so that we can adjust the symbols when inserting alignment
145 for various instructions. We also keep a list of all the symbols on
146 literals, so that we can fix up those symbols when the literals are
147 later moved into the text sections. */
148
149typedef struct sym_list_struct
150{
151 struct sym_list_struct *next;
152 symbolS *sym;
153} sym_list;
154
155static sym_list *insn_labels = NULL;
156static sym_list *free_insn_labels = NULL;
157static sym_list *saved_insn_labels = NULL;
158
159static sym_list *literal_syms;
160
161
43cd72b9
BW		 162/* Flags to determine whether to prefer const16 or l32r
163 if both options are available. */
164int prefer_const16 = 0;
165int prefer_l32r = 0;
166
e0001a05
NC		 167/* Global flag to indicate when we are emitting literals. */
168int generating_literals = 0;
169
43cd72b9
BW		 170/* The following PROPERTY table definitions are copied from
171 <elf/xtensa.h> and must be kept in sync with the code there. */
172
173/* Flags in the property tables to specify whether blocks of memory
174 are literals, instructions, data, or unreachable. For
175 instructions, blocks that begin loop targets and branch targets are
176 designated. Blocks that do not allow density, instruction
177 reordering or transformation are also specified. Finally, for
178 branch targets, branch target alignment priority is included.
179 Alignment of the next block is specified in the current block
180 and the size of the current block does not include any fill required
181 to align to the next block. */
182
183#define XTENSA_PROP_LITERAL 0x00000001
184#define XTENSA_PROP_INSN 0x00000002
185#define XTENSA_PROP_DATA 0x00000004
186#define XTENSA_PROP_UNREACHABLE 0x00000008
187/* Instruction only properties at beginning of code. */
188#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
189#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
190/* Instruction only properties about code. */
191#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
192#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
193#define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194
195/* Branch target alignment information. This transmits information
196 to the linker optimization about the priority of aligning a
197 particular block for branch target alignment: None, low priority,
198 high priority, or required. These only need to be checked in
199 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 Common usage is
201
202 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
203 case XTENSA_PROP_BT_ALIGN_NONE:
204 case XTENSA_PROP_BT_ALIGN_LOW:
205 case XTENSA_PROP_BT_ALIGN_HIGH:
206 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207*/
208#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209
210/* No branch target alignment. */
211#define XTENSA_PROP_BT_ALIGN_NONE 0x0
212/* Low priority branch target alignment. */
213#define XTENSA_PROP_BT_ALIGN_LOW 0x1
214/* High priority branch target alignment. */
215#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
216/* Required branch target alignment. */
217#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218
219#define GET_XTENSA_PROP_BT_ALIGN(flag) \
220 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
221#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
222 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
223 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
224
225
226/* Alignment is specified in the block BEFORE the one that needs
227 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
228 get the required alignment specified as a power of 2. Use
229 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
230 alignment. Be careful of side effects since the SET will evaluate
231 flags twice. Also, note that the SIZE of a block in the property
232 table does not include the alignment size, so the alignment fill
233 must be calculated to determine if two blocks are contiguous.
234 TEXT_ALIGN is not currently implemented but is a placeholder for a
235 possible future implementation. */
236
237#define XTENSA_PROP_ALIGN 0x00000800
238
239#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240
241#define GET_XTENSA_PROP_ALIGNMENT(flag) \
242 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
243#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
244 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
245 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246
247#define XTENSA_PROP_INSN_ABSLIT 0x00020000
248
249
250/* Structure for saving instruction and alignment per-fragment data
251 that will be written to the object file. This structure is
252 equivalent to the actual data that will be written out to the file
253 but is easier to use. We provide a conversion to file flags
254 in frag_flags_to_number. */
255
256typedef struct frag_flags_struct frag_flags;
257
258struct frag_flags_struct
259{
260 /* is_literal should only be used after xtensa_move_literals.
261 If you need to check if you are generating a literal fragment,
262 then use the generating_literals global. */
263
264 unsigned is_literal : 1;
265 unsigned is_insn : 1;
266 unsigned is_data : 1;
267 unsigned is_unreachable : 1;
268
269 struct
270 {
271 unsigned is_loop_target : 1;
272 unsigned is_branch_target : 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority : 2;
274
275 unsigned is_no_density : 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
277 /* is_specific_opcode implies no_transform. */
278 unsigned is_no_transform : 1;
279
280 unsigned is_no_reorder : 1;
281
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit : 1;
284 } insn;
285 unsigned is_align : 1;
286 unsigned alignment : 5;
287};
288
289
290/* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292struct xtensa_block_info_struct
293{
294 segT sec;
295 bfd_vma offset;
296 size_t size;
297 frag_flags flags;
298 struct xtensa_block_info_struct *next;
299};
300
e0001a05
NC		 301
302/* Structure for saving the current state before emitting literals. */
303typedef struct emit_state_struct
304{
305 const char *name;
306 segT now_seg;
307 subsegT now_subseg;
308 int generating_literals;
309} emit_state;
310
311
43cd72b9
BW		 312/* A map that keeps information on a per-subsegment basis. This is
313 maintained during initial assembly, but is invalid once the
314 subsegments are smashed together. I.E., it cannot be used during
315 the relaxation. */
316
317typedef struct subseg_map_struct
318{
319 /* the key */
320 segT seg;
321 subsegT subseg;
322
323 /* the data */
324 unsigned flags;
325 /* the fall-through frequency + the branch target frequency
326 typically used for the instruction after a call */
327 float cur_total_freq;
328 /* the branch target frequency alone */
329 float cur_target_freq;
330
331 struct subseg_map_struct *next;
332} subseg_map;
333
334
335/* Opcode placement information */
336
337typedef unsigned long long bitfield;
338#define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
339#define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
340#define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
341
342#define MAX_FORMATS 32
343
344typedef struct op_placement_info_struct
345{
346 int num_formats;
347 /* A number describing how restrictive the issue is for this
348 opcode. For example, an opcode that fits lots of different
349 formats has a high freedom, as does an opcode that fits
350 only one format but many slots in that format. The most
351 restrictive is the opcode that fits only one slot in one
352 format. */
353 int issuef;
354 /* The single format (i.e., if the op can live in a bundle by itself),
355 narrowest format, and widest format the op can be bundled in
356 and their sizes: */
357 xtensa_format single;
358 xtensa_format narrowest;
359 xtensa_format widest;
360 char narrowest_size;
361 char widest_size;
362 char single_size;
363
364 /* formats is a bitfield with the Nth bit set
365 if the opcode fits in the Nth xtensa_format. */
366 bitfield formats;
367
368 /* slots[N]'s Mth bit is set if the op fits in the
369 Mth slot of the Nth xtensa_format. */
370 bitfield slots[MAX_FORMATS];
371
372 /* A count of the number of slots in a given format
373 an op can fit (i.e., the bitcount of the slot field above). */
374 char slots_in_format[MAX_FORMATS];
375
376} op_placement_info, *op_placement_info_table;
377
378op_placement_info_table op_placement_table;
379
380
381/* Extra expression types. */
382
383#define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
384#define O_hi16 O_md2 /* use high 16 bits of symbolic value */
385#define O_lo16 O_md3 /* use low 16 bits of symbolic value */
386
387
e0001a05
NC		 388/* Directives. */
389
390typedef enum
391{
392 directive_none = 0,
393 directive_literal,
394 directive_density,
43cd72b9 395 directive_transform,
e0001a05
NC		 396 directive_freeregs,
397 directive_longcalls,
43cd72b9
BW		 398 directive_literal_prefix,
399 directive_schedule,
400 directive_absolute_literals,
401 directive_last_directive
e0001a05
NC		 402} directiveE;
403
404typedef struct
405{
406 const char *name;
407 bfd_boolean can_be_negated;
408} directive_infoS;
409
410const directive_infoS directive_info[] =
411{
43cd72b9
BW		 412 { "none", FALSE },
413 { "literal", FALSE },
414 { "density", TRUE },
415 { "transform", TRUE },
416 { "freeregs", FALSE },
417 { "longcalls", TRUE },
418 { "literal_prefix", FALSE },
419 { "schedule", TRUE },
420 { "absolute-literals", TRUE }
e0001a05
NC		 421};
422
423bfd_boolean directive_state[] =
424{
425 FALSE, /* none */
426 FALSE, /* literal */
43cd72b9 427#if !XCHAL_HAVE_DENSITY
e0001a05
NC		 428 FALSE, /* density */
429#else
430 TRUE, /* density */
431#endif
43cd72b9 432 TRUE, /* transform */
e0001a05
NC		 433 FALSE, /* freeregs */
434 FALSE, /* longcalls */
43cd72b9
BW		 435 FALSE, /* literal_prefix */
436 TRUE, /* schedule */
437#if XSHAL_USE_ABSOLUTE_LITERALS
438 TRUE /* absolute_literals */
439#else
440 FALSE /* absolute_literals */
441#endif
e0001a05
NC		 442};
443
e0001a05 444typedef bfd_boolean (*frag_predicate) (const fragS *);
43cd72b9 445typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
e0001a05 446
43cd72b9
BW		 447/* Command-line option functions. */
448static void xtensa_setup_hw_workarounds PARAMS ((int, int));
e0001a05
NC		 449
450/* Directive functions. */
451
43cd72b9 452static bfd_boolean use_transform
e0001a05
NC		 453 PARAMS ((void));
454static bfd_boolean use_longcalls
455 PARAMS ((void));
43cd72b9 456static bfd_boolean do_align_targets
e0001a05
NC		 457 PARAMS ((void));
458static void directive_push
459 PARAMS ((directiveE, bfd_boolean, const void *));
460static void directive_pop
461 PARAMS ((directiveE *, bfd_boolean *, const char **,
462 unsigned int *, const void **));
463static void directive_balance
464 PARAMS ((void));
465static bfd_boolean inside_directive
466 PARAMS ((directiveE));
467static void get_directive
468 PARAMS ((directiveE *, bfd_boolean *));
469static void xtensa_begin_directive
470 PARAMS ((int));
471static void xtensa_end_directive
472 PARAMS ((int));
43cd72b9
BW		 473static void xtensa_dwarf2_directive_loc
474 PARAMS ((int));
475static void xtensa_dwarf2_emit_insn
476 PARAMS ((int, struct dwarf2_line_info *));
e0001a05
NC		 477static void xtensa_literal_prefix
478 PARAMS ((char const *, int));
479static void xtensa_literal_position
480 PARAMS ((int));
481static void xtensa_literal_pseudo
482 PARAMS ((int));
43cd72b9
BW		 483static void xtensa_frequency_pseudo
484 PARAMS ((int));
485static void xtensa_elf_cons
486 PARAMS ((int));
487static bfd_reloc_code_real_type xtensa_elf_suffix
488 PARAMS ((char **, expressionS *));
e0001a05
NC		 489
490/* Parsing and Idiom Translation Functions. */
491
492static const char *expression_end
493 PARAMS ((const char *));
494static unsigned tc_get_register
495 PARAMS ((const char *));
496static void expression_maybe_register
43cd72b9 497 PARAMS ((xtensa_opcode, int, expressionS *));
e0001a05
NC		 498static int tokenize_arguments
499 PARAMS ((char **, char *));
500static bfd_boolean parse_arguments
501 PARAMS ((TInsn *, int, char **));
43cd72b9
BW		 502static int get_invisible_operands
503 PARAMS ((TInsn *));
e0001a05
NC		 504static int xg_translate_idioms
505 PARAMS ((char **, int *, char **));
506static int xg_translate_sysreg_op
507 PARAMS ((char **, int *, char **));
43cd72b9
BW		 508static int xtensa_translate_old_userreg_ops
509 PARAMS ((char **));
510static int xtensa_translate_zero_immed
511 PARAMS ((char *, char *, char **, int *, char **));
e0001a05
NC		 512static void xg_reverse_shift_count
513 PARAMS ((char **));
514static int xg_arg_is_constant
515 PARAMS ((char *, offsetT *));
516static void xg_replace_opname
517 PARAMS ((char **, char *));
518static int xg_check_num_args
519 PARAMS ((int *, int, char *, char **));
520
521/* Functions for dealing with the Xtensa ISA. */
522
e0001a05
NC		 523static int get_relaxable_immed
524 PARAMS ((xtensa_opcode));
525static xtensa_opcode get_opcode_from_buf
43cd72b9
BW		 526 PARAMS ((const char *, int));
527#ifdef TENSILICA_DEBUG
528static void xtensa_print_insn_table
529 PARAMS ((void));
530static void print_vliw_insn
531 PARAMS ((xtensa_insnbuf));
532#endif
e0001a05
NC		 533static bfd_boolean is_direct_call_opcode
534 PARAMS ((xtensa_opcode));
e0001a05
NC		 535static bfd_boolean is_entry_opcode
536 PARAMS ((xtensa_opcode));
43cd72b9 537static bfd_boolean is_movi_opcode
e0001a05
NC		 538 PARAMS ((xtensa_opcode));
539static bfd_boolean is_the_loop_opcode
540 PARAMS ((xtensa_opcode));
541static bfd_boolean is_jx_opcode
542 PARAMS ((xtensa_opcode));
543static bfd_boolean is_windowed_return_opcode
544 PARAMS ((xtensa_opcode));
43cd72b9
BW		 545static int decode_reloc
546 PARAMS ((bfd_reloc_code_real_type, int *, bfd_boolean *));
547static bfd_reloc_code_real_type encode_reloc
548 PARAMS ((int));
549static bfd_reloc_code_real_type encode_alt_reloc
e0001a05 550 PARAMS ((int));
e0001a05 551static void xtensa_insnbuf_set_operand
43cd72b9 552 PARAMS ((xtensa_insnbuf, xtensa_format, int, xtensa_opcode, int, uint32,
e0001a05
NC		 553 const char *, unsigned int));
554static uint32 xtensa_insnbuf_get_operand
43cd72b9 555 PARAMS ((xtensa_insnbuf, xtensa_format, int, xtensa_opcode, int));
e0001a05 556
e0001a05
NC		 557/* Various Other Internal Functions. */
558
559static bfd_boolean is_unique_insn_expansion
560 PARAMS ((TransitionRule *));
e0001a05
NC		 561static int xg_get_build_instr_size
562 PARAMS ((BuildInstr *));
563static bfd_boolean xg_is_narrow_insn
564 PARAMS ((TInsn *));
565static bfd_boolean xg_is_single_relaxable_insn
566 PARAMS ((TInsn *));
e0001a05
NC		 567static int xg_get_max_insn_widen_size
568 PARAMS ((xtensa_opcode));
569static int xg_get_max_insn_widen_literal_size
570 PARAMS ((xtensa_opcode));
571static bfd_boolean xg_is_relaxable_insn
572 PARAMS ((TInsn *, int));
573static symbolS *get_special_literal_symbol
574 PARAMS ((void));
575static symbolS *get_special_label_symbol
576 PARAMS ((void));
577static bfd_boolean xg_build_to_insn
578 PARAMS ((TInsn *, TInsn *, BuildInstr *));
579static bfd_boolean xg_build_to_stack
580 PARAMS ((IStack *, TInsn *, BuildInstr *));
581static bfd_boolean xg_expand_to_stack
582 PARAMS ((IStack *, TInsn *, int));
583static bfd_boolean xg_expand_narrow
584 PARAMS ((TInsn *, TInsn *));
585static bfd_boolean xg_immeds_fit
586 PARAMS ((const TInsn *));
587static bfd_boolean xg_symbolic_immeds_fit
588 PARAMS ((const TInsn *, segT, fragS *, offsetT, long));
589static bfd_boolean xg_check_operand
43cd72b9 590 PARAMS ((int32, xtensa_opcode, int));
e0001a05
NC		 591static int xg_assembly_relax
592 PARAMS ((IStack *, TInsn *, segT, fragS *, offsetT, int, long));
593static void xg_force_frag_space
594 PARAMS ((int));
595static void xg_finish_frag
43cd72b9
BW		 596 PARAMS ((char *, enum xtensa_relax_statesE, enum xtensa_relax_statesE,
597 int, bfd_boolean));
e0001a05
NC		 598static bfd_boolean is_branch_jmp_to_next
599 PARAMS ((TInsn *, fragS *));
600static void xg_add_branch_and_loop_targets
601 PARAMS ((TInsn *));
43cd72b9
BW		 602static bfd_boolean xg_instruction_matches_options
603 PARAMS ((TInsn *, const ReqOption *));
604static bfd_boolean xg_instruction_matches_or_options
605 PARAMS ((TInsn *, const ReqOrOptionList *));
606static bfd_boolean xg_instruction_matches_option_term
607 PARAMS ((TInsn *, const ReqOrOption *));
e0001a05
NC		 608static bfd_boolean xg_instruction_matches_rule
609 PARAMS ((TInsn *, TransitionRule *));
610static TransitionRule *xg_instruction_match
611 PARAMS ((TInsn *));
43cd72b9
BW		 612static int transition_rule_cmp
613 PARAMS ((const TransitionRule *, const TransitionRule *));
e0001a05
NC		 614static bfd_boolean xg_build_token_insn
615 PARAMS ((BuildInstr *, TInsn *, TInsn *));
616static bfd_boolean xg_simplify_insn
617 PARAMS ((TInsn *, TInsn *));
618static bfd_boolean xg_expand_assembly_insn
619 PARAMS ((IStack *, TInsn *));
620static symbolS *xg_assemble_literal
621 PARAMS ((TInsn *));
43cd72b9
BW		 622static bfd_boolean xg_valid_literal_expression
623 PARAMS ((const expressionS *));
e0001a05 624static void xg_assemble_literal_space
43cd72b9 625 PARAMS ((int, int));
e0001a05
NC		 626static symbolS *xtensa_create_literal_symbol
627 PARAMS ((segT, fragS *));
82e7541d
BW		 628static void xtensa_add_literal_sym
629 PARAMS ((symbolS *));
630static void xtensa_add_insn_label
631 PARAMS ((symbolS *));
632static void xtensa_clear_insn_labels
633 PARAMS ((void));
e0001a05
NC		 634static bfd_boolean get_is_linkonce_section
635 PARAMS ((bfd *, segT));
e0001a05 636static bfd_boolean xg_emit_insn_to_buf
43cd72b9 637 PARAMS ((TInsn *, xtensa_format, char *, fragS *, offsetT, bfd_boolean));
e0001a05 638static bfd_boolean xg_add_opcode_fix
43cd72b9 639 PARAMS ((TInsn *, int, xtensa_format, int, expressionS *, fragS *, offsetT));
e0001a05
NC		 640static void xg_resolve_literals
641 PARAMS ((TInsn *, symbolS *));
642static void xg_resolve_labels
643 PARAMS ((TInsn *, symbolS *));
e0001a05
NC		 644static bfd_boolean is_register_writer
645 PARAMS ((const TInsn *, const char *, int));
646static bfd_boolean is_bad_loopend_opcode
647 PARAMS ((const TInsn *));
648static bfd_boolean is_unaligned_label
649 PARAMS ((symbolS *));
650static fragS *next_non_empty_frag
651 PARAMS ((const fragS *));
43cd72b9
BW		 652static bfd_boolean next_frag_opcode_is_loop
653 PARAMS ((const fragS *, xtensa_opcode *));
654static int next_frag_format_size
e0001a05 655 PARAMS ((const fragS *));
43cd72b9
BW		 656static int frag_format_size
657 PARAMS ((const fragS *));
658static void update_next_frag_state
659 PARAMS ((fragS *, bfd_boolean));
e0001a05
NC		 660static bfd_boolean next_frag_is_branch_target
661 PARAMS ((const fragS *));
662static bfd_boolean next_frag_is_loop_target
663 PARAMS ((const fragS *));
664static addressT next_frag_pre_opcode_bytes
665 PARAMS ((const fragS *));
666static bfd_boolean is_next_frag_target
667 PARAMS ((const fragS *, const fragS *));
668static void xtensa_mark_literal_pool_location
61846f28 669 PARAMS ((void));
e0001a05 670static void xtensa_move_labels
82e7541d 671 PARAMS ((fragS *, valueT, bfd_boolean));
e0001a05
NC		 672static void assemble_nop
673 PARAMS ((size_t, char *));
43cd72b9
BW		 674static void build_nop
675 PARAMS ((TInsn *, int));
e0001a05
NC		 676static addressT get_expanded_loop_offset
677 PARAMS ((xtensa_opcode));
678static fragS *get_literal_pool_location
679 PARAMS ((segT));
680static void set_literal_pool_location
681 PARAMS ((segT, fragS *));
43cd72b9
BW		 682static void xtensa_set_frag_assembly_state
683 PARAMS ((fragS *));
684static bfd_boolean relaxable_section
685 PARAMS ((asection *));
686static void xtensa_find_unmarked_state_frags
687 PARAMS ((void));
688static void xtensa_find_unaligned_branch_targets
689 PARAMS ((bfd *, asection *, PTR));
690static void xtensa_find_unaligned_loops
691 PARAMS ((bfd *, asection *, PTR));
692static void xg_apply_tentative_value
693 PARAMS ((fixS *, valueT));
694static void finish_vinsn
695 PARAMS ((vliw_insn *));
696static bfd_boolean find_vinsn_conflicts
697 PARAMS ((vliw_insn *));
698static char check_t1_t2_reads_and_writes
699 PARAMS ((TInsn *, TInsn *));
700static bfd_boolean resources_conflict
701 PARAMS ((vliw_insn *));
702static xtensa_format xg_find_narrowest_format
703 PARAMS ((vliw_insn *));
704static int relaxation_requirements
705 PARAMS ((vliw_insn *));
706static void bundle_single_op
707 PARAMS ((TInsn *));
708static bfd_boolean emit_single_op
709 PARAMS ((TInsn *));
710static void xg_assemble_vliw_tokens
711 PARAMS ((vliw_insn *));
e0001a05
NC		 712
713/* Helpers for xtensa_end(). */
714
715static void xtensa_cleanup_align_frags
716 PARAMS ((void));
717static void xtensa_fix_target_frags
718 PARAMS ((void));
719static bfd_boolean frag_can_negate_branch
720 PARAMS ((fragS *));
43cd72b9
BW		 721static void xtensa_mark_narrow_branches
722 PARAMS ((void));
723static bfd_boolean is_narrow_branch_guaranteed_in_range
724 PARAMS ((fragS *, TInsn *));
725static void xtensa_mark_zcl_first_insns
726 PARAMS ((void));
e0001a05
NC		 727static void xtensa_fix_a0_b_retw_frags
728 PARAMS ((void));
729static bfd_boolean next_instrs_are_b_retw
730 PARAMS ((fragS *));
731static void xtensa_fix_b_j_loop_end_frags
732 PARAMS ((void));
733static bfd_boolean next_instr_is_loop_end
734 PARAMS ((fragS *));
735static void xtensa_fix_close_loop_end_frags
736 PARAMS ((void));
737static size_t min_bytes_to_other_loop_end
738 PARAMS ((fragS *, fragS *, offsetT, size_t));
739static size_t unrelaxed_frag_min_size
740 PARAMS ((fragS *));
43cd72b9
BW		 741static size_t unrelaxed_frag_max_size
742 PARAMS ((fragS *));
e0001a05
NC		 743static void xtensa_fix_short_loop_frags
744 PARAMS ((void));
745static size_t count_insns_to_loop_end
746 PARAMS ((fragS *, bfd_boolean, size_t));
747static size_t unrelaxed_frag_min_insn_count
748 PARAMS ((fragS *));
749static bfd_boolean branch_before_loop_end
750 PARAMS ((fragS *));
751static bfd_boolean unrelaxed_frag_has_b_j
752 PARAMS ((fragS *));
753static void xtensa_sanity_check
754 PARAMS ((void));
755static bfd_boolean is_empty_loop
756 PARAMS ((const TInsn *, fragS *));
757static bfd_boolean is_local_forward_loop
758 PARAMS ((const TInsn *, fragS *));
759
760/* Alignment Functions. */
761
762static size_t get_text_align_power
763 PARAMS ((int));
764static addressT get_text_align_max_fill_size
765 PARAMS ((int, bfd_boolean, bfd_boolean));
766static addressT get_text_align_fill_size
767 PARAMS ((addressT, int, int, bfd_boolean, bfd_boolean));
768static size_t get_text_align_nop_count
769 PARAMS ((size_t, bfd_boolean));
770static size_t get_text_align_nth_nop_size
771 PARAMS ((size_t, size_t, bfd_boolean));
772static addressT get_noop_aligned_address
773 PARAMS ((fragS *, addressT));
43cd72b9
BW		 774static addressT get_aligned_diff
775 PARAMS ((fragS *, addressT, addressT *));
e0001a05
NC		 776
777/* Helpers for xtensa_relax_frag(). */
778
43cd72b9 779static long relax_frag_loop_align
e0001a05
NC		 780 PARAMS ((fragS *, long));
781static long relax_frag_add_nop
782 PARAMS ((fragS *));
43cd72b9 783static long relax_frag_for_align
e0001a05 784 PARAMS ((fragS *, long));
43cd72b9 785static long future_alignment_required
e0001a05 786 PARAMS ((fragS *, long));
43cd72b9
BW		 787static addressT find_address_of_next_align_frag
788 PARAMS ((fragS **, int *, int *, int *, bfd_boolean *));
789static long bytes_to_stretch
790 PARAMS ((fragS *, int, int, int, int));
e0001a05 791static long relax_frag_immed
43cd72b9 792 PARAMS ((segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean));
e0001a05
NC		 793
794/* Helpers for md_convert_frag(). */
795
796static void convert_frag_align_next_opcode
797 PARAMS ((fragS *));
798static void convert_frag_narrow
43cd72b9
BW		 799 PARAMS ((segT, fragS *, xtensa_format, int));
800static void convert_frag_fill_nop
e0001a05
NC		 801 PARAMS ((fragS *));
802static void convert_frag_immed
43cd72b9 803 PARAMS ((segT, fragS *, int, xtensa_format, int));
e0001a05
NC		 804static fixS *fix_new_exp_in_seg
805 PARAMS ((segT, subsegT, fragS *, int, int, expressionS *, int,
806 bfd_reloc_code_real_type));
807static void convert_frag_immed_finish_loop
808 PARAMS ((segT, fragS *, TInsn *));
809static offsetT get_expression_value
810 PARAMS ((segT, expressionS *));
811
812/* Flags for the Last Instruction in Each Subsegment. */
813
814static unsigned get_last_insn_flags
815 PARAMS ((segT, subsegT));
816static void set_last_insn_flags
817 PARAMS ((segT, subsegT, unsigned, bfd_boolean));
818
819/* Segment list functions. */
820
821static void xtensa_remove_section
822 PARAMS ((segT));
823static void xtensa_insert_section
824 PARAMS ((segT, segT));
825static void xtensa_move_seg_list_to_beginning
826 PARAMS ((seg_list *));
43cd72b9
BW		 827static subseg_map *get_subseg_info
828 PARAMS ((segT, subsegT));
e0001a05
NC		 829static void xtensa_move_literals
830 PARAMS ((void));
a7877748
BW		 831static void mark_literal_frags
832 PARAMS ((seg_list *));
e0001a05
NC		 833static void xtensa_reorder_seg_list
834 PARAMS ((seg_list *, segT));
835static void xtensa_reorder_segments
836 PARAMS ((void));
837static segT get_last_sec
838 PARAMS ((void));
839static void xtensa_switch_to_literal_fragment
840 PARAMS ((emit_state *));
43cd72b9
BW		 841static void xtensa_switch_to_non_abs_literal_fragment
842 PARAMS ((emit_state *));
e0001a05
NC		 843static void xtensa_switch_section_emit_state
844 PARAMS ((emit_state *, segT, subsegT));
845static void xtensa_restore_emit_state
846 PARAMS ((emit_state *));
847static void cache_literal_section
43cd72b9 848 PARAMS ((seg_list *, const char *, segT *, bfd_boolean));
e0001a05 849static segT retrieve_literal_seg
43cd72b9 850 PARAMS ((seg_list *, const char *, bfd_boolean));
e0001a05
NC		 851static segT seg_present
852 PARAMS ((const char *));
853static void add_seg_list
854 PARAMS ((seg_list *, segT));
855
43cd72b9 856/* Property flags on fragments and conversion to object file flags. */
e0001a05 857
43cd72b9
BW		 858static bfd_boolean get_frag_is_literal
859 PARAMS ((const fragS *));
860static bfd_boolean get_frag_is_insn
861 PARAMS ((const fragS *));
862static bfd_boolean get_frag_is_no_transform
863 PARAMS ((fragS *));
864static void set_frag_is_specific_opcode
865 PARAMS ((fragS *, bfd_boolean));
866static void set_frag_is_no_transform
867 PARAMS ((fragS *, bfd_boolean));
e0001a05 868static void xtensa_create_property_segments
43cd72b9
BW		 869 PARAMS ((frag_predicate, frag_predicate, const char *, xt_section_type));
870static void xtensa_create_xproperty_segments
871 PARAMS ((frag_flags_fn, const char *, xt_section_type));
e0001a05
NC		 872static segment_info_type *retrieve_segment_info
873 PARAMS ((segT));
874static segT retrieve_xtensa_section
875 PARAMS ((char *));
876static bfd_boolean section_has_property
43cd72b9
BW		 877 PARAMS ((segT, frag_predicate));
878static bfd_boolean section_has_xproperty
879 PARAMS ((segT, frag_flags_fn));
e0001a05 880static void add_xt_block_frags
43cd72b9
BW		 881 PARAMS ((segT, segT, xtensa_block_info **, frag_predicate, frag_predicate));
882static bfd_boolean xtensa_frag_flags_is_empty
883 PARAMS ((const frag_flags *));
884static void xtensa_frag_flags_init
885 PARAMS ((frag_flags *));
886static void get_frag_property_flags
887 PARAMS ((const fragS *, frag_flags *));
888static bfd_vma frag_flags_to_number
889 PARAMS ((const frag_flags *));
890static bfd_boolean xtensa_frag_flags_combinable
891 PARAMS ((const frag_flags *, const frag_flags *));
892static bfd_vma xt_block_aligned_size
893 PARAMS ((const xtensa_block_info *));
894static bfd_boolean xtensa_xt_block_combine
895 PARAMS ((xtensa_block_info *, const xtensa_block_info *));
896static void add_xt_prop_frags
897 PARAMS ((segT, segT, xtensa_block_info **, frag_flags_fn));
e0001a05
NC		 898
899/* Import from elf32-xtensa.c in BFD library. */
43cd72b9 900
e0001a05 901extern char *xtensa_get_property_section_name
b614a702 902 PARAMS ((asection *, const char *));
e0001a05 903
43cd72b9
BW		 904/* op_placement_info functions. */
905
906static void init_op_placement_info_table
907 PARAMS ((void));
908extern bfd_boolean opcode_fits_format_slot
909 PARAMS ((xtensa_opcode, xtensa_format, int));
910static int xg_get_single_size
911 PARAMS ((xtensa_opcode));
912static xtensa_format xg_get_single_format
913 PARAMS ((xtensa_opcode));
914
e0001a05 915/* TInsn and IStack functions. */
43cd72b9 916
e0001a05
NC		 917static bfd_boolean tinsn_has_symbolic_operands
918 PARAMS ((const TInsn *));
919static bfd_boolean tinsn_has_invalid_symbolic_operands
920 PARAMS ((const TInsn *));
921static bfd_boolean tinsn_has_complex_operands
922 PARAMS ((const TInsn *));
923static bfd_boolean tinsn_to_insnbuf
924 PARAMS ((TInsn *, xtensa_insnbuf));
43cd72b9
BW		 925static bfd_boolean tinsn_to_slotbuf
926 PARAMS ((xtensa_format, int, TInsn *, xtensa_insnbuf));
e0001a05
NC		 927static bfd_boolean tinsn_check_arguments
928 PARAMS ((const TInsn *));
929static void tinsn_from_chars
43cd72b9
BW		 930 PARAMS ((TInsn *, char *, int));
931static void tinsn_from_insnbuf
932 PARAMS ((TInsn *, xtensa_insnbuf, xtensa_format, int));
e0001a05 933static void tinsn_immed_from_frag
43cd72b9 934 PARAMS ((TInsn *, fragS *, int));
e0001a05
NC		 935static int get_num_stack_text_bytes
936 PARAMS ((IStack *));
937static int get_num_stack_literal_bytes
938 PARAMS ((IStack *));
939
43cd72b9
BW		 940/* vliw_insn functions. */
941
942static void xg_init_vinsn
943 PARAMS ((vliw_insn *));
944static void xg_clear_vinsn
945 PARAMS ((vliw_insn *));
946static bfd_boolean vinsn_has_specific_opcodes
947 PARAMS ((vliw_insn *));
948static void xg_free_vinsn
949 PARAMS ((vliw_insn *));
950static bfd_boolean vinsn_to_insnbuf
951 PARAMS ((vliw_insn *, char *, fragS *, bfd_boolean));
952static void vinsn_from_chars
953 PARAMS ((vliw_insn *, char *));
954
e0001a05 955/* Expression Utilities. */
43cd72b9 956
e0001a05
NC		 957bfd_boolean expr_is_const
958 PARAMS ((const expressionS *));
959offsetT get_expr_const
960 PARAMS ((const expressionS *));
961void set_expr_const
962 PARAMS ((expressionS *, offsetT));
43cd72b9
BW		 963bfd_boolean expr_is_register
964 PARAMS ((const expressionS *));
965offsetT get_expr_register
966 PARAMS ((const expressionS *));
e0001a05
NC		 967void set_expr_symbol_offset
968 PARAMS ((expressionS *, symbolS *, offsetT));
43cd72b9
BW		 969static void set_expr_symbol_offset_diff
970 PARAMS ((expressionS *, symbolS *, symbolS *, offsetT));
e0001a05
NC		 971bfd_boolean expr_is_equal
972 PARAMS ((expressionS *, expressionS *));
973static void copy_expr
974 PARAMS ((expressionS *, const expressionS *));
975
976#ifdef XTENSA_SECTION_RENAME
977static void build_section_rename
978 PARAMS ((const char *));
979static void add_section_rename
980 PARAMS ((char *, char *));
981#endif
982
e0001a05
NC		 983
984/* ISA imported from bfd. */
985extern xtensa_isa xtensa_default_isa;
986
987extern int target_big_endian;
988
989static xtensa_opcode xtensa_addi_opcode;
990static xtensa_opcode xtensa_addmi_opcode;
991static xtensa_opcode xtensa_call0_opcode;
992static xtensa_opcode xtensa_call4_opcode;
993static xtensa_opcode xtensa_call8_opcode;
994static xtensa_opcode xtensa_call12_opcode;
995static xtensa_opcode xtensa_callx0_opcode;
996static xtensa_opcode xtensa_callx4_opcode;
997static xtensa_opcode xtensa_callx8_opcode;
998static xtensa_opcode xtensa_callx12_opcode;
43cd72b9 999static xtensa_opcode xtensa_const16_opcode;
e0001a05 1000static xtensa_opcode xtensa_entry_opcode;
43cd72b9
BW		 1001static xtensa_opcode xtensa_movi_opcode;
1002static xtensa_opcode xtensa_movi_n_opcode;
e0001a05 1003static xtensa_opcode xtensa_isync_opcode;
e0001a05 1004static xtensa_opcode xtensa_jx_opcode;
43cd72b9 1005static xtensa_opcode xtensa_l32r_opcode;
e0001a05
NC		 1006static xtensa_opcode xtensa_loop_opcode;
1007static xtensa_opcode xtensa_loopnez_opcode;
1008static xtensa_opcode xtensa_loopgtz_opcode;
43cd72b9 1009static xtensa_opcode xtensa_nop_opcode;
e0001a05
NC		 1010static xtensa_opcode xtensa_nop_n_opcode;
1011static xtensa_opcode xtensa_or_opcode;
1012static xtensa_opcode xtensa_ret_opcode;
1013static xtensa_opcode xtensa_ret_n_opcode;
1014static xtensa_opcode xtensa_retw_opcode;
1015static xtensa_opcode xtensa_retw_n_opcode;
43cd72b9 1016static xtensa_opcode xtensa_rsr_lcount_opcode;
e0001a05
NC		 1017static xtensa_opcode xtensa_waiti_opcode;
1018
1019\f
1020/* Command-line Options. */
1021
1022bfd_boolean use_literal_section = TRUE;
1023static bfd_boolean align_targets = TRUE;
43cd72b9 1024static bfd_boolean warn_unaligned_branch_targets = FALSE;
e0001a05 1025static bfd_boolean has_a0_b_retw = FALSE;
43cd72b9
BW		 1026static bfd_boolean workaround_a0_b_retw = FALSE;
1027static bfd_boolean workaround_b_j_loop_end = FALSE;
1028static bfd_boolean workaround_short_loop = FALSE;
e0001a05 1029static bfd_boolean maybe_has_short_loop = FALSE;
43cd72b9 1030static bfd_boolean workaround_close_loop_end = FALSE;
e0001a05
NC		 1031static bfd_boolean maybe_has_close_loop_end = FALSE;
1032
43cd72b9
BW		 1033/* When workaround_short_loops is TRUE, all loops with early exits must
1034 have at least 3 instructions. workaround_all_short_loops is a modifier
1035 to the workaround_short_loop flag. In addition to the
1036 workaround_short_loop actions, all straightline loopgtz and loopnez
1037 must have at least 3 instructions. */
e0001a05 1038
43cd72b9 1039static bfd_boolean workaround_all_short_loops = FALSE;
e0001a05
NC		 1040
1041enum
1042{
1043 option_density = OPTION_MD_BASE,
1044 option_no_density,
1045
1046 option_relax,
1047 option_no_relax,
1048
43cd72b9
BW		 1049 option_link_relax,
1050 option_no_link_relax,
1051
e0001a05
NC		 1052 option_generics,
1053 option_no_generics,
1054
43cd72b9
BW		 1055 option_transform,
1056 option_no_transform,
1057
e0001a05
NC		 1058 option_text_section_literals,
1059 option_no_text_section_literals,
1060
43cd72b9
BW		 1061 option_absolute_literals,
1062 option_no_absolute_literals,
1063
e0001a05
NC		 1064 option_align_targets,
1065 option_no_align_targets,
1066
43cd72b9 1067 option_warn_unaligned_targets,
e0001a05
NC		 1068
1069 option_longcalls,
1070 option_no_longcalls,
1071
1072 option_workaround_a0_b_retw,
1073 option_no_workaround_a0_b_retw,
1074
1075 option_workaround_b_j_loop_end,
1076 option_no_workaround_b_j_loop_end,
1077
1078 option_workaround_short_loop,
1079 option_no_workaround_short_loop,
1080
1081 option_workaround_all_short_loops,
1082 option_no_workaround_all_short_loops,
1083
1084 option_workaround_close_loop_end,
1085 option_no_workaround_close_loop_end,
1086
1087 option_no_workarounds,
1088
1089#ifdef XTENSA_SECTION_RENAME
e0001a05
NC		 1090 option_rename_section_name,
1091#endif
1092
43cd72b9
BW		 1093 option_prefer_l32r,
1094 option_prefer_const16,
1095
1096 option_target_hardware
e0001a05
NC		 1097};
1098
1099const char *md_shortopts = "";
1100
1101struct option md_longopts[] =
1102{
43cd72b9
BW		 1103 { "density", no_argument, NULL, option_density },
1104 { "no-density", no_argument, NULL, option_no_density },
1105
1106 /* Both "relax" and "generics" are deprecated and treated as equivalent
1107 to the "transform" option. */
1108 { "relax", no_argument, NULL, option_relax },
1109 { "no-relax", no_argument, NULL, option_no_relax },
1110 { "generics", no_argument, NULL, option_generics },
1111 { "no-generics", no_argument, NULL, option_no_generics },
1112
1113 { "transform", no_argument, NULL, option_transform },
1114 { "no-transform", no_argument, NULL, option_no_transform },
1115 { "text-section-literals", no_argument, NULL, option_text_section_literals },
1116 { "no-text-section-literals", no_argument, NULL,
1117 option_no_text_section_literals },
1118 { "absolute-literals", no_argument, NULL, option_absolute_literals },
1119 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
e0001a05
NC		 1120 /* This option was changed from -align-target to -target-align
1121 because it conflicted with the "-al" option. */
43cd72b9
BW		 1122 { "target-align", no_argument, NULL, option_align_targets },
1123 { "no-target-align", no_argument, NULL,
1124 option_no_align_targets },
1125 { "warn-unaligned-targets", no_argument, NULL, option_warn_unaligned_targets },
1126 { "longcalls", no_argument, NULL, option_longcalls },
1127 { "no-longcalls", no_argument, NULL, option_no_longcalls },
1128
1129 { "no-workaround-a0-b-retw", no_argument, NULL,
1130 option_no_workaround_a0_b_retw },
1131 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
e0001a05 1132
43cd72b9
BW		 1133 { "no-workaround-b-j-loop-end", no_argument, NULL,
1134 option_no_workaround_b_j_loop_end },
1135 { "workaround-b-j-loop-end", no_argument, NULL,
1136 option_workaround_b_j_loop_end },
e0001a05 1137
43cd72b9
BW		 1138 { "no-workaround-short-loops", no_argument, NULL,
1139 option_no_workaround_short_loop },
1140 { "workaround-short-loops", no_argument, NULL, option_workaround_short_loop },
e0001a05 1141
43cd72b9
BW		 1142 { "no-workaround-all-short-loops", no_argument, NULL,
1143 option_no_workaround_all_short_loops },
1144 { "workaround-all-short-loop", no_argument, NULL,
1145 option_workaround_all_short_loops },
1146
1147 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
1148 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
1149
1150 { "no-workarounds", no_argument, NULL, option_no_workarounds },
1151
1152 { "no-workaround-close-loop-end", no_argument, NULL,
1153 option_no_workaround_close_loop_end },
1154 { "workaround-close-loop-end", no_argument, NULL,
1155 option_workaround_close_loop_end },
e0001a05
NC		 1156
1157#ifdef XTENSA_SECTION_RENAME
43cd72b9
BW		 1158 { "rename-section", required_argument, NULL,
1159 option_rename_section_name },
e0001a05
NC		 1160#endif /* XTENSA_SECTION_RENAME */
1161
43cd72b9
BW		 1162 { "link-relax", no_argument, NULL, option_link_relax },
1163 { "no-link-relax", no_argument, NULL, option_no_link_relax },
1164
1165 { "target-hardware", required_argument, NULL, option_target_hardware },
1166
1167 { NULL, no_argument, NULL, 0 }
e0001a05
NC		 1168};
1169
1170size_t md_longopts_size = sizeof md_longopts;
1171
1172
1173int
1174md_parse_option (c, arg)
1175 int c;
1176 char *arg;
1177{
1178 switch (c)
1179 {
1180 case option_density:
43cd72b9 1181 as_warn (_("--density option is ignored"));
e0001a05
NC		 1182 return 1;
1183 case option_no_density:
43cd72b9 1184 as_warn (_("--no-density option is ignored"));
e0001a05 1185 return 1;
43cd72b9
BW		 1186 case option_link_relax:
1187 linkrelax = 1;
e0001a05 1188 return 1;
43cd72b9
BW		 1189 case option_no_link_relax:
1190 linkrelax = 0;
e0001a05 1191 return 1;
43cd72b9
BW		 1192 case option_generics:
1193 as_warn (_("--generics is deprecated; use --transform instead"));
1194 return md_parse_option (option_transform, arg);
1195 case option_no_generics:
1196 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
1197 return md_parse_option (option_no_transform, arg);
1198 case option_relax:
1199 as_warn (_("--relax is deprecated; use --transform instead"));
1200 return md_parse_option (option_transform, arg);
1201 case option_no_relax:
1202 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
1203 return md_parse_option (option_no_transform, arg);
e0001a05
NC		 1204 case option_longcalls:
1205 directive_state[directive_longcalls] = TRUE;
1206 return 1;
1207 case option_no_longcalls:
1208 directive_state[directive_longcalls] = FALSE;
1209 return 1;
1210 case option_text_section_literals:
1211 use_literal_section = FALSE;
1212 return 1;
1213 case option_no_text_section_literals:
1214 use_literal_section = TRUE;
1215 return 1;
43cd72b9
BW		 1216 case option_absolute_literals:
1217 if (!absolute_literals_supported)
1218 {
1219 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
1220 return 0;
1221 }
1222 directive_state[directive_absolute_literals] = TRUE;
1223 return 1;
1224 case option_no_absolute_literals:
1225 directive_state[directive_absolute_literals] = FALSE;
1226 return 1;
1227
e0001a05
NC		 1228 case option_workaround_a0_b_retw:
1229 workaround_a0_b_retw = TRUE;
e0001a05
NC		 1230 return 1;
1231 case option_no_workaround_a0_b_retw:
1232 workaround_a0_b_retw = FALSE;
e0001a05
NC		 1233 return 1;
1234 case option_workaround_b_j_loop_end:
1235 workaround_b_j_loop_end = TRUE;
e0001a05
NC		 1236 return 1;
1237 case option_no_workaround_b_j_loop_end:
1238 workaround_b_j_loop_end = FALSE;
e0001a05
NC		 1239 return 1;
1240
1241 case option_workaround_short_loop:
1242 workaround_short_loop = TRUE;
e0001a05
NC		 1243 return 1;
1244 case option_no_workaround_short_loop:
1245 workaround_short_loop = FALSE;
e0001a05
NC		 1246 return 1;
1247
1248 case option_workaround_all_short_loops:
1249 workaround_all_short_loops = TRUE;
e0001a05
NC		 1250 return 1;
1251 case option_no_workaround_all_short_loops:
1252 workaround_all_short_loops = FALSE;
e0001a05
NC		 1253 return 1;
1254
1255 case option_workaround_close_loop_end:
1256 workaround_close_loop_end = TRUE;
e0001a05
NC		 1257 return 1;
1258 case option_no_workaround_close_loop_end:
1259 workaround_close_loop_end = FALSE;
e0001a05
NC		 1260 return 1;
1261
1262 case option_no_workarounds:
1263 workaround_a0_b_retw = FALSE;
e0001a05 1264 workaround_b_j_loop_end = FALSE;
e0001a05 1265 workaround_short_loop = FALSE;
e0001a05 1266 workaround_all_short_loops = FALSE;
e0001a05 1267 workaround_close_loop_end = FALSE;
e0001a05 1268 return 1;
43cd72b9 1269
e0001a05
NC		 1270 case option_align_targets:
1271 align_targets = TRUE;
1272 return 1;
1273 case option_no_align_targets:
1274 align_targets = FALSE;
1275 return 1;
1276
43cd72b9
BW		 1277 case option_warn_unaligned_targets:
1278 warn_unaligned_branch_targets = TRUE;
e0001a05
NC		 1279 return 1;
1280
1281#ifdef XTENSA_SECTION_RENAME
e0001a05
NC		 1282 case option_rename_section_name:
1283 build_section_rename (arg);
1284 return 1;
1285#endif /* XTENSA_SECTION_RENAME */
1286
1287 case 'Q':
1288 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1289 should be emitted or not. FIXME: Not implemented. */
1290 return 1;
1291
43cd72b9
BW		 1292 case option_prefer_l32r:
1293 if (prefer_const16)
1294 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
1295 prefer_l32r = 1;
1296 return 1;
1297
1298 case option_prefer_const16:
1299 if (prefer_l32r)
1300 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
1301 prefer_const16 = 1;
1302 return 1;
1303
1304 case option_target_hardware:
1305 {
1306 int earliest, latest = 0;
1307 if (*arg == 0 || *arg == '-')
1308 as_fatal (_("invalid target hardware version"));
1309
1310 earliest = strtol (arg, &arg, 0);
1311
1312 if (*arg == 0)
1313 latest = earliest;
1314 else if (*arg == '-')
1315 {
1316 if (*++arg == 0)
1317 as_fatal (_("invalid target hardware version"));
1318 latest = strtol (arg, &arg, 0);
1319 }
1320 if (*arg != 0)
1321 as_fatal (_("invalid target hardware version"));
1322
1323 xtensa_setup_hw_workarounds (earliest, latest);
1324 return 1;
1325 }
1326
1327 case option_transform:
1328 /* This option has no affect other than to use the defaults,
1329 which are already set. */
1330 return 1;
1331
1332 case option_no_transform:
1333 /* This option turns off all transformations of any kind.
1334 However, because we want to preserve the state of other
1335 directives, we only change its own field. Thus, before
1336 you perform any transformation, always check if transform
1337 is available. If you use the functions we provide for this
1338 purpose, you will be ok. */
1339 directive_state[directive_transform] = FALSE;
1340 return 1;
1341
e0001a05
NC		 1342 default:
1343 return 0;
1344 }
1345}
1346
1347
1348void
1349md_show_usage (stream)
1350 FILE *stream;
1351{
43cd72b9
BW		 1352 fputs ("\n\
1353Xtensa options:\n\
1354--[no-]text-section-literals\n\
1355 [Do not] put literals in the text section\n\
1356--[no-]absolute-literals\n\
1357 [Do not] default to use non-PC-relative literals\n\
1358--[no-]target-align [Do not] try to align branch targets\n\
1359--[no-]longcalls [Do not] emit 32-bit call sequences\n\
1360--[no-]transform [Do not] transform instructions\n"
e0001a05 1361#ifdef XTENSA_SECTION_RENAME
43cd72b9
BW		 1362"--rename-section old=new(:old1=new1)*\n\
1363 Rename section 'old' to 'new'\n"
1364#endif /* XTENSA_SECTION_RENAME */
e0001a05
NC		 1365 , stream);
1366}
1367
43cd72b9
BW		 1368
1369static void
1370xtensa_setup_hw_workarounds (earliest, latest)
1371 int earliest;
1372 int latest;
1373{
1374 if (earliest > latest)
1375 as_fatal (_("illegal range of target hardware versions"));
1376
1377 /* Enable all workarounds for pre-T1050.0 hardware. */
1378 if (earliest < 105000 || latest < 105000)
1379 {
1380 workaround_a0_b_retw |= TRUE;
1381 workaround_b_j_loop_end |= TRUE;
1382 workaround_short_loop |= TRUE;
1383 workaround_close_loop_end |= TRUE;
1384 workaround_all_short_loops |= TRUE;
1385 }
1386}
1387
e0001a05
NC		 1388\f
1389/* Directive data and functions. */
1390
1391typedef struct state_stackS_struct
1392{
1393 directiveE directive;
1394 bfd_boolean negated;
1395 bfd_boolean old_state;
1396 const char *file;
1397 unsigned int line;
1398 const void *datum;
1399 struct state_stackS_struct *prev;
1400} state_stackS;
1401
1402state_stackS *directive_state_stack;
1403
1404const pseudo_typeS md_pseudo_table[] =
1405{
43cd72b9
BW		 1406 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1407 { "literal_position", xtensa_literal_position, 0 },
1408 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1409 { "long", xtensa_elf_cons, 4 },
1410 { "word", xtensa_elf_cons, 4 },
1411 { "short", xtensa_elf_cons, 2 },
1412 { "begin", xtensa_begin_directive, 0 },
1413 { "end", xtensa_end_directive, 0 },
1414 { "loc", xtensa_dwarf2_directive_loc, 0 },
1415 { "literal", xtensa_literal_pseudo, 0 },
1416 { "frequency", xtensa_frequency_pseudo, 0 },
1417 { NULL, 0, 0 },
e0001a05
NC		 1418};
1419
1420
1421bfd_boolean
43cd72b9 1422use_transform ()
e0001a05 1423{
43cd72b9
BW		 1424 /* After md_end, you should be checking frag by frag, rather
1425 than state directives. */
1426 assert (!past_xtensa_end);
1427 return directive_state[directive_transform];
e0001a05
NC		 1428}
1429
1430
1431bfd_boolean
1432use_longcalls ()
1433{
43cd72b9
BW		 1434 /* After md_end, you should be checking frag by frag, rather
1435 than state directives. */
1436 assert (!past_xtensa_end);
1437 return directive_state[directive_longcalls] && use_transform ();
e0001a05
NC		 1438}
1439
1440
1441bfd_boolean
43cd72b9 1442do_align_targets ()
e0001a05 1443{
43cd72b9
BW		 1444 /* After md_end, you should be checking frag by frag, rather
1445 than state directives. */
1446 assert (!past_xtensa_end);
1447 return align_targets && use_transform ();
e0001a05
NC		 1448}
1449
1450
1451static void
1452directive_push (directive, negated, datum)
1453 directiveE directive;
1454 bfd_boolean negated;
1455 const void *datum;
1456{
1457 char *file;
1458 unsigned int line;
1459 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1460
1461 as_where (&file, &line);
1462
1463 stack->directive = directive;
1464 stack->negated = negated;
1465 stack->old_state = directive_state[directive];
1466 stack->file = file;
1467 stack->line = line;
1468 stack->datum = datum;
1469 stack->prev = directive_state_stack;
1470 directive_state_stack = stack;
1471
1472 directive_state[directive] = !negated;
1473}
1474
1475static void
1476directive_pop (directive, negated, file, line, datum)
1477 directiveE *directive;
1478 bfd_boolean *negated;
1479 const char **file;
1480 unsigned int *line;
1481 const void **datum;
1482{
1483 state_stackS *top = directive_state_stack;
1484
1485 if (!directive_state_stack)
1486 {
1487 as_bad (_("unmatched end directive"));
1488 *directive = directive_none;
1489 return;
1490 }
1491
1492 directive_state[directive_state_stack->directive] = top->old_state;
1493 *directive = top->directive;
1494 *negated = top->negated;
1495 *file = top->file;
1496 *line = top->line;
1497 *datum = top->datum;
1498 directive_state_stack = top->prev;
1499 free (top);
1500}
1501
1502
1503static void
1504directive_balance ()
1505{
1506 while (directive_state_stack)
1507 {
1508 directiveE directive;
1509 bfd_boolean negated;
1510 const char *file;
1511 unsigned int line;
1512 const void *datum;
1513
1514 directive_pop (&directive, &negated, &file, &line, &datum);
1515 as_warn_where ((char *) file, line,
1516 _(".begin directive with no matching .end directive"));
1517 }
1518}
1519
1520
1521static bfd_boolean
1522inside_directive (dir)
1523 directiveE dir;
1524{
1525 state_stackS *top = directive_state_stack;
1526
1527 while (top && top->directive != dir)
1528 top = top->prev;
1529
1530 return (top != NULL);
1531}
1532
1533
1534static void
1535get_directive (directive, negated)
1536 directiveE *directive;
1537 bfd_boolean *negated;
1538{
1539 int len;
1540 unsigned i;
43cd72b9 1541 char *directive_string;
e0001a05
NC		 1542
1543 if (strncmp (input_line_pointer, "no-", 3) != 0)
1544 *negated = FALSE;
1545 else
1546 {
1547 *negated = TRUE;
1548 input_line_pointer += 3;
1549 }
1550
1551 len = strspn (input_line_pointer,
43cd72b9
BW		 1552 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1553
1554 /* This code is a hack to make .begin [no-][generics|relax] exactly
1555 equivalent to .begin [no-]transform. We should remove it when
1556 we stop accepting those options. */
1557
1558 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1559 {
1560 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1561 directive_string = "transform";
1562 }
1563 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1564 {
1565 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1566 directive_string = "transform";
1567 }
1568 else
1569 directive_string = input_line_pointer;
e0001a05
NC		 1570
1571 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1572 {
43cd72b9 1573 if (strncmp (directive_string, directive_info[i].name, len) == 0)
e0001a05
NC		 1574 {
1575 input_line_pointer += len;
1576 *directive = (directiveE) i;
1577 if (*negated && !directive_info[i].can_be_negated)
43cd72b9 1578 as_bad (_("directive %s cannot be negated"),
e0001a05
NC		 1579 directive_info[i].name);
1580 return;
1581 }
1582 }
1583
1584 as_bad (_("unknown directive"));
1585 *directive = (directiveE) XTENSA_UNDEFINED;
1586}
1587
1588
1589static void
1590xtensa_begin_directive (ignore)
1591 int ignore ATTRIBUTE_UNUSED;
1592{
1593 directiveE directive;
1594 bfd_boolean negated;
1595 emit_state *state;
1596 int len;
1597 lit_state *ls;
1598
1599 get_directive (&directive, &negated);
1600 if (directive == (directiveE) XTENSA_UNDEFINED)
1601 {
1602 discard_rest_of_line ();
1603 return;
1604 }
1605
43cd72b9
BW		 1606 if (cur_vinsn.inside_bundle)
1607 as_bad (_("directives are not valid inside bundles"));
1608
e0001a05
NC		 1609 switch (directive)
1610 {
1611 case directive_literal:
82e7541d
BW		 1612 if (!inside_directive (directive_literal))
1613 {
1614 /* Previous labels go with whatever follows this directive, not with
1615 the literal, so save them now. */
1616 saved_insn_labels = insn_labels;
1617 insn_labels = NULL;
1618 }
43cd72b9 1619 as_warn (_(".begin literal is deprecated; use .literal instead"));
e0001a05
NC		 1620 state = (emit_state *) xmalloc (sizeof (emit_state));
1621 xtensa_switch_to_literal_fragment (state);
1622 directive_push (directive_literal, negated, state);
1623 break;
1624
1625 case directive_literal_prefix:
43cd72b9
BW		 1626 /* Have to flush pending output because a movi relaxed to an l32r
1627 might produce a literal. */
1628 md_flush_pending_output ();
e0001a05
NC		 1629 /* Check to see if the current fragment is a literal
1630 fragment. If it is, then this operation is not allowed. */
43cd72b9 1631 if (generating_literals)
e0001a05
NC		 1632 {
1633 as_bad (_("cannot set literal_prefix inside literal fragment"));
1634 return;
1635 }
1636
1637 /* Allocate the literal state for this section and push
1638 onto the directive stack. */
1639 ls = xmalloc (sizeof (lit_state));
1640 assert (ls);
1641
1642 *ls = default_lit_sections;
1643
1644 directive_push (directive_literal_prefix, negated, ls);
1645
1646 /* Parse the new prefix from the input_line_pointer. */
1647 SKIP_WHITESPACE ();
1648 len = strspn (input_line_pointer,
1649 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1650 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1651
1652 /* Process the new prefix. */
1653 xtensa_literal_prefix (input_line_pointer, len);
1654
1655 /* Skip the name in the input line. */
1656 input_line_pointer += len;
1657 break;
1658
1659 case directive_freeregs:
1660 /* This information is currently unused, but we'll accept the statement
1661 and just discard the rest of the line. This won't check the syntax,
1662 but it will accept every correct freeregs directive. */
1663 input_line_pointer += strcspn (input_line_pointer, "\n");
1664 directive_push (directive_freeregs, negated, 0);
1665 break;
1666
43cd72b9
BW		 1667 case directive_schedule:
1668 md_flush_pending_output ();
1669 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1670 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1671 directive_push (directive_schedule, negated, 0);
1672 xtensa_set_frag_assembly_state (frag_now);
1673 break;
1674
e0001a05 1675 case directive_density:
43cd72b9
BW		 1676 as_warn (_(".begin [no-]density is ignored"));
1677 break;
1678
1679 case directive_absolute_literals:
1680 md_flush_pending_output ();
1681 if (!absolute_literals_supported && !negated)
e0001a05 1682 {
43cd72b9 1683 as_warn (_("Xtensa absolute literals option not supported; ignored"));
e0001a05
NC		 1684 break;
1685 }
43cd72b9
BW		 1686 xtensa_set_frag_assembly_state (frag_now);
1687 directive_push (directive, negated, 0);
1688 break;
e0001a05
NC		 1689
1690 default:
43cd72b9
BW		 1691 md_flush_pending_output ();
1692 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1693 directive_push (directive, negated, 0);
1694 break;
1695 }
1696
1697 demand_empty_rest_of_line ();
1698}
1699
1700
1701static void
1702xtensa_end_directive (ignore)
1703 int ignore ATTRIBUTE_UNUSED;
1704{
1705 directiveE begin_directive, end_directive;
1706 bfd_boolean begin_negated, end_negated;
1707 const char *file;
1708 unsigned int line;
1709 emit_state *state;
43cd72b9 1710 emit_state **state_ptr;
e0001a05
NC		 1711 lit_state *s;
1712
43cd72b9
BW		 1713 if (cur_vinsn.inside_bundle)
1714 as_bad (_("directives are not valid inside bundles"));
82e7541d 1715
e0001a05 1716 get_directive (&end_directive, &end_negated);
43cd72b9
BW		 1717
1718 md_flush_pending_output ();
1719
1720 switch (end_directive)
e0001a05 1721 {
43cd72b9 1722 case (directiveE) XTENSA_UNDEFINED:
e0001a05
NC		 1723 discard_rest_of_line ();
1724 return;
e0001a05 1725
43cd72b9
BW		 1726 case directive_density:
1727 as_warn (_(".end [no-]density is ignored"));
e0001a05 1728 demand_empty_rest_of_line ();
43cd72b9
BW		 1729 break;
1730
1731 case directive_absolute_literals:
1732 if (!absolute_literals_supported && !end_negated)
1733 {
1734 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1735 demand_empty_rest_of_line ();
1736 return;
1737 }
1738 break;
1739
1740 default:
1741 break;
e0001a05
NC		 1742 }
1743
43cd72b9 1744 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
e0001a05 1745 directive_pop (&begin_directive, &begin_negated, &file, &line,
43cd72b9 1746 (const void **) state_ptr);
e0001a05
NC		 1747
1748 if (begin_directive != directive_none)
1749 {
1750 if (begin_directive != end_directive || begin_negated != end_negated)
1751 {
1752 as_bad (_("does not match begin %s%s at %s:%d"),
1753 begin_negated ? "no-" : "",
1754 directive_info[begin_directive].name, file, line);
1755 }
1756 else
1757 {
1758 switch (end_directive)
1759 {
1760 case directive_literal:
1761 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1762 xtensa_restore_emit_state (state);
43cd72b9 1763 xtensa_set_frag_assembly_state (frag_now);
e0001a05 1764 free (state);
82e7541d
BW		 1765 if (!inside_directive (directive_literal))
1766 {
1767 /* Restore the list of current labels. */
1768 xtensa_clear_insn_labels ();
1769 insn_labels = saved_insn_labels;
1770 }
e0001a05
NC		 1771 break;
1772
e0001a05
NC		 1773 case directive_literal_prefix:
1774 /* Restore the default collection sections from saved state. */
1775 s = (lit_state *) state;
1776 assert (s);
1777
1778 if (use_literal_section)
1779 default_lit_sections = *s;
1780
1781 /* free the state storage */
1782 free (s);
1783 break;
1784
43cd72b9
BW		 1785 case directive_schedule:
1786 case directive_freeregs:
1787 break;
1788
e0001a05 1789 default:
43cd72b9 1790 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1791 break;
1792 }
1793 }
1794 }
1795
1796 demand_empty_rest_of_line ();
1797}
1798
1799
43cd72b9
BW		 1800/* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1801
1802static bfd_boolean xtensa_loc_directive_seen = FALSE;
1803
1804static void
1805xtensa_dwarf2_directive_loc (x)
1806 int x;
1807{
1808 xtensa_loc_directive_seen = TRUE;
1809 dwarf2_directive_loc (x);
1810}
1811
1812
1813static void
1814xtensa_dwarf2_emit_insn (size, loc)
1815 int size;
1816 struct dwarf2_line_info *loc;
1817{
1818 if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen)
1819 return;
1820 xtensa_loc_directive_seen = FALSE;
1821 dwarf2_gen_line_info (frag_now_fix () - size, loc);
1822}
1823
1824
e0001a05
NC		 1825/* Place an aligned literal fragment at the current location. */
1826
1827static void
1828xtensa_literal_position (ignore)
1829 int ignore ATTRIBUTE_UNUSED;
1830{
43cd72b9
BW		 1831 md_flush_pending_output ();
1832
e0001a05
NC		 1833 if (inside_directive (directive_literal))
1834 as_warn (_(".literal_position inside literal directive; ignoring"));
43cd72b9 1835 xtensa_mark_literal_pool_location ();
e0001a05
NC		 1836
1837 demand_empty_rest_of_line ();
82e7541d 1838 xtensa_clear_insn_labels ();
e0001a05
NC		 1839}
1840
1841
43cd72b9 1842/* Support .literal label, expr, ... */
e0001a05
NC		 1843
1844static void
1845xtensa_literal_pseudo (ignored)
1846 int ignored ATTRIBUTE_UNUSED;
1847{
1848 emit_state state;
1745fcba 1849 char *p, *base_name;
e0001a05 1850 char c;
e0001a05
NC		 1851 segT dest_seg;
1852
82e7541d
BW		 1853 if (inside_directive (directive_literal))
1854 {
1855 as_bad (_(".literal not allowed inside .begin literal region"));
1856 ignore_rest_of_line ();
1857 return;
1858 }
1859
43cd72b9
BW		 1860 md_flush_pending_output ();
1861
82e7541d
BW		 1862 /* Previous labels go with whatever follows this directive, not with
1863 the literal, so save them now. */
1864 saved_insn_labels = insn_labels;
1865 insn_labels = NULL;
1866
e0001a05
NC		 1867 /* If we are using text-section literals, then this is the right value... */
1868 dest_seg = now_seg;
1869
1870 base_name = input_line_pointer;
1871
1872 xtensa_switch_to_literal_fragment (&state);
1873
43cd72b9 1874 /* ...but if we aren't using text-section-literals, then we
e0001a05 1875 need to put them in the section we just switched to. */
43cd72b9 1876 if (use_literal_section || directive_state[directive_absolute_literals])
e0001a05
NC		 1877 dest_seg = now_seg;
1878
43cd72b9
BW		 1879 /* All literals are aligned to four-byte boundaries. */
1880 frag_align (2, 0, 0);
1881 record_alignment (now_seg, 2);
e0001a05
NC		 1882
1883 c = get_symbol_end ();
1884 /* Just after name is now '\0'. */
1885 p = input_line_pointer;
1886 *p = c;
1887 SKIP_WHITESPACE ();
1888
1889 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1890 {
1891 as_bad (_("expected comma or colon after symbol name; "
1892 "rest of line ignored"));
1893 ignore_rest_of_line ();
1894 xtensa_restore_emit_state (&state);
1895 return;
1896 }
1897 *p = 0;
1898
e0001a05 1899 colon (base_name);
e0001a05 1900
e0001a05 1901 *p = c;
43cd72b9 1902 input_line_pointer++; /* skip ',' or ':' */
e0001a05 1903
43cd72b9 1904 xtensa_elf_cons (4);
e0001a05
NC		 1905
1906 xtensa_restore_emit_state (&state);
82e7541d
BW		 1907
1908 /* Restore the list of current labels. */
1909 xtensa_clear_insn_labels ();
1910 insn_labels = saved_insn_labels;
e0001a05
NC		 1911}
1912
1913
1914static void
1915xtensa_literal_prefix (start, len)
1916 char const *start;
1917 int len;
1918{
43cd72b9
BW		 1919 char *name, *linkonce_suffix;
1920 char *newname, *newname4;
1921 size_t linkonce_len;
e0001a05
NC		 1922
1923 /* Get a null-terminated copy of the name. */
1924 name = xmalloc (len + 1);
1925 assert (name);
1926
1927 strncpy (name, start, len);
1928 name[len] = 0;
1929
1930 /* Allocate the sections (interesting note: the memory pointing to
1931 the name is actually used for the name by the new section). */
43cd72b9 1932
e0001a05 1933 newname = xmalloc (len + strlen (".literal") + 1);
43cd72b9 1934 newname4 = xmalloc (len + strlen (".lit4") + 1);
e0001a05 1935
43cd72b9
BW		 1936 linkonce_len = sizeof (".gnu.linkonce.") - 1;
1937 if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
1938 && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
1939 {
1940 strcpy (newname, ".gnu.linkonce.literal");
1941 strcpy (newname4, ".gnu.linkonce.lit4");
e0001a05 1942
43cd72b9
BW		 1943 strcat (newname, linkonce_suffix);
1944 strcat (newname4, linkonce_suffix);
1945 }
1946 else
1947 {
1948 int suffix_pos = len;
1949
1950 /* If the section name ends with ".text", then replace that suffix
1951 instead of appending an additional suffix. */
1952 if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
1953 suffix_pos -= 5;
1954
1955 strcpy (newname, name);
1956 strcpy (newname4, name);
1957
1958 strcpy (newname + suffix_pos, ".literal");
1959 strcpy (newname4 + suffix_pos, ".lit4");
1960 }
1961
1962 /* Note that retrieve_literal_seg does not create a segment if
1963 it already exists. */
1964 default_lit_sections.lit_seg = NULL;
1965 default_lit_sections.lit4_seg = NULL;
1966
1967 /* Canonicalizing section names allows renaming literal
e0001a05 1968 sections to occur correctly. */
43cd72b9
BW		 1969 default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
1970 default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
e0001a05
NC		 1971
1972 free (name);
43cd72b9
BW		 1973}
1974
1975
1976/* Support ".frequency branch_target_frequency fall_through_frequency". */
1977
1978static void
1979xtensa_frequency_pseudo (ignored)
1980 int ignored ATTRIBUTE_UNUSED;
1981{
1982 float fall_through_f, target_f;
1983 subseg_map *seginfo;
1984
1985 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1986 if (fall_through_f < 0)
1987 {
1988 as_bad (_("fall through frequency must be greater than 0"));
1989 ignore_rest_of_line ();
1990 return;
1991 }
1992
1993 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1994 if (target_f < 0)
1995 {
1996 as_bad (_("branch target frequency must be greater than 0"));
1997 ignore_rest_of_line ();
1998 return;
1999 }
2000
2001 seginfo = get_subseg_info (now_seg, now_subseg);
2002 seginfo->cur_target_freq = target_f;
2003 seginfo->cur_total_freq = target_f + fall_through_f;
2004
2005 demand_empty_rest_of_line ();
2006}
2007
2008
2009/* Like normal .long/.short/.word, except support @plt, etc.
2010 Clobbers input_line_pointer, checks end-of-line. */
2011
2012static void
2013xtensa_elf_cons (nbytes)
2014 int nbytes;
2015{
2016 expressionS exp;
2017 bfd_reloc_code_real_type reloc;
2018
2019 md_flush_pending_output ();
2020
2021 if (cur_vinsn.inside_bundle)
2022 as_bad (_("directives are not valid inside bundles"));
2023
2024 if (is_it_end_of_statement ())
2025 {
2026 demand_empty_rest_of_line ();
2027 return;
2028 }
2029
2030 do
2031 {
2032 expression (&exp);
2033 if (exp.X_op == O_symbol
2034 && *input_line_pointer == '@'
2035 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
2036 != BFD_RELOC_NONE))
2037 {
2038 reloc_howto_type *reloc_howto =
2039 bfd_reloc_type_lookup (stdoutput, reloc);
2040
2041 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
2042 as_bad (_("unsupported relocation"));
2043 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2044 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2045 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2046 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
2047 as_bad (_("opcode-specific %s relocation used outside "
2048 "an instruction"), reloc_howto->name);
2049 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
2050 as_bad (_("%s relocations do not fit in %d bytes"),
2051 reloc_howto->name, nbytes);
2052 else
2053 {
2054 char *p = frag_more ((int) nbytes);
2055 xtensa_set_frag_assembly_state (frag_now);
2056 fix_new_exp (frag_now, p - frag_now->fr_literal,
2057 nbytes, &exp, 0, reloc);
2058 }
2059 }
2060 else
2061 emit_expr (&exp, (unsigned int) nbytes);
2062 }
2063 while (*input_line_pointer++ == ',');
2064
2065 input_line_pointer--; /* Put terminator back into stream. */
2066 demand_empty_rest_of_line ();
2067}
2068
2069
2070/* Parse @plt, etc. and return the desired relocation. */
2071static bfd_reloc_code_real_type
2072xtensa_elf_suffix (str_p, exp_p)
2073 char **str_p;
2074 expressionS *exp_p;
2075{
2076 struct map_bfd
2077 {
2078 char *string;
2079 int length;
2080 bfd_reloc_code_real_type reloc;
2081 };
2082
2083 char ident[20];
2084 char *str = *str_p;
2085 char *str2;
2086 int ch;
2087 int len;
2088 struct map_bfd *ptr;
2089
2090#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
e0001a05 2091
43cd72b9
BW		 2092 static struct map_bfd mapping[] =
2093 {
2094 MAP ("l", BFD_RELOC_LO16),
2095 MAP ("h", BFD_RELOC_HI16),
2096 MAP ("plt", BFD_RELOC_XTENSA_PLT),
2097 { (char *) 0, 0, BFD_RELOC_UNUSED }
2098 };
2099
2100 if (*str++ != '@')
2101 return BFD_RELOC_NONE;
2102
2103 for (ch = *str, str2 = ident;
2104 (str2 < ident + sizeof (ident) - 1
2105 && (ISALNUM (ch) || ch == '@'));
2106 ch = *++str)
2107 {
2108 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
2109 }
2110
2111 *str2 = '\0';
2112 len = str2 - ident;
2113
2114 ch = ident[0];
2115 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
2116 if (ch == ptr->string[0]
2117 && len == ptr->length
2118 && memcmp (ident, ptr->string, ptr->length) == 0)
2119 {
2120 /* Now check for "identifier@suffix+constant". */
2121 if (*str == '-' || *str == '+')
2122 {
2123 char *orig_line = input_line_pointer;
2124 expressionS new_exp;
2125
2126 input_line_pointer = str;
2127 expression (&new_exp);
2128 if (new_exp.X_op == O_constant)
2129 {
2130 exp_p->X_add_number += new_exp.X_add_number;
2131 str = input_line_pointer;
2132 }
2133
2134 if (&input_line_pointer != str_p)
2135 input_line_pointer = orig_line;
2136 }
2137
2138 *str_p = str;
2139 return ptr->reloc;
2140 }
2141
2142 return BFD_RELOC_UNUSED;
e0001a05
NC		 2143}
2144
2145\f
2146/* Parsing and Idiom Translation. */
2147
2148static const char *
2149expression_end (name)
2150 const char *name;
2151{
2152 while (1)
2153 {
2154 switch (*name)
2155 {
43cd72b9 2156 case '}':
e0001a05
NC		 2157 case ';':
2158 case '\0':
2159 case ',':
43cd72b9 2160 case ':':
e0001a05
NC		 2161 return name;
2162 case ' ':
2163 case '\t':
2164 ++name;
2165 continue;
2166 default:
2167 return 0;
2168 }
2169 }
2170}
2171
2172
2173#define ERROR_REG_NUM ((unsigned) -1)
2174
2175static unsigned
2176tc_get_register (prefix)
2177 const char *prefix;
2178{
2179 unsigned reg;
2180 const char *next_expr;
2181 const char *old_line_pointer;
2182
2183 SKIP_WHITESPACE ();
2184 old_line_pointer = input_line_pointer;
2185
2186 if (*input_line_pointer == '$')
2187 ++input_line_pointer;
2188
2189 /* Accept "sp" as a synonym for "a1". */
2190 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
2191 && expression_end (input_line_pointer + 2))
2192 {
2193 input_line_pointer += 2;
2194 return 1; /* AR[1] */
2195 }
2196
2197 while (*input_line_pointer++ == *prefix++)
2198 ;
2199 --input_line_pointer;
2200 --prefix;
2201
2202 if (*prefix)
2203 {
2204 as_bad (_("bad register name: %s"), old_line_pointer);
2205 return ERROR_REG_NUM;
2206 }
2207
2208 if (!ISDIGIT ((unsigned char) *input_line_pointer))
2209 {
2210 as_bad (_("bad register number: %s"), input_line_pointer);
2211 return ERROR_REG_NUM;
2212 }
2213
2214 reg = 0;
2215
2216 while (ISDIGIT ((int) *input_line_pointer))
2217 reg = reg * 10 + *input_line_pointer++ - '0';
2218
2219 if (!(next_expr = expression_end (input_line_pointer)))
2220 {
2221 as_bad (_("bad register name: %s"), old_line_pointer);
2222 return ERROR_REG_NUM;
2223 }
2224
2225 input_line_pointer = (char *) next_expr;
2226
2227 return reg;
2228}
2229
2230
e0001a05 2231static void
43cd72b9
BW		 2232expression_maybe_register (opc, opnd, tok)
2233 xtensa_opcode opc;
2234 int opnd;
e0001a05
NC		 2235 expressionS *tok;
2236{
43cd72b9 2237 xtensa_isa isa = xtensa_default_isa;
e0001a05 2238
43cd72b9
BW		 2239 /* Check if this is an immediate operand. */
2240 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
e0001a05 2241 {
43cd72b9 2242 bfd_reloc_code_real_type reloc;
e0001a05 2243 segT t = expression (tok);
43cd72b9
BW		 2244 if (t == absolute_section
2245 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
e0001a05
NC		 2246 {
2247 assert (tok->X_op == O_constant);
2248 tok->X_op = O_symbol;
2249 tok->X_add_symbol = &abs_symbol;
2250 }
43cd72b9
BW		 2251
2252 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
2253 && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
2254 && (reloc != BFD_RELOC_NONE))
e0001a05 2255 {
43cd72b9
BW		 2256 switch (reloc)
2257 {
2258 default:
2259 case BFD_RELOC_UNUSED:
2260 as_bad (_("unsupported relocation"));
2261 break;
2262
2263 case BFD_RELOC_XTENSA_PLT:
2264 tok->X_op = O_pltrel;
2265 break;
2266
2267 case BFD_RELOC_LO16:
2268 if (tok->X_op == O_constant)
2269 tok->X_add_number &= 0xffff;
2270 else
2271 tok->X_op = O_lo16;
2272 break;
2273
2274 case BFD_RELOC_HI16:
2275 if (tok->X_op == O_constant)
2276 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
2277 else
2278 tok->X_op = O_hi16;
2279 break;
2280 }
e0001a05 2281 }
e0001a05
NC		 2282 }
2283 else
2284 {
43cd72b9
BW		 2285 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
2286 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
e0001a05
NC		 2287
2288 if (reg != ERROR_REG_NUM) /* Already errored */
2289 {
2290 uint32 buf = reg;
43cd72b9 2291 if (xtensa_operand_encode (isa, opc, opnd, &buf))
e0001a05
NC		 2292 as_bad (_("register number out of range"));
2293 }
2294
2295 tok->X_op = O_register;
2296 tok->X_add_symbol = 0;
2297 tok->X_add_number = reg;
2298 }
2299}
2300
2301
2302/* Split up the arguments for an opcode or pseudo-op. */
2303
2304static int
2305tokenize_arguments (args, str)
2306 char **args;
2307 char *str;
2308{
2309 char *old_input_line_pointer;
2310 bfd_boolean saw_comma = FALSE;
2311 bfd_boolean saw_arg = FALSE;
43cd72b9 2312 bfd_boolean saw_colon = FALSE;
e0001a05
NC		 2313 int num_args = 0;
2314 char *arg_end, *arg;
2315 int arg_len;
43cd72b9
BW		 2316
2317 /* Save and restore input_line_pointer around this function. */
e0001a05
NC		 2318 old_input_line_pointer = input_line_pointer;
2319 input_line_pointer = str;
2320
2321 while (*input_line_pointer)
2322 {
2323 SKIP_WHITESPACE ();
2324 switch (*input_line_pointer)
2325 {
2326 case '\0':
43cd72b9 2327 case '}':
e0001a05
NC		 2328 goto fini;
2329
43cd72b9
BW		 2330 case ':':
2331 input_line_pointer++;
2332 if (saw_comma || saw_colon || !saw_arg)
2333 goto err;
2334 saw_colon = TRUE;
2335 break;
2336
e0001a05
NC		 2337 case ',':
2338 input_line_pointer++;
43cd72b9 2339 if (saw_comma || saw_colon || !saw_arg)
e0001a05
NC		 2340 goto err;
2341 saw_comma = TRUE;
2342 break;
2343
2344 default:
43cd72b9 2345 if (!saw_comma && !saw_colon && saw_arg)
e0001a05
NC		 2346 goto err;
2347
2348 arg_end = input_line_pointer + 1;
2349 while (!expression_end (arg_end))
2350 arg_end += 1;
43cd72b9 2351
e0001a05 2352 arg_len = arg_end - input_line_pointer;
43cd72b9 2353 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
e0001a05
NC		 2354 args[num_args] = arg;
2355
43cd72b9
BW		 2356 if (saw_colon)
2357 *arg++ = ':';
e0001a05
NC		 2358 strncpy (arg, input_line_pointer, arg_len);
2359 arg[arg_len] = '\0';
43cd72b9 2360
e0001a05
NC		 2361 input_line_pointer = arg_end;
2362 num_args += 1;
2363 saw_comma = FALSE;
43cd72b9 2364 saw_colon = FALSE;
e0001a05
NC		 2365 saw_arg = TRUE;
2366 break;
2367 }
2368 }
2369
2370fini:
43cd72b9 2371 if (saw_comma || saw_colon)
e0001a05
NC		 2372 goto err;
2373 input_line_pointer = old_input_line_pointer;
2374 return num_args;
2375
2376err:
43cd72b9
BW		 2377 if (saw_comma)
2378 as_bad (_("extra comma"));
2379 else if (saw_colon)
2380 as_bad (_("extra colon"));
2381 else if (!saw_arg)
2382 as_bad (_("missing argument"));
2383 else
2384 as_bad (_("missing comma or colon"));
e0001a05
NC		 2385 input_line_pointer = old_input_line_pointer;
2386 return -1;
2387}
2388
2389
43cd72b9 2390/* Parse the arguments to an opcode. Return TRUE on error. */
e0001a05
NC		 2391
2392static bfd_boolean
2393parse_arguments (insn, num_args, arg_strings)
2394 TInsn *insn;
2395 int num_args;
2396 char **arg_strings;
2397{
43cd72b9 2398 expressionS *tok, *last_tok;
e0001a05
NC		 2399 xtensa_opcode opcode = insn->opcode;
2400 bfd_boolean had_error = TRUE;
43cd72b9
BW		 2401 xtensa_isa isa = xtensa_default_isa;
2402 int n, num_regs = 0;
e0001a05 2403 int opcode_operand_count;
43cd72b9
BW		 2404 int opnd_cnt, last_opnd_cnt;
2405 unsigned int next_reg = 0;
e0001a05
NC		 2406 char *old_input_line_pointer;
2407
2408 if (insn->insn_type == ITYPE_LITERAL)
2409 opcode_operand_count = 1;
2410 else
43cd72b9 2411 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
e0001a05 2412
43cd72b9 2413 tok = insn->tok;
e0001a05
NC		 2414 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
2415
2416 /* Save and restore input_line_pointer around this function. */
43cd72b9
BW		 2417 old_input_line_pointer = input_line_pointer;
2418
2419 last_tok = 0;
2420 last_opnd_cnt = -1;
2421 opnd_cnt = 0;
2422
2423 /* Skip invisible operands. */
2424 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2425 {
2426 opnd_cnt += 1;
2427 tok++;
2428 }
e0001a05
NC		 2429
2430 for (n = 0; n < num_args; n++)
43cd72b9 2431 {
e0001a05 2432 input_line_pointer = arg_strings[n];
43cd72b9
BW		 2433 if (*input_line_pointer == ':')
2434 {
2435 xtensa_regfile opnd_rf;
2436 input_line_pointer++;
2437 if (num_regs == 0)
2438 goto err;
2439 assert (opnd_cnt > 0);
2440 num_regs--;
2441 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2442 if (next_reg
2443 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2444 as_warn (_("incorrect register number, ignoring"));
2445 next_reg++;
2446 }
2447 else
2448 {
2449 if (opnd_cnt >= opcode_operand_count)
2450 {
2451 as_warn (_("too many arguments"));
2452 goto err;
2453 }
2454 assert (opnd_cnt < MAX_INSN_ARGS);
2455
2456 expression_maybe_register (opcode, opnd_cnt, tok);
2457 next_reg = tok->X_add_number + 1;
2458
2459 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2460 goto err;
2461 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2462 {
2463 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2464 /* minus 1 because we are seeing one right now */
2465 }
2466 else
2467 num_regs = 0;
e0001a05 2468
43cd72b9
BW		 2469 last_tok = tok;
2470 last_opnd_cnt = opnd_cnt;
e0001a05 2471
43cd72b9
BW		 2472 do
2473 {
2474 opnd_cnt += 1;
2475 tok++;
2476 }
2477 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2478 }
2479 }
e0001a05 2480
43cd72b9
BW		 2481 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2482 goto err;
e0001a05
NC		 2483
2484 insn->ntok = tok - insn->tok;
2485 had_error = FALSE;
2486
2487 err:
43cd72b9 2488 input_line_pointer = old_input_line_pointer;
e0001a05
NC		 2489 return had_error;
2490}
2491
2492
43cd72b9
BW		 2493static int
2494get_invisible_operands (insn)
2495 TInsn *insn;
2496{
2497 xtensa_isa isa = xtensa_default_isa;
2498 static xtensa_insnbuf slotbuf = NULL;
2499 xtensa_format fmt;
2500 xtensa_opcode opc = insn->opcode;
2501 int slot, opnd, fmt_found;
2502 unsigned val;
2503
2504 if (!slotbuf)
2505 slotbuf = xtensa_insnbuf_alloc (isa);
2506
2507 /* Find format/slot where this can be encoded. */
2508 fmt_found = 0;
2509 slot = 0;
2510 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2511 {
2512 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2513 {
2514 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2515 {
2516 fmt_found = 1;
2517 break;
2518 }
2519 }
2520 if (fmt_found) break;
2521 }
2522
2523 if (!fmt_found)
2524 {
2525 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2526 return -1;
2527 }
2528
2529 /* First encode all the visible operands
2530 (to deal with shared field operands). */
2531 for (opnd = 0; opnd < insn->ntok; opnd++)
2532 {
2533 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2534 && (insn->tok[opnd].X_op == O_register
2535 || insn->tok[opnd].X_op == O_constant))
2536 {
2537 val = insn->tok[opnd].X_add_number;
2538 xtensa_operand_encode (isa, opc, opnd, &val);
2539 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2540 }
2541 }
2542
2543 /* Then pull out the values for the invisible ones. */
2544 for (opnd = 0; opnd < insn->ntok; opnd++)
2545 {
2546 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2547 {
2548 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2549 xtensa_operand_decode (isa, opc, opnd, &val);
2550 insn->tok[opnd].X_add_number = val;
2551 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2552 insn->tok[opnd].X_op = O_register;
2553 else
2554 insn->tok[opnd].X_op = O_constant;
2555 }
2556 }
2557
2558 return 0;
2559}
2560
2561
e0001a05
NC		 2562static void
2563xg_reverse_shift_count (cnt_argp)
2564 char **cnt_argp;
2565{
2566 char *cnt_arg, *new_arg;
2567 cnt_arg = *cnt_argp;
2568
2569 /* replace the argument with "31-(argument)" */
2570 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2571 sprintf (new_arg, "31-(%s)", cnt_arg);
2572
2573 free (cnt_arg);
2574 *cnt_argp = new_arg;
2575}
2576
2577
2578/* If "arg" is a constant expression, return non-zero with the value
2579 in *valp. */
2580
2581static int
2582xg_arg_is_constant (arg, valp)
2583 char *arg;
2584 offsetT *valp;
2585{
2586 expressionS exp;
2587 char *save_ptr = input_line_pointer;
2588
2589 input_line_pointer = arg;
2590 expression (&exp);
2591 input_line_pointer = save_ptr;
2592
2593 if (exp.X_op == O_constant)
2594 {
2595 *valp = exp.X_add_number;
2596 return 1;
2597 }
2598
2599 return 0;
2600}
2601
2602
2603static void
2604xg_replace_opname (popname, newop)
2605 char **popname;
2606 char *newop;
2607{
2608 free (*popname);
2609 *popname = (char *) xmalloc (strlen (newop) + 1);
2610 strcpy (*popname, newop);
2611}
2612
2613
2614static int
2615xg_check_num_args (pnum_args, expected_num, opname, arg_strings)
2616 int *pnum_args;
43cd72b9 2617 int expected_num;
e0001a05
NC		 2618 char *opname;
2619 char **arg_strings;
2620{
2621 int num_args = *pnum_args;
2622
43cd72b9 2623 if (num_args < expected_num)
e0001a05
NC		 2624 {
2625 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2626 num_args, opname, expected_num);
2627 return -1;
2628 }
2629
2630 if (num_args > expected_num)
2631 {
2632 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2633 num_args, opname, expected_num);
2634 while (num_args-- > expected_num)
2635 {
2636 free (arg_strings[num_args]);
2637 arg_strings[num_args] = 0;
2638 }
2639 *pnum_args = expected_num;
2640 return -1;
2641 }
2642
2643 return 0;
2644}
2645
2646
43cd72b9
BW		 2647/* If the register is not specified as part of the opcode,
2648 then get it from the operand and move it to the opcode. */
2649
e0001a05
NC		 2650static int
2651xg_translate_sysreg_op (popname, pnum_args, arg_strings)
2652 char **popname;
2653 int *pnum_args;
2654 char **arg_strings;
2655{
43cd72b9
BW		 2656 xtensa_isa isa = xtensa_default_isa;
2657 xtensa_sysreg sr;
e0001a05 2658 char *opname, *new_opname;
43cd72b9
BW		 2659 const char *sr_name;
2660 int is_user, is_write;
e0001a05
NC		 2661 bfd_boolean has_underbar = FALSE;
2662
2663 opname = *popname;
2664 if (*opname == '_')
2665 {
2666 has_underbar = TRUE;
2667 opname += 1;
2668 }
43cd72b9
BW		 2669 is_user = (opname[1] == 'u');
2670 is_write = (opname[0] == 'w');
e0001a05 2671
43cd72b9 2672 /* Opname == [rw]ur or [rwx]sr... */
e0001a05 2673
43cd72b9
BW		 2674 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2675 return -1;
e0001a05 2676
43cd72b9
BW		 2677 /* Check if the argument is a symbolic register name. */
2678 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2679 /* Handle WSR to "INTSET" as a special case. */
2680 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2681 && !strcasecmp (arg_strings[1], "intset"))
2682 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2683 if (sr == XTENSA_UNDEFINED
2684 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2685 {
2686 /* Maybe it's a register number.... */
2687 offsetT val;
e0001a05
NC		 2688 if (!xg_arg_is_constant (arg_strings[1], &val))
2689 {
43cd72b9
BW		 2690 as_bad (_("invalid register '%s' for '%s' instruction"),
2691 arg_strings[1], opname);
e0001a05
NC		 2692 return -1;
2693 }
43cd72b9
BW		 2694 sr = xtensa_sysreg_lookup (isa, val, is_user);
2695 if (sr == XTENSA_UNDEFINED)
e0001a05 2696 {
43cd72b9 2697 as_bad (_("invalid register number (%ld) for '%s' instruction"),
e0001a05
NC		 2698 val, opname);
2699 return -1;
2700 }
43cd72b9 2701 }
e0001a05 2702
43cd72b9
BW		 2703 /* Remove the last argument, which is now part of the opcode. */
2704 free (arg_strings[1]);
2705 arg_strings[1] = 0;
2706 *pnum_args = 1;
2707
2708 /* Translate the opcode. */
2709 sr_name = xtensa_sysreg_name (isa, sr);
2710 /* Another special case for "WSR.INTSET".... */
2711 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2712 sr_name = "intset";
2713 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2714 sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""),
2715 *popname, sr_name);
2716 free (*popname);
2717 *popname = new_opname;
2718
2719 return 0;
2720}
2721
2722
2723static int
2724xtensa_translate_old_userreg_ops (popname)
2725 char **popname;
2726{
2727 xtensa_isa isa = xtensa_default_isa;
2728 xtensa_sysreg sr;
2729 char *opname, *new_opname;
2730 const char *sr_name;
2731 bfd_boolean has_underbar = FALSE;
2732
2733 opname = *popname;
2734 if (opname[0] == '_')
2735 {
2736 has_underbar = TRUE;
2737 opname += 1;
2738 }
2739
2740 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2741 if (sr != XTENSA_UNDEFINED)
2742 {
2743 /* The new default name ("nnn") is different from the old default
2744 name ("URnnn"). The old default is handled below, and we don't
2745 want to recognize [RW]nnn, so do nothing if the name is the (new)
2746 default. */
2747 static char namebuf[10];
2748 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2749 if (strcmp (namebuf, opname + 1) == 0)
2750 return 0;
2751 }
2752 else
2753 {
2754 offsetT val;
2755 char *end;
2756
2757 /* Only continue if the reg name is "URnnn". */
2758 if (opname[1] != 'u' || opname[2] != 'r')
2759 return 0;
2760 val = strtoul (opname + 3, &end, 10);
2761 if (*end != '\0')
2762 return 0;
2763
2764 sr = xtensa_sysreg_lookup (isa, val, 1);
2765 if (sr == XTENSA_UNDEFINED)
2766 {
2767 as_bad (_("invalid register number (%ld) for '%s'"),
2768 val, opname);
2769 return -1;
2770 }
2771 }
2772
2773 /* Translate the opcode. */
2774 sr_name = xtensa_sysreg_name (isa, sr);
2775 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2776 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2777 opname[0], sr_name);
2778 free (*popname);
2779 *popname = new_opname;
2780
2781 return 0;
2782}
2783
2784
2785static int
2786xtensa_translate_zero_immed (old_op, new_op, popname, pnum_args, arg_strings)
2787 char *old_op;
2788 char *new_op;
2789 char **popname;
2790 int *pnum_args;
2791 char **arg_strings;
2792{
2793 char *opname;
2794 offsetT val;
2795
2796 opname = *popname;
2797 assert (opname[0] != '_');
2798
2799 if (strcmp (opname, old_op) != 0)
2800 return 0;
e0001a05 2801
43cd72b9
BW		 2802 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2803 return -1;
2804 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2805 {
2806 xg_replace_opname (popname, new_op);
2807 free (arg_strings[1]);
2808 arg_strings[1] = arg_strings[2];
2809 arg_strings[2] = 0;
2810 *pnum_args = 2;
e0001a05
NC		 2811 }
2812
2813 return 0;
2814}
2815
2816
2817/* If the instruction is an idiom (i.e., a built-in macro), translate it.
2818 Returns non-zero if an error was found. */
2819
2820static int
2821xg_translate_idioms (popname, pnum_args, arg_strings)
2822 char **popname;
2823 int *pnum_args;
2824 char **arg_strings;
2825{
2826 char *opname = *popname;
2827 bfd_boolean has_underbar = FALSE;
2828
43cd72b9
BW		 2829 if (cur_vinsn.inside_bundle)
2830 return 0;
2831
e0001a05
NC		 2832 if (*opname == '_')
2833 {
2834 has_underbar = TRUE;
2835 opname += 1;
2836 }
2837
2838 if (strcmp (opname, "mov") == 0)
2839 {
43cd72b9 2840 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2841 xg_replace_opname (popname, "mov.n");
2842 else
2843 {
2844 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2845 return -1;
2846 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2847 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2848 strcpy (arg_strings[2], arg_strings[1]);
2849 *pnum_args = 3;
2850 }
2851 return 0;
2852 }
2853
2854 if (strcmp (opname, "bbsi.l") == 0)
2855 {
2856 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2857 return -1;
2858 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2859 if (target_big_endian)
2860 xg_reverse_shift_count (&arg_strings[1]);
2861 return 0;
2862 }
2863
2864 if (strcmp (opname, "bbci.l") == 0)
2865 {
2866 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2867 return -1;
2868 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2869 if (target_big_endian)
2870 xg_reverse_shift_count (&arg_strings[1]);
2871 return 0;
2872 }
2873
43cd72b9
BW		 2874 if (xtensa_nop_opcode == XTENSA_UNDEFINED
2875 && strcmp (opname, "nop") == 0)
e0001a05 2876 {
43cd72b9 2877 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2878 xg_replace_opname (popname, "nop.n");
2879 else
2880 {
2881 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2882 return -1;
2883 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2884 arg_strings[0] = (char *) xmalloc (3);
2885 arg_strings[1] = (char *) xmalloc (3);
2886 arg_strings[2] = (char *) xmalloc (3);
2887 strcpy (arg_strings[0], "a1");
2888 strcpy (arg_strings[1], "a1");
2889 strcpy (arg_strings[2], "a1");
2890 *pnum_args = 3;
2891 }
2892 return 0;
2893 }
2894
43cd72b9
BW		 2895 /* Recognize [RW]UR and [RWX]SR. */
2896 if ((((opname[0] == 'r' || opname[0] == 'w')
2897 && (opname[1] == 'u' || opname[1] == 's'))
2898 || (opname[0] == 'x' && opname[1] == 's'))
2899 && opname[2] == 'r'
2900 && opname[3] == '\0')
e0001a05
NC		 2901 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2902
43cd72b9
BW		 2903 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2904 [RW]<name> if <name> is the non-default name of a user register. */
2905 if ((opname[0] == 'r' || opname[0] == 'w')
2906 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2907 return xtensa_translate_old_userreg_ops (popname);
e0001a05 2908
43cd72b9
BW		 2909 /* Relax branches that don't allow comparisons against an immediate value
2910 of zero to the corresponding branches with implicit zero immediates. */
2911 if (!has_underbar && use_transform ())
2912 {
2913 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2914 pnum_args, arg_strings))
2915 return -1;
e0001a05 2916
43cd72b9
BW		 2917 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2918 pnum_args, arg_strings))
2919 return -1;
e0001a05 2920
43cd72b9
BW		 2921 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2922 pnum_args, arg_strings))
2923 return -1;
e0001a05 2924
43cd72b9
BW		 2925 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2926 pnum_args, arg_strings))
2927 return -1;
2928 }
e0001a05 2929
43cd72b9
BW		 2930 return 0;
2931}
e0001a05 2932
43cd72b9
BW		 2933\f
2934/* Functions for dealing with the Xtensa ISA. */
e0001a05 2935
43cd72b9
BW		 2936/* Currently the assembler only allows us to use a single target per
2937 fragment. Because of this, only one operand for a given
2938 instruction may be symbolic. If there is a PC-relative operand,
2939 the last one is chosen. Otherwise, the result is the number of the
2940 last immediate operand, and if there are none of those, we fail and
2941 return -1. */
e0001a05 2942
43cd72b9
BW		 2943int
2944get_relaxable_immed (opcode)
2945 xtensa_opcode opcode;
2946{
2947 int last_immed = -1;
2948 int noperands, opi;
e0001a05 2949
43cd72b9
BW		 2950 if (opcode == XTENSA_UNDEFINED)
2951 return -1;
e0001a05 2952
43cd72b9
BW		 2953 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2954 for (opi = noperands - 1; opi >= 0; opi--)
2955 {
2956 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2957 continue;
2958 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2959 return opi;
2960 if (last_immed == -1
2961 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2962 last_immed = opi;
e0001a05 2963 }
43cd72b9 2964 return last_immed;
e0001a05
NC		 2965}
2966
e0001a05 2967
43cd72b9
BW		 2968static xtensa_opcode
2969get_opcode_from_buf (buf, slot)
2970 const char *buf;
2971 int slot;
e0001a05 2972{
43cd72b9
BW		 2973 static xtensa_insnbuf insnbuf = NULL;
2974 static xtensa_insnbuf slotbuf = NULL;
2975 xtensa_isa isa = xtensa_default_isa;
2976 xtensa_format fmt;
2977
2978 if (!insnbuf)
e0001a05 2979 {
43cd72b9
BW		 2980 insnbuf = xtensa_insnbuf_alloc (isa);
2981 slotbuf = xtensa_insnbuf_alloc (isa);
e0001a05 2982 }
e0001a05 2983
43cd72b9
BW		 2984 xtensa_insnbuf_from_chars (isa, insnbuf, buf, 0);
2985 fmt = xtensa_format_decode (isa, insnbuf);
2986 if (fmt == XTENSA_UNDEFINED)
2987 return XTENSA_UNDEFINED;
e0001a05 2988
43cd72b9
BW		 2989 if (slot >= xtensa_format_num_slots (isa, fmt))
2990 return XTENSA_UNDEFINED;
e0001a05 2991
43cd72b9
BW		 2992 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2993 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
e0001a05
NC		 2994}
2995
2996
43cd72b9 2997#ifdef TENSILICA_DEBUG
e0001a05 2998
43cd72b9 2999/* For debugging, print out the mapping of opcode numbers to opcodes. */
e0001a05 3000
43cd72b9
BW		 3001void
3002xtensa_print_insn_table ()
3003{
3004 int num_opcodes, num_operands;
3005 xtensa_opcode opcode;
3006 xtensa_isa isa = xtensa_default_isa;
e0001a05 3007
43cd72b9
BW		 3008 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
3009 for (opcode = 0; opcode < num_opcodes; opcode++)
e0001a05 3010 {
43cd72b9
BW		 3011 int opn;
3012 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
3013 num_operands = xtensa_opcode_num_operands (isa, opcode);
3014 for (opn = 0; opn < num_operands; opn++)
3015 {
3016 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
3017 continue;
3018 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
3019 {
3020 xtensa_regfile opnd_rf =
3021 xtensa_operand_regfile (isa, opcode, opn);
3022 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
3023 }
3024 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
3025 fputs ("[lLr] ", stderr);
3026 else
3027 fputs ("i ", stderr);
3028 }
3029 fprintf (stderr, "\n");
e0001a05 3030 }
e0001a05
NC		 3031}
3032
3033
43cd72b9
BW		 3034static void
3035print_vliw_insn (vbuf)
3036 xtensa_insnbuf vbuf;
e0001a05 3037{
e0001a05 3038 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 3039 xtensa_format f = xtensa_format_decode (isa, vbuf);
3040 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
3041 int op;
e0001a05 3042
43cd72b9 3043 fprintf (stderr, "format = %d\n", f);
e0001a05 3044
43cd72b9
BW		 3045 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
3046 {
3047 xtensa_opcode opcode;
3048 const char *opname;
3049 int operands;
3050
3051 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
3052 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
3053 opname = xtensa_opcode_name (isa, opcode);
3054
3055 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
3056 fprintf (stderr, " operands = ");
3057 for (operands = 0;
3058 operands < xtensa_opcode_num_operands (isa, opcode);
3059 operands++)
3060 {
3061 unsigned int val;
3062 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
3063 continue;
3064 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
3065 xtensa_operand_decode (isa, opcode, operands, &val);
3066 fprintf (stderr, "%d ", val);
3067 }
3068 fprintf (stderr, "\n");
3069 }
3070 xtensa_insnbuf_free (isa, sbuf);
e0001a05
NC		 3071}
3072
43cd72b9
BW		 3073#endif /* TENSILICA_DEBUG */
3074
e0001a05
NC		 3075
3076static bfd_boolean
43cd72b9 3077is_direct_call_opcode (opcode)
e0001a05
NC		 3078 xtensa_opcode opcode;
3079{
43cd72b9
BW		 3080 xtensa_isa isa = xtensa_default_isa;
3081 int n, num_operands;
e0001a05 3082
43cd72b9 3083 if (xtensa_opcode_is_call (isa, opcode) == 0)
e0001a05
NC		 3084 return FALSE;
3085
43cd72b9
BW		 3086 num_operands = xtensa_opcode_num_operands (isa, opcode);
3087 for (n = 0; n < num_operands; n++)
3088 {
3089 if (xtensa_operand_is_register (isa, opcode, n) == 0
3090 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
3091 return TRUE;
3092 }
3093 return FALSE;
e0001a05
NC		 3094}
3095
3096
43cd72b9 3097/* Return TRUE if the opcode is an entry opcode. This is used because
e0001a05
NC		 3098 "entry" adds an implicit ".align 4" and also the entry instruction
3099 has an extra check for an operand value. */
3100
3101static bfd_boolean
3102is_entry_opcode (opcode)
3103 xtensa_opcode opcode;
3104{
3105 if (opcode == XTENSA_UNDEFINED)
3106 return FALSE;
3107
3108 return (opcode == xtensa_entry_opcode);
3109}
3110
3111
43cd72b9
BW		 3112/* Return TRUE if the opcode is a movi or movi.n opcode. This is
3113 so we can relax "movi aX, foo" in the front end. */
e0001a05
NC		 3114
3115static bfd_boolean
43cd72b9 3116is_movi_opcode (opcode)
e0001a05
NC		 3117 xtensa_opcode opcode;
3118{
3119 if (opcode == XTENSA_UNDEFINED)
3120 return FALSE;
3121
43cd72b9
BW		 3122 return (opcode == xtensa_movi_opcode)
3123 || (opcode == xtensa_movi_n_opcode);
e0001a05
NC		 3124}
3125
3126
3127static bfd_boolean
3128is_the_loop_opcode (opcode)
3129 xtensa_opcode opcode;
3130{
3131 if (opcode == XTENSA_UNDEFINED)
3132 return FALSE;
3133
3134 return (opcode == xtensa_loop_opcode);
3135}
3136
3137
3138static bfd_boolean
3139is_jx_opcode (opcode)
3140 xtensa_opcode opcode;
3141{
3142 if (opcode == XTENSA_UNDEFINED)
3143 return FALSE;
3144
3145 return (opcode == xtensa_jx_opcode);
3146}
3147
3148
43cd72b9 3149/* Return TRUE if the opcode is a retw or retw.n.
e0001a05
NC		 3150 Needed to add nops to avoid a hardware interlock issue. */
3151
3152static bfd_boolean
3153is_windowed_return_opcode (opcode)
3154 xtensa_opcode opcode;
3155{
3156 if (opcode == XTENSA_UNDEFINED)
3157 return FALSE;
3158
3159 return (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode);
3160}
3161
3162
43cd72b9
BW		 3163/* Convert from BFD relocation type code to slot and operand number.
3164 Returns non-zero on failure. */
e0001a05 3165
43cd72b9
BW		 3166static int
3167decode_reloc (reloc, slot, is_alt)
3168 bfd_reloc_code_real_type reloc;
3169 int *slot;
3170 bfd_boolean *is_alt;
e0001a05 3171{
43cd72b9
BW		 3172 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
3173 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
e0001a05 3174 {
43cd72b9
BW		 3175 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
3176 *is_alt = FALSE;
e0001a05 3177 }
43cd72b9
BW		 3178 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
3179 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
e0001a05 3180 {
43cd72b9
BW		 3181 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
3182 *is_alt = TRUE;
e0001a05 3183 }
43cd72b9
BW		 3184 else
3185 return -1;
3186
3187 return 0;
e0001a05
NC		 3188}
3189
3190
43cd72b9
BW		 3191/* Convert from slot number to BFD relocation type code for the
3192 standard PC-relative relocations. Return BFD_RELOC_NONE on
3193 failure. */
e0001a05 3194
43cd72b9
BW		 3195static bfd_reloc_code_real_type
3196encode_reloc (slot)
3197 int slot;
e0001a05 3198{
43cd72b9
BW		 3199 if (slot < 0 || slot > 14)
3200 return BFD_RELOC_NONE;
3201
3202 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
e0001a05
NC		 3203}
3204
3205
43cd72b9
BW		 3206/* Convert from slot numbers to BFD relocation type code for the
3207 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
e0001a05 3208
43cd72b9
BW		 3209static bfd_reloc_code_real_type
3210encode_alt_reloc (slot)
3211 int slot;
e0001a05 3212{
43cd72b9
BW		 3213 if (slot < 0 || slot > 14)
3214 return BFD_RELOC_NONE;
3215
3216 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
e0001a05
NC		 3217}
3218
3219
3220static void
43cd72b9
BW		 3221xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, operand, value,
3222 file, line)
3223 xtensa_insnbuf slotbuf;
3224 xtensa_format fmt;
3225 int slot;
e0001a05 3226 xtensa_opcode opcode;
43cd72b9
BW		 3227 int operand;
3228 uint32 value;
e0001a05
NC		 3229 const char *file;
3230 unsigned int line;
3231{
e0001a05
NC		 3232 uint32 valbuf = value;
3233
43cd72b9 3234 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
e0001a05 3235 {
43cd72b9
BW		 3236 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
3237 == 1)
3238 as_bad_where ((char *) file, line,
3239 _("operand %u is out of range for '%s'"), value,
3240 xtensa_opcode_name (xtensa_default_isa, opcode));
3241 else
3242 as_bad_where ((char *) file, line,
3243 _("operand %u is invalid for '%s'"), value,
3244 xtensa_opcode_name (xtensa_default_isa, opcode));
3245 return;
e0001a05
NC		 3246 }
3247
43cd72b9
BW		 3248 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
3249 slotbuf, valbuf);
e0001a05
NC		 3250}
3251
3252
3253static uint32
43cd72b9
BW		 3254xtensa_insnbuf_get_operand (slotbuf, fmt, slot, opcode, opnum)
3255 xtensa_insnbuf slotbuf;
3256 xtensa_format fmt;
3257 int slot;
e0001a05
NC		 3258 xtensa_opcode opcode;
3259 int opnum;
3260{
43cd72b9
BW		 3261 uint32 val = 0;
3262 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
3263 fmt, slot, slotbuf, &val);
3264 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
3265 return val;
e0001a05
NC		 3266}
3267
e0001a05
NC		 3268\f
3269/* Various Other Internal Functions. */
3270
3271static bfd_boolean
3272is_unique_insn_expansion (r)
3273 TransitionRule *r;
3274{
3275 if (!r->to_instr || r->to_instr->next != NULL)
3276 return FALSE;
3277 if (r->to_instr->typ != INSTR_INSTR)
3278 return FALSE;
3279 return TRUE;
3280}
3281
3282
e0001a05
NC		 3283static int
3284xg_get_build_instr_size (insn)
3285 BuildInstr *insn;
3286{
3287 assert (insn->typ == INSTR_INSTR);
43cd72b9 3288 return xg_get_single_size (insn->opcode);
e0001a05
NC		 3289}
3290
3291
3292bfd_boolean
3293xg_is_narrow_insn (insn)
3294 TInsn *insn;
3295{
43cd72b9 3296 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3297 TransitionList *l;
3298 int num_match = 0;
3299 assert (insn->insn_type == ITYPE_INSN);
3300 assert (insn->opcode < table->num_opcodes);
3301
3302 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3303 {
3304 TransitionRule *rule = l->rule;
3305
3306 if (xg_instruction_matches_rule (insn, rule)
3307 && is_unique_insn_expansion (rule))
3308 {
3309 /* It only generates one instruction... */
3310 assert (insn->insn_type == ITYPE_INSN);
3311 /* ...and it is a larger instruction. */
43cd72b9 3312 if (xg_get_single_size (insn->opcode)
e0001a05
NC		 3313 < xg_get_build_instr_size (rule->to_instr))
3314 {
3315 num_match++;
3316 if (num_match > 1)
3317 return FALSE;
3318 }
3319 }
3320 }
3321 return (num_match == 1);
3322}
3323
3324
3325bfd_boolean
3326xg_is_single_relaxable_insn (insn)
3327 TInsn *insn;
3328{
43cd72b9 3329 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3330 TransitionList *l;
3331 int num_match = 0;
3332 assert (insn->insn_type == ITYPE_INSN);
3333 assert (insn->opcode < table->num_opcodes);
3334
3335 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3336 {
3337 TransitionRule *rule = l->rule;
3338
3339 if (xg_instruction_matches_rule (insn, rule)
3340 && is_unique_insn_expansion (rule))
3341 {
43cd72b9 3342 /* It only generates one instruction... */
e0001a05
NC		 3343 assert (insn->insn_type == ITYPE_INSN);
3344 /* ... and it is a larger instruction. */
43cd72b9 3345 if (xg_get_single_size (insn->opcode)
e0001a05
NC		 3346 <= xg_get_build_instr_size (rule->to_instr))
3347 {
3348 num_match++;
3349 if (num_match > 1)
3350 return FALSE;
3351 }
3352 }
3353 }
3354 return (num_match == 1);
3355}
3356
3357
e0001a05
NC		 3358/* Return the maximum number of bytes this opcode can expand to. */
3359
3360int
3361xg_get_max_insn_widen_size (opcode)
3362 xtensa_opcode opcode;
3363{
43cd72b9 3364 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05 3365 TransitionList *l;
43cd72b9 3366 int max_size = xg_get_single_size (opcode);
e0001a05
NC		 3367
3368 assert (opcode < table->num_opcodes);
3369
3370 for (l = table->table[opcode]; l != NULL; l = l->next)
3371 {
3372 TransitionRule *rule = l->rule;
3373 BuildInstr *build_list;
3374 int this_size = 0;
3375
3376 if (!rule)
3377 continue;
3378 build_list = rule->to_instr;
3379 if (is_unique_insn_expansion (rule))
3380 {
3381 assert (build_list->typ == INSTR_INSTR);
3382 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3383 }
3384 else
3385 for (; build_list != NULL; build_list = build_list->next)
3386 {
3387 switch (build_list->typ)
3388 {
3389 case INSTR_INSTR:
43cd72b9 3390 this_size += xg_get_single_size (build_list->opcode);
e0001a05
NC		 3391 break;
3392 case INSTR_LITERAL_DEF:
3393 case INSTR_LABEL_DEF:
3394 default:
3395 break;
3396 }
3397 }
3398 if (this_size > max_size)
3399 max_size = this_size;
3400 }
3401 return max_size;
3402}
3403
3404
3405/* Return the maximum number of literal bytes this opcode can generate. */
3406
3407int
3408xg_get_max_insn_widen_literal_size (opcode)
3409 xtensa_opcode opcode;
3410{
43cd72b9 3411 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3412 TransitionList *l;
3413 int max_size = 0;
3414
3415 assert (opcode < table->num_opcodes);
3416
3417 for (l = table->table[opcode]; l != NULL; l = l->next)
3418 {
3419 TransitionRule *rule = l->rule;
3420 BuildInstr *build_list;
3421 int this_size = 0;
3422
3423 if (!rule)
3424 continue;
3425 build_list = rule->to_instr;
3426 if (is_unique_insn_expansion (rule))
3427 {
3428 assert (build_list->typ == INSTR_INSTR);
3429 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3430 }
3431 else
3432 for (; build_list != NULL; build_list = build_list->next)
3433 {
3434 switch (build_list->typ)
3435 {
3436 case INSTR_LITERAL_DEF:
43cd72b9 3437 /* Hard-coded 4-byte literal. */
e0001a05
NC		 3438 this_size += 4;
3439 break;
3440 case INSTR_INSTR:
3441 case INSTR_LABEL_DEF:
3442 default:
3443 break;
3444 }
3445 }
3446 if (this_size > max_size)
3447 max_size = this_size;
3448 }
3449 return max_size;
3450}
3451
3452
3453bfd_boolean
3454xg_is_relaxable_insn (insn, lateral_steps)
3455 TInsn *insn;
3456 int lateral_steps;
3457{
3458 int steps_taken = 0;
43cd72b9 3459 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3460 TransitionList *l;
3461
3462 assert (insn->insn_type == ITYPE_INSN);
3463 assert (insn->opcode < table->num_opcodes);
3464
3465 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3466 {
3467 TransitionRule *rule = l->rule;
3468
3469 if (xg_instruction_matches_rule (insn, rule))
3470 {
3471 if (steps_taken == lateral_steps)
3472 return TRUE;
3473 steps_taken++;
3474 }
3475 }
3476 return FALSE;
3477}
3478
3479
3480static symbolS *
3481get_special_literal_symbol ()
3482{
3483 static symbolS *sym = NULL;
3484
3485 if (sym == NULL)
3486 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3487 return sym;
3488}
3489
3490
3491static symbolS *
3492get_special_label_symbol ()
3493{
3494 static symbolS *sym = NULL;
3495
3496 if (sym == NULL)
3497 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3498 return sym;
3499}
3500
3501
43cd72b9 3502/* Return TRUE on success. */
e0001a05
NC		 3503
3504bfd_boolean
3505xg_build_to_insn (targ, insn, bi)
3506 TInsn *targ;
3507 TInsn *insn;
3508 BuildInstr *bi;
3509{
3510 BuildOp *op;
3511 symbolS *sym;
3512
3513 memset (targ, 0, sizeof (TInsn));
43cd72b9 3514 targ->loc = insn->loc;
e0001a05
NC		 3515 switch (bi->typ)
3516 {
3517 case INSTR_INSTR:
3518 op = bi->ops;
3519 targ->opcode = bi->opcode;
3520 targ->insn_type = ITYPE_INSN;
3521 targ->is_specific_opcode = FALSE;
3522
3523 for (; op != NULL; op = op->next)
3524 {
3525 int op_num = op->op_num;
3526 int op_data = op->op_data;
3527
3528 assert (op->op_num < MAX_INSN_ARGS);
3529
3530 if (targ->ntok <= op_num)
3531 targ->ntok = op_num + 1;
3532
3533 switch (op->typ)
3534 {
3535 case OP_CONSTANT:
3536 set_expr_const (&targ->tok[op_num], op_data);
3537 break;
3538 case OP_OPERAND:
3539 assert (op_data < insn->ntok);
3540 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3541 break;
3542 case OP_LITERAL:
3543 sym = get_special_literal_symbol ();
3544 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3545 break;
3546 case OP_LABEL:
3547 sym = get_special_label_symbol ();
3548 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3549 break;
43cd72b9
BW		 3550 case OP_OPERAND_HI16U:
3551 case OP_OPERAND_LOW16U:
3552 assert (op_data < insn->ntok);
3553 if (expr_is_const (&insn->tok[op_data]))
3554 {
3555 long val;
3556 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3557 val = xg_apply_userdef_op_fn (op->typ,
3558 targ->tok[op_num].
3559 X_add_number);
3560 targ->tok[op_num].X_add_number = val;
3561 }
3562 else
3563 {
3564 /* For const16 we can create relocations for these. */
3565 if (targ->opcode == XTENSA_UNDEFINED
3566 || (targ->opcode != xtensa_const16_opcode))
3567 return FALSE;
3568 assert (op_data < insn->ntok);
3569 /* Need to build a O_lo16 or O_hi16. */
3570 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3571 if (targ->tok[op_num].X_op == O_symbol)
3572 {
3573 if (op->typ == OP_OPERAND_HI16U)
3574 targ->tok[op_num].X_op = O_hi16;
3575 else if (op->typ == OP_OPERAND_LOW16U)
3576 targ->tok[op_num].X_op = O_lo16;
3577 else
3578 return FALSE;
3579 }
3580 }
3581 break;
e0001a05
NC		 3582 default:
3583 /* currently handles:
3584 OP_OPERAND_LOW8
3585 OP_OPERAND_HI24S
3586 OP_OPERAND_F32MINUS */
3587 if (xg_has_userdef_op_fn (op->typ))
3588 {
3589 assert (op_data < insn->ntok);
3590 if (expr_is_const (&insn->tok[op_data]))
3591 {
3592 long val;
3593 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3594 val = xg_apply_userdef_op_fn (op->typ,
3595 targ->tok[op_num].
3596 X_add_number);
3597 targ->tok[op_num].X_add_number = val;
3598 }
3599 else
3600 return FALSE; /* We cannot use a relocation for this. */
3601 break;
3602 }
3603 assert (0);
3604 break;
3605 }
3606 }
3607 break;
3608
3609 case INSTR_LITERAL_DEF:
3610 op = bi->ops;
3611 targ->opcode = XTENSA_UNDEFINED;
3612 targ->insn_type = ITYPE_LITERAL;
3613 targ->is_specific_opcode = FALSE;
3614 for (; op != NULL; op = op->next)
3615 {
3616 int op_num = op->op_num;
3617 int op_data = op->op_data;
3618 assert (op->op_num < MAX_INSN_ARGS);
3619
3620 if (targ->ntok <= op_num)
3621 targ->ntok = op_num + 1;
3622
3623 switch (op->typ)
3624 {
3625 case OP_OPERAND:
3626 assert (op_data < insn->ntok);
43cd72b9
BW		 3627 /* We can only pass resolvable literals through. */
3628 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3629 return FALSE;
e0001a05
NC		 3630 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3631 break;
3632 case OP_LITERAL:
3633 case OP_CONSTANT:
3634 case OP_LABEL:
3635 default:
3636 assert (0);
3637 break;
3638 }
3639 }
3640 break;
3641
3642 case INSTR_LABEL_DEF:
3643 op = bi->ops;
3644 targ->opcode = XTENSA_UNDEFINED;
3645 targ->insn_type = ITYPE_LABEL;
3646 targ->is_specific_opcode = FALSE;
43cd72b9 3647 /* Literal with no ops is a label? */
e0001a05
NC		 3648 assert (op == NULL);
3649 break;
3650
3651 default:
3652 assert (0);
3653 }
3654
3655 return TRUE;
3656}
3657
3658
43cd72b9 3659/* Return TRUE on success. */
e0001a05
NC		 3660
3661bfd_boolean
3662xg_build_to_stack (istack, insn, bi)
3663 IStack *istack;
3664 TInsn *insn;
3665 BuildInstr *bi;
3666{
3667 for (; bi != NULL; bi = bi->next)
3668 {
3669 TInsn *next_insn = istack_push_space (istack);
3670
3671 if (!xg_build_to_insn (next_insn, insn, bi))
3672 return FALSE;
3673 }
3674 return TRUE;
3675}
3676
3677
43cd72b9 3678/* Return TRUE on valid expansion. */
e0001a05
NC		 3679
3680bfd_boolean
3681xg_expand_to_stack (istack, insn, lateral_steps)
3682 IStack *istack;
3683 TInsn *insn;
3684 int lateral_steps;
3685{
3686 int stack_size = istack->ninsn;
3687 int steps_taken = 0;
43cd72b9 3688 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3689 TransitionList *l;
3690
3691 assert (insn->insn_type == ITYPE_INSN);
3692 assert (insn->opcode < table->num_opcodes);
3693
3694 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3695 {
3696 TransitionRule *rule = l->rule;
3697
3698 if (xg_instruction_matches_rule (insn, rule))
3699 {
3700 if (lateral_steps == steps_taken)
3701 {
3702 int i;
3703
3704 /* This is it. Expand the rule to the stack. */
3705 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3706 return FALSE;
3707
3708 /* Check to see if it fits. */
3709 for (i = stack_size; i < istack->ninsn; i++)
3710 {
3711 TInsn *insn = &istack->insn[i];
3712
3713 if (insn->insn_type == ITYPE_INSN
3714 && !tinsn_has_symbolic_operands (insn)
3715 && !xg_immeds_fit (insn))
3716 {
3717 istack->ninsn = stack_size;
3718 return FALSE;
3719 }
3720 }
3721 return TRUE;
3722 }
3723 steps_taken++;
3724 }
3725 }
3726 return FALSE;
3727}
3728
3729
3730bfd_boolean
3731xg_expand_narrow (targ, insn)
3732 TInsn *targ;
3733 TInsn *insn;
3734{
43cd72b9 3735 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3736 TransitionList *l;
3737
3738 assert (insn->insn_type == ITYPE_INSN);
3739 assert (insn->opcode < table->num_opcodes);
3740
3741 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3742 {
3743 TransitionRule *rule = l->rule;
3744 if (xg_instruction_matches_rule (insn, rule)
3745 && is_unique_insn_expansion (rule))
3746 {
3747 /* Is it a larger instruction? */
43cd72b9 3748 if (xg_get_single_size (insn->opcode)
e0001a05
NC		 3749 <= xg_get_build_instr_size (rule->to_instr))
3750 {
3751 xg_build_to_insn (targ, insn, rule->to_instr);
3752 return FALSE;
3753 }
3754 }
3755 }
3756 return TRUE;
3757}
3758
3759
3760/* Assumes: All immeds are constants. Check that all constants fit
43cd72b9 3761 into their immeds; return FALSE if not. */
e0001a05
NC		 3762
3763static bfd_boolean
3764xg_immeds_fit (insn)
3765 const TInsn *insn;
3766{
43cd72b9 3767 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 3768 int i;
3769
3770 int n = insn->ntok;
3771 assert (insn->insn_type == ITYPE_INSN);
3772 for (i = 0; i < n; ++i)
3773 {
3774 const expressionS *expr = &insn->tok[i];
43cd72b9 3775 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
e0001a05
NC		 3776 continue;
3777
3778 switch (expr->X_op)
3779 {
3780 case O_register:
3781 case O_constant:
43cd72b9
BW		 3782 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3783 return FALSE;
e0001a05 3784 break;
43cd72b9 3785
e0001a05
NC		 3786 default:
3787 /* The symbol should have a fixup associated with it. */
3788 assert (FALSE);
3789 break;
3790 }
3791 }
3792 return TRUE;
3793}
3794
3795
3796/* This should only be called after we have an initial
3797 estimate of the addresses. */
3798
3799static bfd_boolean
3800xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3801 const TInsn *insn;
3802 segT pc_seg;
3803 fragS *pc_frag;
3804 offsetT pc_offset;
3805 long stretch;
3806{
43cd72b9 3807 xtensa_isa isa = xtensa_default_isa;
e0001a05 3808 symbolS *symbolP;
43cd72b9
BW		 3809 fragS *sym_frag;
3810 offsetT target, pc;
3811 uint32 new_offset;
e0001a05
NC		 3812 int i;
3813 int n = insn->ntok;
3814
3815 assert (insn->insn_type == ITYPE_INSN);
3816
3817 for (i = 0; i < n; ++i)
3818 {
3819 const expressionS *expr = &insn->tok[i];
43cd72b9 3820 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
e0001a05
NC		 3821 continue;
3822
3823 switch (expr->X_op)
3824 {
3825 case O_register:
3826 case O_constant:
43cd72b9
BW		 3827 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3828 return FALSE;
3829 break;
3830
3831 case O_lo16:
3832 case O_hi16:
3833 /* Check for the worst case. */
3834 if (xg_check_operand (0xffff, insn->opcode, i))
e0001a05
NC		 3835 return FALSE;
3836 break;
3837
3838 case O_symbol:
3839 /* We only allow symbols for pc-relative stuff.
3840 If pc_frag == 0, then we don't have frag locations yet. */
3841 if (pc_frag == 0)
3842 return FALSE;
3843
43cd72b9
BW		 3844 /* If it is PC-relative and the symbol is not in the same
3845 segment as the PC.... */
3846 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0
e0001a05
NC		 3847 || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3848 return FALSE;
3849
43cd72b9
BW		 3850 /* If it is a weak symbol, then assume it won't reach. This will
3851 only affect calls when longcalls are enabled, because if
3852 longcalls are disabled, then the call is marked as a specific
3853 opcode. */
3854 if (S_IS_WEAK (expr->X_add_symbol))
3855 return FALSE;
3856
e0001a05 3857 symbolP = expr->X_add_symbol;
43cd72b9 3858 sym_frag = symbol_get_frag (symbolP);
e0001a05
NC		 3859 target = S_GET_VALUE (symbolP) + expr->X_add_number;
3860 pc = pc_frag->fr_address + pc_offset;
3861
3862 /* If frag has yet to be reached on this pass, assume it
3863 will move by STRETCH just as we did. If this is not so,
3864 it will be because some frag between grows, and that will
3865 force another pass. Beware zero-length frags. There
3866 should be a faster way to do this. */
3867
43cd72b9
BW		 3868 if (stretch != 0
3869 && sym_frag->relax_marker != pc_frag->relax_marker
3870 && S_GET_SEGMENT (symbolP) == pc_seg)
3871 {
3872 target += stretch;
3873 }
3874
3875 new_offset = target;
3876 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3877 if (xg_check_operand (new_offset, insn->opcode, i))
e0001a05
NC		 3878 return FALSE;
3879 break;
3880
3881 default:
3882 /* The symbol should have a fixup associated with it. */
3883 return FALSE;
3884 }
3885 }
3886
3887 return TRUE;
3888}
3889
3890
3891/* This will check to see if the value can be converted into the
43cd72b9 3892 operand type. It will return TRUE if it does not fit. */
e0001a05
NC		 3893
3894static bfd_boolean
43cd72b9 3895xg_check_operand (value, opcode, operand)
e0001a05 3896 int32 value;
43cd72b9
BW		 3897 xtensa_opcode opcode;
3898 int operand;
e0001a05
NC		 3899{
3900 uint32 valbuf = value;
43cd72b9
BW		 3901 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3902 return TRUE;
3903 return FALSE;
e0001a05
NC		 3904}
3905
43cd72b9 3906\f
e0001a05 3907
43cd72b9
BW		 3908/* Relax the assembly instruction at least "min_steps".
3909 Return the number of steps taken. */
e0001a05
NC		 3910
3911int
3912xg_assembly_relax (istack, insn, pc_seg, pc_frag, pc_offset, min_steps,
3913 stretch)
3914 IStack *istack;
3915 TInsn *insn;
3916 segT pc_seg;
43cd72b9
BW		 3917 fragS *pc_frag; /* if pc_frag == 0, then no pc-relative */
3918 offsetT pc_offset; /* offset in fragment */
3919 int min_steps; /* minimum number of conversion steps */
3920 long stretch; /* number of bytes stretched so far */
e0001a05
NC		 3921{
3922 int steps_taken = 0;
3923
3924 /* assert (has no symbolic operands)
3925 Some of its immeds don't fit.
3926 Try to build a relaxed version.
3927 This may go through a couple of stages
3928 of single instruction transformations before
3929 we get there. */
3930
3931 TInsn single_target;
3932 TInsn current_insn;
3933 int lateral_steps = 0;
3934 int istack_size = istack->ninsn;
3935
3936 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3937 && steps_taken >= min_steps)
3938 {
3939 istack_push (istack, insn);
3940 return steps_taken;
3941 }
43cd72b9 3942 current_insn = *insn;
e0001a05
NC		 3943
3944 /* Walk through all of the single instruction expansions. */
3945 while (xg_is_single_relaxable_insn (&current_insn))
3946 {
3947 int error_val = xg_expand_narrow (&single_target, &current_insn);
3948
3949 assert (!error_val);
3950
3951 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3952 stretch))
3953 {
3954 steps_taken++;
3955 if (steps_taken >= min_steps)
3956 {
3957 istack_push (istack, &single_target);
3958 return steps_taken;
3959 }
3960 }
43cd72b9 3961 current_insn = single_target;
e0001a05
NC		 3962 }
3963
3964 /* Now check for a multi-instruction expansion. */
3965 while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3966 {
3967 if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3968 stretch))
3969 {
3970 if (steps_taken >= min_steps)
3971 {
3972 istack_push (istack, &current_insn);
3973 return steps_taken;
3974 }
3975 }
3976 steps_taken++;
3977 if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3978 {
3979 if (steps_taken >= min_steps)
3980 return steps_taken;
3981 }
3982 lateral_steps++;
3983 istack->ninsn = istack_size;
3984 }
3985
3986 /* It's not going to work -- use the original. */
3987 istack_push (istack, insn);
3988 return steps_taken;
3989}
3990
3991
3992static void
3993xg_force_frag_space (size)
3994 int size;
3995{
3996 /* This may have the side effect of creating a new fragment for the
3997 space to go into. I just do not like the name of the "frag"
3998 functions. */
3999 frag_grow (size);
4000}
4001
4002
4003void
43cd72b9 4004xg_finish_frag (last_insn, frag_state, slot0_state, max_growth, is_insn)
e0001a05 4005 char *last_insn;
43cd72b9
BW		 4006 enum xtensa_relax_statesE frag_state;
4007 enum xtensa_relax_statesE slot0_state;
e0001a05
NC		 4008 int max_growth;
4009 bfd_boolean is_insn;
4010{
4011 /* Finish off this fragment so that it has at LEAST the desired
4012 max_growth. If it doesn't fit in this fragment, close this one
4013 and start a new one. In either case, return a pointer to the
4014 beginning of the growth area. */
4015
4016 fragS *old_frag;
43cd72b9 4017
e0001a05
NC		 4018 xg_force_frag_space (max_growth);
4019
4020 old_frag = frag_now;
4021
4022 frag_now->fr_opcode = last_insn;
4023 if (is_insn)
4024 frag_now->tc_frag_data.is_insn = TRUE;
4025
4026 frag_var (rs_machine_dependent, max_growth, max_growth,
43cd72b9
BW		 4027 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
4028
4029 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
4030 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4031
4032 /* Just to make sure that we did not split it up. */
4033 assert (old_frag->fr_next == frag_now);
4034}
4035
4036
4037static bfd_boolean
4038is_branch_jmp_to_next (insn, fragP)
4039 TInsn *insn;
4040 fragS *fragP;
4041{
4042 xtensa_isa isa = xtensa_default_isa;
4043 int i;
43cd72b9 4044 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 4045 int target_op = -1;
4046 symbolS *sym;
4047 fragS *target_frag;
4048
43cd72b9
BW		 4049 if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
4050 && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
e0001a05
NC		 4051 return FALSE;
4052
4053 for (i = 0; i < num_ops; i++)
4054 {
43cd72b9 4055 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
e0001a05
NC		 4056 {
4057 target_op = i;
4058 break;
4059 }
4060 }
4061 if (target_op == -1)
4062 return FALSE;
4063
4064 if (insn->ntok <= target_op)
4065 return FALSE;
4066
4067 if (insn->tok[target_op].X_op != O_symbol)
4068 return FALSE;
4069
4070 sym = insn->tok[target_op].X_add_symbol;
4071 if (sym == NULL)
4072 return FALSE;
4073
4074 if (insn->tok[target_op].X_add_number != 0)
4075 return FALSE;
4076
4077 target_frag = symbol_get_frag (sym);
4078 if (target_frag == NULL)
4079 return FALSE;
4080
4081 if (is_next_frag_target (fragP->fr_next, target_frag)
4082 && S_GET_VALUE (sym) == target_frag->fr_address)
4083 return TRUE;
4084
4085 return FALSE;
4086}
4087
4088
4089static void
4090xg_add_branch_and_loop_targets (insn)
4091 TInsn *insn;
4092{
4093 xtensa_isa isa = xtensa_default_isa;
43cd72b9 4094 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05 4095
43cd72b9 4096 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
e0001a05
NC		 4097 {
4098 int i = 1;
43cd72b9
BW		 4099 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
4100 && insn->tok[i].X_op == O_symbol)
4101 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
e0001a05
NC		 4102 return;
4103 }
4104
43cd72b9
BW		 4105 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
4106 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
e0001a05
NC		 4107 {
4108 int i;
4109
4110 for (i = 0; i < insn->ntok && i < num_ops; i++)
4111 {
43cd72b9 4112 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
e0001a05 4113 && insn->tok[i].X_op == O_symbol)
82e7541d
BW		 4114 {
4115 symbolS *sym = insn->tok[i].X_add_symbol;
4116 symbol_get_tc (sym)->is_branch_target = TRUE;
4117 if (S_IS_DEFINED (sym))
4118 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
4119 }
e0001a05
NC		 4120 }
4121 }
4122}
4123
4124
43cd72b9
BW		 4125/* The routine xg_instruction_matches_option_term must return TRUE
4126 when a given option term is true. The meaning of all of the option
4127 terms is given interpretation by this function. This is needed when
4128 an option depends on the state of a directive, but there are no such
4129 options in use right now. */
4130
4131bfd_boolean
4132xg_instruction_matches_option_term (insn, option)
4133 TInsn *insn ATTRIBUTE_UNUSED;
4134 const ReqOrOption *option;
4135{
4136 if (strcmp (option->option_name, "realnop") == 0
4137 || strncmp (option->option_name, "IsaUse", 6) == 0)
4138 {
4139 /* These conditions were evaluated statically when building the
4140 relaxation table. There's no need to reevaluate them now. */
4141 return TRUE;
4142 }
4143 else
4144 {
4145 as_fatal (_("internal error: unknown option name '%s'"),
4146 option->option_name);
4147 }
4148}
4149
4150
4151bfd_boolean
4152xg_instruction_matches_or_options (insn, or_option)
4153 TInsn *insn;
4154 const ReqOrOptionList *or_option;
4155{
4156 const ReqOrOption *option;
4157 /* Must match each of the AND terms. */
4158 for (option = or_option; option != NULL; option = option->next)
4159 {
4160 if (xg_instruction_matches_option_term (insn, option))
4161 return TRUE;
4162 }
4163 return FALSE;
4164}
4165
4166
4167bfd_boolean
4168xg_instruction_matches_options (insn, options)
4169 TInsn *insn;
4170 const ReqOptionList *options;
4171{
4172 const ReqOption *req_options;
4173 /* Must match each of the AND terms. */
4174 for (req_options = options;
4175 req_options != NULL;
4176 req_options = req_options->next)
4177 {
4178 /* Must match one of the OR clauses. */
4179 if (!xg_instruction_matches_or_options (insn,
4180 req_options->or_option_terms))
4181 return FALSE;
4182 }
4183 return TRUE;
4184}
4185
4186
e0001a05
NC		 4187/* Return the transition rule that matches or NULL if none matches. */
4188
4189bfd_boolean
4190xg_instruction_matches_rule (insn, rule)
4191 TInsn *insn;
4192 TransitionRule *rule;
4193{
4194 PreconditionList *condition_l;
4195
4196 if (rule->opcode != insn->opcode)
4197 return FALSE;
4198
4199 for (condition_l = rule->conditions;
4200 condition_l != NULL;
4201 condition_l = condition_l->next)
4202 {
4203 expressionS *exp1;
4204 expressionS *exp2;
4205 Precondition *cond = condition_l->precond;
4206
4207 switch (cond->typ)
4208 {
4209 case OP_CONSTANT:
4210 /* The expression must be the constant. */
4211 assert (cond->op_num < insn->ntok);
4212 exp1 = &insn->tok[cond->op_num];
43cd72b9 4213 if (expr_is_const (exp1))
e0001a05 4214 {
43cd72b9
BW		 4215 switch (cond->cmp)
4216 {
4217 case OP_EQUAL:
4218 if (get_expr_const (exp1) != cond->op_data)
4219 return FALSE;
4220 break;
4221 case OP_NOTEQUAL:
4222 if (get_expr_const (exp1) == cond->op_data)
4223 return FALSE;
4224 break;
4225 default:
4226 return FALSE;
4227 }
4228 }
4229 else if (expr_is_register (exp1))
4230 {
4231 switch (cond->cmp)
4232 {
4233 case OP_EQUAL:
4234 if (get_expr_register (exp1) != cond->op_data)
4235 return FALSE;
4236 break;
4237 case OP_NOTEQUAL:
4238 if (get_expr_register (exp1) == cond->op_data)
4239 return FALSE;
4240 break;
4241 default:
4242 return FALSE;
4243 }
e0001a05 4244 }
43cd72b9
BW		 4245 else
4246 return FALSE;
e0001a05
NC		 4247 break;
4248
4249 case OP_OPERAND:
4250 assert (cond->op_num < insn->ntok);
4251 assert (cond->op_data < insn->ntok);
4252 exp1 = &insn->tok[cond->op_num];
4253 exp2 = &insn->tok[cond->op_data];
4254
4255 switch (cond->cmp)
4256 {
4257 case OP_EQUAL:
4258 if (!expr_is_equal (exp1, exp2))
4259 return FALSE;
4260 break;
4261 case OP_NOTEQUAL:
4262 if (expr_is_equal (exp1, exp2))
4263 return FALSE;
4264 break;
4265 }
4266 break;
4267
4268 case OP_LITERAL:
4269 case OP_LABEL:
4270 default:
4271 return FALSE;
4272 }
4273 }
43cd72b9
BW		 4274 if (!xg_instruction_matches_options (insn, rule->options))
4275 return FALSE;
4276
e0001a05
NC		 4277 return TRUE;
4278}
4279
4280
43cd72b9
BW		 4281static int
4282transition_rule_cmp (a, b)
4283 const TransitionRule *a;
4284 const TransitionRule *b;
4285{
4286 bfd_boolean a_greater = FALSE;
4287 bfd_boolean b_greater = FALSE;
4288
4289 ReqOptionList *l_a = a->options;
4290 ReqOptionList *l_b = b->options;
4291
4292 /* We only care if they both are the same except for
4293 a const16 vs. an l32r. */
4294
4295 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
4296 {
4297 ReqOrOptionList *l_or_a = l_a->or_option_terms;
4298 ReqOrOptionList *l_or_b = l_b->or_option_terms;
4299 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
4300 {
4301 if (l_or_a->is_true != l_or_b->is_true)
4302 return 0;
4303 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
4304 {
4305 /* This is the case we care about. */
4306 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
4307 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
4308 {
4309 if (prefer_const16)
4310 a_greater = TRUE;
4311 else
4312 b_greater = TRUE;
4313 }
4314 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
4315 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
4316 {
4317 if (prefer_const16)
4318 b_greater = TRUE;
4319 else
4320 a_greater = TRUE;
4321 }
4322 else
4323 return 0;
4324 }
4325 l_or_a = l_or_a->next;
4326 l_or_b = l_or_b->next;
4327 }
4328 if (l_or_a || l_or_b)
4329 return 0;
4330
4331 l_a = l_a->next;
4332 l_b = l_b->next;
4333 }
4334 if (l_a || l_b)
4335 return 0;
4336
4337 /* Incomparable if the substitution was used differently in two cases. */
4338 if (a_greater && b_greater)
4339 return 0;
4340
4341 if (b_greater)
4342 return 1;
4343 if (a_greater)
4344 return -1;
4345
4346 return 0;
4347}
4348
4349
e0001a05
NC		 4350TransitionRule *
4351xg_instruction_match (insn)
4352 TInsn *insn;
4353{
43cd72b9 4354 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
e0001a05
NC		 4355 TransitionList *l;
4356 assert (insn->opcode < table->num_opcodes);
4357
4358 /* Walk through all of the possible transitions. */
4359 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
4360 {
4361 TransitionRule *rule = l->rule;
4362 if (xg_instruction_matches_rule (insn, rule))
4363 return rule;
4364 }
4365 return NULL;
4366}
4367
4368
43cd72b9 4369/* Return FALSE if no error. */
e0001a05
NC		 4370
4371bfd_boolean
4372xg_build_token_insn (instr_spec, old_insn, new_insn)
4373 BuildInstr *instr_spec;
4374 TInsn *old_insn;
4375 TInsn *new_insn;
4376{
4377 int num_ops = 0;
4378 BuildOp *b_op;
4379
4380 switch (instr_spec->typ)
4381 {
4382 case INSTR_INSTR:
4383 new_insn->insn_type = ITYPE_INSN;
4384 new_insn->opcode = instr_spec->opcode;
4385 new_insn->is_specific_opcode = FALSE;
43cd72b9 4386 new_insn->loc = old_insn->loc;
e0001a05
NC		 4387 break;
4388 case INSTR_LITERAL_DEF:
4389 new_insn->insn_type = ITYPE_LITERAL;
4390 new_insn->opcode = XTENSA_UNDEFINED;
4391 new_insn->is_specific_opcode = FALSE;
43cd72b9 4392 new_insn->loc = old_insn->loc;
e0001a05
NC		 4393 break;
4394 case INSTR_LABEL_DEF:
4395 as_bad (_("INSTR_LABEL_DEF not supported yet"));
4396 break;
4397 }
4398
4399 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
4400 {
4401 expressionS *exp;
4402 const expressionS *src_exp;
4403
4404 num_ops++;
4405 switch (b_op->typ)
4406 {
4407 case OP_CONSTANT:
4408 /* The expression must be the constant. */
4409 assert (b_op->op_num < MAX_INSN_ARGS);
4410 exp = &new_insn->tok[b_op->op_num];
4411 set_expr_const (exp, b_op->op_data);
4412 break;
4413
4414 case OP_OPERAND:
4415 assert (b_op->op_num < MAX_INSN_ARGS);
4416 assert (b_op->op_data < (unsigned) old_insn->ntok);
4417 src_exp = &old_insn->tok[b_op->op_data];
4418 exp = &new_insn->tok[b_op->op_num];
4419 copy_expr (exp, src_exp);
4420 break;
4421
4422 case OP_LITERAL:
4423 case OP_LABEL:
4424 as_bad (_("can't handle generation of literal/labels yet"));
4425 assert (0);
4426
4427 default:
4428 as_bad (_("can't handle undefined OP TYPE"));
4429 assert (0);
4430 }
4431 }
4432
4433 new_insn->ntok = num_ops;
4434 return FALSE;
4435}
4436
4437
43cd72b9 4438/* Return TRUE if it was simplified. */
e0001a05
NC		 4439
4440bfd_boolean
4441xg_simplify_insn (old_insn, new_insn)
4442 TInsn *old_insn;
4443 TInsn *new_insn;
4444{
43cd72b9 4445 TransitionRule *rule;
e0001a05 4446 BuildInstr *insn_spec;
43cd72b9
BW		 4447
4448 if (old_insn->is_specific_opcode || !density_supported)
4449 return FALSE;
4450
4451 rule = xg_instruction_match (old_insn);
e0001a05
NC		 4452 if (rule == NULL)
4453 return FALSE;
4454
4455 insn_spec = rule->to_instr;
4456 /* There should only be one. */
4457 assert (insn_spec != NULL);
4458 assert (insn_spec->next == NULL);
4459 if (insn_spec->next != NULL)
4460 return FALSE;
4461
4462 xg_build_token_insn (insn_spec, old_insn, new_insn);
4463
4464 return TRUE;
4465}
4466
4467
4468/* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4469 l32i.n. (2) Check the number of operands. (3) Place the instruction
4470 tokens into the stack or if we can relax it at assembly time, place
43cd72b9 4471 multiple instructions/literals onto the stack. Return FALSE if no
e0001a05
NC		 4472 error. */
4473
4474static bfd_boolean
4475xg_expand_assembly_insn (istack, orig_insn)
4476 IStack *istack;
4477 TInsn *orig_insn;
4478{
4479 int noperands;
4480 TInsn new_insn;
4481 memset (&new_insn, 0, sizeof (TInsn));
4482
43cd72b9
BW		 4483 /* Narrow it if we can. xg_simplify_insn now does all the
4484 appropriate checking (e.g., for the density option). */
4485 if (xg_simplify_insn (orig_insn, &new_insn))
4486 orig_insn = &new_insn;
e0001a05 4487
43cd72b9
BW		 4488 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
4489 orig_insn->opcode);
e0001a05
NC		 4490 if (orig_insn->ntok < noperands)
4491 {
4492 as_bad (_("found %d operands for '%s': Expected %d"),
4493 orig_insn->ntok,
4494 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4495 noperands);
4496 return TRUE;
4497 }
4498 if (orig_insn->ntok > noperands)
4499 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
4500 orig_insn->ntok,
4501 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4502 noperands);
4503
43cd72b9 4504 /* If there are not enough operands, we will assert above. If there
e0001a05
NC		 4505 are too many, just cut out the extras here. */
4506
4507 orig_insn->ntok = noperands;
4508
43cd72b9 4509 /* Cases:
e0001a05
NC		 4510
4511 Instructions with all constant immeds:
4512 Assemble them and relax the instruction if possible.
4513 Give error if not possible; no fixup needed.
4514
4515 Instructions with symbolic immeds:
4516 Assemble them with a Fix up (that may cause instruction expansion).
43cd72b9
BW		 4517 Also close out the fragment if the fixup may cause instruction expansion.
4518
e0001a05
NC		 4519 There are some other special cases where we need alignment.
4520 1) before certain instructions with required alignment (OPCODE_ALIGN)
4521 2) before labels that have jumps (LABEL_ALIGN)
4522 3) after call instructions (RETURN_ALIGN)
43cd72b9
BW		 4523 Multiple of these may be possible on the same fragment.
4524 If so, make sure to satisfy the required alignment.
e0001a05
NC		 4525 Then try to get the desired alignment. */
4526
4527 if (tinsn_has_invalid_symbolic_operands (orig_insn))
4528 return TRUE;
4529
43cd72b9 4530 if (orig_insn->is_specific_opcode || !use_transform ())
e0001a05
NC		 4531 {
4532 istack_push (istack, orig_insn);
4533 return FALSE;
4534 }
4535
4536 if (tinsn_has_symbolic_operands (orig_insn))
4537 {
4538 if (tinsn_has_complex_operands (orig_insn))
4539 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4540 else
4541 istack_push (istack, orig_insn);
4542 }
4543 else
4544 {
4545 if (xg_immeds_fit (orig_insn))
4546 istack_push (istack, orig_insn);
4547 else
4548 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4549 }
4550
e0001a05
NC		 4551 return FALSE;
4552}
4553
4554
4555/* Currently all literals that are generated here are 32-bit L32R targets. */
4556
4557symbolS *
4558xg_assemble_literal (insn)
4559 /* const */ TInsn *insn;
4560{
4561 emit_state state;
4562 symbolS *lit_sym = NULL;
4563
4564 /* size = 4 for L32R. It could easily be larger when we move to
4565 larger constants. Add a parameter later. */
4566 offsetT litsize = 4;
4567 offsetT litalign = 2; /* 2^2 = 4 */
4568 expressionS saved_loc;
43cd72b9
BW		 4569 expressionS * emit_val;
4570
e0001a05
NC		 4571 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4572
4573 assert (insn->insn_type == ITYPE_LITERAL);
77cd6497 4574 assert (insn->ntok == 1); /* must be only one token here */
e0001a05
NC		 4575
4576 xtensa_switch_to_literal_fragment (&state);
4577
43cd72b9
BW		 4578 emit_val = &insn->tok[0];
4579 if (emit_val->X_op == O_big)
4580 {
4581 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4582 if (size > litsize)
4583 {
4584 /* This happens when someone writes a "movi a2, big_number". */
4585 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4586 _("invalid immediate"));
4587 xtensa_restore_emit_state (&state);
4588 return NULL;
4589 }
4590 }
4591
e0001a05
NC		 4592 /* Force a 4-byte align here. Note that this opens a new frag, so all
4593 literals done with this function have a frag to themselves. That's
4594 important for the way text section literals work. */
4595 frag_align (litalign, 0, 0);
43cd72b9 4596 record_alignment (now_seg, litalign);
e0001a05 4597
43cd72b9
BW		 4598 if (emit_val->X_op == O_pltrel)
4599 {
4600 char *p = frag_more (litsize);
4601 xtensa_set_frag_assembly_state (frag_now);
4602 if (emit_val->X_add_symbol)
4603 emit_val->X_op = O_symbol;
4604 else
4605 emit_val->X_op = O_constant;
4606 fix_new_exp (frag_now, p - frag_now->fr_literal,
4607 litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
4608 }
4609 else
4610 emit_expr (emit_val, litsize);
e0001a05
NC		 4611
4612 assert (frag_now->tc_frag_data.literal_frag == NULL);
4613 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4614 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4615 lit_sym = frag_now->fr_symbol;
4616 frag_now->tc_frag_data.is_literal = TRUE;
4617
4618 /* Go back. */
4619 xtensa_restore_emit_state (&state);
4620 return lit_sym;
4621}
4622
4623
43cd72b9
BW		 4624bfd_boolean
4625xg_valid_literal_expression (exp)
4626 const expressionS *exp;
4627{
4628 switch (exp->X_op)
4629 {
4630 case O_constant:
4631 case O_symbol:
4632 case O_big:
4633 case O_uminus:
4634 case O_subtract:
4635 case O_pltrel:
4636 return TRUE;
4637 default:
4638 return FALSE;
4639 }
4640}
4641
4642
e0001a05 4643static void
43cd72b9 4644xg_assemble_literal_space (size, slot)
e0001a05 4645 /* const */ int size;
43cd72b9 4646 int slot;
e0001a05
NC		 4647{
4648 emit_state state;
43cd72b9 4649 /* We might have to do something about this alignment. It only
e0001a05
NC		 4650 takes effect if something is placed here. */
4651 offsetT litalign = 2; /* 2^2 = 4 */
4652 fragS *lit_saved_frag;
4653
e0001a05 4654 assert (size % 4 == 0);
e0001a05
NC		 4655
4656 xtensa_switch_to_literal_fragment (&state);
4657
4658 /* Force a 4-byte align here. */
4659 frag_align (litalign, 0, 0);
43cd72b9 4660 record_alignment (now_seg, litalign);
e0001a05
NC		 4661
4662 xg_force_frag_space (size);
4663
4664 lit_saved_frag = frag_now;
4665 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4666 frag_now->tc_frag_data.is_literal = TRUE;
4667 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
43cd72b9 4668 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
e0001a05
NC		 4669
4670 /* Go back. */
4671 xtensa_restore_emit_state (&state);
43cd72b9 4672 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
e0001a05
NC		 4673}
4674
4675
4676symbolS *
4677xtensa_create_literal_symbol (sec, frag)
4678 segT sec;
4679 fragS *frag;
4680{
4681 static int lit_num = 0;
4682 static char name[256];
61846f28 4683 symbolS *symbolP;
e0001a05
NC		 4684
4685 sprintf (name, ".L_lit_sym%d", lit_num);
e0001a05 4686
61846f28
BW		 4687 /* Create a local symbol. If it is in a linkonce section, we have to
4688 be careful to make sure that if it is used in a relocation that the
4689 symbol will be in the output file. */
4690 if (get_is_linkonce_section (stdoutput, sec))
e0001a05 4691 {
61846f28 4692 symbolP = symbol_new (name, sec, 0, frag);
e0001a05
NC		 4693 S_CLEAR_EXTERNAL (symbolP);
4694 /* symbolP->local = 1; */
4695 }
4696 else
61846f28 4697 symbolP = symbol_new (name, sec, 0, frag);
e0001a05 4698
82e7541d
BW		 4699 xtensa_add_literal_sym (symbolP);
4700
61846f28
BW		 4701 frag->tc_frag_data.is_literal = TRUE;
4702 lit_num++;
e0001a05
NC		 4703 return symbolP;
4704}
4705
4706
82e7541d
BW		 4707static void
4708xtensa_add_literal_sym (sym)
4709 symbolS *sym;
4710{
4711 sym_list *l;
4712
4713 l = (sym_list *) xmalloc (sizeof (sym_list));
4714 l->sym = sym;
4715 l->next = literal_syms;
4716 literal_syms = l;
4717}
4718
4719
4720static void
4721xtensa_add_insn_label (sym)
4722 symbolS *sym;
4723{
4724 sym_list *l;
4725
4726 if (!free_insn_labels)
4727 l = (sym_list *) xmalloc (sizeof (sym_list));
4728 else
4729 {
4730 l = free_insn_labels;
4731 free_insn_labels = l->next;
4732 }
4733
4734 l->sym = sym;
4735 l->next = insn_labels;
4736 insn_labels = l;
4737}
4738
4739
4740static void
4741xtensa_clear_insn_labels (void)
4742{
4743 sym_list **pl;
4744
4745 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
4746 ;
4747 *pl = insn_labels;
4748 insn_labels = NULL;
4749}
4750
4751
43cd72b9 4752/* Return TRUE if the section flags are marked linkonce
e0001a05
NC		 4753 or the name is .gnu.linkonce*. */
4754
4755bfd_boolean
4756get_is_linkonce_section (abfd, sec)
4757 bfd *abfd ATTRIBUTE_UNUSED;
4758 segT sec;
4759{
4760 flagword flags, link_once_flags;
4761
4762 flags = bfd_get_section_flags (abfd, sec);
4763 link_once_flags = (flags & SEC_LINK_ONCE);
4764
4765 /* Flags might not be set yet. */
4766 if (!link_once_flags)
4767 {
4768 static size_t len = sizeof ".gnu.linkonce.t.";
4769
4770 if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
4771 link_once_flags = SEC_LINK_ONCE;
4772 }
4773 return (link_once_flags != 0);
4774}
4775
4776
e0001a05 4777static bfd_boolean
43cd72b9
BW		 4778xg_emit_insn_to_buf (tinsn, fmt, buf, fragP, offset, build_fix)
4779 TInsn *tinsn;
4780 xtensa_format fmt;
e0001a05
NC		 4781 char *buf;
4782 fragS *fragP;
4783 offsetT offset;
4784 bfd_boolean build_fix;
4785{
4786 static xtensa_insnbuf insnbuf = NULL;
4787 bfd_boolean has_symbolic_immed = FALSE;
4788 bfd_boolean ok = TRUE;
4789 if (!insnbuf)
4790 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4791
43cd72b9 4792 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
e0001a05
NC		 4793 if (has_symbolic_immed && build_fix)
4794 {
4795 /* Add a fixup. */
43cd72b9
BW		 4796 int opnum = get_relaxable_immed (tinsn->opcode);
4797 expressionS *exp = &tinsn->tok[opnum];
e0001a05 4798
43cd72b9 4799 if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset))
e0001a05
NC		 4800 ok = FALSE;
4801 }
4802 fragP->tc_frag_data.is_insn = TRUE;
43cd72b9 4803 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
e0001a05
NC		 4804 return ok;
4805}
4806
4807
4808/* Put in a fixup record based on the opcode.
43cd72b9 4809 Return TRUE on success. */
e0001a05
NC		 4810
4811bfd_boolean
43cd72b9
BW		 4812xg_add_opcode_fix (tinsn, opnum, fmt, slot, expr, fragP, offset)
4813 TInsn *tinsn;
e0001a05 4814 int opnum;
43cd72b9
BW		 4815 xtensa_format fmt;
4816 int slot;
e0001a05
NC		 4817 expressionS *expr;
4818 fragS *fragP;
4819 offsetT offset;
43cd72b9
BW		 4820{
4821 xtensa_opcode opcode = tinsn->opcode;
4822 bfd_reloc_code_real_type reloc;
4823 reloc_howto_type *howto;
4824 int fmt_length;
e0001a05
NC		 4825 fixS *the_fix;
4826
43cd72b9
BW		 4827 reloc = BFD_RELOC_NONE;
4828
4829 /* First try the special cases for "alternate" relocs. */
4830 if (opcode == xtensa_l32r_opcode)
4831 {
4832 if (fragP->tc_frag_data.use_absolute_literals)
4833 reloc = encode_alt_reloc (slot);
4834 }
4835 else if (opcode == xtensa_const16_opcode)
4836 {
4837 if (expr->X_op == O_lo16)
4838 {
4839 reloc = encode_reloc (slot);
4840 expr->X_op = O_symbol;
4841 }
4842 else if (expr->X_op == O_hi16)
4843 {
4844 reloc = encode_alt_reloc (slot);
4845 expr->X_op = O_symbol;
4846 }
4847 }
4848
4849 if (opnum != get_relaxable_immed (opcode))
e0001a05 4850 {
43cd72b9 4851 as_bad (_("invalid relocation for operand %i of '%s'"),
e0001a05
NC		 4852 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4853 return FALSE;
4854 }
4855
43cd72b9
BW		 4856 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4857 into the symbol table where the generic portions of the assembler
4858 won't know what to do with them. */
4859 if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4860 {
4861 as_bad (_("invalid expression for operand %i of '%s'"),
4862 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4863 return FALSE;
4864 }
4865
4866 /* Next try the generic relocs. */
4867 if (reloc == BFD_RELOC_NONE)
4868 reloc = encode_reloc (slot);
4869 if (reloc == BFD_RELOC_NONE)
4870 {
4871 as_bad (_("invalid relocation in instruction slot %i"), slot);
4872 return FALSE;
4873 }
e0001a05 4874
43cd72b9 4875 howto = bfd_reloc_type_lookup (stdoutput, reloc);
e0001a05
NC		 4876 if (!howto)
4877 {
43cd72b9 4878 as_bad (_("undefined symbol for opcode \"%s\""),
e0001a05
NC		 4879 xtensa_opcode_name (xtensa_default_isa, opcode));
4880 return FALSE;
4881 }
4882
43cd72b9
BW		 4883 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4884 the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
e0001a05
NC		 4885 howto->pc_relative, reloc);
4886
43cd72b9
BW		 4887 if (expr->X_add_symbol
4888 && (S_IS_EXTERNAL (expr->X_add_symbol)
4889 || S_IS_WEAK (expr->X_add_symbol)))
e0001a05 4890 the_fix->fx_plt = TRUE;
43cd72b9
BW		 4891
4892 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4893 the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4894 the_fix->tc_fix_data.slot = slot;
e0001a05
NC		 4895
4896 return TRUE;
4897}
4898
4899
4900void
4901xg_resolve_literals (insn, lit_sym)
4902 TInsn *insn;
4903 symbolS *lit_sym;
4904{
4905 symbolS *sym = get_special_literal_symbol ();
4906 int i;
4907 if (lit_sym == 0)
4908 return;
4909 assert (insn->insn_type == ITYPE_INSN);
4910 for (i = 0; i < insn->ntok; i++)
4911 if (insn->tok[i].X_add_symbol == sym)
4912 insn->tok[i].X_add_symbol = lit_sym;
4913
4914}
4915
4916
4917void
4918xg_resolve_labels (insn, label_sym)
4919 TInsn *insn;
4920 symbolS *label_sym;
4921{
4922 symbolS *sym = get_special_label_symbol ();
4923 int i;
43cd72b9 4924 /* assert (!insn->is_literal); */
e0001a05
NC		 4925 for (i = 0; i < insn->ntok; i++)
4926 if (insn->tok[i].X_add_symbol == sym)
4927 insn->tok[i].X_add_symbol = label_sym;
4928
4929}
4930
4931
43cd72b9 4932/* Return TRUE if the instruction can write to the specified
e0001a05
NC		 4933 integer register. */
4934
4935static bfd_boolean
4936is_register_writer (insn, regset, regnum)
4937 const TInsn *insn;
4938 const char *regset;
4939 int regnum;
4940{
4941 int i;
4942 int num_ops;
4943 xtensa_isa isa = xtensa_default_isa;
4944
43cd72b9 4945 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 4946
4947 for (i = 0; i < num_ops; i++)
4948 {
43cd72b9
BW		 4949 char inout;
4950 inout = xtensa_operand_inout (isa, insn->opcode, i);
4951 if ((inout == 'o' || inout == 'm')
4952 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
e0001a05 4953 {
43cd72b9
BW		 4954 xtensa_regfile opnd_rf =
4955 xtensa_operand_regfile (isa, insn->opcode, i);
4956 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
e0001a05
NC		 4957 {
4958 if ((insn->tok[i].X_op == O_register)
4959 && (insn->tok[i].X_add_number == regnum))
4960 return TRUE;
4961 }
4962 }
4963 }
4964 return FALSE;
4965}
4966
4967
4968static bfd_boolean
4969is_bad_loopend_opcode (tinsn)
4970 const TInsn * tinsn;
4971{
4972 xtensa_opcode opcode = tinsn->opcode;
4973
4974 if (opcode == XTENSA_UNDEFINED)
4975 return FALSE;
4976
4977 if (opcode == xtensa_call0_opcode
4978 || opcode == xtensa_callx0_opcode
4979 || opcode == xtensa_call4_opcode
4980 || opcode == xtensa_callx4_opcode
4981 || opcode == xtensa_call8_opcode
4982 || opcode == xtensa_callx8_opcode
4983 || opcode == xtensa_call12_opcode
4984 || opcode == xtensa_callx12_opcode
4985 || opcode == xtensa_isync_opcode
4986 || opcode == xtensa_ret_opcode
4987 || opcode == xtensa_ret_n_opcode
4988 || opcode == xtensa_retw_opcode
4989 || opcode == xtensa_retw_n_opcode
43cd72b9
BW		 4990 || opcode == xtensa_waiti_opcode
4991 || opcode == xtensa_rsr_lcount_opcode)
e0001a05
NC		 4992 return TRUE;
4993
e0001a05
NC		 4994 return FALSE;
4995}
4996
4997
4998/* Labels that begin with ".Ln" or ".LM" are unaligned.
4999 This allows the debugger to add unaligned labels.
5000 Also, the assembler generates stabs labels that need
5001 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
5002
5003bfd_boolean
43cd72b9
BW		 5004is_unaligned_label (sym)
5005 symbolS *sym;
e0001a05
NC		 5006{
5007 const char *name = S_GET_NAME (sym);
5008 static size_t fake_size = 0;
5009
5010 if (name
5011 && name[0] == '.'
5012 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
5013 return TRUE;
5014
5015 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
5016 if (fake_size == 0)
5017 fake_size = strlen (FAKE_LABEL_NAME);
5018
43cd72b9 5019 if (name
e0001a05
NC		 5020 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
5021 && (name[fake_size] == 'F'
5022 || name[fake_size] == 'L'
5023 || (name[fake_size] == 'e'
5024 && strncmp ("endfunc", name+fake_size, 7) == 0)))
5025 return TRUE;
5026
5027 return FALSE;
5028}
5029
5030
5031fragS *
5032next_non_empty_frag (fragP)
5033 const fragS *fragP;
5034{
5035 fragS *next_fragP = fragP->fr_next;
5036
5037 /* Sometimes an empty will end up here due storage allocation issues.
5038 So we have to skip until we find something legit. */
5039 while (next_fragP && next_fragP->fr_fix == 0)
5040 next_fragP = next_fragP->fr_next;
5041
5042 if (next_fragP == NULL || next_fragP->fr_fix == 0)
5043 return NULL;
5044
5045 return next_fragP;
5046}
5047
5048
43cd72b9
BW		 5049static bfd_boolean
5050next_frag_opcode_is_loop (fragP, opcode)
5051 const fragS *fragP;
5052 xtensa_opcode *opcode;
5053{
5054 xtensa_opcode out_opcode;
5055 const fragS *next_fragP = next_non_empty_frag (fragP);
5056
5057 if (next_fragP == NULL)
5058 return FALSE;
5059
5060 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
5061 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
5062 {
5063 *opcode = out_opcode;
5064 return TRUE;
5065 }
5066 return FALSE;
5067}
5068
5069
5070static int
5071next_frag_format_size (fragP)
5072 const fragS *fragP;
e0001a05
NC		 5073{
5074 const fragS *next_fragP = next_non_empty_frag (fragP);
43cd72b9
BW		 5075 return frag_format_size (next_fragP);
5076}
5077
5078
5079static int
5080frag_format_size (fragP)
5081 const fragS * fragP;
5082{
e0001a05
NC		 5083 static xtensa_insnbuf insnbuf = NULL;
5084 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 5085 xtensa_format fmt;
5086 int fmt_size;
e0001a05
NC		 5087
5088 if (!insnbuf)
5089 insnbuf = xtensa_insnbuf_alloc (isa);
5090
43cd72b9
BW		 5091 if (fragP == NULL)
5092 return XTENSA_UNDEFINED;
5093
5094 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal, 0);
5095
5096 fmt = xtensa_format_decode (isa, insnbuf);
5097 if (fmt == XTENSA_UNDEFINED)
e0001a05 5098 return XTENSA_UNDEFINED;
43cd72b9
BW		 5099 fmt_size = xtensa_format_length (isa, fmt);
5100
5101 /* If the next format won't be changing due to relaxation, just
5102 return the length of the first format. */
5103 if (fragP->fr_opcode != fragP->fr_literal)
5104 return fmt_size;
5105
5106 /* If during relaxation we have to pull an instruction out of a
5107 multi-slot instruction, we will return the more conservative
5108 number. This works because alignment on bigger instructions
5109 is more restrictive than alignment on smaller instructions.
5110 This is more conservative than we would like, but it happens
5111 infrequently. */
5112
5113 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
5114 return fmt_size;
5115
5116 /* If we aren't doing one of our own relaxations or it isn't
5117 slot-based, then the insn size won't change. */
5118 if (fragP->fr_type != rs_machine_dependent)
5119 return fmt_size;
5120 if (fragP->fr_subtype != RELAX_SLOTS)
5121 return fmt_size;
5122
5123 /* If an instruction is about to grow, return the longer size. */
5124 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
5125 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
5126 return 3;
5127
5128 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
5129 return 2 + fragP->tc_frag_data.text_expansion[0];
e0001a05 5130
43cd72b9 5131 return fmt_size;
e0001a05
NC		 5132}
5133
5134
43cd72b9 5135/* Return TRUE if the target frag is one of the next non-empty frags. */
e0001a05
NC		 5136
5137bfd_boolean
5138is_next_frag_target (fragP, target)
5139 const fragS *fragP;
5140 const fragS *target;
5141{
5142 if (fragP == NULL)
5143 return FALSE;
5144
5145 for (; fragP; fragP = fragP->fr_next)
5146 {
5147 if (fragP == target)
5148 return TRUE;
5149 if (fragP->fr_fix != 0)
5150 return FALSE;
5151 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
5152 return FALSE;
5153 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
5154 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
5155 return FALSE;
5156 if (fragP->fr_type == rs_space)
5157 return FALSE;
5158 }
5159 return FALSE;
5160}
5161
5162
5163/* If the next legit fragment is an end-of-loop marker,
5164 switch its state so it will instantiate a NOP. */
5165
5166static void
43cd72b9 5167update_next_frag_state (fragP, unreachable)
e0001a05 5168 fragS *fragP;
43cd72b9 5169 bfd_boolean unreachable;
e0001a05
NC		 5170{
5171 fragS *next_fragP = fragP->fr_next;
43cd72b9 5172 fragS *new_target = NULL;
e0001a05 5173
43cd72b9
BW		 5174 if (align_targets)
5175 {
5176 /* We are guaranteed there will be one of these... */
5177 while (!(next_fragP->fr_type == rs_machine_dependent
5178 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
5179 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
5180 next_fragP = next_fragP->fr_next;
5181
5182 assert (next_fragP->fr_type == rs_machine_dependent
5183 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
5184 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
5185
5186 /* ...and one of these. */
5187 new_target = next_fragP->fr_next;
5188 while (!(new_target->fr_type == rs_machine_dependent
5189 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
5190 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
5191 new_target = new_target->fr_next;
5192
5193 assert (new_target->fr_type == rs_machine_dependent
5194 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
5195 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
5196 }
5197 if (unreachable)
e0001a05 5198 {
43cd72b9 5199 if (align_targets)
e0001a05 5200 {
43cd72b9
BW		 5201 next_fragP->fr_subtype = RELAX_UNREACHABLE;
5202 next_fragP->tc_frag_data.is_unreachable = TRUE;
5203 new_target->fr_subtype = RELAX_DESIRE_ALIGN;
5204 new_target->tc_frag_data.is_branch_target = TRUE;
5205 }
5206 while (next_fragP && next_fragP->fr_fix == 0)
5207 {
5208 if (next_fragP->fr_type == rs_machine_dependent
5209 && next_fragP->fr_subtype == RELAX_LOOP_END)
5210 {
5211 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
5212 return;
5213 }
5214
5215 next_fragP = next_fragP->fr_next;
5216 }
5217 }
5218 else
5219 {
5220 if (align_targets)
5221 {
5222 next_fragP->fr_subtype = RELAX_MAYBE_UNREACHABLE;
5223 next_fragP->tc_frag_data.is_unreachable = FALSE;
5224 new_target->fr_subtype = RELAX_MAYBE_DESIRE_ALIGN;
5225 new_target->tc_frag_data.is_branch_target = FALSE;
e0001a05 5226 }
e0001a05
NC		 5227 }
5228}
5229
5230
5231static bfd_boolean
5232next_frag_is_branch_target (fragP)
5233 const fragS *fragP;
5234{
43cd72b9 5235 /* Sometimes an empty will end up here due to storage allocation issues,
e0001a05
NC		 5236 so we have to skip until we find something legit. */
5237 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
5238 {
5239 if (fragP->tc_frag_data.is_branch_target)
5240 return TRUE;
5241 if (fragP->fr_fix != 0)
5242 break;
5243 }
5244 return FALSE;
5245}
5246
5247
5248static bfd_boolean
5249next_frag_is_loop_target (fragP)
5250 const fragS *fragP;
5251{
5252 /* Sometimes an empty will end up here due storage allocation issues.
5253 So we have to skip until we find something legit. */
5254 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
5255 {
5256 if (fragP->tc_frag_data.is_loop_target)
5257 return TRUE;
5258 if (fragP->fr_fix != 0)
5259 break;
5260 }
5261 return FALSE;
5262}
5263
5264
5265static addressT
5266next_frag_pre_opcode_bytes (fragp)
5267 const fragS *fragp;
5268{
5269 const fragS *next_fragp = fragp->fr_next;
43cd72b9 5270 xtensa_opcode next_opcode;
e0001a05 5271
43cd72b9 5272 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
e0001a05
NC		 5273 return 0;
5274
43cd72b9
BW		 5275 /* Sometimes an empty will end up here due to storage allocation issues,
5276 so we have to skip until we find something legit. */
e0001a05
NC		 5277 while (next_fragp->fr_fix == 0)
5278 next_fragp = next_fragp->fr_next;
5279
5280 if (next_fragp->fr_type != rs_machine_dependent)
5281 return 0;
5282
5283 /* There is some implicit knowledge encoded in here.
5284 The LOOP instructions that are NOT RELAX_IMMED have
43cd72b9
BW		 5285 been relaxed. Note that we can assume that the LOOP
5286 instruction is in slot 0 because loops aren't bundleable. */
5287 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
e0001a05
NC		 5288 return get_expanded_loop_offset (next_opcode);
5289
5290 return 0;
5291}
5292
5293
5294/* Mark a location where we can later insert literal frags. Update
5295 the section's literal_pool_loc, so subsequent literals can be
5296 placed nearest to their use. */
5297
5298static void
61846f28 5299xtensa_mark_literal_pool_location ()
e0001a05
NC		 5300{
5301 /* Any labels pointing to the current location need
5302 to be adjusted to after the literal pool. */
5303 emit_state s;
e0001a05 5304 fragS *pool_location;
e0001a05 5305
43cd72b9
BW		 5306 if (use_literal_section && !directive_state[directive_absolute_literals])
5307 return;
5308
e0001a05 5309 frag_align (2, 0, 0);
43cd72b9 5310 record_alignment (now_seg, 2);
e0001a05
NC		 5311
5312 /* We stash info in the fr_var of these frags
43cd72b9 5313 so we can later move the literal's fixes into this
e0001a05
NC		 5314 frchain's fix list. We can use fr_var because fr_var's
5315 interpretation depends solely on the fr_type and subtype. */
5316 pool_location = frag_now;
43cd72b9 5317 frag_variant (rs_machine_dependent, 0, (int) frchain_now,
e0001a05 5318 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
43cd72b9
BW		 5319 xtensa_set_frag_assembly_state (frag_now);
5320 frag_variant (rs_machine_dependent, 0, (int) now_seg,
e0001a05 5321 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
43cd72b9 5322 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5323
5324 /* Now put a frag into the literal pool that points to this location. */
5325 set_literal_pool_location (now_seg, pool_location);
43cd72b9
BW		 5326 xtensa_switch_to_non_abs_literal_fragment (&s);
5327 frag_align (2, 0, 0);
5328 record_alignment (now_seg, 2);
e0001a05
NC		 5329
5330 /* Close whatever frag is there. */
5331 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 5332 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5333 frag_now->tc_frag_data.literal_frag = pool_location;
5334 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
5335 xtensa_restore_emit_state (&s);
43cd72b9 5336 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5337}
5338
5339
82e7541d
BW		 5340/* The "loops_ok" argument is provided to allow ignoring labels that
5341 define loop ends. This fixes a bug where the NOPs to align a
5342 loop opcode were included in a previous zero-cost loop:
5343
5344 loop a0, loopend
5345 <loop1 body>
5346 loopend:
5347
5348 loop a2, loopend2
5349 <loop2 body>
5350
5351 would become:
5352
5353 loop a0, loopend
5354 <loop1 body>
5355 nop.n <===== bad!
5356 loopend:
5357
5358 loop a2, loopend2
5359 <loop2 body>
5360
5361 This argument is used to prevent moving the NOP to before the
5362 loop-end label, which is what you want in this special case. */
5363
e0001a05 5364static void
82e7541d
BW		 5365xtensa_move_labels (new_frag, new_offset, loops_ok)
5366 fragS *new_frag;
e0001a05 5367 valueT new_offset;
82e7541d 5368 bfd_boolean loops_ok;
e0001a05 5369{
82e7541d 5370 sym_list *lit;
e0001a05 5371
82e7541d 5372 for (lit = insn_labels; lit; lit = lit->next)
e0001a05 5373 {
82e7541d 5374 symbolS *lit_sym = lit->sym;
43cd72b9 5375 if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
82e7541d
BW		 5376 {
5377 S_SET_VALUE (lit_sym, new_offset);
5378 symbol_set_frag (lit_sym, new_frag);
5379 }
e0001a05
NC		 5380 }
5381}
5382
5383
43cd72b9
BW		 5384/* Build a nop of the correct size into tinsn. */
5385
5386static void
5387build_nop (tinsn, size)
5388 TInsn *tinsn;
5389 int size;
5390{
5391 tinsn_init (tinsn);
5392 switch (size)
5393 {
5394 case 2:
5395 tinsn->opcode = xtensa_nop_n_opcode;
5396 tinsn->ntok = 0;
5397 if (tinsn->opcode == XTENSA_UNDEFINED)
5398 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
5399 break;
5400
5401 case 3:
5402 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
5403 {
5404 tinsn->opcode = xtensa_or_opcode;
5405 set_expr_const (&tinsn->tok[0], 1);
5406 set_expr_const (&tinsn->tok[1], 1);
5407 set_expr_const (&tinsn->tok[2], 1);
5408 tinsn->ntok = 3;
5409 }
5410 else
5411 tinsn->opcode = xtensa_nop_opcode;
5412
5413 assert (tinsn->opcode != XTENSA_UNDEFINED);
5414 }
5415}
5416
5417
e0001a05
NC		 5418/* Assemble a NOP of the requested size in the buffer. User must have
5419 allocated "buf" with at least "size" bytes. */
5420
5421void
5422assemble_nop (size, buf)
5423 size_t size;
5424 char *buf;
5425{
5426 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 5427 TInsn tinsn;
e0001a05 5428
43cd72b9 5429 build_nop (&tinsn, size);
e0001a05 5430
43cd72b9
BW		 5431 if (!insnbuf)
5432 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
e0001a05 5433
43cd72b9
BW		 5434 tinsn_to_insnbuf (&tinsn, insnbuf);
5435 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
e0001a05
NC		 5436}
5437
5438
5439/* Return the number of bytes for the offset of the expanded loop
5440 instruction. This should be incorporated into the relaxation
5441 specification but is hard-coded here. This is used to auto-align
5442 the loop instruction. It is invalid to call this function if the
5443 configuration does not have loops or if the opcode is not a loop
5444 opcode. */
5445
5446static addressT
5447get_expanded_loop_offset (opcode)
5448 xtensa_opcode opcode;
5449{
5450 /* This is the OFFSET of the loop instruction in the expanded loop.
5451 This MUST correspond directly to the specification of the loop
5452 expansion. It will be validated on fragment conversion. */
43cd72b9 5453 assert (opcode != XTENSA_UNDEFINED);
e0001a05
NC		 5454 if (opcode == xtensa_loop_opcode)
5455 return 0;
5456 if (opcode == xtensa_loopnez_opcode)
5457 return 3;
5458 if (opcode == xtensa_loopgtz_opcode)
5459 return 6;
5460 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
5461 return 0;
5462}
5463
5464
5465fragS *
5466get_literal_pool_location (seg)
5467 segT seg;
5468{
5469 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
5470}
5471
5472
5473static void
5474set_literal_pool_location (seg, literal_pool_loc)
5475 segT seg;
5476 fragS *literal_pool_loc;
5477{
5478 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
5479}
5480
43cd72b9
BW		 5481
5482/* Set frag assembly state should be called when a new frag is
5483 opened and after a frag has been closed. */
5484
5485void
5486xtensa_set_frag_assembly_state (fragP)
5487 fragS *fragP;
5488{
5489 if (!density_supported)
5490 fragP->tc_frag_data.is_no_density = TRUE;
5491
5492 /* This function is called from subsegs_finish, which is called
5493 after xtensa_end, so we can't use "use_transform" or
5494 "use_schedule" here. */
5495 if (!directive_state[directive_transform])
5496 fragP->tc_frag_data.is_no_transform = TRUE;
5497 fragP->tc_frag_data.use_absolute_literals =
5498 directive_state[directive_absolute_literals];
5499 fragP->tc_frag_data.is_assembly_state_set = TRUE;
5500}
5501
5502
5503bfd_boolean
5504relaxable_section (sec)
5505 asection *sec;
5506{
5507 return (sec->flags & SEC_DEBUGGING) == 0;
5508}
5509
5510
5511static void
5512xtensa_find_unmarked_state_frags ()
5513{
5514 segT *seclist;
5515
5516 /* Walk over each fragment of all of the current segments. For each
5517 unmarked fragment, mark it with the same info as the previous
5518 fragment. */
5519 for (seclist = &stdoutput->sections;
5520 seclist && *seclist;
5521 seclist = &(*seclist)->next)
5522 {
5523 segT sec = *seclist;
5524 segment_info_type *seginfo;
5525 fragS *fragP;
5526 flagword flags;
5527 flags = bfd_get_section_flags (stdoutput, sec);
5528 if (flags & SEC_DEBUGGING)
5529 continue;
5530 if (!(flags & SEC_ALLOC))
5531 continue;
5532
5533 seginfo = seg_info (sec);
5534 if (seginfo && seginfo->frchainP)
5535 {
5536 fragS *last_fragP = 0;
5537 for (fragP = seginfo->frchainP->frch_root; fragP;
5538 fragP = fragP->fr_next)
5539 {
5540 if (fragP->fr_fix != 0
5541 && !fragP->tc_frag_data.is_assembly_state_set)
5542 {
5543 if (last_fragP == 0)
5544 {
5545 as_warn_where (fragP->fr_file, fragP->fr_line,
5546 _("assembly state not set for first frag in section %s"),
5547 sec->name);
5548 }
5549 else
5550 {
5551 fragP->tc_frag_data.is_assembly_state_set = TRUE;
5552 fragP->tc_frag_data.is_no_density =
5553 last_fragP->tc_frag_data.is_no_density;
5554 fragP->tc_frag_data.is_no_transform =
5555 last_fragP->tc_frag_data.is_no_transform;
5556 fragP->tc_frag_data.use_absolute_literals =
5557 last_fragP->tc_frag_data.use_absolute_literals;
5558 }
5559 }
5560 if (fragP->tc_frag_data.is_assembly_state_set)
5561 last_fragP = fragP;
5562 }
5563 }
5564 }
5565}
5566
5567
5568static void
5569xtensa_find_unaligned_branch_targets (abfd, sec, unused)
5570 bfd *abfd ATTRIBUTE_UNUSED;
5571 asection *sec;
5572 PTR unused ATTRIBUTE_UNUSED;
5573{
5574 flagword flags = bfd_get_section_flags (abfd, sec);
5575 segment_info_type *seginfo = seg_info (sec);
5576 fragS *frag = seginfo->frchainP->frch_root;
5577
5578 if (flags & SEC_CODE)
5579 {
5580 xtensa_isa isa = xtensa_default_isa;
5581 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5582 while (frag != NULL)
5583 {
5584 if (frag->tc_frag_data.is_branch_target)
5585 {
5586 int op_size;
5587 int frag_addr;
5588 xtensa_format fmt;
5589
5590 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
5591 fmt = xtensa_format_decode (isa, insnbuf);
5592 op_size = xtensa_format_length (isa, fmt);
5593 frag_addr = frag->fr_address % xtensa_fetch_width;
5594 if (frag_addr + op_size > (int) xtensa_fetch_width)
5595 as_warn_where (frag->fr_file, frag->fr_line,
5596 _("unaligned branch target: %d bytes at 0x%lx"),
5597 op_size, frag->fr_address);
5598 }
5599 frag = frag->fr_next;
5600 }
5601 xtensa_insnbuf_free (isa, insnbuf);
5602 }
5603}
5604
5605
5606static void
5607xtensa_find_unaligned_loops (abfd, sec, unused)
5608 bfd *abfd ATTRIBUTE_UNUSED;
5609 asection *sec;
5610 PTR unused ATTRIBUTE_UNUSED;
5611{
5612 flagword flags = bfd_get_section_flags (abfd, sec);
5613 segment_info_type *seginfo = seg_info (sec);
5614 fragS *frag = seginfo->frchainP->frch_root;
5615 xtensa_isa isa = xtensa_default_isa;
5616
5617 if (flags & SEC_CODE)
5618 {
5619 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5620 while (frag != NULL)
5621 {
5622 if (frag->tc_frag_data.is_first_loop_insn)
5623 {
5624 int op_size;
5625 int frag_addr;
5626 xtensa_format fmt;
5627
5628 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
5629 fmt = xtensa_format_decode (isa, insnbuf);
5630 op_size = xtensa_format_length (isa, fmt);
5631 frag_addr = frag->fr_address % xtensa_fetch_width;
5632
5633 if (frag_addr + op_size > (signed) xtensa_fetch_width)
5634 as_warn_where (frag->fr_file, frag->fr_line,
5635 _("unaligned loop: %d bytes at 0x%lx"),
5636 op_size, frag->fr_address);
5637 }
5638 frag = frag->fr_next;
5639 }
5640 xtensa_insnbuf_free (isa, insnbuf);
5641 }
5642}
5643
5644
5645void
5646xg_apply_tentative_value (fixP, val)
5647 fixS *fixP;
5648 valueT val;
5649{
5650 xtensa_isa isa = xtensa_default_isa;
5651 static xtensa_insnbuf insnbuf = NULL;
5652 static xtensa_insnbuf slotbuf = NULL;
5653 xtensa_format fmt;
5654 int slot;
5655 bfd_boolean alt_reloc;
5656 xtensa_opcode opcode;
5657 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5658
5659 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
5660 if (alt_reloc)
5661 as_fatal (_("unexpected fix"));
5662
5663 if (!insnbuf)
5664 {
5665 insnbuf = xtensa_insnbuf_alloc (isa);
5666 slotbuf = xtensa_insnbuf_alloc (isa);
5667 }
5668
5669 xtensa_insnbuf_from_chars (isa, insnbuf, fixpos, 0);
5670 fmt = xtensa_format_decode (isa, insnbuf);
5671 if (fmt == XTENSA_UNDEFINED)
5672 as_fatal (_("undecodable fix"));
5673 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5674 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5675 if (opcode == XTENSA_UNDEFINED)
5676 as_fatal (_("undecodable fix"));
5677
5678 /* CONST16 immediates are not PC-relative, despite the fact that we
5679 reuse the normal PC-relative operand relocations for the low part
5680 of a CONST16 operand. The code in tc_gen_reloc does not decode
5681 the opcodes so it is more convenient to detect this special case
5682 here. */
5683 if (opcode == xtensa_const16_opcode)
5684 return;
5685
5686 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5687 get_relaxable_immed (opcode), val,
5688 fixP->fx_file, fixP->fx_line);
5689
5690 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5691 xtensa_insnbuf_to_chars (isa, insnbuf, fixpos, 0);
5692}
5693
e0001a05
NC		 5694\f
5695/* External Functions and Other GAS Hooks. */
5696
5697const char *
5698xtensa_target_format ()
5699{
5700 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5701}
5702
5703
5704void
5705xtensa_file_arch_init (abfd)
5706 bfd *abfd;
5707{
5708 bfd_set_private_flags (abfd, 0x100 | 0x200);
5709}
5710
5711
5712void
5713md_number_to_chars (buf, val, n)
5714 char *buf;
5715 valueT val;
5716 int n;
5717{
5718 if (target_big_endian)
5719 number_to_chars_bigendian (buf, val, n);
5720 else
5721 number_to_chars_littleendian (buf, val, n);
5722}
5723
5724
5725/* This function is called once, at assembler startup time. It should
5726 set up all the tables, etc. that the MD part of the assembler will
5727 need. */
5728
5729void
5730md_begin ()
5731{
5732 segT current_section = now_seg;
5733 int current_subsec = now_subseg;
5734 xtensa_isa isa;
5735
43cd72b9 5736 xtensa_default_isa = xtensa_isa_init (0, 0);
e0001a05 5737 isa = xtensa_default_isa;
e0001a05 5738
43cd72b9
BW		 5739 linkrelax = 1;
5740
5741 /* Set up the .literal, .fini.literal and .init.literal sections. */
e0001a05
NC		 5742 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5743 default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
5744 default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
5745 default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
43cd72b9 5746 default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
e0001a05
NC		 5747
5748 subseg_set (current_section, current_subsec);
5749
43cd72b9
BW		 5750 xg_init_vinsn (&cur_vinsn);
5751
e0001a05
NC		 5752 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5753 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5754 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5755 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5756 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5757 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5758 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5759 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5760 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5761 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
43cd72b9 5762 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
e0001a05 5763 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
43cd72b9
BW		 5764 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5765 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
e0001a05 5766 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
e0001a05 5767 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
43cd72b9 5768 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
e0001a05
NC		 5769 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5770 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5771 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
43cd72b9 5772 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
e0001a05
NC		 5773 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5774 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5775 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5776 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5777 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5778 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
43cd72b9 5779 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
e0001a05 5780 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
43cd72b9
BW		 5781
5782 init_op_placement_info_table ();
5783
5784 /* Set up the assembly state. */
5785 if (!frag_now->tc_frag_data.is_assembly_state_set)
5786 xtensa_set_frag_assembly_state (frag_now);
5787}
5788
5789
5790/* TC_INIT_FIX_DATA hook */
5791
5792void
5793xtensa_init_fix_data (x)
5794 fixS *x;
5795{
5796 x->tc_fix_data.slot = 0;
5797 x->tc_fix_data.X_add_symbol = NULL;
5798 x->tc_fix_data.X_add_number = 0;
e0001a05
NC		 5799}
5800
5801
5802/* tc_frob_label hook */
5803
5804void
5805xtensa_frob_label (sym)
5806 symbolS *sym;
5807{
43cd72b9
BW		 5808 /* Since the label was already attached to a frag associated with the
5809 previous basic block, it now needs to be reset to the current frag. */
5810 symbol_set_frag (sym, frag_now);
5811 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5812
82e7541d
BW		 5813 if (generating_literals)
5814 xtensa_add_literal_sym (sym);
5815 else
5816 xtensa_add_insn_label (sym);
5817
5818 if (symbol_get_tc (sym)->is_loop_target
e0001a05
NC		 5819 && (get_last_insn_flags (now_seg, now_subseg)
5820 & FLAG_IS_BAD_LOOPEND) != 0)
5821 as_bad (_("invalid last instruction for a zero-overhead loop"));
5822
5823 /* No target aligning in the absolute section. */
61846f28 5824 if (now_seg != absolute_section
43cd72b9 5825 && do_align_targets ()
61846f28 5826 && !is_unaligned_label (sym)
43cd72b9
BW		 5827 && !generating_literals)
5828 {
5829 float freq = get_subseg_info (now_seg, now_subseg)->cur_target_freq;
5830 xtensa_set_frag_assembly_state (frag_now);
5831
5832 /* The only time this type of frag grows is when there is a
5833 negatable branch that needs to be relaxed as the last
5834 instruction in a zero-overhead loop. Because alignment frags
5835 are so common, marking them all as possibly growing four
5836 bytes makes any worst-case analysis appear much worse than it
5837 is. So, we make fr_var not actually reflect the amount of
5838 memory allocated at the end of this frag, but rather the
5839 amount of memory this frag might grow. The "4, 0" below
5840 allocates four bytes at the end of the frag for room to grow
5841 if we need to relax a loop end with a NOP. Frags prior to
5842 this one might grow to align this one, but the frag itself
5843 won't grow unless it meets the condition above. */
5844
5845#define RELAX_LOOP_END_BYTES 4
5846
5847 frag_var (rs_machine_dependent,
5848 RELAX_LOOP_END_BYTES, (int) freq,
e0001a05
NC		 5849 RELAX_DESIRE_ALIGN_IF_TARGET,
5850 frag_now->fr_symbol, frag_now->fr_offset, NULL);
43cd72b9 5851 xtensa_set_frag_assembly_state (frag_now);
82e7541d 5852 xtensa_move_labels (frag_now, 0, TRUE);
43cd72b9
BW		 5853 }
5854
5855 /* We need to mark the following properties even if we aren't aligning. */
5856
5857 /* If the label is already known to be a branch target, i.e., a
5858 forward branch, mark the frag accordingly. Backward branches
5859 are handled by xg_add_branch_and_loop_targets. */
5860 if (symbol_get_tc (sym)->is_branch_target)
5861 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5862
5863 /* Loops only go forward, so they can be identified here. */
5864 if (symbol_get_tc (sym)->is_loop_target)
5865 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5866}
5867
5868
5869/* tc_unrecognized_line hook */
5870
5871int
5872xtensa_unrecognized_line (ch)
5873 int ch;
5874{
5875 switch (ch)
5876 {
5877 case '{' :
5878 if (cur_vinsn.inside_bundle == 0)
5879 {
5880 /* PR8110: Cannot emit line number info inside a FLIX bundle
5881 when using --gstabs. Temporarily disable debug info. */
5882 generate_lineno_debug ();
5883 if (debug_type == DEBUG_STABS)
5884 {
5885 xt_saved_debug_type = debug_type;
5886 debug_type = DEBUG_NONE;
5887 }
82e7541d 5888
43cd72b9
BW		 5889 cur_vinsn.inside_bundle = 1;
5890 }
5891 else
5892 {
5893 as_bad (_("extra opening brace"));
5894 return 0;
5895 }
5896 break;
82e7541d 5897
43cd72b9
BW		 5898 case '}' :
5899 if (cur_vinsn.inside_bundle)
5900 finish_vinsn (&cur_vinsn);
5901 else
5902 {
5903 as_bad (_("extra closing brace"));
5904 return 0;
5905 }
5906 break;
5907 default:
5908 as_bad (_("syntax error"));
5909 return 0;
e0001a05 5910 }
43cd72b9 5911 return 1;
e0001a05
NC		 5912}
5913
5914
5915/* md_flush_pending_output hook */
5916
5917void
5918xtensa_flush_pending_output ()
5919{
43cd72b9
BW		 5920 if (cur_vinsn.inside_bundle)
5921 as_bad (_("missing closing brace"));
5922
e0001a05
NC		 5923 /* If there is a non-zero instruction fragment, close it. */
5924 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5925 {
5926 frag_wane (frag_now);
5927 frag_new (0);
43cd72b9 5928 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5929 }
5930 frag_now->tc_frag_data.is_insn = FALSE;
82e7541d
BW		 5931
5932 xtensa_clear_insn_labels ();
e0001a05
NC		 5933}
5934
5935
43cd72b9
BW		 5936/* We had an error while parsing an instruction. The string might look
5937 like this: "insn arg1, arg2 }". If so, we need to see the closing
5938 brace and reset some fields. Otherwise, the vinsn never gets closed
5939 and the num_slots field will grow past the end of the array of slots,
5940 and bad things happen. */
5941
5942static void
5943error_reset_cur_vinsn ()
5944{
5945 if (cur_vinsn.inside_bundle)
5946 {
5947 if (*input_line_pointer == '}'
5948 || *(input_line_pointer - 1) == '}'
5949 || *(input_line_pointer - 2) == '}')
5950 xg_clear_vinsn (&cur_vinsn);
5951 }
5952}
5953
5954
e0001a05
NC		 5955void
5956md_assemble (str)
5957 char *str;
5958{
5959 xtensa_isa isa = xtensa_default_isa;
5960 char *opname;
5961 unsigned opnamelen;
5962 bfd_boolean has_underbar = FALSE;
43cd72b9 5963 char *arg_strings[MAX_INSN_ARGS];
e0001a05 5964 int num_args;
e0001a05 5965 TInsn orig_insn; /* Original instruction from the input. */
e0001a05 5966
e0001a05
NC		 5967 tinsn_init (&orig_insn);
5968
5969 /* Split off the opcode. */
5970 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5971 opname = xmalloc (opnamelen + 1);
5972 memcpy (opname, str, opnamelen);
5973 opname[opnamelen] = '\0';
5974
5975 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5976 if (num_args == -1)
5977 {
5978 as_bad (_("syntax error"));
5979 return;
5980 }
5981
5982 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5983 return;
5984
5985 /* Check for an underbar prefix. */
5986 if (*opname == '_')
5987 {
5988 has_underbar = TRUE;
5989 opname += 1;
5990 }
5991
5992 orig_insn.insn_type = ITYPE_INSN;
5993 orig_insn.ntok = 0;
43cd72b9 5994 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
e0001a05
NC		 5995
5996 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5997 if (orig_insn.opcode == XTENSA_UNDEFINED)
5998 {
43cd72b9
BW		 5999 xtensa_format fmt = xtensa_format_lookup (isa, opname);
6000 if (fmt == XTENSA_UNDEFINED)
6001 {
6002 as_bad (_("unknown opcode or format name '%s'"), opname);
6003 error_reset_cur_vinsn ();
6004 return;
6005 }
6006 if (!cur_vinsn.inside_bundle)
6007 {
6008 as_bad (_("format names only valid inside bundles"));
6009 error_reset_cur_vinsn ();
6010 return;
6011 }
6012 if (cur_vinsn.format != XTENSA_UNDEFINED)
6013 as_warn (_("multiple formats specified for one bundle; using '%s'"),
6014 opname);
6015 cur_vinsn.format = fmt;
6016 free (has_underbar ? opname - 1 : opname);
6017 error_reset_cur_vinsn ();
e0001a05
NC		 6018 return;
6019 }
6020
e0001a05
NC		 6021 /* Special case: The call instructions should be marked "specific opcode"
6022 to keep them from expanding. */
6023 if (!use_longcalls () && is_direct_call_opcode (orig_insn.opcode))
6024 orig_insn.is_specific_opcode = TRUE;
6025
6026 /* Parse the arguments. */
6027 if (parse_arguments (&orig_insn, num_args, arg_strings))
6028 {
6029 as_bad (_("syntax error"));
43cd72b9 6030 error_reset_cur_vinsn ();
e0001a05
NC		 6031 return;
6032 }
6033
6034 /* Free the opcode and argument strings, now that they've been parsed. */
6035 free (has_underbar ? opname - 1 : opname);
6036 opname = 0;
6037 while (num_args-- > 0)
6038 free (arg_strings[num_args]);
6039
43cd72b9
BW		 6040 /* Get expressions for invisible operands. */
6041 if (get_invisible_operands (&orig_insn))
6042 {
6043 error_reset_cur_vinsn ();
6044 return;
6045 }
6046
e0001a05
NC		 6047 /* Check for the right number and type of arguments. */
6048 if (tinsn_check_arguments (&orig_insn))
e0001a05 6049 {
43cd72b9
BW		 6050 error_reset_cur_vinsn ();
6051 return;
e0001a05
NC		 6052 }
6053
43cd72b9
BW		 6054 dwarf2_where (&orig_insn.loc);
6055
6056 xg_add_branch_and_loop_targets (&orig_insn);
6057
61846f28 6058 /* Special-case for "entry" instruction. */
e0001a05
NC		 6059 if (is_entry_opcode (orig_insn.opcode))
6060 {
43cd72b9
BW		 6061 /* Check that the third opcode (#2) is >= 16. */
6062 if (orig_insn.ntok >= 3)
e0001a05 6063 {
43cd72b9 6064 expressionS *exp = &orig_insn.tok[2];
e0001a05
NC		 6065 switch (exp->X_op)
6066 {
6067 case O_constant:
6068 if (exp->X_add_number < 16)
6069 as_warn (_("entry instruction with stack decrement < 16"));
6070 break;
6071
6072 default:
6073 as_warn (_("entry instruction with non-constant decrement"));
6074 }
6075 }
e0001a05
NC		 6076 }
6077
e0001a05 6078 /* Finish it off:
43cd72b9
BW		 6079 assemble_tokens (opcode, tok, ntok);
6080 expand the tokens from the orig_insn into the
6081 stack of instructions that will not expand
e0001a05 6082 unless required at relaxation time. */
e0001a05 6083
43cd72b9
BW		 6084 if (!cur_vinsn.inside_bundle)
6085 emit_single_op (&orig_insn);
6086 else /* We are inside a bundle. */
e0001a05 6087 {
43cd72b9
BW		 6088 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
6089 cur_vinsn.num_slots++;
6090 if (*input_line_pointer == '}'
6091 || *(input_line_pointer - 1) == '}'
6092 || *(input_line_pointer - 2) == '}')
6093 finish_vinsn (&cur_vinsn);
e0001a05
NC		 6094 }
6095
43cd72b9
BW		 6096 /* We've just emitted a new instruction so clear the list of labels. */
6097 xtensa_clear_insn_labels ();
e0001a05
NC		 6098}
6099
6100
43cd72b9 6101/* HANDLE_ALIGN hook */
e0001a05 6102
43cd72b9
BW		 6103/* For a .align directive, we mark the previous block with the alignment
6104 information. This will be placed in the object file in the
6105 property section corresponding to this section. */
e0001a05 6106
43cd72b9
BW		 6107void
6108xtensa_handle_align (fragP)
6109 fragS *fragP;
6110{
6111 if (linkrelax
6112 && !get_frag_is_literal (fragP)
6113 && (fragP->fr_type == rs_align
6114 || fragP->fr_type == rs_align_code)
6115 && fragP->fr_address + fragP->fr_fix > 0
6116 && fragP->fr_offset > 0
6117 && now_seg != bss_section)
e0001a05 6118 {
43cd72b9
BW		 6119 fragP->tc_frag_data.is_align = TRUE;
6120 fragP->tc_frag_data.alignment = fragP->fr_offset;
e0001a05
NC		 6121 }
6122
43cd72b9 6123 if (fragP->fr_type == rs_align_test)
e0001a05 6124 {
43cd72b9
BW		 6125 int count;
6126 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
6127 if (count != 0)
6128 as_bad_where (fragP->fr_file, fragP->fr_line,
6129 _("unaligned entry instruction"));
e0001a05 6130 }
e0001a05 6131}
43cd72b9 6132
e0001a05
NC		 6133
6134/* TC_FRAG_INIT hook */
6135
6136void
6137xtensa_frag_init (frag)
6138 fragS *frag;
6139{
43cd72b9 6140 xtensa_set_frag_assembly_state (frag);
e0001a05
NC		 6141}
6142
6143
6144symbolS *
6145md_undefined_symbol (name)
6146 char *name ATTRIBUTE_UNUSED;
6147{
6148 return NULL;
6149}
6150
6151
6152/* Round up a section size to the appropriate boundary. */
6153
6154valueT
6155md_section_align (segment, size)
6156 segT segment ATTRIBUTE_UNUSED;
6157 valueT size;
6158{
6159 return size; /* Byte alignment is fine. */
6160}
6161
6162
6163long
6164md_pcrel_from (fixP)
6165 fixS *fixP;
6166{
6167 char *insn_p;
6168 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 6169 static xtensa_insnbuf slotbuf = NULL;
e0001a05 6170 int opnum;
43cd72b9 6171 uint32 opnd_value;
e0001a05 6172 xtensa_opcode opcode;
43cd72b9
BW		 6173 xtensa_format fmt;
6174 int slot;
e0001a05
NC		 6175 xtensa_isa isa = xtensa_default_isa;
6176 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
43cd72b9 6177 bfd_boolean alt_reloc;
e0001a05
NC		 6178
6179 if (fixP->fx_done)
6180 return addr;
6181
6182 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
6183 return addr;
6184
6185 if (!insnbuf)
43cd72b9
BW		 6186 {
6187 insnbuf = xtensa_insnbuf_alloc (isa);
6188 slotbuf = xtensa_insnbuf_alloc (isa);
6189 }
e0001a05
NC		 6190
6191 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
43cd72b9
BW		 6192 xtensa_insnbuf_from_chars (isa, insnbuf, insn_p, 0);
6193 fmt = xtensa_format_decode (isa, insnbuf);
6194
6195 if (fmt == XTENSA_UNDEFINED)
6196 as_fatal (_("bad instruction format"));
6197
6198 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
6199 as_fatal (_("invalid relocation"));
6200
6201 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
6202 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
6203
6204 /* Check for "alternate" relocation (operand not specified). */
6205 if (alt_reloc || opcode == xtensa_const16_opcode)
6206 {
6207 if (opcode != xtensa_l32r_opcode
6208 && opcode != xtensa_const16_opcode)
6209 as_fatal (_("invalid relocation for '%s' instruction"),
6210 xtensa_opcode_name (isa, opcode));
e0001a05
NC		 6211 return addr;
6212 }
6213
43cd72b9
BW		 6214 opnum = get_relaxable_immed (opcode);
6215 opnd_value = 0;
6216 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
6217 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
e0001a05
NC		 6218 {
6219 as_bad_where (fixP->fx_file,
6220 fixP->fx_line,
6221 _("invalid relocation for operand %d of '%s'"),
6222 opnum, xtensa_opcode_name (isa, opcode));
6223 return addr;
6224 }
43cd72b9
BW		 6225 return 0 - opnd_value;
6226}
6227
6228
6229/* TC_FORCE_RELOCATION hook */
6230
6231int
6232xtensa_force_relocation (fix)
6233 fixS *fix;
6234{
6235 switch (fix->fx_r_type)
6236 {
6237 case BFD_RELOC_XTENSA_SLOT0_ALT:
6238 case BFD_RELOC_XTENSA_SLOT1_ALT:
6239 case BFD_RELOC_XTENSA_SLOT2_ALT:
6240 case BFD_RELOC_XTENSA_SLOT3_ALT:
6241 case BFD_RELOC_XTENSA_SLOT4_ALT:
6242 case BFD_RELOC_XTENSA_SLOT5_ALT:
6243 case BFD_RELOC_XTENSA_SLOT6_ALT:
6244 case BFD_RELOC_XTENSA_SLOT7_ALT:
6245 case BFD_RELOC_XTENSA_SLOT8_ALT:
6246 case BFD_RELOC_XTENSA_SLOT9_ALT:
6247 case BFD_RELOC_XTENSA_SLOT10_ALT:
6248 case BFD_RELOC_XTENSA_SLOT11_ALT:
6249 case BFD_RELOC_XTENSA_SLOT12_ALT:
6250 case BFD_RELOC_XTENSA_SLOT13_ALT:
6251 case BFD_RELOC_XTENSA_SLOT14_ALT:
6252 case BFD_RELOC_VTABLE_INHERIT:
6253 case BFD_RELOC_VTABLE_ENTRY:
6254 return 1;
6255 default:
6256 break;
e0001a05
NC		 6257 }
6258
43cd72b9
BW		 6259 if (linkrelax && fix->fx_addsy
6260 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
6261 return 1;
6262
6263 return generic_force_reloc (fix);
6264}
6265
6266
6267/* NO_PSEUDO_DOT hook */
6268
6269/* This function has nothing to do with pseudo dots, but this is the
6270 nearest macro to where the check needs to take place. FIXME: This
6271 seems wrong. */
6272
6273bfd_boolean
6274xtensa_check_inside_bundle ()
6275{
6276 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
6277 as_bad (_("directives are not valid inside bundles"));
6278
6279 /* This function must always return FALSE because it is called via a
6280 macro that has nothing to do with bundling. */
6281 return FALSE;
e0001a05
NC		 6282}
6283
6284
43cd72b9 6285/* md_elf_section_change_hook */
e0001a05
NC		 6286
6287void
43cd72b9 6288xtensa_elf_section_change_hook ()
e0001a05 6289{
43cd72b9
BW		 6290 /* Set up the assembly state. */
6291 if (!frag_now->tc_frag_data.is_assembly_state_set)
6292 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 6293}
6294
6295
6296/* tc_fix_adjustable hook */
6297
6298bfd_boolean
6299xtensa_fix_adjustable (fixP)
6300 fixS *fixP;
6301{
43cd72b9
BW		 6302 /* An offset is not allowed in combination with the difference of two
6303 symbols, but that cannot be easily detected after a local symbol
6304 has been adjusted to a (section+offset) form. Return 0 so that such
6305 an fix will not be adjusted. */
6306 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
6307 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
6308 return 0;
6309
e0001a05
NC		 6310 /* We need the symbol name for the VTABLE entries. */
6311 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
6312 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6313 return 0;
6314
43cd72b9
BW		 6315 if (fixP->fx_addsy
6316 && (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
6317 return 0;
6318
6319#if 0
6320 /* We may someday want to enable this code to preserve relocations for
6321 non-PC-relative fixes, possibly under control of a PIC flag. */
6322 return (fixP->fx_pcrel
6323 || (fixP->fx_subsy != NULL
6324 && (S_GET_SEGMENT (fixP->fx_subsy)
6325 == S_GET_SEGMENT (fixP->fx_addsy)))
6326 || S_IS_LOCAL (fixP->fx_addsy));
6327#else
e0001a05 6328 return 1;
43cd72b9 6329#endif
e0001a05
NC		 6330}
6331
6332
6333void
6334md_apply_fix3 (fixP, valP, seg)
6335 fixS *fixP;
6336 valueT *valP;
6337 segT seg ATTRIBUTE_UNUSED;
6338{
6339 if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
6340 {
e0001a05 6341 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
e0001a05
NC		 6342
6343 switch (fixP->fx_r_type)
6344 {
6345 case BFD_RELOC_XTENSA_ASM_EXPAND:
6346 fixP->fx_done = 1;
6347 break;
6348
6349 case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
6350 as_bad (_("unhandled local relocation fix %s"),
6351 bfd_get_reloc_code_name (fixP->fx_r_type));
6352 break;
6353
6354 case BFD_RELOC_32:
6355 case BFD_RELOC_16:
6356 case BFD_RELOC_8:
6357 /* The only one we support that isn't an instruction field. */
6358 md_number_to_chars (fixpos, *valP, fixP->fx_size);
6359 fixP->fx_done = 1;
6360 break;
6361
e0001a05
NC		 6362 case BFD_RELOC_VTABLE_INHERIT:
6363 case BFD_RELOC_VTABLE_ENTRY:
6364 fixP->fx_done = 0;
6365 break;
6366
6367 default:
6368 as_bad (_("unhandled local relocation fix %s"),
6369 bfd_get_reloc_code_name (fixP->fx_r_type));
6370 }
6371 }
6372}
6373
6374
6375char *
6376md_atof (type, litP, sizeP)
6377 int type;
6378 char *litP;
6379 int *sizeP;
6380{
6381 int prec;
6382 LITTLENUM_TYPE words[4];
6383 char *t;
6384 int i;
6385
6386 switch (type)
6387 {
6388 case 'f':
6389 prec = 2;
6390 break;
6391
6392 case 'd':
6393 prec = 4;
6394 break;
6395
6396 default:
6397 *sizeP = 0;
6398 return "bad call to md_atof";
6399 }
6400
6401 t = atof_ieee (input_line_pointer, type, words);
6402 if (t)
6403 input_line_pointer = t;
6404
6405 *sizeP = prec * 2;
6406
6407 for (i = prec - 1; i >= 0; i--)
6408 {
6409 int idx = i;
6410 if (target_big_endian)
6411 idx = (prec - 1 - i);
6412
6413 md_number_to_chars (litP, (valueT) words[idx], 2);
6414 litP += 2;
6415 }
6416
6417 return NULL;
6418}
6419
6420
6421int
6422md_estimate_size_before_relax (fragP, seg)
6423 fragS *fragP;
6424 segT seg ATTRIBUTE_UNUSED;
6425{
43cd72b9 6426 return fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 6427}
6428
6429
6430/* Translate internal representation of relocation info to BFD target
6431 format. */
6432
6433arelent *
6434tc_gen_reloc (section, fixp)
43cd72b9 6435 asection *section;
e0001a05
NC		 6436 fixS *fixp;
6437{
6438 arelent *reloc;
43cd72b9 6439 bfd_boolean apply_tentative_value = FALSE;
e0001a05
NC		 6440
6441 reloc = (arelent *) xmalloc (sizeof (arelent));
6442 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6443 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6444 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6445
6446 /* Make sure none of our internal relocations make it this far.
6447 They'd better have been fully resolved by this point. */
6448 assert ((int) fixp->fx_r_type > 0);
6449
43cd72b9
BW		 6450 if (linkrelax && fixp->fx_subsy
6451 && (fixp->fx_r_type == BFD_RELOC_8
6452 || fixp->fx_r_type == BFD_RELOC_16
6453 || fixp->fx_r_type == BFD_RELOC_32))
6454 {
6455 int diff_size = 0;
6456 bfd_vma diff_value, diff_mask = 0;
6457
6458 switch (fixp->fx_r_type)
6459 {
6460 case BFD_RELOC_8:
6461 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
6462 diff_size = 1;
6463 diff_mask = 0xff;
6464 break;
6465 case BFD_RELOC_16:
6466 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
6467 diff_size = 2;
6468 diff_mask = 0xffff;
6469 break;
6470 case BFD_RELOC_32:
6471 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
6472 diff_size = 4;
6473 diff_mask = 0xffffffff;
6474 break;
6475 default:
6476 break;
6477 }
6478
6479 /* An offset is only allowed when it results from adjusting a local
6480 symbol into a section-relative offset. If the offset came from the
6481 original expression, tc_fix_adjustable will have prevented the fix
6482 from being converted to a section-relative form so that we can flag
6483 the error here. */
6484 if (fixp->fx_offset != 0 && !symbol_section_p (fixp->fx_addsy))
6485 {
6486 as_bad_where (fixp->fx_file, fixp->fx_line,
6487 _("cannot represent subtraction with an offset"));
6488 free (reloc->sym_ptr_ptr);
6489 free (reloc);
6490 return NULL;
6491 }
6492
6493 assert (S_GET_SEGMENT (fixp->fx_addsy)
6494 == S_GET_SEGMENT (fixp->fx_subsy));
6495
6496 diff_value = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
6497 - S_GET_VALUE (fixp->fx_subsy));
6498
6499 /* Check for overflow. */
6500 if ((diff_value & ~diff_mask) != 0)
6501 {
6502 as_bad_where (fixp->fx_file, fixp->fx_line,
6503 _("value of %ld too large"), diff_value);
6504 free (reloc->sym_ptr_ptr);
6505 free (reloc);
6506 return NULL;
6507 }
6508
6509 md_number_to_chars (fixp->fx_frag->fr_literal + fixp->fx_where,
6510 diff_value, diff_size);
6511 reloc->addend = fixp->fx_offset - diff_value;
6512 }
6513 else
6514 {
6515 reloc->addend = fixp->fx_offset;
6516
6517 switch (fixp->fx_r_type)
6518 {
6519 case BFD_RELOC_XTENSA_SLOT0_OP:
6520 case BFD_RELOC_XTENSA_SLOT1_OP:
6521 case BFD_RELOC_XTENSA_SLOT2_OP:
6522 case BFD_RELOC_XTENSA_SLOT3_OP:
6523 case BFD_RELOC_XTENSA_SLOT4_OP:
6524 case BFD_RELOC_XTENSA_SLOT5_OP:
6525 case BFD_RELOC_XTENSA_SLOT6_OP:
6526 case BFD_RELOC_XTENSA_SLOT7_OP:
6527 case BFD_RELOC_XTENSA_SLOT8_OP:
6528 case BFD_RELOC_XTENSA_SLOT9_OP:
6529 case BFD_RELOC_XTENSA_SLOT10_OP:
6530 case BFD_RELOC_XTENSA_SLOT11_OP:
6531 case BFD_RELOC_XTENSA_SLOT12_OP:
6532 case BFD_RELOC_XTENSA_SLOT13_OP:
6533 case BFD_RELOC_XTENSA_SLOT14_OP:
6534 /* As a special case, the immediate value for a CONST16 opcode
6535 should not be applied, since this kind of relocation is
6536 handled specially for CONST16 and is not really PC-relative.
6537 Rather than decode the opcode here, just wait and handle it
6538 in xg_apply_tentative_value. */
6539 apply_tentative_value = TRUE;
6540 break;
6541
6542 case BFD_RELOC_XTENSA_SLOT0_ALT:
6543 case BFD_RELOC_XTENSA_SLOT1_ALT:
6544 case BFD_RELOC_XTENSA_SLOT2_ALT:
6545 case BFD_RELOC_XTENSA_SLOT3_ALT:
6546 case BFD_RELOC_XTENSA_SLOT4_ALT:
6547 case BFD_RELOC_XTENSA_SLOT5_ALT:
6548 case BFD_RELOC_XTENSA_SLOT6_ALT:
6549 case BFD_RELOC_XTENSA_SLOT7_ALT:
6550 case BFD_RELOC_XTENSA_SLOT8_ALT:
6551 case BFD_RELOC_XTENSA_SLOT9_ALT:
6552 case BFD_RELOC_XTENSA_SLOT10_ALT:
6553 case BFD_RELOC_XTENSA_SLOT11_ALT:
6554 case BFD_RELOC_XTENSA_SLOT12_ALT:
6555 case BFD_RELOC_XTENSA_SLOT13_ALT:
6556 case BFD_RELOC_XTENSA_SLOT14_ALT:
6557 case BFD_RELOC_XTENSA_ASM_EXPAND:
6558 case BFD_RELOC_32:
6559 case BFD_RELOC_XTENSA_PLT:
6560 case BFD_RELOC_VTABLE_INHERIT:
6561 case BFD_RELOC_VTABLE_ENTRY:
6562 break;
6563
6564 case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
6565 as_warn (_("emitting simplification relocation"));
6566 break;
6567
6568 default:
6569 as_warn (_("emitting unknown relocation"));
6570 }
6571 }
6572
e0001a05
NC		 6573 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
6574 if (reloc->howto == NULL)
6575 {
6576 as_bad_where (fixp->fx_file, fixp->fx_line,
6577 _("cannot represent `%s' relocation in object file"),
6578 bfd_get_reloc_code_name (fixp->fx_r_type));
43cd72b9
BW		 6579 free (reloc->sym_ptr_ptr);
6580 free (reloc);
e0001a05
NC		 6581 return NULL;
6582 }
6583
6584 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
43cd72b9
BW		 6585 as_fatal (_("internal error? cannot generate `%s' relocation"),
6586 bfd_get_reloc_code_name (fixp->fx_r_type));
e0001a05 6587
43cd72b9
BW		 6588 /* Write the tentative value of a PC-relative relocation to a local symbol
6589 into the instruction. The value will be ignored by the linker, and it
6590 makes the object file disassembly readable when the linkrelax flag is
6591 set and all branch targets are encoded in relocations. */
e0001a05 6592
43cd72b9 6593 if (linkrelax && apply_tentative_value && fixp->fx_pcrel)
e0001a05 6594 {
43cd72b9
BW		 6595 valueT val;
6596 assert (fixp->fx_addsy);
6597 if (S_GET_SEGMENT (fixp->fx_addsy) == section && !fixp->fx_plt
6598 && !S_FORCE_RELOC (fixp->fx_addsy, 1))
6599 {
6600 val = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
6601 - md_pcrel_from (fixp));
6602 xg_apply_tentative_value (fixp, val);
6603 }
e0001a05
NC		 6604 }
6605
6606 return reloc;
6607}
6608
43cd72b9
BW		 6609
6610/* md_post_relax_hook */
6611
6612#define XTENSA_INSN_SEC_NAME ".xt.insn"
6613#define XTENSA_LIT_SEC_NAME ".xt.lit"
6614#define XTENSA_PROP_SEC_NAME ".xt.prop"
6615
e0001a05 6616void
43cd72b9 6617xtensa_post_relax_hook ()
e0001a05 6618{
43cd72b9
BW		 6619 xtensa_move_seg_list_to_beginning (literal_head);
6620 xtensa_move_seg_list_to_beginning (init_literal_head);
6621 xtensa_move_seg_list_to_beginning (fini_literal_head);
e0001a05 6622
43cd72b9 6623 xtensa_find_unmarked_state_frags ();
e0001a05 6624
43cd72b9
BW		 6625 if (use_literal_section)
6626 xtensa_create_property_segments (get_frag_is_literal,
6627 NULL,
6628 XTENSA_LIT_SEC_NAME,
6629 xt_literal_sec);
6630 xtensa_create_xproperty_segments (get_frag_property_flags,
6631 XTENSA_PROP_SEC_NAME,
6632 xt_prop_sec);
e0001a05 6633
43cd72b9
BW		 6634 if (warn_unaligned_branch_targets)
6635 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
6636 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
e0001a05
NC		 6637}
6638
6639
43cd72b9
BW		 6640/* We have reached the end of a bundle; emit into the frag. */
6641
e0001a05 6642static void
43cd72b9
BW		 6643finish_vinsn (vinsn)
6644 vliw_insn *vinsn;
e0001a05 6645{
43cd72b9
BW		 6646 IStack slotstack;
6647 int i;
6648 char *file_name;
6649 int line;
e0001a05 6650
43cd72b9
BW		 6651 if (find_vinsn_conflicts (vinsn))
6652 return;
6653
6654 /* First, find a format that works. */
6655 if (vinsn->format == XTENSA_UNDEFINED)
6656 vinsn->format = xg_find_narrowest_format (vinsn);
6657
6658 if (vinsn->format == XTENSA_UNDEFINED)
6659 {
6660 as_where (&file_name, &line);
6661 as_bad_where (file_name, line,
6662 _("couldn't find a valid instruction format"));
6663 fprintf (stderr, _(" ops were: "));
6664 for (i = 0; i < vinsn->num_slots; i++)
6665 fprintf (stderr, _(" %s;"),
6666 xtensa_opcode_name (xtensa_default_isa,
6667 vinsn->slots[i].opcode));
6668 fprintf (stderr, _("\n"));
6669 xg_clear_vinsn (vinsn);
6670 return;
6671 }
6672
6673 if (vinsn->num_slots
6674 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
e0001a05 6675 {
43cd72b9
BW		 6676 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6677 xtensa_format_name (xtensa_default_isa, vinsn->format),
6678 xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6679 vinsn->num_slots);
6680 xg_clear_vinsn (vinsn);
6681 return;
6682 }
e0001a05 6683
43cd72b9
BW		 6684 if (resources_conflict (vinsn))
6685 {
6686 as_where (&file_name, &line);
6687 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6688 fprintf (stderr, " ops were: ");
6689 for (i = 0; i < vinsn->num_slots; i++)
6690 fprintf (stderr, " %s;",
6691 xtensa_opcode_name (xtensa_default_isa,
6692 vinsn->slots[i].opcode));
6693 fprintf (stderr, "\n");
6694 xg_clear_vinsn (vinsn);
6695 return;
6696 }
6697
6698 for (i = 0; i < vinsn->num_slots; i++)
6699 {
6700 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
e0001a05 6701 {
43cd72b9
BW		 6702 symbolS *lit_sym = NULL;
6703 int j;
6704 bfd_boolean e = FALSE;
6705 bfd_boolean saved_density = density_supported;
6706
6707 /* We don't want to narrow ops inside multi-slot bundles. */
6708 if (vinsn->num_slots > 1)
6709 density_supported = FALSE;
6710
6711 istack_init (&slotstack);
6712 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
e0001a05 6713 {
43cd72b9
BW		 6714 vinsn->slots[i].opcode =
6715 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6716 vinsn->format, i);
6717 vinsn->slots[i].ntok = 0;
6718 }
e0001a05 6719
43cd72b9
BW		 6720 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6721 {
6722 e = TRUE;
6723 continue;
e0001a05 6724 }
e0001a05 6725
43cd72b9 6726 density_supported = saved_density;
e0001a05 6727
43cd72b9
BW		 6728 if (e)
6729 {
6730 xg_clear_vinsn (vinsn);
6731 return;
6732 }
e0001a05 6733
43cd72b9
BW		 6734 for (j = 0; j < slotstack.ninsn - 1; j++)
6735 {
6736 TInsn *insn = &slotstack.insn[j];
6737 if (insn->insn_type == ITYPE_LITERAL)
6738 {
6739 assert (lit_sym == NULL);
6740 lit_sym = xg_assemble_literal (insn);
6741 }
6742 else
6743 {
6744 if (lit_sym)
6745 xg_resolve_literals (insn, lit_sym);
6746 emit_single_op (insn);
6747 }
6748 }
6749
6750 if (vinsn->num_slots > 1)
6751 {
6752 if (opcode_fits_format_slot
6753 (slotstack.insn[slotstack.ninsn - 1].opcode,
6754 vinsn->format, i))
6755 {
6756 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6757 }
6758 else
6759 {
6760 bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6761 if (vinsn->format == XTENSA_UNDEFINED)
6762 vinsn->slots[i].opcode = xtensa_nop_opcode;
6763 else
6764 vinsn->slots[i].opcode
6765 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6766 vinsn->format, i);
6767
6768 vinsn->slots[i].ntok = 0;
6769 }
6770 }
6771 else
6772 {
6773 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6774 vinsn->format = XTENSA_UNDEFINED;
6775 }
6776 }
6777 }
6778
6779 /* Now check resource conflicts on the modified bundle. */
6780 if (resources_conflict (vinsn))
6781 {
6782 as_where (&file_name, &line);
6783 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6784 fprintf (stderr, " ops were: ");
6785 for (i = 0; i < vinsn->num_slots; i++)
6786 fprintf (stderr, " %s;",
6787 xtensa_opcode_name (xtensa_default_isa,
6788 vinsn->slots[i].opcode));
6789 fprintf (stderr, "\n");
6790 xg_clear_vinsn (vinsn);
6791 return;
6792 }
6793
6794 /* First, find a format that works. */
6795 if (vinsn->format == XTENSA_UNDEFINED)
6796 vinsn->format = xg_find_narrowest_format (vinsn);
6797
6798 xg_assemble_vliw_tokens (vinsn);
6799
6800 xg_clear_vinsn (vinsn);
6801}
6802
6803
6804/* Given an vliw instruction, what conflicts are there in register
6805 usage and in writes to states and queues?
6806
6807 This function does two things:
6808 1. Reports an error when a vinsn contains illegal combinations
6809 of writes to registers states or queues.
6810 2. Marks individual tinsns as not relaxable if the combination
6811 contains antidependencies.
6812
6813 Job 2 handles things like swap semantics in instructions that need
6814 to be relaxed. For example,
6815
6816 addi a0, a1, 100000
6817
6818 normally would be relaxed to
6819
6820 l32r a0, some_label
6821 add a0, a1, a0
6822
6823 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6824
6825 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6826
6827 then we can't relax it into
6828
6829 l32r a0, some_label
6830 { add a0, a1, a0 ; add a2, a0, a4 ; }
6831
6832 because the value of a0 is trashed before the second add can read it. */
6833
6834static bfd_boolean
6835find_vinsn_conflicts (vinsn)
6836 vliw_insn *vinsn;
6837{
6838 int i, j;
6839 int branches = 0;
6840 xtensa_isa isa = xtensa_default_isa;
6841
6842 assert (!past_xtensa_end);
6843
6844 for (i = 0 ; i < vinsn->num_slots; i++)
6845 {
6846 TInsn *op1 = &vinsn->slots[i];
6847 if (op1->is_specific_opcode)
6848 op1->keep_wide = TRUE;
6849 else
6850 op1->keep_wide = FALSE;
6851 }
6852
6853 for (i = 0 ; i < vinsn->num_slots; i++)
6854 {
6855 TInsn *op1 = &vinsn->slots[i];
6856
6857 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6858 branches++;
6859
6860 for (j = 0; j < vinsn->num_slots; j++)
6861 {
6862 if (i != j)
6863 {
6864 TInsn *op2 = &vinsn->slots[j];
6865 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6866 switch (conflict_type)
6867 {
6868 case 'c':
6869 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6870 xtensa_opcode_name (isa, op1->opcode), i,
6871 xtensa_opcode_name (isa, op2->opcode), j);
6872 return TRUE;
6873 case 'd':
6874 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6875 xtensa_opcode_name (isa, op1->opcode), i,
6876 xtensa_opcode_name (isa, op2->opcode), j);
6877 return TRUE;
6878 case 'e':
6879 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6880 xtensa_opcode_name (isa, op1->opcode), i,
6881 xtensa_opcode_name (isa, op2->opcode), j);
6882 return TRUE;
6883 case 'f':
6884 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6885 xtensa_opcode_name (isa, op1->opcode), i,
6886 xtensa_opcode_name (isa, op2->opcode), j);
6887 return TRUE;
6888 default:
6889 /* Everything is OK. */
6890 break;
6891 }
6892 op2->is_specific_opcode = (op2->is_specific_opcode
6893 || conflict_type == 'a');
6894 }
6895 }
6896 }
6897
6898 if (branches > 1)
6899 {
6900 as_bad (_("multiple branches or jumps in the same bundle"));
6901 return TRUE;
6902 }
6903
6904 return FALSE;
6905}
6906
6907
6908/* Check how the result registers of t1 and t2 relate.
6909 Cases found are:
6910
6911 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6912 case B: no relationship between what is read and written (both could
6913 read the same reg though)
6914 case C: t1 writes a register t2 writes (a register conflict within a
6915 bundle)
6916 case D: t1 writes a state that t2 also writes
6917 case E: t1 writes a tie queue that t2 also writes
6918 case F: two volatile queue writes
6919*/
6920
6921static char
6922check_t1_t2_reads_and_writes (t1, t2)
6923 TInsn *t1;
6924 TInsn *t2;
6925{
6926 xtensa_isa isa = xtensa_default_isa;
6927 xtensa_regfile t1_regfile, t2_regfile;
6928 int t1_reg, t2_reg;
6929 int t1_base_reg, t1_last_reg;
6930 int t2_base_reg, t2_last_reg;
6931 char t1_inout, t2_inout;
6932 int i, j;
6933 char conflict = 'b';
6934 int t1_states;
6935 int t2_states;
6936 int t1_interfaces;
6937 int t2_interfaces;
6938 bfd_boolean t1_volatile = FALSE;
6939 bfd_boolean t2_volatile = FALSE;
6940
6941 /* Check registers. */
6942 for (j = 0; j < t2->ntok; j++)
6943 {
6944 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6945 continue;
6946
6947 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6948 t2_base_reg = t2->tok[j].X_add_number;
6949 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6950
6951 for (i = 0; i < t1->ntok; i++)
6952 {
6953 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6954 continue;
6955
6956 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6957
6958 if (t1_regfile != t2_regfile)
6959 continue;
6960
6961 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6962 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6963
6964 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6965 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6966 {
6967 if (t1_inout == 'm' || t1_inout == 'o'
6968 || t2_inout == 'm' || t2_inout == 'o')
6969 {
6970 conflict = 'a';
6971 continue;
6972 }
6973 }
6974
6975 t1_base_reg = t1->tok[i].X_add_number;
6976 t1_last_reg = (t1_base_reg
6977 + xtensa_operand_num_regs (isa, t1->opcode, i));
6978
6979 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6980 {
6981 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6982 {
6983 if (t1_reg != t2_reg)
6984 continue;
6985
6986 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6987 {
6988 conflict = 'a';
6989 continue;
6990 }
6991
6992 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6993 {
6994 conflict = 'a';
6995 continue;
6996 }
6997
6998 if (t1_inout != 'i' && t2_inout != 'i')
6999 return 'c';
7000 }
7001 }
7002 }
7003 }
7004
7005 /* Check states. */
7006 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
7007 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
7008 for (j = 0; j < t2_states; j++)
7009 {
7010 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
7011 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
7012 for (i = 0; i < t1_states; i++)
7013 {
7014 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
7015 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
7016 if (t1_so != t2_so)
7017 continue;
7018
7019 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
7020 {
7021 conflict = 'a';
7022 continue;
7023 }
7024
7025 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
7026 {
7027 conflict = 'a';
7028 continue;
7029 }
7030
7031 if (t1_inout != 'i' && t2_inout != 'i')
7032 return 'd';
7033 }
7034 }
7035
7036 /* Check tieports. */
7037 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
7038 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
7039 for (j = 0; j < t2_interfaces; j++)
7040 {
7041 xtensa_interface t2_int
7042 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
7043 t2_inout = xtensa_interface_inout (isa, j);
7044 if (xtensa_interface_has_side_effect (isa, t2_int) == 1
7045 && t2_inout != 'i')
7046 t2_volatile = TRUE;
7047 for (i = 0; i < t1_interfaces; i++)
7048 {
7049 xtensa_interface t1_int
7050 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
7051 t1_inout = xtensa_interface_inout (isa, i);
7052 if (xtensa_interface_has_side_effect (isa, t1_int) == 1
7053 && t1_inout != 'i')
7054 t1_volatile = TRUE;
7055
7056 if (t1_int != t2_int)
7057 continue;
7058
7059 if (t2_inout == 'i' && t1_inout == 'o')
7060 {
7061 conflict = 'a';
7062 continue;
7063 }
7064
7065 if (t1_inout == 'i' && t2_inout == 'o')
7066 {
7067 conflict = 'a';
7068 continue;
7069 }
7070
7071 if (t1_inout != 'i' && t2_inout != 'i')
7072 return 'e';
7073 }
7074 }
7075
7076 if (t1_volatile && t2_volatile)
7077 return 'f';
7078
7079 return conflict;
7080}
7081
7082
7083/* The func unit stuff could be implemented as bit-vectors rather
7084 than the iterative approach here. If it ends up being too
7085 slow, we will switch it. */
7086
7087resource_table *
7088new_resource_table (data, cycles, nu, uncf, onuf, ouuf, ousf)
7089 void *data;
7090 int cycles;
7091 int nu;
7092 unit_num_copies_func uncf;
7093 opcode_num_units_func onuf;
7094 opcode_funcUnit_use_unit_func ouuf;
7095 opcode_funcUnit_use_stage_func ousf;
7096{
7097 int i;
7098 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
7099 rt->data = data;
7100 rt->cycles = cycles;
7101 rt->allocated_cycles = cycles;
7102 rt->num_units = nu;
7103 rt->unit_num_copies = uncf;
7104 rt->opcode_num_units = onuf;
7105 rt->opcode_unit_use = ouuf;
7106 rt->opcode_unit_stage = ousf;
7107
7108 rt->units = (char **) xcalloc (cycles, sizeof (char *));
7109 for (i = 0; i < cycles; i++)
7110 rt->units[i] = (char *) xcalloc (nu, sizeof (char));
7111
7112 return rt;
7113}
7114
7115
7116void
7117clear_resource_table (rt)
7118 resource_table *rt;
7119{
7120 int i, j;
7121 for (i = 0; i < rt->allocated_cycles; i++)
7122 for (j = 0; j < rt->num_units; j++)
7123 rt->units[i][j] = 0;
7124}
7125
7126
7127/* We never shrink it, just fake it into thinking so. */
7128
7129void
7130resize_resource_table (rt, cycles)
7131 resource_table *rt;
7132 int cycles;
7133{
7134 int i, old_cycles;
7135
7136 rt->cycles = cycles;
7137 if (cycles <= rt->allocated_cycles)
7138 return;
7139
7140 old_cycles = rt->allocated_cycles;
7141 rt->allocated_cycles = cycles;
7142
7143 rt->units = xrealloc (rt->units, sizeof (char *) * rt->allocated_cycles);
7144 for (i = 0; i < old_cycles; i++)
7145 rt->units[i] = xrealloc (rt->units[i], sizeof (char) * rt->num_units);
7146 for (i = old_cycles; i < cycles; i++)
7147 rt->units[i] = xcalloc (rt->num_units, sizeof (char));
7148}
7149
7150
7151bfd_boolean
7152resources_available (rt, opcode, cycle)
7153 resource_table *rt;
7154 xtensa_opcode opcode;
7155 int cycle;
7156{
7157 int i;
7158 int uses = (rt->opcode_num_units) (rt->data, opcode);
7159
7160 for (i = 0; i < uses; i++)
7161 {
7162 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
7163 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
7164 int copies_in_use = rt->units[stage + cycle][unit];
7165 int copies = (rt->unit_num_copies) (rt->data, unit);
7166 if (copies_in_use >= copies)
7167 return FALSE;
7168 }
7169 return TRUE;
7170}
7171
7172
7173void
7174reserve_resources (rt, opcode, cycle)
7175 resource_table *rt;
7176 xtensa_opcode opcode;
7177 int cycle;
7178{
7179 int i;
7180 int uses = (rt->opcode_num_units) (rt->data, opcode);
7181
7182 for (i = 0; i < uses; i++)
7183 {
7184 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
7185 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
7186 /* Note that this allows resources to be oversubscribed. That's
7187 essential to the way the optional scheduler works.
7188 resources_available reports when a resource is over-subscribed,
7189 so it's easy to tell. */
7190 rt->units[stage + cycle][unit]++;
7191 }
7192}
7193
7194
7195void
7196release_resources (rt, opcode, cycle)
7197 resource_table *rt;
7198 xtensa_opcode opcode;
7199 int cycle;
7200{
7201 int i;
7202 int uses = (rt->opcode_num_units) (rt->data, opcode);
7203
7204 for (i = 0; i < uses; i++)
7205 {
7206 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
7207 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
7208 rt->units[stage + cycle][unit]--;
7209 assert (rt->units[stage + cycle][unit] >= 0);
7210 }
7211}
7212
7213
7214/* Wrapper functions make parameterized resource reservation
7215 more convenient. */
7216
7217int
7218opcode_funcUnit_use_unit (data, opcode, idx)
7219 void *data;
7220 xtensa_opcode opcode;
7221 int idx;
7222{
7223 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
7224 return use->unit;
7225}
7226
7227
7228int
7229opcode_funcUnit_use_stage (data, opcode, idx)
7230 void *data;
7231 xtensa_opcode opcode;
7232 int idx;
7233{
7234 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
7235 return use->stage;
7236}
7237
7238
7239/* Note that this function does not check issue constraints, but
7240 solely whether the hardware is available to execute the given
7241 instructions together. It also doesn't check if the tinsns
7242 write the same state, or access the same tieports. That is
7243 checked by check_t1_t2_read_write. */
7244
7245static bfd_boolean
7246resources_conflict (vinsn)
7247 vliw_insn *vinsn;
7248{
7249 int i;
7250 static resource_table *rt = NULL;
7251
7252 /* This is the most common case by far. Optimize it. */
7253 if (vinsn->num_slots == 1)
7254 return FALSE;
7255
7256 if (rt == NULL)
7257 {
7258 xtensa_isa isa = xtensa_default_isa;
7259 rt = new_resource_table
7260 (isa, xtensa_isa_num_pipe_stages (isa),
7261 xtensa_isa_num_funcUnits (isa),
7262 (unit_num_copies_func) xtensa_funcUnit_num_copies,
7263 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
7264 opcode_funcUnit_use_unit,
7265 opcode_funcUnit_use_stage);
7266 }
7267
7268 clear_resource_table (rt);
7269
7270 for (i = 0; i < vinsn->num_slots; i++)
7271 {
7272 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
7273 return TRUE;
7274 reserve_resources (rt, vinsn->slots[i].opcode, 0);
7275 }
7276
7277 return FALSE;
7278}
7279
7280
7281static xtensa_format
7282xg_find_narrowest_format (vinsn)
7283 vliw_insn *vinsn;
7284{
7285 /* Right now we assume that the ops within the vinsn are properly
7286 ordered for the slots that the programmer wanted them in. In
7287 other words, we don't rearrange the ops in hopes of finding a
7288 better format. The scheduler handles that. */
7289
7290 xtensa_isa isa = xtensa_default_isa;
7291 xtensa_format format;
7292 vliw_insn v_copy = *vinsn;
7293 xtensa_opcode nop_opcode = xtensa_nop_opcode;
7294
7295 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
7296 {
7297 v_copy = *vinsn;
7298 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
7299 {
7300 int slot;
7301 int fit = 0;
7302 for (slot = 0; slot < v_copy.num_slots; slot++)
7303 {
7304 if (v_copy.slots[slot].opcode == nop_opcode)
7305 {
7306 v_copy.slots[slot].opcode =
7307 xtensa_format_slot_nop_opcode (isa, format, slot);
7308 v_copy.slots[slot].ntok = 0;
7309 }
7310
7311 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
7312 format, slot))
7313 fit++;
7314 else
7315 {
7316 if (v_copy.num_slots > 1)
7317 {
7318 TInsn widened;
7319 /* Try the widened version. */
7320 if (!v_copy.slots[slot].keep_wide
7321 && !v_copy.slots[slot].is_specific_opcode
7322 && xg_is_narrow_insn (&v_copy.slots[slot])
7323 && !xg_expand_narrow (&widened, &v_copy.slots[slot])
7324 && opcode_fits_format_slot (widened.opcode,
7325 format, slot))
7326 {
7327 /* The xg_is_narrow clause requires some explanation:
7328
7329 addi can be "widened" to an addmi, which is then
7330 expanded to an addmi/addi pair if the immediate
7331 requires it, but here we must have a single widen
7332 only.
7333
7334 xg_is_narrow tells us that addi isn't really
7335 narrow. The widen_spec_list says that there are
7336 other cases. */
7337
7338 v_copy.slots[slot] = widened;
7339 fit++;
7340 }
7341 }
7342 }
7343 }
7344 if (fit == v_copy.num_slots)
7345 {
7346 *vinsn = v_copy;
7347 xtensa_format_encode (isa, format, vinsn->insnbuf);
7348 vinsn->format = format;
7349 break;
7350 }
7351 }
7352 }
7353
7354 if (format == xtensa_isa_num_formats (isa))
7355 return XTENSA_UNDEFINED;
7356
7357 return format;
7358}
7359
7360
7361/* Return the additional space needed in a frag
7362 for possible relaxations of any ops in a VLIW insn.
7363 Also fill out the relaxations that might be required of
7364 each tinsn in the vinsn. */
7365
7366static int
7367relaxation_requirements (vinsn)
7368 vliw_insn *vinsn;
7369{
7370 int extra_space = 0;
7371 int slot;
7372
7373 for (slot = 0; slot < vinsn->num_slots; slot++)
7374 {
7375 TInsn *tinsn = &vinsn->slots[slot];
7376 if (!tinsn_has_symbolic_operands (tinsn))
7377 {
7378 /* A narrow instruction could be widened later to help
7379 alignment issues. */
7380 if (xg_is_narrow_insn (tinsn)
7381 && !tinsn->is_specific_opcode
7382 && vinsn->num_slots == 1)
7383 {
7384 /* Difference in bytes between narrow and wide insns... */
7385 extra_space += 1;
7386 tinsn->subtype = RELAX_NARROW;
7387 tinsn->record_fix = TRUE;
7388 break;
7389 }
7390 else
7391 {
7392 tinsn->record_fix = FALSE;
7393 /* No extra_space needed. */
7394 }
7395 }
7396 else
7397 {
7398 if (workaround_b_j_loop_end && is_jx_opcode (tinsn->opcode)
7399 && use_transform ())
7400 {
7401 /* Add 2 of these. */
7402 extra_space += 3; /* for the nop size */
7403 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
7404 }
7405
7406 /* Need to assemble it with space for the relocation. */
7407 if (xg_is_relaxable_insn (tinsn, 0)
7408 && !tinsn->is_specific_opcode)
7409 {
7410 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
7411 int max_literal_size =
7412 xg_get_max_insn_widen_literal_size (tinsn->opcode);
7413
7414 tinsn->literal_space = max_literal_size;
7415
7416 tinsn->subtype = RELAX_IMMED;
7417 tinsn->record_fix = FALSE;
7418 extra_space += max_size;
7419 }
7420 else
7421 {
7422 tinsn->record_fix = TRUE;
7423 /* No extra space needed. */
7424 }
7425 }
7426 }
7427 return extra_space;
7428}
7429
7430
7431static void
7432bundle_single_op (orig_insn)
7433 TInsn *orig_insn;
7434{
7435 xtensa_isa isa = xtensa_default_isa;
7436 vliw_insn v;
7437 int slot;
7438
7439 xg_init_vinsn (&v);
7440 v.format = op_placement_table[orig_insn->opcode].narrowest;
7441 assert (v.format != XTENSA_UNDEFINED);
7442 v.num_slots = xtensa_format_num_slots (isa, v.format);
7443
7444 for (slot = 0;
7445 !opcode_fits_format_slot (orig_insn->opcode, v.format, slot);
7446 slot++)
7447 {
7448 v.slots[slot].opcode =
7449 xtensa_format_slot_nop_opcode (isa, v.format, slot);
7450 v.slots[slot].ntok = 0;
7451 v.slots[slot].insn_type = ITYPE_INSN;
7452 }
7453
7454 v.slots[slot] = *orig_insn;
7455 slot++;
7456
7457 for ( ; slot < v.num_slots; slot++)
7458 {
7459 v.slots[slot].opcode =
7460 xtensa_format_slot_nop_opcode (isa, v.format, slot);
7461 v.slots[slot].ntok = 0;
7462 v.slots[slot].insn_type = ITYPE_INSN;
7463 }
7464
7465 finish_vinsn (&v);
7466 xg_free_vinsn (&v);
7467}
7468
7469
7470static bfd_boolean
7471emit_single_op (orig_insn)
7472 TInsn *orig_insn;
7473{
7474 int i;
7475 IStack istack; /* put instructions into here */
7476 symbolS *lit_sym = NULL;
7477 symbolS *label_sym = NULL;
7478
7479 istack_init (&istack);
7480
7481 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
7482 Because the scheduling and bundling characteristics of movi and
7483 l32r or const16 are so different, we can do much better if we relax
7484 it prior to scheduling and bundling, rather than after. */
7485 if (is_movi_opcode (orig_insn->opcode) && !cur_vinsn.inside_bundle
7486 && (orig_insn->tok[1].X_op == O_symbol
7487 || orig_insn->tok[1].X_op == O_pltrel))
7488 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
7489 else
7490 if (xg_expand_assembly_insn (&istack, orig_insn))
7491 return TRUE;
7492
7493 for (i = 0; i < istack.ninsn; i++)
7494 {
7495 TInsn *insn = &istack.insn[i];
7496 switch (insn->insn_type)
7497 {
7498 case ITYPE_LITERAL:
7499 assert (lit_sym == NULL);
7500 lit_sym = xg_assemble_literal (insn);
7501 break;
7502 case ITYPE_LABEL:
7503 {
7504 static int relaxed_sym_idx = 0;
7505 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
7506 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
7507 colon (label);
7508 assert (label_sym == NULL);
7509 label_sym = symbol_find_or_make (label);
7510 assert (label_sym);
7511 free (label);
7512 }
7513 break;
7514 case ITYPE_INSN:
7515 if (lit_sym)
7516 xg_resolve_literals (insn, lit_sym);
7517 if (label_sym)
7518 xg_resolve_labels (insn, label_sym);
7519 bundle_single_op (insn);
7520 break;
7521 default:
7522 assert (0);
7523 break;
7524 }
7525 }
7526 return FALSE;
7527}
7528
7529
7530/* Emit a vliw instruction to the current fragment. */
7531
7532void
7533xg_assemble_vliw_tokens (vinsn)
7534 vliw_insn *vinsn;
7535{
7536 bfd_boolean finish_frag = FALSE;
7537 bfd_boolean is_jump = FALSE;
7538 bfd_boolean is_branch = FALSE;
7539 xtensa_isa isa = xtensa_default_isa;
7540 int i;
7541 int insn_size;
7542 int extra_space;
7543 char *f = NULL;
7544 int slot;
7545 struct dwarf2_line_info best_loc;
7546
7547 best_loc.line = INT_MAX;
7548
7549 if (generating_literals)
7550 {
7551 static int reported = 0;
7552 if (reported < 4)
7553 as_bad_where (frag_now->fr_file, frag_now->fr_line,
7554 _("cannot assemble into a literal fragment"));
7555 if (reported == 3)
7556 as_bad (_("..."));
7557 reported++;
7558 return;
7559 }
7560
7561 if (frag_now_fix () != 0
7562 && (!get_frag_is_insn (frag_now)
7563 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7564 || !use_transform () != get_frag_is_no_transform (frag_now)
7565 || (directive_state[directive_absolute_literals]
7566 != frag_now->tc_frag_data.use_absolute_literals)))
7567 {
7568 frag_wane (frag_now);
7569 frag_new (0);
7570 xtensa_set_frag_assembly_state (frag_now);
7571 }
7572
7573 if (workaround_a0_b_retw
7574 && vinsn->num_slots == 1
7575 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
7576 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
7577 && use_transform ())
7578 {
7579 has_a0_b_retw = TRUE;
7580
7581 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7582 After the first assembly pass we will check all of them and
7583 add a nop if needed. */
7584 frag_now->tc_frag_data.is_insn = TRUE;
7585 frag_var (rs_machine_dependent, 4, 4,
7586 RELAX_ADD_NOP_IF_A0_B_RETW,
7587 frag_now->fr_symbol,
7588 frag_now->fr_offset,
7589 NULL);
7590 xtensa_set_frag_assembly_state (frag_now);
7591 frag_now->tc_frag_data.is_insn = TRUE;
7592 frag_var (rs_machine_dependent, 4, 4,
7593 RELAX_ADD_NOP_IF_A0_B_RETW,
7594 frag_now->fr_symbol,
7595 frag_now->fr_offset,
7596 NULL);
7597 xtensa_set_frag_assembly_state (frag_now);
7598 }
7599
7600 for (i = 0; i < vinsn->num_slots; i++)
7601 {
7602 /* See if the instruction implies an aligned section. */
7603 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
7604 record_alignment (now_seg, 2);
7605
7606 /* Also determine the best line number for debug info. */
7607 best_loc = vinsn->slots[i].loc.line < best_loc.line
7608 ? vinsn->slots[i].loc : best_loc;
7609 }
7610
7611 /* Special cases for instructions that force an alignment... */
7612 /* None of these opcodes are bundle-able. */
7613 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
7614 {
7615 size_t max_fill;
7616
7617 xtensa_set_frag_assembly_state (frag_now);
7618 frag_now->tc_frag_data.is_insn = TRUE;
7619
7620 max_fill = get_text_align_max_fill_size
7621 (get_text_align_power (xtensa_fetch_width),
7622 TRUE, frag_now->tc_frag_data.is_no_density);
7623
7624 if (use_transform ())
7625 frag_var (rs_machine_dependent, max_fill, max_fill,
7626 RELAX_ALIGN_NEXT_OPCODE,
7627 frag_now->fr_symbol,
7628 frag_now->fr_offset,
7629 NULL);
7630 else
7631 frag_var (rs_machine_dependent, 0, 0,
7632 RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
7633 xtensa_set_frag_assembly_state (frag_now);
7634
7635 xtensa_move_labels (frag_now, 0, FALSE);
7636 }
7637
7638 if (is_entry_opcode (vinsn->slots[0].opcode)
7639 && !vinsn->slots[0].is_specific_opcode)
7640 {
7641 xtensa_mark_literal_pool_location ();
7642 xtensa_move_labels (frag_now, 0, TRUE);
7643 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
7644 }
7645
7646 if (vinsn->num_slots == 1)
7647 {
7648 if (workaround_a0_b_retw && use_transform ())
7649 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
7650 is_register_writer (&vinsn->slots[0], "a", 0));
7651
7652 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
7653 is_bad_loopend_opcode (&vinsn->slots[0]));
7654 }
7655 else
7656 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
7657
7658 insn_size = xtensa_format_length (isa, vinsn->format);
7659
7660 extra_space = relaxation_requirements (vinsn);
7661
7662 /* vinsn_to_insnbuf will produce the error. */
7663 if (vinsn->format != XTENSA_UNDEFINED)
7664 {
7665 f = (char *) frag_more (insn_size + extra_space);
7666 xtensa_set_frag_assembly_state (frag_now);
7667 frag_now->tc_frag_data.is_insn = TRUE;
7668 }
7669
7670 vinsn_to_insnbuf (vinsn, f, frag_now, TRUE);
7671 if (vinsn->format == XTENSA_UNDEFINED)
7672 return;
7673
7674 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, f, 0);
7675
7676 xtensa_dwarf2_emit_insn (insn_size - extra_space, &best_loc);
7677
7678 for (slot = 0; slot < vinsn->num_slots; slot++)
7679 {
7680 TInsn *tinsn = &vinsn->slots[slot];
7681 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7682 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7683 frag_now->tc_frag_data.slot_sub_symbols[slot] = tinsn->sub_symbol;
7684 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
7685 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7686 if (tinsn->literal_space != 0)
7687 xg_assemble_literal_space (tinsn->literal_space, slot);
7688
7689 if (tinsn->subtype == RELAX_NARROW)
7690 assert (vinsn->num_slots == 1);
7691 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7692 is_jump = TRUE;
7693 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7694 is_branch = TRUE;
7695
7696 if (tinsn->subtype || tinsn->symbol || tinsn->record_fix
7697 || tinsn->offset || tinsn->literal_frag || is_jump || is_branch)
7698 finish_frag = TRUE;
7699 }
7700
7701 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7702 set_frag_is_specific_opcode (frag_now, TRUE);
7703
7704 if (finish_frag)
7705 {
7706 frag_variant (rs_machine_dependent,
7707 extra_space, extra_space, RELAX_SLOTS,
7708 frag_now->fr_symbol, frag_now->fr_offset, f);
7709 xtensa_set_frag_assembly_state (frag_now);
7710 }
7711
7712 /* Special cases for loops:
7713 close_loop_end should be inserted AFTER short_loop.
7714 Make sure that CLOSE loops are processed BEFORE short_loops
7715 when converting them. */
7716
7717 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7718 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
7719 && !vinsn->slots[0].is_specific_opcode)
7720 {
7721 if (workaround_short_loop && use_transform ())
7722 {
7723 maybe_has_short_loop = TRUE;
7724 frag_now->tc_frag_data.is_insn = TRUE;
7725 frag_var (rs_machine_dependent, 4, 4,
7726 RELAX_ADD_NOP_IF_SHORT_LOOP,
7727 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7728 frag_now->tc_frag_data.is_insn = TRUE;
7729 frag_var (rs_machine_dependent, 4, 4,
7730 RELAX_ADD_NOP_IF_SHORT_LOOP,
7731 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7732 }
7733
7734 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7735 loop at least 12 bytes away from another loop's end. */
7736 if (workaround_close_loop_end && use_transform ())
7737 {
7738 maybe_has_close_loop_end = TRUE;
7739 frag_now->tc_frag_data.is_insn = TRUE;
7740 frag_var (rs_machine_dependent, 12, 12,
7741 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7742 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7743 }
7744 }
7745
7746 if (use_transform ())
7747 {
7748 if (is_jump)
7749 {
7750 assert (finish_frag);
7751 frag_var (rs_machine_dependent,
7752 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7753 RELAX_UNREACHABLE,
7754 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7755 xtensa_set_frag_assembly_state (frag_now);
7756 }
7757 else if (is_branch && align_targets)
7758 {
7759 assert (finish_frag);
7760 frag_var (rs_machine_dependent,
7761 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7762 RELAX_MAYBE_UNREACHABLE,
7763 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7764 xtensa_set_frag_assembly_state (frag_now);
7765 frag_var (rs_machine_dependent,
7766 0, 0,
7767 RELAX_MAYBE_DESIRE_ALIGN,
7768 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7769 xtensa_set_frag_assembly_state (frag_now);
7770 }
7771 }
7772
7773 /* Now, if the original opcode was a call... */
7774 if (do_align_targets ()
7775 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7776 {
7777 float freq = get_subseg_info (now_seg, now_subseg)->cur_total_freq;
7778 frag_now->tc_frag_data.is_insn = TRUE;
7779 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7780 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7781 xtensa_set_frag_assembly_state (frag_now);
7782 }
7783
7784 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7785 {
7786 frag_wane (frag_now);
7787 frag_new (0);
7788 xtensa_set_frag_assembly_state (frag_now);
7789 }
7790}
7791
7792\f
7793void
7794xtensa_end ()
7795{
7796 directive_balance ();
7797 xtensa_flush_pending_output ();
7798
7799 past_xtensa_end = TRUE;
7800
7801 xtensa_move_literals ();
7802
7803 xtensa_reorder_segments ();
7804 xtensa_cleanup_align_frags ();
7805 xtensa_fix_target_frags ();
7806 if (workaround_a0_b_retw && has_a0_b_retw)
7807 xtensa_fix_a0_b_retw_frags ();
7808 if (workaround_b_j_loop_end)
7809 xtensa_fix_b_j_loop_end_frags ();
7810
7811 /* "close_loop_end" should be processed BEFORE "short_loop". */
7812 if (workaround_close_loop_end && maybe_has_close_loop_end)
7813 xtensa_fix_close_loop_end_frags ();
7814
7815 if (workaround_short_loop && maybe_has_short_loop)
7816 xtensa_fix_short_loop_frags ();
7817 xtensa_mark_narrow_branches ();
7818 xtensa_mark_zcl_first_insns ();
7819
7820 xtensa_sanity_check ();
7821}
7822
7823
7824static void
7825xtensa_cleanup_align_frags ()
7826{
7827 frchainS *frchP;
7828
7829 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7830 {
7831 fragS *fragP;
7832 /* Walk over all of the fragments in a subsection. */
7833 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7834 {
7835 if ((fragP->fr_type == rs_align
7836 || fragP->fr_type == rs_align_code
7837 || (fragP->fr_type == rs_machine_dependent
7838 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7839 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7840 && fragP->fr_fix == 0)
7841 {
7842 fragS *next = fragP->fr_next;
7843
7844 while (next
7845 && next->fr_fix == 0
7846 && next->fr_type == rs_machine_dependent
7847 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7848 {
7849 frag_wane (next);
7850 next = next->fr_next;
7851 }
7852 }
7853 /* If we don't widen branch targets, then they
7854 will be easier to align. */
7855 if (fragP->tc_frag_data.is_branch_target
7856 && fragP->fr_opcode == fragP->fr_literal
7857 && fragP->fr_type == rs_machine_dependent
7858 && fragP->fr_subtype == RELAX_SLOTS
7859 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7860 frag_wane (fragP);
7861 if (fragP->fr_type == rs_machine_dependent
7862 && fragP->fr_subtype == RELAX_UNREACHABLE)
7863 fragP->tc_frag_data.is_unreachable = TRUE;
7864 }
7865 }
7866}
7867
7868
7869/* Re-process all of the fragments looking to convert all of the
7870 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7871 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7872 If the next fragment starts with a loop target, AND the previous
7873 fragment can be expanded to negate the branch, convert this to a
7874 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7875
7876static void
7877xtensa_fix_target_frags ()
e0001a05
NC		 7878{
7879 frchainS *frchP;
7880
7881 /* When this routine is called, all of the subsections are still intact
7882 so we walk over subsections instead of sections. */
7883 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7884 {
7885 bfd_boolean prev_frag_can_negate_branch = FALSE;
7886 fragS *fragP;
7887
7888 /* Walk over all of the fragments in a subsection. */
7889 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7890 {
7891 if (fragP->fr_type == rs_machine_dependent
7892 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7893 {
7894 if (next_frag_is_loop_target (fragP))
7895 {
7896 if (prev_frag_can_negate_branch)
43cd72b9
BW		 7897 {
7898 fragP->fr_subtype = RELAX_LOOP_END;
7899 /* See the comment near the frag_var with a
7900 RELAX_DESIRE_ALIGN to see why we do this. */
7901 fragP->fr_var = RELAX_LOOP_END_BYTES;
7902 }
e0001a05
NC		 7903 else
7904 {
43cd72b9 7905 if (next_frag_is_branch_target (fragP))
e0001a05
NC		 7906 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7907 else
7908 frag_wane (fragP);
7909 }
7910 }
43cd72b9 7911 else if (next_frag_is_branch_target (fragP))
e0001a05
NC		 7912 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7913 else
7914 frag_wane (fragP);
7915 }
7916 if (fragP->fr_fix != 0)
7917 prev_frag_can_negate_branch = FALSE;
7918 if (frag_can_negate_branch (fragP))
7919 prev_frag_can_negate_branch = TRUE;
7920 }
7921 }
7922}
7923
7924
7925static bfd_boolean
7926frag_can_negate_branch (fragP)
7927 fragS *fragP;
7928{
43cd72b9
BW		 7929 xtensa_isa isa = xtensa_default_isa;
7930 vliw_insn vinsn;
7931 int slot;
7932
7933 if (fragP->fr_type != rs_machine_dependent
7934 || fragP->fr_subtype != RELAX_SLOTS)
7935 return FALSE;
7936
7937 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7938
7939 for (slot = 0; slot < xtensa_format_num_slots (isa, vinsn.format); slot++)
e0001a05 7940 {
43cd72b9
BW		 7941 if ((fragP->tc_frag_data.slot_subtypes[slot] == RELAX_IMMED)
7942 && xtensa_opcode_is_branch (isa, vinsn.slots[slot].opcode) == 1)
e0001a05
NC		 7943 return TRUE;
7944 }
43cd72b9
BW		 7945
7946 return FALSE;
7947}
7948
7949
7950static void
7951xtensa_mark_narrow_branches ()
7952{
7953 frchainS *frchP;
7954
7955 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7956 {
7957 fragS *fragP;
7958 /* Walk over all of the fragments in a subsection. */
7959 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7960 {
7961 if (fragP->fr_type == rs_machine_dependent
7962 && fragP->fr_subtype == RELAX_SLOTS
7963 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7964 {
7965 vliw_insn vinsn;
7966 const expressionS *expr;
7967 symbolS *symbolP;
7968
7969 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7970 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7971
7972 expr = &vinsn.slots[0].tok[1];
7973 symbolP = expr->X_add_symbol;
7974
7975 if (vinsn.num_slots == 1
7976 && xtensa_opcode_is_branch (xtensa_default_isa,
7977 vinsn.slots[0].opcode)
7978 && xg_get_single_size (vinsn.slots[0].opcode) == 2
7979 && is_narrow_branch_guaranteed_in_range (fragP,
7980 &vinsn.slots[0]))
7981 {
7982 fragP->fr_subtype = RELAX_SLOTS;
7983 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7984 }
7985 }
7986 }
7987 }
7988}
7989
7990
7991/* A branch is typically widened only when its target is out of
7992 range. However, we would like to widen them to align a subsequent
7993 branch target when possible.
7994
7995 Because the branch relaxation code is so convoluted, the optimal solution
7996 (combining the two cases) is difficult to get right in all circumstances.
7997 We therefore go with an "almost as good" solution, where we only
7998 use for alignment narrow branches that definitely will not expand to a
7999 jump and a branch. These functions find and mark these cases. */
8000
8001/* the range in bytes of a bnez.n and beqz.n */
8002#define MAX_IMMED6 68
8003
8004static bfd_boolean
8005is_narrow_branch_guaranteed_in_range (fragP, tinsn)
8006 fragS *fragP;
8007 TInsn *tinsn;
8008{
8009 const expressionS *expr = &tinsn->tok[1];
8010 symbolS *symbolP = expr->X_add_symbol;
8011 fragS *target_frag = symbol_get_frag (symbolP);
8012 size_t max_distance = expr->X_add_number;
8013 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
8014 if (is_branch_jmp_to_next (tinsn, fragP))
8015 return FALSE;
8016
8017 /* The branch doesn't branch over it's own frag,
8018 but over the subsequent ones. */
8019 fragP = fragP->fr_next;
8020 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
8021 {
8022 max_distance += unrelaxed_frag_max_size (fragP);
8023 fragP = fragP->fr_next;
8024 }
8025 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
8026 return TRUE;
e0001a05
NC		 8027 return FALSE;
8028}
8029
8030
43cd72b9
BW		 8031static void
8032xtensa_mark_zcl_first_insns ()
8033{
8034 frchainS *frchP;
8035
8036 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
8037 {
8038 fragS *fragP;
8039 /* Walk over all of the fragments in a subsection. */
8040 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8041 {
8042 if (fragP->fr_type == rs_machine_dependent
8043 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8044 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8045 {
8046 /* Find the loop frag. */
8047 fragS *targ_frag = next_non_empty_frag (fragP);
8048 /* Find the first insn frag. */
8049 targ_frag = next_non_empty_frag (targ_frag);
8050
8051 /* Of course, sometimes (mostly for toy test cases) a
8052 zero-cost loop instruction is the last in a section. */
8053 if (targ_frag)
8054 {
8055 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
8056 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
8057 frag_wane (fragP);
8058 }
8059 }
8060 }
8061 }
8062}
8063
8064
e0001a05
NC		 8065/* Re-process all of the fragments looking to convert all of the
8066 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8067 conditional branch or a retw/retw.n, convert this frag to one that
8068 will generate a NOP. In any case close it off with a .fill 0. */
8069
8070static void
8071xtensa_fix_a0_b_retw_frags ()
8072{
8073 frchainS *frchP;
8074
8075 /* When this routine is called, all of the subsections are still intact
8076 so we walk over subsections instead of sections. */
8077 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
8078 {
8079 fragS *fragP;
8080
8081 /* Walk over all of the fragments in a subsection. */
8082 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8083 {
8084 if (fragP->fr_type == rs_machine_dependent
8085 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
8086 {
8087 if (next_instrs_are_b_retw (fragP))
43cd72b9
BW		 8088 {
8089 if (get_frag_is_no_transform (fragP))
8090 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8091 else
8092 relax_frag_add_nop (fragP);
8093 }
8094 frag_wane (fragP);
e0001a05
NC		 8095 }
8096 }
8097 }
8098}
8099
8100
8101bfd_boolean
8102next_instrs_are_b_retw (fragP)
43cd72b9 8103 fragS *fragP;
e0001a05
NC		 8104{
8105 xtensa_opcode opcode;
43cd72b9 8106 xtensa_format fmt;
e0001a05
NC		 8107 const fragS *next_fragP = next_non_empty_frag (fragP);
8108 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 8109 static xtensa_insnbuf slotbuf = NULL;
e0001a05
NC		 8110 xtensa_isa isa = xtensa_default_isa;
8111 int offset = 0;
43cd72b9
BW		 8112 int slot;
8113 bfd_boolean branch_seen = FALSE;
e0001a05
NC		 8114
8115 if (!insnbuf)
43cd72b9
BW		 8116 {
8117 insnbuf = xtensa_insnbuf_alloc (isa);
8118 slotbuf = xtensa_insnbuf_alloc (isa);
8119 }
e0001a05
NC		 8120
8121 if (next_fragP == NULL)
8122 return FALSE;
8123
8124 /* Check for the conditional branch. */
43cd72b9
BW		 8125 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
8126 fmt = xtensa_format_decode (isa, insnbuf);
8127 if (fmt == XTENSA_UNDEFINED)
8128 return FALSE;
8129
8130 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8131 {
8132 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
8133 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
8134
8135 branch_seen = (branch_seen
8136 || xtensa_opcode_is_branch (isa, opcode) == 1);
8137 }
e0001a05 8138
43cd72b9 8139 if (!branch_seen)
e0001a05
NC		 8140 return FALSE;
8141
43cd72b9 8142 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 8143 if (offset == next_fragP->fr_fix)
8144 {
8145 next_fragP = next_non_empty_frag (next_fragP);
8146 offset = 0;
8147 }
43cd72b9 8148
e0001a05
NC		 8149 if (next_fragP == NULL)
8150 return FALSE;
8151
8152 /* Check for the retw/retw.n. */
43cd72b9
BW		 8153 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
8154 fmt = xtensa_format_decode (isa, insnbuf);
8155
8156 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8157 have no problems. */
8158 if (fmt == XTENSA_UNDEFINED
8159 || xtensa_format_num_slots (isa, fmt) != 1)
8160 return FALSE;
8161
8162 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
8163 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
e0001a05
NC		 8164
8165 if (is_windowed_return_opcode (opcode))
8166 return TRUE;
43cd72b9 8167
e0001a05
NC		 8168 return FALSE;
8169}
8170
8171
8172/* Re-process all of the fragments looking to convert all of the
8173 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8174 loop end label, convert this frag to one that will generate a NOP.
8175 In any case close it off with a .fill 0. */
8176
8177static void
8178xtensa_fix_b_j_loop_end_frags ()
8179{
8180 frchainS *frchP;
8181
8182 /* When this routine is called, all of the subsections are still intact
8183 so we walk over subsections instead of sections. */
8184 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
8185 {
8186 fragS *fragP;
8187
8188 /* Walk over all of the fragments in a subsection. */
8189 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8190 {
8191 if (fragP->fr_type == rs_machine_dependent
8192 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
8193 {
8194 if (next_instr_is_loop_end (fragP))
43cd72b9
BW		 8195 {
8196 if (get_frag_is_no_transform (fragP))
8197 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8198 else
8199 relax_frag_add_nop (fragP);
8200 }
8201 frag_wane (fragP);
e0001a05
NC		 8202 }
8203 }
8204 }
8205}
8206
8207
8208bfd_boolean
8209next_instr_is_loop_end (fragP)
8210 fragS * fragP;
8211{
8212 const fragS *next_fragP;
8213
8214 if (next_frag_is_loop_target (fragP))
8215 return FALSE;
8216
8217 next_fragP = next_non_empty_frag (fragP);
8218 if (next_fragP == NULL)
8219 return FALSE;
8220
8221 if (!next_frag_is_loop_target (next_fragP))
8222 return FALSE;
8223
8224 /* If the size is >= 3 then there is more than one instruction here.
8225 The hardware bug will not fire. */
8226 if (next_fragP->fr_fix > 3)
8227 return FALSE;
8228
8229 return TRUE;
8230}
8231
8232
8233/* Re-process all of the fragments looking to convert all of the
8234 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8235 not MY loop's loop end within 12 bytes, add enough nops here to
8236 make it at least 12 bytes away. In any case close it off with a
8237 .fill 0. */
8238
8239static void
8240xtensa_fix_close_loop_end_frags ()
8241{
8242 frchainS *frchP;
8243
8244 /* When this routine is called, all of the subsections are still intact
8245 so we walk over subsections instead of sections. */
8246 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
8247 {
8248 fragS *fragP;
8249
8250 fragS *current_target = NULL;
8251 offsetT current_offset = 0;
8252
8253 /* Walk over all of the fragments in a subsection. */
8254 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8255 {
8256 if (fragP->fr_type == rs_machine_dependent
43cd72b9
BW		 8257 && ((fragP->fr_subtype == RELAX_IMMED)
8258 || ((fragP->fr_subtype == RELAX_SLOTS)
8259 && (fragP->tc_frag_data.slot_subtypes[0]
8260 == RELAX_IMMED))))
e0001a05
NC		 8261 {
8262 /* Read it. If the instruction is a loop, get the target. */
43cd72b9
BW		 8263 TInsn t_insn;
8264 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8265 if (xtensa_opcode_is_loop (xtensa_default_isa,
8266 t_insn.opcode) == 1)
e0001a05 8267 {
e0001a05 8268 /* Get the current fragment target. */
43cd72b9 8269 if (fragP->tc_frag_data.slot_symbols[0])
e0001a05 8270 {
43cd72b9
BW		 8271 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
8272 current_target = symbol_get_frag (sym);
e0001a05
NC		 8273 current_offset = fragP->fr_offset;
8274 }
8275 }
8276 }
8277
8278 if (current_target
8279 && fragP->fr_type == rs_machine_dependent
8280 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
8281 {
8282 size_t min_bytes;
8283 size_t bytes_added = 0;
8284
8285#define REQUIRED_LOOP_DIVIDING_BYTES 12
8286 /* Max out at 12. */
8287 min_bytes = min_bytes_to_other_loop_end
8288 (fragP->fr_next, current_target, current_offset,
8289 REQUIRED_LOOP_DIVIDING_BYTES);
8290
8291 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
8292 {
43cd72b9
BW		 8293 if (get_frag_is_no_transform (fragP))
8294 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8295 else
e0001a05 8296 {
43cd72b9
BW		 8297 while (min_bytes + bytes_added
8298 < REQUIRED_LOOP_DIVIDING_BYTES)
e0001a05 8299 {
43cd72b9
BW		 8300 int length = 3;
8301
8302 if (fragP->fr_var < length)
8303 as_fatal (_("fr_var %lu < length %d"),
8304 fragP->fr_var, length);
8305 else
8306 {
8307 assemble_nop (length,
8308 fragP->fr_literal + fragP->fr_fix);
8309 fragP->fr_fix += length;
8310 fragP->fr_var -= length;
8311 }
8312 bytes_added += length;
e0001a05 8313 }
e0001a05
NC		 8314 }
8315 }
8316 frag_wane (fragP);
8317 }
43cd72b9
BW		 8318 assert (fragP->fr_type != rs_machine_dependent
8319 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
e0001a05
NC		 8320 }
8321 }
8322}
8323
8324
43cd72b9 8325static size_t
e0001a05
NC		 8326min_bytes_to_other_loop_end (fragP, current_target, current_offset, max_size)
8327 fragS *fragP;
8328 fragS *current_target;
8329 offsetT current_offset;
8330 size_t max_size;
8331{
8332 size_t offset = 0;
8333 fragS *current_fragP;
8334
8335 for (current_fragP = fragP;
8336 current_fragP;
8337 current_fragP = current_fragP->fr_next)
8338 {
8339 if (current_fragP->tc_frag_data.is_loop_target
8340 && current_fragP != current_target)
8341 return offset + current_offset;
8342
8343 offset += unrelaxed_frag_min_size (current_fragP);
8344
8345 if (offset + current_offset >= max_size)
8346 return max_size;
8347 }
8348 return max_size;
8349}
8350
8351
43cd72b9 8352static size_t
e0001a05 8353unrelaxed_frag_min_size (fragP)
43cd72b9 8354 fragS *fragP;
e0001a05
NC		 8355{
8356 size_t size = fragP->fr_fix;
8357
8358 /* add fill size */
8359 if (fragP->fr_type == rs_fill)
8360 size += fragP->fr_offset;
8361
8362 return size;
8363}
8364
8365
43cd72b9
BW		 8366static size_t
8367unrelaxed_frag_max_size (fragP)
8368 fragS *fragP;
8369{
8370 size_t size = fragP->fr_fix;
8371 switch (fragP->fr_type)
8372 {
8373 case 0:
8374 /* Empty frags created by the obstack allocation scheme
8375 end up with type 0. */
8376 break;
8377 case rs_fill:
8378 case rs_org:
8379 case rs_space:
8380 size += fragP->fr_offset;
8381 break;
8382 case rs_align:
8383 case rs_align_code:
8384 case rs_align_test:
8385 case rs_leb128:
8386 case rs_cfa:
8387 case rs_dwarf2dbg:
8388 /* No further adjustments needed. */
8389 break;
8390 case rs_machine_dependent:
8391 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
8392 size += fragP->fr_var;
8393 break;
8394 default:
8395 /* We had darn well better know how big it is. */
8396 assert (0);
8397 break;
8398 }
8399
8400 return size;
8401}
8402
8403
e0001a05
NC		 8404/* Re-process all of the fragments looking to convert all
8405 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8406
8407 A)
8408 1) the instruction size count to the loop end label
8409 is too short (<= 2 instructions),
8410 2) loop has a jump or branch in it
8411
8412 or B)
43cd72b9 8413 1) workaround_all_short_loops is TRUE
e0001a05
NC		 8414 2) The generating loop was a 'loopgtz' or 'loopnez'
8415 3) the instruction size count to the loop end label is too short
8416 (<= 2 instructions)
8417 then convert this frag (and maybe the next one) to generate a NOP.
8418 In any case close it off with a .fill 0. */
8419
8420static void
8421xtensa_fix_short_loop_frags ()
8422{
8423 frchainS *frchP;
8424
8425 /* When this routine is called, all of the subsections are still intact
8426 so we walk over subsections instead of sections. */
8427 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
8428 {
8429 fragS *fragP;
8430 fragS *current_target = NULL;
8431 offsetT current_offset = 0;
8432 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
8433
8434 /* Walk over all of the fragments in a subsection. */
8435 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8436 {
43cd72b9 8437 /* Check on the current loop. */
e0001a05 8438 if (fragP->fr_type == rs_machine_dependent
43cd72b9
BW		 8439 && ((fragP->fr_subtype == RELAX_IMMED)
8440 || ((fragP->fr_subtype == RELAX_SLOTS)
8441 && (fragP->tc_frag_data.slot_subtypes[0]
8442 == RELAX_IMMED))))
e0001a05 8443 {
43cd72b9
BW		 8444 TInsn t_insn;
8445
e0001a05 8446 /* Read it. If the instruction is a loop, get the target. */
43cd72b9
BW		 8447 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8448 if (xtensa_opcode_is_loop (xtensa_default_isa,
8449 t_insn.opcode) == 1)
e0001a05 8450 {
e0001a05 8451 /* Get the current fragment target. */
43cd72b9 8452 if (fragP->tc_frag_data.slot_symbols[0])
e0001a05 8453 {
43cd72b9
BW		 8454 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
8455 current_target = symbol_get_frag (sym);
e0001a05 8456 current_offset = fragP->fr_offset;
43cd72b9 8457 current_opcode = t_insn.opcode;
e0001a05
NC		 8458 }
8459 }
8460 }
8461
8462 if (fragP->fr_type == rs_machine_dependent
8463 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8464 {
8465 size_t insn_count =
8466 count_insns_to_loop_end (fragP->fr_next, TRUE, 3);
8467 if (insn_count < 3
8468 && (branch_before_loop_end (fragP->fr_next)
43cd72b9 8469 || (workaround_all_short_loops
e0001a05
NC		 8470 && current_opcode != XTENSA_UNDEFINED
8471 && !is_the_loop_opcode (current_opcode))))
43cd72b9
BW		 8472 {
8473 if (get_frag_is_no_transform (fragP))
8474 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8475 else
8476 relax_frag_add_nop (fragP);
8477 }
8478 frag_wane (fragP);
e0001a05
NC		 8479 }
8480 }
8481 }
8482}
8483
8484
43cd72b9 8485static size_t
e0001a05
NC		 8486count_insns_to_loop_end (base_fragP, count_relax_add, max_count)
8487 fragS *base_fragP;
8488 bfd_boolean count_relax_add;
8489 size_t max_count;
8490{
8491 fragS *fragP = NULL;
8492 size_t insn_count = 0;
8493
8494 fragP = base_fragP;
8495
8496 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
8497 {
8498 insn_count += unrelaxed_frag_min_insn_count (fragP);
8499 if (insn_count >= max_count)
8500 return max_count;
8501
8502 if (count_relax_add)
8503 {
8504 if (fragP->fr_type == rs_machine_dependent
8505 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8506 {
8507 /* In order to add the appropriate number of
8508 NOPs, we count an instruction for downstream
8509 occurrences. */
8510 insn_count++;
8511 if (insn_count >= max_count)
8512 return max_count;
8513 }
8514 }
8515 }
8516 return insn_count;
8517}
8518
8519
43cd72b9 8520static size_t
e0001a05
NC		 8521unrelaxed_frag_min_insn_count (fragP)
8522 fragS *fragP;
8523{
43cd72b9
BW		 8524 xtensa_isa isa = xtensa_default_isa;
8525 static xtensa_insnbuf insnbuf = NULL;
e0001a05
NC		 8526 size_t insn_count = 0;
8527 int offset = 0;
8528
8529 if (!fragP->tc_frag_data.is_insn)
8530 return insn_count;
8531
43cd72b9
BW		 8532 if (!insnbuf)
8533 insnbuf = xtensa_insnbuf_alloc (isa);
8534
e0001a05
NC		 8535 /* Decode the fixed instructions. */
8536 while (offset < fragP->fr_fix)
8537 {
43cd72b9
BW		 8538 xtensa_format fmt;
8539
8540 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
8541 fmt = xtensa_format_decode (isa, insnbuf);
8542
8543 if (fmt == XTENSA_UNDEFINED)
e0001a05
NC		 8544 {
8545 as_fatal (_("undecodable instruction in instruction frag"));
8546 return insn_count;
8547 }
43cd72b9 8548 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 8549 insn_count++;
8550 }
8551
8552 return insn_count;
8553}
8554
8555
43cd72b9 8556static bfd_boolean
e0001a05
NC		 8557branch_before_loop_end (base_fragP)
8558 fragS *base_fragP;
8559{
8560 fragS *fragP;
8561
8562 for (fragP = base_fragP;
8563 fragP && !fragP->tc_frag_data.is_loop_target;
8564 fragP = fragP->fr_next)
8565 {
8566 if (unrelaxed_frag_has_b_j (fragP))
8567 return TRUE;
8568 }
8569 return FALSE;
8570}
8571
8572
43cd72b9 8573static bfd_boolean
e0001a05
NC		 8574unrelaxed_frag_has_b_j (fragP)
8575 fragS *fragP;
8576{
43cd72b9
BW		 8577 static xtensa_insnbuf insnbuf = NULL;
8578 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 8579 int offset = 0;
8580
8581 if (!fragP->tc_frag_data.is_insn)
8582 return FALSE;
8583
43cd72b9
BW		 8584 if (!insnbuf)
8585 insnbuf = xtensa_insnbuf_alloc (isa);
8586
e0001a05
NC		 8587 /* Decode the fixed instructions. */
8588 while (offset < fragP->fr_fix)
8589 {
43cd72b9
BW		 8590 xtensa_format fmt;
8591 int slot;
8592
8593 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
8594 fmt = xtensa_format_decode (isa, insnbuf);
8595 if (fmt == XTENSA_UNDEFINED)
8596 return FALSE;
8597
8598 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
e0001a05 8599 {
43cd72b9
BW		 8600 xtensa_opcode opcode =
8601 get_opcode_from_buf (fragP->fr_literal + offset, slot);
8602 if (xtensa_opcode_is_branch (isa, opcode) == 1
8603 || xtensa_opcode_is_jump (isa, opcode) == 1)
8604 return TRUE;
e0001a05 8605 }
43cd72b9 8606 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 8607 }
8608 return FALSE;
8609}
8610
8611
8612/* Checks to be made after initial assembly but before relaxation. */
8613
8614static void
8615xtensa_sanity_check ()
8616{
8617 char *file_name;
8618 int line;
8619
8620 frchainS *frchP;
8621
8622 as_where (&file_name, &line);
8623 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
8624 {
8625 fragS *fragP;
8626
8627 /* Walk over all of the fragments in a subsection. */
8628 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8629 {
8630 /* Currently we only check for empty loops here. */
8631 if (fragP->fr_type == rs_machine_dependent
8632 && fragP->fr_subtype == RELAX_IMMED)
8633 {
8634 static xtensa_insnbuf insnbuf = NULL;
8635 TInsn t_insn;
8636
8637 if (fragP->fr_opcode != NULL)
8638 {
8639 if (!insnbuf)
8640 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
43cd72b9
BW		 8641 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8642 tinsn_immed_from_frag (&t_insn, fragP, 0);
e0001a05 8643
43cd72b9
BW		 8644 if (xtensa_opcode_is_loop (xtensa_default_isa,
8645 t_insn.opcode) == 1)
e0001a05
NC		 8646 {
8647 if (is_empty_loop (&t_insn, fragP))
8648 {
8649 new_logical_line (fragP->fr_file, fragP->fr_line);
8650 as_bad (_("invalid empty loop"));
8651 }
8652 if (!is_local_forward_loop (&t_insn, fragP))
8653 {
8654 new_logical_line (fragP->fr_file, fragP->fr_line);
8655 as_bad (_("loop target does not follow "
8656 "loop instruction in section"));
8657 }
8658 }
8659 }
8660 }
8661 }
8662 }
8663 new_logical_line (file_name, line);
8664}
8665
8666
8667#define LOOP_IMMED_OPN 1
8668
43cd72b9 8669/* Return TRUE if the loop target is the next non-zero fragment. */
e0001a05
NC		 8670
8671bfd_boolean
8672is_empty_loop (insn, fragP)
8673 const TInsn *insn;
8674 fragS *fragP;
8675{
8676 const expressionS *expr;
8677 symbolS *symbolP;
8678 fragS *next_fragP;
8679
8680 if (insn->insn_type != ITYPE_INSN)
8681 return FALSE;
8682
43cd72b9 8683 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
e0001a05
NC		 8684 return FALSE;
8685
8686 if (insn->ntok <= LOOP_IMMED_OPN)
8687 return FALSE;
8688
8689 expr = &insn->tok[LOOP_IMMED_OPN];
8690
8691 if (expr->X_op != O_symbol)
8692 return FALSE;
8693
8694 symbolP = expr->X_add_symbol;
8695 if (!symbolP)
8696 return FALSE;
8697
8698 if (symbol_get_frag (symbolP) == NULL)
8699 return FALSE;
8700
8701 if (S_GET_VALUE (symbolP) != 0)
8702 return FALSE;
8703
8704 /* Walk through the zero-size fragments from this one. If we find
8705 the target fragment, then this is a zero-size loop. */
43cd72b9 8706
e0001a05
NC		 8707 for (next_fragP = fragP->fr_next;
8708 next_fragP != NULL;
8709 next_fragP = next_fragP->fr_next)
8710 {
8711 if (next_fragP == symbol_get_frag (symbolP))
8712 return TRUE;
8713 if (next_fragP->fr_fix != 0)
8714 return FALSE;
8715 }
8716 return FALSE;
8717}
8718
8719
8720bfd_boolean
8721is_local_forward_loop (insn, fragP)
8722 const TInsn *insn;
8723 fragS *fragP;
8724{
8725 const expressionS *expr;
8726 symbolS *symbolP;
8727 fragS *next_fragP;
8728
8729 if (insn->insn_type != ITYPE_INSN)
8730 return FALSE;
8731
43cd72b9 8732 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
e0001a05
NC		 8733 return FALSE;
8734
8735 if (insn->ntok <= LOOP_IMMED_OPN)
8736 return FALSE;
8737
8738 expr = &insn->tok[LOOP_IMMED_OPN];
8739
8740 if (expr->X_op != O_symbol)
8741 return FALSE;
8742
8743 symbolP = expr->X_add_symbol;
8744 if (!symbolP)
8745 return FALSE;
8746
8747 if (symbol_get_frag (symbolP) == NULL)
8748 return FALSE;
8749
8750 /* Walk through fragments until we find the target.
8751 If we do not find the target, then this is an invalid loop. */
43cd72b9 8752
e0001a05
NC		 8753 for (next_fragP = fragP->fr_next;
8754 next_fragP != NULL;
8755 next_fragP = next_fragP->fr_next)
43cd72b9
BW		 8756 {
8757 if (next_fragP == symbol_get_frag (symbolP))
8758 return TRUE;
8759 }
e0001a05
NC		 8760
8761 return FALSE;
8762}
8763
8764\f
8765/* Alignment Functions. */
8766
43cd72b9 8767static size_t
e0001a05
NC		 8768get_text_align_power (target_size)
8769 int target_size;
8770{
8771 size_t i = 0;
8772 for (i = 0; i < sizeof (size_t); i++)
8773 {
8774 if (target_size <= (1 << i))
8775 return i;
8776 }
43cd72b9 8777 assert (0);
e0001a05
NC		 8778 return 0;
8779}
8780
8781
43cd72b9 8782static addressT
e0001a05
NC		 8783get_text_align_max_fill_size (align_pow, use_nops, use_no_density)
8784 int align_pow;
8785 bfd_boolean use_nops;
8786 bfd_boolean use_no_density;
8787{
8788 if (!use_nops)
8789 return (1 << align_pow);
8790 if (use_no_density)
8791 return 3 * (1 << align_pow);
8792
8793 return 1 + (1 << align_pow);
8794}
8795
8796
8797/* get_text_align_fill_size ()
43cd72b9 8798
e0001a05
NC		 8799 Desired alignments:
8800 give the address
8801 target_size = size of next instruction
8802 align_pow = get_text_align_power (target_size).
8803 use_nops = 0
8804 use_no_density = 0;
8805 Loop alignments:
8806 address = current address + loop instruction size;
8807 target_size = 3 (for 2 or 3 byte target)
43cd72b9 8808 = 4 (for 4 byte target)
e0001a05
NC		 8809 = 8 (for 8 byte target)
8810 align_pow = get_text_align_power (target_size);
8811 use_nops = 1
8812 use_no_density = set appropriately
8813 Text alignments:
8814 address = current address + loop instruction size;
8815 target_size = 0
8816 align_pow = get_text_align_power (target_size);
8817 use_nops = 0
8818 use_no_density = 0. */
8819
43cd72b9 8820static addressT
e0001a05
NC		 8821get_text_align_fill_size (address, align_pow, target_size,
8822 use_nops, use_no_density)
8823 addressT address;
8824 int align_pow;
8825 int target_size;
8826 bfd_boolean use_nops;
8827 bfd_boolean use_no_density;
8828{
8829 /* Input arguments:
8830
8831 align_pow: log2 (required alignment).
8832
8833 target_size: alignment must allow the new_address and
8834 new_address+target_size-1.
8835
43cd72b9 8836 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
e0001a05
NC		 8837
8838 use_no_density: if use_nops and use_no_density, we can only use
8839 3-byte nops.
8840
43cd72b9
BW		 8841 Usually the align_pow is the power of 2 that is greater than
8842 or equal to the target_size. This handles the 2-byte, 3-byte
8843 and 8-byte instructions.
8844
8845 Two cases:
8846
8847 (1) aligning an instruction properly, but without using NOPs.
8848 E.G.: a 3-byte instruction can go on any address where address mod 4
8849 is zero or one. The aligner uses this case to find the optimal
8850 number of fill bytes for relax_frag_for_align.
8851
8852 (2) aligning an instruction properly, but where we might need to use
8853 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8854 or similar to get the optimal location. */
e0001a05
NC		 8855
8856 size_t alignment = (1 << align_pow);
43cd72b9
BW		 8857
8858 assert (target_size != 0);
8859
e0001a05
NC		 8860 if (!use_nops)
8861 {
43cd72b9
BW		 8862 unsigned fill_bytes;
8863 for (fill_bytes = 0; fill_bytes < alignment; fill_bytes++)
8864 {
8865 addressT end_address = address + target_size - 1 + fill_bytes;
8866 addressT start_address = address + fill_bytes;
8867 if ((end_address >> align_pow) == (start_address >> align_pow))
8868 return fill_bytes;
8869 }
8870 assert (0);
e0001a05
NC		 8871 }
8872
8873 /* This is the slightly harder case. */
8874 assert ((int) alignment >= target_size);
8875 assert (target_size > 0);
8876 if (!use_no_density)
8877 {
8878 size_t i;
8879 for (i = 0; i < alignment * 2; i++)
8880 {
8881 if (i == 1)
8882 continue;
43cd72b9
BW		 8883 if ((address + i) >> align_pow
8884 == (address + i + target_size - 1) >> align_pow)
e0001a05
NC		 8885 return i;
8886 }
8887 }
8888 else
8889 {
8890 size_t i;
8891
8892 /* Can only fill multiples of 3. */
8893 for (i = 0; i <= alignment * 3; i += 3)
8894 {
43cd72b9
BW		 8895 if ((address + i) >> align_pow
8896 == (address + i + target_size - 1) >> align_pow)
e0001a05
NC		 8897 return i;
8898 }
8899 }
8900 assert (0);
8901 return 0;
8902}
8903
8904
8905/* This will assert if it is not possible. */
8906
8907size_t
8908get_text_align_nop_count (fill_size, use_no_density)
8909 size_t fill_size;
8910 bfd_boolean use_no_density;
8911{
8912 size_t count = 0;
8913 if (use_no_density)
8914 {
8915 assert (fill_size % 3 == 0);
8916 return (fill_size / 3);
8917 }
8918
8919 assert (fill_size != 1); /* Bad argument. */
8920
8921 while (fill_size > 1)
8922 {
8923 size_t insn_size = 3;
8924 if (fill_size == 2 || fill_size == 4)
8925 insn_size = 2;
8926 fill_size -= insn_size;
8927 count++;
8928 }
8929 assert (fill_size != 1); /* Bad algorithm. */
8930 return count;
8931}
8932
8933
8934size_t
8935get_text_align_nth_nop_size (fill_size, n, use_no_density)
8936 size_t fill_size;
8937 size_t n;
8938 bfd_boolean use_no_density;
8939{
8940 size_t count = 0;
8941
8942 assert (get_text_align_nop_count (fill_size, use_no_density) > n);
8943
8944 if (use_no_density)
8945 return 3;
8946
8947 while (fill_size > 1)
8948 {
8949 size_t insn_size = 3;
8950 if (fill_size == 2 || fill_size == 4)
8951 insn_size = 2;
8952 fill_size -= insn_size;
8953 count++;
8954 if (n + 1 == count)
8955 return insn_size;
8956 }
8957 assert (0);
8958 return 0;
8959}
8960
8961
8962/* For the given fragment, find the appropriate address
8963 for it to begin at if we are using NOPs to align it. */
8964
8965static addressT
8966get_noop_aligned_address (fragP, address)
8967 fragS *fragP;
8968 addressT address;
8969{
43cd72b9
BW		 8970 /* The rule is: get next fragment's FIRST instruction. Find
8971 the smallest number of bytes that need to be added to
8972 ensure that the next fragment's FIRST instruction will fit
8973 in a single word.
8974
8975 E.G., 2 bytes : 0, 1, 2 mod 4
8976 3 bytes: 0, 1 mod 4
8977
8978 If the FIRST instruction MIGHT be relaxed,
8979 assume that it will become a 3-byte instruction.
8980
8981 Note again here that LOOP instructions are not bundleable,
8982 and this relaxation only applies to LOOP opcodes. */
8983
e0001a05 8984 size_t fill_size = 0;
43cd72b9
BW		 8985 int first_insn_size;
8986 int loop_insn_size;
8987 addressT pre_opcode_bytes;
8988 size_t alignment;
8989 fragS *first_insn;
8990 xtensa_opcode opcode;
8991 bfd_boolean is_loop;
e0001a05 8992
43cd72b9
BW		 8993 assert (fragP->fr_type == rs_machine_dependent);
8994 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
e0001a05 8995
43cd72b9
BW		 8996 /* Find the loop frag. */
8997 first_insn = next_non_empty_frag (fragP);
8998 /* Now find the first insn frag. */
8999 first_insn = next_non_empty_frag (first_insn);
e0001a05 9000
43cd72b9
BW		 9001 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
9002 assert (is_loop);
9003 loop_insn_size = xg_get_single_size (opcode);
e0001a05 9004
43cd72b9
BW		 9005 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
9006 pre_opcode_bytes += loop_insn_size;
e0001a05 9007
43cd72b9
BW		 9008 /* For loops, the alignment depends on the size of the
9009 instruction following the loop, not the LOOP instruction. */
e0001a05 9010
43cd72b9
BW		 9011 if (first_insn == NULL)
9012 return address;
e0001a05 9013
43cd72b9 9014 assert (first_insn->tc_frag_data.is_first_loop_insn);
e0001a05 9015
43cd72b9 9016 first_insn_size = frag_format_size (first_insn);
e0001a05 9017
43cd72b9
BW		 9018 if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED)
9019 first_insn_size = 3; /* ISA specifies this */
e0001a05 9020
43cd72b9
BW		 9021 /* If it was 8, then we'll need a larger alignment for the section. */
9022 alignment = get_text_align_power (first_insn_size);
e0001a05 9023
43cd72b9
BW		 9024 /* Is now_seg valid? */
9025 record_alignment (now_seg, alignment);
9026
9027 fill_size = get_text_align_fill_size
9028 (address + pre_opcode_bytes,
9029 get_text_align_power (first_insn_size),
9030 first_insn_size, TRUE, fragP->tc_frag_data.is_no_density);
e0001a05
NC		 9031
9032 return address + fill_size;
9033}
9034
9035
43cd72b9
BW		 9036/* 3 mechanisms for relaxing an alignment:
9037
9038 Align to a power of 2.
9039 Align so the next fragment's instruction does not cross a word boundary.
9040 Align the current instruction so that if the next instruction
9041 were 3 bytes, it would not cross a word boundary.
9042
e0001a05
NC		 9043 We can align with:
9044
43cd72b9
BW		 9045 zeros - This is easy; always insert zeros.
9046 nops - 3-byte and 2-byte instructions
9047 2 - 2-byte nop
9048 3 - 3-byte nop
9049 4 - 2 2-byte nops
9050 >=5 : 3-byte instruction + fn (n-3)
e0001a05
NC		 9051 widening - widen previous instructions. */
9052
9053static addressT
43cd72b9 9054get_aligned_diff (fragP, address, max_diff)
e0001a05
NC		 9055 fragS *fragP;
9056 addressT address;
43cd72b9 9057 addressT *max_diff;
e0001a05 9058{
43cd72b9
BW		 9059 addressT target_address, loop_insn_offset;
9060 int target_size;
9061 xtensa_opcode loop_opcode;
9062 bfd_boolean is_loop;
9063 int text_align_power;
9064 addressT opt_diff;
e0001a05 9065
43cd72b9
BW		 9066 assert (fragP->fr_type == rs_machine_dependent);
9067 switch (fragP->fr_subtype)
e0001a05 9068 {
43cd72b9
BW		 9069 case RELAX_DESIRE_ALIGN:
9070 target_size = next_frag_format_size (fragP);
9071 if (target_size == XTENSA_UNDEFINED)
9072 target_size = 3;
9073 text_align_power = get_text_align_power (xtensa_fetch_width);
9074 opt_diff = get_text_align_fill_size (address, text_align_power,
9075 target_size, FALSE, FALSE);
9076
9077 *max_diff = opt_diff + xtensa_fetch_width
9078 - (target_size + ((address + opt_diff) % xtensa_fetch_width));
9079 assert (*max_diff >= opt_diff);
9080 return opt_diff;
e0001a05 9081
43cd72b9
BW		 9082 case RELAX_ALIGN_NEXT_OPCODE:
9083 target_size = next_frag_format_size (fragP);
9084 loop_insn_offset = 0;
9085 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
9086 assert (is_loop);
9087
9088 /* If the loop has been expanded then the LOOP instruction
9089 could be at an offset from this fragment. */
9090 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
9091 != RELAX_IMMED)
9092 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
9093
9094 if (target_size == 2)
9095 target_size = 3; /* ISA specifies this */
9096
9097 /* In an ideal world, which is what we are shooting for here,
9098 we wouldn't need to use any NOPs immediately prior to the
9099 LOOP instruction. If this approach fails, relax_frag_loop_align
9100 will call get_noop_aligned_address. */
9101 target_address =
9102 address + loop_insn_offset + xg_get_single_size (loop_opcode);
9103 text_align_power = get_text_align_power (target_size),
9104 opt_diff = get_text_align_fill_size (target_address, text_align_power,
9105 target_size, FALSE, FALSE);
9106
9107 *max_diff = xtensa_fetch_width
9108 - ((target_address + opt_diff) % xtensa_fetch_width)
9109 - target_size + opt_diff;
9110 assert (*max_diff >= opt_diff);
9111 return opt_diff;
e0001a05 9112
43cd72b9
BW		 9113 default:
9114 break;
e0001a05 9115 }
43cd72b9
BW		 9116 assert (0);
9117 return 0;
e0001a05
NC		 9118}
9119
9120\f
9121/* md_relax_frag Hook and Helper Functions. */
9122
9123/* Return the number of bytes added to this fragment, given that the
9124 input has been stretched already by "stretch". */
9125
9126long
9127xtensa_relax_frag (fragP, stretch, stretched_p)
9128 fragS *fragP;
9129 long stretch;
9130 int *stretched_p;
9131{
43cd72b9 9132 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 9133 int unreported = fragP->tc_frag_data.unreported_expansion;
9134 long new_stretch = 0;
9135 char *file_name;
9136 int line, lit_size;
43cd72b9
BW		 9137 static xtensa_insnbuf vbuf = NULL;
9138 int slot, num_slots;
9139 xtensa_format fmt;
e0001a05
NC		 9140
9141 as_where (&file_name, &line);
9142 new_logical_line (fragP->fr_file, fragP->fr_line);
9143
9144 fragP->tc_frag_data.unreported_expansion = 0;
9145
9146 switch (fragP->fr_subtype)
9147 {
9148 case RELAX_ALIGN_NEXT_OPCODE:
9149 /* Always convert. */
43cd72b9
BW		 9150 if (fragP->tc_frag_data.relax_seen)
9151 new_stretch = relax_frag_loop_align (fragP, stretch);
e0001a05
NC		 9152 break;
9153
9154 case RELAX_LOOP_END:
9155 /* Do nothing. */
9156 break;
9157
9158 case RELAX_LOOP_END_ADD_NOP:
9159 /* Add a NOP and switch to .fill 0. */
9160 new_stretch = relax_frag_add_nop (fragP);
43cd72b9 9161 frag_wane (fragP);
e0001a05
NC		 9162 break;
9163
9164 case RELAX_DESIRE_ALIGN:
43cd72b9 9165 /* Do nothing. The narrowing before this frag will either align
e0001a05
NC		 9166 it or not. */
9167 break;
9168
9169 case RELAX_LITERAL:
9170 case RELAX_LITERAL_FINAL:
9171 return 0;
9172
9173 case RELAX_LITERAL_NR:
9174 lit_size = 4;
9175 fragP->fr_subtype = RELAX_LITERAL_FINAL;
9176 assert (unreported == lit_size);
9177 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
9178 fragP->fr_var -= lit_size;
9179 fragP->fr_fix += lit_size;
9180 new_stretch = 4;
9181 break;
9182
43cd72b9
BW		 9183 case RELAX_SLOTS:
9184 if (vbuf == NULL)
9185 vbuf = xtensa_insnbuf_alloc (isa);
9186
9187 xtensa_insnbuf_from_chars (isa, vbuf, fragP->fr_opcode, 0);
9188 fmt = xtensa_format_decode (isa, vbuf);
9189 num_slots = xtensa_format_num_slots (isa, fmt);
e0001a05 9190
43cd72b9
BW		 9191 for (slot = 0; slot < num_slots; slot++)
9192 {
9193 switch (fragP->tc_frag_data.slot_subtypes[slot])
9194 {
9195 case RELAX_NARROW:
9196 if (fragP->tc_frag_data.relax_seen)
9197 new_stretch += relax_frag_for_align (fragP, stretch);
9198 break;
9199
9200 case RELAX_IMMED:
9201 case RELAX_IMMED_STEP1:
9202 case RELAX_IMMED_STEP2:
9203 /* Place the immediate. */
9204 new_stretch += relax_frag_immed
9205 (now_seg, fragP, stretch,
9206 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9207 fmt, slot, stretched_p, FALSE);
9208 break;
9209
9210 default:
9211 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9212 break;
9213 }
9214 }
e0001a05
NC		 9215 break;
9216
9217 case RELAX_LITERAL_POOL_BEGIN:
9218 case RELAX_LITERAL_POOL_END:
43cd72b9
BW		 9219 case RELAX_MAYBE_UNREACHABLE:
9220 case RELAX_MAYBE_DESIRE_ALIGN:
e0001a05
NC		 9221 /* No relaxation required. */
9222 break;
9223
43cd72b9
BW		 9224 case RELAX_FILL_NOP:
9225 case RELAX_UNREACHABLE:
9226 if (fragP->tc_frag_data.relax_seen)
9227 new_stretch += relax_frag_for_align (fragP, stretch);
9228 break;
9229
e0001a05
NC		 9230 default:
9231 as_bad (_("bad relaxation state"));
9232 }
9233
43cd72b9
BW		 9234 /* Tell gas we need another relaxation pass. */
9235 if (! fragP->tc_frag_data.relax_seen)
9236 {
9237 fragP->tc_frag_data.relax_seen = TRUE;
9238 *stretched_p = 1;
9239 }
9240
e0001a05
NC		 9241 new_logical_line (file_name, line);
9242 return new_stretch;
9243}
9244
9245
9246static long
43cd72b9 9247relax_frag_loop_align (fragP, stretch)
e0001a05
NC		 9248 fragS *fragP;
9249 long stretch;
9250{
9251 addressT old_address, old_next_address, old_size;
9252 addressT new_address, new_next_address, new_size;
9253 addressT growth;
9254
43cd72b9
BW		 9255 /* All the frags with relax_frag_for_alignment prior to this one in the
9256 section have been done, hopefully eliminating the need for a NOP here.
9257 But, this will put it in if necessary. */
e0001a05
NC		 9258
9259 /* Calculate the old address of this fragment and the next fragment. */
9260 old_address = fragP->fr_address - stretch;
9261 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
43cd72b9 9262 fragP->tc_frag_data.text_expansion[0]);
e0001a05
NC		 9263 old_size = old_next_address - old_address;
9264
9265 /* Calculate the new address of this fragment and the next fragment. */
9266 new_address = fragP->fr_address;
9267 new_next_address =
9268 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
9269 new_size = new_next_address - new_address;
9270
9271 growth = new_size - old_size;
9272
9273 /* Fix up the text_expansion field and return the new growth. */
43cd72b9 9274 fragP->tc_frag_data.text_expansion[0] += growth;
e0001a05
NC		 9275 return growth;
9276}
9277
9278
43cd72b9 9279/* Add a NOP instruction. */
e0001a05
NC		 9280
9281static long
9282relax_frag_add_nop (fragP)
9283 fragS *fragP;
9284{
e0001a05 9285 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
43cd72b9
BW		 9286 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
9287 assemble_nop (length, nop_buf);
e0001a05 9288 fragP->tc_frag_data.is_insn = TRUE;
e0001a05 9289
e0001a05
NC		 9290 if (fragP->fr_var < length)
9291 {
43cd72b9 9292 as_fatal (_("fr_var (%ld) < length (%d)"), fragP->fr_var, length);
e0001a05
NC		 9293 return 0;
9294 }
9295
9296 fragP->fr_fix += length;
9297 fragP->fr_var -= length;
e0001a05
NC		 9298 return length;
9299}
9300
9301
9302static long
43cd72b9 9303relax_frag_for_align (fragP, stretch)
e0001a05
NC		 9304 fragS *fragP;
9305 long stretch;
9306{
43cd72b9
BW		 9307 /* Overview of the relaxation procedure for alignment:
9308 We can widen with NOPs or by widening instructions or by filling
9309 bytes after jump instructions. Find the opportune places and widen
9310 them if necessary. */
9311
9312 long stretch_me;
9313 long diff;
e0001a05 9314
43cd72b9
BW		 9315 assert (fragP->fr_subtype == RELAX_FILL_NOP
9316 || fragP->fr_subtype == RELAX_UNREACHABLE
9317 || (fragP->fr_subtype == RELAX_SLOTS
9318 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
9319
9320 stretch_me = future_alignment_required (fragP, stretch);
9321 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
9322 if (diff == 0)
9323 return 0;
e0001a05 9324
43cd72b9 9325 if (diff < 0)
e0001a05 9326 {
43cd72b9
BW		 9327 /* We expanded on a previous pass. Can we shrink now? */
9328 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
9329 if (shrink <= stretch && stretch > 0)
e0001a05 9330 {
43cd72b9
BW		 9331 fragP->tc_frag_data.text_expansion[0] = stretch_me;
9332 return -shrink;
e0001a05
NC		 9333 }
9334 return 0;
9335 }
9336
43cd72b9
BW		 9337 /* Below here, diff > 0. */
9338 fragP->tc_frag_data.text_expansion[0] = stretch_me;
e0001a05 9339
43cd72b9 9340 return diff;
e0001a05
NC		 9341}
9342
9343
43cd72b9
BW		 9344/* Return the address of the next frag that should be aligned.
9345
9346 By "address" we mean the address it _would_ be at if there
9347 is no action taken to align it between here and the target frag.
9348 In other words, if no narrows and no fill nops are used between
9349 here and the frag to align, _even_if_ some of the frags we use
9350 to align targets have already expanded on a previous relaxation
9351 pass.
9352
9353 Also, count each frag that may be used to help align the target.
9354
9355 Return 0 if there are no frags left in the chain that need to be
9356 aligned. */
9357
9358static addressT
9359find_address_of_next_align_frag (fragPP, wide_nops, narrow_nops,
9360 widens, paddable)
9361 fragS **fragPP;
9362 int *wide_nops;
9363 int *narrow_nops;
9364 int *widens;
9365 bfd_boolean *paddable;
e0001a05 9366{
43cd72b9
BW		 9367 fragS *fragP = *fragPP;
9368 addressT address = fragP->fr_address;
9369
9370 /* Do not reset the counts to 0. */
e0001a05
NC		 9371
9372 while (fragP)
9373 {
9374 /* Limit this to a small search. */
43cd72b9
BW		 9375 if (*widens > 8)
9376 {
9377 *fragPP = fragP;
9378 return 0;
9379 }
e0001a05
NC		 9380 address += fragP->fr_fix;
9381
43cd72b9
BW		 9382 if (fragP->fr_type == rs_fill)
9383 address += fragP->fr_offset * fragP->fr_var;
9384 else if (fragP->fr_type == rs_machine_dependent)
e0001a05 9385 {
e0001a05
NC		 9386 switch (fragP->fr_subtype)
9387 {
43cd72b9
BW		 9388 case RELAX_UNREACHABLE:
9389 *paddable = TRUE;
9390 break;
9391
9392 case RELAX_FILL_NOP:
9393 (*wide_nops)++;
9394 if (!fragP->tc_frag_data.is_no_density)
9395 (*narrow_nops)++;
9396 break;
9397
9398 case RELAX_SLOTS:
9399 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9400 {
9401 (*widens)++;
9402 break;
9403 }
9404 /* FIXME: shouldn't this add the expansion of all slots? */
9405 address += fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 9406 break;
9407
9408 case RELAX_IMMED:
43cd72b9 9409 address += fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 9410 break;
9411
9412 case RELAX_ALIGN_NEXT_OPCODE:
9413 case RELAX_DESIRE_ALIGN:
43cd72b9
BW		 9414 *fragPP = fragP;
9415 return address;
9416
9417 case RELAX_MAYBE_UNREACHABLE:
9418 case RELAX_MAYBE_DESIRE_ALIGN:
9419 /* Do nothing. */
e0001a05
NC		 9420 break;
9421
9422 default:
43cd72b9
BW		 9423 /* Just punt if we don't know the type. */
9424 *fragPP = fragP;
9425 return 0;
e0001a05 9426 }
43cd72b9
BW		 9427 }
9428 else
9429 {
9430 /* Just punt if we don't know the type. */
9431 *fragPP = fragP;
9432 return 0;
9433 }
9434 fragP = fragP->fr_next;
9435 }
9436
9437 *fragPP = fragP;
9438 return 0;
9439}
9440
9441
9442/* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
9443 I'll leave this in until I am more confident this works. */
9444
9445#define LOOKAHEAD_ALIGNER 1
9446
9447static long
9448future_alignment_required (fragP, stretch)
9449 fragS *fragP;
9450 long stretch ATTRIBUTE_UNUSED;
9451{
9452 fragS *this_frag = fragP;
9453 long address;
9454 int num_widens = 0;
9455 int wide_nops = 0;
9456 int narrow_nops = 0;
9457 bfd_boolean paddable = FALSE;
9458 offsetT local_opt_diff;
9459 offsetT opt_diff;
9460 offsetT max_diff;
9461 int stretch_amount = 0;
9462 int local_stretch_amount;
9463 int global_stretch_amount;
9464
9465 address
9466 = find_address_of_next_align_frag (&fragP, &wide_nops, &narrow_nops,
9467 &num_widens, &paddable);
9468
9469 if (address)
9470 {
9471 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
9472 opt_diff = local_opt_diff;
9473 assert (opt_diff >= 0);
9474 assert (max_diff >= opt_diff);
9475 if (max_diff == 0)
9476 return 0;
9477#ifdef LOOKAHEAD_ALIGNER
9478 if (fragP)
9479 fragP = fragP->fr_next;
9480
9481 while (fragP && opt_diff < max_diff && address)
9482 {
9483 /* We only use these to determine if we can exit early
9484 because there will be plenty of ways to align future
9485 align frags. */
9486 unsigned int glob_widens = 0;
9487 int dnn = 0;
9488 int dw = 0;
9489 bfd_boolean glob_pad = 0;
9490 address =
9491 find_address_of_next_align_frag (&fragP, &glob_widens,
9492 &dnn, &dw, &glob_pad);
9493 /* If there is a padable portion, then skip. */
9494 if (glob_pad || (glob_widens >= xtensa_fetch_width))
9495 break;
9496
9497 if (address)
9498 {
9499 offsetT next_m_diff;
9500 offsetT next_o_diff;
9501
9502 /* Downrange frags haven't had stretch added to them yet. */
9503 address += stretch;
9504
9505 /* The address also includes any text expansion from this
9506 frag in a previous pass, but we don't want that. */
9507 address -= this_frag->tc_frag_data.text_expansion[0];
9508
9509 /* Assume we are going to move at least opt_diff. In
9510 reality, we might not be able to, but assuming that
9511 we will helps catch cases where moving opt_diff pushes
9512 the next target from aligned to unaligned. */
9513 address += opt_diff;
9514
9515 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
9516
9517 /* Now cleanup for the adjustments to address. */
9518 next_o_diff += opt_diff;
9519 next_m_diff += opt_diff;
9520 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
9521 opt_diff = next_o_diff;
9522 if (next_m_diff < max_diff)
9523 max_diff = next_m_diff;
9524 fragP = fragP->fr_next;
9525 }
9526 }
9527#endif /* LOOKAHEAD_ALIGNER */
9528 /* If there are enough wideners in between, do it. */
9529 if (paddable)
9530 {
9531 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
9532 {
9533 assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
9534 return opt_diff;
9535 }
9536 return 0;
9537 }
9538 local_stretch_amount
9539 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9540 num_widens, local_opt_diff);
9541#ifdef LOOKAHEAD_ALIGNER
9542 global_stretch_amount
9543 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9544 num_widens, opt_diff);
9545 /* If the condition below is true, then the frag couldn't
9546 stretch the correct amount for the global case, so we just
9547 optimize locally. We'll rely on the subsequent frags to get
9548 the correct alignment in the global case. */
9549 if (global_stretch_amount < local_stretch_amount)
9550 stretch_amount = local_stretch_amount;
9551 else
9552 stretch_amount = global_stretch_amount;
9553#else /* ! LOOKAHEAD_ALIGNER */
9554 stretch_amount = local_stretch_amount;
9555#endif /* ! LOOKAHEAD_ALIGNER */
9556 if (this_frag->fr_subtype == RELAX_SLOTS
9557 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9558 assert (stretch_amount <= 1);
9559 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
9560 {
9561 if (this_frag->tc_frag_data.is_no_density)
9562 assert (stretch_amount == 3 || stretch_amount == 0);
9563 else
9564 assert (stretch_amount <= 3);
9565 }
9566 }
9567 return stretch_amount;
9568}
9569
9570
9571/* The idea: widen everything you can to get a target or loop aligned,
9572 then start using NOPs.
9573
9574 When we must have a NOP, here is a table of how we decide
9575 (so you don't have to fight through the control flow below):
9576
9577 wide_nops = the number of wide NOPs available for aligning
9578 narrow_nops = the number of narrow NOPs available for aligning
9579 (a subset of wide_nops)
9580 widens = the number of narrow instructions that should be widened
9581
9582 Desired wide narrow
9583 Diff nop nop widens
9584 1 0 0 1
9585 2 0 1 0
9586 3a 1 0 0
9587 b 0 1 1 (case 3a makes this case unnecessary)
9588 4a 1 0 1
9589 b 0 2 0
9590 c 0 1 2 (case 4a makes this case unnecessary)
9591 5a 1 0 2
9592 b 1 1 0
9593 c 0 2 1 (case 5b makes this case unnecessary)
9594 6a 2 0 0
9595 b 1 0 3
9596 c 0 1 4 (case 6b makes this case unneccesary)
9597 d 1 1 1 (case 6a makes this case unnecessary)
9598 e 0 2 2 (case 6a makes this case unnecessary)
9599 f 0 3 0 (case 6a makes this case unnecessary)
9600 7a 1 0 4
9601 b 2 0 1
9602 c 1 1 2 (case 7b makes this case unnecessary)
9603 d 0 1 5 (case 7a makes this case unnecessary)
9604 e 0 2 3 (case 7b makes this case unnecessary)
9605 f 0 3 1 (case 7b makes this case unnecessary)
9606 g 1 2 1 (case 7b makes this case unnecessary)
9607*/
9608
9609static long
9610bytes_to_stretch (this_frag, wide_nops, narrow_nops, num_widens, desired_diff)
9611 fragS *this_frag;
9612 int wide_nops;
9613 int narrow_nops;
9614 int num_widens;
9615 int desired_diff;
9616{
9617 int bytes_short = desired_diff - num_widens;
9618
9619 assert (desired_diff >= 0 && desired_diff < 8);
9620 if (desired_diff == 0)
9621 return 0;
9622
9623 assert (wide_nops > 0 || num_widens > 0);
e0001a05 9624
43cd72b9
BW		 9625 /* Always prefer widening to NOP-filling. */
9626 if (bytes_short < 0)
9627 {
9628 /* There are enough RELAX_NARROW frags after this one
9629 to align the target without widening this frag in any way. */
9630 return 0;
9631 }
9632
9633 if (bytes_short == 0)
9634 {
9635 /* Widen every narrow between here and the align target
9636 and the align target will be properly aligned. */
9637 if (this_frag->fr_subtype == RELAX_FILL_NOP)
9638 return 0;
9639 else
9640 return 1;
9641 }
9642
9643 /* From here we will need at least one NOP to get an alignment.
9644 However, we may not be able to align at all, in which case,
9645 don't widen. */
9646 if (this_frag->fr_subtype == RELAX_FILL_NOP)
9647 {
9648 switch (desired_diff)
9649 {
9650 case 1:
9651 return 0;
9652 case 2:
9653 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
9654 return 2; /* case 2 */
9655 return 0;
9656 case 3:
9657 if (wide_nops > 1)
9658 return 0;
9659 else
9660 return 3; /* case 3a */
9661 case 4:
9662 if (num_widens >= 1 && wide_nops == 1)
9663 return 3; /* case 4a */
9664 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
9665 return 2; /* case 4b */
9666 return 0;
9667 case 5:
9668 if (num_widens >= 2 && wide_nops == 1)
9669 return 3; /* case 5a */
9670 /* We will need two nops. Are there enough nops
9671 between here and the align target? */
9672 if (wide_nops < 2 || narrow_nops == 0)
9673 return 0;
9674 /* Are there other nops closer that can serve instead? */
9675 if (wide_nops > 2 && narrow_nops > 1)
9676 return 0;
9677 /* Take the density one first, because there might not be
9678 another density one available. */
9679 if (!this_frag->tc_frag_data.is_no_density)
9680 return 2; /* case 5b narrow */
9681 else
9682 return 3; /* case 5b wide */
9683 return 0;
9684 case 6:
9685 if (wide_nops == 2)
9686 return 3; /* case 6a */
9687 else if (num_widens >= 3 && wide_nops == 1)
9688 return 3; /* case 6b */
9689 return 0;
9690 case 7:
9691 if (wide_nops == 1 && num_widens >= 4)
9692 return 3; /* case 7a */
9693 else if (wide_nops == 2 && num_widens >= 1)
9694 return 3; /* case 7b */
9695 return 0;
e0001a05 9696 default:
43cd72b9 9697 assert (0);
e0001a05 9698 }
e0001a05 9699 }
43cd72b9
BW		 9700 else
9701 {
9702 /* We will need a NOP no matter what, but should we widen
9703 this instruction to help?
e0001a05 9704
43cd72b9
BW		 9705 This is a RELAX_FRAG_NARROW frag. */
9706 switch (desired_diff)
9707 {
9708 case 1:
9709 assert (0);
9710 return 0;
9711 case 2:
9712 case 3:
9713 return 0;
9714 case 4:
9715 if (wide_nops >= 1 && num_widens == 1)
9716 return 1; /* case 4a */
9717 return 0;
9718 case 5:
9719 if (wide_nops >= 1 && num_widens == 2)
9720 return 1; /* case 5a */
9721 return 0;
9722 case 6:
9723 if (wide_nops >= 2)
9724 return 0; /* case 6a */
9725 else if (wide_nops >= 1 && num_widens == 3)
9726 return 1; /* case 6b */
9727 return 0;
9728 case 7:
9729 if (wide_nops >= 1 && num_widens == 4)
9730 return 1; /* case 7a */
9731 else if (wide_nops >= 2 && num_widens == 1)
9732 return 1; /* case 7b */
9733 return 0;
9734 default:
9735 assert (0);
9736 return 0;
9737 }
9738 }
9739 assert (0);
9740 return 0;
e0001a05
NC		 9741}
9742
9743
9744static long
43cd72b9
BW		 9745relax_frag_immed (segP, fragP, stretch, min_steps, fmt, slot, stretched_p,
9746 estimate_only)
e0001a05
NC		 9747 segT segP;
9748 fragS *fragP;
9749 long stretch;
9750 int min_steps;
43cd72b9
BW		 9751 xtensa_format fmt;
9752 int slot;
e0001a05 9753 int *stretched_p;
43cd72b9 9754 bfd_boolean estimate_only;
e0001a05 9755{
43cd72b9
BW		 9756 TInsn tinsn;
9757 vliw_insn orig_vinsn;
e0001a05
NC		 9758 int old_size;
9759 bfd_boolean negatable_branch = FALSE;
9760 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 9761 bfd_boolean wide_insn = FALSE;
9762 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 9763 IStack istack;
9764 offsetT frag_offset;
9765 int num_steps;
9766 fragS *lit_fragP;
9767 int num_text_bytes, num_literal_bytes;
43cd72b9 9768 int literal_diff, total_text_diff, this_text_diff, first;
e0001a05
NC		 9769
9770 assert (fragP->fr_opcode != NULL);
9771
43cd72b9
BW		 9772 xg_init_vinsn (&orig_vinsn);
9773 vinsn_from_chars (&orig_vinsn, fragP->fr_opcode);
9774 if (xtensa_format_num_slots (isa, fmt) > 1)
9775 wide_insn = TRUE;
9776
9777 tinsn = orig_vinsn.slots[slot];
9778 tinsn_immed_from_frag (&tinsn, fragP, slot);
e0001a05 9779
43cd72b9
BW		 9780 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
9781 return 0;
e0001a05 9782
43cd72b9
BW		 9783 if (workaround_b_j_loop_end && !get_frag_is_no_transform (fragP))
9784 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
e0001a05 9785
43cd72b9 9786 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
e0001a05 9787
43cd72b9 9788 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 9789
9790 /* Special case: replace a branch to the next instruction with a NOP.
9791 This is required to work around a hardware bug in T1040.0 and also
9792 serves as an optimization. */
9793
9794 if (branch_jmp_to_next
9795 && ((old_size == 2) || (old_size == 3))
9796 && !next_frag_is_loop_target (fragP))
9797 return 0;
9798
9799 /* Here is the fun stuff: Get the immediate field from this
9800 instruction. If it fits, we are done. If not, find the next
9801 instruction sequence that fits. */
9802
9803 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9804 istack_init (&istack);
43cd72b9 9805 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
e0001a05
NC		 9806 min_steps, stretch);
9807 if (num_steps < min_steps)
9808 {
9809 as_fatal (_("internal error: relaxation failed"));
9810 return 0;
9811 }
9812
9813 if (num_steps > RELAX_IMMED_MAXSTEPS)
9814 {
9815 as_fatal (_("internal error: relaxation requires too many steps"));
9816 return 0;
9817 }
9818
43cd72b9 9819 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
e0001a05
NC		 9820
9821 /* Figure out the number of bytes needed. */
9822 lit_fragP = 0;
e0001a05 9823 num_literal_bytes = get_num_stack_literal_bytes (&istack);
43cd72b9
BW		 9824 literal_diff =
9825 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9826 first = 0;
9827 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9828 first++;
9829 num_text_bytes = get_num_stack_text_bytes (&istack);
9830 if (wide_insn)
9831 {
9832 num_text_bytes += old_size;
9833 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9834 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9835 }
9836 total_text_diff = num_text_bytes - old_size;
9837 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
e0001a05
NC		 9838
9839 /* It MUST get larger. If not, we could get an infinite loop. */
43cd72b9
BW		 9840 assert (num_text_bytes >= 0);
9841 assert (literal_diff >= 0);
9842 assert (total_text_diff >= 0);
e0001a05 9843
43cd72b9
BW		 9844 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9845 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9846 assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9847 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
e0001a05
NC		 9848
9849 /* Find the associated expandable literal for this. */
9850 if (literal_diff != 0)
9851 {
43cd72b9 9852 lit_fragP = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9853 if (lit_fragP)
9854 {
9855 assert (literal_diff == 4);
9856 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9857
9858 /* We expect that the literal section state has NOT been
9859 modified yet. */
9860 assert (lit_fragP->fr_type == rs_machine_dependent
9861 && lit_fragP->fr_subtype == RELAX_LITERAL);
9862 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9863
9864 /* We need to mark this section for another iteration
9865 of relaxation. */
9866 (*stretched_p)++;
9867 }
9868 }
9869
43cd72b9
BW		 9870 /* FIXME: When a negatable branch expands and then contracts in a
9871 subsequent pass, update_next_frag_state correctly updates the
9872 type of the frag to RELAX_MAYBE_UNREACHABLE, but it doesn't undo
9873 any expansion relax_frag_for_align may have expected it to. For
9874 now, change back to only call it when the branch expands. */
9875 if (negatable_branch && istack.ninsn > 1)
9876 update_next_frag_state (fragP, FALSE /* istack.ninsn > 1 */);
e0001a05 9877
43cd72b9 9878 return this_text_diff;
e0001a05
NC		 9879}
9880
9881\f
9882/* md_convert_frag Hook and Helper Functions. */
9883
9884void
9885md_convert_frag (abfd, sec, fragp)
9886 bfd *abfd ATTRIBUTE_UNUSED;
9887 segT sec;
9888 fragS *fragp;
9889{
43cd72b9
BW		 9890 static xtensa_insnbuf vbuf = NULL;
9891 xtensa_isa isa = xtensa_default_isa;
9892 int slot;
9893 int num_slots;
9894 xtensa_format fmt;
e0001a05
NC		 9895 char *file_name;
9896 int line;
9897
9898 as_where (&file_name, &line);
9899 new_logical_line (fragp->fr_file, fragp->fr_line);
9900
9901 switch (fragp->fr_subtype)
9902 {
9903 case RELAX_ALIGN_NEXT_OPCODE:
9904 /* Always convert. */
9905 convert_frag_align_next_opcode (fragp);
9906 break;
9907
9908 case RELAX_DESIRE_ALIGN:
9909 /* Do nothing. If not aligned already, too bad. */
9910 break;
9911
43cd72b9
BW		 9912 case RELAX_LITERAL:
9913 case RELAX_LITERAL_FINAL:
9914 break;
9915
9916 case RELAX_SLOTS:
9917 if (vbuf == NULL)
9918 vbuf = xtensa_insnbuf_alloc (isa);
9919
9920 xtensa_insnbuf_from_chars (isa, vbuf, fragp->fr_opcode, 0);
9921 fmt = xtensa_format_decode (isa, vbuf);
9922 num_slots = xtensa_format_num_slots (isa, fmt);
9923
9924 for (slot = 0; slot < num_slots; slot++)
9925 {
9926 switch (fragp->tc_frag_data.slot_subtypes[slot])
9927 {
9928 case RELAX_NARROW:
9929 convert_frag_narrow (sec, fragp, fmt, slot);
9930 break;
9931
9932 case RELAX_IMMED:
9933 case RELAX_IMMED_STEP1:
9934 case RELAX_IMMED_STEP2:
9935 /* Place the immediate. */
9936 convert_frag_immed
9937 (sec, fragp,
9938 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9939 fmt, slot);
9940 break;
9941
9942 default:
9943 /* This is OK because some slots could have
9944 relaxations and others have none. */
9945 break;
9946 }
9947 }
9948 break;
9949
9950 case RELAX_UNREACHABLE:
9951 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9952 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9953 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9954 frag_wane (fragp);
e0001a05
NC		 9955 break;
9956
43cd72b9
BW		 9957 case RELAX_MAYBE_UNREACHABLE:
9958 case RELAX_MAYBE_DESIRE_ALIGN:
9959 frag_wane (fragp);
e0001a05
NC		 9960 break;
9961
43cd72b9
BW		 9962 case RELAX_FILL_NOP:
9963 convert_frag_fill_nop (fragp);
e0001a05
NC		 9964 break;
9965
9966 case RELAX_LITERAL_NR:
9967 if (use_literal_section)
9968 {
9969 /* This should have been handled during relaxation. When
9970 relaxing a code segment, literals sometimes need to be
9971 added to the corresponding literal segment. If that
9972 literal segment has already been relaxed, then we end up
9973 in this situation. Marking the literal segments as data
9974 would make this happen less often (since GAS always relaxes
9975 code before data), but we could still get into trouble if
9976 there are instructions in a segment that is not marked as
9977 containing code. Until we can implement a better solution,
9978 cheat and adjust the addresses of all the following frags.
9979 This could break subsequent alignments, but the linker's
9980 literal coalescing will do that anyway. */
9981
9982 fragS *f;
9983 fragp->fr_subtype = RELAX_LITERAL_FINAL;
9984 assert (fragp->tc_frag_data.unreported_expansion == 4);
9985 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9986 fragp->fr_var -= 4;
9987 fragp->fr_fix += 4;
9988 for (f = fragp->fr_next; f; f = f->fr_next)
9989 f->fr_address += 4;
9990 }
9991 else
9992 as_bad (_("invalid relaxation fragment result"));
9993 break;
9994 }
9995
9996 fragp->fr_var = 0;
9997 new_logical_line (file_name, line);
9998}
9999
10000
10001void
10002convert_frag_align_next_opcode (fragp)
10003 fragS *fragp;
10004{
10005 char *nop_buf; /* Location for Writing. */
10006 size_t i;
10007
10008 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
10009 addressT aligned_address;
10010 size_t fill_size, nop_count;
10011
10012 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
10013 fragp->fr_fix);
10014 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
10015 nop_count = get_text_align_nop_count (fill_size, use_no_density);
10016 nop_buf = fragp->fr_literal + fragp->fr_fix;
10017
10018 for (i = 0; i < nop_count; i++)
10019 {
10020 size_t nop_size;
10021 nop_size = get_text_align_nth_nop_size (fill_size, i, use_no_density);
10022
10023 assemble_nop (nop_size, nop_buf);
10024 nop_buf += nop_size;
10025 }
10026
10027 fragp->fr_fix += fill_size;
10028 fragp->fr_var -= fill_size;
10029}
10030
10031
10032static void
43cd72b9
BW		 10033convert_frag_narrow (segP, fragP, fmt, slot)
10034 segT segP;
e0001a05 10035 fragS *fragP;
43cd72b9
BW		 10036 xtensa_format fmt;
10037 int slot;
e0001a05 10038{
43cd72b9
BW		 10039 TInsn tinsn, single_target;
10040 xtensa_format single_fmt;
e0001a05
NC		 10041 int size, old_size, diff, error_val;
10042 offsetT frag_offset;
10043
43cd72b9
BW		 10044 assert (slot == 0);
10045 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
10046
10047 if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1)
10048 {
10049 assert (fragP->tc_frag_data.text_expansion[0] == 1
10050 || fragP->tc_frag_data.text_expansion[0] == 0);
10051 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
10052 fmt, slot);
10053 return;
10054 }
10055
10056 if (fragP->tc_frag_data.text_expansion[0] == 0)
e0001a05
NC		 10057 {
10058 /* No conversion. */
10059 fragP->fr_var = 0;
10060 return;
10061 }
10062
10063 assert (fragP->fr_opcode != NULL);
10064
43cd72b9
BW		 10065 /* Frags in this relaxation state should only contain
10066 single instruction bundles. */
10067 tinsn_immed_from_frag (&tinsn, fragP, 0);
e0001a05
NC		 10068
10069 /* Just convert it to a wide form.... */
10070 size = 0;
43cd72b9 10071 old_size = xg_get_single_size (tinsn.opcode);
e0001a05
NC		 10072
10073 tinsn_init (&single_target);
10074 frag_offset = fragP->fr_opcode - fragP->fr_literal;
10075
43cd72b9 10076 error_val = xg_expand_narrow (&single_target, &tinsn);
e0001a05 10077 if (error_val)
43cd72b9
BW		 10078 {
10079 as_bad (_("unable to widen instruction"));
10080 return;
10081 }
10082
10083 size = xg_get_single_size (single_target.opcode);
10084 single_fmt = xg_get_single_format (single_target.opcode);
e0001a05 10085
43cd72b9 10086 xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode,
e0001a05
NC		 10087 fragP, frag_offset, TRUE);
10088
10089 diff = size - old_size;
10090 assert (diff >= 0);
10091 assert (diff <= fragP->fr_var);
10092 fragP->fr_var -= diff;
10093 fragP->fr_fix += diff;
10094
10095 /* clean it up */
10096 fragP->fr_var = 0;
10097}
10098
10099
10100static void
43cd72b9
BW		 10101convert_frag_fill_nop (fragP)
10102 fragS *fragP;
10103{
10104 char *loc = &fragP->fr_literal[fragP->fr_fix];
10105 int size = fragP->tc_frag_data.text_expansion[0];
10106 assert ((unsigned) size == (fragP->fr_next->fr_address
10107 - fragP->fr_address - fragP->fr_fix));
10108 if (size == 0)
10109 {
10110 /* No conversion. */
10111 fragP->fr_var = 0;
10112 return;
10113 }
10114 assemble_nop (size, loc);
10115 fragP->tc_frag_data.is_insn = TRUE;
10116 fragP->fr_var -= size;
10117 fragP->fr_fix += size;
10118 frag_wane (fragP);
10119}
10120
10121
10122static void
10123convert_frag_immed (segP, fragP, min_steps, fmt, slot)
e0001a05
NC		 10124 segT segP;
10125 fragS *fragP;
10126 int min_steps;
43cd72b9
BW		 10127 xtensa_format fmt;
10128 int slot;
e0001a05
NC		 10129{
10130 char *immed_instr = fragP->fr_opcode;
43cd72b9 10131 TInsn orig_tinsn;
e0001a05 10132 bfd_boolean expanded = FALSE;
e0001a05 10133 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 10134 char *fr_opcode = fragP->fr_opcode;
10135 vliw_insn orig_vinsn;
10136 xtensa_isa isa = xtensa_default_isa;
10137 bfd_boolean wide_insn = FALSE;
10138 int bytes;
10139 bfd_boolean is_loop;
e0001a05 10140
43cd72b9 10141 assert (fr_opcode != NULL);
e0001a05 10142
43cd72b9 10143 xg_init_vinsn (&orig_vinsn);
e0001a05 10144
43cd72b9
BW		 10145 vinsn_from_chars (&orig_vinsn, fr_opcode);
10146 if (xtensa_format_num_slots (isa, fmt) > 1)
10147 wide_insn = TRUE;
e0001a05 10148
43cd72b9
BW		 10149 orig_tinsn = orig_vinsn.slots[slot];
10150 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
10151
10152 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
e0001a05 10153
43cd72b9
BW		 10154 if (workaround_b_j_loop_end && !get_frag_is_no_transform (fragP))
10155 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
e0001a05
NC		 10156
10157 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
10158 {
10159 /* Conversion just inserts a NOP and marks the fix as completed. */
43cd72b9
BW		 10160 bytes = xtensa_format_length (isa, fmt);
10161 if (bytes >= 4)
10162 {
10163 orig_vinsn.slots[slot].opcode =
10164 xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot);
10165 orig_vinsn.slots[slot].ntok = 0;
10166 }
10167 else
10168 {
10169 bytes += fragP->tc_frag_data.text_expansion[0];
10170 assert (bytes == 2 || bytes == 3);
10171 build_nop (&orig_vinsn.slots[0], bytes);
10172 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
10173 }
10174 vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE);
10175 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf, fr_opcode, 0);
e0001a05
NC		 10176 fragP->fr_var = 0;
10177 }
43cd72b9 10178 else if (!orig_tinsn.is_specific_opcode)
e0001a05 10179 {
43cd72b9
BW		 10180 /* Here is the fun stuff: Get the immediate field from this
10181 instruction. If it fits, we're done. If not, find the next
10182 instruction sequence that fits. */
10183
e0001a05
NC		 10184 IStack istack;
10185 int i;
10186 symbolS *lit_sym = NULL;
10187 int total_size = 0;
43cd72b9 10188 int target_offset = 0;
e0001a05
NC		 10189 int old_size;
10190 int diff;
10191 symbolS *gen_label = NULL;
10192 offsetT frag_offset;
43cd72b9
BW		 10193 bfd_boolean first = TRUE;
10194 bfd_boolean last_is_jump;
e0001a05 10195
43cd72b9 10196 /* It does not fit. Find something that does and
e0001a05 10197 convert immediately. */
43cd72b9 10198 frag_offset = fr_opcode - fragP->fr_literal;
e0001a05 10199 istack_init (&istack);
43cd72b9 10200 xg_assembly_relax (&istack, &orig_tinsn,
e0001a05
NC		 10201 segP, fragP, frag_offset, min_steps, 0);
10202
43cd72b9 10203 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 10204
10205 /* Assemble this right inline. */
10206
10207 /* First, create the mapping from a label name to the REAL label. */
43cd72b9 10208 target_offset = 0;
e0001a05
NC		 10209 for (i = 0; i < istack.ninsn; i++)
10210 {
43cd72b9 10211 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 10212 fragS *lit_frag;
10213
43cd72b9 10214 switch (tinsn->insn_type)
e0001a05
NC		 10215 {
10216 case ITYPE_LITERAL:
10217 if (lit_sym != NULL)
10218 as_bad (_("multiple literals in expansion"));
10219 /* First find the appropriate space in the literal pool. */
43cd72b9 10220 lit_frag = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 10221 if (lit_frag == NULL)
10222 as_bad (_("no registered fragment for literal"));
43cd72b9 10223 if (tinsn->ntok != 1)
e0001a05
NC		 10224 as_bad (_("number of literal tokens != 1"));
10225
10226 /* Set the literal symbol and add a fixup. */
10227 lit_sym = lit_frag->fr_symbol;
10228 break;
10229
10230 case ITYPE_LABEL:
43cd72b9
BW		 10231 if (align_targets && !is_loop)
10232 {
10233 fragS *unreach = fragP->fr_next;
10234 while (!(unreach->fr_type == rs_machine_dependent
10235 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10236 || unreach->fr_subtype == RELAX_UNREACHABLE)))
10237 {
10238 unreach = unreach->fr_next;
10239 }
10240
10241 assert (unreach->fr_type == rs_machine_dependent
10242 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10243 || unreach->fr_subtype == RELAX_UNREACHABLE));
10244
10245 target_offset += unreach->tc_frag_data.text_expansion[0];
10246 }
e0001a05
NC		 10247 assert (gen_label == NULL);
10248 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
43cd72b9
BW		 10249 fr_opcode - fragP->fr_literal
10250 + target_offset, fragP);
e0001a05
NC		 10251 break;
10252
10253 case ITYPE_INSN:
43cd72b9
BW		 10254 if (first && wide_insn)
10255 {
10256 target_offset += xtensa_format_length (isa, fmt);
10257 first = FALSE;
10258 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10259 target_offset += xg_get_single_size (tinsn->opcode);
10260 }
10261 else
10262 target_offset += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 10263 break;
10264 }
10265 }
10266
10267 total_size = 0;
43cd72b9
BW		 10268 first = TRUE;
10269 last_is_jump = FALSE;
e0001a05
NC		 10270 for (i = 0; i < istack.ninsn; i++)
10271 {
43cd72b9 10272 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 10273 fragS *lit_frag;
10274 int size;
10275 segT target_seg;
43cd72b9 10276 bfd_reloc_code_real_type reloc_type;
e0001a05 10277
43cd72b9 10278 switch (tinsn->insn_type)
e0001a05
NC		 10279 {
10280 case ITYPE_LITERAL:
43cd72b9
BW		 10281 lit_frag = fragP->tc_frag_data.literal_frags[slot];
10282 /* Already checked. */
e0001a05
NC		 10283 assert (lit_frag != NULL);
10284 assert (lit_sym != NULL);
43cd72b9
BW		 10285 assert (tinsn->ntok == 1);
10286 /* Add a fixup. */
e0001a05
NC		 10287 target_seg = S_GET_SEGMENT (lit_sym);
10288 assert (target_seg);
43cd72b9
BW		 10289 if (tinsn->tok[0].X_op == O_pltrel)
10290 reloc_type = BFD_RELOC_XTENSA_PLT;
10291 else
10292 reloc_type = BFD_RELOC_32;
e0001a05 10293 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
43cd72b9 10294 &tinsn->tok[0], FALSE, reloc_type);
e0001a05
NC		 10295 break;
10296
10297 case ITYPE_LABEL:
10298 break;
10299
10300 case ITYPE_INSN:
43cd72b9
BW		 10301 xg_resolve_labels (tinsn, gen_label);
10302 xg_resolve_literals (tinsn, lit_sym);
10303 if (wide_insn && first)
10304 {
10305 first = FALSE;
10306 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10307 {
10308 tinsn->record_fix = TRUE;
10309 orig_vinsn.slots[slot] = *tinsn;
10310 }
10311 else
10312 {
10313 orig_vinsn.slots[slot].opcode =
10314 xtensa_format_slot_nop_opcode (isa, fmt, slot);
10315 orig_vinsn.slots[slot].ntok = 0;
10316 orig_vinsn.slots[slot].record_fix = FALSE;
10317 }
10318 vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE);
10319 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf,
10320 immed_instr, 0);
10321 fragP->tc_frag_data.is_insn = TRUE;
10322 size = xtensa_format_length (isa, fmt);
10323 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10324 {
10325 xtensa_format single_fmt =
10326 xg_get_single_format (tinsn->opcode);
10327
10328 xg_emit_insn_to_buf
10329 (tinsn, single_fmt, immed_instr + size, fragP,
10330 immed_instr - fragP->fr_literal + size, TRUE);
10331 size += xg_get_single_size (tinsn->opcode);
10332 }
10333 }
10334 else
10335 {
10336 xtensa_format single_format;
10337 size = xg_get_single_size (tinsn->opcode);
10338 single_format = xg_get_single_format (tinsn->opcode);
10339 xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
10340 fragP,
10341 immed_instr - fragP->fr_literal, TRUE);
10342#if 0
10343 /* Code to recognize branch-around expansion
10344 so the fragment is properly marked as ending in a
10345 jump. */
10346 if ((((i == istack.ninsn - 2)
10347 && (istack.insn[istack.ninsn-1].insn_type
10348 == ITYPE_LABEL))
10349 || i == istack.ninsn -1)
10350 && xtensa_opcode_is_jump (xtensa_default_isa,
10351 tinsn->opcode) == 1
10352 && fragP->fr_next != NULL
10353 && ! fragP->fr_next->tc_frag_data.is_unreachable)
10354 {
10355 /* Create a new unreachable frag of zero size. */
10356 size_t frag_size = sizeof (fragS);
10357 fragS *new_fragP = (fragS *) xmalloc (frag_size);
10358 memset (new_fragP, 0, frag_size);
10359 new_fragP->fr_address = fragP->fr_next->fr_address;
10360 new_fragP->fr_next = fragP->fr_next;
10361 new_fragP->fr_fix = 0;
10362 new_fragP->fr_var = 0;
10363 new_fragP->fr_type = rs_fill;
10364 new_fragP->tc_frag_data.is_unreachable = TRUE;
10365 /* The rest are zeros.... */
10366 /* Link it in to the chain. */
10367 fragP->fr_next = new_fragP;
10368 }
10369#endif
10370 }
e0001a05 10371 immed_instr += size;
43cd72b9 10372 total_size += size;
e0001a05
NC		 10373 break;
10374 }
10375 }
10376
10377 diff = total_size - old_size;
10378 assert (diff >= 0);
10379 if (diff != 0)
10380 expanded = TRUE;
10381 assert (diff <= fragP->fr_var);
10382 fragP->fr_var -= diff;
10383 fragP->fr_fix += diff;
10384 }
10385
10386 /* Clean it up. */
43cd72b9 10387 xg_free_vinsn (&orig_vinsn);
e0001a05
NC		 10388
10389 /* Check for undefined immediates in LOOP instructions. */
43cd72b9 10390 if (is_loop)
e0001a05
NC		 10391 {
10392 symbolS *sym;
43cd72b9 10393 sym = orig_tinsn.tok[1].X_add_symbol;
e0001a05
NC		 10394 if (sym != NULL && !S_IS_DEFINED (sym))
10395 {
10396 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10397 return;
10398 }
43cd72b9 10399 sym = orig_tinsn.tok[1].X_op_symbol;
e0001a05
NC		 10400 if (sym != NULL && !S_IS_DEFINED (sym))
10401 {
10402 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10403 return;
10404 }
10405 }
10406
43cd72b9
BW		 10407 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
10408 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
e0001a05 10409
43cd72b9 10410 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
e0001a05
NC		 10411 {
10412 /* Add an expansion note on the expanded instruction. */
10413 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
43cd72b9 10414 &orig_tinsn.tok[0], TRUE,
e0001a05 10415 BFD_RELOC_XTENSA_ASM_EXPAND);
e0001a05
NC		 10416 }
10417}
10418
10419
10420/* Add a new fix expression into the desired segment. We have to
10421 switch to that segment to do this. */
10422
10423static fixS *
10424fix_new_exp_in_seg (new_seg, new_subseg,
10425 frag, where, size, exp, pcrel, r_type)
10426 segT new_seg;
10427 subsegT new_subseg;
10428 fragS *frag;
10429 int where;
10430 int size;
10431 expressionS *exp;
10432 int pcrel;
10433 bfd_reloc_code_real_type r_type;
10434{
10435 fixS *new_fix;
10436 segT seg = now_seg;
10437 subsegT subseg = now_subseg;
43cd72b9 10438
e0001a05
NC		 10439 assert (new_seg != 0);
10440 subseg_set (new_seg, new_subseg);
10441
e0001a05
NC		 10442 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
10443 subseg_set (seg, subseg);
10444 return new_fix;
10445}
10446
10447
43cd72b9
BW		 10448/* Relax a loop instruction so that it can span loop >256 bytes.
10449
10450 loop as, .L1
10451 .L0:
10452 rsr as, LEND
10453 wsr as, LBEG
10454 addi as, as, lo8 (label-.L1)
10455 addmi as, as, mid8 (label-.L1)
10456 wsr as, LEND
10457 isync
10458 rsr as, LCOUNT
10459 addi as, as, 1
10460 .L1:
10461 <<body>>
10462 label:
10463*/
e0001a05
NC		 10464
10465static void
43cd72b9 10466convert_frag_immed_finish_loop (segP, fragP, tinsn)
e0001a05
NC		 10467 segT segP;
10468 fragS *fragP;
43cd72b9 10469 TInsn *tinsn;
e0001a05
NC		 10470{
10471 TInsn loop_insn;
10472 TInsn addi_insn;
10473 TInsn addmi_insn;
10474 unsigned long target;
10475 static xtensa_insnbuf insnbuf = NULL;
10476 unsigned int loop_length, loop_length_hi, loop_length_lo;
10477 xtensa_isa isa = xtensa_default_isa;
10478 addressT loop_offset;
10479 addressT addi_offset = 9;
10480 addressT addmi_offset = 12;
43cd72b9
BW		 10481 fragS *next_fragP;
10482 size_t target_count;
e0001a05
NC		 10483
10484 if (!insnbuf)
10485 insnbuf = xtensa_insnbuf_alloc (isa);
10486
10487 /* Get the loop offset. */
43cd72b9 10488 loop_offset = get_expanded_loop_offset (tinsn->opcode);
e0001a05 10489
43cd72b9
BW		 10490 /* Validate that there really is a LOOP at the loop_offset. Because
10491 loops are not bundleable, we can assume that the instruction will be
10492 in slot 0. */
10493 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
10494 tinsn_immed_from_frag (&loop_insn, fragP, 0);
10495
10496 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
e0001a05
NC		 10497 addi_offset += loop_offset;
10498 addmi_offset += loop_offset;
10499
43cd72b9
BW		 10500 assert (tinsn->ntok == 2);
10501 target = get_expression_value (segP, &tinsn->tok[1]);
e0001a05
NC		 10502
10503 know (symbolP);
10504 know (symbolP->sy_frag);
10505 know (!(S_GET_SEGMENT (symbolP) == absolute_section)
10506 || symbol_get_frag (symbolP) == &zero_address_frag);
10507
10508 loop_length = target - (fragP->fr_address + fragP->fr_fix);
10509 loop_length_hi = loop_length & ~0x0ff;
10510 loop_length_lo = loop_length & 0x0ff;
10511 if (loop_length_lo >= 128)
10512 {
10513 loop_length_lo -= 256;
10514 loop_length_hi += 256;
10515 }
10516
43cd72b9 10517 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
e0001a05
NC		 10518 32512. If the loop is larger than that, then we just fail. */
10519 if (loop_length_hi > 32512)
10520 as_bad_where (fragP->fr_file, fragP->fr_line,
10521 _("loop too long for LOOP instruction"));
10522
43cd72b9 10523 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 10524 assert (addi_insn.opcode == xtensa_addi_opcode);
10525
43cd72b9 10526 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
e0001a05
NC		 10527 assert (addmi_insn.opcode == xtensa_addmi_opcode);
10528
10529 set_expr_const (&addi_insn.tok[2], loop_length_lo);
10530 tinsn_to_insnbuf (&addi_insn, insnbuf);
43cd72b9 10531
e0001a05 10532 fragP->tc_frag_data.is_insn = TRUE;
43cd72b9 10533 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 10534
10535 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
10536 tinsn_to_insnbuf (&addmi_insn, insnbuf);
43cd72b9
BW		 10537 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addmi_offset, 0);
10538
10539 /* Walk through all of the frags from here to the loop end
10540 and mark them as no_transform to keep them from being modified
10541 by the linker. If we ever have a relocation for the
10542 addi/addmi of the difference of two symbols we can remove this. */
10543
10544 target_count = 0;
10545 for (next_fragP = fragP; next_fragP != NULL;
10546 next_fragP = next_fragP->fr_next)
10547 {
10548 set_frag_is_no_transform (next_fragP, TRUE);
10549 if (next_fragP->tc_frag_data.is_loop_target)
10550 target_count++;
10551 if (target_count == 2)
10552 break;
10553 }
e0001a05
NC		 10554}
10555
10556
10557static offsetT
10558get_expression_value (segP, exp)
10559 segT segP;
10560 expressionS *exp;
10561{
10562 if (exp->X_op == O_constant)
10563 return exp->X_add_number;
10564 if (exp->X_op == O_symbol)
10565 {
10566 /* Find the fragment. */
10567 symbolS *sym = exp->X_add_symbol;
10568
10569 assert (S_GET_SEGMENT (sym) == segP
10570 || S_GET_SEGMENT (sym) == absolute_section);
10571
10572 return (S_GET_VALUE (sym) + exp->X_add_number);
10573 }
10574 as_bad (_("invalid expression evaluation type %d"), exp->X_op);
10575 return 0;
10576}
10577
10578\f
e0001a05
NC		 10579static subseg_map *sseg_map = NULL;
10580
10581
10582static unsigned
10583get_last_insn_flags (seg, subseg)
10584 segT seg;
10585 subsegT subseg;
10586{
43cd72b9
BW		 10587 subseg_map *subseg_e = get_subseg_info (seg, subseg);
10588 return subseg_e->flags;
e0001a05
NC		 10589}
10590
10591
43cd72b9
BW		 10592static subseg_map *
10593get_subseg_info (seg, subseg)
e0001a05
NC		 10594 segT seg;
10595 subsegT subseg;
e0001a05
NC		 10596{
10597 subseg_map *subseg_e;
10598
10599 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
e0001a05 10600 {
43cd72b9
BW		 10601 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
10602 return subseg_e;
e0001a05 10603 }
43cd72b9
BW		 10604
10605 subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
10606 memset (subseg_e, 0, sizeof (subseg_map));
10607 subseg_e->seg = seg;
10608 subseg_e->subseg = subseg;
10609 subseg_e->flags = 0;
10610 /* Start off considering every branch target very important. */
10611 subseg_e->cur_target_freq = 1.0;
10612 subseg_e->cur_total_freq = 1.0;
10613 subseg_e->next = sseg_map;
10614 sseg_map = subseg_e;
10615
10616 return subseg_e;
10617}
e0001a05 10618
43cd72b9
BW		 10619static void
10620set_last_insn_flags (seg, subseg, fl, val)
10621 segT seg;
10622 subsegT subseg;
10623 unsigned fl;
10624 bfd_boolean val;
10625{
10626 subseg_map *subseg_e = get_subseg_info (seg, subseg);
e0001a05
NC		 10627 if (val)
10628 subseg_e->flags |= fl;
10629 else
10630 subseg_e->flags &= ~fl;
10631}
10632
10633\f
10634/* Segment Lists and emit_state Stuff. */
10635
10636/* Remove the segment from the global sections list. */
10637
10638static void
10639xtensa_remove_section (sec)
10640 segT sec;
10641{
10642 /* Handle brain-dead bfd_section_list_remove macro, which
10643 expect the address of the prior section's "next" field, not
10644 just the address of the section to remove. */
10645
10646 segT *ps_next_ptr = &stdoutput->sections;
10647 while (*ps_next_ptr != sec && *ps_next_ptr != NULL)
10648 ps_next_ptr = &(*ps_next_ptr)->next;
10649
10650 assert (*ps_next_ptr != NULL);
10651
10652 bfd_section_list_remove (stdoutput, ps_next_ptr);
10653}
10654
10655
10656static void
10657xtensa_insert_section (after_sec, sec)
10658 segT after_sec;
10659 segT sec;
10660{
10661 segT *after_sec_next;
10662 if (after_sec == NULL)
10663 after_sec_next = &stdoutput->sections;
10664 else
10665 after_sec_next = &after_sec->next;
10666
10667 bfd_section_list_insert (stdoutput, after_sec_next, sec);
10668}
10669
10670
10671static void
10672xtensa_move_seg_list_to_beginning (head)
10673 seg_list *head;
10674{
10675 head = head->next;
10676 while (head)
10677 {
10678 segT literal_section = head->seg;
10679
10680 /* Move the literal section to the front of the section list. */
10681 assert (literal_section);
10682 xtensa_remove_section (literal_section);
10683 xtensa_insert_section (NULL, literal_section);
10684
10685 head = head->next;
10686 }
10687}
10688
10689
10690void
10691xtensa_move_literals ()
10692{
10693 seg_list *segment;
10694 frchainS *frchain_from, *frchain_to;
10695 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
10696 fragS **frag_splice;
10697 emit_state state;
10698 segT dest_seg;
10699 fixS *fix, *next_fix, **fix_splice;
82e7541d 10700 sym_list *lit;
e0001a05 10701
a7877748
BW		 10702 mark_literal_frags (literal_head->next);
10703 mark_literal_frags (init_literal_head->next);
10704 mark_literal_frags (fini_literal_head->next);
e0001a05
NC		 10705
10706 if (use_literal_section)
10707 return;
10708
10709 segment = literal_head->next;
10710 while (segment)
10711 {
10712 frchain_from = seg_info (segment->seg)->frchainP;
10713 search_frag = frchain_from->frch_root;
10714 literal_pool = NULL;
10715 frchain_to = NULL;
10716 frag_splice = &(frchain_from->frch_root);
10717
10718 while (!search_frag->tc_frag_data.literal_frag)
10719 {
10720 assert (search_frag->fr_fix == 0
10721 || search_frag->fr_type == rs_align);
10722 search_frag = search_frag->fr_next;
10723 }
10724
10725 assert (search_frag->tc_frag_data.literal_frag->fr_subtype
10726 == RELAX_LITERAL_POOL_BEGIN);
10727 xtensa_switch_section_emit_state (&state, segment->seg, 0);
10728
10729 /* Make sure that all the frags in this series are closed, and
10730 that there is at least one left over of zero-size. This
10731 prevents us from making a segment with an frchain without any
10732 frags in it. */
10733 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10734 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 10735 last_frag = frag_now;
10736 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10737 xtensa_set_frag_assembly_state (frag_now);
e0001a05 10738
43cd72b9 10739 while (search_frag != frag_now)
e0001a05
NC		 10740 {
10741 next_frag = search_frag->fr_next;
10742
43cd72b9 10743 /* First, move the frag out of the literal section and
e0001a05
NC		 10744 to the appropriate place. */
10745 if (search_frag->tc_frag_data.literal_frag)
10746 {
10747 literal_pool = search_frag->tc_frag_data.literal_frag;
10748 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
43cd72b9 10749 /* Note that we set this fr_var to be a fix
e0001a05
NC		 10750 chain when we created the literal pool location
10751 as RELAX_LITERAL_POOL_BEGIN. */
10752 frchain_to = (frchainS *) literal_pool->fr_var;
10753 }
10754 insert_after = literal_pool;
43cd72b9 10755
e0001a05
NC		 10756 while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
10757 insert_after = insert_after->fr_next;
10758
10759 dest_seg = (segT) insert_after->fr_next->fr_var;
43cd72b9 10760
e0001a05
NC		 10761 *frag_splice = next_frag;
10762 search_frag->fr_next = insert_after->fr_next;
10763 insert_after->fr_next = search_frag;
10764 search_frag->tc_frag_data.lit_seg = dest_seg;
10765
10766 /* Now move any fixups associated with this frag to the
10767 right section. */
10768 fix = frchain_from->fix_root;
10769 fix_splice = &(frchain_from->fix_root);
10770 while (fix)
10771 {
10772 next_fix = fix->fx_next;
10773 if (fix->fx_frag == search_frag)
10774 {
10775 *fix_splice = next_fix;
10776 fix->fx_next = frchain_to->fix_root;
10777 frchain_to->fix_root = fix;
10778 if (frchain_to->fix_tail == NULL)
10779 frchain_to->fix_tail = fix;
10780 }
10781 else
10782 fix_splice = &(fix->fx_next);
10783 fix = next_fix;
10784 }
10785 search_frag = next_frag;
10786 }
10787
10788 if (frchain_from->fix_root != NULL)
10789 {
10790 frchain_from = seg_info (segment->seg)->frchainP;
10791 as_warn (_("fixes not all moved from %s"), segment->seg->name);
10792
10793 assert (frchain_from->fix_root == NULL);
10794 }
10795 frchain_from->fix_tail = NULL;
10796 xtensa_restore_emit_state (&state);
10797 segment = segment->next;
10798 }
10799
82e7541d
BW		 10800 /* Now fix up the SEGMENT value for all the literal symbols. */
10801 for (lit = literal_syms; lit; lit = lit->next)
10802 {
10803 symbolS *lit_sym = lit->sym;
10804 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
43cd72b9
BW		 10805 if (dest_seg)
10806 S_SET_SEGMENT (lit_sym, dest_seg);
82e7541d 10807 }
e0001a05
NC		 10808}
10809
10810
a7877748
BW		 10811/* Walk over all the frags for segments in a list and mark them as
10812 containing literals. As clunky as this is, we can't rely on frag_var
10813 and frag_variant to get called in all situations. */
10814
10815static void
10816mark_literal_frags (segment)
10817 seg_list *segment;
10818{
10819 frchainS *frchain_from;
10820 fragS *search_frag;
10821
10822 while (segment)
10823 {
10824 frchain_from = seg_info (segment->seg)->frchainP;
10825 search_frag = frchain_from->frch_root;
10826 while (search_frag)
10827 {
10828 search_frag->tc_frag_data.is_literal = TRUE;
10829 search_frag = search_frag->fr_next;
10830 }
10831 segment = segment->next;
10832 }
10833}
10834
10835
e0001a05
NC		 10836static void
10837xtensa_reorder_seg_list (head, after)
10838 seg_list *head;
10839 segT after;
10840{
10841 /* Move all of the sections in the section list to come
10842 after "after" in the gnu segment list. */
10843
10844 head = head->next;
10845 while (head)
10846 {
10847 segT literal_section = head->seg;
10848
10849 /* Move the literal section after "after". */
10850 assert (literal_section);
10851 if (literal_section != after)
10852 {
10853 xtensa_remove_section (literal_section);
10854 xtensa_insert_section (after, literal_section);
10855 }
10856
10857 head = head->next;
10858 }
10859}
10860
10861
10862/* Push all the literal segments to the end of the gnu list. */
10863
10864void
10865xtensa_reorder_segments ()
10866{
10867 segT sec;
10868 segT last_sec;
10869 int old_count = 0;
10870 int new_count = 0;
10871
10872 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10873 old_count++;
10874
10875 /* Now that we have the last section, push all the literal
10876 sections to the end. */
10877 last_sec = get_last_sec ();
10878 xtensa_reorder_seg_list (literal_head, last_sec);
10879 xtensa_reorder_seg_list (init_literal_head, last_sec);
10880 xtensa_reorder_seg_list (fini_literal_head, last_sec);
10881
10882 /* Now perform the final error check. */
10883 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10884 new_count++;
10885 assert (new_count == old_count);
10886}
10887
10888
10889segT
10890get_last_sec ()
10891{
10892 segT last_sec = stdoutput->sections;
10893 while (last_sec->next != NULL)
10894 last_sec = last_sec->next;
10895
10896 return last_sec;
10897}
10898
10899
10900/* Change the emit state (seg, subseg, and frag related stuff) to the
10901 correct location. Return a emit_state which can be passed to
10902 xtensa_restore_emit_state to return to current fragment. */
10903
10904void
10905xtensa_switch_to_literal_fragment (result)
10906 emit_state *result;
43cd72b9
BW		 10907{
10908 if (directive_state[directive_absolute_literals])
10909 {
10910 cache_literal_section (0, default_lit_sections.lit4_seg_name,
10911 &default_lit_sections.lit4_seg, FALSE);
10912 xtensa_switch_section_emit_state (result,
10913 default_lit_sections.lit4_seg, 0);
10914 }
10915 else
10916 xtensa_switch_to_non_abs_literal_fragment (result);
10917
10918 /* Do a 4-byte align here. */
10919 frag_align (2, 0, 0);
10920 record_alignment (now_seg, 2);
10921}
10922
10923
10924void
10925xtensa_switch_to_non_abs_literal_fragment (result)
10926 emit_state *result;
e0001a05
NC		 10927{
10928 /* When we mark a literal pool location, we want to put a frag in
10929 the literal pool that points to it. But to do that, we want to
10930 switch_to_literal_fragment. But literal sections don't have
10931 literal pools, so their location is always null, so we would
10932 recurse forever. This is kind of hacky, but it works. */
10933
10934 static bfd_boolean recursive = FALSE;
10935 fragS *pool_location = get_literal_pool_location (now_seg);
10936 bfd_boolean is_init =
10937 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
10938
10939 bfd_boolean is_fini =
10940 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
e0001a05 10941
43cd72b9
BW		 10942 if (pool_location == NULL
10943 && !use_literal_section
e0001a05
NC		 10944 && !recursive
10945 && !is_init && ! is_fini)
10946 {
43cd72b9 10947 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
e0001a05 10948 recursive = TRUE;
61846f28 10949 xtensa_mark_literal_pool_location ();
e0001a05
NC		 10950 recursive = FALSE;
10951 }
10952
10953 /* Special case: If we are in the ".fini" or ".init" section, then
10954 we will ALWAYS be generating to the ".fini.literal" and
10955 ".init.literal" sections. */
10956
10957 if (is_init)
10958 {
10959 cache_literal_section (init_literal_head,
10960 default_lit_sections.init_lit_seg_name,
43cd72b9 10961 &default_lit_sections.init_lit_seg, TRUE);
e0001a05
NC		 10962 xtensa_switch_section_emit_state (result,
10963 default_lit_sections.init_lit_seg, 0);
10964 }
10965 else if (is_fini)
10966 {
10967 cache_literal_section (fini_literal_head,
10968 default_lit_sections.fini_lit_seg_name,
43cd72b9 10969 &default_lit_sections.fini_lit_seg, TRUE);
e0001a05
NC		 10970 xtensa_switch_section_emit_state (result,
10971 default_lit_sections.fini_lit_seg, 0);
10972 }
43cd72b9 10973 else
e0001a05
NC		 10974 {
10975 cache_literal_section (literal_head,
10976 default_lit_sections.lit_seg_name,
43cd72b9 10977 &default_lit_sections.lit_seg, TRUE);
e0001a05
NC		 10978 xtensa_switch_section_emit_state (result,
10979 default_lit_sections.lit_seg, 0);
10980 }
10981
43cd72b9
BW		 10982 if (!use_literal_section
10983 && !is_init && !is_fini
10984 && get_literal_pool_location (now_seg) != pool_location)
e0001a05
NC		 10985 {
10986 /* Close whatever frag is there. */
10987 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10988 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 10989 frag_now->tc_frag_data.literal_frag = pool_location;
10990 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10991 xtensa_set_frag_assembly_state (frag_now);
e0001a05 10992 }
e0001a05
NC		 10993}
10994
10995
10996/* Call this function before emitting data into the literal section.
10997 This is a helper function for xtensa_switch_to_literal_fragment.
10998 This is similar to a .section new_now_seg subseg. */
10999
11000void
11001xtensa_switch_section_emit_state (state, new_now_seg, new_now_subseg)
11002 emit_state *state;
11003 segT new_now_seg;
11004 subsegT new_now_subseg;
11005{
11006 state->name = now_seg->name;
11007 state->now_seg = now_seg;
11008 state->now_subseg = now_subseg;
11009 state->generating_literals = generating_literals;
11010 generating_literals++;
11011 subseg_new (segment_name (new_now_seg), new_now_subseg);
11012}
11013
11014
11015/* Use to restore the emitting into the normal place. */
11016
11017void
11018xtensa_restore_emit_state (state)
11019 emit_state *state;
11020{
11021 generating_literals = state->generating_literals;
11022 subseg_new (state->name, state->now_subseg);
11023}
11024
11025
11026/* Get a segment of a given name. If the segment is already
11027 present, return it; otherwise, create a new one. */
11028
11029static void
43cd72b9 11030cache_literal_section (head, name, seg, is_code)
e0001a05
NC		 11031 seg_list *head;
11032 const char *name;
11033 segT *seg;
43cd72b9 11034 bfd_boolean is_code;
e0001a05
NC		 11035{
11036 segT current_section = now_seg;
11037 int current_subsec = now_subseg;
11038
11039 if (*seg != 0)
11040 return;
43cd72b9 11041 *seg = retrieve_literal_seg (head, name, is_code);
e0001a05
NC		 11042 subseg_set (current_section, current_subsec);
11043}
11044
11045
11046/* Get a segment of a given name. If the segment is already
11047 present, return it; otherwise, create a new one. */
11048
11049static segT
43cd72b9 11050retrieve_literal_seg (head, name, is_code)
e0001a05
NC		 11051 seg_list *head;
11052 const char *name;
43cd72b9 11053 bfd_boolean is_code;
e0001a05
NC		 11054{
11055 segT ret = 0;
11056
e0001a05
NC		 11057 ret = seg_present (name);
11058 if (!ret)
11059 {
11060 ret = subseg_new (name, (subsegT) 0);
43cd72b9
BW		 11061 if (head)
11062 add_seg_list (head, ret);
e0001a05 11063 bfd_set_section_flags (stdoutput, ret, SEC_HAS_CONTENTS |
43cd72b9
BW		 11064 SEC_READONLY | SEC_ALLOC | SEC_LOAD
11065 | (is_code ? SEC_CODE : SEC_DATA));
e0001a05
NC		 11066 bfd_set_section_alignment (stdoutput, ret, 2);
11067 }
11068
11069 return ret;
11070}
11071
11072
11073/* Return a segment of a given name if it is present. */
11074
11075static segT
11076seg_present (name)
11077 const char *name;
11078{
11079 segT seg;
11080 seg = stdoutput->sections;
11081
11082 while (seg)
11083 {
11084 if (!strcmp (segment_name (seg), name))
11085 return seg;
11086 seg = seg->next;
11087 }
11088
11089 return 0;
11090}
11091
11092
11093/* Add a segment to a segment list. */
11094
11095static void
11096add_seg_list (head, seg)
11097 seg_list *head;
11098 segT seg;
11099{
11100 seg_list *n;
11101 n = (seg_list *) xmalloc (sizeof (seg_list));
11102 assert (n);
11103
11104 n->seg = seg;
11105 n->next = head->next;
11106 head->next = n;
11107}
11108
43cd72b9
BW		 11109\f
11110/* Property Tables Stuff. */
11111
11112/* This function is only meaningful after xtensa_move_literals. */
11113
11114static bfd_boolean
11115get_frag_is_literal (fragP)
11116 const fragS *fragP;
11117{
11118 assert (fragP != NULL);
11119 return fragP->tc_frag_data.is_literal;
11120}
11121
11122
11123static bfd_boolean
11124get_frag_is_insn (fragP)
11125 const fragS *fragP;
11126{
11127 assert (fragP != NULL);
11128 return fragP->tc_frag_data.is_insn;
11129}
11130
11131
11132bfd_boolean
11133get_frag_is_no_transform (fragP)
11134 fragS *fragP;
11135{
11136 return fragP->tc_frag_data.is_no_transform;
11137}
11138
11139
11140void
11141set_frag_is_specific_opcode (fragP, is_specific_opcode)
11142 fragS *fragP;
11143 bfd_boolean is_specific_opcode;
11144{
11145 fragP->tc_frag_data.is_specific_opcode = is_specific_opcode;
11146}
11147
11148
11149void
11150set_frag_is_no_transform (fragP, is_no_transform)
11151 fragS *fragP;
11152 bfd_boolean is_no_transform;
11153{
11154 fragP->tc_frag_data.is_no_transform = is_no_transform;
11155}
11156
11157
11158static void
11159xtensa_create_property_segments (property_function, end_property_function,
11160 section_name_base, sec_type)
11161 frag_predicate property_function;
11162 frag_predicate end_property_function;
11163 const char *section_name_base;
11164 xt_section_type sec_type;
11165{
11166 segT *seclist;
11167
11168 /* Walk over all of the current segments.
11169 Walk over each fragment
11170 For each non-empty fragment,
11171 Build a property record (append where possible). */
11172
11173 for (seclist = &stdoutput->sections;
11174 seclist && *seclist;
11175 seclist = &(*seclist)->next)
11176 {
11177 segT sec = *seclist;
11178 flagword flags;
11179
11180 flags = bfd_get_section_flags (stdoutput, sec);
11181 if (flags & SEC_DEBUGGING)
11182 continue;
11183 if (!(flags & SEC_ALLOC))
11184 continue;
11185
11186 if (section_has_property (sec, property_function))
11187 {
11188 char *property_section_name =
11189 xtensa_get_property_section_name (sec, section_name_base);
11190 segT insn_sec = retrieve_xtensa_section (property_section_name);
11191 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
11192 xtensa_block_info **xt_blocks =
11193 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11194 /* Walk over all of the frchains here and add new sections. */
11195 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
11196 end_property_function);
11197 }
11198 }
11199
11200 /* Now we fill them out.... */
11201
11202 for (seclist = &stdoutput->sections;
11203 seclist && *seclist;
11204 seclist = &(*seclist)->next)
11205 {
11206 segment_info_type *seginfo;
11207 xtensa_block_info *block;
11208 segT sec = *seclist;
11209
11210 seginfo = seg_info (sec);
11211 block = seginfo->tc_segment_info_data.blocks[sec_type];
11212
11213 if (block)
11214 {
11215 xtensa_block_info *cur_block;
11216 /* This is a section with some data. */
11217 int num_recs = 0;
11218 size_t rec_size;
11219
11220 for (cur_block = block; cur_block; cur_block = cur_block->next)
11221 num_recs++;
11222
11223 rec_size = num_recs * 8;
11224 bfd_set_section_size (stdoutput, sec, rec_size);
11225
11226 /* In order to make this work with the assembler, we have to
11227 build some frags and then build the "fixups" for it. It
11228 would be easier to just set the contents then set the
11229 arlents. */
11230
11231 if (num_recs)
11232 {
11233 /* Allocate a fragment and leak it. */
11234 fragS *fragP;
11235 size_t frag_size;
11236 fixS *fixes;
11237 frchainS *frchainP;
11238 int i;
11239 char *frag_data;
11240
11241 frag_size = sizeof (fragS) + rec_size;
11242 fragP = (fragS *) xmalloc (frag_size);
e0001a05 11243
43cd72b9
BW		 11244 memset (fragP, 0, frag_size);
11245 fragP->fr_address = 0;
11246 fragP->fr_next = NULL;
11247 fragP->fr_fix = rec_size;
11248 fragP->fr_var = 0;
11249 fragP->fr_type = rs_fill;
11250 /* The rest are zeros. */
e0001a05 11251
43cd72b9
BW		 11252 frchainP = seginfo->frchainP;
11253 frchainP->frch_root = fragP;
11254 frchainP->frch_last = fragP;
e0001a05 11255
43cd72b9
BW		 11256 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
11257 memset (fixes, 0, sizeof (fixS) * num_recs);
e0001a05 11258
43cd72b9
BW		 11259 seginfo->fix_root = fixes;
11260 seginfo->fix_tail = &fixes[num_recs - 1];
11261 cur_block = block;
11262 frag_data = &fragP->fr_literal[0];
11263 for (i = 0; i < num_recs; i++)
11264 {
11265 fixS *fix = &fixes[i];
11266 assert (cur_block);
e0001a05 11267
43cd72b9
BW		 11268 /* Write the fixup. */
11269 if (i != num_recs - 1)
11270 fix->fx_next = &fixes[i + 1];
11271 else
11272 fix->fx_next = NULL;
11273 fix->fx_size = 4;
11274 fix->fx_done = 0;
11275 fix->fx_frag = fragP;
11276 fix->fx_where = i * 8;
11277 fix->fx_addsy = section_symbol (cur_block->sec);
11278 fix->fx_offset = cur_block->offset;
11279 fix->fx_r_type = BFD_RELOC_32;
11280 fix->fx_file = "Internal Assembly";
11281 fix->fx_line = 0;
e0001a05 11282
43cd72b9
BW		 11283 /* Write the length. */
11284 md_number_to_chars (&frag_data[4 + 8 * i],
11285 cur_block->size, 4);
11286 cur_block = cur_block->next;
11287 }
11288 }
11289 }
11290 }
e0001a05
NC		 11291}
11292
11293
43cd72b9
BW		 11294void
11295xtensa_create_xproperty_segments (flag_fn, section_name_base, sec_type)
11296 frag_flags_fn flag_fn;
11297 const char *section_name_base;
e0001a05
NC		 11298 xt_section_type sec_type;
11299{
11300 segT *seclist;
11301
11302 /* Walk over all of the current segments.
43cd72b9
BW		 11303 Walk over each fragment.
11304 For each fragment that has instructions,
11305 build an instruction record (append where possible). */
e0001a05
NC		 11306
11307 for (seclist = &stdoutput->sections;
11308 seclist && *seclist;
11309 seclist = &(*seclist)->next)
11310 {
11311 segT sec = *seclist;
43cd72b9
BW		 11312 flagword flags;
11313
11314 flags = bfd_get_section_flags (stdoutput, sec);
11315 if (flags & SEC_DEBUGGING)
11316 continue;
11317 if (!(flags & SEC_ALLOC))
11318 continue;
11319
11320 if (section_has_xproperty (sec, flag_fn))
e0001a05 11321 {
b614a702
BW		 11322 char *property_section_name =
11323 xtensa_get_property_section_name (sec, section_name_base);
e0001a05
NC		 11324 segT insn_sec = retrieve_xtensa_section (property_section_name);
11325 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
43cd72b9 11326 xtensa_block_info **xt_blocks =
e0001a05
NC		 11327 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11328 /* Walk over all of the frchains here and add new sections. */
43cd72b9 11329 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
e0001a05
NC		 11330 }
11331 }
11332
11333 /* Now we fill them out.... */
11334
11335 for (seclist = &stdoutput->sections;
11336 seclist && *seclist;
11337 seclist = &(*seclist)->next)
11338 {
11339 segment_info_type *seginfo;
11340 xtensa_block_info *block;
11341 segT sec = *seclist;
43cd72b9 11342
e0001a05
NC		 11343 seginfo = seg_info (sec);
11344 block = seginfo->tc_segment_info_data.blocks[sec_type];
11345
11346 if (block)
11347 {
11348 xtensa_block_info *cur_block;
11349 /* This is a section with some data. */
43cd72b9 11350 int num_recs = 0;
e0001a05
NC		 11351 size_t rec_size;
11352
11353 for (cur_block = block; cur_block; cur_block = cur_block->next)
11354 num_recs++;
11355
43cd72b9 11356 rec_size = num_recs * (8 + 4);
e0001a05
NC		 11357 bfd_set_section_size (stdoutput, sec, rec_size);
11358
43cd72b9
BW		 11359 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11360
11361 /* In order to make this work with the assembler, we have to build
11362 some frags then build the "fixups" for it. It would be easier to
11363 just set the contents then set the arlents. */
e0001a05
NC		 11364
11365 if (num_recs)
11366 {
43cd72b9 11367 /* Allocate a fragment and (unfortunately) leak it. */
e0001a05
NC		 11368 fragS *fragP;
11369 size_t frag_size;
11370 fixS *fixes;
11371 frchainS *frchainP;
43cd72b9 11372 int i;
e0001a05
NC		 11373 char *frag_data;
11374
11375 frag_size = sizeof (fragS) + rec_size;
11376 fragP = (fragS *) xmalloc (frag_size);
11377
11378 memset (fragP, 0, frag_size);
11379 fragP->fr_address = 0;
11380 fragP->fr_next = NULL;
11381 fragP->fr_fix = rec_size;
11382 fragP->fr_var = 0;
11383 fragP->fr_type = rs_fill;
43cd72b9 11384 /* The rest are zeros. */
e0001a05
NC		 11385
11386 frchainP = seginfo->frchainP;
11387 frchainP->frch_root = fragP;
11388 frchainP->frch_last = fragP;
11389
11390 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
11391 memset (fixes, 0, sizeof (fixS) * num_recs);
11392
11393 seginfo->fix_root = fixes;
11394 seginfo->fix_tail = &fixes[num_recs - 1];
11395 cur_block = block;
11396 frag_data = &fragP->fr_literal[0];
11397 for (i = 0; i < num_recs; i++)
11398 {
11399 fixS *fix = &fixes[i];
11400 assert (cur_block);
11401
11402 /* Write the fixup. */
11403 if (i != num_recs - 1)
11404 fix->fx_next = &fixes[i + 1];
11405 else
11406 fix->fx_next = NULL;
11407 fix->fx_size = 4;
11408 fix->fx_done = 0;
11409 fix->fx_frag = fragP;
43cd72b9 11410 fix->fx_where = i * (8 + 4);
e0001a05
NC		 11411 fix->fx_addsy = section_symbol (cur_block->sec);
11412 fix->fx_offset = cur_block->offset;
11413 fix->fx_r_type = BFD_RELOC_32;
11414 fix->fx_file = "Internal Assembly";
11415 fix->fx_line = 0;
11416
11417 /* Write the length. */
43cd72b9 11418 md_number_to_chars (&frag_data[4 + (8+4) * i],
e0001a05 11419 cur_block->size, 4);
43cd72b9
BW		 11420 md_number_to_chars (&frag_data[8 + (8+4) * i],
11421 frag_flags_to_number (&cur_block->flags),
11422 4);
e0001a05
NC		 11423 cur_block = cur_block->next;
11424 }
11425 }
11426 }
11427 }
11428}
11429
11430
11431segment_info_type *
11432retrieve_segment_info (seg)
11433 segT seg;
11434{
11435 segment_info_type *seginfo;
11436 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
11437 if (!seginfo)
11438 {
11439 frchainS *frchainP;
11440
11441 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
11442 memset ((PTR) seginfo, 0, sizeof (*seginfo));
11443 seginfo->fix_root = NULL;
11444 seginfo->fix_tail = NULL;
11445 seginfo->bfd_section = seg;
11446 seginfo->sym = 0;
11447 /* We will not be dealing with these, only our special ones. */
11448#if 0
11449 if (seg == bfd_abs_section_ptr)
11450 abs_seg_info = seginfo;
11451 else if (seg == bfd_und_section_ptr)
11452 und_seg_info = seginfo;
11453 else
11454#endif
11455 bfd_set_section_userdata (stdoutput, seg, (PTR) seginfo);
11456#if 0
11457 seg_fix_rootP = &segment_info[seg].fix_root;
11458 seg_fix_tailP = &segment_info[seg].fix_tail;
11459#endif
11460
11461 frchainP = (frchainS *) xmalloc (sizeof (frchainS));
11462 frchainP->frch_root = NULL;
11463 frchainP->frch_last = NULL;
11464 frchainP->frch_next = NULL;
11465 frchainP->frch_seg = seg;
11466 frchainP->frch_subseg = 0;
11467 frchainP->fix_root = NULL;
11468 frchainP->fix_tail = NULL;
11469 /* Do not init the objstack. */
11470 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
11471 /* frchainP->frch_frag_now = fragP; */
11472 frchainP->frch_frag_now = NULL;
11473
11474 seginfo->frchainP = frchainP;
11475 }
11476
11477 return seginfo;
11478}
11479
11480
11481segT
11482retrieve_xtensa_section (sec_name)
11483 char *sec_name;
11484{
11485 bfd *abfd = stdoutput;
11486 flagword flags, out_flags, link_once_flags;
11487 segT s;
11488
11489 flags = bfd_get_section_flags (abfd, now_seg);
11490 link_once_flags = (flags & SEC_LINK_ONCE);
11491 if (link_once_flags)
11492 link_once_flags |= (flags & SEC_LINK_DUPLICATES);
11493 out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
11494
11495 s = bfd_make_section_old_way (abfd, sec_name);
11496 if (s == NULL)
11497 as_bad (_("could not create section %s"), sec_name);
11498 if (!bfd_set_section_flags (abfd, s, out_flags))
11499 as_bad (_("invalid flag combination on section %s"), sec_name);
11500
11501 return s;
11502}
11503
11504
11505bfd_boolean
11506section_has_property (sec, property_function)
11507 segT sec;
11508 frag_predicate property_function;
11509{
11510 segment_info_type *seginfo = seg_info (sec);
11511 fragS *fragP;
11512
11513 if (seginfo && seginfo->frchainP)
11514 {
11515 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
11516 {
11517 if (property_function (fragP)
11518 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
11519 return TRUE;
11520 }
11521 }
11522 return FALSE;
11523}
11524
11525
43cd72b9
BW		 11526bfd_boolean
11527section_has_xproperty (sec, property_function)
11528 segT sec;
11529 frag_flags_fn property_function;
11530{
11531 segment_info_type *seginfo = seg_info (sec);
11532 fragS *fragP;
11533
11534 if (seginfo && seginfo->frchainP)
11535 {
11536 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
11537 {
11538 frag_flags prop_flags;
11539 property_function (fragP, &prop_flags);
11540 if (!xtensa_frag_flags_is_empty (&prop_flags))
11541 return TRUE;
11542 }
11543 }
11544 return FALSE;
11545}
11546
11547
e0001a05
NC		 11548/* Two types of block sections exist right now: literal and insns. */
11549
11550void
43cd72b9
BW		 11551add_xt_block_frags (sec, xt_block_sec, xt_block, property_function,
11552 end_property_function)
e0001a05
NC		 11553 segT sec;
11554 segT xt_block_sec;
11555 xtensa_block_info **xt_block;
11556 frag_predicate property_function;
43cd72b9 11557 frag_predicate end_property_function;
e0001a05
NC		 11558{
11559 segment_info_type *seg_info;
11560 segment_info_type *xt_seg_info;
11561 bfd_vma seg_offset;
11562 fragS *fragP;
11563
11564 xt_seg_info = retrieve_segment_info (xt_block_sec);
11565 seg_info = retrieve_segment_info (sec);
11566
11567 /* Build it if needed. */
11568 while (*xt_block != NULL)
11569 xt_block = &(*xt_block)->next;
11570 /* We are either at NULL at the beginning or at the end. */
11571
11572 /* Walk through the frags. */
11573 seg_offset = 0;
11574
11575 if (seg_info->frchainP)
11576 {
11577 for (fragP = seg_info->frchainP->frch_root;
11578 fragP;
11579 fragP = fragP->fr_next)
11580 {
11581 if (property_function (fragP)
11582 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
11583 {
11584 if (*xt_block != NULL)
11585 {
11586 if ((*xt_block)->offset + (*xt_block)->size
11587 == fragP->fr_address)
11588 (*xt_block)->size += fragP->fr_fix;
11589 else
11590 xt_block = &((*xt_block)->next);
11591 }
11592 if (*xt_block == NULL)
11593 {
43cd72b9
BW		 11594 xtensa_block_info *new_block = (xtensa_block_info *)
11595 xmalloc (sizeof (xtensa_block_info));
11596 new_block->sec = sec;
11597 new_block->offset = fragP->fr_address;
11598 new_block->size = fragP->fr_fix;
11599 new_block->next = NULL;
11600 xtensa_frag_flags_init (&new_block->flags);
11601 *xt_block = new_block;
11602 }
11603 if (end_property_function
11604 && end_property_function (fragP))
11605 {
11606 xt_block = &((*xt_block)->next);
11607 }
11608 }
11609 }
11610 }
11611}
11612
11613
11614/* Break the encapsulation of add_xt_prop_frags here. */
11615
11616bfd_boolean
11617xtensa_frag_flags_is_empty (prop_flags)
11618 const frag_flags *prop_flags;
11619{
11620 if (prop_flags->is_literal
11621 || prop_flags->is_insn
11622 || prop_flags->is_data
11623 || prop_flags->is_unreachable)
11624 return FALSE;
11625 return TRUE;
11626}
11627
11628
11629void
11630xtensa_frag_flags_init (prop_flags)
11631 frag_flags *prop_flags;
11632{
11633 memset (prop_flags, 0, sizeof (frag_flags));
11634}
11635
11636
11637void
11638get_frag_property_flags (fragP, prop_flags)
11639 const fragS *fragP;
11640 frag_flags *prop_flags;
11641{
11642 xtensa_frag_flags_init (prop_flags);
11643 if (fragP->tc_frag_data.is_literal)
11644 prop_flags->is_literal = TRUE;
11645 if (fragP->tc_frag_data.is_unreachable)
11646 {
11647 prop_flags->is_unreachable = TRUE;
11648 }
11649 else if (fragP->tc_frag_data.is_insn)
11650 {
11651 prop_flags->is_insn = TRUE;
11652 if (fragP->tc_frag_data.is_loop_target)
11653 prop_flags->insn.is_loop_target = TRUE;
11654 if (fragP->tc_frag_data.is_branch_target)
11655 prop_flags->insn.is_branch_target = TRUE;
11656 if (fragP->tc_frag_data.is_specific_opcode
11657 || fragP->tc_frag_data.is_no_transform)
11658 prop_flags->insn.is_no_transform = TRUE;
11659 if (fragP->tc_frag_data.is_no_density)
11660 prop_flags->insn.is_no_density = TRUE;
11661 if (fragP->tc_frag_data.use_absolute_literals)
11662 prop_flags->insn.is_abslit = TRUE;
11663 }
11664 if (fragP->tc_frag_data.is_align)
11665 {
11666 prop_flags->is_align = TRUE;
11667 prop_flags->alignment = fragP->tc_frag_data.alignment;
11668 if (xtensa_frag_flags_is_empty (prop_flags))
11669 prop_flags->is_data = TRUE;
11670 }
11671}
11672
11673
11674bfd_vma
11675frag_flags_to_number (prop_flags)
11676 const frag_flags *prop_flags;
11677{
11678 bfd_vma num = 0;
11679 if (prop_flags->is_literal)
11680 num |= XTENSA_PROP_LITERAL;
11681 if (prop_flags->is_insn)
11682 num |= XTENSA_PROP_INSN;
11683 if (prop_flags->is_data)
11684 num |= XTENSA_PROP_DATA;
11685 if (prop_flags->is_unreachable)
11686 num |= XTENSA_PROP_UNREACHABLE;
11687 if (prop_flags->insn.is_loop_target)
11688 num |= XTENSA_PROP_INSN_LOOP_TARGET;
11689 if (prop_flags->insn.is_branch_target)
11690 {
11691 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
11692 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
11693 }
11694
11695 if (prop_flags->insn.is_no_density)
11696 num |= XTENSA_PROP_INSN_NO_DENSITY;
11697 if (prop_flags->insn.is_no_transform)
11698 num |= XTENSA_PROP_INSN_NO_TRANSFORM;
11699 if (prop_flags->insn.is_no_reorder)
11700 num |= XTENSA_PROP_INSN_NO_REORDER;
11701 if (prop_flags->insn.is_abslit)
11702 num |= XTENSA_PROP_INSN_ABSLIT;
11703
11704 if (prop_flags->is_align)
11705 {
11706 num |= XTENSA_PROP_ALIGN;
11707 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
11708 }
11709
11710 return num;
11711}
11712
11713
11714static bfd_boolean
11715xtensa_frag_flags_combinable (prop_flags_1, prop_flags_2)
11716 const frag_flags *prop_flags_1;
11717 const frag_flags *prop_flags_2;
11718{
11719 /* Cannot combine with an end marker. */
11720
11721 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
11722 return FALSE;
11723 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
11724 return FALSE;
11725 if (prop_flags_1->is_data != prop_flags_2->is_data)
11726 return FALSE;
11727
11728 if (prop_flags_1->is_insn)
11729 {
11730 /* Properties of the beginning of the frag. */
11731 if (prop_flags_2->insn.is_loop_target)
11732 return FALSE;
11733 if (prop_flags_2->insn.is_branch_target)
11734 return FALSE;
11735 if (prop_flags_1->insn.is_no_density !=
11736 prop_flags_2->insn.is_no_density)
11737 return FALSE;
11738 if (prop_flags_1->insn.is_no_transform !=
11739 prop_flags_2->insn.is_no_transform)
11740 return FALSE;
11741 if (prop_flags_1->insn.is_no_reorder !=
11742 prop_flags_2->insn.is_no_reorder)
11743 return FALSE;
11744 if (prop_flags_1->insn.is_abslit !=
11745 prop_flags_2->insn.is_abslit)
11746 return FALSE;
11747 }
11748
11749 if (prop_flags_1->is_align)
11750 return FALSE;
11751
11752 return TRUE;
11753}
11754
11755
11756bfd_vma
11757xt_block_aligned_size (xt_block)
11758 const xtensa_block_info *xt_block;
11759{
11760 bfd_vma end_addr;
11761 size_t align_bits;
11762
11763 if (!xt_block->flags.is_align)
11764 return xt_block->size;
11765
11766 end_addr = xt_block->offset + xt_block->size;
11767 align_bits = xt_block->flags.alignment;
11768 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
11769 return end_addr - xt_block->offset;
11770}
11771
11772
11773static bfd_boolean
11774xtensa_xt_block_combine (xt_block, xt_block_2)
11775 xtensa_block_info *xt_block;
11776 const xtensa_block_info *xt_block_2;
11777{
11778 if (xt_block->sec != xt_block_2->sec)
11779 return FALSE;
11780 if (xt_block->offset + xt_block_aligned_size (xt_block)
11781 != xt_block_2->offset)
11782 return FALSE;
11783
11784 if (xt_block_2->size == 0
11785 && (!xt_block_2->flags.is_unreachable
11786 || xt_block->flags.is_unreachable))
11787 {
11788 if (xt_block_2->flags.is_align
11789 && xt_block->flags.is_align)
11790 {
11791 /* Nothing needed. */
11792 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
11793 return TRUE;
11794 }
11795 else
11796 {
11797 if (xt_block_2->flags.is_align)
11798 {
11799 /* Push alignment to previous entry. */
11800 xt_block->flags.is_align = xt_block_2->flags.is_align;
11801 xt_block->flags.alignment = xt_block_2->flags.alignment;
11802 }
11803 return TRUE;
11804 }
11805 }
11806 if (!xtensa_frag_flags_combinable (&xt_block->flags,
11807 &xt_block_2->flags))
11808 return FALSE;
11809
11810 xt_block->size += xt_block_2->size;
11811
11812 if (xt_block_2->flags.is_align)
11813 {
11814 xt_block->flags.is_align = TRUE;
11815 xt_block->flags.alignment = xt_block_2->flags.alignment;
11816 }
11817
11818 return TRUE;
11819}
11820
11821
11822void
11823add_xt_prop_frags (sec, xt_block_sec, xt_block, property_function)
11824 segT sec;
11825 segT xt_block_sec;
11826 xtensa_block_info **xt_block;
11827 frag_flags_fn property_function;
11828{
11829 segment_info_type *seg_info;
11830 segment_info_type *xt_seg_info;
11831 bfd_vma seg_offset;
11832 fragS *fragP;
11833
11834 xt_seg_info = retrieve_segment_info (xt_block_sec);
11835 seg_info = retrieve_segment_info (sec);
11836 /* Build it if needed. */
11837 while (*xt_block != NULL)
11838 {
11839 xt_block = &(*xt_block)->next;
11840 }
11841 /* We are either at NULL at the beginning or at the end. */
11842
11843 /* Walk through the frags. */
11844 seg_offset = 0;
11845
11846 if (seg_info->frchainP)
11847 {
11848 for (fragP = seg_info->frchainP->frch_root; fragP;
11849 fragP = fragP->fr_next)
11850 {
11851 xtensa_block_info tmp_block;
11852 tmp_block.sec = sec;
11853 tmp_block.offset = fragP->fr_address;
11854 tmp_block.size = fragP->fr_fix;
11855 tmp_block.next = NULL;
11856 property_function (fragP, &tmp_block.flags);
11857
11858 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
11859 /* && fragP->fr_fix != 0) */
11860 {
11861 if ((*xt_block) == NULL
11862 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
11863 {
11864 xtensa_block_info *new_block;
11865 if ((*xt_block) != NULL)
11866 xt_block = &(*xt_block)->next;
11867 new_block = (xtensa_block_info *)
11868 xmalloc (sizeof (xtensa_block_info));
11869 *new_block = tmp_block;
11870 *xt_block = new_block;
11871 }
11872 }
11873 }
11874 }
11875}
11876
11877\f
11878/* op_placement_info_table */
11879
11880/* op_placement_info makes it easier to determine which
11881 ops can go in which slots. */
11882
11883static void
11884init_op_placement_info_table ()
11885{
11886 xtensa_isa isa = xtensa_default_isa;
11887 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
11888 xtensa_opcode opcode;
11889 xtensa_format fmt;
11890 int slot;
11891 int num_opcodes = xtensa_isa_num_opcodes (isa);
11892
11893 op_placement_table = (op_placement_info_table)
11894 xmalloc (sizeof (op_placement_info) * num_opcodes);
11895 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
11896
11897 for (opcode = 0; opcode < num_opcodes; opcode++)
11898 {
11899 op_placement_info *opi = &op_placement_table[opcode];
11900 /* FIXME: Make tinsn allocation dynamic. */
11901 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
11902 as_fatal (_("too many operands in instruction"));
11903 opi->single = XTENSA_UNDEFINED;
11904 opi->single_size = 0;
11905 opi->widest = XTENSA_UNDEFINED;
11906 opi->widest_size = 0;
11907 opi->narrowest = XTENSA_UNDEFINED;
11908 opi->narrowest_size = 0x7F;
11909 opi->formats = 0;
11910 opi->num_formats = 0;
11911 opi->issuef = 0;
11912 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
11913 {
11914 opi->slots[fmt] = 0;
11915 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
11916 {
11917 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11918 {
11919 int fmt_length = xtensa_format_length (isa, fmt);
11920 opi->issuef++;
11921 set_bit (fmt, opi->formats);
11922 set_bit (slot, opi->slots[fmt]);
11923 /* opi->slot_count[fmt]++; */
11924 if (fmt_length < opi->narrowest_size)
11925 {
11926 opi->narrowest = fmt;
11927 opi->narrowest_size = fmt_length;
11928 }
11929 if (fmt_length > opi->widest_size)
11930 {
11931 opi->widest = fmt;
11932 opi->widest_size = fmt_length;
11933 }
11934 if (xtensa_format_num_slots (isa, fmt) == 1)
11935 {
11936 if (opi->single_size == 0
11937 || fmt_length < opi->single_size)
11938 {
11939 opi->single = fmt;
11940 opi->single_size = fmt_length;
11941 }
11942 }
e0001a05
NC		 11943 }
11944 }
43cd72b9
BW		 11945 if (opi->formats)
11946 opi->num_formats++;
e0001a05
NC		 11947 }
11948 }
43cd72b9
BW		 11949 xtensa_insnbuf_free (isa, ibuf);
11950}
11951
11952
11953bfd_boolean
11954opcode_fits_format_slot (opcode, fmt, slot)
11955 xtensa_opcode opcode;
11956 xtensa_format fmt;
11957 int slot;
11958{
11959 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11960}
11961
11962
11963/* If the opcode is available in a single slot format, return its size. */
11964
11965int
11966xg_get_single_size (opcode)
11967 xtensa_opcode opcode;
11968{
11969 assert (op_placement_table[opcode].single != XTENSA_UNDEFINED);
11970 return op_placement_table[opcode].single_size;
11971}
11972
11973
11974xtensa_format
11975xg_get_single_format (opcode)
11976 xtensa_opcode opcode;
11977{
11978 return op_placement_table[opcode].single;
e0001a05
NC		 11979}
11980
11981\f
11982/* Instruction Stack Functions (from "xtensa-istack.h"). */
11983
11984void
11985istack_init (stack)
11986 IStack *stack;
11987{
11988 memset (stack, 0, sizeof (IStack));
11989 stack->ninsn = 0;
11990}
11991
11992
11993bfd_boolean
11994istack_empty (stack)
11995 IStack *stack;
11996{
11997 return (stack->ninsn == 0);
11998}
11999
12000
12001bfd_boolean
12002istack_full (stack)
12003 IStack *stack;
12004{
12005 return (stack->ninsn == MAX_ISTACK);
12006}
12007
12008
12009/* Return a pointer to the top IStack entry.
43cd72b9 12010 It is an error to call this if istack_empty () is TRUE. */
e0001a05
NC		 12011
12012TInsn *
12013istack_top (stack)
12014 IStack *stack;
12015{
12016 int rec = stack->ninsn - 1;
12017 assert (!istack_empty (stack));
12018 return &stack->insn[rec];
12019}
12020
12021
12022/* Add a new TInsn to an IStack.
43cd72b9 12023 It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 12024
12025void
12026istack_push (stack, insn)
12027 IStack *stack;
12028 TInsn *insn;
12029{
12030 int rec = stack->ninsn;
12031 assert (!istack_full (stack));
43cd72b9 12032 stack->insn[rec] = *insn;
e0001a05
NC		 12033 stack->ninsn++;
12034}
12035
12036
12037/* Clear space for the next TInsn on the IStack and return a pointer
43cd72b9 12038 to it. It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 12039
12040TInsn *
12041istack_push_space (stack)
12042 IStack *stack;
12043{
12044 int rec = stack->ninsn;
12045 TInsn *insn;
12046 assert (!istack_full (stack));
12047 insn = &stack->insn[rec];
12048 memset (insn, 0, sizeof (TInsn));
12049 stack->ninsn++;
12050 return insn;
12051}
12052
12053
12054/* Remove the last pushed instruction. It is an error to call this if
43cd72b9 12055 istack_empty () returns TRUE. */
e0001a05
NC		 12056
12057void
12058istack_pop (stack)
12059 IStack *stack;
12060{
12061 int rec = stack->ninsn - 1;
12062 assert (!istack_empty (stack));
12063 stack->ninsn--;
12064 memset (&stack->insn[rec], 0, sizeof (TInsn));
12065}
12066
12067\f
12068/* TInsn functions. */
12069
12070void
12071tinsn_init (dst)
12072 TInsn *dst;
12073{
12074 memset (dst, 0, sizeof (TInsn));
12075}
12076
12077
e0001a05
NC		 12078/* Get the ``num''th token of the TInsn.
12079 It is illegal to call this if num > insn->ntoks. */
12080
12081expressionS *
12082tinsn_get_tok (insn, num)
12083 TInsn *insn;
12084 int num;
12085{
12086 assert (num < insn->ntok);
12087 return &insn->tok[num];
12088}
12089
12090
43cd72b9 12091/* Return TRUE if ANY of the operands in the insn are symbolic. */
e0001a05
NC		 12092
12093static bfd_boolean
12094tinsn_has_symbolic_operands (insn)
12095 const TInsn *insn;
12096{
12097 int i;
12098 int n = insn->ntok;
12099
12100 assert (insn->insn_type == ITYPE_INSN);
12101
12102 for (i = 0; i < n; ++i)
12103 {
12104 switch (insn->tok[i].X_op)
12105 {
12106 case O_register:
12107 case O_constant:
12108 break;
12109 default:
12110 return TRUE;
12111 }
12112 }
12113 return FALSE;
12114}
12115
12116
12117bfd_boolean
12118tinsn_has_invalid_symbolic_operands (insn)
12119 const TInsn *insn;
12120{
43cd72b9 12121 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 12122 int i;
12123 int n = insn->ntok;
12124
12125 assert (insn->insn_type == ITYPE_INSN);
12126
12127 for (i = 0; i < n; ++i)
12128 {
12129 switch (insn->tok[i].X_op)
12130 {
12131 case O_register:
12132 case O_constant:
12133 break;
43cd72b9
BW		 12134 case O_big:
12135 case O_illegal:
12136 case O_absent:
12137 /* Errors for these types are caught later. */
12138 break;
12139 case O_hi16:
12140 case O_lo16:
e0001a05 12141 default:
43cd72b9
BW		 12142 /* Symbolic immediates are only allowed on the last immediate
12143 operand. At this time, CONST16 is the only opcode where we
12144 support non-PC-relative relocations. (It isn't necessary
12145 to complain about non-PC-relative relocations here, but
12146 otherwise, no error is reported until the relocations are
12147 generated, and the assembler won't get that far if there
12148 are any other errors. It's nice to see all the problems
12149 at once.) */
12150 if (i != get_relaxable_immed (insn->opcode)
12151 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
12152 && insn->opcode != xtensa_const16_opcode))
12153 {
12154 as_bad (_("invalid symbolic operand %d on '%s'"),
12155 i, xtensa_opcode_name (isa, insn->opcode));
12156 return TRUE;
12157 }
e0001a05
NC		 12158 }
12159 }
12160 return FALSE;
12161}
12162
12163
12164/* For assembly code with complex expressions (e.g. subtraction),
12165 we have to build them in the literal pool so that
12166 their results are calculated correctly after relaxation.
12167 The relaxation only handles expressions that
12168 boil down to SYMBOL + OFFSET. */
12169
12170static bfd_boolean
12171tinsn_has_complex_operands (insn)
12172 const TInsn *insn;
12173{
12174 int i;
12175 int n = insn->ntok;
12176 assert (insn->insn_type == ITYPE_INSN);
12177 for (i = 0; i < n; ++i)
12178 {
12179 switch (insn->tok[i].X_op)
12180 {
12181 case O_register:
12182 case O_constant:
12183 case O_symbol:
43cd72b9
BW		 12184 case O_lo16:
12185 case O_hi16:
e0001a05
NC		 12186 break;
12187 default:
12188 return TRUE;
12189 }
12190 }
12191 return FALSE;
12192}
12193
12194
43cd72b9
BW		 12195/* Convert the constant operands in the tinsn to insnbuf.
12196 Return TRUE if there is a symbol in the immediate field.
e0001a05 12197
43cd72b9 12198 Before this is called,
e0001a05 12199 1) the number of operands are correct
43cd72b9 12200 2) the tinsn is a ITYPE_INSN
e0001a05
NC		 12201 3) ONLY the relaxable_ is built
12202 4) All operands are O_constant, O_symbol. All constants fit
12203 The return value tells whether there are any remaining O_symbols. */
12204
12205static bfd_boolean
43cd72b9
BW		 12206tinsn_to_insnbuf (tinsn, insnbuf)
12207 TInsn *tinsn;
e0001a05
NC		 12208 xtensa_insnbuf insnbuf;
12209{
43cd72b9 12210 static xtensa_insnbuf slotbuf = 0;
e0001a05 12211 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 12212 xtensa_opcode opcode = tinsn->opcode;
12213 xtensa_format fmt = xg_get_single_format (opcode);
e0001a05 12214 bfd_boolean has_fixup = FALSE;
43cd72b9 12215 int noperands = xtensa_opcode_num_operands (isa, opcode);
e0001a05
NC		 12216 int i;
12217 uint32 opnd_value;
12218 char *file_name;
12219 int line;
12220
43cd72b9
BW		 12221 if (!slotbuf)
12222 slotbuf = xtensa_insnbuf_alloc (isa);
12223
12224 assert (tinsn->insn_type == ITYPE_INSN);
12225 if (noperands != tinsn->ntok)
e0001a05
NC		 12226 as_fatal (_("operand number mismatch"));
12227
43cd72b9
BW		 12228 if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode))
12229 as_fatal (_("cannot encode opcode"));
e0001a05
NC		 12230
12231 for (i = 0; i < noperands; ++i)
12232 {
43cd72b9 12233 expressionS *expr = &tinsn->tok[i];
e0001a05
NC		 12234 switch (expr->X_op)
12235 {
12236 case O_register:
43cd72b9
BW		 12237 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12238 break;
12239 /* The register number has already been checked in
e0001a05
NC		 12240 expression_maybe_register, so we don't need to check here. */
12241 opnd_value = expr->X_add_number;
43cd72b9
BW		 12242 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
12243 xtensa_operand_set_field (isa, opcode, i, fmt, 0,
12244 slotbuf, opnd_value);
e0001a05
NC		 12245 break;
12246
12247 case O_constant:
43cd72b9
BW		 12248 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12249 break;
e0001a05
NC		 12250 as_where (&file_name, &line);
12251 /* It is a constant and we called this function,
12252 then we have to try to fit it. */
43cd72b9
BW		 12253 xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i,
12254 expr->X_add_number, file_name, line);
12255 break;
12256
12257 default:
12258 has_fixup = TRUE;
12259 break;
12260 }
12261 }
12262
12263 xtensa_format_encode (isa, fmt, insnbuf);
12264 xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf);
12265
12266 return has_fixup;
12267}
12268
12269
12270/* Convert the constant operands in the tinsn to slotbuf.
12271 Return TRUE if there is a symbol in the immediate field.
12272 (Eventually this should replace tinsn_to_insnbuf.) */
12273
12274/* Before this is called,
12275 1) the number of operands are correct
12276 2) the tinsn is a ITYPE_INSN
12277 3) ONLY the relaxable_ is built
12278 4) All operands are
12279 O_constant, O_symbol
12280 All constants fit
12281
12282 The return value tells whether there are any remaining O_symbols. */
12283
12284static bfd_boolean
12285tinsn_to_slotbuf (fmt, slot, tinsn, slotbuf)
12286 xtensa_format fmt;
12287 int slot;
12288 TInsn *tinsn;
12289 xtensa_insnbuf slotbuf;
12290{
12291 xtensa_isa isa = xtensa_default_isa;
12292 xtensa_opcode opcode = tinsn->opcode;
12293 bfd_boolean has_fixup = FALSE;
12294 int noperands = xtensa_opcode_num_operands (isa, opcode);
12295 int i;
12296
12297 *((int *) &slotbuf[0]) = 0;
12298 *((int *) &slotbuf[1]) = 0;
12299 assert (tinsn->insn_type == ITYPE_INSN);
12300 if (noperands != tinsn->ntok)
12301 as_fatal (_("operand number mismatch"));
12302
12303 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
12304 {
12305 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12306 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
12307 return FALSE;
12308 }
12309
12310 for (i = 0; i < noperands; i++)
12311 {
12312 expressionS *expr = &tinsn->tok[i];
12313 int rc, line;
12314 char *file_name;
12315 uint32 opnd_value;
12316
12317 switch (expr->X_op)
12318 {
12319 case O_register:
12320 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12321 break;
12322 /* The register number has already been checked in
12323 expression_maybe_register, so we don't need to check here. */
12324 opnd_value = expr->X_add_number;
12325 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
12326 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
12327 opnd_value);
12328 if (rc != 0)
12329 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
12330 break;
12331
12332 case O_constant:
12333 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12334 break;
12335 as_where (&file_name, &line);
12336 /* It is a constant and we called this function
12337 then we have to try to fit it. */
12338 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
e0001a05
NC		 12339 expr->X_add_number, file_name, line);
12340 break;
12341
e0001a05
NC		 12342 default:
12343 has_fixup = TRUE;
12344 break;
12345 }
12346 }
43cd72b9 12347
e0001a05
NC		 12348 return has_fixup;
12349}
12350
12351
43cd72b9 12352/* Check the instruction arguments. Return TRUE on failure. */
e0001a05
NC		 12353
12354bfd_boolean
12355tinsn_check_arguments (insn)
12356 const TInsn *insn;
12357{
12358 xtensa_isa isa = xtensa_default_isa;
12359 xtensa_opcode opcode = insn->opcode;
12360
12361 if (opcode == XTENSA_UNDEFINED)
12362 {
12363 as_bad (_("invalid opcode"));
12364 return TRUE;
12365 }
12366
43cd72b9 12367 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
e0001a05
NC		 12368 {
12369 as_bad (_("too few operands"));
12370 return TRUE;
12371 }
12372
43cd72b9 12373 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
e0001a05
NC		 12374 {
12375 as_bad (_("too many operands"));
12376 return TRUE;
12377 }
12378 return FALSE;
12379}
12380
12381
12382/* Load an instruction from its encoded form. */
12383
12384static void
43cd72b9
BW		 12385tinsn_from_chars (tinsn, f, slot)
12386 TInsn *tinsn;
e0001a05 12387 char *f;
43cd72b9 12388 int slot;
e0001a05 12389{
43cd72b9 12390 vliw_insn vinsn;
e0001a05 12391
43cd72b9
BW		 12392 xg_init_vinsn (&vinsn);
12393 vinsn_from_chars (&vinsn, f);
12394
12395 *tinsn = vinsn.slots[slot];
12396 xg_free_vinsn (&vinsn);
12397}
e0001a05 12398
43cd72b9
BW		 12399
12400static void
12401tinsn_from_insnbuf (tinsn, slotbuf, fmt, slot)
12402 TInsn *tinsn;
12403 xtensa_insnbuf slotbuf;
12404 xtensa_format fmt;
12405 int slot;
12406{
12407 int i;
12408 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 12409
12410 /* Find the immed. */
43cd72b9
BW		 12411 tinsn_init (tinsn);
12412 tinsn->insn_type = ITYPE_INSN;
12413 tinsn->is_specific_opcode = FALSE; /* must not be specific */
12414 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
12415 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
12416 for (i = 0; i < tinsn->ntok; i++)
e0001a05 12417 {
43cd72b9
BW		 12418 set_expr_const (&tinsn->tok[i],
12419 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
12420 tinsn->opcode, i));
e0001a05
NC		 12421 }
12422}
12423
12424
12425/* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12426
12427static void
43cd72b9
BW		 12428tinsn_immed_from_frag (tinsn, fragP, slot)
12429 TInsn *tinsn;
e0001a05 12430 fragS *fragP;
43cd72b9 12431 int slot;
e0001a05 12432{
43cd72b9 12433 xtensa_opcode opcode = tinsn->opcode;
e0001a05
NC		 12434 int opnum;
12435
43cd72b9 12436 if (fragP->tc_frag_data.slot_symbols[slot])
e0001a05
NC		 12437 {
12438 opnum = get_relaxable_immed (opcode);
43cd72b9
BW		 12439 assert (opnum >= 0);
12440 if (fragP->tc_frag_data.slot_sub_symbols[slot])
12441 {
12442 set_expr_symbol_offset_diff
12443 (&tinsn->tok[opnum],
12444 fragP->tc_frag_data.slot_symbols[slot],
12445 fragP->tc_frag_data.slot_sub_symbols[slot],
12446 fragP->tc_frag_data.slot_offsets[slot]);
12447 }
12448 else
12449 {
12450 set_expr_symbol_offset
12451 (&tinsn->tok[opnum],
12452 fragP->tc_frag_data.slot_symbols[slot],
12453 fragP->tc_frag_data.slot_offsets[slot]);
12454 }
e0001a05
NC		 12455 }
12456}
12457
12458
12459static int
12460get_num_stack_text_bytes (istack)
12461 IStack *istack;
12462{
12463 int i;
12464 int text_bytes = 0;
12465
12466 for (i = 0; i < istack->ninsn; i++)
12467 {
43cd72b9
BW		 12468 TInsn *tinsn = &istack->insn[i];
12469 if (tinsn->insn_type == ITYPE_INSN)
12470 text_bytes += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 12471 }
12472 return text_bytes;
12473}
12474
12475
12476static int
12477get_num_stack_literal_bytes (istack)
12478 IStack *istack;
12479{
12480 int i;
12481 int lit_bytes = 0;
12482
12483 for (i = 0; i < istack->ninsn; i++)
12484 {
43cd72b9
BW		 12485 TInsn *tinsn = &istack->insn[i];
12486 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
e0001a05
NC		 12487 lit_bytes += 4;
12488 }
12489 return lit_bytes;
12490}
12491
43cd72b9
BW		 12492\f
12493/* vliw_insn functions. */
12494
12495void
12496xg_init_vinsn (v)
12497 vliw_insn *v;
12498{
12499 int i;
12500 xtensa_isa isa = xtensa_default_isa;
12501
12502 xg_clear_vinsn (v);
12503
12504 v->insnbuf = xtensa_insnbuf_alloc (isa);
12505 if (v->insnbuf == NULL)
12506 as_fatal (_("out of memory"));
12507
12508 for (i = 0; i < MAX_SLOTS; i++)
12509 {
12510 tinsn_init (&v->slots[i]);
12511 v->slots[i].opcode = XTENSA_UNDEFINED;
12512 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
12513 if (v->slotbuf[i] == NULL)
12514 as_fatal (_("out of memory"));
12515 }
12516}
12517
12518
12519void
12520xg_clear_vinsn (v)
12521 vliw_insn *v;
12522{
12523 int i;
12524 v->format = XTENSA_UNDEFINED;
12525 v->num_slots = 0;
12526 v->inside_bundle = FALSE;
12527
12528 if (xt_saved_debug_type != DEBUG_NONE)
12529 debug_type = xt_saved_debug_type;
12530
12531 for (i = 0; i < MAX_SLOTS; i++)
12532 {
12533 memset (&v->slots[i], 0, sizeof (TInsn));
12534 v->slots[i].opcode = XTENSA_UNDEFINED;
12535 }
12536}
12537
12538
12539bfd_boolean
12540vinsn_has_specific_opcodes (v)
12541 vliw_insn *v;
12542{
12543 int i;
12544
12545 for (i = 0; i < v->num_slots; i++)
12546 {
12547 if (v->slots[i].is_specific_opcode)
12548 return TRUE;
12549 }
12550 return FALSE;
12551}
12552
12553
12554void
12555xg_free_vinsn (v)
12556 vliw_insn *v;
12557{
12558 int i;
12559 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
12560 for (i = 0; i < MAX_SLOTS; i++)
12561 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
12562}
12563
12564
12565/* Before this is called, we should have
12566 filled out the following fields:
12567
12568 1) the number of operands for each opcode are correct
12569 2) the tinsn in the slots are ITYPE_INSN
12570 3) ONLY the relaxable_ is built
12571 4) All operands are
12572 O_constant, O_symbol
12573 All constants fit
12574
12575 The return value tells whether there are any remaining O_symbols. */
12576
12577static bfd_boolean
12578vinsn_to_insnbuf (vinsn, frag_offset, fragP, record_fixup)
12579 vliw_insn *vinsn;
12580 char *frag_offset;
12581 fragS *fragP;
12582 bfd_boolean record_fixup;
12583{
12584 xtensa_isa isa = xtensa_default_isa;
12585 xtensa_format fmt = vinsn->format;
12586 xtensa_insnbuf insnbuf = vinsn->insnbuf;
12587 int slot;
12588 bfd_boolean has_fixup = FALSE;
12589
12590 xtensa_format_encode (isa, fmt, insnbuf);
12591
12592 for (slot = 0; slot < vinsn->num_slots; slot++)
12593 {
12594 TInsn *tinsn = &vinsn->slots[slot];
12595 bfd_boolean tinsn_has_fixup =
12596 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
12597 vinsn->slotbuf[slot]);
12598
12599 xtensa_format_set_slot (isa, fmt, slot,
12600 insnbuf, vinsn->slotbuf[slot]);
12601 /* tinsn_has_fixup tracks if there is a fixup at all.
12602 record_fixup controls globally. I.E., we use this
12603 function from several places, some of which are after
12604 fixups have already been recorded. Finally,
12605 tinsn->record_fixup controls based on the individual ops,
12606 which may or may not need it based on the relaxation
12607 requirements. */
12608 if (tinsn_has_fixup && record_fixup)
12609 {
12610 int i;
12611 xtensa_opcode opcode = tinsn->opcode;
12612 int noperands = xtensa_opcode_num_operands (isa, opcode);
12613 has_fixup = TRUE;
12614
12615 for (i = 0; i < noperands; i++)
12616 {
12617 expressionS* expr = &tinsn->tok[i];
12618 switch (expr->X_op)
12619 {
12620 case O_symbol:
12621 case O_lo16:
12622 case O_hi16:
12623 if (get_relaxable_immed (opcode) == i)
12624 {
12625 if (tinsn->record_fix || expr->X_op != O_symbol)
12626 {
12627 if (!xg_add_opcode_fix
12628 (tinsn, i, fmt, slot, expr, fragP,
12629 frag_offset - fragP->fr_literal))
12630 as_bad (_("instruction with constant operands does not fit"));
12631 }
12632 else
12633 {
12634 tinsn->symbol = expr->X_add_symbol;
12635 tinsn->offset = expr->X_add_number;
12636 }
12637 }
12638 else
12639 as_bad (_("invalid operand %d on '%s'"),
12640 i, xtensa_opcode_name (isa, opcode));
12641 break;
12642
12643 case O_constant:
12644 case O_register:
12645 break;
12646
12647 case O_subtract:
12648 if (get_relaxable_immed (opcode) == i)
12649 {
12650 if (tinsn->record_fix)
12651 as_bad (_("invalid subtract operand"));
12652 else
12653 {
12654 tinsn->symbol = expr->X_add_symbol;
12655 tinsn->sub_symbol = expr->X_op_symbol;
12656 tinsn->offset = expr->X_add_number;
12657 }
12658 }
12659 else
12660 as_bad (_("invalid operand %d on '%s'"),
12661 i, xtensa_opcode_name (isa, opcode));
12662 break;
12663
12664 default:
12665 as_bad (_("invalid expression for operand %d on '%s'"),
12666 i, xtensa_opcode_name (isa, opcode));
12667 break;
12668 }
12669 }
12670 }
12671 }
12672
12673 return has_fixup;
12674}
12675
12676
12677static void
12678vinsn_from_chars (vinsn, f)
12679 vliw_insn *vinsn;
12680 char *f;
12681{
12682 static xtensa_insnbuf insnbuf = NULL;
12683 static xtensa_insnbuf slotbuf = NULL;
12684 int i;
12685 xtensa_format fmt;
12686 xtensa_isa isa = xtensa_default_isa;
12687
12688 if (!insnbuf)
12689 {
12690 insnbuf = xtensa_insnbuf_alloc (isa);
12691 slotbuf = xtensa_insnbuf_alloc (isa);
12692 }
12693
12694 xtensa_insnbuf_from_chars (isa, insnbuf, f, 0);
12695 fmt = xtensa_format_decode (isa, insnbuf);
12696 if (fmt == XTENSA_UNDEFINED)
12697 as_fatal (_("cannot decode instruction format"));
12698 vinsn->format = fmt;
12699 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
12700
12701 for (i = 0; i < vinsn->num_slots; i++)
12702 {
12703 TInsn *tinsn = &vinsn->slots[i];
12704 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
12705 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
12706 }
12707}
12708
e0001a05
NC		 12709\f
12710/* Expression utilities. */
12711
43cd72b9 12712/* Return TRUE if the expression is an integer constant. */
e0001a05
NC		 12713
12714bfd_boolean
12715expr_is_const (s)
12716 const expressionS *s;
12717{
12718 return (s->X_op == O_constant);
12719}
12720
12721
12722/* Get the expression constant.
43cd72b9 12723 Calling this is illegal if expr_is_const () returns TRUE. */
e0001a05
NC		 12724
12725offsetT
12726get_expr_const (s)
12727 const expressionS *s;
12728{
12729 assert (expr_is_const (s));
12730 return s->X_add_number;
12731}
12732
12733
12734/* Set the expression to a constant value. */
12735
12736void
12737set_expr_const (s, val)
12738 expressionS *s;
12739 offsetT val;
12740{
12741 s->X_op = O_constant;
12742 s->X_add_number = val;
12743 s->X_add_symbol = NULL;
12744 s->X_op_symbol = NULL;
12745}
12746
12747
43cd72b9
BW		 12748bfd_boolean
12749expr_is_register (s)
12750 const expressionS *s;
12751{
12752 return (s->X_op == O_register);
12753}
12754
12755
12756/* Get the expression constant.
12757 Calling this is illegal if expr_is_const () returns TRUE. */
12758
12759offsetT
12760get_expr_register (s)
12761 const expressionS *s;
12762{
12763 assert (expr_is_register (s));
12764 return s->X_add_number;
12765}
12766
12767
e0001a05
NC		 12768/* Set the expression to a symbol + constant offset. */
12769
12770void
12771set_expr_symbol_offset (s, sym, offset)
12772 expressionS *s;
12773 symbolS *sym;
12774 offsetT offset;
12775{
12776 s->X_op = O_symbol;
12777 s->X_add_symbol = sym;
12778 s->X_op_symbol = NULL; /* unused */
12779 s->X_add_number = offset;
12780}
12781
12782
43cd72b9
BW		 12783/* Set the expression to symbol - minus_sym + offset. */
12784
12785void
12786set_expr_symbol_offset_diff (s, sym, minus_sym, offset)
12787 expressionS *s;
12788 symbolS *sym;
12789 symbolS *minus_sym;
12790 offsetT offset;
12791{
12792 s->X_op = O_subtract;
12793 s->X_add_symbol = sym;
12794 s->X_op_symbol = minus_sym; /* unused */
12795 s->X_add_number = offset;
12796}
12797
12798
12799/* Return TRUE if the two expressions are equal. */
12800
e0001a05
NC		 12801bfd_boolean
12802expr_is_equal (s1, s2)
12803 expressionS *s1;
12804 expressionS *s2;
12805{
12806 if (s1->X_op != s2->X_op)
12807 return FALSE;
12808 if (s1->X_add_symbol != s2->X_add_symbol)
12809 return FALSE;
12810 if (s1->X_op_symbol != s2->X_op_symbol)
12811 return FALSE;
12812 if (s1->X_add_number != s2->X_add_number)
12813 return FALSE;
12814 return TRUE;
12815}
12816
12817
12818static void
12819copy_expr (dst, src)
12820 expressionS *dst;
12821 const expressionS *src;
12822{
12823 memcpy (dst, src, sizeof (expressionS));
12824}
12825
12826\f
12827/* Support for Tensilica's "--rename-section" option. */
12828
12829#ifdef XTENSA_SECTION_RENAME
12830
12831struct rename_section_struct
12832{
12833 char *old_name;
12834 char *new_name;
12835 struct rename_section_struct *next;
12836};
12837
12838static struct rename_section_struct *section_rename;
12839
12840
43cd72b9 12841/* Parse the string oldname=new_name:oldname2=new_name2
e0001a05
NC		 12842 and call add_section_rename. */
12843
12844void
12845build_section_rename (arg)
12846 const char *arg;
12847{
12848 char *this_arg = NULL;
12849 char *next_arg = NULL;
12850
12851 for (this_arg = strdup (arg); this_arg != NULL; this_arg = next_arg)
12852 {
12853 if (this_arg)
12854 {
12855 next_arg = strchr (this_arg, ':');
12856 if (next_arg)
12857 {
12858 *next_arg = '\0';
12859 next_arg++;
12860 }
12861 }
12862 {
12863 char *old_name = this_arg;
12864 char *new_name = strchr (this_arg, '=');
12865
12866 if (*old_name == '\0')
12867 {
12868 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12869 continue;
12870 }
12871 if (!new_name || new_name[1] == '\0')
12872 {
12873 as_warn (_("ignoring invalid '-rename-section' "
12874 "specification: '%s'"), old_name);
12875 continue;
12876 }
12877 *new_name = '\0';
12878 new_name++;
12879 add_section_rename (old_name, new_name);
12880 }
12881 }
12882}
12883
12884
12885static void
12886add_section_rename (old_name, new_name)
12887 char *old_name;
12888 char *new_name;
12889{
12890 struct rename_section_struct *r = section_rename;
12891
12892 /* Check for invalid section renaming. */
12893 for (r = section_rename; r != NULL; r = r->next)
12894 {
12895 if (strcmp (r->old_name, old_name) == 0)
12896 as_bad (_("section %s renamed multiple times"), old_name);
12897 if (strcmp (r->new_name, new_name) == 0)
12898 as_bad (_("multiple sections remapped to output section %s"),
12899 new_name);
12900 }
12901
12902 /* Now add it. */
12903 r = (struct rename_section_struct *)
12904 xmalloc (sizeof (struct rename_section_struct));
12905 r->old_name = strdup (old_name);
12906 r->new_name = strdup (new_name);
12907 r->next = section_rename;
12908 section_rename = r;
12909}
12910
12911
12912const char *
12913xtensa_section_rename (name)
12914 const char *name;
12915{
12916 struct rename_section_struct *r = section_rename;
12917
12918 for (r = section_rename; r != NULL; r = r->next)
43cd72b9
BW		 12919 {
12920 if (strcmp (r->old_name, name) == 0)
12921 return r->new_name;
12922 }
e0001a05
NC		 12923
12924 return name;
12925}
12926
12927#endif /* XTENSA_SECTION_RENAME */
GDB Binutils - Deliverables
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