Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
aa820537 AM |
2 | Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
3 | Free Software Foundation, Inc. | |
e0001a05 NC |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
20 | MA 02110-1301, USA. */ | |
e0001a05 | 21 | |
43cd72b9 | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "as.h" |
24 | #include "sb.h" | |
25 | #include "safe-ctype.h" | |
26 | #include "tc-xtensa.h" | |
e0001a05 NC |
27 | #include "subsegs.h" |
28 | #include "xtensa-relax.h" | |
cda2eb9e | 29 | #include "dwarf2dbg.h" |
b224e962 | 30 | #include "xtensa-istack.h" |
e0001a05 NC |
31 | #include "struc-symbol.h" |
32 | #include "xtensa-config.h" | |
33 | ||
2caa7ca0 BW |
34 | /* Provide default values for new configuration settings. */ |
35 | #ifndef XSHAL_ABI | |
36 | #define XSHAL_ABI 0 | |
37 | #endif | |
38 | ||
e0001a05 NC |
39 | #ifndef uint32 |
40 | #define uint32 unsigned int | |
41 | #endif | |
42 | #ifndef int32 | |
43 | #define int32 signed int | |
44 | #endif | |
45 | ||
46 | /* Notes: | |
47 | ||
e0001a05 NC |
48 | Naming conventions (used somewhat inconsistently): |
49 | The xtensa_ functions are exported | |
50 | The xg_ functions are internal | |
51 | ||
52 | We also have a couple of different extensibility mechanisms. | |
53 | 1) The idiom replacement: | |
54 | This is used when a line is first parsed to | |
55 | replace an instruction pattern with another instruction | |
56 | It is currently limited to replacements of instructions | |
57 | with constant operands. | |
58 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
59 | replacement patterns. When an instruction's immediate field | |
60 | does not fit the next instruction sequence is attempted. | |
61 | In addition, "narrow" opcodes are supported this way. */ | |
62 | ||
63 | ||
64 | /* Define characters with special meanings to GAS. */ | |
65 | const char comment_chars[] = "#"; | |
66 | const char line_comment_chars[] = "#"; | |
67 | const char line_separator_chars[] = ";"; | |
68 | const char EXP_CHARS[] = "eE"; | |
69 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
70 | ||
71 | ||
43cd72b9 BW |
72 | /* Flags to indicate whether the hardware supports the density and |
73 | absolute literals options. */ | |
e0001a05 | 74 | |
e0001a05 | 75 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
76 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
77 | ||
78 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
79 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 80 | |
43cd72b9 BW |
81 | static vliw_insn cur_vinsn; |
82 | ||
77cba8a3 | 83 | unsigned xtensa_num_pipe_stages; |
d77b99c9 | 84 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
85 | |
86 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
87 | ||
88 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 89 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
90 | back end. */ |
91 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
92 | |
93 | /* Flags for properties of the last instruction in a segment. */ | |
94 | #define FLAG_IS_A0_WRITER 0x1 | |
95 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
96 | ||
97 | ||
98 | /* We define a special segment names ".literal" to place literals | |
99 | into. The .fini and .init sections are special because they | |
100 | contain code that is moved together by the linker. We give them | |
101 | their own special .fini.literal and .init.literal sections. */ | |
102 | ||
103 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 104 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 105 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 106 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
107 | |
108 | ||
43cd72b9 | 109 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
110 | state of the literal collection pools. If lit_prefix is set, it is |
111 | used to determine the literal section names; otherwise, the literal | |
112 | sections are determined based on the current text section. The | |
113 | lit_seg and lit4_seg fields cache these literal sections, with the | |
114 | current_text_seg field used a tag to indicate whether the cached | |
115 | values are valid. */ | |
e0001a05 NC |
116 | |
117 | typedef struct lit_state_struct | |
118 | { | |
74869ac7 BW |
119 | char *lit_prefix; |
120 | segT current_text_seg; | |
e0001a05 | 121 | segT lit_seg; |
43cd72b9 | 122 | segT lit4_seg; |
e0001a05 NC |
123 | } lit_state; |
124 | ||
125 | static lit_state default_lit_sections; | |
126 | ||
127 | ||
74869ac7 BW |
128 | /* We keep a list of literal segments. The seg_list type is the node |
129 | for this list. The literal_head pointer is the head of the list, | |
130 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
131 | |
132 | typedef struct seg_list_struct | |
133 | { | |
134 | struct seg_list_struct *next; | |
135 | segT seg; | |
136 | } seg_list; | |
137 | ||
138 | static seg_list literal_head_h; | |
139 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
140 | |
141 | ||
82e7541d BW |
142 | /* Lists of symbols. We keep a list of symbols that label the current |
143 | instruction, so that we can adjust the symbols when inserting alignment | |
144 | for various instructions. We also keep a list of all the symbols on | |
145 | literals, so that we can fix up those symbols when the literals are | |
146 | later moved into the text sections. */ | |
147 | ||
148 | typedef struct sym_list_struct | |
149 | { | |
150 | struct sym_list_struct *next; | |
151 | symbolS *sym; | |
152 | } sym_list; | |
153 | ||
154 | static sym_list *insn_labels = NULL; | |
155 | static sym_list *free_insn_labels = NULL; | |
156 | static sym_list *saved_insn_labels = NULL; | |
157 | ||
158 | static sym_list *literal_syms; | |
159 | ||
160 | ||
43cd72b9 BW |
161 | /* Flags to determine whether to prefer const16 or l32r |
162 | if both options are available. */ | |
163 | int prefer_const16 = 0; | |
164 | int prefer_l32r = 0; | |
165 | ||
e0001a05 NC |
166 | /* Global flag to indicate when we are emitting literals. */ |
167 | int generating_literals = 0; | |
168 | ||
43cd72b9 BW |
169 | /* The following PROPERTY table definitions are copied from |
170 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
171 | ||
172 | /* Flags in the property tables to specify whether blocks of memory | |
173 | are literals, instructions, data, or unreachable. For | |
174 | instructions, blocks that begin loop targets and branch targets are | |
175 | designated. Blocks that do not allow density, instruction | |
176 | reordering or transformation are also specified. Finally, for | |
177 | branch targets, branch target alignment priority is included. | |
178 | Alignment of the next block is specified in the current block | |
179 | and the size of the current block does not include any fill required | |
180 | to align to the next block. */ | |
181 | ||
182 | #define XTENSA_PROP_LITERAL 0x00000001 | |
183 | #define XTENSA_PROP_INSN 0x00000002 | |
184 | #define XTENSA_PROP_DATA 0x00000004 | |
185 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
186 | /* Instruction only properties at beginning of code. */ | |
187 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
188 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
189 | /* Instruction only properties about code. */ | |
190 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
191 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
192 | /* Historically, NO_TRANSFORM was a property of instructions, |
193 | but it should apply to literals under certain circumstances. */ | |
194 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
195 | |
196 | /* Branch target alignment information. This transmits information | |
197 | to the linker optimization about the priority of aligning a | |
198 | particular block for branch target alignment: None, low priority, | |
199 | high priority, or required. These only need to be checked in | |
200 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
201 | Common usage is | |
202 | ||
203 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
204 | case XTENSA_PROP_BT_ALIGN_NONE: | |
205 | case XTENSA_PROP_BT_ALIGN_LOW: | |
206 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
207 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
208 | */ | |
209 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
210 | ||
211 | /* No branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
213 | /* Low priority branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
215 | /* High priority branch target alignment. */ | |
216 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
217 | /* Required branch target alignment. */ | |
218 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
219 | ||
220 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
221 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
222 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
223 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
224 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
225 | ||
226 | ||
227 | /* Alignment is specified in the block BEFORE the one that needs | |
228 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
229 | get the required alignment specified as a power of 2. Use | |
230 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
231 | alignment. Be careful of side effects since the SET will evaluate | |
232 | flags twice. Also, note that the SIZE of a block in the property | |
233 | table does not include the alignment size, so the alignment fill | |
234 | must be calculated to determine if two blocks are contiguous. | |
235 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
236 | possible future implementation. */ | |
237 | ||
238 | #define XTENSA_PROP_ALIGN 0x00000800 | |
239 | ||
240 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
241 | ||
242 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
243 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
244 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
245 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
246 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
247 | ||
248 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
249 | ||
250 | ||
251 | /* Structure for saving instruction and alignment per-fragment data | |
252 | that will be written to the object file. This structure is | |
253 | equivalent to the actual data that will be written out to the file | |
254 | but is easier to use. We provide a conversion to file flags | |
255 | in frag_flags_to_number. */ | |
256 | ||
257 | typedef struct frag_flags_struct frag_flags; | |
258 | ||
259 | struct frag_flags_struct | |
260 | { | |
261 | /* is_literal should only be used after xtensa_move_literals. | |
262 | If you need to check if you are generating a literal fragment, | |
263 | then use the generating_literals global. */ | |
264 | ||
265 | unsigned is_literal : 1; | |
266 | unsigned is_insn : 1; | |
267 | unsigned is_data : 1; | |
268 | unsigned is_unreachable : 1; | |
269 | ||
99ded152 BW |
270 | /* is_specific_opcode implies no_transform. */ |
271 | unsigned is_no_transform : 1; | |
272 | ||
43cd72b9 BW |
273 | struct |
274 | { | |
275 | unsigned is_loop_target : 1; | |
276 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
277 | unsigned bt_align_priority : 2; | |
278 | ||
279 | unsigned is_no_density : 1; | |
280 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
281 | |
282 | unsigned is_no_reorder : 1; | |
283 | ||
284 | /* Uses absolute literal addressing for l32r. */ | |
285 | unsigned is_abslit : 1; | |
286 | } insn; | |
287 | unsigned is_align : 1; | |
288 | unsigned alignment : 5; | |
289 | }; | |
290 | ||
291 | ||
292 | /* Structure for saving information about a block of property data | |
293 | for frags that have the same flags. */ | |
294 | struct xtensa_block_info_struct | |
295 | { | |
296 | segT sec; | |
297 | bfd_vma offset; | |
298 | size_t size; | |
299 | frag_flags flags; | |
300 | struct xtensa_block_info_struct *next; | |
301 | }; | |
302 | ||
e0001a05 NC |
303 | |
304 | /* Structure for saving the current state before emitting literals. */ | |
305 | typedef struct emit_state_struct | |
306 | { | |
307 | const char *name; | |
308 | segT now_seg; | |
309 | subsegT now_subseg; | |
310 | int generating_literals; | |
311 | } emit_state; | |
312 | ||
313 | ||
43cd72b9 BW |
314 | /* Opcode placement information */ |
315 | ||
316 | typedef unsigned long long bitfield; | |
317 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
318 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
319 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
320 | ||
321 | #define MAX_FORMATS 32 | |
322 | ||
323 | typedef struct op_placement_info_struct | |
324 | { | |
325 | int num_formats; | |
326 | /* A number describing how restrictive the issue is for this | |
327 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 328 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 329 | only one format but many slots in that format. The most |
c138bc38 | 330 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
331 | format. */ |
332 | int issuef; | |
43cd72b9 | 333 | xtensa_format narrowest; |
43cd72b9 | 334 | char narrowest_size; |
b2d179be | 335 | char narrowest_slot; |
43cd72b9 BW |
336 | |
337 | /* formats is a bitfield with the Nth bit set | |
338 | if the opcode fits in the Nth xtensa_format. */ | |
339 | bitfield formats; | |
340 | ||
341 | /* slots[N]'s Mth bit is set if the op fits in the | |
342 | Mth slot of the Nth xtensa_format. */ | |
343 | bitfield slots[MAX_FORMATS]; | |
344 | ||
345 | /* A count of the number of slots in a given format | |
346 | an op can fit (i.e., the bitcount of the slot field above). */ | |
347 | char slots_in_format[MAX_FORMATS]; | |
348 | ||
349 | } op_placement_info, *op_placement_info_table; | |
350 | ||
351 | op_placement_info_table op_placement_table; | |
352 | ||
353 | ||
354 | /* Extra expression types. */ | |
355 | ||
356 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
357 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
358 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 359 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
360 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
361 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
362 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
363 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
364 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 365 | |
bbdd25a8 BW |
366 | struct suffix_reloc_map |
367 | { | |
368 | char *suffix; | |
369 | int length; | |
370 | bfd_reloc_code_real_type reloc; | |
371 | unsigned char operator; | |
372 | }; | |
373 | ||
374 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
375 | ||
376 | static struct suffix_reloc_map suffix_relocs[] = | |
377 | { | |
378 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
379 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
380 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 381 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
382 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
383 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
384 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
385 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
386 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
387 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } |
388 | }; | |
389 | ||
43cd72b9 | 390 | |
e0001a05 NC |
391 | /* Directives. */ |
392 | ||
393 | typedef enum | |
394 | { | |
395 | directive_none = 0, | |
396 | directive_literal, | |
397 | directive_density, | |
43cd72b9 | 398 | directive_transform, |
e0001a05 NC |
399 | directive_freeregs, |
400 | directive_longcalls, | |
43cd72b9 BW |
401 | directive_literal_prefix, |
402 | directive_schedule, | |
403 | directive_absolute_literals, | |
404 | directive_last_directive | |
e0001a05 NC |
405 | } directiveE; |
406 | ||
407 | typedef struct | |
408 | { | |
409 | const char *name; | |
410 | bfd_boolean can_be_negated; | |
411 | } directive_infoS; | |
412 | ||
413 | const directive_infoS directive_info[] = | |
414 | { | |
43cd72b9 BW |
415 | { "none", FALSE }, |
416 | { "literal", FALSE }, | |
417 | { "density", TRUE }, | |
418 | { "transform", TRUE }, | |
419 | { "freeregs", FALSE }, | |
420 | { "longcalls", TRUE }, | |
421 | { "literal_prefix", FALSE }, | |
422 | { "schedule", TRUE }, | |
423 | { "absolute-literals", TRUE } | |
e0001a05 NC |
424 | }; |
425 | ||
426 | bfd_boolean directive_state[] = | |
427 | { | |
428 | FALSE, /* none */ | |
429 | FALSE, /* literal */ | |
43cd72b9 | 430 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
431 | FALSE, /* density */ |
432 | #else | |
433 | TRUE, /* density */ | |
434 | #endif | |
43cd72b9 | 435 | TRUE, /* transform */ |
e0001a05 NC |
436 | FALSE, /* freeregs */ |
437 | FALSE, /* longcalls */ | |
43cd72b9 | 438 | FALSE, /* literal_prefix */ |
2caa7ca0 | 439 | FALSE, /* schedule */ |
43cd72b9 BW |
440 | #if XSHAL_USE_ABSOLUTE_LITERALS |
441 | TRUE /* absolute_literals */ | |
442 | #else | |
443 | FALSE /* absolute_literals */ | |
444 | #endif | |
e0001a05 NC |
445 | }; |
446 | ||
e0001a05 NC |
447 | |
448 | /* Directive functions. */ | |
449 | ||
7fa3d080 BW |
450 | static void xtensa_begin_directive (int); |
451 | static void xtensa_end_directive (int); | |
74869ac7 | 452 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
453 | static void xtensa_literal_position (int); |
454 | static void xtensa_literal_pseudo (int); | |
455 | static void xtensa_frequency_pseudo (int); | |
456 | static void xtensa_elf_cons (int); | |
fb227da0 | 457 | static void xtensa_leb128 (int); |
e0001a05 | 458 | |
7fa3d080 | 459 | /* Parsing and Idiom Translation. */ |
e0001a05 | 460 | |
7fa3d080 | 461 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 462 | |
e0001a05 NC |
463 | /* Various Other Internal Functions. */ |
464 | ||
84b08ed9 BW |
465 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
466 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
467 | static void xtensa_mark_literal_pool_location (void); |
468 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
469 | static fragS *get_literal_pool_location (segT); | |
470 | static void set_literal_pool_location (segT, fragS *); | |
471 | static void xtensa_set_frag_assembly_state (fragS *); | |
472 | static void finish_vinsn (vliw_insn *); | |
473 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 474 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
475 | |
476 | /* Alignment Functions. */ | |
477 | ||
d77b99c9 BW |
478 | static int get_text_align_power (unsigned); |
479 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 480 | static int branch_align_power (segT); |
e0001a05 NC |
481 | |
482 | /* Helpers for xtensa_relax_frag(). */ | |
483 | ||
7fa3d080 | 484 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 485 | |
b08b5071 | 486 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 487 | |
7fa3d080 BW |
488 | static unsigned get_last_insn_flags (segT, subsegT); |
489 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
490 | static float get_subseg_total_freq (segT, subsegT); |
491 | static float get_subseg_target_freq (segT, subsegT); | |
492 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
493 | |
494 | /* Segment list functions. */ | |
495 | ||
7fa3d080 BW |
496 | static void xtensa_move_literals (void); |
497 | static void xtensa_reorder_segments (void); | |
498 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
499 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
500 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
501 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 502 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 503 | |
e0001a05 | 504 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 505 | |
51c8ebc1 | 506 | extern asection *xtensa_make_property_section (asection *, const char *); |
e0001a05 | 507 | |
43cd72b9 BW |
508 | /* op_placement_info functions. */ |
509 | ||
7fa3d080 BW |
510 | static void init_op_placement_info_table (void); |
511 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
512 | static int xg_get_single_size (xtensa_opcode); | |
513 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 514 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 515 | |
e0001a05 | 516 | /* TInsn and IStack functions. */ |
43cd72b9 | 517 | |
7fa3d080 BW |
518 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
519 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
520 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
521 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
522 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
523 | static void tinsn_from_chars (TInsn *, char *, int); | |
524 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
525 | static int get_num_stack_text_bytes (IStack *); | |
526 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 527 | |
43cd72b9 BW |
528 | /* vliw_insn functions. */ |
529 | ||
7fa3d080 | 530 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 531 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 BW |
532 | static void xg_clear_vinsn (vliw_insn *); |
533 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
534 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 535 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
536 | (vliw_insn *, char *, fragS *, bfd_boolean); |
537 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 538 | |
e0001a05 | 539 | /* Expression Utilities. */ |
43cd72b9 | 540 | |
7fa3d080 BW |
541 | bfd_boolean expr_is_const (const expressionS *); |
542 | offsetT get_expr_const (const expressionS *); | |
543 | void set_expr_const (expressionS *, offsetT); | |
544 | bfd_boolean expr_is_register (const expressionS *); | |
545 | offsetT get_expr_register (const expressionS *); | |
546 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
547 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
548 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 549 | |
9456465c BW |
550 | /* Section renaming. */ |
551 | ||
7fa3d080 | 552 | static void build_section_rename (const char *); |
e0001a05 | 553 | |
e0001a05 NC |
554 | |
555 | /* ISA imported from bfd. */ | |
556 | extern xtensa_isa xtensa_default_isa; | |
557 | ||
558 | extern int target_big_endian; | |
559 | ||
560 | static xtensa_opcode xtensa_addi_opcode; | |
561 | static xtensa_opcode xtensa_addmi_opcode; | |
562 | static xtensa_opcode xtensa_call0_opcode; | |
563 | static xtensa_opcode xtensa_call4_opcode; | |
564 | static xtensa_opcode xtensa_call8_opcode; | |
565 | static xtensa_opcode xtensa_call12_opcode; | |
566 | static xtensa_opcode xtensa_callx0_opcode; | |
567 | static xtensa_opcode xtensa_callx4_opcode; | |
568 | static xtensa_opcode xtensa_callx8_opcode; | |
569 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 570 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 571 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 572 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
573 | static xtensa_opcode xtensa_movi_opcode; |
574 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 575 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 576 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 577 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 578 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
579 | static xtensa_opcode xtensa_loop_opcode; |
580 | static xtensa_opcode xtensa_loopnez_opcode; | |
581 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 582 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
583 | static xtensa_opcode xtensa_nop_n_opcode; |
584 | static xtensa_opcode xtensa_or_opcode; | |
585 | static xtensa_opcode xtensa_ret_opcode; | |
586 | static xtensa_opcode xtensa_ret_n_opcode; | |
587 | static xtensa_opcode xtensa_retw_opcode; | |
588 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 589 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 590 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 591 | static int config_max_slots = 0; |
e0001a05 NC |
592 | |
593 | \f | |
594 | /* Command-line Options. */ | |
595 | ||
596 | bfd_boolean use_literal_section = TRUE; | |
19fc3723 | 597 | enum flix_level produce_flix = FLIX_ALL; |
e0001a05 | 598 | static bfd_boolean align_targets = TRUE; |
43cd72b9 | 599 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 600 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
601 | static bfd_boolean workaround_a0_b_retw = FALSE; |
602 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
603 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 604 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 605 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 606 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 607 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 608 | |
43cd72b9 BW |
609 | /* When workaround_short_loops is TRUE, all loops with early exits must |
610 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
611 | to the workaround_short_loop flag. In addition to the | |
612 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
613 | must have at least 3 instructions. */ | |
e0001a05 | 614 | |
43cd72b9 | 615 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 616 | |
7fa3d080 BW |
617 | |
618 | static void | |
619 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
620 | { | |
621 | if (earliest > latest) | |
622 | as_fatal (_("illegal range of target hardware versions")); | |
623 | ||
624 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
625 | if (earliest < 105000 || latest < 105000) | |
626 | { | |
627 | workaround_a0_b_retw |= TRUE; | |
628 | workaround_b_j_loop_end |= TRUE; | |
629 | workaround_short_loop |= TRUE; | |
630 | workaround_close_loop_end |= TRUE; | |
631 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 632 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
633 | } |
634 | } | |
635 | ||
636 | ||
e0001a05 NC |
637 | enum |
638 | { | |
639 | option_density = OPTION_MD_BASE, | |
640 | option_no_density, | |
641 | ||
19fc3723 SA |
642 | option_flix, |
643 | option_no_generate_flix, | |
644 | option_no_flix, | |
645 | ||
e0001a05 NC |
646 | option_relax, |
647 | option_no_relax, | |
648 | ||
43cd72b9 BW |
649 | option_link_relax, |
650 | option_no_link_relax, | |
651 | ||
e0001a05 NC |
652 | option_generics, |
653 | option_no_generics, | |
654 | ||
43cd72b9 BW |
655 | option_transform, |
656 | option_no_transform, | |
657 | ||
e0001a05 NC |
658 | option_text_section_literals, |
659 | option_no_text_section_literals, | |
660 | ||
43cd72b9 BW |
661 | option_absolute_literals, |
662 | option_no_absolute_literals, | |
663 | ||
e0001a05 NC |
664 | option_align_targets, |
665 | option_no_align_targets, | |
666 | ||
43cd72b9 | 667 | option_warn_unaligned_targets, |
e0001a05 NC |
668 | |
669 | option_longcalls, | |
670 | option_no_longcalls, | |
671 | ||
672 | option_workaround_a0_b_retw, | |
673 | option_no_workaround_a0_b_retw, | |
674 | ||
675 | option_workaround_b_j_loop_end, | |
676 | option_no_workaround_b_j_loop_end, | |
677 | ||
678 | option_workaround_short_loop, | |
679 | option_no_workaround_short_loop, | |
680 | ||
681 | option_workaround_all_short_loops, | |
682 | option_no_workaround_all_short_loops, | |
683 | ||
684 | option_workaround_close_loop_end, | |
685 | option_no_workaround_close_loop_end, | |
686 | ||
687 | option_no_workarounds, | |
688 | ||
e0001a05 | 689 | option_rename_section_name, |
e0001a05 | 690 | |
43cd72b9 BW |
691 | option_prefer_l32r, |
692 | option_prefer_const16, | |
693 | ||
694 | option_target_hardware | |
e0001a05 NC |
695 | }; |
696 | ||
697 | const char *md_shortopts = ""; | |
698 | ||
699 | struct option md_longopts[] = | |
700 | { | |
43cd72b9 BW |
701 | { "density", no_argument, NULL, option_density }, |
702 | { "no-density", no_argument, NULL, option_no_density }, | |
703 | ||
19fc3723 SA |
704 | { "flix", no_argument, NULL, option_flix }, |
705 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
706 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
707 | ||
43cd72b9 BW |
708 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
709 | to the "transform" option. */ | |
710 | { "relax", no_argument, NULL, option_relax }, | |
711 | { "no-relax", no_argument, NULL, option_no_relax }, | |
712 | { "generics", no_argument, NULL, option_generics }, | |
713 | { "no-generics", no_argument, NULL, option_no_generics }, | |
714 | ||
715 | { "transform", no_argument, NULL, option_transform }, | |
716 | { "no-transform", no_argument, NULL, option_no_transform }, | |
717 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
718 | { "no-text-section-literals", no_argument, NULL, | |
719 | option_no_text_section_literals }, | |
720 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
721 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
722 | /* This option was changed from -align-target to -target-align |
723 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 724 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
725 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
726 | { "warn-unaligned-targets", no_argument, NULL, | |
727 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
728 | { "longcalls", no_argument, NULL, option_longcalls }, |
729 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
730 | ||
731 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
732 | option_no_workaround_a0_b_retw }, | |
733 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 734 | |
43cd72b9 BW |
735 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
736 | option_no_workaround_b_j_loop_end }, | |
737 | { "workaround-b-j-loop-end", no_argument, NULL, | |
738 | option_workaround_b_j_loop_end }, | |
e0001a05 | 739 | |
43cd72b9 BW |
740 | { "no-workaround-short-loops", no_argument, NULL, |
741 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
742 | { "workaround-short-loops", no_argument, NULL, |
743 | option_workaround_short_loop }, | |
e0001a05 | 744 | |
43cd72b9 BW |
745 | { "no-workaround-all-short-loops", no_argument, NULL, |
746 | option_no_workaround_all_short_loops }, | |
747 | { "workaround-all-short-loop", no_argument, NULL, | |
748 | option_workaround_all_short_loops }, | |
749 | ||
750 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
751 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
752 | ||
753 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
754 | ||
755 | { "no-workaround-close-loop-end", no_argument, NULL, | |
756 | option_no_workaround_close_loop_end }, | |
757 | { "workaround-close-loop-end", no_argument, NULL, | |
758 | option_workaround_close_loop_end }, | |
e0001a05 | 759 | |
7fa3d080 | 760 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 761 | |
43cd72b9 BW |
762 | { "link-relax", no_argument, NULL, option_link_relax }, |
763 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
764 | ||
765 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
766 | ||
767 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
768 | }; |
769 | ||
770 | size_t md_longopts_size = sizeof md_longopts; | |
771 | ||
772 | ||
773 | int | |
7fa3d080 | 774 | md_parse_option (int c, char *arg) |
e0001a05 NC |
775 | { |
776 | switch (c) | |
777 | { | |
778 | case option_density: | |
43cd72b9 | 779 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
780 | return 1; |
781 | case option_no_density: | |
43cd72b9 | 782 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 783 | return 1; |
43cd72b9 BW |
784 | case option_link_relax: |
785 | linkrelax = 1; | |
e0001a05 | 786 | return 1; |
43cd72b9 BW |
787 | case option_no_link_relax: |
788 | linkrelax = 0; | |
e0001a05 | 789 | return 1; |
19fc3723 SA |
790 | case option_flix: |
791 | produce_flix = FLIX_ALL; | |
792 | return 1; | |
793 | case option_no_generate_flix: | |
794 | produce_flix = FLIX_NO_GENERATE; | |
795 | return 1; | |
796 | case option_no_flix: | |
797 | produce_flix = FLIX_NONE; | |
798 | return 1; | |
43cd72b9 BW |
799 | case option_generics: |
800 | as_warn (_("--generics is deprecated; use --transform instead")); | |
801 | return md_parse_option (option_transform, arg); | |
802 | case option_no_generics: | |
803 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
804 | return md_parse_option (option_no_transform, arg); | |
805 | case option_relax: | |
806 | as_warn (_("--relax is deprecated; use --transform instead")); | |
807 | return md_parse_option (option_transform, arg); | |
808 | case option_no_relax: | |
809 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
810 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
811 | case option_longcalls: |
812 | directive_state[directive_longcalls] = TRUE; | |
813 | return 1; | |
814 | case option_no_longcalls: | |
815 | directive_state[directive_longcalls] = FALSE; | |
816 | return 1; | |
817 | case option_text_section_literals: | |
818 | use_literal_section = FALSE; | |
819 | return 1; | |
820 | case option_no_text_section_literals: | |
821 | use_literal_section = TRUE; | |
822 | return 1; | |
43cd72b9 BW |
823 | case option_absolute_literals: |
824 | if (!absolute_literals_supported) | |
825 | { | |
826 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
827 | return 0; | |
828 | } | |
829 | directive_state[directive_absolute_literals] = TRUE; | |
830 | return 1; | |
831 | case option_no_absolute_literals: | |
832 | directive_state[directive_absolute_literals] = FALSE; | |
833 | return 1; | |
834 | ||
e0001a05 NC |
835 | case option_workaround_a0_b_retw: |
836 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
837 | return 1; |
838 | case option_no_workaround_a0_b_retw: | |
839 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
840 | return 1; |
841 | case option_workaround_b_j_loop_end: | |
842 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
843 | return 1; |
844 | case option_no_workaround_b_j_loop_end: | |
845 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
846 | return 1; |
847 | ||
848 | case option_workaround_short_loop: | |
849 | workaround_short_loop = TRUE; | |
e0001a05 NC |
850 | return 1; |
851 | case option_no_workaround_short_loop: | |
852 | workaround_short_loop = FALSE; | |
e0001a05 NC |
853 | return 1; |
854 | ||
855 | case option_workaround_all_short_loops: | |
856 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
857 | return 1; |
858 | case option_no_workaround_all_short_loops: | |
859 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
860 | return 1; |
861 | ||
862 | case option_workaround_close_loop_end: | |
863 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
864 | return 1; |
865 | case option_no_workaround_close_loop_end: | |
866 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
867 | return 1; |
868 | ||
869 | case option_no_workarounds: | |
870 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 871 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 872 | workaround_short_loop = FALSE; |
e0001a05 | 873 | workaround_all_short_loops = FALSE; |
e0001a05 | 874 | workaround_close_loop_end = FALSE; |
e0001a05 | 875 | return 1; |
43cd72b9 | 876 | |
e0001a05 NC |
877 | case option_align_targets: |
878 | align_targets = TRUE; | |
879 | return 1; | |
880 | case option_no_align_targets: | |
881 | align_targets = FALSE; | |
882 | return 1; | |
883 | ||
43cd72b9 BW |
884 | case option_warn_unaligned_targets: |
885 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
886 | return 1; |
887 | ||
e0001a05 NC |
888 | case option_rename_section_name: |
889 | build_section_rename (arg); | |
890 | return 1; | |
e0001a05 NC |
891 | |
892 | case 'Q': | |
893 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
894 | should be emitted or not. FIXME: Not implemented. */ | |
895 | return 1; | |
c138bc38 | 896 | |
43cd72b9 BW |
897 | case option_prefer_l32r: |
898 | if (prefer_const16) | |
899 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
900 | prefer_l32r = 1; | |
901 | return 1; | |
902 | ||
903 | case option_prefer_const16: | |
904 | if (prefer_l32r) | |
905 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
906 | prefer_const16 = 1; | |
907 | return 1; | |
908 | ||
c138bc38 | 909 | case option_target_hardware: |
43cd72b9 BW |
910 | { |
911 | int earliest, latest = 0; | |
912 | if (*arg == 0 || *arg == '-') | |
913 | as_fatal (_("invalid target hardware version")); | |
914 | ||
915 | earliest = strtol (arg, &arg, 0); | |
916 | ||
917 | if (*arg == 0) | |
918 | latest = earliest; | |
919 | else if (*arg == '-') | |
920 | { | |
921 | if (*++arg == 0) | |
922 | as_fatal (_("invalid target hardware version")); | |
923 | latest = strtol (arg, &arg, 0); | |
924 | } | |
925 | if (*arg != 0) | |
926 | as_fatal (_("invalid target hardware version")); | |
927 | ||
928 | xtensa_setup_hw_workarounds (earliest, latest); | |
929 | return 1; | |
930 | } | |
931 | ||
932 | case option_transform: | |
933 | /* This option has no affect other than to use the defaults, | |
934 | which are already set. */ | |
935 | return 1; | |
936 | ||
937 | case option_no_transform: | |
938 | /* This option turns off all transformations of any kind. | |
939 | However, because we want to preserve the state of other | |
940 | directives, we only change its own field. Thus, before | |
941 | you perform any transformation, always check if transform | |
942 | is available. If you use the functions we provide for this | |
943 | purpose, you will be ok. */ | |
944 | directive_state[directive_transform] = FALSE; | |
945 | return 1; | |
946 | ||
e0001a05 NC |
947 | default: |
948 | return 0; | |
949 | } | |
950 | } | |
951 | ||
952 | ||
953 | void | |
7fa3d080 | 954 | md_show_usage (FILE *stream) |
e0001a05 | 955 | { |
43cd72b9 BW |
956 | fputs ("\n\ |
957 | Xtensa options:\n\ | |
9456465c BW |
958 | --[no-]text-section-literals\n\ |
959 | [Do not] put literals in the text section\n\ | |
960 | --[no-]absolute-literals\n\ | |
961 | [Do not] default to use non-PC-relative literals\n\ | |
962 | --[no-]target-align [Do not] try to align branch targets\n\ | |
963 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
964 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
965 | --flix both allow hand-written and generate flix bundles\n\ |
966 | --no-generate-flix allow hand-written but do not generate\n\ | |
967 | flix bundles\n\ | |
968 | --no-allow-flix neither allow hand-written nor generate\n\ | |
969 | flix bundles\n\ | |
9456465c | 970 | --rename-section old=new Rename section 'old' to 'new'\n", stream); |
e0001a05 NC |
971 | } |
972 | ||
7fa3d080 BW |
973 | \f |
974 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
975 | |
976 | static void | |
7fa3d080 | 977 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 978 | { |
7fa3d080 | 979 | sym_list *l; |
43cd72b9 | 980 | |
7fa3d080 BW |
981 | if (!free_insn_labels) |
982 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
983 | else | |
43cd72b9 | 984 | { |
7fa3d080 BW |
985 | l = free_insn_labels; |
986 | free_insn_labels = l->next; | |
987 | } | |
988 | ||
989 | l->sym = sym; | |
990 | l->next = insn_labels; | |
991 | insn_labels = l; | |
992 | } | |
993 | ||
994 | ||
995 | static void | |
996 | xtensa_clear_insn_labels (void) | |
997 | { | |
998 | sym_list **pl; | |
999 | ||
1000 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1001 | ; | |
1002 | *pl = insn_labels; | |
1003 | insn_labels = NULL; | |
1004 | } | |
1005 | ||
1006 | ||
7fa3d080 | 1007 | static void |
c3ea6048 | 1008 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1009 | { |
1010 | sym_list *lit; | |
1011 | ||
1012 | for (lit = insn_labels; lit; lit = lit->next) | |
1013 | { | |
1014 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1015 | S_SET_VALUE (lit_sym, new_offset); |
1016 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1017 | } |
1018 | } | |
1019 | ||
e0001a05 NC |
1020 | \f |
1021 | /* Directive data and functions. */ | |
1022 | ||
1023 | typedef struct state_stackS_struct | |
1024 | { | |
1025 | directiveE directive; | |
1026 | bfd_boolean negated; | |
1027 | bfd_boolean old_state; | |
1028 | const char *file; | |
1029 | unsigned int line; | |
1030 | const void *datum; | |
1031 | struct state_stackS_struct *prev; | |
1032 | } state_stackS; | |
1033 | ||
1034 | state_stackS *directive_state_stack; | |
1035 | ||
1036 | const pseudo_typeS md_pseudo_table[] = | |
1037 | { | |
43cd72b9 BW |
1038 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1039 | { "literal_position", xtensa_literal_position, 0 }, | |
1040 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1041 | { "long", xtensa_elf_cons, 4 }, | |
1042 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1043 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1044 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1045 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1046 | { "sleb128", xtensa_leb128, 1}, |
1047 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1048 | { "begin", xtensa_begin_directive, 0 }, |
1049 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1050 | { "literal", xtensa_literal_pseudo, 0 }, |
1051 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1052 | { NULL, 0, 0 }, | |
e0001a05 NC |
1053 | }; |
1054 | ||
1055 | ||
7fa3d080 BW |
1056 | static bfd_boolean |
1057 | use_transform (void) | |
e0001a05 | 1058 | { |
43cd72b9 BW |
1059 | /* After md_end, you should be checking frag by frag, rather |
1060 | than state directives. */ | |
9c2799c2 | 1061 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1062 | return directive_state[directive_transform]; |
e0001a05 NC |
1063 | } |
1064 | ||
1065 | ||
7fa3d080 BW |
1066 | static bfd_boolean |
1067 | do_align_targets (void) | |
e0001a05 | 1068 | { |
7b1cc377 BW |
1069 | /* Do not use this function after md_end; just look at align_targets |
1070 | instead. There is no target-align directive, so alignment is either | |
1071 | enabled for all frags or not done at all. */ | |
9c2799c2 | 1072 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1073 | return align_targets && use_transform (); |
e0001a05 NC |
1074 | } |
1075 | ||
1076 | ||
1077 | static void | |
7fa3d080 | 1078 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1079 | { |
1080 | char *file; | |
1081 | unsigned int line; | |
1082 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1083 | ||
1084 | as_where (&file, &line); | |
1085 | ||
1086 | stack->directive = directive; | |
1087 | stack->negated = negated; | |
1088 | stack->old_state = directive_state[directive]; | |
1089 | stack->file = file; | |
1090 | stack->line = line; | |
1091 | stack->datum = datum; | |
1092 | stack->prev = directive_state_stack; | |
1093 | directive_state_stack = stack; | |
1094 | ||
1095 | directive_state[directive] = !negated; | |
1096 | } | |
1097 | ||
7fa3d080 | 1098 | |
e0001a05 | 1099 | static void |
7fa3d080 BW |
1100 | directive_pop (directiveE *directive, |
1101 | bfd_boolean *negated, | |
1102 | const char **file, | |
1103 | unsigned int *line, | |
1104 | const void **datum) | |
e0001a05 NC |
1105 | { |
1106 | state_stackS *top = directive_state_stack; | |
1107 | ||
1108 | if (!directive_state_stack) | |
1109 | { | |
1110 | as_bad (_("unmatched end directive")); | |
1111 | *directive = directive_none; | |
1112 | return; | |
1113 | } | |
1114 | ||
1115 | directive_state[directive_state_stack->directive] = top->old_state; | |
1116 | *directive = top->directive; | |
1117 | *negated = top->negated; | |
1118 | *file = top->file; | |
1119 | *line = top->line; | |
1120 | *datum = top->datum; | |
1121 | directive_state_stack = top->prev; | |
1122 | free (top); | |
1123 | } | |
1124 | ||
1125 | ||
1126 | static void | |
7fa3d080 | 1127 | directive_balance (void) |
e0001a05 NC |
1128 | { |
1129 | while (directive_state_stack) | |
1130 | { | |
1131 | directiveE directive; | |
1132 | bfd_boolean negated; | |
1133 | const char *file; | |
1134 | unsigned int line; | |
1135 | const void *datum; | |
1136 | ||
1137 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1138 | as_warn_where ((char *) file, line, | |
1139 | _(".begin directive with no matching .end directive")); | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | ||
1144 | static bfd_boolean | |
7fa3d080 | 1145 | inside_directive (directiveE dir) |
e0001a05 NC |
1146 | { |
1147 | state_stackS *top = directive_state_stack; | |
1148 | ||
1149 | while (top && top->directive != dir) | |
1150 | top = top->prev; | |
1151 | ||
1152 | return (top != NULL); | |
1153 | } | |
1154 | ||
1155 | ||
1156 | static void | |
7fa3d080 | 1157 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1158 | { |
1159 | int len; | |
1160 | unsigned i; | |
43cd72b9 | 1161 | char *directive_string; |
e0001a05 NC |
1162 | |
1163 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1164 | *negated = FALSE; | |
1165 | else | |
1166 | { | |
1167 | *negated = TRUE; | |
1168 | input_line_pointer += 3; | |
1169 | } | |
1170 | ||
1171 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1172 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1173 | ||
1174 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1175 | equivalent to .begin [no-]transform. We should remove it when | |
1176 | we stop accepting those options. */ | |
c138bc38 | 1177 | |
43cd72b9 BW |
1178 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1179 | { | |
1180 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1181 | directive_string = "transform"; | |
1182 | } | |
1183 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1184 | { | |
1185 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1186 | directive_string = "transform"; | |
c138bc38 | 1187 | } |
43cd72b9 BW |
1188 | else |
1189 | directive_string = input_line_pointer; | |
e0001a05 NC |
1190 | |
1191 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1192 | { | |
43cd72b9 | 1193 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1194 | { |
1195 | input_line_pointer += len; | |
1196 | *directive = (directiveE) i; | |
1197 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1198 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1199 | directive_info[i].name); |
1200 | return; | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | as_bad (_("unknown directive")); | |
1205 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1206 | } | |
1207 | ||
1208 | ||
1209 | static void | |
7fa3d080 | 1210 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1211 | { |
1212 | directiveE directive; | |
1213 | bfd_boolean negated; | |
1214 | emit_state *state; | |
e0001a05 NC |
1215 | lit_state *ls; |
1216 | ||
1217 | get_directive (&directive, &negated); | |
1218 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1219 | { | |
1220 | discard_rest_of_line (); | |
1221 | return; | |
1222 | } | |
1223 | ||
43cd72b9 BW |
1224 | if (cur_vinsn.inside_bundle) |
1225 | as_bad (_("directives are not valid inside bundles")); | |
1226 | ||
e0001a05 NC |
1227 | switch (directive) |
1228 | { | |
1229 | case directive_literal: | |
82e7541d BW |
1230 | if (!inside_directive (directive_literal)) |
1231 | { | |
1232 | /* Previous labels go with whatever follows this directive, not with | |
1233 | the literal, so save them now. */ | |
1234 | saved_insn_labels = insn_labels; | |
1235 | insn_labels = NULL; | |
1236 | } | |
43cd72b9 | 1237 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1238 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1239 | xtensa_switch_to_literal_fragment (state); | |
1240 | directive_push (directive_literal, negated, state); | |
1241 | break; | |
1242 | ||
1243 | case directive_literal_prefix: | |
c138bc38 | 1244 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1245 | might produce a literal. */ |
1246 | md_flush_pending_output (); | |
e0001a05 NC |
1247 | /* Check to see if the current fragment is a literal |
1248 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1249 | if (generating_literals) |
e0001a05 NC |
1250 | { |
1251 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1252 | return; | |
1253 | } | |
1254 | ||
1255 | /* Allocate the literal state for this section and push | |
1256 | onto the directive stack. */ | |
1257 | ls = xmalloc (sizeof (lit_state)); | |
9c2799c2 | 1258 | gas_assert (ls); |
e0001a05 NC |
1259 | |
1260 | *ls = default_lit_sections; | |
e0001a05 NC |
1261 | directive_push (directive_literal_prefix, negated, ls); |
1262 | ||
e0001a05 | 1263 | /* Process the new prefix. */ |
74869ac7 | 1264 | xtensa_literal_prefix (); |
e0001a05 NC |
1265 | break; |
1266 | ||
1267 | case directive_freeregs: | |
1268 | /* This information is currently unused, but we'll accept the statement | |
1269 | and just discard the rest of the line. This won't check the syntax, | |
1270 | but it will accept every correct freeregs directive. */ | |
1271 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1272 | directive_push (directive_freeregs, negated, 0); | |
1273 | break; | |
1274 | ||
43cd72b9 BW |
1275 | case directive_schedule: |
1276 | md_flush_pending_output (); | |
1277 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1278 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1279 | directive_push (directive_schedule, negated, 0); | |
1280 | xtensa_set_frag_assembly_state (frag_now); | |
1281 | break; | |
1282 | ||
e0001a05 | 1283 | case directive_density: |
43cd72b9 BW |
1284 | as_warn (_(".begin [no-]density is ignored")); |
1285 | break; | |
1286 | ||
1287 | case directive_absolute_literals: | |
1288 | md_flush_pending_output (); | |
1289 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1290 | { |
43cd72b9 | 1291 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1292 | break; |
1293 | } | |
43cd72b9 BW |
1294 | xtensa_set_frag_assembly_state (frag_now); |
1295 | directive_push (directive, negated, 0); | |
1296 | break; | |
e0001a05 NC |
1297 | |
1298 | default: | |
43cd72b9 BW |
1299 | md_flush_pending_output (); |
1300 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1301 | directive_push (directive, negated, 0); |
1302 | break; | |
1303 | } | |
1304 | ||
1305 | demand_empty_rest_of_line (); | |
1306 | } | |
1307 | ||
1308 | ||
1309 | static void | |
7fa3d080 | 1310 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1311 | { |
1312 | directiveE begin_directive, end_directive; | |
1313 | bfd_boolean begin_negated, end_negated; | |
1314 | const char *file; | |
1315 | unsigned int line; | |
1316 | emit_state *state; | |
43cd72b9 | 1317 | emit_state **state_ptr; |
e0001a05 NC |
1318 | lit_state *s; |
1319 | ||
43cd72b9 BW |
1320 | if (cur_vinsn.inside_bundle) |
1321 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1322 | |
e0001a05 | 1323 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1324 | |
1325 | md_flush_pending_output (); | |
1326 | ||
1327 | switch (end_directive) | |
e0001a05 | 1328 | { |
43cd72b9 | 1329 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1330 | discard_rest_of_line (); |
1331 | return; | |
e0001a05 | 1332 | |
43cd72b9 BW |
1333 | case directive_density: |
1334 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1335 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1336 | break; |
1337 | ||
1338 | case directive_absolute_literals: | |
1339 | if (!absolute_literals_supported && !end_negated) | |
1340 | { | |
1341 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1342 | demand_empty_rest_of_line (); | |
1343 | return; | |
1344 | } | |
1345 | break; | |
1346 | ||
1347 | default: | |
1348 | break; | |
e0001a05 NC |
1349 | } |
1350 | ||
43cd72b9 | 1351 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1352 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1353 | (const void **) state_ptr); |
e0001a05 NC |
1354 | |
1355 | if (begin_directive != directive_none) | |
1356 | { | |
1357 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1358 | { | |
1359 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1360 | begin_negated ? "no-" : "", | |
1361 | directive_info[begin_directive].name, file, line); | |
1362 | } | |
1363 | else | |
1364 | { | |
1365 | switch (end_directive) | |
1366 | { | |
1367 | case directive_literal: | |
1368 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1369 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1370 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1371 | free (state); |
82e7541d BW |
1372 | if (!inside_directive (directive_literal)) |
1373 | { | |
1374 | /* Restore the list of current labels. */ | |
1375 | xtensa_clear_insn_labels (); | |
1376 | insn_labels = saved_insn_labels; | |
1377 | } | |
e0001a05 NC |
1378 | break; |
1379 | ||
e0001a05 NC |
1380 | case directive_literal_prefix: |
1381 | /* Restore the default collection sections from saved state. */ | |
1382 | s = (lit_state *) state; | |
9c2799c2 | 1383 | gas_assert (s); |
e8247da7 | 1384 | default_lit_sections = *s; |
e0001a05 | 1385 | |
74869ac7 BW |
1386 | /* Free the state storage. */ |
1387 | free (s->lit_prefix); | |
e0001a05 NC |
1388 | free (s); |
1389 | break; | |
1390 | ||
43cd72b9 BW |
1391 | case directive_schedule: |
1392 | case directive_freeregs: | |
1393 | break; | |
1394 | ||
e0001a05 | 1395 | default: |
43cd72b9 | 1396 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1397 | break; |
1398 | } | |
1399 | } | |
1400 | } | |
1401 | ||
1402 | demand_empty_rest_of_line (); | |
1403 | } | |
1404 | ||
1405 | ||
1406 | /* Place an aligned literal fragment at the current location. */ | |
1407 | ||
1408 | static void | |
7fa3d080 | 1409 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1410 | { |
43cd72b9 BW |
1411 | md_flush_pending_output (); |
1412 | ||
e0001a05 NC |
1413 | if (inside_directive (directive_literal)) |
1414 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1415 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1416 | |
1417 | demand_empty_rest_of_line (); | |
82e7541d | 1418 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1419 | } |
1420 | ||
1421 | ||
43cd72b9 | 1422 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1423 | |
1424 | static void | |
7fa3d080 | 1425 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1426 | { |
1427 | emit_state state; | |
1745fcba | 1428 | char *p, *base_name; |
e0001a05 | 1429 | char c; |
e0001a05 NC |
1430 | segT dest_seg; |
1431 | ||
82e7541d BW |
1432 | if (inside_directive (directive_literal)) |
1433 | { | |
1434 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1435 | ignore_rest_of_line (); | |
1436 | return; | |
1437 | } | |
1438 | ||
43cd72b9 BW |
1439 | md_flush_pending_output (); |
1440 | ||
82e7541d BW |
1441 | /* Previous labels go with whatever follows this directive, not with |
1442 | the literal, so save them now. */ | |
1443 | saved_insn_labels = insn_labels; | |
1444 | insn_labels = NULL; | |
1445 | ||
e0001a05 NC |
1446 | /* If we are using text-section literals, then this is the right value... */ |
1447 | dest_seg = now_seg; | |
1448 | ||
1449 | base_name = input_line_pointer; | |
1450 | ||
1451 | xtensa_switch_to_literal_fragment (&state); | |
1452 | ||
43cd72b9 | 1453 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1454 | need to put them in the section we just switched to. */ |
43cd72b9 | 1455 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1456 | dest_seg = now_seg; |
1457 | ||
43cd72b9 BW |
1458 | /* All literals are aligned to four-byte boundaries. */ |
1459 | frag_align (2, 0, 0); | |
1460 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1461 | |
1462 | c = get_symbol_end (); | |
1463 | /* Just after name is now '\0'. */ | |
1464 | p = input_line_pointer; | |
1465 | *p = c; | |
1466 | SKIP_WHITESPACE (); | |
1467 | ||
1468 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1469 | { | |
1470 | as_bad (_("expected comma or colon after symbol name; " | |
1471 | "rest of line ignored")); | |
1472 | ignore_rest_of_line (); | |
1473 | xtensa_restore_emit_state (&state); | |
1474 | return; | |
1475 | } | |
1476 | *p = 0; | |
1477 | ||
e0001a05 | 1478 | colon (base_name); |
e0001a05 | 1479 | |
e0001a05 | 1480 | *p = c; |
43cd72b9 | 1481 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1482 | |
43cd72b9 | 1483 | xtensa_elf_cons (4); |
e0001a05 NC |
1484 | |
1485 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1486 | |
1487 | /* Restore the list of current labels. */ | |
1488 | xtensa_clear_insn_labels (); | |
1489 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1490 | } |
1491 | ||
1492 | ||
1493 | static void | |
74869ac7 | 1494 | xtensa_literal_prefix (void) |
e0001a05 | 1495 | { |
74869ac7 BW |
1496 | char *name; |
1497 | int len; | |
1498 | ||
1499 | /* Parse the new prefix from the input_line_pointer. */ | |
1500 | SKIP_WHITESPACE (); | |
1501 | len = strspn (input_line_pointer, | |
1502 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1503 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1504 | |
1505 | /* Get a null-terminated copy of the name. */ | |
1506 | name = xmalloc (len + 1); | |
9c2799c2 | 1507 | gas_assert (name); |
74869ac7 | 1508 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1509 | name[len] = 0; |
1510 | ||
74869ac7 BW |
1511 | /* Skip the name in the input line. */ |
1512 | input_line_pointer += len; | |
43cd72b9 | 1513 | |
74869ac7 | 1514 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1515 | |
74869ac7 | 1516 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1517 | default_lit_sections.lit_seg = NULL; |
1518 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1519 | } |
1520 | ||
1521 | ||
1522 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1523 | ||
1524 | static void | |
7fa3d080 | 1525 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1526 | { |
1527 | float fall_through_f, target_f; | |
43cd72b9 BW |
1528 | |
1529 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1530 | if (fall_through_f < 0) | |
1531 | { | |
1532 | as_bad (_("fall through frequency must be greater than 0")); | |
1533 | ignore_rest_of_line (); | |
1534 | return; | |
1535 | } | |
1536 | ||
1537 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1538 | if (target_f < 0) | |
1539 | { | |
1540 | as_bad (_("branch target frequency must be greater than 0")); | |
1541 | ignore_rest_of_line (); | |
1542 | return; | |
1543 | } | |
1544 | ||
b08b5071 | 1545 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1546 | |
1547 | demand_empty_rest_of_line (); | |
1548 | } | |
1549 | ||
1550 | ||
1551 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1552 | Clobbers input_line_pointer, checks end-of-line. */ | |
1553 | ||
1554 | static void | |
7fa3d080 | 1555 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1556 | { |
1557 | expressionS exp; | |
1558 | bfd_reloc_code_real_type reloc; | |
1559 | ||
1560 | md_flush_pending_output (); | |
1561 | ||
1562 | if (cur_vinsn.inside_bundle) | |
1563 | as_bad (_("directives are not valid inside bundles")); | |
1564 | ||
1565 | if (is_it_end_of_statement ()) | |
1566 | { | |
1567 | demand_empty_rest_of_line (); | |
1568 | return; | |
1569 | } | |
1570 | ||
1571 | do | |
1572 | { | |
1573 | expression (&exp); | |
1574 | if (exp.X_op == O_symbol | |
1575 | && *input_line_pointer == '@' | |
1576 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1577 | != BFD_RELOC_NONE)) | |
1578 | { | |
1579 | reloc_howto_type *reloc_howto = | |
1580 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1581 | ||
1582 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1583 | as_bad (_("unsupported relocation")); | |
1584 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1585 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1586 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1587 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1588 | as_bad (_("opcode-specific %s relocation used outside " | |
1589 | "an instruction"), reloc_howto->name); | |
1590 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1591 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1592 | reloc_howto->name, nbytes); | |
28dbbc02 BW |
1593 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1594 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1595 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1596 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1597 | else |
1598 | { | |
1599 | char *p = frag_more ((int) nbytes); | |
1600 | xtensa_set_frag_assembly_state (frag_now); | |
1601 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1602 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1603 | } |
1604 | } | |
1605 | else | |
1f7efbae BW |
1606 | { |
1607 | xtensa_set_frag_assembly_state (frag_now); | |
1608 | emit_expr (&exp, (unsigned int) nbytes); | |
1609 | } | |
43cd72b9 BW |
1610 | } |
1611 | while (*input_line_pointer++ == ','); | |
1612 | ||
1613 | input_line_pointer--; /* Put terminator back into stream. */ | |
1614 | demand_empty_rest_of_line (); | |
1615 | } | |
1616 | ||
fb227da0 BW |
1617 | static bfd_boolean is_leb128_expr; |
1618 | ||
1619 | static void | |
1620 | xtensa_leb128 (int sign) | |
1621 | { | |
1622 | is_leb128_expr = TRUE; | |
1623 | s_leb128 (sign); | |
1624 | is_leb128_expr = FALSE; | |
1625 | } | |
1626 | ||
7fa3d080 BW |
1627 | \f |
1628 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1629 | |
1630 | /* Parse @plt, etc. and return the desired relocation. */ | |
1631 | static bfd_reloc_code_real_type | |
7fa3d080 | 1632 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1633 | { |
43cd72b9 BW |
1634 | char ident[20]; |
1635 | char *str = *str_p; | |
1636 | char *str2; | |
1637 | int ch; | |
1638 | int len; | |
bbdd25a8 | 1639 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1640 | |
1641 | if (*str++ != '@') | |
1642 | return BFD_RELOC_NONE; | |
1643 | ||
1644 | for (ch = *str, str2 = ident; | |
1645 | (str2 < ident + sizeof (ident) - 1 | |
1646 | && (ISALNUM (ch) || ch == '@')); | |
1647 | ch = *++str) | |
1648 | { | |
1649 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1650 | } | |
1651 | ||
1652 | *str2 = '\0'; | |
1653 | len = str2 - ident; | |
1654 | ||
1655 | ch = ident[0]; | |
bbdd25a8 BW |
1656 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1657 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1658 | && len == ptr->length |
bbdd25a8 | 1659 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1660 | { |
1661 | /* Now check for "identifier@suffix+constant". */ | |
1662 | if (*str == '-' || *str == '+') | |
1663 | { | |
1664 | char *orig_line = input_line_pointer; | |
1665 | expressionS new_exp; | |
1666 | ||
1667 | input_line_pointer = str; | |
1668 | expression (&new_exp); | |
1669 | if (new_exp.X_op == O_constant) | |
1670 | { | |
1671 | exp_p->X_add_number += new_exp.X_add_number; | |
1672 | str = input_line_pointer; | |
1673 | } | |
1674 | ||
1675 | if (&input_line_pointer != str_p) | |
1676 | input_line_pointer = orig_line; | |
1677 | } | |
1678 | ||
1679 | *str_p = str; | |
1680 | return ptr->reloc; | |
1681 | } | |
1682 | ||
1683 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1684 | } |
1685 | ||
e0001a05 | 1686 | |
bbdd25a8 BW |
1687 | /* Find the matching operator type. */ |
1688 | static unsigned char | |
1689 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1690 | { | |
1691 | struct suffix_reloc_map *sfx; | |
1692 | unsigned char operator = (unsigned char) -1; | |
1693 | ||
1694 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1695 | { | |
1696 | if (sfx->reloc == reloc) | |
1697 | { | |
1698 | operator = sfx->operator; | |
1699 | break; | |
1700 | } | |
1701 | } | |
9c2799c2 | 1702 | gas_assert (operator != (unsigned char) -1); |
bbdd25a8 BW |
1703 | return operator; |
1704 | } | |
1705 | ||
1706 | ||
1707 | /* Find the matching reloc type. */ | |
1708 | static bfd_reloc_code_real_type | |
28dbbc02 | 1709 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 BW |
1710 | { |
1711 | struct suffix_reloc_map *sfx; | |
1712 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1713 | ||
1714 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1715 | { | |
1716 | if (sfx->operator == operator) | |
1717 | { | |
1718 | reloc = sfx->reloc; | |
1719 | break; | |
1720 | } | |
1721 | } | |
1722 | ||
28dbbc02 BW |
1723 | if (is_literal) |
1724 | { | |
1725 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1726 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1727 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1728 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1729 | } | |
1730 | ||
bbdd25a8 BW |
1731 | if (reloc == BFD_RELOC_UNUSED) |
1732 | return BFD_RELOC_32; | |
1733 | ||
1734 | return reloc; | |
1735 | } | |
1736 | ||
1737 | ||
e0001a05 | 1738 | static const char * |
7fa3d080 | 1739 | expression_end (const char *name) |
e0001a05 NC |
1740 | { |
1741 | while (1) | |
1742 | { | |
1743 | switch (*name) | |
1744 | { | |
43cd72b9 | 1745 | case '}': |
e0001a05 NC |
1746 | case ';': |
1747 | case '\0': | |
1748 | case ',': | |
43cd72b9 | 1749 | case ':': |
e0001a05 NC |
1750 | return name; |
1751 | case ' ': | |
1752 | case '\t': | |
1753 | ++name; | |
1754 | continue; | |
1755 | default: | |
1756 | return 0; | |
1757 | } | |
1758 | } | |
1759 | } | |
1760 | ||
1761 | ||
1762 | #define ERROR_REG_NUM ((unsigned) -1) | |
1763 | ||
1764 | static unsigned | |
7fa3d080 | 1765 | tc_get_register (const char *prefix) |
e0001a05 NC |
1766 | { |
1767 | unsigned reg; | |
1768 | const char *next_expr; | |
1769 | const char *old_line_pointer; | |
1770 | ||
1771 | SKIP_WHITESPACE (); | |
1772 | old_line_pointer = input_line_pointer; | |
1773 | ||
1774 | if (*input_line_pointer == '$') | |
1775 | ++input_line_pointer; | |
1776 | ||
1777 | /* Accept "sp" as a synonym for "a1". */ | |
1778 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1779 | && expression_end (input_line_pointer + 2)) | |
1780 | { | |
1781 | input_line_pointer += 2; | |
1782 | return 1; /* AR[1] */ | |
1783 | } | |
1784 | ||
1785 | while (*input_line_pointer++ == *prefix++) | |
1786 | ; | |
1787 | --input_line_pointer; | |
1788 | --prefix; | |
1789 | ||
1790 | if (*prefix) | |
1791 | { | |
1792 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1793 | return ERROR_REG_NUM; | |
1794 | } | |
1795 | ||
1796 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1797 | { | |
1798 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1799 | return ERROR_REG_NUM; | |
1800 | } | |
1801 | ||
1802 | reg = 0; | |
1803 | ||
1804 | while (ISDIGIT ((int) *input_line_pointer)) | |
1805 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1806 | ||
1807 | if (!(next_expr = expression_end (input_line_pointer))) | |
1808 | { | |
1809 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1810 | return ERROR_REG_NUM; | |
1811 | } | |
1812 | ||
1813 | input_line_pointer = (char *) next_expr; | |
1814 | ||
1815 | return reg; | |
1816 | } | |
1817 | ||
1818 | ||
e0001a05 | 1819 | static void |
7fa3d080 | 1820 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1821 | { |
43cd72b9 | 1822 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1823 | |
43cd72b9 BW |
1824 | /* Check if this is an immediate operand. */ |
1825 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1826 | { |
43cd72b9 | 1827 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1828 | segT t = expression (tok); |
91d6fa6a | 1829 | |
43cd72b9 BW |
1830 | if (t == absolute_section |
1831 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1832 | { |
9c2799c2 | 1833 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1834 | tok->X_op = O_symbol; |
1835 | tok->X_add_symbol = &abs_symbol; | |
1836 | } | |
43cd72b9 BW |
1837 | |
1838 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1839 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1840 | != BFD_RELOC_NONE)) | |
e0001a05 | 1841 | { |
1bbb5f21 | 1842 | switch (reloc) |
43cd72b9 | 1843 | { |
1bbb5f21 BW |
1844 | case BFD_RELOC_LO16: |
1845 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1846 | { |
43cd72b9 | 1847 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1848 | return; |
1bbb5f21 BW |
1849 | } |
1850 | break; | |
1851 | case BFD_RELOC_HI16: | |
1852 | if (tok->X_op == O_constant) | |
1853 | { | |
43cd72b9 | 1854 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1855 | return; |
bbdd25a8 | 1856 | } |
1bbb5f21 BW |
1857 | break; |
1858 | case BFD_RELOC_UNUSED: | |
1859 | as_bad (_("unsupported relocation")); | |
1860 | return; | |
1861 | case BFD_RELOC_32_PCREL: | |
1862 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1863 | return; | |
1864 | default: | |
1865 | break; | |
43cd72b9 | 1866 | } |
bbdd25a8 | 1867 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1868 | } |
e0001a05 NC |
1869 | } |
1870 | else | |
1871 | { | |
43cd72b9 BW |
1872 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1873 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1874 | |
1875 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1876 | { | |
1877 | uint32 buf = reg; | |
43cd72b9 | 1878 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1879 | as_bad (_("register number out of range")); |
1880 | } | |
1881 | ||
1882 | tok->X_op = O_register; | |
1883 | tok->X_add_symbol = 0; | |
1884 | tok->X_add_number = reg; | |
1885 | } | |
1886 | } | |
1887 | ||
1888 | ||
1889 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1890 | ||
1891 | static int | |
7fa3d080 | 1892 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1893 | { |
1894 | char *old_input_line_pointer; | |
1895 | bfd_boolean saw_comma = FALSE; | |
1896 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1897 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1898 | int num_args = 0; |
1899 | char *arg_end, *arg; | |
1900 | int arg_len; | |
43cd72b9 BW |
1901 | |
1902 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1903 | old_input_line_pointer = input_line_pointer; |
1904 | input_line_pointer = str; | |
1905 | ||
1906 | while (*input_line_pointer) | |
1907 | { | |
1908 | SKIP_WHITESPACE (); | |
1909 | switch (*input_line_pointer) | |
1910 | { | |
1911 | case '\0': | |
43cd72b9 | 1912 | case '}': |
e0001a05 NC |
1913 | goto fini; |
1914 | ||
43cd72b9 BW |
1915 | case ':': |
1916 | input_line_pointer++; | |
1917 | if (saw_comma || saw_colon || !saw_arg) | |
1918 | goto err; | |
1919 | saw_colon = TRUE; | |
1920 | break; | |
1921 | ||
e0001a05 NC |
1922 | case ',': |
1923 | input_line_pointer++; | |
43cd72b9 | 1924 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1925 | goto err; |
1926 | saw_comma = TRUE; | |
1927 | break; | |
1928 | ||
1929 | default: | |
43cd72b9 | 1930 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1931 | goto err; |
1932 | ||
1933 | arg_end = input_line_pointer + 1; | |
1934 | while (!expression_end (arg_end)) | |
1935 | arg_end += 1; | |
43cd72b9 | 1936 | |
e0001a05 | 1937 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1938 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1939 | args[num_args] = arg; |
1940 | ||
43cd72b9 BW |
1941 | if (saw_colon) |
1942 | *arg++ = ':'; | |
e0001a05 NC |
1943 | strncpy (arg, input_line_pointer, arg_len); |
1944 | arg[arg_len] = '\0'; | |
43cd72b9 | 1945 | |
e0001a05 NC |
1946 | input_line_pointer = arg_end; |
1947 | num_args += 1; | |
c138bc38 | 1948 | saw_comma = FALSE; |
43cd72b9 | 1949 | saw_colon = FALSE; |
c138bc38 | 1950 | saw_arg = TRUE; |
e0001a05 NC |
1951 | break; |
1952 | } | |
1953 | } | |
1954 | ||
1955 | fini: | |
43cd72b9 | 1956 | if (saw_comma || saw_colon) |
e0001a05 NC |
1957 | goto err; |
1958 | input_line_pointer = old_input_line_pointer; | |
1959 | return num_args; | |
1960 | ||
1961 | err: | |
43cd72b9 BW |
1962 | if (saw_comma) |
1963 | as_bad (_("extra comma")); | |
1964 | else if (saw_colon) | |
1965 | as_bad (_("extra colon")); | |
1966 | else if (!saw_arg) | |
c138bc38 | 1967 | as_bad (_("missing argument")); |
43cd72b9 BW |
1968 | else |
1969 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1970 | input_line_pointer = old_input_line_pointer; |
1971 | return -1; | |
1972 | } | |
1973 | ||
1974 | ||
43cd72b9 | 1975 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1976 | |
1977 | static bfd_boolean | |
7fa3d080 | 1978 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1979 | { |
43cd72b9 | 1980 | expressionS *tok, *last_tok; |
e0001a05 NC |
1981 | xtensa_opcode opcode = insn->opcode; |
1982 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1983 | xtensa_isa isa = xtensa_default_isa; |
1984 | int n, num_regs = 0; | |
e0001a05 | 1985 | int opcode_operand_count; |
43cd72b9 BW |
1986 | int opnd_cnt, last_opnd_cnt; |
1987 | unsigned int next_reg = 0; | |
e0001a05 NC |
1988 | char *old_input_line_pointer; |
1989 | ||
1990 | if (insn->insn_type == ITYPE_LITERAL) | |
1991 | opcode_operand_count = 1; | |
1992 | else | |
43cd72b9 | 1993 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1994 | |
43cd72b9 | 1995 | tok = insn->tok; |
e0001a05 NC |
1996 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1997 | ||
1998 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1999 | old_input_line_pointer = input_line_pointer; |
2000 | ||
2001 | last_tok = 0; | |
2002 | last_opnd_cnt = -1; | |
2003 | opnd_cnt = 0; | |
2004 | ||
2005 | /* Skip invisible operands. */ | |
2006 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2007 | { | |
2008 | opnd_cnt += 1; | |
2009 | tok++; | |
2010 | } | |
e0001a05 NC |
2011 | |
2012 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2013 | { |
e0001a05 | 2014 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2015 | if (*input_line_pointer == ':') |
2016 | { | |
2017 | xtensa_regfile opnd_rf; | |
2018 | input_line_pointer++; | |
2019 | if (num_regs == 0) | |
2020 | goto err; | |
9c2799c2 | 2021 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2022 | num_regs--; |
2023 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2024 | if (next_reg | |
2025 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2026 | as_warn (_("incorrect register number, ignoring")); | |
2027 | next_reg++; | |
2028 | } | |
2029 | else | |
2030 | { | |
2031 | if (opnd_cnt >= opcode_operand_count) | |
2032 | { | |
2033 | as_warn (_("too many arguments")); | |
2034 | goto err; | |
2035 | } | |
9c2799c2 | 2036 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2037 | |
2038 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2039 | next_reg = tok->X_add_number + 1; | |
2040 | ||
2041 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2042 | goto err; | |
2043 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2044 | { | |
2045 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2046 | /* minus 1 because we are seeing one right now */ | |
2047 | } | |
2048 | else | |
2049 | num_regs = 0; | |
e0001a05 | 2050 | |
43cd72b9 BW |
2051 | last_tok = tok; |
2052 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2053 | demand_empty_rest_of_line (); |
e0001a05 | 2054 | |
43cd72b9 BW |
2055 | do |
2056 | { | |
2057 | opnd_cnt += 1; | |
2058 | tok++; | |
2059 | } | |
2060 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2061 | } | |
2062 | } | |
e0001a05 | 2063 | |
43cd72b9 BW |
2064 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2065 | goto err; | |
e0001a05 NC |
2066 | |
2067 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2068 | had_error = FALSE; |
e0001a05 NC |
2069 | |
2070 | err: | |
43cd72b9 | 2071 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2072 | return had_error; |
2073 | } | |
2074 | ||
2075 | ||
43cd72b9 | 2076 | static int |
7fa3d080 | 2077 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2078 | { |
2079 | xtensa_isa isa = xtensa_default_isa; | |
2080 | static xtensa_insnbuf slotbuf = NULL; | |
2081 | xtensa_format fmt; | |
2082 | xtensa_opcode opc = insn->opcode; | |
2083 | int slot, opnd, fmt_found; | |
2084 | unsigned val; | |
2085 | ||
2086 | if (!slotbuf) | |
2087 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2088 | ||
2089 | /* Find format/slot where this can be encoded. */ | |
2090 | fmt_found = 0; | |
2091 | slot = 0; | |
2092 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2093 | { | |
2094 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2095 | { | |
2096 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2097 | { | |
2098 | fmt_found = 1; | |
2099 | break; | |
2100 | } | |
2101 | } | |
2102 | if (fmt_found) break; | |
2103 | } | |
2104 | ||
2105 | if (!fmt_found) | |
2106 | { | |
2107 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2108 | return -1; | |
2109 | } | |
2110 | ||
2111 | /* First encode all the visible operands | |
2112 | (to deal with shared field operands). */ | |
2113 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2114 | { | |
2115 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2116 | && (insn->tok[opnd].X_op == O_register | |
2117 | || insn->tok[opnd].X_op == O_constant)) | |
2118 | { | |
2119 | val = insn->tok[opnd].X_add_number; | |
2120 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2121 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | /* Then pull out the values for the invisible ones. */ | |
2126 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2127 | { | |
2128 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2129 | { | |
2130 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2131 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2132 | insn->tok[opnd].X_add_number = val; | |
2133 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2134 | insn->tok[opnd].X_op = O_register; | |
2135 | else | |
2136 | insn->tok[opnd].X_op = O_constant; | |
2137 | } | |
2138 | } | |
2139 | ||
2140 | return 0; | |
2141 | } | |
2142 | ||
2143 | ||
e0001a05 | 2144 | static void |
7fa3d080 | 2145 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2146 | { |
2147 | char *cnt_arg, *new_arg; | |
2148 | cnt_arg = *cnt_argp; | |
2149 | ||
2150 | /* replace the argument with "31-(argument)" */ | |
2151 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2152 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2153 | ||
2154 | free (cnt_arg); | |
2155 | *cnt_argp = new_arg; | |
2156 | } | |
2157 | ||
2158 | ||
2159 | /* If "arg" is a constant expression, return non-zero with the value | |
2160 | in *valp. */ | |
2161 | ||
2162 | static int | |
7fa3d080 | 2163 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2164 | { |
2165 | expressionS exp; | |
2166 | char *save_ptr = input_line_pointer; | |
2167 | ||
2168 | input_line_pointer = arg; | |
2169 | expression (&exp); | |
2170 | input_line_pointer = save_ptr; | |
2171 | ||
2172 | if (exp.X_op == O_constant) | |
2173 | { | |
2174 | *valp = exp.X_add_number; | |
2175 | return 1; | |
2176 | } | |
2177 | ||
2178 | return 0; | |
2179 | } | |
2180 | ||
2181 | ||
2182 | static void | |
7fa3d080 | 2183 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2184 | { |
2185 | free (*popname); | |
2186 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2187 | strcpy (*popname, newop); | |
2188 | } | |
2189 | ||
2190 | ||
2191 | static int | |
7fa3d080 BW |
2192 | xg_check_num_args (int *pnum_args, |
2193 | int expected_num, | |
2194 | char *opname, | |
2195 | char **arg_strings) | |
e0001a05 NC |
2196 | { |
2197 | int num_args = *pnum_args; | |
2198 | ||
43cd72b9 | 2199 | if (num_args < expected_num) |
e0001a05 NC |
2200 | { |
2201 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2202 | num_args, opname, expected_num); | |
2203 | return -1; | |
2204 | } | |
2205 | ||
2206 | if (num_args > expected_num) | |
2207 | { | |
2208 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2209 | num_args, opname, expected_num); | |
2210 | while (num_args-- > expected_num) | |
2211 | { | |
2212 | free (arg_strings[num_args]); | |
2213 | arg_strings[num_args] = 0; | |
2214 | } | |
2215 | *pnum_args = expected_num; | |
2216 | return -1; | |
2217 | } | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | ||
43cd72b9 BW |
2223 | /* If the register is not specified as part of the opcode, |
2224 | then get it from the operand and move it to the opcode. */ | |
2225 | ||
e0001a05 | 2226 | static int |
7fa3d080 | 2227 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2228 | { |
43cd72b9 BW |
2229 | xtensa_isa isa = xtensa_default_isa; |
2230 | xtensa_sysreg sr; | |
e0001a05 | 2231 | char *opname, *new_opname; |
43cd72b9 BW |
2232 | const char *sr_name; |
2233 | int is_user, is_write; | |
e0001a05 NC |
2234 | |
2235 | opname = *popname; | |
2236 | if (*opname == '_') | |
80ca4e2c | 2237 | opname += 1; |
43cd72b9 BW |
2238 | is_user = (opname[1] == 'u'); |
2239 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2240 | |
43cd72b9 | 2241 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2242 | |
43cd72b9 BW |
2243 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2244 | return -1; | |
e0001a05 | 2245 | |
43cd72b9 BW |
2246 | /* Check if the argument is a symbolic register name. */ |
2247 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2248 | /* Handle WSR to "INTSET" as a special case. */ | |
2249 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2250 | && !strcasecmp (arg_strings[1], "intset")) | |
2251 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2252 | if (sr == XTENSA_UNDEFINED | |
2253 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2254 | { | |
2255 | /* Maybe it's a register number.... */ | |
2256 | offsetT val; | |
e0001a05 NC |
2257 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2258 | { | |
43cd72b9 BW |
2259 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2260 | arg_strings[1], opname); | |
e0001a05 NC |
2261 | return -1; |
2262 | } | |
43cd72b9 BW |
2263 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2264 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2265 | { |
43cd72b9 | 2266 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2267 | (long) val, opname); |
e0001a05 NC |
2268 | return -1; |
2269 | } | |
43cd72b9 | 2270 | } |
e0001a05 | 2271 | |
43cd72b9 BW |
2272 | /* Remove the last argument, which is now part of the opcode. */ |
2273 | free (arg_strings[1]); | |
2274 | arg_strings[1] = 0; | |
2275 | *pnum_args = 1; | |
2276 | ||
2277 | /* Translate the opcode. */ | |
2278 | sr_name = xtensa_sysreg_name (isa, sr); | |
2279 | /* Another special case for "WSR.INTSET".... */ | |
2280 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2281 | sr_name = "intset"; | |
2282 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2283 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2284 | free (*popname); |
2285 | *popname = new_opname; | |
2286 | ||
2287 | return 0; | |
2288 | } | |
2289 | ||
2290 | ||
2291 | static int | |
7fa3d080 | 2292 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2293 | { |
2294 | xtensa_isa isa = xtensa_default_isa; | |
2295 | xtensa_sysreg sr; | |
2296 | char *opname, *new_opname; | |
2297 | const char *sr_name; | |
2298 | bfd_boolean has_underbar = FALSE; | |
2299 | ||
2300 | opname = *popname; | |
2301 | if (opname[0] == '_') | |
2302 | { | |
2303 | has_underbar = TRUE; | |
2304 | opname += 1; | |
2305 | } | |
2306 | ||
2307 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2308 | if (sr != XTENSA_UNDEFINED) | |
2309 | { | |
2310 | /* The new default name ("nnn") is different from the old default | |
2311 | name ("URnnn"). The old default is handled below, and we don't | |
2312 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2313 | default. */ | |
2314 | static char namebuf[10]; | |
2315 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2316 | if (strcmp (namebuf, opname + 1) == 0) | |
2317 | return 0; | |
2318 | } | |
2319 | else | |
2320 | { | |
2321 | offsetT val; | |
2322 | char *end; | |
2323 | ||
2324 | /* Only continue if the reg name is "URnnn". */ | |
2325 | if (opname[1] != 'u' || opname[2] != 'r') | |
2326 | return 0; | |
2327 | val = strtoul (opname + 3, &end, 10); | |
2328 | if (*end != '\0') | |
2329 | return 0; | |
2330 | ||
2331 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2332 | if (sr == XTENSA_UNDEFINED) | |
2333 | { | |
2334 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2335 | (long) val, opname); |
43cd72b9 BW |
2336 | return -1; |
2337 | } | |
2338 | } | |
2339 | ||
2340 | /* Translate the opcode. */ | |
2341 | sr_name = xtensa_sysreg_name (isa, sr); | |
2342 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2343 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2344 | opname[0], sr_name); | |
2345 | free (*popname); | |
2346 | *popname = new_opname; | |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
2351 | ||
2352 | static int | |
7fa3d080 BW |
2353 | xtensa_translate_zero_immed (char *old_op, |
2354 | char *new_op, | |
2355 | char **popname, | |
2356 | int *pnum_args, | |
2357 | char **arg_strings) | |
43cd72b9 BW |
2358 | { |
2359 | char *opname; | |
2360 | offsetT val; | |
2361 | ||
2362 | opname = *popname; | |
9c2799c2 | 2363 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2364 | |
2365 | if (strcmp (opname, old_op) != 0) | |
2366 | return 0; | |
e0001a05 | 2367 | |
43cd72b9 BW |
2368 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2369 | return -1; | |
2370 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2371 | { | |
2372 | xg_replace_opname (popname, new_op); | |
2373 | free (arg_strings[1]); | |
2374 | arg_strings[1] = arg_strings[2]; | |
2375 | arg_strings[2] = 0; | |
2376 | *pnum_args = 2; | |
e0001a05 NC |
2377 | } |
2378 | ||
2379 | return 0; | |
2380 | } | |
2381 | ||
2382 | ||
2383 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2384 | Returns non-zero if an error was found. */ | |
2385 | ||
2386 | static int | |
7fa3d080 | 2387 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2388 | { |
2389 | char *opname = *popname; | |
2390 | bfd_boolean has_underbar = FALSE; | |
2391 | ||
2392 | if (*opname == '_') | |
2393 | { | |
2394 | has_underbar = TRUE; | |
2395 | opname += 1; | |
2396 | } | |
2397 | ||
2398 | if (strcmp (opname, "mov") == 0) | |
2399 | { | |
43cd72b9 | 2400 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2401 | xg_replace_opname (popname, "mov.n"); |
2402 | else | |
2403 | { | |
2404 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2405 | return -1; | |
2406 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2407 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2408 | strcpy (arg_strings[2], arg_strings[1]); | |
2409 | *pnum_args = 3; | |
2410 | } | |
2411 | return 0; | |
2412 | } | |
2413 | ||
2414 | if (strcmp (opname, "bbsi.l") == 0) | |
2415 | { | |
2416 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2417 | return -1; | |
2418 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2419 | if (target_big_endian) | |
2420 | xg_reverse_shift_count (&arg_strings[1]); | |
2421 | return 0; | |
2422 | } | |
2423 | ||
2424 | if (strcmp (opname, "bbci.l") == 0) | |
2425 | { | |
2426 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2427 | return -1; | |
2428 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2429 | if (target_big_endian) | |
2430 | xg_reverse_shift_count (&arg_strings[1]); | |
2431 | return 0; | |
2432 | } | |
2433 | ||
eb6d9dce BW |
2434 | /* Don't do anything special with NOPs inside FLIX instructions. They |
2435 | are handled elsewhere. Real NOP instructions are always available | |
2436 | in configurations with FLIX, so this should never be an issue but | |
2437 | check for it anyway. */ | |
2438 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2439 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2440 | { |
43cd72b9 | 2441 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2442 | xg_replace_opname (popname, "nop.n"); |
2443 | else | |
2444 | { | |
2445 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2446 | return -1; | |
2447 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2448 | arg_strings[0] = (char *) xmalloc (3); | |
2449 | arg_strings[1] = (char *) xmalloc (3); | |
2450 | arg_strings[2] = (char *) xmalloc (3); | |
2451 | strcpy (arg_strings[0], "a1"); | |
2452 | strcpy (arg_strings[1], "a1"); | |
2453 | strcpy (arg_strings[2], "a1"); | |
2454 | *pnum_args = 3; | |
2455 | } | |
2456 | return 0; | |
2457 | } | |
2458 | ||
43cd72b9 BW |
2459 | /* Recognize [RW]UR and [RWX]SR. */ |
2460 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2461 | && (opname[1] == 'u' || opname[1] == 's')) | |
2462 | || (opname[0] == 'x' && opname[1] == 's')) | |
2463 | && opname[2] == 'r' | |
2464 | && opname[3] == '\0') | |
e0001a05 NC |
2465 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2466 | ||
43cd72b9 BW |
2467 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2468 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2469 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2470 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2471 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2472 | |
43cd72b9 BW |
2473 | /* Relax branches that don't allow comparisons against an immediate value |
2474 | of zero to the corresponding branches with implicit zero immediates. */ | |
2475 | if (!has_underbar && use_transform ()) | |
2476 | { | |
2477 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2478 | pnum_args, arg_strings)) | |
2479 | return -1; | |
e0001a05 | 2480 | |
43cd72b9 BW |
2481 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2482 | pnum_args, arg_strings)) | |
2483 | return -1; | |
e0001a05 | 2484 | |
43cd72b9 BW |
2485 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2486 | pnum_args, arg_strings)) | |
2487 | return -1; | |
e0001a05 | 2488 | |
43cd72b9 BW |
2489 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2490 | pnum_args, arg_strings)) | |
2491 | return -1; | |
2492 | } | |
e0001a05 | 2493 | |
43cd72b9 BW |
2494 | return 0; |
2495 | } | |
e0001a05 | 2496 | |
43cd72b9 BW |
2497 | \f |
2498 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2499 | |
43cd72b9 BW |
2500 | /* Currently the assembler only allows us to use a single target per |
2501 | fragment. Because of this, only one operand for a given | |
2502 | instruction may be symbolic. If there is a PC-relative operand, | |
2503 | the last one is chosen. Otherwise, the result is the number of the | |
2504 | last immediate operand, and if there are none of those, we fail and | |
2505 | return -1. */ | |
e0001a05 | 2506 | |
7fa3d080 BW |
2507 | static int |
2508 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2509 | { |
2510 | int last_immed = -1; | |
2511 | int noperands, opi; | |
e0001a05 | 2512 | |
43cd72b9 BW |
2513 | if (opcode == XTENSA_UNDEFINED) |
2514 | return -1; | |
e0001a05 | 2515 | |
43cd72b9 BW |
2516 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2517 | for (opi = noperands - 1; opi >= 0; opi--) | |
2518 | { | |
2519 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2520 | continue; | |
2521 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2522 | return opi; | |
2523 | if (last_immed == -1 | |
2524 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2525 | last_immed = opi; | |
e0001a05 | 2526 | } |
43cd72b9 | 2527 | return last_immed; |
e0001a05 NC |
2528 | } |
2529 | ||
e0001a05 | 2530 | |
43cd72b9 | 2531 | static xtensa_opcode |
7fa3d080 | 2532 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2533 | { |
43cd72b9 BW |
2534 | static xtensa_insnbuf insnbuf = NULL; |
2535 | static xtensa_insnbuf slotbuf = NULL; | |
2536 | xtensa_isa isa = xtensa_default_isa; | |
2537 | xtensa_format fmt; | |
2538 | ||
2539 | if (!insnbuf) | |
e0001a05 | 2540 | { |
43cd72b9 BW |
2541 | insnbuf = xtensa_insnbuf_alloc (isa); |
2542 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2543 | } |
e0001a05 | 2544 | |
d77b99c9 | 2545 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2546 | fmt = xtensa_format_decode (isa, insnbuf); |
2547 | if (fmt == XTENSA_UNDEFINED) | |
2548 | return XTENSA_UNDEFINED; | |
e0001a05 | 2549 | |
43cd72b9 BW |
2550 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2551 | return XTENSA_UNDEFINED; | |
e0001a05 | 2552 | |
43cd72b9 BW |
2553 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2554 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2555 | } |
2556 | ||
2557 | ||
43cd72b9 | 2558 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2559 | |
43cd72b9 | 2560 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2561 | |
7fa3d080 BW |
2562 | static void |
2563 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2564 | { |
2565 | int num_opcodes, num_operands; | |
2566 | xtensa_opcode opcode; | |
2567 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2568 | |
43cd72b9 BW |
2569 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2570 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2571 | { |
43cd72b9 BW |
2572 | int opn; |
2573 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2574 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2575 | for (opn = 0; opn < num_operands; opn++) | |
2576 | { | |
2577 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2578 | continue; | |
2579 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2580 | { | |
2581 | xtensa_regfile opnd_rf = | |
2582 | xtensa_operand_regfile (isa, opcode, opn); | |
2583 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2584 | } | |
2585 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2586 | fputs ("[lLr] ", stderr); | |
2587 | else | |
2588 | fputs ("i ", stderr); | |
2589 | } | |
2590 | fprintf (stderr, "\n"); | |
e0001a05 | 2591 | } |
e0001a05 NC |
2592 | } |
2593 | ||
2594 | ||
43cd72b9 | 2595 | static void |
7fa3d080 | 2596 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2597 | { |
e0001a05 | 2598 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2599 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2600 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2601 | int op; | |
e0001a05 | 2602 | |
43cd72b9 | 2603 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2604 | |
43cd72b9 BW |
2605 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2606 | { | |
2607 | xtensa_opcode opcode; | |
2608 | const char *opname; | |
2609 | int operands; | |
2610 | ||
2611 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2612 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2613 | opname = xtensa_opcode_name (isa, opcode); | |
2614 | ||
2615 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2616 | fprintf (stderr, " operands = "); | |
2617 | for (operands = 0; | |
2618 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2619 | operands++) | |
2620 | { | |
2621 | unsigned int val; | |
2622 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2623 | continue; | |
2624 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2625 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2626 | fprintf (stderr, "%d ", val); | |
2627 | } | |
2628 | fprintf (stderr, "\n"); | |
2629 | } | |
2630 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2631 | } |
2632 | ||
43cd72b9 BW |
2633 | #endif /* TENSILICA_DEBUG */ |
2634 | ||
e0001a05 NC |
2635 | |
2636 | static bfd_boolean | |
7fa3d080 | 2637 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2638 | { |
43cd72b9 BW |
2639 | xtensa_isa isa = xtensa_default_isa; |
2640 | int n, num_operands; | |
e0001a05 | 2641 | |
64b607e6 | 2642 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2643 | return FALSE; |
2644 | ||
43cd72b9 BW |
2645 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2646 | for (n = 0; n < num_operands; n++) | |
2647 | { | |
2648 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2649 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2650 | return TRUE; | |
2651 | } | |
2652 | return FALSE; | |
e0001a05 NC |
2653 | } |
2654 | ||
2655 | ||
43cd72b9 BW |
2656 | /* Convert from BFD relocation type code to slot and operand number. |
2657 | Returns non-zero on failure. */ | |
e0001a05 | 2658 | |
43cd72b9 | 2659 | static int |
7fa3d080 | 2660 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2661 | { |
43cd72b9 BW |
2662 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2663 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2664 | { |
43cd72b9 BW |
2665 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2666 | *is_alt = FALSE; | |
e0001a05 | 2667 | } |
43cd72b9 BW |
2668 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2669 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2670 | { |
43cd72b9 BW |
2671 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2672 | *is_alt = TRUE; | |
e0001a05 | 2673 | } |
43cd72b9 BW |
2674 | else |
2675 | return -1; | |
2676 | ||
2677 | return 0; | |
e0001a05 NC |
2678 | } |
2679 | ||
2680 | ||
43cd72b9 BW |
2681 | /* Convert from slot number to BFD relocation type code for the |
2682 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2683 | failure. */ | |
e0001a05 | 2684 | |
43cd72b9 | 2685 | static bfd_reloc_code_real_type |
7fa3d080 | 2686 | encode_reloc (int slot) |
e0001a05 | 2687 | { |
43cd72b9 BW |
2688 | if (slot < 0 || slot > 14) |
2689 | return BFD_RELOC_NONE; | |
2690 | ||
2691 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2692 | } |
2693 | ||
2694 | ||
43cd72b9 BW |
2695 | /* Convert from slot numbers to BFD relocation type code for the |
2696 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2697 | |
43cd72b9 | 2698 | static bfd_reloc_code_real_type |
7fa3d080 | 2699 | encode_alt_reloc (int slot) |
e0001a05 | 2700 | { |
43cd72b9 BW |
2701 | if (slot < 0 || slot > 14) |
2702 | return BFD_RELOC_NONE; | |
2703 | ||
2704 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2705 | } |
2706 | ||
2707 | ||
2708 | static void | |
7fa3d080 BW |
2709 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2710 | xtensa_format fmt, | |
2711 | int slot, | |
2712 | xtensa_opcode opcode, | |
2713 | int operand, | |
2714 | uint32 value, | |
2715 | const char *file, | |
2716 | unsigned int line) | |
e0001a05 | 2717 | { |
e0001a05 NC |
2718 | uint32 valbuf = value; |
2719 | ||
43cd72b9 | 2720 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2721 | { |
43cd72b9 BW |
2722 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2723 | == 1) | |
2724 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2725 | _("operand %d of '%s' has out of range value '%u'"), |
2726 | operand + 1, | |
2727 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2728 | value); | |
43cd72b9 BW |
2729 | else |
2730 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2731 | _("operand %d of '%s' has invalid value '%u'"), |
2732 | operand + 1, | |
2733 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2734 | value); | |
43cd72b9 | 2735 | return; |
e0001a05 NC |
2736 | } |
2737 | ||
43cd72b9 BW |
2738 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2739 | slotbuf, valbuf); | |
e0001a05 NC |
2740 | } |
2741 | ||
2742 | ||
2743 | static uint32 | |
7fa3d080 BW |
2744 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2745 | xtensa_format fmt, | |
2746 | int slot, | |
2747 | xtensa_opcode opcode, | |
2748 | int opnum) | |
e0001a05 | 2749 | { |
43cd72b9 BW |
2750 | uint32 val = 0; |
2751 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2752 | fmt, slot, slotbuf, &val); | |
2753 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2754 | return val; | |
e0001a05 NC |
2755 | } |
2756 | ||
e0001a05 | 2757 | \f |
7fa3d080 | 2758 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2759 | |
7fa3d080 BW |
2760 | /* The routine xg_instruction_matches_option_term must return TRUE |
2761 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2762 | terms is given interpretation by this function. */ |
e0001a05 | 2763 | |
7fa3d080 | 2764 | static bfd_boolean |
19e8f41a | 2765 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2766 | { |
7fa3d080 BW |
2767 | if (strcmp (option->option_name, "realnop") == 0 |
2768 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2769 | { | |
2770 | /* These conditions were evaluated statically when building the | |
2771 | relaxation table. There's no need to reevaluate them now. */ | |
2772 | return TRUE; | |
2773 | } | |
19e8f41a BW |
2774 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2775 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2776 | else |
2777 | { | |
2778 | as_fatal (_("internal error: unknown option name '%s'"), | |
2779 | option->option_name); | |
2780 | } | |
e0001a05 NC |
2781 | } |
2782 | ||
2783 | ||
7fa3d080 BW |
2784 | static bfd_boolean |
2785 | xg_instruction_matches_or_options (TInsn *insn, | |
2786 | const ReqOrOptionList *or_option) | |
e0001a05 | 2787 | { |
7fa3d080 BW |
2788 | const ReqOrOption *option; |
2789 | /* Must match each of the AND terms. */ | |
2790 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2791 | { |
7fa3d080 BW |
2792 | if (xg_instruction_matches_option_term (insn, option)) |
2793 | return TRUE; | |
e0001a05 | 2794 | } |
7fa3d080 | 2795 | return FALSE; |
e0001a05 NC |
2796 | } |
2797 | ||
2798 | ||
7fa3d080 BW |
2799 | static bfd_boolean |
2800 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2801 | { |
7fa3d080 BW |
2802 | const ReqOption *req_options; |
2803 | /* Must match each of the AND terms. */ | |
2804 | for (req_options = options; | |
2805 | req_options != NULL; | |
2806 | req_options = req_options->next) | |
e0001a05 | 2807 | { |
7fa3d080 BW |
2808 | /* Must match one of the OR clauses. */ |
2809 | if (!xg_instruction_matches_or_options (insn, | |
2810 | req_options->or_option_terms)) | |
2811 | return FALSE; | |
e0001a05 | 2812 | } |
7fa3d080 | 2813 | return TRUE; |
e0001a05 NC |
2814 | } |
2815 | ||
2816 | ||
7fa3d080 | 2817 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2818 | |
7fa3d080 BW |
2819 | static bfd_boolean |
2820 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2821 | { |
7fa3d080 | 2822 | PreconditionList *condition_l; |
e0001a05 | 2823 | |
7fa3d080 BW |
2824 | if (rule->opcode != insn->opcode) |
2825 | return FALSE; | |
e0001a05 | 2826 | |
7fa3d080 BW |
2827 | for (condition_l = rule->conditions; |
2828 | condition_l != NULL; | |
2829 | condition_l = condition_l->next) | |
e0001a05 | 2830 | { |
7fa3d080 BW |
2831 | expressionS *exp1; |
2832 | expressionS *exp2; | |
2833 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2834 | |
7fa3d080 | 2835 | switch (cond->typ) |
e0001a05 | 2836 | { |
7fa3d080 BW |
2837 | case OP_CONSTANT: |
2838 | /* The expression must be the constant. */ | |
9c2799c2 | 2839 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2840 | exp1 = &insn->tok[cond->op_num]; |
2841 | if (expr_is_const (exp1)) | |
2842 | { | |
2843 | switch (cond->cmp) | |
2844 | { | |
2845 | case OP_EQUAL: | |
2846 | if (get_expr_const (exp1) != cond->op_data) | |
2847 | return FALSE; | |
2848 | break; | |
2849 | case OP_NOTEQUAL: | |
2850 | if (get_expr_const (exp1) == cond->op_data) | |
2851 | return FALSE; | |
2852 | break; | |
2853 | default: | |
2854 | return FALSE; | |
2855 | } | |
2856 | } | |
2857 | else if (expr_is_register (exp1)) | |
2858 | { | |
2859 | switch (cond->cmp) | |
2860 | { | |
2861 | case OP_EQUAL: | |
2862 | if (get_expr_register (exp1) != cond->op_data) | |
2863 | return FALSE; | |
2864 | break; | |
2865 | case OP_NOTEQUAL: | |
2866 | if (get_expr_register (exp1) == cond->op_data) | |
2867 | return FALSE; | |
2868 | break; | |
2869 | default: | |
2870 | return FALSE; | |
2871 | } | |
2872 | } | |
2873 | else | |
2874 | return FALSE; | |
2875 | break; | |
2876 | ||
2877 | case OP_OPERAND: | |
9c2799c2 NC |
2878 | gas_assert (cond->op_num < insn->ntok); |
2879 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
2880 | exp1 = &insn->tok[cond->op_num]; |
2881 | exp2 = &insn->tok[cond->op_data]; | |
2882 | ||
2883 | switch (cond->cmp) | |
2884 | { | |
2885 | case OP_EQUAL: | |
2886 | if (!expr_is_equal (exp1, exp2)) | |
2887 | return FALSE; | |
2888 | break; | |
2889 | case OP_NOTEQUAL: | |
2890 | if (expr_is_equal (exp1, exp2)) | |
2891 | return FALSE; | |
2892 | break; | |
2893 | } | |
2894 | break; | |
2895 | ||
2896 | case OP_LITERAL: | |
2897 | case OP_LABEL: | |
2898 | default: | |
2899 | return FALSE; | |
2900 | } | |
2901 | } | |
2902 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2903 | return FALSE; | |
2904 | ||
2905 | return TRUE; | |
2906 | } | |
2907 | ||
2908 | ||
2909 | static int | |
2910 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2911 | { | |
2912 | bfd_boolean a_greater = FALSE; | |
2913 | bfd_boolean b_greater = FALSE; | |
2914 | ||
2915 | ReqOptionList *l_a = a->options; | |
2916 | ReqOptionList *l_b = b->options; | |
2917 | ||
2918 | /* We only care if they both are the same except for | |
2919 | a const16 vs. an l32r. */ | |
2920 | ||
2921 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2922 | { | |
2923 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2924 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2925 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2926 | { | |
2927 | if (l_or_a->is_true != l_or_b->is_true) | |
2928 | return 0; | |
2929 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2930 | { | |
2931 | /* This is the case we care about. */ | |
2932 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2933 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2934 | { | |
2935 | if (prefer_const16) | |
2936 | a_greater = TRUE; | |
2937 | else | |
2938 | b_greater = TRUE; | |
2939 | } | |
2940 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2941 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2942 | { | |
2943 | if (prefer_const16) | |
2944 | b_greater = TRUE; | |
2945 | else | |
2946 | a_greater = TRUE; | |
2947 | } | |
2948 | else | |
2949 | return 0; | |
2950 | } | |
2951 | l_or_a = l_or_a->next; | |
2952 | l_or_b = l_or_b->next; | |
2953 | } | |
2954 | if (l_or_a || l_or_b) | |
2955 | return 0; | |
2956 | ||
2957 | l_a = l_a->next; | |
2958 | l_b = l_b->next; | |
2959 | } | |
2960 | if (l_a || l_b) | |
2961 | return 0; | |
2962 | ||
2963 | /* Incomparable if the substitution was used differently in two cases. */ | |
2964 | if (a_greater && b_greater) | |
2965 | return 0; | |
2966 | ||
2967 | if (b_greater) | |
2968 | return 1; | |
2969 | if (a_greater) | |
2970 | return -1; | |
2971 | ||
2972 | return 0; | |
2973 | } | |
2974 | ||
2975 | ||
2976 | static TransitionRule * | |
2977 | xg_instruction_match (TInsn *insn) | |
2978 | { | |
2979 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2980 | TransitionList *l; | |
9c2799c2 | 2981 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
2982 | |
2983 | /* Walk through all of the possible transitions. */ | |
2984 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2985 | { | |
2986 | TransitionRule *rule = l->rule; | |
2987 | if (xg_instruction_matches_rule (insn, rule)) | |
2988 | return rule; | |
2989 | } | |
2990 | return NULL; | |
2991 | } | |
2992 | ||
2993 | \f | |
2994 | /* Various Other Internal Functions. */ | |
2995 | ||
2996 | static bfd_boolean | |
2997 | is_unique_insn_expansion (TransitionRule *r) | |
2998 | { | |
2999 | if (!r->to_instr || r->to_instr->next != NULL) | |
3000 | return FALSE; | |
3001 | if (r->to_instr->typ != INSTR_INSTR) | |
3002 | return FALSE; | |
3003 | return TRUE; | |
3004 | } | |
3005 | ||
3006 | ||
84b08ed9 BW |
3007 | /* Check if there is exactly one relaxation for INSN that converts it to |
3008 | another instruction of equal or larger size. If so, and if TARG is | |
3009 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3010 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3011 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3012 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3013 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3014 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3015 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3016 | |
84b08ed9 BW |
3017 | bfd_boolean |
3018 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
3019 | { |
3020 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3021 | TransitionList *l; | |
84b08ed9 | 3022 | TransitionRule *match = 0; |
7fa3d080 | 3023 | |
9c2799c2 NC |
3024 | gas_assert (insn->insn_type == ITYPE_INSN); |
3025 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3026 | |
3027 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3028 | { | |
3029 | TransitionRule *rule = l->rule; | |
3030 | ||
3031 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3032 | && is_unique_insn_expansion (rule) |
3033 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3034 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3035 | { |
84b08ed9 BW |
3036 | if (match) |
3037 | return FALSE; | |
3038 | match = rule; | |
7fa3d080 BW |
3039 | } |
3040 | } | |
84b08ed9 BW |
3041 | if (!match) |
3042 | return FALSE; | |
3043 | ||
3044 | if (targ) | |
3045 | xg_build_to_insn (targ, insn, match->to_instr); | |
3046 | return TRUE; | |
7fa3d080 BW |
3047 | } |
3048 | ||
3049 | ||
3050 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3051 | ||
3052 | static int | |
3053 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3054 | { | |
3055 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3056 | TransitionList *l; | |
3057 | int max_size = xg_get_single_size (opcode); | |
3058 | ||
9c2799c2 | 3059 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3060 | |
3061 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3062 | { | |
3063 | TransitionRule *rule = l->rule; | |
3064 | BuildInstr *build_list; | |
3065 | int this_size = 0; | |
3066 | ||
3067 | if (!rule) | |
3068 | continue; | |
3069 | build_list = rule->to_instr; | |
3070 | if (is_unique_insn_expansion (rule)) | |
3071 | { | |
9c2799c2 | 3072 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3073 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3074 | } | |
3075 | else | |
3076 | for (; build_list != NULL; build_list = build_list->next) | |
3077 | { | |
3078 | switch (build_list->typ) | |
3079 | { | |
3080 | case INSTR_INSTR: | |
3081 | this_size += xg_get_single_size (build_list->opcode); | |
3082 | break; | |
3083 | case INSTR_LITERAL_DEF: | |
3084 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3085 | default: |
3086 | break; | |
3087 | } | |
3088 | } | |
3089 | if (this_size > max_size) | |
3090 | max_size = this_size; | |
3091 | } | |
3092 | return max_size; | |
3093 | } | |
3094 | ||
3095 | ||
3096 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3097 | ||
7fa3d080 BW |
3098 | static int |
3099 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3100 | { |
43cd72b9 | 3101 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3102 | TransitionList *l; |
3103 | int max_size = 0; | |
3104 | ||
9c2799c2 | 3105 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3106 | |
3107 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3108 | { | |
3109 | TransitionRule *rule = l->rule; | |
3110 | BuildInstr *build_list; | |
3111 | int this_size = 0; | |
3112 | ||
3113 | if (!rule) | |
3114 | continue; | |
3115 | build_list = rule->to_instr; | |
3116 | if (is_unique_insn_expansion (rule)) | |
3117 | { | |
9c2799c2 | 3118 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3119 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3120 | } | |
3121 | else | |
3122 | for (; build_list != NULL; build_list = build_list->next) | |
3123 | { | |
3124 | switch (build_list->typ) | |
3125 | { | |
3126 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3127 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3128 | this_size += 4; |
3129 | break; | |
3130 | case INSTR_INSTR: | |
3131 | case INSTR_LABEL_DEF: | |
3132 | default: | |
3133 | break; | |
3134 | } | |
3135 | } | |
3136 | if (this_size > max_size) | |
3137 | max_size = this_size; | |
3138 | } | |
3139 | return max_size; | |
3140 | } | |
3141 | ||
3142 | ||
7fa3d080 BW |
3143 | static bfd_boolean |
3144 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3145 | { | |
3146 | int steps_taken = 0; | |
3147 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3148 | TransitionList *l; | |
3149 | ||
9c2799c2 NC |
3150 | gas_assert (insn->insn_type == ITYPE_INSN); |
3151 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3152 | |
3153 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3154 | { | |
3155 | TransitionRule *rule = l->rule; | |
3156 | ||
3157 | if (xg_instruction_matches_rule (insn, rule)) | |
3158 | { | |
3159 | if (steps_taken == lateral_steps) | |
3160 | return TRUE; | |
3161 | steps_taken++; | |
3162 | } | |
3163 | } | |
3164 | return FALSE; | |
3165 | } | |
3166 | ||
3167 | ||
3168 | static symbolS * | |
3169 | get_special_literal_symbol (void) | |
3170 | { | |
3171 | static symbolS *sym = NULL; | |
3172 | ||
3173 | if (sym == NULL) | |
3174 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3175 | return sym; | |
3176 | } | |
3177 | ||
3178 | ||
3179 | static symbolS * | |
3180 | get_special_label_symbol (void) | |
3181 | { | |
3182 | static symbolS *sym = NULL; | |
3183 | ||
3184 | if (sym == NULL) | |
3185 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3186 | return sym; | |
3187 | } | |
3188 | ||
3189 | ||
3190 | static bfd_boolean | |
3191 | xg_valid_literal_expression (const expressionS *exp) | |
3192 | { | |
3193 | switch (exp->X_op) | |
3194 | { | |
3195 | case O_constant: | |
3196 | case O_symbol: | |
3197 | case O_big: | |
3198 | case O_uminus: | |
3199 | case O_subtract: | |
3200 | case O_pltrel: | |
1bbb5f21 | 3201 | case O_pcrel: |
28dbbc02 BW |
3202 | case O_tlsfunc: |
3203 | case O_tlsarg: | |
3204 | case O_tpoff: | |
3205 | case O_dtpoff: | |
7fa3d080 BW |
3206 | return TRUE; |
3207 | default: | |
3208 | return FALSE; | |
3209 | } | |
3210 | } | |
3211 | ||
3212 | ||
3213 | /* This will check to see if the value can be converted into the | |
3214 | operand type. It will return TRUE if it does not fit. */ | |
3215 | ||
3216 | static bfd_boolean | |
3217 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3218 | { | |
3219 | uint32 valbuf = value; | |
3220 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3221 | return TRUE; | |
3222 | return FALSE; | |
3223 | } | |
3224 | ||
3225 | ||
3226 | /* Assumes: All immeds are constants. Check that all constants fit | |
3227 | into their immeds; return FALSE if not. */ | |
3228 | ||
3229 | static bfd_boolean | |
3230 | xg_immeds_fit (const TInsn *insn) | |
3231 | { | |
3232 | xtensa_isa isa = xtensa_default_isa; | |
3233 | int i; | |
3234 | ||
3235 | int n = insn->ntok; | |
9c2799c2 | 3236 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3237 | for (i = 0; i < n; ++i) |
3238 | { | |
91d6fa6a NC |
3239 | const expressionS *exp = &insn->tok[i]; |
3240 | ||
7fa3d080 BW |
3241 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3242 | continue; | |
3243 | ||
91d6fa6a | 3244 | switch (exp->X_op) |
7fa3d080 BW |
3245 | { |
3246 | case O_register: | |
3247 | case O_constant: | |
91d6fa6a | 3248 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3249 | return FALSE; |
3250 | break; | |
3251 | ||
3252 | default: | |
3253 | /* The symbol should have a fixup associated with it. */ | |
9c2799c2 | 3254 | gas_assert (FALSE); |
7fa3d080 BW |
3255 | break; |
3256 | } | |
3257 | } | |
3258 | return TRUE; | |
3259 | } | |
3260 | ||
3261 | ||
3262 | /* This should only be called after we have an initial | |
3263 | estimate of the addresses. */ | |
3264 | ||
3265 | static bfd_boolean | |
3266 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3267 | segT pc_seg, | |
3268 | fragS *pc_frag, | |
3269 | offsetT pc_offset, | |
3270 | long stretch) | |
e0001a05 | 3271 | { |
7fa3d080 BW |
3272 | xtensa_isa isa = xtensa_default_isa; |
3273 | symbolS *symbolP; | |
3274 | fragS *sym_frag; | |
3275 | offsetT target, pc; | |
3276 | uint32 new_offset; | |
3277 | int i; | |
3278 | int n = insn->ntok; | |
e0001a05 | 3279 | |
9c2799c2 | 3280 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3281 | |
7fa3d080 | 3282 | for (i = 0; i < n; ++i) |
e0001a05 | 3283 | { |
91d6fa6a NC |
3284 | const expressionS *exp = &insn->tok[i]; |
3285 | ||
7fa3d080 BW |
3286 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3287 | continue; | |
e0001a05 | 3288 | |
91d6fa6a | 3289 | switch (exp->X_op) |
e0001a05 | 3290 | { |
7fa3d080 BW |
3291 | case O_register: |
3292 | case O_constant: | |
91d6fa6a | 3293 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3294 | return FALSE; |
3295 | break; | |
e0001a05 | 3296 | |
7fa3d080 BW |
3297 | case O_lo16: |
3298 | case O_hi16: | |
3299 | /* Check for the worst case. */ | |
3300 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3301 | return FALSE; | |
3302 | break; | |
e0001a05 | 3303 | |
7fa3d080 | 3304 | case O_symbol: |
7c834684 | 3305 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3306 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3307 | if (pc_frag == 0 |
3308 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3309 | return FALSE; |
e0001a05 | 3310 | |
8e6bc631 BW |
3311 | /* If it is a weak symbol or a symbol in a different section, |
3312 | it cannot be known to fit at assembly time. */ | |
91d6fa6a NC |
3313 | if (S_IS_WEAK (exp->X_add_symbol) |
3314 | || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) | |
7c834684 | 3315 | { |
8e6bc631 | 3316 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3317 | assume it will be in range. If the symbol is weak and |
3318 | undefined, it may remain undefined at link-time, in which | |
3319 | case it will have a zero value and almost certainly be out | |
3320 | of range for a direct call; thus, relax for undefined weak | |
3321 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3322 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f | 3323 | && ! pc_frag->tc_frag_data.use_longcalls |
91d6fa6a NC |
3324 | && (! S_IS_WEAK (exp->X_add_symbol) |
3325 | || S_IS_DEFINED (exp->X_add_symbol))) | |
7c834684 | 3326 | return TRUE; |
7c834684 | 3327 | |
8e6bc631 BW |
3328 | return FALSE; |
3329 | } | |
e0001a05 | 3330 | |
91d6fa6a | 3331 | symbolP = exp->X_add_symbol; |
7fa3d080 | 3332 | sym_frag = symbol_get_frag (symbolP); |
91d6fa6a | 3333 | target = S_GET_VALUE (symbolP) + exp->X_add_number; |
7fa3d080 | 3334 | pc = pc_frag->fr_address + pc_offset; |
e0001a05 | 3335 | |
7fa3d080 BW |
3336 | /* If frag has yet to be reached on this pass, assume it |
3337 | will move by STRETCH just as we did. If this is not so, | |
3338 | it will be because some frag between grows, and that will | |
3339 | force another pass. Beware zero-length frags. There | |
3340 | should be a faster way to do this. */ | |
3341 | ||
3342 | if (stretch != 0 | |
3343 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3344 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3345 | { | |
3346 | target += stretch; | |
3347 | } | |
c138bc38 | 3348 | |
7fa3d080 BW |
3349 | new_offset = target; |
3350 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3351 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3352 | return FALSE; | |
3353 | break; | |
3354 | ||
3355 | default: | |
3356 | /* The symbol should have a fixup associated with it. */ | |
3357 | return FALSE; | |
3358 | } | |
3359 | } | |
3360 | ||
3361 | return TRUE; | |
e0001a05 NC |
3362 | } |
3363 | ||
3364 | ||
43cd72b9 | 3365 | /* Return TRUE on success. */ |
e0001a05 | 3366 | |
7fa3d080 BW |
3367 | static bfd_boolean |
3368 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3369 | { |
3370 | BuildOp *op; | |
3371 | symbolS *sym; | |
3372 | ||
60242db2 | 3373 | tinsn_init (targ); |
b224e962 BW |
3374 | targ->debug_line = insn->debug_line; |
3375 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3376 | switch (bi->typ) |
3377 | { | |
3378 | case INSTR_INSTR: | |
3379 | op = bi->ops; | |
3380 | targ->opcode = bi->opcode; | |
3381 | targ->insn_type = ITYPE_INSN; | |
3382 | targ->is_specific_opcode = FALSE; | |
3383 | ||
3384 | for (; op != NULL; op = op->next) | |
3385 | { | |
3386 | int op_num = op->op_num; | |
3387 | int op_data = op->op_data; | |
3388 | ||
9c2799c2 | 3389 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3390 | |
3391 | if (targ->ntok <= op_num) | |
3392 | targ->ntok = op_num + 1; | |
3393 | ||
3394 | switch (op->typ) | |
3395 | { | |
3396 | case OP_CONSTANT: | |
3397 | set_expr_const (&targ->tok[op_num], op_data); | |
3398 | break; | |
3399 | case OP_OPERAND: | |
9c2799c2 | 3400 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3401 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3402 | break; | |
19e8f41a BW |
3403 | case OP_FREEREG: |
3404 | if (insn->extra_arg.X_op != O_register) | |
3405 | return FALSE; | |
3406 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3407 | break; | |
e0001a05 NC |
3408 | case OP_LITERAL: |
3409 | sym = get_special_literal_symbol (); | |
3410 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3411 | if (insn->tok[op_data].X_op == O_tlsfunc |
3412 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3413 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3414 | break; |
3415 | case OP_LABEL: | |
3416 | sym = get_special_label_symbol (); | |
3417 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3418 | break; | |
43cd72b9 BW |
3419 | case OP_OPERAND_HI16U: |
3420 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3421 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3422 | if (expr_is_const (&insn->tok[op_data])) |
3423 | { | |
3424 | long val; | |
3425 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3426 | val = xg_apply_userdef_op_fn (op->typ, | |
3427 | targ->tok[op_num]. | |
3428 | X_add_number); | |
3429 | targ->tok[op_num].X_add_number = val; | |
3430 | } | |
3431 | else | |
3432 | { | |
3433 | /* For const16 we can create relocations for these. */ | |
3434 | if (targ->opcode == XTENSA_UNDEFINED | |
3435 | || (targ->opcode != xtensa_const16_opcode)) | |
3436 | return FALSE; | |
9c2799c2 | 3437 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3438 | /* Need to build a O_lo16 or O_hi16. */ |
3439 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3440 | if (targ->tok[op_num].X_op == O_symbol) | |
3441 | { | |
3442 | if (op->typ == OP_OPERAND_HI16U) | |
3443 | targ->tok[op_num].X_op = O_hi16; | |
3444 | else if (op->typ == OP_OPERAND_LOW16U) | |
3445 | targ->tok[op_num].X_op = O_lo16; | |
3446 | else | |
3447 | return FALSE; | |
3448 | } | |
3449 | } | |
3450 | break; | |
e0001a05 NC |
3451 | default: |
3452 | /* currently handles: | |
3453 | OP_OPERAND_LOW8 | |
3454 | OP_OPERAND_HI24S | |
3455 | OP_OPERAND_F32MINUS */ | |
3456 | if (xg_has_userdef_op_fn (op->typ)) | |
3457 | { | |
9c2799c2 | 3458 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3459 | if (expr_is_const (&insn->tok[op_data])) |
3460 | { | |
3461 | long val; | |
3462 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3463 | val = xg_apply_userdef_op_fn (op->typ, | |
3464 | targ->tok[op_num]. | |
3465 | X_add_number); | |
3466 | targ->tok[op_num].X_add_number = val; | |
3467 | } | |
3468 | else | |
3469 | return FALSE; /* We cannot use a relocation for this. */ | |
3470 | break; | |
3471 | } | |
9c2799c2 | 3472 | gas_assert (0); |
e0001a05 NC |
3473 | break; |
3474 | } | |
3475 | } | |
3476 | break; | |
3477 | ||
3478 | case INSTR_LITERAL_DEF: | |
3479 | op = bi->ops; | |
3480 | targ->opcode = XTENSA_UNDEFINED; | |
3481 | targ->insn_type = ITYPE_LITERAL; | |
3482 | targ->is_specific_opcode = FALSE; | |
3483 | for (; op != NULL; op = op->next) | |
3484 | { | |
3485 | int op_num = op->op_num; | |
3486 | int op_data = op->op_data; | |
9c2799c2 | 3487 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3488 | |
3489 | if (targ->ntok <= op_num) | |
3490 | targ->ntok = op_num + 1; | |
3491 | ||
3492 | switch (op->typ) | |
3493 | { | |
3494 | case OP_OPERAND: | |
9c2799c2 | 3495 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3496 | /* We can only pass resolvable literals through. */ |
3497 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3498 | return FALSE; | |
e0001a05 NC |
3499 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3500 | break; | |
3501 | case OP_LITERAL: | |
3502 | case OP_CONSTANT: | |
3503 | case OP_LABEL: | |
3504 | default: | |
9c2799c2 | 3505 | gas_assert (0); |
e0001a05 NC |
3506 | break; |
3507 | } | |
3508 | } | |
3509 | break; | |
3510 | ||
3511 | case INSTR_LABEL_DEF: | |
3512 | op = bi->ops; | |
3513 | targ->opcode = XTENSA_UNDEFINED; | |
3514 | targ->insn_type = ITYPE_LABEL; | |
3515 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3516 | /* Literal with no ops is a label? */ |
9c2799c2 | 3517 | gas_assert (op == NULL); |
e0001a05 NC |
3518 | break; |
3519 | ||
3520 | default: | |
9c2799c2 | 3521 | gas_assert (0); |
e0001a05 NC |
3522 | } |
3523 | ||
3524 | return TRUE; | |
3525 | } | |
3526 | ||
3527 | ||
43cd72b9 | 3528 | /* Return TRUE on success. */ |
e0001a05 | 3529 | |
7fa3d080 BW |
3530 | static bfd_boolean |
3531 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3532 | { |
3533 | for (; bi != NULL; bi = bi->next) | |
3534 | { | |
3535 | TInsn *next_insn = istack_push_space (istack); | |
3536 | ||
3537 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3538 | return FALSE; | |
3539 | } | |
3540 | return TRUE; | |
3541 | } | |
3542 | ||
3543 | ||
43cd72b9 | 3544 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3545 | |
7fa3d080 BW |
3546 | static bfd_boolean |
3547 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3548 | { |
3549 | int stack_size = istack->ninsn; | |
3550 | int steps_taken = 0; | |
43cd72b9 | 3551 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3552 | TransitionList *l; |
3553 | ||
9c2799c2 NC |
3554 | gas_assert (insn->insn_type == ITYPE_INSN); |
3555 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3556 | |
3557 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3558 | { | |
3559 | TransitionRule *rule = l->rule; | |
3560 | ||
3561 | if (xg_instruction_matches_rule (insn, rule)) | |
3562 | { | |
3563 | if (lateral_steps == steps_taken) | |
3564 | { | |
3565 | int i; | |
3566 | ||
3567 | /* This is it. Expand the rule to the stack. */ | |
3568 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3569 | return FALSE; | |
3570 | ||
3571 | /* Check to see if it fits. */ | |
3572 | for (i = stack_size; i < istack->ninsn; i++) | |
3573 | { | |
91d6fa6a | 3574 | TInsn *tinsn = &istack->insn[i]; |
e0001a05 | 3575 | |
91d6fa6a NC |
3576 | if (tinsn->insn_type == ITYPE_INSN |
3577 | && !tinsn_has_symbolic_operands (tinsn) | |
3578 | && !xg_immeds_fit (tinsn)) | |
e0001a05 NC |
3579 | { |
3580 | istack->ninsn = stack_size; | |
3581 | return FALSE; | |
3582 | } | |
3583 | } | |
3584 | return TRUE; | |
3585 | } | |
3586 | steps_taken++; | |
3587 | } | |
3588 | } | |
3589 | return FALSE; | |
3590 | } | |
3591 | ||
43cd72b9 | 3592 | \f |
43cd72b9 | 3593 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3594 | Return the number of steps taken. |
3595 | ||
3596 | For relaxation to correctly terminate, every relaxation chain must | |
3597 | terminate in one of two ways: | |
3598 | ||
3599 | 1. If the chain from one instruction to the next consists entirely of | |
3600 | single instructions, then the chain *must* handle all possible | |
3601 | immediates without failing. It must not ever fail because an | |
3602 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3603 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3604 | immediate larger than 32 bits, so it satisfies this condition. | |
3605 | Single instruction relaxation chains are as defined by | |
3606 | xg_is_single_relaxable_instruction. | |
3607 | ||
3608 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3609 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3610 | ||
3611 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3612 | -- in particular when the last two instructions have the same single | |
3613 | size. But nevertheless, you should guarantee the above two conditions. | |
3614 | ||
3615 | We could fix this so that single-instruction expansions correctly | |
3616 | terminate when they can't handle the range, but the error messages are | |
3617 | worse, and it actually turns out that in every case but one (18-bit wide | |
3618 | branches), you need a multi-instruction expansion to get the full range | |
3619 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3620 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3621 | |
7fa3d080 BW |
3622 | static int |
3623 | xg_assembly_relax (IStack *istack, | |
3624 | TInsn *insn, | |
3625 | segT pc_seg, | |
3626 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3627 | offsetT pc_offset, /* offset in fragment */ | |
3628 | int min_steps, /* minimum conversion steps */ | |
3629 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3630 | { |
3631 | int steps_taken = 0; | |
3632 | ||
b81bf389 BW |
3633 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3634 | This may go through a couple of stages of single instruction | |
3635 | transformations before we get there. */ | |
e0001a05 NC |
3636 | |
3637 | TInsn single_target; | |
3638 | TInsn current_insn; | |
3639 | int lateral_steps = 0; | |
3640 | int istack_size = istack->ninsn; | |
3641 | ||
3642 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3643 | && steps_taken >= min_steps) | |
3644 | { | |
3645 | istack_push (istack, insn); | |
3646 | return steps_taken; | |
3647 | } | |
43cd72b9 | 3648 | current_insn = *insn; |
e0001a05 | 3649 | |
7c834684 | 3650 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3651 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3652 | { |
21af2bbd | 3653 | steps_taken++; |
e0001a05 NC |
3654 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3655 | stretch)) | |
3656 | { | |
e0001a05 NC |
3657 | if (steps_taken >= min_steps) |
3658 | { | |
3659 | istack_push (istack, &single_target); | |
3660 | return steps_taken; | |
3661 | } | |
3662 | } | |
43cd72b9 | 3663 | current_insn = single_target; |
e0001a05 NC |
3664 | } |
3665 | ||
3666 | /* Now check for a multi-instruction expansion. */ | |
3667 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3668 | { | |
3669 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3670 | stretch)) | |
3671 | { | |
3672 | if (steps_taken >= min_steps) | |
3673 | { | |
3674 | istack_push (istack, ¤t_insn); | |
3675 | return steps_taken; | |
3676 | } | |
3677 | } | |
3678 | steps_taken++; | |
3679 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3680 | { | |
3681 | if (steps_taken >= min_steps) | |
3682 | return steps_taken; | |
3683 | } | |
3684 | lateral_steps++; | |
3685 | istack->ninsn = istack_size; | |
3686 | } | |
3687 | ||
3688 | /* It's not going to work -- use the original. */ | |
3689 | istack_push (istack, insn); | |
3690 | return steps_taken; | |
3691 | } | |
3692 | ||
3693 | ||
7fa3d080 BW |
3694 | static void |
3695 | xg_finish_frag (char *last_insn, | |
3696 | enum xtensa_relax_statesE frag_state, | |
3697 | enum xtensa_relax_statesE slot0_state, | |
3698 | int max_growth, | |
3699 | bfd_boolean is_insn) | |
e0001a05 NC |
3700 | { |
3701 | /* Finish off this fragment so that it has at LEAST the desired | |
3702 | max_growth. If it doesn't fit in this fragment, close this one | |
3703 | and start a new one. In either case, return a pointer to the | |
3704 | beginning of the growth area. */ | |
3705 | ||
3706 | fragS *old_frag; | |
43cd72b9 | 3707 | |
542f8b94 | 3708 | frag_grow (max_growth); |
e0001a05 NC |
3709 | old_frag = frag_now; |
3710 | ||
3711 | frag_now->fr_opcode = last_insn; | |
3712 | if (is_insn) | |
3713 | frag_now->tc_frag_data.is_insn = TRUE; | |
3714 | ||
3715 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3716 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3717 | ||
3718 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3719 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3720 | |
3721 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3722 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3723 | } |
3724 | ||
3725 | ||
7fa3d080 BW |
3726 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3727 | ||
3728 | static bfd_boolean | |
3729 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3730 | { | |
3731 | if (fragP == NULL) | |
3732 | return FALSE; | |
3733 | ||
3734 | for (; fragP; fragP = fragP->fr_next) | |
3735 | { | |
3736 | if (fragP == target) | |
3737 | return TRUE; | |
3738 | if (fragP->fr_fix != 0) | |
3739 | return FALSE; | |
3740 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3741 | return FALSE; | |
3742 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3743 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3744 | return FALSE; | |
3745 | if (fragP->fr_type == rs_space) | |
3746 | return FALSE; | |
3747 | } | |
3748 | return FALSE; | |
3749 | } | |
3750 | ||
3751 | ||
e0001a05 | 3752 | static bfd_boolean |
7fa3d080 | 3753 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3754 | { |
3755 | xtensa_isa isa = xtensa_default_isa; | |
3756 | int i; | |
43cd72b9 | 3757 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3758 | int target_op = -1; |
3759 | symbolS *sym; | |
3760 | fragS *target_frag; | |
3761 | ||
64b607e6 BW |
3762 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3763 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3764 | return FALSE; |
3765 | ||
3766 | for (i = 0; i < num_ops; i++) | |
3767 | { | |
43cd72b9 | 3768 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3769 | { |
3770 | target_op = i; | |
3771 | break; | |
3772 | } | |
3773 | } | |
3774 | if (target_op == -1) | |
3775 | return FALSE; | |
3776 | ||
3777 | if (insn->ntok <= target_op) | |
3778 | return FALSE; | |
3779 | ||
3780 | if (insn->tok[target_op].X_op != O_symbol) | |
3781 | return FALSE; | |
3782 | ||
3783 | sym = insn->tok[target_op].X_add_symbol; | |
3784 | if (sym == NULL) | |
3785 | return FALSE; | |
3786 | ||
3787 | if (insn->tok[target_op].X_add_number != 0) | |
3788 | return FALSE; | |
3789 | ||
3790 | target_frag = symbol_get_frag (sym); | |
3791 | if (target_frag == NULL) | |
3792 | return FALSE; | |
3793 | ||
c138bc38 | 3794 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3795 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3796 | return TRUE; | |
3797 | ||
3798 | return FALSE; | |
3799 | } | |
3800 | ||
3801 | ||
3802 | static void | |
7fa3d080 | 3803 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3804 | { |
3805 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3806 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3807 | |
7fa3d080 BW |
3808 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3809 | { | |
3810 | int i = 1; | |
3811 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3812 | && insn->tok[i].X_op == O_symbol) | |
3813 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3814 | return; | |
3815 | } | |
e0001a05 | 3816 | |
7fa3d080 BW |
3817 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3818 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3819 | { |
7fa3d080 BW |
3820 | int i; |
3821 | ||
3822 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3823 | { | |
3824 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3825 | && insn->tok[i].X_op == O_symbol) | |
3826 | { | |
3827 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3828 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3829 | if (S_IS_DEFINED (sym)) | |
3830 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3831 | } | |
3832 | } | |
e0001a05 | 3833 | } |
e0001a05 NC |
3834 | } |
3835 | ||
3836 | ||
43cd72b9 | 3837 | /* Return FALSE if no error. */ |
e0001a05 | 3838 | |
7fa3d080 BW |
3839 | static bfd_boolean |
3840 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3841 | { |
3842 | int num_ops = 0; | |
3843 | BuildOp *b_op; | |
3844 | ||
3845 | switch (instr_spec->typ) | |
3846 | { | |
3847 | case INSTR_INSTR: | |
3848 | new_insn->insn_type = ITYPE_INSN; | |
3849 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3850 | break; |
3851 | case INSTR_LITERAL_DEF: | |
3852 | new_insn->insn_type = ITYPE_LITERAL; | |
3853 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3854 | break; |
3855 | case INSTR_LABEL_DEF: | |
b224e962 | 3856 | abort (); |
e0001a05 | 3857 | } |
b224e962 BW |
3858 | new_insn->is_specific_opcode = FALSE; |
3859 | new_insn->debug_line = old_insn->debug_line; | |
3860 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3861 | |
3862 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3863 | { | |
3864 | expressionS *exp; | |
3865 | const expressionS *src_exp; | |
3866 | ||
3867 | num_ops++; | |
3868 | switch (b_op->typ) | |
3869 | { | |
3870 | case OP_CONSTANT: | |
3871 | /* The expression must be the constant. */ | |
9c2799c2 | 3872 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3873 | exp = &new_insn->tok[b_op->op_num]; |
3874 | set_expr_const (exp, b_op->op_data); | |
3875 | break; | |
3876 | ||
3877 | case OP_OPERAND: | |
9c2799c2 NC |
3878 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
3879 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
3880 | src_exp = &old_insn->tok[b_op->op_data]; |
3881 | exp = &new_insn->tok[b_op->op_num]; | |
3882 | copy_expr (exp, src_exp); | |
3883 | break; | |
3884 | ||
3885 | case OP_LITERAL: | |
3886 | case OP_LABEL: | |
3887 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 3888 | gas_assert (0); |
e0001a05 NC |
3889 | |
3890 | default: | |
3891 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 3892 | gas_assert (0); |
e0001a05 NC |
3893 | } |
3894 | } | |
3895 | ||
3896 | new_insn->ntok = num_ops; | |
3897 | return FALSE; | |
3898 | } | |
3899 | ||
3900 | ||
43cd72b9 | 3901 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3902 | |
7fa3d080 BW |
3903 | static bfd_boolean |
3904 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3905 | { |
43cd72b9 | 3906 | TransitionRule *rule; |
e0001a05 | 3907 | BuildInstr *insn_spec; |
43cd72b9 BW |
3908 | |
3909 | if (old_insn->is_specific_opcode || !density_supported) | |
3910 | return FALSE; | |
3911 | ||
3912 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3913 | if (rule == NULL) |
3914 | return FALSE; | |
3915 | ||
3916 | insn_spec = rule->to_instr; | |
3917 | /* There should only be one. */ | |
9c2799c2 NC |
3918 | gas_assert (insn_spec != NULL); |
3919 | gas_assert (insn_spec->next == NULL); | |
e0001a05 NC |
3920 | if (insn_spec->next != NULL) |
3921 | return FALSE; | |
3922 | ||
3923 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3924 | ||
3925 | return TRUE; | |
3926 | } | |
3927 | ||
3928 | ||
3929 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3930 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3931 | tokens into the stack or relax it and place multiple |
3932 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3933 | |
3934 | static bfd_boolean | |
7fa3d080 | 3935 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3936 | { |
3937 | int noperands; | |
3938 | TInsn new_insn; | |
7c834684 BW |
3939 | bfd_boolean do_expand; |
3940 | ||
60242db2 | 3941 | tinsn_init (&new_insn); |
e0001a05 | 3942 | |
43cd72b9 BW |
3943 | /* Narrow it if we can. xg_simplify_insn now does all the |
3944 | appropriate checking (e.g., for the density option). */ | |
3945 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3946 | orig_insn = &new_insn; | |
e0001a05 | 3947 | |
43cd72b9 BW |
3948 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3949 | orig_insn->opcode); | |
e0001a05 NC |
3950 | if (orig_insn->ntok < noperands) |
3951 | { | |
3952 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3953 | orig_insn->ntok, | |
3954 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3955 | noperands); | |
3956 | return TRUE; | |
3957 | } | |
3958 | if (orig_insn->ntok > noperands) | |
3959 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3960 | orig_insn->ntok, | |
3961 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3962 | noperands); | |
3963 | ||
43cd72b9 | 3964 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3965 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3966 | orig_insn->ntok = noperands; |
3967 | ||
e0001a05 NC |
3968 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3969 | return TRUE; | |
3970 | ||
d12f9798 BW |
3971 | /* Special case for extui opcode which has constraints not handled |
3972 | by the ordinary operand encoding checks. The number of operands | |
3973 | and related syntax issues have already been checked. */ | |
3974 | if (orig_insn->opcode == xtensa_extui_opcode) | |
3975 | { | |
3976 | int shiftimm = orig_insn->tok[2].X_add_number; | |
3977 | int maskimm = orig_insn->tok[3].X_add_number; | |
3978 | if (shiftimm + maskimm > 32) | |
3979 | { | |
3980 | as_bad (_("immediate operands sum to greater than 32")); | |
3981 | return TRUE; | |
3982 | } | |
3983 | } | |
3984 | ||
7c834684 BW |
3985 | /* If the instruction will definitely need to be relaxed, it is better |
3986 | to expand it now for better scheduling. Decide whether to expand | |
3987 | now.... */ | |
3988 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3989 | ||
3990 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3991 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3992 | adjacent. */ | |
3993 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3994 | do_expand = FALSE; | |
e0001a05 NC |
3995 | |
3996 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3997 | { | |
7c834684 BW |
3998 | /* The values of symbolic operands are not known yet, so only expand |
3999 | now if an operand is "complex" (e.g., difference of symbols) and | |
4000 | will have to be stored as a literal regardless of the value. */ | |
4001 | if (!tinsn_has_complex_operands (orig_insn)) | |
4002 | do_expand = FALSE; | |
e0001a05 | 4003 | } |
7c834684 BW |
4004 | else if (xg_immeds_fit (orig_insn)) |
4005 | do_expand = FALSE; | |
4006 | ||
4007 | if (do_expand) | |
4008 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4009 | else |
7c834684 | 4010 | istack_push (istack, orig_insn); |
e0001a05 | 4011 | |
e0001a05 NC |
4012 | return FALSE; |
4013 | } | |
4014 | ||
4015 | ||
7fa3d080 | 4016 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4017 | or the name is .gnu.linkonce.*. */ |
4018 | ||
4019 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
4020 | |
4021 | static bfd_boolean | |
4022 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4023 | { | |
4024 | flagword flags, link_once_flags; | |
4025 | ||
4026 | flags = bfd_get_section_flags (abfd, sec); | |
4027 | link_once_flags = (flags & SEC_LINK_ONCE); | |
4028 | ||
4029 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4030 | if (!link_once_flags |
4031 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4032 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4033 | |
7fa3d080 BW |
4034 | return (link_once_flags != 0); |
4035 | } | |
4036 | ||
4037 | ||
4038 | static void | |
4039 | xtensa_add_literal_sym (symbolS *sym) | |
4040 | { | |
4041 | sym_list *l; | |
4042 | ||
4043 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
4044 | l->sym = sym; | |
4045 | l->next = literal_syms; | |
4046 | literal_syms = l; | |
4047 | } | |
4048 | ||
4049 | ||
4050 | static symbolS * | |
4051 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4052 | { | |
4053 | static int lit_num = 0; | |
4054 | static char name[256]; | |
4055 | symbolS *symbolP; | |
4056 | ||
4057 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4058 | ||
4059 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4060 | be careful to make sure that if it is used in a relocation that the | |
4061 | symbol will be in the output file. */ | |
4062 | if (get_is_linkonce_section (stdoutput, sec)) | |
4063 | { | |
4064 | symbolP = symbol_new (name, sec, 0, frag); | |
4065 | S_CLEAR_EXTERNAL (symbolP); | |
4066 | /* symbolP->local = 1; */ | |
4067 | } | |
4068 | else | |
4069 | symbolP = symbol_new (name, sec, 0, frag); | |
4070 | ||
4071 | xtensa_add_literal_sym (symbolP); | |
4072 | ||
7fa3d080 BW |
4073 | lit_num++; |
4074 | return symbolP; | |
4075 | } | |
4076 | ||
4077 | ||
e0001a05 NC |
4078 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4079 | ||
7fa3d080 BW |
4080 | static symbolS * |
4081 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4082 | { |
4083 | emit_state state; | |
4084 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4085 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4086 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4087 | char *p; |
e0001a05 NC |
4088 | |
4089 | /* size = 4 for L32R. It could easily be larger when we move to | |
4090 | larger constants. Add a parameter later. */ | |
4091 | offsetT litsize = 4; | |
4092 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4093 | expressionS saved_loc; | |
43cd72b9 BW |
4094 | expressionS * emit_val; |
4095 | ||
e0001a05 NC |
4096 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4097 | ||
9c2799c2 NC |
4098 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4099 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4100 | |
4101 | xtensa_switch_to_literal_fragment (&state); | |
4102 | ||
43cd72b9 BW |
4103 | emit_val = &insn->tok[0]; |
4104 | if (emit_val->X_op == O_big) | |
4105 | { | |
4106 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4107 | if (size > litsize) | |
4108 | { | |
4109 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4110 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4111 | _("invalid immediate")); |
4112 | xtensa_restore_emit_state (&state); | |
4113 | return NULL; | |
4114 | } | |
4115 | } | |
4116 | ||
e0001a05 NC |
4117 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4118 | literals done with this function have a frag to themselves. That's | |
4119 | important for the way text section literals work. */ | |
4120 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4121 | record_alignment (now_seg, litalign); |
e0001a05 | 4122 | |
bbdd25a8 | 4123 | switch (emit_val->X_op) |
43cd72b9 | 4124 | { |
1bbb5f21 BW |
4125 | case O_pcrel: |
4126 | pcrel = TRUE; | |
4127 | /* fall through */ | |
bbdd25a8 | 4128 | case O_pltrel: |
28dbbc02 BW |
4129 | case O_tlsfunc: |
4130 | case O_tlsarg: | |
4131 | case O_tpoff: | |
4132 | case O_dtpoff: | |
bbdd25a8 | 4133 | p = frag_more (litsize); |
43cd72b9 | 4134 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4135 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4136 | if (emit_val->X_add_symbol) |
4137 | emit_val->X_op = O_symbol; | |
4138 | else | |
4139 | emit_val->X_op = O_constant; | |
4140 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4141 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4142 | break; |
4143 | ||
4144 | default: | |
4145 | emit_expr (emit_val, litsize); | |
4146 | break; | |
43cd72b9 | 4147 | } |
e0001a05 | 4148 | |
9c2799c2 | 4149 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4150 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4151 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4152 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4153 | |
4154 | /* Go back. */ | |
4155 | xtensa_restore_emit_state (&state); | |
4156 | return lit_sym; | |
4157 | } | |
4158 | ||
4159 | ||
4160 | static void | |
7fa3d080 | 4161 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4162 | { |
4163 | emit_state state; | |
43cd72b9 | 4164 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4165 | takes effect if something is placed here. */ |
4166 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4167 | fragS *lit_saved_frag; | |
4168 | ||
9c2799c2 | 4169 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4170 | |
4171 | xtensa_switch_to_literal_fragment (&state); | |
4172 | ||
4173 | /* Force a 4-byte align here. */ | |
4174 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4175 | record_alignment (now_seg, litalign); |
e0001a05 | 4176 | |
542f8b94 | 4177 | frag_grow (size); |
e0001a05 NC |
4178 | |
4179 | lit_saved_frag = frag_now; | |
4180 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4181 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4182 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4183 | |
4184 | /* Go back. */ | |
4185 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4186 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4187 | } |
4188 | ||
4189 | ||
e0001a05 | 4190 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4191 | Return TRUE on success. */ |
e0001a05 | 4192 | |
7fa3d080 BW |
4193 | static bfd_boolean |
4194 | xg_add_opcode_fix (TInsn *tinsn, | |
4195 | int opnum, | |
4196 | xtensa_format fmt, | |
4197 | int slot, | |
91d6fa6a | 4198 | expressionS *exp, |
7fa3d080 BW |
4199 | fragS *fragP, |
4200 | offsetT offset) | |
43cd72b9 BW |
4201 | { |
4202 | xtensa_opcode opcode = tinsn->opcode; | |
4203 | bfd_reloc_code_real_type reloc; | |
4204 | reloc_howto_type *howto; | |
4205 | int fmt_length; | |
e0001a05 NC |
4206 | fixS *the_fix; |
4207 | ||
43cd72b9 BW |
4208 | reloc = BFD_RELOC_NONE; |
4209 | ||
4210 | /* First try the special cases for "alternate" relocs. */ | |
4211 | if (opcode == xtensa_l32r_opcode) | |
4212 | { | |
4213 | if (fragP->tc_frag_data.use_absolute_literals) | |
4214 | reloc = encode_alt_reloc (slot); | |
4215 | } | |
4216 | else if (opcode == xtensa_const16_opcode) | |
4217 | { | |
91d6fa6a | 4218 | if (exp->X_op == O_lo16) |
43cd72b9 BW |
4219 | { |
4220 | reloc = encode_reloc (slot); | |
91d6fa6a | 4221 | exp->X_op = O_symbol; |
43cd72b9 | 4222 | } |
91d6fa6a | 4223 | else if (exp->X_op == O_hi16) |
43cd72b9 BW |
4224 | { |
4225 | reloc = encode_alt_reloc (slot); | |
91d6fa6a | 4226 | exp->X_op = O_symbol; |
43cd72b9 BW |
4227 | } |
4228 | } | |
4229 | ||
4230 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4231 | { |
43cd72b9 | 4232 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4233 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4234 | return FALSE; |
4235 | } | |
4236 | ||
43cd72b9 BW |
4237 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4238 | into the symbol table where the generic portions of the assembler | |
4239 | won't know what to do with them. */ | |
91d6fa6a | 4240 | if (exp->X_op == O_lo16 || exp->X_op == O_hi16) |
43cd72b9 BW |
4241 | { |
4242 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4243 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4244 | return FALSE; |
4245 | } | |
4246 | ||
4247 | /* Next try the generic relocs. */ | |
4248 | if (reloc == BFD_RELOC_NONE) | |
4249 | reloc = encode_reloc (slot); | |
4250 | if (reloc == BFD_RELOC_NONE) | |
4251 | { | |
4252 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4253 | return FALSE; | |
4254 | } | |
e0001a05 | 4255 | |
43cd72b9 | 4256 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4257 | if (!howto) |
4258 | { | |
43cd72b9 | 4259 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4260 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4261 | return FALSE; | |
4262 | } | |
4263 | ||
43cd72b9 | 4264 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
91d6fa6a | 4265 | the_fix = fix_new_exp (fragP, offset, fmt_length, exp, |
e0001a05 | 4266 | howto->pc_relative, reloc); |
d9740523 | 4267 | the_fix->fx_no_overflow = 1; |
91d6fa6a NC |
4268 | the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; |
4269 | the_fix->tc_fix_data.X_add_number = exp->X_add_number; | |
7fa3d080 | 4270 | the_fix->tc_fix_data.slot = slot; |
c138bc38 | 4271 | |
7fa3d080 BW |
4272 | return TRUE; |
4273 | } | |
4274 | ||
4275 | ||
4276 | static bfd_boolean | |
4277 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4278 | char *buf, |
4279 | fragS *fragP, | |
4280 | offsetT offset, | |
4281 | bfd_boolean build_fix) | |
4282 | { | |
4283 | static xtensa_insnbuf insnbuf = NULL; | |
4284 | bfd_boolean has_symbolic_immed = FALSE; | |
4285 | bfd_boolean ok = TRUE; | |
b2d179be | 4286 | |
7fa3d080 BW |
4287 | if (!insnbuf) |
4288 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4289 | ||
4290 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4291 | if (has_symbolic_immed && build_fix) | |
4292 | { | |
4293 | /* Add a fixup. */ | |
b2d179be BW |
4294 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4295 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4296 | int opnum = get_relaxable_immed (tinsn->opcode); |
4297 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4298 | |
b2d179be | 4299 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4300 | ok = FALSE; |
4301 | } | |
4302 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4303 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4304 | (unsigned char *) buf, 0); | |
7fa3d080 | 4305 | return ok; |
e0001a05 NC |
4306 | } |
4307 | ||
4308 | ||
7fa3d080 BW |
4309 | static void |
4310 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4311 | { |
4312 | symbolS *sym = get_special_literal_symbol (); | |
4313 | int i; | |
4314 | if (lit_sym == 0) | |
4315 | return; | |
9c2799c2 | 4316 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4317 | for (i = 0; i < insn->ntok; i++) |
4318 | if (insn->tok[i].X_add_symbol == sym) | |
4319 | insn->tok[i].X_add_symbol = lit_sym; | |
4320 | ||
4321 | } | |
4322 | ||
4323 | ||
7fa3d080 BW |
4324 | static void |
4325 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4326 | { |
4327 | symbolS *sym = get_special_label_symbol (); | |
4328 | int i; | |
e0001a05 NC |
4329 | for (i = 0; i < insn->ntok; i++) |
4330 | if (insn->tok[i].X_add_symbol == sym) | |
4331 | insn->tok[i].X_add_symbol = label_sym; | |
4332 | ||
4333 | } | |
4334 | ||
4335 | ||
43cd72b9 | 4336 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4337 | integer register. */ |
4338 | ||
4339 | static bfd_boolean | |
7fa3d080 | 4340 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4341 | { |
4342 | int i; | |
4343 | int num_ops; | |
4344 | xtensa_isa isa = xtensa_default_isa; | |
4345 | ||
43cd72b9 | 4346 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4347 | |
4348 | for (i = 0; i < num_ops; i++) | |
4349 | { | |
43cd72b9 BW |
4350 | char inout; |
4351 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4352 | if ((inout == 'o' || inout == 'm') | |
4353 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4354 | { |
43cd72b9 BW |
4355 | xtensa_regfile opnd_rf = |
4356 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4357 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4358 | { |
4359 | if ((insn->tok[i].X_op == O_register) | |
4360 | && (insn->tok[i].X_add_number == regnum)) | |
4361 | return TRUE; | |
4362 | } | |
4363 | } | |
4364 | } | |
4365 | return FALSE; | |
4366 | } | |
4367 | ||
4368 | ||
4369 | static bfd_boolean | |
7fa3d080 | 4370 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4371 | { |
4372 | xtensa_opcode opcode = tinsn->opcode; | |
4373 | ||
4374 | if (opcode == XTENSA_UNDEFINED) | |
4375 | return FALSE; | |
4376 | ||
4377 | if (opcode == xtensa_call0_opcode | |
4378 | || opcode == xtensa_callx0_opcode | |
4379 | || opcode == xtensa_call4_opcode | |
4380 | || opcode == xtensa_callx4_opcode | |
4381 | || opcode == xtensa_call8_opcode | |
4382 | || opcode == xtensa_callx8_opcode | |
4383 | || opcode == xtensa_call12_opcode | |
4384 | || opcode == xtensa_callx12_opcode | |
4385 | || opcode == xtensa_isync_opcode | |
4386 | || opcode == xtensa_ret_opcode | |
4387 | || opcode == xtensa_ret_n_opcode | |
4388 | || opcode == xtensa_retw_opcode | |
4389 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4390 | || opcode == xtensa_waiti_opcode |
4391 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4392 | return TRUE; |
c138bc38 | 4393 | |
e0001a05 NC |
4394 | return FALSE; |
4395 | } | |
4396 | ||
4397 | ||
4398 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4399 | This allows the debugger to add unaligned labels. | |
4400 | Also, the assembler generates stabs labels that need | |
4401 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4402 | ||
7fa3d080 BW |
4403 | static bfd_boolean |
4404 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4405 | { |
4406 | const char *name = S_GET_NAME (sym); | |
4407 | static size_t fake_size = 0; | |
4408 | ||
4409 | if (name | |
4410 | && name[0] == '.' | |
4411 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4412 | return TRUE; | |
4413 | ||
4414 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4415 | if (fake_size == 0) | |
4416 | fake_size = strlen (FAKE_LABEL_NAME); | |
4417 | ||
43cd72b9 | 4418 | if (name |
e0001a05 NC |
4419 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4420 | && (name[fake_size] == 'F' | |
4421 | || name[fake_size] == 'L' | |
4422 | || (name[fake_size] == 'e' | |
4423 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4424 | return TRUE; | |
4425 | ||
4426 | return FALSE; | |
4427 | } | |
4428 | ||
4429 | ||
7fa3d080 BW |
4430 | static fragS * |
4431 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4432 | { |
4433 | fragS *next_fragP = fragP->fr_next; | |
4434 | ||
c138bc38 | 4435 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4436 | So we have to skip until we find something legit. */ |
4437 | while (next_fragP && next_fragP->fr_fix == 0) | |
4438 | next_fragP = next_fragP->fr_next; | |
4439 | ||
4440 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4441 | return NULL; | |
4442 | ||
4443 | return next_fragP; | |
4444 | } | |
4445 | ||
4446 | ||
43cd72b9 | 4447 | static bfd_boolean |
7fa3d080 | 4448 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4449 | { |
4450 | xtensa_opcode out_opcode; | |
4451 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4452 | ||
4453 | if (next_fragP == NULL) | |
4454 | return FALSE; | |
4455 | ||
4456 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4457 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4458 | { | |
4459 | *opcode = out_opcode; | |
4460 | return TRUE; | |
4461 | } | |
4462 | return FALSE; | |
4463 | } | |
4464 | ||
4465 | ||
4466 | static int | |
7fa3d080 | 4467 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4468 | { |
e0001a05 NC |
4469 | static xtensa_insnbuf insnbuf = NULL; |
4470 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4471 | xtensa_format fmt; |
c138bc38 | 4472 | int fmt_size; |
e0001a05 NC |
4473 | |
4474 | if (!insnbuf) | |
4475 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4476 | ||
43cd72b9 BW |
4477 | if (fragP == NULL) |
4478 | return XTENSA_UNDEFINED; | |
4479 | ||
d77b99c9 BW |
4480 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4481 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4482 | |
4483 | fmt = xtensa_format_decode (isa, insnbuf); | |
4484 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4485 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4486 | fmt_size = xtensa_format_length (isa, fmt); |
4487 | ||
4488 | /* If the next format won't be changing due to relaxation, just | |
4489 | return the length of the first format. */ | |
4490 | if (fragP->fr_opcode != fragP->fr_literal) | |
4491 | return fmt_size; | |
4492 | ||
c138bc38 | 4493 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4494 | multi-slot instruction, we will return the more conservative |
4495 | number. This works because alignment on bigger instructions | |
4496 | is more restrictive than alignment on smaller instructions. | |
4497 | This is more conservative than we would like, but it happens | |
4498 | infrequently. */ | |
4499 | ||
4500 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4501 | return fmt_size; | |
4502 | ||
4503 | /* If we aren't doing one of our own relaxations or it isn't | |
4504 | slot-based, then the insn size won't change. */ | |
4505 | if (fragP->fr_type != rs_machine_dependent) | |
4506 | return fmt_size; | |
4507 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4508 | return fmt_size; | |
4509 | ||
4510 | /* If an instruction is about to grow, return the longer size. */ | |
4511 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4512 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4513 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4514 | { |
4515 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4516 | instruction in the relaxed version is of length 3. (The case | |
4517 | where we have to pull the instruction out of a FLIX bundle | |
4518 | is handled conservatively above.) However, frags with opcodes | |
4519 | that are expanding to wide branches end up having formats that | |
4520 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4521 | we can't tell directly what format the relaxer picked. This | |
4522 | is a wart in the design of the relaxer that should someday be | |
4523 | fixed, but would require major changes, or at least should | |
4524 | be accompanied by major changes to make use of that data. | |
4525 | ||
4526 | In any event, we can tell that we are expanding from a single-slot | |
4527 | three-byte format to a wider one with the logic below. */ | |
4528 | ||
4529 | if (fmt_size <= 3 && fragP->tc_frag_data.text_expansion[0] != 3) | |
4530 | return 3 + fragP->tc_frag_data.text_expansion[0]; | |
4531 | else | |
4532 | return 3; | |
4533 | } | |
c138bc38 | 4534 | |
43cd72b9 BW |
4535 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4536 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4537 | |
43cd72b9 | 4538 | return fmt_size; |
e0001a05 NC |
4539 | } |
4540 | ||
4541 | ||
7fa3d080 BW |
4542 | static int |
4543 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4544 | { |
7fa3d080 BW |
4545 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4546 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4547 | } |
4548 | ||
4549 | ||
03aaa593 BW |
4550 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4551 | required two-byte instructions to be treated as three-byte instructions | |
4552 | for loop instruction alignment. This restriction was removed beginning | |
4553 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4554 | is that the first instruction of the loop must appear at an address that | |
4555 | does not cross a fetch boundary. */ | |
4556 | ||
4557 | static int | |
4558 | get_loop_align_size (int insn_size) | |
4559 | { | |
4560 | if (insn_size == XTENSA_UNDEFINED) | |
4561 | return xtensa_fetch_width; | |
4562 | ||
4563 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4564 | return 3; | |
4565 | ||
4566 | return insn_size; | |
4567 | } | |
4568 | ||
4569 | ||
e0001a05 NC |
4570 | /* If the next legit fragment is an end-of-loop marker, |
4571 | switch its state so it will instantiate a NOP. */ | |
4572 | ||
4573 | static void | |
1d19a770 | 4574 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4575 | { |
4576 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4577 | fragS *new_target = NULL; |
e0001a05 | 4578 | |
7b1cc377 | 4579 | if (align_targets) |
43cd72b9 BW |
4580 | { |
4581 | /* We are guaranteed there will be one of these... */ | |
4582 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4583 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4584 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4585 | next_fragP = next_fragP->fr_next; | |
4586 | ||
9c2799c2 | 4587 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4588 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4589 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4590 | ||
4591 | /* ...and one of these. */ | |
4592 | new_target = next_fragP->fr_next; | |
4593 | while (!(new_target->fr_type == rs_machine_dependent | |
4594 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4595 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4596 | new_target = new_target->fr_next; | |
4597 | ||
9c2799c2 | 4598 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4599 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4600 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4601 | } | |
43cd72b9 | 4602 | |
1d19a770 | 4603 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4604 | { |
1d19a770 BW |
4605 | if (next_fragP->fr_type == rs_machine_dependent |
4606 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4607 | { |
1d19a770 BW |
4608 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4609 | return; | |
e0001a05 | 4610 | } |
1d19a770 BW |
4611 | |
4612 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4613 | } |
4614 | } | |
4615 | ||
4616 | ||
4617 | static bfd_boolean | |
7fa3d080 | 4618 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4619 | { |
43cd72b9 | 4620 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4621 | so we have to skip until we find something legit. */ |
4622 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4623 | { | |
4624 | if (fragP->tc_frag_data.is_branch_target) | |
4625 | return TRUE; | |
4626 | if (fragP->fr_fix != 0) | |
4627 | break; | |
4628 | } | |
4629 | return FALSE; | |
4630 | } | |
4631 | ||
4632 | ||
4633 | static bfd_boolean | |
7fa3d080 | 4634 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4635 | { |
c138bc38 | 4636 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4637 | So we have to skip until we find something legit. */ |
4638 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4639 | { | |
4640 | if (fragP->tc_frag_data.is_loop_target) | |
4641 | return TRUE; | |
4642 | if (fragP->fr_fix != 0) | |
4643 | break; | |
4644 | } | |
4645 | return FALSE; | |
4646 | } | |
4647 | ||
4648 | ||
4649 | static addressT | |
7fa3d080 | 4650 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4651 | { |
4652 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4653 | xtensa_opcode next_opcode; |
e0001a05 | 4654 | |
43cd72b9 | 4655 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4656 | return 0; |
4657 | ||
43cd72b9 BW |
4658 | /* Sometimes an empty will end up here due to storage allocation issues, |
4659 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4660 | while (next_fragp->fr_fix == 0) |
4661 | next_fragp = next_fragp->fr_next; | |
4662 | ||
4663 | if (next_fragp->fr_type != rs_machine_dependent) | |
4664 | return 0; | |
4665 | ||
4666 | /* There is some implicit knowledge encoded in here. | |
4667 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4668 | been relaxed. Note that we can assume that the LOOP |
4669 | instruction is in slot 0 because loops aren't bundleable. */ | |
4670 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4671 | return get_expanded_loop_offset (next_opcode); |
4672 | ||
4673 | return 0; | |
4674 | } | |
4675 | ||
4676 | ||
4677 | /* Mark a location where we can later insert literal frags. Update | |
4678 | the section's literal_pool_loc, so subsequent literals can be | |
4679 | placed nearest to their use. */ | |
4680 | ||
4681 | static void | |
7fa3d080 | 4682 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4683 | { |
4684 | /* Any labels pointing to the current location need | |
4685 | to be adjusted to after the literal pool. */ | |
4686 | emit_state s; | |
e0001a05 | 4687 | fragS *pool_location; |
e0001a05 | 4688 | |
1f2a7e38 | 4689 | if (use_literal_section) |
43cd72b9 BW |
4690 | return; |
4691 | ||
dd49a749 BW |
4692 | /* We stash info in these frags so we can later move the literal's |
4693 | fixes into this frchain's fix list. */ | |
e0001a05 | 4694 | pool_location = frag_now; |
dd49a749 | 4695 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4696 | frag_now->tc_frag_data.literal_frag = frag_now; |
dd49a749 | 4697 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4698 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4699 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4700 | frag_now->tc_frag_data.lit_seg = now_seg; |
4701 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4702 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4703 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4704 | |
4705 | /* Now put a frag into the literal pool that points to this location. */ | |
4706 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4707 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4708 | frag_align (2, 0, 0); | |
4709 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4710 | |
4711 | /* Close whatever frag is there. */ | |
4712 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4713 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4714 | frag_now->tc_frag_data.literal_frag = pool_location; |
4715 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4716 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4717 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4718 | } |
4719 | ||
4720 | ||
43cd72b9 BW |
4721 | /* Build a nop of the correct size into tinsn. */ |
4722 | ||
4723 | static void | |
7fa3d080 | 4724 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4725 | { |
4726 | tinsn_init (tinsn); | |
4727 | switch (size) | |
4728 | { | |
4729 | case 2: | |
4730 | tinsn->opcode = xtensa_nop_n_opcode; | |
4731 | tinsn->ntok = 0; | |
4732 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4733 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4734 | break; | |
4735 | ||
4736 | case 3: | |
4737 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4738 | { | |
4739 | tinsn->opcode = xtensa_or_opcode; | |
4740 | set_expr_const (&tinsn->tok[0], 1); | |
4741 | set_expr_const (&tinsn->tok[1], 1); | |
4742 | set_expr_const (&tinsn->tok[2], 1); | |
4743 | tinsn->ntok = 3; | |
4744 | } | |
4745 | else | |
4746 | tinsn->opcode = xtensa_nop_opcode; | |
4747 | ||
9c2799c2 | 4748 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4749 | } |
4750 | } | |
4751 | ||
4752 | ||
e0001a05 NC |
4753 | /* Assemble a NOP of the requested size in the buffer. User must have |
4754 | allocated "buf" with at least "size" bytes. */ | |
4755 | ||
7fa3d080 | 4756 | static void |
d77b99c9 | 4757 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4758 | { |
4759 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4760 | TInsn tinsn; |
e0001a05 | 4761 | |
43cd72b9 | 4762 | build_nop (&tinsn, size); |
e0001a05 | 4763 | |
43cd72b9 BW |
4764 | if (!insnbuf) |
4765 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4766 | |
43cd72b9 | 4767 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4768 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4769 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4770 | } |
4771 | ||
4772 | ||
4773 | /* Return the number of bytes for the offset of the expanded loop | |
4774 | instruction. This should be incorporated into the relaxation | |
4775 | specification but is hard-coded here. This is used to auto-align | |
4776 | the loop instruction. It is invalid to call this function if the | |
4777 | configuration does not have loops or if the opcode is not a loop | |
4778 | opcode. */ | |
4779 | ||
4780 | static addressT | |
7fa3d080 | 4781 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4782 | { |
4783 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4784 | This MUST correspond directly to the specification of the loop | |
4785 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4786 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4787 | if (opcode == xtensa_loop_opcode) |
4788 | return 0; | |
4789 | if (opcode == xtensa_loopnez_opcode) | |
4790 | return 3; | |
4791 | if (opcode == xtensa_loopgtz_opcode) | |
4792 | return 6; | |
4793 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4794 | return 0; | |
4795 | } | |
4796 | ||
4797 | ||
7fa3d080 BW |
4798 | static fragS * |
4799 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4800 | { |
4801 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4802 | } | |
4803 | ||
4804 | ||
4805 | static void | |
7fa3d080 | 4806 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4807 | { |
4808 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4809 | } | |
4810 | ||
43cd72b9 BW |
4811 | |
4812 | /* Set frag assembly state should be called when a new frag is | |
4813 | opened and after a frag has been closed. */ | |
4814 | ||
7fa3d080 BW |
4815 | static void |
4816 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4817 | { |
4818 | if (!density_supported) | |
4819 | fragP->tc_frag_data.is_no_density = TRUE; | |
4820 | ||
4821 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4822 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4823 | "use_schedule" here. */ |
4824 | if (!directive_state[directive_transform]) | |
4825 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4826 | if (directive_state[directive_longcalls]) |
4827 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4828 | fragP->tc_frag_data.use_absolute_literals = |
4829 | directive_state[directive_absolute_literals]; | |
4830 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4831 | } | |
4832 | ||
4833 | ||
7fa3d080 BW |
4834 | static bfd_boolean |
4835 | relaxable_section (asection *sec) | |
43cd72b9 | 4836 | { |
11ac2671 BW |
4837 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4838 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4839 | } |
4840 | ||
4841 | ||
99ded152 BW |
4842 | static void |
4843 | xtensa_mark_frags_for_org (void) | |
4844 | { | |
4845 | segT *seclist; | |
4846 | ||
4847 | /* Walk over each fragment of all of the current segments. If we find | |
4848 | a .org frag in any of the segments, mark all frags prior to it as | |
4849 | "no transform", which will prevent linker optimizations from messing | |
4850 | up the .org distance. This should be done after | |
4851 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4852 | about that function trashing the data we save here. */ | |
4853 | ||
4854 | for (seclist = &stdoutput->sections; | |
4855 | seclist && *seclist; | |
4856 | seclist = &(*seclist)->next) | |
4857 | { | |
4858 | segT sec = *seclist; | |
4859 | segment_info_type *seginfo; | |
4860 | fragS *fragP; | |
4861 | flagword flags; | |
4862 | flags = bfd_get_section_flags (stdoutput, sec); | |
4863 | if (flags & SEC_DEBUGGING) | |
4864 | continue; | |
4865 | if (!(flags & SEC_ALLOC)) | |
4866 | continue; | |
4867 | ||
4868 | seginfo = seg_info (sec); | |
4869 | if (seginfo && seginfo->frchainP) | |
4870 | { | |
4871 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4872 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4873 | fragP = fragP->fr_next) | |
4874 | { | |
4875 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4876 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4877 | if (fragP->fr_subtype == RELAX_ORG) | |
4878 | { | |
4879 | while (last_fragP != fragP->fr_next) | |
4880 | { | |
4881 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4882 | last_fragP = last_fragP->fr_next; | |
4883 | } | |
4884 | } | |
4885 | } | |
4886 | } | |
4887 | } | |
4888 | } | |
4889 | ||
4890 | ||
43cd72b9 | 4891 | static void |
7fa3d080 | 4892 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4893 | { |
4894 | segT *seclist; | |
4895 | ||
4896 | /* Walk over each fragment of all of the current segments. For each | |
4897 | unmarked fragment, mark it with the same info as the previous | |
4898 | fragment. */ | |
4899 | for (seclist = &stdoutput->sections; | |
4900 | seclist && *seclist; | |
4901 | seclist = &(*seclist)->next) | |
4902 | { | |
4903 | segT sec = *seclist; | |
4904 | segment_info_type *seginfo; | |
4905 | fragS *fragP; | |
4906 | flagword flags; | |
4907 | flags = bfd_get_section_flags (stdoutput, sec); | |
4908 | if (flags & SEC_DEBUGGING) | |
4909 | continue; | |
4910 | if (!(flags & SEC_ALLOC)) | |
4911 | continue; | |
4912 | ||
4913 | seginfo = seg_info (sec); | |
4914 | if (seginfo && seginfo->frchainP) | |
4915 | { | |
4916 | fragS *last_fragP = 0; | |
4917 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4918 | fragP = fragP->fr_next) | |
4919 | { | |
4920 | if (fragP->fr_fix != 0 | |
4921 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4922 | { | |
4923 | if (last_fragP == 0) | |
4924 | { | |
4925 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4926 | _("assembly state not set for first frag in section %s"), | |
4927 | sec->name); | |
4928 | } | |
4929 | else | |
4930 | { | |
4931 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4932 | fragP->tc_frag_data.is_no_density = | |
4933 | last_fragP->tc_frag_data.is_no_density; | |
4934 | fragP->tc_frag_data.is_no_transform = | |
4935 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4936 | fragP->tc_frag_data.use_longcalls = |
4937 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4938 | fragP->tc_frag_data.use_absolute_literals = |
4939 | last_fragP->tc_frag_data.use_absolute_literals; | |
4940 | } | |
4941 | } | |
4942 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4943 | last_fragP = fragP; | |
4944 | } | |
4945 | } | |
4946 | } | |
4947 | } | |
4948 | ||
4949 | ||
4950 | static void | |
7fa3d080 BW |
4951 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4952 | asection *sec, | |
4953 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4954 | { |
4955 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4956 | segment_info_type *seginfo = seg_info (sec); | |
4957 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4958 | |
43cd72b9 | 4959 | if (flags & SEC_CODE) |
c138bc38 | 4960 | { |
43cd72b9 BW |
4961 | xtensa_isa isa = xtensa_default_isa; |
4962 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4963 | while (frag != NULL) | |
4964 | { | |
4965 | if (frag->tc_frag_data.is_branch_target) | |
4966 | { | |
4967 | int op_size; | |
664df4e4 | 4968 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4969 | xtensa_format fmt; |
4970 | ||
d77b99c9 BW |
4971 | xtensa_insnbuf_from_chars |
4972 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4973 | fmt = xtensa_format_decode (isa, insnbuf); |
4974 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4975 | branch_align = 1 << branch_align_power (sec); |
4976 | frag_addr = frag->fr_address % branch_align; | |
4977 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4978 | as_warn_where (frag->fr_file, frag->fr_line, |
4979 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4980 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4981 | } |
4982 | frag = frag->fr_next; | |
4983 | } | |
4984 | xtensa_insnbuf_free (isa, insnbuf); | |
4985 | } | |
4986 | } | |
4987 | ||
4988 | ||
4989 | static void | |
7fa3d080 BW |
4990 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4991 | asection *sec, | |
4992 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4993 | { |
4994 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4995 | segment_info_type *seginfo = seg_info (sec); | |
4996 | fragS *frag = seginfo->frchainP->frch_root; | |
4997 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4998 | |
43cd72b9 | 4999 | if (flags & SEC_CODE) |
c138bc38 | 5000 | { |
43cd72b9 BW |
5001 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
5002 | while (frag != NULL) | |
5003 | { | |
5004 | if (frag->tc_frag_data.is_first_loop_insn) | |
5005 | { | |
5006 | int op_size; | |
d77b99c9 | 5007 | addressT frag_addr; |
43cd72b9 BW |
5008 | xtensa_format fmt; |
5009 | ||
d77b99c9 BW |
5010 | xtensa_insnbuf_from_chars |
5011 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5012 | fmt = xtensa_format_decode (isa, insnbuf); |
5013 | op_size = xtensa_format_length (isa, fmt); | |
5014 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
5015 | ||
d77b99c9 | 5016 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
5017 | as_warn_where (frag->fr_file, frag->fr_line, |
5018 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 5019 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5020 | } |
5021 | frag = frag->fr_next; | |
5022 | } | |
5023 | xtensa_insnbuf_free (isa, insnbuf); | |
5024 | } | |
5025 | } | |
5026 | ||
5027 | ||
30f725a1 BW |
5028 | static int |
5029 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5030 | { |
5031 | xtensa_isa isa = xtensa_default_isa; | |
5032 | static xtensa_insnbuf insnbuf = NULL; | |
5033 | static xtensa_insnbuf slotbuf = NULL; | |
5034 | xtensa_format fmt; | |
5035 | int slot; | |
5036 | bfd_boolean alt_reloc; | |
5037 | xtensa_opcode opcode; | |
5038 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5039 | ||
1b6e95c2 BW |
5040 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5041 | || alt_reloc) | |
43cd72b9 BW |
5042 | as_fatal (_("unexpected fix")); |
5043 | ||
5044 | if (!insnbuf) | |
5045 | { | |
5046 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5047 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5048 | } | |
5049 | ||
d77b99c9 | 5050 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5051 | fmt = xtensa_format_decode (isa, insnbuf); |
5052 | if (fmt == XTENSA_UNDEFINED) | |
5053 | as_fatal (_("undecodable fix")); | |
5054 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5055 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5056 | if (opcode == XTENSA_UNDEFINED) | |
5057 | as_fatal (_("undecodable fix")); | |
5058 | ||
5059 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5060 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5061 | of a CONST16 operand. */ |
43cd72b9 | 5062 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5063 | return 0; |
43cd72b9 BW |
5064 | |
5065 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5066 | get_relaxable_immed (opcode), val, | |
5067 | fixP->fx_file, fixP->fx_line); | |
5068 | ||
5069 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5070 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5071 | |
5072 | return 1; | |
43cd72b9 BW |
5073 | } |
5074 | ||
e0001a05 NC |
5075 | \f |
5076 | /* External Functions and Other GAS Hooks. */ | |
5077 | ||
5078 | const char * | |
7fa3d080 | 5079 | xtensa_target_format (void) |
e0001a05 NC |
5080 | { |
5081 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5082 | } | |
5083 | ||
5084 | ||
5085 | void | |
7fa3d080 | 5086 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5087 | { |
5088 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5089 | } | |
5090 | ||
5091 | ||
5092 | void | |
7fa3d080 | 5093 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5094 | { |
5095 | if (target_big_endian) | |
5096 | number_to_chars_bigendian (buf, val, n); | |
5097 | else | |
5098 | number_to_chars_littleendian (buf, val, n); | |
5099 | } | |
5100 | ||
5101 | ||
5102 | /* This function is called once, at assembler startup time. It should | |
5103 | set up all the tables, etc. that the MD part of the assembler will | |
5104 | need. */ | |
5105 | ||
5106 | void | |
7fa3d080 | 5107 | md_begin (void) |
e0001a05 NC |
5108 | { |
5109 | segT current_section = now_seg; | |
5110 | int current_subsec = now_subseg; | |
5111 | xtensa_isa isa; | |
62af60e2 | 5112 | int i; |
e0001a05 | 5113 | |
43cd72b9 | 5114 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5115 | isa = xtensa_default_isa; |
e0001a05 | 5116 | |
43cd72b9 BW |
5117 | linkrelax = 1; |
5118 | ||
74869ac7 | 5119 | /* Set up the literal sections. */ |
e0001a05 | 5120 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5121 | |
5122 | subseg_set (current_section, current_subsec); | |
5123 | ||
5124 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5125 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5126 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5127 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5128 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5129 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5130 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5131 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5132 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5133 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5134 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5135 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5136 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5137 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5138 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5139 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5140 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5141 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5142 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5143 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5144 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5145 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5146 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5147 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5148 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5149 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5150 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5151 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5152 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5153 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5154 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5155 | |
62af60e2 SA |
5156 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
5157 | { | |
5158 | int format_slots = xtensa_format_num_slots (isa, i); | |
5159 | if (format_slots > config_max_slots) | |
5160 | config_max_slots = format_slots; | |
5161 | } | |
5162 | ||
5163 | xg_init_vinsn (&cur_vinsn); | |
5164 | ||
77cba8a3 BW |
5165 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5166 | ||
43cd72b9 BW |
5167 | init_op_placement_info_table (); |
5168 | ||
5169 | /* Set up the assembly state. */ | |
5170 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5171 | xtensa_set_frag_assembly_state (frag_now); | |
5172 | } | |
5173 | ||
5174 | ||
5175 | /* TC_INIT_FIX_DATA hook */ | |
5176 | ||
5177 | void | |
7fa3d080 | 5178 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5179 | { |
5180 | x->tc_fix_data.slot = 0; | |
5181 | x->tc_fix_data.X_add_symbol = NULL; | |
5182 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5183 | } |
5184 | ||
5185 | ||
5186 | /* tc_frob_label hook */ | |
5187 | ||
5188 | void | |
7fa3d080 | 5189 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5190 | { |
3ea38ac2 BW |
5191 | float freq; |
5192 | ||
5193 | if (cur_vinsn.inside_bundle) | |
5194 | { | |
5195 | as_bad (_("labels are not valid inside bundles")); | |
5196 | return; | |
5197 | } | |
5198 | ||
5199 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5200 | |
43cd72b9 BW |
5201 | /* Since the label was already attached to a frag associated with the |
5202 | previous basic block, it now needs to be reset to the current frag. */ | |
5203 | symbol_set_frag (sym, frag_now); | |
5204 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5205 | ||
82e7541d BW |
5206 | if (generating_literals) |
5207 | xtensa_add_literal_sym (sym); | |
5208 | else | |
5209 | xtensa_add_insn_label (sym); | |
5210 | ||
7b1cc377 BW |
5211 | if (symbol_get_tc (sym)->is_loop_target) |
5212 | { | |
5213 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5214 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5215 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5216 | ||
5217 | xtensa_set_frag_assembly_state (frag_now); | |
5218 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5219 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5220 | ||
5221 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5222 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5223 | } |
e0001a05 NC |
5224 | |
5225 | /* No target aligning in the absolute section. */ | |
61846f28 | 5226 | if (now_seg != absolute_section |
61846f28 | 5227 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5228 | && !generating_literals) |
5229 | { | |
43cd72b9 BW |
5230 | xtensa_set_frag_assembly_state (frag_now); |
5231 | ||
b7afdeef SA |
5232 | if (do_align_targets ()) |
5233 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5234 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5235 | frag_now->fr_offset, NULL); | |
5236 | else | |
5237 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5238 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5239 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5240 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5241 | } |
5242 | ||
5243 | /* We need to mark the following properties even if we aren't aligning. */ | |
5244 | ||
5245 | /* If the label is already known to be a branch target, i.e., a | |
5246 | forward branch, mark the frag accordingly. Backward branches | |
5247 | are handled by xg_add_branch_and_loop_targets. */ | |
5248 | if (symbol_get_tc (sym)->is_branch_target) | |
5249 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5250 | ||
5251 | /* Loops only go forward, so they can be identified here. */ | |
5252 | if (symbol_get_tc (sym)->is_loop_target) | |
5253 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5254 | |
5255 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5256 | } |
5257 | ||
5258 | ||
5259 | /* tc_unrecognized_line hook */ | |
5260 | ||
5261 | int | |
7fa3d080 | 5262 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5263 | { |
5264 | switch (ch) | |
5265 | { | |
5266 | case '{' : | |
5267 | if (cur_vinsn.inside_bundle == 0) | |
5268 | { | |
5269 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5270 | when using --gstabs. Temporarily disable debug info. */ | |
5271 | generate_lineno_debug (); | |
5272 | if (debug_type == DEBUG_STABS) | |
5273 | { | |
5274 | xt_saved_debug_type = debug_type; | |
5275 | debug_type = DEBUG_NONE; | |
5276 | } | |
82e7541d | 5277 | |
43cd72b9 BW |
5278 | cur_vinsn.inside_bundle = 1; |
5279 | } | |
5280 | else | |
5281 | { | |
5282 | as_bad (_("extra opening brace")); | |
5283 | return 0; | |
5284 | } | |
5285 | break; | |
82e7541d | 5286 | |
43cd72b9 BW |
5287 | case '}' : |
5288 | if (cur_vinsn.inside_bundle) | |
5289 | finish_vinsn (&cur_vinsn); | |
5290 | else | |
5291 | { | |
5292 | as_bad (_("extra closing brace")); | |
5293 | return 0; | |
5294 | } | |
5295 | break; | |
5296 | default: | |
5297 | as_bad (_("syntax error")); | |
5298 | return 0; | |
e0001a05 | 5299 | } |
43cd72b9 | 5300 | return 1; |
e0001a05 NC |
5301 | } |
5302 | ||
5303 | ||
5304 | /* md_flush_pending_output hook */ | |
5305 | ||
5306 | void | |
7fa3d080 | 5307 | xtensa_flush_pending_output (void) |
e0001a05 | 5308 | { |
a3582eee BW |
5309 | /* This line fixes a bug where automatically generated gstabs info |
5310 | separates a function label from its entry instruction, ending up | |
5311 | with the literal position between the function label and the entry | |
5312 | instruction and crashing code. It only happens with --gstabs and | |
5313 | --text-section-literals, and when several other obscure relaxation | |
5314 | conditions are met. */ | |
5315 | if (outputting_stabs_line_debug) | |
5316 | return; | |
5317 | ||
43cd72b9 BW |
5318 | if (cur_vinsn.inside_bundle) |
5319 | as_bad (_("missing closing brace")); | |
5320 | ||
e0001a05 NC |
5321 | /* If there is a non-zero instruction fragment, close it. */ |
5322 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5323 | { | |
5324 | frag_wane (frag_now); | |
5325 | frag_new (0); | |
43cd72b9 | 5326 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5327 | } |
5328 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5329 | |
5330 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5331 | } |
5332 | ||
5333 | ||
43cd72b9 BW |
5334 | /* We had an error while parsing an instruction. The string might look |
5335 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5336 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5337 | and the num_slots field will grow past the end of the array of slots, | |
5338 | and bad things happen. */ | |
5339 | ||
5340 | static void | |
7fa3d080 | 5341 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5342 | { |
5343 | if (cur_vinsn.inside_bundle) | |
5344 | { | |
5345 | if (*input_line_pointer == '}' | |
5346 | || *(input_line_pointer - 1) == '}' | |
5347 | || *(input_line_pointer - 2) == '}') | |
5348 | xg_clear_vinsn (&cur_vinsn); | |
5349 | } | |
5350 | } | |
5351 | ||
5352 | ||
e0001a05 | 5353 | void |
7fa3d080 | 5354 | md_assemble (char *str) |
e0001a05 NC |
5355 | { |
5356 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5357 | char *opname; |
e0001a05 NC |
5358 | unsigned opnamelen; |
5359 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5360 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5361 | int num_args; |
e0001a05 | 5362 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5363 | |
e0001a05 NC |
5364 | tinsn_init (&orig_insn); |
5365 | ||
5366 | /* Split off the opcode. */ | |
5367 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5368 | opname = xmalloc (opnamelen + 1); | |
5369 | memcpy (opname, str, opnamelen); | |
5370 | opname[opnamelen] = '\0'; | |
5371 | ||
5372 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5373 | if (num_args == -1) | |
5374 | { | |
5375 | as_bad (_("syntax error")); | |
5376 | return; | |
5377 | } | |
5378 | ||
5379 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5380 | return; | |
5381 | ||
5382 | /* Check for an underbar prefix. */ | |
5383 | if (*opname == '_') | |
5384 | { | |
5385 | has_underbar = TRUE; | |
5386 | opname += 1; | |
5387 | } | |
5388 | ||
5389 | orig_insn.insn_type = ITYPE_INSN; | |
5390 | orig_insn.ntok = 0; | |
43cd72b9 | 5391 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5392 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 BW |
5393 | |
5394 | /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its | |
5395 | extra argument and set the opcode to "CALLXn". */ | |
5396 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5397 | && strncasecmp (opname, "callx", 5) == 0) | |
5398 | { | |
5399 | unsigned long window_size; | |
5400 | char *suffix; | |
5401 | ||
5402 | window_size = strtoul (opname + 5, &suffix, 10); | |
5403 | if (suffix != opname + 5 | |
5404 | && (window_size == 0 | |
5405 | || window_size == 4 | |
5406 | || window_size == 8 | |
5407 | || window_size == 12) | |
5408 | && strcasecmp (suffix, ".tls") == 0) | |
5409 | { | |
5410 | switch (window_size) | |
5411 | { | |
5412 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5413 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5414 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5415 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5416 | } | |
5417 | ||
5418 | if (num_args != 2) | |
5419 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5420 | else | |
5421 | { | |
5422 | bfd_reloc_code_real_type reloc; | |
5423 | char *old_input_line_pointer; | |
19e8f41a | 5424 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5425 | segT t; |
5426 | ||
5427 | old_input_line_pointer = input_line_pointer; | |
5428 | input_line_pointer = arg_strings[num_args - 1]; | |
5429 | ||
5430 | t = expression (tok); | |
5431 | if (tok->X_op == O_symbol | |
5432 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5433 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5434 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5435 | else | |
5436 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5437 | ||
5438 | input_line_pointer = old_input_line_pointer; | |
5439 | num_args -= 1; | |
5440 | } | |
5441 | } | |
5442 | } | |
5443 | ||
19e8f41a BW |
5444 | /* Special case: Check for "j.l" psuedo op. */ |
5445 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5446 | && strncasecmp (opname, "j.l", 3) == 0) | |
5447 | { | |
5448 | if (num_args != 2) | |
5449 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5450 | else | |
5451 | { | |
5452 | char *old_input_line_pointer; | |
5453 | expressionS *tok = &orig_insn.extra_arg; | |
5454 | ||
5455 | old_input_line_pointer = input_line_pointer; | |
5456 | input_line_pointer = arg_strings[num_args - 1]; | |
5457 | ||
5458 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5459 | input_line_pointer = old_input_line_pointer; | |
5460 | ||
5461 | num_args -= 1; | |
5462 | orig_insn.opcode = xtensa_j_opcode; | |
5463 | } | |
5464 | } | |
5465 | ||
e0001a05 NC |
5466 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5467 | { | |
43cd72b9 BW |
5468 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5469 | if (fmt == XTENSA_UNDEFINED) | |
5470 | { | |
5471 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5472 | error_reset_cur_vinsn (); | |
5473 | return; | |
5474 | } | |
5475 | if (!cur_vinsn.inside_bundle) | |
5476 | { | |
5477 | as_bad (_("format names only valid inside bundles")); | |
5478 | error_reset_cur_vinsn (); | |
5479 | return; | |
5480 | } | |
5481 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5482 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5483 | opname); | |
5484 | cur_vinsn.format = fmt; | |
5485 | free (has_underbar ? opname - 1 : opname); | |
5486 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5487 | return; |
5488 | } | |
5489 | ||
e0001a05 NC |
5490 | /* Parse the arguments. */ |
5491 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5492 | { | |
5493 | as_bad (_("syntax error")); | |
43cd72b9 | 5494 | error_reset_cur_vinsn (); |
e0001a05 NC |
5495 | return; |
5496 | } | |
5497 | ||
5498 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5499 | free (has_underbar ? opname - 1 : opname); | |
5500 | opname = 0; | |
5501 | while (num_args-- > 0) | |
5502 | free (arg_strings[num_args]); | |
5503 | ||
43cd72b9 BW |
5504 | /* Get expressions for invisible operands. */ |
5505 | if (get_invisible_operands (&orig_insn)) | |
5506 | { | |
5507 | error_reset_cur_vinsn (); | |
5508 | return; | |
5509 | } | |
5510 | ||
e0001a05 NC |
5511 | /* Check for the right number and type of arguments. */ |
5512 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5513 | { |
43cd72b9 BW |
5514 | error_reset_cur_vinsn (); |
5515 | return; | |
e0001a05 NC |
5516 | } |
5517 | ||
b224e962 BW |
5518 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5519 | spread across multiple input lines and individual instructions may be | |
5520 | moved around in some cases. */ | |
5521 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5522 | dwarf2_where (&orig_insn.debug_line); | |
5523 | dwarf2_consume_line_info (); | |
c138bc38 | 5524 | |
43cd72b9 BW |
5525 | xg_add_branch_and_loop_targets (&orig_insn); |
5526 | ||
431ad2d0 BW |
5527 | /* Check that immediate value for ENTRY is >= 16. */ |
5528 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5529 | { |
431ad2d0 BW |
5530 | expressionS *exp = &orig_insn.tok[2]; |
5531 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5532 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5533 | } |
5534 | ||
e0001a05 | 5535 | /* Finish it off: |
43cd72b9 BW |
5536 | assemble_tokens (opcode, tok, ntok); |
5537 | expand the tokens from the orig_insn into the | |
5538 | stack of instructions that will not expand | |
e0001a05 | 5539 | unless required at relaxation time. */ |
e0001a05 | 5540 | |
43cd72b9 BW |
5541 | if (!cur_vinsn.inside_bundle) |
5542 | emit_single_op (&orig_insn); | |
5543 | else /* We are inside a bundle. */ | |
e0001a05 | 5544 | { |
43cd72b9 BW |
5545 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5546 | cur_vinsn.num_slots++; | |
5547 | if (*input_line_pointer == '}' | |
5548 | || *(input_line_pointer - 1) == '}' | |
5549 | || *(input_line_pointer - 2) == '}') | |
5550 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5551 | } |
5552 | ||
43cd72b9 BW |
5553 | /* We've just emitted a new instruction so clear the list of labels. */ |
5554 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5555 | } |
5556 | ||
5557 | ||
43cd72b9 | 5558 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5559 | |
43cd72b9 BW |
5560 | /* For a .align directive, we mark the previous block with the alignment |
5561 | information. This will be placed in the object file in the | |
5562 | property section corresponding to this section. */ | |
e0001a05 | 5563 | |
43cd72b9 | 5564 | void |
7fa3d080 | 5565 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5566 | { |
5567 | if (linkrelax | |
b08b5071 | 5568 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5569 | && (fragP->fr_type == rs_align |
5570 | || fragP->fr_type == rs_align_code) | |
5571 | && fragP->fr_address + fragP->fr_fix > 0 | |
5572 | && fragP->fr_offset > 0 | |
5573 | && now_seg != bss_section) | |
e0001a05 | 5574 | { |
43cd72b9 BW |
5575 | fragP->tc_frag_data.is_align = TRUE; |
5576 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5577 | } |
5578 | ||
43cd72b9 | 5579 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5580 | { |
43cd72b9 BW |
5581 | int count; |
5582 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5583 | if (count != 0) | |
c138bc38 | 5584 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5585 | _("unaligned entry instruction")); |
e0001a05 | 5586 | } |
99ded152 BW |
5587 | |
5588 | if (linkrelax && fragP->fr_type == rs_org) | |
5589 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5590 | } |
43cd72b9 | 5591 | |
e0001a05 NC |
5592 | |
5593 | /* TC_FRAG_INIT hook */ | |
5594 | ||
5595 | void | |
7fa3d080 | 5596 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5597 | { |
43cd72b9 | 5598 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5599 | } |
5600 | ||
5601 | ||
5602 | symbolS * | |
7fa3d080 | 5603 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5604 | { |
5605 | return NULL; | |
5606 | } | |
5607 | ||
5608 | ||
5609 | /* Round up a section size to the appropriate boundary. */ | |
5610 | ||
5611 | valueT | |
7fa3d080 | 5612 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5613 | { |
5614 | return size; /* Byte alignment is fine. */ | |
5615 | } | |
5616 | ||
5617 | ||
5618 | long | |
7fa3d080 | 5619 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5620 | { |
5621 | char *insn_p; | |
5622 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5623 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5624 | int opnum; |
43cd72b9 | 5625 | uint32 opnd_value; |
e0001a05 | 5626 | xtensa_opcode opcode; |
43cd72b9 BW |
5627 | xtensa_format fmt; |
5628 | int slot; | |
e0001a05 NC |
5629 | xtensa_isa isa = xtensa_default_isa; |
5630 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5631 | bfd_boolean alt_reloc; |
e0001a05 | 5632 | |
e0001a05 | 5633 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5634 | return 0; |
e0001a05 | 5635 | |
1bbb5f21 BW |
5636 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5637 | return addr; | |
5638 | ||
e0001a05 | 5639 | if (!insnbuf) |
43cd72b9 BW |
5640 | { |
5641 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5642 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5643 | } | |
e0001a05 NC |
5644 | |
5645 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5646 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5647 | fmt = xtensa_format_decode (isa, insnbuf); |
5648 | ||
5649 | if (fmt == XTENSA_UNDEFINED) | |
5650 | as_fatal (_("bad instruction format")); | |
5651 | ||
5652 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5653 | as_fatal (_("invalid relocation")); | |
5654 | ||
5655 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5656 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5657 | ||
30f725a1 BW |
5658 | /* Check for "alternate" relocations (operand not specified). None |
5659 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5660 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5661 | { | |
5662 | if (opcode != xtensa_l32r_opcode | |
5663 | && opcode != xtensa_const16_opcode) | |
5664 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5665 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5666 | return 0; |
e0001a05 NC |
5667 | } |
5668 | ||
43cd72b9 BW |
5669 | opnum = get_relaxable_immed (opcode); |
5670 | opnd_value = 0; | |
5671 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5672 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5673 | { |
5674 | as_bad_where (fixP->fx_file, | |
5675 | fixP->fx_line, | |
5676 | _("invalid relocation for operand %d of '%s'"), | |
5677 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5678 | return 0; |
e0001a05 | 5679 | } |
43cd72b9 BW |
5680 | return 0 - opnd_value; |
5681 | } | |
5682 | ||
5683 | ||
5684 | /* TC_FORCE_RELOCATION hook */ | |
5685 | ||
5686 | int | |
7fa3d080 | 5687 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5688 | { |
5689 | switch (fix->fx_r_type) | |
30f725a1 BW |
5690 | { |
5691 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5692 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5693 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5694 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5695 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5696 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5697 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5698 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5699 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5700 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5701 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5702 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5703 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5704 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5705 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5706 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5707 | return 1; |
5708 | default: | |
5709 | break; | |
e0001a05 NC |
5710 | } |
5711 | ||
43cd72b9 BW |
5712 | if (linkrelax && fix->fx_addsy |
5713 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5714 | return 1; | |
5715 | ||
5716 | return generic_force_reloc (fix); | |
5717 | } | |
5718 | ||
5719 | ||
30f725a1 BW |
5720 | /* TC_VALIDATE_FIX_SUB hook */ |
5721 | ||
5722 | int | |
5723 | xtensa_validate_fix_sub (fixS *fix) | |
5724 | { | |
5725 | segT add_symbol_segment, sub_symbol_segment; | |
5726 | ||
5727 | /* The difference of two symbols should be resolved by the assembler when | |
5728 | linkrelax is not set. If the linker may relax the section containing | |
5729 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5730 | the linker knows to adjust the difference value. */ | |
5731 | if (!linkrelax || fix->fx_addsy == NULL) | |
5732 | return 0; | |
5733 | ||
5734 | /* Make sure both symbols are in the same segment, and that segment is | |
5735 | "normal" and relaxable. If the segment is not "normal", then the | |
5736 | fix is not valid. If the segment is not "relaxable", then the fix | |
5737 | should have been handled earlier. */ | |
5738 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5739 | if (! SEG_NORMAL (add_symbol_segment) || | |
5740 | ! relaxable_section (add_symbol_segment)) | |
5741 | return 0; | |
5742 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5743 | return (sub_symbol_segment == add_symbol_segment); | |
5744 | } | |
5745 | ||
5746 | ||
43cd72b9 BW |
5747 | /* NO_PSEUDO_DOT hook */ |
5748 | ||
5749 | /* This function has nothing to do with pseudo dots, but this is the | |
5750 | nearest macro to where the check needs to take place. FIXME: This | |
5751 | seems wrong. */ | |
5752 | ||
5753 | bfd_boolean | |
7fa3d080 | 5754 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5755 | { |
5756 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5757 | as_bad (_("directives are not valid inside bundles")); | |
5758 | ||
5759 | /* This function must always return FALSE because it is called via a | |
5760 | macro that has nothing to do with bundling. */ | |
5761 | return FALSE; | |
e0001a05 NC |
5762 | } |
5763 | ||
5764 | ||
43cd72b9 | 5765 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5766 | |
5767 | void | |
7fa3d080 | 5768 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5769 | { |
43cd72b9 BW |
5770 | /* Set up the assembly state. */ |
5771 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5772 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5773 | } |
5774 | ||
5775 | ||
5776 | /* tc_fix_adjustable hook */ | |
5777 | ||
5778 | bfd_boolean | |
7fa3d080 | 5779 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 NC |
5780 | { |
5781 | /* We need the symbol name for the VTABLE entries. */ | |
5782 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5783 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5784 | return 0; | |
5785 | ||
5786 | return 1; | |
5787 | } | |
5788 | ||
5789 | ||
6a7eedfe BW |
5790 | /* tc_symbol_new_hook */ |
5791 | ||
5792 | symbolS *expr_symbols = NULL; | |
5793 | ||
5794 | void | |
5795 | xtensa_symbol_new_hook (symbolS *sym) | |
5796 | { | |
fb227da0 | 5797 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5798 | { |
5799 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5800 | expr_symbols = sym; | |
5801 | } | |
5802 | } | |
5803 | ||
5804 | ||
e0001a05 | 5805 | void |
55cf6793 | 5806 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5807 | { |
30f725a1 | 5808 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5809 | valueT val = 0; |
30f725a1 | 5810 | |
e7da6241 BW |
5811 | /* Subtracted symbols are only allowed for a few relocation types, and |
5812 | unless linkrelax is enabled, they should not make it to this point. */ | |
5813 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5814 | || fixP->fx_r_type == BFD_RELOC_16 | |
5815 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5816 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5817 | ||
30f725a1 | 5818 | switch (fixP->fx_r_type) |
e0001a05 | 5819 | { |
1bbb5f21 | 5820 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5821 | case BFD_RELOC_32: |
5822 | case BFD_RELOC_16: | |
5823 | case BFD_RELOC_8: | |
e7da6241 | 5824 | if (fixP->fx_subsy) |
30f725a1 BW |
5825 | { |
5826 | switch (fixP->fx_r_type) | |
5827 | { | |
5828 | case BFD_RELOC_8: | |
5829 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5830 | break; | |
5831 | case BFD_RELOC_16: | |
5832 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5833 | break; | |
5834 | case BFD_RELOC_32: | |
5835 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5836 | break; | |
5837 | default: | |
5838 | break; | |
5839 | } | |
e0001a05 | 5840 | |
30f725a1 BW |
5841 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
5842 | - S_GET_VALUE (fixP->fx_subsy)); | |
5843 | ||
5844 | /* The difference value gets written out, and the DIFF reloc | |
5845 | identifies the address of the subtracted symbol (i.e., the one | |
5846 | with the lowest address). */ | |
5847 | *valP = val; | |
5848 | fixP->fx_offset -= val; | |
5849 | fixP->fx_subsy = NULL; | |
5850 | } | |
5851 | else if (! fixP->fx_addsy) | |
e0001a05 | 5852 | { |
30f725a1 | 5853 | val = *valP; |
e0001a05 | 5854 | fixP->fx_done = 1; |
30f725a1 | 5855 | } |
d47d412e BW |
5856 | /* fall through */ |
5857 | ||
5858 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5859 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5860 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5861 | break; | |
e0001a05 | 5862 | |
28dbbc02 BW |
5863 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
5864 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
5865 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
5866 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
5867 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
5868 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
5869 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5870 | break; | |
5871 | ||
30f725a1 BW |
5872 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5873 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5874 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5875 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5876 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5877 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5878 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5879 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5880 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5881 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5882 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5883 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5884 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5885 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5886 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5887 | if (linkrelax) | |
5888 | { | |
5889 | /* Write the tentative value of a PC-relative relocation to a | |
5890 | local symbol into the instruction. The value will be ignored | |
5891 | by the linker, and it makes the object file disassembly | |
5892 | readable when all branch targets are encoded in relocations. */ | |
5893 | ||
9c2799c2 | 5894 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 5895 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5896 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5897 | { | |
5898 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5899 | - md_pcrel_from (fixP)); | |
5900 | (void) xg_apply_fix_value (fixP, val); | |
5901 | } | |
5902 | } | |
5903 | else if (! fixP->fx_addsy) | |
5904 | { | |
5905 | val = *valP; | |
5906 | if (xg_apply_fix_value (fixP, val)) | |
5907 | fixP->fx_done = 1; | |
5908 | } | |
5909 | break; | |
e0001a05 | 5910 | |
30f725a1 | 5911 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
5912 | case BFD_RELOC_XTENSA_TLS_FUNC: |
5913 | case BFD_RELOC_XTENSA_TLS_ARG: | |
5914 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
5915 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5916 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5917 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5918 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5919 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5920 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5921 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5922 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5923 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5924 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5925 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5926 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5927 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5928 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5929 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5930 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5931 | break; | |
e0001a05 | 5932 | |
30f725a1 BW |
5933 | case BFD_RELOC_VTABLE_INHERIT: |
5934 | case BFD_RELOC_VTABLE_ENTRY: | |
5935 | fixP->fx_done = 0; | |
5936 | break; | |
e0001a05 | 5937 | |
30f725a1 BW |
5938 | default: |
5939 | as_bad (_("unhandled local relocation fix %s"), | |
5940 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5941 | } |
5942 | } | |
5943 | ||
5944 | ||
5945 | char * | |
7fa3d080 | 5946 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 5947 | { |
499ac353 | 5948 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
5949 | } |
5950 | ||
5951 | ||
5952 | int | |
7fa3d080 | 5953 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5954 | { |
34e41783 | 5955 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5956 | } |
5957 | ||
5958 | ||
5959 | /* Translate internal representation of relocation info to BFD target | |
5960 | format. */ | |
5961 | ||
5962 | arelent * | |
30f725a1 | 5963 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5964 | { |
5965 | arelent *reloc; | |
5966 | ||
5967 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5968 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5969 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5970 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5971 | ||
5972 | /* Make sure none of our internal relocations make it this far. | |
5973 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 5974 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 5975 | |
30f725a1 | 5976 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5977 | |
e0001a05 NC |
5978 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5979 | if (reloc->howto == NULL) | |
5980 | { | |
5981 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5982 | _("cannot represent `%s' relocation in object file"), | |
5983 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5984 | free (reloc->sym_ptr_ptr); |
5985 | free (reloc); | |
e0001a05 NC |
5986 | return NULL; |
5987 | } | |
5988 | ||
5989 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 5990 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 5991 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 5992 | |
e0001a05 NC |
5993 | return reloc; |
5994 | } | |
5995 | ||
7fa3d080 BW |
5996 | \f |
5997 | /* Checks for resource conflicts between instructions. */ | |
5998 | ||
c138bc38 BW |
5999 | /* The func unit stuff could be implemented as bit-vectors rather |
6000 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6001 | slow, we will switch it. */ |
6002 | ||
c138bc38 | 6003 | resource_table * |
7fa3d080 BW |
6004 | new_resource_table (void *data, |
6005 | int cycles, | |
6006 | int nu, | |
6007 | unit_num_copies_func uncf, | |
6008 | opcode_num_units_func onuf, | |
6009 | opcode_funcUnit_use_unit_func ouuf, | |
6010 | opcode_funcUnit_use_stage_func ousf) | |
6011 | { | |
6012 | int i; | |
6013 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
6014 | rt->data = data; | |
6015 | rt->cycles = cycles; | |
6016 | rt->allocated_cycles = cycles; | |
6017 | rt->num_units = nu; | |
6018 | rt->unit_num_copies = uncf; | |
6019 | rt->opcode_num_units = onuf; | |
6020 | rt->opcode_unit_use = ouuf; | |
6021 | rt->opcode_unit_stage = ousf; | |
6022 | ||
0bf60745 | 6023 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 6024 | for (i = 0; i < cycles; i++) |
0bf60745 | 6025 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
6026 | |
6027 | return rt; | |
6028 | } | |
6029 | ||
6030 | ||
c138bc38 | 6031 | void |
7fa3d080 BW |
6032 | clear_resource_table (resource_table *rt) |
6033 | { | |
6034 | int i, j; | |
6035 | for (i = 0; i < rt->allocated_cycles; i++) | |
6036 | for (j = 0; j < rt->num_units; j++) | |
6037 | rt->units[i][j] = 0; | |
6038 | } | |
6039 | ||
6040 | ||
6041 | /* We never shrink it, just fake it into thinking so. */ | |
6042 | ||
c138bc38 | 6043 | void |
7fa3d080 BW |
6044 | resize_resource_table (resource_table *rt, int cycles) |
6045 | { | |
6046 | int i, old_cycles; | |
6047 | ||
6048 | rt->cycles = cycles; | |
6049 | if (cycles <= rt->allocated_cycles) | |
6050 | return; | |
6051 | ||
6052 | old_cycles = rt->allocated_cycles; | |
6053 | rt->allocated_cycles = cycles; | |
6054 | ||
0bf60745 BW |
6055 | rt->units = xrealloc (rt->units, |
6056 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 6057 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
6058 | rt->units[i] = xrealloc (rt->units[i], |
6059 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 6060 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 6061 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
6062 | } |
6063 | ||
6064 | ||
c138bc38 | 6065 | bfd_boolean |
7fa3d080 BW |
6066 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6067 | { | |
6068 | int i; | |
6069 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6070 | ||
c138bc38 | 6071 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6072 | { |
6073 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6074 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6075 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6076 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6077 | if (copies_in_use >= copies) | |
6078 | return FALSE; | |
6079 | } | |
6080 | return TRUE; | |
6081 | } | |
7fa3d080 | 6082 | |
c138bc38 BW |
6083 | |
6084 | void | |
7fa3d080 BW |
6085 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6086 | { | |
6087 | int i; | |
6088 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6089 | ||
c138bc38 | 6090 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6091 | { |
6092 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6093 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6094 | /* Note that this allows resources to be oversubscribed. That's |
6095 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6096 | resources_available reports when a resource is over-subscribed, |
6097 | so it's easy to tell. */ | |
6098 | rt->units[stage + cycle][unit]++; | |
6099 | } | |
6100 | } | |
6101 | ||
6102 | ||
c138bc38 | 6103 | void |
7fa3d080 BW |
6104 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6105 | { | |
6106 | int i; | |
6107 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6108 | ||
c138bc38 | 6109 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6110 | { |
6111 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6112 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6113 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6114 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6115 | } |
6116 | } | |
c138bc38 | 6117 | |
7fa3d080 BW |
6118 | |
6119 | /* Wrapper functions make parameterized resource reservation | |
6120 | more convenient. */ | |
6121 | ||
c138bc38 | 6122 | int |
7fa3d080 BW |
6123 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6124 | { | |
6125 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6126 | return use->unit; |
7fa3d080 BW |
6127 | } |
6128 | ||
6129 | ||
c138bc38 | 6130 | int |
7fa3d080 BW |
6131 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6132 | { | |
6133 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6134 | return use->stage; | |
6135 | } | |
6136 | ||
6137 | ||
6138 | /* Note that this function does not check issue constraints, but | |
6139 | solely whether the hardware is available to execute the given | |
c138bc38 | 6140 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6141 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6142 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6143 | |
6144 | static bfd_boolean | |
6145 | resources_conflict (vliw_insn *vinsn) | |
6146 | { | |
6147 | int i; | |
6148 | static resource_table *rt = NULL; | |
6149 | ||
6150 | /* This is the most common case by far. Optimize it. */ | |
6151 | if (vinsn->num_slots == 1) | |
6152 | return FALSE; | |
43cd72b9 | 6153 | |
c138bc38 | 6154 | if (rt == NULL) |
7fa3d080 BW |
6155 | { |
6156 | xtensa_isa isa = xtensa_default_isa; | |
6157 | rt = new_resource_table | |
77cba8a3 | 6158 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6159 | xtensa_isa_num_funcUnits (isa), |
6160 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6161 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6162 | opcode_funcUnit_use_unit, | |
6163 | opcode_funcUnit_use_stage); | |
6164 | } | |
43cd72b9 | 6165 | |
7fa3d080 | 6166 | clear_resource_table (rt); |
43cd72b9 | 6167 | |
7fa3d080 BW |
6168 | for (i = 0; i < vinsn->num_slots; i++) |
6169 | { | |
6170 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6171 | return TRUE; | |
6172 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6173 | } | |
e0001a05 | 6174 | |
7fa3d080 BW |
6175 | return FALSE; |
6176 | } | |
e0001a05 | 6177 | |
7fa3d080 BW |
6178 | \f |
6179 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6180 | |
7fa3d080 BW |
6181 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6182 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6183 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6184 | |
6185 | ||
43cd72b9 BW |
6186 | /* We have reached the end of a bundle; emit into the frag. */ |
6187 | ||
e0001a05 | 6188 | static void |
7fa3d080 | 6189 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6190 | { |
43cd72b9 BW |
6191 | IStack slotstack; |
6192 | int i; | |
6193 | char *file_name; | |
d77b99c9 | 6194 | unsigned line; |
e0001a05 | 6195 | |
43cd72b9 | 6196 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6197 | { |
6198 | xg_clear_vinsn (vinsn); | |
6199 | return; | |
6200 | } | |
43cd72b9 BW |
6201 | |
6202 | /* First, find a format that works. */ | |
6203 | if (vinsn->format == XTENSA_UNDEFINED) | |
6204 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6205 | ||
19fc3723 SA |
6206 | if (xtensa_format_num_slots (xtensa_default_isa, vinsn->format) > 1 |
6207 | && produce_flix == FLIX_NONE) | |
6208 | { | |
6209 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6210 | xg_clear_vinsn (vinsn); | |
6211 | return; | |
6212 | } | |
6213 | ||
43cd72b9 BW |
6214 | if (vinsn->format == XTENSA_UNDEFINED) |
6215 | { | |
6216 | as_where (&file_name, &line); | |
6217 | as_bad_where (file_name, line, | |
6218 | _("couldn't find a valid instruction format")); | |
6219 | fprintf (stderr, _(" ops were: ")); | |
6220 | for (i = 0; i < vinsn->num_slots; i++) | |
6221 | fprintf (stderr, _(" %s;"), | |
6222 | xtensa_opcode_name (xtensa_default_isa, | |
6223 | vinsn->slots[i].opcode)); | |
6224 | fprintf (stderr, _("\n")); | |
6225 | xg_clear_vinsn (vinsn); | |
6226 | return; | |
6227 | } | |
6228 | ||
6229 | if (vinsn->num_slots | |
6230 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6231 | { |
43cd72b9 BW |
6232 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6233 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6234 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6235 | vinsn->num_slots); | |
6236 | xg_clear_vinsn (vinsn); | |
6237 | return; | |
6238 | } | |
e0001a05 | 6239 | |
c138bc38 | 6240 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6241 | { |
6242 | as_where (&file_name, &line); | |
6243 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6244 | fprintf (stderr, " ops were: "); | |
6245 | for (i = 0; i < vinsn->num_slots; i++) | |
6246 | fprintf (stderr, " %s;", | |
6247 | xtensa_opcode_name (xtensa_default_isa, | |
6248 | vinsn->slots[i].opcode)); | |
6249 | fprintf (stderr, "\n"); | |
6250 | xg_clear_vinsn (vinsn); | |
6251 | return; | |
6252 | } | |
6253 | ||
6254 | for (i = 0; i < vinsn->num_slots; i++) | |
6255 | { | |
6256 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6257 | { |
43cd72b9 BW |
6258 | symbolS *lit_sym = NULL; |
6259 | int j; | |
6260 | bfd_boolean e = FALSE; | |
6261 | bfd_boolean saved_density = density_supported; | |
6262 | ||
6263 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6264 | if (vinsn->num_slots > 1) | |
6265 | density_supported = FALSE; | |
6266 | ||
6267 | istack_init (&slotstack); | |
6268 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6269 | { |
43cd72b9 BW |
6270 | vinsn->slots[i].opcode = |
6271 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6272 | vinsn->format, i); | |
6273 | vinsn->slots[i].ntok = 0; | |
6274 | } | |
e0001a05 | 6275 | |
43cd72b9 BW |
6276 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6277 | { | |
6278 | e = TRUE; | |
6279 | continue; | |
e0001a05 | 6280 | } |
e0001a05 | 6281 | |
43cd72b9 | 6282 | density_supported = saved_density; |
e0001a05 | 6283 | |
43cd72b9 BW |
6284 | if (e) |
6285 | { | |
6286 | xg_clear_vinsn (vinsn); | |
6287 | return; | |
6288 | } | |
e0001a05 | 6289 | |
0fa77c95 | 6290 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6291 | { |
6292 | TInsn *insn = &slotstack.insn[j]; | |
6293 | if (insn->insn_type == ITYPE_LITERAL) | |
6294 | { | |
9c2799c2 | 6295 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6296 | lit_sym = xg_assemble_literal (insn); |
6297 | } | |
6298 | else | |
6299 | { | |
9c2799c2 | 6300 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6301 | if (lit_sym) |
6302 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6303 | if (j != slotstack.ninsn - 1) |
6304 | emit_single_op (insn); | |
43cd72b9 BW |
6305 | } |
6306 | } | |
6307 | ||
6308 | if (vinsn->num_slots > 1) | |
6309 | { | |
6310 | if (opcode_fits_format_slot | |
6311 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6312 | vinsn->format, i)) | |
6313 | { | |
6314 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6315 | } | |
6316 | else | |
6317 | { | |
b2d179be | 6318 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6319 | if (vinsn->format == XTENSA_UNDEFINED) |
6320 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6321 | else | |
c138bc38 | 6322 | vinsn->slots[i].opcode |
43cd72b9 BW |
6323 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6324 | vinsn->format, i); | |
6325 | ||
6326 | vinsn->slots[i].ntok = 0; | |
6327 | } | |
6328 | } | |
6329 | else | |
6330 | { | |
6331 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6332 | vinsn->format = XTENSA_UNDEFINED; | |
6333 | } | |
6334 | } | |
6335 | } | |
6336 | ||
6337 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6338 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6339 | { |
6340 | as_where (&file_name, &line); | |
6341 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6342 | fprintf (stderr, " ops were: "); | |
6343 | for (i = 0; i < vinsn->num_slots; i++) | |
6344 | fprintf (stderr, " %s;", | |
6345 | xtensa_opcode_name (xtensa_default_isa, | |
6346 | vinsn->slots[i].opcode)); | |
6347 | fprintf (stderr, "\n"); | |
6348 | xg_clear_vinsn (vinsn); | |
6349 | return; | |
6350 | } | |
6351 | ||
6352 | /* First, find a format that works. */ | |
6353 | if (vinsn->format == XTENSA_UNDEFINED) | |
6354 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6355 | ||
6356 | xg_assemble_vliw_tokens (vinsn); | |
6357 | ||
6358 | xg_clear_vinsn (vinsn); | |
6359 | } | |
6360 | ||
6361 | ||
6362 | /* Given an vliw instruction, what conflicts are there in register | |
6363 | usage and in writes to states and queues? | |
6364 | ||
6365 | This function does two things: | |
6366 | 1. Reports an error when a vinsn contains illegal combinations | |
6367 | of writes to registers states or queues. | |
6368 | 2. Marks individual tinsns as not relaxable if the combination | |
6369 | contains antidependencies. | |
6370 | ||
6371 | Job 2 handles things like swap semantics in instructions that need | |
6372 | to be relaxed. For example, | |
6373 | ||
6374 | addi a0, a1, 100000 | |
6375 | ||
6376 | normally would be relaxed to | |
6377 | ||
6378 | l32r a0, some_label | |
6379 | add a0, a1, a0 | |
6380 | ||
6381 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6382 | ||
6383 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6384 | ||
6385 | then we can't relax it into | |
6386 | ||
6387 | l32r a0, some_label | |
6388 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6389 | ||
6390 | because the value of a0 is trashed before the second add can read it. */ | |
6391 | ||
7fa3d080 BW |
6392 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6393 | ||
43cd72b9 | 6394 | static bfd_boolean |
7fa3d080 | 6395 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6396 | { |
6397 | int i, j; | |
6398 | int branches = 0; | |
6399 | xtensa_isa isa = xtensa_default_isa; | |
6400 | ||
9c2799c2 | 6401 | gas_assert (!past_xtensa_end); |
43cd72b9 BW |
6402 | |
6403 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6404 | { | |
6405 | TInsn *op1 = &vinsn->slots[i]; | |
6406 | if (op1->is_specific_opcode) | |
6407 | op1->keep_wide = TRUE; | |
6408 | else | |
6409 | op1->keep_wide = FALSE; | |
6410 | } | |
6411 | ||
6412 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6413 | { | |
6414 | TInsn *op1 = &vinsn->slots[i]; | |
6415 | ||
6416 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6417 | branches++; | |
6418 | ||
6419 | for (j = 0; j < vinsn->num_slots; j++) | |
6420 | { | |
6421 | if (i != j) | |
6422 | { | |
6423 | TInsn *op2 = &vinsn->slots[j]; | |
6424 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6425 | switch (conflict_type) | |
6426 | { | |
6427 | case 'c': | |
6428 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6429 | xtensa_opcode_name (isa, op1->opcode), i, | |
6430 | xtensa_opcode_name (isa, op2->opcode), j); | |
6431 | return TRUE; | |
6432 | case 'd': | |
6433 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6434 | xtensa_opcode_name (isa, op1->opcode), i, | |
6435 | xtensa_opcode_name (isa, op2->opcode), j); | |
6436 | return TRUE; | |
6437 | case 'e': | |
53dfbcc7 | 6438 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6439 | xtensa_opcode_name (isa, op1->opcode), i, |
6440 | xtensa_opcode_name (isa, op2->opcode), j); | |
6441 | return TRUE; | |
6442 | case 'f': | |
53dfbcc7 | 6443 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6444 | xtensa_opcode_name (isa, op1->opcode), i, |
6445 | xtensa_opcode_name (isa, op2->opcode), j); | |
6446 | return TRUE; | |
6447 | default: | |
6448 | /* Everything is OK. */ | |
6449 | break; | |
6450 | } | |
6451 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6452 | || conflict_type == 'a'); | |
6453 | } | |
6454 | } | |
6455 | } | |
6456 | ||
6457 | if (branches > 1) | |
6458 | { | |
6459 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6460 | return TRUE; | |
6461 | } | |
6462 | ||
6463 | return FALSE; | |
6464 | } | |
6465 | ||
6466 | ||
a1ace8d8 | 6467 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6468 | Cases found are: |
6469 | ||
6470 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6471 | case B: no relationship between what is read and written (both could | |
6472 | read the same reg though) | |
c138bc38 | 6473 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6474 | bundle) |
6475 | case D: t1 writes a state that t2 also writes | |
6476 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6477 | case F: two volatile queue accesses |
43cd72b9 BW |
6478 | */ |
6479 | ||
6480 | static char | |
7fa3d080 | 6481 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6482 | { |
6483 | xtensa_isa isa = xtensa_default_isa; | |
6484 | xtensa_regfile t1_regfile, t2_regfile; | |
6485 | int t1_reg, t2_reg; | |
6486 | int t1_base_reg, t1_last_reg; | |
6487 | int t2_base_reg, t2_last_reg; | |
6488 | char t1_inout, t2_inout; | |
6489 | int i, j; | |
6490 | char conflict = 'b'; | |
6491 | int t1_states; | |
6492 | int t2_states; | |
6493 | int t1_interfaces; | |
6494 | int t2_interfaces; | |
6495 | bfd_boolean t1_volatile = FALSE; | |
6496 | bfd_boolean t2_volatile = FALSE; | |
6497 | ||
6498 | /* Check registers. */ | |
6499 | for (j = 0; j < t2->ntok; j++) | |
6500 | { | |
6501 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6502 | continue; | |
6503 | ||
6504 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6505 | t2_base_reg = t2->tok[j].X_add_number; | |
6506 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6507 | ||
6508 | for (i = 0; i < t1->ntok; i++) | |
6509 | { | |
6510 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6511 | continue; | |
6512 | ||
6513 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6514 | ||
6515 | if (t1_regfile != t2_regfile) | |
6516 | continue; | |
6517 | ||
6518 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6519 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6520 | ||
6521 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6522 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6523 | { | |
6524 | if (t1_inout == 'm' || t1_inout == 'o' | |
6525 | || t2_inout == 'm' || t2_inout == 'o') | |
6526 | { | |
6527 | conflict = 'a'; | |
6528 | continue; | |
6529 | } | |
6530 | } | |
6531 | ||
6532 | t1_base_reg = t1->tok[i].X_add_number; | |
6533 | t1_last_reg = (t1_base_reg | |
6534 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6535 | ||
6536 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6537 | { | |
6538 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6539 | { | |
6540 | if (t1_reg != t2_reg) | |
6541 | continue; | |
6542 | ||
6543 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6544 | { |
6545 | conflict = 'a'; | |
6546 | continue; | |
6547 | } | |
43cd72b9 | 6548 | |
7fa3d080 BW |
6549 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6550 | { | |
6551 | conflict = 'a'; | |
6552 | continue; | |
6553 | } | |
43cd72b9 | 6554 | |
7fa3d080 BW |
6555 | if (t1_inout != 'i' && t2_inout != 'i') |
6556 | return 'c'; | |
6557 | } | |
6558 | } | |
6559 | } | |
6560 | } | |
43cd72b9 | 6561 | |
7fa3d080 BW |
6562 | /* Check states. */ |
6563 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6564 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6565 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6566 | { |
7fa3d080 BW |
6567 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6568 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6569 | for (i = 0; i < t1_states; i++) | |
6570 | { | |
6571 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6572 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6573 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6574 | continue; |
43cd72b9 | 6575 | |
7fa3d080 BW |
6576 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6577 | { | |
6578 | conflict = 'a'; | |
6579 | continue; | |
6580 | } | |
c138bc38 | 6581 | |
7fa3d080 BW |
6582 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6583 | { | |
6584 | conflict = 'a'; | |
6585 | continue; | |
6586 | } | |
c138bc38 | 6587 | |
7fa3d080 BW |
6588 | if (t1_inout != 'i' && t2_inout != 'i') |
6589 | return 'd'; | |
c138bc38 | 6590 | } |
7fa3d080 | 6591 | } |
43cd72b9 | 6592 | |
7fa3d080 BW |
6593 | /* Check tieports. */ |
6594 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6595 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6596 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6597 | { |
7fa3d080 BW |
6598 | xtensa_interface t2_int |
6599 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6600 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6601 | ||
53dfbcc7 | 6602 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6603 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6604 | t2_volatile = TRUE; |
a1ace8d8 | 6605 | |
7fa3d080 BW |
6606 | for (i = 0; i < t1_interfaces; i++) |
6607 | { | |
6608 | xtensa_interface t1_int | |
6609 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6610 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6611 | |
53dfbcc7 | 6612 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6613 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6614 | t1_volatile = TRUE; |
a1ace8d8 BW |
6615 | |
6616 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6617 | return 'f'; | |
c138bc38 | 6618 | |
7fa3d080 BW |
6619 | if (t1_int != t2_int) |
6620 | continue; | |
c138bc38 | 6621 | |
7fa3d080 BW |
6622 | if (t2_inout == 'i' && t1_inout == 'o') |
6623 | { | |
6624 | conflict = 'a'; | |
6625 | continue; | |
6626 | } | |
c138bc38 | 6627 | |
7fa3d080 BW |
6628 | if (t1_inout == 'i' && t2_inout == 'o') |
6629 | { | |
6630 | conflict = 'a'; | |
6631 | continue; | |
6632 | } | |
c138bc38 | 6633 | |
7fa3d080 BW |
6634 | if (t1_inout != 'i' && t2_inout != 'i') |
6635 | return 'e'; | |
6636 | } | |
43cd72b9 | 6637 | } |
c138bc38 | 6638 | |
7fa3d080 | 6639 | return conflict; |
43cd72b9 BW |
6640 | } |
6641 | ||
6642 | ||
6643 | static xtensa_format | |
7fa3d080 | 6644 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6645 | { |
6646 | /* Right now we assume that the ops within the vinsn are properly | |
6647 | ordered for the slots that the programmer wanted them in. In | |
6648 | other words, we don't rearrange the ops in hopes of finding a | |
6649 | better format. The scheduler handles that. */ | |
6650 | ||
6651 | xtensa_isa isa = xtensa_default_isa; | |
6652 | xtensa_format format; | |
43cd72b9 BW |
6653 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6654 | ||
65738a7d BW |
6655 | if (vinsn->num_slots == 1) |
6656 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6657 | ||
43cd72b9 BW |
6658 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6659 | { | |
d8392fd9 SA |
6660 | vliw_insn v_copy; |
6661 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6662 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6663 | { | |
6664 | int slot; | |
6665 | int fit = 0; | |
6666 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6667 | { | |
6668 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6669 | { | |
6670 | v_copy.slots[slot].opcode = | |
6671 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6672 | v_copy.slots[slot].ntok = 0; | |
6673 | } | |
6674 | ||
6675 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6676 | format, slot)) | |
6677 | fit++; | |
7fa3d080 | 6678 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6679 | { |
7fa3d080 BW |
6680 | TInsn widened; |
6681 | /* Try the widened version. */ | |
6682 | if (!v_copy.slots[slot].keep_wide | |
6683 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6684 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6685 | &widened, TRUE) | |
7fa3d080 BW |
6686 | && opcode_fits_format_slot (widened.opcode, |
6687 | format, slot)) | |
43cd72b9 | 6688 | { |
7fa3d080 BW |
6689 | v_copy.slots[slot] = widened; |
6690 | fit++; | |
43cd72b9 BW |
6691 | } |
6692 | } | |
6693 | } | |
6694 | if (fit == v_copy.num_slots) | |
6695 | { | |
d8392fd9 | 6696 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6697 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6698 | vinsn->format = format; | |
6699 | break; | |
6700 | } | |
6701 | } | |
6702 | } | |
6703 | ||
6704 | if (format == xtensa_isa_num_formats (isa)) | |
6705 | return XTENSA_UNDEFINED; | |
6706 | ||
6707 | return format; | |
6708 | } | |
6709 | ||
6710 | ||
6711 | /* Return the additional space needed in a frag | |
6712 | for possible relaxations of any ops in a VLIW insn. | |
6713 | Also fill out the relaxations that might be required of | |
6714 | each tinsn in the vinsn. */ | |
6715 | ||
6716 | static int | |
e7da6241 | 6717 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6718 | { |
e7da6241 | 6719 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6720 | int extra_space = 0; |
6721 | int slot; | |
6722 | ||
6723 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6724 | { | |
6725 | TInsn *tinsn = &vinsn->slots[slot]; | |
6726 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6727 | { | |
6728 | /* A narrow instruction could be widened later to help | |
6729 | alignment issues. */ | |
84b08ed9 | 6730 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6731 | && !tinsn->is_specific_opcode |
6732 | && vinsn->num_slots == 1) | |
6733 | { | |
6734 | /* Difference in bytes between narrow and wide insns... */ | |
6735 | extra_space += 1; | |
6736 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6737 | } |
6738 | } | |
6739 | else | |
6740 | { | |
b08b5071 BW |
6741 | if (workaround_b_j_loop_end |
6742 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6743 | && use_transform ()) |
6744 | { | |
6745 | /* Add 2 of these. */ | |
6746 | extra_space += 3; /* for the nop size */ | |
6747 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6748 | } | |
c138bc38 | 6749 | |
43cd72b9 BW |
6750 | /* Need to assemble it with space for the relocation. */ |
6751 | if (xg_is_relaxable_insn (tinsn, 0) | |
6752 | && !tinsn->is_specific_opcode) | |
6753 | { | |
6754 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6755 | int max_literal_size = | |
6756 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6757 | |
43cd72b9 | 6758 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6759 | |
43cd72b9 | 6760 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6761 | extra_space += max_size; |
6762 | } | |
6763 | else | |
6764 | { | |
e7da6241 BW |
6765 | /* A fix record will be added for this instruction prior |
6766 | to relaxation, so make it end the frag. */ | |
6767 | finish_frag = TRUE; | |
43cd72b9 BW |
6768 | } |
6769 | } | |
6770 | } | |
e7da6241 | 6771 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6772 | return extra_space; |
6773 | } | |
6774 | ||
6775 | ||
6776 | static void | |
b2d179be | 6777 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6778 | { |
6779 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6780 | int slot, chosen_slot; |
43cd72b9 | 6781 | |
b2d179be | 6782 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6783 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6784 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6785 | |
b2d179be BW |
6786 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6787 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6788 | { |
b2d179be BW |
6789 | if (slot == chosen_slot) |
6790 | vinsn->slots[slot] = *tinsn; | |
6791 | else | |
6792 | { | |
6793 | vinsn->slots[slot].opcode = | |
6794 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6795 | vinsn->slots[slot].ntok = 0; | |
6796 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6797 | } | |
43cd72b9 | 6798 | } |
43cd72b9 BW |
6799 | } |
6800 | ||
6801 | ||
6802 | static bfd_boolean | |
7fa3d080 | 6803 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6804 | { |
6805 | int i; | |
6806 | IStack istack; /* put instructions into here */ | |
6807 | symbolS *lit_sym = NULL; | |
6808 | symbolS *label_sym = NULL; | |
6809 | ||
6810 | istack_init (&istack); | |
6811 | ||
6812 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6813 | Because the scheduling and bundling characteristics of movi and |
6814 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6815 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6816 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6817 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6818 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6819 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
6820 | || orig_insn->tok[1].X_op == O_pltrel |
6821 | || orig_insn->tok[1].X_op == O_tlsfunc | |
6822 | || orig_insn->tok[1].X_op == O_tlsarg | |
6823 | || orig_insn->tok[1].X_op == O_tpoff | |
6824 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 6825 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
6826 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6827 | else | |
6828 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6829 | return TRUE; | |
6830 | ||
6831 | for (i = 0; i < istack.ninsn; i++) | |
6832 | { | |
6833 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6834 | switch (insn->insn_type) |
43cd72b9 BW |
6835 | { |
6836 | case ITYPE_LITERAL: | |
9c2799c2 | 6837 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6838 | lit_sym = xg_assemble_literal (insn); |
6839 | break; | |
6840 | case ITYPE_LABEL: | |
6841 | { | |
6842 | static int relaxed_sym_idx = 0; | |
6843 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6844 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6845 | colon (label); | |
9c2799c2 | 6846 | gas_assert (label_sym == NULL); |
43cd72b9 | 6847 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 6848 | gas_assert (label_sym); |
43cd72b9 BW |
6849 | free (label); |
6850 | } | |
6851 | break; | |
6852 | case ITYPE_INSN: | |
b2d179be BW |
6853 | { |
6854 | vliw_insn v; | |
6855 | if (lit_sym) | |
6856 | xg_resolve_literals (insn, lit_sym); | |
6857 | if (label_sym) | |
6858 | xg_resolve_labels (insn, label_sym); | |
6859 | xg_init_vinsn (&v); | |
6860 | bundle_tinsn (insn, &v); | |
6861 | finish_vinsn (&v); | |
6862 | xg_free_vinsn (&v); | |
6863 | } | |
43cd72b9 BW |
6864 | break; |
6865 | default: | |
9c2799c2 | 6866 | gas_assert (0); |
43cd72b9 BW |
6867 | break; |
6868 | } | |
6869 | } | |
6870 | return FALSE; | |
6871 | } | |
6872 | ||
6873 | ||
34e41783 BW |
6874 | static int |
6875 | total_frag_text_expansion (fragS *fragP) | |
6876 | { | |
6877 | int slot; | |
6878 | int total_expansion = 0; | |
6879 | ||
62af60e2 | 6880 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
6881 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
6882 | ||
6883 | return total_expansion; | |
6884 | } | |
6885 | ||
6886 | ||
43cd72b9 BW |
6887 | /* Emit a vliw instruction to the current fragment. */ |
6888 | ||
7fa3d080 BW |
6889 | static void |
6890 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6891 | { |
e7da6241 | 6892 | bfd_boolean finish_frag; |
43cd72b9 BW |
6893 | bfd_boolean is_jump = FALSE; |
6894 | bfd_boolean is_branch = FALSE; | |
6895 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
6896 | int insn_size; |
6897 | int extra_space; | |
6898 | char *f = NULL; | |
6899 | int slot; | |
b224e962 BW |
6900 | struct dwarf2_line_info debug_line; |
6901 | bfd_boolean loc_directive_seen = FALSE; | |
6902 | TInsn *tinsn; | |
43cd72b9 | 6903 | |
b224e962 | 6904 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
6905 | |
6906 | if (generating_literals) | |
6907 | { | |
6908 | static int reported = 0; | |
6909 | if (reported < 4) | |
6910 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6911 | _("cannot assemble into a literal fragment")); | |
6912 | if (reported == 3) | |
6913 | as_bad (_("...")); | |
6914 | reported++; | |
6915 | return; | |
6916 | } | |
6917 | ||
6918 | if (frag_now_fix () != 0 | |
b08b5071 | 6919 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6920 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6921 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6922 | || (directive_state[directive_longcalls] |
6923 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6924 | || (directive_state[directive_absolute_literals] |
6925 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6926 | { | |
6927 | frag_wane (frag_now); | |
6928 | frag_new (0); | |
6929 | xtensa_set_frag_assembly_state (frag_now); | |
6930 | } | |
6931 | ||
6932 | if (workaround_a0_b_retw | |
6933 | && vinsn->num_slots == 1 | |
6934 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6935 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6936 | && use_transform ()) | |
6937 | { | |
6938 | has_a0_b_retw = TRUE; | |
6939 | ||
6940 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6941 | After the first assembly pass we will check all of them and | |
6942 | add a nop if needed. */ | |
6943 | frag_now->tc_frag_data.is_insn = TRUE; | |
6944 | frag_var (rs_machine_dependent, 4, 4, | |
6945 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6946 | frag_now->fr_symbol, | |
6947 | frag_now->fr_offset, | |
6948 | NULL); | |
6949 | xtensa_set_frag_assembly_state (frag_now); | |
6950 | frag_now->tc_frag_data.is_insn = TRUE; | |
6951 | frag_var (rs_machine_dependent, 4, 4, | |
6952 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6953 | frag_now->fr_symbol, | |
6954 | frag_now->fr_offset, | |
6955 | NULL); | |
6956 | xtensa_set_frag_assembly_state (frag_now); | |
6957 | } | |
6958 | ||
b224e962 | 6959 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 6960 | { |
b224e962 BW |
6961 | tinsn = &vinsn->slots[slot]; |
6962 | ||
43cd72b9 | 6963 | /* See if the instruction implies an aligned section. */ |
b224e962 | 6964 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 6965 | record_alignment (now_seg, 2); |
c138bc38 | 6966 | |
b224e962 BW |
6967 | /* Determine the best line number for debug info. */ |
6968 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
6969 | && (tinsn->debug_line.filenum != debug_line.filenum | |
6970 | || tinsn->debug_line.line < debug_line.line | |
6971 | || tinsn->debug_line.column < debug_line.column)) | |
6972 | debug_line = tinsn->debug_line; | |
6973 | if (tinsn->loc_directive_seen) | |
6974 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
6975 | } |
6976 | ||
6977 | /* Special cases for instructions that force an alignment... */ | |
6978 | /* None of these opcodes are bundle-able. */ | |
6979 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6980 | { | |
d77b99c9 | 6981 | int max_fill; |
c138bc38 | 6982 | |
05d58145 BW |
6983 | /* Remember the symbol that marks the end of the loop in the frag |
6984 | that marks the start of the loop. This way we can easily find | |
6985 | the end of the loop at the beginning, without adding special code | |
6986 | to mark the loop instructions themselves. */ | |
6987 | symbolS *target_sym = NULL; | |
6988 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6989 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6990 | ||
43cd72b9 BW |
6991 | xtensa_set_frag_assembly_state (frag_now); |
6992 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6993 | |
43cd72b9 BW |
6994 | max_fill = get_text_align_max_fill_size |
6995 | (get_text_align_power (xtensa_fetch_width), | |
6996 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6997 | ||
6998 | if (use_transform ()) | |
6999 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7000 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7001 | else |
c138bc38 | 7002 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7003 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7004 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7005 | } |
7006 | ||
b08b5071 | 7007 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7008 | && !vinsn->slots[0].is_specific_opcode) |
7009 | { | |
7010 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7011 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7012 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7013 | } | |
7014 | ||
7015 | if (vinsn->num_slots == 1) | |
7016 | { | |
7017 | if (workaround_a0_b_retw && use_transform ()) | |
7018 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7019 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7020 | ||
7021 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7022 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7023 | } | |
7024 | else | |
7025 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
7026 | ||
7027 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7028 | ||
e7da6241 | 7029 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7030 | |
7031 | /* vinsn_to_insnbuf will produce the error. */ | |
7032 | if (vinsn->format != XTENSA_UNDEFINED) | |
7033 | { | |
d77b99c9 | 7034 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7035 | xtensa_set_frag_assembly_state (frag_now); |
7036 | frag_now->tc_frag_data.is_insn = TRUE; | |
7037 | } | |
7038 | ||
e7da6241 | 7039 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7040 | if (vinsn->format == XTENSA_UNDEFINED) |
7041 | return; | |
7042 | ||
d77b99c9 | 7043 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7044 | |
b224e962 BW |
7045 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7046 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7047 | &debug_line); | |
43cd72b9 BW |
7048 | |
7049 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7050 | { | |
b224e962 | 7051 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7052 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7053 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7054 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
7055 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
7056 | if (tinsn->literal_space != 0) | |
7057 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7058 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7059 | |
7060 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7061 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 BW |
7062 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
7063 | is_jump = TRUE; | |
7064 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7065 | is_branch = TRUE; | |
7066 | ||
e7da6241 BW |
7067 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7068 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7069 | finish_frag = TRUE; |
7070 | } | |
7071 | ||
7072 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7073 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7074 | |
7075 | if (finish_frag) | |
7076 | { | |
7077 | frag_variant (rs_machine_dependent, | |
7078 | extra_space, extra_space, RELAX_SLOTS, | |
7079 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7080 | xtensa_set_frag_assembly_state (frag_now); | |
7081 | } | |
7082 | ||
7083 | /* Special cases for loops: | |
7084 | close_loop_end should be inserted AFTER short_loop. | |
7085 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7086 | when converting them. */ | |
7087 | ||
7088 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7089 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7090 | && !vinsn->slots[0].is_specific_opcode) |
7091 | { | |
7092 | if (workaround_short_loop && use_transform ()) | |
7093 | { | |
7094 | maybe_has_short_loop = TRUE; | |
7095 | frag_now->tc_frag_data.is_insn = TRUE; | |
7096 | frag_var (rs_machine_dependent, 4, 4, | |
7097 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7098 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7099 | frag_now->tc_frag_data.is_insn = TRUE; | |
7100 | frag_var (rs_machine_dependent, 4, 4, | |
7101 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7102 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7103 | } | |
7104 | ||
7105 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7106 | loop at least 12 bytes away from another loop's end. */ | |
7107 | if (workaround_close_loop_end && use_transform ()) | |
7108 | { | |
7109 | maybe_has_close_loop_end = TRUE; | |
7110 | frag_now->tc_frag_data.is_insn = TRUE; | |
7111 | frag_var (rs_machine_dependent, 12, 12, | |
7112 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7113 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7114 | } | |
7115 | } | |
7116 | ||
7117 | if (use_transform ()) | |
7118 | { | |
7119 | if (is_jump) | |
7120 | { | |
9c2799c2 | 7121 | gas_assert (finish_frag); |
43cd72b9 BW |
7122 | frag_var (rs_machine_dependent, |
7123 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
7124 | RELAX_UNREACHABLE, | |
7125 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7126 | xtensa_set_frag_assembly_state (frag_now); | |
7127 | } | |
7b1cc377 | 7128 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7129 | { |
9c2799c2 | 7130 | gas_assert (finish_frag); |
43cd72b9 BW |
7131 | frag_var (rs_machine_dependent, |
7132 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
7133 | RELAX_MAYBE_UNREACHABLE, | |
7134 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7135 | xtensa_set_frag_assembly_state (frag_now); | |
7136 | frag_var (rs_machine_dependent, | |
7137 | 0, 0, | |
7138 | RELAX_MAYBE_DESIRE_ALIGN, | |
7139 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7140 | xtensa_set_frag_assembly_state (frag_now); | |
7141 | } | |
7142 | } | |
7143 | ||
7144 | /* Now, if the original opcode was a call... */ | |
7145 | if (do_align_targets () | |
7146 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7147 | { | |
b08b5071 | 7148 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7149 | frag_now->tc_frag_data.is_insn = TRUE; |
7150 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7151 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7152 | xtensa_set_frag_assembly_state (frag_now); | |
7153 | } | |
7154 | ||
7155 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7156 | { | |
7157 | frag_wane (frag_now); | |
7158 | frag_new (0); | |
7159 | xtensa_set_frag_assembly_state (frag_now); | |
7160 | } | |
7161 | } | |
7162 | ||
7163 | \f | |
7fa3d080 BW |
7164 | /* xtensa_end and helper functions. */ |
7165 | ||
7166 | static void xtensa_cleanup_align_frags (void); | |
7167 | static void xtensa_fix_target_frags (void); | |
7168 | static void xtensa_mark_narrow_branches (void); | |
7169 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7170 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7171 | static void xtensa_fix_a0_b_retw_frags (void); |
7172 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7173 | static void xtensa_fix_close_loop_end_frags (void); | |
7174 | static void xtensa_fix_short_loop_frags (void); | |
7175 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7176 | static void xtensa_add_config_info (void); |
7fa3d080 | 7177 | |
43cd72b9 | 7178 | void |
7fa3d080 | 7179 | xtensa_end (void) |
43cd72b9 BW |
7180 | { |
7181 | directive_balance (); | |
7182 | xtensa_flush_pending_output (); | |
7183 | ||
7184 | past_xtensa_end = TRUE; | |
7185 | ||
7186 | xtensa_move_literals (); | |
7187 | ||
7188 | xtensa_reorder_segments (); | |
7189 | xtensa_cleanup_align_frags (); | |
7190 | xtensa_fix_target_frags (); | |
7191 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7192 | xtensa_fix_a0_b_retw_frags (); | |
7193 | if (workaround_b_j_loop_end) | |
7194 | xtensa_fix_b_j_loop_end_frags (); | |
7195 | ||
7196 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7197 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7198 | xtensa_fix_close_loop_end_frags (); | |
7199 | ||
7200 | if (workaround_short_loop && maybe_has_short_loop) | |
7201 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7202 | if (align_targets) |
7203 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7204 | xtensa_mark_zcl_first_insns (); |
7205 | ||
7206 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7207 | |
7208 | xtensa_add_config_info (); | |
43cd72b9 BW |
7209 | } |
7210 | ||
7211 | ||
7212 | static void | |
7fa3d080 | 7213 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7214 | { |
7215 | frchainS *frchP; | |
c9049d30 | 7216 | asection *s; |
43cd72b9 | 7217 | |
c9049d30 AM |
7218 | for (s = stdoutput->sections; s; s = s->next) |
7219 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7220 | { | |
7221 | fragS *fragP; | |
7222 | /* Walk over all of the fragments in a subsection. */ | |
7223 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7224 | { | |
7225 | if ((fragP->fr_type == rs_align | |
7226 | || fragP->fr_type == rs_align_code | |
7227 | || (fragP->fr_type == rs_machine_dependent | |
7228 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7229 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7230 | && fragP->fr_fix == 0) | |
7231 | { | |
7232 | fragS *next = fragP->fr_next; | |
7233 | ||
7234 | while (next | |
7235 | && next->fr_fix == 0 | |
7236 | && next->fr_type == rs_machine_dependent | |
7237 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7238 | { | |
7239 | frag_wane (next); | |
7240 | next = next->fr_next; | |
7241 | } | |
7242 | } | |
7243 | /* If we don't widen branch targets, then they | |
7244 | will be easier to align. */ | |
7245 | if (fragP->tc_frag_data.is_branch_target | |
7246 | && fragP->fr_opcode == fragP->fr_literal | |
7247 | && fragP->fr_type == rs_machine_dependent | |
7248 | && fragP->fr_subtype == RELAX_SLOTS | |
7249 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7250 | frag_wane (fragP); | |
7251 | if (fragP->fr_type == rs_machine_dependent | |
7252 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7253 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7254 | } | |
7255 | } | |
43cd72b9 BW |
7256 | } |
7257 | ||
7258 | ||
7259 | /* Re-process all of the fragments looking to convert all of the | |
7260 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7261 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7262 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7263 | |
43cd72b9 | 7264 | static void |
7fa3d080 | 7265 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7266 | { |
7267 | frchainS *frchP; | |
c9049d30 | 7268 | asection *s; |
e0001a05 NC |
7269 | |
7270 | /* When this routine is called, all of the subsections are still intact | |
7271 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7272 | for (s = stdoutput->sections; s; s = s->next) |
7273 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7274 | { | |
7275 | fragS *fragP; | |
e0001a05 | 7276 | |
c9049d30 AM |
7277 | /* Walk over all of the fragments in a subsection. */ |
7278 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7279 | { | |
7280 | if (fragP->fr_type == rs_machine_dependent | |
7281 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7282 | { | |
7283 | if (next_frag_is_branch_target (fragP)) | |
7284 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7285 | else | |
7286 | frag_wane (fragP); | |
7287 | } | |
7288 | } | |
7289 | } | |
e0001a05 NC |
7290 | } |
7291 | ||
7292 | ||
7fa3d080 BW |
7293 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7294 | ||
43cd72b9 | 7295 | static void |
7fa3d080 | 7296 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7297 | { |
7298 | frchainS *frchP; | |
c9049d30 | 7299 | asection *s; |
43cd72b9 | 7300 | |
c9049d30 AM |
7301 | for (s = stdoutput->sections; s; s = s->next) |
7302 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7303 | { | |
7304 | fragS *fragP; | |
7305 | /* Walk over all of the fragments in a subsection. */ | |
7306 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7307 | { | |
7308 | if (fragP->fr_type == rs_machine_dependent | |
7309 | && fragP->fr_subtype == RELAX_SLOTS | |
7310 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7311 | { | |
7312 | vliw_insn vinsn; | |
7313 | ||
7314 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7315 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7316 | ||
7317 | if (vinsn.num_slots == 1 | |
7318 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7319 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7320 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7321 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7322 | &vinsn.slots[0])) | |
7323 | { | |
7324 | fragP->fr_subtype = RELAX_SLOTS; | |
7325 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7326 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7327 | } | |
7328 | } | |
7329 | } | |
7330 | } | |
43cd72b9 BW |
7331 | } |
7332 | ||
7333 | ||
7334 | /* A branch is typically widened only when its target is out of | |
7335 | range. However, we would like to widen them to align a subsequent | |
7336 | branch target when possible. | |
7337 | ||
7338 | Because the branch relaxation code is so convoluted, the optimal solution | |
7339 | (combining the two cases) is difficult to get right in all circumstances. | |
7340 | We therefore go with an "almost as good" solution, where we only | |
7341 | use for alignment narrow branches that definitely will not expand to a | |
7342 | jump and a branch. These functions find and mark these cases. */ | |
7343 | ||
a67517f4 BW |
7344 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7345 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7346 | We start counting beginning with the frag after the 2-byte branch, so the | |
7347 | maximum offset is (4 - 2) + 63 = 65. */ | |
7348 | #define MAX_IMMED6 65 | |
43cd72b9 | 7349 | |
d77b99c9 | 7350 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7351 | |
43cd72b9 | 7352 | static bfd_boolean |
7fa3d080 | 7353 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 | 7354 | { |
91d6fa6a NC |
7355 | const expressionS *exp = &tinsn->tok[1]; |
7356 | symbolS *symbolP = exp->X_add_symbol; | |
7357 | offsetT max_distance = exp->X_add_number; | |
e7da6241 BW |
7358 | fragS *target_frag; |
7359 | ||
91d6fa6a | 7360 | if (exp->X_op != O_symbol) |
e7da6241 BW |
7361 | return FALSE; |
7362 | ||
7363 | target_frag = symbol_get_frag (symbolP); | |
7364 | ||
43cd72b9 BW |
7365 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7366 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7367 | return FALSE; | |
7368 | ||
7369 | /* The branch doesn't branch over it's own frag, | |
7370 | but over the subsequent ones. */ | |
7371 | fragP = fragP->fr_next; | |
7372 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7373 | { | |
7374 | max_distance += unrelaxed_frag_max_size (fragP); | |
7375 | fragP = fragP->fr_next; | |
7376 | } | |
7377 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7378 | return TRUE; | |
e0001a05 NC |
7379 | return FALSE; |
7380 | } | |
7381 | ||
7382 | ||
43cd72b9 | 7383 | static void |
7fa3d080 | 7384 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7385 | { |
7386 | frchainS *frchP; | |
c9049d30 | 7387 | asection *s; |
43cd72b9 | 7388 | |
c9049d30 AM |
7389 | for (s = stdoutput->sections; s; s = s->next) |
7390 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7391 | { | |
7392 | fragS *fragP; | |
7393 | /* Walk over all of the fragments in a subsection. */ | |
7394 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7395 | { | |
7396 | if (fragP->fr_type == rs_machine_dependent | |
7397 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7398 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7399 | { | |
7400 | /* Find the loop frag. */ | |
7401 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7402 | /* Find the first insn frag. */ | |
7403 | targ_frag = next_non_empty_frag (targ_frag); | |
7404 | ||
7405 | /* Of course, sometimes (mostly for toy test cases) a | |
7406 | zero-cost loop instruction is the last in a section. */ | |
7407 | if (targ_frag) | |
7408 | { | |
7409 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7410 | /* Do not widen a frag that is the first instruction of a | |
7411 | zero-cost loop. It makes that loop harder to align. */ | |
7412 | if (targ_frag->fr_type == rs_machine_dependent | |
7413 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7414 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7415 | == RELAX_NARROW)) | |
7416 | { | |
7417 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7418 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7419 | else | |
7420 | { | |
7421 | frag_wane (targ_frag); | |
7422 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7423 | } | |
7424 | } | |
7425 | } | |
7426 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7427 | frag_wane (fragP); | |
7428 | } | |
7429 | } | |
7430 | } | |
43cd72b9 BW |
7431 | } |
7432 | ||
7433 | ||
fb227da0 BW |
7434 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
7435 | sleb128 value, the linker is unable to adjust that value to account for | |
7436 | link-time relaxation. Mark all the code between such symbols so that | |
7437 | its size cannot be changed by linker relaxation. */ | |
7438 | ||
6a7eedfe BW |
7439 | static void |
7440 | xtensa_mark_difference_of_two_symbols (void) | |
7441 | { | |
7442 | symbolS *expr_sym; | |
7443 | ||
7444 | for (expr_sym = expr_symbols; expr_sym; | |
7445 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) | |
7446 | { | |
91d6fa6a | 7447 | expressionS *exp = symbol_get_value_expression (expr_sym); |
6a7eedfe | 7448 | |
91d6fa6a | 7449 | if (exp->X_op == O_subtract) |
6a7eedfe | 7450 | { |
91d6fa6a NC |
7451 | symbolS *left = exp->X_add_symbol; |
7452 | symbolS *right = exp->X_op_symbol; | |
6a7eedfe BW |
7453 | |
7454 | /* Difference of two symbols not in the same section | |
7455 | are handled with relocations in the linker. */ | |
7456 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7457 | { | |
7458 | fragS *start; | |
7459 | fragS *end; | |
983f90e3 | 7460 | fragS *walk; |
6a7eedfe BW |
7461 | |
7462 | if (symbol_get_frag (left)->fr_address | |
7463 | <= symbol_get_frag (right)->fr_address) | |
7464 | { | |
7465 | start = symbol_get_frag (left); | |
7466 | end = symbol_get_frag (right); | |
7467 | } | |
7468 | else | |
7469 | { | |
7470 | start = symbol_get_frag (right); | |
7471 | end = symbol_get_frag (left); | |
7472 | } | |
983f90e3 SA |
7473 | |
7474 | if (start->tc_frag_data.no_transform_end != NULL) | |
7475 | walk = start->tc_frag_data.no_transform_end; | |
7476 | else | |
7477 | walk = start; | |
6a7eedfe BW |
7478 | do |
7479 | { | |
983f90e3 SA |
7480 | walk->tc_frag_data.is_no_transform = 1; |
7481 | walk = walk->fr_next; | |
6a7eedfe | 7482 | } |
983f90e3 SA |
7483 | while (walk && walk->fr_address < end->fr_address); |
7484 | ||
7485 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
7486 | } |
7487 | } | |
7488 | } | |
7489 | } | |
7490 | ||
7491 | ||
e0001a05 NC |
7492 | /* Re-process all of the fragments looking to convert all of the |
7493 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7494 | conditional branch or a retw/retw.n, convert this frag to one that | |
7495 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7496 | ||
7fa3d080 BW |
7497 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7498 | ||
e0001a05 | 7499 | static void |
7fa3d080 | 7500 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7501 | { |
7502 | frchainS *frchP; | |
c9049d30 | 7503 | asection *s; |
e0001a05 NC |
7504 | |
7505 | /* When this routine is called, all of the subsections are still intact | |
7506 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7507 | for (s = stdoutput->sections; s; s = s->next) |
7508 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7509 | { | |
7510 | fragS *fragP; | |
e0001a05 | 7511 | |
c9049d30 AM |
7512 | /* Walk over all of the fragments in a subsection. */ |
7513 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7514 | { | |
7515 | if (fragP->fr_type == rs_machine_dependent | |
7516 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7517 | { | |
7518 | if (next_instrs_are_b_retw (fragP)) | |
7519 | { | |
7520 | if (fragP->tc_frag_data.is_no_transform) | |
7521 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7522 | else | |
7523 | relax_frag_add_nop (fragP); | |
7524 | } | |
7525 | frag_wane (fragP); | |
7526 | } | |
7527 | } | |
7528 | } | |
e0001a05 NC |
7529 | } |
7530 | ||
7531 | ||
7fa3d080 BW |
7532 | static bfd_boolean |
7533 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7534 | { |
7535 | xtensa_opcode opcode; | |
43cd72b9 | 7536 | xtensa_format fmt; |
e0001a05 NC |
7537 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7538 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7539 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7540 | xtensa_isa isa = xtensa_default_isa; |
7541 | int offset = 0; | |
43cd72b9 BW |
7542 | int slot; |
7543 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7544 | |
7545 | if (!insnbuf) | |
43cd72b9 BW |
7546 | { |
7547 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7548 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7549 | } | |
e0001a05 NC |
7550 | |
7551 | if (next_fragP == NULL) | |
7552 | return FALSE; | |
7553 | ||
7554 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7555 | xtensa_insnbuf_from_chars |
7556 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7557 | fmt = xtensa_format_decode (isa, insnbuf); |
7558 | if (fmt == XTENSA_UNDEFINED) | |
7559 | return FALSE; | |
7560 | ||
7561 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7562 | { | |
7563 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7564 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7565 | ||
7566 | branch_seen = (branch_seen | |
7567 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7568 | } | |
e0001a05 | 7569 | |
43cd72b9 | 7570 | if (!branch_seen) |
e0001a05 NC |
7571 | return FALSE; |
7572 | ||
43cd72b9 | 7573 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7574 | if (offset == next_fragP->fr_fix) |
7575 | { | |
7576 | next_fragP = next_non_empty_frag (next_fragP); | |
7577 | offset = 0; | |
7578 | } | |
43cd72b9 | 7579 | |
e0001a05 NC |
7580 | if (next_fragP == NULL) |
7581 | return FALSE; | |
7582 | ||
7583 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7584 | xtensa_insnbuf_from_chars |
7585 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7586 | fmt = xtensa_format_decode (isa, insnbuf); |
7587 | ||
7588 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7589 | have no problems. */ | |
7590 | if (fmt == XTENSA_UNDEFINED | |
7591 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7592 | return FALSE; | |
7593 | ||
7594 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7595 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7596 | |
b08b5071 | 7597 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7598 | return TRUE; |
43cd72b9 | 7599 | |
e0001a05 NC |
7600 | return FALSE; |
7601 | } | |
7602 | ||
7603 | ||
7604 | /* Re-process all of the fragments looking to convert all of the | |
7605 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7606 | loop end label, convert this frag to one that will generate a NOP. | |
7607 | In any case close it off with a .fill 0. */ | |
7608 | ||
7fa3d080 BW |
7609 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7610 | ||
e0001a05 | 7611 | static void |
7fa3d080 | 7612 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7613 | { |
7614 | frchainS *frchP; | |
c9049d30 | 7615 | asection *s; |
e0001a05 NC |
7616 | |
7617 | /* When this routine is called, all of the subsections are still intact | |
7618 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7619 | for (s = stdoutput->sections; s; s = s->next) |
7620 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7621 | { | |
7622 | fragS *fragP; | |
e0001a05 | 7623 | |
c9049d30 AM |
7624 | /* Walk over all of the fragments in a subsection. */ |
7625 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7626 | { | |
7627 | if (fragP->fr_type == rs_machine_dependent | |
7628 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7629 | { | |
7630 | if (next_instr_is_loop_end (fragP)) | |
7631 | { | |
7632 | if (fragP->tc_frag_data.is_no_transform) | |
7633 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7634 | else | |
7635 | relax_frag_add_nop (fragP); | |
7636 | } | |
7637 | frag_wane (fragP); | |
7638 | } | |
7639 | } | |
7640 | } | |
e0001a05 NC |
7641 | } |
7642 | ||
7643 | ||
7fa3d080 BW |
7644 | static bfd_boolean |
7645 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7646 | { |
7647 | const fragS *next_fragP; | |
7648 | ||
7649 | if (next_frag_is_loop_target (fragP)) | |
7650 | return FALSE; | |
7651 | ||
7652 | next_fragP = next_non_empty_frag (fragP); | |
7653 | if (next_fragP == NULL) | |
7654 | return FALSE; | |
7655 | ||
7656 | if (!next_frag_is_loop_target (next_fragP)) | |
7657 | return FALSE; | |
7658 | ||
7659 | /* If the size is >= 3 then there is more than one instruction here. | |
7660 | The hardware bug will not fire. */ | |
7661 | if (next_fragP->fr_fix > 3) | |
7662 | return FALSE; | |
7663 | ||
7664 | return TRUE; | |
7665 | } | |
7666 | ||
7667 | ||
7668 | /* Re-process all of the fragments looking to convert all of the | |
7669 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7670 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7671 | make it at least 12 bytes away. In any case close it off with a | |
7672 | .fill 0. */ | |
7673 | ||
d77b99c9 | 7674 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7675 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7676 | |
e0001a05 | 7677 | static void |
7fa3d080 | 7678 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7679 | { |
7680 | frchainS *frchP; | |
c9049d30 | 7681 | asection *s; |
e0001a05 NC |
7682 | |
7683 | /* When this routine is called, all of the subsections are still intact | |
7684 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7685 | for (s = stdoutput->sections; s; s = s->next) |
7686 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7687 | { | |
7688 | fragS *fragP; | |
e0001a05 | 7689 | |
c9049d30 | 7690 | fragS *current_target = NULL; |
e0001a05 | 7691 | |
c9049d30 AM |
7692 | /* Walk over all of the fragments in a subsection. */ |
7693 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7694 | { | |
7695 | if (fragP->fr_type == rs_machine_dependent | |
7696 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7697 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7698 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7699 | |
c9049d30 AM |
7700 | if (current_target |
7701 | && fragP->fr_type == rs_machine_dependent | |
7702 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7703 | { | |
7704 | offsetT min_bytes; | |
7705 | int bytes_added = 0; | |
e0001a05 NC |
7706 | |
7707 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7708 | /* Max out at 12. */ |
7709 | min_bytes = min_bytes_to_other_loop_end | |
7710 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7711 | ||
7712 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7713 | { | |
7714 | if (fragP->tc_frag_data.is_no_transform) | |
7715 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7716 | else | |
7717 | { | |
7718 | while (min_bytes + bytes_added | |
7719 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7720 | { | |
7721 | int length = 3; | |
7722 | ||
7723 | if (fragP->fr_var < length) | |
7724 | as_fatal (_("fr_var %lu < length %d"), | |
7725 | (long) fragP->fr_var, length); | |
7726 | else | |
7727 | { | |
7728 | assemble_nop (length, | |
7729 | fragP->fr_literal + fragP->fr_fix); | |
7730 | fragP->fr_fix += length; | |
7731 | fragP->fr_var -= length; | |
7732 | } | |
7733 | bytes_added += length; | |
7734 | } | |
7735 | } | |
7736 | } | |
7737 | frag_wane (fragP); | |
7738 | } | |
9c2799c2 | 7739 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
7740 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
7741 | } | |
7742 | } | |
e0001a05 NC |
7743 | } |
7744 | ||
7745 | ||
d77b99c9 | 7746 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7747 | |
d77b99c9 | 7748 | static offsetT |
7fa3d080 BW |
7749 | min_bytes_to_other_loop_end (fragS *fragP, |
7750 | fragS *current_target, | |
d77b99c9 | 7751 | offsetT max_size) |
e0001a05 | 7752 | { |
d77b99c9 | 7753 | offsetT offset = 0; |
e0001a05 NC |
7754 | fragS *current_fragP; |
7755 | ||
7756 | for (current_fragP = fragP; | |
7757 | current_fragP; | |
7758 | current_fragP = current_fragP->fr_next) | |
7759 | { | |
7760 | if (current_fragP->tc_frag_data.is_loop_target | |
7761 | && current_fragP != current_target) | |
05d58145 | 7762 | return offset; |
e0001a05 NC |
7763 | |
7764 | offset += unrelaxed_frag_min_size (current_fragP); | |
7765 | ||
05d58145 | 7766 | if (offset >= max_size) |
e0001a05 NC |
7767 | return max_size; |
7768 | } | |
7769 | return max_size; | |
7770 | } | |
7771 | ||
7772 | ||
d77b99c9 | 7773 | static offsetT |
7fa3d080 | 7774 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7775 | { |
d77b99c9 | 7776 | offsetT size = fragP->fr_fix; |
e0001a05 | 7777 | |
d77b99c9 | 7778 | /* Add fill size. */ |
e0001a05 NC |
7779 | if (fragP->fr_type == rs_fill) |
7780 | size += fragP->fr_offset; | |
7781 | ||
7782 | return size; | |
7783 | } | |
7784 | ||
7785 | ||
d77b99c9 | 7786 | static offsetT |
7fa3d080 | 7787 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7788 | { |
d77b99c9 | 7789 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7790 | switch (fragP->fr_type) |
7791 | { | |
7792 | case 0: | |
c138bc38 | 7793 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7794 | end up with type 0. */ |
7795 | break; | |
7796 | case rs_fill: | |
7797 | case rs_org: | |
7798 | case rs_space: | |
7799 | size += fragP->fr_offset; | |
7800 | break; | |
7801 | case rs_align: | |
7802 | case rs_align_code: | |
7803 | case rs_align_test: | |
7804 | case rs_leb128: | |
7805 | case rs_cfa: | |
7806 | case rs_dwarf2dbg: | |
7807 | /* No further adjustments needed. */ | |
7808 | break; | |
7809 | case rs_machine_dependent: | |
7810 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7811 | size += fragP->fr_var; | |
7812 | break; | |
7813 | default: | |
7814 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 7815 | gas_assert (0); |
43cd72b9 BW |
7816 | break; |
7817 | } | |
7818 | ||
7819 | return size; | |
7820 | } | |
7821 | ||
7822 | ||
e0001a05 NC |
7823 | /* Re-process all of the fragments looking to convert all |
7824 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7825 | ||
7826 | A) | |
7827 | 1) the instruction size count to the loop end label | |
7828 | is too short (<= 2 instructions), | |
7829 | 2) loop has a jump or branch in it | |
7830 | ||
7831 | or B) | |
43cd72b9 | 7832 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7833 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7834 | 3) the instruction size count to the loop end label is too short | |
7835 | (<= 2 instructions) | |
7836 | then convert this frag (and maybe the next one) to generate a NOP. | |
7837 | In any case close it off with a .fill 0. */ | |
7838 | ||
d77b99c9 | 7839 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7840 | static bfd_boolean branch_before_loop_end (fragS *); |
7841 | ||
e0001a05 | 7842 | static void |
7fa3d080 | 7843 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7844 | { |
7845 | frchainS *frchP; | |
c9049d30 | 7846 | asection *s; |
e0001a05 NC |
7847 | |
7848 | /* When this routine is called, all of the subsections are still intact | |
7849 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7850 | for (s = stdoutput->sections; s; s = s->next) |
7851 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7852 | { | |
7853 | fragS *fragP; | |
7854 | fragS *current_target = NULL; | |
7855 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7856 | |
c9049d30 AM |
7857 | /* Walk over all of the fragments in a subsection. */ |
7858 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7859 | { | |
7860 | if (fragP->fr_type == rs_machine_dependent | |
7861 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7862 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7863 | { | |
7864 | TInsn t_insn; | |
7865 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7866 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7867 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7868 | current_opcode = t_insn.opcode; | |
9c2799c2 | 7869 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 7870 | current_opcode) == 1); |
c9049d30 | 7871 | } |
e0001a05 | 7872 | |
c9049d30 AM |
7873 | if (fragP->fr_type == rs_machine_dependent |
7874 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7875 | { | |
7876 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7877 | && (branch_before_loop_end (fragP->fr_next) | |
7878 | || (workaround_all_short_loops | |
7879 | && current_opcode != XTENSA_UNDEFINED | |
7880 | && current_opcode != xtensa_loop_opcode))) | |
7881 | { | |
7882 | if (fragP->tc_frag_data.is_no_transform) | |
7883 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7884 | else | |
7885 | relax_frag_add_nop (fragP); | |
7886 | } | |
7887 | frag_wane (fragP); | |
7888 | } | |
7889 | } | |
7890 | } | |
e0001a05 NC |
7891 | } |
7892 | ||
7893 | ||
d77b99c9 | 7894 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7895 | |
d77b99c9 | 7896 | static int |
7fa3d080 BW |
7897 | count_insns_to_loop_end (fragS *base_fragP, |
7898 | bfd_boolean count_relax_add, | |
d77b99c9 | 7899 | int max_count) |
e0001a05 NC |
7900 | { |
7901 | fragS *fragP = NULL; | |
d77b99c9 | 7902 | int insn_count = 0; |
e0001a05 NC |
7903 | |
7904 | fragP = base_fragP; | |
7905 | ||
7906 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7907 | { | |
7908 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7909 | if (insn_count >= max_count) | |
7910 | return max_count; | |
7911 | ||
7912 | if (count_relax_add) | |
7913 | { | |
7914 | if (fragP->fr_type == rs_machine_dependent | |
7915 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7916 | { | |
7917 | /* In order to add the appropriate number of | |
7918 | NOPs, we count an instruction for downstream | |
7919 | occurrences. */ | |
7920 | insn_count++; | |
7921 | if (insn_count >= max_count) | |
7922 | return max_count; | |
7923 | } | |
7924 | } | |
7925 | } | |
7926 | return insn_count; | |
7927 | } | |
7928 | ||
7929 | ||
d77b99c9 | 7930 | static int |
7fa3d080 | 7931 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7932 | { |
43cd72b9 BW |
7933 | xtensa_isa isa = xtensa_default_isa; |
7934 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7935 | int insn_count = 0; |
e0001a05 NC |
7936 | int offset = 0; |
7937 | ||
7938 | if (!fragP->tc_frag_data.is_insn) | |
7939 | return insn_count; | |
7940 | ||
43cd72b9 BW |
7941 | if (!insnbuf) |
7942 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7943 | ||
e0001a05 NC |
7944 | /* Decode the fixed instructions. */ |
7945 | while (offset < fragP->fr_fix) | |
7946 | { | |
43cd72b9 BW |
7947 | xtensa_format fmt; |
7948 | ||
d77b99c9 BW |
7949 | xtensa_insnbuf_from_chars |
7950 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7951 | fmt = xtensa_format_decode (isa, insnbuf); |
7952 | ||
7953 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7954 | { |
7955 | as_fatal (_("undecodable instruction in instruction frag")); | |
7956 | return insn_count; | |
7957 | } | |
43cd72b9 | 7958 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7959 | insn_count++; |
7960 | } | |
7961 | ||
7962 | return insn_count; | |
7963 | } | |
7964 | ||
7965 | ||
7fa3d080 BW |
7966 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7967 | ||
43cd72b9 | 7968 | static bfd_boolean |
7fa3d080 | 7969 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7970 | { |
7971 | fragS *fragP; | |
7972 | ||
7973 | for (fragP = base_fragP; | |
7974 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7975 | fragP = fragP->fr_next) | |
7976 | { | |
7977 | if (unrelaxed_frag_has_b_j (fragP)) | |
7978 | return TRUE; | |
7979 | } | |
7980 | return FALSE; | |
7981 | } | |
7982 | ||
7983 | ||
43cd72b9 | 7984 | static bfd_boolean |
7fa3d080 | 7985 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7986 | { |
43cd72b9 BW |
7987 | static xtensa_insnbuf insnbuf = NULL; |
7988 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7989 | int offset = 0; |
7990 | ||
7991 | if (!fragP->tc_frag_data.is_insn) | |
7992 | return FALSE; | |
7993 | ||
43cd72b9 BW |
7994 | if (!insnbuf) |
7995 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7996 | ||
e0001a05 NC |
7997 | /* Decode the fixed instructions. */ |
7998 | while (offset < fragP->fr_fix) | |
7999 | { | |
43cd72b9 BW |
8000 | xtensa_format fmt; |
8001 | int slot; | |
8002 | ||
d77b99c9 BW |
8003 | xtensa_insnbuf_from_chars |
8004 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8005 | fmt = xtensa_format_decode (isa, insnbuf); |
8006 | if (fmt == XTENSA_UNDEFINED) | |
8007 | return FALSE; | |
8008 | ||
8009 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8010 | { |
43cd72b9 BW |
8011 | xtensa_opcode opcode = |
8012 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8013 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8014 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
8015 | return TRUE; | |
e0001a05 | 8016 | } |
43cd72b9 | 8017 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8018 | } |
8019 | return FALSE; | |
8020 | } | |
8021 | ||
8022 | ||
8023 | /* Checks to be made after initial assembly but before relaxation. */ | |
8024 | ||
7fa3d080 BW |
8025 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
8026 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
8027 | ||
e0001a05 | 8028 | static void |
7fa3d080 | 8029 | xtensa_sanity_check (void) |
e0001a05 NC |
8030 | { |
8031 | char *file_name; | |
d77b99c9 | 8032 | unsigned line; |
e0001a05 | 8033 | frchainS *frchP; |
c9049d30 | 8034 | asection *s; |
e0001a05 NC |
8035 | |
8036 | as_where (&file_name, &line); | |
c9049d30 AM |
8037 | for (s = stdoutput->sections; s; s = s->next) |
8038 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8039 | { | |
8040 | fragS *fragP; | |
e0001a05 | 8041 | |
c9049d30 AM |
8042 | /* Walk over all of the fragments in a subsection. */ |
8043 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8044 | { | |
c9049d30 | 8045 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
8046 | && fragP->fr_subtype == RELAX_SLOTS |
8047 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
8048 | { |
8049 | static xtensa_insnbuf insnbuf = NULL; | |
8050 | TInsn t_insn; | |
8051 | ||
8052 | if (fragP->fr_opcode != NULL) | |
8053 | { | |
8054 | if (!insnbuf) | |
8055 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8056 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8057 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8058 | ||
8059 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8060 | t_insn.opcode) == 1) | |
8061 | { | |
8062 | if (is_empty_loop (&t_insn, fragP)) | |
8063 | { | |
8064 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8065 | as_bad (_("invalid empty loop")); | |
8066 | } | |
8067 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8068 | { | |
8069 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8070 | as_bad (_("loop target does not follow " | |
8071 | "loop instruction in section")); | |
8072 | } | |
8073 | } | |
8074 | } | |
8075 | } | |
8076 | } | |
8077 | } | |
e0001a05 NC |
8078 | new_logical_line (file_name, line); |
8079 | } | |
8080 | ||
8081 | ||
8082 | #define LOOP_IMMED_OPN 1 | |
8083 | ||
43cd72b9 | 8084 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8085 | |
7fa3d080 BW |
8086 | static bfd_boolean |
8087 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8088 | { |
91d6fa6a | 8089 | const expressionS *exp; |
e0001a05 NC |
8090 | symbolS *symbolP; |
8091 | fragS *next_fragP; | |
8092 | ||
8093 | if (insn->insn_type != ITYPE_INSN) | |
8094 | return FALSE; | |
8095 | ||
43cd72b9 | 8096 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8097 | return FALSE; |
8098 | ||
8099 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8100 | return FALSE; | |
8101 | ||
91d6fa6a | 8102 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8103 | |
91d6fa6a | 8104 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8105 | return FALSE; |
8106 | ||
91d6fa6a | 8107 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8108 | if (!symbolP) |
8109 | return FALSE; | |
8110 | ||
8111 | if (symbol_get_frag (symbolP) == NULL) | |
8112 | return FALSE; | |
8113 | ||
8114 | if (S_GET_VALUE (symbolP) != 0) | |
8115 | return FALSE; | |
8116 | ||
8117 | /* Walk through the zero-size fragments from this one. If we find | |
8118 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8119 | |
e0001a05 NC |
8120 | for (next_fragP = fragP->fr_next; |
8121 | next_fragP != NULL; | |
8122 | next_fragP = next_fragP->fr_next) | |
8123 | { | |
8124 | if (next_fragP == symbol_get_frag (symbolP)) | |
8125 | return TRUE; | |
8126 | if (next_fragP->fr_fix != 0) | |
8127 | return FALSE; | |
8128 | } | |
8129 | return FALSE; | |
8130 | } | |
8131 | ||
8132 | ||
7fa3d080 BW |
8133 | static bfd_boolean |
8134 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8135 | { |
91d6fa6a | 8136 | const expressionS *exp; |
e0001a05 NC |
8137 | symbolS *symbolP; |
8138 | fragS *next_fragP; | |
8139 | ||
8140 | if (insn->insn_type != ITYPE_INSN) | |
8141 | return FALSE; | |
8142 | ||
64b607e6 | 8143 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8144 | return FALSE; |
8145 | ||
8146 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8147 | return FALSE; | |
8148 | ||
91d6fa6a | 8149 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8150 | |
91d6fa6a | 8151 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8152 | return FALSE; |
8153 | ||
91d6fa6a | 8154 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8155 | if (!symbolP) |
8156 | return FALSE; | |
8157 | ||
8158 | if (symbol_get_frag (symbolP) == NULL) | |
8159 | return FALSE; | |
8160 | ||
8161 | /* Walk through fragments until we find the target. | |
8162 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8163 | |
e0001a05 NC |
8164 | for (next_fragP = fragP->fr_next; |
8165 | next_fragP != NULL; | |
8166 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8167 | { |
8168 | if (next_fragP == symbol_get_frag (symbolP)) | |
8169 | return TRUE; | |
8170 | } | |
e0001a05 NC |
8171 | |
8172 | return FALSE; | |
8173 | } | |
8174 | ||
2caa7ca0 BW |
8175 | |
8176 | #define XTINFO_NAME "Xtensa_Info" | |
8177 | #define XTINFO_NAMESZ 12 | |
8178 | #define XTINFO_TYPE 1 | |
8179 | ||
8180 | static void | |
8181 | xtensa_add_config_info (void) | |
8182 | { | |
8183 | asection *info_sec; | |
8184 | char *data, *p; | |
8185 | int sz; | |
8186 | ||
8187 | info_sec = subseg_new (".xtensa.info", 0); | |
8188 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8189 | ||
8190 | data = xmalloc (100); | |
8191 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
8192 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8193 | sz = strlen (data) + 1; | |
8194 | ||
8195 | /* Add enough null terminators to pad to a word boundary. */ | |
8196 | do | |
8197 | data[sz++] = 0; | |
8198 | while ((sz & 3) != 0); | |
8199 | ||
8200 | /* Follow the standard note section layout: | |
8201 | First write the length of the name string. */ | |
8202 | p = frag_more (4); | |
8203 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8204 | ||
8205 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8206 | p = frag_more (4); | |
8207 | md_number_to_chars (p, (valueT) sz, 4); | |
8208 | ||
8209 | /* Write the note type. */ | |
8210 | p = frag_more (4); | |
8211 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8212 | ||
8213 | /* Write the name field. */ | |
8214 | p = frag_more (XTINFO_NAMESZ); | |
8215 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8216 | ||
8217 | /* Finally, write the descriptor. */ | |
8218 | p = frag_more (sz); | |
8219 | memcpy (p, data, sz); | |
8220 | ||
8221 | free (data); | |
8222 | } | |
8223 | ||
e0001a05 NC |
8224 | \f |
8225 | /* Alignment Functions. */ | |
8226 | ||
d77b99c9 BW |
8227 | static int |
8228 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8229 | { |
03aaa593 BW |
8230 | if (target_size <= 4) |
8231 | return 2; | |
9c2799c2 | 8232 | gas_assert (target_size == 8); |
03aaa593 | 8233 | return 3; |
e0001a05 NC |
8234 | } |
8235 | ||
8236 | ||
d77b99c9 | 8237 | static int |
7fa3d080 BW |
8238 | get_text_align_max_fill_size (int align_pow, |
8239 | bfd_boolean use_nops, | |
8240 | bfd_boolean use_no_density) | |
e0001a05 NC |
8241 | { |
8242 | if (!use_nops) | |
8243 | return (1 << align_pow); | |
8244 | if (use_no_density) | |
8245 | return 3 * (1 << align_pow); | |
8246 | ||
8247 | return 1 + (1 << align_pow); | |
8248 | } | |
8249 | ||
8250 | ||
d77b99c9 BW |
8251 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8252 | target instruction of size "target_size" so that it does not cross a | |
8253 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8254 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8255 | be filled by NOP instructions. */ | |
e0001a05 | 8256 | |
d77b99c9 | 8257 | static int |
7fa3d080 BW |
8258 | get_text_align_fill_size (addressT address, |
8259 | int align_pow, | |
8260 | int target_size, | |
8261 | bfd_boolean use_nops, | |
8262 | bfd_boolean use_no_density) | |
e0001a05 | 8263 | { |
d77b99c9 BW |
8264 | addressT alignment, fill, fill_limit, fill_step; |
8265 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8266 | |
d77b99c9 | 8267 | alignment = (1 << align_pow); |
9c2799c2 | 8268 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 8269 | |
e0001a05 NC |
8270 | if (!use_nops) |
8271 | { | |
d77b99c9 BW |
8272 | fill_limit = alignment; |
8273 | fill_step = 1; | |
e0001a05 | 8274 | } |
d77b99c9 | 8275 | else if (!use_no_density) |
e0001a05 | 8276 | { |
d77b99c9 BW |
8277 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8278 | fill_limit = alignment * 2; | |
8279 | fill_step = 1; | |
8280 | skip_one = TRUE; | |
e0001a05 NC |
8281 | } |
8282 | else | |
8283 | { | |
d77b99c9 BW |
8284 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8285 | fill_limit = alignment * 3; | |
8286 | fill_step = 3; | |
8287 | } | |
e0001a05 | 8288 | |
d77b99c9 BW |
8289 | /* Try all fill sizes until finding one that works. */ |
8290 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8291 | { | |
8292 | if (skip_one && fill == 1) | |
8293 | continue; | |
8294 | if ((address + fill) >> align_pow | |
8295 | == (address + fill + target_size - 1) >> align_pow) | |
8296 | return fill; | |
e0001a05 | 8297 | } |
9c2799c2 | 8298 | gas_assert (0); |
e0001a05 NC |
8299 | return 0; |
8300 | } | |
8301 | ||
8302 | ||
664df4e4 BW |
8303 | static int |
8304 | branch_align_power (segT sec) | |
8305 | { | |
8306 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8307 | is aligned to at least an 8-byte boundary, then a branch target need | |
8308 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8309 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8310 | (which may be insufficient, e.g., if the section has no alignment, but | |
8311 | it's good enough). */ | |
8312 | if (xtensa_fetch_width == 8) | |
8313 | { | |
8314 | if (get_recorded_alignment (sec) >= 3) | |
8315 | return 3; | |
8316 | } | |
8317 | else | |
9c2799c2 | 8318 | gas_assert (xtensa_fetch_width == 4); |
664df4e4 BW |
8319 | |
8320 | return 2; | |
8321 | } | |
8322 | ||
8323 | ||
e0001a05 NC |
8324 | /* This will assert if it is not possible. */ |
8325 | ||
d77b99c9 BW |
8326 | static int |
8327 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8328 | { |
d77b99c9 BW |
8329 | int count = 0; |
8330 | ||
e0001a05 NC |
8331 | if (use_no_density) |
8332 | { | |
9c2799c2 | 8333 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
8334 | return (fill_size / 3); |
8335 | } | |
8336 | ||
9c2799c2 | 8337 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
8338 | |
8339 | while (fill_size > 1) | |
8340 | { | |
d77b99c9 | 8341 | int insn_size = 3; |
e0001a05 NC |
8342 | if (fill_size == 2 || fill_size == 4) |
8343 | insn_size = 2; | |
8344 | fill_size -= insn_size; | |
8345 | count++; | |
8346 | } | |
9c2799c2 | 8347 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
8348 | return count; |
8349 | } | |
8350 | ||
8351 | ||
d77b99c9 BW |
8352 | static int |
8353 | get_text_align_nth_nop_size (offsetT fill_size, | |
8354 | int n, | |
7fa3d080 | 8355 | bfd_boolean use_no_density) |
e0001a05 | 8356 | { |
d77b99c9 | 8357 | int count = 0; |
e0001a05 NC |
8358 | |
8359 | if (use_no_density) | |
8360 | return 3; | |
8361 | ||
9c2799c2 | 8362 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 8363 | |
e0001a05 NC |
8364 | while (fill_size > 1) |
8365 | { | |
d77b99c9 | 8366 | int insn_size = 3; |
e0001a05 NC |
8367 | if (fill_size == 2 || fill_size == 4) |
8368 | insn_size = 2; | |
8369 | fill_size -= insn_size; | |
8370 | count++; | |
8371 | if (n + 1 == count) | |
8372 | return insn_size; | |
8373 | } | |
9c2799c2 | 8374 | gas_assert (0); |
e0001a05 NC |
8375 | return 0; |
8376 | } | |
8377 | ||
8378 | ||
8379 | /* For the given fragment, find the appropriate address | |
8380 | for it to begin at if we are using NOPs to align it. */ | |
8381 | ||
8382 | static addressT | |
7fa3d080 | 8383 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8384 | { |
43cd72b9 BW |
8385 | /* The rule is: get next fragment's FIRST instruction. Find |
8386 | the smallest number of bytes that need to be added to | |
8387 | ensure that the next fragment's FIRST instruction will fit | |
8388 | in a single word. | |
c138bc38 | 8389 | |
43cd72b9 BW |
8390 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8391 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8392 | |
43cd72b9 BW |
8393 | If the FIRST instruction MIGHT be relaxed, |
8394 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8395 | |
43cd72b9 BW |
8396 | Note again here that LOOP instructions are not bundleable, |
8397 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8398 | |
d77b99c9 | 8399 | int fill_size = 0; |
43cd72b9 BW |
8400 | int first_insn_size; |
8401 | int loop_insn_size; | |
8402 | addressT pre_opcode_bytes; | |
d77b99c9 | 8403 | int align_power; |
43cd72b9 BW |
8404 | fragS *first_insn; |
8405 | xtensa_opcode opcode; | |
8406 | bfd_boolean is_loop; | |
e0001a05 | 8407 | |
9c2799c2 NC |
8408 | gas_assert (fragP->fr_type == rs_machine_dependent); |
8409 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8410 | |
43cd72b9 BW |
8411 | /* Find the loop frag. */ |
8412 | first_insn = next_non_empty_frag (fragP); | |
8413 | /* Now find the first insn frag. */ | |
8414 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8415 | |
43cd72b9 | 8416 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 8417 | gas_assert (is_loop); |
43cd72b9 | 8418 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 8419 | |
43cd72b9 BW |
8420 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8421 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8422 | |
43cd72b9 BW |
8423 | /* For loops, the alignment depends on the size of the |
8424 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8425 | |
43cd72b9 | 8426 | if (first_insn == NULL) |
03aaa593 BW |
8427 | first_insn_size = xtensa_fetch_width; |
8428 | else | |
8429 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8430 | |
43cd72b9 | 8431 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8432 | align_power = get_text_align_power (first_insn_size); |
8433 | record_alignment (now_seg, align_power); | |
c138bc38 | 8434 | |
43cd72b9 | 8435 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8436 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8437 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8438 | |
8439 | return address + fill_size; | |
8440 | } | |
8441 | ||
8442 | ||
43cd72b9 BW |
8443 | /* 3 mechanisms for relaxing an alignment: |
8444 | ||
8445 | Align to a power of 2. | |
8446 | Align so the next fragment's instruction does not cross a word boundary. | |
8447 | Align the current instruction so that if the next instruction | |
8448 | were 3 bytes, it would not cross a word boundary. | |
8449 | ||
e0001a05 NC |
8450 | We can align with: |
8451 | ||
43cd72b9 BW |
8452 | zeros - This is easy; always insert zeros. |
8453 | nops - 3-byte and 2-byte instructions | |
8454 | 2 - 2-byte nop | |
8455 | 3 - 3-byte nop | |
8456 | 4 - 2 2-byte nops | |
8457 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8458 | widening - widen previous instructions. */ |
8459 | ||
d77b99c9 BW |
8460 | static offsetT |
8461 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8462 | { |
43cd72b9 BW |
8463 | addressT target_address, loop_insn_offset; |
8464 | int target_size; | |
8465 | xtensa_opcode loop_opcode; | |
8466 | bfd_boolean is_loop; | |
d77b99c9 BW |
8467 | int align_power; |
8468 | offsetT opt_diff; | |
5f9084e9 | 8469 | offsetT branch_align; |
def13efb | 8470 | fragS *loop_frag; |
e0001a05 | 8471 | |
9c2799c2 | 8472 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 8473 | switch (fragP->fr_subtype) |
e0001a05 | 8474 | { |
43cd72b9 BW |
8475 | case RELAX_DESIRE_ALIGN: |
8476 | target_size = next_frag_format_size (fragP); | |
8477 | if (target_size == XTENSA_UNDEFINED) | |
8478 | target_size = 3; | |
664df4e4 BW |
8479 | align_power = branch_align_power (now_seg); |
8480 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8481 | /* Don't count on the section alignment being as large as the target. */ |
8482 | if (target_size > branch_align) | |
8483 | target_size = branch_align; | |
d77b99c9 | 8484 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8485 | target_size, FALSE, FALSE); |
8486 | ||
664df4e4 BW |
8487 | *max_diff = (opt_diff + branch_align |
8488 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 8489 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 8490 | return opt_diff; |
e0001a05 | 8491 | |
43cd72b9 | 8492 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
8493 | /* The next non-empty frag after this one holds the LOOP instruction |
8494 | that needs to be aligned. The required alignment depends on the | |
8495 | size of the next non-empty frag after the loop frag, i.e., the | |
8496 | first instruction in the loop. */ | |
8497 | loop_frag = next_non_empty_frag (fragP); | |
8498 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
8499 | loop_insn_offset = 0; |
8500 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 8501 | gas_assert (is_loop); |
43cd72b9 BW |
8502 | |
8503 | /* If the loop has been expanded then the LOOP instruction | |
8504 | could be at an offset from this fragment. */ | |
def13efb | 8505 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
8506 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
8507 | ||
43cd72b9 BW |
8508 | /* In an ideal world, which is what we are shooting for here, |
8509 | we wouldn't need to use any NOPs immediately prior to the | |
8510 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8511 | will call get_noop_aligned_address. */ | |
8512 | target_address = | |
8513 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 8514 | align_power = get_text_align_power (target_size); |
d77b99c9 | 8515 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
8516 | target_size, FALSE, FALSE); |
8517 | ||
8518 | *max_diff = xtensa_fetch_width | |
8519 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8520 | - target_size + opt_diff; | |
9c2799c2 | 8521 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 8522 | return opt_diff; |
e0001a05 | 8523 | |
43cd72b9 BW |
8524 | default: |
8525 | break; | |
e0001a05 | 8526 | } |
9c2799c2 | 8527 | gas_assert (0); |
43cd72b9 | 8528 | return 0; |
e0001a05 NC |
8529 | } |
8530 | ||
8531 | \f | |
8532 | /* md_relax_frag Hook and Helper Functions. */ | |
8533 | ||
7fa3d080 BW |
8534 | static long relax_frag_loop_align (fragS *, long); |
8535 | static long relax_frag_for_align (fragS *, long); | |
8536 | static long relax_frag_immed | |
8537 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8538 | ||
8539 | ||
e0001a05 NC |
8540 | /* Return the number of bytes added to this fragment, given that the |
8541 | input has been stretched already by "stretch". */ | |
8542 | ||
8543 | long | |
7fa3d080 | 8544 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8545 | { |
43cd72b9 | 8546 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8547 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8548 | long new_stretch = 0; | |
8549 | char *file_name; | |
d77b99c9 BW |
8550 | unsigned line; |
8551 | int lit_size; | |
43cd72b9 BW |
8552 | static xtensa_insnbuf vbuf = NULL; |
8553 | int slot, num_slots; | |
8554 | xtensa_format fmt; | |
e0001a05 NC |
8555 | |
8556 | as_where (&file_name, &line); | |
8557 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8558 | ||
8559 | fragP->tc_frag_data.unreported_expansion = 0; | |
8560 | ||
8561 | switch (fragP->fr_subtype) | |
8562 | { | |
8563 | case RELAX_ALIGN_NEXT_OPCODE: | |
8564 | /* Always convert. */ | |
43cd72b9 BW |
8565 | if (fragP->tc_frag_data.relax_seen) |
8566 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8567 | break; |
8568 | ||
8569 | case RELAX_LOOP_END: | |
8570 | /* Do nothing. */ | |
8571 | break; | |
8572 | ||
8573 | case RELAX_LOOP_END_ADD_NOP: | |
8574 | /* Add a NOP and switch to .fill 0. */ | |
8575 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8576 | frag_wane (fragP); |
e0001a05 NC |
8577 | break; |
8578 | ||
8579 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8580 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8581 | it or not. */ |
8582 | break; | |
8583 | ||
8584 | case RELAX_LITERAL: | |
8585 | case RELAX_LITERAL_FINAL: | |
8586 | return 0; | |
8587 | ||
8588 | case RELAX_LITERAL_NR: | |
8589 | lit_size = 4; | |
8590 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 8591 | gas_assert (unreported == lit_size); |
e0001a05 NC |
8592 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
8593 | fragP->fr_var -= lit_size; | |
8594 | fragP->fr_fix += lit_size; | |
8595 | new_stretch = 4; | |
8596 | break; | |
8597 | ||
43cd72b9 BW |
8598 | case RELAX_SLOTS: |
8599 | if (vbuf == NULL) | |
8600 | vbuf = xtensa_insnbuf_alloc (isa); | |
8601 | ||
d77b99c9 BW |
8602 | xtensa_insnbuf_from_chars |
8603 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8604 | fmt = xtensa_format_decode (isa, vbuf); |
8605 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8606 | |
43cd72b9 BW |
8607 | for (slot = 0; slot < num_slots; slot++) |
8608 | { | |
8609 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8610 | { | |
8611 | case RELAX_NARROW: | |
8612 | if (fragP->tc_frag_data.relax_seen) | |
8613 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8614 | break; | |
8615 | ||
8616 | case RELAX_IMMED: | |
8617 | case RELAX_IMMED_STEP1: | |
8618 | case RELAX_IMMED_STEP2: | |
b81bf389 | 8619 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
8620 | /* Place the immediate. */ |
8621 | new_stretch += relax_frag_immed | |
8622 | (now_seg, fragP, stretch, | |
8623 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8624 | fmt, slot, stretched_p, FALSE); | |
8625 | break; | |
8626 | ||
8627 | default: | |
8628 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8629 | break; | |
8630 | } | |
8631 | } | |
e0001a05 NC |
8632 | break; |
8633 | ||
8634 | case RELAX_LITERAL_POOL_BEGIN: | |
8635 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8636 | case RELAX_MAYBE_UNREACHABLE: |
8637 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8638 | /* No relaxation required. */ |
8639 | break; | |
8640 | ||
43cd72b9 BW |
8641 | case RELAX_FILL_NOP: |
8642 | case RELAX_UNREACHABLE: | |
8643 | if (fragP->tc_frag_data.relax_seen) | |
8644 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8645 | break; | |
8646 | ||
e0001a05 NC |
8647 | default: |
8648 | as_bad (_("bad relaxation state")); | |
8649 | } | |
8650 | ||
43cd72b9 | 8651 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8652 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8653 | { |
8654 | fragP->tc_frag_data.relax_seen = TRUE; | |
8655 | *stretched_p = 1; | |
8656 | } | |
8657 | ||
e0001a05 NC |
8658 | new_logical_line (file_name, line); |
8659 | return new_stretch; | |
8660 | } | |
8661 | ||
8662 | ||
8663 | static long | |
7fa3d080 | 8664 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8665 | { |
8666 | addressT old_address, old_next_address, old_size; | |
8667 | addressT new_address, new_next_address, new_size; | |
8668 | addressT growth; | |
8669 | ||
43cd72b9 BW |
8670 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8671 | section have been done, hopefully eliminating the need for a NOP here. | |
8672 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8673 | |
8674 | /* Calculate the old address of this fragment and the next fragment. */ | |
8675 | old_address = fragP->fr_address - stretch; | |
8676 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8677 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8678 | old_size = old_next_address - old_address; |
8679 | ||
8680 | /* Calculate the new address of this fragment and the next fragment. */ | |
8681 | new_address = fragP->fr_address; | |
8682 | new_next_address = | |
8683 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8684 | new_size = new_next_address - new_address; | |
8685 | ||
8686 | growth = new_size - old_size; | |
8687 | ||
8688 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8689 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8690 | return growth; |
8691 | } | |
8692 | ||
8693 | ||
43cd72b9 | 8694 | /* Add a NOP instruction. */ |
e0001a05 NC |
8695 | |
8696 | static long | |
7fa3d080 | 8697 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8698 | { |
e0001a05 | 8699 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8700 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8701 | assemble_nop (length, nop_buf); | |
e0001a05 | 8702 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8703 | |
e0001a05 NC |
8704 | if (fragP->fr_var < length) |
8705 | { | |
dd49a749 | 8706 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8707 | return 0; |
8708 | } | |
8709 | ||
8710 | fragP->fr_fix += length; | |
8711 | fragP->fr_var -= length; | |
e0001a05 NC |
8712 | return length; |
8713 | } | |
8714 | ||
8715 | ||
7fa3d080 BW |
8716 | static long future_alignment_required (fragS *, long); |
8717 | ||
e0001a05 | 8718 | static long |
7fa3d080 | 8719 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8720 | { |
43cd72b9 BW |
8721 | /* Overview of the relaxation procedure for alignment: |
8722 | We can widen with NOPs or by widening instructions or by filling | |
8723 | bytes after jump instructions. Find the opportune places and widen | |
8724 | them if necessary. */ | |
8725 | ||
8726 | long stretch_me; | |
8727 | long diff; | |
e0001a05 | 8728 | |
9c2799c2 | 8729 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
8730 | || fragP->fr_subtype == RELAX_UNREACHABLE |
8731 | || (fragP->fr_subtype == RELAX_SLOTS | |
8732 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8733 | ||
8734 | stretch_me = future_alignment_required (fragP, stretch); | |
8735 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8736 | if (diff == 0) | |
8737 | return 0; | |
e0001a05 | 8738 | |
43cd72b9 | 8739 | if (diff < 0) |
e0001a05 | 8740 | { |
43cd72b9 BW |
8741 | /* We expanded on a previous pass. Can we shrink now? */ |
8742 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8743 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8744 | { |
43cd72b9 BW |
8745 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8746 | return -shrink; | |
e0001a05 NC |
8747 | } |
8748 | return 0; | |
8749 | } | |
8750 | ||
43cd72b9 BW |
8751 | /* Below here, diff > 0. */ |
8752 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8753 | |
43cd72b9 | 8754 | return diff; |
e0001a05 NC |
8755 | } |
8756 | ||
8757 | ||
43cd72b9 BW |
8758 | /* Return the address of the next frag that should be aligned. |
8759 | ||
8760 | By "address" we mean the address it _would_ be at if there | |
8761 | is no action taken to align it between here and the target frag. | |
8762 | In other words, if no narrows and no fill nops are used between | |
8763 | here and the frag to align, _even_if_ some of the frags we use | |
8764 | to align targets have already expanded on a previous relaxation | |
8765 | pass. | |
8766 | ||
8767 | Also, count each frag that may be used to help align the target. | |
8768 | ||
8769 | Return 0 if there are no frags left in the chain that need to be | |
8770 | aligned. */ | |
8771 | ||
8772 | static addressT | |
7fa3d080 BW |
8773 | find_address_of_next_align_frag (fragS **fragPP, |
8774 | int *wide_nops, | |
8775 | int *narrow_nops, | |
8776 | int *widens, | |
8777 | bfd_boolean *paddable) | |
e0001a05 | 8778 | { |
43cd72b9 BW |
8779 | fragS *fragP = *fragPP; |
8780 | addressT address = fragP->fr_address; | |
8781 | ||
8782 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8783 | |
8784 | while (fragP) | |
8785 | { | |
8786 | /* Limit this to a small search. */ | |
b5e4a23d | 8787 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8788 | { |
8789 | *fragPP = fragP; | |
8790 | return 0; | |
8791 | } | |
e0001a05 NC |
8792 | address += fragP->fr_fix; |
8793 | ||
43cd72b9 BW |
8794 | if (fragP->fr_type == rs_fill) |
8795 | address += fragP->fr_offset * fragP->fr_var; | |
8796 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8797 | { |
e0001a05 NC |
8798 | switch (fragP->fr_subtype) |
8799 | { | |
43cd72b9 BW |
8800 | case RELAX_UNREACHABLE: |
8801 | *paddable = TRUE; | |
8802 | break; | |
8803 | ||
8804 | case RELAX_FILL_NOP: | |
8805 | (*wide_nops)++; | |
8806 | if (!fragP->tc_frag_data.is_no_density) | |
8807 | (*narrow_nops)++; | |
8808 | break; | |
8809 | ||
8810 | case RELAX_SLOTS: | |
8811 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8812 | { | |
8813 | (*widens)++; | |
8814 | break; | |
8815 | } | |
34e41783 | 8816 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8817 | break; |
8818 | ||
8819 | case RELAX_IMMED: | |
43cd72b9 | 8820 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8821 | break; |
8822 | ||
8823 | case RELAX_ALIGN_NEXT_OPCODE: | |
8824 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8825 | *fragPP = fragP; |
8826 | return address; | |
8827 | ||
8828 | case RELAX_MAYBE_UNREACHABLE: | |
8829 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8830 | /* Do nothing. */ | |
e0001a05 NC |
8831 | break; |
8832 | ||
8833 | default: | |
43cd72b9 BW |
8834 | /* Just punt if we don't know the type. */ |
8835 | *fragPP = fragP; | |
8836 | return 0; | |
e0001a05 | 8837 | } |
43cd72b9 | 8838 | } |
c138bc38 | 8839 | else |
43cd72b9 BW |
8840 | { |
8841 | /* Just punt if we don't know the type. */ | |
8842 | *fragPP = fragP; | |
8843 | return 0; | |
8844 | } | |
8845 | fragP = fragP->fr_next; | |
8846 | } | |
8847 | ||
8848 | *fragPP = fragP; | |
8849 | return 0; | |
8850 | } | |
8851 | ||
8852 | ||
7fa3d080 BW |
8853 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8854 | ||
43cd72b9 | 8855 | static long |
7fa3d080 | 8856 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8857 | { |
8858 | fragS *this_frag = fragP; | |
8859 | long address; | |
8860 | int num_widens = 0; | |
8861 | int wide_nops = 0; | |
8862 | int narrow_nops = 0; | |
8863 | bfd_boolean paddable = FALSE; | |
8864 | offsetT local_opt_diff; | |
8865 | offsetT opt_diff; | |
8866 | offsetT max_diff; | |
8867 | int stretch_amount = 0; | |
8868 | int local_stretch_amount; | |
8869 | int global_stretch_amount; | |
8870 | ||
7fa3d080 BW |
8871 | address = find_address_of_next_align_frag |
8872 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8873 | |
b5e4a23d BW |
8874 | if (!address) |
8875 | { | |
8876 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8877 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8878 | else | |
8879 | frag_wane (this_frag); | |
8880 | } | |
8881 | else | |
43cd72b9 BW |
8882 | { |
8883 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8884 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
8885 | gas_assert (opt_diff >= 0); |
8886 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 8887 | if (max_diff == 0) |
43cd72b9 | 8888 | return 0; |
d2a033cd | 8889 | |
43cd72b9 BW |
8890 | if (fragP) |
8891 | fragP = fragP->fr_next; | |
8892 | ||
8893 | while (fragP && opt_diff < max_diff && address) | |
8894 | { | |
8895 | /* We only use these to determine if we can exit early | |
c138bc38 | 8896 | because there will be plenty of ways to align future |
43cd72b9 | 8897 | align frags. */ |
d77b99c9 | 8898 | int glob_widens = 0; |
43cd72b9 BW |
8899 | int dnn = 0; |
8900 | int dw = 0; | |
8901 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8902 | address = find_address_of_next_align_frag |
8903 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8904 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8905 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8906 | address = 0; |
43cd72b9 | 8907 | |
c138bc38 | 8908 | if (address) |
43cd72b9 BW |
8909 | { |
8910 | offsetT next_m_diff; | |
8911 | offsetT next_o_diff; | |
8912 | ||
8913 | /* Downrange frags haven't had stretch added to them yet. */ | |
8914 | address += stretch; | |
8915 | ||
8916 | /* The address also includes any text expansion from this | |
8917 | frag in a previous pass, but we don't want that. */ | |
8918 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8919 | ||
8920 | /* Assume we are going to move at least opt_diff. In | |
8921 | reality, we might not be able to, but assuming that | |
8922 | we will helps catch cases where moving opt_diff pushes | |
8923 | the next target from aligned to unaligned. */ | |
8924 | address += opt_diff; | |
8925 | ||
8926 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8927 | ||
8928 | /* Now cleanup for the adjustments to address. */ | |
8929 | next_o_diff += opt_diff; | |
8930 | next_m_diff += opt_diff; | |
8931 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8932 | opt_diff = next_o_diff; | |
8933 | if (next_m_diff < max_diff) | |
8934 | max_diff = next_m_diff; | |
8935 | fragP = fragP->fr_next; | |
8936 | } | |
8937 | } | |
d2a033cd | 8938 | |
43cd72b9 BW |
8939 | /* If there are enough wideners in between, do it. */ |
8940 | if (paddable) | |
8941 | { | |
8942 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8943 | { | |
9c2799c2 | 8944 | gas_assert (opt_diff <= UNREACHABLE_MAX_WIDTH); |
43cd72b9 BW |
8945 | return opt_diff; |
8946 | } | |
8947 | return 0; | |
8948 | } | |
c138bc38 | 8949 | local_stretch_amount |
43cd72b9 BW |
8950 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8951 | num_widens, local_opt_diff); | |
c138bc38 BW |
8952 | global_stretch_amount |
8953 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8954 | num_widens, opt_diff); |
c138bc38 BW |
8955 | /* If the condition below is true, then the frag couldn't |
8956 | stretch the correct amount for the global case, so we just | |
8957 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8958 | the correct alignment in the global case. */ |
8959 | if (global_stretch_amount < local_stretch_amount) | |
8960 | stretch_amount = local_stretch_amount; | |
8961 | else | |
8962 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8963 | |
43cd72b9 BW |
8964 | if (this_frag->fr_subtype == RELAX_SLOTS |
8965 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 8966 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
8967 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
8968 | { | |
8969 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 8970 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 8971 | else |
9c2799c2 | 8972 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
8973 | } |
8974 | } | |
8975 | return stretch_amount; | |
8976 | } | |
8977 | ||
8978 | ||
8979 | /* The idea: widen everything you can to get a target or loop aligned, | |
8980 | then start using NOPs. | |
8981 | ||
8982 | When we must have a NOP, here is a table of how we decide | |
8983 | (so you don't have to fight through the control flow below): | |
8984 | ||
8985 | wide_nops = the number of wide NOPs available for aligning | |
8986 | narrow_nops = the number of narrow NOPs available for aligning | |
8987 | (a subset of wide_nops) | |
8988 | widens = the number of narrow instructions that should be widened | |
8989 | ||
8990 | Desired wide narrow | |
8991 | Diff nop nop widens | |
8992 | 1 0 0 1 | |
8993 | 2 0 1 0 | |
8994 | 3a 1 0 0 | |
8995 | b 0 1 1 (case 3a makes this case unnecessary) | |
8996 | 4a 1 0 1 | |
8997 | b 0 2 0 | |
8998 | c 0 1 2 (case 4a makes this case unnecessary) | |
8999 | 5a 1 0 2 | |
9000 | b 1 1 0 | |
9001 | c 0 2 1 (case 5b makes this case unnecessary) | |
9002 | 6a 2 0 0 | |
9003 | b 1 0 3 | |
708587a4 | 9004 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
9005 | d 1 1 1 (case 6a makes this case unnecessary) |
9006 | e 0 2 2 (case 6a makes this case unnecessary) | |
9007 | f 0 3 0 (case 6a makes this case unnecessary) | |
9008 | 7a 1 0 4 | |
9009 | b 2 0 1 | |
9010 | c 1 1 2 (case 7b makes this case unnecessary) | |
9011 | d 0 1 5 (case 7a makes this case unnecessary) | |
9012 | e 0 2 3 (case 7b makes this case unnecessary) | |
9013 | f 0 3 1 (case 7b makes this case unnecessary) | |
9014 | g 1 2 1 (case 7b makes this case unnecessary) | |
9015 | */ | |
9016 | ||
9017 | static long | |
7fa3d080 BW |
9018 | bytes_to_stretch (fragS *this_frag, |
9019 | int wide_nops, | |
9020 | int narrow_nops, | |
9021 | int num_widens, | |
9022 | int desired_diff) | |
43cd72b9 BW |
9023 | { |
9024 | int bytes_short = desired_diff - num_widens; | |
9025 | ||
9c2799c2 | 9026 | gas_assert (desired_diff >= 0 && desired_diff < 8); |
43cd72b9 BW |
9027 | if (desired_diff == 0) |
9028 | return 0; | |
c138bc38 | 9029 | |
9c2799c2 | 9030 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 9031 | |
43cd72b9 BW |
9032 | /* Always prefer widening to NOP-filling. */ |
9033 | if (bytes_short < 0) | |
9034 | { | |
9035 | /* There are enough RELAX_NARROW frags after this one | |
9036 | to align the target without widening this frag in any way. */ | |
9037 | return 0; | |
9038 | } | |
c138bc38 | 9039 | |
43cd72b9 BW |
9040 | if (bytes_short == 0) |
9041 | { | |
9042 | /* Widen every narrow between here and the align target | |
9043 | and the align target will be properly aligned. */ | |
9044 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9045 | return 0; | |
9046 | else | |
9047 | return 1; | |
9048 | } | |
c138bc38 | 9049 | |
43cd72b9 BW |
9050 | /* From here we will need at least one NOP to get an alignment. |
9051 | However, we may not be able to align at all, in which case, | |
9052 | don't widen. */ | |
9053 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9054 | { | |
9055 | switch (desired_diff) | |
9056 | { | |
9057 | case 1: | |
9058 | return 0; | |
9059 | case 2: | |
9060 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
9061 | return 2; /* case 2 */ | |
9062 | return 0; | |
c138bc38 | 9063 | case 3: |
43cd72b9 BW |
9064 | if (wide_nops > 1) |
9065 | return 0; | |
9066 | else | |
9067 | return 3; /* case 3a */ | |
9068 | case 4: | |
9069 | if (num_widens >= 1 && wide_nops == 1) | |
9070 | return 3; /* case 4a */ | |
9071 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
9072 | return 2; /* case 4b */ | |
9073 | return 0; | |
9074 | case 5: | |
9075 | if (num_widens >= 2 && wide_nops == 1) | |
9076 | return 3; /* case 5a */ | |
c138bc38 | 9077 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
9078 | between here and the align target? */ |
9079 | if (wide_nops < 2 || narrow_nops == 0) | |
9080 | return 0; | |
9081 | /* Are there other nops closer that can serve instead? */ | |
9082 | if (wide_nops > 2 && narrow_nops > 1) | |
9083 | return 0; | |
9084 | /* Take the density one first, because there might not be | |
9085 | another density one available. */ | |
9086 | if (!this_frag->tc_frag_data.is_no_density) | |
9087 | return 2; /* case 5b narrow */ | |
9088 | else | |
9089 | return 3; /* case 5b wide */ | |
9090 | return 0; | |
9091 | case 6: | |
9092 | if (wide_nops == 2) | |
9093 | return 3; /* case 6a */ | |
9094 | else if (num_widens >= 3 && wide_nops == 1) | |
9095 | return 3; /* case 6b */ | |
9096 | return 0; | |
9097 | case 7: | |
9098 | if (wide_nops == 1 && num_widens >= 4) | |
9099 | return 3; /* case 7a */ | |
9100 | else if (wide_nops == 2 && num_widens >= 1) | |
9101 | return 3; /* case 7b */ | |
9102 | return 0; | |
e0001a05 | 9103 | default: |
9c2799c2 | 9104 | gas_assert (0); |
e0001a05 | 9105 | } |
e0001a05 | 9106 | } |
43cd72b9 BW |
9107 | else |
9108 | { | |
c138bc38 | 9109 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 9110 | this instruction to help? |
e0001a05 | 9111 | |
03aaa593 | 9112 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
9113 | switch (desired_diff) |
9114 | { | |
9115 | case 1: | |
9c2799c2 | 9116 | gas_assert (0); |
43cd72b9 BW |
9117 | return 0; |
9118 | case 2: | |
9119 | case 3: | |
9120 | return 0; | |
9121 | case 4: | |
9122 | if (wide_nops >= 1 && num_widens == 1) | |
9123 | return 1; /* case 4a */ | |
9124 | return 0; | |
9125 | case 5: | |
9126 | if (wide_nops >= 1 && num_widens == 2) | |
9127 | return 1; /* case 5a */ | |
9128 | return 0; | |
9129 | case 6: | |
9130 | if (wide_nops >= 2) | |
9131 | return 0; /* case 6a */ | |
9132 | else if (wide_nops >= 1 && num_widens == 3) | |
9133 | return 1; /* case 6b */ | |
9134 | return 0; | |
9135 | case 7: | |
9136 | if (wide_nops >= 1 && num_widens == 4) | |
9137 | return 1; /* case 7a */ | |
9138 | else if (wide_nops >= 2 && num_widens == 1) | |
9139 | return 1; /* case 7b */ | |
9140 | return 0; | |
9141 | default: | |
9c2799c2 | 9142 | gas_assert (0); |
43cd72b9 BW |
9143 | return 0; |
9144 | } | |
9145 | } | |
9c2799c2 | 9146 | gas_assert (0); |
43cd72b9 | 9147 | return 0; |
e0001a05 NC |
9148 | } |
9149 | ||
9150 | ||
9151 | static long | |
7fa3d080 BW |
9152 | relax_frag_immed (segT segP, |
9153 | fragS *fragP, | |
9154 | long stretch, | |
9155 | int min_steps, | |
9156 | xtensa_format fmt, | |
9157 | int slot, | |
9158 | int *stretched_p, | |
9159 | bfd_boolean estimate_only) | |
e0001a05 | 9160 | { |
43cd72b9 | 9161 | TInsn tinsn; |
e0001a05 NC |
9162 | int old_size; |
9163 | bfd_boolean negatable_branch = FALSE; | |
9164 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 9165 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 9166 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9167 | IStack istack; |
9168 | offsetT frag_offset; | |
9169 | int num_steps; | |
e0001a05 | 9170 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 9171 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 9172 | |
9c2799c2 | 9173 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 9174 | |
b5e4a23d BW |
9175 | xg_clear_vinsn (&cur_vinsn); |
9176 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 9177 | if (cur_vinsn.num_slots > 1) |
def13efb | 9178 | from_wide_insn = TRUE; |
43cd72b9 | 9179 | |
b5e4a23d | 9180 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 9181 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 9182 | |
64b607e6 | 9183 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 9184 | return 0; |
e0001a05 | 9185 | |
b08b5071 | 9186 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9187 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 9188 | |
43cd72b9 | 9189 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 9190 | |
43cd72b9 | 9191 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9192 | |
9193 | /* Special case: replace a branch to the next instruction with a NOP. | |
9194 | This is required to work around a hardware bug in T1040.0 and also | |
9195 | serves as an optimization. */ | |
9196 | ||
9197 | if (branch_jmp_to_next | |
9198 | && ((old_size == 2) || (old_size == 3)) | |
9199 | && !next_frag_is_loop_target (fragP)) | |
9200 | return 0; | |
9201 | ||
9202 | /* Here is the fun stuff: Get the immediate field from this | |
9203 | instruction. If it fits, we are done. If not, find the next | |
9204 | instruction sequence that fits. */ | |
9205 | ||
9206 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9207 | istack_init (&istack); | |
43cd72b9 | 9208 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 9209 | min_steps, stretch); |
9c2799c2 | 9210 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 9211 | |
43cd72b9 | 9212 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
9213 | |
9214 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 9215 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
9216 | literal_diff |
9217 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 9218 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
9219 | |
9220 | if (from_wide_insn) | |
43cd72b9 | 9221 | { |
2276bc20 BW |
9222 | int first = 0; |
9223 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
9224 | first++; | |
9225 | ||
43cd72b9 BW |
9226 | num_text_bytes += old_size; |
9227 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
9228 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
9229 | else |
9230 | { | |
9231 | /* The first instruction in the relaxed sequence will go after | |
9232 | the current wide instruction, and thus its symbolic immediates | |
9233 | might not fit. */ | |
9234 | ||
9235 | istack_init (&istack); | |
9236 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, | |
9237 | frag_offset + old_size, | |
9238 | min_steps, stretch + old_size); | |
9c2799c2 | 9239 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 BW |
9240 | |
9241 | fragP->tc_frag_data.slot_subtypes[slot] | |
9242 | = (int) RELAX_IMMED + num_steps; | |
9243 | ||
9244 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
9245 | literal_diff | |
9246 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
9247 | ||
9248 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; | |
9249 | } | |
43cd72b9 | 9250 | } |
def13efb | 9251 | |
43cd72b9 BW |
9252 | total_text_diff = num_text_bytes - old_size; |
9253 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
9254 | |
9255 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
9256 | gas_assert (num_text_bytes >= 0); |
9257 | gas_assert (literal_diff >= 0); | |
9258 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 9259 | |
43cd72b9 BW |
9260 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
9261 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
9262 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
9263 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
9264 | |
9265 | /* Find the associated expandable literal for this. */ | |
9266 | if (literal_diff != 0) | |
9267 | { | |
2276bc20 | 9268 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9269 | if (lit_fragP) |
9270 | { | |
9c2799c2 | 9271 | gas_assert (literal_diff == 4); |
e0001a05 NC |
9272 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
9273 | ||
9274 | /* We expect that the literal section state has NOT been | |
9275 | modified yet. */ | |
9c2799c2 | 9276 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
9277 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
9278 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
9279 | ||
9280 | /* We need to mark this section for another iteration | |
9281 | of relaxation. */ | |
9282 | (*stretched_p)++; | |
9283 | } | |
9284 | } | |
9285 | ||
43cd72b9 | 9286 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 9287 | update_next_frag_state (fragP); |
e0001a05 | 9288 | |
43cd72b9 | 9289 | return this_text_diff; |
e0001a05 NC |
9290 | } |
9291 | ||
9292 | \f | |
9293 | /* md_convert_frag Hook and Helper Functions. */ | |
9294 | ||
7fa3d080 BW |
9295 | static void convert_frag_align_next_opcode (fragS *); |
9296 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
9297 | static void convert_frag_fill_nop (fragS *); | |
9298 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
9299 | ||
e0001a05 | 9300 | void |
7fa3d080 | 9301 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9302 | { |
43cd72b9 BW |
9303 | static xtensa_insnbuf vbuf = NULL; |
9304 | xtensa_isa isa = xtensa_default_isa; | |
9305 | int slot; | |
9306 | int num_slots; | |
9307 | xtensa_format fmt; | |
e0001a05 | 9308 | char *file_name; |
d77b99c9 | 9309 | unsigned line; |
e0001a05 NC |
9310 | |
9311 | as_where (&file_name, &line); | |
9312 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9313 | ||
9314 | switch (fragp->fr_subtype) | |
9315 | { | |
9316 | case RELAX_ALIGN_NEXT_OPCODE: | |
9317 | /* Always convert. */ | |
9318 | convert_frag_align_next_opcode (fragp); | |
9319 | break; | |
9320 | ||
9321 | case RELAX_DESIRE_ALIGN: | |
9322 | /* Do nothing. If not aligned already, too bad. */ | |
9323 | break; | |
9324 | ||
43cd72b9 BW |
9325 | case RELAX_LITERAL: |
9326 | case RELAX_LITERAL_FINAL: | |
9327 | break; | |
9328 | ||
9329 | case RELAX_SLOTS: | |
9330 | if (vbuf == NULL) | |
9331 | vbuf = xtensa_insnbuf_alloc (isa); | |
9332 | ||
d77b99c9 BW |
9333 | xtensa_insnbuf_from_chars |
9334 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9335 | fmt = xtensa_format_decode (isa, vbuf); |
9336 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9337 | ||
9338 | for (slot = 0; slot < num_slots; slot++) | |
9339 | { | |
9340 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9341 | { | |
9342 | case RELAX_NARROW: | |
9343 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9344 | break; | |
9345 | ||
9346 | case RELAX_IMMED: | |
9347 | case RELAX_IMMED_STEP1: | |
9348 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9349 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9350 | /* Place the immediate. */ |
9351 | convert_frag_immed | |
9352 | (sec, fragp, | |
9353 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9354 | fmt, slot); | |
9355 | break; | |
9356 | ||
9357 | default: | |
9358 | /* This is OK because some slots could have | |
9359 | relaxations and others have none. */ | |
9360 | break; | |
9361 | } | |
9362 | } | |
9363 | break; | |
9364 | ||
9365 | case RELAX_UNREACHABLE: | |
9366 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9367 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9368 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9369 | frag_wane (fragp); | |
e0001a05 NC |
9370 | break; |
9371 | ||
43cd72b9 BW |
9372 | case RELAX_MAYBE_UNREACHABLE: |
9373 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9374 | frag_wane (fragp); | |
e0001a05 NC |
9375 | break; |
9376 | ||
43cd72b9 BW |
9377 | case RELAX_FILL_NOP: |
9378 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9379 | break; |
9380 | ||
9381 | case RELAX_LITERAL_NR: | |
9382 | if (use_literal_section) | |
9383 | { | |
9384 | /* This should have been handled during relaxation. When | |
9385 | relaxing a code segment, literals sometimes need to be | |
9386 | added to the corresponding literal segment. If that | |
9387 | literal segment has already been relaxed, then we end up | |
9388 | in this situation. Marking the literal segments as data | |
9389 | would make this happen less often (since GAS always relaxes | |
9390 | code before data), but we could still get into trouble if | |
9391 | there are instructions in a segment that is not marked as | |
9392 | containing code. Until we can implement a better solution, | |
9393 | cheat and adjust the addresses of all the following frags. | |
9394 | This could break subsequent alignments, but the linker's | |
9395 | literal coalescing will do that anyway. */ | |
9396 | ||
9397 | fragS *f; | |
9398 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9399 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
9400 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
9401 | fragp->fr_var -= 4; | |
9402 | fragp->fr_fix += 4; | |
9403 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9404 | f->fr_address += 4; | |
9405 | } | |
9406 | else | |
9407 | as_bad (_("invalid relaxation fragment result")); | |
9408 | break; | |
9409 | } | |
9410 | ||
9411 | fragp->fr_var = 0; | |
9412 | new_logical_line (file_name, line); | |
9413 | } | |
9414 | ||
9415 | ||
7fa3d080 BW |
9416 | static void |
9417 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9418 | { |
9419 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9420 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9421 | addressT aligned_address; | |
d77b99c9 BW |
9422 | offsetT fill_size; |
9423 | int nop, nop_count; | |
e0001a05 NC |
9424 | |
9425 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9426 | fragp->fr_fix); | |
9427 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9428 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9429 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9430 | ||
d77b99c9 | 9431 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9432 | { |
d77b99c9 BW |
9433 | int nop_size; |
9434 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9435 | |
9436 | assemble_nop (nop_size, nop_buf); | |
9437 | nop_buf += nop_size; | |
9438 | } | |
9439 | ||
9440 | fragp->fr_fix += fill_size; | |
9441 | fragp->fr_var -= fill_size; | |
9442 | } | |
9443 | ||
9444 | ||
9445 | static void | |
7fa3d080 | 9446 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9447 | { |
43cd72b9 | 9448 | TInsn tinsn, single_target; |
84b08ed9 | 9449 | int size, old_size, diff; |
e0001a05 NC |
9450 | offsetT frag_offset; |
9451 | ||
9c2799c2 | 9452 | gas_assert (slot == 0); |
43cd72b9 BW |
9453 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
9454 | ||
b5e4a23d | 9455 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 9456 | { |
9c2799c2 | 9457 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
9458 | || fragP->tc_frag_data.text_expansion[0] == 0); |
9459 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9460 | fmt, slot); | |
9461 | return; | |
9462 | } | |
9463 | ||
9464 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9465 | { |
9466 | /* No conversion. */ | |
9467 | fragP->fr_var = 0; | |
9468 | return; | |
9469 | } | |
9470 | ||
9c2799c2 | 9471 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 9472 | |
43cd72b9 BW |
9473 | /* Frags in this relaxation state should only contain |
9474 | single instruction bundles. */ | |
9475 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9476 | |
9477 | /* Just convert it to a wide form.... */ | |
9478 | size = 0; | |
43cd72b9 | 9479 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9480 | |
9481 | tinsn_init (&single_target); | |
9482 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9483 | ||
84b08ed9 | 9484 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9485 | { |
9486 | as_bad (_("unable to widen instruction")); | |
9487 | return; | |
9488 | } | |
9489 | ||
9490 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9491 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9492 | frag_offset, TRUE); | |
e0001a05 NC |
9493 | |
9494 | diff = size - old_size; | |
9c2799c2 NC |
9495 | gas_assert (diff >= 0); |
9496 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
9497 | fragP->fr_var -= diff; |
9498 | fragP->fr_fix += diff; | |
9499 | ||
9500 | /* clean it up */ | |
9501 | fragP->fr_var = 0; | |
9502 | } | |
9503 | ||
9504 | ||
9505 | static void | |
7fa3d080 | 9506 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9507 | { |
9508 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9509 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 9510 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
9511 | - fragP->fr_address - fragP->fr_fix)); |
9512 | if (size == 0) | |
9513 | { | |
9514 | /* No conversion. */ | |
9515 | fragP->fr_var = 0; | |
9516 | return; | |
9517 | } | |
9518 | assemble_nop (size, loc); | |
9519 | fragP->tc_frag_data.is_insn = TRUE; | |
9520 | fragP->fr_var -= size; | |
9521 | fragP->fr_fix += size; | |
9522 | frag_wane (fragP); | |
9523 | } | |
9524 | ||
9525 | ||
7fa3d080 BW |
9526 | static fixS *fix_new_exp_in_seg |
9527 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9528 | bfd_reloc_code_real_type); | |
9529 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9530 | ||
43cd72b9 | 9531 | static void |
7fa3d080 BW |
9532 | convert_frag_immed (segT segP, |
9533 | fragS *fragP, | |
9534 | int min_steps, | |
9535 | xtensa_format fmt, | |
9536 | int slot) | |
e0001a05 NC |
9537 | { |
9538 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9539 | TInsn orig_tinsn; |
e0001a05 | 9540 | bfd_boolean expanded = FALSE; |
e0001a05 | 9541 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9542 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 9543 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 9544 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
9545 | int bytes; |
9546 | bfd_boolean is_loop; | |
e0001a05 | 9547 | |
9c2799c2 | 9548 | gas_assert (fr_opcode != NULL); |
e0001a05 | 9549 | |
b5e4a23d | 9550 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9551 | |
b5e4a23d | 9552 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9553 | if (cur_vinsn.num_slots > 1) |
def13efb | 9554 | from_wide_insn = TRUE; |
e0001a05 | 9555 | |
b5e4a23d | 9556 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9557 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9558 | ||
9559 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9560 | |
b08b5071 | 9561 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9562 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9563 | |
9564 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9565 | { | |
9566 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9567 | bytes = xtensa_format_length (isa, fmt); |
9568 | if (bytes >= 4) | |
9569 | { | |
b5e4a23d BW |
9570 | cur_vinsn.slots[slot].opcode = |
9571 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9572 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9573 | } |
9574 | else | |
9575 | { | |
9576 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 9577 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 9578 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9579 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9580 | } | |
e7da6241 | 9581 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9582 | xtensa_insnbuf_to_chars |
b5e4a23d | 9583 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9584 | fragP->fr_var = 0; |
9585 | } | |
7c834684 | 9586 | else |
e0001a05 | 9587 | { |
43cd72b9 BW |
9588 | /* Here is the fun stuff: Get the immediate field from this |
9589 | instruction. If it fits, we're done. If not, find the next | |
9590 | instruction sequence that fits. */ | |
9591 | ||
e0001a05 NC |
9592 | IStack istack; |
9593 | int i; | |
9594 | symbolS *lit_sym = NULL; | |
9595 | int total_size = 0; | |
43cd72b9 | 9596 | int target_offset = 0; |
e0001a05 NC |
9597 | int old_size; |
9598 | int diff; | |
9599 | symbolS *gen_label = NULL; | |
9600 | offsetT frag_offset; | |
43cd72b9 BW |
9601 | bfd_boolean first = TRUE; |
9602 | bfd_boolean last_is_jump; | |
e0001a05 | 9603 | |
43cd72b9 | 9604 | /* It does not fit. Find something that does and |
e0001a05 | 9605 | convert immediately. */ |
43cd72b9 | 9606 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9607 | istack_init (&istack); |
43cd72b9 | 9608 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9609 | segP, fragP, frag_offset, min_steps, 0); |
9610 | ||
43cd72b9 | 9611 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9612 | |
9613 | /* Assemble this right inline. */ | |
9614 | ||
9615 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9616 | target_offset = 0; |
e0001a05 NC |
9617 | for (i = 0; i < istack.ninsn; i++) |
9618 | { | |
43cd72b9 | 9619 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9620 | fragS *lit_frag; |
9621 | ||
43cd72b9 | 9622 | switch (tinsn->insn_type) |
e0001a05 NC |
9623 | { |
9624 | case ITYPE_LITERAL: | |
9625 | if (lit_sym != NULL) | |
9626 | as_bad (_("multiple literals in expansion")); | |
9627 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9628 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9629 | if (lit_frag == NULL) |
9630 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9631 | if (tinsn->ntok != 1) |
e0001a05 NC |
9632 | as_bad (_("number of literal tokens != 1")); |
9633 | ||
9634 | /* Set the literal symbol and add a fixup. */ | |
9635 | lit_sym = lit_frag->fr_symbol; | |
9636 | break; | |
9637 | ||
9638 | case ITYPE_LABEL: | |
43cd72b9 BW |
9639 | if (align_targets && !is_loop) |
9640 | { | |
9641 | fragS *unreach = fragP->fr_next; | |
9642 | while (!(unreach->fr_type == rs_machine_dependent | |
9643 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9644 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9645 | { | |
9646 | unreach = unreach->fr_next; | |
9647 | } | |
9648 | ||
9c2799c2 | 9649 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
9650 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
9651 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9652 | ||
9653 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9654 | } | |
9c2799c2 | 9655 | gas_assert (gen_label == NULL); |
e0001a05 | 9656 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, |
43cd72b9 BW |
9657 | fr_opcode - fragP->fr_literal |
9658 | + target_offset, fragP); | |
e0001a05 NC |
9659 | break; |
9660 | ||
9661 | case ITYPE_INSN: | |
def13efb | 9662 | if (first && from_wide_insn) |
43cd72b9 BW |
9663 | { |
9664 | target_offset += xtensa_format_length (isa, fmt); | |
9665 | first = FALSE; | |
9666 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9667 | target_offset += xg_get_single_size (tinsn->opcode); | |
9668 | } | |
9669 | else | |
9670 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9671 | break; |
9672 | } | |
9673 | } | |
9674 | ||
9675 | total_size = 0; | |
43cd72b9 BW |
9676 | first = TRUE; |
9677 | last_is_jump = FALSE; | |
e0001a05 NC |
9678 | for (i = 0; i < istack.ninsn; i++) |
9679 | { | |
43cd72b9 | 9680 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9681 | fragS *lit_frag; |
9682 | int size; | |
9683 | segT target_seg; | |
43cd72b9 | 9684 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9685 | |
43cd72b9 | 9686 | switch (tinsn->insn_type) |
e0001a05 NC |
9687 | { |
9688 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9689 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9690 | /* Already checked. */ | |
9c2799c2 NC |
9691 | gas_assert (lit_frag != NULL); |
9692 | gas_assert (lit_sym != NULL); | |
9693 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 9694 | /* Add a fixup. */ |
e0001a05 | 9695 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 9696 | gas_assert (target_seg); |
28dbbc02 | 9697 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 9698 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9699 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9700 | break; |
9701 | ||
9702 | case ITYPE_LABEL: | |
9703 | break; | |
9704 | ||
9705 | case ITYPE_INSN: | |
43cd72b9 BW |
9706 | xg_resolve_labels (tinsn, gen_label); |
9707 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 9708 | if (from_wide_insn && first) |
43cd72b9 BW |
9709 | { |
9710 | first = FALSE; | |
9711 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9712 | { | |
b5e4a23d | 9713 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9714 | } |
9715 | else | |
9716 | { | |
b5e4a23d | 9717 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9718 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9719 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9720 | } |
b5e4a23d BW |
9721 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9722 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9723 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9724 | fragP->tc_frag_data.is_insn = TRUE; |
9725 | size = xtensa_format_length (isa, fmt); | |
9726 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9727 | { | |
43cd72b9 | 9728 | xg_emit_insn_to_buf |
b2d179be | 9729 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9730 | immed_instr - fragP->fr_literal + size, TRUE); |
9731 | size += xg_get_single_size (tinsn->opcode); | |
9732 | } | |
9733 | } | |
9734 | else | |
9735 | { | |
43cd72b9 | 9736 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9737 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9738 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9739 | } |
e0001a05 | 9740 | immed_instr += size; |
43cd72b9 | 9741 | total_size += size; |
e0001a05 NC |
9742 | break; |
9743 | } | |
9744 | } | |
9745 | ||
9746 | diff = total_size - old_size; | |
9c2799c2 | 9747 | gas_assert (diff >= 0); |
e0001a05 NC |
9748 | if (diff != 0) |
9749 | expanded = TRUE; | |
9c2799c2 | 9750 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
9751 | fragP->fr_var -= diff; |
9752 | fragP->fr_fix += diff; | |
9753 | } | |
9754 | ||
e0001a05 | 9755 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9756 | if (is_loop) |
e0001a05 NC |
9757 | { |
9758 | symbolS *sym; | |
43cd72b9 | 9759 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9760 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9761 | { | |
9762 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9763 | return; | |
9764 | } | |
43cd72b9 | 9765 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9766 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9767 | { | |
9768 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9769 | return; | |
9770 | } | |
9771 | } | |
9772 | ||
43cd72b9 BW |
9773 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9774 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9775 | |
43cd72b9 | 9776 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9777 | { |
9778 | /* Add an expansion note on the expanded instruction. */ | |
9779 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9780 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9781 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9782 | } |
9783 | } | |
9784 | ||
9785 | ||
9786 | /* Add a new fix expression into the desired segment. We have to | |
9787 | switch to that segment to do this. */ | |
9788 | ||
9789 | static fixS * | |
7fa3d080 BW |
9790 | fix_new_exp_in_seg (segT new_seg, |
9791 | subsegT new_subseg, | |
9792 | fragS *frag, | |
9793 | int where, | |
9794 | int size, | |
9795 | expressionS *exp, | |
9796 | int pcrel, | |
9797 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9798 | { |
9799 | fixS *new_fix; | |
9800 | segT seg = now_seg; | |
9801 | subsegT subseg = now_subseg; | |
43cd72b9 | 9802 | |
9c2799c2 | 9803 | gas_assert (new_seg != 0); |
e0001a05 NC |
9804 | subseg_set (new_seg, new_subseg); |
9805 | ||
e0001a05 NC |
9806 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9807 | subseg_set (seg, subseg); | |
9808 | return new_fix; | |
9809 | } | |
9810 | ||
9811 | ||
43cd72b9 BW |
9812 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9813 | ||
9814 | loop as, .L1 | |
9815 | .L0: | |
9816 | rsr as, LEND | |
9817 | wsr as, LBEG | |
9818 | addi as, as, lo8 (label-.L1) | |
9819 | addmi as, as, mid8 (label-.L1) | |
9820 | wsr as, LEND | |
9821 | isync | |
9822 | rsr as, LCOUNT | |
9823 | addi as, as, 1 | |
9824 | .L1: | |
9825 | <<body>> | |
9826 | label: | |
9827 | */ | |
e0001a05 NC |
9828 | |
9829 | static void | |
7fa3d080 | 9830 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9831 | { |
9832 | TInsn loop_insn; | |
9833 | TInsn addi_insn; | |
9834 | TInsn addmi_insn; | |
9835 | unsigned long target; | |
9836 | static xtensa_insnbuf insnbuf = NULL; | |
9837 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9838 | xtensa_isa isa = xtensa_default_isa; | |
9839 | addressT loop_offset; | |
9840 | addressT addi_offset = 9; | |
9841 | addressT addmi_offset = 12; | |
43cd72b9 | 9842 | fragS *next_fragP; |
d77b99c9 | 9843 | int target_count; |
e0001a05 NC |
9844 | |
9845 | if (!insnbuf) | |
9846 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9847 | ||
9848 | /* Get the loop offset. */ | |
43cd72b9 | 9849 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9850 | |
43cd72b9 BW |
9851 | /* Validate that there really is a LOOP at the loop_offset. Because |
9852 | loops are not bundleable, we can assume that the instruction will be | |
9853 | in slot 0. */ | |
9854 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9855 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9856 | ||
9c2799c2 | 9857 | gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); |
e0001a05 NC |
9858 | addi_offset += loop_offset; |
9859 | addmi_offset += loop_offset; | |
9860 | ||
9c2799c2 | 9861 | gas_assert (tinsn->ntok == 2); |
b08b5071 BW |
9862 | if (tinsn->tok[1].X_op == O_constant) |
9863 | target = tinsn->tok[1].X_add_number; | |
9864 | else if (tinsn->tok[1].X_op == O_symbol) | |
9865 | { | |
9866 | /* Find the fragment. */ | |
9867 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9c2799c2 | 9868 | gas_assert (S_GET_SEGMENT (sym) == segP |
b08b5071 BW |
9869 | || S_GET_SEGMENT (sym) == absolute_section); |
9870 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9871 | } | |
9872 | else | |
9873 | { | |
9874 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9875 | target = 0; | |
9876 | } | |
e0001a05 | 9877 | |
e0001a05 NC |
9878 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
9879 | loop_length_hi = loop_length & ~0x0ff; | |
9880 | loop_length_lo = loop_length & 0x0ff; | |
9881 | if (loop_length_lo >= 128) | |
9882 | { | |
9883 | loop_length_lo -= 256; | |
9884 | loop_length_hi += 256; | |
9885 | } | |
9886 | ||
43cd72b9 | 9887 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9888 | 32512. If the loop is larger than that, then we just fail. */ |
9889 | if (loop_length_hi > 32512) | |
9890 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9891 | _("loop too long for LOOP instruction")); | |
9892 | ||
43cd72b9 | 9893 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
9c2799c2 | 9894 | gas_assert (addi_insn.opcode == xtensa_addi_opcode); |
e0001a05 | 9895 | |
43cd72b9 | 9896 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
9c2799c2 | 9897 | gas_assert (addmi_insn.opcode == xtensa_addmi_opcode); |
e0001a05 NC |
9898 | |
9899 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9900 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9901 | |
e0001a05 | 9902 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9903 | xtensa_insnbuf_to_chars |
9904 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9905 | |
9906 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9907 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9908 | xtensa_insnbuf_to_chars |
9909 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9910 | |
9911 | /* Walk through all of the frags from here to the loop end | |
9912 | and mark them as no_transform to keep them from being modified | |
9913 | by the linker. If we ever have a relocation for the | |
9914 | addi/addmi of the difference of two symbols we can remove this. */ | |
9915 | ||
9916 | target_count = 0; | |
9917 | for (next_fragP = fragP; next_fragP != NULL; | |
9918 | next_fragP = next_fragP->fr_next) | |
9919 | { | |
b08b5071 | 9920 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9921 | if (next_fragP->tc_frag_data.is_loop_target) |
9922 | target_count++; | |
9923 | if (target_count == 2) | |
9924 | break; | |
9925 | } | |
e0001a05 NC |
9926 | } |
9927 | ||
b08b5071 BW |
9928 | \f |
9929 | /* A map that keeps information on a per-subsegment basis. This is | |
9930 | maintained during initial assembly, but is invalid once the | |
9931 | subsegments are smashed together. I.E., it cannot be used during | |
9932 | the relaxation. */ | |
e0001a05 | 9933 | |
b08b5071 | 9934 | typedef struct subseg_map_struct |
e0001a05 | 9935 | { |
b08b5071 BW |
9936 | /* the key */ |
9937 | segT seg; | |
9938 | subsegT subseg; | |
e0001a05 | 9939 | |
b08b5071 BW |
9940 | /* the data */ |
9941 | unsigned flags; | |
9942 | float total_freq; /* fall-through + branch target frequency */ | |
9943 | float target_freq; /* branch target frequency alone */ | |
9944 | ||
9945 | struct subseg_map_struct *next; | |
9946 | } subseg_map; | |
e0001a05 | 9947 | |
e0001a05 | 9948 | |
e0001a05 NC |
9949 | static subseg_map *sseg_map = NULL; |
9950 | ||
43cd72b9 | 9951 | static subseg_map * |
7fa3d080 | 9952 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9953 | { |
9954 | subseg_map *subseg_e; | |
9955 | ||
9956 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9957 | { |
43cd72b9 | 9958 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9959 | break; |
e0001a05 | 9960 | } |
b08b5071 BW |
9961 | return subseg_e; |
9962 | } | |
9963 | ||
9964 | ||
9965 | static subseg_map * | |
9966 | add_subseg_info (segT seg, subsegT subseg) | |
9967 | { | |
9968 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9969 | memset (subseg_e, 0, sizeof (subseg_map)); |
9970 | subseg_e->seg = seg; | |
9971 | subseg_e->subseg = subseg; | |
9972 | subseg_e->flags = 0; | |
9973 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9974 | subseg_e->target_freq = 1.0; |
9975 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9976 | subseg_e->next = sseg_map; |
9977 | sseg_map = subseg_e; | |
43cd72b9 BW |
9978 | return subseg_e; |
9979 | } | |
e0001a05 | 9980 | |
7fa3d080 BW |
9981 | |
9982 | static unsigned | |
9983 | get_last_insn_flags (segT seg, subsegT subseg) | |
9984 | { | |
9985 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9986 | if (subseg_e) |
9987 | return subseg_e->flags; | |
9988 | return 0; | |
7fa3d080 BW |
9989 | } |
9990 | ||
9991 | ||
43cd72b9 | 9992 | static void |
7fa3d080 BW |
9993 | set_last_insn_flags (segT seg, |
9994 | subsegT subseg, | |
9995 | unsigned fl, | |
9996 | bfd_boolean val) | |
43cd72b9 BW |
9997 | { |
9998 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9999 | if (! subseg_e) |
10000 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
10001 | if (val) |
10002 | subseg_e->flags |= fl; | |
10003 | else | |
10004 | subseg_e->flags &= ~fl; | |
10005 | } | |
10006 | ||
b08b5071 BW |
10007 | |
10008 | static float | |
10009 | get_subseg_total_freq (segT seg, subsegT subseg) | |
10010 | { | |
10011 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10012 | if (subseg_e) | |
10013 | return subseg_e->total_freq; | |
10014 | return 1.0; | |
10015 | } | |
10016 | ||
10017 | ||
10018 | static float | |
10019 | get_subseg_target_freq (segT seg, subsegT subseg) | |
10020 | { | |
10021 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10022 | if (subseg_e) | |
10023 | return subseg_e->target_freq; | |
10024 | return 1.0; | |
10025 | } | |
10026 | ||
10027 | ||
10028 | static void | |
10029 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
10030 | { | |
10031 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10032 | if (! subseg_e) | |
10033 | subseg_e = add_subseg_info (seg, subseg); | |
10034 | subseg_e->total_freq = total_f; | |
10035 | subseg_e->target_freq = target_f; | |
10036 | } | |
10037 | ||
e0001a05 NC |
10038 | \f |
10039 | /* Segment Lists and emit_state Stuff. */ | |
10040 | ||
e0001a05 | 10041 | static void |
7fa3d080 | 10042 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
10043 | { |
10044 | head = head->next; | |
10045 | while (head) | |
10046 | { | |
10047 | segT literal_section = head->seg; | |
10048 | ||
10049 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 10050 | gas_assert (literal_section); |
69852798 AM |
10051 | if (literal_section != stdoutput->sections) |
10052 | { | |
10053 | bfd_section_list_remove (stdoutput, literal_section); | |
10054 | bfd_section_list_prepend (stdoutput, literal_section); | |
10055 | } | |
e0001a05 NC |
10056 | head = head->next; |
10057 | } | |
10058 | } | |
10059 | ||
10060 | ||
7fa3d080 BW |
10061 | static void mark_literal_frags (seg_list *); |
10062 | ||
10063 | static void | |
10064 | xtensa_move_literals (void) | |
e0001a05 NC |
10065 | { |
10066 | seg_list *segment; | |
10067 | frchainS *frchain_from, *frchain_to; | |
10068 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
10069 | fragS **frag_splice; | |
10070 | emit_state state; | |
10071 | segT dest_seg; | |
10072 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 10073 | sym_list *lit; |
e0001a05 | 10074 | |
a7877748 | 10075 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
10076 | |
10077 | if (use_literal_section) | |
10078 | return; | |
10079 | ||
74869ac7 | 10080 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 10081 | { |
74869ac7 BW |
10082 | /* Keep the literals for .init and .fini in separate sections. */ |
10083 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
10084 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
10085 | continue; | |
10086 | ||
e0001a05 NC |
10087 | frchain_from = seg_info (segment->seg)->frchainP; |
10088 | search_frag = frchain_from->frch_root; | |
10089 | literal_pool = NULL; | |
10090 | frchain_to = NULL; | |
10091 | frag_splice = &(frchain_from->frch_root); | |
10092 | ||
10093 | while (!search_frag->tc_frag_data.literal_frag) | |
10094 | { | |
9c2799c2 | 10095 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
10096 | || search_frag->fr_type == rs_align); |
10097 | search_frag = search_frag->fr_next; | |
10098 | } | |
10099 | ||
9c2799c2 | 10100 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
10101 | == RELAX_LITERAL_POOL_BEGIN); |
10102 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
10103 | ||
10104 | /* Make sure that all the frags in this series are closed, and | |
10105 | that there is at least one left over of zero-size. This | |
10106 | prevents us from making a segment with an frchain without any | |
10107 | frags in it. */ | |
10108 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10109 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10110 | last_frag = frag_now; |
10111 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10112 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10113 | |
43cd72b9 | 10114 | while (search_frag != frag_now) |
e0001a05 NC |
10115 | { |
10116 | next_frag = search_frag->fr_next; | |
10117 | ||
43cd72b9 | 10118 | /* First, move the frag out of the literal section and |
e0001a05 NC |
10119 | to the appropriate place. */ |
10120 | if (search_frag->tc_frag_data.literal_frag) | |
10121 | { | |
10122 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 10123 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 10124 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 10125 | gas_assert (frchain_to); |
e0001a05 | 10126 | } |
c48aaca0 | 10127 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 10128 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 10129 | |
e0001a05 NC |
10130 | *frag_splice = next_frag; |
10131 | search_frag->fr_next = insert_after->fr_next; | |
10132 | insert_after->fr_next = search_frag; | |
10133 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 10134 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
10135 | |
10136 | /* Now move any fixups associated with this frag to the | |
10137 | right section. */ | |
10138 | fix = frchain_from->fix_root; | |
10139 | fix_splice = &(frchain_from->fix_root); | |
10140 | while (fix) | |
10141 | { | |
10142 | next_fix = fix->fx_next; | |
10143 | if (fix->fx_frag == search_frag) | |
10144 | { | |
10145 | *fix_splice = next_fix; | |
10146 | fix->fx_next = frchain_to->fix_root; | |
10147 | frchain_to->fix_root = fix; | |
10148 | if (frchain_to->fix_tail == NULL) | |
10149 | frchain_to->fix_tail = fix; | |
10150 | } | |
10151 | else | |
10152 | fix_splice = &(fix->fx_next); | |
10153 | fix = next_fix; | |
10154 | } | |
10155 | search_frag = next_frag; | |
10156 | } | |
10157 | ||
10158 | if (frchain_from->fix_root != NULL) | |
10159 | { | |
10160 | frchain_from = seg_info (segment->seg)->frchainP; | |
10161 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
10162 | ||
9c2799c2 | 10163 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
10164 | } |
10165 | frchain_from->fix_tail = NULL; | |
10166 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
10167 | } |
10168 | ||
82e7541d BW |
10169 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
10170 | for (lit = literal_syms; lit; lit = lit->next) | |
10171 | { | |
10172 | symbolS *lit_sym = lit->sym; | |
91d6fa6a NC |
10173 | segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; |
10174 | if (dseg) | |
10175 | S_SET_SEGMENT (lit_sym, dseg); | |
82e7541d | 10176 | } |
e0001a05 NC |
10177 | } |
10178 | ||
10179 | ||
a7877748 BW |
10180 | /* Walk over all the frags for segments in a list and mark them as |
10181 | containing literals. As clunky as this is, we can't rely on frag_var | |
10182 | and frag_variant to get called in all situations. */ | |
10183 | ||
10184 | static void | |
7fa3d080 | 10185 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
10186 | { |
10187 | frchainS *frchain_from; | |
10188 | fragS *search_frag; | |
10189 | ||
10190 | while (segment) | |
10191 | { | |
10192 | frchain_from = seg_info (segment->seg)->frchainP; | |
10193 | search_frag = frchain_from->frch_root; | |
c138bc38 | 10194 | while (search_frag) |
a7877748 BW |
10195 | { |
10196 | search_frag->tc_frag_data.is_literal = TRUE; | |
10197 | search_frag = search_frag->fr_next; | |
10198 | } | |
10199 | segment = segment->next; | |
10200 | } | |
10201 | } | |
10202 | ||
10203 | ||
e0001a05 | 10204 | static void |
7fa3d080 | 10205 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
10206 | { |
10207 | /* Move all of the sections in the section list to come | |
10208 | after "after" in the gnu segment list. */ | |
10209 | ||
10210 | head = head->next; | |
10211 | while (head) | |
10212 | { | |
10213 | segT literal_section = head->seg; | |
10214 | ||
10215 | /* Move the literal section after "after". */ | |
9c2799c2 | 10216 | gas_assert (literal_section); |
e0001a05 NC |
10217 | if (literal_section != after) |
10218 | { | |
69852798 AM |
10219 | bfd_section_list_remove (stdoutput, literal_section); |
10220 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
10221 | } |
10222 | ||
10223 | head = head->next; | |
10224 | } | |
10225 | } | |
10226 | ||
10227 | ||
10228 | /* Push all the literal segments to the end of the gnu list. */ | |
10229 | ||
7fa3d080 BW |
10230 | static void |
10231 | xtensa_reorder_segments (void) | |
e0001a05 NC |
10232 | { |
10233 | segT sec; | |
b08b5071 | 10234 | segT last_sec = 0; |
e0001a05 NC |
10235 | int old_count = 0; |
10236 | int new_count = 0; | |
10237 | ||
10238 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
10239 | { |
10240 | last_sec = sec; | |
10241 | old_count++; | |
10242 | } | |
e0001a05 NC |
10243 | |
10244 | /* Now that we have the last section, push all the literal | |
10245 | sections to the end. */ | |
e0001a05 | 10246 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
10247 | |
10248 | /* Now perform the final error check. */ | |
10249 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10250 | new_count++; | |
9c2799c2 | 10251 | gas_assert (new_count == old_count); |
e0001a05 NC |
10252 | } |
10253 | ||
10254 | ||
e0001a05 NC |
10255 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10256 | correct location. Return a emit_state which can be passed to | |
10257 | xtensa_restore_emit_state to return to current fragment. */ | |
10258 | ||
7fa3d080 BW |
10259 | static void |
10260 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10261 | { |
10262 | if (directive_state[directive_absolute_literals]) | |
10263 | { | |
74869ac7 BW |
10264 | segT lit4_seg = cache_literal_section (TRUE); |
10265 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
10266 | } |
10267 | else | |
10268 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10269 | ||
10270 | /* Do a 4-byte align here. */ | |
10271 | frag_align (2, 0, 0); | |
10272 | record_alignment (now_seg, 2); | |
10273 | } | |
10274 | ||
10275 | ||
7fa3d080 BW |
10276 | static void |
10277 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 10278 | { |
e0001a05 NC |
10279 | static bfd_boolean recursive = FALSE; |
10280 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 10281 | segT lit_seg; |
c138bc38 | 10282 | bfd_boolean is_init = |
e0001a05 | 10283 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 10284 | bfd_boolean is_fini = |
e0001a05 | 10285 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 10286 | |
43cd72b9 BW |
10287 | if (pool_location == NULL |
10288 | && !use_literal_section | |
e0001a05 NC |
10289 | && !recursive |
10290 | && !is_init && ! is_fini) | |
10291 | { | |
43cd72b9 | 10292 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
10293 | |
10294 | /* When we mark a literal pool location, we want to put a frag in | |
10295 | the literal pool that points to it. But to do that, we want to | |
10296 | switch_to_literal_fragment. But literal sections don't have | |
10297 | literal pools, so their location is always null, so we would | |
10298 | recurse forever. This is kind of hacky, but it works. */ | |
10299 | ||
e0001a05 | 10300 | recursive = TRUE; |
61846f28 | 10301 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10302 | recursive = FALSE; |
10303 | } | |
10304 | ||
74869ac7 BW |
10305 | lit_seg = cache_literal_section (FALSE); |
10306 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 10307 | |
43cd72b9 BW |
10308 | if (!use_literal_section |
10309 | && !is_init && !is_fini | |
10310 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10311 | { |
10312 | /* Close whatever frag is there. */ | |
10313 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10314 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10315 | frag_now->tc_frag_data.literal_frag = pool_location; |
10316 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10317 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10318 | } |
e0001a05 NC |
10319 | } |
10320 | ||
10321 | ||
10322 | /* Call this function before emitting data into the literal section. | |
10323 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10324 | This is similar to a .section new_now_seg subseg. */ | |
10325 | ||
7fa3d080 BW |
10326 | static void |
10327 | xtensa_switch_section_emit_state (emit_state *state, | |
10328 | segT new_now_seg, | |
10329 | subsegT new_now_subseg) | |
e0001a05 NC |
10330 | { |
10331 | state->name = now_seg->name; | |
10332 | state->now_seg = now_seg; | |
10333 | state->now_subseg = now_subseg; | |
10334 | state->generating_literals = generating_literals; | |
10335 | generating_literals++; | |
2b0210eb | 10336 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10337 | } |
10338 | ||
10339 | ||
10340 | /* Use to restore the emitting into the normal place. */ | |
10341 | ||
7fa3d080 BW |
10342 | static void |
10343 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10344 | { |
10345 | generating_literals = state->generating_literals; | |
2b0210eb | 10346 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10347 | } |
10348 | ||
10349 | ||
74869ac7 | 10350 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10351 | |
74869ac7 BW |
10352 | static bfd_boolean |
10353 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10354 | { |
74869ac7 BW |
10355 | const char *gname = inf; |
10356 | const char *group_name = elf_group_name (sec); | |
10357 | ||
10358 | return (group_name == gname | |
10359 | || (group_name != NULL | |
10360 | && gname != NULL | |
10361 | && strcmp (group_name, gname) == 0)); | |
10362 | } | |
e0001a05 | 10363 | |
e0001a05 | 10364 | |
74869ac7 BW |
10365 | /* Get the literal section to be used for the current text section. |
10366 | The result may be cached in the default_lit_sections structure. */ | |
10367 | ||
10368 | static segT | |
10369 | cache_literal_section (bfd_boolean use_abs_literals) | |
10370 | { | |
10371 | const char *text_name, *group_name = 0; | |
10372 | char *base_name, *name, *suffix; | |
10373 | segT *pcached; | |
10374 | segT seg, current_section; | |
10375 | int current_subsec; | |
10376 | bfd_boolean linkonce = FALSE; | |
10377 | ||
10378 | /* Save the current section/subsection. */ | |
10379 | current_section = now_seg; | |
10380 | current_subsec = now_subseg; | |
10381 | ||
10382 | /* Clear the cached values if they are no longer valid. */ | |
10383 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10384 | { |
74869ac7 BW |
10385 | default_lit_sections.current_text_seg = now_seg; |
10386 | default_lit_sections.lit_seg = NULL; | |
10387 | default_lit_sections.lit4_seg = NULL; | |
10388 | } | |
10389 | ||
10390 | /* Check if the literal section is already cached. */ | |
10391 | if (use_abs_literals) | |
10392 | pcached = &default_lit_sections.lit4_seg; | |
10393 | else | |
10394 | pcached = &default_lit_sections.lit_seg; | |
10395 | ||
10396 | if (*pcached) | |
10397 | return *pcached; | |
10398 | ||
10399 | text_name = default_lit_sections.lit_prefix; | |
10400 | if (! text_name || ! *text_name) | |
10401 | { | |
10402 | text_name = segment_name (current_section); | |
10403 | group_name = elf_group_name (current_section); | |
10404 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10405 | } | |
10406 | ||
10407 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10408 | if (group_name) | |
10409 | { | |
10410 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10411 | sprintf (name, "%s.%s", base_name, group_name); | |
10412 | } | |
10413 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10414 | { | |
10415 | suffix = strchr (text_name + linkonce_len, '.'); | |
10416 | ||
10417 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10418 | + (suffix ? strlen (suffix) : 0)); | |
10419 | strcpy (name, ".gnu.linkonce"); | |
10420 | strcat (name, base_name); | |
10421 | if (suffix) | |
10422 | strcat (name, suffix); | |
10423 | linkonce = TRUE; | |
10424 | } | |
10425 | else | |
10426 | { | |
10427 | /* If the section name ends with ".text", then replace that suffix | |
10428 | instead of appending an additional suffix. */ | |
10429 | size_t len = strlen (text_name); | |
10430 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10431 | len -= 5; | |
10432 | ||
10433 | name = xmalloc (len + strlen (base_name) + 1); | |
10434 | strcpy (name, text_name); | |
10435 | strcpy (name + len, base_name); | |
b08b5071 | 10436 | } |
e0001a05 | 10437 | |
74869ac7 BW |
10438 | /* Canonicalize section names to allow renaming literal sections. |
10439 | The group name, if any, came from the current text section and | |
10440 | has already been canonicalized. */ | |
10441 | name = tc_canonicalize_symbol_name (name); | |
10442 | ||
10443 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10444 | (void *) group_name); | |
10445 | if (! seg) | |
e0001a05 | 10446 | { |
74869ac7 BW |
10447 | flagword flags; |
10448 | ||
10449 | seg = subseg_force_new (name, 0); | |
10450 | ||
10451 | if (! use_abs_literals) | |
b08b5071 | 10452 | { |
74869ac7 | 10453 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10454 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10455 | n->seg = seg; | |
74869ac7 BW |
10456 | n->next = literal_head->next; |
10457 | literal_head->next = n; | |
b08b5071 | 10458 | } |
74869ac7 BW |
10459 | |
10460 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10461 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10462 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10463 | ||
10464 | elf_group_name (seg) = group_name; | |
10465 | ||
10466 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10467 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10468 | } |
10469 | ||
74869ac7 | 10470 | *pcached = seg; |
b08b5071 | 10471 | subseg_set (current_section, current_subsec); |
74869ac7 | 10472 | return seg; |
e0001a05 NC |
10473 | } |
10474 | ||
43cd72b9 BW |
10475 | \f |
10476 | /* Property Tables Stuff. */ | |
10477 | ||
7fa3d080 BW |
10478 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10479 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10480 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10481 | ||
10482 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10483 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10484 | ||
b08b5071 | 10485 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10486 | static void xtensa_create_property_segments |
10487 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10488 | static void xtensa_create_xproperty_segments | |
10489 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 10490 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
10491 | static bfd_boolean section_has_property (segT, frag_predicate); |
10492 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10493 | static void add_xt_block_frags | |
542f8b94 | 10494 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
10495 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
10496 | static void xtensa_frag_flags_init (frag_flags *); | |
10497 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 10498 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 10499 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
10500 | |
10501 | /* Set up property tables after relaxation. */ | |
10502 | ||
10503 | void | |
10504 | xtensa_post_relax_hook (void) | |
10505 | { | |
10506 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10507 | |
10508 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 10509 | xtensa_mark_frags_for_org (); |
6a7eedfe | 10510 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 10511 | |
b29757dc BW |
10512 | xtensa_create_property_segments (get_frag_is_literal, |
10513 | NULL, | |
10514 | XTENSA_LIT_SEC_NAME, | |
10515 | xt_literal_sec); | |
7fa3d080 BW |
10516 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10517 | XTENSA_PROP_SEC_NAME, | |
10518 | xt_prop_sec); | |
10519 | ||
10520 | if (warn_unaligned_branch_targets) | |
10521 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10522 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10523 | } | |
10524 | ||
10525 | ||
43cd72b9 BW |
10526 | /* This function is only meaningful after xtensa_move_literals. */ |
10527 | ||
10528 | static bfd_boolean | |
7fa3d080 | 10529 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 10530 | { |
9c2799c2 | 10531 | gas_assert (fragP != NULL); |
43cd72b9 BW |
10532 | return fragP->tc_frag_data.is_literal; |
10533 | } | |
10534 | ||
10535 | ||
43cd72b9 | 10536 | static void |
7fa3d080 BW |
10537 | xtensa_create_property_segments (frag_predicate property_function, |
10538 | frag_predicate end_property_function, | |
10539 | const char *section_name_base, | |
10540 | xt_section_type sec_type) | |
43cd72b9 BW |
10541 | { |
10542 | segT *seclist; | |
10543 | ||
10544 | /* Walk over all of the current segments. | |
10545 | Walk over each fragment | |
10546 | For each non-empty fragment, | |
10547 | Build a property record (append where possible). */ | |
10548 | ||
10549 | for (seclist = &stdoutput->sections; | |
10550 | seclist && *seclist; | |
10551 | seclist = &(*seclist)->next) | |
10552 | { | |
10553 | segT sec = *seclist; | |
43cd72b9 | 10554 | |
532f93bd | 10555 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
10556 | continue; |
10557 | ||
10558 | if (section_has_property (sec, property_function)) | |
10559 | { | |
542f8b94 BW |
10560 | segment_info_type *xt_seg_info; |
10561 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 10562 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
10563 | |
10564 | prop_sec->output_section = prop_sec; | |
10565 | subseg_set (prop_sec, 0); | |
10566 | xt_seg_info = seg_info (prop_sec); | |
10567 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10568 | ||
43cd72b9 | 10569 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10570 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
10571 | end_property_function); |
10572 | } | |
10573 | } | |
10574 | ||
10575 | /* Now we fill them out.... */ | |
10576 | ||
10577 | for (seclist = &stdoutput->sections; | |
10578 | seclist && *seclist; | |
10579 | seclist = &(*seclist)->next) | |
10580 | { | |
10581 | segment_info_type *seginfo; | |
10582 | xtensa_block_info *block; | |
10583 | segT sec = *seclist; | |
10584 | ||
10585 | seginfo = seg_info (sec); | |
10586 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10587 | ||
10588 | if (block) | |
10589 | { | |
10590 | xtensa_block_info *cur_block; | |
43cd72b9 | 10591 | int num_recs = 0; |
d77b99c9 | 10592 | bfd_size_type rec_size; |
43cd72b9 BW |
10593 | |
10594 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10595 | num_recs++; | |
10596 | ||
10597 | rec_size = num_recs * 8; | |
10598 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10599 | ||
43cd72b9 BW |
10600 | if (num_recs) |
10601 | { | |
43cd72b9 | 10602 | char *frag_data; |
542f8b94 | 10603 | int i; |
43cd72b9 | 10604 | |
542f8b94 BW |
10605 | subseg_set (sec, 0); |
10606 | frag_data = frag_more (rec_size); | |
43cd72b9 | 10607 | cur_block = block; |
43cd72b9 BW |
10608 | for (i = 0; i < num_recs; i++) |
10609 | { | |
542f8b94 | 10610 | fixS *fix; |
e0001a05 | 10611 | |
43cd72b9 | 10612 | /* Write the fixup. */ |
9c2799c2 | 10613 | gas_assert (cur_block); |
542f8b94 BW |
10614 | fix = fix_new (frag_now, i * 8, 4, |
10615 | section_symbol (cur_block->sec), | |
10616 | cur_block->offset, | |
10617 | FALSE, BFD_RELOC_32); | |
10618 | fix->fx_file = "<internal>"; | |
43cd72b9 | 10619 | fix->fx_line = 0; |
e0001a05 | 10620 | |
43cd72b9 | 10621 | /* Write the length. */ |
542f8b94 | 10622 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
10623 | cur_block->size, 4); |
10624 | cur_block = cur_block->next; | |
10625 | } | |
542f8b94 BW |
10626 | frag_wane (frag_now); |
10627 | frag_new (0); | |
10628 | frag_wane (frag_now); | |
43cd72b9 BW |
10629 | } |
10630 | } | |
10631 | } | |
e0001a05 NC |
10632 | } |
10633 | ||
10634 | ||
7fa3d080 BW |
10635 | static void |
10636 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10637 | const char *section_name_base, | |
10638 | xt_section_type sec_type) | |
e0001a05 NC |
10639 | { |
10640 | segT *seclist; | |
10641 | ||
10642 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10643 | Walk over each fragment. |
10644 | For each fragment that has instructions, | |
10645 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10646 | |
10647 | for (seclist = &stdoutput->sections; | |
10648 | seclist && *seclist; | |
10649 | seclist = &(*seclist)->next) | |
10650 | { | |
10651 | segT sec = *seclist; | |
43cd72b9 | 10652 | |
532f93bd | 10653 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
10654 | continue; |
10655 | ||
10656 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10657 | { |
542f8b94 BW |
10658 | segment_info_type *xt_seg_info; |
10659 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 10660 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
10661 | |
10662 | prop_sec->output_section = prop_sec; | |
10663 | subseg_set (prop_sec, 0); | |
10664 | xt_seg_info = seg_info (prop_sec); | |
10665 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10666 | ||
e0001a05 | 10667 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10668 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
10669 | } |
10670 | } | |
10671 | ||
10672 | /* Now we fill them out.... */ | |
10673 | ||
10674 | for (seclist = &stdoutput->sections; | |
10675 | seclist && *seclist; | |
10676 | seclist = &(*seclist)->next) | |
10677 | { | |
10678 | segment_info_type *seginfo; | |
10679 | xtensa_block_info *block; | |
10680 | segT sec = *seclist; | |
43cd72b9 | 10681 | |
e0001a05 NC |
10682 | seginfo = seg_info (sec); |
10683 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10684 | ||
10685 | if (block) | |
10686 | { | |
10687 | xtensa_block_info *cur_block; | |
43cd72b9 | 10688 | int num_recs = 0; |
d77b99c9 | 10689 | bfd_size_type rec_size; |
e0001a05 NC |
10690 | |
10691 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10692 | num_recs++; | |
10693 | ||
43cd72b9 | 10694 | rec_size = num_recs * (8 + 4); |
e0001a05 | 10695 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
10696 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10697 | ||
e0001a05 NC |
10698 | if (num_recs) |
10699 | { | |
e0001a05 | 10700 | char *frag_data; |
542f8b94 | 10701 | int i; |
e0001a05 | 10702 | |
542f8b94 BW |
10703 | subseg_set (sec, 0); |
10704 | frag_data = frag_more (rec_size); | |
e0001a05 | 10705 | cur_block = block; |
e0001a05 NC |
10706 | for (i = 0; i < num_recs; i++) |
10707 | { | |
542f8b94 | 10708 | fixS *fix; |
e0001a05 NC |
10709 | |
10710 | /* Write the fixup. */ | |
9c2799c2 | 10711 | gas_assert (cur_block); |
542f8b94 BW |
10712 | fix = fix_new (frag_now, i * 12, 4, |
10713 | section_symbol (cur_block->sec), | |
10714 | cur_block->offset, | |
10715 | FALSE, BFD_RELOC_32); | |
10716 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
10717 | fix->fx_line = 0; |
10718 | ||
10719 | /* Write the length. */ | |
542f8b94 | 10720 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 10721 | cur_block->size, 4); |
542f8b94 | 10722 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 10723 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 10724 | sizeof (flagword)); |
e0001a05 NC |
10725 | cur_block = cur_block->next; |
10726 | } | |
542f8b94 BW |
10727 | frag_wane (frag_now); |
10728 | frag_new (0); | |
10729 | frag_wane (frag_now); | |
e0001a05 NC |
10730 | } |
10731 | } | |
10732 | } | |
10733 | } | |
10734 | ||
10735 | ||
532f93bd BW |
10736 | static bfd_boolean |
10737 | exclude_section_from_property_tables (segT sec) | |
10738 | { | |
10739 | flagword flags = bfd_get_section_flags (stdoutput, sec); | |
10740 | ||
10741 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
10742 | if ((flags & SEC_DEBUGGING) | |
10743 | || !(flags & SEC_ALLOC) | |
10744 | || (flags & SEC_MERGE)) | |
10745 | return TRUE; | |
10746 | ||
10747 | /* Linker cie and fde optimizations mess up property entries for | |
10748 | eh_frame sections, but there is nothing inside them relevant to | |
10749 | property tables anyway. */ | |
10750 | if (strcmp (sec->name, ".eh_frame") == 0) | |
10751 | return TRUE; | |
10752 | ||
10753 | return FALSE; | |
10754 | } | |
10755 | ||
10756 | ||
7fa3d080 BW |
10757 | static bfd_boolean |
10758 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10759 | { |
10760 | segment_info_type *seginfo = seg_info (sec); | |
10761 | fragS *fragP; | |
10762 | ||
10763 | if (seginfo && seginfo->frchainP) | |
10764 | { | |
10765 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10766 | { | |
10767 | if (property_function (fragP) | |
10768 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10769 | return TRUE; | |
10770 | } | |
10771 | } | |
10772 | return FALSE; | |
10773 | } | |
10774 | ||
10775 | ||
7fa3d080 BW |
10776 | static bfd_boolean |
10777 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10778 | { |
10779 | segment_info_type *seginfo = seg_info (sec); | |
10780 | fragS *fragP; | |
10781 | ||
10782 | if (seginfo && seginfo->frchainP) | |
10783 | { | |
10784 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10785 | { | |
10786 | frag_flags prop_flags; | |
10787 | property_function (fragP, &prop_flags); | |
10788 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10789 | return TRUE; | |
10790 | } | |
10791 | } | |
10792 | return FALSE; | |
10793 | } | |
10794 | ||
10795 | ||
e0001a05 NC |
10796 | /* Two types of block sections exist right now: literal and insns. */ |
10797 | ||
7fa3d080 BW |
10798 | static void |
10799 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
10800 | xtensa_block_info **xt_block, |
10801 | frag_predicate property_function, | |
10802 | frag_predicate end_property_function) | |
e0001a05 | 10803 | { |
e0001a05 NC |
10804 | fragS *fragP; |
10805 | ||
e0001a05 NC |
10806 | /* Build it if needed. */ |
10807 | while (*xt_block != NULL) | |
10808 | xt_block = &(*xt_block)->next; | |
10809 | /* We are either at NULL at the beginning or at the end. */ | |
10810 | ||
10811 | /* Walk through the frags. */ | |
542f8b94 | 10812 | if (seg_info (sec)->frchainP) |
e0001a05 | 10813 | { |
542f8b94 | 10814 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
10815 | fragP; |
10816 | fragP = fragP->fr_next) | |
10817 | { | |
10818 | if (property_function (fragP) | |
10819 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10820 | { | |
10821 | if (*xt_block != NULL) | |
10822 | { | |
10823 | if ((*xt_block)->offset + (*xt_block)->size | |
10824 | == fragP->fr_address) | |
10825 | (*xt_block)->size += fragP->fr_fix; | |
10826 | else | |
10827 | xt_block = &((*xt_block)->next); | |
10828 | } | |
10829 | if (*xt_block == NULL) | |
10830 | { | |
43cd72b9 BW |
10831 | xtensa_block_info *new_block = (xtensa_block_info *) |
10832 | xmalloc (sizeof (xtensa_block_info)); | |
10833 | new_block->sec = sec; | |
10834 | new_block->offset = fragP->fr_address; | |
10835 | new_block->size = fragP->fr_fix; | |
10836 | new_block->next = NULL; | |
10837 | xtensa_frag_flags_init (&new_block->flags); | |
10838 | *xt_block = new_block; | |
10839 | } | |
10840 | if (end_property_function | |
10841 | && end_property_function (fragP)) | |
10842 | { | |
10843 | xt_block = &((*xt_block)->next); | |
10844 | } | |
10845 | } | |
10846 | } | |
10847 | } | |
10848 | } | |
10849 | ||
10850 | ||
10851 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10852 | ||
7fa3d080 BW |
10853 | static bfd_boolean |
10854 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10855 | { |
10856 | if (prop_flags->is_literal | |
10857 | || prop_flags->is_insn | |
10858 | || prop_flags->is_data | |
10859 | || prop_flags->is_unreachable) | |
10860 | return FALSE; | |
10861 | return TRUE; | |
10862 | } | |
10863 | ||
10864 | ||
7fa3d080 BW |
10865 | static void |
10866 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10867 | { |
10868 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10869 | } | |
10870 | ||
10871 | ||
7fa3d080 BW |
10872 | static void |
10873 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10874 | { |
10875 | xtensa_frag_flags_init (prop_flags); | |
10876 | if (fragP->tc_frag_data.is_literal) | |
10877 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
10878 | if (fragP->tc_frag_data.is_specific_opcode |
10879 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
10880 | { |
10881 | prop_flags->is_no_transform = TRUE; | |
10882 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10883 | prop_flags->is_data = TRUE; | |
10884 | } | |
43cd72b9 | 10885 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 10886 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10887 | else if (fragP->tc_frag_data.is_insn) |
10888 | { | |
10889 | prop_flags->is_insn = TRUE; | |
10890 | if (fragP->tc_frag_data.is_loop_target) | |
10891 | prop_flags->insn.is_loop_target = TRUE; | |
10892 | if (fragP->tc_frag_data.is_branch_target) | |
10893 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
10894 | if (fragP->tc_frag_data.is_no_density) |
10895 | prop_flags->insn.is_no_density = TRUE; | |
10896 | if (fragP->tc_frag_data.use_absolute_literals) | |
10897 | prop_flags->insn.is_abslit = TRUE; | |
10898 | } | |
10899 | if (fragP->tc_frag_data.is_align) | |
10900 | { | |
10901 | prop_flags->is_align = TRUE; | |
10902 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10903 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10904 | prop_flags->is_data = TRUE; | |
10905 | } | |
10906 | } | |
10907 | ||
10908 | ||
2f1bf5c1 | 10909 | static flagword |
7fa3d080 | 10910 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 10911 | { |
2f1bf5c1 | 10912 | flagword num = 0; |
43cd72b9 BW |
10913 | if (prop_flags->is_literal) |
10914 | num |= XTENSA_PROP_LITERAL; | |
10915 | if (prop_flags->is_insn) | |
10916 | num |= XTENSA_PROP_INSN; | |
10917 | if (prop_flags->is_data) | |
10918 | num |= XTENSA_PROP_DATA; | |
10919 | if (prop_flags->is_unreachable) | |
10920 | num |= XTENSA_PROP_UNREACHABLE; | |
10921 | if (prop_flags->insn.is_loop_target) | |
10922 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10923 | if (prop_flags->insn.is_branch_target) | |
10924 | { | |
10925 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10926 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10927 | } | |
10928 | ||
10929 | if (prop_flags->insn.is_no_density) | |
10930 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
10931 | if (prop_flags->is_no_transform) |
10932 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
10933 | if (prop_flags->insn.is_no_reorder) |
10934 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10935 | if (prop_flags->insn.is_abslit) | |
10936 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10937 | ||
10938 | if (prop_flags->is_align) | |
10939 | { | |
10940 | num |= XTENSA_PROP_ALIGN; | |
10941 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10942 | } | |
10943 | ||
10944 | return num; | |
10945 | } | |
10946 | ||
10947 | ||
10948 | static bfd_boolean | |
7fa3d080 BW |
10949 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10950 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10951 | { |
10952 | /* Cannot combine with an end marker. */ | |
10953 | ||
10954 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10955 | return FALSE; | |
10956 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10957 | return FALSE; | |
10958 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10959 | return FALSE; | |
10960 | ||
10961 | if (prop_flags_1->is_insn) | |
10962 | { | |
10963 | /* Properties of the beginning of the frag. */ | |
10964 | if (prop_flags_2->insn.is_loop_target) | |
10965 | return FALSE; | |
10966 | if (prop_flags_2->insn.is_branch_target) | |
10967 | return FALSE; | |
10968 | if (prop_flags_1->insn.is_no_density != | |
10969 | prop_flags_2->insn.is_no_density) | |
10970 | return FALSE; | |
99ded152 BW |
10971 | if (prop_flags_1->is_no_transform != |
10972 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
10973 | return FALSE; |
10974 | if (prop_flags_1->insn.is_no_reorder != | |
10975 | prop_flags_2->insn.is_no_reorder) | |
10976 | return FALSE; | |
10977 | if (prop_flags_1->insn.is_abslit != | |
10978 | prop_flags_2->insn.is_abslit) | |
10979 | return FALSE; | |
10980 | } | |
10981 | ||
10982 | if (prop_flags_1->is_align) | |
10983 | return FALSE; | |
10984 | ||
10985 | return TRUE; | |
10986 | } | |
10987 | ||
10988 | ||
7fa3d080 BW |
10989 | static bfd_vma |
10990 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10991 | { |
10992 | bfd_vma end_addr; | |
d77b99c9 | 10993 | unsigned align_bits; |
43cd72b9 BW |
10994 | |
10995 | if (!xt_block->flags.is_align) | |
10996 | return xt_block->size; | |
10997 | ||
10998 | end_addr = xt_block->offset + xt_block->size; | |
10999 | align_bits = xt_block->flags.alignment; | |
11000 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
11001 | return end_addr - xt_block->offset; | |
11002 | } | |
11003 | ||
11004 | ||
11005 | static bfd_boolean | |
7fa3d080 BW |
11006 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
11007 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
11008 | { |
11009 | if (xt_block->sec != xt_block_2->sec) | |
11010 | return FALSE; | |
11011 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
11012 | != xt_block_2->offset) | |
11013 | return FALSE; | |
11014 | ||
11015 | if (xt_block_2->size == 0 | |
11016 | && (!xt_block_2->flags.is_unreachable | |
11017 | || xt_block->flags.is_unreachable)) | |
11018 | { | |
11019 | if (xt_block_2->flags.is_align | |
11020 | && xt_block->flags.is_align) | |
11021 | { | |
11022 | /* Nothing needed. */ | |
11023 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
11024 | return TRUE; | |
11025 | } | |
11026 | else | |
11027 | { | |
11028 | if (xt_block_2->flags.is_align) | |
11029 | { | |
11030 | /* Push alignment to previous entry. */ | |
11031 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
11032 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
11033 | } | |
11034 | return TRUE; | |
11035 | } | |
11036 | } | |
11037 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
11038 | &xt_block_2->flags)) | |
11039 | return FALSE; | |
11040 | ||
11041 | xt_block->size += xt_block_2->size; | |
11042 | ||
11043 | if (xt_block_2->flags.is_align) | |
11044 | { | |
11045 | xt_block->flags.is_align = TRUE; | |
11046 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
11047 | } | |
11048 | ||
11049 | return TRUE; | |
11050 | } | |
11051 | ||
11052 | ||
7fa3d080 BW |
11053 | static void |
11054 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
11055 | xtensa_block_info **xt_block, |
11056 | frag_flags_fn property_function) | |
43cd72b9 | 11057 | { |
43cd72b9 BW |
11058 | fragS *fragP; |
11059 | ||
43cd72b9 BW |
11060 | /* Build it if needed. */ |
11061 | while (*xt_block != NULL) | |
11062 | { | |
11063 | xt_block = &(*xt_block)->next; | |
11064 | } | |
11065 | /* We are either at NULL at the beginning or at the end. */ | |
11066 | ||
11067 | /* Walk through the frags. */ | |
542f8b94 | 11068 | if (seg_info (sec)->frchainP) |
43cd72b9 | 11069 | { |
542f8b94 | 11070 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
11071 | fragP = fragP->fr_next) |
11072 | { | |
11073 | xtensa_block_info tmp_block; | |
11074 | tmp_block.sec = sec; | |
11075 | tmp_block.offset = fragP->fr_address; | |
11076 | tmp_block.size = fragP->fr_fix; | |
11077 | tmp_block.next = NULL; | |
11078 | property_function (fragP, &tmp_block.flags); | |
11079 | ||
11080 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
11081 | /* && fragP->fr_fix != 0) */ | |
11082 | { | |
11083 | if ((*xt_block) == NULL | |
11084 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
11085 | { | |
11086 | xtensa_block_info *new_block; | |
11087 | if ((*xt_block) != NULL) | |
11088 | xt_block = &(*xt_block)->next; | |
11089 | new_block = (xtensa_block_info *) | |
11090 | xmalloc (sizeof (xtensa_block_info)); | |
11091 | *new_block = tmp_block; | |
11092 | *xt_block = new_block; | |
11093 | } | |
11094 | } | |
11095 | } | |
11096 | } | |
11097 | } | |
11098 | ||
11099 | \f | |
11100 | /* op_placement_info_table */ | |
11101 | ||
11102 | /* op_placement_info makes it easier to determine which | |
11103 | ops can go in which slots. */ | |
11104 | ||
11105 | static void | |
7fa3d080 | 11106 | init_op_placement_info_table (void) |
43cd72b9 BW |
11107 | { |
11108 | xtensa_isa isa = xtensa_default_isa; | |
11109 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
11110 | xtensa_opcode opcode; | |
11111 | xtensa_format fmt; | |
11112 | int slot; | |
11113 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
11114 | ||
11115 | op_placement_table = (op_placement_info_table) | |
11116 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
9c2799c2 | 11117 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
11118 | |
11119 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
11120 | { | |
11121 | op_placement_info *opi = &op_placement_table[opcode]; | |
11122 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 11123 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 11124 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
11125 | opi->narrowest = XTENSA_UNDEFINED; |
11126 | opi->narrowest_size = 0x7F; | |
b2d179be | 11127 | opi->narrowest_slot = 0; |
43cd72b9 BW |
11128 | opi->formats = 0; |
11129 | opi->num_formats = 0; | |
11130 | opi->issuef = 0; | |
11131 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
11132 | { | |
11133 | opi->slots[fmt] = 0; | |
11134 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
11135 | { | |
11136 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
11137 | { | |
11138 | int fmt_length = xtensa_format_length (isa, fmt); | |
11139 | opi->issuef++; | |
11140 | set_bit (fmt, opi->formats); | |
11141 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
11142 | if (fmt_length < opi->narrowest_size |
11143 | || (fmt_length == opi->narrowest_size | |
11144 | && (xtensa_format_num_slots (isa, fmt) | |
11145 | < xtensa_format_num_slots (isa, | |
11146 | opi->narrowest)))) | |
43cd72b9 BW |
11147 | { |
11148 | opi->narrowest = fmt; | |
11149 | opi->narrowest_size = fmt_length; | |
b2d179be | 11150 | opi->narrowest_slot = slot; |
43cd72b9 | 11151 | } |
e0001a05 NC |
11152 | } |
11153 | } | |
43cd72b9 BW |
11154 | if (opi->formats) |
11155 | opi->num_formats++; | |
e0001a05 NC |
11156 | } |
11157 | } | |
43cd72b9 BW |
11158 | xtensa_insnbuf_free (isa, ibuf); |
11159 | } | |
11160 | ||
11161 | ||
11162 | bfd_boolean | |
7fa3d080 | 11163 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
11164 | { |
11165 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
11166 | } | |
11167 | ||
11168 | ||
11169 | /* If the opcode is available in a single slot format, return its size. */ | |
11170 | ||
7fa3d080 BW |
11171 | static int |
11172 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 11173 | { |
b2d179be | 11174 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
11175 | } |
11176 | ||
11177 | ||
7fa3d080 BW |
11178 | static xtensa_format |
11179 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 11180 | { |
b2d179be BW |
11181 | return op_placement_table[opcode].narrowest; |
11182 | } | |
11183 | ||
11184 | ||
11185 | static int | |
11186 | xg_get_single_slot (xtensa_opcode opcode) | |
11187 | { | |
11188 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
11189 | } |
11190 | ||
11191 | \f | |
11192 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
11193 | ||
11194 | void | |
7fa3d080 | 11195 | istack_init (IStack *stack) |
e0001a05 NC |
11196 | { |
11197 | memset (stack, 0, sizeof (IStack)); | |
11198 | stack->ninsn = 0; | |
11199 | } | |
11200 | ||
11201 | ||
11202 | bfd_boolean | |
7fa3d080 | 11203 | istack_empty (IStack *stack) |
e0001a05 NC |
11204 | { |
11205 | return (stack->ninsn == 0); | |
11206 | } | |
11207 | ||
11208 | ||
11209 | bfd_boolean | |
7fa3d080 | 11210 | istack_full (IStack *stack) |
e0001a05 NC |
11211 | { |
11212 | return (stack->ninsn == MAX_ISTACK); | |
11213 | } | |
11214 | ||
11215 | ||
11216 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 11217 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
11218 | |
11219 | TInsn * | |
7fa3d080 | 11220 | istack_top (IStack *stack) |
e0001a05 NC |
11221 | { |
11222 | int rec = stack->ninsn - 1; | |
9c2799c2 | 11223 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
11224 | return &stack->insn[rec]; |
11225 | } | |
11226 | ||
11227 | ||
11228 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 11229 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11230 | |
11231 | void | |
7fa3d080 | 11232 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
11233 | { |
11234 | int rec = stack->ninsn; | |
9c2799c2 | 11235 | gas_assert (!istack_full (stack)); |
43cd72b9 | 11236 | stack->insn[rec] = *insn; |
e0001a05 NC |
11237 | stack->ninsn++; |
11238 | } | |
11239 | ||
11240 | ||
11241 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11242 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11243 | |
11244 | TInsn * | |
7fa3d080 | 11245 | istack_push_space (IStack *stack) |
e0001a05 NC |
11246 | { |
11247 | int rec = stack->ninsn; | |
11248 | TInsn *insn; | |
9c2799c2 | 11249 | gas_assert (!istack_full (stack)); |
e0001a05 | 11250 | insn = &stack->insn[rec]; |
60242db2 | 11251 | tinsn_init (insn); |
e0001a05 NC |
11252 | stack->ninsn++; |
11253 | return insn; | |
11254 | } | |
11255 | ||
11256 | ||
11257 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11258 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11259 | |
11260 | void | |
7fa3d080 | 11261 | istack_pop (IStack *stack) |
e0001a05 NC |
11262 | { |
11263 | int rec = stack->ninsn - 1; | |
9c2799c2 | 11264 | gas_assert (!istack_empty (stack)); |
e0001a05 | 11265 | stack->ninsn--; |
60242db2 | 11266 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11267 | } |
11268 | ||
11269 | \f | |
11270 | /* TInsn functions. */ | |
11271 | ||
11272 | void | |
7fa3d080 | 11273 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11274 | { |
11275 | memset (dst, 0, sizeof (TInsn)); | |
11276 | } | |
11277 | ||
11278 | ||
43cd72b9 | 11279 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11280 | |
11281 | static bfd_boolean | |
7fa3d080 | 11282 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11283 | { |
11284 | int i; | |
11285 | int n = insn->ntok; | |
11286 | ||
9c2799c2 | 11287 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
11288 | |
11289 | for (i = 0; i < n; ++i) | |
11290 | { | |
11291 | switch (insn->tok[i].X_op) | |
11292 | { | |
11293 | case O_register: | |
11294 | case O_constant: | |
11295 | break; | |
11296 | default: | |
11297 | return TRUE; | |
11298 | } | |
11299 | } | |
11300 | return FALSE; | |
11301 | } | |
11302 | ||
11303 | ||
11304 | bfd_boolean | |
7fa3d080 | 11305 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11306 | { |
43cd72b9 | 11307 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11308 | int i; |
11309 | int n = insn->ntok; | |
11310 | ||
9c2799c2 | 11311 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
11312 | |
11313 | for (i = 0; i < n; ++i) | |
11314 | { | |
11315 | switch (insn->tok[i].X_op) | |
11316 | { | |
11317 | case O_register: | |
11318 | case O_constant: | |
11319 | break; | |
43cd72b9 BW |
11320 | case O_big: |
11321 | case O_illegal: | |
11322 | case O_absent: | |
11323 | /* Errors for these types are caught later. */ | |
11324 | break; | |
11325 | case O_hi16: | |
11326 | case O_lo16: | |
e0001a05 | 11327 | default: |
43cd72b9 BW |
11328 | /* Symbolic immediates are only allowed on the last immediate |
11329 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11330 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11331 | if (i != get_relaxable_immed (insn->opcode) |
11332 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11333 | && insn->opcode != xtensa_const16_opcode)) | |
11334 | { | |
431ad2d0 | 11335 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11336 | return TRUE; |
11337 | } | |
e0001a05 NC |
11338 | } |
11339 | } | |
11340 | return FALSE; | |
11341 | } | |
11342 | ||
11343 | ||
11344 | /* For assembly code with complex expressions (e.g. subtraction), | |
11345 | we have to build them in the literal pool so that | |
11346 | their results are calculated correctly after relaxation. | |
11347 | The relaxation only handles expressions that | |
11348 | boil down to SYMBOL + OFFSET. */ | |
11349 | ||
11350 | static bfd_boolean | |
7fa3d080 | 11351 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11352 | { |
11353 | int i; | |
11354 | int n = insn->ntok; | |
9c2799c2 | 11355 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
11356 | for (i = 0; i < n; ++i) |
11357 | { | |
11358 | switch (insn->tok[i].X_op) | |
11359 | { | |
11360 | case O_register: | |
11361 | case O_constant: | |
11362 | case O_symbol: | |
43cd72b9 BW |
11363 | case O_lo16: |
11364 | case O_hi16: | |
e0001a05 NC |
11365 | break; |
11366 | default: | |
11367 | return TRUE; | |
11368 | } | |
11369 | } | |
11370 | return FALSE; | |
11371 | } | |
11372 | ||
11373 | ||
b2d179be BW |
11374 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11375 | Return TRUE if there is a symbol in the immediate field. This | |
11376 | function assumes that: | |
11377 | 1) The number of operands are correct. | |
11378 | 2) The insn_type is ITYPE_INSN. | |
11379 | 3) The opcode can be encoded in the specified format and slot. | |
11380 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11381 | |
11382 | static bfd_boolean | |
7fa3d080 BW |
11383 | tinsn_to_slotbuf (xtensa_format fmt, |
11384 | int slot, | |
11385 | TInsn *tinsn, | |
11386 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11387 | { |
11388 | xtensa_isa isa = xtensa_default_isa; | |
11389 | xtensa_opcode opcode = tinsn->opcode; | |
11390 | bfd_boolean has_fixup = FALSE; | |
11391 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11392 | int i; | |
11393 | ||
9c2799c2 | 11394 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
11395 | if (noperands != tinsn->ntok) |
11396 | as_fatal (_("operand number mismatch")); | |
11397 | ||
11398 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11399 | { | |
11400 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11401 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11402 | return FALSE; | |
11403 | } | |
11404 | ||
11405 | for (i = 0; i < noperands; i++) | |
11406 | { | |
91d6fa6a | 11407 | expressionS *exp = &tinsn->tok[i]; |
d77b99c9 BW |
11408 | int rc; |
11409 | unsigned line; | |
43cd72b9 BW |
11410 | char *file_name; |
11411 | uint32 opnd_value; | |
11412 | ||
91d6fa6a | 11413 | switch (exp->X_op) |
43cd72b9 BW |
11414 | { |
11415 | case O_register: | |
11416 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11417 | break; | |
11418 | /* The register number has already been checked in | |
11419 | expression_maybe_register, so we don't need to check here. */ | |
91d6fa6a | 11420 | opnd_value = exp->X_add_number; |
43cd72b9 BW |
11421 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
11422 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11423 | opnd_value); | |
11424 | if (rc != 0) | |
11425 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11426 | break; | |
11427 | ||
11428 | case O_constant: | |
11429 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11430 | break; | |
11431 | as_where (&file_name, &line); | |
11432 | /* It is a constant and we called this function | |
11433 | then we have to try to fit it. */ | |
11434 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
91d6fa6a | 11435 | exp->X_add_number, file_name, line); |
e0001a05 NC |
11436 | break; |
11437 | ||
e0001a05 NC |
11438 | default: |
11439 | has_fixup = TRUE; | |
11440 | break; | |
11441 | } | |
11442 | } | |
43cd72b9 | 11443 | |
e0001a05 NC |
11444 | return has_fixup; |
11445 | } | |
11446 | ||
11447 | ||
b2d179be BW |
11448 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11449 | into a multi-slot instruction, fill the other slots with NOPs. | |
11450 | Return TRUE if there is a symbol in the immediate field. See also the | |
11451 | assumptions listed for tinsn_to_slotbuf. */ | |
11452 | ||
11453 | static bfd_boolean | |
11454 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11455 | { | |
11456 | static xtensa_insnbuf slotbuf = 0; | |
11457 | static vliw_insn vinsn; | |
11458 | xtensa_isa isa = xtensa_default_isa; | |
11459 | bfd_boolean has_fixup = FALSE; | |
11460 | int i; | |
11461 | ||
11462 | if (!slotbuf) | |
11463 | { | |
11464 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11465 | xg_init_vinsn (&vinsn); | |
11466 | } | |
11467 | ||
11468 | xg_clear_vinsn (&vinsn); | |
11469 | ||
11470 | bundle_tinsn (tinsn, &vinsn); | |
11471 | ||
11472 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11473 | ||
11474 | for (i = 0; i < vinsn.num_slots; i++) | |
11475 | { | |
11476 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11477 | has_fixup |= | |
11478 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11479 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11480 | } | |
11481 | ||
11482 | return has_fixup; | |
11483 | } | |
11484 | ||
11485 | ||
43cd72b9 | 11486 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11487 | |
7fa3d080 BW |
11488 | static bfd_boolean |
11489 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11490 | { |
11491 | xtensa_isa isa = xtensa_default_isa; | |
11492 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
11493 | xtensa_regfile t1_regfile, t2_regfile; |
11494 | int t1_reg, t2_reg; | |
11495 | int t1_base_reg, t1_last_reg; | |
11496 | int t2_base_reg, t2_last_reg; | |
11497 | char t1_inout, t2_inout; | |
11498 | int i, j; | |
e0001a05 NC |
11499 | |
11500 | if (opcode == XTENSA_UNDEFINED) | |
11501 | { | |
11502 | as_bad (_("invalid opcode")); | |
11503 | return TRUE; | |
11504 | } | |
11505 | ||
43cd72b9 | 11506 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11507 | { |
11508 | as_bad (_("too few operands")); | |
11509 | return TRUE; | |
11510 | } | |
11511 | ||
43cd72b9 | 11512 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11513 | { |
11514 | as_bad (_("too many operands")); | |
11515 | return TRUE; | |
11516 | } | |
6dc6b655 BW |
11517 | |
11518 | /* Check registers. */ | |
11519 | for (j = 0; j < insn->ntok; j++) | |
11520 | { | |
11521 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
11522 | continue; | |
11523 | ||
11524 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
11525 | t2_base_reg = insn->tok[j].X_add_number; | |
11526 | t2_last_reg | |
11527 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
11528 | ||
11529 | for (i = 0; i < insn->ntok; i++) | |
11530 | { | |
11531 | if (i == j) | |
11532 | continue; | |
11533 | ||
11534 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
11535 | continue; | |
11536 | ||
11537 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
11538 | ||
11539 | if (t1_regfile != t2_regfile) | |
11540 | continue; | |
11541 | ||
11542 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
11543 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
11544 | ||
11545 | t1_base_reg = insn->tok[i].X_add_number; | |
11546 | t1_last_reg = (t1_base_reg | |
11547 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
11548 | ||
11549 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
11550 | { | |
11551 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
11552 | { | |
11553 | if (t1_reg != t2_reg) | |
11554 | continue; | |
11555 | ||
11556 | if (t1_inout != 'i' && t2_inout != 'i') | |
11557 | { | |
11558 | as_bad (_("multiple writes to the same register")); | |
11559 | return TRUE; | |
11560 | } | |
11561 | } | |
11562 | } | |
11563 | } | |
11564 | } | |
e0001a05 NC |
11565 | return FALSE; |
11566 | } | |
11567 | ||
11568 | ||
11569 | /* Load an instruction from its encoded form. */ | |
11570 | ||
11571 | static void | |
7fa3d080 | 11572 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11573 | { |
43cd72b9 | 11574 | vliw_insn vinsn; |
e0001a05 | 11575 | |
43cd72b9 BW |
11576 | xg_init_vinsn (&vinsn); |
11577 | vinsn_from_chars (&vinsn, f); | |
11578 | ||
11579 | *tinsn = vinsn.slots[slot]; | |
11580 | xg_free_vinsn (&vinsn); | |
11581 | } | |
e0001a05 | 11582 | |
43cd72b9 BW |
11583 | |
11584 | static void | |
7fa3d080 BW |
11585 | tinsn_from_insnbuf (TInsn *tinsn, |
11586 | xtensa_insnbuf slotbuf, | |
11587 | xtensa_format fmt, | |
11588 | int slot) | |
43cd72b9 BW |
11589 | { |
11590 | int i; | |
11591 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11592 | |
11593 | /* Find the immed. */ | |
43cd72b9 BW |
11594 | tinsn_init (tinsn); |
11595 | tinsn->insn_type = ITYPE_INSN; | |
11596 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11597 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11598 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11599 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11600 | { |
43cd72b9 BW |
11601 | set_expr_const (&tinsn->tok[i], |
11602 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11603 | tinsn->opcode, i)); | |
e0001a05 NC |
11604 | } |
11605 | } | |
11606 | ||
11607 | ||
11608 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11609 | ||
11610 | static void | |
7fa3d080 | 11611 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11612 | { |
43cd72b9 | 11613 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11614 | int opnum; |
11615 | ||
43cd72b9 | 11616 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11617 | { |
11618 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 11619 | gas_assert (opnum >= 0); |
e7da6241 BW |
11620 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11621 | fragP->tc_frag_data.slot_symbols[slot], | |
11622 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 11623 | } |
19e8f41a | 11624 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
11625 | } |
11626 | ||
11627 | ||
11628 | static int | |
7fa3d080 | 11629 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11630 | { |
11631 | int i; | |
11632 | int text_bytes = 0; | |
11633 | ||
11634 | for (i = 0; i < istack->ninsn; i++) | |
11635 | { | |
43cd72b9 BW |
11636 | TInsn *tinsn = &istack->insn[i]; |
11637 | if (tinsn->insn_type == ITYPE_INSN) | |
11638 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11639 | } |
11640 | return text_bytes; | |
11641 | } | |
11642 | ||
11643 | ||
11644 | static int | |
7fa3d080 | 11645 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11646 | { |
11647 | int i; | |
11648 | int lit_bytes = 0; | |
11649 | ||
11650 | for (i = 0; i < istack->ninsn; i++) | |
11651 | { | |
43cd72b9 BW |
11652 | TInsn *tinsn = &istack->insn[i]; |
11653 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11654 | lit_bytes += 4; |
11655 | } | |
11656 | return lit_bytes; | |
11657 | } | |
11658 | ||
43cd72b9 BW |
11659 | \f |
11660 | /* vliw_insn functions. */ | |
11661 | ||
7fa3d080 BW |
11662 | static void |
11663 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11664 | { |
11665 | int i; | |
11666 | xtensa_isa isa = xtensa_default_isa; | |
11667 | ||
11668 | xg_clear_vinsn (v); | |
11669 | ||
11670 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11671 | if (v->insnbuf == NULL) | |
11672 | as_fatal (_("out of memory")); | |
11673 | ||
62af60e2 | 11674 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 11675 | { |
43cd72b9 BW |
11676 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11677 | if (v->slotbuf[i] == NULL) | |
11678 | as_fatal (_("out of memory")); | |
11679 | } | |
11680 | } | |
11681 | ||
11682 | ||
7fa3d080 BW |
11683 | static void |
11684 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11685 | { |
11686 | int i; | |
65738a7d | 11687 | |
62af60e2 SA |
11688 | memset (v, 0, offsetof (vliw_insn, slots) |
11689 | + sizeof(TInsn) * config_max_slots); | |
65738a7d | 11690 | |
43cd72b9 BW |
11691 | v->format = XTENSA_UNDEFINED; |
11692 | v->num_slots = 0; | |
11693 | v->inside_bundle = FALSE; | |
11694 | ||
11695 | if (xt_saved_debug_type != DEBUG_NONE) | |
11696 | debug_type = xt_saved_debug_type; | |
11697 | ||
62af60e2 | 11698 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 11699 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11700 | } |
11701 | ||
11702 | ||
d8392fd9 SA |
11703 | static void |
11704 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
11705 | { | |
11706 | memcpy (dst, src, | |
11707 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); | |
11708 | dst->insnbuf = src->insnbuf; | |
11709 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
11710 | } | |
11711 | ||
11712 | ||
7fa3d080 BW |
11713 | static bfd_boolean |
11714 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11715 | { |
11716 | int i; | |
c138bc38 | 11717 | |
43cd72b9 BW |
11718 | for (i = 0; i < v->num_slots; i++) |
11719 | { | |
11720 | if (v->slots[i].is_specific_opcode) | |
11721 | return TRUE; | |
11722 | } | |
11723 | return FALSE; | |
11724 | } | |
11725 | ||
11726 | ||
7fa3d080 BW |
11727 | static void |
11728 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11729 | { |
11730 | int i; | |
11731 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 11732 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
11733 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
11734 | } | |
11735 | ||
11736 | ||
e7da6241 BW |
11737 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11738 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11739 | |
11740 | static bfd_boolean | |
7fa3d080 BW |
11741 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11742 | char *frag_offset, | |
11743 | fragS *fragP, | |
11744 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11745 | { |
11746 | xtensa_isa isa = xtensa_default_isa; | |
11747 | xtensa_format fmt = vinsn->format; | |
11748 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11749 | int slot; | |
11750 | bfd_boolean has_fixup = FALSE; | |
11751 | ||
11752 | xtensa_format_encode (isa, fmt, insnbuf); | |
11753 | ||
11754 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11755 | { | |
11756 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 11757 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
11758 | bfd_boolean tinsn_has_fixup = |
11759 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11760 | vinsn->slotbuf[slot]); | |
11761 | ||
11762 | xtensa_format_set_slot (isa, fmt, slot, | |
11763 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 11764 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
11765 | { |
11766 | if (vinsn->num_slots != 1) | |
11767 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
11768 | else if (record_fixup) | |
11769 | /* Instructions that generate TLS relocations should always be | |
11770 | relaxed in the front-end. If "record_fixup" is set, then this | |
11771 | function is being called during back-end relaxation, so flag | |
11772 | the unexpected behavior as an error. */ | |
11773 | as_bad (_("unexpected TLS relocation")); | |
11774 | else | |
11775 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
11776 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
11777 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
11778 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 11779 | } |
e7da6241 | 11780 | if (tinsn_has_fixup) |
43cd72b9 BW |
11781 | { |
11782 | int i; | |
11783 | xtensa_opcode opcode = tinsn->opcode; | |
11784 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11785 | has_fixup = TRUE; | |
11786 | ||
11787 | for (i = 0; i < noperands; i++) | |
11788 | { | |
91d6fa6a NC |
11789 | expressionS* exp = &tinsn->tok[i]; |
11790 | switch (exp->X_op) | |
43cd72b9 BW |
11791 | { |
11792 | case O_symbol: | |
11793 | case O_lo16: | |
11794 | case O_hi16: | |
11795 | if (get_relaxable_immed (opcode) == i) | |
11796 | { | |
e7da6241 BW |
11797 | /* Add a fix record for the instruction, except if this |
11798 | function is being called prior to relaxation, i.e., | |
11799 | if record_fixup is false, and the instruction might | |
11800 | be relaxed later. */ | |
11801 | if (record_fixup | |
11802 | || tinsn->is_specific_opcode | |
11803 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11804 | { |
91d6fa6a | 11805 | xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, |
e7da6241 | 11806 | frag_offset - fragP->fr_literal); |
43cd72b9 BW |
11807 | } |
11808 | else | |
11809 | { | |
91d6fa6a | 11810 | if (exp->X_op != O_symbol) |
e7da6241 | 11811 | as_bad (_("invalid operand")); |
91d6fa6a NC |
11812 | tinsn->symbol = exp->X_add_symbol; |
11813 | tinsn->offset = exp->X_add_number; | |
43cd72b9 BW |
11814 | } |
11815 | } | |
11816 | else | |
e7da6241 | 11817 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11818 | break; |
11819 | ||
11820 | case O_constant: | |
11821 | case O_register: | |
11822 | break; | |
11823 | ||
43cd72b9 | 11824 | default: |
e7da6241 | 11825 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11826 | break; |
11827 | } | |
11828 | } | |
11829 | } | |
11830 | } | |
11831 | ||
11832 | return has_fixup; | |
11833 | } | |
11834 | ||
11835 | ||
11836 | static void | |
7fa3d080 | 11837 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11838 | { |
11839 | static xtensa_insnbuf insnbuf = NULL; | |
11840 | static xtensa_insnbuf slotbuf = NULL; | |
11841 | int i; | |
11842 | xtensa_format fmt; | |
11843 | xtensa_isa isa = xtensa_default_isa; | |
11844 | ||
11845 | if (!insnbuf) | |
11846 | { | |
11847 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11848 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11849 | } | |
11850 | ||
d77b99c9 | 11851 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11852 | fmt = xtensa_format_decode (isa, insnbuf); |
11853 | if (fmt == XTENSA_UNDEFINED) | |
11854 | as_fatal (_("cannot decode instruction format")); | |
11855 | vinsn->format = fmt; | |
11856 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11857 | ||
11858 | for (i = 0; i < vinsn->num_slots; i++) | |
11859 | { | |
11860 | TInsn *tinsn = &vinsn->slots[i]; | |
11861 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11862 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11863 | } | |
11864 | } | |
11865 | ||
e0001a05 NC |
11866 | \f |
11867 | /* Expression utilities. */ | |
11868 | ||
43cd72b9 | 11869 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11870 | |
11871 | bfd_boolean | |
7fa3d080 | 11872 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11873 | { |
11874 | return (s->X_op == O_constant); | |
11875 | } | |
11876 | ||
11877 | ||
11878 | /* Get the expression constant. | |
43cd72b9 | 11879 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11880 | |
11881 | offsetT | |
7fa3d080 | 11882 | get_expr_const (const expressionS *s) |
e0001a05 | 11883 | { |
9c2799c2 | 11884 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
11885 | return s->X_add_number; |
11886 | } | |
11887 | ||
11888 | ||
11889 | /* Set the expression to a constant value. */ | |
11890 | ||
11891 | void | |
7fa3d080 | 11892 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11893 | { |
11894 | s->X_op = O_constant; | |
11895 | s->X_add_number = val; | |
11896 | s->X_add_symbol = NULL; | |
11897 | s->X_op_symbol = NULL; | |
11898 | } | |
11899 | ||
11900 | ||
43cd72b9 | 11901 | bfd_boolean |
7fa3d080 | 11902 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11903 | { |
11904 | return (s->X_op == O_register); | |
11905 | } | |
11906 | ||
11907 | ||
11908 | /* Get the expression constant. | |
11909 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11910 | ||
11911 | offsetT | |
7fa3d080 | 11912 | get_expr_register (const expressionS *s) |
43cd72b9 | 11913 | { |
9c2799c2 | 11914 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
11915 | return s->X_add_number; |
11916 | } | |
11917 | ||
11918 | ||
e0001a05 NC |
11919 | /* Set the expression to a symbol + constant offset. */ |
11920 | ||
11921 | void | |
7fa3d080 | 11922 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11923 | { |
11924 | s->X_op = O_symbol; | |
11925 | s->X_add_symbol = sym; | |
11926 | s->X_op_symbol = NULL; /* unused */ | |
11927 | s->X_add_number = offset; | |
11928 | } | |
11929 | ||
11930 | ||
43cd72b9 BW |
11931 | /* Return TRUE if the two expressions are equal. */ |
11932 | ||
e0001a05 | 11933 | bfd_boolean |
7fa3d080 | 11934 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11935 | { |
11936 | if (s1->X_op != s2->X_op) | |
11937 | return FALSE; | |
11938 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11939 | return FALSE; | |
11940 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11941 | return FALSE; | |
11942 | if (s1->X_add_number != s2->X_add_number) | |
11943 | return FALSE; | |
11944 | return TRUE; | |
11945 | } | |
11946 | ||
11947 | ||
11948 | static void | |
7fa3d080 | 11949 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11950 | { |
11951 | memcpy (dst, src, sizeof (expressionS)); | |
11952 | } | |
11953 | ||
11954 | \f | |
9456465c | 11955 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11956 | |
11957 | struct rename_section_struct | |
11958 | { | |
11959 | char *old_name; | |
11960 | char *new_name; | |
11961 | struct rename_section_struct *next; | |
11962 | }; | |
11963 | ||
11964 | static struct rename_section_struct *section_rename; | |
11965 | ||
11966 | ||
9456465c BW |
11967 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11968 | entries to the section_rename list. Note: Specifying multiple | |
11969 | renamings separated by colons is not documented and is retained only | |
11970 | for backward compatibility. */ | |
e0001a05 | 11971 | |
7fa3d080 BW |
11972 | static void |
11973 | build_section_rename (const char *arg) | |
e0001a05 | 11974 | { |
9456465c | 11975 | struct rename_section_struct *r; |
e0001a05 NC |
11976 | char *this_arg = NULL; |
11977 | char *next_arg = NULL; | |
11978 | ||
9456465c | 11979 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11980 | { |
9456465c BW |
11981 | char *old_name, *new_name; |
11982 | ||
e0001a05 NC |
11983 | if (this_arg) |
11984 | { | |
11985 | next_arg = strchr (this_arg, ':'); | |
11986 | if (next_arg) | |
11987 | { | |
11988 | *next_arg = '\0'; | |
11989 | next_arg++; | |
11990 | } | |
11991 | } | |
e0001a05 | 11992 | |
9456465c BW |
11993 | old_name = this_arg; |
11994 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11995 | |
9456465c BW |
11996 | if (*old_name == '\0') |
11997 | { | |
11998 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11999 | continue; | |
12000 | } | |
12001 | if (!new_name || new_name[1] == '\0') | |
12002 | { | |
12003 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
12004 | old_name); | |
12005 | continue; | |
12006 | } | |
12007 | *new_name = '\0'; | |
12008 | new_name++; | |
e0001a05 | 12009 | |
9456465c BW |
12010 | /* Check for invalid section renaming. */ |
12011 | for (r = section_rename; r != NULL; r = r->next) | |
12012 | { | |
12013 | if (strcmp (r->old_name, old_name) == 0) | |
12014 | as_bad (_("section %s renamed multiple times"), old_name); | |
12015 | if (strcmp (r->new_name, new_name) == 0) | |
12016 | as_bad (_("multiple sections remapped to output section %s"), | |
12017 | new_name); | |
12018 | } | |
e0001a05 | 12019 | |
9456465c BW |
12020 | /* Now add it. */ |
12021 | r = (struct rename_section_struct *) | |
12022 | xmalloc (sizeof (struct rename_section_struct)); | |
12023 | r->old_name = xstrdup (old_name); | |
12024 | r->new_name = xstrdup (new_name); | |
12025 | r->next = section_rename; | |
12026 | section_rename = r; | |
e0001a05 | 12027 | } |
e0001a05 NC |
12028 | } |
12029 | ||
12030 | ||
9456465c BW |
12031 | char * |
12032 | xtensa_section_rename (char *name) | |
e0001a05 NC |
12033 | { |
12034 | struct rename_section_struct *r = section_rename; | |
12035 | ||
12036 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
12037 | { |
12038 | if (strcmp (r->old_name, name) == 0) | |
12039 | return r->new_name; | |
12040 | } | |
e0001a05 NC |
12041 | |
12042 | return name; | |
12043 | } |