Update copyright years
[deliverable/binutils-gdb.git] / gas / config / tc-xtensa.h
CommitLineData
e0001a05 1/* tc-xtensa.h -- Header file for tc-xtensa.c.
4b95cf5c 2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
e0001a05
NC
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
e0001a05
NC
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
e0001a05
NC
20
21#ifndef TC_XTENSA
22#define TC_XTENSA 1
23
e0001a05 24struct fix;
e0001a05 25
e0001a05
NC
26#ifndef OBJ_ELF
27#error Xtensa support requires ELF object format
28#endif
29
43cd72b9 30#include "xtensa-isa.h"
e0001a05
NC
31#include "xtensa-config.h"
32
33#define TARGET_BYTES_BIG_ENDIAN XCHAL_HAVE_BE
34
35
43cd72b9 36/* Maximum number of opcode slots in a VLIW instruction. */
b08b5071 37#define MAX_SLOTS 15
43cd72b9
BW
38
39
40/* For all xtensa relax states except RELAX_DESIRE_ALIGN and
41 RELAX_DESIRE_ALIGN_IF_TARGET, the amount a frag might grow is stored
42 in the fr_var field. For the two exceptions, fr_var is a float value
43 that records the frequency with which the following instruction is
44 executed as a branch target. The aligner uses this information to
45 tell which targets are most important to be aligned. */
46
47enum xtensa_relax_statesE
48{
58502fec
BW
49 RELAX_XTENSA_NONE,
50
43cd72b9
BW
51 RELAX_ALIGN_NEXT_OPCODE,
52 /* Use the first opcode of the next fragment to determine the
53 alignment requirements. This is ONLY used for LOOPs currently. */
54
55 RELAX_CHECK_ALIGN_NEXT_OPCODE,
56 /* The next non-empty frag contains a loop instruction. Check to see
57 if it is correctly aligned, but do not align it. */
58
59 RELAX_DESIRE_ALIGN_IF_TARGET,
60 /* These are placed in front of labels and converted to either
61 RELAX_DESIRE_ALIGN / RELAX_LOOP_END or rs_fill of 0 before
62 relaxation begins. */
63
64 RELAX_ADD_NOP_IF_A0_B_RETW,
65 /* These are placed in front of conditional branches. Before
66 relaxation begins, they are turned into either NOPs for branches
67 immediately followed by RETW or RETW.N or rs_fills of 0. This is
68 used to avoid a hardware bug in some early versions of the
69 processor. */
70
71 RELAX_ADD_NOP_IF_PRE_LOOP_END,
72 /* These are placed after JX instructions. Before relaxation begins,
73 they are turned into either NOPs, if the JX is one instruction
74 before a loop end label, or rs_fills of 0. This is used to avoid a
75 hardware interlock issue prior to Xtensa version T1040. */
76
77 RELAX_ADD_NOP_IF_SHORT_LOOP,
78 /* These are placed after LOOP instructions and turned into NOPs when:
79 (1) there are less than 3 instructions in the loop; we place 2 of
80 these in a row to add up to 2 NOPS in short loops; or (2) the
81 instructions in the loop do not include a branch or jump.
82 Otherwise they are turned into rs_fills of 0 before relaxation
83 begins. This is used to avoid hardware bug PR3830. */
84
85 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
86 /* These are placed after LOOP instructions and turned into NOPs if
87 there are less than 12 bytes to the end of some other loop's end.
88 Otherwise they are turned into rs_fills of 0 before relaxation
89 begins. This is used to avoid hardware bug PR3830. */
90
91 RELAX_DESIRE_ALIGN,
92 /* The next fragment would like its first instruction to NOT cross an
93 instruction fetch boundary. */
94
95 RELAX_MAYBE_DESIRE_ALIGN,
96 /* The next fragment might like its first instruction to NOT cross an
97 instruction fetch boundary. These are placed after a branch that
98 might be relaxed. If the branch is relaxed, then this frag will be
99 a branch target and this frag will be changed to RELAX_DESIRE_ALIGN
100 frag. */
101
102 RELAX_LOOP_END,
103 /* This will be turned into a NOP or NOP.N if the previous instruction
104 is expanded to negate a loop. */
105
106 RELAX_LOOP_END_ADD_NOP,
107 /* When the code density option is available, this will generate a
108 NOP.N marked RELAX_NARROW. Otherwise, it will create an rs_fill
3b492825
BW
109 fragment with a NOP in it. Once a frag has been converted to
110 RELAX_LOOP_END_ADD_NOP, it should never be changed back to
111 RELAX_LOOP_END. */
43cd72b9
BW
112
113 RELAX_LITERAL,
114 /* Another fragment could generate an expansion here but has not yet. */
115
116 RELAX_LITERAL_NR,
117 /* Expansion has been generated by an instruction that generates a
118 literal. However, the stretch has NOT been reported yet in this
119 fragment. */
120
121 RELAX_LITERAL_FINAL,
122 /* Expansion has been generated by an instruction that generates a
123 literal. */
124
125 RELAX_LITERAL_POOL_BEGIN,
126 RELAX_LITERAL_POOL_END,
127 /* Technically these are not relaxations at all but mark a location
128 to store literals later. Note that fr_var stores the frchain for
129 BEGIN frags and fr_var stores now_seg for END frags. */
130
131 RELAX_NARROW,
132 /* The last instruction in this fragment (at->fr_opcode) can be
133 freely replaced with a single wider instruction if a future
134 alignment desires or needs it. */
135
136 RELAX_IMMED,
137 /* The last instruction in this fragment (at->fr_opcode) contains
b81bf389
BW
138 an immediate or symbol. If the value does not fit, relax the
139 opcode using expansions from the relax table. */
c138bc38 140
43cd72b9
BW
141 RELAX_IMMED_STEP1,
142 /* The last instruction in this fragment (at->fr_opcode) contains a
b81bf389 143 literal. It has already been expanded 1 step. */
43cd72b9
BW
144
145 RELAX_IMMED_STEP2,
146 /* The last instruction in this fragment (at->fr_opcode) contains a
b81bf389
BW
147 literal. It has already been expanded 2 steps. */
148
149 RELAX_IMMED_STEP3,
150 /* The last instruction in this fragment (at->fr_opcode) contains a
151 literal. It has already been expanded 3 steps. */
43cd72b9
BW
152
153 RELAX_SLOTS,
154 /* There are instructions within the last VLIW instruction that need
155 relaxation. Find the relaxation based on the slot info in
156 xtensa_frag_type. Relaxations that deal with particular opcodes
157 are slot-based (e.g., converting a MOVI to an L32R). Relaxations
158 that deal with entire instructions, such as alignment, are not
159 slot-based. */
160
161 RELAX_FILL_NOP,
162 /* This marks the location of a pipeline stall. We can fill these guys
163 in for alignment of any size. */
164
165 RELAX_UNREACHABLE,
166 /* This marks the location as unreachable. The assembler may widen or
167 narrow this area to meet alignment requirements of nearby
168 instructions. */
169
170 RELAX_MAYBE_UNREACHABLE,
171 /* This marks the location as possibly unreachable. These are placed
172 after a branch that may be relaxed into a branch and jump. If the
c138bc38 173 branch is relaxed, then this frag will be converted to a
43cd72b9
BW
174 RELAX_UNREACHABLE frag. */
175
99ded152
BW
176 RELAX_ORG,
177 /* This marks the location as having previously been an rs_org frag.
178 rs_org frags are converted to fill-zero frags immediately after
179 relaxation. However, we need to remember where they were so we can
180 prevent the linker from changing the size of any frag between the
181 section start and the org frag. */
182
43cd72b9
BW
183 RELAX_NONE
184};
185
186/* This is used as a stopper to bound the number of steps that
187 can be taken. */
b81bf389 188#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP3 - RELAX_IMMED)
43cd72b9 189
e0001a05
NC
190struct xtensa_frag_type
191{
43cd72b9
BW
192 /* Info about the current state of assembly, e.g., transform,
193 absolute_literals, etc. These need to be passed to the backend and
194 then to the object file.
195
196 When is_assembly_state_set is false, the frag inherits some of the
197 state settings from the previous frag in this segment. Because it
198 is not possible to intercept all fragment closures (frag_more and
199 frag_append_1_char can close a frag), we use a pass after initial
200 assembly to fill in the assembly states. */
201
202 unsigned int is_assembly_state_set : 1;
203 unsigned int is_no_density : 1;
204 unsigned int is_no_transform : 1;
7c834684 205 unsigned int use_longcalls : 1;
43cd72b9
BW
206 unsigned int use_absolute_literals : 1;
207
208 /* Inhibits relaxation of machine-dependent alignment frags the
209 first time through a relaxation.... */
210 unsigned int relax_seen : 1;
211
0fa77c95 212 /* Information that is needed in the object file and set when known. */
43cd72b9
BW
213 unsigned int is_literal : 1;
214 unsigned int is_loop_target : 1;
215 unsigned int is_branch_target : 1;
216 unsigned int is_insn : 1;
217 unsigned int is_unreachable : 1;
e0001a05 218
43cd72b9 219 unsigned int is_specific_opcode : 1; /* also implies no_transform */
e0001a05 220
43cd72b9
BW
221 unsigned int is_align : 1;
222 unsigned int is_text_align : 1;
223 unsigned int alignment : 5;
224
225 /* A frag with this bit set is the first in a loop that actually
226 contains an instruction. */
227 unsigned int is_first_loop_insn : 1;
e0001a05 228
b5e4a23d
BW
229 /* A frag with this bit set is a branch that we are using to
230 align branch targets as if it were a normal narrow instruction. */
231 unsigned int is_aligning_branch : 1;
232
e0001a05
NC
233 /* For text fragments that can generate literals at relax time, this
234 variable points to the frag where the literal will be stored. For
235 literal frags, this variable points to the nearest literal pool
236 location frag. This literal frag will be moved to after this
c48aaca0
BW
237 location. For RELAX_LITERAL_POOL_BEGIN frags, this field points
238 to the frag immediately before the corresponding RELAX_LITERAL_POOL_END
239 frag, to make moving frags for this literal pool efficient. */
e0001a05
NC
240 fragS *literal_frag;
241
242 /* The destination segment for literal frags. (Note that this is only
dd49a749
BW
243 valid after xtensa_move_literals.) This field is also used for
244 LITERAL_POOL_END frags. */
e0001a05
NC
245 segT lit_seg;
246
dd49a749
BW
247 /* Frag chain for LITERAL_POOL_BEGIN frags. */
248 struct frchain *lit_frchain;
249
e0001a05
NC
250 /* For the relaxation scheme, some literal fragments can have their
251 expansions modified by an instruction that relaxes. */
43cd72b9
BW
252 int text_expansion[MAX_SLOTS];
253 int literal_expansion[MAX_SLOTS];
254 int unreported_expansion;
255
19e8f41a
BW
256 /* For slots that have a free register for relaxation, record that
257 register. */
258 expressionS free_reg[MAX_SLOTS];
259
43cd72b9
BW
260 /* For text fragments that can generate literals at relax time: */
261 fragS *literal_frags[MAX_SLOTS];
262 enum xtensa_relax_statesE slot_subtypes[MAX_SLOTS];
263 symbolS *slot_symbols[MAX_SLOTS];
43cd72b9
BW
264 offsetT slot_offsets[MAX_SLOTS];
265
983f90e3
SA
266 /* When marking frags after this one in the chain as no transform,
267 cache the last one in the chain, so that we can skip to the
268 end of the chain. */
269 fragS *no_transform_end;
e0001a05
NC
270};
271
43cd72b9
BW
272
273/* For VLIW support, we need to know what slot a fixup applies to. */
274typedef struct xtensa_fix_data_struct
275{
276 int slot;
277 symbolS *X_add_symbol;
278 offsetT X_add_number;
279} xtensa_fix_data;
280
281
282/* Structure to record xtensa-specific symbol information. */
283typedef struct xtensa_symfield_type
e0001a05 284{
43cd72b9
BW
285 unsigned int is_loop_target : 1;
286 unsigned int is_branch_target : 1;
6a7eedfe 287 symbolS *next_expr_symbol;
43cd72b9
BW
288} xtensa_symfield_type;
289
290
291/* Structure for saving information about a block of property data
292 for frags that have the same flags. The forward reference is
293 in this header file. The actual definition is in tc-xtensa.c. */
294struct xtensa_block_info_struct;
295typedef struct xtensa_block_info_struct xtensa_block_info;
296
e0001a05 297
43cd72b9 298/* Property section types. */
e0001a05
NC
299typedef enum
300{
e0001a05 301 xt_literal_sec,
43cd72b9 302 xt_prop_sec,
e0001a05
NC
303 max_xt_sec
304} xt_section_type;
305
306typedef struct xtensa_segment_info_struct
307{
308 fragS *literal_pool_loc;
309 xtensa_block_info *blocks[max_xt_sec];
310} xtensa_segment_info;
311
e0001a05 312
7fa3d080
BW
313extern const char *xtensa_target_format (void);
314extern void xtensa_init_fix_data (struct fix *);
315extern void xtensa_frag_init (fragS *);
316extern int xtensa_force_relocation (struct fix *);
30f725a1 317extern int xtensa_validate_fix_sub (struct fix *);
7fa3d080
BW
318extern void xtensa_frob_label (struct symbol *);
319extern void xtensa_end (void);
320extern void xtensa_post_relax_hook (void);
321extern void xtensa_file_arch_init (bfd *);
322extern void xtensa_flush_pending_output (void);
323extern bfd_boolean xtensa_fix_adjustable (struct fix *);
324extern void xtensa_symbol_new_hook (symbolS *);
325extern long xtensa_relax_frag (fragS *, long, int *);
326extern void xtensa_elf_section_change_hook (void);
327extern int xtensa_unrecognized_line (int);
328extern bfd_boolean xtensa_check_inside_bundle (void);
329extern void xtensa_handle_align (fragS *);
9456465c 330extern char *xtensa_section_rename (char *);
e0001a05
NC
331
332#define TARGET_FORMAT xtensa_target_format ()
333#define TARGET_ARCH bfd_arch_xtensa
334#define TC_SEGMENT_INFO_TYPE xtensa_segment_info
43cd72b9
BW
335#define TC_SYMFIELD_TYPE struct xtensa_symfield_type
336#define TC_FIX_TYPE xtensa_fix_data
337#define TC_INIT_FIX_DATA(x) xtensa_init_fix_data (x)
e0001a05
NC
338#define TC_FRAG_TYPE struct xtensa_frag_type
339#define TC_FRAG_INIT(frag) xtensa_frag_init (frag)
43cd72b9 340#define TC_FORCE_RELOCATION(fix) xtensa_force_relocation (fix)
30f725a1
BW
341#define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \
342 (! SEG_NORMAL (seg) || xtensa_force_relocation (fix))
5db484ff 343#define TC_VALIDATE_FIX_SUB(fix, seg) xtensa_validate_fix_sub (fix)
43cd72b9 344#define NO_PSEUDO_DOT xtensa_check_inside_bundle ()
e0001a05 345#define tc_canonicalize_symbol_name(s) xtensa_section_rename (s)
9456465c 346#define tc_canonicalize_section_name(s) xtensa_section_rename (s)
e0001a05
NC
347#define tc_init_after_args() xtensa_file_arch_init (stdoutput)
348#define tc_fix_adjustable(fix) xtensa_fix_adjustable (fix)
349#define tc_frob_label(sym) xtensa_frob_label (sym)
43cd72b9 350#define tc_unrecognized_line(ch) xtensa_unrecognized_line (ch)
6a7eedfe 351#define tc_symbol_new_hook(sym) xtensa_symbol_new_hook (sym)
43cd72b9
BW
352#define md_do_align(a,b,c,d,e) xtensa_flush_pending_output ()
353#define md_elf_section_change_hook xtensa_elf_section_change_hook
e0001a05
NC
354#define md_end xtensa_end
355#define md_flush_pending_output() xtensa_flush_pending_output ()
356#define md_operand(x)
357#define TEXT_SECTION_NAME xtensa_section_rename (".text")
358#define DATA_SECTION_NAME xtensa_section_rename (".data")
359#define BSS_SECTION_NAME xtensa_section_rename (".bss")
43cd72b9 360#define HANDLE_ALIGN(fragP) xtensa_handle_align (fragP)
cf523b8e 361#define MAX_MEM_FOR_RS_ALIGN_CODE 1
e0001a05
NC
362
363
364/* The renumber_section function must be mapped over all the sections
365 after calling xtensa_post_relax_hook. That function is static in
366 write.c so it cannot be called from xtensa_post_relax_hook itself. */
367
368#define md_post_relax_hook \
369 do \
370 { \
371 int i = 0; \
372 xtensa_post_relax_hook (); \
373 bfd_map_over_sections (stdoutput, renumber_sections, &i); \
374 } \
375 while (0)
376
377
378/* Because xtensa relaxation can insert a new literal into the middle of
379 fragment and thus require re-running the relaxation pass on the
380 section, we need an explicit flag here. We explicitly use the name
381 "stretched" here to avoid changing the source code in write.c. */
382
383#define md_relax_frag(segment, fragP, stretch) \
384 xtensa_relax_frag (fragP, stretch, &stretched)
385
ee6365aa
BW
386/* Only allow call frame debug info optimization when linker relaxation is
387 not enabled as otherwise we could generate the DWARF directives without
388 the relocs necessary to patch them up. */
389#define md_allow_eh_opt (linkrelax == 0)
e0001a05
NC
390
391#define LOCAL_LABELS_FB 1
392#define WORKING_DOT_WORD 1
393#define DOUBLESLASH_LINE_COMMENTS
394#define TC_HANDLES_FX_DONE
395#define TC_FINALIZE_SYMS_BEFORE_SIZE_SEG 0
43cd72b9 396#define TC_LINKRELAX_FIXUP(SEG) 0
e0001a05 397#define MD_APPLY_SYM_VALUE(FIX) 0
43cd72b9
BW
398#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
399
1737851b
BW
400/* Use line number format that is amenable to linker relaxation. */
401#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
402
43cd72b9
BW
403
404/* Resource reservation info functions. */
405
406/* Returns the number of copies of a particular unit. */
407typedef int (*unit_num_copies_func) (void *, xtensa_funcUnit);
408
409/* Returns the number of units the opcode uses. */
410typedef int (*opcode_num_units_func) (void *, xtensa_opcode);
411
c138bc38 412/* Given an opcode and an index into the opcode's funcUnit list,
43cd72b9
BW
413 returns the unit used for the index. */
414typedef int (*opcode_funcUnit_use_unit_func) (void *, xtensa_opcode, int);
415
c138bc38 416/* Given an opcode and an index into the opcode's funcUnit list,
43cd72b9
BW
417 returns the cycle during which the unit is used. */
418typedef int (*opcode_funcUnit_use_stage_func) (void *, xtensa_opcode, int);
419
c138bc38 420/* The above typedefs parameterize the resource_table so that the
43cd72b9 421 optional scheduler doesn't need its own resource reservation system.
c138bc38
BW
422
423 For simple resource checking, which is all that happens normally,
424 the functions will be as follows (with some wrapping to make the
425 interface more convenient):
43cd72b9
BW
426
427 unit_num_copies_func = xtensa_funcUnit_num_copies
428 opcode_num_units_func = xtensa_opcode_num_funcUnit_uses
429 opcode_funcUnit_use_unit_func = xtensa_opcode_funcUnit_use->unit
430 opcode_funcUnit_use_stage_func = xtensa_opcode_funcUnit_use->stage
431
c138bc38 432 Of course the optional scheduler has its own reservation table
43cd72b9
BW
433 and functions. */
434
7fa3d080
BW
435int opcode_funcUnit_use_unit (void *, xtensa_opcode, int);
436int opcode_funcUnit_use_stage (void *, xtensa_opcode, int);
43cd72b9
BW
437
438typedef struct
439{
440 void *data;
441 int cycles;
442 int allocated_cycles;
443 int num_units;
444 unit_num_copies_func unit_num_copies;
445 opcode_num_units_func opcode_num_units;
446 opcode_funcUnit_use_unit_func opcode_unit_use;
447 opcode_funcUnit_use_stage_func opcode_unit_stage;
0bf60745 448 unsigned char **units;
43cd72b9
BW
449} resource_table;
450
c138bc38
BW
451resource_table *new_resource_table
452 (void *, int, int, unit_num_copies_func, opcode_num_units_func,
7fa3d080
BW
453 opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func);
454void resize_resource_table (resource_table *, int);
455void clear_resource_table (resource_table *);
456bfd_boolean resources_available (resource_table *, xtensa_opcode, int);
457void reserve_resources (resource_table *, xtensa_opcode, int);
458void release_resources (resource_table *, xtensa_opcode, int);
e0001a05 459
e0001a05 460#endif /* TC_XTENSA */
This page took 0.520566 seconds and 4 git commands to generate.