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82704155 | 1 | @c Copyright (C) 2009-2019 Free Software Foundation, Inc. |
a06ea964 NC |
2 | @c Contributed by ARM Ltd. |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @c man end | |
6 | ||
7 | @ifset GENERIC | |
8 | @page | |
9 | @node AArch64-Dependent | |
10 | @chapter AArch64 Dependent Features | |
11 | @end ifset | |
12 | ||
13 | @ifclear GENERIC | |
14 | @node Machine Dependencies | |
15 | @chapter AArch64 Dependent Features | |
16 | @end ifclear | |
17 | ||
18 | @cindex AArch64 support | |
a06ea964 NC |
19 | @menu |
20 | * AArch64 Options:: Options | |
df359aa7 | 21 | * AArch64 Extensions:: Extensions |
a06ea964 NC |
22 | * AArch64 Syntax:: Syntax |
23 | * AArch64 Floating Point:: Floating Point | |
24 | * AArch64 Directives:: AArch64 Machine Directives | |
25 | * AArch64 Opcodes:: Opcodes | |
26 | * AArch64 Mapping Symbols:: Mapping Symbols | |
27 | @end menu | |
28 | ||
29 | @node AArch64 Options | |
30 | @section Options | |
31 | @cindex AArch64 options (none) | |
32 | @cindex options for AArch64 (none) | |
33 | ||
34 | @c man begin OPTIONS | |
35 | @table @gcctabopt | |
36 | ||
a05a5b64 | 37 | @cindex @option{-EB} command-line option, AArch64 |
a06ea964 NC |
38 | @item -EB |
39 | This option specifies that the output generated by the assembler should | |
40 | be marked as being encoded for a big-endian processor. | |
41 | ||
a05a5b64 | 42 | @cindex @option{-EL} command-line option, AArch64 |
a06ea964 NC |
43 | @item -EL |
44 | This option specifies that the output generated by the assembler should | |
45 | be marked as being encoded for a little-endian processor. | |
46 | ||
a05a5b64 | 47 | @cindex @option{-mabi=} command-line option, AArch64 |
69091a2c YZ |
48 | @item -mabi=@var{abi} |
49 | Specify which ABI the source code uses. The recognized arguments | |
50 | are: @code{ilp32} and @code{lp64}, which decides the generated object | |
51 | file in ELF32 and ELF64 format respectively. The default is @code{lp64}. | |
52 | ||
a05a5b64 | 53 | @cindex @option{-mcpu=} command-line option, AArch64 |
df359aa7 RE |
54 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] |
55 | This option specifies the target processor. The assembler will issue an error | |
56 | message if an attempt is made to assemble an instruction which will not execute | |
57 | on the target processor. The following processor names are recognized: | |
9c352f1c | 58 | @code{cortex-a35}, |
df359aa7 | 59 | @code{cortex-a53}, |
1e292627 | 60 | @code{cortex-a55}, |
df359aa7 | 61 | @code{cortex-a57}, |
2abdd192 | 62 | @code{cortex-a72}, |
1aa70332 | 63 | @code{cortex-a73}, |
1e292627 | 64 | @code{cortex-a75}, |
c2a0f929 | 65 | @code{cortex-a76}, |
2412d878 | 66 | @code{exynos-m1}, |
2fe9c2a0 | 67 | @code{falkor}, |
6b21c2bf | 68 | @code{qdf24xx}, |
7605d944 | 69 | @code{saphira}, |
55fbd992 | 70 | @code{thunderx}, |
0a8be2fe | 71 | @code{vulcan}, |
0a9ce86d | 72 | @code{xgene1} |
df359aa7 | 73 | and |
0a9ce86d | 74 | @code{xgene2}. |
df359aa7 RE |
75 | The special name @code{all} may be used to allow the assembler to accept |
76 | instructions valid for any supported processor, including all optional | |
77 | extensions. | |
78 | ||
79 | In addition to the basic instruction set, the assembler can be told to | |
80 | accept, or restrict, various extension mnemonics that extend the | |
81 | processor. @xref{AArch64 Extensions}. | |
82 | ||
83 | If some implementations of a particular processor can have an | |
84 | extension, then then those extensions are automatically enabled. | |
85 | Consequently, you will not normally have to specify any additional | |
86 | extensions. | |
87 | ||
a05a5b64 | 88 | @cindex @option{-march=} command-line option, AArch64 |
df359aa7 RE |
89 | @item -march=@var{architecture}[+@var{extension}@dots{}] |
90 | This option specifies the target architecture. The assembler will | |
91 | issue an error message if an attempt is made to assemble an | |
92 | instruction which will not execute on the target architecture. The | |
acb787b0 | 93 | following architecture names are recognized: @code{armv8-a}, |
70d56181 SD |
94 | @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a} |
95 | and @code{armv8.5-a}. | |
df359aa7 RE |
96 | |
97 | If both @option{-mcpu} and @option{-march} are specified, the | |
98 | assembler will use the setting for @option{-mcpu}. If neither are | |
99 | specified, the assembler will default to @option{-mcpu=all}. | |
100 | ||
101 | The architecture option can be extended with the same instruction set | |
102 | extension options as the @option{-mcpu} option. Unlike | |
103 | @option{-mcpu}, extensions are not always enabled by default, | |
104 | @xref{AArch64 Extensions}. | |
105 | ||
a05a5b64 | 106 | @cindex @code{-mverbose-error} command-line option, AArch64 |
a52e6fd3 YZ |
107 | @item -mverbose-error |
108 | This option enables verbose error messages for AArch64 gas. This option | |
109 | is enabled by default. | |
110 | ||
a05a5b64 | 111 | @cindex @code{-mno-verbose-error} command-line option, AArch64 |
a52e6fd3 YZ |
112 | @item -mno-verbose-error |
113 | This option disables verbose error messages in AArch64 gas. | |
114 | ||
a06ea964 NC |
115 | @end table |
116 | @c man end | |
117 | ||
df359aa7 RE |
118 | @node AArch64 Extensions |
119 | @section Architecture Extensions | |
120 | ||
121 | The table below lists the permitted architecture extensions that are | |
122 | supported by the assembler and the conditions under which they are | |
123 | automatically enabled. | |
124 | ||
125 | Multiple extensions may be specified, separated by a @code{+}. | |
126 | Extension mnemonics may also be removed from those the assembler | |
127 | accepts. This is done by prepending @code{no} to the option that adds | |
128 | the extension. Extensions that are removed must be listed after all | |
129 | extensions that have been added. | |
130 | ||
131 | Enabling an extension that requires other extensions will | |
132 | automatically cause those extensions to be enabled. Similarly, | |
133 | disabling an extension that is required by other extensions will | |
134 | automatically cause those extensions to be disabled. | |
135 | ||
136 | @multitable @columnfractions .12 .17 .17 .54 | |
137 | @headitem Extension @tab Minimum Architecture @tab Enabled by default | |
138 | @tab Description | |
f482d304 RS |
139 | @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later |
140 | @tab Enable the complex number SIMD extensions. This implies | |
141 | @code{fp16} and @code{simd}. | |
af117b3c | 142 | @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later |
df359aa7 RE |
143 | @tab Enable CRC instructions. |
144 | @item @code{crypto} @tab ARMv8-A @tab No | |
68ffd936 TC |
145 | @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}. |
146 | @item @code{aes} @tab ARMv8-A @tab No | |
147 | @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}. | |
148 | @item @code{sha2} @tab ARMv8-A @tab No | |
149 | @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}. | |
150 | @item @code{sha3} @tab ARMv8.2-A @tab No | |
151 | @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}. | |
152 | @item @code{sm4} @tab ARMv8.2-A @tab No | |
153 | @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}. | |
df359aa7 RE |
154 | @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later |
155 | @tab Enable floating-point extensions. | |
87018195 MW |
156 | @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later |
157 | @tab Enable ARMv8.2 16-bit floating-point support. This implies | |
158 | @code{fp}. | |
b607cde1 JG |
159 | @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later |
160 | @tab Enable Limited Ordering Regions extensions. | |
161 | @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later | |
162 | @tab Enable Large System extensions. | |
163 | @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later | |
164 | @tab Enable Privileged Access Never support. | |
73af8ed6 MW |
165 | @item @code{profile} @tab ARMv8.2-A @tab No |
166 | @tab Enable statistical profiling extensions. | |
50cc854c MW |
167 | @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later |
168 | @tab Enable the Reliability, Availability and Serviceability | |
169 | extension. | |
01cca2f9 SN |
170 | @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later |
171 | @tab Enable the weak release consistency extension. | |
b607cde1 JG |
172 | @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later |
173 | @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. | |
174 | @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later | |
175 | @tab Enable Advanced SIMD extensions. This implies @code{fp}. | |
582e12bf RS |
176 | @item @code{sve} @tab ARMv8.2-A @tab No |
177 | @tab Enable the Scalable Vector Extensions. This implies @code{fp16}, | |
178 | @code{simd} and @code{compnum}. | |
68ffd936 | 179 | @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later |
65a55fbb | 180 | @tab Enable the Dot Product extension. This implies @code{simd}. |
d0f7791c TC |
181 | @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later |
182 | @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. | |
183 | This implies @code{fp16}. | |
68dfbb92 SD |
184 | @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later |
185 | @tab Enable the speculation barrier instruction sb. | |
2ac435d4 SD |
186 | @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later |
187 | @tab Enable the Execution and Data and Prediction instructions. | |
af4bcb4c SD |
188 | @item @code{rng} @tab ARMv8.5-A @tab No |
189 | @tab Enable ARMv8.5-A random number instructions. | |
104fefee SD |
190 | @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later |
191 | @tab Enable Speculative Store Bypassing Safe state read and write. | |
73b605ec SD |
192 | @item @code{memtag} @tab ARMv8.5-A @tab No |
193 | @tab Enable ARMv8.5-A Memory Tagging Extensions. | |
df359aa7 RE |
194 | @end multitable |
195 | ||
a06ea964 NC |
196 | @node AArch64 Syntax |
197 | @section Syntax | |
198 | @menu | |
199 | * AArch64-Chars:: Special Characters | |
200 | * AArch64-Regs:: Register Names | |
201 | * AArch64-Relocations:: Relocations | |
202 | @end menu | |
203 | ||
204 | @node AArch64-Chars | |
205 | @subsection Special Characters | |
206 | ||
207 | @cindex line comment character, AArch64 | |
208 | @cindex AArch64 line comment character | |
209 | The presence of a @samp{//} on a line indicates the start of a comment | |
210 | that extends to the end of the current line. If a @samp{#} appears as | |
211 | the first character of a line, the whole line is treated as a comment. | |
212 | ||
213 | @cindex line separator, AArch64 | |
214 | @cindex statement separator, AArch64 | |
215 | @cindex AArch64 line separator | |
216 | The @samp{;} character can be used instead of a newline to separate | |
217 | statements. | |
218 | ||
219 | @cindex immediate character, AArch64 | |
220 | @cindex AArch64 immediate character | |
221 | The @samp{#} can be optionally used to indicate immediate operands. | |
222 | ||
223 | @node AArch64-Regs | |
224 | @subsection Register Names | |
225 | ||
226 | @cindex AArch64 register names | |
227 | @cindex register names, AArch64 | |
228 | Please refer to the section @samp{4.4 Register Names} of | |
229 | @samp{ARMv8 Instruction Set Overview}, which is available at | |
230 | @uref{http://infocenter.arm.com}. | |
231 | ||
232 | @node AArch64-Relocations | |
233 | @subsection Relocations | |
234 | ||
235 | @cindex relocations, AArch64 | |
236 | @cindex AArch64 relocations | |
237 | @cindex MOVN, MOVZ and MOVK group relocations, AArch64 | |
238 | Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated | |
239 | by prefixing the label with @samp{#:abs_g2:} etc. | |
240 | For example to load the 48-bit absolute address of @var{foo} into x0: | |
241 | ||
242 | @smallexample | |
243 | movz x0, #:abs_g2:foo // bits 32-47, overflow check | |
244 | movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check | |
245 | movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check | |
246 | @end smallexample | |
247 | ||
248 | @cindex ADRP, ADD, LDR/STR group relocations, AArch64 | |
249 | Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} | |
250 | instructions can be generated by prefixing the label with | |
34fd659b | 251 | @samp{:pg_hi21:} and @samp{#:lo12:} respectively. |
a06ea964 | 252 | |
34bca508 | 253 | For example to use 33-bit (+/-4GB) pc-relative addressing to |
a06ea964 NC |
254 | load the address of @var{foo} into x0: |
255 | ||
256 | @smallexample | |
34fd659b | 257 | adrp x0, :pg_hi21:foo |
a06ea964 NC |
258 | add x0, x0, #:lo12:foo |
259 | @end smallexample | |
260 | ||
261 | Or to load the value of @var{foo} into x0: | |
262 | ||
263 | @smallexample | |
34fd659b | 264 | adrp x0, :pg_hi21:foo |
a06ea964 NC |
265 | ldr x0, [x0, #:lo12:foo] |
266 | @end smallexample | |
267 | ||
34fd659b | 268 | Note that @samp{:pg_hi21:} is optional. |
a06ea964 NC |
269 | |
270 | @smallexample | |
271 | adrp x0, foo | |
272 | @end smallexample | |
273 | ||
274 | is equivalent to | |
275 | ||
276 | @smallexample | |
34fd659b | 277 | adrp x0, :pg_hi21:foo |
a06ea964 NC |
278 | @end smallexample |
279 | ||
280 | @node AArch64 Floating Point | |
281 | @section Floating Point | |
282 | ||
283 | @cindex floating point, AArch64 (@sc{ieee}) | |
284 | @cindex AArch64 floating point (@sc{ieee}) | |
285 | The AArch64 architecture uses @sc{ieee} floating-point numbers. | |
286 | ||
287 | @node AArch64 Directives | |
288 | @section AArch64 Machine Directives | |
289 | ||
290 | @cindex machine directives, AArch64 | |
291 | @cindex AArch64 machine directives | |
292 | @table @code | |
293 | ||
294 | @c AAAAAAAAAAAAAAAAAAAAAAAAA | |
8e02d7f5 JW |
295 | |
296 | @cindex @code{.arch} directive, AArch64 | |
297 | @item .arch @var{name} | |
298 | Select the target architecture. Valid values for @var{name} are the same as | |
a05a5b64 | 299 | for the @option{-march} command-line option. |
8e02d7f5 JW |
300 | |
301 | Specifying @code{.arch} clears any previously selected architecture | |
302 | extensions. | |
303 | ||
304 | @cindex @code{.arch_extension} directive, AArch64 | |
305 | @item .arch_extension @var{name} | |
306 | Add or remove an architecture extension to the target architecture. Valid | |
307 | values for @var{name} are the same as those accepted as architectural | |
a05a5b64 | 308 | extensions by the @option{-mcpu} command-line option. |
8e02d7f5 JW |
309 | |
310 | @code{.arch_extension} may be used multiple times to add or remove extensions | |
311 | incrementally to the architecture being compiled for. | |
312 | ||
a06ea964 NC |
313 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
314 | ||
315 | @cindex @code{.bss} directive, AArch64 | |
316 | @item .bss | |
317 | This directive switches to the @code{.bss} section. | |
318 | ||
319 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC | |
30fab421 NC |
320 | |
321 | @cindex @code{.cpu} directive, AArch64 | |
322 | @item .cpu @var{name} | |
323 | Set the target processor. Valid values for @var{name} are the same as | |
a05a5b64 | 324 | those accepted by the @option{-mcpu=} command-line option. |
30fab421 | 325 | |
a06ea964 | 326 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD |
30fab421 NC |
327 | |
328 | @cindex @code{.dword} directive, AArch64 | |
329 | @item .dword @var{expressions} | |
330 | The @code{.dword} directive produces 64 bit values. | |
331 | ||
a06ea964 | 332 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE |
30fab421 NC |
333 | |
334 | @cindex @code{.even} directive, AArch64 | |
335 | @item .even | |
336 | The @code{.even} directive aligns the output on the next even byte | |
337 | boundary. | |
338 | ||
a06ea964 NC |
339 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF |
340 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG | |
341 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
342 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
30fab421 NC |
343 | |
344 | @cindex @code{.inst} directive, AArch64 | |
345 | @item .inst @var{expressions} | |
346 | Inserts the expressions into the output as if they were instructions, | |
347 | rather than data. | |
348 | ||
a06ea964 NC |
349 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ |
350 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
351 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
352 | ||
353 | @cindex @code{.ltorg} directive, AArch64 | |
354 | @item .ltorg | |
355 | This directive causes the current contents of the literal pool to be | |
356 | dumped into the current section (which is assumed to be the .text | |
357 | section) at the current location (aligned to a word boundary). | |
df359aa7 | 358 | GAS maintains a separate literal pool for each section and each |
a06ea964 NC |
359 | sub-section. The @code{.ltorg} directive will only affect the literal |
360 | pool of the current section and sub-section. At the end of assembly | |
361 | all remaining, un-empty literal pools will automatically be dumped. | |
362 | ||
df359aa7 | 363 | Note - older versions of GAS would dump the current literal |
a06ea964 NC |
364 | pool any time a section change occurred. This is no longer done, since |
365 | it prevents accurate control of the placement of literal pools. | |
366 | ||
367 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM | |
368 | ||
369 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN | |
370 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
371 | ||
372 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP | |
373 | ||
374 | @cindex @code{.pool} directive, AArch64 | |
375 | @item .pool | |
376 | This is a synonym for .ltorg. | |
377 | ||
378 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ | |
379 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
380 | ||
381 | @cindex @code{.req} directive, AArch64 | |
382 | @item @var{name} .req @var{register name} | |
383 | This creates an alias for @var{register name} called @var{name}. For | |
384 | example: | |
385 | ||
386 | @smallexample | |
387 | foo .req w0 | |
388 | @end smallexample | |
389 | ||
8975f864 RR |
390 | ip0, ip1, lr and fp are automatically defined to |
391 | alias to X16, X17, X30 and X29 respectively. | |
392 | ||
a06ea964 NC |
393 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS |
394 | ||
395 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT | |
396 | ||
30fab421 NC |
397 | @cindex @code{.tlsdescadd} directive, AArch64 |
398 | @item @code{.tlsdescadd} | |
399 | Emits a TLSDESC_ADD reloc on the next instruction. | |
400 | ||
401 | @cindex @code{.tlsdesccall} directive, AArch64 | |
402 | @item @code{.tlsdesccall} | |
403 | Emits a TLSDESC_CALL reloc on the next instruction. | |
404 | ||
405 | @cindex @code{.tlsdescldr} directive, AArch64 | |
406 | @item @code{.tlsdescldr} | |
407 | Emits a TLSDESC_LDR reloc on the next instruction. | |
408 | ||
a06ea964 NC |
409 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU |
410 | ||
411 | @cindex @code{.unreq} directive, AArch64 | |
412 | @item .unreq @var{alias-name} | |
413 | This undefines a register alias which was previously defined using the | |
414 | @code{req} directive. For example: | |
415 | ||
416 | @smallexample | |
417 | foo .req w0 | |
418 | .unreq foo | |
419 | @end smallexample | |
420 | ||
421 | An error occurs if the name is undefined. Note - this pseudo op can | |
422 | be used to delete builtin in register name aliases (eg 'w0'). This | |
423 | should only be done if it is really necessary. | |
424 | ||
425 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV | |
426 | ||
427 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW | |
428 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
a06ea964 | 429 | |
edc66de9 | 430 | @cindex @code{.xword} directive, AArch64 |
30fab421 NC |
431 | @item .xword @var{expressions} |
432 | The @code{.xword} directive produces 64 bit values. This is the same | |
433 | as the @code{.dword} directive. | |
434 | ||
435 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
436 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
edc66de9 | 437 | |
3a67e1a6 ST |
438 | @cindex @code{.cfi_b_key_frame} directive, AArch64 |
439 | @item @code{.cfi_b_key_frame} | |
440 | The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE | |
441 | corresponding to the current frame's FDE, meaning that its return address has | |
442 | been signed with the B-key. If two frames are signed with differing keys then | |
443 | they will not share the same CIE. This information is intended to be used by | |
444 | the stack unwinder in order to properly authenticate return addresses. | |
445 | ||
a06ea964 NC |
446 | @end table |
447 | ||
448 | @node AArch64 Opcodes | |
449 | @section Opcodes | |
450 | ||
451 | @cindex AArch64 opcodes | |
452 | @cindex opcodes for AArch64 | |
df359aa7 | 453 | GAS implements all the standard AArch64 opcodes. It also |
a06ea964 | 454 | implements several pseudo opcodes, including several synthetic load |
34bca508 | 455 | instructions. |
a06ea964 NC |
456 | |
457 | @table @code | |
458 | ||
459 | @cindex @code{LDR reg,=<expr>} pseudo op, AArch64 | |
460 | @item LDR = | |
461 | @smallexample | |
462 | ldr <register> , =<expression> | |
463 | @end smallexample | |
464 | ||
465 | The constant expression will be placed into the nearest literal pool (if it not | |
466 | already there) and a PC-relative LDR instruction will be generated. | |
467 | ||
468 | @end table | |
469 | ||
470 | For more information on the AArch64 instruction set and assembly language | |
471 | notation, see @samp{ARMv8 Instruction Set Overview} available at | |
472 | @uref{http://infocenter.arm.com}. | |
473 | ||
474 | ||
475 | @node AArch64 Mapping Symbols | |
476 | @section Mapping Symbols | |
477 | ||
478 | The AArch64 ELF specification requires that special symbols be inserted | |
479 | into object files to mark certain features: | |
480 | ||
481 | @table @code | |
482 | ||
483 | @cindex @code{$x} | |
484 | @item $x | |
485 | At the start of a region of code containing AArch64 instructions. | |
486 | ||
487 | @cindex @code{$d} | |
488 | @item $d | |
489 | At the start of a region of data. | |
490 | ||
491 | @end table |