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2571583a | 1 | @c Copyright (C) 2009-2017 Free Software Foundation, Inc. |
a06ea964 NC |
2 | @c Contributed by ARM Ltd. |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @c man end | |
6 | ||
7 | @ifset GENERIC | |
8 | @page | |
9 | @node AArch64-Dependent | |
10 | @chapter AArch64 Dependent Features | |
11 | @end ifset | |
12 | ||
13 | @ifclear GENERIC | |
14 | @node Machine Dependencies | |
15 | @chapter AArch64 Dependent Features | |
16 | @end ifclear | |
17 | ||
18 | @cindex AArch64 support | |
a06ea964 NC |
19 | @menu |
20 | * AArch64 Options:: Options | |
df359aa7 | 21 | * AArch64 Extensions:: Extensions |
a06ea964 NC |
22 | * AArch64 Syntax:: Syntax |
23 | * AArch64 Floating Point:: Floating Point | |
24 | * AArch64 Directives:: AArch64 Machine Directives | |
25 | * AArch64 Opcodes:: Opcodes | |
26 | * AArch64 Mapping Symbols:: Mapping Symbols | |
27 | @end menu | |
28 | ||
29 | @node AArch64 Options | |
30 | @section Options | |
31 | @cindex AArch64 options (none) | |
32 | @cindex options for AArch64 (none) | |
33 | ||
34 | @c man begin OPTIONS | |
35 | @table @gcctabopt | |
36 | ||
df359aa7 | 37 | @cindex @option{-EB} command line option, AArch64 |
a06ea964 NC |
38 | @item -EB |
39 | This option specifies that the output generated by the assembler should | |
40 | be marked as being encoded for a big-endian processor. | |
41 | ||
df359aa7 | 42 | @cindex @option{-EL} command line option, AArch64 |
a06ea964 NC |
43 | @item -EL |
44 | This option specifies that the output generated by the assembler should | |
45 | be marked as being encoded for a little-endian processor. | |
46 | ||
df359aa7 | 47 | @cindex @option{-mabi=} command line option, AArch64 |
69091a2c YZ |
48 | @item -mabi=@var{abi} |
49 | Specify which ABI the source code uses. The recognized arguments | |
50 | are: @code{ilp32} and @code{lp64}, which decides the generated object | |
51 | file in ELF32 and ELF64 format respectively. The default is @code{lp64}. | |
52 | ||
df359aa7 RE |
53 | @cindex @option{-mcpu=} command line option, AArch64 |
54 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] | |
55 | This option specifies the target processor. The assembler will issue an error | |
56 | message if an attempt is made to assemble an instruction which will not execute | |
57 | on the target processor. The following processor names are recognized: | |
9c352f1c | 58 | @code{cortex-a35}, |
df359aa7 | 59 | @code{cortex-a53}, |
1e292627 | 60 | @code{cortex-a55}, |
df359aa7 | 61 | @code{cortex-a57}, |
2abdd192 | 62 | @code{cortex-a72}, |
1aa70332 | 63 | @code{cortex-a73}, |
1e292627 | 64 | @code{cortex-a75}, |
2412d878 | 65 | @code{exynos-m1}, |
2fe9c2a0 | 66 | @code{falkor}, |
6b21c2bf | 67 | @code{qdf24xx}, |
55fbd992 | 68 | @code{thunderx}, |
0a8be2fe | 69 | @code{vulcan}, |
0a9ce86d | 70 | @code{xgene1} |
df359aa7 | 71 | and |
0a9ce86d | 72 | @code{xgene2}. |
df359aa7 RE |
73 | The special name @code{all} may be used to allow the assembler to accept |
74 | instructions valid for any supported processor, including all optional | |
75 | extensions. | |
76 | ||
77 | In addition to the basic instruction set, the assembler can be told to | |
78 | accept, or restrict, various extension mnemonics that extend the | |
79 | processor. @xref{AArch64 Extensions}. | |
80 | ||
81 | If some implementations of a particular processor can have an | |
82 | extension, then then those extensions are automatically enabled. | |
83 | Consequently, you will not normally have to specify any additional | |
84 | extensions. | |
85 | ||
86 | @cindex @option{-march=} command line option, AArch64 | |
87 | @item -march=@var{architecture}[+@var{extension}@dots{}] | |
88 | This option specifies the target architecture. The assembler will | |
89 | issue an error message if an attempt is made to assemble an | |
90 | instruction which will not execute on the target architecture. The | |
acb787b0 | 91 | following architecture names are recognized: @code{armv8-a}, |
1924ff75 | 92 | @code{armv8.1-a}, @code{armv8.2-a} and @code{armv8.3-a}. |
df359aa7 RE |
93 | |
94 | If both @option{-mcpu} and @option{-march} are specified, the | |
95 | assembler will use the setting for @option{-mcpu}. If neither are | |
96 | specified, the assembler will default to @option{-mcpu=all}. | |
97 | ||
98 | The architecture option can be extended with the same instruction set | |
99 | extension options as the @option{-mcpu} option. Unlike | |
100 | @option{-mcpu}, extensions are not always enabled by default, | |
101 | @xref{AArch64 Extensions}. | |
102 | ||
a52e6fd3 YZ |
103 | @cindex @code{-mverbose-error} command line option, AArch64 |
104 | @item -mverbose-error | |
105 | This option enables verbose error messages for AArch64 gas. This option | |
106 | is enabled by default. | |
107 | ||
108 | @cindex @code{-mno-verbose-error} command line option, AArch64 | |
109 | @item -mno-verbose-error | |
110 | This option disables verbose error messages in AArch64 gas. | |
111 | ||
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112 | @end table |
113 | @c man end | |
114 | ||
df359aa7 RE |
115 | @node AArch64 Extensions |
116 | @section Architecture Extensions | |
117 | ||
118 | The table below lists the permitted architecture extensions that are | |
119 | supported by the assembler and the conditions under which they are | |
120 | automatically enabled. | |
121 | ||
122 | Multiple extensions may be specified, separated by a @code{+}. | |
123 | Extension mnemonics may also be removed from those the assembler | |
124 | accepts. This is done by prepending @code{no} to the option that adds | |
125 | the extension. Extensions that are removed must be listed after all | |
126 | extensions that have been added. | |
127 | ||
128 | Enabling an extension that requires other extensions will | |
129 | automatically cause those extensions to be enabled. Similarly, | |
130 | disabling an extension that is required by other extensions will | |
131 | automatically cause those extensions to be disabled. | |
132 | ||
133 | @multitable @columnfractions .12 .17 .17 .54 | |
134 | @headitem Extension @tab Minimum Architecture @tab Enabled by default | |
135 | @tab Description | |
f482d304 RS |
136 | @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later |
137 | @tab Enable the complex number SIMD extensions. This implies | |
138 | @code{fp16} and @code{simd}. | |
af117b3c | 139 | @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later |
df359aa7 RE |
140 | @tab Enable CRC instructions. |
141 | @item @code{crypto} @tab ARMv8-A @tab No | |
142 | @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. | |
143 | @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later | |
144 | @tab Enable floating-point extensions. | |
87018195 MW |
145 | @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later |
146 | @tab Enable ARMv8.2 16-bit floating-point support. This implies | |
147 | @code{fp}. | |
b607cde1 JG |
148 | @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later |
149 | @tab Enable Limited Ordering Regions extensions. | |
150 | @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later | |
151 | @tab Enable Large System extensions. | |
152 | @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later | |
153 | @tab Enable Privileged Access Never support. | |
73af8ed6 MW |
154 | @item @code{profile} @tab ARMv8.2-A @tab No |
155 | @tab Enable statistical profiling extensions. | |
50cc854c MW |
156 | @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later |
157 | @tab Enable the Reliability, Availability and Serviceability | |
158 | extension. | |
01cca2f9 SN |
159 | @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later |
160 | @tab Enable the weak release consistency extension. | |
b607cde1 JG |
161 | @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later |
162 | @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. | |
163 | @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later | |
164 | @tab Enable Advanced SIMD extensions. This implies @code{fp}. | |
582e12bf RS |
165 | @item @code{sve} @tab ARMv8.2-A @tab No |
166 | @tab Enable the Scalable Vector Extensions. This implies @code{fp16}, | |
167 | @code{simd} and @code{compnum}. | |
df359aa7 RE |
168 | @end multitable |
169 | ||
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170 | @node AArch64 Syntax |
171 | @section Syntax | |
172 | @menu | |
173 | * AArch64-Chars:: Special Characters | |
174 | * AArch64-Regs:: Register Names | |
175 | * AArch64-Relocations:: Relocations | |
176 | @end menu | |
177 | ||
178 | @node AArch64-Chars | |
179 | @subsection Special Characters | |
180 | ||
181 | @cindex line comment character, AArch64 | |
182 | @cindex AArch64 line comment character | |
183 | The presence of a @samp{//} on a line indicates the start of a comment | |
184 | that extends to the end of the current line. If a @samp{#} appears as | |
185 | the first character of a line, the whole line is treated as a comment. | |
186 | ||
187 | @cindex line separator, AArch64 | |
188 | @cindex statement separator, AArch64 | |
189 | @cindex AArch64 line separator | |
190 | The @samp{;} character can be used instead of a newline to separate | |
191 | statements. | |
192 | ||
193 | @cindex immediate character, AArch64 | |
194 | @cindex AArch64 immediate character | |
195 | The @samp{#} can be optionally used to indicate immediate operands. | |
196 | ||
197 | @node AArch64-Regs | |
198 | @subsection Register Names | |
199 | ||
200 | @cindex AArch64 register names | |
201 | @cindex register names, AArch64 | |
202 | Please refer to the section @samp{4.4 Register Names} of | |
203 | @samp{ARMv8 Instruction Set Overview}, which is available at | |
204 | @uref{http://infocenter.arm.com}. | |
205 | ||
206 | @node AArch64-Relocations | |
207 | @subsection Relocations | |
208 | ||
209 | @cindex relocations, AArch64 | |
210 | @cindex AArch64 relocations | |
211 | @cindex MOVN, MOVZ and MOVK group relocations, AArch64 | |
212 | Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated | |
213 | by prefixing the label with @samp{#:abs_g2:} etc. | |
214 | For example to load the 48-bit absolute address of @var{foo} into x0: | |
215 | ||
216 | @smallexample | |
217 | movz x0, #:abs_g2:foo // bits 32-47, overflow check | |
218 | movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check | |
219 | movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check | |
220 | @end smallexample | |
221 | ||
222 | @cindex ADRP, ADD, LDR/STR group relocations, AArch64 | |
223 | Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} | |
224 | instructions can be generated by prefixing the label with | |
34fd659b | 225 | @samp{:pg_hi21:} and @samp{#:lo12:} respectively. |
a06ea964 | 226 | |
34bca508 | 227 | For example to use 33-bit (+/-4GB) pc-relative addressing to |
a06ea964 NC |
228 | load the address of @var{foo} into x0: |
229 | ||
230 | @smallexample | |
34fd659b | 231 | adrp x0, :pg_hi21:foo |
a06ea964 NC |
232 | add x0, x0, #:lo12:foo |
233 | @end smallexample | |
234 | ||
235 | Or to load the value of @var{foo} into x0: | |
236 | ||
237 | @smallexample | |
34fd659b | 238 | adrp x0, :pg_hi21:foo |
a06ea964 NC |
239 | ldr x0, [x0, #:lo12:foo] |
240 | @end smallexample | |
241 | ||
34fd659b | 242 | Note that @samp{:pg_hi21:} is optional. |
a06ea964 NC |
243 | |
244 | @smallexample | |
245 | adrp x0, foo | |
246 | @end smallexample | |
247 | ||
248 | is equivalent to | |
249 | ||
250 | @smallexample | |
34fd659b | 251 | adrp x0, :pg_hi21:foo |
a06ea964 NC |
252 | @end smallexample |
253 | ||
254 | @node AArch64 Floating Point | |
255 | @section Floating Point | |
256 | ||
257 | @cindex floating point, AArch64 (@sc{ieee}) | |
258 | @cindex AArch64 floating point (@sc{ieee}) | |
259 | The AArch64 architecture uses @sc{ieee} floating-point numbers. | |
260 | ||
261 | @node AArch64 Directives | |
262 | @section AArch64 Machine Directives | |
263 | ||
264 | @cindex machine directives, AArch64 | |
265 | @cindex AArch64 machine directives | |
266 | @table @code | |
267 | ||
268 | @c AAAAAAAAAAAAAAAAAAAAAAAAA | |
8e02d7f5 JW |
269 | |
270 | @cindex @code{.arch} directive, AArch64 | |
271 | @item .arch @var{name} | |
272 | Select the target architecture. Valid values for @var{name} are the same as | |
273 | for the @option{-march} commandline option. | |
274 | ||
275 | Specifying @code{.arch} clears any previously selected architecture | |
276 | extensions. | |
277 | ||
278 | @cindex @code{.arch_extension} directive, AArch64 | |
279 | @item .arch_extension @var{name} | |
280 | Add or remove an architecture extension to the target architecture. Valid | |
281 | values for @var{name} are the same as those accepted as architectural | |
282 | extensions by the @option{-mcpu} commandline option. | |
283 | ||
284 | @code{.arch_extension} may be used multiple times to add or remove extensions | |
285 | incrementally to the architecture being compiled for. | |
286 | ||
a06ea964 NC |
287 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
288 | ||
289 | @cindex @code{.bss} directive, AArch64 | |
290 | @item .bss | |
291 | This directive switches to the @code{.bss} section. | |
292 | ||
293 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC | |
30fab421 NC |
294 | |
295 | @cindex @code{.cpu} directive, AArch64 | |
296 | @item .cpu @var{name} | |
297 | Set the target processor. Valid values for @var{name} are the same as | |
298 | those accepted by the @option{-mcpu=} command line option. | |
299 | ||
a06ea964 | 300 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD |
30fab421 NC |
301 | |
302 | @cindex @code{.dword} directive, AArch64 | |
303 | @item .dword @var{expressions} | |
304 | The @code{.dword} directive produces 64 bit values. | |
305 | ||
a06ea964 | 306 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE |
30fab421 NC |
307 | |
308 | @cindex @code{.even} directive, AArch64 | |
309 | @item .even | |
310 | The @code{.even} directive aligns the output on the next even byte | |
311 | boundary. | |
312 | ||
a06ea964 NC |
313 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF |
314 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG | |
315 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
316 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
30fab421 NC |
317 | |
318 | @cindex @code{.inst} directive, AArch64 | |
319 | @item .inst @var{expressions} | |
320 | Inserts the expressions into the output as if they were instructions, | |
321 | rather than data. | |
322 | ||
a06ea964 NC |
323 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ |
324 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
325 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
326 | ||
327 | @cindex @code{.ltorg} directive, AArch64 | |
328 | @item .ltorg | |
329 | This directive causes the current contents of the literal pool to be | |
330 | dumped into the current section (which is assumed to be the .text | |
331 | section) at the current location (aligned to a word boundary). | |
df359aa7 | 332 | GAS maintains a separate literal pool for each section and each |
a06ea964 NC |
333 | sub-section. The @code{.ltorg} directive will only affect the literal |
334 | pool of the current section and sub-section. At the end of assembly | |
335 | all remaining, un-empty literal pools will automatically be dumped. | |
336 | ||
df359aa7 | 337 | Note - older versions of GAS would dump the current literal |
a06ea964 NC |
338 | pool any time a section change occurred. This is no longer done, since |
339 | it prevents accurate control of the placement of literal pools. | |
340 | ||
341 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM | |
342 | ||
343 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN | |
344 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
345 | ||
346 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP | |
347 | ||
348 | @cindex @code{.pool} directive, AArch64 | |
349 | @item .pool | |
350 | This is a synonym for .ltorg. | |
351 | ||
352 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ | |
353 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
354 | ||
355 | @cindex @code{.req} directive, AArch64 | |
356 | @item @var{name} .req @var{register name} | |
357 | This creates an alias for @var{register name} called @var{name}. For | |
358 | example: | |
359 | ||
360 | @smallexample | |
361 | foo .req w0 | |
362 | @end smallexample | |
363 | ||
364 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS | |
365 | ||
366 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT | |
367 | ||
30fab421 NC |
368 | @cindex @code{.tlsdescadd} directive, AArch64 |
369 | @item @code{.tlsdescadd} | |
370 | Emits a TLSDESC_ADD reloc on the next instruction. | |
371 | ||
372 | @cindex @code{.tlsdesccall} directive, AArch64 | |
373 | @item @code{.tlsdesccall} | |
374 | Emits a TLSDESC_CALL reloc on the next instruction. | |
375 | ||
376 | @cindex @code{.tlsdescldr} directive, AArch64 | |
377 | @item @code{.tlsdescldr} | |
378 | Emits a TLSDESC_LDR reloc on the next instruction. | |
379 | ||
a06ea964 NC |
380 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU |
381 | ||
382 | @cindex @code{.unreq} directive, AArch64 | |
383 | @item .unreq @var{alias-name} | |
384 | This undefines a register alias which was previously defined using the | |
385 | @code{req} directive. For example: | |
386 | ||
387 | @smallexample | |
388 | foo .req w0 | |
389 | .unreq foo | |
390 | @end smallexample | |
391 | ||
392 | An error occurs if the name is undefined. Note - this pseudo op can | |
393 | be used to delete builtin in register name aliases (eg 'w0'). This | |
394 | should only be done if it is really necessary. | |
395 | ||
396 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV | |
397 | ||
398 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW | |
399 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
a06ea964 | 400 | |
edc66de9 | 401 | @cindex @code{.xword} directive, AArch64 |
30fab421 NC |
402 | @item .xword @var{expressions} |
403 | The @code{.xword} directive produces 64 bit values. This is the same | |
404 | as the @code{.dword} directive. | |
405 | ||
406 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
407 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
edc66de9 | 408 | |
a06ea964 NC |
409 | @end table |
410 | ||
411 | @node AArch64 Opcodes | |
412 | @section Opcodes | |
413 | ||
414 | @cindex AArch64 opcodes | |
415 | @cindex opcodes for AArch64 | |
df359aa7 | 416 | GAS implements all the standard AArch64 opcodes. It also |
a06ea964 | 417 | implements several pseudo opcodes, including several synthetic load |
34bca508 | 418 | instructions. |
a06ea964 NC |
419 | |
420 | @table @code | |
421 | ||
422 | @cindex @code{LDR reg,=<expr>} pseudo op, AArch64 | |
423 | @item LDR = | |
424 | @smallexample | |
425 | ldr <register> , =<expression> | |
426 | @end smallexample | |
427 | ||
428 | The constant expression will be placed into the nearest literal pool (if it not | |
429 | already there) and a PC-relative LDR instruction will be generated. | |
430 | ||
431 | @end table | |
432 | ||
433 | For more information on the AArch64 instruction set and assembly language | |
434 | notation, see @samp{ARMv8 Instruction Set Overview} available at | |
435 | @uref{http://infocenter.arm.com}. | |
436 | ||
437 | ||
438 | @node AArch64 Mapping Symbols | |
439 | @section Mapping Symbols | |
440 | ||
441 | The AArch64 ELF specification requires that special symbols be inserted | |
442 | into object files to mark certain features: | |
443 | ||
444 | @table @code | |
445 | ||
446 | @cindex @code{$x} | |
447 | @item $x | |
448 | At the start of a region of code containing AArch64 instructions. | |
449 | ||
450 | @cindex @code{$d} | |
451 | @item $d | |
452 | At the start of a region of data. | |
453 | ||
454 | @end table |