Commit | Line | Data |
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0dd132b6 | 1 | @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004 |
f7e42eb4 | 2 | @c Free Software Foundation, Inc. |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | ||
6 | @ifset GENERIC | |
7 | @page | |
8 | @node ARM-Dependent | |
9 | @chapter ARM Dependent Features | |
10 | @end ifset | |
11 | ||
12 | @ifclear GENERIC | |
13 | @node Machine Dependencies | |
14 | @chapter ARM Dependent Features | |
15 | @end ifclear | |
16 | ||
17 | @cindex ARM support | |
18 | @cindex Thumb support | |
19 | @menu | |
20 | * ARM Options:: Options | |
21 | * ARM Syntax:: Syntax | |
22 | * ARM Floating Point:: Floating Point | |
23 | * ARM Directives:: ARM Machine Directives | |
24 | * ARM Opcodes:: Opcodes | |
6057a28f | 25 | * ARM Mapping Symbols:: Mapping Symbols |
252b5132 RH |
26 | @end menu |
27 | ||
28 | @node ARM Options | |
29 | @section Options | |
30 | @cindex ARM options (none) | |
31 | @cindex options for ARM (none) | |
adcf07e6 | 32 | |
252b5132 | 33 | @table @code |
adcf07e6 | 34 | |
03b1477f | 35 | @cindex @code{-mcpu=} command line option, ARM |
92081f48 | 36 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] |
252b5132 RH |
37 | This option specifies the target processor. The assembler will issue an |
38 | error message if an attempt is made to assemble an instruction which | |
03b1477f RE |
39 | will not execute on the target processor. The following processor names are |
40 | recognized: | |
41 | @code{arm1}, | |
42 | @code{arm2}, | |
43 | @code{arm250}, | |
44 | @code{arm3}, | |
45 | @code{arm6}, | |
46 | @code{arm60}, | |
47 | @code{arm600}, | |
48 | @code{arm610}, | |
49 | @code{arm620}, | |
50 | @code{arm7}, | |
51 | @code{arm7m}, | |
52 | @code{arm7d}, | |
53 | @code{arm7dm}, | |
54 | @code{arm7di}, | |
55 | @code{arm7dmi}, | |
56 | @code{arm70}, | |
57 | @code{arm700}, | |
58 | @code{arm700i}, | |
59 | @code{arm710}, | |
60 | @code{arm710t}, | |
61 | @code{arm720}, | |
62 | @code{arm720t}, | |
63 | @code{arm740t}, | |
64 | @code{arm710c}, | |
65 | @code{arm7100}, | |
66 | @code{arm7500}, | |
67 | @code{arm7500fe}, | |
68 | @code{arm7t}, | |
69 | @code{arm7tdmi}, | |
1ff4677c | 70 | @code{arm7tdmi-s}, |
03b1477f RE |
71 | @code{arm8}, |
72 | @code{arm810}, | |
73 | @code{strongarm}, | |
74 | @code{strongarm1}, | |
75 | @code{strongarm110}, | |
76 | @code{strongarm1100}, | |
77 | @code{strongarm1110}, | |
78 | @code{arm9}, | |
79 | @code{arm920}, | |
80 | @code{arm920t}, | |
81 | @code{arm922t}, | |
82 | @code{arm940t}, | |
83 | @code{arm9tdmi}, | |
84 | @code{arm9e}, | |
7de9afa2 | 85 | @code{arm926e}, |
1ff4677c | 86 | @code{arm926ej-s}, |
03b1477f RE |
87 | @code{arm946e-r0}, |
88 | @code{arm946e}, | |
89 | @code{arm966e-r0}, | |
90 | @code{arm966e}, | |
91 | @code{arm10t}, | |
92 | @code{arm10e}, | |
93 | @code{arm1020}, | |
94 | @code{arm1020t}, | |
7de9afa2 | 95 | @code{arm1020e}, |
1ff4677c RE |
96 | @code{arm1026ej-s}, |
97 | @code{arm1136j-s}, | |
98 | @code{arm1136jf-s}, | |
0dd132b6 NC |
99 | @code{arm1176jz-s}, |
100 | @code{arm1176jzf-s}, | |
101 | @code{mpcore}, | |
102 | @code{mpcorenovfp}, | |
03b1477f RE |
103 | @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), |
104 | @code{i80200} (Intel XScale processor) | |
e16bb312 | 105 | @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) |
03b1477f RE |
106 | and |
107 | @code{xscale}. | |
108 | The special name @code{all} may be used to allow the | |
109 | assembler to accept instructions valid for any ARM processor. | |
110 | ||
111 | In addition to the basic instruction set, the assembler can be told to | |
112 | accept various extension mnemonics that extend the processor using the | |
113 | co-processor instruction space. For example, @code{-mcpu=arm920+maverick} | |
114 | is equivalent to specifying @code{-mcpu=ep9312}. The following extensions | |
115 | are currently supported: | |
116 | @code{+maverick} | |
e16bb312 | 117 | @code{+iwmmxt} |
03b1477f RE |
118 | and |
119 | @code{+xscale}. | |
120 | ||
121 | @cindex @code{-march=} command line option, ARM | |
92081f48 | 122 | @item -march=@var{architecture}[+@var{extension}@dots{}] |
252b5132 RH |
123 | This option specifies the target architecture. The assembler will issue |
124 | an error message if an attempt is made to assemble an instruction which | |
03b1477f RE |
125 | will not execute on the target architecture. The following architecture |
126 | names are recognized: | |
127 | @code{armv1}, | |
128 | @code{armv2}, | |
129 | @code{armv2a}, | |
130 | @code{armv2s}, | |
131 | @code{armv3}, | |
132 | @code{armv3m}, | |
133 | @code{armv4}, | |
134 | @code{armv4xm}, | |
135 | @code{armv4t}, | |
136 | @code{armv4txm}, | |
137 | @code{armv5}, | |
138 | @code{armv5t}, | |
139 | @code{armv5txm}, | |
140 | @code{armv5te}, | |
09d92015 | 141 | @code{armv5texp}, |
c5f98204 | 142 | @code{armv6}, |
1ddd7f43 | 143 | @code{armv6j}, |
0dd132b6 NC |
144 | @code{armv6k}, |
145 | @code{armv6z}, | |
146 | @code{armv6zk}, | |
e16bb312 | 147 | @code{iwmmxt} |
03b1477f RE |
148 | and |
149 | @code{xscale}. | |
150 | If both @code{-mcpu} and | |
151 | @code{-march} are specified, the assembler will use | |
152 | the setting for @code{-mcpu}. | |
153 | ||
154 | The architecture option can be extended with the same instruction set | |
155 | extension options as the @code{-mcpu} option. | |
156 | ||
157 | @cindex @code{-mfpu=} command line option, ARM | |
158 | @item -mfpu=@var{floating-point-format} | |
159 | ||
160 | This option specifies the floating point format to assemble for. The | |
161 | assembler will issue an error message if an attempt is made to assemble | |
162 | an instruction which will not execute on the target floating point unit. | |
163 | The following format options are recognized: | |
164 | @code{softfpa}, | |
165 | @code{fpe}, | |
bc89618b RE |
166 | @code{fpe2}, |
167 | @code{fpe3}, | |
03b1477f RE |
168 | @code{fpa}, |
169 | @code{fpa10}, | |
170 | @code{fpa11}, | |
171 | @code{arm7500fe}, | |
172 | @code{softvfp}, | |
173 | @code{softvfp+vfp}, | |
174 | @code{vfp}, | |
175 | @code{vfp10}, | |
176 | @code{vfp10-r0}, | |
177 | @code{vfp9}, | |
178 | @code{vfpxd}, | |
09d92015 MM |
179 | @code{arm1020t}, |
180 | @code{arm1020e}, | |
1ff4677c | 181 | @code{arm1136jf-s} |
03b1477f | 182 | and |
33a392fb | 183 | @code{maverick}. |
03b1477f RE |
184 | |
185 | In addition to determining which instructions are assembled, this option | |
186 | also affects the way in which the @code{.double} assembler directive behaves | |
187 | when assembling little-endian code. | |
188 | ||
189 | The default is dependent on the processor selected. For Architecture 5 or | |
190 | later, the default is to assembler for VFP instructions; for earlier | |
191 | architectures the default is to assemble for FPA instructions. | |
adcf07e6 | 192 | |
252b5132 RH |
193 | @cindex @code{-mthumb} command line option, ARM |
194 | @item -mthumb | |
03b1477f RE |
195 | This option specifies that the assembler should start assembling Thumb |
196 | instructions; that is, it should behave as though the file starts with a | |
197 | @code{.code 16} directive. | |
adcf07e6 | 198 | |
252b5132 RH |
199 | @cindex @code{-mthumb-interwork} command line option, ARM |
200 | @item -mthumb-interwork | |
201 | This option specifies that the output generated by the assembler should | |
202 | be marked as supporting interworking. | |
adcf07e6 | 203 | |
252b5132 | 204 | @cindex @code{-mapcs} command line option, ARM |
0ac658b8 | 205 | @item -mapcs @code{[26|32]} |
252b5132 RH |
206 | This option specifies that the output generated by the assembler should |
207 | be marked as supporting the indicated version of the Arm Procedure. | |
208 | Calling Standard. | |
adcf07e6 | 209 | |
077b8428 NC |
210 | @cindex @code{-matpcs} command line option, ARM |
211 | @item -matpcs | |
212 | This option specifies that the output generated by the assembler should | |
213 | be marked as supporting the Arm/Thumb Procedure Calling Standard. If | |
214 | enabled this option will cause the assembler to create an empty | |
215 | debugging section in the object file called .arm.atpcs. Debuggers can | |
216 | use this to determine the ABI being used by. | |
217 | ||
adcf07e6 | 218 | @cindex @code{-mapcs-float} command line option, ARM |
252b5132 | 219 | @item -mapcs-float |
1be59579 | 220 | This indicates the floating point variant of the APCS should be |
252b5132 | 221 | used. In this variant floating point arguments are passed in FP |
550262c4 | 222 | registers rather than integer registers. |
adcf07e6 NC |
223 | |
224 | @cindex @code{-mapcs-reentrant} command line option, ARM | |
252b5132 RH |
225 | @item -mapcs-reentrant |
226 | This indicates that the reentrant variant of the APCS should be used. | |
227 | This variant supports position independent code. | |
adcf07e6 | 228 | |
33a392fb PB |
229 | @cindex @code{-mfloat-abi=} command line option, ARM |
230 | @item -mfloat-abi=@var{abi} | |
231 | This option specifies that the output generated by the assembler should be | |
232 | marked as using specified floating point ABI. | |
233 | The following values are recognized: | |
234 | @code{soft}, | |
235 | @code{softfp} | |
236 | and | |
237 | @code{hard}. | |
238 | ||
d507cf36 PB |
239 | @cindex @code{-eabi=} command line option, ARM |
240 | @item -meabi=@var{ver} | |
241 | This option specifies which EABI version the produced object files should | |
242 | conform to. | |
243 | The following values are recognised: | |
244 | @code{gnu} | |
245 | and | |
8cb51566 | 246 | @code{4}. |
d507cf36 | 247 | |
252b5132 RH |
248 | @cindex @code{-EB} command line option, ARM |
249 | @item -EB | |
250 | This option specifies that the output generated by the assembler should | |
251 | be marked as being encoded for a big-endian processor. | |
adcf07e6 | 252 | |
252b5132 RH |
253 | @cindex @code{-EL} command line option, ARM |
254 | @item -EL | |
255 | This option specifies that the output generated by the assembler should | |
256 | be marked as being encoded for a little-endian processor. | |
adcf07e6 | 257 | |
252b5132 RH |
258 | @cindex @code{-k} command line option, ARM |
259 | @cindex PIC code generation for ARM | |
260 | @item -k | |
a349d9dd PB |
261 | This option specifies that the output of the assembler should be marked |
262 | as position-independent code (PIC). | |
adcf07e6 | 263 | |
252b5132 RH |
264 | @end table |
265 | ||
266 | ||
267 | @node ARM Syntax | |
268 | @section Syntax | |
269 | @menu | |
270 | * ARM-Chars:: Special Characters | |
271 | * ARM-Regs:: Register Names | |
272 | @end menu | |
273 | ||
274 | @node ARM-Chars | |
275 | @subsection Special Characters | |
276 | ||
277 | @cindex line comment character, ARM | |
278 | @cindex ARM line comment character | |
550262c4 NC |
279 | The presence of a @samp{@@} on a line indicates the start of a comment |
280 | that extends to the end of the current line. If a @samp{#} appears as | |
281 | the first character of a line, the whole line is treated as a comment. | |
282 | ||
283 | @cindex line separator, ARM | |
284 | @cindex statement separator, ARM | |
285 | @cindex ARM line separator | |
a349d9dd PB |
286 | The @samp{;} character can be used instead of a newline to separate |
287 | statements. | |
550262c4 NC |
288 | |
289 | @cindex immediate character, ARM | |
290 | @cindex ARM immediate character | |
291 | Either @samp{#} or @samp{$} can be used to indicate immediate operands. | |
252b5132 RH |
292 | |
293 | @cindex identifiers, ARM | |
294 | @cindex ARM identifiers | |
295 | *TODO* Explain about /data modifier on symbols. | |
296 | ||
297 | @node ARM-Regs | |
298 | @subsection Register Names | |
299 | ||
300 | @cindex ARM register names | |
301 | @cindex register names, ARM | |
302 | *TODO* Explain about ARM register naming, and the predefined names. | |
303 | ||
304 | @node ARM Floating Point | |
305 | @section Floating Point | |
306 | ||
307 | @cindex floating point, ARM (@sc{ieee}) | |
308 | @cindex ARM floating point (@sc{ieee}) | |
309 | The ARM family uses @sc{ieee} floating-point numbers. | |
310 | ||
311 | ||
312 | ||
313 | @node ARM Directives | |
314 | @section ARM Machine Directives | |
315 | ||
316 | @cindex machine directives, ARM | |
317 | @cindex ARM machine directives | |
318 | @table @code | |
319 | ||
adcf07e6 NC |
320 | @cindex @code{align} directive, ARM |
321 | @item .align @var{expression} [, @var{expression}] | |
322 | This is the generic @var{.align} directive. For the ARM however if the | |
323 | first argument is zero (ie no alignment is needed) the assembler will | |
324 | behave as if the argument had been 2 (ie pad to the next four byte | |
062b7c0c | 325 | boundary). This is for compatibility with ARM's own assembler. |
adcf07e6 | 326 | |
252b5132 RH |
327 | @cindex @code{req} directive, ARM |
328 | @item @var{name} .req @var{register name} | |
329 | This creates an alias for @var{register name} called @var{name}. For | |
330 | example: | |
331 | ||
332 | @smallexample | |
333 | foo .req r0 | |
334 | @end smallexample | |
335 | ||
0bbf2aa4 NC |
336 | @cindex @code{unreq} directive, ARM |
337 | @item .unreq @var{alias-name} | |
338 | This undefines a register alias which was previously defined using the | |
339 | @code{req} directive. For example: | |
340 | ||
341 | @smallexample | |
342 | foo .req r0 | |
343 | .unreq foo | |
344 | @end smallexample | |
345 | ||
346 | An error occurs if the name is undefined. Note - this pseudo op can | |
347 | be used to delete builtin in register name aliases (eg 'r0'). This | |
348 | should only be done if it is really necessary. | |
349 | ||
252b5132 | 350 | @cindex @code{code} directive, ARM |
0ac658b8 | 351 | @item .code @code{[16|32]} |
252b5132 RH |
352 | This directive selects the instruction set being generated. The value 16 |
353 | selects Thumb, with the value 32 selecting ARM. | |
354 | ||
355 | @cindex @code{thumb} directive, ARM | |
356 | @item .thumb | |
357 | This performs the same action as @var{.code 16}. | |
358 | ||
359 | @cindex @code{arm} directive, ARM | |
360 | @item .arm | |
361 | This performs the same action as @var{.code 32}. | |
362 | ||
363 | @cindex @code{force_thumb} directive, ARM | |
364 | @item .force_thumb | |
365 | This directive forces the selection of Thumb instructions, even if the | |
366 | target processor does not support those instructions | |
367 | ||
368 | @cindex @code{thumb_func} directive, ARM | |
369 | @item .thumb_func | |
370 | This directive specifies that the following symbol is the name of a | |
371 | Thumb encoded function. This information is necessary in order to allow | |
372 | the assembler and linker to generate correct code for interworking | |
373 | between Arm and Thumb instructions and should be used even if | |
1994a7c7 NC |
374 | interworking is not going to be performed. The presence of this |
375 | directive also implies @code{.thumb} | |
252b5132 | 376 | |
5395a469 NC |
377 | @cindex @code{thumb_set} directive, ARM |
378 | @item .thumb_set | |
379 | This performs the equivalent of a @code{.set} directive in that it | |
380 | creates a symbol which is an alias for another symbol (possibly not yet | |
381 | defined). This directive also has the added property in that it marks | |
382 | the aliased symbol as being a thumb function entry point, in the same | |
383 | way that the @code{.thumb_func} directive does. | |
384 | ||
252b5132 RH |
385 | @cindex @code{.ltorg} directive, ARM |
386 | @item .ltorg | |
387 | This directive causes the current contents of the literal pool to be | |
388 | dumped into the current section (which is assumed to be the .text | |
389 | section) at the current location (aligned to a word boundary). | |
3d0c9500 NC |
390 | @code{GAS} maintains a separate literal pool for each section and each |
391 | sub-section. The @code{.ltorg} directive will only affect the literal | |
392 | pool of the current section and sub-section. At the end of assembly | |
393 | all remaining, un-empty literal pools will automatically be dumped. | |
394 | ||
395 | Note - older versions of @code{GAS} would dump the current literal | |
396 | pool any time a section change occurred. This is no longer done, since | |
397 | it prevents accurate control of the placement of literal pools. | |
252b5132 RH |
398 | |
399 | @cindex @code{.pool} directive, ARM | |
400 | @item .pool | |
401 | This is a synonym for .ltorg. | |
402 | ||
7ed4c4c5 NC |
403 | @cindex @code{.fnstart} directive, ARM |
404 | @item .unwind_fnstart | |
405 | Marks the start of a function with an unwind table entry. | |
406 | ||
407 | @cindex @code{.fnend} directive, ARM | |
408 | @item .unwind_fnend | |
409 | Marks the end of a function with an unwind table entry. The unwind index | |
410 | table entry is created when this directive is processed. | |
411 | ||
412 | If no personality routine has been specified then standard personality | |
413 | routine 0 or 1 will be used, depending on the number of unwind opcodes | |
414 | required. | |
415 | ||
416 | @cindex @code{.cantunwind} directive, ARM | |
417 | @item .cantunwind | |
418 | Prevents unwinding through the current function. No personality routine | |
419 | or exception table data is required or permitted. | |
420 | ||
421 | @cindex @code{.personality} directive, ARM | |
422 | @item .personality @var{name} | |
423 | Sets the personality routine for the current function to @var{name}. | |
424 | ||
425 | @cindex @code{.personalityindex} directive, ARM | |
426 | @item .personalityindex @var{index} | |
427 | Sets the personality routine for the current function to the EABI standard | |
428 | routine number @var{index} | |
429 | ||
430 | @cindex @code{.handlerdata} directive, ARM | |
431 | @item .handlerdata | |
432 | Marks the end of the current function, and the start of the exception table | |
433 | entry for that function. Anything between this directive and the | |
434 | @code{.fnend} directive will be added to the exception table entry. | |
435 | ||
436 | Must be preceded by a @code{.personality} or @code{.personalityindex} | |
437 | directive. | |
438 | ||
439 | @cindex @code{.save} directive, ARM | |
440 | @item .save @var{reglist} | |
441 | Generate unwinder annotations to restore the registers in @var{reglist}. | |
442 | The format of @var{reglist} is the same as the corresponding store-multiple | |
443 | instruction. | |
444 | ||
445 | @smallexample | |
446 | @exdent @emph{core registers} | |
447 | .save @{r4, r5, r6, lr@} | |
448 | stmfd sp!, @{r4, r5, r6, lr@} | |
449 | @exdent @emph{FPA registers} | |
450 | .save f4, 2 | |
451 | sfmfd f4, 2, [sp]! | |
452 | @exdent @emph{VFP registers} | |
453 | .save @{d8, d9, d10@} | |
454 | fstmdf sp!, @{d8, d9, d10@} | |
455 | @exdent @emph{iWMMXt registers} | |
456 | .save @{wr10, wr11@} | |
457 | wstrd wr11, [sp, #-8]! | |
458 | wstrd wr10, [sp, #-8]! | |
459 | or | |
460 | .save wr11 | |
461 | wstrd wr11, [sp, #-8]! | |
462 | .save wr10 | |
463 | wstrd wr10, [sp, #-8]! | |
464 | @end smallexample | |
465 | ||
466 | @cindex @code{.pad} directive, ARM | |
467 | @item .pad #@var{count} | |
468 | Generate unwinder annotations for a stack adjustment of @var{count} bytes. | |
469 | A positive value indicates the function prologue allocated stack space by | |
470 | decrementing the stack pointer. | |
471 | ||
472 | @cindex @code{.movsp} directive, ARM | |
473 | @item .movsp @var{reg} | |
474 | Tell the unwinder that @var{reg} contains the current stack pointer. | |
475 | ||
476 | @cindex @code{.setfp} directive, ARM | |
477 | @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] | |
478 | Make all unwinder annotations relaive to a frame pointer. Without this | |
479 | the unwinder will use offsets from the stack pointer. | |
480 | ||
481 | The syntax of this directive is the same as the @code{sub} or @code{mov} | |
482 | instruction used to set the frame pointer. @var{spreg} must be either | |
483 | @code{sp} or mentioned in a previous @code{.movsp} directive. | |
484 | ||
485 | @smallexample | |
486 | .movsp ip | |
487 | mov ip, sp | |
488 | @dots{} | |
489 | .setfp fp, ip, #4 | |
490 | sub fp, ip, #4 | |
491 | @end smallexample | |
492 | ||
493 | @cindex @code{.unwind_raw} directive, ARM | |
494 | @item .raw @var{offset}, @var{byte1}, @dots{} | |
495 | Insert one of more arbitary unwind opcode bytes, which are known to adjust | |
496 | the stack pointer by @var{offset} bytes. | |
497 | ||
498 | For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to | |
499 | @code{.save @{r0@}} | |
500 | ||
252b5132 RH |
501 | @end table |
502 | ||
503 | @node ARM Opcodes | |
504 | @section Opcodes | |
505 | ||
506 | @cindex ARM opcodes | |
507 | @cindex opcodes for ARM | |
49a5575c NC |
508 | @code{@value{AS}} implements all the standard ARM opcodes. It also |
509 | implements several pseudo opcodes, including several synthetic load | |
510 | instructions. | |
252b5132 | 511 | |
49a5575c NC |
512 | @table @code |
513 | ||
514 | @cindex @code{NOP} pseudo op, ARM | |
515 | @item NOP | |
516 | @smallexample | |
517 | nop | |
518 | @end smallexample | |
252b5132 | 519 | |
49a5575c NC |
520 | This pseudo op will always evaluate to a legal ARM instruction that does |
521 | nothing. Currently it will evaluate to MOV r0, r0. | |
252b5132 | 522 | |
49a5575c NC |
523 | @cindex @code{LDR reg,=<label>} pseudo op, ARM |
524 | @item LDR | |
252b5132 RH |
525 | @smallexample |
526 | ldr <register> , = <expression> | |
527 | @end smallexample | |
528 | ||
529 | If expression evaluates to a numeric constant then a MOV or MVN | |
530 | instruction will be used in place of the LDR instruction, if the | |
531 | constant can be generated by either of these instructions. Otherwise | |
532 | the constant will be placed into the nearest literal pool (if it not | |
533 | already there) and a PC relative LDR instruction will be generated. | |
534 | ||
49a5575c NC |
535 | @cindex @code{ADR reg,<label>} pseudo op, ARM |
536 | @item ADR | |
537 | @smallexample | |
538 | adr <register> <label> | |
539 | @end smallexample | |
540 | ||
541 | This instruction will load the address of @var{label} into the indicated | |
542 | register. The instruction will evaluate to a PC relative ADD or SUB | |
543 | instruction depending upon where the label is located. If the label is | |
544 | out of range, or if it is not defined in the same file (and section) as | |
545 | the ADR instruction, then an error will be generated. This instruction | |
546 | will not make use of the literal pool. | |
547 | ||
548 | @cindex @code{ADRL reg,<label>} pseudo op, ARM | |
549 | @item ADRL | |
550 | @smallexample | |
551 | adrl <register> <label> | |
552 | @end smallexample | |
553 | ||
554 | This instruction will load the address of @var{label} into the indicated | |
a349d9dd | 555 | register. The instruction will evaluate to one or two PC relative ADD |
49a5575c NC |
556 | or SUB instructions depending upon where the label is located. If a |
557 | second instruction is not needed a NOP instruction will be generated in | |
558 | its place, so that this instruction is always 8 bytes long. | |
559 | ||
560 | If the label is out of range, or if it is not defined in the same file | |
561 | (and section) as the ADRL instruction, then an error will be generated. | |
562 | This instruction will not make use of the literal pool. | |
563 | ||
564 | @end table | |
565 | ||
252b5132 RH |
566 | For information on the ARM or Thumb instruction sets, see @cite{ARM |
567 | Software Development Toolkit Reference Manual}, Advanced RISC Machines | |
568 | Ltd. | |
569 | ||
6057a28f NC |
570 | @node ARM Mapping Symbols |
571 | @section Mapping Symbols | |
572 | ||
573 | The ARM ELF specification requires that special symbols be inserted | |
574 | into object files to mark certain features: | |
575 | ||
576 | @table @code | |
577 | ||
578 | @cindex @code{$a} | |
579 | @item $a | |
580 | At the start of a region of code containing ARM instructions. | |
581 | ||
582 | @cindex @code{$t} | |
583 | @item $t | |
584 | At the start of a region of code containing THUMB instructions. | |
585 | ||
586 | @cindex @code{$d} | |
587 | @item $d | |
588 | At the start of a region of data. | |
589 | ||
590 | @end table | |
591 | ||
592 | The assembler will automatically insert these symbols for you - there | |
593 | is no need to code them yourself. Support for tagging symbols ($b, | |
594 | $f, $p and $m) which is also mentioned in the current ARM ELF | |
595 | specification is not implemented. This is because they have been | |
596 | dropped from the new EABI and so tools cannot rely upon their | |
597 | presence. | |
598 |