Commit | Line | Data |
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82704155 | 1 | @c Copyright (C) 1996-2019 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | ||
5 | @ifset GENERIC | |
6 | @page | |
7 | @node ARM-Dependent | |
8 | @chapter ARM Dependent Features | |
9 | @end ifset | |
10 | ||
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter ARM Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex ARM support | |
17 | @cindex Thumb support | |
18 | @menu | |
19 | * ARM Options:: Options | |
20 | * ARM Syntax:: Syntax | |
21 | * ARM Floating Point:: Floating Point | |
22 | * ARM Directives:: ARM Machine Directives | |
23 | * ARM Opcodes:: Opcodes | |
6057a28f | 24 | * ARM Mapping Symbols:: Mapping Symbols |
7da4f750 | 25 | * ARM Unwinding Tutorial:: Unwinding |
252b5132 RH |
26 | @end menu |
27 | ||
28 | @node ARM Options | |
29 | @section Options | |
30 | @cindex ARM options (none) | |
31 | @cindex options for ARM (none) | |
adcf07e6 | 32 | |
252b5132 | 33 | @table @code |
adcf07e6 | 34 | |
a05a5b64 | 35 | @cindex @code{-mcpu=} command-line option, ARM |
92081f48 | 36 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] |
252b5132 RH |
37 | This option specifies the target processor. The assembler will issue an |
38 | error message if an attempt is made to assemble an instruction which | |
03b1477f | 39 | will not execute on the target processor. The following processor names are |
34bca508 | 40 | recognized: |
03b1477f RE |
41 | @code{arm1}, |
42 | @code{arm2}, | |
43 | @code{arm250}, | |
44 | @code{arm3}, | |
45 | @code{arm6}, | |
46 | @code{arm60}, | |
47 | @code{arm600}, | |
48 | @code{arm610}, | |
49 | @code{arm620}, | |
50 | @code{arm7}, | |
51 | @code{arm7m}, | |
52 | @code{arm7d}, | |
53 | @code{arm7dm}, | |
54 | @code{arm7di}, | |
55 | @code{arm7dmi}, | |
56 | @code{arm70}, | |
57 | @code{arm700}, | |
58 | @code{arm700i}, | |
59 | @code{arm710}, | |
60 | @code{arm710t}, | |
61 | @code{arm720}, | |
62 | @code{arm720t}, | |
63 | @code{arm740t}, | |
64 | @code{arm710c}, | |
65 | @code{arm7100}, | |
66 | @code{arm7500}, | |
67 | @code{arm7500fe}, | |
68 | @code{arm7t}, | |
69 | @code{arm7tdmi}, | |
1ff4677c | 70 | @code{arm7tdmi-s}, |
03b1477f RE |
71 | @code{arm8}, |
72 | @code{arm810}, | |
73 | @code{strongarm}, | |
74 | @code{strongarm1}, | |
75 | @code{strongarm110}, | |
76 | @code{strongarm1100}, | |
77 | @code{strongarm1110}, | |
78 | @code{arm9}, | |
79 | @code{arm920}, | |
80 | @code{arm920t}, | |
81 | @code{arm922t}, | |
82 | @code{arm940t}, | |
83 | @code{arm9tdmi}, | |
7fac0536 NC |
84 | @code{fa526} (Faraday FA526 processor), |
85 | @code{fa626} (Faraday FA626 processor), | |
03b1477f | 86 | @code{arm9e}, |
7de9afa2 | 87 | @code{arm926e}, |
1ff4677c | 88 | @code{arm926ej-s}, |
03b1477f RE |
89 | @code{arm946e-r0}, |
90 | @code{arm946e}, | |
db8ac8f9 | 91 | @code{arm946e-s}, |
03b1477f RE |
92 | @code{arm966e-r0}, |
93 | @code{arm966e}, | |
db8ac8f9 PB |
94 | @code{arm966e-s}, |
95 | @code{arm968e-s}, | |
03b1477f | 96 | @code{arm10t}, |
db8ac8f9 | 97 | @code{arm10tdmi}, |
03b1477f RE |
98 | @code{arm10e}, |
99 | @code{arm1020}, | |
100 | @code{arm1020t}, | |
7de9afa2 | 101 | @code{arm1020e}, |
db8ac8f9 | 102 | @code{arm1022e}, |
1ff4677c | 103 | @code{arm1026ej-s}, |
4a58c4bd NC |
104 | @code{fa606te} (Faraday FA606TE processor), |
105 | @code{fa616te} (Faraday FA616TE processor), | |
7fac0536 | 106 | @code{fa626te} (Faraday FA626TE processor), |
4a58c4bd | 107 | @code{fmp626} (Faraday FMP626 processor), |
7fac0536 | 108 | @code{fa726te} (Faraday FA726TE processor), |
1ff4677c RE |
109 | @code{arm1136j-s}, |
110 | @code{arm1136jf-s}, | |
db8ac8f9 PB |
111 | @code{arm1156t2-s}, |
112 | @code{arm1156t2f-s}, | |
0dd132b6 NC |
113 | @code{arm1176jz-s}, |
114 | @code{arm1176jzf-s}, | |
115 | @code{mpcore}, | |
116 | @code{mpcorenovfp}, | |
b38f9f31 | 117 | @code{cortex-a5}, |
c90460e4 | 118 | @code{cortex-a7}, |
62b3e311 | 119 | @code{cortex-a8}, |
15290f0a | 120 | @code{cortex-a9}, |
dbb1f804 | 121 | @code{cortex-a15}, |
ed5491b9 | 122 | @code{cortex-a17}, |
6735952f | 123 | @code{cortex-a32}, |
43cdc0a8 | 124 | @code{cortex-a35}, |
4469186b | 125 | @code{cortex-a53}, |
15a7695f | 126 | @code{cortex-a55}, |
4469186b KT |
127 | @code{cortex-a57}, |
128 | @code{cortex-a72}, | |
362a3eba | 129 | @code{cortex-a73}, |
15a7695f | 130 | @code{cortex-a75}, |
7ebd1359 | 131 | @code{cortex-a76}, |
ef8df4ca | 132 | @code{ares}, |
62b3e311 | 133 | @code{cortex-r4}, |
307c948d | 134 | @code{cortex-r4f}, |
70a8bc5b | 135 | @code{cortex-r5}, |
136 | @code{cortex-r7}, | |
5f474010 | 137 | @code{cortex-r8}, |
0cda1e19 | 138 | @code{cortex-r52}, |
b19ea8d2 | 139 | @code{cortex-m33}, |
ce1b0a45 | 140 | @code{cortex-m23}, |
a715796b | 141 | @code{cortex-m7}, |
7ef07ba0 | 142 | @code{cortex-m4}, |
62b3e311 | 143 | @code{cortex-m3}, |
5b19eaba NC |
144 | @code{cortex-m1}, |
145 | @code{cortex-m0}, | |
ce32bd10 | 146 | @code{cortex-m0plus}, |
246496bb | 147 | @code{exynos-m1}, |
ea0d6bb9 PT |
148 | @code{marvell-pj4}, |
149 | @code{marvell-whitney}, | |
83f43c83 | 150 | @code{neoverse-n1}, |
ea0d6bb9 PT |
151 | @code{xgene1}, |
152 | @code{xgene2}, | |
03b1477f RE |
153 | @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), |
154 | @code{i80200} (Intel XScale processor) | |
e16bb312 | 155 | @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) |
03b1477f | 156 | and |
34bca508 | 157 | @code{xscale}. |
03b1477f RE |
158 | The special name @code{all} may be used to allow the |
159 | assembler to accept instructions valid for any ARM processor. | |
160 | ||
34bca508 L |
161 | In addition to the basic instruction set, the assembler can be told to |
162 | accept various extension mnemonics that extend the processor using the | |
03b1477f | 163 | co-processor instruction space. For example, @code{-mcpu=arm920+maverick} |
34bca508 | 164 | is equivalent to specifying @code{-mcpu=ep9312}. |
69133863 | 165 | |
34bca508 | 166 | Multiple extensions may be specified, separated by a @code{+}. The |
69133863 MGD |
167 | extensions should be specified in ascending alphabetical order. |
168 | ||
34bca508 | 169 | Some extensions may be restricted to particular architectures; this is |
60e5ef9f MGD |
170 | documented in the list of extensions below. |
171 | ||
34bca508 L |
172 | Extension mnemonics may also be removed from those the assembler accepts. |
173 | This is done be prepending @code{no} to the option that adds the extension. | |
174 | Extensions that are removed should be listed after all extensions which have | |
175 | been added, again in ascending alphabetical order. For example, | |
69133863 MGD |
176 | @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}. |
177 | ||
178 | ||
eea54501 | 179 | The following extensions are currently supported: |
ea0d6bb9 | 180 | @code{crc} |
bca38921 | 181 | @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), |
c604a79a | 182 | @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}), |
bca38921 | 183 | @code{fp} (Floating Point Extensions for v8-A architecture), |
01f48020 TC |
184 | @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}), |
185 | @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}), | |
bca38921 | 186 | @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures), |
69133863 MGD |
187 | @code{iwmmxt}, |
188 | @code{iwmmxt2}, | |
ea0d6bb9 | 189 | @code{xscale}, |
69133863 | 190 | @code{maverick}, |
ea0d6bb9 PT |
191 | @code{mp} (Multiprocessing Extensions for v7-A and v7-R |
192 | architectures), | |
b2a5fbdc | 193 | @code{os} (Operating System for v6M architecture), |
dad0c3bf SD |
194 | @code{predres} (Execution and Data Prediction Restriction Instruction for |
195 | v8-A architectures, added by default from v8.5-A), | |
7fadb25d SD |
196 | @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by |
197 | default from v8.5-A), | |
f4c65163 | 198 | @code{sec} (Security Extensions for v6K and v7-A architectures), |
bca38921 | 199 | @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), |
34bca508 | 200 | @code{virt} (Virtualization Extensions for v7-A architecture, implies |
90ec0d68 | 201 | @code{idiv}), |
33eaf5de | 202 | @code{pan} (Privileged Access Never Extensions for v8-A architecture), |
4d1464f2 MW |
203 | @code{ras} (Reliability, Availability and Serviceability extensions |
204 | for v8-A architecture), | |
d6b4b13e MW |
205 | @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies |
206 | @code{simd}) | |
03b1477f | 207 | and |
69133863 | 208 | @code{xscale}. |
03b1477f | 209 | |
a05a5b64 | 210 | @cindex @code{-march=} command-line option, ARM |
92081f48 | 211 | @item -march=@var{architecture}[+@var{extension}@dots{}] |
252b5132 RH |
212 | This option specifies the target architecture. The assembler will issue |
213 | an error message if an attempt is made to assemble an instruction which | |
34bca508 L |
214 | will not execute on the target architecture. The following architecture |
215 | names are recognized: | |
03b1477f RE |
216 | @code{armv1}, |
217 | @code{armv2}, | |
218 | @code{armv2a}, | |
219 | @code{armv2s}, | |
220 | @code{armv3}, | |
221 | @code{armv3m}, | |
222 | @code{armv4}, | |
223 | @code{armv4xm}, | |
224 | @code{armv4t}, | |
225 | @code{armv4txm}, | |
226 | @code{armv5}, | |
227 | @code{armv5t}, | |
228 | @code{armv5txm}, | |
229 | @code{armv5te}, | |
09d92015 | 230 | @code{armv5texp}, |
c5f98204 | 231 | @code{armv6}, |
1ddd7f43 | 232 | @code{armv6j}, |
0dd132b6 NC |
233 | @code{armv6k}, |
234 | @code{armv6z}, | |
f33026a9 | 235 | @code{armv6kz}, |
b2a5fbdc MGD |
236 | @code{armv6-m}, |
237 | @code{armv6s-m}, | |
62b3e311 | 238 | @code{armv7}, |
c450d570 | 239 | @code{armv7-a}, |
c9fb6e58 | 240 | @code{armv7ve}, |
c450d570 PB |
241 | @code{armv7-r}, |
242 | @code{armv7-m}, | |
9e3c6df6 | 243 | @code{armv7e-m}, |
bca38921 | 244 | @code{armv8-a}, |
a5932920 | 245 | @code{armv8.1-a}, |
56a1b672 | 246 | @code{armv8.2-a}, |
a12fd8e1 | 247 | @code{armv8.3-a}, |
ced40572 | 248 | @code{armv8-r}, |
dec41383 | 249 | @code{armv8.4-a}, |
23f233a5 | 250 | @code{armv8.5-a}, |
34ef62f4 AV |
251 | @code{armv8-m.base}, |
252 | @code{armv8-m.main}, | |
e0991585 | 253 | @code{armv8.1-m.main}, |
34ef62f4 | 254 | @code{iwmmxt}, |
ea0d6bb9 | 255 | @code{iwmmxt2} |
03b1477f RE |
256 | and |
257 | @code{xscale}. | |
258 | If both @code{-mcpu} and | |
259 | @code{-march} are specified, the assembler will use | |
260 | the setting for @code{-mcpu}. | |
261 | ||
34ef62f4 AV |
262 | The architecture option can be extended with a set extension options. These |
263 | extensions are context sensitive, i.e. the same extension may mean different | |
264 | things when used with different architectures. When used together with a | |
265 | @code{-mfpu} option, the union of both feature enablement is taken. | |
266 | See their availability and meaning below: | |
267 | ||
268 | For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}: | |
269 | ||
270 | @code{+fp}: Enables VFPv2 instructions. | |
271 | @code{+nofp}: Disables all FPU instrunctions. | |
272 | ||
273 | For @code{armv7}: | |
274 | ||
275 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. | |
276 | @code{+nofp}: Disables all FPU instructions. | |
277 | ||
278 | For @code{armv7-a}: | |
279 | ||
280 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. | |
281 | @code{+vfpv3-d16}: Alias for @code{+fp}. | |
282 | @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. | |
283 | @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point | |
284 | conversion instructions and 16 double-word registers. | |
285 | @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion | |
286 | instructions and 32 double-word registers. | |
287 | @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers. | |
288 | @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. | |
289 | @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word | |
290 | registers. | |
291 | @code{+neon}: Alias for @code{+simd}. | |
292 | @code{+neon-vfpv3}: Alias for @code{+simd}. | |
293 | @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and | |
294 | NEONv1 instructions with 32 double-word registers. | |
295 | @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 | |
296 | double-word registers. | |
297 | @code{+mp}: Enables Multiprocessing Extensions. | |
298 | @code{+sec}: Enables Security Extensions. | |
299 | @code{+nofp}: Disables all FPU and NEON instructions. | |
300 | @code{+nosimd}: Disables all NEON instructions. | |
301 | ||
302 | For @code{armv7ve}: | |
303 | ||
304 | @code{+fp}: Enables VFPv4 instructions with 16 double-word registers. | |
305 | @code{+vfpv4-d16}: Alias for @code{+fp}. | |
306 | @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers. | |
307 | @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. | |
308 | @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point | |
309 | conversion instructions and 16 double-word registers. | |
310 | @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion | |
311 | instructions and 32 double-word registers. | |
312 | @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. | |
313 | @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 | |
314 | double-word registers. | |
315 | @code{+neon-vfpv4}: Alias for @code{+simd}. | |
316 | @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word | |
317 | registers. | |
318 | @code{+neon-vfpv3}: Alias for @code{+neon}. | |
319 | @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and | |
320 | NEONv1 instructions with 32 double-word registers. | |
321 | double-word registers. | |
322 | @code{+nofp}: Disables all FPU and NEON instructions. | |
323 | @code{+nosimd}: Disables all NEON instructions. | |
324 | ||
325 | For @code{armv7-r}: | |
326 | ||
327 | @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16 | |
328 | double-word registers. | |
329 | @code{+vfpv3xd}: Alias for @code{+fp.sp}. | |
330 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. | |
331 | @code{+vfpv3-d16}: Alias for @code{+fp}. | |
332 | @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half | |
333 | floating-point conversion instructions with 16 double-word registers. | |
334 | @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point | |
335 | conversion instructions with 16 double-word registers. | |
336 | @code{+idiv}: Enables integer division instructions in ARM mode. | |
337 | @code{+nofp}: Disables all FPU instructions. | |
338 | ||
339 | For @code{armv7e-m}: | |
340 | ||
341 | @code{+fp}: Enables single-precision only VFPv4 instructions with 16 | |
342 | double-word registers. | |
343 | @code{+vfpvf4-sp-d16}: Alias for @code{+fp}. | |
344 | @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 | |
345 | double-word registers. | |
346 | @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. | |
347 | @code{+fpv5-d16"}: Alias for @code{+fp.dp}. | |
348 | @code{+nofp}: Disables all FPU instructions. | |
349 | ||
350 | For @code{armv8-m.main}: | |
351 | ||
352 | @code{+dsp}: Enables DSP Extension. | |
353 | @code{+fp}: Enables single-precision only VFPv5 instructions with 16 | |
354 | double-word registers. | |
355 | @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. | |
356 | @code{+nofp}: Disables all FPU instructions. | |
357 | @code{+nodsp}: Disables DSP Extension. | |
358 | ||
e0991585 AV |
359 | For @code{armv8.1-m.main}: |
360 | ||
361 | @code{+dsp}: Enables DSP Extension. | |
362 | @code{+fp}: Enables single and half precision scalar Floating Point Extensions | |
363 | for Armv8.1-M Mainline with 16 double-word registers. | |
364 | @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for | |
365 | Armv8.1-M Mainline, implies @code{+fp}. | |
a7ad558c AV |
366 | @code{+mve}: Enables integer only M-profile Vector Extension for |
367 | Armv8.1-M Mainline, implies @code{+dsp}. | |
368 | @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for | |
369 | Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}. | |
e0991585 AV |
370 | @code{+nofp}: Disables all FPU instructions. |
371 | @code{+nodsp}: Disables DSP Extension. | |
a7ad558c | 372 | @code{+nomve}: Disables all M-profile Vector Extensions. |
e0991585 | 373 | |
34ef62f4 AV |
374 | For @code{armv8-a}: |
375 | ||
376 | @code{+crc}: Enables CRC32 Extension. | |
377 | @code{+simd}: Enables VFP and NEON for Armv8-A. | |
378 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
379 | @code{+simd}. | |
380 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
381 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
382 | for Armv8-A. | |
383 | @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. | |
384 | @code{+nocrypto}: Disables Cryptography Extensions. | |
385 | ||
386 | For @code{armv8.1-a}: | |
387 | ||
388 | @code{+simd}: Enables VFP and NEON for Armv8.1-A. | |
389 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
390 | @code{+simd}. | |
391 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
392 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
393 | for Armv8-A. | |
394 | @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. | |
395 | @code{+nocrypto}: Disables Cryptography Extensions. | |
396 | ||
397 | For @code{armv8.2-a} and @code{armv8.3-a}: | |
398 | ||
399 | @code{+simd}: Enables VFP and NEON for Armv8.1-A. | |
400 | @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}. | |
401 | @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions | |
402 | for Armv8.2-A, implies @code{+fp16}. | |
403 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
404 | @code{+simd}. | |
405 | @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies | |
406 | @code{+simd}. | |
407 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
408 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
409 | for Armv8-A. | |
410 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. | |
411 | @code{+nocrypto}: Disables Cryptography Extensions. | |
412 | ||
413 | For @code{armv8.4-a}: | |
414 | ||
415 | @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for | |
416 | Armv8.2-A. | |
417 | @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication | |
418 | Variant Extensions for Armv8.2-A, implies @code{+simd}. | |
419 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
420 | @code{+simd}. | |
421 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
422 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
423 | for Armv8-A. | |
424 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. | |
425 | @code{+nocryptp}: Disables Cryptography Extensions. | |
426 | ||
427 | For @code{armv8.5-a}: | |
428 | ||
429 | @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for | |
430 | Armv8.2-A. | |
431 | @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication | |
432 | Variant Extensions for Armv8.2-A, implies @code{+simd}. | |
433 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
434 | @code{+simd}. | |
435 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. | |
436 | @code{+nocryptp}: Disables Cryptography Extensions. | |
437 | ||
03b1477f | 438 | |
a05a5b64 | 439 | @cindex @code{-mfpu=} command-line option, ARM |
03b1477f RE |
440 | @item -mfpu=@var{floating-point-format} |
441 | ||
442 | This option specifies the floating point format to assemble for. The | |
443 | assembler will issue an error message if an attempt is made to assemble | |
34bca508 | 444 | an instruction which will not execute on the target floating point unit. |
03b1477f RE |
445 | The following format options are recognized: |
446 | @code{softfpa}, | |
447 | @code{fpe}, | |
bc89618b RE |
448 | @code{fpe2}, |
449 | @code{fpe3}, | |
03b1477f RE |
450 | @code{fpa}, |
451 | @code{fpa10}, | |
452 | @code{fpa11}, | |
453 | @code{arm7500fe}, | |
454 | @code{softvfp}, | |
455 | @code{softvfp+vfp}, | |
456 | @code{vfp}, | |
457 | @code{vfp10}, | |
458 | @code{vfp10-r0}, | |
459 | @code{vfp9}, | |
460 | @code{vfpxd}, | |
62f3b8c8 PB |
461 | @code{vfpv2}, |
462 | @code{vfpv3}, | |
463 | @code{vfpv3-fp16}, | |
464 | @code{vfpv3-d16}, | |
465 | @code{vfpv3-d16-fp16}, | |
466 | @code{vfpv3xd}, | |
467 | @code{vfpv3xd-d16}, | |
468 | @code{vfpv4}, | |
469 | @code{vfpv4-d16}, | |
f0cd0667 | 470 | @code{fpv4-sp-d16}, |
a715796b TG |
471 | @code{fpv5-sp-d16}, |
472 | @code{fpv5-d16}, | |
bca38921 | 473 | @code{fp-armv8}, |
09d92015 MM |
474 | @code{arm1020t}, |
475 | @code{arm1020e}, | |
b1cc4aeb | 476 | @code{arm1136jf-s}, |
62f3b8c8 PB |
477 | @code{maverick}, |
478 | @code{neon}, | |
d5e0ba9c RE |
479 | @code{neon-vfpv3}, |
480 | @code{neon-fp16}, | |
bca38921 MGD |
481 | @code{neon-vfpv4}, |
482 | @code{neon-fp-armv8}, | |
081e4c7d MW |
483 | @code{crypto-neon-fp-armv8}, |
484 | @code{neon-fp-armv8.1} | |
d6b4b13e | 485 | and |
081e4c7d | 486 | @code{crypto-neon-fp-armv8.1}. |
03b1477f RE |
487 | |
488 | In addition to determining which instructions are assembled, this option | |
489 | also affects the way in which the @code{.double} assembler directive behaves | |
490 | when assembling little-endian code. | |
491 | ||
34bca508 | 492 | The default is dependent on the processor selected. For Architecture 5 or |
d5e0ba9c | 493 | later, the default is to assemble for VFP instructions; for earlier |
03b1477f | 494 | architectures the default is to assemble for FPA instructions. |
adcf07e6 | 495 | |
a05a5b64 | 496 | @cindex @code{-mthumb} command-line option, ARM |
252b5132 | 497 | @item -mthumb |
03b1477f | 498 | This option specifies that the assembler should start assembling Thumb |
34bca508 | 499 | instructions; that is, it should behave as though the file starts with a |
03b1477f | 500 | @code{.code 16} directive. |
adcf07e6 | 501 | |
a05a5b64 | 502 | @cindex @code{-mthumb-interwork} command-line option, ARM |
252b5132 RH |
503 | @item -mthumb-interwork |
504 | This option specifies that the output generated by the assembler should | |
fc6141f0 NC |
505 | be marked as supporting interworking. It also affects the behaviour |
506 | of the @code{ADR} and @code{ADRL} pseudo opcodes. | |
adcf07e6 | 507 | |
a05a5b64 | 508 | @cindex @code{-mimplicit-it} command-line option, ARM |
52970753 NC |
509 | @item -mimplicit-it=never |
510 | @itemx -mimplicit-it=always | |
511 | @itemx -mimplicit-it=arm | |
512 | @itemx -mimplicit-it=thumb | |
513 | The @code{-mimplicit-it} option controls the behavior of the assembler when | |
514 | conditional instructions are not enclosed in IT blocks. | |
515 | There are four possible behaviors. | |
516 | If @code{never} is specified, such constructs cause a warning in ARM | |
517 | code and an error in Thumb-2 code. | |
518 | If @code{always} is specified, such constructs are accepted in both | |
519 | ARM and Thumb-2 code, where the IT instruction is added implicitly. | |
520 | If @code{arm} is specified, such constructs are accepted in ARM code | |
521 | and cause an error in Thumb-2 code. | |
522 | If @code{thumb} is specified, such constructs cause a warning in ARM | |
523 | code and are accepted in Thumb-2 code. If you omit this option, the | |
524 | behavior is equivalent to @code{-mimplicit-it=arm}. | |
e07e6e58 | 525 | |
a05a5b64 TP |
526 | @cindex @code{-mapcs-26} command-line option, ARM |
527 | @cindex @code{-mapcs-32} command-line option, ARM | |
5a5829dd NS |
528 | @item -mapcs-26 |
529 | @itemx -mapcs-32 | |
530 | These options specify that the output generated by the assembler should | |
252b5132 RH |
531 | be marked as supporting the indicated version of the Arm Procedure. |
532 | Calling Standard. | |
adcf07e6 | 533 | |
a05a5b64 | 534 | @cindex @code{-matpcs} command-line option, ARM |
077b8428 | 535 | @item -matpcs |
34bca508 | 536 | This option specifies that the output generated by the assembler should |
077b8428 NC |
537 | be marked as supporting the Arm/Thumb Procedure Calling Standard. If |
538 | enabled this option will cause the assembler to create an empty | |
539 | debugging section in the object file called .arm.atpcs. Debuggers can | |
540 | use this to determine the ABI being used by. | |
541 | ||
a05a5b64 | 542 | @cindex @code{-mapcs-float} command-line option, ARM |
252b5132 | 543 | @item -mapcs-float |
1be59579 | 544 | This indicates the floating point variant of the APCS should be |
252b5132 | 545 | used. In this variant floating point arguments are passed in FP |
550262c4 | 546 | registers rather than integer registers. |
adcf07e6 | 547 | |
a05a5b64 | 548 | @cindex @code{-mapcs-reentrant} command-line option, ARM |
252b5132 RH |
549 | @item -mapcs-reentrant |
550 | This indicates that the reentrant variant of the APCS should be used. | |
551 | This variant supports position independent code. | |
adcf07e6 | 552 | |
a05a5b64 | 553 | @cindex @code{-mfloat-abi=} command-line option, ARM |
33a392fb PB |
554 | @item -mfloat-abi=@var{abi} |
555 | This option specifies that the output generated by the assembler should be | |
556 | marked as using specified floating point ABI. | |
557 | The following values are recognized: | |
558 | @code{soft}, | |
559 | @code{softfp} | |
560 | and | |
561 | @code{hard}. | |
562 | ||
a05a5b64 | 563 | @cindex @code{-eabi=} command-line option, ARM |
d507cf36 PB |
564 | @item -meabi=@var{ver} |
565 | This option specifies which EABI version the produced object files should | |
566 | conform to. | |
b45619c0 | 567 | The following values are recognized: |
3a4a14e9 PB |
568 | @code{gnu}, |
569 | @code{4} | |
d507cf36 | 570 | and |
3a4a14e9 | 571 | @code{5}. |
d507cf36 | 572 | |
a05a5b64 | 573 | @cindex @code{-EB} command-line option, ARM |
252b5132 RH |
574 | @item -EB |
575 | This option specifies that the output generated by the assembler should | |
576 | be marked as being encoded for a big-endian processor. | |
adcf07e6 | 577 | |
080bb7bb NC |
578 | Note: If a program is being built for a system with big-endian data |
579 | and little-endian instructions then it should be assembled with the | |
580 | @option{-EB} option, (all of it, code and data) and then linked with | |
581 | the @option{--be8} option. This will reverse the endianness of the | |
582 | instructions back to little-endian, but leave the data as big-endian. | |
583 | ||
a05a5b64 | 584 | @cindex @code{-EL} command-line option, ARM |
252b5132 RH |
585 | @item -EL |
586 | This option specifies that the output generated by the assembler should | |
587 | be marked as being encoded for a little-endian processor. | |
adcf07e6 | 588 | |
a05a5b64 | 589 | @cindex @code{-k} command-line option, ARM |
252b5132 RH |
590 | @cindex PIC code generation for ARM |
591 | @item -k | |
a349d9dd PB |
592 | This option specifies that the output of the assembler should be marked |
593 | as position-independent code (PIC). | |
adcf07e6 | 594 | |
a05a5b64 | 595 | @cindex @code{--fix-v4bx} command-line option, ARM |
845b51d6 PB |
596 | @item --fix-v4bx |
597 | Allow @code{BX} instructions in ARMv4 code. This is intended for use with | |
598 | the linker option of the same name. | |
599 | ||
a05a5b64 | 600 | @cindex @code{-mwarn-deprecated} command-line option, ARM |
278df34e NS |
601 | @item -mwarn-deprecated |
602 | @itemx -mno-warn-deprecated | |
603 | Enable or disable warnings about using deprecated options or | |
604 | features. The default is to warn. | |
605 | ||
a05a5b64 | 606 | @cindex @code{-mccs} command-line option, ARM |
2e6976a8 DG |
607 | @item -mccs |
608 | Turns on CodeComposer Studio assembly syntax compatibility mode. | |
609 | ||
a05a5b64 | 610 | @cindex @code{-mwarn-syms} command-line option, ARM |
8b2d793c NC |
611 | @item -mwarn-syms |
612 | @itemx -mno-warn-syms | |
613 | Enable or disable warnings about symbols that match the names of ARM | |
614 | instructions. The default is to warn. | |
615 | ||
252b5132 RH |
616 | @end table |
617 | ||
618 | ||
619 | @node ARM Syntax | |
620 | @section Syntax | |
621 | @menu | |
cab7e4d9 | 622 | * ARM-Instruction-Set:: Instruction Set |
252b5132 RH |
623 | * ARM-Chars:: Special Characters |
624 | * ARM-Regs:: Register Names | |
b6895b4f | 625 | * ARM-Relocations:: Relocations |
99f1a7a7 | 626 | * ARM-Neon-Alignment:: NEON Alignment Specifiers |
252b5132 RH |
627 | @end menu |
628 | ||
cab7e4d9 NC |
629 | @node ARM-Instruction-Set |
630 | @subsection Instruction Set Syntax | |
631 | Two slightly different syntaxes are support for ARM and THUMB | |
632 | instructions. The default, @code{divided}, uses the old style where | |
633 | ARM and THUMB instructions had their own, separate syntaxes. The new, | |
634 | @code{unified} syntax, which can be selected via the @code{.syntax} | |
635 | directive, and has the following main features: | |
636 | ||
9e6f3811 AS |
637 | @itemize @bullet |
638 | @item | |
cab7e4d9 NC |
639 | Immediate operands do not require a @code{#} prefix. |
640 | ||
9e6f3811 | 641 | @item |
cab7e4d9 NC |
642 | The @code{IT} instruction may appear, and if it does it is validated |
643 | against subsequent conditional affixes. In ARM mode it does not | |
644 | generate machine code, in THUMB mode it does. | |
645 | ||
9e6f3811 | 646 | @item |
cab7e4d9 NC |
647 | For ARM instructions the conditional affixes always appear at the end |
648 | of the instruction. For THUMB instructions conditional affixes can be | |
649 | used, but only inside the scope of an @code{IT} instruction. | |
650 | ||
9e6f3811 | 651 | @item |
cab7e4d9 NC |
652 | All of the instructions new to the V6T2 architecture (and later) are |
653 | available. (Only a few such instructions can be written in the | |
654 | @code{divided} syntax). | |
655 | ||
9e6f3811 | 656 | @item |
cab7e4d9 NC |
657 | The @code{.N} and @code{.W} suffixes are recognized and honored. |
658 | ||
9e6f3811 | 659 | @item |
cab7e4d9 NC |
660 | All instructions set the flags if and only if they have an @code{s} |
661 | affix. | |
9e6f3811 | 662 | @end itemize |
cab7e4d9 | 663 | |
252b5132 RH |
664 | @node ARM-Chars |
665 | @subsection Special Characters | |
666 | ||
667 | @cindex line comment character, ARM | |
668 | @cindex ARM line comment character | |
7c31ae13 NC |
669 | The presence of a @samp{@@} anywhere on a line indicates the start of |
670 | a comment that extends to the end of that line. | |
671 | ||
672 | If a @samp{#} appears as the first character of a line then the whole | |
673 | line is treated as a comment, but in this case the line could also be | |
674 | a logical line number directive (@pxref{Comments}) or a preprocessor | |
675 | control command (@pxref{Preprocessing}). | |
550262c4 NC |
676 | |
677 | @cindex line separator, ARM | |
678 | @cindex statement separator, ARM | |
679 | @cindex ARM line separator | |
a349d9dd PB |
680 | The @samp{;} character can be used instead of a newline to separate |
681 | statements. | |
550262c4 NC |
682 | |
683 | @cindex immediate character, ARM | |
684 | @cindex ARM immediate character | |
685 | Either @samp{#} or @samp{$} can be used to indicate immediate operands. | |
252b5132 RH |
686 | |
687 | @cindex identifiers, ARM | |
688 | @cindex ARM identifiers | |
689 | *TODO* Explain about /data modifier on symbols. | |
690 | ||
691 | @node ARM-Regs | |
692 | @subsection Register Names | |
693 | ||
694 | @cindex ARM register names | |
695 | @cindex register names, ARM | |
696 | *TODO* Explain about ARM register naming, and the predefined names. | |
697 | ||
b6895b4f PB |
698 | @node ARM-Relocations |
699 | @subsection ARM relocation generation | |
700 | ||
701 | @cindex data relocations, ARM | |
702 | @cindex ARM data relocations | |
703 | Specific data relocations can be generated by putting the relocation name | |
704 | in parentheses after the symbol name. For example: | |
705 | ||
706 | @smallexample | |
707 | .word foo(TARGET1) | |
708 | @end smallexample | |
709 | ||
710 | This will generate an @samp{R_ARM_TARGET1} relocation against the symbol | |
711 | @var{foo}. | |
712 | The following relocations are supported: | |
713 | @code{GOT}, | |
714 | @code{GOTOFF}, | |
715 | @code{TARGET1}, | |
716 | @code{TARGET2}, | |
717 | @code{SBREL}, | |
718 | @code{TLSGD}, | |
719 | @code{TLSLDM}, | |
720 | @code{TLSLDO}, | |
0855e32b NS |
721 | @code{TLSDESC}, |
722 | @code{TLSCALL}, | |
b43420e6 NC |
723 | @code{GOTTPOFF}, |
724 | @code{GOT_PREL} | |
b6895b4f PB |
725 | and |
726 | @code{TPOFF}. | |
727 | ||
728 | For compatibility with older toolchains the assembler also accepts | |
3da1d841 NC |
729 | @code{(PLT)} after branch targets. On legacy targets this will |
730 | generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI | |
731 | targets it will encode either the @samp{R_ARM_CALL} or | |
732 | @samp{R_ARM_JUMP24} relocation, as appropriate. | |
b6895b4f PB |
733 | |
734 | @cindex MOVW and MOVT relocations, ARM | |
735 | Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated | |
736 | by prefixing the value with @samp{#:lower16:} and @samp{#:upper16} | |
b45619c0 | 737 | respectively. For example to load the 32-bit address of foo into r0: |
252b5132 | 738 | |
b6895b4f PB |
739 | @smallexample |
740 | MOVW r0, #:lower16:foo | |
741 | MOVT r0, #:upper16:foo | |
742 | @end smallexample | |
252b5132 | 743 | |
72d98d16 MG |
744 | Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC}, |
745 | @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be | |
746 | generated by prefixing the value with @samp{#:lower0_7:#}, | |
747 | @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#} | |
748 | respectively. For example to load the 32-bit address of foo into r0: | |
749 | ||
750 | @smallexample | |
751 | MOVS r0, #:upper8_15:#foo | |
752 | LSLS r0, r0, #8 | |
753 | ADDS r0, #:upper0_7:#foo | |
754 | LSLS r0, r0, #8 | |
755 | ADDS r0, #:lower8_15:#foo | |
756 | LSLS r0, r0, #8 | |
757 | ADDS r0, #:lower0_7:#foo | |
758 | @end smallexample | |
759 | ||
ba724cfc NC |
760 | @node ARM-Neon-Alignment |
761 | @subsection NEON Alignment Specifiers | |
762 | ||
763 | @cindex alignment for NEON instructions | |
764 | Some NEON load/store instructions allow an optional address | |
765 | alignment qualifier. | |
766 | The ARM documentation specifies that this is indicated by | |
767 | @samp{@@ @var{align}}. However GAS already interprets | |
768 | the @samp{@@} character as a "line comment" start, | |
769 | so @samp{: @var{align}} is used instead. For example: | |
770 | ||
771 | @smallexample | |
772 | vld1.8 @{q0@}, [r0, :128] | |
773 | @end smallexample | |
774 | ||
775 | @node ARM Floating Point | |
776 | @section Floating Point | |
777 | ||
778 | @cindex floating point, ARM (@sc{ieee}) | |
779 | @cindex ARM floating point (@sc{ieee}) | |
780 | The ARM family uses @sc{ieee} floating-point numbers. | |
781 | ||
252b5132 RH |
782 | @node ARM Directives |
783 | @section ARM Machine Directives | |
784 | ||
785 | @cindex machine directives, ARM | |
786 | @cindex ARM machine directives | |
787 | @table @code | |
788 | ||
4a6bc624 NS |
789 | @c AAAAAAAAAAAAAAAAAAAAAAAAA |
790 | ||
2b841ec2 | 791 | @ifclear ELF |
4a6bc624 NS |
792 | @cindex @code{.2byte} directive, ARM |
793 | @cindex @code{.4byte} directive, ARM | |
794 | @cindex @code{.8byte} directive, ARM | |
795 | @item .2byte @var{expression} [, @var{expression}]* | |
796 | @itemx .4byte @var{expression} [, @var{expression}]* | |
797 | @itemx .8byte @var{expression} [, @var{expression}]* | |
798 | These directives write 2, 4 or 8 byte values to the output section. | |
2b841ec2 | 799 | @end ifclear |
4a6bc624 NS |
800 | |
801 | @cindex @code{.align} directive, ARM | |
adcf07e6 NC |
802 | @item .align @var{expression} [, @var{expression}] |
803 | This is the generic @var{.align} directive. For the ARM however if the | |
804 | first argument is zero (ie no alignment is needed) the assembler will | |
805 | behave as if the argument had been 2 (ie pad to the next four byte | |
062b7c0c | 806 | boundary). This is for compatibility with ARM's own assembler. |
adcf07e6 | 807 | |
4a6bc624 NS |
808 | @cindex @code{.arch} directive, ARM |
809 | @item .arch @var{name} | |
810 | Select the target architecture. Valid values for @var{name} are the same as | |
54691107 TP |
811 | for the @option{-march} command-line option without the instruction set |
812 | extension. | |
252b5132 | 813 | |
34bca508 | 814 | Specifying @code{.arch} clears any previously selected architecture |
69133863 MGD |
815 | extensions. |
816 | ||
817 | @cindex @code{.arch_extension} directive, ARM | |
818 | @item .arch_extension @var{name} | |
34bca508 L |
819 | Add or remove an architecture extension to the target architecture. Valid |
820 | values for @var{name} are the same as those accepted as architectural | |
a05a5b64 | 821 | extensions by the @option{-mcpu} and @option{-march} command-line options. |
69133863 MGD |
822 | |
823 | @code{.arch_extension} may be used multiple times to add or remove extensions | |
824 | incrementally to the architecture being compiled for. | |
825 | ||
4a6bc624 NS |
826 | @cindex @code{.arm} directive, ARM |
827 | @item .arm | |
828 | This performs the same action as @var{.code 32}. | |
252b5132 | 829 | |
4a6bc624 | 830 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
0bbf2aa4 | 831 | |
4a6bc624 NS |
832 | @cindex @code{.bss} directive, ARM |
833 | @item .bss | |
834 | This directive switches to the @code{.bss} section. | |
0bbf2aa4 | 835 | |
4a6bc624 NS |
836 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC |
837 | ||
838 | @cindex @code{.cantunwind} directive, ARM | |
839 | @item .cantunwind | |
840 | Prevents unwinding through the current function. No personality routine | |
841 | or exception table data is required or permitted. | |
842 | ||
843 | @cindex @code{.code} directive, ARM | |
844 | @item .code @code{[16|32]} | |
845 | This directive selects the instruction set being generated. The value 16 | |
846 | selects Thumb, with the value 32 selecting ARM. | |
847 | ||
848 | @cindex @code{.cpu} directive, ARM | |
849 | @item .cpu @var{name} | |
850 | Select the target processor. Valid values for @var{name} are the same as | |
54691107 TP |
851 | for the @option{-mcpu} command-line option without the instruction set |
852 | extension. | |
4a6bc624 | 853 | |
34bca508 | 854 | Specifying @code{.cpu} clears any previously selected architecture |
69133863 MGD |
855 | extensions. |
856 | ||
4a6bc624 NS |
857 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD |
858 | ||
859 | @cindex @code{.dn} and @code{.qn} directives, ARM | |
f467aa98 | 860 | @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]] |
1f9bb1ca | 861 | @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]] |
23753660 JB |
862 | |
863 | The @code{dn} and @code{qn} directives are used to create typed | |
864 | and/or indexed register aliases for use in Advanced SIMD Extension | |
865 | (Neon) instructions. The former should be used to create aliases | |
866 | of double-precision registers, and the latter to create aliases of | |
867 | quad-precision registers. | |
868 | ||
869 | If these directives are used to create typed aliases, those aliases can | |
870 | be used in Neon instructions instead of writing types after the mnemonic | |
871 | or after each operand. For example: | |
872 | ||
873 | @smallexample | |
874 | x .dn d2.f32 | |
875 | y .dn d3.f32 | |
876 | z .dn d4.f32[1] | |
877 | vmul x,y,z | |
878 | @end smallexample | |
879 | ||
880 | This is equivalent to writing the following: | |
881 | ||
882 | @smallexample | |
883 | vmul.f32 d2,d3,d4[1] | |
884 | @end smallexample | |
885 | ||
886 | Aliases created using @code{dn} or @code{qn} can be destroyed using | |
887 | @code{unreq}. | |
888 | ||
4a6bc624 | 889 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE |
252b5132 | 890 | |
4a6bc624 NS |
891 | @cindex @code{.eabi_attribute} directive, ARM |
892 | @item .eabi_attribute @var{tag}, @var{value} | |
893 | Set the EABI object attribute @var{tag} to @var{value}. | |
252b5132 | 894 | |
4a6bc624 NS |
895 | The @var{tag} is either an attribute number, or one of the following: |
896 | @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch}, | |
897 | @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use}, | |
75375b3e | 898 | @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch}, |
a7ad558c | 899 | @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config}, |
4a6bc624 NS |
900 | @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data}, |
901 | @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use}, | |
902 | @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding}, | |
903 | @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions}, | |
904 | @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model}, | |
75375b3e | 905 | @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved}, |
4a6bc624 NS |
906 | @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use}, |
907 | @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args}, | |
908 | @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals}, | |
909 | @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access}, | |
75375b3e | 910 | @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format}, |
cd21e546 | 911 | @code{Tag_MPextension_use}, @code{Tag_DIV_use}, |
4a6bc624 NS |
912 | @code{Tag_nodefaults}, @code{Tag_also_compatible_with}, |
913 | @code{Tag_conformance}, @code{Tag_T2EE_use}, | |
cd21e546 | 914 | @code{Tag_Virtualization_use} |
4a6bc624 NS |
915 | |
916 | The @var{value} is either a @code{number}, @code{"string"}, or | |
917 | @code{number, "string"} depending on the tag. | |
918 | ||
75375b3e | 919 | Note - the following legacy values are also accepted by @var{tag}: |
34bca508 | 920 | @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, |
75375b3e MGD |
921 | @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, |
922 | ||
4a6bc624 NS |
923 | @cindex @code{.even} directive, ARM |
924 | @item .even | |
925 | This directive aligns to an even-numbered address. | |
926 | ||
927 | @cindex @code{.extend} directive, ARM | |
928 | @cindex @code{.ldouble} directive, ARM | |
929 | @item .extend @var{expression} [, @var{expression}]* | |
930 | @itemx .ldouble @var{expression} [, @var{expression}]* | |
931 | These directives write 12byte long double floating-point values to the | |
932 | output section. These are not compatible with current ARM processors | |
933 | or ABIs. | |
934 | ||
935 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF | |
936 | ||
937 | @anchor{arm_fnend} | |
938 | @cindex @code{.fnend} directive, ARM | |
939 | @item .fnend | |
940 | Marks the end of a function with an unwind table entry. The unwind index | |
941 | table entry is created when this directive is processed. | |
252b5132 | 942 | |
4a6bc624 NS |
943 | If no personality routine has been specified then standard personality |
944 | routine 0 or 1 will be used, depending on the number of unwind opcodes | |
945 | required. | |
946 | ||
947 | @anchor{arm_fnstart} | |
948 | @cindex @code{.fnstart} directive, ARM | |
949 | @item .fnstart | |
950 | Marks the start of a function with an unwind table entry. | |
951 | ||
952 | @cindex @code{.force_thumb} directive, ARM | |
252b5132 RH |
953 | @item .force_thumb |
954 | This directive forces the selection of Thumb instructions, even if the | |
955 | target processor does not support those instructions | |
956 | ||
4a6bc624 NS |
957 | @cindex @code{.fpu} directive, ARM |
958 | @item .fpu @var{name} | |
959 | Select the floating-point unit to assemble for. Valid values for @var{name} | |
a05a5b64 | 960 | are the same as for the @option{-mfpu} command-line option. |
252b5132 | 961 | |
4a6bc624 NS |
962 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG |
963 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
e1da3f5b | 964 | |
4a6bc624 NS |
965 | @cindex @code{.handlerdata} directive, ARM |
966 | @item .handlerdata | |
967 | Marks the end of the current function, and the start of the exception table | |
968 | entry for that function. Anything between this directive and the | |
969 | @code{.fnend} directive will be added to the exception table entry. | |
970 | ||
971 | Must be preceded by a @code{.personality} or @code{.personalityindex} | |
972 | directive. | |
973 | ||
974 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
c921be7d NC |
975 | |
976 | @cindex @code{.inst} directive, ARM | |
977 | @item .inst @var{opcode} [ , @dots{} ] | |
1f9bb1ca AS |
978 | @itemx .inst.n @var{opcode} [ , @dots{} ] |
979 | @itemx .inst.w @var{opcode} [ , @dots{} ] | |
c921be7d NC |
980 | Generates the instruction corresponding to the numerical value @var{opcode}. |
981 | @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be | |
982 | specified explicitly, overriding the normal encoding rules. | |
983 | ||
4a6bc624 NS |
984 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ |
985 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
986 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
987 | ||
988 | @item .ldouble @var{expression} [, @var{expression}]* | |
989 | See @code{.extend}. | |
5395a469 | 990 | |
252b5132 RH |
991 | @cindex @code{.ltorg} directive, ARM |
992 | @item .ltorg | |
993 | This directive causes the current contents of the literal pool to be | |
994 | dumped into the current section (which is assumed to be the .text | |
995 | section) at the current location (aligned to a word boundary). | |
3d0c9500 NC |
996 | @code{GAS} maintains a separate literal pool for each section and each |
997 | sub-section. The @code{.ltorg} directive will only affect the literal | |
998 | pool of the current section and sub-section. At the end of assembly | |
999 | all remaining, un-empty literal pools will automatically be dumped. | |
1000 | ||
1001 | Note - older versions of @code{GAS} would dump the current literal | |
1002 | pool any time a section change occurred. This is no longer done, since | |
1003 | it prevents accurate control of the placement of literal pools. | |
252b5132 | 1004 | |
4a6bc624 | 1005 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM |
252b5132 | 1006 | |
4a6bc624 NS |
1007 | @cindex @code{.movsp} directive, ARM |
1008 | @item .movsp @var{reg} [, #@var{offset}] | |
1009 | Tell the unwinder that @var{reg} contains an offset from the current | |
1010 | stack pointer. If @var{offset} is not specified then it is assumed to be | |
1011 | zero. | |
7ed4c4c5 | 1012 | |
4a6bc624 NS |
1013 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN |
1014 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
7ed4c4c5 | 1015 | |
4a6bc624 NS |
1016 | @cindex @code{.object_arch} directive, ARM |
1017 | @item .object_arch @var{name} | |
1018 | Override the architecture recorded in the EABI object attribute section. | |
1019 | Valid values for @var{name} are the same as for the @code{.arch} directive. | |
1020 | Typically this is useful when code uses runtime detection of CPU features. | |
7ed4c4c5 | 1021 | |
4a6bc624 NS |
1022 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP |
1023 | ||
1024 | @cindex @code{.packed} directive, ARM | |
1025 | @item .packed @var{expression} [, @var{expression}]* | |
1026 | This directive writes 12-byte packed floating-point values to the | |
1027 | output section. These are not compatible with current ARM processors | |
1028 | or ABIs. | |
1029 | ||
ea4cff4f | 1030 | @anchor{arm_pad} |
4a6bc624 NS |
1031 | @cindex @code{.pad} directive, ARM |
1032 | @item .pad #@var{count} | |
1033 | Generate unwinder annotations for a stack adjustment of @var{count} bytes. | |
1034 | A positive value indicates the function prologue allocated stack space by | |
1035 | decrementing the stack pointer. | |
7ed4c4c5 NC |
1036 | |
1037 | @cindex @code{.personality} directive, ARM | |
1038 | @item .personality @var{name} | |
1039 | Sets the personality routine for the current function to @var{name}. | |
1040 | ||
1041 | @cindex @code{.personalityindex} directive, ARM | |
1042 | @item .personalityindex @var{index} | |
1043 | Sets the personality routine for the current function to the EABI standard | |
1044 | routine number @var{index} | |
1045 | ||
4a6bc624 NS |
1046 | @cindex @code{.pool} directive, ARM |
1047 | @item .pool | |
1048 | This is a synonym for .ltorg. | |
7ed4c4c5 | 1049 | |
4a6bc624 NS |
1050 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ |
1051 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
1052 | ||
1053 | @cindex @code{.req} directive, ARM | |
1054 | @item @var{name} .req @var{register name} | |
1055 | This creates an alias for @var{register name} called @var{name}. For | |
1056 | example: | |
1057 | ||
1058 | @smallexample | |
1059 | foo .req r0 | |
1060 | @end smallexample | |
1061 | ||
1062 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS | |
7ed4c4c5 | 1063 | |
7da4f750 | 1064 | @anchor{arm_save} |
7ed4c4c5 NC |
1065 | @cindex @code{.save} directive, ARM |
1066 | @item .save @var{reglist} | |
1067 | Generate unwinder annotations to restore the registers in @var{reglist}. | |
1068 | The format of @var{reglist} is the same as the corresponding store-multiple | |
1069 | instruction. | |
1070 | ||
1071 | @smallexample | |
1072 | @exdent @emph{core registers} | |
1073 | .save @{r4, r5, r6, lr@} | |
1074 | stmfd sp!, @{r4, r5, r6, lr@} | |
1075 | @exdent @emph{FPA registers} | |
1076 | .save f4, 2 | |
1077 | sfmfd f4, 2, [sp]! | |
1078 | @exdent @emph{VFP registers} | |
1079 | .save @{d8, d9, d10@} | |
fa073d69 | 1080 | fstmdx sp!, @{d8, d9, d10@} |
7ed4c4c5 NC |
1081 | @exdent @emph{iWMMXt registers} |
1082 | .save @{wr10, wr11@} | |
1083 | wstrd wr11, [sp, #-8]! | |
1084 | wstrd wr10, [sp, #-8]! | |
1085 | or | |
1086 | .save wr11 | |
1087 | wstrd wr11, [sp, #-8]! | |
1088 | .save wr10 | |
1089 | wstrd wr10, [sp, #-8]! | |
1090 | @end smallexample | |
1091 | ||
7da4f750 | 1092 | @anchor{arm_setfp} |
7ed4c4c5 NC |
1093 | @cindex @code{.setfp} directive, ARM |
1094 | @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] | |
4a6bc624 | 1095 | Make all unwinder annotations relative to a frame pointer. Without this |
7ed4c4c5 NC |
1096 | the unwinder will use offsets from the stack pointer. |
1097 | ||
a5b82cbe | 1098 | The syntax of this directive is the same as the @code{add} or @code{mov} |
7ed4c4c5 NC |
1099 | instruction used to set the frame pointer. @var{spreg} must be either |
1100 | @code{sp} or mentioned in a previous @code{.movsp} directive. | |
1101 | ||
1102 | @smallexample | |
1103 | .movsp ip | |
1104 | mov ip, sp | |
1105 | @dots{} | |
1106 | .setfp fp, ip, #4 | |
a5b82cbe | 1107 | add fp, ip, #4 |
7ed4c4c5 NC |
1108 | @end smallexample |
1109 | ||
4a6bc624 NS |
1110 | @cindex @code{.secrel32} directive, ARM |
1111 | @item .secrel32 @var{expression} [, @var{expression}]* | |
1112 | This directive emits relocations that evaluate to the section-relative | |
1113 | offset of each expression's symbol. This directive is only supported | |
1114 | for PE targets. | |
1115 | ||
cab7e4d9 NC |
1116 | @cindex @code{.syntax} directive, ARM |
1117 | @item .syntax [@code{unified} | @code{divided}] | |
1118 | This directive sets the Instruction Set Syntax as described in the | |
1119 | @ref{ARM-Instruction-Set} section. | |
1120 | ||
4a6bc624 NS |
1121 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT |
1122 | ||
1123 | @cindex @code{.thumb} directive, ARM | |
1124 | @item .thumb | |
1125 | This performs the same action as @var{.code 16}. | |
1126 | ||
1127 | @cindex @code{.thumb_func} directive, ARM | |
1128 | @item .thumb_func | |
1129 | This directive specifies that the following symbol is the name of a | |
1130 | Thumb encoded function. This information is necessary in order to allow | |
1131 | the assembler and linker to generate correct code for interworking | |
1132 | between Arm and Thumb instructions and should be used even if | |
1133 | interworking is not going to be performed. The presence of this | |
1134 | directive also implies @code{.thumb} | |
1135 | ||
33eaf5de | 1136 | This directive is not necessary when generating EABI objects. On these |
4a6bc624 NS |
1137 | targets the encoding is implicit when generating Thumb code. |
1138 | ||
1139 | @cindex @code{.thumb_set} directive, ARM | |
1140 | @item .thumb_set | |
1141 | This performs the equivalent of a @code{.set} directive in that it | |
1142 | creates a symbol which is an alias for another symbol (possibly not yet | |
1143 | defined). This directive also has the added property in that it marks | |
1144 | the aliased symbol as being a thumb function entry point, in the same | |
1145 | way that the @code{.thumb_func} directive does. | |
1146 | ||
0855e32b NS |
1147 | @cindex @code{.tlsdescseq} directive, ARM |
1148 | @item .tlsdescseq @var{tls-variable} | |
1149 | This directive is used to annotate parts of an inlined TLS descriptor | |
1150 | trampoline. Normally the trampoline is provided by the linker, and | |
1151 | this directive is not needed. | |
1152 | ||
4a6bc624 NS |
1153 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU |
1154 | ||
1155 | @cindex @code{.unreq} directive, ARM | |
1156 | @item .unreq @var{alias-name} | |
1157 | This undefines a register alias which was previously defined using the | |
1158 | @code{req}, @code{dn} or @code{qn} directives. For example: | |
1159 | ||
1160 | @smallexample | |
1161 | foo .req r0 | |
1162 | .unreq foo | |
1163 | @end smallexample | |
1164 | ||
1165 | An error occurs if the name is undefined. Note - this pseudo op can | |
1166 | be used to delete builtin in register name aliases (eg 'r0'). This | |
1167 | should only be done if it is really necessary. | |
1168 | ||
7ed4c4c5 | 1169 | @cindex @code{.unwind_raw} directive, ARM |
4a6bc624 | 1170 | @item .unwind_raw @var{offset}, @var{byte1}, @dots{} |
33eaf5de | 1171 | Insert one of more arbitrary unwind opcode bytes, which are known to adjust |
7ed4c4c5 NC |
1172 | the stack pointer by @var{offset} bytes. |
1173 | ||
1174 | For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to | |
1175 | @code{.save @{r0@}} | |
1176 | ||
4a6bc624 | 1177 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV |
ee065d83 | 1178 | |
4a6bc624 NS |
1179 | @cindex @code{.vsave} directive, ARM |
1180 | @item .vsave @var{vfp-reglist} | |
1181 | Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist} | |
1182 | using FLDMD. Also works for VFPv3 registers | |
1183 | that are to be restored using VLDM. | |
1184 | The format of @var{vfp-reglist} is the same as the corresponding store-multiple | |
1185 | instruction. | |
ee065d83 | 1186 | |
4a6bc624 NS |
1187 | @smallexample |
1188 | @exdent @emph{VFP registers} | |
1189 | .vsave @{d8, d9, d10@} | |
1190 | fstmdd sp!, @{d8, d9, d10@} | |
1191 | @exdent @emph{VFPv3 registers} | |
1192 | .vsave @{d15, d16, d17@} | |
1193 | vstm sp!, @{d15, d16, d17@} | |
1194 | @end smallexample | |
e04befd0 | 1195 | |
4a6bc624 NS |
1196 | Since FLDMX and FSTMX are now deprecated, this directive should be |
1197 | used in favour of @code{.save} for saving VFP registers for ARMv6 and above. | |
e04befd0 | 1198 | |
4a6bc624 NS |
1199 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW |
1200 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
1201 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
1202 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
ee065d83 | 1203 | |
252b5132 RH |
1204 | @end table |
1205 | ||
1206 | @node ARM Opcodes | |
1207 | @section Opcodes | |
1208 | ||
1209 | @cindex ARM opcodes | |
1210 | @cindex opcodes for ARM | |
49a5575c NC |
1211 | @code{@value{AS}} implements all the standard ARM opcodes. It also |
1212 | implements several pseudo opcodes, including several synthetic load | |
34bca508 | 1213 | instructions. |
252b5132 | 1214 | |
49a5575c NC |
1215 | @table @code |
1216 | ||
1217 | @cindex @code{NOP} pseudo op, ARM | |
1218 | @item NOP | |
1219 | @smallexample | |
1220 | nop | |
1221 | @end smallexample | |
252b5132 | 1222 | |
49a5575c NC |
1223 | This pseudo op will always evaluate to a legal ARM instruction that does |
1224 | nothing. Currently it will evaluate to MOV r0, r0. | |
252b5132 | 1225 | |
49a5575c | 1226 | @cindex @code{LDR reg,=<label>} pseudo op, ARM |
34bca508 | 1227 | @item LDR |
252b5132 RH |
1228 | @smallexample |
1229 | ldr <register> , = <expression> | |
1230 | @end smallexample | |
1231 | ||
1232 | If expression evaluates to a numeric constant then a MOV or MVN | |
1233 | instruction will be used in place of the LDR instruction, if the | |
1234 | constant can be generated by either of these instructions. Otherwise | |
1235 | the constant will be placed into the nearest literal pool (if it not | |
1236 | already there) and a PC relative LDR instruction will be generated. | |
1237 | ||
49a5575c NC |
1238 | @cindex @code{ADR reg,<label>} pseudo op, ARM |
1239 | @item ADR | |
1240 | @smallexample | |
1241 | adr <register> <label> | |
1242 | @end smallexample | |
1243 | ||
1244 | This instruction will load the address of @var{label} into the indicated | |
1245 | register. The instruction will evaluate to a PC relative ADD or SUB | |
1246 | instruction depending upon where the label is located. If the label is | |
1247 | out of range, or if it is not defined in the same file (and section) as | |
1248 | the ADR instruction, then an error will be generated. This instruction | |
1249 | will not make use of the literal pool. | |
1250 | ||
fc6141f0 NC |
1251 | If @var{label} is a thumb function symbol, and thumb interworking has |
1252 | been enabled via the @option{-mthumb-interwork} option then the bottom | |
1253 | bit of the value stored into @var{register} will be set. This allows | |
1254 | the following sequence to work as expected: | |
1255 | ||
1256 | @smallexample | |
1257 | adr r0, thumb_function | |
1258 | blx r0 | |
1259 | @end smallexample | |
1260 | ||
49a5575c | 1261 | @cindex @code{ADRL reg,<label>} pseudo op, ARM |
34bca508 | 1262 | @item ADRL |
49a5575c NC |
1263 | @smallexample |
1264 | adrl <register> <label> | |
1265 | @end smallexample | |
1266 | ||
1267 | This instruction will load the address of @var{label} into the indicated | |
a349d9dd | 1268 | register. The instruction will evaluate to one or two PC relative ADD |
49a5575c NC |
1269 | or SUB instructions depending upon where the label is located. If a |
1270 | second instruction is not needed a NOP instruction will be generated in | |
1271 | its place, so that this instruction is always 8 bytes long. | |
1272 | ||
1273 | If the label is out of range, or if it is not defined in the same file | |
1274 | (and section) as the ADRL instruction, then an error will be generated. | |
1275 | This instruction will not make use of the literal pool. | |
1276 | ||
fc6141f0 NC |
1277 | If @var{label} is a thumb function symbol, and thumb interworking has |
1278 | been enabled via the @option{-mthumb-interwork} option then the bottom | |
1279 | bit of the value stored into @var{register} will be set. | |
1280 | ||
49a5575c NC |
1281 | @end table |
1282 | ||
252b5132 RH |
1283 | For information on the ARM or Thumb instruction sets, see @cite{ARM |
1284 | Software Development Toolkit Reference Manual}, Advanced RISC Machines | |
1285 | Ltd. | |
1286 | ||
6057a28f NC |
1287 | @node ARM Mapping Symbols |
1288 | @section Mapping Symbols | |
1289 | ||
1290 | The ARM ELF specification requires that special symbols be inserted | |
1291 | into object files to mark certain features: | |
1292 | ||
1293 | @table @code | |
1294 | ||
1295 | @cindex @code{$a} | |
1296 | @item $a | |
1297 | At the start of a region of code containing ARM instructions. | |
1298 | ||
1299 | @cindex @code{$t} | |
1300 | @item $t | |
1301 | At the start of a region of code containing THUMB instructions. | |
1302 | ||
1303 | @cindex @code{$d} | |
1304 | @item $d | |
1305 | At the start of a region of data. | |
1306 | ||
1307 | @end table | |
1308 | ||
1309 | The assembler will automatically insert these symbols for you - there | |
1310 | is no need to code them yourself. Support for tagging symbols ($b, | |
1311 | $f, $p and $m) which is also mentioned in the current ARM ELF | |
1312 | specification is not implemented. This is because they have been | |
1313 | dropped from the new EABI and so tools cannot rely upon their | |
1314 | presence. | |
1315 | ||
7da4f750 MM |
1316 | @node ARM Unwinding Tutorial |
1317 | @section Unwinding | |
1318 | ||
1319 | The ABI for the ARM Architecture specifies a standard format for | |
1320 | exception unwind information. This information is used when an | |
1321 | exception is thrown to determine where control should be transferred. | |
1322 | In particular, the unwind information is used to determine which | |
1323 | function called the function that threw the exception, and which | |
1324 | function called that one, and so forth. This information is also used | |
1325 | to restore the values of callee-saved registers in the function | |
1326 | catching the exception. | |
1327 | ||
1328 | If you are writing functions in assembly code, and those functions | |
1329 | call other functions that throw exceptions, you must use assembly | |
1330 | pseudo ops to ensure that appropriate exception unwind information is | |
1331 | generated. Otherwise, if one of the functions called by your assembly | |
1332 | code throws an exception, the run-time library will be unable to | |
1333 | unwind the stack through your assembly code and your program will not | |
1334 | behave correctly. | |
1335 | ||
1336 | To illustrate the use of these pseudo ops, we will examine the code | |
1337 | that G++ generates for the following C++ input: | |
1338 | ||
1339 | @verbatim | |
1340 | void callee (int *); | |
1341 | ||
34bca508 L |
1342 | int |
1343 | caller () | |
7da4f750 MM |
1344 | { |
1345 | int i; | |
1346 | callee (&i); | |
34bca508 | 1347 | return i; |
7da4f750 MM |
1348 | } |
1349 | @end verbatim | |
1350 | ||
1351 | This example does not show how to throw or catch an exception from | |
1352 | assembly code. That is a much more complex operation and should | |
1353 | always be done in a high-level language, such as C++, that directly | |
1354 | supports exceptions. | |
1355 | ||
1356 | The code generated by one particular version of G++ when compiling the | |
1357 | example above is: | |
1358 | ||
1359 | @verbatim | |
1360 | _Z6callerv: | |
1361 | .fnstart | |
1362 | .LFB2: | |
1363 | @ Function supports interworking. | |
1364 | @ args = 0, pretend = 0, frame = 8 | |
1365 | @ frame_needed = 1, uses_anonymous_args = 0 | |
1366 | stmfd sp!, {fp, lr} | |
1367 | .save {fp, lr} | |
1368 | .LCFI0: | |
1369 | .setfp fp, sp, #4 | |
1370 | add fp, sp, #4 | |
1371 | .LCFI1: | |
1372 | .pad #8 | |
1373 | sub sp, sp, #8 | |
1374 | .LCFI2: | |
1375 | sub r3, fp, #8 | |
1376 | mov r0, r3 | |
1377 | bl _Z6calleePi | |
1378 | ldr r3, [fp, #-8] | |
1379 | mov r0, r3 | |
1380 | sub sp, fp, #4 | |
1381 | ldmfd sp!, {fp, lr} | |
1382 | bx lr | |
1383 | .LFE2: | |
1384 | .fnend | |
1385 | @end verbatim | |
1386 | ||
1387 | Of course, the sequence of instructions varies based on the options | |
1388 | you pass to GCC and on the version of GCC in use. The exact | |
1389 | instructions are not important since we are focusing on the pseudo ops | |
1390 | that are used to generate unwind information. | |
1391 | ||
1392 | An important assumption made by the unwinder is that the stack frame | |
1393 | does not change during the body of the function. In particular, since | |
1394 | we assume that the assembly code does not itself throw an exception, | |
1395 | the only point where an exception can be thrown is from a call, such | |
1396 | as the @code{bl} instruction above. At each call site, the same saved | |
1397 | registers (including @code{lr}, which indicates the return address) | |
1398 | must be located in the same locations relative to the frame pointer. | |
1399 | ||
1400 | The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo | |
1401 | op appears immediately before the first instruction of the function | |
1402 | while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo | |
1403 | op appears immediately after the last instruction of the function. | |
34bca508 | 1404 | These pseudo ops specify the range of the function. |
7da4f750 MM |
1405 | |
1406 | Only the order of the other pseudos ops (e.g., @code{.setfp} or | |
1407 | @code{.pad}) matters; their exact locations are irrelevant. In the | |
1408 | example above, the compiler emits the pseudo ops with particular | |
1409 | instructions. That makes it easier to understand the code, but it is | |
1410 | not required for correctness. It would work just as well to emit all | |
1411 | of the pseudo ops other than @code{.fnend} in the same order, but | |
1412 | immediately after @code{.fnstart}. | |
1413 | ||
1414 | The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op | |
1415 | indicates registers that have been saved to the stack so that they can | |
1416 | be restored before the function returns. The argument to the | |
1417 | @code{.save} pseudo op is a list of registers to save. If a register | |
1418 | is ``callee-saved'' (as specified by the ABI) and is modified by the | |
1419 | function you are writing, then your code must save the value before it | |
1420 | is modified and restore the original value before the function | |
1421 | returns. If an exception is thrown, the run-time library restores the | |
1422 | values of these registers from their locations on the stack before | |
1423 | returning control to the exception handler. (Of course, if an | |
1424 | exception is not thrown, the function that contains the @code{.save} | |
1425 | pseudo op restores these registers in the function epilogue, as is | |
1426 | done with the @code{ldmfd} instruction above.) | |
1427 | ||
1428 | You do not have to save callee-saved registers at the very beginning | |
1429 | of the function and you do not need to use the @code{.save} pseudo op | |
1430 | immediately following the point at which the registers are saved. | |
1431 | However, if you modify a callee-saved register, you must save it on | |
1432 | the stack before modifying it and before calling any functions which | |
1433 | might throw an exception. And, you must use the @code{.save} pseudo | |
1434 | op to indicate that you have done so. | |
1435 | ||
1436 | The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a | |
1437 | modification of the stack pointer that does not save any registers. | |
1438 | The argument is the number of bytes (in decimal) that are subtracted | |
1439 | from the stack pointer. (On ARM CPUs, the stack grows downwards, so | |
1440 | subtracting from the stack pointer increases the size of the stack.) | |
1441 | ||
1442 | The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op | |
1443 | indicates the register that contains the frame pointer. The first | |
1444 | argument is the register that is set, which is typically @code{fp}. | |
1445 | The second argument indicates the register from which the frame | |
1446 | pointer takes its value. The third argument, if present, is the value | |
1447 | (in decimal) added to the register specified by the second argument to | |
1448 | compute the value of the frame pointer. You should not modify the | |
1449 | frame pointer in the body of the function. | |
1450 | ||
1451 | If you do not use a frame pointer, then you should not use the | |
1452 | @code{.setfp} pseudo op. If you do not use a frame pointer, then you | |
1453 | should avoid modifying the stack pointer outside of the function | |
1454 | prologue. Otherwise, the run-time library will be unable to find | |
1455 | saved registers when it is unwinding the stack. | |
1456 | ||
1457 | The pseudo ops described above are sufficient for writing assembly | |
1458 | code that calls functions which may throw exceptions. If you need to | |
1459 | know more about the object-file format used to represent unwind | |
1460 | information, you may consult the @cite{Exception Handling ABI for the | |
1461 | ARM Architecture} available from @uref{http://infocenter.arm.com}. | |
91f68a68 | 1462 |