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aa820537 | 1 | @c Copyright 2005, 2006, 2009 |
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2 | @c Free Software Foundation, Inc. |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @ifset GENERIC | |
6 | @page | |
3b4e1885 | 7 | @node Blackfin-Dependent |
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8 | @chapter Blackfin Dependent Features |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter Blackfin Dependent Features | |
13 | @end ifclear | |
14 | ||
15 | @cindex Blackfin support | |
16 | @menu | |
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17 | * Blackfin Options:: Blackfin Options |
18 | * Blackfin Syntax:: Blackfin Syntax | |
19 | * Blackfin Directives:: Blackfin Directives | |
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20 | @end menu |
21 | ||
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22 | @node Blackfin Options |
23 | @section Options | |
24 | @cindex Blackfin options (none) | |
25 | @cindex options for Blackfin (none) | |
26 | ||
27 | @table @code | |
28 | ||
29 | @cindex @code{-mcpu=} command line option, Blackfin | |
30 | @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]} | |
31 | This option specifies the target processor. The optional @var{sirevision} | |
32 | is not used in assembler. It's here such that GCC can easily pass down its | |
33 | @code{-mcpu=} option. The assembler will issue an | |
34 | error message if an attempt is made to assemble an instruction which | |
35 | will not execute on the target processor. The following processor names are | |
36 | recognized: | |
a23c851a MF |
37 | @code{bf504}, |
38 | @code{bf506}, | |
3b4e1885 JZ |
39 | @code{bf512}, |
40 | @code{bf514}, | |
41 | @code{bf516}, | |
42 | @code{bf518}, | |
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43 | @code{bf522}, |
44 | @code{bf523}, | |
45 | @code{bf524}, | |
46 | @code{bf525}, | |
47 | @code{bf526}, | |
48 | @code{bf527}, | |
49 | @code{bf531}, | |
50 | @code{bf532}, | |
51 | @code{bf533}, | |
52 | @code{bf534}, | |
53 | @code{bf535} (not implemented yet), | |
54 | @code{bf536}, | |
55 | @code{bf537}, | |
56 | @code{bf538}, | |
57 | @code{bf539}, | |
58 | @code{bf542}, | |
59 | @code{bf542m}, | |
60 | @code{bf544}, | |
61 | @code{bf544m}, | |
62 | @code{bf547}, | |
63 | @code{bf547m}, | |
64 | @code{bf548}, | |
65 | @code{bf548m}, | |
66 | @code{bf549}, | |
67 | @code{bf549m}, | |
68 | and | |
69 | @code{bf561}. | |
70 | ||
9982501a JZ |
71 | @cindex @code{-mfdpic} command line option, Blackfin |
72 | @item -mfdpic | |
73 | Assemble for the FDPIC ABI. | |
74 | ||
75 | @cindex @code{-mno-fdpic} command line option, Blackfin | |
76 | @cindex @code{-mnopic} command line option, Blackfin | |
77 | @item -mno-fdpic/-mnopic | |
78 | Disable -mfdpic. | |
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79 | @end table |
80 | ||
81 | @node Blackfin Syntax | |
07c1b327 | 82 | @section Syntax |
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83 | @cindex Blackfin syntax |
84 | @cindex syntax, Blackfin | |
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85 | |
86 | @table @code | |
87 | @item Special Characters | |
88 | Assembler input is free format and may appear anywhere on the line. | |
89 | One instruction may extend across multiple lines or more than one | |
90 | instruction may appear on the same line. White space (space, tab, | |
91 | comments or newline) may appear anywhere between tokens. A token must | |
92 | not have embedded spaces. Tokens include numbers, register names, | |
93 | keywords, user identifiers, and also some multicharacter special | |
94 | symbols like "+=", "/*" or "||". | |
95 | ||
96 | @item Instruction Delimiting | |
97 | A semicolon must terminate every instruction. Sometimes a complete | |
98 | instruction will consist of more than one operation. There are two | |
99 | cases where this occurs. The first is when two general operations | |
100 | are combined. Normally a comma separates the different parts, as in | |
101 | ||
102 | @smallexample | |
103 | a0= r3.h * r2.l, a1 = r3.l * r2.h ; | |
104 | @end smallexample | |
105 | ||
106 | The second case occurs when a general instruction is combined with one | |
107 | or two memory references for joint issue. The latter portions are | |
108 | set off by a "||" token. | |
109 | ||
110 | @smallexample | |
111 | a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; | |
112 | @end smallexample | |
113 | ||
114 | @item Register Names | |
115 | ||
116 | The assembler treats register names and instruction keywords in a case | |
117 | insensitive manner. User identifiers are case sensitive. Thus, R3.l, | |
118 | R3.L, r3.l and r3.L are all equivalent input to the assembler. | |
119 | ||
120 | Register names are reserved and may not be used as program identifiers. | |
121 | ||
122 | Some operations (such as "Move Register") require a register pair. | |
123 | Register pairs are always data registers and are denoted using a colon, | |
124 | eg., R3:2. The larger number must be written firsts. Note that the | |
125 | hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. | |
126 | ||
127 | Some instructions (such as --SP (Push Multiple)) require a group of | |
128 | adjacent registers. Adjacent registers are denoted in the syntax by | |
129 | the range enclosed in parentheses and separated by a colon, eg., (R7:3). | |
130 | Again, the larger number appears first. | |
131 | ||
132 | Portions of a particular register may be individually specified. This | |
133 | is written with a dot (".") following the register name and then a | |
134 | letter denoting the desired portion. For 32-bit registers, ".H" | |
135 | denotes the most significant ("High") portion. ".L" denotes the | |
136 | least-significant portion. The subdivisions of the 40-bit registers | |
137 | are described later. | |
138 | ||
139 | @item Accumulators | |
140 | The set of 40-bit registers A1 and A0 that normally contain data that | |
141 | is being manipulated. Each accumulator can be accessed in four ways. | |
142 | ||
143 | @table @code | |
144 | @item one 40-bit register | |
145 | The register will be referred to as A1 or A0. | |
146 | @item one 32-bit register | |
147 | The registers are designated as A1.W or A0.W. | |
148 | @item two 16-bit registers | |
149 | The registers are designated as A1.H, A1.L, A0.H or A0.L. | |
150 | @item one 8-bit register | |
151 | The registers are designated as A1.X or A0.X for the bits that | |
152 | extend beyond bit 31. | |
153 | @end table | |
154 | ||
155 | @item Data Registers | |
156 | The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that | |
157 | normally contain data for manipulation. These are abbreviated as | |
158 | D-register or Dreg. Data registers can be accessed as 32-bit registers | |
159 | or as two independent 16-bit registers. The least significant 16 bits | |
b45619c0 | 160 | of each register is called the "low" half and is designated with ".L" |
07c1b327 | 161 | following the register name. The most significant 16 bits are called |
b45619c0 | 162 | the "high" half and is designated with ".H" following the name. |
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163 | |
164 | @smallexample | |
165 | R7.L, r2.h, r4.L, R0.H | |
166 | @end smallexample | |
167 | ||
168 | @item Pointer Registers | |
169 | The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that | |
170 | normally contain byte addresses of data structures. These are | |
171 | abbreviated as P-register or Preg. | |
172 | ||
173 | @smallexample | |
174 | p2, p5, fp, sp | |
175 | @end smallexample | |
176 | ||
177 | @item Stack Pointer SP | |
178 | The stack pointer contains the 32-bit address of the last occupied | |
179 | byte location in the stack. The stack grows by decrementing the | |
180 | stack pointer. | |
181 | ||
182 | @item Frame Pointer FP | |
183 | The frame pointer contains the 32-bit address of the previous frame | |
184 | pointer in the stack. It is located at the top of a frame. | |
185 | ||
186 | @item Loop Top | |
187 | LT0 and LT1. These registers contain the 32-bit address of the top of | |
188 | a zero overhead loop. | |
189 | ||
190 | @item Loop Count | |
191 | LC0 and LC1. These registers contain the 32-bit counter of the zero | |
192 | overhead loop executions. | |
193 | ||
194 | @item Loop Bottom | |
195 | LB0 and LB1. These registers contain the 32-bit address of the bottom | |
196 | of a zero overhead loop. | |
197 | ||
198 | @item Index Registers | |
199 | The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte | |
200 | addresses of data structures. Abbreviated I-register or Ireg. | |
201 | ||
202 | @item Modify Registers | |
203 | The set of 32-bit registers (M0, M1, M2, M3) that normally contain | |
204 | offset values that are added and subracted to one of the index | |
205 | registers. Abbreviated as Mreg. | |
206 | ||
207 | @item Length Registers | |
208 | The set of 32-bit registers (L0, L1, L2, L3) that normally contain the | |
209 | length in bytes of the circular buffer. Abbreviated as Lreg. Clear | |
210 | the Lreg to disable circular addressing for the corresponding Ireg. | |
211 | ||
212 | @item Base Registers | |
213 | The set of 32-bit registers (B0, B1, B2, B3) that normally contain the | |
214 | base address in bytes of the circular buffer. Abbreviated as Breg. | |
215 | ||
216 | @item Floating Point | |
217 | The Blackfin family has no hardware floating point but the .float | |
218 | directive generates ieee floating point numbers for use with software | |
219 | floating point libraries. | |
220 | ||
221 | @item Blackfin Opcodes | |
222 | For detailed information on the Blackfin machine instruction set, see | |
223 | the Blackfin(r) Processor Instruction Set Reference. | |
224 | ||
225 | @end table | |
226 | ||
6306cd85 | 227 | @node Blackfin Directives |
07c1b327 | 228 | @section Directives |
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229 | @cindex Blackfin directives |
230 | @cindex directives, Blackfin | |
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231 | |
232 | The following directives are provided for compatibility with the VDSP assembler. | |
233 | ||
234 | @table @code | |
235 | @item .byte2 | |
236 | Initializes a four byte data object. | |
237 | @item .byte4 | |
238 | Initializes a two byte data object. | |
239 | @item .db | |
240 | TBD | |
241 | @item .dd | |
242 | TBD | |
243 | @item .dw | |
244 | TBD | |
245 | @item .var | |
246 | Define and initialize a 32 bit data object. | |
247 | @end table |