Commit | Line | Data |
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4b95cf5c | 1 | @c Copyright (C) 1991-2014 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
731caf76 L |
4 | @c man end |
5 | ||
252b5132 RH |
6 | @ifset GENERIC |
7 | @page | |
8 | @node i386-Dependent | |
9 | @chapter 80386 Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter 80386 Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex i386 support | |
b6169b20 | 17 | @cindex i80386 support |
55b62671 AJ |
18 | @cindex x86-64 support |
19 | ||
20 | The i386 version @code{@value{AS}} supports both the original Intel 386 | |
21 | architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture | |
22 | extending the Intel architecture to 64-bits. | |
23 | ||
252b5132 RH |
24 | @menu |
25 | * i386-Options:: Options | |
a6c24e68 | 26 | * i386-Directives:: X86 specific directives |
7c31ae13 | 27 | * i386-Syntax:: Syntactical considerations |
252b5132 RH |
28 | * i386-Mnemonics:: Instruction Naming |
29 | * i386-Regs:: Register Naming | |
30 | * i386-Prefixes:: Instruction Prefixes | |
31 | * i386-Memory:: Memory References | |
fddf5b5b | 32 | * i386-Jumps:: Handling of Jump Instructions |
252b5132 RH |
33 | * i386-Float:: Floating Point |
34 | * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations | |
f88c9eb0 | 35 | * i386-LWP:: AMD's Lightweight Profiling Instructions |
87973e9f | 36 | * i386-BMI:: Bit Manipulation Instruction |
2a2a0f38 | 37 | * i386-TBM:: AMD's Trailing Bit Manipulation Instructions |
252b5132 | 38 | * i386-16bit:: Writing 16-bit Code |
e413e4e9 | 39 | * i386-Arch:: Specifying an x86 CPU architecture |
252b5132 RH |
40 | * i386-Bugs:: AT&T Syntax bugs |
41 | * i386-Notes:: Notes | |
42 | @end menu | |
43 | ||
44 | @node i386-Options | |
45 | @section Options | |
46 | ||
55b62671 AJ |
47 | @cindex options for i386 |
48 | @cindex options for x86-64 | |
49 | @cindex i386 options | |
34bca508 | 50 | @cindex x86-64 options |
55b62671 AJ |
51 | |
52 | The i386 version of @code{@value{AS}} has a few machine | |
53 | dependent options: | |
54 | ||
731caf76 L |
55 | @c man begin OPTIONS |
56 | @table @gcctabopt | |
55b62671 AJ |
57 | @cindex @samp{--32} option, i386 |
58 | @cindex @samp{--32} option, x86-64 | |
570561f7 L |
59 | @cindex @samp{--x32} option, i386 |
60 | @cindex @samp{--x32} option, x86-64 | |
55b62671 AJ |
61 | @cindex @samp{--64} option, i386 |
62 | @cindex @samp{--64} option, x86-64 | |
570561f7 | 63 | @item --32 | --x32 | --64 |
35cc6a0b | 64 | Select the word size, either 32 bits or 64 bits. @samp{--32} |
570561f7 | 65 | implies Intel i386 architecture, while @samp{--x32} and @samp{--64} |
35cc6a0b L |
66 | imply AMD x86-64 architecture with 32-bit or 64-bit word-size |
67 | respectively. | |
55b62671 AJ |
68 | |
69 | These options are only available with the ELF object file format, and | |
70 | require that the necessary BFD support has been included (on a 32-bit | |
71 | platform you have to add --enable-64-bit-bfd to configure enable 64-bit | |
72 | usage and use x86-64 as target platform). | |
12b55ccc L |
73 | |
74 | @item -n | |
75 | By default, x86 GAS replaces multiple nop instructions used for | |
76 | alignment within code sections with multi-byte nop instructions such | |
77 | as leal 0(%esi,1),%esi. This switch disables the optimization. | |
b3b91714 AM |
78 | |
79 | @cindex @samp{--divide} option, i386 | |
80 | @item --divide | |
81 | On SVR4-derived platforms, the character @samp{/} is treated as a comment | |
82 | character, which means that it cannot be used in expressions. The | |
83 | @samp{--divide} option turns @samp{/} into a normal character. This does | |
84 | not disable @samp{/} at the beginning of a line starting a comment, or | |
85 | affect using @samp{#} for starting a comment. | |
86 | ||
9103f4f4 L |
87 | @cindex @samp{-march=} option, i386 |
88 | @cindex @samp{-march=} option, x86-64 | |
6305a203 L |
89 | @item -march=@var{CPU}[+@var{EXTENSION}@dots{}] |
90 | This option specifies the target processor. The assembler will | |
91 | issue an error message if an attempt is made to assemble an instruction | |
92 | which will not execute on the target processor. The following | |
34bca508 | 93 | processor names are recognized: |
9103f4f4 L |
94 | @code{i8086}, |
95 | @code{i186}, | |
96 | @code{i286}, | |
97 | @code{i386}, | |
98 | @code{i486}, | |
99 | @code{i586}, | |
100 | @code{i686}, | |
101 | @code{pentium}, | |
102 | @code{pentiumpro}, | |
103 | @code{pentiumii}, | |
104 | @code{pentiumiii}, | |
105 | @code{pentium4}, | |
106 | @code{prescott}, | |
107 | @code{nocona}, | |
ef05d495 L |
108 | @code{core}, |
109 | @code{core2}, | |
bd5295b2 | 110 | @code{corei7}, |
8a9036a4 | 111 | @code{l1om}, |
7a9068fe | 112 | @code{k1om}, |
9103f4f4 L |
113 | @code{k6}, |
114 | @code{k6_2}, | |
115 | @code{athlon}, | |
9103f4f4 L |
116 | @code{opteron}, |
117 | @code{k8}, | |
1ceab344 | 118 | @code{amdfam10}, |
68339fdf | 119 | @code{bdver1}, |
af2f724e | 120 | @code{bdver2}, |
5e5c50d3 | 121 | @code{bdver3}, |
c7b0bd56 | 122 | @code{bdver4}, |
7b458c12 L |
123 | @code{btver1}, |
124 | @code{btver2}, | |
9103f4f4 L |
125 | @code{generic32} and |
126 | @code{generic64}. | |
127 | ||
34bca508 | 128 | In addition to the basic instruction set, the assembler can be told to |
6305a203 L |
129 | accept various extension mnemonics. For example, |
130 | @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and | |
131 | @var{vmx}. The following extensions are currently supported: | |
309d3373 JB |
132 | @code{8087}, |
133 | @code{287}, | |
134 | @code{387}, | |
135 | @code{no87}, | |
6305a203 | 136 | @code{mmx}, |
309d3373 | 137 | @code{nommx}, |
6305a203 L |
138 | @code{sse}, |
139 | @code{sse2}, | |
140 | @code{sse3}, | |
141 | @code{ssse3}, | |
142 | @code{sse4.1}, | |
143 | @code{sse4.2}, | |
144 | @code{sse4}, | |
309d3373 | 145 | @code{nosse}, |
c0f3af97 | 146 | @code{avx}, |
6c30d220 | 147 | @code{avx2}, |
e2e1fcde L |
148 | @code{adx}, |
149 | @code{rdseed}, | |
150 | @code{prfchw}, | |
5c111e37 | 151 | @code{smap}, |
7e8b059b | 152 | @code{mpx}, |
a0046408 | 153 | @code{sha}, |
1dfc6506 L |
154 | @code{prefetchwt1}, |
155 | @code{clflushopt}, | |
156 | @code{se1}, | |
43234a1e L |
157 | @code{avx512f}, |
158 | @code{avx512cd}, | |
159 | @code{avx512er}, | |
160 | @code{avx512pf}, | |
1dfc6506 L |
161 | @code{avx512vl}, |
162 | @code{avx512bw}, | |
163 | @code{avx512dq}, | |
309d3373 | 164 | @code{noavx}, |
6305a203 | 165 | @code{vmx}, |
8729a6f6 | 166 | @code{vmfunc}, |
6305a203 | 167 | @code{smx}, |
f03fe4c1 | 168 | @code{xsave}, |
c7b8aa3a | 169 | @code{xsaveopt}, |
1dfc6506 L |
170 | @code{xsavec}, |
171 | @code{xsaves}, | |
c0f3af97 | 172 | @code{aes}, |
594ab6a3 | 173 | @code{pclmul}, |
c7b8aa3a L |
174 | @code{fsgsbase}, |
175 | @code{rdrnd}, | |
176 | @code{f16c}, | |
6c30d220 | 177 | @code{bmi2}, |
c0f3af97 | 178 | @code{fma}, |
f1f8f695 L |
179 | @code{movbe}, |
180 | @code{ept}, | |
6c30d220 | 181 | @code{lzcnt}, |
42164a71 L |
182 | @code{hle}, |
183 | @code{rtm}, | |
6c30d220 | 184 | @code{invpcid}, |
bd5295b2 | 185 | @code{clflush}, |
f88c9eb0 | 186 | @code{lwp}, |
5dd85c99 SP |
187 | @code{fma4}, |
188 | @code{xop}, | |
60aa667e | 189 | @code{cx16}, |
bd5295b2 | 190 | @code{syscall}, |
1b7f3fb0 | 191 | @code{rdtscp}, |
6305a203 L |
192 | @code{3dnow}, |
193 | @code{3dnowa}, | |
194 | @code{sse4a}, | |
195 | @code{sse5}, | |
196 | @code{svme}, | |
197 | @code{abm} and | |
198 | @code{padlock}. | |
309d3373 JB |
199 | Note that rather than extending a basic instruction set, the extension |
200 | mnemonics starting with @code{no} revoke the respective functionality. | |
6305a203 L |
201 | |
202 | When the @code{.arch} directive is used with @option{-march}, the | |
9103f4f4 L |
203 | @code{.arch} directive will take precedent. |
204 | ||
205 | @cindex @samp{-mtune=} option, i386 | |
206 | @cindex @samp{-mtune=} option, x86-64 | |
207 | @item -mtune=@var{CPU} | |
208 | This option specifies a processor to optimize for. When used in | |
209 | conjunction with the @option{-march} option, only instructions | |
210 | of the processor specified by the @option{-march} option will be | |
211 | generated. | |
212 | ||
6305a203 L |
213 | Valid @var{CPU} values are identical to the processor list of |
214 | @option{-march=@var{CPU}}. | |
9103f4f4 | 215 | |
c0f3af97 L |
216 | @cindex @samp{-msse2avx} option, i386 |
217 | @cindex @samp{-msse2avx} option, x86-64 | |
218 | @item -msse2avx | |
219 | This option specifies that the assembler should encode SSE instructions | |
220 | with VEX prefix. | |
221 | ||
daf50ae7 L |
222 | @cindex @samp{-msse-check=} option, i386 |
223 | @cindex @samp{-msse-check=} option, x86-64 | |
224 | @item -msse-check=@var{none} | |
1f9bb1ca AS |
225 | @itemx -msse-check=@var{warning} |
226 | @itemx -msse-check=@var{error} | |
9aff4b7a | 227 | These options control if the assembler should check SSE instructions. |
daf50ae7 L |
228 | @option{-msse-check=@var{none}} will make the assembler not to check SSE |
229 | instructions, which is the default. @option{-msse-check=@var{warning}} | |
9aff4b7a | 230 | will make the assembler issue a warning for any SSE instruction. |
daf50ae7 | 231 | @option{-msse-check=@var{error}} will make the assembler issue an error |
9aff4b7a | 232 | for any SSE instruction. |
daf50ae7 | 233 | |
539f890d L |
234 | @cindex @samp{-mavxscalar=} option, i386 |
235 | @cindex @samp{-mavxscalar=} option, x86-64 | |
236 | @item -mavxscalar=@var{128} | |
1f9bb1ca | 237 | @itemx -mavxscalar=@var{256} |
2aab8acd | 238 | These options control how the assembler should encode scalar AVX |
539f890d L |
239 | instructions. @option{-mavxscalar=@var{128}} will encode scalar |
240 | AVX instructions with 128bit vector length, which is the default. | |
241 | @option{-mavxscalar=@var{256}} will encode scalar AVX instructions | |
242 | with 256bit vector length. | |
243 | ||
43234a1e L |
244 | @cindex @samp{-mevexlig=} option, i386 |
245 | @cindex @samp{-mevexlig=} option, x86-64 | |
246 | @item -mevexlig=@var{128} | |
247 | @itemx -mevexlig=@var{256} | |
248 | @itemx -mevexlig=@var{512} | |
249 | These options control how the assembler should encode length-ignored | |
250 | (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG | |
251 | EVEX instructions with 128bit vector length, which is the default. | |
252 | @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will | |
253 | encode LIG EVEX instructions with 256bit and 512bit vector length, | |
254 | respectively. | |
255 | ||
256 | @cindex @samp{-mevexwig=} option, i386 | |
257 | @cindex @samp{-mevexwig=} option, x86-64 | |
258 | @item -mevexwig=@var{0} | |
259 | @itemx -mevexwig=@var{1} | |
260 | These options control how the assembler should encode w-ignored (WIG) | |
261 | EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG | |
262 | EVEX instructions with evex.w = 0, which is the default. | |
263 | @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with | |
264 | evex.w = 1. | |
265 | ||
1efbbeb4 L |
266 | @cindex @samp{-mmnemonic=} option, i386 |
267 | @cindex @samp{-mmnemonic=} option, x86-64 | |
268 | @item -mmnemonic=@var{att} | |
1f9bb1ca | 269 | @itemx -mmnemonic=@var{intel} |
34bca508 | 270 | This option specifies instruction mnemonic for matching instructions. |
1efbbeb4 L |
271 | The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will |
272 | take precedent. | |
273 | ||
274 | @cindex @samp{-msyntax=} option, i386 | |
275 | @cindex @samp{-msyntax=} option, x86-64 | |
276 | @item -msyntax=@var{att} | |
1f9bb1ca | 277 | @itemx -msyntax=@var{intel} |
34bca508 | 278 | This option specifies instruction syntax when processing instructions. |
1efbbeb4 L |
279 | The @code{.att_syntax} and @code{.intel_syntax} directives will |
280 | take precedent. | |
281 | ||
282 | @cindex @samp{-mnaked-reg} option, i386 | |
283 | @cindex @samp{-mnaked-reg} option, x86-64 | |
284 | @item -mnaked-reg | |
285 | This opetion specifies that registers don't require a @samp{%} prefix. | |
e1d4d893 | 286 | The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. |
1efbbeb4 | 287 | |
7e8b059b L |
288 | @cindex @samp{-madd-bnd-prefix} option, i386 |
289 | @cindex @samp{-madd-bnd-prefix} option, x86-64 | |
290 | @item -madd-bnd-prefix | |
291 | This option forces the assembler to add BND prefix to all branches, even | |
292 | if such prefix was not explicitly specified in the source code. | |
293 | ||
167ad85b TG |
294 | @cindex @samp{-mbig-obj} option, x86-64 |
295 | @item -mbig-obj | |
296 | On x86-64 PE/COFF target this option forces the use of big object file | |
297 | format, which allows more than 32768 sections. | |
298 | ||
d022bddd IT |
299 | @cindex @samp{-momit-lock-prefix=} option, i386 |
300 | @cindex @samp{-momit-lock-prefix=} option, x86-64 | |
301 | @item -momit-lock-prefix=@var{no} | |
302 | @itemx -momit-lock-prefix=@var{yes} | |
303 | These options control how the assembler should encode lock prefix. | |
304 | This option is intended as a workaround for processors, that fail on | |
305 | lock prefix. This option can only be safely used with single-core, | |
306 | single-thread computers | |
307 | @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. | |
308 | @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, | |
309 | which is the default. | |
310 | ||
d3d3c6db IT |
311 | @cindex @samp{-mevexrcig=} option, i386 |
312 | @cindex @samp{-mevexrcig=} option, x86-64 | |
313 | @item -mevexrcig=@var{rne} | |
314 | @itemx -mevexrcig=@var{rd} | |
315 | @itemx -mevexrcig=@var{ru} | |
316 | @itemx -mevexrcig=@var{rz} | |
317 | These options control how the assembler should encode SAE-only | |
318 | EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits | |
319 | of EVEX instruction with 00, which is the default. | |
320 | @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} | |
321 | and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions | |
322 | with 01, 10 and 11 RC bits, respectively. | |
323 | ||
55b62671 | 324 | @end table |
731caf76 | 325 | @c man end |
e413e4e9 | 326 | |
a6c24e68 NC |
327 | @node i386-Directives |
328 | @section x86 specific Directives | |
329 | ||
330 | @cindex machine directives, x86 | |
331 | @cindex x86 machine directives | |
332 | @table @code | |
333 | ||
334 | @cindex @code{lcomm} directive, COFF | |
335 | @item .lcomm @var{symbol} , @var{length}[, @var{alignment}] | |
336 | Reserve @var{length} (an absolute expression) bytes for a local common | |
337 | denoted by @var{symbol}. The section and value of @var{symbol} are | |
338 | those of the new local common. The addresses are allocated in the bss | |
704209c0 NC |
339 | section, so that at run-time the bytes start off zeroed. Since |
340 | @var{symbol} is not declared global, it is normally not visible to | |
341 | @code{@value{LD}}. The optional third parameter, @var{alignment}, | |
342 | specifies the desired alignment of the symbol in the bss section. | |
a6c24e68 NC |
343 | |
344 | This directive is only available for COFF based x86 targets. | |
345 | ||
346 | @c FIXME: Document other x86 specific directives ? Eg: .code16gcc, | |
347 | @c .largecomm | |
348 | ||
349 | @end table | |
350 | ||
252b5132 | 351 | @node i386-Syntax |
7c31ae13 NC |
352 | @section i386 Syntactical Considerations |
353 | @menu | |
354 | * i386-Variations:: AT&T Syntax versus Intel Syntax | |
355 | * i386-Chars:: Special Characters | |
356 | @end menu | |
357 | ||
358 | @node i386-Variations | |
359 | @subsection AT&T Syntax versus Intel Syntax | |
252b5132 | 360 | |
e413e4e9 AM |
361 | @cindex i386 intel_syntax pseudo op |
362 | @cindex intel_syntax pseudo op, i386 | |
363 | @cindex i386 att_syntax pseudo op | |
364 | @cindex att_syntax pseudo op, i386 | |
252b5132 RH |
365 | @cindex i386 syntax compatibility |
366 | @cindex syntax compatibility, i386 | |
55b62671 AJ |
367 | @cindex x86-64 intel_syntax pseudo op |
368 | @cindex intel_syntax pseudo op, x86-64 | |
369 | @cindex x86-64 att_syntax pseudo op | |
370 | @cindex att_syntax pseudo op, x86-64 | |
371 | @cindex x86-64 syntax compatibility | |
372 | @cindex syntax compatibility, x86-64 | |
e413e4e9 AM |
373 | |
374 | @code{@value{AS}} now supports assembly using Intel assembler syntax. | |
375 | @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches | |
376 | back to the usual AT&T mode for compatibility with the output of | |
377 | @code{@value{GCC}}. Either of these directives may have an optional | |
378 | argument, @code{prefix}, or @code{noprefix} specifying whether registers | |
379 | require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite | |
252b5132 RH |
380 | different from Intel syntax. We mention these differences because |
381 | almost all 80386 documents use Intel syntax. Notable differences | |
382 | between the two syntaxes are: | |
383 | ||
384 | @cindex immediate operands, i386 | |
385 | @cindex i386 immediate operands | |
386 | @cindex register operands, i386 | |
387 | @cindex i386 register operands | |
388 | @cindex jump/call operands, i386 | |
389 | @cindex i386 jump/call operands | |
390 | @cindex operand delimiters, i386 | |
55b62671 AJ |
391 | |
392 | @cindex immediate operands, x86-64 | |
393 | @cindex x86-64 immediate operands | |
394 | @cindex register operands, x86-64 | |
395 | @cindex x86-64 register operands | |
396 | @cindex jump/call operands, x86-64 | |
397 | @cindex x86-64 jump/call operands | |
398 | @cindex operand delimiters, x86-64 | |
252b5132 RH |
399 | @itemize @bullet |
400 | @item | |
401 | AT&T immediate operands are preceded by @samp{$}; Intel immediate | |
402 | operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). | |
403 | AT&T register operands are preceded by @samp{%}; Intel register operands | |
404 | are undelimited. AT&T absolute (as opposed to PC relative) jump/call | |
405 | operands are prefixed by @samp{*}; they are undelimited in Intel syntax. | |
406 | ||
407 | @cindex i386 source, destination operands | |
408 | @cindex source, destination operands; i386 | |
55b62671 AJ |
409 | @cindex x86-64 source, destination operands |
410 | @cindex source, destination operands; x86-64 | |
252b5132 RH |
411 | @item |
412 | AT&T and Intel syntax use the opposite order for source and destination | |
413 | operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The | |
414 | @samp{source, dest} convention is maintained for compatibility with | |
96ef6e0f L |
415 | previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and |
416 | instructions with 2 immediate operands, such as the @samp{enter} | |
417 | instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. | |
252b5132 RH |
418 | |
419 | @cindex mnemonic suffixes, i386 | |
420 | @cindex sizes operands, i386 | |
421 | @cindex i386 size suffixes | |
55b62671 AJ |
422 | @cindex mnemonic suffixes, x86-64 |
423 | @cindex sizes operands, x86-64 | |
424 | @cindex x86-64 size suffixes | |
252b5132 RH |
425 | @item |
426 | In AT&T syntax the size of memory operands is determined from the last | |
427 | character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, | |
55b62671 AJ |
428 | @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long |
429 | (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes | |
430 | this by prefixing memory operands (@emph{not} the instruction mnemonics) with | |
431 | @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, | |
432 | Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T | |
433 | syntax. | |
252b5132 | 434 | |
4b06377f L |
435 | In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} |
436 | instruction with the 64-bit displacement or immediate operand. | |
437 | ||
252b5132 RH |
438 | @cindex return instructions, i386 |
439 | @cindex i386 jump, call, return | |
55b62671 AJ |
440 | @cindex return instructions, x86-64 |
441 | @cindex x86-64 jump, call, return | |
252b5132 RH |
442 | @item |
443 | Immediate form long jumps and calls are | |
444 | @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the | |
445 | Intel syntax is | |
446 | @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return | |
447 | instruction | |
448 | is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is | |
449 | @samp{ret far @var{stack-adjust}}. | |
450 | ||
451 | @cindex sections, i386 | |
452 | @cindex i386 sections | |
55b62671 AJ |
453 | @cindex sections, x86-64 |
454 | @cindex x86-64 sections | |
252b5132 RH |
455 | @item |
456 | The AT&T assembler does not provide support for multiple section | |
457 | programs. Unix style systems expect all programs to be single sections. | |
458 | @end itemize | |
459 | ||
7c31ae13 NC |
460 | @node i386-Chars |
461 | @subsection Special Characters | |
462 | ||
463 | @cindex line comment character, i386 | |
464 | @cindex i386 line comment character | |
465 | The presence of a @samp{#} appearing anywhere on a line indicates the | |
466 | start of a comment that extends to the end of that line. | |
467 | ||
468 | If a @samp{#} appears as the first character of a line then the whole | |
469 | line is treated as a comment, but in this case the line can also be a | |
470 | logical line number directive (@pxref{Comments}) or a preprocessor | |
471 | control command (@pxref{Preprocessing}). | |
472 | ||
473 | If the @option{--divide} command line option has not been specified | |
474 | then the @samp{/} character appearing anywhere on a line also | |
475 | introduces a line comment. | |
476 | ||
477 | @cindex line separator, i386 | |
478 | @cindex statement separator, i386 | |
479 | @cindex i386 line separator | |
480 | The @samp{;} character can be used to separate statements on the same | |
481 | line. | |
482 | ||
252b5132 RH |
483 | @node i386-Mnemonics |
484 | @section Instruction Naming | |
485 | ||
486 | @cindex i386 instruction naming | |
487 | @cindex instruction naming, i386 | |
55b62671 AJ |
488 | @cindex x86-64 instruction naming |
489 | @cindex instruction naming, x86-64 | |
490 | ||
252b5132 | 491 | Instruction mnemonics are suffixed with one character modifiers which |
55b62671 AJ |
492 | specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} |
493 | and @samp{q} specify byte, word, long and quadruple word operands. If | |
494 | no suffix is specified by an instruction then @code{@value{AS}} tries to | |
495 | fill in the missing suffix based on the destination register operand | |
496 | (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent | |
497 | to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to | |
498 | @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix | |
499 | assembler which assumes that a missing mnemonic suffix implies long | |
500 | operand size. (This incompatibility does not affect compiler output | |
501 | since compilers always explicitly specify the mnemonic suffix.) | |
252b5132 RH |
502 | |
503 | Almost all instructions have the same names in AT&T and Intel format. | |
504 | There are a few exceptions. The sign extend and zero extend | |
505 | instructions need two sizes to specify them. They need a size to | |
506 | sign/zero extend @emph{from} and a size to zero extend @emph{to}. This | |
507 | is accomplished by using two instruction mnemonic suffixes in AT&T | |
508 | syntax. Base names for sign extend and zero extend are | |
509 | @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} | |
510 | and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes | |
511 | are tacked on to this base name, the @emph{from} suffix before the | |
512 | @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for | |
513 | ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, | |
514 | thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), | |
55b62671 AJ |
515 | @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), |
516 | @samp{wq} (from word to quadruple word), and @samp{lq} (from long to | |
517 | quadruple word). | |
252b5132 | 518 | |
b6169b20 L |
519 | @cindex encoding options, i386 |
520 | @cindex encoding options, x86-64 | |
521 | ||
522 | Different encoding options can be specified via optional mnemonic | |
523 | suffix. @samp{.s} suffix swaps 2 register operands in encoding when | |
a501d77e L |
524 | moving from one register to another. @samp{.d8} or @samp{.d32} suffix |
525 | prefers 8bit or 32bit displacement in encoding. | |
b6169b20 | 526 | |
252b5132 RH |
527 | @cindex conversion instructions, i386 |
528 | @cindex i386 conversion instructions | |
55b62671 AJ |
529 | @cindex conversion instructions, x86-64 |
530 | @cindex x86-64 conversion instructions | |
252b5132 RH |
531 | The Intel-syntax conversion instructions |
532 | ||
533 | @itemize @bullet | |
534 | @item | |
535 | @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, | |
536 | ||
537 | @item | |
538 | @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, | |
539 | ||
540 | @item | |
541 | @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, | |
542 | ||
543 | @item | |
544 | @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, | |
55b62671 AJ |
545 | |
546 | @item | |
547 | @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} | |
548 | (x86-64 only), | |
549 | ||
550 | @item | |
d5f0cf92 | 551 | @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in |
55b62671 | 552 | @samp{%rdx:%rax} (x86-64 only), |
252b5132 RH |
553 | @end itemize |
554 | ||
555 | @noindent | |
55b62671 AJ |
556 | are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and |
557 | @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these | |
558 | instructions. | |
252b5132 RH |
559 | |
560 | @cindex jump instructions, i386 | |
561 | @cindex call instructions, i386 | |
55b62671 AJ |
562 | @cindex jump instructions, x86-64 |
563 | @cindex call instructions, x86-64 | |
252b5132 RH |
564 | Far call/jump instructions are @samp{lcall} and @samp{ljmp} in |
565 | AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel | |
566 | convention. | |
567 | ||
1efbbeb4 L |
568 | @section AT&T Mnemonic versus Intel Mnemonic |
569 | ||
570 | @cindex i386 mnemonic compatibility | |
571 | @cindex mnemonic compatibility, i386 | |
572 | ||
573 | @code{@value{AS}} supports assembly using Intel mnemonic. | |
574 | @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and | |
575 | @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T | |
576 | syntax for compatibility with the output of @code{@value{GCC}}. | |
1efbbeb4 L |
577 | Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, |
578 | @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, | |
579 | @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 | |
580 | assembler with different mnemonics from those in Intel IA32 specification. | |
581 | @code{@value{GCC}} generates those instructions with AT&T mnemonic. | |
582 | ||
252b5132 RH |
583 | @node i386-Regs |
584 | @section Register Naming | |
585 | ||
586 | @cindex i386 registers | |
587 | @cindex registers, i386 | |
55b62671 AJ |
588 | @cindex x86-64 registers |
589 | @cindex registers, x86-64 | |
252b5132 RH |
590 | Register operands are always prefixed with @samp{%}. The 80386 registers |
591 | consist of | |
592 | ||
593 | @itemize @bullet | |
594 | @item | |
595 | the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, | |
596 | @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the | |
597 | frame pointer), and @samp{%esp} (the stack pointer). | |
598 | ||
599 | @item | |
600 | the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, | |
601 | @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. | |
602 | ||
603 | @item | |
604 | the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, | |
605 | @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These | |
606 | are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, | |
607 | @samp{%cx}, and @samp{%dx}) | |
608 | ||
609 | @item | |
610 | the 6 section registers @samp{%cs} (code section), @samp{%ds} | |
611 | (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, | |
612 | and @samp{%gs}. | |
613 | ||
614 | @item | |
615 | the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and | |
616 | @samp{%cr3}. | |
617 | ||
618 | @item | |
619 | the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, | |
620 | @samp{%db3}, @samp{%db6}, and @samp{%db7}. | |
621 | ||
622 | @item | |
623 | the 2 test registers @samp{%tr6} and @samp{%tr7}. | |
624 | ||
625 | @item | |
626 | the 8 floating point register stack @samp{%st} or equivalently | |
627 | @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, | |
628 | @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. | |
55b62671 AJ |
629 | These registers are overloaded by 8 MMX registers @samp{%mm0}, |
630 | @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, | |
631 | @samp{%mm6} and @samp{%mm7}. | |
632 | ||
633 | @item | |
634 | the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, | |
635 | @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. | |
636 | @end itemize | |
637 | ||
638 | The AMD x86-64 architecture extends the register set by: | |
639 | ||
640 | @itemize @bullet | |
641 | @item | |
642 | enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the | |
643 | accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, | |
644 | @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack | |
645 | pointer) | |
646 | ||
647 | @item | |
648 | the 8 extended registers @samp{%r8}--@samp{%r15}. | |
649 | ||
650 | @item | |
651 | the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d} | |
652 | ||
653 | @item | |
654 | the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w} | |
655 | ||
656 | @item | |
657 | the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b} | |
658 | ||
659 | @item | |
660 | the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. | |
661 | ||
662 | @item | |
663 | the 8 debug registers: @samp{%db8}--@samp{%db15}. | |
664 | ||
665 | @item | |
666 | the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}. | |
252b5132 RH |
667 | @end itemize |
668 | ||
669 | @node i386-Prefixes | |
670 | @section Instruction Prefixes | |
671 | ||
672 | @cindex i386 instruction prefixes | |
673 | @cindex instruction prefixes, i386 | |
674 | @cindex prefixes, i386 | |
675 | Instruction prefixes are used to modify the following instruction. They | |
676 | are used to repeat string instructions, to provide section overrides, to | |
677 | perform bus lock operations, and to change operand and address sizes. | |
678 | (Most instructions that normally operate on 32-bit operands will use | |
679 | 16-bit operands if the instruction has an ``operand size'' prefix.) | |
680 | Instruction prefixes are best written on the same line as the instruction | |
681 | they act upon. For example, the @samp{scas} (scan string) instruction is | |
682 | repeated with: | |
683 | ||
684 | @smallexample | |
685 | repne scas %es:(%edi),%al | |
686 | @end smallexample | |
687 | ||
688 | You may also place prefixes on the lines immediately preceding the | |
689 | instruction, but this circumvents checks that @code{@value{AS}} does | |
690 | with prefixes, and will not work with all prefixes. | |
691 | ||
692 | Here is a list of instruction prefixes: | |
693 | ||
694 | @cindex section override prefixes, i386 | |
695 | @itemize @bullet | |
696 | @item | |
697 | Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, | |
698 | @samp{fs}, @samp{gs}. These are automatically added by specifying | |
699 | using the @var{section}:@var{memory-operand} form for memory references. | |
700 | ||
701 | @cindex size prefixes, i386 | |
702 | @item | |
703 | Operand/Address size prefixes @samp{data16} and @samp{addr16} | |
704 | change 32-bit operands/addresses into 16-bit operands/addresses, | |
705 | while @samp{data32} and @samp{addr32} change 16-bit ones (in a | |
706 | @code{.code16} section) into 32-bit operands/addresses. These prefixes | |
707 | @emph{must} appear on the same line of code as the instruction they | |
708 | modify. For example, in a 16-bit @code{.code16} section, you might | |
709 | write: | |
710 | ||
711 | @smallexample | |
712 | addr32 jmpl *(%ebx) | |
713 | @end smallexample | |
714 | ||
715 | @cindex bus lock prefixes, i386 | |
716 | @cindex inhibiting interrupts, i386 | |
717 | @item | |
718 | The bus lock prefix @samp{lock} inhibits interrupts during execution of | |
719 | the instruction it precedes. (This is only valid with certain | |
720 | instructions; see a 80386 manual for details). | |
721 | ||
722 | @cindex coprocessor wait, i386 | |
723 | @item | |
724 | The wait for coprocessor prefix @samp{wait} waits for the coprocessor to | |
725 | complete the current instruction. This should never be needed for the | |
726 | 80386/80387 combination. | |
727 | ||
728 | @cindex repeat prefixes, i386 | |
729 | @item | |
730 | The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added | |
731 | to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} | |
732 | times if the current address size is 16-bits). | |
55b62671 AJ |
733 | @cindex REX prefixes, i386 |
734 | @item | |
735 | The @samp{rex} family of prefixes is used by x86-64 to encode | |
736 | extensions to i386 instruction set. The @samp{rex} prefix has four | |
737 | bits --- an operand size overwrite (@code{64}) used to change operand size | |
738 | from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the | |
739 | register set. | |
740 | ||
741 | You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} | |
742 | instruction emits @samp{rex} prefix with all the bits set. By omitting | |
743 | the @code{64}, @code{x}, @code{y} or @code{z} you may write other | |
744 | prefixes as well. Normally, there is no need to write the prefixes | |
745 | explicitly, since gas will automatically generate them based on the | |
746 | instruction operands. | |
252b5132 RH |
747 | @end itemize |
748 | ||
749 | @node i386-Memory | |
750 | @section Memory References | |
751 | ||
752 | @cindex i386 memory references | |
753 | @cindex memory references, i386 | |
55b62671 AJ |
754 | @cindex x86-64 memory references |
755 | @cindex memory references, x86-64 | |
252b5132 RH |
756 | An Intel syntax indirect memory reference of the form |
757 | ||
758 | @smallexample | |
759 | @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] | |
760 | @end smallexample | |
761 | ||
762 | @noindent | |
763 | is translated into the AT&T syntax | |
764 | ||
765 | @smallexample | |
766 | @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) | |
767 | @end smallexample | |
768 | ||
769 | @noindent | |
770 | where @var{base} and @var{index} are the optional 32-bit base and | |
771 | index registers, @var{disp} is the optional displacement, and | |
772 | @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} | |
773 | to calculate the address of the operand. If no @var{scale} is | |
774 | specified, @var{scale} is taken to be 1. @var{section} specifies the | |
775 | optional section register for the memory operand, and may override the | |
776 | default section register (see a 80386 manual for section register | |
777 | defaults). Note that section overrides in AT&T syntax @emph{must} | |
778 | be preceded by a @samp{%}. If you specify a section override which | |
779 | coincides with the default section register, @code{@value{AS}} does @emph{not} | |
780 | output any section register override prefixes to assemble the given | |
781 | instruction. Thus, section overrides can be specified to emphasize which | |
782 | section register is used for a given memory operand. | |
783 | ||
784 | Here are some examples of Intel and AT&T style memory references: | |
785 | ||
786 | @table @asis | |
787 | @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} | |
788 | @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is | |
789 | missing, and the default section is used (@samp{%ss} for addressing with | |
790 | @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. | |
791 | ||
792 | @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} | |
793 | @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is | |
794 | @samp{foo}. All other fields are missing. The section register here | |
795 | defaults to @samp{%ds}. | |
796 | ||
797 | @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} | |
798 | This uses the value pointed to by @samp{foo} as a memory operand. | |
799 | Note that @var{base} and @var{index} are both missing, but there is only | |
800 | @emph{one} @samp{,}. This is a syntactic exception. | |
801 | ||
802 | @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} | |
803 | This selects the contents of the variable @samp{foo} with section | |
804 | register @var{section} being @samp{%gs}. | |
805 | @end table | |
806 | ||
807 | Absolute (as opposed to PC relative) call and jump operands must be | |
808 | prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} | |
809 | always chooses PC relative addressing for jump/call labels. | |
810 | ||
811 | Any instruction that has a memory operand, but no register operand, | |
55b62671 AJ |
812 | @emph{must} specify its size (byte, word, long, or quadruple) with an |
813 | instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, | |
814 | respectively). | |
815 | ||
816 | The x86-64 architecture adds an RIP (instruction pointer relative) | |
817 | addressing. This addressing mode is specified by using @samp{rip} as a | |
818 | base register. Only constant offsets are valid. For example: | |
819 | ||
820 | @table @asis | |
821 | @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} | |
822 | Points to the address 1234 bytes past the end of the current | |
823 | instruction. | |
824 | ||
825 | @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} | |
826 | Points to the @code{symbol} in RIP relative way, this is shorter than | |
827 | the default absolute addressing. | |
828 | @end table | |
829 | ||
830 | Other addressing modes remain unchanged in x86-64 architecture, except | |
831 | registers used are 64-bit instead of 32-bit. | |
252b5132 | 832 | |
fddf5b5b | 833 | @node i386-Jumps |
252b5132 RH |
834 | @section Handling of Jump Instructions |
835 | ||
836 | @cindex jump optimization, i386 | |
837 | @cindex i386 jump optimization | |
55b62671 AJ |
838 | @cindex jump optimization, x86-64 |
839 | @cindex x86-64 jump optimization | |
252b5132 RH |
840 | Jump instructions are always optimized to use the smallest possible |
841 | displacements. This is accomplished by using byte (8-bit) displacement | |
842 | jumps whenever the target is sufficiently close. If a byte displacement | |
fddf5b5b | 843 | is insufficient a long displacement is used. We do not support |
252b5132 RH |
844 | word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump |
845 | instruction with the @samp{data16} instruction prefix), since the 80386 | |
846 | insists upon masking @samp{%eip} to 16 bits after the word displacement | |
fddf5b5b | 847 | is added. (See also @pxref{i386-Arch}) |
252b5132 RH |
848 | |
849 | Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, | |
850 | @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte | |
851 | displacements, so that if you use these instructions (@code{@value{GCC}} does | |
852 | not use them) you may get an error message (and incorrect code). The AT&T | |
853 | 80386 assembler tries to get around this problem by expanding @samp{jcxz foo} | |
854 | to | |
855 | ||
856 | @smallexample | |
857 | jcxz cx_zero | |
858 | jmp cx_nonzero | |
859 | cx_zero: jmp foo | |
860 | cx_nonzero: | |
861 | @end smallexample | |
862 | ||
863 | @node i386-Float | |
864 | @section Floating Point | |
865 | ||
866 | @cindex i386 floating point | |
867 | @cindex floating point, i386 | |
55b62671 AJ |
868 | @cindex x86-64 floating point |
869 | @cindex floating point, x86-64 | |
252b5132 RH |
870 | All 80387 floating point types except packed BCD are supported. |
871 | (BCD support may be added without much difficulty). These data | |
872 | types are 16-, 32-, and 64- bit integers, and single (32-bit), | |
873 | double (64-bit), and extended (80-bit) precision floating point. | |
874 | Each supported type has an instruction mnemonic suffix and a constructor | |
875 | associated with it. Instruction mnemonic suffixes specify the operand's | |
876 | data type. Constructors build these data types into memory. | |
877 | ||
878 | @cindex @code{float} directive, i386 | |
879 | @cindex @code{single} directive, i386 | |
880 | @cindex @code{double} directive, i386 | |
881 | @cindex @code{tfloat} directive, i386 | |
55b62671 AJ |
882 | @cindex @code{float} directive, x86-64 |
883 | @cindex @code{single} directive, x86-64 | |
884 | @cindex @code{double} directive, x86-64 | |
885 | @cindex @code{tfloat} directive, x86-64 | |
252b5132 RH |
886 | @itemize @bullet |
887 | @item | |
888 | Floating point constructors are @samp{.float} or @samp{.single}, | |
889 | @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. | |
890 | These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, | |
891 | and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 | |
892 | only supports this format via the @samp{fldt} (load 80-bit real to stack | |
893 | top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. | |
894 | ||
895 | @cindex @code{word} directive, i386 | |
896 | @cindex @code{long} directive, i386 | |
897 | @cindex @code{int} directive, i386 | |
898 | @cindex @code{quad} directive, i386 | |
55b62671 AJ |
899 | @cindex @code{word} directive, x86-64 |
900 | @cindex @code{long} directive, x86-64 | |
901 | @cindex @code{int} directive, x86-64 | |
902 | @cindex @code{quad} directive, x86-64 | |
252b5132 RH |
903 | @item |
904 | Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and | |
905 | @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The | |
906 | corresponding instruction mnemonic suffixes are @samp{s} (single), | |
907 | @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, | |
908 | the 64-bit @samp{q} format is only present in the @samp{fildq} (load | |
909 | quad integer to stack top) and @samp{fistpq} (store quad integer and pop | |
910 | stack) instructions. | |
911 | @end itemize | |
912 | ||
913 | Register to register operations should not use instruction mnemonic suffixes. | |
914 | @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you | |
915 | wrote @samp{fst %st, %st(1)}, since all register to register operations | |
916 | use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, | |
917 | which converts @samp{%st} from 80-bit to 64-bit floating point format, | |
918 | then stores the result in the 4 byte location @samp{mem}) | |
919 | ||
920 | @node i386-SIMD | |
921 | @section Intel's MMX and AMD's 3DNow! SIMD Operations | |
922 | ||
923 | @cindex MMX, i386 | |
924 | @cindex 3DNow!, i386 | |
925 | @cindex SIMD, i386 | |
55b62671 AJ |
926 | @cindex MMX, x86-64 |
927 | @cindex 3DNow!, x86-64 | |
928 | @cindex SIMD, x86-64 | |
252b5132 RH |
929 | |
930 | @code{@value{AS}} supports Intel's MMX instruction set (SIMD | |
931 | instructions for integer data), available on Intel's Pentium MMX | |
932 | processors and Pentium II processors, AMD's K6 and K6-2 processors, | |
b45619c0 | 933 | Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: |
252b5132 RH |
934 | instruction set (SIMD instructions for 32-bit floating point data) |
935 | available on AMD's K6-2 processor and possibly others in the future. | |
936 | ||
937 | Currently, @code{@value{AS}} does not support Intel's floating point | |
938 | SIMD, Katmai (KNI). | |
939 | ||
940 | The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, | |
941 | @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four | |
942 | 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit | |
943 | floating point values. The MMX registers cannot be used at the same time | |
944 | as the floating point stack. | |
945 | ||
946 | See Intel and AMD documentation, keeping in mind that the operand order in | |
947 | instructions is reversed from the Intel syntax. | |
948 | ||
f88c9eb0 SP |
949 | @node i386-LWP |
950 | @section AMD's Lightweight Profiling Instructions | |
951 | ||
952 | @cindex LWP, i386 | |
953 | @cindex LWP, x86-64 | |
954 | ||
955 | @code{@value{AS}} supports AMD's Lightweight Profiling (LWP) | |
956 | instruction set, available on AMD's Family 15h (Orochi) processors. | |
957 | ||
958 | LWP enables applications to collect and manage performance data, and | |
959 | react to performance events. The collection of performance data | |
960 | requires no context switches. LWP runs in the context of a thread and | |
961 | so several counters can be used independently across multiple threads. | |
962 | LWP can be used in both 64-bit and legacy 32-bit modes. | |
963 | ||
964 | For detailed information on the LWP instruction set, see the | |
965 | @cite{AMD Lightweight Profiling Specification} available at | |
966 | @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. | |
967 | ||
87973e9f QN |
968 | @node i386-BMI |
969 | @section Bit Manipulation Instructions | |
970 | ||
971 | @cindex BMI, i386 | |
972 | @cindex BMI, x86-64 | |
973 | ||
974 | @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. | |
975 | ||
976 | BMI instructions provide several instructions implementing individual | |
977 | bit manipulation operations such as isolation, masking, setting, or | |
34bca508 | 978 | resetting. |
87973e9f QN |
979 | |
980 | @c Need to add a specification citation here when available. | |
981 | ||
2a2a0f38 QN |
982 | @node i386-TBM |
983 | @section AMD's Trailing Bit Manipulation Instructions | |
984 | ||
985 | @cindex TBM, i386 | |
986 | @cindex TBM, x86-64 | |
987 | ||
988 | @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) | |
989 | instruction set, available on AMD's BDVER2 processors (Trinity and | |
990 | Viperfish). | |
991 | ||
992 | TBM instructions provide instructions implementing individual bit | |
993 | manipulation operations such as isolating, masking, setting, resetting, | |
994 | complementing, and operations on trailing zeros and ones. | |
995 | ||
996 | @c Need to add a specification citation here when available. | |
87973e9f | 997 | |
252b5132 RH |
998 | @node i386-16bit |
999 | @section Writing 16-bit Code | |
1000 | ||
1001 | @cindex i386 16-bit code | |
1002 | @cindex 16-bit code, i386 | |
1003 | @cindex real-mode code, i386 | |
eecb386c | 1004 | @cindex @code{code16gcc} directive, i386 |
252b5132 RH |
1005 | @cindex @code{code16} directive, i386 |
1006 | @cindex @code{code32} directive, i386 | |
55b62671 AJ |
1007 | @cindex @code{code64} directive, i386 |
1008 | @cindex @code{code64} directive, x86-64 | |
1009 | While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code | |
1010 | or 64-bit x86-64 code depending on the default configuration, | |
252b5132 | 1011 | it also supports writing code to run in real mode or in 16-bit protected |
eecb386c AM |
1012 | mode code segments. To do this, put a @samp{.code16} or |
1013 | @samp{.code16gcc} directive before the assembly language instructions to | |
995cef8c L |
1014 | be run in 16-bit mode. You can switch @code{@value{AS}} to writing |
1015 | 32-bit code with the @samp{.code32} directive or 64-bit code with the | |
1016 | @samp{.code64} directive. | |
eecb386c AM |
1017 | |
1018 | @samp{.code16gcc} provides experimental support for generating 16-bit | |
1019 | code from gcc, and differs from @samp{.code16} in that @samp{call}, | |
1020 | @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, | |
1021 | @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions | |
1022 | default to 32-bit size. This is so that the stack pointer is | |
1023 | manipulated in the same way over function calls, allowing access to | |
1024 | function parameters at the same stack offsets as in 32-bit mode. | |
1025 | @samp{.code16gcc} also automatically adds address size prefixes where | |
1026 | necessary to use the 32-bit addressing modes that gcc generates. | |
252b5132 RH |
1027 | |
1028 | The code which @code{@value{AS}} generates in 16-bit mode will not | |
1029 | necessarily run on a 16-bit pre-80386 processor. To write code that | |
1030 | runs on such a processor, you must refrain from using @emph{any} 32-bit | |
1031 | constructs which require @code{@value{AS}} to output address or operand | |
1032 | size prefixes. | |
1033 | ||
1034 | Note that writing 16-bit code instructions by explicitly specifying a | |
1035 | prefix or an instruction mnemonic suffix within a 32-bit code section | |
1036 | generates different machine instructions than those generated for a | |
1037 | 16-bit code segment. In a 32-bit code section, the following code | |
1038 | generates the machine opcode bytes @samp{66 6a 04}, which pushes the | |
1039 | value @samp{4} onto the stack, decrementing @samp{%esp} by 2. | |
1040 | ||
1041 | @smallexample | |
1042 | pushw $4 | |
1043 | @end smallexample | |
1044 | ||
1045 | The same code in a 16-bit code section would generate the machine | |
b45619c0 | 1046 | opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which |
252b5132 RH |
1047 | is correct since the processor default operand size is assumed to be 16 |
1048 | bits in a 16-bit code section. | |
1049 | ||
1050 | @node i386-Bugs | |
1051 | @section AT&T Syntax bugs | |
1052 | ||
1053 | The UnixWare assembler, and probably other AT&T derived ix86 Unix | |
1054 | assemblers, generate floating point instructions with reversed source | |
1055 | and destination registers in certain cases. Unfortunately, gcc and | |
1056 | possibly many other programs use this reversed syntax, so we're stuck | |
1057 | with it. | |
1058 | ||
1059 | For example | |
1060 | ||
1061 | @smallexample | |
1062 | fsub %st,%st(3) | |
1063 | @end smallexample | |
1064 | @noindent | |
1065 | results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather | |
1066 | than the expected @samp{%st(3) - %st}. This happens with all the | |
1067 | non-commutative arithmetic floating point operations with two register | |
1068 | operands where the source register is @samp{%st} and the destination | |
1069 | register is @samp{%st(i)}. | |
1070 | ||
e413e4e9 AM |
1071 | @node i386-Arch |
1072 | @section Specifying CPU Architecture | |
1073 | ||
1074 | @cindex arch directive, i386 | |
1075 | @cindex i386 arch directive | |
55b62671 AJ |
1076 | @cindex arch directive, x86-64 |
1077 | @cindex x86-64 arch directive | |
e413e4e9 AM |
1078 | |
1079 | @code{@value{AS}} may be told to assemble for a particular CPU | |
5c6af06e | 1080 | (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This |
e413e4e9 AM |
1081 | directive enables a warning when gas detects an instruction that is not |
1082 | supported on the CPU specified. The choices for @var{cpu_type} are: | |
1083 | ||
1084 | @multitable @columnfractions .20 .20 .20 .20 | |
1085 | @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} | |
1086 | @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} | |
5c6af06e | 1087 | @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} |
ef05d495 | 1088 | @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} |
7a9068fe | 1089 | @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} |
1543849b | 1090 | @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} |
5e5c50d3 | 1091 | @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} |
c7b0bd56 | 1092 | @item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2} |
1ceab344 | 1093 | @item @samp{generic32} @tab @samp{generic64} |
9103f4f4 | 1094 | @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} |
d76f7bc1 | 1095 | @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} |
c7b8aa3a L |
1096 | @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} |
1097 | @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} | |
1098 | @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} | |
6c30d220 | 1099 | @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} |
42164a71 | 1100 | @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} |
e2e1fcde | 1101 | @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} |
1dfc6506 L |
1102 | @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} |
1103 | @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} | |
1104 | @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} | |
1105 | @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} | |
1ceab344 | 1106 | @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} |
f72d7f29 | 1107 | @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} |
60aa667e | 1108 | @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} |
1ceab344 | 1109 | @item @samp{.padlock} |
e413e4e9 AM |
1110 | @end multitable |
1111 | ||
fddf5b5b AM |
1112 | Apart from the warning, there are only two other effects on |
1113 | @code{@value{AS}} operation; Firstly, if you specify a CPU other than | |
e413e4e9 AM |
1114 | @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} |
1115 | will automatically use a two byte opcode sequence. The larger three | |
1116 | byte opcode sequence is used on the 486 (and when no architecture is | |
1117 | specified) because it executes faster on the 486. Note that you can | |
1118 | explicitly request the two byte opcode by writing @samp{sarl %eax}. | |
fddf5b5b AM |
1119 | Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, |
1120 | @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset | |
1121 | conditional jumps will be promoted when necessary to a two instruction | |
1122 | sequence consisting of a conditional jump of the opposite sense around | |
1123 | an unconditional jump to the target. | |
1124 | ||
5c6af06e JB |
1125 | Following the CPU architecture (but not a sub-architecture, which are those |
1126 | starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to | |
1127 | control automatic promotion of conditional jumps. @samp{jumps} is the | |
1128 | default, and enables jump promotion; All external jumps will be of the long | |
1129 | variety, and file-local jumps will be promoted as necessary. | |
1130 | (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as | |
1131 | byte offset jumps, and warns about file-local conditional jumps that | |
1132 | @code{@value{AS}} promotes. | |
fddf5b5b AM |
1133 | Unconditional jumps are treated as for @samp{jumps}. |
1134 | ||
1135 | For example | |
1136 | ||
1137 | @smallexample | |
1138 | .arch i8086,nojumps | |
1139 | @end smallexample | |
e413e4e9 | 1140 | |
252b5132 RH |
1141 | @node i386-Notes |
1142 | @section Notes | |
1143 | ||
1144 | @cindex i386 @code{mul}, @code{imul} instructions | |
1145 | @cindex @code{mul} instruction, i386 | |
1146 | @cindex @code{imul} instruction, i386 | |
55b62671 AJ |
1147 | @cindex @code{mul} instruction, x86-64 |
1148 | @cindex @code{imul} instruction, x86-64 | |
252b5132 | 1149 | There is some trickery concerning the @samp{mul} and @samp{imul} |
55b62671 | 1150 | instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding |
252b5132 RH |
1151 | multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 |
1152 | for @samp{imul}) can be output only in the one operand form. Thus, | |
1153 | @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; | |
1154 | the expanding multiply would clobber the @samp{%edx} register, and this | |
1155 | would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the | |
1156 | 64-bit product in @samp{%edx:%eax}. | |
1157 | ||
1158 | We have added a two operand form of @samp{imul} when the first operand | |
1159 | is an immediate mode expression and the second operand is a register. | |
1160 | This is just a shorthand, so that, multiplying @samp{%eax} by 69, for | |
1161 | example, can be done with @samp{imul $69, %eax} rather than @samp{imul | |
1162 | $69, %eax, %eax}. | |
1163 |