x86: Add {rex} pseudo prefix
[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi
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219d1afa 1@c Copyright (C) 1991-2018 Free Software Foundation, Inc.
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2@c This is part of the GAS manual.
3@c For copying conditions, see the file as.texinfo.
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4@c man end
5
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6@ifset GENERIC
7@page
8@node i386-Dependent
9@chapter 80386 Dependent Features
10@end ifset
11@ifclear GENERIC
12@node Machine Dependencies
13@chapter 80386 Dependent Features
14@end ifclear
15
16@cindex i386 support
b6169b20 17@cindex i80386 support
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18@cindex x86-64 support
19
20The i386 version @code{@value{AS}} supports both the original Intel 386
21architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22extending the Intel architecture to 64-bits.
23
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24@menu
25* i386-Options:: Options
a6c24e68 26* i386-Directives:: X86 specific directives
7c31ae13 27* i386-Syntax:: Syntactical considerations
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28* i386-Mnemonics:: Instruction Naming
29* i386-Regs:: Register Naming
30* i386-Prefixes:: Instruction Prefixes
31* i386-Memory:: Memory References
fddf5b5b 32* i386-Jumps:: Handling of Jump Instructions
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33* i386-Float:: Floating Point
34* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
f88c9eb0 35* i386-LWP:: AMD's Lightweight Profiling Instructions
87973e9f 36* i386-BMI:: Bit Manipulation Instruction
2a2a0f38 37* i386-TBM:: AMD's Trailing Bit Manipulation Instructions
252b5132 38* i386-16bit:: Writing 16-bit Code
e413e4e9 39* i386-Arch:: Specifying an x86 CPU architecture
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40* i386-Bugs:: AT&T Syntax bugs
41* i386-Notes:: Notes
42@end menu
43
44@node i386-Options
45@section Options
46
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47@cindex options for i386
48@cindex options for x86-64
49@cindex i386 options
34bca508 50@cindex x86-64 options
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51
52The i386 version of @code{@value{AS}} has a few machine
53dependent options:
54
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55@c man begin OPTIONS
56@table @gcctabopt
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57@cindex @samp{--32} option, i386
58@cindex @samp{--32} option, x86-64
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59@cindex @samp{--x32} option, i386
60@cindex @samp{--x32} option, x86-64
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61@cindex @samp{--64} option, i386
62@cindex @samp{--64} option, x86-64
570561f7 63@item --32 | --x32 | --64
35cc6a0b 64Select the word size, either 32 bits or 64 bits. @samp{--32}
570561f7 65implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
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66imply AMD x86-64 architecture with 32-bit or 64-bit word-size
67respectively.
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68
69These options are only available with the ELF object file format, and
70require that the necessary BFD support has been included (on a 32-bit
71platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72usage and use x86-64 as target platform).
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73
74@item -n
75By default, x86 GAS replaces multiple nop instructions used for
76alignment within code sections with multi-byte nop instructions such
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77as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78byte nop (0x90) is explicitly specified as the fill byte for alignment.
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79
80@cindex @samp{--divide} option, i386
81@item --divide
82On SVR4-derived platforms, the character @samp{/} is treated as a comment
83character, which means that it cannot be used in expressions. The
84@samp{--divide} option turns @samp{/} into a normal character. This does
85not disable @samp{/} at the beginning of a line starting a comment, or
86affect using @samp{#} for starting a comment.
87
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88@cindex @samp{-march=} option, i386
89@cindex @samp{-march=} option, x86-64
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90@item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91This option specifies the target processor. The assembler will
92issue an error message if an attempt is made to assemble an instruction
93which will not execute on the target processor. The following
34bca508 94processor names are recognized:
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95@code{i8086},
96@code{i186},
97@code{i286},
98@code{i386},
99@code{i486},
100@code{i586},
101@code{i686},
102@code{pentium},
103@code{pentiumpro},
104@code{pentiumii},
105@code{pentiumiii},
106@code{pentium4},
107@code{prescott},
108@code{nocona},
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109@code{core},
110@code{core2},
bd5295b2 111@code{corei7},
8a9036a4 112@code{l1om},
7a9068fe 113@code{k1om},
81486035 114@code{iamcu},
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115@code{k6},
116@code{k6_2},
117@code{athlon},
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118@code{opteron},
119@code{k8},
1ceab344 120@code{amdfam10},
68339fdf 121@code{bdver1},
af2f724e 122@code{bdver2},
5e5c50d3 123@code{bdver3},
c7b0bd56 124@code{bdver4},
029f3522 125@code{znver1},
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126@code{btver1},
127@code{btver2},
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128@code{generic32} and
129@code{generic64}.
130
34bca508 131In addition to the basic instruction set, the assembler can be told to
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132accept various extension mnemonics. For example,
133@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
134@var{vmx}. The following extensions are currently supported:
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135@code{8087},
136@code{287},
137@code{387},
1848e567 138@code{687},
309d3373 139@code{no87},
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140@code{no287},
141@code{no387},
142@code{no687},
6305a203 143@code{mmx},
309d3373 144@code{nommx},
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145@code{sse},
146@code{sse2},
147@code{sse3},
148@code{ssse3},
149@code{sse4.1},
150@code{sse4.2},
151@code{sse4},
309d3373 152@code{nosse},
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153@code{nosse2},
154@code{nosse3},
155@code{nossse3},
156@code{nosse4.1},
157@code{nosse4.2},
158@code{nosse4},
c0f3af97 159@code{avx},
6c30d220 160@code{avx2},
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161@code{noavx},
162@code{noavx2},
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163@code{adx},
164@code{rdseed},
165@code{prfchw},
5c111e37 166@code{smap},
7e8b059b 167@code{mpx},
a0046408 168@code{sha},
8bc52696 169@code{rdpid},
6b40c462 170@code{ptwrite},
603555e5 171@code{cet},
48521003 172@code{gfni},
8dcf1fad 173@code{vaes},
ff1982d5 174@code{vpclmulqdq},
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175@code{prefetchwt1},
176@code{clflushopt},
177@code{se1},
c5e7287a 178@code{clwb},
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179@code{avx512f},
180@code{avx512cd},
181@code{avx512er},
182@code{avx512pf},
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183@code{avx512vl},
184@code{avx512bw},
185@code{avx512dq},
2cc1b5aa 186@code{avx512ifma},
14f195c9 187@code{avx512vbmi},
920d2ddc 188@code{avx512_4fmaps},
47acf0bd 189@code{avx512_4vnniw},
620214f7 190@code{avx512_vpopcntdq},
53467f57 191@code{avx512_vbmi2},
8cfcb765 192@code{avx512_vnni},
ee6872be 193@code{avx512_bitalg},
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194@code{noavx512f},
195@code{noavx512cd},
196@code{noavx512er},
197@code{noavx512pf},
198@code{noavx512vl},
199@code{noavx512bw},
200@code{noavx512dq},
201@code{noavx512ifma},
202@code{noavx512vbmi},
920d2ddc 203@code{noavx512_4fmaps},
47acf0bd 204@code{noavx512_4vnniw},
620214f7 205@code{noavx512_vpopcntdq},
53467f57 206@code{noavx512_vbmi2},
8cfcb765 207@code{noavx512_vnni},
ee6872be 208@code{noavx512_bitalg},
6305a203 209@code{vmx},
8729a6f6 210@code{vmfunc},
6305a203 211@code{smx},
f03fe4c1 212@code{xsave},
c7b8aa3a 213@code{xsaveopt},
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214@code{xsavec},
215@code{xsaves},
c0f3af97 216@code{aes},
594ab6a3 217@code{pclmul},
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218@code{fsgsbase},
219@code{rdrnd},
220@code{f16c},
6c30d220 221@code{bmi2},
c0f3af97 222@code{fma},
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223@code{movbe},
224@code{ept},
6c30d220 225@code{lzcnt},
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226@code{hle},
227@code{rtm},
6c30d220 228@code{invpcid},
bd5295b2 229@code{clflush},
9916071f 230@code{mwaitx},
029f3522 231@code{clzero},
3233d7d0 232@code{wbnoinvd},
be3a8dca 233@code{pconfig},
f88c9eb0 234@code{lwp},
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235@code{fma4},
236@code{xop},
60aa667e 237@code{cx16},
bd5295b2 238@code{syscall},
1b7f3fb0 239@code{rdtscp},
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240@code{3dnow},
241@code{3dnowa},
242@code{sse4a},
243@code{sse5},
244@code{svme},
245@code{abm} and
246@code{padlock}.
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247Note that rather than extending a basic instruction set, the extension
248mnemonics starting with @code{no} revoke the respective functionality.
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249
250When the @code{.arch} directive is used with @option{-march}, the
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251@code{.arch} directive will take precedent.
252
253@cindex @samp{-mtune=} option, i386
254@cindex @samp{-mtune=} option, x86-64
255@item -mtune=@var{CPU}
256This option specifies a processor to optimize for. When used in
257conjunction with the @option{-march} option, only instructions
258of the processor specified by the @option{-march} option will be
259generated.
260
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261Valid @var{CPU} values are identical to the processor list of
262@option{-march=@var{CPU}}.
9103f4f4 263
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264@cindex @samp{-msse2avx} option, i386
265@cindex @samp{-msse2avx} option, x86-64
266@item -msse2avx
267This option specifies that the assembler should encode SSE instructions
268with VEX prefix.
269
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270@cindex @samp{-msse-check=} option, i386
271@cindex @samp{-msse-check=} option, x86-64
272@item -msse-check=@var{none}
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273@itemx -msse-check=@var{warning}
274@itemx -msse-check=@var{error}
9aff4b7a 275These options control if the assembler should check SSE instructions.
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276@option{-msse-check=@var{none}} will make the assembler not to check SSE
277instructions, which is the default. @option{-msse-check=@var{warning}}
9aff4b7a 278will make the assembler issue a warning for any SSE instruction.
daf50ae7 279@option{-msse-check=@var{error}} will make the assembler issue an error
9aff4b7a 280for any SSE instruction.
daf50ae7 281
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282@cindex @samp{-mavxscalar=} option, i386
283@cindex @samp{-mavxscalar=} option, x86-64
284@item -mavxscalar=@var{128}
1f9bb1ca 285@itemx -mavxscalar=@var{256}
2aab8acd 286These options control how the assembler should encode scalar AVX
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287instructions. @option{-mavxscalar=@var{128}} will encode scalar
288AVX instructions with 128bit vector length, which is the default.
289@option{-mavxscalar=@var{256}} will encode scalar AVX instructions
290with 256bit vector length.
291
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292@cindex @samp{-mevexlig=} option, i386
293@cindex @samp{-mevexlig=} option, x86-64
294@item -mevexlig=@var{128}
295@itemx -mevexlig=@var{256}
296@itemx -mevexlig=@var{512}
297These options control how the assembler should encode length-ignored
298(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
299EVEX instructions with 128bit vector length, which is the default.
300@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
301encode LIG EVEX instructions with 256bit and 512bit vector length,
302respectively.
303
304@cindex @samp{-mevexwig=} option, i386
305@cindex @samp{-mevexwig=} option, x86-64
306@item -mevexwig=@var{0}
307@itemx -mevexwig=@var{1}
308These options control how the assembler should encode w-ignored (WIG)
309EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
310EVEX instructions with evex.w = 0, which is the default.
311@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
312evex.w = 1.
313
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314@cindex @samp{-mmnemonic=} option, i386
315@cindex @samp{-mmnemonic=} option, x86-64
316@item -mmnemonic=@var{att}
1f9bb1ca 317@itemx -mmnemonic=@var{intel}
34bca508 318This option specifies instruction mnemonic for matching instructions.
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319The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
320take precedent.
321
322@cindex @samp{-msyntax=} option, i386
323@cindex @samp{-msyntax=} option, x86-64
324@item -msyntax=@var{att}
1f9bb1ca 325@itemx -msyntax=@var{intel}
34bca508 326This option specifies instruction syntax when processing instructions.
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327The @code{.att_syntax} and @code{.intel_syntax} directives will
328take precedent.
329
330@cindex @samp{-mnaked-reg} option, i386
331@cindex @samp{-mnaked-reg} option, x86-64
332@item -mnaked-reg
33eaf5de 333This option specifies that registers don't require a @samp{%} prefix.
e1d4d893 334The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
1efbbeb4 335
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336@cindex @samp{-madd-bnd-prefix} option, i386
337@cindex @samp{-madd-bnd-prefix} option, x86-64
338@item -madd-bnd-prefix
339This option forces the assembler to add BND prefix to all branches, even
340if such prefix was not explicitly specified in the source code.
341
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342@cindex @samp{-mshared} option, i386
343@cindex @samp{-mshared} option, x86-64
344@item -mno-shared
345On ELF target, the assembler normally optimizes out non-PLT relocations
346against defined non-weak global branch targets with default visibility.
347The @samp{-mshared} option tells the assembler to generate code which
348may go into a shared library where all non-weak global branch targets
349with default visibility can be preempted. The resulting code is
350slightly bigger. This option only affects the handling of branch
351instructions.
352
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353@cindex @samp{-mbig-obj} option, x86-64
354@item -mbig-obj
355On x86-64 PE/COFF target this option forces the use of big object file
356format, which allows more than 32768 sections.
357
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358@cindex @samp{-momit-lock-prefix=} option, i386
359@cindex @samp{-momit-lock-prefix=} option, x86-64
360@item -momit-lock-prefix=@var{no}
361@itemx -momit-lock-prefix=@var{yes}
362These options control how the assembler should encode lock prefix.
363This option is intended as a workaround for processors, that fail on
364lock prefix. This option can only be safely used with single-core,
365single-thread computers
366@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
367@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
368which is the default.
369
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370@cindex @samp{-mfence-as-lock-add=} option, i386
371@cindex @samp{-mfence-as-lock-add=} option, x86-64
372@item -mfence-as-lock-add=@var{no}
373@itemx -mfence-as-lock-add=@var{yes}
374These options control how the assembler should encode lfence, mfence and
375sfence.
376@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
377sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
378@samp{lock addl $0x0, (%esp)} in 32-bit mode.
379@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
380sfence as usual, which is the default.
381
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382@cindex @samp{-mrelax-relocations=} option, i386
383@cindex @samp{-mrelax-relocations=} option, x86-64
384@item -mrelax-relocations=@var{no}
385@itemx -mrelax-relocations=@var{yes}
386These options control whether the assembler should generate relax
387relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
388R_X86_64_REX_GOTPCRELX, in 64-bit mode.
389@option{-mrelax-relocations=@var{yes}} will generate relax relocations.
390@option{-mrelax-relocations=@var{no}} will not generate relax
391relocations. The default can be controlled by a configure option
392@option{--enable-x86-relax-relocations}.
393
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394@cindex @samp{-mevexrcig=} option, i386
395@cindex @samp{-mevexrcig=} option, x86-64
396@item -mevexrcig=@var{rne}
397@itemx -mevexrcig=@var{rd}
398@itemx -mevexrcig=@var{ru}
399@itemx -mevexrcig=@var{rz}
400These options control how the assembler should encode SAE-only
401EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
402of EVEX instruction with 00, which is the default.
403@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
404and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
405with 01, 10 and 11 RC bits, respectively.
406
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407@cindex @samp{-mamd64} option, x86-64
408@cindex @samp{-mintel64} option, x86-64
409@item -mamd64
410@itemx -mintel64
411This option specifies that the assembler should accept only AMD64 or
412Intel64 ISA in 64-bit mode. The default is to accept both.
413
55b62671 414@end table
731caf76 415@c man end
e413e4e9 416
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417@node i386-Directives
418@section x86 specific Directives
419
420@cindex machine directives, x86
421@cindex x86 machine directives
422@table @code
423
424@cindex @code{lcomm} directive, COFF
425@item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
426Reserve @var{length} (an absolute expression) bytes for a local common
427denoted by @var{symbol}. The section and value of @var{symbol} are
428those of the new local common. The addresses are allocated in the bss
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429section, so that at run-time the bytes start off zeroed. Since
430@var{symbol} is not declared global, it is normally not visible to
431@code{@value{LD}}. The optional third parameter, @var{alignment},
432specifies the desired alignment of the symbol in the bss section.
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433
434This directive is only available for COFF based x86 targets.
435
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436@cindex @code{largecomm} directive, ELF
437@item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
438This directive behaves in the same way as the @code{comm} directive
439except that the data is placed into the @var{.lbss} section instead of
440the @var{.bss} section @ref{Comm}.
441
442The directive is intended to be used for data which requires a large
443amount of space, and it is only available for ELF based x86_64
444targets.
445
a6c24e68 446@c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
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447
448@end table
449
252b5132 450@node i386-Syntax
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451@section i386 Syntactical Considerations
452@menu
453* i386-Variations:: AT&T Syntax versus Intel Syntax
454* i386-Chars:: Special Characters
455@end menu
456
457@node i386-Variations
458@subsection AT&T Syntax versus Intel Syntax
252b5132 459
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460@cindex i386 intel_syntax pseudo op
461@cindex intel_syntax pseudo op, i386
462@cindex i386 att_syntax pseudo op
463@cindex att_syntax pseudo op, i386
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464@cindex i386 syntax compatibility
465@cindex syntax compatibility, i386
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466@cindex x86-64 intel_syntax pseudo op
467@cindex intel_syntax pseudo op, x86-64
468@cindex x86-64 att_syntax pseudo op
469@cindex att_syntax pseudo op, x86-64
470@cindex x86-64 syntax compatibility
471@cindex syntax compatibility, x86-64
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472
473@code{@value{AS}} now supports assembly using Intel assembler syntax.
474@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
475back to the usual AT&T mode for compatibility with the output of
476@code{@value{GCC}}. Either of these directives may have an optional
477argument, @code{prefix}, or @code{noprefix} specifying whether registers
478require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
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479different from Intel syntax. We mention these differences because
480almost all 80386 documents use Intel syntax. Notable differences
481between the two syntaxes are:
482
483@cindex immediate operands, i386
484@cindex i386 immediate operands
485@cindex register operands, i386
486@cindex i386 register operands
487@cindex jump/call operands, i386
488@cindex i386 jump/call operands
489@cindex operand delimiters, i386
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490
491@cindex immediate operands, x86-64
492@cindex x86-64 immediate operands
493@cindex register operands, x86-64
494@cindex x86-64 register operands
495@cindex jump/call operands, x86-64
496@cindex x86-64 jump/call operands
497@cindex operand delimiters, x86-64
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498@itemize @bullet
499@item
500AT&T immediate operands are preceded by @samp{$}; Intel immediate
501operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
502AT&T register operands are preceded by @samp{%}; Intel register operands
503are undelimited. AT&T absolute (as opposed to PC relative) jump/call
504operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
505
506@cindex i386 source, destination operands
507@cindex source, destination operands; i386
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508@cindex x86-64 source, destination operands
509@cindex source, destination operands; x86-64
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510@item
511AT&T and Intel syntax use the opposite order for source and destination
512operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
513@samp{source, dest} convention is maintained for compatibility with
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514previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
515instructions with 2 immediate operands, such as the @samp{enter}
516instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
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517
518@cindex mnemonic suffixes, i386
519@cindex sizes operands, i386
520@cindex i386 size suffixes
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521@cindex mnemonic suffixes, x86-64
522@cindex sizes operands, x86-64
523@cindex x86-64 size suffixes
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524@item
525In AT&T syntax the size of memory operands is determined from the last
526character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
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527@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
528(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
529this by prefixing memory operands (@emph{not} the instruction mnemonics) with
530@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
531Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
532syntax.
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534In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
535instruction with the 64-bit displacement or immediate operand.
536
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537@cindex return instructions, i386
538@cindex i386 jump, call, return
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539@cindex return instructions, x86-64
540@cindex x86-64 jump, call, return
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541@item
542Immediate form long jumps and calls are
543@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
544Intel syntax is
545@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
546instruction
547is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
548@samp{ret far @var{stack-adjust}}.
549
550@cindex sections, i386
551@cindex i386 sections
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552@cindex sections, x86-64
553@cindex x86-64 sections
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554@item
555The AT&T assembler does not provide support for multiple section
556programs. Unix style systems expect all programs to be single sections.
557@end itemize
558
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559@node i386-Chars
560@subsection Special Characters
561
562@cindex line comment character, i386
563@cindex i386 line comment character
564The presence of a @samp{#} appearing anywhere on a line indicates the
565start of a comment that extends to the end of that line.
566
567If a @samp{#} appears as the first character of a line then the whole
568line is treated as a comment, but in this case the line can also be a
569logical line number directive (@pxref{Comments}) or a preprocessor
570control command (@pxref{Preprocessing}).
571
572If the @option{--divide} command line option has not been specified
573then the @samp{/} character appearing anywhere on a line also
574introduces a line comment.
575
576@cindex line separator, i386
577@cindex statement separator, i386
578@cindex i386 line separator
579The @samp{;} character can be used to separate statements on the same
580line.
581
252b5132 582@node i386-Mnemonics
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583@section i386-Mnemonics
584@subsection Instruction Naming
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585
586@cindex i386 instruction naming
587@cindex instruction naming, i386
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588@cindex x86-64 instruction naming
589@cindex instruction naming, x86-64
590
252b5132 591Instruction mnemonics are suffixed with one character modifiers which
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592specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
593and @samp{q} specify byte, word, long and quadruple word operands. If
594no suffix is specified by an instruction then @code{@value{AS}} tries to
595fill in the missing suffix based on the destination register operand
596(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
597to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
598@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
599assembler which assumes that a missing mnemonic suffix implies long
600operand size. (This incompatibility does not affect compiler output
601since compilers always explicitly specify the mnemonic suffix.)
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602
603Almost all instructions have the same names in AT&T and Intel format.
604There are a few exceptions. The sign extend and zero extend
605instructions need two sizes to specify them. They need a size to
606sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
607is accomplished by using two instruction mnemonic suffixes in AT&T
608syntax. Base names for sign extend and zero extend are
609@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
610and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
611are tacked on to this base name, the @emph{from} suffix before the
612@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
613``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
614thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
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615@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
616@samp{wq} (from word to quadruple word), and @samp{lq} (from long to
617quadruple word).
252b5132 618
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619@cindex encoding options, i386
620@cindex encoding options, x86-64
621
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622Different encoding options can be specified via pseudo prefixes:
623
624@itemize @bullet
625@item
626@samp{@{disp8@}} -- prefer 8-bit displacement.
627
628@item
629@samp{@{disp32@}} -- prefer 32-bit displacement.
630
631@item
632@samp{@{load@}} -- prefer load-form instruction.
633
634@item
635@samp{@{store@}} -- prefer store-form instruction.
636
637@item
638@samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
639
640@item
641@samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
642
643@item
644@samp{@{evex@}} -- encode with EVEX prefix.
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645
646@item
647@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
648instructions (x86-64 only). Note that this differs from the @samp{rex}
649prefix which generates REX prefix unconditionally.
86fa6981 650@end itemize
b6169b20 651
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652@cindex conversion instructions, i386
653@cindex i386 conversion instructions
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654@cindex conversion instructions, x86-64
655@cindex x86-64 conversion instructions
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656The Intel-syntax conversion instructions
657
658@itemize @bullet
659@item
660@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
661
662@item
663@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
664
665@item
666@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
667
668@item
669@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
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670
671@item
672@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
673(x86-64 only),
674
675@item
d5f0cf92 676@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
55b62671 677@samp{%rdx:%rax} (x86-64 only),
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678@end itemize
679
680@noindent
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681are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
682@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
683instructions.
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684
685@cindex jump instructions, i386
686@cindex call instructions, i386
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687@cindex jump instructions, x86-64
688@cindex call instructions, x86-64
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689Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
690AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
691convention.
692
d3b47e2b 693@subsection AT&T Mnemonic versus Intel Mnemonic
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694
695@cindex i386 mnemonic compatibility
696@cindex mnemonic compatibility, i386
697
698@code{@value{AS}} supports assembly using Intel mnemonic.
699@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
700@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
701syntax for compatibility with the output of @code{@value{GCC}}.
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702Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
703@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
704@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
705assembler with different mnemonics from those in Intel IA32 specification.
706@code{@value{GCC}} generates those instructions with AT&T mnemonic.
707
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708@node i386-Regs
709@section Register Naming
710
711@cindex i386 registers
712@cindex registers, i386
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713@cindex x86-64 registers
714@cindex registers, x86-64
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715Register operands are always prefixed with @samp{%}. The 80386 registers
716consist of
717
718@itemize @bullet
719@item
720the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
721@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
722frame pointer), and @samp{%esp} (the stack pointer).
723
724@item
725the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
726@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
727
728@item
729the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
730@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
731are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
732@samp{%cx}, and @samp{%dx})
733
734@item
735the 6 section registers @samp{%cs} (code section), @samp{%ds}
736(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
737and @samp{%gs}.
738
739@item
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740the 5 processor control registers @samp{%cr0}, @samp{%cr2},
741@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
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742
743@item
744the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
745@samp{%db3}, @samp{%db6}, and @samp{%db7}.
746
747@item
748the 2 test registers @samp{%tr6} and @samp{%tr7}.
749
750@item
751the 8 floating point register stack @samp{%st} or equivalently
752@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
753@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
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754These registers are overloaded by 8 MMX registers @samp{%mm0},
755@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
756@samp{%mm6} and @samp{%mm7}.
757
758@item
4bde3cdd 759the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
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760@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
761@end itemize
762
763The AMD x86-64 architecture extends the register set by:
764
765@itemize @bullet
766@item
767enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
768accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
769@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
770pointer)
771
772@item
773the 8 extended registers @samp{%r8}--@samp{%r15}.
774
775@item
4bde3cdd 776the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
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777
778@item
4bde3cdd 779the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
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780
781@item
4bde3cdd 782the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
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783
784@item
785the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
786
787@item
788the 8 debug registers: @samp{%db8}--@samp{%db15}.
789
790@item
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791the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
792@end itemize
793
794With the AVX extensions more registers were made available:
795
796@itemize @bullet
797
798@item
799the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
800available in 32-bit mode). The bottom 128 bits are overlaid with the
801@samp{xmm0}--@samp{xmm15} registers.
802
803@end itemize
804
805The AVX2 extensions made in 64-bit mode more registers available:
806
807@itemize @bullet
808
809@item
810the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
811registers @samp{%ymm16}--@samp{%ymm31}.
812
813@end itemize
814
815The AVX512 extensions added the following registers:
816
817@itemize @bullet
818
819@item
820the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
821available in 32-bit mode). The bottom 128 bits are overlaid with the
822@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
823overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
824
825@item
826the 8 mask registers @samp{%k0}--@samp{%k7}.
827
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828@end itemize
829
830@node i386-Prefixes
831@section Instruction Prefixes
832
833@cindex i386 instruction prefixes
834@cindex instruction prefixes, i386
835@cindex prefixes, i386
836Instruction prefixes are used to modify the following instruction. They
837are used to repeat string instructions, to provide section overrides, to
838perform bus lock operations, and to change operand and address sizes.
839(Most instructions that normally operate on 32-bit operands will use
84016-bit operands if the instruction has an ``operand size'' prefix.)
841Instruction prefixes are best written on the same line as the instruction
842they act upon. For example, the @samp{scas} (scan string) instruction is
843repeated with:
844
845@smallexample
846 repne scas %es:(%edi),%al
847@end smallexample
848
849You may also place prefixes on the lines immediately preceding the
850instruction, but this circumvents checks that @code{@value{AS}} does
851with prefixes, and will not work with all prefixes.
852
853Here is a list of instruction prefixes:
854
855@cindex section override prefixes, i386
856@itemize @bullet
857@item
858Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
859@samp{fs}, @samp{gs}. These are automatically added by specifying
860using the @var{section}:@var{memory-operand} form for memory references.
861
862@cindex size prefixes, i386
863@item
864Operand/Address size prefixes @samp{data16} and @samp{addr16}
865change 32-bit operands/addresses into 16-bit operands/addresses,
866while @samp{data32} and @samp{addr32} change 16-bit ones (in a
867@code{.code16} section) into 32-bit operands/addresses. These prefixes
868@emph{must} appear on the same line of code as the instruction they
869modify. For example, in a 16-bit @code{.code16} section, you might
870write:
871
872@smallexample
873 addr32 jmpl *(%ebx)
874@end smallexample
875
876@cindex bus lock prefixes, i386
877@cindex inhibiting interrupts, i386
878@item
879The bus lock prefix @samp{lock} inhibits interrupts during execution of
880the instruction it precedes. (This is only valid with certain
881instructions; see a 80386 manual for details).
882
883@cindex coprocessor wait, i386
884@item
885The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
886complete the current instruction. This should never be needed for the
88780386/80387 combination.
888
889@cindex repeat prefixes, i386
890@item
891The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
892to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
893times if the current address size is 16-bits).
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894@cindex REX prefixes, i386
895@item
896The @samp{rex} family of prefixes is used by x86-64 to encode
897extensions to i386 instruction set. The @samp{rex} prefix has four
898bits --- an operand size overwrite (@code{64}) used to change operand size
899from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
900register set.
901
902You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
903instruction emits @samp{rex} prefix with all the bits set. By omitting
904the @code{64}, @code{x}, @code{y} or @code{z} you may write other
905prefixes as well. Normally, there is no need to write the prefixes
906explicitly, since gas will automatically generate them based on the
907instruction operands.
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908@end itemize
909
910@node i386-Memory
911@section Memory References
912
913@cindex i386 memory references
914@cindex memory references, i386
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915@cindex x86-64 memory references
916@cindex memory references, x86-64
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917An Intel syntax indirect memory reference of the form
918
919@smallexample
920@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
921@end smallexample
922
923@noindent
924is translated into the AT&T syntax
925
926@smallexample
927@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
928@end smallexample
929
930@noindent
931where @var{base} and @var{index} are the optional 32-bit base and
932index registers, @var{disp} is the optional displacement, and
933@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
934to calculate the address of the operand. If no @var{scale} is
935specified, @var{scale} is taken to be 1. @var{section} specifies the
936optional section register for the memory operand, and may override the
937default section register (see a 80386 manual for section register
938defaults). Note that section overrides in AT&T syntax @emph{must}
939be preceded by a @samp{%}. If you specify a section override which
940coincides with the default section register, @code{@value{AS}} does @emph{not}
941output any section register override prefixes to assemble the given
942instruction. Thus, section overrides can be specified to emphasize which
943section register is used for a given memory operand.
944
945Here are some examples of Intel and AT&T style memory references:
946
947@table @asis
948@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
949@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
950missing, and the default section is used (@samp{%ss} for addressing with
951@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
952
953@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
954@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
955@samp{foo}. All other fields are missing. The section register here
956defaults to @samp{%ds}.
957
958@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
959This uses the value pointed to by @samp{foo} as a memory operand.
960Note that @var{base} and @var{index} are both missing, but there is only
961@emph{one} @samp{,}. This is a syntactic exception.
962
963@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
964This selects the contents of the variable @samp{foo} with section
965register @var{section} being @samp{%gs}.
966@end table
967
968Absolute (as opposed to PC relative) call and jump operands must be
969prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
970always chooses PC relative addressing for jump/call labels.
971
972Any instruction that has a memory operand, but no register operand,
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973@emph{must} specify its size (byte, word, long, or quadruple) with an
974instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
975respectively).
976
977The x86-64 architecture adds an RIP (instruction pointer relative)
978addressing. This addressing mode is specified by using @samp{rip} as a
979base register. Only constant offsets are valid. For example:
980
981@table @asis
982@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
983Points to the address 1234 bytes past the end of the current
984instruction.
985
986@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
987Points to the @code{symbol} in RIP relative way, this is shorter than
988the default absolute addressing.
989@end table
990
991Other addressing modes remain unchanged in x86-64 architecture, except
992registers used are 64-bit instead of 32-bit.
252b5132 993
fddf5b5b 994@node i386-Jumps
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995@section Handling of Jump Instructions
996
997@cindex jump optimization, i386
998@cindex i386 jump optimization
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999@cindex jump optimization, x86-64
1000@cindex x86-64 jump optimization
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1001Jump instructions are always optimized to use the smallest possible
1002displacements. This is accomplished by using byte (8-bit) displacement
1003jumps whenever the target is sufficiently close. If a byte displacement
fddf5b5b 1004is insufficient a long displacement is used. We do not support
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1005word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1006instruction with the @samp{data16} instruction prefix), since the 80386
1007insists upon masking @samp{%eip} to 16 bits after the word displacement
fddf5b5b 1008is added. (See also @pxref{i386-Arch})
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1009
1010Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1011@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1012displacements, so that if you use these instructions (@code{@value{GCC}} does
1013not use them) you may get an error message (and incorrect code). The AT&T
101480386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1015to
1016
1017@smallexample
1018 jcxz cx_zero
1019 jmp cx_nonzero
1020cx_zero: jmp foo
1021cx_nonzero:
1022@end smallexample
1023
1024@node i386-Float
1025@section Floating Point
1026
1027@cindex i386 floating point
1028@cindex floating point, i386
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1029@cindex x86-64 floating point
1030@cindex floating point, x86-64
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1031All 80387 floating point types except packed BCD are supported.
1032(BCD support may be added without much difficulty). These data
1033types are 16-, 32-, and 64- bit integers, and single (32-bit),
1034double (64-bit), and extended (80-bit) precision floating point.
1035Each supported type has an instruction mnemonic suffix and a constructor
1036associated with it. Instruction mnemonic suffixes specify the operand's
1037data type. Constructors build these data types into memory.
1038
1039@cindex @code{float} directive, i386
1040@cindex @code{single} directive, i386
1041@cindex @code{double} directive, i386
1042@cindex @code{tfloat} directive, i386
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AJ
1043@cindex @code{float} directive, x86-64
1044@cindex @code{single} directive, x86-64
1045@cindex @code{double} directive, x86-64
1046@cindex @code{tfloat} directive, x86-64
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RH
1047@itemize @bullet
1048@item
1049Floating point constructors are @samp{.float} or @samp{.single},
1050@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1051These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1052and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1053only supports this format via the @samp{fldt} (load 80-bit real to stack
1054top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1055
1056@cindex @code{word} directive, i386
1057@cindex @code{long} directive, i386
1058@cindex @code{int} directive, i386
1059@cindex @code{quad} directive, i386
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1060@cindex @code{word} directive, x86-64
1061@cindex @code{long} directive, x86-64
1062@cindex @code{int} directive, x86-64
1063@cindex @code{quad} directive, x86-64
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RH
1064@item
1065Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1066@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1067corresponding instruction mnemonic suffixes are @samp{s} (single),
1068@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1069the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1070quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1071stack) instructions.
1072@end itemize
1073
1074Register to register operations should not use instruction mnemonic suffixes.
1075@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1076wrote @samp{fst %st, %st(1)}, since all register to register operations
1077use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1078which converts @samp{%st} from 80-bit to 64-bit floating point format,
1079then stores the result in the 4 byte location @samp{mem})
1080
1081@node i386-SIMD
1082@section Intel's MMX and AMD's 3DNow! SIMD Operations
1083
1084@cindex MMX, i386
1085@cindex 3DNow!, i386
1086@cindex SIMD, i386
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1087@cindex MMX, x86-64
1088@cindex 3DNow!, x86-64
1089@cindex SIMD, x86-64
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RH
1090
1091@code{@value{AS}} supports Intel's MMX instruction set (SIMD
1092instructions for integer data), available on Intel's Pentium MMX
1093processors and Pentium II processors, AMD's K6 and K6-2 processors,
b45619c0 1094Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
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RH
1095instruction set (SIMD instructions for 32-bit floating point data)
1096available on AMD's K6-2 processor and possibly others in the future.
1097
1098Currently, @code{@value{AS}} does not support Intel's floating point
1099SIMD, Katmai (KNI).
1100
1101The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1102@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
110316-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1104floating point values. The MMX registers cannot be used at the same time
1105as the floating point stack.
1106
1107See Intel and AMD documentation, keeping in mind that the operand order in
1108instructions is reversed from the Intel syntax.
1109
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SP
1110@node i386-LWP
1111@section AMD's Lightweight Profiling Instructions
1112
1113@cindex LWP, i386
1114@cindex LWP, x86-64
1115
1116@code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1117instruction set, available on AMD's Family 15h (Orochi) processors.
1118
1119LWP enables applications to collect and manage performance data, and
1120react to performance events. The collection of performance data
1121requires no context switches. LWP runs in the context of a thread and
1122so several counters can be used independently across multiple threads.
1123LWP can be used in both 64-bit and legacy 32-bit modes.
1124
1125For detailed information on the LWP instruction set, see the
1126@cite{AMD Lightweight Profiling Specification} available at
1127@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1128
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1129@node i386-BMI
1130@section Bit Manipulation Instructions
1131
1132@cindex BMI, i386
1133@cindex BMI, x86-64
1134
1135@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1136
1137BMI instructions provide several instructions implementing individual
1138bit manipulation operations such as isolation, masking, setting, or
34bca508 1139resetting.
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QN
1140
1141@c Need to add a specification citation here when available.
1142
2a2a0f38
QN
1143@node i386-TBM
1144@section AMD's Trailing Bit Manipulation Instructions
1145
1146@cindex TBM, i386
1147@cindex TBM, x86-64
1148
1149@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1150instruction set, available on AMD's BDVER2 processors (Trinity and
1151Viperfish).
1152
1153TBM instructions provide instructions implementing individual bit
1154manipulation operations such as isolating, masking, setting, resetting,
1155complementing, and operations on trailing zeros and ones.
1156
1157@c Need to add a specification citation here when available.
87973e9f 1158
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RH
1159@node i386-16bit
1160@section Writing 16-bit Code
1161
1162@cindex i386 16-bit code
1163@cindex 16-bit code, i386
1164@cindex real-mode code, i386
eecb386c 1165@cindex @code{code16gcc} directive, i386
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RH
1166@cindex @code{code16} directive, i386
1167@cindex @code{code32} directive, i386
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1168@cindex @code{code64} directive, i386
1169@cindex @code{code64} directive, x86-64
1170While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1171or 64-bit x86-64 code depending on the default configuration,
252b5132 1172it also supports writing code to run in real mode or in 16-bit protected
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1173mode code segments. To do this, put a @samp{.code16} or
1174@samp{.code16gcc} directive before the assembly language instructions to
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1175be run in 16-bit mode. You can switch @code{@value{AS}} to writing
117632-bit code with the @samp{.code32} directive or 64-bit code with the
1177@samp{.code64} directive.
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1178
1179@samp{.code16gcc} provides experimental support for generating 16-bit
1180code from gcc, and differs from @samp{.code16} in that @samp{call},
1181@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1182@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1183default to 32-bit size. This is so that the stack pointer is
1184manipulated in the same way over function calls, allowing access to
1185function parameters at the same stack offsets as in 32-bit mode.
1186@samp{.code16gcc} also automatically adds address size prefixes where
1187necessary to use the 32-bit addressing modes that gcc generates.
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1188
1189The code which @code{@value{AS}} generates in 16-bit mode will not
1190necessarily run on a 16-bit pre-80386 processor. To write code that
1191runs on such a processor, you must refrain from using @emph{any} 32-bit
1192constructs which require @code{@value{AS}} to output address or operand
1193size prefixes.
1194
1195Note that writing 16-bit code instructions by explicitly specifying a
1196prefix or an instruction mnemonic suffix within a 32-bit code section
1197generates different machine instructions than those generated for a
119816-bit code segment. In a 32-bit code section, the following code
1199generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1200value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1201
1202@smallexample
1203 pushw $4
1204@end smallexample
1205
1206The same code in a 16-bit code section would generate the machine
b45619c0 1207opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
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RH
1208is correct since the processor default operand size is assumed to be 16
1209bits in a 16-bit code section.
1210
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1211@node i386-Arch
1212@section Specifying CPU Architecture
1213
1214@cindex arch directive, i386
1215@cindex i386 arch directive
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1216@cindex arch directive, x86-64
1217@cindex x86-64 arch directive
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1218
1219@code{@value{AS}} may be told to assemble for a particular CPU
5c6af06e 1220(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
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1221directive enables a warning when gas detects an instruction that is not
1222supported on the CPU specified. The choices for @var{cpu_type} are:
1223
1224@multitable @columnfractions .20 .20 .20 .20
1225@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1226@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
5c6af06e 1227@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
ef05d495 1228@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
81486035 1229@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1543849b 1230@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
5e5c50d3 1231@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
029f3522 1232@item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1ceab344 1233@item @samp{generic32} @tab @samp{generic64}
9103f4f4 1234@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
d76f7bc1 1235@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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1236@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1237@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1238@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
6c30d220 1239@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
42164a71 1240@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
e2e1fcde 1241@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
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1242@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1243@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1244@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
2cc1b5aa 1245@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
47acf0bd 1246@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
8cfcb765 1247@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
ee6872be 1248@item @samp{.avx512_bitalg}
d777820b 1249@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
be3a8dca 1250@item @samp{.wbnoinvd} @tab @samp{.pconfig}
d777820b 1251@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1ceab344 1252@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
f72d7f29 1253@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
60aa667e 1254@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
d777820b 1255@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
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1256@end multitable
1257
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1258Apart from the warning, there are only two other effects on
1259@code{@value{AS}} operation; Firstly, if you specify a CPU other than
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1260@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1261will automatically use a two byte opcode sequence. The larger three
1262byte opcode sequence is used on the 486 (and when no architecture is
1263specified) because it executes faster on the 486. Note that you can
1264explicitly request the two byte opcode by writing @samp{sarl %eax}.
fddf5b5b
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1265Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1266@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1267conditional jumps will be promoted when necessary to a two instruction
1268sequence consisting of a conditional jump of the opposite sense around
1269an unconditional jump to the target.
1270
5c6af06e
JB
1271Following the CPU architecture (but not a sub-architecture, which are those
1272starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1273control automatic promotion of conditional jumps. @samp{jumps} is the
1274default, and enables jump promotion; All external jumps will be of the long
1275variety, and file-local jumps will be promoted as necessary.
1276(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1277byte offset jumps, and warns about file-local conditional jumps that
1278@code{@value{AS}} promotes.
fddf5b5b
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1279Unconditional jumps are treated as for @samp{jumps}.
1280
1281For example
1282
1283@smallexample
1284 .arch i8086,nojumps
1285@end smallexample
e413e4e9 1286
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1287@node i386-Bugs
1288@section AT&T Syntax bugs
1289
1290The UnixWare assembler, and probably other AT&T derived ix86 Unix
1291assemblers, generate floating point instructions with reversed source
1292and destination registers in certain cases. Unfortunately, gcc and
1293possibly many other programs use this reversed syntax, so we're stuck
1294with it.
1295
1296For example
1297
1298@smallexample
1299 fsub %st,%st(3)
1300@end smallexample
1301@noindent
1302results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1303than the expected @samp{%st(3) - %st}. This happens with all the
1304non-commutative arithmetic floating point operations with two register
1305operands where the source register is @samp{%st} and the destination
1306register is @samp{%st(i)}.
1307
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RH
1308@node i386-Notes
1309@section Notes
1310
1311@cindex i386 @code{mul}, @code{imul} instructions
1312@cindex @code{mul} instruction, i386
1313@cindex @code{imul} instruction, i386
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AJ
1314@cindex @code{mul} instruction, x86-64
1315@cindex @code{imul} instruction, x86-64
252b5132 1316There is some trickery concerning the @samp{mul} and @samp{imul}
55b62671 1317instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
252b5132
RH
1318multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1319for @samp{imul}) can be output only in the one operand form. Thus,
1320@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1321the expanding multiply would clobber the @samp{%edx} register, and this
1322would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
132364-bit product in @samp{%edx:%eax}.
1324
1325We have added a two operand form of @samp{imul} when the first operand
1326is an immediate mode expression and the second operand is a register.
1327This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1328example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1329$69, %eax, %eax}.
1330
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