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b3adc24a | 1 | @c Copyright (C) 1991-2020 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
731caf76 L |
4 | @c man end |
5 | ||
252b5132 RH |
6 | @ifset GENERIC |
7 | @page | |
8 | @node i386-Dependent | |
9 | @chapter 80386 Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter 80386 Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex i386 support | |
b6169b20 | 17 | @cindex i80386 support |
55b62671 AJ |
18 | @cindex x86-64 support |
19 | ||
20 | The i386 version @code{@value{AS}} supports both the original Intel 386 | |
21 | architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture | |
22 | extending the Intel architecture to 64-bits. | |
23 | ||
252b5132 RH |
24 | @menu |
25 | * i386-Options:: Options | |
a6c24e68 | 26 | * i386-Directives:: X86 specific directives |
7c31ae13 | 27 | * i386-Syntax:: Syntactical considerations |
252b5132 RH |
28 | * i386-Mnemonics:: Instruction Naming |
29 | * i386-Regs:: Register Naming | |
30 | * i386-Prefixes:: Instruction Prefixes | |
31 | * i386-Memory:: Memory References | |
fddf5b5b | 32 | * i386-Jumps:: Handling of Jump Instructions |
252b5132 RH |
33 | * i386-Float:: Floating Point |
34 | * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations | |
f88c9eb0 | 35 | * i386-LWP:: AMD's Lightweight Profiling Instructions |
87973e9f | 36 | * i386-BMI:: Bit Manipulation Instruction |
2a2a0f38 | 37 | * i386-TBM:: AMD's Trailing Bit Manipulation Instructions |
252b5132 | 38 | * i386-16bit:: Writing 16-bit Code |
e413e4e9 | 39 | * i386-Arch:: Specifying an x86 CPU architecture |
bc31405e | 40 | * i386-ISA:: AMD64 ISA vs. Intel64 ISA |
252b5132 RH |
41 | * i386-Bugs:: AT&T Syntax bugs |
42 | * i386-Notes:: Notes | |
43 | @end menu | |
44 | ||
45 | @node i386-Options | |
46 | @section Options | |
47 | ||
55b62671 AJ |
48 | @cindex options for i386 |
49 | @cindex options for x86-64 | |
50 | @cindex i386 options | |
34bca508 | 51 | @cindex x86-64 options |
55b62671 AJ |
52 | |
53 | The i386 version of @code{@value{AS}} has a few machine | |
54 | dependent options: | |
55 | ||
731caf76 L |
56 | @c man begin OPTIONS |
57 | @table @gcctabopt | |
55b62671 AJ |
58 | @cindex @samp{--32} option, i386 |
59 | @cindex @samp{--32} option, x86-64 | |
570561f7 L |
60 | @cindex @samp{--x32} option, i386 |
61 | @cindex @samp{--x32} option, x86-64 | |
55b62671 AJ |
62 | @cindex @samp{--64} option, i386 |
63 | @cindex @samp{--64} option, x86-64 | |
570561f7 | 64 | @item --32 | --x32 | --64 |
35cc6a0b | 65 | Select the word size, either 32 bits or 64 bits. @samp{--32} |
570561f7 | 66 | implies Intel i386 architecture, while @samp{--x32} and @samp{--64} |
35cc6a0b L |
67 | imply AMD x86-64 architecture with 32-bit or 64-bit word-size |
68 | respectively. | |
55b62671 AJ |
69 | |
70 | These options are only available with the ELF object file format, and | |
71 | require that the necessary BFD support has been included (on a 32-bit | |
72 | platform you have to add --enable-64-bit-bfd to configure enable 64-bit | |
73 | usage and use x86-64 as target platform). | |
12b55ccc L |
74 | |
75 | @item -n | |
76 | By default, x86 GAS replaces multiple nop instructions used for | |
77 | alignment within code sections with multi-byte nop instructions such | |
f9233288 JW |
78 | as leal 0(%esi,1),%esi. This switch disables the optimization if a single |
79 | byte nop (0x90) is explicitly specified as the fill byte for alignment. | |
b3b91714 AM |
80 | |
81 | @cindex @samp{--divide} option, i386 | |
82 | @item --divide | |
83 | On SVR4-derived platforms, the character @samp{/} is treated as a comment | |
84 | character, which means that it cannot be used in expressions. The | |
85 | @samp{--divide} option turns @samp{/} into a normal character. This does | |
86 | not disable @samp{/} at the beginning of a line starting a comment, or | |
87 | affect using @samp{#} for starting a comment. | |
88 | ||
9103f4f4 L |
89 | @cindex @samp{-march=} option, i386 |
90 | @cindex @samp{-march=} option, x86-64 | |
6305a203 L |
91 | @item -march=@var{CPU}[+@var{EXTENSION}@dots{}] |
92 | This option specifies the target processor. The assembler will | |
93 | issue an error message if an attempt is made to assemble an instruction | |
94 | which will not execute on the target processor. The following | |
34bca508 | 95 | processor names are recognized: |
9103f4f4 L |
96 | @code{i8086}, |
97 | @code{i186}, | |
98 | @code{i286}, | |
99 | @code{i386}, | |
100 | @code{i486}, | |
101 | @code{i586}, | |
102 | @code{i686}, | |
103 | @code{pentium}, | |
104 | @code{pentiumpro}, | |
105 | @code{pentiumii}, | |
106 | @code{pentiumiii}, | |
107 | @code{pentium4}, | |
108 | @code{prescott}, | |
109 | @code{nocona}, | |
ef05d495 L |
110 | @code{core}, |
111 | @code{core2}, | |
bd5295b2 | 112 | @code{corei7}, |
8a9036a4 | 113 | @code{l1om}, |
7a9068fe | 114 | @code{k1om}, |
81486035 | 115 | @code{iamcu}, |
9103f4f4 L |
116 | @code{k6}, |
117 | @code{k6_2}, | |
118 | @code{athlon}, | |
9103f4f4 L |
119 | @code{opteron}, |
120 | @code{k8}, | |
1ceab344 | 121 | @code{amdfam10}, |
68339fdf | 122 | @code{bdver1}, |
af2f724e | 123 | @code{bdver2}, |
5e5c50d3 | 124 | @code{bdver3}, |
c7b0bd56 | 125 | @code{bdver4}, |
029f3522 | 126 | @code{znver1}, |
a9660a6f | 127 | @code{znver2}, |
7b458c12 L |
128 | @code{btver1}, |
129 | @code{btver2}, | |
9103f4f4 L |
130 | @code{generic32} and |
131 | @code{generic64}. | |
132 | ||
34bca508 | 133 | In addition to the basic instruction set, the assembler can be told to |
6305a203 L |
134 | accept various extension mnemonics. For example, |
135 | @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and | |
136 | @var{vmx}. The following extensions are currently supported: | |
309d3373 JB |
137 | @code{8087}, |
138 | @code{287}, | |
139 | @code{387}, | |
1848e567 | 140 | @code{687}, |
309d3373 | 141 | @code{no87}, |
1848e567 L |
142 | @code{no287}, |
143 | @code{no387}, | |
144 | @code{no687}, | |
d871f3f4 L |
145 | @code{cmov}, |
146 | @code{nocmov}, | |
147 | @code{fxsr}, | |
148 | @code{nofxsr}, | |
6305a203 | 149 | @code{mmx}, |
309d3373 | 150 | @code{nommx}, |
6305a203 L |
151 | @code{sse}, |
152 | @code{sse2}, | |
153 | @code{sse3}, | |
af5c13b0 | 154 | @code{sse4a}, |
6305a203 L |
155 | @code{ssse3}, |
156 | @code{sse4.1}, | |
157 | @code{sse4.2}, | |
158 | @code{sse4}, | |
309d3373 | 159 | @code{nosse}, |
1848e567 L |
160 | @code{nosse2}, |
161 | @code{nosse3}, | |
af5c13b0 | 162 | @code{nosse4a}, |
1848e567 L |
163 | @code{nossse3}, |
164 | @code{nosse4.1}, | |
165 | @code{nosse4.2}, | |
166 | @code{nosse4}, | |
c0f3af97 | 167 | @code{avx}, |
6c30d220 | 168 | @code{avx2}, |
1848e567 L |
169 | @code{noavx}, |
170 | @code{noavx2}, | |
e2e1fcde L |
171 | @code{adx}, |
172 | @code{rdseed}, | |
173 | @code{prfchw}, | |
5c111e37 | 174 | @code{smap}, |
7e8b059b | 175 | @code{mpx}, |
a0046408 | 176 | @code{sha}, |
8bc52696 | 177 | @code{rdpid}, |
6b40c462 | 178 | @code{ptwrite}, |
603555e5 | 179 | @code{cet}, |
48521003 | 180 | @code{gfni}, |
8dcf1fad | 181 | @code{vaes}, |
ff1982d5 | 182 | @code{vpclmulqdq}, |
1dfc6506 L |
183 | @code{prefetchwt1}, |
184 | @code{clflushopt}, | |
185 | @code{se1}, | |
c5e7287a | 186 | @code{clwb}, |
c0a30a9f L |
187 | @code{movdiri}, |
188 | @code{movdir64b}, | |
5d79adc4 | 189 | @code{enqcmd}, |
4b27d27c | 190 | @code{serialize}, |
bb651e8b | 191 | @code{tsxldtrk}, |
43234a1e L |
192 | @code{avx512f}, |
193 | @code{avx512cd}, | |
194 | @code{avx512er}, | |
195 | @code{avx512pf}, | |
1dfc6506 L |
196 | @code{avx512vl}, |
197 | @code{avx512bw}, | |
198 | @code{avx512dq}, | |
2cc1b5aa | 199 | @code{avx512ifma}, |
14f195c9 | 200 | @code{avx512vbmi}, |
920d2ddc | 201 | @code{avx512_4fmaps}, |
47acf0bd | 202 | @code{avx512_4vnniw}, |
620214f7 | 203 | @code{avx512_vpopcntdq}, |
53467f57 | 204 | @code{avx512_vbmi2}, |
8cfcb765 | 205 | @code{avx512_vnni}, |
ee6872be | 206 | @code{avx512_bitalg}, |
d6aab7a1 | 207 | @code{avx512_bf16}, |
144b71e2 L |
208 | @code{noavx512f}, |
209 | @code{noavx512cd}, | |
210 | @code{noavx512er}, | |
211 | @code{noavx512pf}, | |
212 | @code{noavx512vl}, | |
213 | @code{noavx512bw}, | |
214 | @code{noavx512dq}, | |
215 | @code{noavx512ifma}, | |
216 | @code{noavx512vbmi}, | |
920d2ddc | 217 | @code{noavx512_4fmaps}, |
47acf0bd | 218 | @code{noavx512_4vnniw}, |
620214f7 | 219 | @code{noavx512_vpopcntdq}, |
53467f57 | 220 | @code{noavx512_vbmi2}, |
8cfcb765 | 221 | @code{noavx512_vnni}, |
ee6872be | 222 | @code{noavx512_bitalg}, |
9186c494 | 223 | @code{noavx512_vp2intersect}, |
d6aab7a1 | 224 | @code{noavx512_bf16}, |
dd455cf5 | 225 | @code{noenqcmd}, |
4b27d27c | 226 | @code{noserialize}, |
bb651e8b | 227 | @code{notsxldtrk}, |
6305a203 | 228 | @code{vmx}, |
8729a6f6 | 229 | @code{vmfunc}, |
6305a203 | 230 | @code{smx}, |
f03fe4c1 | 231 | @code{xsave}, |
c7b8aa3a | 232 | @code{xsaveopt}, |
1dfc6506 L |
233 | @code{xsavec}, |
234 | @code{xsaves}, | |
c0f3af97 | 235 | @code{aes}, |
594ab6a3 | 236 | @code{pclmul}, |
c7b8aa3a L |
237 | @code{fsgsbase}, |
238 | @code{rdrnd}, | |
239 | @code{f16c}, | |
6c30d220 | 240 | @code{bmi2}, |
c0f3af97 | 241 | @code{fma}, |
f1f8f695 L |
242 | @code{movbe}, |
243 | @code{ept}, | |
6c30d220 | 244 | @code{lzcnt}, |
272a84b1 | 245 | @code{popcnt}, |
42164a71 L |
246 | @code{hle}, |
247 | @code{rtm}, | |
6c30d220 | 248 | @code{invpcid}, |
bd5295b2 | 249 | @code{clflush}, |
9916071f | 250 | @code{mwaitx}, |
029f3522 | 251 | @code{clzero}, |
3233d7d0 | 252 | @code{wbnoinvd}, |
be3a8dca | 253 | @code{pconfig}, |
de89d0a3 | 254 | @code{waitpkg}, |
c48935d7 | 255 | @code{cldemote}, |
142861df JB |
256 | @code{rdpru}, |
257 | @code{mcommit}, | |
a847e322 | 258 | @code{sev_es}, |
f88c9eb0 | 259 | @code{lwp}, |
5dd85c99 SP |
260 | @code{fma4}, |
261 | @code{xop}, | |
60aa667e | 262 | @code{cx16}, |
bd5295b2 | 263 | @code{syscall}, |
1b7f3fb0 | 264 | @code{rdtscp}, |
6305a203 L |
265 | @code{3dnow}, |
266 | @code{3dnowa}, | |
267 | @code{sse4a}, | |
268 | @code{sse5}, | |
272a84b1 | 269 | @code{svme} and |
6305a203 | 270 | @code{padlock}. |
309d3373 JB |
271 | Note that rather than extending a basic instruction set, the extension |
272 | mnemonics starting with @code{no} revoke the respective functionality. | |
6305a203 L |
273 | |
274 | When the @code{.arch} directive is used with @option{-march}, the | |
9103f4f4 L |
275 | @code{.arch} directive will take precedent. |
276 | ||
277 | @cindex @samp{-mtune=} option, i386 | |
278 | @cindex @samp{-mtune=} option, x86-64 | |
279 | @item -mtune=@var{CPU} | |
280 | This option specifies a processor to optimize for. When used in | |
281 | conjunction with the @option{-march} option, only instructions | |
282 | of the processor specified by the @option{-march} option will be | |
283 | generated. | |
284 | ||
6305a203 L |
285 | Valid @var{CPU} values are identical to the processor list of |
286 | @option{-march=@var{CPU}}. | |
9103f4f4 | 287 | |
c0f3af97 L |
288 | @cindex @samp{-msse2avx} option, i386 |
289 | @cindex @samp{-msse2avx} option, x86-64 | |
290 | @item -msse2avx | |
291 | This option specifies that the assembler should encode SSE instructions | |
292 | with VEX prefix. | |
293 | ||
daf50ae7 L |
294 | @cindex @samp{-msse-check=} option, i386 |
295 | @cindex @samp{-msse-check=} option, x86-64 | |
296 | @item -msse-check=@var{none} | |
1f9bb1ca AS |
297 | @itemx -msse-check=@var{warning} |
298 | @itemx -msse-check=@var{error} | |
9aff4b7a | 299 | These options control if the assembler should check SSE instructions. |
daf50ae7 L |
300 | @option{-msse-check=@var{none}} will make the assembler not to check SSE |
301 | instructions, which is the default. @option{-msse-check=@var{warning}} | |
9aff4b7a | 302 | will make the assembler issue a warning for any SSE instruction. |
daf50ae7 | 303 | @option{-msse-check=@var{error}} will make the assembler issue an error |
9aff4b7a | 304 | for any SSE instruction. |
daf50ae7 | 305 | |
539f890d L |
306 | @cindex @samp{-mavxscalar=} option, i386 |
307 | @cindex @samp{-mavxscalar=} option, x86-64 | |
308 | @item -mavxscalar=@var{128} | |
1f9bb1ca | 309 | @itemx -mavxscalar=@var{256} |
2aab8acd | 310 | These options control how the assembler should encode scalar AVX |
539f890d L |
311 | instructions. @option{-mavxscalar=@var{128}} will encode scalar |
312 | AVX instructions with 128bit vector length, which is the default. | |
313 | @option{-mavxscalar=@var{256}} will encode scalar AVX instructions | |
314 | with 256bit vector length. | |
315 | ||
4970191f JB |
316 | WARNING: Don't use this for production code - due to CPU errata the |
317 | resulting code may not work on certain models. | |
318 | ||
03751133 L |
319 | @cindex @samp{-mvexwig=} option, i386 |
320 | @cindex @samp{-mvexwig=} option, x86-64 | |
321 | @item -mvexwig=@var{0} | |
322 | @itemx -mvexwig=@var{1} | |
323 | These options control how the assembler should encode VEX.W-ignored (WIG) | |
324 | VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX | |
325 | instructions with vex.w = 0, which is the default. | |
326 | @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with | |
327 | vex.w = 1. | |
328 | ||
4970191f JB |
329 | WARNING: Don't use this for production code - due to CPU errata the |
330 | resulting code may not work on certain models. | |
331 | ||
43234a1e L |
332 | @cindex @samp{-mevexlig=} option, i386 |
333 | @cindex @samp{-mevexlig=} option, x86-64 | |
334 | @item -mevexlig=@var{128} | |
335 | @itemx -mevexlig=@var{256} | |
336 | @itemx -mevexlig=@var{512} | |
337 | These options control how the assembler should encode length-ignored | |
338 | (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG | |
339 | EVEX instructions with 128bit vector length, which is the default. | |
340 | @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will | |
341 | encode LIG EVEX instructions with 256bit and 512bit vector length, | |
342 | respectively. | |
343 | ||
344 | @cindex @samp{-mevexwig=} option, i386 | |
345 | @cindex @samp{-mevexwig=} option, x86-64 | |
346 | @item -mevexwig=@var{0} | |
347 | @itemx -mevexwig=@var{1} | |
348 | These options control how the assembler should encode w-ignored (WIG) | |
349 | EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG | |
350 | EVEX instructions with evex.w = 0, which is the default. | |
351 | @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with | |
352 | evex.w = 1. | |
353 | ||
1efbbeb4 L |
354 | @cindex @samp{-mmnemonic=} option, i386 |
355 | @cindex @samp{-mmnemonic=} option, x86-64 | |
356 | @item -mmnemonic=@var{att} | |
1f9bb1ca | 357 | @itemx -mmnemonic=@var{intel} |
34bca508 | 358 | This option specifies instruction mnemonic for matching instructions. |
1efbbeb4 L |
359 | The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will |
360 | take precedent. | |
361 | ||
362 | @cindex @samp{-msyntax=} option, i386 | |
363 | @cindex @samp{-msyntax=} option, x86-64 | |
364 | @item -msyntax=@var{att} | |
1f9bb1ca | 365 | @itemx -msyntax=@var{intel} |
34bca508 | 366 | This option specifies instruction syntax when processing instructions. |
1efbbeb4 L |
367 | The @code{.att_syntax} and @code{.intel_syntax} directives will |
368 | take precedent. | |
369 | ||
370 | @cindex @samp{-mnaked-reg} option, i386 | |
371 | @cindex @samp{-mnaked-reg} option, x86-64 | |
372 | @item -mnaked-reg | |
33eaf5de | 373 | This option specifies that registers don't require a @samp{%} prefix. |
e1d4d893 | 374 | The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. |
1efbbeb4 | 375 | |
7e8b059b L |
376 | @cindex @samp{-madd-bnd-prefix} option, i386 |
377 | @cindex @samp{-madd-bnd-prefix} option, x86-64 | |
378 | @item -madd-bnd-prefix | |
379 | This option forces the assembler to add BND prefix to all branches, even | |
380 | if such prefix was not explicitly specified in the source code. | |
381 | ||
8dcea932 L |
382 | @cindex @samp{-mshared} option, i386 |
383 | @cindex @samp{-mshared} option, x86-64 | |
384 | @item -mno-shared | |
385 | On ELF target, the assembler normally optimizes out non-PLT relocations | |
386 | against defined non-weak global branch targets with default visibility. | |
387 | The @samp{-mshared} option tells the assembler to generate code which | |
388 | may go into a shared library where all non-weak global branch targets | |
389 | with default visibility can be preempted. The resulting code is | |
390 | slightly bigger. This option only affects the handling of branch | |
391 | instructions. | |
392 | ||
167ad85b TG |
393 | @cindex @samp{-mbig-obj} option, x86-64 |
394 | @item -mbig-obj | |
395 | On x86-64 PE/COFF target this option forces the use of big object file | |
396 | format, which allows more than 32768 sections. | |
397 | ||
d022bddd IT |
398 | @cindex @samp{-momit-lock-prefix=} option, i386 |
399 | @cindex @samp{-momit-lock-prefix=} option, x86-64 | |
400 | @item -momit-lock-prefix=@var{no} | |
401 | @itemx -momit-lock-prefix=@var{yes} | |
402 | These options control how the assembler should encode lock prefix. | |
403 | This option is intended as a workaround for processors, that fail on | |
404 | lock prefix. This option can only be safely used with single-core, | |
405 | single-thread computers | |
406 | @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. | |
407 | @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, | |
408 | which is the default. | |
409 | ||
e4e00185 AS |
410 | @cindex @samp{-mfence-as-lock-add=} option, i386 |
411 | @cindex @samp{-mfence-as-lock-add=} option, x86-64 | |
412 | @item -mfence-as-lock-add=@var{no} | |
413 | @itemx -mfence-as-lock-add=@var{yes} | |
414 | These options control how the assembler should encode lfence, mfence and | |
415 | sfence. | |
416 | @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and | |
417 | sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and | |
418 | @samp{lock addl $0x0, (%esp)} in 32-bit mode. | |
419 | @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and | |
420 | sfence as usual, which is the default. | |
421 | ||
0cb4071e L |
422 | @cindex @samp{-mrelax-relocations=} option, i386 |
423 | @cindex @samp{-mrelax-relocations=} option, x86-64 | |
424 | @item -mrelax-relocations=@var{no} | |
425 | @itemx -mrelax-relocations=@var{yes} | |
426 | These options control whether the assembler should generate relax | |
427 | relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and | |
428 | R_X86_64_REX_GOTPCRELX, in 64-bit mode. | |
429 | @option{-mrelax-relocations=@var{yes}} will generate relax relocations. | |
430 | @option{-mrelax-relocations=@var{no}} will not generate relax | |
431 | relocations. The default can be controlled by a configure option | |
432 | @option{--enable-x86-relax-relocations}. | |
433 | ||
e379e5f3 L |
434 | @cindex @samp{-malign-branch-boundary=} option, i386 |
435 | @cindex @samp{-malign-branch-boundary=} option, x86-64 | |
436 | @item -malign-branch-boundary=@var{NUM} | |
437 | This option controls how the assembler should align branches with segment | |
438 | prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or | |
439 | no less than 16. Branches will be aligned within @var{NUM} byte | |
440 | boundary. @option{-malign-branch-boundary=0}, which is the default, | |
441 | doesn't align branches. | |
442 | ||
443 | @cindex @samp{-malign-branch=} option, i386 | |
444 | @cindex @samp{-malign-branch=} option, x86-64 | |
445 | @item -malign-branch=@var{TYPE}[+@var{TYPE}...] | |
446 | This option specifies types of branches to align. @var{TYPE} is | |
447 | combination of @samp{jcc}, which aligns conditional jumps, | |
448 | @samp{fused}, which aligns fused conditional jumps, @samp{jmp}, | |
449 | which aligns unconditional jumps, @samp{call} which aligns calls, | |
450 | @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect | |
451 | jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. | |
452 | ||
453 | @cindex @samp{-malign-branch-prefix-size=} option, i386 | |
454 | @cindex @samp{-malign-branch-prefix-size=} option, x86-64 | |
455 | @item -malign-branch-prefix-size=@var{NUM} | |
456 | This option specifies the maximum number of prefixes on an instruction | |
457 | to align branches. @var{NUM} should be between 0 and 5. The default | |
458 | @var{NUM} is 5. | |
459 | ||
76cf450b L |
460 | @cindex @samp{-mbranches-within-32B-boundaries} option, i386 |
461 | @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64 | |
462 | @item -mbranches-within-32B-boundaries | |
463 | This option aligns conditional jumps, fused conditional jumps and | |
464 | unconditional jumps within 32 byte boundary with up to 5 segment prefixes | |
465 | on an instruction. It is equivalent to | |
466 | @option{-malign-branch-boundary=32} | |
467 | @option{-malign-branch=jcc+fused+jmp} | |
468 | @option{-malign-branch-prefix-size=5}. | |
469 | The default doesn't align branches. | |
470 | ||
ae531041 L |
471 | @cindex @samp{-mlfence-after-load=} option, i386 |
472 | @cindex @samp{-mlfence-after-load=} option, x86-64 | |
473 | @item -mlfence-after-load=@var{no} | |
474 | @itemx -mlfence-after-load=@var{yes} | |
475 | These options control whether the assembler should generate lfence | |
476 | after load instructions. @option{-mlfence-after-load=@var{yes}} will | |
477 | generate lfence. @option{-mlfence-after-load=@var{no}} will not generate | |
478 | lfence, which is the default. | |
479 | ||
480 | @cindex @samp{-mlfence-before-indirect-branch=} option, i386 | |
481 | @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64 | |
482 | @item -mlfence-before-indirect-branch=@var{none} | |
483 | @item -mlfence-before-indirect-branch=@var{all} | |
484 | @item -mlfence-before-indirect-branch=@var{register} | |
485 | @itemx -mlfence-before-indirect-branch=@var{memory} | |
486 | These options control whether the assembler should generate lfence | |
3071b197 | 487 | before indirect near branch instructions. |
ae531041 | 488 | @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence |
3071b197 | 489 | before indirect near branch via register and issue a warning before |
ae531041 | 490 | indirect near branch via memory. |
a09f656b | 491 | It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when |
492 | there's no explict @option{-mlfence-before-ret=}. | |
ae531041 | 493 | @option{-mlfence-before-indirect-branch=@var{register}} will generate |
3071b197 | 494 | lfence before indirect near branch via register. |
ae531041 L |
495 | @option{-mlfence-before-indirect-branch=@var{memory}} will issue a |
496 | warning before indirect near branch via memory. | |
497 | @option{-mlfence-before-indirect-branch=@var{none}} will not generate | |
498 | lfence nor issue warning, which is the default. Note that lfence won't | |
499 | be generated before indirect near branch via register with | |
500 | @option{-mlfence-after-load=@var{yes}} since lfence will be generated | |
501 | after loading branch target register. | |
502 | ||
503 | @cindex @samp{-mlfence-before-ret=} option, i386 | |
504 | @cindex @samp{-mlfence-before-ret=} option, x86-64 | |
505 | @item -mlfence-before-ret=@var{none} | |
a09f656b | 506 | @item -mlfence-before-ret=@var{shl} |
ae531041 | 507 | @item -mlfence-before-ret=@var{or} |
a09f656b | 508 | @item -mlfence-before-ret=@var{yes} |
ae531041 L |
509 | @itemx -mlfence-before-ret=@var{not} |
510 | These options control whether the assembler should generate lfence | |
511 | before ret. @option{-mlfence-before-ret=@var{or}} will generate | |
512 | generate or instruction with lfence. | |
a09f656b | 513 | @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction |
514 | with lfence. @option{-mlfence-before-ret=@var{not}} will generate not | |
515 | instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not | |
516 | generate lfence, which is the default. | |
ae531041 | 517 | |
b4a3a7b4 L |
518 | @cindex @samp{-mx86-used-note=} option, i386 |
519 | @cindex @samp{-mx86-used-note=} option, x86-64 | |
520 | @item -mx86-used-note=@var{no} | |
521 | @itemx -mx86-used-note=@var{yes} | |
522 | These options control whether the assembler should generate | |
523 | GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED | |
524 | GNU property notes. The default can be controlled by the | |
525 | @option{--enable-x86-used-note} configure option. | |
526 | ||
d3d3c6db IT |
527 | @cindex @samp{-mevexrcig=} option, i386 |
528 | @cindex @samp{-mevexrcig=} option, x86-64 | |
529 | @item -mevexrcig=@var{rne} | |
530 | @itemx -mevexrcig=@var{rd} | |
531 | @itemx -mevexrcig=@var{ru} | |
532 | @itemx -mevexrcig=@var{rz} | |
533 | These options control how the assembler should encode SAE-only | |
534 | EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits | |
535 | of EVEX instruction with 00, which is the default. | |
536 | @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} | |
537 | and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions | |
538 | with 01, 10 and 11 RC bits, respectively. | |
539 | ||
5db04b09 L |
540 | @cindex @samp{-mamd64} option, x86-64 |
541 | @cindex @samp{-mintel64} option, x86-64 | |
542 | @item -mamd64 | |
543 | @itemx -mintel64 | |
544 | This option specifies that the assembler should accept only AMD64 or | |
4b5aaf5f L |
545 | Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 |
546 | only and AMD64 ISAs. | |
5db04b09 | 547 | |
b6f8c7c4 L |
548 | @cindex @samp{-O0} option, i386 |
549 | @cindex @samp{-O0} option, x86-64 | |
550 | @cindex @samp{-O} option, i386 | |
551 | @cindex @samp{-O} option, x86-64 | |
552 | @cindex @samp{-O1} option, i386 | |
553 | @cindex @samp{-O1} option, x86-64 | |
554 | @cindex @samp{-O2} option, i386 | |
555 | @cindex @samp{-O2} option, x86-64 | |
556 | @cindex @samp{-Os} option, i386 | |
557 | @cindex @samp{-Os} option, x86-64 | |
558 | @item -O0 | -O | -O1 | -O2 | -Os | |
559 | Optimize instruction encoding with smaller instruction size. @samp{-O} | |
560 | and @samp{-O1} encode 64-bit register load instructions with 64-bit | |
561 | immediate as 32-bit register load instructions with 31-bit or 32-bits | |
99112332 | 562 | immediates, encode 64-bit register clearing instructions with 32-bit |
a0a1771e JB |
563 | register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector |
564 | register clearing instructions with 128-bit VEX vector register | |
565 | clearing instructions, encode 128-bit/256-bit EVEX vector | |
97ed31ae | 566 | register load/store instructions with VEX vector register load/store |
a0a1771e JB |
567 | instructions, and encode 128-bit/256-bit EVEX packed integer logical |
568 | instructions with 128-bit/256-bit VEX packed integer logical. | |
569 | ||
570 | @samp{-O2} includes @samp{-O1} optimization plus encodes | |
571 | 256-bit/512-bit EVEX vector register clearing instructions with 128-bit | |
79dec6b7 JB |
572 | EVEX vector register clearing instructions. In 64-bit mode VEX encoded |
573 | instructions with commutative source operands will also have their | |
574 | source operands swapped if this allows using the 2-byte VEX prefix form | |
5641ec01 JB |
575 | instead of the 3-byte one. Certain forms of AND as well as OR with the |
576 | same (register) operand specified twice will also be changed to TEST. | |
a0a1771e | 577 | |
b6f8c7c4 L |
578 | @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit |
579 | and 64-bit register tests with immediate as 8-bit register test with | |
580 | immediate. @samp{-O0} turns off this optimization. | |
581 | ||
55b62671 | 582 | @end table |
731caf76 | 583 | @c man end |
e413e4e9 | 584 | |
a6c24e68 NC |
585 | @node i386-Directives |
586 | @section x86 specific Directives | |
587 | ||
588 | @cindex machine directives, x86 | |
589 | @cindex x86 machine directives | |
590 | @table @code | |
591 | ||
592 | @cindex @code{lcomm} directive, COFF | |
593 | @item .lcomm @var{symbol} , @var{length}[, @var{alignment}] | |
594 | Reserve @var{length} (an absolute expression) bytes for a local common | |
595 | denoted by @var{symbol}. The section and value of @var{symbol} are | |
596 | those of the new local common. The addresses are allocated in the bss | |
704209c0 NC |
597 | section, so that at run-time the bytes start off zeroed. Since |
598 | @var{symbol} is not declared global, it is normally not visible to | |
599 | @code{@value{LD}}. The optional third parameter, @var{alignment}, | |
600 | specifies the desired alignment of the symbol in the bss section. | |
a6c24e68 NC |
601 | |
602 | This directive is only available for COFF based x86 targets. | |
603 | ||
102e9361 NC |
604 | @cindex @code{largecomm} directive, ELF |
605 | @item .largecomm @var{symbol} , @var{length}[, @var{alignment}] | |
606 | This directive behaves in the same way as the @code{comm} directive | |
607 | except that the data is placed into the @var{.lbss} section instead of | |
608 | the @var{.bss} section @ref{Comm}. | |
609 | ||
610 | The directive is intended to be used for data which requires a large | |
611 | amount of space, and it is only available for ELF based x86_64 | |
612 | targets. | |
613 | ||
f2f51cd5 NC |
614 | @cindex @code{value} directive |
615 | @item .value @var{expression} [, @var{expression}] | |
616 | This directive behaves in the same way as the @code{.short} directive, | |
617 | taking a series of comma separated expressions and storing them as | |
618 | two-byte wide values into the current section. | |
619 | ||
a6c24e68 | 620 | @c FIXME: Document other x86 specific directives ? Eg: .code16gcc, |
a6c24e68 NC |
621 | |
622 | @end table | |
623 | ||
252b5132 | 624 | @node i386-Syntax |
7c31ae13 NC |
625 | @section i386 Syntactical Considerations |
626 | @menu | |
627 | * i386-Variations:: AT&T Syntax versus Intel Syntax | |
628 | * i386-Chars:: Special Characters | |
629 | @end menu | |
630 | ||
631 | @node i386-Variations | |
632 | @subsection AT&T Syntax versus Intel Syntax | |
252b5132 | 633 | |
e413e4e9 AM |
634 | @cindex i386 intel_syntax pseudo op |
635 | @cindex intel_syntax pseudo op, i386 | |
636 | @cindex i386 att_syntax pseudo op | |
637 | @cindex att_syntax pseudo op, i386 | |
252b5132 RH |
638 | @cindex i386 syntax compatibility |
639 | @cindex syntax compatibility, i386 | |
55b62671 AJ |
640 | @cindex x86-64 intel_syntax pseudo op |
641 | @cindex intel_syntax pseudo op, x86-64 | |
642 | @cindex x86-64 att_syntax pseudo op | |
643 | @cindex att_syntax pseudo op, x86-64 | |
644 | @cindex x86-64 syntax compatibility | |
645 | @cindex syntax compatibility, x86-64 | |
e413e4e9 AM |
646 | |
647 | @code{@value{AS}} now supports assembly using Intel assembler syntax. | |
648 | @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches | |
649 | back to the usual AT&T mode for compatibility with the output of | |
650 | @code{@value{GCC}}. Either of these directives may have an optional | |
651 | argument, @code{prefix}, or @code{noprefix} specifying whether registers | |
652 | require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite | |
252b5132 RH |
653 | different from Intel syntax. We mention these differences because |
654 | almost all 80386 documents use Intel syntax. Notable differences | |
655 | between the two syntaxes are: | |
656 | ||
657 | @cindex immediate operands, i386 | |
658 | @cindex i386 immediate operands | |
659 | @cindex register operands, i386 | |
660 | @cindex i386 register operands | |
661 | @cindex jump/call operands, i386 | |
662 | @cindex i386 jump/call operands | |
663 | @cindex operand delimiters, i386 | |
55b62671 AJ |
664 | |
665 | @cindex immediate operands, x86-64 | |
666 | @cindex x86-64 immediate operands | |
667 | @cindex register operands, x86-64 | |
668 | @cindex x86-64 register operands | |
669 | @cindex jump/call operands, x86-64 | |
670 | @cindex x86-64 jump/call operands | |
671 | @cindex operand delimiters, x86-64 | |
252b5132 RH |
672 | @itemize @bullet |
673 | @item | |
674 | AT&T immediate operands are preceded by @samp{$}; Intel immediate | |
675 | operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). | |
676 | AT&T register operands are preceded by @samp{%}; Intel register operands | |
677 | are undelimited. AT&T absolute (as opposed to PC relative) jump/call | |
678 | operands are prefixed by @samp{*}; they are undelimited in Intel syntax. | |
679 | ||
680 | @cindex i386 source, destination operands | |
681 | @cindex source, destination operands; i386 | |
55b62671 AJ |
682 | @cindex x86-64 source, destination operands |
683 | @cindex source, destination operands; x86-64 | |
252b5132 RH |
684 | @item |
685 | AT&T and Intel syntax use the opposite order for source and destination | |
686 | operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The | |
687 | @samp{source, dest} convention is maintained for compatibility with | |
96ef6e0f L |
688 | previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and |
689 | instructions with 2 immediate operands, such as the @samp{enter} | |
690 | instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. | |
252b5132 RH |
691 | |
692 | @cindex mnemonic suffixes, i386 | |
693 | @cindex sizes operands, i386 | |
694 | @cindex i386 size suffixes | |
55b62671 AJ |
695 | @cindex mnemonic suffixes, x86-64 |
696 | @cindex sizes operands, x86-64 | |
697 | @cindex x86-64 size suffixes | |
252b5132 RH |
698 | @item |
699 | In AT&T syntax the size of memory operands is determined from the last | |
700 | character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, | |
55b62671 | 701 | @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long |
aa108c0c LC |
702 | (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes |
703 | of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm | |
704 | (256-bit vector) and zmm (512-bit vector) memory references, only when there's | |
705 | no other way to disambiguate an instruction. Intel syntax accomplishes this by | |
706 | prefixing memory operands (@emph{not} the instruction mnemonics) with | |
707 | @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, | |
708 | @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel | |
709 | syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T | |
710 | syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and | |
711 | @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. | |
252b5132 | 712 | |
4b06377f L |
713 | In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} |
714 | instruction with the 64-bit displacement or immediate operand. | |
715 | ||
252b5132 RH |
716 | @cindex return instructions, i386 |
717 | @cindex i386 jump, call, return | |
55b62671 AJ |
718 | @cindex return instructions, x86-64 |
719 | @cindex x86-64 jump, call, return | |
252b5132 RH |
720 | @item |
721 | Immediate form long jumps and calls are | |
722 | @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the | |
723 | Intel syntax is | |
724 | @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return | |
725 | instruction | |
726 | is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is | |
727 | @samp{ret far @var{stack-adjust}}. | |
728 | ||
729 | @cindex sections, i386 | |
730 | @cindex i386 sections | |
55b62671 AJ |
731 | @cindex sections, x86-64 |
732 | @cindex x86-64 sections | |
252b5132 RH |
733 | @item |
734 | The AT&T assembler does not provide support for multiple section | |
735 | programs. Unix style systems expect all programs to be single sections. | |
736 | @end itemize | |
737 | ||
7c31ae13 NC |
738 | @node i386-Chars |
739 | @subsection Special Characters | |
740 | ||
741 | @cindex line comment character, i386 | |
742 | @cindex i386 line comment character | |
743 | The presence of a @samp{#} appearing anywhere on a line indicates the | |
744 | start of a comment that extends to the end of that line. | |
745 | ||
746 | If a @samp{#} appears as the first character of a line then the whole | |
747 | line is treated as a comment, but in this case the line can also be a | |
748 | logical line number directive (@pxref{Comments}) or a preprocessor | |
749 | control command (@pxref{Preprocessing}). | |
750 | ||
a05a5b64 | 751 | If the @option{--divide} command-line option has not been specified |
7c31ae13 NC |
752 | then the @samp{/} character appearing anywhere on a line also |
753 | introduces a line comment. | |
754 | ||
755 | @cindex line separator, i386 | |
756 | @cindex statement separator, i386 | |
757 | @cindex i386 line separator | |
758 | The @samp{;} character can be used to separate statements on the same | |
759 | line. | |
760 | ||
252b5132 | 761 | @node i386-Mnemonics |
d3b47e2b L |
762 | @section i386-Mnemonics |
763 | @subsection Instruction Naming | |
252b5132 RH |
764 | |
765 | @cindex i386 instruction naming | |
766 | @cindex instruction naming, i386 | |
55b62671 AJ |
767 | @cindex x86-64 instruction naming |
768 | @cindex instruction naming, x86-64 | |
769 | ||
252b5132 | 770 | Instruction mnemonics are suffixed with one character modifiers which |
55b62671 AJ |
771 | specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} |
772 | and @samp{q} specify byte, word, long and quadruple word operands. If | |
773 | no suffix is specified by an instruction then @code{@value{AS}} tries to | |
774 | fill in the missing suffix based on the destination register operand | |
775 | (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent | |
776 | to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to | |
777 | @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix | |
778 | assembler which assumes that a missing mnemonic suffix implies long | |
779 | operand size. (This incompatibility does not affect compiler output | |
780 | since compilers always explicitly specify the mnemonic suffix.) | |
252b5132 | 781 | |
c006a730 JB |
782 | When there is no sizing suffix and no (suitable) register operands to |
783 | deduce the size of memory operands, with a few exceptions and where long | |
784 | operand size is possible in the first place, operand size will default | |
785 | to long in 32- and 64-bit modes. Similarly it will default to short in | |
786 | 16-bit mode. Noteworthy exceptions are | |
787 | ||
788 | @itemize @bullet | |
789 | @item | |
790 | Instructions with an implicit on-stack operand as well as branches, | |
791 | which default to quad in 64-bit mode. | |
792 | ||
793 | @item | |
794 | Sign- and zero-extending moves, which default to byte size source | |
795 | operands. | |
796 | ||
797 | @item | |
798 | Floating point insns with integer operands, which default to short (for | |
799 | perhaps historical reasons). | |
800 | ||
801 | @item | |
802 | CRC32 with a 64-bit destination, which defaults to a quad source | |
803 | operand. | |
804 | ||
805 | @end itemize | |
806 | ||
b6169b20 L |
807 | @cindex encoding options, i386 |
808 | @cindex encoding options, x86-64 | |
809 | ||
86fa6981 L |
810 | Different encoding options can be specified via pseudo prefixes: |
811 | ||
812 | @itemize @bullet | |
813 | @item | |
814 | @samp{@{disp8@}} -- prefer 8-bit displacement. | |
815 | ||
816 | @item | |
817 | @samp{@{disp32@}} -- prefer 32-bit displacement. | |
818 | ||
819 | @item | |
820 | @samp{@{load@}} -- prefer load-form instruction. | |
821 | ||
822 | @item | |
823 | @samp{@{store@}} -- prefer store-form instruction. | |
824 | ||
825 | @item | |
42e04b36 | 826 | @samp{@{vex@}} -- encode with VEX prefix. |
86fa6981 L |
827 | |
828 | @item | |
42e04b36 | 829 | @samp{@{vex3@}} -- encode with 3-byte VEX prefix. |
86fa6981 L |
830 | |
831 | @item | |
832 | @samp{@{evex@}} -- encode with EVEX prefix. | |
6b6b6807 L |
833 | |
834 | @item | |
835 | @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector | |
836 | instructions (x86-64 only). Note that this differs from the @samp{rex} | |
837 | prefix which generates REX prefix unconditionally. | |
b6f8c7c4 L |
838 | |
839 | @item | |
840 | @samp{@{nooptimize@}} -- disable instruction size optimization. | |
86fa6981 | 841 | @end itemize |
b6169b20 | 842 | |
252b5132 RH |
843 | @cindex conversion instructions, i386 |
844 | @cindex i386 conversion instructions | |
55b62671 AJ |
845 | @cindex conversion instructions, x86-64 |
846 | @cindex x86-64 conversion instructions | |
252b5132 RH |
847 | The Intel-syntax conversion instructions |
848 | ||
849 | @itemize @bullet | |
850 | @item | |
851 | @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, | |
852 | ||
853 | @item | |
854 | @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, | |
855 | ||
856 | @item | |
857 | @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, | |
858 | ||
859 | @item | |
860 | @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, | |
55b62671 AJ |
861 | |
862 | @item | |
863 | @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} | |
864 | (x86-64 only), | |
865 | ||
866 | @item | |
d5f0cf92 | 867 | @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in |
55b62671 | 868 | @samp{%rdx:%rax} (x86-64 only), |
252b5132 RH |
869 | @end itemize |
870 | ||
871 | @noindent | |
55b62671 AJ |
872 | are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and |
873 | @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these | |
874 | instructions. | |
252b5132 | 875 | |
0e6724de L |
876 | @cindex extension instructions, i386 |
877 | @cindex i386 extension instructions | |
878 | @cindex extension instructions, x86-64 | |
879 | @cindex x86-64 extension instructions | |
880 | The Intel-syntax extension instructions | |
881 | ||
882 | @itemize @bullet | |
883 | @item | |
884 | @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. | |
885 | ||
886 | @item | |
887 | @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. | |
888 | ||
889 | @item | |
890 | @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} | |
891 | (x86-64 only). | |
892 | ||
893 | @item | |
894 | @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} | |
895 | ||
896 | @item | |
897 | @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} | |
898 | (x86-64 only). | |
899 | ||
900 | @item | |
901 | @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} | |
902 | (x86-64 only). | |
903 | ||
904 | @item | |
905 | @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. | |
906 | ||
907 | @item | |
908 | @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. | |
909 | ||
910 | @item | |
911 | @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} | |
912 | (x86-64 only). | |
913 | ||
914 | @item | |
915 | @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} | |
916 | ||
917 | @item | |
918 | @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} | |
919 | (x86-64 only). | |
920 | @end itemize | |
921 | ||
922 | @noindent | |
923 | are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx}, | |
924 | @samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, | |
925 | @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx}, | |
926 | @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx}, | |
927 | @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax. | |
928 | ||
252b5132 RH |
929 | @cindex jump instructions, i386 |
930 | @cindex call instructions, i386 | |
55b62671 AJ |
931 | @cindex jump instructions, x86-64 |
932 | @cindex call instructions, x86-64 | |
252b5132 RH |
933 | Far call/jump instructions are @samp{lcall} and @samp{ljmp} in |
934 | AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel | |
935 | convention. | |
936 | ||
d3b47e2b | 937 | @subsection AT&T Mnemonic versus Intel Mnemonic |
1efbbeb4 L |
938 | |
939 | @cindex i386 mnemonic compatibility | |
940 | @cindex mnemonic compatibility, i386 | |
941 | ||
942 | @code{@value{AS}} supports assembly using Intel mnemonic. | |
943 | @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and | |
944 | @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T | |
945 | syntax for compatibility with the output of @code{@value{GCC}}. | |
1efbbeb4 L |
946 | Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, |
947 | @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, | |
948 | @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 | |
949 | assembler with different mnemonics from those in Intel IA32 specification. | |
950 | @code{@value{GCC}} generates those instructions with AT&T mnemonic. | |
951 | ||
bc31405e L |
952 | @itemize @bullet |
953 | @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination | |
954 | register. @samp{movsxd} should be used to encode 16-bit or 32-bit | |
955 | destination register with both AT&T and Intel mnemonics. | |
956 | @end itemize | |
957 | ||
252b5132 RH |
958 | @node i386-Regs |
959 | @section Register Naming | |
960 | ||
961 | @cindex i386 registers | |
962 | @cindex registers, i386 | |
55b62671 AJ |
963 | @cindex x86-64 registers |
964 | @cindex registers, x86-64 | |
252b5132 RH |
965 | Register operands are always prefixed with @samp{%}. The 80386 registers |
966 | consist of | |
967 | ||
968 | @itemize @bullet | |
969 | @item | |
970 | the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, | |
971 | @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the | |
972 | frame pointer), and @samp{%esp} (the stack pointer). | |
973 | ||
974 | @item | |
975 | the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, | |
976 | @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. | |
977 | ||
978 | @item | |
979 | the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, | |
980 | @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These | |
981 | are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, | |
982 | @samp{%cx}, and @samp{%dx}) | |
983 | ||
984 | @item | |
985 | the 6 section registers @samp{%cs} (code section), @samp{%ds} | |
986 | (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, | |
987 | and @samp{%gs}. | |
988 | ||
989 | @item | |
4bde3cdd UD |
990 | the 5 processor control registers @samp{%cr0}, @samp{%cr2}, |
991 | @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. | |
252b5132 RH |
992 | |
993 | @item | |
994 | the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, | |
995 | @samp{%db3}, @samp{%db6}, and @samp{%db7}. | |
996 | ||
997 | @item | |
998 | the 2 test registers @samp{%tr6} and @samp{%tr7}. | |
999 | ||
1000 | @item | |
1001 | the 8 floating point register stack @samp{%st} or equivalently | |
1002 | @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, | |
1003 | @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. | |
55b62671 AJ |
1004 | These registers are overloaded by 8 MMX registers @samp{%mm0}, |
1005 | @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, | |
1006 | @samp{%mm6} and @samp{%mm7}. | |
1007 | ||
1008 | @item | |
4bde3cdd | 1009 | the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, |
55b62671 AJ |
1010 | @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. |
1011 | @end itemize | |
1012 | ||
1013 | The AMD x86-64 architecture extends the register set by: | |
1014 | ||
1015 | @itemize @bullet | |
1016 | @item | |
1017 | enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the | |
1018 | accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, | |
1019 | @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack | |
1020 | pointer) | |
1021 | ||
1022 | @item | |
1023 | the 8 extended registers @samp{%r8}--@samp{%r15}. | |
1024 | ||
1025 | @item | |
4bde3cdd | 1026 | the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. |
55b62671 AJ |
1027 | |
1028 | @item | |
4bde3cdd | 1029 | the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. |
55b62671 AJ |
1030 | |
1031 | @item | |
4bde3cdd | 1032 | the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. |
55b62671 AJ |
1033 | |
1034 | @item | |
1035 | the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. | |
1036 | ||
1037 | @item | |
1038 | the 8 debug registers: @samp{%db8}--@samp{%db15}. | |
1039 | ||
1040 | @item | |
4bde3cdd UD |
1041 | the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. |
1042 | @end itemize | |
1043 | ||
1044 | With the AVX extensions more registers were made available: | |
1045 | ||
1046 | @itemize @bullet | |
1047 | ||
1048 | @item | |
1049 | the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 | |
1050 | available in 32-bit mode). The bottom 128 bits are overlaid with the | |
1051 | @samp{xmm0}--@samp{xmm15} registers. | |
1052 | ||
1053 | @end itemize | |
1054 | ||
1055 | The AVX2 extensions made in 64-bit mode more registers available: | |
1056 | ||
1057 | @itemize @bullet | |
1058 | ||
1059 | @item | |
1060 | the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit | |
1061 | registers @samp{%ymm16}--@samp{%ymm31}. | |
1062 | ||
1063 | @end itemize | |
1064 | ||
1065 | The AVX512 extensions added the following registers: | |
1066 | ||
1067 | @itemize @bullet | |
1068 | ||
1069 | @item | |
1070 | the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 | |
1071 | available in 32-bit mode). The bottom 128 bits are overlaid with the | |
1072 | @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are | |
1073 | overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. | |
1074 | ||
1075 | @item | |
1076 | the 8 mask registers @samp{%k0}--@samp{%k7}. | |
1077 | ||
252b5132 RH |
1078 | @end itemize |
1079 | ||
1080 | @node i386-Prefixes | |
1081 | @section Instruction Prefixes | |
1082 | ||
1083 | @cindex i386 instruction prefixes | |
1084 | @cindex instruction prefixes, i386 | |
1085 | @cindex prefixes, i386 | |
1086 | Instruction prefixes are used to modify the following instruction. They | |
1087 | are used to repeat string instructions, to provide section overrides, to | |
1088 | perform bus lock operations, and to change operand and address sizes. | |
1089 | (Most instructions that normally operate on 32-bit operands will use | |
1090 | 16-bit operands if the instruction has an ``operand size'' prefix.) | |
1091 | Instruction prefixes are best written on the same line as the instruction | |
1092 | they act upon. For example, the @samp{scas} (scan string) instruction is | |
1093 | repeated with: | |
1094 | ||
1095 | @smallexample | |
1096 | repne scas %es:(%edi),%al | |
1097 | @end smallexample | |
1098 | ||
1099 | You may also place prefixes on the lines immediately preceding the | |
1100 | instruction, but this circumvents checks that @code{@value{AS}} does | |
1101 | with prefixes, and will not work with all prefixes. | |
1102 | ||
1103 | Here is a list of instruction prefixes: | |
1104 | ||
1105 | @cindex section override prefixes, i386 | |
1106 | @itemize @bullet | |
1107 | @item | |
1108 | Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, | |
1109 | @samp{fs}, @samp{gs}. These are automatically added by specifying | |
1110 | using the @var{section}:@var{memory-operand} form for memory references. | |
1111 | ||
1112 | @cindex size prefixes, i386 | |
1113 | @item | |
1114 | Operand/Address size prefixes @samp{data16} and @samp{addr16} | |
1115 | change 32-bit operands/addresses into 16-bit operands/addresses, | |
1116 | while @samp{data32} and @samp{addr32} change 16-bit ones (in a | |
1117 | @code{.code16} section) into 32-bit operands/addresses. These prefixes | |
1118 | @emph{must} appear on the same line of code as the instruction they | |
1119 | modify. For example, in a 16-bit @code{.code16} section, you might | |
1120 | write: | |
1121 | ||
1122 | @smallexample | |
1123 | addr32 jmpl *(%ebx) | |
1124 | @end smallexample | |
1125 | ||
1126 | @cindex bus lock prefixes, i386 | |
1127 | @cindex inhibiting interrupts, i386 | |
1128 | @item | |
1129 | The bus lock prefix @samp{lock} inhibits interrupts during execution of | |
1130 | the instruction it precedes. (This is only valid with certain | |
1131 | instructions; see a 80386 manual for details). | |
1132 | ||
1133 | @cindex coprocessor wait, i386 | |
1134 | @item | |
1135 | The wait for coprocessor prefix @samp{wait} waits for the coprocessor to | |
1136 | complete the current instruction. This should never be needed for the | |
1137 | 80386/80387 combination. | |
1138 | ||
1139 | @cindex repeat prefixes, i386 | |
1140 | @item | |
1141 | The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added | |
1142 | to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} | |
1143 | times if the current address size is 16-bits). | |
55b62671 AJ |
1144 | @cindex REX prefixes, i386 |
1145 | @item | |
1146 | The @samp{rex} family of prefixes is used by x86-64 to encode | |
1147 | extensions to i386 instruction set. The @samp{rex} prefix has four | |
1148 | bits --- an operand size overwrite (@code{64}) used to change operand size | |
1149 | from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the | |
1150 | register set. | |
1151 | ||
1152 | You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} | |
1153 | instruction emits @samp{rex} prefix with all the bits set. By omitting | |
1154 | the @code{64}, @code{x}, @code{y} or @code{z} you may write other | |
1155 | prefixes as well. Normally, there is no need to write the prefixes | |
1156 | explicitly, since gas will automatically generate them based on the | |
1157 | instruction operands. | |
252b5132 RH |
1158 | @end itemize |
1159 | ||
1160 | @node i386-Memory | |
1161 | @section Memory References | |
1162 | ||
1163 | @cindex i386 memory references | |
1164 | @cindex memory references, i386 | |
55b62671 AJ |
1165 | @cindex x86-64 memory references |
1166 | @cindex memory references, x86-64 | |
252b5132 RH |
1167 | An Intel syntax indirect memory reference of the form |
1168 | ||
1169 | @smallexample | |
1170 | @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] | |
1171 | @end smallexample | |
1172 | ||
1173 | @noindent | |
1174 | is translated into the AT&T syntax | |
1175 | ||
1176 | @smallexample | |
1177 | @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) | |
1178 | @end smallexample | |
1179 | ||
1180 | @noindent | |
1181 | where @var{base} and @var{index} are the optional 32-bit base and | |
1182 | index registers, @var{disp} is the optional displacement, and | |
1183 | @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} | |
1184 | to calculate the address of the operand. If no @var{scale} is | |
1185 | specified, @var{scale} is taken to be 1. @var{section} specifies the | |
1186 | optional section register for the memory operand, and may override the | |
1187 | default section register (see a 80386 manual for section register | |
1188 | defaults). Note that section overrides in AT&T syntax @emph{must} | |
1189 | be preceded by a @samp{%}. If you specify a section override which | |
1190 | coincides with the default section register, @code{@value{AS}} does @emph{not} | |
1191 | output any section register override prefixes to assemble the given | |
1192 | instruction. Thus, section overrides can be specified to emphasize which | |
1193 | section register is used for a given memory operand. | |
1194 | ||
1195 | Here are some examples of Intel and AT&T style memory references: | |
1196 | ||
1197 | @table @asis | |
1198 | @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} | |
1199 | @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is | |
1200 | missing, and the default section is used (@samp{%ss} for addressing with | |
1201 | @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. | |
1202 | ||
1203 | @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} | |
1204 | @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is | |
1205 | @samp{foo}. All other fields are missing. The section register here | |
1206 | defaults to @samp{%ds}. | |
1207 | ||
1208 | @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} | |
1209 | This uses the value pointed to by @samp{foo} as a memory operand. | |
1210 | Note that @var{base} and @var{index} are both missing, but there is only | |
1211 | @emph{one} @samp{,}. This is a syntactic exception. | |
1212 | ||
1213 | @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} | |
1214 | This selects the contents of the variable @samp{foo} with section | |
1215 | register @var{section} being @samp{%gs}. | |
1216 | @end table | |
1217 | ||
1218 | Absolute (as opposed to PC relative) call and jump operands must be | |
1219 | prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} | |
1220 | always chooses PC relative addressing for jump/call labels. | |
1221 | ||
1222 | Any instruction that has a memory operand, but no register operand, | |
55b62671 AJ |
1223 | @emph{must} specify its size (byte, word, long, or quadruple) with an |
1224 | instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, | |
1225 | respectively). | |
1226 | ||
1227 | The x86-64 architecture adds an RIP (instruction pointer relative) | |
1228 | addressing. This addressing mode is specified by using @samp{rip} as a | |
1229 | base register. Only constant offsets are valid. For example: | |
1230 | ||
1231 | @table @asis | |
1232 | @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} | |
1233 | Points to the address 1234 bytes past the end of the current | |
1234 | instruction. | |
1235 | ||
1236 | @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} | |
1237 | Points to the @code{symbol} in RIP relative way, this is shorter than | |
1238 | the default absolute addressing. | |
1239 | @end table | |
1240 | ||
1241 | Other addressing modes remain unchanged in x86-64 architecture, except | |
1242 | registers used are 64-bit instead of 32-bit. | |
252b5132 | 1243 | |
fddf5b5b | 1244 | @node i386-Jumps |
252b5132 RH |
1245 | @section Handling of Jump Instructions |
1246 | ||
1247 | @cindex jump optimization, i386 | |
1248 | @cindex i386 jump optimization | |
55b62671 AJ |
1249 | @cindex jump optimization, x86-64 |
1250 | @cindex x86-64 jump optimization | |
252b5132 RH |
1251 | Jump instructions are always optimized to use the smallest possible |
1252 | displacements. This is accomplished by using byte (8-bit) displacement | |
1253 | jumps whenever the target is sufficiently close. If a byte displacement | |
fddf5b5b | 1254 | is insufficient a long displacement is used. We do not support |
252b5132 RH |
1255 | word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump |
1256 | instruction with the @samp{data16} instruction prefix), since the 80386 | |
1257 | insists upon masking @samp{%eip} to 16 bits after the word displacement | |
fddf5b5b | 1258 | is added. (See also @pxref{i386-Arch}) |
252b5132 RH |
1259 | |
1260 | Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, | |
1261 | @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte | |
1262 | displacements, so that if you use these instructions (@code{@value{GCC}} does | |
1263 | not use them) you may get an error message (and incorrect code). The AT&T | |
1264 | 80386 assembler tries to get around this problem by expanding @samp{jcxz foo} | |
1265 | to | |
1266 | ||
1267 | @smallexample | |
1268 | jcxz cx_zero | |
1269 | jmp cx_nonzero | |
1270 | cx_zero: jmp foo | |
1271 | cx_nonzero: | |
1272 | @end smallexample | |
1273 | ||
1274 | @node i386-Float | |
1275 | @section Floating Point | |
1276 | ||
1277 | @cindex i386 floating point | |
1278 | @cindex floating point, i386 | |
55b62671 AJ |
1279 | @cindex x86-64 floating point |
1280 | @cindex floating point, x86-64 | |
252b5132 RH |
1281 | All 80387 floating point types except packed BCD are supported. |
1282 | (BCD support may be added without much difficulty). These data | |
1283 | types are 16-, 32-, and 64- bit integers, and single (32-bit), | |
1284 | double (64-bit), and extended (80-bit) precision floating point. | |
1285 | Each supported type has an instruction mnemonic suffix and a constructor | |
1286 | associated with it. Instruction mnemonic suffixes specify the operand's | |
1287 | data type. Constructors build these data types into memory. | |
1288 | ||
1289 | @cindex @code{float} directive, i386 | |
1290 | @cindex @code{single} directive, i386 | |
1291 | @cindex @code{double} directive, i386 | |
1292 | @cindex @code{tfloat} directive, i386 | |
55b62671 AJ |
1293 | @cindex @code{float} directive, x86-64 |
1294 | @cindex @code{single} directive, x86-64 | |
1295 | @cindex @code{double} directive, x86-64 | |
1296 | @cindex @code{tfloat} directive, x86-64 | |
252b5132 RH |
1297 | @itemize @bullet |
1298 | @item | |
1299 | Floating point constructors are @samp{.float} or @samp{.single}, | |
1300 | @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. | |
1301 | These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, | |
1302 | and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 | |
1303 | only supports this format via the @samp{fldt} (load 80-bit real to stack | |
1304 | top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. | |
1305 | ||
1306 | @cindex @code{word} directive, i386 | |
1307 | @cindex @code{long} directive, i386 | |
1308 | @cindex @code{int} directive, i386 | |
1309 | @cindex @code{quad} directive, i386 | |
55b62671 AJ |
1310 | @cindex @code{word} directive, x86-64 |
1311 | @cindex @code{long} directive, x86-64 | |
1312 | @cindex @code{int} directive, x86-64 | |
1313 | @cindex @code{quad} directive, x86-64 | |
252b5132 RH |
1314 | @item |
1315 | Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and | |
1316 | @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The | |
1317 | corresponding instruction mnemonic suffixes are @samp{s} (single), | |
1318 | @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, | |
1319 | the 64-bit @samp{q} format is only present in the @samp{fildq} (load | |
1320 | quad integer to stack top) and @samp{fistpq} (store quad integer and pop | |
1321 | stack) instructions. | |
1322 | @end itemize | |
1323 | ||
1324 | Register to register operations should not use instruction mnemonic suffixes. | |
1325 | @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you | |
1326 | wrote @samp{fst %st, %st(1)}, since all register to register operations | |
1327 | use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, | |
1328 | which converts @samp{%st} from 80-bit to 64-bit floating point format, | |
1329 | then stores the result in the 4 byte location @samp{mem}) | |
1330 | ||
1331 | @node i386-SIMD | |
1332 | @section Intel's MMX and AMD's 3DNow! SIMD Operations | |
1333 | ||
1334 | @cindex MMX, i386 | |
1335 | @cindex 3DNow!, i386 | |
1336 | @cindex SIMD, i386 | |
55b62671 AJ |
1337 | @cindex MMX, x86-64 |
1338 | @cindex 3DNow!, x86-64 | |
1339 | @cindex SIMD, x86-64 | |
252b5132 RH |
1340 | |
1341 | @code{@value{AS}} supports Intel's MMX instruction set (SIMD | |
1342 | instructions for integer data), available on Intel's Pentium MMX | |
1343 | processors and Pentium II processors, AMD's K6 and K6-2 processors, | |
b45619c0 | 1344 | Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: |
252b5132 RH |
1345 | instruction set (SIMD instructions for 32-bit floating point data) |
1346 | available on AMD's K6-2 processor and possibly others in the future. | |
1347 | ||
1348 | Currently, @code{@value{AS}} does not support Intel's floating point | |
1349 | SIMD, Katmai (KNI). | |
1350 | ||
1351 | The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, | |
1352 | @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four | |
1353 | 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit | |
1354 | floating point values. The MMX registers cannot be used at the same time | |
1355 | as the floating point stack. | |
1356 | ||
1357 | See Intel and AMD documentation, keeping in mind that the operand order in | |
1358 | instructions is reversed from the Intel syntax. | |
1359 | ||
f88c9eb0 SP |
1360 | @node i386-LWP |
1361 | @section AMD's Lightweight Profiling Instructions | |
1362 | ||
1363 | @cindex LWP, i386 | |
1364 | @cindex LWP, x86-64 | |
1365 | ||
1366 | @code{@value{AS}} supports AMD's Lightweight Profiling (LWP) | |
1367 | instruction set, available on AMD's Family 15h (Orochi) processors. | |
1368 | ||
1369 | LWP enables applications to collect and manage performance data, and | |
1370 | react to performance events. The collection of performance data | |
1371 | requires no context switches. LWP runs in the context of a thread and | |
1372 | so several counters can be used independently across multiple threads. | |
1373 | LWP can be used in both 64-bit and legacy 32-bit modes. | |
1374 | ||
1375 | For detailed information on the LWP instruction set, see the | |
1376 | @cite{AMD Lightweight Profiling Specification} available at | |
1377 | @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. | |
1378 | ||
87973e9f QN |
1379 | @node i386-BMI |
1380 | @section Bit Manipulation Instructions | |
1381 | ||
1382 | @cindex BMI, i386 | |
1383 | @cindex BMI, x86-64 | |
1384 | ||
1385 | @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. | |
1386 | ||
1387 | BMI instructions provide several instructions implementing individual | |
1388 | bit manipulation operations such as isolation, masking, setting, or | |
34bca508 | 1389 | resetting. |
87973e9f QN |
1390 | |
1391 | @c Need to add a specification citation here when available. | |
1392 | ||
2a2a0f38 QN |
1393 | @node i386-TBM |
1394 | @section AMD's Trailing Bit Manipulation Instructions | |
1395 | ||
1396 | @cindex TBM, i386 | |
1397 | @cindex TBM, x86-64 | |
1398 | ||
1399 | @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) | |
1400 | instruction set, available on AMD's BDVER2 processors (Trinity and | |
1401 | Viperfish). | |
1402 | ||
1403 | TBM instructions provide instructions implementing individual bit | |
1404 | manipulation operations such as isolating, masking, setting, resetting, | |
1405 | complementing, and operations on trailing zeros and ones. | |
1406 | ||
1407 | @c Need to add a specification citation here when available. | |
87973e9f | 1408 | |
252b5132 RH |
1409 | @node i386-16bit |
1410 | @section Writing 16-bit Code | |
1411 | ||
1412 | @cindex i386 16-bit code | |
1413 | @cindex 16-bit code, i386 | |
1414 | @cindex real-mode code, i386 | |
eecb386c | 1415 | @cindex @code{code16gcc} directive, i386 |
252b5132 RH |
1416 | @cindex @code{code16} directive, i386 |
1417 | @cindex @code{code32} directive, i386 | |
55b62671 AJ |
1418 | @cindex @code{code64} directive, i386 |
1419 | @cindex @code{code64} directive, x86-64 | |
1420 | While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code | |
1421 | or 64-bit x86-64 code depending on the default configuration, | |
252b5132 | 1422 | it also supports writing code to run in real mode or in 16-bit protected |
eecb386c AM |
1423 | mode code segments. To do this, put a @samp{.code16} or |
1424 | @samp{.code16gcc} directive before the assembly language instructions to | |
995cef8c L |
1425 | be run in 16-bit mode. You can switch @code{@value{AS}} to writing |
1426 | 32-bit code with the @samp{.code32} directive or 64-bit code with the | |
1427 | @samp{.code64} directive. | |
eecb386c AM |
1428 | |
1429 | @samp{.code16gcc} provides experimental support for generating 16-bit | |
1430 | code from gcc, and differs from @samp{.code16} in that @samp{call}, | |
1431 | @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, | |
1432 | @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions | |
1433 | default to 32-bit size. This is so that the stack pointer is | |
1434 | manipulated in the same way over function calls, allowing access to | |
1435 | function parameters at the same stack offsets as in 32-bit mode. | |
1436 | @samp{.code16gcc} also automatically adds address size prefixes where | |
1437 | necessary to use the 32-bit addressing modes that gcc generates. | |
252b5132 RH |
1438 | |
1439 | The code which @code{@value{AS}} generates in 16-bit mode will not | |
1440 | necessarily run on a 16-bit pre-80386 processor. To write code that | |
1441 | runs on such a processor, you must refrain from using @emph{any} 32-bit | |
1442 | constructs which require @code{@value{AS}} to output address or operand | |
1443 | size prefixes. | |
1444 | ||
1445 | Note that writing 16-bit code instructions by explicitly specifying a | |
1446 | prefix or an instruction mnemonic suffix within a 32-bit code section | |
1447 | generates different machine instructions than those generated for a | |
1448 | 16-bit code segment. In a 32-bit code section, the following code | |
1449 | generates the machine opcode bytes @samp{66 6a 04}, which pushes the | |
1450 | value @samp{4} onto the stack, decrementing @samp{%esp} by 2. | |
1451 | ||
1452 | @smallexample | |
1453 | pushw $4 | |
1454 | @end smallexample | |
1455 | ||
1456 | The same code in a 16-bit code section would generate the machine | |
b45619c0 | 1457 | opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which |
252b5132 RH |
1458 | is correct since the processor default operand size is assumed to be 16 |
1459 | bits in a 16-bit code section. | |
1460 | ||
e413e4e9 AM |
1461 | @node i386-Arch |
1462 | @section Specifying CPU Architecture | |
1463 | ||
1464 | @cindex arch directive, i386 | |
1465 | @cindex i386 arch directive | |
55b62671 AJ |
1466 | @cindex arch directive, x86-64 |
1467 | @cindex x86-64 arch directive | |
e413e4e9 AM |
1468 | |
1469 | @code{@value{AS}} may be told to assemble for a particular CPU | |
5c6af06e | 1470 | (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This |
e413e4e9 AM |
1471 | directive enables a warning when gas detects an instruction that is not |
1472 | supported on the CPU specified. The choices for @var{cpu_type} are: | |
1473 | ||
1474 | @multitable @columnfractions .20 .20 .20 .20 | |
1475 | @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} | |
1476 | @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} | |
5c6af06e | 1477 | @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} |
ef05d495 | 1478 | @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} |
d871f3f4 | 1479 | @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} |
1543849b | 1480 | @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} |
5e5c50d3 | 1481 | @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} |
a9660a6f | 1482 | @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} |
d871f3f4 L |
1483 | @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} |
1484 | @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} | |
272a84b1 | 1485 | @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} |
d76f7bc1 | 1486 | @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} |
c7b8aa3a L |
1487 | @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} |
1488 | @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} | |
1489 | @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} | |
6c30d220 | 1490 | @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} |
272a84b1 L |
1491 | @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} |
1492 | @item @samp{.hle} | |
e2e1fcde | 1493 | @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} |
1dfc6506 L |
1494 | @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} |
1495 | @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} | |
1496 | @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} | |
2cc1b5aa | 1497 | @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} |
47acf0bd | 1498 | @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} |
8cfcb765 | 1499 | @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} |
9186c494 | 1500 | @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} |
d777820b | 1501 | @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} |
c48935d7 | 1502 | @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} |
d777820b | 1503 | @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} |
bb651e8b | 1504 | @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} |
1ceab344 | 1505 | @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} |
272a84b1 | 1506 | @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} |
60aa667e | 1507 | @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} |
142861df | 1508 | @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} |
a847e322 | 1509 | @item @samp{.mcommit} @tab @samp{.sev_es} |
e413e4e9 AM |
1510 | @end multitable |
1511 | ||
fddf5b5b AM |
1512 | Apart from the warning, there are only two other effects on |
1513 | @code{@value{AS}} operation; Firstly, if you specify a CPU other than | |
e413e4e9 AM |
1514 | @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} |
1515 | will automatically use a two byte opcode sequence. The larger three | |
1516 | byte opcode sequence is used on the 486 (and when no architecture is | |
1517 | specified) because it executes faster on the 486. Note that you can | |
1518 | explicitly request the two byte opcode by writing @samp{sarl %eax}. | |
fddf5b5b AM |
1519 | Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, |
1520 | @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset | |
1521 | conditional jumps will be promoted when necessary to a two instruction | |
1522 | sequence consisting of a conditional jump of the opposite sense around | |
1523 | an unconditional jump to the target. | |
1524 | ||
5c6af06e JB |
1525 | Following the CPU architecture (but not a sub-architecture, which are those |
1526 | starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to | |
1527 | control automatic promotion of conditional jumps. @samp{jumps} is the | |
1528 | default, and enables jump promotion; All external jumps will be of the long | |
1529 | variety, and file-local jumps will be promoted as necessary. | |
1530 | (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as | |
1531 | byte offset jumps, and warns about file-local conditional jumps that | |
1532 | @code{@value{AS}} promotes. | |
fddf5b5b AM |
1533 | Unconditional jumps are treated as for @samp{jumps}. |
1534 | ||
1535 | For example | |
1536 | ||
1537 | @smallexample | |
1538 | .arch i8086,nojumps | |
1539 | @end smallexample | |
e413e4e9 | 1540 | |
bc31405e L |
1541 | @node i386-ISA |
1542 | @section AMD64 ISA vs. Intel64 ISA | |
1543 | ||
1544 | There are some discrepancies between AMD64 and Intel64 ISAs. | |
1545 | ||
1546 | @itemize @bullet | |
1547 | @item For @samp{movsxd} with 16-bit destination register, AMD64 | |
1548 | supports 32-bit source operand and Intel64 supports 16-bit source | |
1549 | operand. | |
5990e377 JB |
1550 | |
1551 | @item For far branches (with explicit memory operand), both ISAs support | |
1552 | 32- and 16-bit operand size. Intel64 additionally supports 64-bit | |
1553 | operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax | |
1554 | and with an explicit @samp{tbyte ptr} operand size specifier in Intel | |
1555 | syntax. | |
1556 | ||
1557 | @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16- | |
1558 | and 32-bit operand size (32- and 48-bit memory operand) in both ISAs, | |
1559 | while Intel64 additionally supports 64-bit operand sise (80-bit memory | |
1560 | operands). | |
1561 | ||
bc31405e L |
1562 | @end itemize |
1563 | ||
5c9352f3 AM |
1564 | @node i386-Bugs |
1565 | @section AT&T Syntax bugs | |
1566 | ||
1567 | The UnixWare assembler, and probably other AT&T derived ix86 Unix | |
1568 | assemblers, generate floating point instructions with reversed source | |
1569 | and destination registers in certain cases. Unfortunately, gcc and | |
1570 | possibly many other programs use this reversed syntax, so we're stuck | |
1571 | with it. | |
1572 | ||
1573 | For example | |
1574 | ||
1575 | @smallexample | |
1576 | fsub %st,%st(3) | |
1577 | @end smallexample | |
1578 | @noindent | |
1579 | results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather | |
1580 | than the expected @samp{%st(3) - %st}. This happens with all the | |
1581 | non-commutative arithmetic floating point operations with two register | |
1582 | operands where the source register is @samp{%st} and the destination | |
1583 | register is @samp{%st(i)}. | |
1584 | ||
252b5132 RH |
1585 | @node i386-Notes |
1586 | @section Notes | |
1587 | ||
1588 | @cindex i386 @code{mul}, @code{imul} instructions | |
1589 | @cindex @code{mul} instruction, i386 | |
1590 | @cindex @code{imul} instruction, i386 | |
55b62671 AJ |
1591 | @cindex @code{mul} instruction, x86-64 |
1592 | @cindex @code{imul} instruction, x86-64 | |
252b5132 | 1593 | There is some trickery concerning the @samp{mul} and @samp{imul} |
55b62671 | 1594 | instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding |
252b5132 RH |
1595 | multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 |
1596 | for @samp{imul}) can be output only in the one operand form. Thus, | |
1597 | @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; | |
1598 | the expanding multiply would clobber the @samp{%edx} register, and this | |
1599 | would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the | |
1600 | 64-bit product in @samp{%edx:%eax}. | |
1601 | ||
1602 | We have added a two operand form of @samp{imul} when the first operand | |
1603 | is an immediate mode expression and the second operand is a register. | |
1604 | This is just a shorthand, so that, multiplying @samp{%eax} by 69, for | |
1605 | example, can be done with @samp{imul $69, %eax} rather than @samp{imul | |
1606 | $69, %eax, %eax}. | |
1607 |