Commit | Line | Data |
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78849248 | 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, |
a4ac1c42 | 2 | @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013 |
f7e42eb4 | 3 | @c Free Software Foundation, Inc. |
252b5132 RH |
4 | @c This is part of the GAS manual. |
5 | @c For copying conditions, see the file as.texinfo. | |
6 | @ifset GENERIC | |
7 | @page | |
8 | @node MIPS-Dependent | |
9 | @chapter MIPS Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter MIPS Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex MIPS processor | |
17 | @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several | |
84ea6cf2 | 18 | different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, |
584da044 NC |
19 | and MIPS64. For information about the @sc{mips} instruction set, see |
20 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). | |
21 | For an overview of @sc{mips} assembly conventions, see ``Appendix D: | |
22 | Assembly Language Programming'' in the same work. | |
252b5132 RH |
23 | |
24 | @menu | |
25 | * MIPS Opts:: Assembler options | |
26 | * MIPS Object:: ECOFF object code | |
252b5132 | 27 | * MIPS ISA:: Directives to override the ISA level |
aed1a261 | 28 | * MIPS symbol sizes:: Directives to override the size of symbols |
252b5132 RH |
29 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
30 | * MIPS insn:: Directive to mark data as an instruction | |
31 | * MIPS option stack:: Directives to save and restore options | |
0eb7102d AJ |
32 | * MIPS ASE instruction generation overrides:: Directives to control |
33 | generation of MIPS ASE instructions | |
037b32b9 | 34 | * MIPS floating-point:: Directives to override floating-point options |
7c31ae13 | 35 | * MIPS Syntax:: MIPS specific syntactical considerations |
252b5132 RH |
36 | @end menu |
37 | ||
38 | @node MIPS Opts | |
39 | @section Assembler options | |
40 | ||
41 | The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these | |
42 | special options: | |
43 | ||
44 | @table @code | |
45 | @cindex @code{-G} option (MIPS) | |
46 | @item -G @var{num} | |
47 | This option sets the largest size of an object that can be referenced | |
48 | implicitly with the @code{gp} register. It is only accepted for targets | |
49 | that use @sc{ecoff} format. The default value is 8. | |
50 | ||
51 | @cindex @code{-EB} option (MIPS) | |
52 | @cindex @code{-EL} option (MIPS) | |
53 | @cindex MIPS big-endian output | |
54 | @cindex MIPS little-endian output | |
55 | @cindex big-endian output, MIPS | |
56 | @cindex little-endian output, MIPS | |
57 | @item -EB | |
58 | @itemx -EL | |
59 | Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or | |
60 | little-endian output at run time (unlike the other @sc{gnu} development | |
61 | tools, which must be configured for one or the other). Use @samp{-EB} | |
62 | to select big-endian output, and @samp{-EL} for little-endian. | |
63 | ||
0c000745 RS |
64 | @item -KPIC |
65 | @cindex PIC selection, MIPS | |
66 | @cindex @option{-KPIC} option, MIPS | |
67 | Generate SVR4-style PIC. This option tells the assembler to generate | |
68 | SVR4-style position-independent macro expansions. It also tells the | |
69 | assembler to mark the output file as PIC. | |
70 | ||
71 | @item -mvxworks-pic | |
72 | @cindex @option{-mvxworks-pic} option, MIPS | |
73 | Generate VxWorks PIC. This option tells the assembler to generate | |
74 | VxWorks-style position-independent macro expansions. | |
75 | ||
252b5132 RH |
76 | @cindex MIPS architecture options |
77 | @item -mips1 | |
78 | @itemx -mips2 | |
79 | @itemx -mips3 | |
80 | @itemx -mips4 | |
b1929900 | 81 | @itemx -mips5 |
e7af610e | 82 | @itemx -mips32 |
af7ee8bf | 83 | @itemx -mips32r2 |
84ea6cf2 | 84 | @itemx -mips64 |
5f74bc13 | 85 | @itemx -mips64r2 |
252b5132 RH |
86 | Generate code for a particular MIPS Instruction Set Architecture level. |
87 | @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, | |
88 | @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the | |
84ea6cf2 | 89 | @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and |
5f74bc13 CD |
90 | @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, |
91 | @samp{-mips64}, and @samp{-mips64r2} | |
92 | correspond to generic | |
93 | @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, | |
94 | and @sc{MIPS64 Release 2} | |
95 | ISA processors, respectively. You can also switch | |
584da044 | 96 | instruction sets during the assembly; see @ref{MIPS ISA, Directives to |
ec68c924 | 97 | override the ISA level}. |
252b5132 | 98 | |
6349b5f4 | 99 | @item -mgp32 |
ca4e0257 RS |
100 | @itemx -mfp32 |
101 | Some macros have different expansions for 32-bit and 64-bit registers. | |
102 | The register sizes are normally inferred from the ISA and ABI, but these | |
103 | flags force a certain group of registers to be treated as 32 bits wide at | |
104 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
105 | and @samp{-mfp32} controls the size of floating-point registers. | |
106 | ||
ad3fea08 TS |
107 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
108 | of registers to be changed for parts of an object. The default value is | |
109 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
110 | ||
ca4e0257 RS |
111 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
112 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
113 | save the 32-bit registers on a context switch, so it is essential never | |
114 | to use the 64-bit registers. | |
6349b5f4 AH |
115 | |
116 | @item -mgp64 | |
ad3fea08 TS |
117 | @itemx -mfp64 |
118 | Assume that 64-bit registers are available. This is provided in the | |
119 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. | |
120 | ||
121 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size | |
122 | of registers to be changed for parts of an object. The default value is | |
123 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
6349b5f4 | 124 | |
252b5132 RH |
125 | @item -mips16 |
126 | @itemx -no-mips16 | |
127 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
ad3fea08 | 128 | @code{.set mips16} at the start of the assembly file. @samp{-no-mips16} |
252b5132 RH |
129 | turns off this option. |
130 | ||
df58fc94 RS |
131 | @item -mmicromips |
132 | @itemx -mno-micromips | |
133 | Generate code for the microMIPS processor. This is equivalent to putting | |
134 | @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips} | |
135 | turns off this option. This is equivalent to putting @code{.set nomicromips} | |
136 | at the start of the assembly file. | |
137 | ||
e16bfa71 TS |
138 | @item -msmartmips |
139 | @itemx -mno-smartmips | |
140 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which | |
141 | provides a number of new instructions which target smartcard and | |
142 | cryptographic applications. This is equivalent to putting | |
ad3fea08 | 143 | @code{.set smartmips} at the start of the assembly file. |
e16bfa71 TS |
144 | @samp{-mno-smartmips} turns off this option. |
145 | ||
1f25f5d3 CD |
146 | @item -mips3d |
147 | @itemx -no-mips3d | |
148 | Generate code for the MIPS-3D Application Specific Extension. | |
149 | This tells the assembler to accept MIPS-3D instructions. | |
150 | @samp{-no-mips3d} turns off this option. | |
151 | ||
deec1734 CD |
152 | @item -mdmx |
153 | @itemx -no-mdmx | |
154 | Generate code for the MDMX Application Specific Extension. | |
155 | This tells the assembler to accept MDMX instructions. | |
156 | @samp{-no-mdmx} turns off this option. | |
157 | ||
2ef2b9ae CF |
158 | @item -mdsp |
159 | @itemx -mno-dsp | |
8b082fb1 TS |
160 | Generate code for the DSP Release 1 Application Specific Extension. |
161 | This tells the assembler to accept DSP Release 1 instructions. | |
2ef2b9ae CF |
162 | @samp{-mno-dsp} turns off this option. |
163 | ||
8b082fb1 TS |
164 | @item -mdspr2 |
165 | @itemx -mno-dspr2 | |
166 | Generate code for the DSP Release 2 Application Specific Extension. | |
167 | This option implies -mdsp. | |
168 | This tells the assembler to accept DSP Release 2 instructions. | |
169 | @samp{-mno-dspr2} turns off this option. | |
170 | ||
ef2e4d86 CF |
171 | @item -mmt |
172 | @itemx -mno-mt | |
173 | Generate code for the MT Application Specific Extension. | |
174 | This tells the assembler to accept MT instructions. | |
175 | @samp{-mno-mt} turns off this option. | |
176 | ||
dec0624d MR |
177 | @item -mmcu |
178 | @itemx -mno-mcu | |
179 | Generate code for the MCU Application Specific Extension. | |
180 | This tells the assembler to accept MCU instructions. | |
181 | @samp{-mno-mcu} turns off this option. | |
182 | ||
b015e599 AP |
183 | @item -mvirt |
184 | @itemx -mno-virt | |
185 | Generate code for the Virtualization Application Specific Extension. | |
186 | This tells the assembler to accept Virtualization instructions. | |
187 | @samp{-mno-virt} turns off this option. | |
188 | ||
6b76fefe | 189 | @item -mfix7000 |
9ee72ff1 | 190 | @itemx -mno-fix7000 |
6b76fefe CM |
191 | Cause nops to be inserted if the read of the destination register |
192 | of an mfhi or mflo instruction occurs in the following two instructions. | |
193 | ||
c67a084a NC |
194 | @item -mfix-loongson2f-jump |
195 | @itemx -mno-fix-loongson2f-jump | |
196 | Eliminate instruction fetch from outside 256M region to work around the | |
197 | Loongson2F @samp{jump} instructions. Without it, under extreme cases, | |
198 | the kernel may crash. The issue has been solved in latest processor | |
199 | batches, but this fix has no side effect to them. | |
200 | ||
201 | @item -mfix-loongson2f-nop | |
202 | @itemx -mno-fix-loongson2f-nop | |
203 | Replace nops by @code{or at,at,zero} to work around the Loongson2F | |
204 | @samp{nop} errata. Without it, under extreme cases, cpu might | |
205 | deadlock. The issue has been solved in latest loongson2f batches, but | |
206 | this fix has no side effect to them. | |
207 | ||
d766e8ec | 208 | @item -mfix-vr4120 |
2babba43 | 209 | @itemx -mno-fix-vr4120 |
d766e8ec RS |
210 | Insert nops to work around certain VR4120 errata. This option is |
211 | intended to be used on GCC-generated code: it is not designed to catch | |
212 | all problems in hand-written assembler code. | |
60b63b72 | 213 | |
11db99f8 | 214 | @item -mfix-vr4130 |
2babba43 | 215 | @itemx -mno-fix-vr4130 |
11db99f8 RS |
216 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
217 | ||
6a32d874 | 218 | @item -mfix-24k |
45e279f5 | 219 | @itemx -mno-fix-24k |
6a32d874 CM |
220 | Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. |
221 | ||
d954098f DD |
222 | @item -mfix-cn63xxp1 |
223 | @itemx -mno-fix-cn63xxp1 | |
224 | Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around | |
225 | certain CN63XXP1 errata. | |
226 | ||
252b5132 RH |
227 | @item -m4010 |
228 | @itemx -no-m4010 | |
229 | Generate code for the LSI @sc{r4010} chip. This tells the assembler to | |
230 | accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, | |
231 | etc.), and to not schedule @samp{nop} instructions around accesses to | |
232 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
233 | option. | |
234 | ||
235 | @item -m4650 | |
236 | @itemx -no-m4650 | |
237 | Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept | |
238 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} | |
239 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
240 | @samp{-no-m4650} turns off this option. | |
241 | ||
a4ac1c42 | 242 | @item -m3900 |
252b5132 RH |
243 | @itemx -no-m3900 |
244 | @itemx -m4100 | |
245 | @itemx -no-m4100 | |
246 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
247 | @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions | |
248 | specific to that chip, and to schedule for that chip's hazards. | |
249 | ||
ec68c924 | 250 | @item -march=@var{cpu} |
252b5132 RH |
251 | Generate code for a particular MIPS cpu. It is exactly equivalent to |
252 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} | |
253 | understood. Valid @var{cpu} value are: | |
254 | ||
255 | @quotation | |
256 | 2000, | |
257 | 3000, | |
258 | 3900, | |
259 | 4000, | |
260 | 4010, | |
261 | 4100, | |
262 | 4111, | |
60b63b72 RS |
263 | vr4120, |
264 | vr4130, | |
265 | vr4181, | |
252b5132 RH |
266 | 4300, |
267 | 4400, | |
268 | 4600, | |
269 | 4650, | |
270 | 5000, | |
b946ec34 NC |
271 | rm5200, |
272 | rm5230, | |
273 | rm5231, | |
274 | rm5261, | |
275 | rm5721, | |
60b63b72 RS |
276 | vr5400, |
277 | vr5500, | |
252b5132 | 278 | 6000, |
b946ec34 | 279 | rm7000, |
252b5132 | 280 | 8000, |
963ac363 | 281 | rm9000, |
e7af610e | 282 | 10000, |
18ae5d72 | 283 | 12000, |
3aa3176b TS |
284 | 14000, |
285 | 16000, | |
ad3fea08 TS |
286 | 4kc, |
287 | 4km, | |
288 | 4kp, | |
289 | 4ksc, | |
290 | 4kec, | |
291 | 4kem, | |
292 | 4kep, | |
293 | 4ksd, | |
294 | m4k, | |
295 | m4kp, | |
b5503c7b MR |
296 | m14k, |
297 | m14kc, | |
7a795ef4 MR |
298 | m14ke, |
299 | m14kec, | |
ad3fea08 | 300 | 24kc, |
0fdf1951 | 301 | 24kf2_1, |
ad3fea08 | 302 | 24kf, |
0fdf1951 | 303 | 24kf1_1, |
ad3fea08 | 304 | 24kec, |
0fdf1951 | 305 | 24kef2_1, |
ad3fea08 | 306 | 24kef, |
0fdf1951 | 307 | 24kef1_1, |
ad3fea08 | 308 | 34kc, |
0fdf1951 | 309 | 34kf2_1, |
ad3fea08 | 310 | 34kf, |
0fdf1951 | 311 | 34kf1_1, |
711eefe4 | 312 | 34kn, |
f281862d | 313 | 74kc, |
0fdf1951 | 314 | 74kf2_1, |
f281862d | 315 | 74kf, |
0fdf1951 RS |
316 | 74kf1_1, |
317 | 74kf3_2, | |
30f8113a SL |
318 | 1004kc, |
319 | 1004kf2_1, | |
320 | 1004kf, | |
321 | 1004kf1_1, | |
ad3fea08 TS |
322 | 5kc, |
323 | 5kf, | |
324 | 20kc, | |
325 | 25kf, | |
82100185 | 326 | sb1, |
350cc38d MS |
327 | sb1a, |
328 | loongson2e, | |
037b32b9 | 329 | loongson2f, |
fd503541 | 330 | loongson3a, |
52b6b6b9 | 331 | octeon, |
dd6a37e7 | 332 | octeon+, |
432233b3 | 333 | octeon2, |
55a36193 MK |
334 | xlr, |
335 | xlp | |
252b5132 RH |
336 | @end quotation |
337 | ||
0fdf1951 RS |
338 | For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are |
339 | accepted as synonyms for @samp{@var{n}f1_1}. These values are | |
340 | deprecated. | |
341 | ||
ec68c924 EC |
342 | @item -mtune=@var{cpu} |
343 | Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are | |
344 | identical to @samp{-march=@var{cpu}}. | |
345 | ||
316f5878 RS |
346 | @item -mabi=@var{abi} |
347 | Record which ABI the source code uses. The recognized arguments | |
348 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
252b5132 | 349 | |
aed1a261 RS |
350 | @item -msym32 |
351 | @itemx -mno-sym32 | |
352 | @cindex -msym32 | |
353 | @cindex -mno-sym32 | |
354 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to | |
355 | the beginning of the assembler input. @xref{MIPS symbol sizes}. | |
356 | ||
252b5132 RH |
357 | @cindex @code{-nocpp} ignored (MIPS) |
358 | @item -nocpp | |
359 | This option is ignored. It is accepted for command-line compatibility with | |
360 | other assemblers, which use it to turn off C style preprocessing. With | |
361 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
362 | @sc{gnu} assembler itself never runs the C preprocessor. | |
363 | ||
037b32b9 AN |
364 | @item -msoft-float |
365 | @itemx -mhard-float | |
366 | Disable or enable floating-point instructions. Note that by default | |
367 | floating-point instructions are always allowed even with CPU targets | |
368 | that don't have support for these instructions. | |
369 | ||
370 | @item -msingle-float | |
371 | @itemx -mdouble-float | |
372 | Disable or enable double-precision floating-point operations. Note | |
373 | that by default double-precision floating-point operations are always | |
374 | allowed even with CPU targets that don't have support for these | |
375 | operations. | |
376 | ||
119d663a NC |
377 | @item --construct-floats |
378 | @itemx --no-construct-floats | |
119d663a NC |
379 | The @code{--no-construct-floats} option disables the construction of |
380 | double width floating point constants by loading the two halves of the | |
381 | value into the two single width floating point registers that make up | |
382 | the double width register. This feature is useful if the processor | |
383 | support the FR bit in its status register, and this bit is known (by | |
384 | the programmer) to be set. This bit prevents the aliasing of the double | |
385 | width register by the single width registers. | |
386 | ||
63bf5651 | 387 | By default @code{--construct-floats} is selected, allowing construction |
119d663a NC |
388 | of these floating point constants. |
389 | ||
3bf0dbfb MR |
390 | @item --relax-branch |
391 | @itemx --no-relax-branch | |
392 | The @samp{--relax-branch} option enables the relaxation of out-of-range | |
393 | branches. Any branches whose target cannot be reached directly are | |
394 | converted to a small instruction sequence including an inverse-condition | |
395 | branch to the physically next instruction, and a jump to the original | |
396 | target is inserted between the two instructions. In PIC code the jump | |
397 | will involve further instructions for address calculation. | |
398 | ||
399 | The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, | |
400 | @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from | |
401 | relaxation, because they have no complementing counterparts. They could | |
402 | be relaxed with the use of a longer sequence involving another branch, | |
403 | however this has not been implemented and if their target turns out of | |
404 | reach, they produce an error even if branch relaxation is enabled. | |
405 | ||
406 | Also no @sc{mips16} branches are ever relaxed. | |
407 | ||
408 | By default @samp{--no-relax-branch} is selected, causing any out-of-range | |
409 | branches to produce an error. | |
410 | ||
252b5132 RH |
411 | @item --trap |
412 | @itemx --no-break | |
413 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
414 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
415 | @code{@value{AS}} automatically macro expands certain division and | |
416 | multiplication instructions to check for overflow and division by zero. This | |
417 | option causes @code{@value{AS}} to generate code to take a trap exception | |
418 | rather than a break exception when an error is detected. The trap instructions | |
419 | are only supported at Instruction Set Architecture level 2 and higher. | |
420 | ||
421 | @item --break | |
422 | @itemx --no-trap | |
423 | Generate code to take a break exception rather than a trap exception when an | |
424 | error is detected. This is the default. | |
63486801 | 425 | |
dcd410fe RO |
426 | @item -mpdr |
427 | @itemx -mno-pdr | |
428 | Control generation of @code{.pdr} sections. Off by default on IRIX, on | |
429 | elsewhere. | |
aa6975fb ILT |
430 | |
431 | @item -mshared | |
432 | @itemx -mno-shared | |
433 | When generating code using the Unix calling conventions (selected by | |
434 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code | |
435 | which can go into a shared library. The @samp{-mno-shared} option | |
436 | tells gas to generate code which uses the calling convention, but can | |
437 | not go into a shared library. The resulting code is slightly more | |
438 | efficient. This option only affects the handling of the | |
439 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. | |
252b5132 RH |
440 | @end table |
441 | ||
442 | @node MIPS Object | |
443 | @section MIPS ECOFF object code | |
444 | ||
445 | @cindex ECOFF sections | |
446 | @cindex MIPS ECOFF sections | |
447 | Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections | |
448 | besides the usual @code{.text}, @code{.data} and @code{.bss}. The | |
449 | additional sections are @code{.rdata}, used for read-only data, | |
450 | @code{.sdata}, used for small data, and @code{.sbss}, used for small | |
451 | common objects. | |
452 | ||
453 | @cindex small objects, MIPS ECOFF | |
454 | @cindex @code{gp} register, MIPS | |
455 | When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) | |
456 | register to form the address of a ``small object''. Any object in the | |
457 | @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. | |
458 | For external objects, or for objects in the @code{.bss} section, you can use | |
459 | the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via | |
460 | @code{$gp}; the default value is 8, meaning that a reference to any object | |
461 | eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to | |
462 | @code{@value{AS}} prevents it from using the @code{$gp} register on the basis | |
463 | of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} | |
464 | or @code{sbss} in any case). The size of an object in the @code{.bss} section | |
465 | is set by the @code{.comm} or @code{.lcomm} directive that defines it. The | |
466 | size of an external object may be set with the @code{.extern} directive. For | |
467 | example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes | |
468 | in length, whie leaving @code{sym} otherwise undefined. | |
469 | ||
470 | Using small @sc{ecoff} objects requires linker support, and assumes that the | |
471 | @code{$gp} register is correctly initialized (normally done automatically by | |
472 | the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the | |
473 | @code{$gp} register. | |
474 | ||
aed1a261 RS |
475 | @node MIPS symbol sizes |
476 | @section Directives to override the size of symbols | |
477 | ||
478 | @cindex @code{.set sym32} | |
479 | @cindex @code{.set nosym32} | |
480 | The n64 ABI allows symbols to have any 64-bit value. Although this | |
481 | provides a great deal of flexibility, it means that some macros have | |
482 | much longer expansions than their 32-bit counterparts. For example, | |
483 | the non-PIC expansion of @samp{dla $4,sym} is usually: | |
484 | ||
485 | @smallexample | |
486 | lui $4,%highest(sym) | |
487 | lui $1,%hi(sym) | |
488 | daddiu $4,$4,%higher(sym) | |
489 | daddiu $1,$1,%lo(sym) | |
490 | dsll32 $4,$4,0 | |
491 | daddu $4,$4,$1 | |
492 | @end smallexample | |
493 | ||
494 | whereas the 32-bit expansion is simply: | |
495 | ||
496 | @smallexample | |
497 | lui $4,%hi(sym) | |
498 | daddiu $4,$4,%lo(sym) | |
499 | @end smallexample | |
500 | ||
501 | n64 code is sometimes constructed in such a way that all symbolic | |
502 | constants are known to have 32-bit values, and in such cases, it's | |
503 | preferable to use the 32-bit expansion instead of the 64-bit | |
504 | expansion. | |
505 | ||
506 | You can use the @code{.set sym32} directive to tell the assembler | |
507 | that, from this point on, all expressions of the form | |
508 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} | |
509 | have 32-bit values. For example: | |
510 | ||
511 | @smallexample | |
512 | .set sym32 | |
513 | dla $4,sym | |
514 | lw $4,sym+16 | |
515 | sw $4,sym+0x8000($4) | |
516 | @end smallexample | |
517 | ||
518 | will cause the assembler to treat @samp{sym}, @code{sym+16} and | |
519 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic | |
520 | addresses is not affected. | |
521 | ||
522 | The directive @code{.set nosym32} ends a @code{.set sym32} block and | |
523 | reverts to the normal behavior. It is also possible to change the | |
524 | symbol size using the command-line options @option{-msym32} and | |
525 | @option{-mno-sym32}. | |
526 | ||
527 | These options and directives are always accepted, but at present, | |
528 | they have no effect for anything other than n64. | |
529 | ||
252b5132 RH |
530 | @node MIPS ISA |
531 | @section Directives to override the ISA level | |
532 | ||
533 | @cindex MIPS ISA override | |
534 | @kindex @code{.set mips@var{n}} | |
535 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
536 | the @sc{mips} Instruction Set Architecture level on the fly: @code{.set | |
5f74bc13 CD |
537 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 |
538 | or 64r2. | |
071742cf | 539 | The values other than 0 make the assembler accept instructions |
584da044 NC |
540 | for the corresponding @sc{isa} level, from that point on in the |
541 | assembly. @code{.set mips@var{n}} affects not only which instructions | |
542 | are permitted, but also how certain macros are expanded. @code{.set | |
543 | mips0} restores the @sc{isa} level to its original level: either the | |
544 | level you selected with command line options, or the default for your | |
ad3fea08 | 545 | configuration. You can use this feature to permit specific @sc{mips3} |
584da044 | 546 | instructions while assembling in 32 bit mode. Use this directive with |
ec68c924 | 547 | care! |
252b5132 | 548 | |
ad3fea08 TS |
549 | @cindex MIPS CPU override |
550 | @kindex @code{.set arch=@var{cpu}} | |
551 | The @code{.set arch=@var{cpu}} directive provides even finer control. | |
552 | It changes the effective CPU target and allows the assembler to use | |
553 | instructions specific to a particular CPU. All CPUs supported by the | |
554 | @samp{-march} command line option are also selectable by this directive. | |
555 | The original value is restored by @code{.set arch=default}. | |
252b5132 | 556 | |
ad3fea08 TS |
557 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
558 | in which it will assemble instructions for the MIPS 16 processor. Use | |
559 | @code{.set nomips16} to return to normal 32 bit mode. | |
e16bfa71 | 560 | |
ec68c924 | 561 | Traditional @sc{mips} assemblers do not support this directive. |
252b5132 | 562 | |
df58fc94 RS |
563 | The directive @code{.set micromips} puts the assembler into microMIPS mode, |
564 | in which it will assemble instructions for the microMIPS processor. Use | |
565 | @code{.set nomicromips} to return to normal 32 bit mode. | |
566 | ||
567 | Traditional @sc{mips} assemblers do not support this directive. | |
568 | ||
252b5132 RH |
569 | @node MIPS autoextend |
570 | @section Directives for extending MIPS 16 bit instructions | |
571 | ||
572 | @kindex @code{.set autoextend} | |
573 | @kindex @code{.set noautoextend} | |
574 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
ad3fea08 TS |
575 | when necessary. The directive @code{.set noautoextend} will turn this |
576 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction | |
577 | must be explicitly extended with the @code{.e} modifier (e.g., | |
578 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used | |
252b5132 RH |
579 | to once again automatically extend instructions when necessary. |
580 | ||
581 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
582 | @sc{mips} assemblers do not support this directive. | |
583 | ||
584 | @node MIPS insn | |
585 | @section Directive to mark data as an instruction | |
586 | ||
587 | @kindex @code{.insn} | |
588 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
df58fc94 RS |
589 | data is actually instructions. This makes a difference in MIPS 16 and |
590 | microMIPS modes: when loading the address of a label which precedes | |
591 | instructions, @code{@value{AS}} automatically adds 1 to the value, so | |
592 | that jumping to the loaded address will do the right thing. | |
252b5132 | 593 | |
a946d7e3 NC |
594 | @kindex @code{.global} |
595 | The @code{.global} and @code{.globl} directives supported by | |
596 | @code{@value{AS}} will by default mark the symbol as pointing to a | |
597 | region of data not code. This means that, for example, any | |
598 | instructions following such a symbol will not be disassembled by | |
f746e6b9 | 599 | @code{objdump} as it will regard them as data. To change this |
a946d7e3 NC |
600 | behaviour an optional section name can be placed after the symbol name |
601 | in the @code{.global} directive. If this section exists and is known | |
602 | to be a code section, then the symbol will be marked as poiting at | |
603 | code not data. Ie the syntax for the directive is: | |
604 | ||
605 | @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, | |
606 | ||
607 | Here is a short example: | |
608 | ||
609 | @example | |
610 | .global foo .text, bar, baz .data | |
611 | foo: | |
612 | nop | |
613 | bar: | |
614 | .word 0x0 | |
615 | baz: | |
616 | .word 0x1 | |
34bca508 | 617 | |
a946d7e3 NC |
618 | @end example |
619 | ||
252b5132 RH |
620 | @node MIPS option stack |
621 | @section Directives to save and restore options | |
622 | ||
623 | @cindex MIPS option stack | |
624 | @kindex @code{.set push} | |
625 | @kindex @code{.set pop} | |
626 | The directives @code{.set push} and @code{.set pop} may be used to save | |
627 | and restore the current settings for all the options which are | |
628 | controlled by @code{.set}. The @code{.set push} directive saves the | |
629 | current settings on a stack. The @code{.set pop} directive pops the | |
630 | stack and restores the settings. | |
631 | ||
632 | These directives can be useful inside an macro which must change an | |
633 | option such as the ISA level or instruction reordering but does not want | |
634 | to change the state of the code which invoked the macro. | |
635 | ||
636 | Traditional @sc{mips} assemblers do not support these directives. | |
1f25f5d3 CD |
637 | |
638 | @node MIPS ASE instruction generation overrides | |
639 | @section Directives to control generation of MIPS ASE instructions | |
640 | ||
641 | @cindex MIPS MIPS-3D instruction generation override | |
642 | @kindex @code{.set mips3d} | |
643 | @kindex @code{.set nomips3d} | |
644 | The directive @code{.set mips3d} makes the assembler accept instructions | |
645 | from the MIPS-3D Application Specific Extension from that point on | |
646 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
647 | instructions from being accepted. | |
648 | ||
ad3fea08 TS |
649 | @cindex SmartMIPS instruction generation override |
650 | @kindex @code{.set smartmips} | |
651 | @kindex @code{.set nosmartmips} | |
652 | The directive @code{.set smartmips} makes the assembler accept | |
653 | instructions from the SmartMIPS Application Specific Extension to the | |
654 | MIPS32 @sc{isa} from that point on in the assembly. The | |
655 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from | |
656 | being accepted. | |
657 | ||
deec1734 CD |
658 | @cindex MIPS MDMX instruction generation override |
659 | @kindex @code{.set mdmx} | |
660 | @kindex @code{.set nomdmx} | |
661 | The directive @code{.set mdmx} makes the assembler accept instructions | |
662 | from the MDMX Application Specific Extension from that point on | |
663 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
664 | instructions from being accepted. | |
665 | ||
8b082fb1 | 666 | @cindex MIPS DSP Release 1 instruction generation override |
2ef2b9ae CF |
667 | @kindex @code{.set dsp} |
668 | @kindex @code{.set nodsp} | |
669 | The directive @code{.set dsp} makes the assembler accept instructions | |
8b082fb1 TS |
670 | from the DSP Release 1 Application Specific Extension from that point |
671 | on in the assembly. The @code{.set nodsp} directive prevents DSP | |
672 | Release 1 instructions from being accepted. | |
673 | ||
674 | @cindex MIPS DSP Release 2 instruction generation override | |
675 | @kindex @code{.set dspr2} | |
676 | @kindex @code{.set nodspr2} | |
677 | The directive @code{.set dspr2} makes the assembler accept instructions | |
678 | from the DSP Release 2 Application Specific Extension from that point | |
679 | on in the assembly. This dirctive implies @code{.set dsp}. The | |
680 | @code{.set nodspr2} directive prevents DSP Release 2 instructions from | |
681 | being accepted. | |
2ef2b9ae | 682 | |
ef2e4d86 CF |
683 | @cindex MIPS MT instruction generation override |
684 | @kindex @code{.set mt} | |
685 | @kindex @code{.set nomt} | |
686 | The directive @code{.set mt} makes the assembler accept instructions | |
687 | from the MT Application Specific Extension from that point on | |
688 | in the assembly. The @code{.set nomt} directive prevents MT | |
689 | instructions from being accepted. | |
690 | ||
dec0624d MR |
691 | @cindex MIPS MCU instruction generation override |
692 | @kindex @code{.set mcu} | |
693 | @kindex @code{.set nomcu} | |
694 | The directive @code{.set mcu} makes the assembler accept instructions | |
695 | from the MCU Application Specific Extension from that point on | |
696 | in the assembly. The @code{.set nomcu} directive prevents MCU | |
697 | instructions from being accepted. | |
698 | ||
b015e599 AP |
699 | @cindex Virtualization instruction generation override |
700 | @kindex @code{.set virt} | |
701 | @kindex @code{.set novirt} | |
702 | The directive @code{.set virt} makes the assembler accept instructions | |
703 | from the Virtualization Application Specific Extension from that point | |
704 | on in the assembly. The @code{.set novirt} directive prevents Virtualization | |
705 | instructions from being accepted. | |
706 | ||
1f25f5d3 | 707 | Traditional @sc{mips} assemblers do not support these directives. |
037b32b9 AN |
708 | |
709 | @node MIPS floating-point | |
710 | @section Directives to override floating-point options | |
711 | ||
712 | @cindex Disable floating-point instructions | |
713 | @kindex @code{.set softfloat} | |
714 | @kindex @code{.set hardfloat} | |
715 | The directives @code{.set softfloat} and @code{.set hardfloat} provide | |
716 | finer control of disabling and enabling float-point instructions. | |
717 | These directives always override the default (that hard-float | |
718 | instructions are accepted) or the command-line options | |
719 | (@samp{-msoft-float} and @samp{-mhard-float}). | |
720 | ||
721 | @cindex Disable single-precision floating-point operations | |
605b1dd4 NH |
722 | @kindex @code{.set singlefloat} |
723 | @kindex @code{.set doublefloat} | |
037b32b9 AN |
724 | The directives @code{.set singlefloat} and @code{.set doublefloat} |
725 | provide finer control of disabling and enabling double-precision | |
726 | float-point operations. These directives always override the default | |
727 | (that double-precision operations are accepted) or the command-line | |
728 | options (@samp{-msingle-float} and @samp{-mdouble-float}). | |
729 | ||
730 | Traditional @sc{mips} assemblers do not support these directives. | |
7c31ae13 NC |
731 | |
732 | @node MIPS Syntax | |
733 | @section Syntactical considerations for the MIPS assembler | |
734 | @menu | |
735 | * MIPS-Chars:: Special Characters | |
736 | @end menu | |
737 | ||
738 | @node MIPS-Chars | |
739 | @subsection Special Characters | |
740 | ||
741 | @cindex line comment character, MIPS | |
742 | @cindex MIPS line comment character | |
743 | The presence of a @samp{#} on a line indicates the start of a comment | |
744 | that extends to the end of the current line. | |
745 | ||
746 | If a @samp{#} appears as the first character of a line, the whole line | |
747 | is treated as a comment, but in this case the line can also be a | |
748 | logical line number directive (@pxref{Comments}) or a | |
749 | preprocessor control command (@pxref{Preprocessing}). | |
750 | ||
751 | @cindex line separator, MIPS | |
752 | @cindex statement separator, MIPS | |
753 | @cindex MIPS line separator | |
754 | The @samp{;} character can be used to separate statements on the same | |
755 | line. |