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2571583a | 1 | @c Copyright (C) 2016-2017 Free Software Foundation, Inc. |
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2 | @c This is part of the GAS anual. |
3 | @c For copying conditions, see the file as.texinfo | |
4 | @c man end | |
5 | ||
6 | @ifset GENERIC | |
7 | @page | |
8 | @node RISC-V-Dependent | |
9 | @chapter RISC-V Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter RISC-V Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex RISC-V support | |
17 | @menu | |
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18 | * RISC-V-Options:: RISC-V Options |
19 | * RISC-V-Directives:: RISC-V Directives | |
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20 | @end menu |
21 | ||
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22 | @node RISC-V-Options |
23 | @section RISC-V Options | |
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b57e49f7 | 25 | The following table lists all available RISC-V specific options. |
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26 | |
27 | @c man begin OPTIONS | |
28 | @table @gcctabopt | |
e23eba97 | 29 | |
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30 | @cindex @samp{-fpic} option, RISC-V |
31 | @item -fpic | |
b57e49f7 | 32 | @itemx -fPIC |
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33 | Generate position-independent code |
34 | ||
35 | @cindex @samp{-fno-pic} option, RISC-V | |
36 | @item -fno-pic | |
37 | Don't generate position-independent code (default) | |
38 | ||
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39 | @cindex @samp{-march=ISA} option, RISC-V |
40 | @item -march=ISA | |
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41 | Select the base isa, as specified by ISA. For example -march=rv32ima. |
42 | ||
43 | @cindex @samp{-mabi=ABI} option, RISC-V | |
44 | @item -mabi=ABI | |
45 | Selects the ABI, which is either "ilp32" or "lp64", optionally followed | |
46 | by "f", "d", or "q" to indicate single-precision, double-precision, or | |
47 | quad-precision floating-point calling convention, or none to indicate | |
48 | the soft-float calling convention. | |
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49 | |
50 | @end table | |
51 | @c man end | |
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52 | |
53 | @node RISC-V-Directives | |
54 | @cindex machine directives, RISC-V | |
55 | @cindex RISC-V machine directives | |
56 | ||
57 | @section RISC-V Directives | |
58 | ||
59 | The following table lists all available RISC-V specific directives. | |
60 | ||
61 | @table @code | |
62 | ||
63 | @cindex @code{align} directive | |
64 | @item .align @var{size-log-2} | |
65 | Align to the given boundary, with the size given as log2 the number of bytes to | |
66 | align to. | |
67 | ||
68 | @cindex Data directives | |
69 | @item .half @var{value} | |
70 | @itemx .word @var{value} | |
71 | @itemx .dword @var{value} | |
72 | Emits a half-word, word, or double-word value at the current position. | |
73 | ||
74 | @cindex DTP-relative data directives | |
75 | @item .dtprelword @var{value} | |
76 | @itemx .dtpreldword @var{value} | |
77 | Emits a DTP-relative word (or double-word) at the current position. This is | |
78 | meant to be used by the compiler in shared libraries for DWARF debug info for | |
79 | thread local variables. | |
80 | ||
81 | @cindex BSS directive | |
82 | @item .bss | |
83 | Sets the current section to the BSS section. | |
84 | ||
85 | @cindex LEB128 directives | |
86 | @item .uleb128 @var{value} | |
87 | @itemx .sleb128 @var{value} | |
88 | Emits a signed or unsigned LEB128 value at the current position. This only | |
89 | accepts constant expressions, because symbol addresses can change with | |
90 | relaxation, and we don't support relocations to modify LEB128 values at link | |
91 | time. | |
92 | ||
93 | @cindex Option directive | |
94 | @cindex @code{option} directive | |
95 | @item .option @var{argument} | |
96 | Modifies RISC-V specific assembler options inline with the assembly code. | |
97 | This is used when particular instruction sequences must be assembled with a | |
98 | specific set of options. For example, since we relax addressing sequences to | |
99 | shorter GP-relative sequences when possible the initial load of GP must not be | |
100 | relaxed and should be emitted as something like | |
101 | ||
102 | @smallexample | |
103 | .option push | |
104 | .option norelax | |
105 | la gp, __global_pointer$ | |
106 | .option pop | |
107 | @end smallexample | |
108 | ||
109 | in order to produce after linker relaxation the expected | |
110 | ||
111 | @smallexample | |
112 | auipc gp, %pcrel_hi(__global_pointer$) | |
113 | addi gp, gp, %pcrel_lo(__global_pointer$) | |
114 | @end smallexample | |
115 | ||
116 | instead of just | |
117 | ||
118 | @smallexample | |
119 | addi gp, gp, 0 | |
120 | @end smallexample | |
121 | ||
122 | It's not expected that options are changed in this manner during regular use, | |
123 | but there are a handful of esoteric cases like the one above where users need | |
124 | to disable particular features of the assembler for particular code sequences. | |
125 | The complete list of option arguments is shown below: | |
126 | ||
127 | @table @code | |
128 | @item push | |
129 | @itemx pop | |
130 | Pushes or pops the current option stack. These should be used whenever | |
131 | changing an option in line with assembly code in order to ensure the user's | |
132 | command-line options are respected for the bulk of the file being assembled. | |
133 | ||
134 | @item rvc | |
135 | @itemx norvc | |
136 | Enables or disables the generation of compressed instructions. Instructions | |
137 | are opportunistically compressed by the RISC-V assembler when possible, but | |
138 | sometimes this behavior is not desirable. | |
139 | ||
140 | @item pic | |
141 | @itemx nopic | |
142 | Enables or disables position-independent code generation. Unless you really | |
143 | know what you're doing, this should only be at the top of a file. | |
144 | ||
145 | @item relax | |
146 | @itemx norelax | |
147 | Enables or disables relaxation. The RISC-V assembler and linker | |
148 | opportunistically relax some code sequences, but sometimes this behavior is not | |
149 | desirable. | |
150 | @end table | |
151 | ||
152 | @end table |