[deliverable/binutils-gdb.git] / gas / doc / c-sh.texi

@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH-Dependent
@chapter Renesas / SuperH SH Dependent Features

@cindex SH support
@menu
* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes
@end menu

@node SH Options
@section Options

@cindex SH options
@cindex options, SH
@code{@value{AS}} has following command-line options for the Renesas
(formerly Hitachi) / SuperH SH family.

@table @code
@kindex -little
@kindex -big
@kindex -relax
@kindex -small
@kindex -dsp

@item -little
Generate little endian code.

@item -big
Generate big endian code.

@item -relax
Alter jump instructions for long displacements.

@item -small
Align sections to 4 byte boundaries, not 16.

@item -dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.

@item -isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
@item -isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item -isa=fp
Enable sh2e, sh3e, sh4, and sh4a insn sets.
@item -isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.

@end table

@node SH Syntax
@section Syntax

@menu
* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes
@end menu

@node SH-Chars
@subsection Special Characters

@cindex line comment character, SH
@cindex SH line comment character
@samp{!} is the line comment character.

@cindex line separator, SH
@cindex statement separator, SH
@cindex SH line separator
You can use @samp{;} instead of a newline to separate statements.

@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.

@node SH-Regs
@subsection Register Names

@cindex SH registers
@cindex registers, SH
You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
and @samp{r15} to refer to the SH registers.

The SH also has these control registers:

@table @code
@item pr
procedure register (holds return address)

@item pc
program counter

@item mach
@itemx macl
high and low multiply accumulator registers

@item sr
status register

@item gbr
global base register

@item vbr
vector base register (for interrupt vectors)
@end table

@node SH-Addressing
@subsection Addressing Modes

@cindex addressing modes, SH
@cindex SH addressing modes
@code{@value{AS}} understands the following addressing modes for the SH.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.

@table @code
@item R@var{n}
Register direct

@item @@R@var{n}
Register indirect

@item @@-R@var{n}
Register indirect with pre-decrement

@item @@R@var{n}+
Register indirect with post-increment

@item @@(@var{disp}, R@var{n})
Register indirect with displacement

@item @@(R0, R@var{n})
Register indexed

@item @@(@var{disp}, GBR)
@code{GBR} offset

@item @@(R0, GBR)
GBR indexed

@item @var{addr}
@itemx @@(@var{disp}, PC)
PC relative address (for branch or for addressing memory).  The
@code{@value{AS}} implementation allows you to use the simpler form
@var{addr} anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.

@item #@var{imm}
Immediate data
@end table

@node SH Floating Point
@section Floating Point

@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
The SH family has no hardware floating point, but the @code{.float}
directive generates @sc{ieee} floating-point numbers for compatibility
with other development tools.

@node SH Directives
@section SH Machine Directives

@cindex SH machine directives
@cindex machine directives, SH
@cindex @code{uaword} directive, SH
@cindex @code{ualong} directive, SH

@table @code
@item uaword
@itemx ualong
@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
@code{.long} directive is used.  You may use @code{.uaword} or
@code{.ualong} to indicate that the value is intentionally misaligned.
@end table

@node SH Opcodes
@section Opcodes

@cindex SH opcode summary
@cindex opcode summary, SH
@cindex mnemonics, SH
@cindex instruction summary, SH
For detailed information on the SH machine instruction set, see
@cite{SH-Microcomputer User's Manual} (Renesas) or
@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).

@code{@value{AS}} implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because @code{@value{AS}} supports a simpler form of PC-relative
addressing, you may simply write (for example)

@example
mov.l  bar,r0
@end example

@noindent
where other assemblers might require an explicit displacement to
@code{bar} from the program counter:

@example
mov.l  @@(@var{disp}, PC)
@end example

@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook.  See comments below "@set SMALL" near top of this file.

Here is a summary of SH opcodes:

@page
@smallexample
@i{Legend:}
Rn        @r{a numbered register}
Rm        @r{another numbered register}
#imm      @r{immediate data}
disp      @r{displacement}
disp8     @r{8-bit displacement}
disp12    @r{12-bit displacement}

add #imm,Rn                    lds.l @@Rn+,PR              
add Rm,Rn                      mac.w @@Rm+,@@Rn+           
addc Rm,Rn                     mov #imm,Rn                 
addv Rm,Rn                     mov Rm,Rn                   
and #imm,R0                    mov.b Rm,@@(R0,Rn)          
and Rm,Rn                      mov.b Rm,@@-Rn              
and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn               
bf disp8                       mov.b @@(disp,Rm),R0        
bra disp12                     mov.b @@(disp,GBR),R0       
bsr disp12                     mov.b @@(R0,Rm),Rn          
bt disp8                       mov.b @@Rm+,Rn              
clrmac                         mov.b @@Rm,Rn               
clrt                           mov.b R0,@@(disp,Rm)        
cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)       
cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)        
cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)          
cmp/gt Rm,Rn                   mov.l Rm,@@-Rn              
cmp/hi Rm,Rn                   mov.l Rm,@@Rn               
cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm        
cmp/pl Rn                      mov.l @@(disp,GBR),R0       
cmp/pz Rn                      mov.l @@(disp,PC),Rn        
cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn          
div0s Rm,Rn                    mov.l @@Rm+,Rn              
div0u                          mov.l @@Rm,Rn               
div1 Rm,Rn                     mov.l R0,@@(disp,GBR)       
exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)          
exts.w Rm,Rn                   mov.w Rm,@@-Rn              
extu.b Rm,Rn                   mov.w Rm,@@Rn               
extu.w Rm,Rn                   mov.w @@(disp,Rm),R0        
jmp @@Rn                        mov.w @@(disp,GBR),R0       
jsr @@Rn                        mov.w @@(disp,PC),Rn        
ldc Rn,GBR                     mov.w @@(R0,Rm),Rn          
ldc Rn,SR                      mov.w @@Rm+,Rn              
ldc Rn,VBR                     mov.w @@Rm,Rn               
ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)        
ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)       
ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0         
lds Rn,MACH                    movt Rn                     
lds Rn,MACL                    muls Rm,Rn                  
lds Rn,PR                      mulu Rm,Rn                  
lds.l @@Rn+,MACH                neg Rm,Rn                   
lds.l @@Rn+,MACL                negc Rm,Rn                  
@page
nop                            stc VBR,Rn                
not Rm,Rn                      stc.l GBR,@@-Rn           
or #imm,R0                     stc.l SR,@@-Rn            
or Rm,Rn                       stc.l VBR,@@-Rn           
or.b #imm,@@(R0,GBR)            sts MACH,Rn               
rotcl Rn                       sts MACL,Rn               
rotcr Rn                       sts PR,Rn                 
rotl Rn                        sts.l MACH,@@-Rn          
rotr Rn                        sts.l MACL,@@-Rn          
rte                            sts.l PR,@@-Rn            
rts                            sub Rm,Rn                 
sett                           subc Rm,Rn                
shal Rn                        subv Rm,Rn                
shar Rn                        swap.b Rm,Rn              
shll Rn                        swap.w Rm,Rn              
shll16 Rn                      tas.b @@Rn                
shll2 Rn                       trapa #imm                
shll8 Rn                       tst #imm,R0               
shlr Rn                        tst Rm,Rn                 
shlr16 Rn                      tst.b #imm,@@(R0,GBR)     
shlr2 Rn                       xor #imm,R0               
shlr8 Rn                       xor Rm,Rn                 
sleep                          xor.b #imm,@@(R0,GBR)     
stc GBR,Rn                     xtrct Rm,Rn               
stc SR,Rn
@end smallexample
@end ifset

@ifset Renesas-all
@ifclear GENERIC
@raisesections
@end ifclear
@end ifset
Commit	Line	Data
7649aa50	1	@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001
f7e42eb4	2	@c Free Software Foundation, Inc.
252b5132 RH	3	@c This is part of the GAS manual.
	4	@c For copying conditions, see the file as.texinfo.
	5	@page
	6	@node SH-Dependent
ef230218	7	@chapter Renesas / SuperH SH Dependent Features
252b5132 RH	8
	9	@cindex SH support
	10	@menu
	11	* SH Options:: Options
	12	* SH Syntax:: Syntax
	13	* SH Floating Point:: Floating Point
	14	* SH Directives:: SH Machine Directives
	15	* SH Opcodes:: Opcodes
	16	@end menu
	17
	18	@node SH Options
	19	@section Options
	20
7649aa50 NC	21	@cindex SH options
7649aa50 NC	22	@cindex options, SH
c2dcd04e	23	@code{@value{AS}} has following command-line options for the Renesas
ef230218	24	(formerly Hitachi) / SuperH SH family.
252b5132	25
7649aa50 NC	26	@table @code
	27	@kindex -little
	28	@kindex -big
	29	@kindex -relax
	30	@kindex -small
	31	@kindex -dsp
	32
	33	@item -little
	34	Generate little endian code.
	35
	36	@item -big
	37	Generate big endian code.
	38
	39	@item -relax
	40	Alter jump instructions for long displacements.
	41
	42	@item -small
	43	Align sections to 4 byte boundaries, not 16.
	44
	45	@item -dsp
	46	Enable sh-dsp insns, and disable sh3e / sh4 insns.
	47
88da98f3 MS	48	@item -isa=sh4 \| sh4a
	49	Specify the sh4 or sh4a instruction set.
	50	@item -isa=dsp
	51	Enable sh-dsp insns, and disable sh3e / sh4 insns.
	52	@item -isa=fp
	53	Enable sh2e, sh3e, sh4, and sh4a insn sets.
	54	@item -isa=all
	55	Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
	56
7649aa50 NC	57	@end table
7649aa50 NC	58
252b5132 RH	59	@node SH Syntax
	60	@section Syntax
	61
	62	@menu
	63	* SH-Chars:: Special Characters
	64	* SH-Regs:: Register Names
	65	* SH-Addressing:: Addressing Modes
	66	@end menu
	67
	68	@node SH-Chars
	69	@subsection Special Characters
	70
	71	@cindex line comment character, SH
	72	@cindex SH line comment character
	73	@samp{!} is the line comment character.
	74
	75	@cindex line separator, SH
	76	@cindex statement separator, SH
	77	@cindex SH line separator
	78	You can use @samp{;} instead of a newline to separate statements.
	79
	80	@cindex symbol names, @samp{$} in
	81	@cindex @code{$} in symbol names
	82	Since @samp{$} has no special meaning, you may use it in symbol names.
	83
	84	@node SH-Regs
	85	@subsection Register Names
	86
	87	@cindex SH registers
	88	@cindex registers, SH
	89	You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
	90	@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
	91	@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
	92	and @samp{r15} to refer to the SH registers.
	93
	94	The SH also has these control registers:
	95
	96	@table @code
	97	@item pr
	98	procedure register (holds return address)
	99
	100	@item pc
	101	program counter
	102
	103	@item mach
	104	@itemx macl
	105	high and low multiply accumulator registers
	106
	107	@item sr
	108	status register
	109
	110	@item gbr
	111	global base register
	112
	113	@item vbr
	114	vector base register (for interrupt vectors)
	115	@end table
	116
	117	@node SH-Addressing
	118	@subsection Addressing Modes
	119
	120	@cindex addressing modes, SH
	121	@cindex SH addressing modes
	122	@code{@value{AS}} understands the following addressing modes for the SH.
123	@code{R@var{n}} in the following refers to any of the numbered
124	registers, but @emph{not} the control registers.
125
126	@table @code
127	@item R@var{n}
128	Register direct
129
130	@item @@R@var{n}
131	Register indirect
132
133	@item @@-R@var{n}
134	Register indirect with pre-decrement
135
136	@item @@R@var{n}+
137	Register indirect with post-increment
138
139	@item @@(@var{disp}, R@var{n})
140	Register indirect with displacement
141
142	@item @@(R0, R@var{n})
143	Register indexed
144
145	@item @@(@var{disp}, GBR)
146	@code{GBR} offset
147
148	@item @@(R0, GBR)
149	GBR indexed
150
151	@item @var{addr}
152	@itemx @@(@var{disp}, PC)
153	PC relative address (for branch or for addressing memory). The
154	@code{@value{AS}} implementation allows you to use the simpler form
155	@var{addr} anywhere a PC relative address is called for; the alternate
156	form is supported for compatibility with other assemblers.
157
158	@item #@var{imm}
159	Immediate data
160	@end table
161
162	@node SH Floating Point
163	@section Floating Point
164
165	@cindex floating point, SH (@sc{ieee})
166	@cindex SH floating point (@sc{ieee})
167	The SH family has no hardware floating point, but the @code{.float}
168	directive generates @sc{ieee} floating-point numbers for compatibility
169	with other development tools.
170
171	@node SH Directives
172	@section SH Machine Directives
173
174	@cindex SH machine directives
175	@cindex machine directives, SH
176	@cindex @code{uaword} directive, SH
177	@cindex @code{ualong} directive, SH
178
179	@table @code
180	@item uaword
181	@itemx ualong
182	@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
183	@code{.long} directive is used. You may use @code{.uaword} or
184	@code{.ualong} to indicate that the value is intentionally misaligned.
185	@end table
186
187	@node SH Opcodes
188	@section Opcodes
189
190	@cindex SH opcode summary
191	@cindex opcode summary, SH
192	@cindex mnemonics, SH
193	@cindex instruction summary, SH
194	For detailed information on the SH machine instruction set, see
ef230218 JR	195	@cite{SH-Microcomputer User's Manual} (Renesas) or
	196	@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
	197	@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
252b5132 RH	198
	199	@code{@value{AS}} implements all the standard SH opcodes. No additional
	200	pseudo-instructions are needed on this family. Note, however, that
	201	because @code{@value{AS}} supports a simpler form of PC-relative
	202	addressing, you may simply write (for example)
	203
	204	@example
	205	mov.l bar,r0
	206	@end example
	207
	208	@noindent
	209	where other assemblers might require an explicit displacement to
	210	@code{bar} from the program counter:
	211
	212	@example
	213	mov.l @@(@var{disp}, PC)
	214	@end example
	215
	216	@ifset SMALL
	217	@c this table, due to the multi-col faking and hardcoded order, looks silly
	218	@c except in smallbook. See comments below "@set SMALL" near top of this file.
	219
	220	Here is a summary of SH opcodes:
	221
	222	@page
	223	@smallexample
	224	@i{Legend:}
	225	Rn @r{a numbered register}
	226	Rm @r{another numbered register}
	227	#imm @r{immediate data}
	228	disp @r{displacement}
	229	disp8 @r{8-bit displacement}
	230	disp12 @r{12-bit displacement}
	231
	232	add #imm,Rn lds.l @@Rn+,PR
	233	add Rm,Rn mac.w @@Rm+,@@Rn+
	234	addc Rm,Rn mov #imm,Rn
	235	addv Rm,Rn mov Rm,Rn
	236	and #imm,R0 mov.b Rm,@@(R0,Rn)
	237	and Rm,Rn mov.b Rm,@@-Rn
	238	and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
	239	bf disp8 mov.b @@(disp,Rm),R0
	240	bra disp12 mov.b @@(disp,GBR),R0
	241	bsr disp12 mov.b @@(R0,Rm),Rn
	242	bt disp8 mov.b @@Rm+,Rn
	243	clrmac mov.b @@Rm,Rn
	244	clrt mov.b R0,@@(disp,Rm)
	245	cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
	246	cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
	247	cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
	248	cmp/gt Rm,Rn mov.l Rm,@@-Rn
	249	cmp/hi Rm,Rn mov.l Rm,@@Rn
	250	cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
	251	cmp/pl Rn mov.l @@(disp,GBR),R0
	252	cmp/pz Rn mov.l @@(disp,PC),Rn
	253	cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
	254	div0s Rm,Rn mov.l @@Rm+,Rn
	255	div0u mov.l @@Rm,Rn
	256	div1 Rm,Rn mov.l R0,@@(disp,GBR)
	257	exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
	258	exts.w Rm,Rn mov.w Rm,@@-Rn
	259	extu.b Rm,Rn mov.w Rm,@@Rn
	260	extu.w Rm,Rn mov.w @@(disp,Rm),R0
	261	jmp @@Rn mov.w @@(disp,GBR),R0
262	jsr @@Rn mov.w @@(disp,PC),Rn
263	ldc Rn,GBR mov.w @@(R0,Rm),Rn
264	ldc Rn,SR mov.w @@Rm+,Rn
265	ldc Rn,VBR mov.w @@Rm,Rn
266	ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
267	ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
268	ldc.l @@Rn+,VBR mova @@(disp,PC),R0
269	lds Rn,MACH movt Rn
270	lds Rn,MACL muls Rm,Rn
271	lds Rn,PR mulu Rm,Rn
272	lds.l @@Rn+,MACH neg Rm,Rn
273	lds.l @@Rn+,MACL negc Rm,Rn
274	@page
275	nop stc VBR,Rn
276	not Rm,Rn stc.l GBR,@@-Rn
277	or #imm,R0 stc.l SR,@@-Rn
278	or Rm,Rn stc.l VBR,@@-Rn
279	or.b #imm,@@(R0,GBR) sts MACH,Rn
280	rotcl Rn sts MACL,Rn
281	rotcr Rn sts PR,Rn
282	rotl Rn sts.l MACH,@@-Rn
283	rotr Rn sts.l MACL,@@-Rn
284	rte sts.l PR,@@-Rn
285	rts sub Rm,Rn
286	sett subc Rm,Rn
287	shal Rn subv Rm,Rn
288	shar Rn swap.b Rm,Rn
289	shll Rn swap.w Rm,Rn
290	shll16 Rn tas.b @@Rn
291	shll2 Rn trapa #imm
292	shll8 Rn tst #imm,R0
293	shlr Rn tst Rm,Rn
294	shlr16 Rn tst.b #imm,@@(R0,GBR)
295	shlr2 Rn xor #imm,R0
296	shlr8 Rn xor Rm,Rn
297	sleep xor.b #imm,@@(R0,GBR)
298	stc GBR,Rn xtrct Rm,Rn
299	stc SR,Rn
300	@end smallexample
301	@end ifset
302
c2dcd04e	303	@ifset Renesas-all
252b5132 RH	304	@ifclear GENERIC
	305	@raisesections
	306	@end ifclear
	307	@end ifset
	308