Commit | Line | Data |
---|---|---|
7c31ae13 | 1 | @c Copyright 1997, 2002, 2003, 2006, 2011 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | ||
5 | @node V850-Dependent | |
6 | @chapter v850 Dependent Features | |
7 | ||
8 | @cindex V850 support | |
9 | @menu | |
10 | * V850 Options:: Options | |
11 | * V850 Syntax:: Syntax | |
12 | * V850 Floating Point:: Floating Point | |
13 | * V850 Directives:: V850 Machine Directives | |
14 | * V850 Opcodes:: Opcodes | |
15 | @end menu | |
16 | ||
17 | @node V850 Options | |
18 | @section Options | |
19 | @cindex V850 options (none) | |
20 | @cindex options for V850 (none) | |
21 | @code{@value{AS}} supports the following additional command-line options | |
22 | for the V850 processor family: | |
23 | ||
24 | @cindex command line options, V850 | |
25 | @cindex V850 command line options | |
26 | @table @code | |
27 | ||
28 | @cindex @code{-wsigned_overflow} command line option, V850 | |
29 | @item -wsigned_overflow | |
30 | Causes warnings to be produced when signed immediate values overflow the | |
31 | space available for then within their opcodes. By default this option | |
32 | is disabled as it is possible to receive spurious warnings due to using | |
33 | exact bit patterns as immediate constants. | |
34 | ||
35 | @cindex @code{-wunsigned_overflow} command line option, V850 | |
36 | @item -wunsigned_overflow | |
37 | Causes warnings to be produced when unsigned immediate values overflow | |
38 | the space available for then within their opcodes. By default this | |
39 | option is disabled as it is possible to receive spurious warnings due to | |
40 | using exact bit patterns as immediate constants. | |
41 | ||
42 | @cindex @code{-mv850} command line option, V850 | |
43 | @item -mv850 | |
44 | Specifies that the assembled code should be marked as being targeted at | |
45 | the V850 processor. This allows the linker to detect attempts to link | |
46 | such code with code assembled for other processors. | |
47 | ||
48 | @cindex @code{-mv850e} command line option, V850 | |
49 | @item -mv850e | |
50 | Specifies that the assembled code should be marked as being targeted at | |
51 | the V850E processor. This allows the linker to detect attempts to link | |
52 | such code with code assembled for other processors. | |
53 | ||
8ad30312 NC |
54 | @cindex @code{-mv850e1} command line option, V850 |
55 | @item -mv850e1 | |
56 | Specifies that the assembled code should be marked as being targeted at | |
57 | the V850E1 processor. This allows the linker to detect attempts to link | |
58 | such code with code assembled for other processors. | |
59 | ||
252b5132 RH |
60 | @cindex @code{-mv850any} command line option, V850 |
61 | @item -mv850any | |
62 | Specifies that the assembled code should be marked as being targeted at | |
63 | the V850 processor but support instructions that are specific to the | |
64 | extended variants of the process. This allows the production of | |
65 | binaries that contain target specific code, but which are also intended | |
66 | to be used in a generic fashion. For example libgcc.a contains generic | |
67 | routines used by the code produced by GCC for all versions of the v850 | |
68 | architecture, together with support routines only used by the V850E | |
69 | architecture. | |
70 | ||
1cd986c5 NC |
71 | @cindex @code{-mv850e2} command line option, V850 |
72 | @item -mv850e2 | |
73 | Specifies that the assembled code should be marked as being targeted at | |
74 | the V850E2 processor. This allows the linker to detect attempts to link | |
75 | such code with code assembled for other processors. | |
76 | ||
77 | @cindex @code{-mv850e2v3} command line option, V850 | |
78 | @item -mv850e2v3 | |
79 | Specifies that the assembled code should be marked as being targeted at | |
80 | the V850E2V3 processor. This allows the linker to detect attempts to link | |
81 | such code with code assembled for other processors. | |
82 | ||
86aba9db NC |
83 | @cindex @code{-mrelax} command line option, V850 |
84 | @item -mrelax | |
85 | Enables relaxation. This allows the .longcall and .longjump pseudo | |
86 | ops to be used in the assembler source code. These ops label sections | |
87 | of code which are either a long function call or a long branch. The | |
88 | assembler will then flag these sections of code and the linker will | |
89 | attempt to relax them. | |
90 | ||
252b5132 RH |
91 | @end table |
92 | ||
93 | ||
94 | @node V850 Syntax | |
95 | @section Syntax | |
96 | @menu | |
97 | * V850-Chars:: Special Characters | |
98 | * V850-Regs:: Register Names | |
99 | @end menu | |
100 | ||
101 | @node V850-Chars | |
102 | @subsection Special Characters | |
103 | ||
104 | @cindex line comment character, V850 | |
105 | @cindex V850 line comment character | |
7c31ae13 NC |
106 | @samp{#} is the line comment character. If a @samp{#} appears as the |
107 | first character of a line, the whole line is treated as a comment, but | |
108 | in this case the line can also be a logical line number directive | |
109 | (@pxref{Comments}) or a preprocessor control command | |
110 | (@pxref{Preprocessing}). | |
111 | ||
112 | Two dashes (@samp{--}) can also be used to start a line comment. | |
113 | ||
114 | @cindex line separator, V850 | |
115 | @cindex statement separator, V850 | |
116 | @cindex V850 line separator | |
117 | ||
118 | The @samp{;} character can be used to separate statements on the same | |
119 | line. | |
120 | ||
252b5132 RH |
121 | @node V850-Regs |
122 | @subsection Register Names | |
123 | ||
124 | @cindex V850 register names | |
125 | @cindex register names, V850 | |
126 | @code{@value{AS}} supports the following names for registers: | |
127 | @table @code | |
128 | @cindex @code{zero} register, V850 | |
129 | @item general register 0 | |
130 | r0, zero | |
131 | @item general register 1 | |
132 | r1 | |
133 | @item general register 2 | |
134 | r2, hp | |
135 | @cindex @code{sp} register, V850 | |
136 | @item general register 3 | |
137 | r3, sp | |
138 | @cindex @code{gp} register, V850 | |
139 | @item general register 4 | |
140 | r4, gp | |
141 | @cindex @code{tp} register, V850 | |
142 | @item general register 5 | |
143 | r5, tp | |
144 | @item general register 6 | |
145 | r6 | |
146 | @item general register 7 | |
147 | r7 | |
148 | @item general register 8 | |
149 | r8 | |
150 | @item general register 9 | |
151 | r9 | |
152 | @item general register 10 | |
153 | r10 | |
154 | @item general register 11 | |
155 | r11 | |
156 | @item general register 12 | |
157 | r12 | |
158 | @item general register 13 | |
159 | r13 | |
160 | @item general register 14 | |
161 | r14 | |
162 | @item general register 15 | |
163 | r15 | |
164 | @item general register 16 | |
165 | r16 | |
166 | @item general register 17 | |
167 | r17 | |
168 | @item general register 18 | |
169 | r18 | |
170 | @item general register 19 | |
171 | r19 | |
172 | @item general register 20 | |
173 | r20 | |
174 | @item general register 21 | |
175 | r21 | |
176 | @item general register 22 | |
177 | r22 | |
178 | @item general register 23 | |
179 | r23 | |
180 | @item general register 24 | |
181 | r24 | |
182 | @item general register 25 | |
183 | r25 | |
184 | @item general register 26 | |
185 | r26 | |
186 | @item general register 27 | |
187 | r27 | |
188 | @item general register 28 | |
189 | r28 | |
190 | @item general register 29 | |
191 | r29 | |
192 | @cindex @code{ep} register, V850 | |
193 | @item general register 30 | |
194 | r30, ep | |
195 | @cindex @code{lp} register, V850 | |
196 | @item general register 31 | |
197 | r31, lp | |
198 | @cindex @code{eipc} register, V850 | |
199 | @item system register 0 | |
200 | eipc | |
201 | @cindex @code{eipsw} register, V850 | |
202 | @item system register 1 | |
203 | eipsw | |
204 | @cindex @code{fepc} register, V850 | |
205 | @item system register 2 | |
206 | fepc | |
207 | @cindex @code{fepsw} register, V850 | |
208 | @item system register 3 | |
209 | fepsw | |
210 | @cindex @code{ecr} register, V850 | |
211 | @item system register 4 | |
212 | ecr | |
213 | @cindex @code{psw} register, V850 | |
214 | @item system register 5 | |
215 | psw | |
216 | @cindex @code{ctpc} register, V850 | |
217 | @item system register 16 | |
218 | ctpc | |
219 | @cindex @code{ctpsw} register, V850 | |
220 | @item system register 17 | |
221 | ctpsw | |
222 | @cindex @code{dbpc} register, V850 | |
223 | @item system register 18 | |
224 | dbpc | |
225 | @cindex @code{dbpsw} register, V850 | |
226 | @item system register 19 | |
227 | dbpsw | |
228 | @cindex @code{ctbp} register, V850 | |
229 | @item system register 20 | |
230 | ctbp | |
231 | @end table | |
232 | ||
233 | @node V850 Floating Point | |
234 | @section Floating Point | |
235 | ||
236 | @cindex floating point, V850 (@sc{ieee}) | |
237 | @cindex V850 floating point (@sc{ieee}) | |
238 | The V850 family uses @sc{ieee} floating-point numbers. | |
239 | ||
240 | @node V850 Directives | |
241 | @section V850 Machine Directives | |
242 | ||
243 | @cindex machine directives, V850 | |
244 | @cindex V850 machine directives | |
245 | @table @code | |
246 | @cindex @code{offset} directive, V850 | |
247 | @item .offset @var{<expression>} | |
248 | Moves the offset into the current section to the specified amount. | |
249 | ||
250 | @cindex @code{section} directive, V850 | |
251 | @item .section "name", <type> | |
252 | This is an extension to the standard .section directive. It sets the | |
253 | current section to be <type> and creates an alias for this section | |
254 | called "name". | |
255 | ||
256 | @cindex @code{.v850} directive, V850 | |
257 | @item .v850 | |
258 | Specifies that the assembled code should be marked as being targeted at | |
259 | the V850 processor. This allows the linker to detect attempts to link | |
260 | such code with code assembled for other processors. | |
261 | ||
262 | @cindex @code{.v850e} directive, V850 | |
263 | @item .v850e | |
264 | Specifies that the assembled code should be marked as being targeted at | |
265 | the V850E processor. This allows the linker to detect attempts to link | |
8ad30312 NC |
266 | such code with code assembled for other processors. |
267 | ||
268 | @cindex @code{.v850e1} directive, V850 | |
269 | @item .v850e1 | |
270 | Specifies that the assembled code should be marked as being targeted at | |
271 | the V850E1 processor. This allows the linker to detect attempts to link | |
1cd986c5 NC |
272 | such code with code assembled for other processors. |
273 | ||
274 | @cindex @code{.v850e2} directive, V850 | |
275 | @item .v850e2 | |
276 | Specifies that the assembled code should be marked as being targeted at | |
277 | the V850E2 processor. This allows the linker to detect attempts to link | |
278 | such code with code assembled for other processors. | |
279 | ||
280 | @cindex @code{.v850e2v3} directive, V850 | |
281 | @item .v850e2v3 | |
282 | Specifies that the assembled code should be marked as being targeted at | |
283 | the V850E2V3 processor. This allows the linker to detect attempts to link | |
252b5132 RH |
284 | such code with code assembled for other processors. |
285 | ||
286 | @end table | |
287 | ||
288 | @node V850 Opcodes | |
289 | @section Opcodes | |
290 | ||
291 | @cindex V850 opcodes | |
292 | @cindex opcodes for V850 | |
293 | @code{@value{AS}} implements all the standard V850 opcodes. | |
294 | ||
295 | @code{@value{AS}} also implements the following pseudo ops: | |
296 | ||
297 | @table @code | |
298 | ||
299 | @cindex @code{hi0} pseudo-op, V850 | |
300 | @item hi0() | |
301 | Computes the higher 16 bits of the given expression and stores it into | |
302 | the immediate operand field of the given instruction. For example: | |
303 | ||
304 | @samp{mulhi hi0(here - there), r5, r6} | |
305 | ||
306 | computes the difference between the address of labels 'here' and | |
307 | 'there', takes the upper 16 bits of this difference, shifts it down 16 | |
b45619c0 | 308 | bits and then multiplies it by the lower 16 bits in register 5, putting |
252b5132 RH |
309 | the result into register 6. |
310 | ||
311 | @cindex @code{lo} pseudo-op, V850 | |
312 | @item lo() | |
313 | Computes the lower 16 bits of the given expression and stores it into | |
314 | the immediate operand field of the given instruction. For example: | |
315 | ||
316 | @samp{addi lo(here - there), r5, r6} | |
317 | ||
318 | computes the difference between the address of labels 'here' and | |
319 | 'there', takes the lower 16 bits of this difference and adds it to | |
320 | register 5, putting the result into register 6. | |
321 | ||
322 | @cindex @code{hi} pseudo-op, V850 | |
323 | @item hi() | |
324 | Computes the higher 16 bits of the given expression and then adds the | |
325 | value of the most significant bit of the lower 16 bits of the expression | |
326 | and stores the result into the immediate operand field of the given | |
327 | instruction. For example the following code can be used to compute the | |
328 | address of the label 'here' and store it into register 6: | |
329 | ||
330 | @samp{movhi hi(here), r0, r6} | |
331 | @samp{movea lo(here), r6, r6} | |
332 | ||
333 | The reason for this special behaviour is that movea performs a sign | |
062b7c0c | 334 | extension on its immediate operand. So for example if the address of |
252b5132 RH |
335 | 'here' was 0xFFFFFFFF then without the special behaviour of the hi() |
336 | pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the | |
337 | movea instruction would takes its immediate operand, 0xFFFF, sign extend | |
338 | it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF | |
339 | which is wrong (the fifth nibble is E). With the hi() pseudo op adding | |
340 | in the top bit of the lo() pseudo op, the movhi instruction actually | |
341 | stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction | |
342 | stores 0xFFFFFFFF into r6 - the right value. | |
343 | ||
344 | @cindex @code{hilo} pseudo-op, V850 | |
345 | @item hilo() | |
346 | Computes the 32 bit value of the given expression and stores it into | |
347 | the immediate operand field of the given instruction (which must be a | |
348 | mov instruction). For example: | |
349 | ||
350 | @samp{mov hilo(here), r6} | |
351 | ||
352 | computes the absolute address of label 'here' and puts the result into | |
353 | register 6. | |
354 | ||
355 | @cindex @code{sdaoff} pseudo-op, V850 | |
356 | @item sdaoff() | |
357 | Computes the offset of the named variable from the start of the Small | |
358 | Data Area (whoes address is held in register 4, the GP register) and | |
359 | stores the result as a 16 bit signed value in the immediate operand | |
360 | field of the given instruction. For example: | |
361 | ||
362 | @samp{ld.w sdaoff(_a_variable)[gp],r6} | |
363 | ||
364 | loads the contents of the location pointed to by the label '_a_variable' | |
365 | into register 6, provided that the label is located somewhere within +/- | |
366 | 32K of the address held in the GP register. [Note the linker assumes | |
367 | that the GP register contains a fixed address set to the address of the | |
368 | label called '__gp'. This can either be set up automatically by the | |
369 | linker, or specifically set by using the @samp{--defsym __gp=<value>} | |
370 | command line option]. | |
371 | ||
372 | @cindex @code{tdaoff} pseudo-op, V850 | |
373 | @item tdaoff() | |
374 | Computes the offset of the named variable from the start of the Tiny | |
375 | Data Area (whoes address is held in register 30, the EP register) and | |
376 | stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate | |
377 | operand field of the given instruction. For example: | |
378 | ||
379 | @samp{sld.w tdaoff(_a_variable)[ep],r6} | |
380 | ||
381 | loads the contents of the location pointed to by the label '_a_variable' | |
382 | into register 6, provided that the label is located somewhere within +256 | |
383 | bytes of the address held in the EP register. [Note the linker assumes | |
384 | that the EP register contains a fixed address set to the address of the | |
385 | label called '__ep'. This can either be set up automatically by the | |
386 | linker, or specifically set by using the @samp{--defsym __ep=<value>} | |
387 | command line option]. | |
388 | ||
389 | @cindex @code{zdaoff} pseudo-op, V850 | |
390 | @item zdaoff() | |
391 | Computes the offset of the named variable from address 0 and stores the | |
392 | result as a 16 bit signed value in the immediate operand field of the | |
393 | given instruction. For example: | |
394 | ||
395 | @samp{movea zdaoff(_a_variable),zero,r6} | |
396 | ||
397 | puts the address of the label '_a_variable' into register 6, assuming | |
398 | that the label is somewhere within the first 32K of memory. (Strictly | |
399 | speaking it also possible to access the last 32K of memory as well, as | |
400 | the offsets are signed). | |
401 | ||
402 | @cindex @code{ctoff} pseudo-op, V850 | |
403 | @item ctoff() | |
404 | Computes the offset of the named variable from the start of the Call | |
405 | Table Area (whoes address is helg in system register 20, the CTBP | |
406 | register) and stores the result a 6 or 16 bit unsigned value in the | |
407 | immediate field of then given instruction or piece of data. For | |
408 | example: | |
409 | ||
410 | @samp{callt ctoff(table_func1)} | |
411 | ||
412 | will put the call the function whoes address is held in the call table | |
413 | at the location labeled 'table_func1'. | |
414 | ||
86aba9db NC |
415 | @cindex @code{longcall} pseudo-op, V850 |
416 | @item .longcall @code{name} | |
417 | Indicates that the following sequence of instructions is a long call | |
418 | to function @code{name}. The linker will attempt to shorten this call | |
419 | sequence if @code{name} is within a 22bit offset of the call. Only | |
420 | valid if the @code{-mrelax} command line switch has been enabled. | |
421 | ||
422 | @cindex @code{longjump} pseudo-op, V850 | |
423 | @item .longjump @code{name} | |
424 | Indicates that the following sequence of instructions is a long jump | |
425 | to label @code{name}. The linker will attempt to shorten this code | |
426 | sequence if @code{name} is within a 22bit offset of the jump. Only | |
427 | valid if the @code{-mrelax} command line switch has been enabled. | |
428 | ||
252b5132 RH |
429 | @end table |
430 | ||
431 | ||
432 | For information on the V850 instruction set, see @cite{V850 | |
433 | Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC. | |
434 | Ltd. |