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efec4a28 | 1 | /* itbl-ops.c |
efec4a28 DP |
2 | Copyright (C) 1997 Free Software Foundation, Inc. |
3 | ||
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
19 | 02111-1307, USA. */ | |
20 | ||
8e5c905e DP |
21 | /*======================================================================*/ |
22 | /* | |
efec4a28 | 23 | * Herein lies the support for dynamic specification of processor |
8e5c905e | 24 | * instructions and registers. Mnemonics, values, and formats for each |
efec4a28 | 25 | * instruction and register are specified in an ascii file consisting of |
8e5c905e DP |
26 | * table entries. The grammar for the table is defined in the document |
27 | * "Processor instruction table specification". | |
28 | * | |
efec4a28 | 29 | * Instructions use the gnu assembler syntax, with the addition of |
8e5c905e DP |
30 | * allowing mnemonics for register. |
31 | * Eg. "func $2,reg3,0x100,symbol ; comment" | |
32 | * func - opcode name | |
33 | * $n - register n | |
34 | * reg3 - mnemonic for processor's register defined in table | |
35 | * 0xddd..d - immediate value | |
36 | * symbol - address of label or external symbol | |
efec4a28 DP |
37 | * |
38 | * First, itbl_parse reads in the table of register and instruction | |
8e5c905e DP |
39 | * names and formats, and builds a list of entries for each |
40 | * processor/type combination. lex and yacc are used to parse | |
41 | * the entries in the table and call functions defined here to | |
42 | * add each entry to our list. | |
efec4a28 DP |
43 | * |
44 | * Then, when assembling or disassembling, these functions are called to | |
45 | * 1) get information on a processor's registers and | |
8e5c905e | 46 | * 2) assemble/disassemble an instruction. |
efec4a28 DP |
47 | * To assemble(disassemble) an instruction, the function |
48 | * itbl_assemble(itbl_disassemble) is called to search the list of | |
49 | * instruction entries, and if a match is found, uses the format | |
50 | * described in the instruction entry structure to complete the action. | |
51 | * | |
8e5c905e DP |
52 | * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2" |
53 | * and we want to define function "pig" which takes two operands. | |
efec4a28 | 54 | * |
8e5c905e DP |
55 | * Given the table entries: |
56 | * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0" | |
57 | * "p3 dreg d2 0x2" | |
58 | * and that the instruction encoding for coprocessor pz has encoding: | |
59 | * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25) | |
60 | * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum) | |
efec4a28 | 61 | * |
8e5c905e DP |
62 | * a structure to describe the instruction might look something like: |
63 | * struct itbl_entry = { | |
64 | * e_processor processor = e_p3 | |
65 | * e_type type = e_insn | |
66 | * char *name = "pig" | |
67 | * uint value = 0x1 | |
68 | * uint flags = 0 | |
69 | * struct itbl_range range = 24-21 | |
70 | * struct itbl_field *field = { | |
efec4a28 | 71 | * e_type type = e_dreg |
8e5c905e DP |
72 | * struct itbl_range range = 20-16 |
73 | * struct itbl_field *next = { | |
74 | * e_type type = e_immed | |
75 | * struct itbl_range range = 15-0 | |
76 | * struct itbl_field *next = 0 | |
efec4a28 DP |
77 | * }; |
78 | * }; | |
8e5c905e DP |
79 | * struct itbl_entry *next = 0 |
80 | * }; | |
81 | * | |
82 | * And the assembler instructions: | |
83 | * "pig d2,0x100" | |
84 | * "pig $2,0x100" | |
efec4a28 | 85 | * |
8e5c905e DP |
86 | * would both assemble to the hex value: |
87 | * "0x4e220100" | |
efec4a28 DP |
88 | * |
89 | */ | |
8e5c905e DP |
90 | |
91 | #include <stdio.h> | |
92 | #include <stdlib.h> | |
93 | #include <string.h> | |
94 | #include "itbl-ops.h" | |
95 | #include "itbl-parse.h" | |
96 | ||
97 | #define DEBUG | |
98 | ||
99 | #ifdef DEBUG | |
100 | #include <assert.h> | |
101 | #define ASSERT(x) assert(x) | |
102 | #define DBG(x) printf x | |
103 | #else | |
efec4a28 | 104 | #define ASSERT(x) |
8e5c905e DP |
105 | #define DBG(x) |
106 | #endif | |
107 | ||
108 | #ifndef min | |
109 | #define min(a,b) (a<b?a:b) | |
110 | #endif | |
111 | ||
efec4a28 DP |
112 | int itbl_have_entries = 0; |
113 | ||
8e5c905e DP |
114 | /*======================================================================*/ |
115 | /* structures for keeping itbl format entries */ | |
116 | ||
efec4a28 DP |
117 | struct itbl_range |
118 | { | |
119 | int sbit; /* mask starting bit position */ | |
120 | int ebit; /* mask ending bit position */ | |
121 | }; | |
122 | ||
123 | struct itbl_field | |
124 | { | |
125 | e_type type; /* dreg/creg/greg/immed/symb */ | |
126 | struct itbl_range range; /* field's bitfield range within instruction */ | |
127 | unsigned long flags; /* field flags */ | |
128 | struct itbl_field *next; /* next field in list */ | |
129 | }; | |
130 | ||
131 | ||
8e5c905e | 132 | /* These structures define the instructions and registers for a processor. |
efec4a28 DP |
133 | * If the type is an instruction, the structure defines the format of an |
134 | * instruction where the fields are the list of operands. | |
135 | * The flags field below uses the same values as those defined in the | |
8e5c905e | 136 | * gnu assembler and are machine specific. */ |
efec4a28 DP |
137 | struct itbl_entry |
138 | { | |
139 | e_processor processor; /* processor number */ | |
140 | e_type type; /* dreg/creg/greg/insn */ | |
141 | char *name; /* mnemionic name for insn/register */ | |
142 | unsigned long value; /* opcode/instruction mask/register number */ | |
143 | unsigned long flags; /* effects of the instruction */ | |
144 | struct itbl_range range; /* bit range within instruction for value */ | |
145 | struct itbl_field *fields; /* list of operand definitions (if any) */ | |
146 | struct itbl_entry *next; /* next entry */ | |
147 | }; | |
8e5c905e DP |
148 | |
149 | ||
150 | /* local data and structures */ | |
151 | ||
152 | static int itbl_num_opcodes = 0; | |
153 | /* Array of entries for each processor and entry type */ | |
154 | static struct itbl_entry *entries[e_nprocs][e_ntypes] = | |
155 | { | |
efec4a28 DP |
156 | {0, 0, 0, 0, 0, 0}, |
157 | {0, 0, 0, 0, 0, 0}, | |
158 | {0, 0, 0, 0, 0, 0}, | |
159 | {0, 0, 0, 0, 0, 0} | |
8e5c905e DP |
160 | }; |
161 | ||
162 | /* local prototypes */ | |
efec4a28 DP |
163 | static unsigned long build_opcode PARAMS ((struct itbl_entry *e)); |
164 | static e_type get_type PARAMS ((int yytype)); | |
165 | static e_processor get_processor PARAMS ((int yyproc)); | |
166 | static struct itbl_entry **get_entries PARAMS ((e_processor processor, | |
167 | e_type type)); | |
168 | static struct itbl_entry *find_entry_byname PARAMS ((e_processor processor, | |
169 | e_type type, char *name)); | |
170 | static struct itbl_entry *find_entry_byval PARAMS ((e_processor processor, | |
171 | e_type type, unsigned long val, struct itbl_range *r)); | |
172 | static struct itbl_entry *alloc_entry PARAMS ((e_processor processor, | |
173 | e_type type, char *name, unsigned long value)); | |
174 | static unsigned long apply_range PARAMS ((unsigned long value, | |
175 | struct itbl_range r)); | |
176 | static unsigned long extract_range PARAMS ((unsigned long value, | |
177 | struct itbl_range r)); | |
178 | static struct itbl_field *alloc_field PARAMS ((e_type type, int sbit, | |
179 | int ebit, unsigned long flags)); | |
8e5c905e DP |
180 | |
181 | ||
182 | /*======================================================================*/ | |
183 | /* Interfaces to the parser */ | |
184 | ||
185 | ||
186 | /* Open the table and use lex and yacc to parse the entries. | |
187 | * Return 1 for failure; 0 for success. */ | |
188 | ||
efec4a28 DP |
189 | int |
190 | itbl_parse (char *insntbl) | |
8e5c905e | 191 | { |
efec4a28 DP |
192 | extern FILE *yyin; |
193 | extern int yyparse (void); | |
194 | yyin = fopen (insntbl, "r"); | |
195 | if (yyin == 0) | |
196 | { | |
197 | printf ("Can't open processor instruction specification file \"%s\"\n", | |
198 | insntbl); | |
199 | return 1; | |
200 | } | |
201 | else | |
202 | { | |
203 | while (yyparse ()); | |
204 | } | |
205 | fclose (yyin); | |
206 | itbl_have_entries = 1; | |
207 | return 0; | |
8e5c905e DP |
208 | } |
209 | ||
210 | /* Add a register entry */ | |
211 | ||
efec4a28 DP |
212 | struct itbl_entry * |
213 | itbl_add_reg (int yyprocessor, int yytype, char *regname, | |
214 | int regnum) | |
8e5c905e | 215 | { |
efec4a28 | 216 | #if 0 |
8e5c905e DP |
217 | #include "as.h" |
218 | #include "symbols.h" | |
219 | /* Since register names don't have a prefix, we put them in the symbol table so | |
220 | they can't be used as symbols. This also simplifies argument parsing as | |
221 | we can let gas parse registers for us. The recorded register number is | |
222 | regnum. */ | |
efec4a28 | 223 | /* Use symbol_create here instead of symbol_new so we don't try to |
8e5c905e | 224 | output registers into the object file's symbol table. */ |
efec4a28 DP |
225 | symbol_table_insert (symbol_create (regname, reg_section, |
226 | regnum, &zero_address_frag)); | |
8e5c905e | 227 | #endif |
efec4a28 DP |
228 | return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname, |
229 | (unsigned long) regnum); | |
8e5c905e DP |
230 | } |
231 | ||
232 | /* Add an instruction entry */ | |
233 | ||
efec4a28 DP |
234 | struct itbl_entry * |
235 | itbl_add_insn (int yyprocessor, char *name, unsigned long value, | |
236 | int sbit, int ebit, unsigned long flags) | |
8e5c905e | 237 | { |
efec4a28 DP |
238 | struct itbl_entry *e; |
239 | e = alloc_entry (get_processor (yyprocessor), e_insn, name, value); | |
240 | if (e) | |
241 | { | |
242 | e->range.sbit = sbit; | |
243 | e->range.ebit = ebit; | |
244 | e->flags = flags; | |
245 | itbl_num_opcodes++; | |
246 | } | |
247 | return e; | |
8e5c905e DP |
248 | } |
249 | ||
250 | /* Add an operand to an instruction entry */ | |
251 | ||
efec4a28 DP |
252 | struct itbl_field * |
253 | itbl_add_operand (struct itbl_entry *e, int yytype, int sbit, | |
254 | int ebit, unsigned long flags) | |
8e5c905e | 255 | { |
efec4a28 DP |
256 | struct itbl_field *f, **last_f; |
257 | if (!e) | |
258 | return 0; | |
259 | /* Add to end of fields' list. */ | |
260 | f = alloc_field (get_type (yytype), sbit, ebit, flags); | |
261 | if (f) | |
262 | { | |
263 | last_f = &e->fields; | |
264 | while (*last_f) | |
265 | last_f = &(*last_f)->next; | |
266 | *last_f = f; | |
267 | f->next = 0; | |
268 | } | |
269 | return f; | |
8e5c905e DP |
270 | } |
271 | ||
272 | ||
273 | /*======================================================================*/ | |
274 | /* Interfaces for assembler and disassembler */ | |
275 | ||
276 | #ifndef STAND_ALONE | |
277 | #include "as.h" | |
278 | #include "symbols.h" | |
efec4a28 | 279 | static void append_insns_as_macros (void); |
8e5c905e DP |
280 | |
281 | /* initialize for gas */ | |
efec4a28 DP |
282 | void |
283 | itbl_init (void) | |
8e5c905e | 284 | { |
efec4a28 DP |
285 | struct itbl_entry *e, **es; |
286 | e_processor procn; | |
287 | e_type type; | |
8e5c905e DP |
288 | |
289 | /* Since register names don't have a prefix, put them in the symbol table so | |
290 | they can't be used as symbols. This simplifies argument parsing as | |
291 | we can let gas parse registers for us. */ | |
efec4a28 | 292 | /* Use symbol_create instead of symbol_new so we don't try to |
8e5c905e DP |
293 | output registers into the object file's symbol table. */ |
294 | ||
efec4a28 DP |
295 | for (type = e_regtype0; type < e_nregtypes; type++) |
296 | for (procn = e_p0; procn < e_nprocs; procn++) | |
297 | { | |
298 | es = get_entries (procn, type); | |
299 | for (e = *es; e; e = e->next) | |
300 | { | |
301 | symbol_table_insert (symbol_create (e->name, reg_section, | |
302 | e->value, &zero_address_frag)); | |
303 | } | |
304 | } | |
305 | append_insns_as_macros (); | |
8e5c905e DP |
306 | } |
307 | ||
308 | ||
efec4a28 DP |
309 | /* Append insns to opcodes table and increase number of opcodes |
310 | * Structure of opcodes table: | |
311 | * struct itbl_opcode | |
312 | * { | |
313 | * const char *name; | |
314 | * const char *args; - string describing the arguments. | |
315 | * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO | |
316 | * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO | |
317 | * unsigned long pinfo; - insn flags, or INSN_MACRO | |
318 | * }; | |
319 | * examples: | |
320 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, | |
321 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, | |
8e5c905e | 322 | */ |
efec4a28 DP |
323 | |
324 | static char *form_args (struct itbl_entry *e); | |
325 | static void | |
326 | append_insns_as_macros (void) | |
8e5c905e | 327 | { |
efec4a28 DP |
328 | struct ITBL_OPCODE_STRUCT *new_opcodes, *o; |
329 | struct itbl_entry *e, **es; | |
330 | int n, id, size, new_size, new_num_opcodes; | |
8e5c905e | 331 | |
efec4a28 DP |
332 | if (!itbl_num_opcodes) /* no new instructions to add! */ |
333 | { | |
334 | return; | |
335 | } | |
336 | DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES)); | |
8e5c905e | 337 | |
efec4a28 DP |
338 | new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes; |
339 | ASSERT (new_num_opcodes >= itbl_num_opcodes); | |
8e5c905e | 340 | |
efec4a28 DP |
341 | size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES; |
342 | ASSERT (size >= 0); | |
343 | DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0]))); | |
8e5c905e | 344 | |
efec4a28 DP |
345 | new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes; |
346 | ASSERT (new_size > size); | |
8e5c905e | 347 | |
efec4a28 | 348 | /* FIXME since ITBL_OPCODES culd be a static table, |
8e5c905e | 349 | we can't realloc or delete the old memory. */ |
efec4a28 DP |
350 | new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size); |
351 | if (!new_opcodes) | |
352 | { | |
353 | printf ("Unable to allocate memory for new instructions\n"); | |
354 | return; | |
355 | } | |
356 | if (size) /* copy prexisting opcodes table */ | |
357 | memcpy (new_opcodes, ITBL_OPCODES, size); | |
8e5c905e | 358 | |
efec4a28 | 359 | /* FIXME! some NUMOPCODES are calculated expressions. |
8e5c905e DP |
360 | These need to be changed before itbls can be supported. */ |
361 | ||
efec4a28 DP |
362 | id = ITBL_NUM_MACROS; /* begin the next macro id after the last */ |
363 | o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */ | |
364 | for (n = e_p0; n < e_nprocs; n++) | |
365 | { | |
366 | es = get_entries (n, e_insn); | |
367 | for (e = *es; e; e = e->next) | |
8e5c905e | 368 | { |
efec4a28 DP |
369 | /* name, args, mask, match, pinfo |
370 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, | |
8e5c905e DP |
371 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, |
372 | * Construct args from itbl_fields. | |
373 | */ | |
efec4a28 DP |
374 | o->name = e->name; |
375 | o->args = strdup (form_args (e)); | |
376 | o->mask = apply_range (e->value, e->range); | |
377 | /* FIXME how to catch durring assembly? */ | |
378 | /* mask to identify this insn */ | |
379 | o->match = apply_range (e->value, e->range); | |
380 | o->pinfo = 0; | |
8e5c905e DP |
381 | |
382 | #ifdef USE_MACROS | |
efec4a28 DP |
383 | o->mask = id++; /* FIXME how to catch durring assembly? */ |
384 | o->match = 0; /* for macros, the insn_isa number */ | |
385 | o->pinfo = INSN_MACRO; | |
8e5c905e DP |
386 | #endif |
387 | ||
efec4a28 DP |
388 | /* Don't add instructions which caused an error */ |
389 | if (o->args) | |
390 | o++; | |
391 | else | |
392 | new_num_opcodes--; | |
8e5c905e | 393 | } |
efec4a28 DP |
394 | } |
395 | ITBL_OPCODES = new_opcodes; | |
396 | ITBL_NUM_OPCODES = new_num_opcodes; | |
8e5c905e | 397 | |
efec4a28 DP |
398 | /* FIXME |
399 | At this point, we can free the entries, as they should have | |
8e5c905e DP |
400 | been added to the assembler's tables. |
401 | Don't free name though, since name is being used by the new | |
402 | opcodes table. | |
403 | ||
efec4a28 DP |
404 | Eventually, we should also free the new opcodes table itself |
405 | on exit. | |
8e5c905e DP |
406 | */ |
407 | } | |
408 | ||
efec4a28 DP |
409 | static char * |
410 | form_args (struct itbl_entry *e) | |
8e5c905e | 411 | { |
efec4a28 DP |
412 | static char s[31]; |
413 | char c = 0, *p = s; | |
414 | struct itbl_field *f; | |
8e5c905e | 415 | |
efec4a28 DP |
416 | ASSERT (e); |
417 | for (f = e->fields; f; f = f->next) | |
418 | { | |
419 | switch (f->type) | |
420 | { | |
421 | case e_dreg: | |
422 | c = 'd'; | |
423 | break; | |
424 | case e_creg: | |
425 | c = 't'; | |
426 | break; | |
427 | case e_greg: | |
428 | c = 's'; | |
429 | break; | |
430 | case e_immed: | |
431 | c = 'i'; | |
432 | break; | |
433 | case e_addr: | |
434 | c = 'a'; | |
435 | break; | |
436 | default: | |
437 | c = 0; /* ignore; unknown field type */ | |
438 | } | |
439 | if (c) | |
8e5c905e | 440 | { |
efec4a28 DP |
441 | if (p != s) |
442 | *p++ = ','; | |
443 | *p++ = c; | |
8e5c905e | 444 | } |
efec4a28 DP |
445 | } |
446 | *p = 0; | |
447 | return s; | |
8e5c905e DP |
448 | } |
449 | #endif /* !STAND_ALONE */ | |
450 | ||
451 | ||
452 | /* Get processor's register name from val */ | |
453 | ||
efec4a28 DP |
454 | unsigned long |
455 | itbl_get_reg_val (char *name) | |
8e5c905e | 456 | { |
efec4a28 DP |
457 | e_type t; |
458 | e_processor p; | |
459 | int r = 0; | |
460 | for (p = e_p0; p < e_nprocs; p++) | |
461 | for (t = e_regtype0; t < e_nregtypes; t++) | |
462 | { | |
463 | if (r = itbl_get_val (p, t, name), r) | |
464 | return r; | |
465 | } | |
466 | return 0; | |
8e5c905e DP |
467 | } |
468 | ||
efec4a28 DP |
469 | char * |
470 | itbl_get_name (e_processor processor, e_type type, unsigned long val) | |
8e5c905e | 471 | { |
efec4a28 DP |
472 | struct itbl_entry *r; |
473 | /* type depends on instruction passed */ | |
474 | r = find_entry_byval (processor, type, val, 0); | |
475 | if (r) | |
476 | return r->name; | |
477 | else | |
478 | return 0; /* error; invalid operand */ | |
8e5c905e DP |
479 | } |
480 | ||
481 | /* Get processor's register value from name */ | |
482 | ||
efec4a28 DP |
483 | unsigned long |
484 | itbl_get_val (e_processor processor, e_type type, char *name) | |
8e5c905e | 485 | { |
efec4a28 DP |
486 | struct itbl_entry *r; |
487 | /* type depends on instruction passed */ | |
488 | r = find_entry_byname (processor, type, name); | |
489 | if (r) | |
490 | return r->value; | |
491 | else | |
492 | return 0; /* error; invalid operand */ | |
8e5c905e DP |
493 | } |
494 | ||
495 | ||
496 | /* Assemble instruction "name" with operands "s". | |
497 | * name - name of instruction | |
498 | * s - operands | |
499 | * returns - long word for assembled instruction */ | |
500 | ||
efec4a28 DP |
501 | unsigned long |
502 | itbl_assemble (char *name, char *s) | |
8e5c905e | 503 | { |
efec4a28 DP |
504 | unsigned long opcode; |
505 | struct itbl_entry *e; | |
506 | struct itbl_field *f; | |
507 | char *n; | |
508 | int processor; | |
8e5c905e | 509 | |
efec4a28 DP |
510 | if (!name || !*name) |
511 | return 0; /* error! must have a opcode name/expr */ | |
8e5c905e | 512 | |
efec4a28 DP |
513 | /* find entry in list of instructions for all processors */ |
514 | for (processor = 0; processor < e_nprocs; processor++) | |
515 | { | |
516 | e = find_entry_byname (processor, e_insn, name); | |
517 | if (e) | |
518 | break; | |
519 | } | |
520 | if (!e) | |
521 | return 0; /* opcode not in table; invalid instrustion */ | |
522 | opcode = build_opcode (e); | |
8e5c905e | 523 | |
efec4a28 DP |
524 | /* parse opcode's args (if any) */ |
525 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ | |
526 | { | |
527 | struct itbl_entry *r; | |
528 | unsigned long value; | |
529 | if (!s || !*s) | |
530 | return 0; /* error - not enough operands */ | |
531 | n = itbl_get_field (&s); | |
532 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ | |
533 | switch (f->type) | |
8e5c905e | 534 | { |
efec4a28 DP |
535 | case e_dreg: |
536 | case e_creg: | |
537 | case e_greg: | |
538 | /* Accept either a string name | |
8e5c905e | 539 | * or '$' followed by the register number */ |
efec4a28 DP |
540 | if (*n == '$') |
541 | { | |
542 | n++; | |
543 | value = strtol (n, 0, 10); | |
544 | /* FIXME! could have "0l"... then what?? */ | |
545 | if (value == 0 && *n != '0') | |
546 | return 0; /* error; invalid operand */ | |
547 | } | |
548 | else | |
549 | { | |
550 | r = find_entry_byname (e->processor, f->type, n); | |
551 | if (r) | |
552 | value = r->value; | |
553 | else | |
554 | return 0; /* error; invalid operand */ | |
555 | } | |
556 | break; | |
557 | case e_addr: | |
558 | /* use assembler's symbol table to find symbol */ | |
559 | /* FIXME!! Do we need this? | |
8e5c905e DP |
560 | if so, what about relocs?? |
561 | my_getExpression (&imm_expr, s); | |
562 | return 0; /-* error; invalid operand *-/ | |
563 | break; | |
564 | */ | |
efec4a28 DP |
565 | /* If not a symbol, fall thru to IMMED */ |
566 | case e_immed: | |
567 | if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */ | |
568 | { | |
569 | n += 2; | |
570 | value = strtol (n, 0, 16); | |
571 | /* FIXME! could have "0xl"... then what?? */ | |
572 | } | |
573 | else | |
574 | { | |
575 | value = strtol (n, 0, 10); | |
576 | /* FIXME! could have "0l"... then what?? */ | |
577 | if (value == 0 && *n != '0') | |
578 | return 0; /* error; invalid operand */ | |
579 | } | |
580 | break; | |
581 | default: | |
582 | return 0; /* error; invalid field spec */ | |
8e5c905e | 583 | } |
efec4a28 DP |
584 | opcode |= apply_range (value, f->range); |
585 | } | |
586 | if (s && *s) | |
587 | return 0; /* error - too many operands */ | |
588 | return opcode; /* done! */ | |
8e5c905e DP |
589 | } |
590 | ||
591 | /* Disassemble instruction "insn". | |
592 | * insn - instruction | |
593 | * s - buffer to hold disassembled instruction | |
594 | * returns - 1 if succeeded; 0 if failed | |
595 | */ | |
596 | ||
efec4a28 DP |
597 | int |
598 | itbl_disassemble (char *s, unsigned long insn) | |
8e5c905e | 599 | { |
efec4a28 DP |
600 | e_processor processor; |
601 | struct itbl_entry *e; | |
602 | struct itbl_field *f; | |
603 | ||
604 | if (!ITBL_IS_INSN (insn)) | |
605 | return 0; /* error*/ | |
606 | processor = get_processor (ITBL_DECODE_PNUM (insn)); | |
607 | ||
608 | /* find entry in list */ | |
609 | e = find_entry_byval (processor, e_insn, insn, 0); | |
610 | if (!e) | |
611 | return 0; /* opcode not in table; invalid instrustion */ | |
612 | strcpy (s, e->name); | |
613 | ||
614 | /* parse insn's args (if any) */ | |
615 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ | |
616 | { | |
617 | struct itbl_entry *r; | |
618 | unsigned long value; | |
619 | ||
620 | if (f == e->fields) /* first operand is preceeded by tab */ | |
621 | strcat (s, "\t"); | |
622 | else /* ','s separate following operands */ | |
623 | strcat (s, ","); | |
624 | value = extract_range (insn, f->range); | |
625 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ | |
626 | switch (f->type) | |
8e5c905e | 627 | { |
efec4a28 DP |
628 | case e_dreg: |
629 | case e_creg: | |
630 | case e_greg: | |
631 | /* Accept either a string name | |
8e5c905e | 632 | * or '$' followed by the register number */ |
efec4a28 DP |
633 | r = find_entry_byval (e->processor, f->type, value, &f->range); |
634 | if (r) | |
635 | strcat (s, r->name); | |
636 | else | |
637 | sprintf (s, "%s$%d", s, value); | |
638 | break; | |
639 | case e_addr: | |
640 | /* use assembler's symbol table to find symbol */ | |
641 | /* FIXME!! Do we need this? | |
8e5c905e DP |
642 | * if so, what about relocs?? |
643 | */ | |
efec4a28 DP |
644 | /* If not a symbol, fall thru to IMMED */ |
645 | case e_immed: | |
646 | sprintf (s, "%s0x%x", s, value); | |
647 | break; | |
648 | default: | |
649 | return 0; /* error; invalid field spec */ | |
8e5c905e | 650 | } |
efec4a28 DP |
651 | } |
652 | return 1; /* done! */ | |
8e5c905e DP |
653 | } |
654 | ||
655 | /*======================================================================*/ | |
656 | /* | |
657 | * Local functions for manipulating private structures containing | |
658 | * the names and format for the new instructions and registers | |
659 | * for each processor. | |
660 | */ | |
661 | ||
662 | /* Calculate instruction's opcode and function values from entry */ | |
663 | ||
efec4a28 DP |
664 | static unsigned long |
665 | build_opcode (struct itbl_entry *e) | |
8e5c905e | 666 | { |
efec4a28 | 667 | unsigned long opcode; |
8e5c905e | 668 | |
efec4a28 DP |
669 | opcode = apply_range (e->value, e->range); |
670 | opcode |= ITBL_ENCODE_PNUM (e->processor); | |
671 | return opcode; | |
8e5c905e DP |
672 | } |
673 | ||
efec4a28 DP |
674 | /* Calculate absolute value given the relative value and bit position range |
675 | * within the instruction. | |
8e5c905e DP |
676 | * The range is inclusive where 0 is least significant bit. |
677 | * A range of { 24, 20 } will have a mask of | |
678 | * bit 3 2 1 | |
679 | * pos: 1098 7654 3210 9876 5432 1098 7654 3210 | |
680 | * bin: 0000 0001 1111 0000 0000 0000 0000 0000 | |
681 | * hex: 0 1 f 0 0 0 0 0 | |
682 | * mask: 0x01f00000. | |
683 | */ | |
684 | ||
efec4a28 DP |
685 | static unsigned long |
686 | apply_range (unsigned long rval, struct itbl_range r) | |
8e5c905e | 687 | { |
efec4a28 DP |
688 | unsigned long mask; |
689 | unsigned long aval; | |
690 | int len = MAX_BITPOS - r.sbit; | |
691 | ||
692 | ASSERT (r.sbit >= r.ebit); | |
693 | ASSERT (MAX_BITPOS >= r.sbit); | |
694 | ASSERT (r.ebit >= 0); | |
695 | ||
696 | /* create mask by truncating 1s by shifting */ | |
697 | mask = 0xffffffff << len; | |
698 | mask = mask >> len; | |
699 | mask = mask >> r.ebit; | |
700 | mask = mask << r.ebit; | |
701 | ||
702 | aval = (rval << r.ebit) & mask; | |
703 | return aval; | |
8e5c905e DP |
704 | } |
705 | ||
efec4a28 | 706 | /* Calculate relative value given the absolute value and bit position range |
8e5c905e DP |
707 | * within the instruction. */ |
708 | ||
efec4a28 DP |
709 | static unsigned long |
710 | extract_range (unsigned long aval, struct itbl_range r) | |
8e5c905e | 711 | { |
efec4a28 DP |
712 | unsigned long mask; |
713 | unsigned long rval; | |
714 | int len = MAX_BITPOS - r.sbit; | |
715 | ||
716 | /* create mask by truncating 1s by shifting */ | |
717 | mask = 0xffffffff << len; | |
718 | mask = mask >> len; | |
719 | mask = mask >> r.ebit; | |
720 | mask = mask << r.ebit; | |
721 | ||
722 | rval = (aval & mask) >> r.ebit; | |
723 | return rval; | |
8e5c905e DP |
724 | } |
725 | ||
efec4a28 | 726 | /* Extract processor's assembly instruction field name from s; |
8e5c905e | 727 | * forms are "n args" "n,args" or "n" */ |
efec4a28 | 728 | /* Return next argument from string pointer "s" and advance s. |
8e5c905e DP |
729 | * delimiters are " ,\0" */ |
730 | ||
efec4a28 DP |
731 | char * |
732 | itbl_get_field (char **S) | |
8e5c905e | 733 | { |
efec4a28 DP |
734 | static char n[128]; |
735 | char *p, *ps, *s; | |
736 | int len; | |
737 | ||
738 | s = *S; | |
739 | if (!s || !*s) | |
740 | return 0; | |
741 | p = s + strlen (s); | |
742 | if (ps = strchr (s, ','), ps) | |
743 | p = ps; | |
744 | if (ps = strchr (s, ' '), ps) | |
745 | p = min (p, ps); | |
746 | if (ps = strchr (s, '\0'), ps) | |
747 | p = min (p, ps); | |
748 | if (p == 0) | |
749 | return 0; /* error! */ | |
750 | len = p - s; | |
751 | ASSERT (128 > len + 1); | |
752 | strncpy (n, s, len); | |
753 | n[len] = 0; | |
754 | if (s[len] == '\0') | |
755 | s = 0; /* no more args */ | |
756 | else | |
757 | s += len + 1; /* advance to next arg */ | |
758 | ||
759 | *S = s; | |
760 | return n; | |
8e5c905e DP |
761 | } |
762 | ||
763 | /* Search entries for a given processor and type | |
764 | * to find one matching the name "n". | |
765 | * Return a pointer to the entry */ | |
766 | ||
efec4a28 DP |
767 | static struct itbl_entry * |
768 | find_entry_byname (e_processor processor, | |
769 | e_type type, char *n) | |
8e5c905e | 770 | { |
efec4a28 | 771 | struct itbl_entry *e, **es; |
8e5c905e | 772 | |
efec4a28 DP |
773 | es = get_entries (processor, type); |
774 | for (e = *es; e; e = e->next) /* for each entry, ... */ | |
775 | { | |
776 | if (!strcmp (e->name, n)) | |
777 | return e; | |
778 | } | |
779 | return 0; | |
8e5c905e DP |
780 | } |
781 | ||
782 | /* Search entries for a given processor and type | |
783 | * to find one matching the value "val" for the range "r". | |
784 | * Return a pointer to the entry. | |
785 | * This function is used for disassembling fields of an instruction. | |
786 | */ | |
787 | ||
efec4a28 DP |
788 | static struct itbl_entry * |
789 | find_entry_byval (e_processor processor, e_type type, | |
790 | unsigned long val, struct itbl_range *r) | |
8e5c905e | 791 | { |
efec4a28 DP |
792 | struct itbl_entry *e, **es; |
793 | unsigned long eval; | |
8e5c905e | 794 | |
efec4a28 DP |
795 | es = get_entries (processor, type); |
796 | for (e = *es; e; e = e->next) /* for each entry, ... */ | |
797 | { | |
798 | if (processor != e->processor) | |
799 | continue; | |
800 | /* For insns, we might not know the range of the opcode, | |
801 | * so a range of 0 will allow this routine to match against | |
8e5c905e DP |
802 | * the range of the entry to be compared with. |
803 | * This could cause ambiguities. | |
804 | * For operands, we get an extracted value and a range. | |
805 | */ | |
efec4a28 DP |
806 | /* if range is 0, mask val against the range of the compared entry. */ |
807 | if (r == 0) /* if no range passed, must be whole 32-bits | |
8e5c905e DP |
808 | * so create 32-bit value from entry's range */ |
809 | { | |
efec4a28 DP |
810 | eval = apply_range (e->value, e->range); |
811 | val &= apply_range (0xffffffff, e->range); | |
8e5c905e | 812 | } |
efec4a28 DP |
813 | else if (r->sbit == e->range.sbit && r->ebit == e->range.ebit |
814 | || e->range.sbit == 0 && e->range.ebit == 0) | |
8e5c905e | 815 | { |
efec4a28 DP |
816 | eval = apply_range (e->value, *r); |
817 | val = apply_range (val, *r); | |
8e5c905e | 818 | } |
efec4a28 DP |
819 | else |
820 | continue; | |
821 | if (val == eval) | |
822 | return e; | |
823 | } | |
824 | return 0; | |
8e5c905e DP |
825 | } |
826 | ||
827 | /* Return a pointer to the list of entries for a given processor and type. */ | |
828 | ||
efec4a28 DP |
829 | static struct itbl_entry ** |
830 | get_entries (e_processor processor, e_type type) | |
8e5c905e | 831 | { |
efec4a28 | 832 | return &entries[processor][type]; |
8e5c905e DP |
833 | } |
834 | ||
835 | /* Return an integral value for the processor passed from yyparse. */ | |
836 | ||
efec4a28 DP |
837 | static e_processor |
838 | get_processor (int yyproc) | |
8e5c905e | 839 | { |
efec4a28 DP |
840 | /* translate from yacc's processor to enum */ |
841 | if (yyproc >= e_p0 && yyproc < e_nprocs) | |
842 | return (e_processor) yyproc; | |
843 | return e_invproc; /* error; invalid processor */ | |
8e5c905e DP |
844 | } |
845 | ||
846 | /* Return an integral value for the entry type passed from yyparse. */ | |
847 | ||
efec4a28 DP |
848 | static e_type |
849 | get_type (int yytype) | |
8e5c905e | 850 | { |
efec4a28 | 851 | switch (yytype) |
8e5c905e | 852 | { |
efec4a28 DP |
853 | /* translate from yacc's type to enum */ |
854 | case INSN: | |
855 | return e_insn; | |
856 | case DREG: | |
857 | return e_dreg; | |
858 | case CREG: | |
859 | return e_creg; | |
860 | case GREG: | |
861 | return e_greg; | |
862 | case ADDR: | |
863 | return e_addr; | |
864 | case IMMED: | |
865 | return e_immed; | |
866 | default: | |
867 | return e_invtype; /* error; invalid type */ | |
8e5c905e DP |
868 | } |
869 | } | |
870 | ||
871 | ||
872 | /* Allocate and initialize an entry */ | |
873 | ||
efec4a28 DP |
874 | static struct itbl_entry * |
875 | alloc_entry (e_processor processor, e_type type, | |
876 | char *name, unsigned long value) | |
8e5c905e | 877 | { |
efec4a28 DP |
878 | struct itbl_entry *e, **es; |
879 | if (!name) | |
880 | return 0; | |
881 | e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry)); | |
882 | if (e) | |
883 | { | |
884 | memset (e, 0, sizeof (struct itbl_entry)); | |
885 | e->name = (char *) malloc (sizeof (strlen (name)) + 1); | |
886 | if (e->name) | |
887 | strcpy (e->name, name); | |
888 | e->processor = processor; | |
889 | e->type = type; | |
890 | e->value = value; | |
891 | es = get_entries (e->processor, e->type); | |
892 | e->next = *es; | |
893 | *es = e; | |
894 | } | |
895 | return e; | |
8e5c905e DP |
896 | } |
897 | ||
898 | /* Allocate and initialize an entry's field */ | |
899 | ||
efec4a28 DP |
900 | static struct itbl_field * |
901 | alloc_field (e_type type, int sbit, int ebit, | |
902 | unsigned long flags) | |
8e5c905e | 903 | { |
efec4a28 DP |
904 | struct itbl_field *f; |
905 | f = (struct itbl_field *) malloc (sizeof (struct itbl_field)); | |
906 | if (f) | |
907 | { | |
908 | memset (f, 0, sizeof (struct itbl_field)); | |
909 | f->type = type; | |
910 | f->range.sbit = sbit; | |
911 | f->range.ebit = ebit; | |
912 | f->flags = flags; | |
913 | } | |
914 | return f; | |
8e5c905e | 915 | } |