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252b5132 | 1 | /* itbl-ops.c |
d7ba4a77 | 2 | Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
19 | 02111-1307, USA. */ | |
20 | ||
21 | /*======================================================================*/ | |
22 | /* | |
23 | * Herein lies the support for dynamic specification of processor | |
24 | * instructions and registers. Mnemonics, values, and formats for each | |
25 | * instruction and register are specified in an ascii file consisting of | |
26 | * table entries. The grammar for the table is defined in the document | |
27 | * "Processor instruction table specification". | |
28 | * | |
29 | * Instructions use the gnu assembler syntax, with the addition of | |
30 | * allowing mnemonics for register. | |
31 | * Eg. "func $2,reg3,0x100,symbol ; comment" | |
32 | * func - opcode name | |
33 | * $n - register n | |
34 | * reg3 - mnemonic for processor's register defined in table | |
35 | * 0xddd..d - immediate value | |
36 | * symbol - address of label or external symbol | |
37 | * | |
38 | * First, itbl_parse reads in the table of register and instruction | |
39 | * names and formats, and builds a list of entries for each | |
40 | * processor/type combination. lex and yacc are used to parse | |
41 | * the entries in the table and call functions defined here to | |
42 | * add each entry to our list. | |
43 | * | |
44 | * Then, when assembling or disassembling, these functions are called to | |
45 | * 1) get information on a processor's registers and | |
46 | * 2) assemble/disassemble an instruction. | |
47 | * To assemble(disassemble) an instruction, the function | |
48 | * itbl_assemble(itbl_disassemble) is called to search the list of | |
49 | * instruction entries, and if a match is found, uses the format | |
50 | * described in the instruction entry structure to complete the action. | |
51 | * | |
52 | * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2" | |
53 | * and we want to define function "pig" which takes two operands. | |
54 | * | |
55 | * Given the table entries: | |
56 | * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0" | |
57 | * "p3 dreg d2 0x2" | |
58 | * and that the instruction encoding for coprocessor pz has encoding: | |
59 | * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25) | |
60 | * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum) | |
61 | * | |
62 | * a structure to describe the instruction might look something like: | |
63 | * struct itbl_entry = { | |
64 | * e_processor processor = e_p3 | |
65 | * e_type type = e_insn | |
66 | * char *name = "pig" | |
67 | * uint value = 0x1 | |
68 | * uint flags = 0 | |
69 | * struct itbl_range range = 24-21 | |
70 | * struct itbl_field *field = { | |
71 | * e_type type = e_dreg | |
72 | * struct itbl_range range = 20-16 | |
73 | * struct itbl_field *next = { | |
74 | * e_type type = e_immed | |
75 | * struct itbl_range range = 15-0 | |
76 | * struct itbl_field *next = 0 | |
77 | * }; | |
78 | * }; | |
79 | * struct itbl_entry *next = 0 | |
80 | * }; | |
81 | * | |
82 | * And the assembler instructions: | |
83 | * "pig d2,0x100" | |
84 | * "pig $2,0x100" | |
85 | * | |
86 | * would both assemble to the hex value: | |
87 | * "0x4e220100" | |
88 | * | |
89 | */ | |
90 | ||
91 | #include <stdio.h> | |
92 | #include <stdlib.h> | |
93 | #include <string.h> | |
94 | #include "itbl-ops.h" | |
95 | #include "itbl-parse.h" | |
96 | ||
97 | /* #define DEBUG */ | |
98 | ||
99 | #ifdef DEBUG | |
100 | #include <assert.h> | |
101 | #define ASSERT(x) assert(x) | |
102 | #define DBG(x) printf x | |
103 | #else | |
104 | #define ASSERT(x) | |
105 | #define DBG(x) | |
106 | #endif | |
107 | ||
108 | #ifndef min | |
109 | #define min(a,b) (a<b?a:b) | |
110 | #endif | |
111 | ||
112 | int itbl_have_entries = 0; | |
113 | ||
114 | /*======================================================================*/ | |
115 | /* structures for keeping itbl format entries */ | |
116 | ||
117 | struct itbl_range | |
118 | { | |
119 | int sbit; /* mask starting bit position */ | |
120 | int ebit; /* mask ending bit position */ | |
121 | }; | |
122 | ||
123 | struct itbl_field | |
124 | { | |
125 | e_type type; /* dreg/creg/greg/immed/symb */ | |
126 | struct itbl_range range; /* field's bitfield range within instruction */ | |
127 | unsigned long flags; /* field flags */ | |
128 | struct itbl_field *next; /* next field in list */ | |
129 | }; | |
130 | ||
252b5132 RH |
131 | /* These structures define the instructions and registers for a processor. |
132 | * If the type is an instruction, the structure defines the format of an | |
133 | * instruction where the fields are the list of operands. | |
134 | * The flags field below uses the same values as those defined in the | |
c488923f | 135 | * gnu assembler and are machine specific. */ |
252b5132 RH |
136 | struct itbl_entry |
137 | { | |
138 | e_processor processor; /* processor number */ | |
139 | e_type type; /* dreg/creg/greg/insn */ | |
140 | char *name; /* mnemionic name for insn/register */ | |
141 | unsigned long value; /* opcode/instruction mask/register number */ | |
142 | unsigned long flags; /* effects of the instruction */ | |
143 | struct itbl_range range; /* bit range within instruction for value */ | |
144 | struct itbl_field *fields; /* list of operand definitions (if any) */ | |
145 | struct itbl_entry *next; /* next entry */ | |
146 | }; | |
147 | ||
252b5132 RH |
148 | /* local data and structures */ |
149 | ||
150 | static int itbl_num_opcodes = 0; | |
151 | /* Array of entries for each processor and entry type */ | |
152 | static struct itbl_entry *entries[e_nprocs][e_ntypes] = | |
153 | { | |
154 | {0, 0, 0, 0, 0, 0}, | |
155 | {0, 0, 0, 0, 0, 0}, | |
156 | {0, 0, 0, 0, 0, 0}, | |
157 | {0, 0, 0, 0, 0, 0} | |
158 | }; | |
159 | ||
160 | /* local prototypes */ | |
161 | static unsigned long build_opcode PARAMS ((struct itbl_entry *e)); | |
162 | static e_type get_type PARAMS ((int yytype)); | |
163 | static e_processor get_processor PARAMS ((int yyproc)); | |
c488923f | 164 | static struct itbl_entry **get_entries PARAMS ((e_processor processor, |
252b5132 | 165 | e_type type)); |
c488923f | 166 | static struct itbl_entry *find_entry_byname PARAMS ((e_processor processor, |
252b5132 | 167 | e_type type, char *name)); |
c488923f | 168 | static struct itbl_entry *find_entry_byval PARAMS ((e_processor processor, |
252b5132 | 169 | e_type type, unsigned long val, struct itbl_range *r)); |
c488923f | 170 | static struct itbl_entry *alloc_entry PARAMS ((e_processor processor, |
252b5132 | 171 | e_type type, char *name, unsigned long value)); |
c488923f | 172 | static unsigned long apply_range PARAMS ((unsigned long value, |
252b5132 | 173 | struct itbl_range r)); |
c488923f | 174 | static unsigned long extract_range PARAMS ((unsigned long value, |
252b5132 | 175 | struct itbl_range r)); |
c488923f | 176 | static struct itbl_field *alloc_field PARAMS ((e_type type, int sbit, |
252b5132 RH |
177 | int ebit, unsigned long flags)); |
178 | ||
252b5132 RH |
179 | /*======================================================================*/ |
180 | /* Interfaces to the parser */ | |
181 | ||
252b5132 RH |
182 | /* Open the table and use lex and yacc to parse the entries. |
183 | * Return 1 for failure; 0 for success. */ | |
184 | ||
c488923f | 185 | int |
252b5132 RH |
186 | itbl_parse (char *insntbl) |
187 | { | |
188 | extern FILE *yyin; | |
189 | extern int yyparse (void); | |
190 | yyin = fopen (insntbl, "r"); | |
191 | if (yyin == 0) | |
192 | { | |
193 | printf ("Can't open processor instruction specification file \"%s\"\n", | |
194 | insntbl); | |
195 | return 1; | |
196 | } | |
197 | else | |
198 | { | |
199 | while (yyparse ()); | |
200 | } | |
201 | fclose (yyin); | |
202 | itbl_have_entries = 1; | |
203 | return 0; | |
204 | } | |
205 | ||
206 | /* Add a register entry */ | |
207 | ||
208 | struct itbl_entry * | |
209 | itbl_add_reg (int yyprocessor, int yytype, char *regname, | |
210 | int regnum) | |
211 | { | |
c488923f | 212 | #if 0 |
252b5132 RH |
213 | #include "as.h" |
214 | #include "symbols.h" | |
215 | /* Since register names don't have a prefix, we put them in the symbol table so | |
216 | they can't be used as symbols. This also simplifies argument parsing as | |
217 | we can let gas parse registers for us. The recorded register number is | |
218 | regnum. */ | |
219 | /* Use symbol_create here instead of symbol_new so we don't try to | |
220 | output registers into the object file's symbol table. */ | |
221 | symbol_table_insert (symbol_create (regname, reg_section, | |
222 | regnum, &zero_address_frag)); | |
223 | #endif | |
224 | return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname, | |
225 | (unsigned long) regnum); | |
226 | } | |
227 | ||
228 | /* Add an instruction entry */ | |
229 | ||
230 | struct itbl_entry * | |
231 | itbl_add_insn (int yyprocessor, char *name, unsigned long value, | |
232 | int sbit, int ebit, unsigned long flags) | |
233 | { | |
234 | struct itbl_entry *e; | |
235 | e = alloc_entry (get_processor (yyprocessor), e_insn, name, value); | |
236 | if (e) | |
237 | { | |
238 | e->range.sbit = sbit; | |
239 | e->range.ebit = ebit; | |
240 | e->flags = flags; | |
241 | itbl_num_opcodes++; | |
242 | } | |
243 | return e; | |
244 | } | |
245 | ||
246 | /* Add an operand to an instruction entry */ | |
247 | ||
248 | struct itbl_field * | |
249 | itbl_add_operand (struct itbl_entry *e, int yytype, int sbit, | |
250 | int ebit, unsigned long flags) | |
251 | { | |
252 | struct itbl_field *f, **last_f; | |
253 | if (!e) | |
254 | return 0; | |
c488923f | 255 | /* Add to end of fields' list. */ |
252b5132 RH |
256 | f = alloc_field (get_type (yytype), sbit, ebit, flags); |
257 | if (f) | |
258 | { | |
259 | last_f = &e->fields; | |
260 | while (*last_f) | |
261 | last_f = &(*last_f)->next; | |
262 | *last_f = f; | |
263 | f->next = 0; | |
264 | } | |
265 | return f; | |
266 | } | |
267 | ||
252b5132 RH |
268 | /*======================================================================*/ |
269 | /* Interfaces for assembler and disassembler */ | |
270 | ||
271 | #ifndef STAND_ALONE | |
272 | #include "as.h" | |
273 | #include "symbols.h" | |
274 | static void append_insns_as_macros (void); | |
275 | ||
276 | /* initialize for gas */ | |
c488923f | 277 | void |
252b5132 RH |
278 | itbl_init (void) |
279 | { | |
280 | struct itbl_entry *e, **es; | |
281 | e_processor procn; | |
282 | e_type type; | |
283 | ||
284 | if (!itbl_have_entries) | |
285 | return; | |
286 | ||
287 | /* Since register names don't have a prefix, put them in the symbol table so | |
288 | they can't be used as symbols. This simplifies argument parsing as | |
c488923f | 289 | we can let gas parse registers for us. */ |
252b5132 RH |
290 | /* Use symbol_create instead of symbol_new so we don't try to |
291 | output registers into the object file's symbol table. */ | |
292 | ||
293 | for (type = e_regtype0; type < e_nregtypes; type++) | |
294 | for (procn = e_p0; procn < e_nprocs; procn++) | |
295 | { | |
296 | es = get_entries (procn, type); | |
297 | for (e = *es; e; e = e->next) | |
298 | { | |
299 | symbol_table_insert (symbol_create (e->name, reg_section, | |
300 | e->value, &zero_address_frag)); | |
301 | } | |
302 | } | |
303 | append_insns_as_macros (); | |
304 | } | |
305 | ||
c488923f KH |
306 | /* Append insns to opcodes table and increase number of opcodes |
307 | * Structure of opcodes table: | |
252b5132 RH |
308 | * struct itbl_opcode |
309 | * { | |
310 | * const char *name; | |
c488923f KH |
311 | * const char *args; - string describing the arguments. |
312 | * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO | |
313 | * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO | |
314 | * unsigned long pinfo; - insn flags, or INSN_MACRO | |
252b5132 RH |
315 | * }; |
316 | * examples: | |
317 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, | |
318 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, | |
319 | */ | |
320 | ||
321 | static char *form_args (struct itbl_entry *e); | |
c488923f | 322 | static void |
252b5132 RH |
323 | append_insns_as_macros (void) |
324 | { | |
325 | struct ITBL_OPCODE_STRUCT *new_opcodes, *o; | |
326 | struct itbl_entry *e, **es; | |
327 | int n, id, size, new_size, new_num_opcodes; | |
328 | ||
329 | if (!itbl_have_entries) | |
330 | return; | |
331 | ||
332 | if (!itbl_num_opcodes) /* no new instructions to add! */ | |
333 | { | |
334 | return; | |
335 | } | |
336 | DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES)); | |
337 | ||
338 | new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes; | |
339 | ASSERT (new_num_opcodes >= itbl_num_opcodes); | |
340 | ||
341 | size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES; | |
342 | ASSERT (size >= 0); | |
343 | DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0]))); | |
344 | ||
345 | new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes; | |
346 | ASSERT (new_size > size); | |
347 | ||
348 | /* FIXME since ITBL_OPCODES culd be a static table, | |
c488923f | 349 | we can't realloc or delete the old memory. */ |
252b5132 RH |
350 | new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size); |
351 | if (!new_opcodes) | |
352 | { | |
353 | printf (_("Unable to allocate memory for new instructions\n")); | |
354 | return; | |
355 | } | |
356 | if (size) /* copy prexisting opcodes table */ | |
357 | memcpy (new_opcodes, ITBL_OPCODES, size); | |
358 | ||
359 | /* FIXME! some NUMOPCODES are calculated expressions. | |
c488923f | 360 | These need to be changed before itbls can be supported. */ |
252b5132 RH |
361 | |
362 | id = ITBL_NUM_MACROS; /* begin the next macro id after the last */ | |
363 | o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */ | |
364 | for (n = e_p0; n < e_nprocs; n++) | |
365 | { | |
366 | es = get_entries (n, e_insn); | |
367 | for (e = *es; e; e = e->next) | |
368 | { | |
369 | /* name, args, mask, match, pinfo | |
370 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, | |
371 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, | |
372 | * Construct args from itbl_fields. | |
373 | */ | |
374 | o->name = e->name; | |
375 | o->args = strdup (form_args (e)); | |
376 | o->mask = apply_range (e->value, e->range); | |
377 | /* FIXME how to catch durring assembly? */ | |
378 | /* mask to identify this insn */ | |
379 | o->match = apply_range (e->value, e->range); | |
380 | o->pinfo = 0; | |
381 | ||
382 | #ifdef USE_MACROS | |
383 | o->mask = id++; /* FIXME how to catch durring assembly? */ | |
384 | o->match = 0; /* for macros, the insn_isa number */ | |
385 | o->pinfo = INSN_MACRO; | |
386 | #endif | |
387 | ||
388 | /* Don't add instructions which caused an error */ | |
389 | if (o->args) | |
390 | o++; | |
391 | else | |
392 | new_num_opcodes--; | |
393 | } | |
394 | } | |
395 | ITBL_OPCODES = new_opcodes; | |
396 | ITBL_NUM_OPCODES = new_num_opcodes; | |
397 | ||
398 | /* FIXME | |
399 | At this point, we can free the entries, as they should have | |
400 | been added to the assembler's tables. | |
401 | Don't free name though, since name is being used by the new | |
402 | opcodes table. | |
403 | ||
c488923f | 404 | Eventually, we should also free the new opcodes table itself |
252b5132 RH |
405 | on exit. |
406 | */ | |
407 | } | |
408 | ||
409 | static char * | |
410 | form_args (struct itbl_entry *e) | |
411 | { | |
412 | static char s[31]; | |
413 | char c = 0, *p = s; | |
414 | struct itbl_field *f; | |
415 | ||
416 | ASSERT (e); | |
417 | for (f = e->fields; f; f = f->next) | |
418 | { | |
419 | switch (f->type) | |
420 | { | |
421 | case e_dreg: | |
422 | c = 'd'; | |
423 | break; | |
424 | case e_creg: | |
425 | c = 't'; | |
426 | break; | |
427 | case e_greg: | |
428 | c = 's'; | |
429 | break; | |
430 | case e_immed: | |
431 | c = 'i'; | |
432 | break; | |
433 | case e_addr: | |
434 | c = 'a'; | |
435 | break; | |
436 | default: | |
437 | c = 0; /* ignore; unknown field type */ | |
438 | } | |
439 | if (c) | |
440 | { | |
441 | if (p != s) | |
442 | *p++ = ','; | |
443 | *p++ = c; | |
444 | } | |
445 | } | |
446 | *p = 0; | |
447 | return s; | |
448 | } | |
449 | #endif /* !STAND_ALONE */ | |
450 | ||
252b5132 RH |
451 | /* Get processor's register name from val */ |
452 | ||
d7ba4a77 ILT |
453 | int |
454 | itbl_get_reg_val (char *name, unsigned long *pval) | |
252b5132 RH |
455 | { |
456 | e_type t; | |
457 | e_processor p; | |
d7ba4a77 | 458 | |
252b5132 | 459 | for (p = e_p0; p < e_nprocs; p++) |
d7ba4a77 ILT |
460 | { |
461 | for (t = e_regtype0; t < e_nregtypes; t++) | |
462 | { | |
463 | if (itbl_get_val (p, t, name, pval)) | |
464 | return 1; | |
465 | } | |
466 | } | |
252b5132 RH |
467 | return 0; |
468 | } | |
469 | ||
470 | char * | |
471 | itbl_get_name (e_processor processor, e_type type, unsigned long val) | |
472 | { | |
473 | struct itbl_entry *r; | |
474 | /* type depends on instruction passed */ | |
475 | r = find_entry_byval (processor, type, val, 0); | |
476 | if (r) | |
477 | return r->name; | |
478 | else | |
479 | return 0; /* error; invalid operand */ | |
480 | } | |
481 | ||
482 | /* Get processor's register value from name */ | |
483 | ||
d7ba4a77 ILT |
484 | int |
485 | itbl_get_val (e_processor processor, e_type type, char *name, | |
486 | unsigned long *pval) | |
252b5132 RH |
487 | { |
488 | struct itbl_entry *r; | |
489 | /* type depends on instruction passed */ | |
490 | r = find_entry_byname (processor, type, name); | |
d7ba4a77 ILT |
491 | if (r == NULL) |
492 | return 0; | |
493 | *pval = r->value; | |
494 | return 1; | |
252b5132 RH |
495 | } |
496 | ||
252b5132 RH |
497 | /* Assemble instruction "name" with operands "s". |
498 | * name - name of instruction | |
499 | * s - operands | |
500 | * returns - long word for assembled instruction */ | |
501 | ||
c488923f | 502 | unsigned long |
252b5132 RH |
503 | itbl_assemble (char *name, char *s) |
504 | { | |
505 | unsigned long opcode; | |
506 | struct itbl_entry *e; | |
507 | struct itbl_field *f; | |
508 | char *n; | |
509 | int processor; | |
510 | ||
511 | if (!name || !*name) | |
512 | return 0; /* error! must have a opcode name/expr */ | |
513 | ||
514 | /* find entry in list of instructions for all processors */ | |
515 | for (processor = 0; processor < e_nprocs; processor++) | |
516 | { | |
517 | e = find_entry_byname (processor, e_insn, name); | |
518 | if (e) | |
519 | break; | |
520 | } | |
521 | if (!e) | |
522 | return 0; /* opcode not in table; invalid instrustion */ | |
523 | opcode = build_opcode (e); | |
524 | ||
525 | /* parse opcode's args (if any) */ | |
c488923f | 526 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ |
252b5132 RH |
527 | { |
528 | struct itbl_entry *r; | |
529 | unsigned long value; | |
530 | if (!s || !*s) | |
531 | return 0; /* error - not enough operands */ | |
532 | n = itbl_get_field (&s); | |
533 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ | |
534 | switch (f->type) | |
535 | { | |
536 | case e_dreg: | |
537 | case e_creg: | |
538 | case e_greg: | |
539 | /* Accept either a string name | |
540 | * or '$' followed by the register number */ | |
541 | if (*n == '$') | |
542 | { | |
543 | n++; | |
544 | value = strtol (n, 0, 10); | |
545 | /* FIXME! could have "0l"... then what?? */ | |
546 | if (value == 0 && *n != '0') | |
547 | return 0; /* error; invalid operand */ | |
548 | } | |
549 | else | |
550 | { | |
551 | r = find_entry_byname (e->processor, f->type, n); | |
552 | if (r) | |
553 | value = r->value; | |
554 | else | |
555 | return 0; /* error; invalid operand */ | |
556 | } | |
557 | break; | |
558 | case e_addr: | |
559 | /* use assembler's symbol table to find symbol */ | |
560 | /* FIXME!! Do we need this? | |
561 | if so, what about relocs?? | |
562 | my_getExpression (&imm_expr, s); | |
563 | return 0; /-* error; invalid operand *-/ | |
564 | break; | |
565 | */ | |
566 | /* If not a symbol, fall thru to IMMED */ | |
567 | case e_immed: | |
c488923f | 568 | if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */ |
252b5132 RH |
569 | { |
570 | n += 2; | |
571 | value = strtol (n, 0, 16); | |
572 | /* FIXME! could have "0xl"... then what?? */ | |
573 | } | |
574 | else | |
575 | { | |
576 | value = strtol (n, 0, 10); | |
577 | /* FIXME! could have "0l"... then what?? */ | |
578 | if (value == 0 && *n != '0') | |
579 | return 0; /* error; invalid operand */ | |
580 | } | |
581 | break; | |
582 | default: | |
583 | return 0; /* error; invalid field spec */ | |
584 | } | |
585 | opcode |= apply_range (value, f->range); | |
586 | } | |
587 | if (s && *s) | |
588 | return 0; /* error - too many operands */ | |
589 | return opcode; /* done! */ | |
590 | } | |
591 | ||
592 | /* Disassemble instruction "insn". | |
593 | * insn - instruction | |
594 | * s - buffer to hold disassembled instruction | |
595 | * returns - 1 if succeeded; 0 if failed | |
596 | */ | |
597 | ||
c488923f | 598 | int |
252b5132 RH |
599 | itbl_disassemble (char *s, unsigned long insn) |
600 | { | |
601 | e_processor processor; | |
602 | struct itbl_entry *e; | |
603 | struct itbl_field *f; | |
604 | ||
605 | if (!ITBL_IS_INSN (insn)) | |
606 | return 0; /* error*/ | |
607 | processor = get_processor (ITBL_DECODE_PNUM (insn)); | |
608 | ||
609 | /* find entry in list */ | |
610 | e = find_entry_byval (processor, e_insn, insn, 0); | |
611 | if (!e) | |
612 | return 0; /* opcode not in table; invalid instrustion */ | |
613 | strcpy (s, e->name); | |
614 | ||
615 | /* parse insn's args (if any) */ | |
c488923f | 616 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ |
252b5132 RH |
617 | { |
618 | struct itbl_entry *r; | |
619 | unsigned long value; | |
620 | ||
621 | if (f == e->fields) /* first operand is preceeded by tab */ | |
622 | strcat (s, "\t"); | |
623 | else /* ','s separate following operands */ | |
624 | strcat (s, ","); | |
625 | value = extract_range (insn, f->range); | |
626 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ | |
627 | switch (f->type) | |
628 | { | |
629 | case e_dreg: | |
630 | case e_creg: | |
631 | case e_greg: | |
632 | /* Accept either a string name | |
633 | * or '$' followed by the register number */ | |
634 | r = find_entry_byval (e->processor, f->type, value, &f->range); | |
635 | if (r) | |
636 | strcat (s, r->name); | |
637 | else | |
41e60a82 | 638 | sprintf (s, "%s$%lu", s, value); |
252b5132 RH |
639 | break; |
640 | case e_addr: | |
641 | /* use assembler's symbol table to find symbol */ | |
642 | /* FIXME!! Do we need this? | |
643 | * if so, what about relocs?? | |
644 | */ | |
645 | /* If not a symbol, fall thru to IMMED */ | |
646 | case e_immed: | |
41e60a82 | 647 | sprintf (s, "%s0x%lx", s, value); |
252b5132 RH |
648 | break; |
649 | default: | |
650 | return 0; /* error; invalid field spec */ | |
651 | } | |
652 | } | |
653 | return 1; /* done! */ | |
654 | } | |
655 | ||
656 | /*======================================================================*/ | |
657 | /* | |
658 | * Local functions for manipulating private structures containing | |
659 | * the names and format for the new instructions and registers | |
660 | * for each processor. | |
661 | */ | |
662 | ||
663 | /* Calculate instruction's opcode and function values from entry */ | |
664 | ||
c488923f | 665 | static unsigned long |
252b5132 RH |
666 | build_opcode (struct itbl_entry *e) |
667 | { | |
668 | unsigned long opcode; | |
669 | ||
670 | opcode = apply_range (e->value, e->range); | |
671 | opcode |= ITBL_ENCODE_PNUM (e->processor); | |
672 | return opcode; | |
673 | } | |
674 | ||
675 | /* Calculate absolute value given the relative value and bit position range | |
676 | * within the instruction. | |
677 | * The range is inclusive where 0 is least significant bit. | |
678 | * A range of { 24, 20 } will have a mask of | |
679 | * bit 3 2 1 | |
680 | * pos: 1098 7654 3210 9876 5432 1098 7654 3210 | |
681 | * bin: 0000 0001 1111 0000 0000 0000 0000 0000 | |
682 | * hex: 0 1 f 0 0 0 0 0 | |
683 | * mask: 0x01f00000. | |
684 | */ | |
685 | ||
c488923f | 686 | static unsigned long |
252b5132 RH |
687 | apply_range (unsigned long rval, struct itbl_range r) |
688 | { | |
689 | unsigned long mask; | |
690 | unsigned long aval; | |
691 | int len = MAX_BITPOS - r.sbit; | |
692 | ||
693 | ASSERT (r.sbit >= r.ebit); | |
694 | ASSERT (MAX_BITPOS >= r.sbit); | |
695 | ASSERT (r.ebit >= 0); | |
696 | ||
697 | /* create mask by truncating 1s by shifting */ | |
698 | mask = 0xffffffff << len; | |
699 | mask = mask >> len; | |
700 | mask = mask >> r.ebit; | |
701 | mask = mask << r.ebit; | |
702 | ||
703 | aval = (rval << r.ebit) & mask; | |
704 | return aval; | |
705 | } | |
706 | ||
707 | /* Calculate relative value given the absolute value and bit position range | |
708 | * within the instruction. */ | |
709 | ||
c488923f | 710 | static unsigned long |
252b5132 RH |
711 | extract_range (unsigned long aval, struct itbl_range r) |
712 | { | |
713 | unsigned long mask; | |
714 | unsigned long rval; | |
715 | int len = MAX_BITPOS - r.sbit; | |
716 | ||
717 | /* create mask by truncating 1s by shifting */ | |
718 | mask = 0xffffffff << len; | |
719 | mask = mask >> len; | |
720 | mask = mask >> r.ebit; | |
721 | mask = mask << r.ebit; | |
722 | ||
723 | rval = (aval & mask) >> r.ebit; | |
724 | return rval; | |
725 | } | |
726 | ||
727 | /* Extract processor's assembly instruction field name from s; | |
728 | * forms are "n args" "n,args" or "n" */ | |
729 | /* Return next argument from string pointer "s" and advance s. | |
d7ba4a77 | 730 | * delimiters are " ,()" */ |
252b5132 RH |
731 | |
732 | char * | |
733 | itbl_get_field (char **S) | |
734 | { | |
735 | static char n[128]; | |
41e60a82 | 736 | char *s; |
252b5132 RH |
737 | int len; |
738 | ||
739 | s = *S; | |
740 | if (!s || !*s) | |
741 | return 0; | |
d7ba4a77 ILT |
742 | /* FIXME: This is a weird set of delimiters. */ |
743 | len = strcspn (s, " \t,()"); | |
252b5132 RH |
744 | ASSERT (128 > len + 1); |
745 | strncpy (n, s, len); | |
746 | n[len] = 0; | |
747 | if (s[len] == '\0') | |
748 | s = 0; /* no more args */ | |
749 | else | |
750 | s += len + 1; /* advance to next arg */ | |
751 | ||
752 | *S = s; | |
753 | return n; | |
754 | } | |
755 | ||
756 | /* Search entries for a given processor and type | |
757 | * to find one matching the name "n". | |
758 | * Return a pointer to the entry */ | |
759 | ||
760 | static struct itbl_entry * | |
761 | find_entry_byname (e_processor processor, | |
762 | e_type type, char *n) | |
763 | { | |
764 | struct itbl_entry *e, **es; | |
765 | ||
766 | es = get_entries (processor, type); | |
c488923f | 767 | for (e = *es; e; e = e->next) /* for each entry, ... */ |
252b5132 RH |
768 | { |
769 | if (!strcmp (e->name, n)) | |
770 | return e; | |
771 | } | |
772 | return 0; | |
773 | } | |
774 | ||
775 | /* Search entries for a given processor and type | |
776 | * to find one matching the value "val" for the range "r". | |
777 | * Return a pointer to the entry. | |
778 | * This function is used for disassembling fields of an instruction. | |
779 | */ | |
780 | ||
781 | static struct itbl_entry * | |
782 | find_entry_byval (e_processor processor, e_type type, | |
783 | unsigned long val, struct itbl_range *r) | |
784 | { | |
785 | struct itbl_entry *e, **es; | |
786 | unsigned long eval; | |
787 | ||
788 | es = get_entries (processor, type); | |
c488923f | 789 | for (e = *es; e; e = e->next) /* for each entry, ... */ |
252b5132 RH |
790 | { |
791 | if (processor != e->processor) | |
792 | continue; | |
793 | /* For insns, we might not know the range of the opcode, | |
794 | * so a range of 0 will allow this routine to match against | |
795 | * the range of the entry to be compared with. | |
796 | * This could cause ambiguities. | |
797 | * For operands, we get an extracted value and a range. | |
798 | */ | |
c488923f | 799 | /* if range is 0, mask val against the range of the compared entry. */ |
252b5132 RH |
800 | if (r == 0) /* if no range passed, must be whole 32-bits |
801 | * so create 32-bit value from entry's range */ | |
802 | { | |
803 | eval = apply_range (e->value, e->range); | |
804 | val &= apply_range (0xffffffff, e->range); | |
805 | } | |
41e60a82 ILT |
806 | else if ((r->sbit == e->range.sbit && r->ebit == e->range.ebit) |
807 | || (e->range.sbit == 0 && e->range.ebit == 0)) | |
252b5132 RH |
808 | { |
809 | eval = apply_range (e->value, *r); | |
810 | val = apply_range (val, *r); | |
811 | } | |
812 | else | |
813 | continue; | |
814 | if (val == eval) | |
815 | return e; | |
816 | } | |
817 | return 0; | |
818 | } | |
819 | ||
c488923f | 820 | /* Return a pointer to the list of entries for a given processor and type. */ |
252b5132 RH |
821 | |
822 | static struct itbl_entry ** | |
823 | get_entries (e_processor processor, e_type type) | |
824 | { | |
825 | return &entries[processor][type]; | |
826 | } | |
827 | ||
c488923f | 828 | /* Return an integral value for the processor passed from yyparse. */ |
252b5132 | 829 | |
c488923f | 830 | static e_processor |
252b5132 RH |
831 | get_processor (int yyproc) |
832 | { | |
833 | /* translate from yacc's processor to enum */ | |
834 | if (yyproc >= e_p0 && yyproc < e_nprocs) | |
835 | return (e_processor) yyproc; | |
836 | return e_invproc; /* error; invalid processor */ | |
837 | } | |
838 | ||
c488923f | 839 | /* Return an integral value for the entry type passed from yyparse. */ |
252b5132 | 840 | |
c488923f | 841 | static e_type |
252b5132 RH |
842 | get_type (int yytype) |
843 | { | |
844 | switch (yytype) | |
845 | { | |
846 | /* translate from yacc's type to enum */ | |
847 | case INSN: | |
848 | return e_insn; | |
849 | case DREG: | |
850 | return e_dreg; | |
851 | case CREG: | |
852 | return e_creg; | |
853 | case GREG: | |
854 | return e_greg; | |
855 | case ADDR: | |
856 | return e_addr; | |
857 | case IMMED: | |
858 | return e_immed; | |
859 | default: | |
860 | return e_invtype; /* error; invalid type */ | |
861 | } | |
862 | } | |
863 | ||
252b5132 RH |
864 | /* Allocate and initialize an entry */ |
865 | ||
866 | static struct itbl_entry * | |
867 | alloc_entry (e_processor processor, e_type type, | |
868 | char *name, unsigned long value) | |
869 | { | |
870 | struct itbl_entry *e, **es; | |
871 | if (!name) | |
872 | return 0; | |
873 | e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry)); | |
874 | if (e) | |
875 | { | |
876 | memset (e, 0, sizeof (struct itbl_entry)); | |
877 | e->name = (char *) malloc (sizeof (strlen (name)) + 1); | |
878 | if (e->name) | |
879 | strcpy (e->name, name); | |
880 | e->processor = processor; | |
881 | e->type = type; | |
882 | e->value = value; | |
883 | es = get_entries (e->processor, e->type); | |
884 | e->next = *es; | |
885 | *es = e; | |
886 | } | |
887 | return e; | |
888 | } | |
889 | ||
890 | /* Allocate and initialize an entry's field */ | |
891 | ||
892 | static struct itbl_field * | |
893 | alloc_field (e_type type, int sbit, int ebit, | |
894 | unsigned long flags) | |
895 | { | |
896 | struct itbl_field *f; | |
897 | f = (struct itbl_field *) malloc (sizeof (struct itbl_field)); | |
898 | if (f) | |
899 | { | |
900 | memset (f, 0, sizeof (struct itbl_field)); | |
901 | f->type = type; | |
902 | f->range.sbit = sbit; | |
903 | f->range.ebit = ebit; | |
904 | f->flags = flags; | |
905 | } | |
906 | return f; | |
907 | } |