Commit | Line | Data |
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e9dbdd80 TC |
1 | # Print a 4 operand instruction |
2 | .macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2= | |
3 | .ifnb \d | |
4 | \op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2 | |
5 | .else | |
6 | .ifnb \n | |
7 | \op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2 | |
8 | .else | |
9 | \op \pm1\m\()\pm2, \pw1\w\()\pw2 | |
10 | .endif | |
11 | .endif | |
12 | .endm | |
13 | ||
14 | .macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r | |
15 | .irp m, 03, 82, 13 | |
16 | \op \pd1\d\()\pd2, [\r, \m] | |
17 | .endr | |
18 | .endm | |
19 | ||
20 | .macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2= | |
21 | .irp w, 3, 11, 15 | |
22 | print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2 | |
23 | .endr | |
24 | .endm | |
25 | ||
26 | .macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2= | |
27 | .irp m, 0, 8, 12 | |
28 | gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2 | |
29 | .endr | |
30 | .endm | |
31 | ||
32 | .macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2= | |
33 | .irp n, 2, 15, 30 | |
34 | gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2 | |
35 | .endr | |
36 | .endm | |
37 | ||
38 | .macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2= | |
39 | .irp d, 0, 7, 16, 30 | |
40 | gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2 | |
41 | .endr | |
42 | .endm | |
43 | ||
44 | # Print a 3 operand instruction | |
45 | .macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2= | |
46 | .irp d, 0, 7, 16, 30 | |
47 | gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2 | |
48 | .endr | |
49 | .endm | |
50 | ||
51 | .macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg | |
52 | .irp l, \x | |
53 | gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l] | |
54 | .endr | |
55 | .endm | |
56 | ||
57 | # Print a 2 operand instruction | |
58 | .macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2= | |
59 | .irp d, 0, 7, 16, 30 | |
60 | gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2 | |
61 | .endr | |
62 | .endm | |
63 | ||
64 | .macro gen2reg_iter_offset op, pd1=, pd2=, r | |
65 | .irp d, 0, 7, 16, 30 | |
66 | gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r, | |
67 | .endr | |
68 | .endm | |
69 | ||
70 | # Print a 1 operand instruction | |
71 | .macro gen1reg_iter op, pd1=, pd2= | |
72 | .irp d, 0, 7, 16, 30 | |
73 | \op \pd1\d\()\pd2 | |
74 | .endr | |
75 | .endm | |
76 | ||
77 | .text | |
78 | func: | |
79 | gen3reg_iter sha512h q,, q,, v,.2d | |
80 | gen3reg_iter sha512h2 q,, q,, v,.2d | |
81 | gen2reg_iter sha512su0 v,.2d, v,.2d | |
82 | gen3reg_iter sha512su1 v,.2d, v,.2d, v,.2d | |
83 | gen4reg_iter eor3 v,.16b, v,.16b, v,.16b, v,.16b | |
84 | gen3reg_iter rax1 v,.2d, v,.2d, v,.2d | |
85 | gen4reg_iter xar v,.2d, v,.2d, v,.2d,, | |
86 | gen4reg_iter bcax v,.16b, v,.16b, v,.16b, v,.16b | |
87 | ||
88 | gen4reg_iter sm3ss1 v,.4s, v,.4s, v,.4s, v,.4s | |
89 | gen3reg_iter_lane sm3tt1a v,.4s, v,.4s, v,.s, 0, 1, 2, 3 | |
90 | gen3reg_iter_lane sm3tt1b v,.4s, v,.4s, v,.s, 0, 1, 2, 3 | |
91 | gen3reg_iter_lane sm3tt2a v,.4s, v,.4s, v,.s, 0, 1, 2, 3 | |
92 | gen3reg_iter_lane sm3tt2b v,.4s, v,.4s, v,.s, 0, 1, 2, 3 | |
93 | gen3reg_iter sm3partw1 v,.4s, v,.4s, v,.4s | |
94 | gen3reg_iter sm3partw2 v,.4s, v,.4s, v,.4s | |
95 | ||
96 | gen2reg_iter sm4e v,.4s, v,.4s | |
97 | gen3reg_iter sm4ekey v,.4s, v,.4s, v,.4s | |
98 | ||
99 | gen3reg_iter fmlal v,.2s, v,.2h, v,.2h | |
100 | gen3reg_iter fmlal v,.4s, v,.4h, v,.4h | |
101 | gen3reg_iter fmlsl v,.2s, v,.2h, v,.2h | |
102 | gen3reg_iter fmlsl v,.4s, v,.4h, v,.4h | |
103 | ||
104 | gen3reg_iter fmlal2 v,.2s, v,.2h, v,.2h | |
105 | gen3reg_iter fmlal2 v,.4s, v,.4h, v,.4h | |
106 | gen3reg_iter fmlsl2 v,.2s, v,.2h, v,.2h | |
107 | gen3reg_iter fmlsl2 v,.4s, v,.4h, v,.4h | |
108 | ||
109 | gen3reg_iter_lane fmlal v,.2s, v,.2h, v,.h, 0, 1, 5, 7 | |
110 | gen3reg_iter_lane fmlal v,.4s, v,.4h, v,.h, 0, 1, 5, 7 | |
111 | gen3reg_iter_lane fmlsl v,.2s, v,.2h, v,.h, 0, 1, 5, 7 | |
112 | gen3reg_iter_lane fmlsl v,.4s, v,.4h, v,.h, 0, 1, 5, 7 | |
113 | ||
114 | gen3reg_iter_lane fmlal2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7 | |
115 | gen3reg_iter_lane fmlal2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7 | |
116 | gen3reg_iter_lane fmlsl2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7 | |
117 | gen3reg_iter_lane fmlsl2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7 | |
118 |