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a06ea964 NC |
1 | /* ldst-reg-unscaled-imm.s Test file for AArch64 |
2 | load-store reg. (unscaled imm.) instructions. | |
3 | ||
4 | Copyright 2011, 2012 Free Software Foundation, Inc. | |
5 | Contributed by ARM Ltd. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the license, or | |
12 | (at your option) any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | ||
24 | /* Prefetch memory instruction is not tested here. | |
25 | ||
26 | Also note that a programmer-friendly disassembler could display | |
27 | LDUR/STUR instructions using the standard LDR/STR mnemonics when | |
28 | the encoded immediate is negative or unaligned. However this behaviour | |
29 | is not required by the architectural assembly language. */ | |
30 | ||
31 | .macro op2_no_imm op, reg | |
32 | \op \reg\()7, [sp] | |
33 | .endm | |
34 | ||
35 | .macro op2 op, reg, simm | |
36 | \op \reg\()7, [sp, #\simm] | |
37 | .endm | |
38 | ||
39 | // load to or store from core register | |
40 | .macro ld_or_st op, suffix, reg | |
41 | .irp simm, -256, -171 | |
42 | op2 \op\suffix, \reg, \simm | |
43 | .endr | |
44 | op2_no_imm \op\suffix, \reg | |
45 | .irp simm, 0, 2, 4, 8, 16, 85, 255 | |
46 | op2 \op\suffix, \reg, \simm | |
47 | .endr | |
48 | .endm | |
49 | ||
50 | // load to or store from FP/SIMD register | |
51 | .macro ld_or_st_v op | |
52 | .irp reg, b, h, s, d, q | |
53 | .irp simm, -256, -171 | |
54 | op2 \op, \reg, \simm | |
55 | .endr | |
56 | op2_no_imm \op, \reg | |
57 | .irp simm, 0, 2, 4, 8, 16, 85, 255 | |
58 | op2 \op, \reg, \simm | |
59 | .endr | |
60 | .endr | |
61 | .endm | |
62 | ||
63 | func: | |
64 | // load to or store from FP/SIMD register | |
65 | ld_or_st_v stur | |
66 | ld_or_st_v ldur | |
67 | ||
68 | // load to or store from core register | |
69 | // op, suffix, reg | |
70 | ld_or_st stur, b, w | |
71 | ld_or_st stur, h, w | |
72 | ld_or_st stur, , w | |
73 | ld_or_st stur, , x | |
74 | ld_or_st ldur, b, w | |
75 | ld_or_st ldur, h, w | |
76 | ld_or_st ldur, , w | |
77 | ld_or_st ldur, , x | |
78 | ld_or_st ldur, sb, x | |
79 | ld_or_st ldur, sh, x | |
80 | ld_or_st ldur, sw, x | |
81 | ld_or_st ldur, sb, w | |
82 | ld_or_st ldur, sh, w |