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1 | /* neon-fp-cvt-ins.s Test file for AArch64 NEON |
2 | floating-point<->fixed-point conversion and | |
3 | floating-point<->integer conversion instructions. | |
4 | ||
2571583a | 5 | Copyright (C) 2011-2017 Free Software Foundation, Inc. |
a06ea964 NC |
6 | Contributed by ARM Ltd. |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the license, or | |
13 | (at your option) any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; see the file COPYING3. If not, | |
22 | see <http://www.gnu.org/licenses/>. */ | |
23 | ||
24 | .macro do_cvt op, fbits, reg, reg_shape | |
25 | .ifc \fbits, 0 | |
26 | // Floating-point<->integer conversions | |
27 | .ifc \reg, V | |
28 | \op V7.\()\reg_shape, V7.\()\reg_shape | |
29 | .else | |
30 | \op \reg\()7, \reg\()7 | |
31 | .endif | |
32 | .else | |
33 | // Floating-point<->fixed-point conversions | |
34 | .ifc \reg, V | |
35 | .ifle \fbits-32 | |
36 | .ifc \reg_shape, 2S | |
37 | \op V7.2S, V7.2S, #\fbits | |
38 | .endif | |
39 | .ifc \reg_shape, 4S | |
40 | \op V7.4S, V7.4S, #\fbits | |
41 | .endif | |
42 | .endif | |
43 | .ifc \reg_shape, 2D | |
44 | \op V7.2D, V7.2D, #\fbits | |
45 | .endif | |
46 | .else | |
47 | .ifc \reg, S | |
48 | .ifle \fbits-32 | |
49 | \op S7, S7, #\fbits | |
50 | .endif | |
51 | .endif | |
52 | .ifc \reg, D | |
53 | \op D7, D7, #\fbits | |
54 | .endif | |
55 | .endif | |
56 | .endif | |
57 | .endm | |
58 | ||
59 | .macro fcvts_with_fbits fbits | |
60 | .ifc \fbits, 0 | |
61 | // fp <-> int | |
62 | // AdvSIMD | |
63 | .irp reg_shape, 2S, 4S, 2D | |
64 | do_cvt FCVTNS, \fbits, V, \reg_shape | |
65 | do_cvt FCVTNU, \fbits, V, \reg_shape | |
66 | do_cvt FCVTPS, \fbits, V, \reg_shape | |
67 | do_cvt FCVTPU, \fbits, V, \reg_shape | |
68 | do_cvt SCVTF, \fbits, V, \reg_shape | |
69 | do_cvt UCVTF, \fbits, V, \reg_shape | |
70 | do_cvt FCVTMS, \fbits, V, \reg_shape | |
71 | do_cvt FCVTMU, \fbits, V, \reg_shape | |
72 | do_cvt FCVTZS, \fbits, V, \reg_shape | |
73 | do_cvt FCVTZU, \fbits, V, \reg_shape | |
74 | do_cvt FCVTAS, \fbits, V, \reg_shape | |
75 | do_cvt FCVTAU, \fbits, V, \reg_shape | |
76 | .endr | |
77 | // AdvSISD | |
78 | .irp reg, S, D | |
79 | do_cvt FCVTNS, \fbits, \reg | |
80 | do_cvt FCVTNU, \fbits, \reg | |
81 | do_cvt FCVTPS, \fbits, \reg | |
82 | do_cvt FCVTPU, \fbits, \reg | |
83 | do_cvt SCVTF, \fbits, \reg | |
84 | do_cvt UCVTF, \fbits, \reg | |
85 | do_cvt FCVTMS, \fbits, \reg | |
86 | do_cvt FCVTMU, \fbits, \reg | |
87 | do_cvt FCVTZS, \fbits, \reg | |
88 | do_cvt FCVTZU, \fbits, \reg | |
89 | do_cvt FCVTAS, \fbits, \reg | |
90 | do_cvt FCVTAU, \fbits, \reg | |
91 | .endr | |
92 | .else | |
93 | // fp <-> fixed-point | |
94 | // AdvSIMD | |
95 | .irp reg_shape, 2S, 4S, 2D | |
96 | do_cvt SCVTF, \fbits, V, \reg_shape | |
97 | do_cvt UCVTF, \fbits, V, \reg_shape | |
98 | do_cvt FCVTZS, \fbits, V, \reg_shape | |
99 | do_cvt FCVTZU, \fbits, V, \reg_shape | |
100 | .endr | |
101 | // AdvSISD | |
102 | .irp reg, S, D | |
103 | do_cvt SCVTF, \fbits, \reg | |
104 | do_cvt UCVTF, \fbits, \reg | |
105 | do_cvt FCVTZS, \fbits, \reg | |
106 | do_cvt FCVTZU, \fbits, \reg | |
107 | .endr | |
108 | .endif | |
109 | .endm | |
110 | ||
111 | ||
112 | .macro fcvts_with_fbits_wrapper from=0, to=64 | |
113 | fcvts_with_fbits \from | |
114 | .if \to-\from | |
115 | fcvts_with_fbits_wrapper "(\from+1)", \to | |
116 | .endif | |
117 | .endm | |
118 | ||
119 | func: | |
120 | // Generate fcvt instructions without fbits and | |
121 | // with fbits from 1 to 64, also generate [us]cvtf | |
122 | fcvts_with_fbits_wrapper from=0, to=64 |