[ARC] Fix warn.exp test error.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / armv8-a+fp.d
CommitLineData
33399f07
MGD
1#name: Valid v8-a+fp
2#objdump: -dr --prefix-addresses --show-raw-insn
8335d6aa 3#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
33399f07
MGD
4
5.*: +file format .*arm.*
6
7Disassembly of section .text:
80[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
90[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1
100[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30
110[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31
120[0-9a-f]+ <[^>]+> fe000b00 vseleq.f64 d0, d0, d0
130[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
140[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
150[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
73924fbc
MGD
160[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
170[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
180[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
190[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
200[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0
210[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16
220[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15
230[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31
240[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
250[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
260[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30
270[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31
280[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0
290[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
300[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
310[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
7e8e6784
MGD
320[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0
330[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
340[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
350[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
827f64ff
WN
360[0-9a-f]+ <[^>]+> febc0bc0 vcvta.s32.f64 s0, d0
370[0-9a-f]+ <[^>]+> fefd0be0 vcvtn.s32.f64 s1, d16
7e8e6784
MGD
380[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
390[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
f8ece37f
RE
400[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32 s0, s0
410[0-9a-f]+ <[^>]+> eef70a60 vrintx.f32 s1, s1
420[0-9a-f]+ <[^>]+> 0eb6fa4f vrintreq.f32 s30, s30
430[0-9a-f]+ <[^>]+> feb80a40 vrinta.f32 s0, s0
440[0-9a-f]+ <[^>]+> fef90a60 vrintn.f32 s1, s1
450[0-9a-f]+ <[^>]+> febafa4f vrintp.f32 s30, s30
460[0-9a-f]+ <[^>]+> fefbfa6f vrintm.f32 s31, s31
470[0-9a-f]+ <[^>]+> eeb60bc0 vrintz.f64 d0, d0
480[0-9a-f]+ <[^>]+> eeb71b41 vrintx.f64 d1, d1
490[0-9a-f]+ <[^>]+> 0ef6eb6e vrintreq.f64 d30, d30
500[0-9a-f]+ <[^>]+> feb80b40 vrinta.f64 d0, d0
510[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64 d1, d1
520[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64 d30, d30
530[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64 d31, d31
c70a8987
MGD
540[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0
550[0-9a-f]+ <[^>]+> eef30b60 vcvtb.f16.f64 s1, d16
560[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15
570[0-9a-f]+ <[^>]+> eef3fb6f vcvtb.f16.f64 s31, d31
580[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0
590[0-9a-f]+ <[^>]+> eef20b60 vcvtb.f64.f16 d16, s1
600[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30
610[0-9a-f]+ <[^>]+> eef2fb6f vcvtb.f64.f16 d31, s31
33399f07
MGD
620[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
630[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
640[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
650[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31
660[0-9a-f]+ <[^>]+> fe00 0b00 vseleq.f64 d0, d0, d0
670[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
680[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
690[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
73924fbc
MGD
700[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
710[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
720[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
730[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
740[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0
750[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16
760[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15
770[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31
780[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
790[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
800[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30
810[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31
820[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0
830[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
840[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
850[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
7e8e6784
MGD
860[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0
870[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
880[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
890[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
827f64ff
WN
900[0-9a-f]+ <[^>]+> febc 0bc0 vcvta.s32.f64 s0, d0
910[0-9a-f]+ <[^>]+> fefd 0be0 vcvtn.s32.f64 s1, d16
7e8e6784
MGD
920[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
930[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
f8ece37f
RE
940[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32 s0, s0
950[0-9a-f]+ <[^>]+> eef7 0a60 vrintx.f32 s1, s1
960[0-9a-f]+ <[^>]+> eeb6 fa4f vrintr.f32 s30, s30
970[0-9a-f]+ <[^>]+> feb8 0a40 vrinta.f32 s0, s0
980[0-9a-f]+ <[^>]+> fef9 0a60 vrintn.f32 s1, s1
990[0-9a-f]+ <[^>]+> feba fa4f vrintp.f32 s30, s30
1000[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32 s31, s31
1010[0-9a-f]+ <[^>]+> eeb6 0bc0 vrintz.f64 d0, d0
1020[0-9a-f]+ <[^>]+> eeb7 1b41 vrintx.f64 d1, d1
1030[0-9a-f]+ <[^>]+> eef6 eb6e vrintr.f64 d30, d30
1040[0-9a-f]+ <[^>]+> feb8 0b40 vrinta.f64 d0, d0
1050[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64 d1, d1
1060[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64 d30, d30
1070[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64 d31, d31
c70a8987
MGD
1080[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0
1090[0-9a-f]+ <[^>]+> eef3 0b60 vcvtb.f16.f64 s1, d16
1100[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15
1110[0-9a-f]+ <[^>]+> eef3 fb6f vcvtb.f16.f64 s31, d31
1120[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0
1130[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1
1140[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30
1150[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31
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