[AArch64] Implement gdbarch_core_read_description
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / crc32-armv8-a-bad.d
CommitLineData
dd5181d5 1#objdump: -dr --prefix-addresses --show-raw-insn
ced40572
TP
2#name: Unpredictable ARMv8-A CRC32 instructions.
3#source: crc32-armv8-ar-bad.s
dd5181d5
KT
4#as: -march=armv8-a+crc
5#stderr: crc32-bad.l
fc7b0af7 6#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
dd5181d5
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7
8.*: +file format .*arm.*
9
10
11Disassembly of section .text:
120+0 <[^>]*> e101f042 crc32b pc, r1, r2 ; <UNPREDICTABLE>
130+4 <[^>]*> e12f0042 crc32h r0, pc, r2 ; <UNPREDICTABLE>
140+8 <[^>]*> e141004f crc32w r0, r1, pc ; <UNPREDICTABLE>
150+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
160+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
170+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
180+18 <[^>]*> fac1 fd82 crc32b sp, r1, r2 ; <UNPREDICTABLE>
190+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; <UNPREDICTABLE>
200+20 <[^>]*> fac1 f0ad crc32w r0, r1, sp ; <UNPREDICTABLE>
210+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
220+28 <[^>]*> fad1 fd92 crc32ch sp, r1, r2 ; <UNPREDICTABLE>
230+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
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