Commit | Line | Data |
---|---|---|
26d97720 NS |
1 | @ Test file for ARM load/store instructions with 0 offset |
2 | ||
3 | .text | |
4 | .syntax unified | |
5 | ldr r1, [r2, #-0] | |
6 | ldr r1, [r2, #-1+1] | |
7 | ||
8 | ldr r1, [r2, #1-1] | |
9 | ldr r1, [r2, #0] | |
10 | ||
11 | ldr r1, [r2, #-0]! | |
12 | ldr r1, [r2, #-1+1]! | |
13 | ||
14 | ldr r1, [r2, #1-1]! | |
15 | ldr r1, [r2, #0]! | |
16 | ||
17 | ldr r1, [r2], #-0 | |
18 | ldr r1, [r2], #-1+1 | |
19 | ||
20 | ldr r1, [r2], #1-1 | |
21 | ldr r1, [r2], #0 | |
22 | ||
23 | ldr r1, [r2]! | |
24 | ldr r1, [r2] | |
25 | ||
26 | ldrbt r1, [r2], #0 | |
27 | ldrbt r1, [r2], #-0 | |
28 | ||
29 | ldrbt r1, [r2] | |
30 | ||
31 | ldclpl p3, c5, [r6, #-0] | |
32 | ldclpl p3, c5, [r6, #0] | |
33 | ||
34 | str r1, [r2, #-0] | |
35 | str r1, [r2, #-1+1] | |
36 | ||
37 | str r1, [r2, #1-1] | |
38 | str r1, [r2, #0] | |
39 | ||
40 | str r1, [r2, #-0]! | |
41 | str r1, [r2, #-1+1]! | |
42 | ||
43 | str r1, [r2, #1-1]! | |
44 | str r1, [r2, #0]! | |
45 | ||
46 | str r1, [r2], #-0 | |
47 | str r1, [r2], #-1+1 | |
48 | ||
49 | str r1, [r2], #1-1 | |
50 | str r1, [r2], #0 | |
51 | ||
52 | str r1, [r2]! | |
53 | str r1, [r2] | |
54 | ||
55 | strbt r1, [r2], #0 | |
56 | strbt r1, [r2], #-0 | |
57 | ||
58 | strbt r1, [r2] | |
59 | ||
60 | stclpl p3, c5, [r6, #-0] | |
61 | stclpl p3, c5, [r6, #0] | |
62 | ||
63 | ldr r0,1f | |
64 | ldr r0,1f | |
65 | ldr r0,1f | |
66 | 1: .word 0 |